1 //===- ARMInstrInfo.td - Target Description for ARM Target -*- tablegen -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file describes the ARM instructions in TableGen format.
12 //===----------------------------------------------------------------------===//
14 //===----------------------------------------------------------------------===//
15 // ARM specific DAG Nodes.
19 def SDT_ARMCallSeqStart : SDCallSeqStart<[ SDTCisVT<0, i32> ]>;
20 def SDT_ARMCallSeqEnd : SDCallSeqEnd<[ SDTCisVT<0, i32>, SDTCisVT<1, i32> ]>;
22 def SDT_ARMSaveCallPC : SDTypeProfile<0, 1, []>;
24 def SDT_ARMcall : SDTypeProfile<0, -1, [SDTCisPtrTy<0>]>;
26 def SDT_ARMCMov : SDTypeProfile<1, 3,
27 [SDTCisSameAs<0, 1>, SDTCisSameAs<0, 2>,
30 def SDT_ARMBrcond : SDTypeProfile<0, 2,
31 [SDTCisVT<0, OtherVT>, SDTCisVT<1, i32>]>;
33 def SDT_ARMBrJT : SDTypeProfile<0, 3,
34 [SDTCisPtrTy<0>, SDTCisVT<1, i32>,
37 def SDT_ARMBr2JT : SDTypeProfile<0, 4,
38 [SDTCisPtrTy<0>, SDTCisVT<1, i32>,
39 SDTCisVT<2, i32>, SDTCisVT<3, i32>]>;
41 def SDT_ARMBCC_i64 : SDTypeProfile<0, 6,
43 SDTCisVT<1, i32>, SDTCisVT<2, i32>,
44 SDTCisVT<3, i32>, SDTCisVT<4, i32>,
45 SDTCisVT<5, OtherVT>]>;
47 def SDT_ARMAnd : SDTypeProfile<1, 2,
48 [SDTCisVT<0, i32>, SDTCisVT<1, i32>,
51 def SDT_ARMCmp : SDTypeProfile<0, 2, [SDTCisSameAs<0, 1>]>;
53 def SDT_ARMPICAdd : SDTypeProfile<1, 2, [SDTCisSameAs<0, 1>,
54 SDTCisPtrTy<1>, SDTCisVT<2, i32>]>;
56 def SDT_ARMThreadPointer : SDTypeProfile<1, 0, [SDTCisPtrTy<0>]>;
57 def SDT_ARMEH_SJLJ_Setjmp : SDTypeProfile<1, 2, [SDTCisInt<0>, SDTCisPtrTy<1>,
59 def SDT_ARMEH_SJLJ_Longjmp: SDTypeProfile<0, 2, [SDTCisPtrTy<0>, SDTCisInt<1>]>;
61 def SDT_ARMMEMBARRIER : SDTypeProfile<0, 1, [SDTCisInt<0>]>;
63 def SDT_ARMPREFETCH : SDTypeProfile<0, 3, [SDTCisPtrTy<0>, SDTCisSameAs<1, 2>,
66 def SDT_ARMTCRET : SDTypeProfile<0, 1, [SDTCisPtrTy<0>]>;
68 def SDT_ARMBFI : SDTypeProfile<1, 3, [SDTCisVT<0, i32>, SDTCisVT<1, i32>,
69 SDTCisVT<2, i32>, SDTCisVT<3, i32>]>;
71 def SDTBinaryArithWithFlags : SDTypeProfile<2, 2,
74 SDTCisInt<0>, SDTCisVT<1, i32>]>;
76 // SDTBinaryArithWithFlagsInOut - RES1, CPSR = op LHS, RHS, CPSR
77 def SDTBinaryArithWithFlagsInOut : SDTypeProfile<2, 3,
84 def ARMWrapper : SDNode<"ARMISD::Wrapper", SDTIntUnaryOp>;
85 def ARMWrapperDYN : SDNode<"ARMISD::WrapperDYN", SDTIntUnaryOp>;
86 def ARMWrapperPIC : SDNode<"ARMISD::WrapperPIC", SDTIntUnaryOp>;
87 def ARMWrapperJT : SDNode<"ARMISD::WrapperJT", SDTIntBinOp>;
89 def ARMcallseq_start : SDNode<"ISD::CALLSEQ_START", SDT_ARMCallSeqStart,
90 [SDNPHasChain, SDNPOutGlue]>;
91 def ARMcallseq_end : SDNode<"ISD::CALLSEQ_END", SDT_ARMCallSeqEnd,
92 [SDNPHasChain, SDNPOptInGlue, SDNPOutGlue]>;
94 def ARMcall : SDNode<"ARMISD::CALL", SDT_ARMcall,
95 [SDNPHasChain, SDNPOptInGlue, SDNPOutGlue,
97 def ARMcall_pred : SDNode<"ARMISD::CALL_PRED", SDT_ARMcall,
98 [SDNPHasChain, SDNPOptInGlue, SDNPOutGlue,
100 def ARMcall_nolink : SDNode<"ARMISD::CALL_NOLINK", SDT_ARMcall,
101 [SDNPHasChain, SDNPOptInGlue, SDNPOutGlue,
104 def ARMretflag : SDNode<"ARMISD::RET_FLAG", SDTNone,
105 [SDNPHasChain, SDNPOptInGlue]>;
107 def ARMcmov : SDNode<"ARMISD::CMOV", SDT_ARMCMov,
110 def ARMbrcond : SDNode<"ARMISD::BRCOND", SDT_ARMBrcond,
111 [SDNPHasChain, SDNPInGlue, SDNPOutGlue]>;
113 def ARMbrjt : SDNode<"ARMISD::BR_JT", SDT_ARMBrJT,
115 def ARMbr2jt : SDNode<"ARMISD::BR2_JT", SDT_ARMBr2JT,
118 def ARMBcci64 : SDNode<"ARMISD::BCC_i64", SDT_ARMBCC_i64,
121 def ARMcmp : SDNode<"ARMISD::CMP", SDT_ARMCmp,
124 def ARMcmpZ : SDNode<"ARMISD::CMPZ", SDT_ARMCmp,
125 [SDNPOutGlue, SDNPCommutative]>;
127 def ARMpic_add : SDNode<"ARMISD::PIC_ADD", SDT_ARMPICAdd>;
129 def ARMsrl_flag : SDNode<"ARMISD::SRL_FLAG", SDTIntUnaryOp, [SDNPOutGlue]>;
130 def ARMsra_flag : SDNode<"ARMISD::SRA_FLAG", SDTIntUnaryOp, [SDNPOutGlue]>;
131 def ARMrrx : SDNode<"ARMISD::RRX" , SDTIntUnaryOp, [SDNPInGlue ]>;
133 def ARMaddc : SDNode<"ARMISD::ADDC", SDTBinaryArithWithFlags,
135 def ARMsubc : SDNode<"ARMISD::SUBC", SDTBinaryArithWithFlags>;
136 def ARMadde : SDNode<"ARMISD::ADDE", SDTBinaryArithWithFlagsInOut>;
137 def ARMsube : SDNode<"ARMISD::SUBE", SDTBinaryArithWithFlagsInOut>;
139 def ARMthread_pointer: SDNode<"ARMISD::THREAD_POINTER", SDT_ARMThreadPointer>;
140 def ARMeh_sjlj_setjmp: SDNode<"ARMISD::EH_SJLJ_SETJMP",
141 SDT_ARMEH_SJLJ_Setjmp, [SDNPHasChain]>;
142 def ARMeh_sjlj_longjmp: SDNode<"ARMISD::EH_SJLJ_LONGJMP",
143 SDT_ARMEH_SJLJ_Longjmp, [SDNPHasChain]>;
145 def ARMMemBarrier : SDNode<"ARMISD::MEMBARRIER", SDT_ARMMEMBARRIER,
147 def ARMMemBarrierMCR : SDNode<"ARMISD::MEMBARRIER_MCR", SDT_ARMMEMBARRIER,
149 def ARMPreload : SDNode<"ARMISD::PRELOAD", SDT_ARMPREFETCH,
150 [SDNPHasChain, SDNPMayLoad, SDNPMayStore]>;
152 def ARMrbit : SDNode<"ARMISD::RBIT", SDTIntUnaryOp>;
154 def ARMtcret : SDNode<"ARMISD::TC_RETURN", SDT_ARMTCRET,
155 [SDNPHasChain, SDNPOptInGlue, SDNPVariadic]>;
158 def ARMbfi : SDNode<"ARMISD::BFI", SDT_ARMBFI>;
160 //===----------------------------------------------------------------------===//
161 // ARM Instruction Predicate Definitions.
163 def HasV4T : Predicate<"Subtarget->hasV4TOps()">,
164 AssemblerPredicate<"HasV4TOps", "armv4t">;
165 def NoV4T : Predicate<"!Subtarget->hasV4TOps()">;
166 def HasV5T : Predicate<"Subtarget->hasV5TOps()">;
167 def HasV5TE : Predicate<"Subtarget->hasV5TEOps()">,
168 AssemblerPredicate<"HasV5TEOps", "armv5te">;
169 def HasV6 : Predicate<"Subtarget->hasV6Ops()">,
170 AssemblerPredicate<"HasV6Ops", "armv6">;
171 def NoV6 : Predicate<"!Subtarget->hasV6Ops()">;
172 def HasV6T2 : Predicate<"Subtarget->hasV6T2Ops()">,
173 AssemblerPredicate<"HasV6T2Ops", "armv6t2">;
174 def NoV6T2 : Predicate<"!Subtarget->hasV6T2Ops()">;
175 def HasV7 : Predicate<"Subtarget->hasV7Ops()">,
176 AssemblerPredicate<"HasV7Ops", "armv7">;
177 def NoVFP : Predicate<"!Subtarget->hasVFP2()">;
178 def HasVFP2 : Predicate<"Subtarget->hasVFP2()">,
179 AssemblerPredicate<"FeatureVFP2", "VFP2">;
180 def HasVFP3 : Predicate<"Subtarget->hasVFP3()">,
181 AssemblerPredicate<"FeatureVFP3", "VFP3">;
182 def HasVFP4 : Predicate<"Subtarget->hasVFP4()">,
183 AssemblerPredicate<"FeatureVFP4", "VFP4">;
184 def HasNEON : Predicate<"Subtarget->hasNEON()">,
185 AssemblerPredicate<"FeatureNEON", "NEON">;
186 def HasFP16 : Predicate<"Subtarget->hasFP16()">,
187 AssemblerPredicate<"FeatureFP16","half-float">;
188 def HasDivide : Predicate<"Subtarget->hasDivide()">,
189 AssemblerPredicate<"FeatureHWDiv", "divide">;
190 def HasT2ExtractPack : Predicate<"Subtarget->hasT2ExtractPack()">,
191 AssemblerPredicate<"FeatureT2XtPk",
193 def HasThumb2DSP : Predicate<"Subtarget->hasThumb2DSP()">,
194 AssemblerPredicate<"FeatureDSPThumb2",
196 def HasDB : Predicate<"Subtarget->hasDataBarrier()">,
197 AssemblerPredicate<"FeatureDB",
199 def HasMP : Predicate<"Subtarget->hasMPExtension()">,
200 AssemblerPredicate<"FeatureMP",
202 def UseNEONForFP : Predicate<"Subtarget->useNEONForSinglePrecisionFP()">;
203 def DontUseNEONForFP : Predicate<"!Subtarget->useNEONForSinglePrecisionFP()">;
204 def IsThumb : Predicate<"Subtarget->isThumb()">,
205 AssemblerPredicate<"ModeThumb", "thumb">;
206 def IsThumb1Only : Predicate<"Subtarget->isThumb1Only()">;
207 def IsThumb2 : Predicate<"Subtarget->isThumb2()">,
208 AssemblerPredicate<"ModeThumb,FeatureThumb2",
210 def IsMClass : Predicate<"Subtarget->isMClass()">,
211 AssemblerPredicate<"FeatureMClass", "armv7m">;
212 def IsARClass : Predicate<"!Subtarget->isMClass()">,
213 AssemblerPredicate<"!FeatureMClass",
215 def IsARM : Predicate<"!Subtarget->isThumb()">,
216 AssemblerPredicate<"!ModeThumb", "arm-mode">;
217 def IsIOS : Predicate<"Subtarget->isTargetIOS()">;
218 def IsNotIOS : Predicate<"!Subtarget->isTargetIOS()">;
219 def IsNaCl : Predicate<"Subtarget->isTargetNaCl()">;
221 // FIXME: Eventually this will be just "hasV6T2Ops".
222 def UseMovt : Predicate<"Subtarget->useMovt()">;
223 def DontUseMovt : Predicate<"!Subtarget->useMovt()">;
224 def UseFPVMLx : Predicate<"Subtarget->useFPVMLx()">;
226 // Prefer fused MAC for fp mul + add over fp VMLA / VMLS if they are available.
227 // But only select them if more precision in FP computation is allowed.
228 // Do not use them for Darwin platforms.
229 def UseFusedMAC : Predicate<"!TM.Options.NoExcessFPPrecision && "
230 "!Subtarget->isTargetDarwin()">;
231 def DontUseFusedMAC : Predicate<"!Subtarget->hasVFP4() || "
232 "Subtarget->isTargetDarwin()">;
234 //===----------------------------------------------------------------------===//
235 // ARM Flag Definitions.
237 class RegConstraint<string C> {
238 string Constraints = C;
241 //===----------------------------------------------------------------------===//
242 // ARM specific transformation functions and pattern fragments.
245 // so_imm_neg_XFORM - Return a so_imm value packed into the format described for
246 // so_imm_neg def below.
247 def so_imm_neg_XFORM : SDNodeXForm<imm, [{
248 return CurDAG->getTargetConstant(-(int)N->getZExtValue(), MVT::i32);
251 // so_imm_not_XFORM - Return a so_imm value packed into the format described for
252 // so_imm_not def below.
253 def so_imm_not_XFORM : SDNodeXForm<imm, [{
254 return CurDAG->getTargetConstant(~(int)N->getZExtValue(), MVT::i32);
257 /// imm16_31 predicate - True if the 32-bit immediate is in the range [16,31].
258 def imm16_31 : ImmLeaf<i32, [{
259 return (int32_t)Imm >= 16 && (int32_t)Imm < 32;
262 def so_imm_neg_asmoperand : AsmOperandClass { let Name = "ARMSOImmNeg"; }
263 def so_imm_neg : Operand<i32>, PatLeaf<(imm), [{
264 int64_t Value = -(int)N->getZExtValue();
265 return Value && ARM_AM::getSOImmVal(Value) != -1;
266 }], so_imm_neg_XFORM> {
267 let ParserMatchClass = so_imm_neg_asmoperand;
270 // Note: this pattern doesn't require an encoder method and such, as it's
271 // only used on aliases (Pat<> and InstAlias<>). The actual encoding
272 // is handled by the destination instructions, which use so_imm.
273 def so_imm_not_asmoperand : AsmOperandClass { let Name = "ARMSOImmNot"; }
274 def so_imm_not : Operand<i32>, PatLeaf<(imm), [{
275 return ARM_AM::getSOImmVal(~(uint32_t)N->getZExtValue()) != -1;
276 }], so_imm_not_XFORM> {
277 let ParserMatchClass = so_imm_not_asmoperand;
280 // sext_16_node predicate - True if the SDNode is sign-extended 16 or more bits.
281 def sext_16_node : PatLeaf<(i32 GPR:$a), [{
282 return CurDAG->ComputeNumSignBits(SDValue(N,0)) >= 17;
285 /// Split a 32-bit immediate into two 16 bit parts.
286 def hi16 : SDNodeXForm<imm, [{
287 return CurDAG->getTargetConstant((uint32_t)N->getZExtValue() >> 16, MVT::i32);
290 def lo16AllZero : PatLeaf<(i32 imm), [{
291 // Returns true if all low 16-bits are 0.
292 return (((uint32_t)N->getZExtValue()) & 0xFFFFUL) == 0;
295 class BinOpWithFlagFrag<dag res> :
296 PatFrag<(ops node:$LHS, node:$RHS, node:$FLAG), res>;
297 class BinOpFrag<dag res> : PatFrag<(ops node:$LHS, node:$RHS), res>;
298 class UnOpFrag <dag res> : PatFrag<(ops node:$Src), res>;
300 // An 'and' node with a single use.
301 def and_su : PatFrag<(ops node:$lhs, node:$rhs), (and node:$lhs, node:$rhs), [{
302 return N->hasOneUse();
305 // An 'xor' node with a single use.
306 def xor_su : PatFrag<(ops node:$lhs, node:$rhs), (xor node:$lhs, node:$rhs), [{
307 return N->hasOneUse();
310 // An 'fmul' node with a single use.
311 def fmul_su : PatFrag<(ops node:$lhs, node:$rhs), (fmul node:$lhs, node:$rhs),[{
312 return N->hasOneUse();
315 // An 'fadd' node which checks for single non-hazardous use.
316 def fadd_mlx : PatFrag<(ops node:$lhs, node:$rhs),(fadd node:$lhs, node:$rhs),[{
317 return hasNoVMLxHazardUse(N);
320 // An 'fsub' node which checks for single non-hazardous use.
321 def fsub_mlx : PatFrag<(ops node:$lhs, node:$rhs),(fsub node:$lhs, node:$rhs),[{
322 return hasNoVMLxHazardUse(N);
325 //===----------------------------------------------------------------------===//
326 // Operand Definitions.
329 // Immediate operands with a shared generic asm render method.
330 class ImmAsmOperand : AsmOperandClass { let RenderMethod = "addImmOperands"; }
333 // FIXME: rename brtarget to t2_brtarget
334 def brtarget : Operand<OtherVT> {
335 let EncoderMethod = "getBranchTargetOpValue";
336 let OperandType = "OPERAND_PCREL";
337 let DecoderMethod = "DecodeT2BROperand";
340 // FIXME: get rid of this one?
341 def uncondbrtarget : Operand<OtherVT> {
342 let EncoderMethod = "getUnconditionalBranchTargetOpValue";
343 let OperandType = "OPERAND_PCREL";
346 // Branch target for ARM. Handles conditional/unconditional
347 def br_target : Operand<OtherVT> {
348 let EncoderMethod = "getARMBranchTargetOpValue";
349 let OperandType = "OPERAND_PCREL";
353 // FIXME: rename bltarget to t2_bl_target?
354 def bltarget : Operand<i32> {
355 // Encoded the same as branch targets.
356 let EncoderMethod = "getBranchTargetOpValue";
357 let OperandType = "OPERAND_PCREL";
360 // Call target for ARM. Handles conditional/unconditional
361 // FIXME: rename bl_target to t2_bltarget?
362 def bl_target : Operand<i32> {
363 let EncoderMethod = "getARMBLTargetOpValue";
364 let OperandType = "OPERAND_PCREL";
367 def blx_target : Operand<i32> {
368 let EncoderMethod = "getARMBLXTargetOpValue";
369 let OperandType = "OPERAND_PCREL";
372 // A list of registers separated by comma. Used by load/store multiple.
373 def RegListAsmOperand : AsmOperandClass { let Name = "RegList"; }
374 def reglist : Operand<i32> {
375 let EncoderMethod = "getRegisterListOpValue";
376 let ParserMatchClass = RegListAsmOperand;
377 let PrintMethod = "printRegisterList";
378 let DecoderMethod = "DecodeRegListOperand";
381 def DPRRegListAsmOperand : AsmOperandClass { let Name = "DPRRegList"; }
382 def dpr_reglist : Operand<i32> {
383 let EncoderMethod = "getRegisterListOpValue";
384 let ParserMatchClass = DPRRegListAsmOperand;
385 let PrintMethod = "printRegisterList";
386 let DecoderMethod = "DecodeDPRRegListOperand";
389 def SPRRegListAsmOperand : AsmOperandClass { let Name = "SPRRegList"; }
390 def spr_reglist : Operand<i32> {
391 let EncoderMethod = "getRegisterListOpValue";
392 let ParserMatchClass = SPRRegListAsmOperand;
393 let PrintMethod = "printRegisterList";
394 let DecoderMethod = "DecodeSPRRegListOperand";
397 // An operand for the CONSTPOOL_ENTRY pseudo-instruction.
398 def cpinst_operand : Operand<i32> {
399 let PrintMethod = "printCPInstOperand";
403 def pclabel : Operand<i32> {
404 let PrintMethod = "printPCLabel";
407 // ADR instruction labels.
408 def adrlabel : Operand<i32> {
409 let EncoderMethod = "getAdrLabelOpValue";
412 def neon_vcvt_imm32 : Operand<i32> {
413 let EncoderMethod = "getNEONVcvtImm32OpValue";
414 let DecoderMethod = "DecodeVCVTImmOperand";
417 // rot_imm: An integer that encodes a rotate amount. Must be 8, 16, or 24.
418 def rot_imm_XFORM: SDNodeXForm<imm, [{
419 switch (N->getZExtValue()){
421 case 0: return CurDAG->getTargetConstant(0, MVT::i32);
422 case 8: return CurDAG->getTargetConstant(1, MVT::i32);
423 case 16: return CurDAG->getTargetConstant(2, MVT::i32);
424 case 24: return CurDAG->getTargetConstant(3, MVT::i32);
427 def RotImmAsmOperand : AsmOperandClass {
429 let ParserMethod = "parseRotImm";
431 def rot_imm : Operand<i32>, PatLeaf<(i32 imm), [{
432 int32_t v = N->getZExtValue();
433 return v == 8 || v == 16 || v == 24; }],
435 let PrintMethod = "printRotImmOperand";
436 let ParserMatchClass = RotImmAsmOperand;
439 // shift_imm: An integer that encodes a shift amount and the type of shift
440 // (asr or lsl). The 6-bit immediate encodes as:
443 // {4-0} imm5 shift amount.
444 // asr #32 encoded as imm5 == 0.
445 def ShifterImmAsmOperand : AsmOperandClass {
446 let Name = "ShifterImm";
447 let ParserMethod = "parseShifterImm";
449 def shift_imm : Operand<i32> {
450 let PrintMethod = "printShiftImmOperand";
451 let ParserMatchClass = ShifterImmAsmOperand;
454 // shifter_operand operands: so_reg_reg, so_reg_imm, and so_imm.
455 def ShiftedRegAsmOperand : AsmOperandClass { let Name = "RegShiftedReg"; }
456 def so_reg_reg : Operand<i32>, // reg reg imm
457 ComplexPattern<i32, 3, "SelectRegShifterOperand",
458 [shl, srl, sra, rotr]> {
459 let EncoderMethod = "getSORegRegOpValue";
460 let PrintMethod = "printSORegRegOperand";
461 let DecoderMethod = "DecodeSORegRegOperand";
462 let ParserMatchClass = ShiftedRegAsmOperand;
463 let MIOperandInfo = (ops GPRnopc, GPRnopc, i32imm);
466 def ShiftedImmAsmOperand : AsmOperandClass { let Name = "RegShiftedImm"; }
467 def so_reg_imm : Operand<i32>, // reg imm
468 ComplexPattern<i32, 2, "SelectImmShifterOperand",
469 [shl, srl, sra, rotr]> {
470 let EncoderMethod = "getSORegImmOpValue";
471 let PrintMethod = "printSORegImmOperand";
472 let DecoderMethod = "DecodeSORegImmOperand";
473 let ParserMatchClass = ShiftedImmAsmOperand;
474 let MIOperandInfo = (ops GPR, i32imm);
477 // FIXME: Does this need to be distinct from so_reg?
478 def shift_so_reg_reg : Operand<i32>, // reg reg imm
479 ComplexPattern<i32, 3, "SelectShiftRegShifterOperand",
480 [shl,srl,sra,rotr]> {
481 let EncoderMethod = "getSORegRegOpValue";
482 let PrintMethod = "printSORegRegOperand";
483 let DecoderMethod = "DecodeSORegRegOperand";
484 let ParserMatchClass = ShiftedRegAsmOperand;
485 let MIOperandInfo = (ops GPR, GPR, i32imm);
488 // FIXME: Does this need to be distinct from so_reg?
489 def shift_so_reg_imm : Operand<i32>, // reg reg imm
490 ComplexPattern<i32, 2, "SelectShiftImmShifterOperand",
491 [shl,srl,sra,rotr]> {
492 let EncoderMethod = "getSORegImmOpValue";
493 let PrintMethod = "printSORegImmOperand";
494 let DecoderMethod = "DecodeSORegImmOperand";
495 let ParserMatchClass = ShiftedImmAsmOperand;
496 let MIOperandInfo = (ops GPR, i32imm);
500 // so_imm - Match a 32-bit shifter_operand immediate operand, which is an
501 // 8-bit immediate rotated by an arbitrary number of bits.
502 def SOImmAsmOperand: ImmAsmOperand { let Name = "ARMSOImm"; }
503 def so_imm : Operand<i32>, ImmLeaf<i32, [{
504 return ARM_AM::getSOImmVal(Imm) != -1;
506 let EncoderMethod = "getSOImmOpValue";
507 let ParserMatchClass = SOImmAsmOperand;
508 let DecoderMethod = "DecodeSOImmOperand";
511 // Break so_imm's up into two pieces. This handles immediates with up to 16
512 // bits set in them. This uses so_imm2part to match and so_imm2part_[12] to
513 // get the first/second pieces.
514 def so_imm2part : PatLeaf<(imm), [{
515 return ARM_AM::isSOImmTwoPartVal((unsigned)N->getZExtValue());
518 /// arm_i32imm - True for +V6T2, or true only if so_imm2part is true.
520 def arm_i32imm : PatLeaf<(imm), [{
521 if (Subtarget->hasV6T2Ops())
523 return ARM_AM::isSOImmTwoPartVal((unsigned)N->getZExtValue());
526 /// imm0_1 predicate - Immediate in the range [0,1].
527 def Imm0_1AsmOperand: ImmAsmOperand { let Name = "Imm0_1"; }
528 def imm0_1 : Operand<i32> { let ParserMatchClass = Imm0_1AsmOperand; }
530 /// imm0_3 predicate - Immediate in the range [0,3].
531 def Imm0_3AsmOperand: ImmAsmOperand { let Name = "Imm0_3"; }
532 def imm0_3 : Operand<i32> { let ParserMatchClass = Imm0_3AsmOperand; }
534 /// imm0_7 predicate - Immediate in the range [0,7].
535 def Imm0_7AsmOperand: ImmAsmOperand { let Name = "Imm0_7"; }
536 def imm0_7 : Operand<i32>, ImmLeaf<i32, [{
537 return Imm >= 0 && Imm < 8;
539 let ParserMatchClass = Imm0_7AsmOperand;
542 /// imm8 predicate - Immediate is exactly 8.
543 def Imm8AsmOperand: ImmAsmOperand { let Name = "Imm8"; }
544 def imm8 : Operand<i32>, ImmLeaf<i32, [{ return Imm == 8; }]> {
545 let ParserMatchClass = Imm8AsmOperand;
548 /// imm16 predicate - Immediate is exactly 16.
549 def Imm16AsmOperand: ImmAsmOperand { let Name = "Imm16"; }
550 def imm16 : Operand<i32>, ImmLeaf<i32, [{ return Imm == 16; }]> {
551 let ParserMatchClass = Imm16AsmOperand;
554 /// imm32 predicate - Immediate is exactly 32.
555 def Imm32AsmOperand: ImmAsmOperand { let Name = "Imm32"; }
556 def imm32 : Operand<i32>, ImmLeaf<i32, [{ return Imm == 32; }]> {
557 let ParserMatchClass = Imm32AsmOperand;
560 /// imm1_7 predicate - Immediate in the range [1,7].
561 def Imm1_7AsmOperand: ImmAsmOperand { let Name = "Imm1_7"; }
562 def imm1_7 : Operand<i32>, ImmLeaf<i32, [{ return Imm > 0 && Imm < 8; }]> {
563 let ParserMatchClass = Imm1_7AsmOperand;
566 /// imm1_15 predicate - Immediate in the range [1,15].
567 def Imm1_15AsmOperand: ImmAsmOperand { let Name = "Imm1_15"; }
568 def imm1_15 : Operand<i32>, ImmLeaf<i32, [{ return Imm > 0 && Imm < 16; }]> {
569 let ParserMatchClass = Imm1_15AsmOperand;
572 /// imm1_31 predicate - Immediate in the range [1,31].
573 def Imm1_31AsmOperand: ImmAsmOperand { let Name = "Imm1_31"; }
574 def imm1_31 : Operand<i32>, ImmLeaf<i32, [{ return Imm > 0 && Imm < 32; }]> {
575 let ParserMatchClass = Imm1_31AsmOperand;
578 /// imm0_15 predicate - Immediate in the range [0,15].
579 def Imm0_15AsmOperand: ImmAsmOperand { let Name = "Imm0_15"; }
580 def imm0_15 : Operand<i32>, ImmLeaf<i32, [{
581 return Imm >= 0 && Imm < 16;
583 let ParserMatchClass = Imm0_15AsmOperand;
586 /// imm0_31 predicate - True if the 32-bit immediate is in the range [0,31].
587 def Imm0_31AsmOperand: ImmAsmOperand { let Name = "Imm0_31"; }
588 def imm0_31 : Operand<i32>, ImmLeaf<i32, [{
589 return Imm >= 0 && Imm < 32;
591 let ParserMatchClass = Imm0_31AsmOperand;
594 /// imm0_32 predicate - True if the 32-bit immediate is in the range [0,32].
595 def Imm0_32AsmOperand: ImmAsmOperand { let Name = "Imm0_32"; }
596 def imm0_32 : Operand<i32>, ImmLeaf<i32, [{
597 return Imm >= 0 && Imm < 32;
599 let ParserMatchClass = Imm0_32AsmOperand;
602 /// imm0_63 predicate - True if the 32-bit immediate is in the range [0,63].
603 def Imm0_63AsmOperand: ImmAsmOperand { let Name = "Imm0_63"; }
604 def imm0_63 : Operand<i32>, ImmLeaf<i32, [{
605 return Imm >= 0 && Imm < 64;
607 let ParserMatchClass = Imm0_63AsmOperand;
610 /// imm0_255 predicate - Immediate in the range [0,255].
611 def Imm0_255AsmOperand : ImmAsmOperand { let Name = "Imm0_255"; }
612 def imm0_255 : Operand<i32>, ImmLeaf<i32, [{ return Imm >= 0 && Imm < 256; }]> {
613 let ParserMatchClass = Imm0_255AsmOperand;
616 /// imm0_65535 - An immediate is in the range [0.65535].
617 def Imm0_65535AsmOperand: ImmAsmOperand { let Name = "Imm0_65535"; }
618 def imm0_65535 : Operand<i32>, ImmLeaf<i32, [{
619 return Imm >= 0 && Imm < 65536;
621 let ParserMatchClass = Imm0_65535AsmOperand;
624 // imm0_65535_expr - For movt/movw - 16-bit immediate that can also reference
625 // a relocatable expression.
627 // FIXME: This really needs a Thumb version separate from the ARM version.
628 // While the range is the same, and can thus use the same match class,
629 // the encoding is different so it should have a different encoder method.
630 def Imm0_65535ExprAsmOperand: ImmAsmOperand { let Name = "Imm0_65535Expr"; }
631 def imm0_65535_expr : Operand<i32> {
632 let EncoderMethod = "getHiLo16ImmOpValue";
633 let ParserMatchClass = Imm0_65535ExprAsmOperand;
636 /// imm24b - True if the 32-bit immediate is encodable in 24 bits.
637 def Imm24bitAsmOperand: ImmAsmOperand { let Name = "Imm24bit"; }
638 def imm24b : Operand<i32>, ImmLeaf<i32, [{
639 return Imm >= 0 && Imm <= 0xffffff;
641 let ParserMatchClass = Imm24bitAsmOperand;
645 /// bf_inv_mask_imm predicate - An AND mask to clear an arbitrary width bitfield
647 def BitfieldAsmOperand : AsmOperandClass {
648 let Name = "Bitfield";
649 let ParserMethod = "parseBitfield";
652 def bf_inv_mask_imm : Operand<i32>,
654 return ARM::isBitFieldInvertedMask(N->getZExtValue());
656 let EncoderMethod = "getBitfieldInvertedMaskOpValue";
657 let PrintMethod = "printBitfieldInvMaskImmOperand";
658 let DecoderMethod = "DecodeBitfieldMaskOperand";
659 let ParserMatchClass = BitfieldAsmOperand;
662 def imm1_32_XFORM: SDNodeXForm<imm, [{
663 return CurDAG->getTargetConstant((int)N->getZExtValue() - 1, MVT::i32);
665 def Imm1_32AsmOperand: AsmOperandClass { let Name = "Imm1_32"; }
666 def imm1_32 : Operand<i32>, PatLeaf<(imm), [{
667 uint64_t Imm = N->getZExtValue();
668 return Imm > 0 && Imm <= 32;
671 let PrintMethod = "printImmPlusOneOperand";
672 let ParserMatchClass = Imm1_32AsmOperand;
675 def imm1_16_XFORM: SDNodeXForm<imm, [{
676 return CurDAG->getTargetConstant((int)N->getZExtValue() - 1, MVT::i32);
678 def Imm1_16AsmOperand: AsmOperandClass { let Name = "Imm1_16"; }
679 def imm1_16 : Operand<i32>, PatLeaf<(imm), [{ return Imm > 0 && Imm <= 16; }],
681 let PrintMethod = "printImmPlusOneOperand";
682 let ParserMatchClass = Imm1_16AsmOperand;
685 // Define ARM specific addressing modes.
686 // addrmode_imm12 := reg +/- imm12
688 def MemImm12OffsetAsmOperand : AsmOperandClass { let Name = "MemImm12Offset"; }
689 def addrmode_imm12 : Operand<i32>,
690 ComplexPattern<i32, 2, "SelectAddrModeImm12", []> {
691 // 12-bit immediate operand. Note that instructions using this encode
692 // #0 and #-0 differently. We flag #-0 as the magic value INT32_MIN. All other
693 // immediate values are as normal.
695 let EncoderMethod = "getAddrModeImm12OpValue";
696 let PrintMethod = "printAddrModeImm12Operand";
697 let DecoderMethod = "DecodeAddrModeImm12Operand";
698 let ParserMatchClass = MemImm12OffsetAsmOperand;
699 let MIOperandInfo = (ops GPR:$base, i32imm:$offsimm);
701 // ldst_so_reg := reg +/- reg shop imm
703 def MemRegOffsetAsmOperand : AsmOperandClass { let Name = "MemRegOffset"; }
704 def ldst_so_reg : Operand<i32>,
705 ComplexPattern<i32, 3, "SelectLdStSOReg", []> {
706 let EncoderMethod = "getLdStSORegOpValue";
707 // FIXME: Simplify the printer
708 let PrintMethod = "printAddrMode2Operand";
709 let DecoderMethod = "DecodeSORegMemOperand";
710 let ParserMatchClass = MemRegOffsetAsmOperand;
711 let MIOperandInfo = (ops GPR:$base, GPRnopc:$offsreg, i32imm:$shift);
714 // postidx_imm8 := +/- [0,255]
717 // {8} 1 is imm8 is non-negative. 0 otherwise.
718 // {7-0} [0,255] imm8 value.
719 def PostIdxImm8AsmOperand : AsmOperandClass { let Name = "PostIdxImm8"; }
720 def postidx_imm8 : Operand<i32> {
721 let PrintMethod = "printPostIdxImm8Operand";
722 let ParserMatchClass = PostIdxImm8AsmOperand;
723 let MIOperandInfo = (ops i32imm);
726 // postidx_imm8s4 := +/- [0,1020]
729 // {8} 1 is imm8 is non-negative. 0 otherwise.
730 // {7-0} [0,255] imm8 value, scaled by 4.
731 def PostIdxImm8s4AsmOperand : AsmOperandClass { let Name = "PostIdxImm8s4"; }
732 def postidx_imm8s4 : Operand<i32> {
733 let PrintMethod = "printPostIdxImm8s4Operand";
734 let ParserMatchClass = PostIdxImm8s4AsmOperand;
735 let MIOperandInfo = (ops i32imm);
739 // postidx_reg := +/- reg
741 def PostIdxRegAsmOperand : AsmOperandClass {
742 let Name = "PostIdxReg";
743 let ParserMethod = "parsePostIdxReg";
745 def postidx_reg : Operand<i32> {
746 let EncoderMethod = "getPostIdxRegOpValue";
747 let DecoderMethod = "DecodePostIdxReg";
748 let PrintMethod = "printPostIdxRegOperand";
749 let ParserMatchClass = PostIdxRegAsmOperand;
750 let MIOperandInfo = (ops GPRnopc, i32imm);
754 // addrmode2 := reg +/- imm12
755 // := reg +/- reg shop imm
757 // FIXME: addrmode2 should be refactored the rest of the way to always
758 // use explicit imm vs. reg versions above (addrmode_imm12 and ldst_so_reg).
759 def AddrMode2AsmOperand : AsmOperandClass { let Name = "AddrMode2"; }
760 def addrmode2 : Operand<i32>,
761 ComplexPattern<i32, 3, "SelectAddrMode2", []> {
762 let EncoderMethod = "getAddrMode2OpValue";
763 let PrintMethod = "printAddrMode2Operand";
764 let ParserMatchClass = AddrMode2AsmOperand;
765 let MIOperandInfo = (ops GPR:$base, GPR:$offsreg, i32imm:$offsimm);
768 def PostIdxRegShiftedAsmOperand : AsmOperandClass {
769 let Name = "PostIdxRegShifted";
770 let ParserMethod = "parsePostIdxReg";
772 def am2offset_reg : Operand<i32>,
773 ComplexPattern<i32, 2, "SelectAddrMode2OffsetReg",
774 [], [SDNPWantRoot]> {
775 let EncoderMethod = "getAddrMode2OffsetOpValue";
776 let PrintMethod = "printAddrMode2OffsetOperand";
777 // When using this for assembly, it's always as a post-index offset.
778 let ParserMatchClass = PostIdxRegShiftedAsmOperand;
779 let MIOperandInfo = (ops GPRnopc, i32imm);
782 // FIXME: am2offset_imm should only need the immediate, not the GPR. Having
783 // the GPR is purely vestigal at this point.
784 def AM2OffsetImmAsmOperand : AsmOperandClass { let Name = "AM2OffsetImm"; }
785 def am2offset_imm : Operand<i32>,
786 ComplexPattern<i32, 2, "SelectAddrMode2OffsetImm",
787 [], [SDNPWantRoot]> {
788 let EncoderMethod = "getAddrMode2OffsetOpValue";
789 let PrintMethod = "printAddrMode2OffsetOperand";
790 let ParserMatchClass = AM2OffsetImmAsmOperand;
791 let MIOperandInfo = (ops GPRnopc, i32imm);
795 // addrmode3 := reg +/- reg
796 // addrmode3 := reg +/- imm8
798 // FIXME: split into imm vs. reg versions.
799 def AddrMode3AsmOperand : AsmOperandClass { let Name = "AddrMode3"; }
800 def addrmode3 : Operand<i32>,
801 ComplexPattern<i32, 3, "SelectAddrMode3", []> {
802 let EncoderMethod = "getAddrMode3OpValue";
803 let PrintMethod = "printAddrMode3Operand";
804 let ParserMatchClass = AddrMode3AsmOperand;
805 let MIOperandInfo = (ops GPR:$base, GPR:$offsreg, i32imm:$offsimm);
808 // FIXME: split into imm vs. reg versions.
809 // FIXME: parser method to handle +/- register.
810 def AM3OffsetAsmOperand : AsmOperandClass {
811 let Name = "AM3Offset";
812 let ParserMethod = "parseAM3Offset";
814 def am3offset : Operand<i32>,
815 ComplexPattern<i32, 2, "SelectAddrMode3Offset",
816 [], [SDNPWantRoot]> {
817 let EncoderMethod = "getAddrMode3OffsetOpValue";
818 let PrintMethod = "printAddrMode3OffsetOperand";
819 let ParserMatchClass = AM3OffsetAsmOperand;
820 let MIOperandInfo = (ops GPR, i32imm);
823 // ldstm_mode := {ia, ib, da, db}
825 def ldstm_mode : OptionalDefOperand<OtherVT, (ops i32), (ops (i32 1))> {
826 let EncoderMethod = "getLdStmModeOpValue";
827 let PrintMethod = "printLdStmModeOperand";
830 // addrmode5 := reg +/- imm8*4
832 def AddrMode5AsmOperand : AsmOperandClass { let Name = "AddrMode5"; }
833 def addrmode5 : Operand<i32>,
834 ComplexPattern<i32, 2, "SelectAddrMode5", []> {
835 let PrintMethod = "printAddrMode5Operand";
836 let EncoderMethod = "getAddrMode5OpValue";
837 let DecoderMethod = "DecodeAddrMode5Operand";
838 let ParserMatchClass = AddrMode5AsmOperand;
839 let MIOperandInfo = (ops GPR:$base, i32imm);
842 // addrmode6 := reg with optional alignment
844 def AddrMode6AsmOperand : AsmOperandClass { let Name = "AlignedMemory"; }
845 def addrmode6 : Operand<i32>,
846 ComplexPattern<i32, 2, "SelectAddrMode6", [], [SDNPWantParent]>{
847 let PrintMethod = "printAddrMode6Operand";
848 let MIOperandInfo = (ops GPR:$addr, i32imm:$align);
849 let EncoderMethod = "getAddrMode6AddressOpValue";
850 let DecoderMethod = "DecodeAddrMode6Operand";
851 let ParserMatchClass = AddrMode6AsmOperand;
854 def am6offset : Operand<i32>,
855 ComplexPattern<i32, 1, "SelectAddrMode6Offset",
856 [], [SDNPWantRoot]> {
857 let PrintMethod = "printAddrMode6OffsetOperand";
858 let MIOperandInfo = (ops GPR);
859 let EncoderMethod = "getAddrMode6OffsetOpValue";
860 let DecoderMethod = "DecodeGPRRegisterClass";
863 // Special version of addrmode6 to handle alignment encoding for VST1/VLD1
864 // (single element from one lane) for size 32.
865 def addrmode6oneL32 : Operand<i32>,
866 ComplexPattern<i32, 2, "SelectAddrMode6", [], [SDNPWantParent]>{
867 let PrintMethod = "printAddrMode6Operand";
868 let MIOperandInfo = (ops GPR:$addr, i32imm);
869 let EncoderMethod = "getAddrMode6OneLane32AddressOpValue";
872 // Special version of addrmode6 to handle alignment encoding for VLD-dup
873 // instructions, specifically VLD4-dup.
874 def addrmode6dup : Operand<i32>,
875 ComplexPattern<i32, 2, "SelectAddrMode6", [], [SDNPWantParent]>{
876 let PrintMethod = "printAddrMode6Operand";
877 let MIOperandInfo = (ops GPR:$addr, i32imm);
878 let EncoderMethod = "getAddrMode6DupAddressOpValue";
879 // FIXME: This is close, but not quite right. The alignment specifier is
881 let ParserMatchClass = AddrMode6AsmOperand;
884 // addrmodepc := pc + reg
886 def addrmodepc : Operand<i32>,
887 ComplexPattern<i32, 2, "SelectAddrModePC", []> {
888 let PrintMethod = "printAddrModePCOperand";
889 let MIOperandInfo = (ops GPR, i32imm);
892 // addr_offset_none := reg
894 def MemNoOffsetAsmOperand : AsmOperandClass { let Name = "MemNoOffset"; }
895 def addr_offset_none : Operand<i32>,
896 ComplexPattern<i32, 1, "SelectAddrOffsetNone", []> {
897 let PrintMethod = "printAddrMode7Operand";
898 let DecoderMethod = "DecodeAddrMode7Operand";
899 let ParserMatchClass = MemNoOffsetAsmOperand;
900 let MIOperandInfo = (ops GPR:$base);
903 def nohash_imm : Operand<i32> {
904 let PrintMethod = "printNoHashImmediate";
907 def CoprocNumAsmOperand : AsmOperandClass {
908 let Name = "CoprocNum";
909 let ParserMethod = "parseCoprocNumOperand";
911 def p_imm : Operand<i32> {
912 let PrintMethod = "printPImmediate";
913 let ParserMatchClass = CoprocNumAsmOperand;
914 let DecoderMethod = "DecodeCoprocessor";
917 def pf_imm : Operand<i32> {
918 let PrintMethod = "printPImmediate";
919 let ParserMatchClass = CoprocNumAsmOperand;
922 def CoprocRegAsmOperand : AsmOperandClass {
923 let Name = "CoprocReg";
924 let ParserMethod = "parseCoprocRegOperand";
926 def c_imm : Operand<i32> {
927 let PrintMethod = "printCImmediate";
928 let ParserMatchClass = CoprocRegAsmOperand;
930 def CoprocOptionAsmOperand : AsmOperandClass {
931 let Name = "CoprocOption";
932 let ParserMethod = "parseCoprocOptionOperand";
934 def coproc_option_imm : Operand<i32> {
935 let PrintMethod = "printCoprocOptionImm";
936 let ParserMatchClass = CoprocOptionAsmOperand;
939 //===----------------------------------------------------------------------===//
941 include "ARMInstrFormats.td"
943 //===----------------------------------------------------------------------===//
944 // Multiclass helpers...
947 /// AsI1_bin_irs - Defines a set of (op r, {so_imm|r|so_reg}) patterns for a
948 /// binop that produces a value.
949 let TwoOperandAliasConstraint = "$Rn = $Rd" in
950 multiclass AsI1_bin_irs<bits<4> opcod, string opc,
951 InstrItinClass iii, InstrItinClass iir, InstrItinClass iis,
952 PatFrag opnode, string baseOpc, bit Commutable = 0> {
953 // The register-immediate version is re-materializable. This is useful
954 // in particular for taking the address of a local.
955 let isReMaterializable = 1 in {
956 def ri : AsI1<opcod, (outs GPR:$Rd), (ins GPR:$Rn, so_imm:$imm), DPFrm,
957 iii, opc, "\t$Rd, $Rn, $imm",
958 [(set GPR:$Rd, (opnode GPR:$Rn, so_imm:$imm))]> {
963 let Inst{19-16} = Rn;
964 let Inst{15-12} = Rd;
965 let Inst{11-0} = imm;
968 def rr : AsI1<opcod, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm), DPFrm,
969 iir, opc, "\t$Rd, $Rn, $Rm",
970 [(set GPR:$Rd, (opnode GPR:$Rn, GPR:$Rm))]> {
975 let isCommutable = Commutable;
976 let Inst{19-16} = Rn;
977 let Inst{15-12} = Rd;
978 let Inst{11-4} = 0b00000000;
982 def rsi : AsI1<opcod, (outs GPR:$Rd),
983 (ins GPR:$Rn, so_reg_imm:$shift), DPSoRegImmFrm,
984 iis, opc, "\t$Rd, $Rn, $shift",
985 [(set GPR:$Rd, (opnode GPR:$Rn, so_reg_imm:$shift))]> {
990 let Inst{19-16} = Rn;
991 let Inst{15-12} = Rd;
992 let Inst{11-5} = shift{11-5};
994 let Inst{3-0} = shift{3-0};
997 def rsr : AsI1<opcod, (outs GPR:$Rd),
998 (ins GPR:$Rn, so_reg_reg:$shift), DPSoRegRegFrm,
999 iis, opc, "\t$Rd, $Rn, $shift",
1000 [(set GPR:$Rd, (opnode GPR:$Rn, so_reg_reg:$shift))]> {
1005 let Inst{19-16} = Rn;
1006 let Inst{15-12} = Rd;
1007 let Inst{11-8} = shift{11-8};
1009 let Inst{6-5} = shift{6-5};
1011 let Inst{3-0} = shift{3-0};
1015 /// AsI1_rbin_irs - Same as AsI1_bin_irs except the order of operands are
1016 /// reversed. The 'rr' form is only defined for the disassembler; for codegen
1017 /// it is equivalent to the AsI1_bin_irs counterpart.
1018 let TwoOperandAliasConstraint = "$Rn = $Rd" in
1019 multiclass AsI1_rbin_irs<bits<4> opcod, string opc,
1020 InstrItinClass iii, InstrItinClass iir, InstrItinClass iis,
1021 PatFrag opnode, string baseOpc, bit Commutable = 0> {
1022 // The register-immediate version is re-materializable. This is useful
1023 // in particular for taking the address of a local.
1024 let isReMaterializable = 1 in {
1025 def ri : AsI1<opcod, (outs GPR:$Rd), (ins GPR:$Rn, so_imm:$imm), DPFrm,
1026 iii, opc, "\t$Rd, $Rn, $imm",
1027 [(set GPR:$Rd, (opnode so_imm:$imm, GPR:$Rn))]> {
1032 let Inst{19-16} = Rn;
1033 let Inst{15-12} = Rd;
1034 let Inst{11-0} = imm;
1037 def rr : AsI1<opcod, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm), DPFrm,
1038 iir, opc, "\t$Rd, $Rn, $Rm",
1039 [/* pattern left blank */]> {
1043 let Inst{11-4} = 0b00000000;
1046 let Inst{15-12} = Rd;
1047 let Inst{19-16} = Rn;
1050 def rsi : AsI1<opcod, (outs GPR:$Rd),
1051 (ins GPR:$Rn, so_reg_imm:$shift), DPSoRegImmFrm,
1052 iis, opc, "\t$Rd, $Rn, $shift",
1053 [(set GPR:$Rd, (opnode so_reg_imm:$shift, GPR:$Rn))]> {
1058 let Inst{19-16} = Rn;
1059 let Inst{15-12} = Rd;
1060 let Inst{11-5} = shift{11-5};
1062 let Inst{3-0} = shift{3-0};
1065 def rsr : AsI1<opcod, (outs GPR:$Rd),
1066 (ins GPR:$Rn, so_reg_reg:$shift), DPSoRegRegFrm,
1067 iis, opc, "\t$Rd, $Rn, $shift",
1068 [(set GPR:$Rd, (opnode so_reg_reg:$shift, GPR:$Rn))]> {
1073 let Inst{19-16} = Rn;
1074 let Inst{15-12} = Rd;
1075 let Inst{11-8} = shift{11-8};
1077 let Inst{6-5} = shift{6-5};
1079 let Inst{3-0} = shift{3-0};
1083 /// AsI1_bin_s_irs - Same as AsI1_bin_irs except it sets the 's' bit by default.
1085 /// These opcodes will be converted to the real non-S opcodes by
1086 /// AdjustInstrPostInstrSelection after giving them an optional CPSR operand.
1087 let hasPostISelHook = 1, Defs = [CPSR] in {
1088 multiclass AsI1_bin_s_irs<InstrItinClass iii, InstrItinClass iir,
1089 InstrItinClass iis, PatFrag opnode,
1090 bit Commutable = 0> {
1091 def ri : ARMPseudoInst<(outs GPR:$Rd), (ins GPR:$Rn, so_imm:$imm, pred:$p),
1093 [(set GPR:$Rd, CPSR, (opnode GPR:$Rn, so_imm:$imm))]>;
1095 def rr : ARMPseudoInst<(outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm, pred:$p),
1097 [(set GPR:$Rd, CPSR, (opnode GPR:$Rn, GPR:$Rm))]> {
1098 let isCommutable = Commutable;
1100 def rsi : ARMPseudoInst<(outs GPR:$Rd),
1101 (ins GPR:$Rn, so_reg_imm:$shift, pred:$p),
1103 [(set GPR:$Rd, CPSR, (opnode GPR:$Rn,
1104 so_reg_imm:$shift))]>;
1106 def rsr : ARMPseudoInst<(outs GPR:$Rd),
1107 (ins GPR:$Rn, so_reg_reg:$shift, pred:$p),
1109 [(set GPR:$Rd, CPSR, (opnode GPR:$Rn,
1110 so_reg_reg:$shift))]>;
1114 /// AsI1_rbin_s_is - Same as AsI1_bin_s_irs, except selection DAG
1115 /// operands are reversed.
1116 let hasPostISelHook = 1, Defs = [CPSR] in {
1117 multiclass AsI1_rbin_s_is<InstrItinClass iii, InstrItinClass iir,
1118 InstrItinClass iis, PatFrag opnode,
1119 bit Commutable = 0> {
1120 def ri : ARMPseudoInst<(outs GPR:$Rd), (ins GPR:$Rn, so_imm:$imm, pred:$p),
1122 [(set GPR:$Rd, CPSR, (opnode so_imm:$imm, GPR:$Rn))]>;
1124 def rsi : ARMPseudoInst<(outs GPR:$Rd),
1125 (ins GPR:$Rn, so_reg_imm:$shift, pred:$p),
1127 [(set GPR:$Rd, CPSR, (opnode so_reg_imm:$shift,
1130 def rsr : ARMPseudoInst<(outs GPR:$Rd),
1131 (ins GPR:$Rn, so_reg_reg:$shift, pred:$p),
1133 [(set GPR:$Rd, CPSR, (opnode so_reg_reg:$shift,
1138 /// AI1_cmp_irs - Defines a set of (op r, {so_imm|r|so_reg}) cmp / test
1139 /// patterns. Similar to AsI1_bin_irs except the instruction does not produce
1140 /// a explicit result, only implicitly set CPSR.
1141 let isCompare = 1, Defs = [CPSR] in {
1142 multiclass AI1_cmp_irs<bits<4> opcod, string opc,
1143 InstrItinClass iii, InstrItinClass iir, InstrItinClass iis,
1144 PatFrag opnode, bit Commutable = 0> {
1145 def ri : AI1<opcod, (outs), (ins GPR:$Rn, so_imm:$imm), DPFrm, iii,
1147 [(opnode GPR:$Rn, so_imm:$imm)]> {
1152 let Inst{19-16} = Rn;
1153 let Inst{15-12} = 0b0000;
1154 let Inst{11-0} = imm;
1156 let Unpredictable{15-12} = 0b1111;
1158 def rr : AI1<opcod, (outs), (ins GPR:$Rn, GPR:$Rm), DPFrm, iir,
1160 [(opnode GPR:$Rn, GPR:$Rm)]> {
1163 let isCommutable = Commutable;
1166 let Inst{19-16} = Rn;
1167 let Inst{15-12} = 0b0000;
1168 let Inst{11-4} = 0b00000000;
1171 let Unpredictable{15-12} = 0b1111;
1173 def rsi : AI1<opcod, (outs),
1174 (ins GPR:$Rn, so_reg_imm:$shift), DPSoRegImmFrm, iis,
1175 opc, "\t$Rn, $shift",
1176 [(opnode GPR:$Rn, so_reg_imm:$shift)]> {
1181 let Inst{19-16} = Rn;
1182 let Inst{15-12} = 0b0000;
1183 let Inst{11-5} = shift{11-5};
1185 let Inst{3-0} = shift{3-0};
1187 let Unpredictable{15-12} = 0b1111;
1189 def rsr : AI1<opcod, (outs),
1190 (ins GPRnopc:$Rn, so_reg_reg:$shift), DPSoRegRegFrm, iis,
1191 opc, "\t$Rn, $shift",
1192 [(opnode GPRnopc:$Rn, so_reg_reg:$shift)]> {
1197 let Inst{19-16} = Rn;
1198 let Inst{15-12} = 0b0000;
1199 let Inst{11-8} = shift{11-8};
1201 let Inst{6-5} = shift{6-5};
1203 let Inst{3-0} = shift{3-0};
1205 let Unpredictable{15-12} = 0b1111;
1211 /// AI_ext_rrot - A unary operation with two forms: one whose operand is a
1212 /// register and one whose operand is a register rotated by 8/16/24.
1213 /// FIXME: Remove the 'r' variant. Its rot_imm is zero.
1214 class AI_ext_rrot<bits<8> opcod, string opc, PatFrag opnode>
1215 : AExtI<opcod, (outs GPRnopc:$Rd), (ins GPRnopc:$Rm, rot_imm:$rot),
1216 IIC_iEXTr, opc, "\t$Rd, $Rm$rot",
1217 [(set GPRnopc:$Rd, (opnode (rotr GPRnopc:$Rm, rot_imm:$rot)))]>,
1218 Requires<[IsARM, HasV6]> {
1222 let Inst{19-16} = 0b1111;
1223 let Inst{15-12} = Rd;
1224 let Inst{11-10} = rot;
1228 class AI_ext_rrot_np<bits<8> opcod, string opc>
1229 : AExtI<opcod, (outs GPRnopc:$Rd), (ins GPRnopc:$Rm, rot_imm:$rot),
1230 IIC_iEXTr, opc, "\t$Rd, $Rm$rot", []>,
1231 Requires<[IsARM, HasV6]> {
1233 let Inst{19-16} = 0b1111;
1234 let Inst{11-10} = rot;
1237 /// AI_exta_rrot - A binary operation with two forms: one whose operand is a
1238 /// register and one whose operand is a register rotated by 8/16/24.
1239 class AI_exta_rrot<bits<8> opcod, string opc, PatFrag opnode>
1240 : AExtI<opcod, (outs GPRnopc:$Rd), (ins GPR:$Rn, GPRnopc:$Rm, rot_imm:$rot),
1241 IIC_iEXTAr, opc, "\t$Rd, $Rn, $Rm$rot",
1242 [(set GPRnopc:$Rd, (opnode GPR:$Rn,
1243 (rotr GPRnopc:$Rm, rot_imm:$rot)))]>,
1244 Requires<[IsARM, HasV6]> {
1249 let Inst{19-16} = Rn;
1250 let Inst{15-12} = Rd;
1251 let Inst{11-10} = rot;
1252 let Inst{9-4} = 0b000111;
1256 class AI_exta_rrot_np<bits<8> opcod, string opc>
1257 : AExtI<opcod, (outs GPRnopc:$Rd), (ins GPR:$Rn, GPRnopc:$Rm, rot_imm:$rot),
1258 IIC_iEXTAr, opc, "\t$Rd, $Rn, $Rm$rot", []>,
1259 Requires<[IsARM, HasV6]> {
1262 let Inst{19-16} = Rn;
1263 let Inst{11-10} = rot;
1266 /// AI1_adde_sube_irs - Define instructions and patterns for adde and sube.
1267 let TwoOperandAliasConstraint = "$Rn = $Rd" in
1268 multiclass AI1_adde_sube_irs<bits<4> opcod, string opc, PatFrag opnode,
1269 string baseOpc, bit Commutable = 0> {
1270 let hasPostISelHook = 1, Defs = [CPSR], Uses = [CPSR] in {
1271 def ri : AsI1<opcod, (outs GPR:$Rd), (ins GPR:$Rn, so_imm:$imm),
1272 DPFrm, IIC_iALUi, opc, "\t$Rd, $Rn, $imm",
1273 [(set GPR:$Rd, CPSR, (opnode GPR:$Rn, so_imm:$imm, CPSR))]>,
1279 let Inst{15-12} = Rd;
1280 let Inst{19-16} = Rn;
1281 let Inst{11-0} = imm;
1283 def rr : AsI1<opcod, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm),
1284 DPFrm, IIC_iALUr, opc, "\t$Rd, $Rn, $Rm",
1285 [(set GPR:$Rd, CPSR, (opnode GPR:$Rn, GPR:$Rm, CPSR))]>,
1290 let Inst{11-4} = 0b00000000;
1292 let isCommutable = Commutable;
1294 let Inst{15-12} = Rd;
1295 let Inst{19-16} = Rn;
1297 def rsi : AsI1<opcod, (outs GPR:$Rd),
1298 (ins GPR:$Rn, so_reg_imm:$shift),
1299 DPSoRegImmFrm, IIC_iALUsr, opc, "\t$Rd, $Rn, $shift",
1300 [(set GPR:$Rd, CPSR, (opnode GPR:$Rn, so_reg_imm:$shift, CPSR))]>,
1306 let Inst{19-16} = Rn;
1307 let Inst{15-12} = Rd;
1308 let Inst{11-5} = shift{11-5};
1310 let Inst{3-0} = shift{3-0};
1312 def rsr : AsI1<opcod, (outs GPRnopc:$Rd),
1313 (ins GPRnopc:$Rn, so_reg_reg:$shift),
1314 DPSoRegRegFrm, IIC_iALUsr, opc, "\t$Rd, $Rn, $shift",
1315 [(set GPRnopc:$Rd, CPSR,
1316 (opnode GPRnopc:$Rn, so_reg_reg:$shift, CPSR))]>,
1322 let Inst{19-16} = Rn;
1323 let Inst{15-12} = Rd;
1324 let Inst{11-8} = shift{11-8};
1326 let Inst{6-5} = shift{6-5};
1328 let Inst{3-0} = shift{3-0};
1333 /// AI1_rsc_irs - Define instructions and patterns for rsc
1334 let TwoOperandAliasConstraint = "$Rn = $Rd" in
1335 multiclass AI1_rsc_irs<bits<4> opcod, string opc, PatFrag opnode,
1337 let hasPostISelHook = 1, Defs = [CPSR], Uses = [CPSR] in {
1338 def ri : AsI1<opcod, (outs GPR:$Rd), (ins GPR:$Rn, so_imm:$imm),
1339 DPFrm, IIC_iALUi, opc, "\t$Rd, $Rn, $imm",
1340 [(set GPR:$Rd, CPSR, (opnode so_imm:$imm, GPR:$Rn, CPSR))]>,
1346 let Inst{15-12} = Rd;
1347 let Inst{19-16} = Rn;
1348 let Inst{11-0} = imm;
1350 def rr : AsI1<opcod, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm),
1351 DPFrm, IIC_iALUr, opc, "\t$Rd, $Rn, $Rm",
1352 [/* pattern left blank */]> {
1356 let Inst{11-4} = 0b00000000;
1359 let Inst{15-12} = Rd;
1360 let Inst{19-16} = Rn;
1362 def rsi : AsI1<opcod, (outs GPR:$Rd), (ins GPR:$Rn, so_reg_imm:$shift),
1363 DPSoRegImmFrm, IIC_iALUsr, opc, "\t$Rd, $Rn, $shift",
1364 [(set GPR:$Rd, CPSR, (opnode so_reg_imm:$shift, GPR:$Rn, CPSR))]>,
1370 let Inst{19-16} = Rn;
1371 let Inst{15-12} = Rd;
1372 let Inst{11-5} = shift{11-5};
1374 let Inst{3-0} = shift{3-0};
1376 def rsr : AsI1<opcod, (outs GPR:$Rd), (ins GPR:$Rn, so_reg_reg:$shift),
1377 DPSoRegRegFrm, IIC_iALUsr, opc, "\t$Rd, $Rn, $shift",
1378 [(set GPR:$Rd, CPSR, (opnode so_reg_reg:$shift, GPR:$Rn, CPSR))]>,
1384 let Inst{19-16} = Rn;
1385 let Inst{15-12} = Rd;
1386 let Inst{11-8} = shift{11-8};
1388 let Inst{6-5} = shift{6-5};
1390 let Inst{3-0} = shift{3-0};
1395 let canFoldAsLoad = 1, isReMaterializable = 1 in {
1396 multiclass AI_ldr1<bit isByte, string opc, InstrItinClass iii,
1397 InstrItinClass iir, PatFrag opnode> {
1398 // Note: We use the complex addrmode_imm12 rather than just an input
1399 // GPR and a constrained immediate so that we can use this to match
1400 // frame index references and avoid matching constant pool references.
1401 def i12: AI2ldst<0b010, 1, isByte, (outs GPR:$Rt), (ins addrmode_imm12:$addr),
1402 AddrMode_i12, LdFrm, iii, opc, "\t$Rt, $addr",
1403 [(set GPR:$Rt, (opnode addrmode_imm12:$addr))]> {
1406 let Inst{23} = addr{12}; // U (add = ('U' == 1))
1407 let Inst{19-16} = addr{16-13}; // Rn
1408 let Inst{15-12} = Rt;
1409 let Inst{11-0} = addr{11-0}; // imm12
1411 def rs : AI2ldst<0b011, 1, isByte, (outs GPR:$Rt), (ins ldst_so_reg:$shift),
1412 AddrModeNone, LdFrm, iir, opc, "\t$Rt, $shift",
1413 [(set GPR:$Rt, (opnode ldst_so_reg:$shift))]> {
1416 let shift{4} = 0; // Inst{4} = 0
1417 let Inst{23} = shift{12}; // U (add = ('U' == 1))
1418 let Inst{19-16} = shift{16-13}; // Rn
1419 let Inst{15-12} = Rt;
1420 let Inst{11-0} = shift{11-0};
1425 let canFoldAsLoad = 1, isReMaterializable = 1 in {
1426 multiclass AI_ldr1nopc<bit isByte, string opc, InstrItinClass iii,
1427 InstrItinClass iir, PatFrag opnode> {
1428 // Note: We use the complex addrmode_imm12 rather than just an input
1429 // GPR and a constrained immediate so that we can use this to match
1430 // frame index references and avoid matching constant pool references.
1431 def i12: AI2ldst<0b010, 1, isByte, (outs GPRnopc:$Rt),
1432 (ins addrmode_imm12:$addr),
1433 AddrMode_i12, LdFrm, iii, opc, "\t$Rt, $addr",
1434 [(set GPRnopc:$Rt, (opnode addrmode_imm12:$addr))]> {
1437 let Inst{23} = addr{12}; // U (add = ('U' == 1))
1438 let Inst{19-16} = addr{16-13}; // Rn
1439 let Inst{15-12} = Rt;
1440 let Inst{11-0} = addr{11-0}; // imm12
1442 def rs : AI2ldst<0b011, 1, isByte, (outs GPRnopc:$Rt),
1443 (ins ldst_so_reg:$shift),
1444 AddrModeNone, LdFrm, iir, opc, "\t$Rt, $shift",
1445 [(set GPRnopc:$Rt, (opnode ldst_so_reg:$shift))]> {
1448 let shift{4} = 0; // Inst{4} = 0
1449 let Inst{23} = shift{12}; // U (add = ('U' == 1))
1450 let Inst{19-16} = shift{16-13}; // Rn
1451 let Inst{15-12} = Rt;
1452 let Inst{11-0} = shift{11-0};
1458 multiclass AI_str1<bit isByte, string opc, InstrItinClass iii,
1459 InstrItinClass iir, PatFrag opnode> {
1460 // Note: We use the complex addrmode_imm12 rather than just an input
1461 // GPR and a constrained immediate so that we can use this to match
1462 // frame index references and avoid matching constant pool references.
1463 def i12 : AI2ldst<0b010, 0, isByte, (outs),
1464 (ins GPR:$Rt, addrmode_imm12:$addr),
1465 AddrMode_i12, StFrm, iii, opc, "\t$Rt, $addr",
1466 [(opnode GPR:$Rt, addrmode_imm12:$addr)]> {
1469 let Inst{23} = addr{12}; // U (add = ('U' == 1))
1470 let Inst{19-16} = addr{16-13}; // Rn
1471 let Inst{15-12} = Rt;
1472 let Inst{11-0} = addr{11-0}; // imm12
1474 def rs : AI2ldst<0b011, 0, isByte, (outs), (ins GPR:$Rt, ldst_so_reg:$shift),
1475 AddrModeNone, StFrm, iir, opc, "\t$Rt, $shift",
1476 [(opnode GPR:$Rt, ldst_so_reg:$shift)]> {
1479 let shift{4} = 0; // Inst{4} = 0
1480 let Inst{23} = shift{12}; // U (add = ('U' == 1))
1481 let Inst{19-16} = shift{16-13}; // Rn
1482 let Inst{15-12} = Rt;
1483 let Inst{11-0} = shift{11-0};
1487 multiclass AI_str1nopc<bit isByte, string opc, InstrItinClass iii,
1488 InstrItinClass iir, PatFrag opnode> {
1489 // Note: We use the complex addrmode_imm12 rather than just an input
1490 // GPR and a constrained immediate so that we can use this to match
1491 // frame index references and avoid matching constant pool references.
1492 def i12 : AI2ldst<0b010, 0, isByte, (outs),
1493 (ins GPRnopc:$Rt, addrmode_imm12:$addr),
1494 AddrMode_i12, StFrm, iii, opc, "\t$Rt, $addr",
1495 [(opnode GPRnopc:$Rt, addrmode_imm12:$addr)]> {
1498 let Inst{23} = addr{12}; // U (add = ('U' == 1))
1499 let Inst{19-16} = addr{16-13}; // Rn
1500 let Inst{15-12} = Rt;
1501 let Inst{11-0} = addr{11-0}; // imm12
1503 def rs : AI2ldst<0b011, 0, isByte, (outs),
1504 (ins GPRnopc:$Rt, ldst_so_reg:$shift),
1505 AddrModeNone, StFrm, iir, opc, "\t$Rt, $shift",
1506 [(opnode GPRnopc:$Rt, ldst_so_reg:$shift)]> {
1509 let shift{4} = 0; // Inst{4} = 0
1510 let Inst{23} = shift{12}; // U (add = ('U' == 1))
1511 let Inst{19-16} = shift{16-13}; // Rn
1512 let Inst{15-12} = Rt;
1513 let Inst{11-0} = shift{11-0};
1518 //===----------------------------------------------------------------------===//
1520 //===----------------------------------------------------------------------===//
1522 //===----------------------------------------------------------------------===//
1523 // Miscellaneous Instructions.
1526 /// CONSTPOOL_ENTRY - This instruction represents a floating constant pool in
1527 /// the function. The first operand is the ID# for this instruction, the second
1528 /// is the index into the MachineConstantPool that this is, the third is the
1529 /// size in bytes of this constant pool entry.
1530 let neverHasSideEffects = 1, isNotDuplicable = 1 in
1531 def CONSTPOOL_ENTRY :
1532 PseudoInst<(outs), (ins cpinst_operand:$instid, cpinst_operand:$cpidx,
1533 i32imm:$size), NoItinerary, []>;
1535 // FIXME: Marking these as hasSideEffects is necessary to prevent machine DCE
1536 // from removing one half of the matched pairs. That breaks PEI, which assumes
1537 // these will always be in pairs, and asserts if it finds otherwise. Better way?
1538 let Defs = [SP], Uses = [SP], hasSideEffects = 1 in {
1539 def ADJCALLSTACKUP :
1540 PseudoInst<(outs), (ins i32imm:$amt1, i32imm:$amt2, pred:$p), NoItinerary,
1541 [(ARMcallseq_end timm:$amt1, timm:$amt2)]>;
1543 def ADJCALLSTACKDOWN :
1544 PseudoInst<(outs), (ins i32imm:$amt, pred:$p), NoItinerary,
1545 [(ARMcallseq_start timm:$amt)]>;
1548 // Atomic pseudo-insts which will be lowered to ldrexd/strexd loops.
1549 // (These pseudos use a hand-written selection code).
1550 let usesCustomInserter = 1, Defs = [CPSR], mayLoad = 1, mayStore = 1 in {
1551 def ATOMOR6432 : PseudoInst<(outs GPR:$dst1, GPR:$dst2),
1552 (ins GPR:$addr, GPR:$src1, GPR:$src2),
1554 def ATOMXOR6432 : PseudoInst<(outs GPR:$dst1, GPR:$dst2),
1555 (ins GPR:$addr, GPR:$src1, GPR:$src2),
1557 def ATOMADD6432 : PseudoInst<(outs GPR:$dst1, GPR:$dst2),
1558 (ins GPR:$addr, GPR:$src1, GPR:$src2),
1560 def ATOMSUB6432 : PseudoInst<(outs GPR:$dst1, GPR:$dst2),
1561 (ins GPR:$addr, GPR:$src1, GPR:$src2),
1563 def ATOMNAND6432 : PseudoInst<(outs GPR:$dst1, GPR:$dst2),
1564 (ins GPR:$addr, GPR:$src1, GPR:$src2),
1566 def ATOMAND6432 : PseudoInst<(outs GPR:$dst1, GPR:$dst2),
1567 (ins GPR:$addr, GPR:$src1, GPR:$src2),
1569 def ATOMSWAP6432 : PseudoInst<(outs GPR:$dst1, GPR:$dst2),
1570 (ins GPR:$addr, GPR:$src1, GPR:$src2),
1572 def ATOMCMPXCHG6432 : PseudoInst<(outs GPR:$dst1, GPR:$dst2),
1573 (ins GPR:$addr, GPR:$cmp1, GPR:$cmp2,
1574 GPR:$set1, GPR:$set2),
1578 def NOP : AI<(outs), (ins), MiscFrm, NoItinerary, "nop", "", []>,
1579 Requires<[IsARM, HasV6T2]> {
1580 let Inst{27-16} = 0b001100100000;
1581 let Inst{15-8} = 0b11110000;
1582 let Inst{7-0} = 0b00000000;
1585 def YIELD : AI<(outs), (ins), MiscFrm, NoItinerary, "yield", "", []>,
1586 Requires<[IsARM, HasV6T2]> {
1587 let Inst{27-16} = 0b001100100000;
1588 let Inst{15-8} = 0b11110000;
1589 let Inst{7-0} = 0b00000001;
1592 def WFE : AI<(outs), (ins), MiscFrm, NoItinerary, "wfe", "", []>,
1593 Requires<[IsARM, HasV6T2]> {
1594 let Inst{27-16} = 0b001100100000;
1595 let Inst{15-8} = 0b11110000;
1596 let Inst{7-0} = 0b00000010;
1599 def WFI : AI<(outs), (ins), MiscFrm, NoItinerary, "wfi", "", []>,
1600 Requires<[IsARM, HasV6T2]> {
1601 let Inst{27-16} = 0b001100100000;
1602 let Inst{15-8} = 0b11110000;
1603 let Inst{7-0} = 0b00000011;
1606 def SEL : AI<(outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm), DPFrm, NoItinerary, "sel",
1607 "\t$Rd, $Rn, $Rm", []>, Requires<[IsARM, HasV6]> {
1612 let Inst{15-12} = Rd;
1613 let Inst{19-16} = Rn;
1614 let Inst{27-20} = 0b01101000;
1615 let Inst{7-4} = 0b1011;
1616 let Inst{11-8} = 0b1111;
1619 def SEV : AI<(outs), (ins), MiscFrm, NoItinerary, "sev", "",
1620 []>, Requires<[IsARM, HasV6T2]> {
1621 let Inst{27-16} = 0b001100100000;
1622 let Inst{15-8} = 0b11110000;
1623 let Inst{7-0} = 0b00000100;
1626 // The i32imm operand $val can be used by a debugger to store more information
1627 // about the breakpoint.
1628 def BKPT : AI<(outs), (ins imm0_65535:$val), MiscFrm, NoItinerary,
1629 "bkpt", "\t$val", []>, Requires<[IsARM]> {
1631 let Inst{3-0} = val{3-0};
1632 let Inst{19-8} = val{15-4};
1633 let Inst{27-20} = 0b00010010;
1634 let Inst{7-4} = 0b0111;
1637 // Change Processor State
1638 // FIXME: We should use InstAlias to handle the optional operands.
1639 class CPS<dag iops, string asm_ops>
1640 : AXI<(outs), iops, MiscFrm, NoItinerary, !strconcat("cps", asm_ops),
1641 []>, Requires<[IsARM]> {
1647 let Inst{31-28} = 0b1111;
1648 let Inst{27-20} = 0b00010000;
1649 let Inst{19-18} = imod;
1650 let Inst{17} = M; // Enabled if mode is set;
1651 let Inst{16-9} = 0b00000000;
1652 let Inst{8-6} = iflags;
1654 let Inst{4-0} = mode;
1657 let DecoderMethod = "DecodeCPSInstruction" in {
1659 def CPS3p : CPS<(ins imod_op:$imod, iflags_op:$iflags, imm0_31:$mode),
1660 "$imod\t$iflags, $mode">;
1661 let mode = 0, M = 0 in
1662 def CPS2p : CPS<(ins imod_op:$imod, iflags_op:$iflags), "$imod\t$iflags">;
1664 let imod = 0, iflags = 0, M = 1 in
1665 def CPS1p : CPS<(ins imm0_31:$mode), "\t$mode">;
1668 // Preload signals the memory system of possible future data/instruction access.
1669 multiclass APreLoad<bits<1> read, bits<1> data, string opc> {
1671 def i12 : AXI<(outs), (ins addrmode_imm12:$addr), MiscFrm, IIC_Preload,
1672 !strconcat(opc, "\t$addr"),
1673 [(ARMPreload addrmode_imm12:$addr, (i32 read), (i32 data))]> {
1676 let Inst{31-26} = 0b111101;
1677 let Inst{25} = 0; // 0 for immediate form
1678 let Inst{24} = data;
1679 let Inst{23} = addr{12}; // U (add = ('U' == 1))
1680 let Inst{22} = read;
1681 let Inst{21-20} = 0b01;
1682 let Inst{19-16} = addr{16-13}; // Rn
1683 let Inst{15-12} = 0b1111;
1684 let Inst{11-0} = addr{11-0}; // imm12
1687 def rs : AXI<(outs), (ins ldst_so_reg:$shift), MiscFrm, IIC_Preload,
1688 !strconcat(opc, "\t$shift"),
1689 [(ARMPreload ldst_so_reg:$shift, (i32 read), (i32 data))]> {
1691 let Inst{31-26} = 0b111101;
1692 let Inst{25} = 1; // 1 for register form
1693 let Inst{24} = data;
1694 let Inst{23} = shift{12}; // U (add = ('U' == 1))
1695 let Inst{22} = read;
1696 let Inst{21-20} = 0b01;
1697 let Inst{19-16} = shift{16-13}; // Rn
1698 let Inst{15-12} = 0b1111;
1699 let Inst{11-0} = shift{11-0};
1704 defm PLD : APreLoad<1, 1, "pld">, Requires<[IsARM]>;
1705 defm PLDW : APreLoad<0, 1, "pldw">, Requires<[IsARM,HasV7,HasMP]>;
1706 defm PLI : APreLoad<1, 0, "pli">, Requires<[IsARM,HasV7]>;
1708 def SETEND : AXI<(outs), (ins setend_op:$end), MiscFrm, NoItinerary,
1709 "setend\t$end", []>, Requires<[IsARM]> {
1711 let Inst{31-10} = 0b1111000100000001000000;
1716 def DBG : AI<(outs), (ins imm0_15:$opt), MiscFrm, NoItinerary, "dbg", "\t$opt",
1717 []>, Requires<[IsARM, HasV7]> {
1719 let Inst{27-4} = 0b001100100000111100001111;
1720 let Inst{3-0} = opt;
1723 // A5.4 Permanently UNDEFINED instructions.
1724 let isBarrier = 1, isTerminator = 1 in
1725 def TRAP : AXI<(outs), (ins), MiscFrm, NoItinerary,
1728 let Inst = 0xe7ffdefe;
1731 // Address computation and loads and stores in PIC mode.
1732 let isNotDuplicable = 1 in {
1733 def PICADD : ARMPseudoInst<(outs GPR:$dst), (ins GPR:$a, pclabel:$cp, pred:$p),
1735 [(set GPR:$dst, (ARMpic_add GPR:$a, imm:$cp))]>;
1737 let AddedComplexity = 10 in {
1738 def PICLDR : ARMPseudoInst<(outs GPR:$dst), (ins addrmodepc:$addr, pred:$p),
1740 [(set GPR:$dst, (load addrmodepc:$addr))]>;
1742 def PICLDRH : ARMPseudoInst<(outs GPR:$Rt), (ins addrmodepc:$addr, pred:$p),
1744 [(set GPR:$Rt, (zextloadi16 addrmodepc:$addr))]>;
1746 def PICLDRB : ARMPseudoInst<(outs GPR:$Rt), (ins addrmodepc:$addr, pred:$p),
1748 [(set GPR:$Rt, (zextloadi8 addrmodepc:$addr))]>;
1750 def PICLDRSH : ARMPseudoInst<(outs GPR:$Rt), (ins addrmodepc:$addr, pred:$p),
1752 [(set GPR:$Rt, (sextloadi16 addrmodepc:$addr))]>;
1754 def PICLDRSB : ARMPseudoInst<(outs GPR:$Rt), (ins addrmodepc:$addr, pred:$p),
1756 [(set GPR:$Rt, (sextloadi8 addrmodepc:$addr))]>;
1758 let AddedComplexity = 10 in {
1759 def PICSTR : ARMPseudoInst<(outs), (ins GPR:$src, addrmodepc:$addr, pred:$p),
1760 4, IIC_iStore_r, [(store GPR:$src, addrmodepc:$addr)]>;
1762 def PICSTRH : ARMPseudoInst<(outs), (ins GPR:$src, addrmodepc:$addr, pred:$p),
1763 4, IIC_iStore_bh_r, [(truncstorei16 GPR:$src,
1764 addrmodepc:$addr)]>;
1766 def PICSTRB : ARMPseudoInst<(outs), (ins GPR:$src, addrmodepc:$addr, pred:$p),
1767 4, IIC_iStore_bh_r, [(truncstorei8 GPR:$src, addrmodepc:$addr)]>;
1769 } // isNotDuplicable = 1
1772 // LEApcrel - Load a pc-relative address into a register without offending the
1774 let neverHasSideEffects = 1, isReMaterializable = 1 in
1775 // The 'adr' mnemonic encodes differently if the label is before or after
1776 // the instruction. The {24-21} opcode bits are set by the fixup, as we don't
1777 // know until then which form of the instruction will be used.
1778 def ADR : AI1<{0,?,?,0}, (outs GPR:$Rd), (ins adrlabel:$label),
1779 MiscFrm, IIC_iALUi, "adr", "\t$Rd, $label", []> {
1782 let Inst{27-25} = 0b001;
1784 let Inst{23-22} = label{13-12};
1787 let Inst{19-16} = 0b1111;
1788 let Inst{15-12} = Rd;
1789 let Inst{11-0} = label{11-0};
1791 def LEApcrel : ARMPseudoInst<(outs GPR:$Rd), (ins i32imm:$label, pred:$p),
1794 def LEApcrelJT : ARMPseudoInst<(outs GPR:$Rd),
1795 (ins i32imm:$label, nohash_imm:$id, pred:$p),
1798 //===----------------------------------------------------------------------===//
1799 // Control Flow Instructions.
1802 let isReturn = 1, isTerminator = 1, isBarrier = 1 in {
1804 def BX_RET : AI<(outs), (ins), BrMiscFrm, IIC_Br,
1805 "bx", "\tlr", [(ARMretflag)]>,
1806 Requires<[IsARM, HasV4T]> {
1807 let Inst{27-0} = 0b0001001011111111111100011110;
1811 def MOVPCLR : AI<(outs), (ins), BrMiscFrm, IIC_Br,
1812 "mov", "\tpc, lr", [(ARMretflag)]>,
1813 Requires<[IsARM, NoV4T]> {
1814 let Inst{27-0} = 0b0001101000001111000000001110;
1818 // Indirect branches
1819 let isBranch = 1, isTerminator = 1, isBarrier = 1, isIndirectBranch = 1 in {
1821 def BX : AXI<(outs), (ins GPR:$dst), BrMiscFrm, IIC_Br, "bx\t$dst",
1822 [(brind GPR:$dst)]>,
1823 Requires<[IsARM, HasV4T]> {
1825 let Inst{31-4} = 0b1110000100101111111111110001;
1826 let Inst{3-0} = dst;
1829 def BX_pred : AI<(outs), (ins GPR:$dst), BrMiscFrm, IIC_Br,
1830 "bx", "\t$dst", [/* pattern left blank */]>,
1831 Requires<[IsARM, HasV4T]> {
1833 let Inst{27-4} = 0b000100101111111111110001;
1834 let Inst{3-0} = dst;
1838 // SP is marked as a use to prevent stack-pointer assignments that appear
1839 // immediately before calls from potentially appearing dead.
1841 // FIXME: Do we really need a non-predicated version? If so, it should
1842 // at least be a pseudo instruction expanding to the predicated version
1843 // at MC lowering time.
1844 Defs = [LR], Uses = [SP] in {
1845 def BL : ABXI<0b1011, (outs), (ins bl_target:$func, variable_ops),
1846 IIC_Br, "bl\t$func",
1847 [(ARMcall tglobaladdr:$func)]>,
1849 let Inst{31-28} = 0b1110;
1851 let Inst{23-0} = func;
1852 let DecoderMethod = "DecodeBranchImmInstruction";
1855 def BL_pred : ABI<0b1011, (outs), (ins bl_target:$func, variable_ops),
1856 IIC_Br, "bl", "\t$func",
1857 [(ARMcall_pred tglobaladdr:$func)]>,
1860 let Inst{23-0} = func;
1861 let DecoderMethod = "DecodeBranchImmInstruction";
1865 def BLX : AXI<(outs), (ins GPR:$func, variable_ops), BrMiscFrm,
1866 IIC_Br, "blx\t$func",
1867 [(ARMcall GPR:$func)]>,
1868 Requires<[IsARM, HasV5T]> {
1870 let Inst{31-4} = 0b1110000100101111111111110011;
1871 let Inst{3-0} = func;
1874 def BLX_pred : AI<(outs), (ins GPR:$func, variable_ops), BrMiscFrm,
1875 IIC_Br, "blx", "\t$func",
1876 [(ARMcall_pred GPR:$func)]>,
1877 Requires<[IsARM, HasV5T]> {
1879 let Inst{27-4} = 0b000100101111111111110011;
1880 let Inst{3-0} = func;
1884 // Note: Restrict $func to the tGPR regclass to prevent it being in LR.
1885 def BX_CALL : ARMPseudoInst<(outs), (ins tGPR:$func, variable_ops),
1886 8, IIC_Br, [(ARMcall_nolink tGPR:$func)]>,
1887 Requires<[IsARM, HasV4T]>;
1890 def BMOVPCRX_CALL : ARMPseudoInst<(outs), (ins tGPR:$func, variable_ops),
1891 8, IIC_Br, [(ARMcall_nolink tGPR:$func)]>,
1892 Requires<[IsARM, NoV4T]>;
1894 // mov lr, pc; b if callee is marked noreturn to avoid confusing the
1895 // return stack predictor.
1896 def BMOVPCB_CALL : ARMPseudoInst<(outs),
1897 (ins bl_target:$func, variable_ops),
1898 8, IIC_Br, [(ARMcall_nolink tglobaladdr:$func)]>,
1902 let isBranch = 1, isTerminator = 1 in {
1903 // FIXME: should be able to write a pattern for ARMBrcond, but can't use
1904 // a two-value operand where a dag node expects two operands. :(
1905 def Bcc : ABI<0b1010, (outs), (ins br_target:$target),
1906 IIC_Br, "b", "\t$target",
1907 [/*(ARMbrcond bb:$target, imm:$cc, CCR:$ccr)*/]> {
1909 let Inst{23-0} = target;
1910 let DecoderMethod = "DecodeBranchImmInstruction";
1913 let isBarrier = 1 in {
1914 // B is "predicable" since it's just a Bcc with an 'always' condition.
1915 let isPredicable = 1 in
1916 // FIXME: We shouldn't need this pseudo at all. Just using Bcc directly
1917 // should be sufficient.
1918 // FIXME: Is B really a Barrier? That doesn't seem right.
1919 def B : ARMPseudoExpand<(outs), (ins br_target:$target), 4, IIC_Br,
1920 [(br bb:$target)], (Bcc br_target:$target, (ops 14, zero_reg))>;
1922 let isNotDuplicable = 1, isIndirectBranch = 1 in {
1923 def BR_JTr : ARMPseudoInst<(outs),
1924 (ins GPR:$target, i32imm:$jt, i32imm:$id),
1926 [(ARMbrjt GPR:$target, tjumptable:$jt, imm:$id)]>;
1927 // FIXME: This shouldn't use the generic "addrmode2," but rather be split
1928 // into i12 and rs suffixed versions.
1929 def BR_JTm : ARMPseudoInst<(outs),
1930 (ins addrmode2:$target, i32imm:$jt, i32imm:$id),
1932 [(ARMbrjt (i32 (load addrmode2:$target)), tjumptable:$jt,
1934 def BR_JTadd : ARMPseudoInst<(outs),
1935 (ins GPR:$target, GPR:$idx, i32imm:$jt, i32imm:$id),
1937 [(ARMbrjt (add GPR:$target, GPR:$idx), tjumptable:$jt,
1939 } // isNotDuplicable = 1, isIndirectBranch = 1
1945 def BLXi : AXI<(outs), (ins blx_target:$target), BrMiscFrm, NoItinerary,
1946 "blx\t$target", []>,
1947 Requires<[IsARM, HasV5T]> {
1948 let Inst{31-25} = 0b1111101;
1950 let Inst{23-0} = target{24-1};
1951 let Inst{24} = target{0};
1954 // Branch and Exchange Jazelle
1955 def BXJ : ABI<0b0001, (outs), (ins GPR:$func), NoItinerary, "bxj", "\t$func",
1956 [/* pattern left blank */]> {
1958 let Inst{23-20} = 0b0010;
1959 let Inst{19-8} = 0xfff;
1960 let Inst{7-4} = 0b0010;
1961 let Inst{3-0} = func;
1966 let isCall = 1, isTerminator = 1, isReturn = 1, isBarrier = 1, Uses = [SP] in {
1967 def TCRETURNdi : PseudoInst<(outs), (ins i32imm:$dst, variable_ops),
1970 def TCRETURNri : PseudoInst<(outs), (ins tcGPR:$dst, variable_ops),
1973 def TAILJMPd : ARMPseudoExpand<(outs), (ins br_target:$dst, variable_ops),
1975 (Bcc br_target:$dst, (ops 14, zero_reg))>,
1978 def TAILJMPr : ARMPseudoExpand<(outs), (ins tcGPR:$dst, variable_ops),
1984 // Secure Monitor Call is a system instruction.
1985 def SMC : ABI<0b0001, (outs), (ins imm0_15:$opt), NoItinerary, "smc", "\t$opt",
1988 let Inst{23-4} = 0b01100000000000000111;
1989 let Inst{3-0} = opt;
1992 // Supervisor Call (Software Interrupt)
1993 let isCall = 1, Uses = [SP] in {
1994 def SVC : ABI<0b1111, (outs), (ins imm24b:$svc), IIC_Br, "svc", "\t$svc", []> {
1996 let Inst{23-0} = svc;
2000 // Store Return State
2001 class SRSI<bit wb, string asm>
2002 : XI<(outs), (ins imm0_31:$mode), AddrModeNone, 4, IndexModeNone, BrFrm,
2003 NoItinerary, asm, "", []> {
2005 let Inst{31-28} = 0b1111;
2006 let Inst{27-25} = 0b100;
2010 let Inst{19-16} = 0b1101; // SP
2011 let Inst{15-5} = 0b00000101000;
2012 let Inst{4-0} = mode;
2015 def SRSDA : SRSI<0, "srsda\tsp, $mode"> {
2016 let Inst{24-23} = 0;
2018 def SRSDA_UPD : SRSI<1, "srsda\tsp!, $mode"> {
2019 let Inst{24-23} = 0;
2021 def SRSDB : SRSI<0, "srsdb\tsp, $mode"> {
2022 let Inst{24-23} = 0b10;
2024 def SRSDB_UPD : SRSI<1, "srsdb\tsp!, $mode"> {
2025 let Inst{24-23} = 0b10;
2027 def SRSIA : SRSI<0, "srsia\tsp, $mode"> {
2028 let Inst{24-23} = 0b01;
2030 def SRSIA_UPD : SRSI<1, "srsia\tsp!, $mode"> {
2031 let Inst{24-23} = 0b01;
2033 def SRSIB : SRSI<0, "srsib\tsp, $mode"> {
2034 let Inst{24-23} = 0b11;
2036 def SRSIB_UPD : SRSI<1, "srsib\tsp!, $mode"> {
2037 let Inst{24-23} = 0b11;
2040 // Return From Exception
2041 class RFEI<bit wb, string asm>
2042 : XI<(outs), (ins GPR:$Rn), AddrModeNone, 4, IndexModeNone, BrFrm,
2043 NoItinerary, asm, "", []> {
2045 let Inst{31-28} = 0b1111;
2046 let Inst{27-25} = 0b100;
2050 let Inst{19-16} = Rn;
2051 let Inst{15-0} = 0xa00;
2054 def RFEDA : RFEI<0, "rfeda\t$Rn"> {
2055 let Inst{24-23} = 0;
2057 def RFEDA_UPD : RFEI<1, "rfeda\t$Rn!"> {
2058 let Inst{24-23} = 0;
2060 def RFEDB : RFEI<0, "rfedb\t$Rn"> {
2061 let Inst{24-23} = 0b10;
2063 def RFEDB_UPD : RFEI<1, "rfedb\t$Rn!"> {
2064 let Inst{24-23} = 0b10;
2066 def RFEIA : RFEI<0, "rfeia\t$Rn"> {
2067 let Inst{24-23} = 0b01;
2069 def RFEIA_UPD : RFEI<1, "rfeia\t$Rn!"> {
2070 let Inst{24-23} = 0b01;
2072 def RFEIB : RFEI<0, "rfeib\t$Rn"> {
2073 let Inst{24-23} = 0b11;
2075 def RFEIB_UPD : RFEI<1, "rfeib\t$Rn!"> {
2076 let Inst{24-23} = 0b11;
2079 //===----------------------------------------------------------------------===//
2080 // Load / Store Instructions.
2086 defm LDR : AI_ldr1<0, "ldr", IIC_iLoad_r, IIC_iLoad_si,
2087 UnOpFrag<(load node:$Src)>>;
2088 defm LDRB : AI_ldr1nopc<1, "ldrb", IIC_iLoad_bh_r, IIC_iLoad_bh_si,
2089 UnOpFrag<(zextloadi8 node:$Src)>>;
2090 defm STR : AI_str1<0, "str", IIC_iStore_r, IIC_iStore_si,
2091 BinOpFrag<(store node:$LHS, node:$RHS)>>;
2092 defm STRB : AI_str1nopc<1, "strb", IIC_iStore_bh_r, IIC_iStore_bh_si,
2093 BinOpFrag<(truncstorei8 node:$LHS, node:$RHS)>>;
2095 // Special LDR for loads from non-pc-relative constpools.
2096 let canFoldAsLoad = 1, mayLoad = 1, neverHasSideEffects = 1,
2097 isReMaterializable = 1, isCodeGenOnly = 1 in
2098 def LDRcp : AI2ldst<0b010, 1, 0, (outs GPR:$Rt), (ins addrmode_imm12:$addr),
2099 AddrMode_i12, LdFrm, IIC_iLoad_r, "ldr", "\t$Rt, $addr",
2103 let Inst{23} = addr{12}; // U (add = ('U' == 1))
2104 let Inst{19-16} = 0b1111;
2105 let Inst{15-12} = Rt;
2106 let Inst{11-0} = addr{11-0}; // imm12
2109 // Loads with zero extension
2110 def LDRH : AI3ld<0b1011, 1, (outs GPR:$Rt), (ins addrmode3:$addr), LdMiscFrm,
2111 IIC_iLoad_bh_r, "ldrh", "\t$Rt, $addr",
2112 [(set GPR:$Rt, (zextloadi16 addrmode3:$addr))]>;
2114 // Loads with sign extension
2115 def LDRSH : AI3ld<0b1111, 1, (outs GPR:$Rt), (ins addrmode3:$addr), LdMiscFrm,
2116 IIC_iLoad_bh_r, "ldrsh", "\t$Rt, $addr",
2117 [(set GPR:$Rt, (sextloadi16 addrmode3:$addr))]>;
2119 def LDRSB : AI3ld<0b1101, 1, (outs GPR:$Rt), (ins addrmode3:$addr), LdMiscFrm,
2120 IIC_iLoad_bh_r, "ldrsb", "\t$Rt, $addr",
2121 [(set GPR:$Rt, (sextloadi8 addrmode3:$addr))]>;
2123 let mayLoad = 1, neverHasSideEffects = 1, hasExtraDefRegAllocReq = 1 in {
2125 def LDRD : AI3ld<0b1101, 0, (outs GPR:$Rd, GPR:$dst2),
2126 (ins addrmode3:$addr), LdMiscFrm,
2127 IIC_iLoad_d_r, "ldrd", "\t$Rd, $dst2, $addr",
2128 []>, Requires<[IsARM, HasV5TE]>;
2132 multiclass AI2_ldridx<bit isByte, string opc,
2133 InstrItinClass iii, InstrItinClass iir> {
2134 def _PRE_IMM : AI2ldstidx<1, isByte, 1, (outs GPR:$Rt, GPR:$Rn_wb),
2135 (ins addrmode_imm12:$addr), IndexModePre, LdFrm, iii,
2136 opc, "\t$Rt, $addr!", "$addr.base = $Rn_wb", []> {
2139 let Inst{23} = addr{12};
2140 let Inst{19-16} = addr{16-13};
2141 let Inst{11-0} = addr{11-0};
2142 let DecoderMethod = "DecodeLDRPreImm";
2143 let AsmMatchConverter = "cvtLdWriteBackRegAddrModeImm12";
2146 def _PRE_REG : AI2ldstidx<1, isByte, 1, (outs GPR:$Rt, GPR:$Rn_wb),
2147 (ins ldst_so_reg:$addr), IndexModePre, LdFrm, iir,
2148 opc, "\t$Rt, $addr!", "$addr.base = $Rn_wb", []> {
2151 let Inst{23} = addr{12};
2152 let Inst{19-16} = addr{16-13};
2153 let Inst{11-0} = addr{11-0};
2155 let DecoderMethod = "DecodeLDRPreReg";
2156 let AsmMatchConverter = "cvtLdWriteBackRegAddrMode2";
2159 def _POST_REG : AI2ldstidx<1, isByte, 0, (outs GPR:$Rt, GPR:$Rn_wb),
2160 (ins addr_offset_none:$addr, am2offset_reg:$offset),
2161 IndexModePost, LdFrm, iir,
2162 opc, "\t$Rt, $addr, $offset",
2163 "$addr.base = $Rn_wb", []> {
2169 let Inst{23} = offset{12};
2170 let Inst{19-16} = addr;
2171 let Inst{11-0} = offset{11-0};
2173 let DecoderMethod = "DecodeAddrMode2IdxInstruction";
2176 def _POST_IMM : AI2ldstidx<1, isByte, 0, (outs GPR:$Rt, GPR:$Rn_wb),
2177 (ins addr_offset_none:$addr, am2offset_imm:$offset),
2178 IndexModePost, LdFrm, iii,
2179 opc, "\t$Rt, $addr, $offset",
2180 "$addr.base = $Rn_wb", []> {
2186 let Inst{23} = offset{12};
2187 let Inst{19-16} = addr;
2188 let Inst{11-0} = offset{11-0};
2190 let DecoderMethod = "DecodeAddrMode2IdxInstruction";
2195 let mayLoad = 1, neverHasSideEffects = 1 in {
2196 // FIXME: for LDR_PRE_REG etc. the itineray should be either IIC_iLoad_ru or
2197 // IIC_iLoad_siu depending on whether it the offset register is shifted.
2198 defm LDR : AI2_ldridx<0, "ldr", IIC_iLoad_iu, IIC_iLoad_ru>;
2199 defm LDRB : AI2_ldridx<1, "ldrb", IIC_iLoad_bh_iu, IIC_iLoad_bh_ru>;
2202 multiclass AI3_ldridx<bits<4> op, string opc, InstrItinClass itin> {
2203 def _PRE : AI3ldstidx<op, 1, 1, (outs GPR:$Rt, GPR:$Rn_wb),
2204 (ins addrmode3:$addr), IndexModePre,
2206 opc, "\t$Rt, $addr!", "$addr.base = $Rn_wb", []> {
2208 let Inst{23} = addr{8}; // U bit
2209 let Inst{22} = addr{13}; // 1 == imm8, 0 == Rm
2210 let Inst{19-16} = addr{12-9}; // Rn
2211 let Inst{11-8} = addr{7-4}; // imm7_4/zero
2212 let Inst{3-0} = addr{3-0}; // imm3_0/Rm
2213 let AsmMatchConverter = "cvtLdWriteBackRegAddrMode3";
2214 let DecoderMethod = "DecodeAddrMode3Instruction";
2216 def _POST : AI3ldstidx<op, 1, 0, (outs GPR:$Rt, GPR:$Rn_wb),
2217 (ins addr_offset_none:$addr, am3offset:$offset),
2218 IndexModePost, LdMiscFrm, itin,
2219 opc, "\t$Rt, $addr, $offset", "$addr.base = $Rn_wb",
2223 let Inst{23} = offset{8}; // U bit
2224 let Inst{22} = offset{9}; // 1 == imm8, 0 == Rm
2225 let Inst{19-16} = addr;
2226 let Inst{11-8} = offset{7-4}; // imm7_4/zero
2227 let Inst{3-0} = offset{3-0}; // imm3_0/Rm
2228 let DecoderMethod = "DecodeAddrMode3Instruction";
2232 let mayLoad = 1, neverHasSideEffects = 1 in {
2233 defm LDRH : AI3_ldridx<0b1011, "ldrh", IIC_iLoad_bh_ru>;
2234 defm LDRSH : AI3_ldridx<0b1111, "ldrsh", IIC_iLoad_bh_ru>;
2235 defm LDRSB : AI3_ldridx<0b1101, "ldrsb", IIC_iLoad_bh_ru>;
2236 let hasExtraDefRegAllocReq = 1 in {
2237 def LDRD_PRE : AI3ldstidx<0b1101, 0, 1, (outs GPR:$Rt, GPR:$Rt2, GPR:$Rn_wb),
2238 (ins addrmode3:$addr), IndexModePre,
2239 LdMiscFrm, IIC_iLoad_d_ru,
2240 "ldrd", "\t$Rt, $Rt2, $addr!",
2241 "$addr.base = $Rn_wb", []> {
2243 let Inst{23} = addr{8}; // U bit
2244 let Inst{22} = addr{13}; // 1 == imm8, 0 == Rm
2245 let Inst{19-16} = addr{12-9}; // Rn
2246 let Inst{11-8} = addr{7-4}; // imm7_4/zero
2247 let Inst{3-0} = addr{3-0}; // imm3_0/Rm
2248 let DecoderMethod = "DecodeAddrMode3Instruction";
2249 let AsmMatchConverter = "cvtLdrdPre";
2251 def LDRD_POST: AI3ldstidx<0b1101, 0, 0, (outs GPR:$Rt, GPR:$Rt2, GPR:$Rn_wb),
2252 (ins addr_offset_none:$addr, am3offset:$offset),
2253 IndexModePost, LdMiscFrm, IIC_iLoad_d_ru,
2254 "ldrd", "\t$Rt, $Rt2, $addr, $offset",
2255 "$addr.base = $Rn_wb", []> {
2258 let Inst{23} = offset{8}; // U bit
2259 let Inst{22} = offset{9}; // 1 == imm8, 0 == Rm
2260 let Inst{19-16} = addr;
2261 let Inst{11-8} = offset{7-4}; // imm7_4/zero
2262 let Inst{3-0} = offset{3-0}; // imm3_0/Rm
2263 let DecoderMethod = "DecodeAddrMode3Instruction";
2265 } // hasExtraDefRegAllocReq = 1
2266 } // mayLoad = 1, neverHasSideEffects = 1
2268 // LDRT, LDRBT, LDRSBT, LDRHT, LDRSHT.
2269 let mayLoad = 1, neverHasSideEffects = 1 in {
2270 def LDRT_POST_REG : AI2ldstidx<1, 0, 0, (outs GPR:$Rt, GPR:$Rn_wb),
2271 (ins addr_offset_none:$addr, am2offset_reg:$offset),
2272 IndexModePost, LdFrm, IIC_iLoad_ru,
2273 "ldrt", "\t$Rt, $addr, $offset",
2274 "$addr.base = $Rn_wb", []> {
2280 let Inst{23} = offset{12};
2281 let Inst{21} = 1; // overwrite
2282 let Inst{19-16} = addr;
2283 let Inst{11-5} = offset{11-5};
2285 let Inst{3-0} = offset{3-0};
2286 let DecoderMethod = "DecodeAddrMode2IdxInstruction";
2289 def LDRT_POST_IMM : AI2ldstidx<1, 0, 0, (outs GPR:$Rt, GPR:$Rn_wb),
2290 (ins addr_offset_none:$addr, am2offset_imm:$offset),
2291 IndexModePost, LdFrm, IIC_iLoad_ru,
2292 "ldrt", "\t$Rt, $addr, $offset",
2293 "$addr.base = $Rn_wb", []> {
2299 let Inst{23} = offset{12};
2300 let Inst{21} = 1; // overwrite
2301 let Inst{19-16} = addr;
2302 let Inst{11-0} = offset{11-0};
2303 let DecoderMethod = "DecodeAddrMode2IdxInstruction";
2306 def LDRBT_POST_REG : AI2ldstidx<1, 1, 0, (outs GPR:$Rt, GPR:$Rn_wb),
2307 (ins addr_offset_none:$addr, am2offset_reg:$offset),
2308 IndexModePost, LdFrm, IIC_iLoad_bh_ru,
2309 "ldrbt", "\t$Rt, $addr, $offset",
2310 "$addr.base = $Rn_wb", []> {
2316 let Inst{23} = offset{12};
2317 let Inst{21} = 1; // overwrite
2318 let Inst{19-16} = addr;
2319 let Inst{11-5} = offset{11-5};
2321 let Inst{3-0} = offset{3-0};
2322 let DecoderMethod = "DecodeAddrMode2IdxInstruction";
2325 def LDRBT_POST_IMM : AI2ldstidx<1, 1, 0, (outs GPR:$Rt, GPR:$Rn_wb),
2326 (ins addr_offset_none:$addr, am2offset_imm:$offset),
2327 IndexModePost, LdFrm, IIC_iLoad_bh_ru,
2328 "ldrbt", "\t$Rt, $addr, $offset",
2329 "$addr.base = $Rn_wb", []> {
2335 let Inst{23} = offset{12};
2336 let Inst{21} = 1; // overwrite
2337 let Inst{19-16} = addr;
2338 let Inst{11-0} = offset{11-0};
2339 let DecoderMethod = "DecodeAddrMode2IdxInstruction";
2342 multiclass AI3ldrT<bits<4> op, string opc> {
2343 def i : AI3ldstidxT<op, 1, (outs GPR:$Rt, GPR:$base_wb),
2344 (ins addr_offset_none:$addr, postidx_imm8:$offset),
2345 IndexModePost, LdMiscFrm, IIC_iLoad_bh_ru, opc,
2346 "\t$Rt, $addr, $offset", "$addr.base = $base_wb", []> {
2348 let Inst{23} = offset{8};
2350 let Inst{11-8} = offset{7-4};
2351 let Inst{3-0} = offset{3-0};
2352 let AsmMatchConverter = "cvtLdExtTWriteBackImm";
2354 def r : AI3ldstidxT<op, 1, (outs GPRnopc:$Rt, GPRnopc:$base_wb),
2355 (ins addr_offset_none:$addr, postidx_reg:$Rm),
2356 IndexModePost, LdMiscFrm, IIC_iLoad_bh_ru, opc,
2357 "\t$Rt, $addr, $Rm", "$addr.base = $base_wb", []> {
2359 let Inst{23} = Rm{4};
2362 let Unpredictable{11-8} = 0b1111;
2363 let Inst{3-0} = Rm{3-0};
2364 let AsmMatchConverter = "cvtLdExtTWriteBackReg";
2365 let DecoderMethod = "DecodeLDR";
2369 defm LDRSBT : AI3ldrT<0b1101, "ldrsbt">;
2370 defm LDRHT : AI3ldrT<0b1011, "ldrht">;
2371 defm LDRSHT : AI3ldrT<0b1111, "ldrsht">;
2376 // Stores with truncate
2377 def STRH : AI3str<0b1011, (outs), (ins GPR:$Rt, addrmode3:$addr), StMiscFrm,
2378 IIC_iStore_bh_r, "strh", "\t$Rt, $addr",
2379 [(truncstorei16 GPR:$Rt, addrmode3:$addr)]>;
2382 let mayStore = 1, neverHasSideEffects = 1, hasExtraSrcRegAllocReq = 1 in
2383 def STRD : AI3str<0b1111, (outs), (ins GPR:$Rt, GPR:$src2, addrmode3:$addr),
2384 StMiscFrm, IIC_iStore_d_r,
2385 "strd", "\t$Rt, $src2, $addr", []>,
2386 Requires<[IsARM, HasV5TE]> {
2391 multiclass AI2_stridx<bit isByte, string opc,
2392 InstrItinClass iii, InstrItinClass iir> {
2393 def _PRE_IMM : AI2ldstidx<0, isByte, 1, (outs GPR:$Rn_wb),
2394 (ins GPR:$Rt, addrmode_imm12:$addr), IndexModePre,
2396 opc, "\t$Rt, $addr!", "$addr.base = $Rn_wb", []> {
2399 let Inst{23} = addr{12}; // U (add = ('U' == 1))
2400 let Inst{19-16} = addr{16-13}; // Rn
2401 let Inst{11-0} = addr{11-0}; // imm12
2402 let AsmMatchConverter = "cvtStWriteBackRegAddrModeImm12";
2403 let DecoderMethod = "DecodeSTRPreImm";
2406 def _PRE_REG : AI2ldstidx<0, isByte, 1, (outs GPR:$Rn_wb),
2407 (ins GPR:$Rt, ldst_so_reg:$addr),
2408 IndexModePre, StFrm, iir,
2409 opc, "\t$Rt, $addr!", "$addr.base = $Rn_wb", []> {
2412 let Inst{23} = addr{12}; // U (add = ('U' == 1))
2413 let Inst{19-16} = addr{16-13}; // Rn
2414 let Inst{11-0} = addr{11-0};
2415 let Inst{4} = 0; // Inst{4} = 0
2416 let AsmMatchConverter = "cvtStWriteBackRegAddrMode2";
2417 let DecoderMethod = "DecodeSTRPreReg";
2419 def _POST_REG : AI2ldstidx<0, isByte, 0, (outs GPR:$Rn_wb),
2420 (ins GPR:$Rt, addr_offset_none:$addr, am2offset_reg:$offset),
2421 IndexModePost, StFrm, iir,
2422 opc, "\t$Rt, $addr, $offset",
2423 "$addr.base = $Rn_wb", []> {
2429 let Inst{23} = offset{12};
2430 let Inst{19-16} = addr;
2431 let Inst{11-0} = offset{11-0};
2433 let DecoderMethod = "DecodeAddrMode2IdxInstruction";
2436 def _POST_IMM : AI2ldstidx<0, isByte, 0, (outs GPR:$Rn_wb),
2437 (ins GPR:$Rt, addr_offset_none:$addr, am2offset_imm:$offset),
2438 IndexModePost, StFrm, iii,
2439 opc, "\t$Rt, $addr, $offset",
2440 "$addr.base = $Rn_wb", []> {
2446 let Inst{23} = offset{12};
2447 let Inst{19-16} = addr;
2448 let Inst{11-0} = offset{11-0};
2450 let DecoderMethod = "DecodeAddrMode2IdxInstruction";
2454 let mayStore = 1, neverHasSideEffects = 1 in {
2455 // FIXME: for STR_PRE_REG etc. the itineray should be either IIC_iStore_ru or
2456 // IIC_iStore_siu depending on whether it the offset register is shifted.
2457 defm STR : AI2_stridx<0, "str", IIC_iStore_iu, IIC_iStore_ru>;
2458 defm STRB : AI2_stridx<1, "strb", IIC_iStore_bh_iu, IIC_iStore_bh_ru>;
2461 def : ARMPat<(post_store GPR:$Rt, addr_offset_none:$addr,
2462 am2offset_reg:$offset),
2463 (STR_POST_REG GPR:$Rt, addr_offset_none:$addr,
2464 am2offset_reg:$offset)>;
2465 def : ARMPat<(post_store GPR:$Rt, addr_offset_none:$addr,
2466 am2offset_imm:$offset),
2467 (STR_POST_IMM GPR:$Rt, addr_offset_none:$addr,
2468 am2offset_imm:$offset)>;
2469 def : ARMPat<(post_truncsti8 GPR:$Rt, addr_offset_none:$addr,
2470 am2offset_reg:$offset),
2471 (STRB_POST_REG GPR:$Rt, addr_offset_none:$addr,
2472 am2offset_reg:$offset)>;
2473 def : ARMPat<(post_truncsti8 GPR:$Rt, addr_offset_none:$addr,
2474 am2offset_imm:$offset),
2475 (STRB_POST_IMM GPR:$Rt, addr_offset_none:$addr,
2476 am2offset_imm:$offset)>;
2478 // Pseudo-instructions for pattern matching the pre-indexed stores. We can't
2479 // put the patterns on the instruction definitions directly as ISel wants
2480 // the address base and offset to be separate operands, not a single
2481 // complex operand like we represent the instructions themselves. The
2482 // pseudos map between the two.
2483 let usesCustomInserter = 1,
2484 Constraints = "$Rn = $Rn_wb,@earlyclobber $Rn_wb" in {
2485 def STRi_preidx: ARMPseudoInst<(outs GPR:$Rn_wb),
2486 (ins GPR:$Rt, GPR:$Rn, am2offset_imm:$offset, pred:$p),
2489 (pre_store GPR:$Rt, GPR:$Rn, am2offset_imm:$offset))]>;
2490 def STRr_preidx: ARMPseudoInst<(outs GPR:$Rn_wb),
2491 (ins GPR:$Rt, GPR:$Rn, am2offset_reg:$offset, pred:$p),
2494 (pre_store GPR:$Rt, GPR:$Rn, am2offset_reg:$offset))]>;
2495 def STRBi_preidx: ARMPseudoInst<(outs GPR:$Rn_wb),
2496 (ins GPR:$Rt, GPR:$Rn, am2offset_imm:$offset, pred:$p),
2499 (pre_truncsti8 GPR:$Rt, GPR:$Rn, am2offset_imm:$offset))]>;
2500 def STRBr_preidx: ARMPseudoInst<(outs GPR:$Rn_wb),
2501 (ins GPR:$Rt, GPR:$Rn, am2offset_reg:$offset, pred:$p),
2504 (pre_truncsti8 GPR:$Rt, GPR:$Rn, am2offset_reg:$offset))]>;
2505 def STRH_preidx: ARMPseudoInst<(outs GPR:$Rn_wb),
2506 (ins GPR:$Rt, GPR:$Rn, am3offset:$offset, pred:$p),
2509 (pre_truncsti16 GPR:$Rt, GPR:$Rn, am3offset:$offset))]>;
2514 def STRH_PRE : AI3ldstidx<0b1011, 0, 1, (outs GPR:$Rn_wb),
2515 (ins GPR:$Rt, addrmode3:$addr), IndexModePre,
2516 StMiscFrm, IIC_iStore_bh_ru,
2517 "strh", "\t$Rt, $addr!", "$addr.base = $Rn_wb", []> {
2519 let Inst{23} = addr{8}; // U bit
2520 let Inst{22} = addr{13}; // 1 == imm8, 0 == Rm
2521 let Inst{19-16} = addr{12-9}; // Rn
2522 let Inst{11-8} = addr{7-4}; // imm7_4/zero
2523 let Inst{3-0} = addr{3-0}; // imm3_0/Rm
2524 let AsmMatchConverter = "cvtStWriteBackRegAddrMode3";
2525 let DecoderMethod = "DecodeAddrMode3Instruction";
2528 def STRH_POST : AI3ldstidx<0b1011, 0, 0, (outs GPR:$Rn_wb),
2529 (ins GPR:$Rt, addr_offset_none:$addr, am3offset:$offset),
2530 IndexModePost, StMiscFrm, IIC_iStore_bh_ru,
2531 "strh", "\t$Rt, $addr, $offset", "$addr.base = $Rn_wb",
2532 [(set GPR:$Rn_wb, (post_truncsti16 GPR:$Rt,
2533 addr_offset_none:$addr,
2534 am3offset:$offset))]> {
2537 let Inst{23} = offset{8}; // U bit
2538 let Inst{22} = offset{9}; // 1 == imm8, 0 == Rm
2539 let Inst{19-16} = addr;
2540 let Inst{11-8} = offset{7-4}; // imm7_4/zero
2541 let Inst{3-0} = offset{3-0}; // imm3_0/Rm
2542 let DecoderMethod = "DecodeAddrMode3Instruction";
2545 let mayStore = 1, neverHasSideEffects = 1, hasExtraSrcRegAllocReq = 1 in {
2546 def STRD_PRE : AI3ldstidx<0b1111, 0, 1, (outs GPR:$Rn_wb),
2547 (ins GPR:$Rt, GPR:$Rt2, addrmode3:$addr),
2548 IndexModePre, StMiscFrm, IIC_iStore_d_ru,
2549 "strd", "\t$Rt, $Rt2, $addr!",
2550 "$addr.base = $Rn_wb", []> {
2552 let Inst{23} = addr{8}; // U bit
2553 let Inst{22} = addr{13}; // 1 == imm8, 0 == Rm
2554 let Inst{19-16} = addr{12-9}; // Rn
2555 let Inst{11-8} = addr{7-4}; // imm7_4/zero
2556 let Inst{3-0} = addr{3-0}; // imm3_0/Rm
2557 let DecoderMethod = "DecodeAddrMode3Instruction";
2558 let AsmMatchConverter = "cvtStrdPre";
2561 def STRD_POST: AI3ldstidx<0b1111, 0, 0, (outs GPR:$Rn_wb),
2562 (ins GPR:$Rt, GPR:$Rt2, addr_offset_none:$addr,
2564 IndexModePost, StMiscFrm, IIC_iStore_d_ru,
2565 "strd", "\t$Rt, $Rt2, $addr, $offset",
2566 "$addr.base = $Rn_wb", []> {
2569 let Inst{23} = offset{8}; // U bit
2570 let Inst{22} = offset{9}; // 1 == imm8, 0 == Rm
2571 let Inst{19-16} = addr;
2572 let Inst{11-8} = offset{7-4}; // imm7_4/zero
2573 let Inst{3-0} = offset{3-0}; // imm3_0/Rm
2574 let DecoderMethod = "DecodeAddrMode3Instruction";
2576 } // mayStore = 1, neverHasSideEffects = 1, hasExtraSrcRegAllocReq = 1
2578 // STRT, STRBT, and STRHT
2580 def STRBT_POST_REG : AI2ldstidx<0, 1, 0, (outs GPR:$Rn_wb),
2581 (ins GPR:$Rt, addr_offset_none:$addr, am2offset_reg:$offset),
2582 IndexModePost, StFrm, IIC_iStore_bh_ru,
2583 "strbt", "\t$Rt, $addr, $offset",
2584 "$addr.base = $Rn_wb", []> {
2590 let Inst{23} = offset{12};
2591 let Inst{21} = 1; // overwrite
2592 let Inst{19-16} = addr;
2593 let Inst{11-5} = offset{11-5};
2595 let Inst{3-0} = offset{3-0};
2596 let DecoderMethod = "DecodeAddrMode2IdxInstruction";
2599 def STRBT_POST_IMM : AI2ldstidx<0, 1, 0, (outs GPR:$Rn_wb),
2600 (ins GPR:$Rt, addr_offset_none:$addr, am2offset_imm:$offset),
2601 IndexModePost, StFrm, IIC_iStore_bh_ru,
2602 "strbt", "\t$Rt, $addr, $offset",
2603 "$addr.base = $Rn_wb", []> {
2609 let Inst{23} = offset{12};
2610 let Inst{21} = 1; // overwrite
2611 let Inst{19-16} = addr;
2612 let Inst{11-0} = offset{11-0};
2613 let DecoderMethod = "DecodeAddrMode2IdxInstruction";
2616 let mayStore = 1, neverHasSideEffects = 1 in {
2617 def STRT_POST_REG : AI2ldstidx<0, 0, 0, (outs GPR:$Rn_wb),
2618 (ins GPR:$Rt, addr_offset_none:$addr, am2offset_reg:$offset),
2619 IndexModePost, StFrm, IIC_iStore_ru,
2620 "strt", "\t$Rt, $addr, $offset",
2621 "$addr.base = $Rn_wb", []> {
2627 let Inst{23} = offset{12};
2628 let Inst{21} = 1; // overwrite
2629 let Inst{19-16} = addr;
2630 let Inst{11-5} = offset{11-5};
2632 let Inst{3-0} = offset{3-0};
2633 let DecoderMethod = "DecodeAddrMode2IdxInstruction";
2636 def STRT_POST_IMM : AI2ldstidx<0, 0, 0, (outs GPR:$Rn_wb),
2637 (ins GPR:$Rt, addr_offset_none:$addr, am2offset_imm:$offset),
2638 IndexModePost, StFrm, IIC_iStore_ru,
2639 "strt", "\t$Rt, $addr, $offset",
2640 "$addr.base = $Rn_wb", []> {
2646 let Inst{23} = offset{12};
2647 let Inst{21} = 1; // overwrite
2648 let Inst{19-16} = addr;
2649 let Inst{11-0} = offset{11-0};
2650 let DecoderMethod = "DecodeAddrMode2IdxInstruction";
2655 multiclass AI3strT<bits<4> op, string opc> {
2656 def i : AI3ldstidxT<op, 0, (outs GPR:$base_wb),
2657 (ins GPR:$Rt, addr_offset_none:$addr, postidx_imm8:$offset),
2658 IndexModePost, StMiscFrm, IIC_iStore_bh_ru, opc,
2659 "\t$Rt, $addr, $offset", "$addr.base = $base_wb", []> {
2661 let Inst{23} = offset{8};
2663 let Inst{11-8} = offset{7-4};
2664 let Inst{3-0} = offset{3-0};
2665 let AsmMatchConverter = "cvtStExtTWriteBackImm";
2667 def r : AI3ldstidxT<op, 0, (outs GPR:$base_wb),
2668 (ins GPR:$Rt, addr_offset_none:$addr, postidx_reg:$Rm),
2669 IndexModePost, StMiscFrm, IIC_iStore_bh_ru, opc,
2670 "\t$Rt, $addr, $Rm", "$addr.base = $base_wb", []> {
2672 let Inst{23} = Rm{4};
2675 let Inst{3-0} = Rm{3-0};
2676 let AsmMatchConverter = "cvtStExtTWriteBackReg";
2681 defm STRHT : AI3strT<0b1011, "strht">;
2684 //===----------------------------------------------------------------------===//
2685 // Load / store multiple Instructions.
2688 multiclass arm_ldst_mult<string asm, string sfx, bit L_bit, bit P_bit, Format f,
2689 InstrItinClass itin, InstrItinClass itin_upd> {
2690 // IA is the default, so no need for an explicit suffix on the
2691 // mnemonic here. Without it is the cannonical spelling.
2693 AXI4<(outs), (ins GPR:$Rn, pred:$p, reglist:$regs, variable_ops),
2694 IndexModeNone, f, itin,
2695 !strconcat(asm, "${p}\t$Rn, $regs", sfx), "", []> {
2696 let Inst{24-23} = 0b01; // Increment After
2697 let Inst{22} = P_bit;
2698 let Inst{21} = 0; // No writeback
2699 let Inst{20} = L_bit;
2702 AXI4<(outs GPR:$wb), (ins GPR:$Rn, pred:$p, reglist:$regs, variable_ops),
2703 IndexModeUpd, f, itin_upd,
2704 !strconcat(asm, "${p}\t$Rn!, $regs", sfx), "$Rn = $wb", []> {
2705 let Inst{24-23} = 0b01; // Increment After
2706 let Inst{22} = P_bit;
2707 let Inst{21} = 1; // Writeback
2708 let Inst{20} = L_bit;
2710 let DecoderMethod = "DecodeMemMultipleWritebackInstruction";
2713 AXI4<(outs), (ins GPR:$Rn, pred:$p, reglist:$regs, variable_ops),
2714 IndexModeNone, f, itin,
2715 !strconcat(asm, "da${p}\t$Rn, $regs", sfx), "", []> {
2716 let Inst{24-23} = 0b00; // Decrement After
2717 let Inst{22} = P_bit;
2718 let Inst{21} = 0; // No writeback
2719 let Inst{20} = L_bit;
2722 AXI4<(outs GPR:$wb), (ins GPR:$Rn, pred:$p, reglist:$regs, variable_ops),
2723 IndexModeUpd, f, itin_upd,
2724 !strconcat(asm, "da${p}\t$Rn!, $regs", sfx), "$Rn = $wb", []> {
2725 let Inst{24-23} = 0b00; // Decrement After
2726 let Inst{22} = P_bit;
2727 let Inst{21} = 1; // Writeback
2728 let Inst{20} = L_bit;
2730 let DecoderMethod = "DecodeMemMultipleWritebackInstruction";
2733 AXI4<(outs), (ins GPR:$Rn, pred:$p, reglist:$regs, variable_ops),
2734 IndexModeNone, f, itin,
2735 !strconcat(asm, "db${p}\t$Rn, $regs", sfx), "", []> {
2736 let Inst{24-23} = 0b10; // Decrement Before
2737 let Inst{22} = P_bit;
2738 let Inst{21} = 0; // No writeback
2739 let Inst{20} = L_bit;
2742 AXI4<(outs GPR:$wb), (ins GPR:$Rn, pred:$p, reglist:$regs, variable_ops),
2743 IndexModeUpd, f, itin_upd,
2744 !strconcat(asm, "db${p}\t$Rn!, $regs", sfx), "$Rn = $wb", []> {
2745 let Inst{24-23} = 0b10; // Decrement Before
2746 let Inst{22} = P_bit;
2747 let Inst{21} = 1; // Writeback
2748 let Inst{20} = L_bit;
2750 let DecoderMethod = "DecodeMemMultipleWritebackInstruction";
2753 AXI4<(outs), (ins GPR:$Rn, pred:$p, reglist:$regs, variable_ops),
2754 IndexModeNone, f, itin,
2755 !strconcat(asm, "ib${p}\t$Rn, $regs", sfx), "", []> {
2756 let Inst{24-23} = 0b11; // Increment Before
2757 let Inst{22} = P_bit;
2758 let Inst{21} = 0; // No writeback
2759 let Inst{20} = L_bit;
2762 AXI4<(outs GPR:$wb), (ins GPR:$Rn, pred:$p, reglist:$regs, variable_ops),
2763 IndexModeUpd, f, itin_upd,
2764 !strconcat(asm, "ib${p}\t$Rn!, $regs", sfx), "$Rn = $wb", []> {
2765 let Inst{24-23} = 0b11; // Increment Before
2766 let Inst{22} = P_bit;
2767 let Inst{21} = 1; // Writeback
2768 let Inst{20} = L_bit;
2770 let DecoderMethod = "DecodeMemMultipleWritebackInstruction";
2774 let neverHasSideEffects = 1 in {
2776 let mayLoad = 1, hasExtraDefRegAllocReq = 1 in
2777 defm LDM : arm_ldst_mult<"ldm", "", 1, 0, LdStMulFrm, IIC_iLoad_m,
2780 let mayStore = 1, hasExtraSrcRegAllocReq = 1 in
2781 defm STM : arm_ldst_mult<"stm", "", 0, 0, LdStMulFrm, IIC_iStore_m,
2784 } // neverHasSideEffects
2786 // FIXME: remove when we have a way to marking a MI with these properties.
2787 // FIXME: Should pc be an implicit operand like PICADD, etc?
2788 let isReturn = 1, isTerminator = 1, isBarrier = 1, mayLoad = 1,
2789 hasExtraDefRegAllocReq = 1, isCodeGenOnly = 1 in
2790 def LDMIA_RET : ARMPseudoExpand<(outs GPR:$wb), (ins GPR:$Rn, pred:$p,
2791 reglist:$regs, variable_ops),
2792 4, IIC_iLoad_mBr, [],
2793 (LDMIA_UPD GPR:$wb, GPR:$Rn, pred:$p, reglist:$regs)>,
2794 RegConstraint<"$Rn = $wb">;
2796 let mayLoad = 1, hasExtraDefRegAllocReq = 1 in
2797 defm sysLDM : arm_ldst_mult<"ldm", " ^", 1, 1, LdStMulFrm, IIC_iLoad_m,
2800 let mayStore = 1, hasExtraSrcRegAllocReq = 1 in
2801 defm sysSTM : arm_ldst_mult<"stm", " ^", 0, 1, LdStMulFrm, IIC_iStore_m,
2806 //===----------------------------------------------------------------------===//
2807 // Move Instructions.
2810 let neverHasSideEffects = 1 in
2811 def MOVr : AsI1<0b1101, (outs GPR:$Rd), (ins GPR:$Rm), DPFrm, IIC_iMOVr,
2812 "mov", "\t$Rd, $Rm", []>, UnaryDP {
2816 let Inst{19-16} = 0b0000;
2817 let Inst{11-4} = 0b00000000;
2820 let Inst{15-12} = Rd;
2823 def : ARMInstAlias<"movs${p} $Rd, $Rm",
2824 (MOVr GPR:$Rd, GPR:$Rm, pred:$p, CPSR)>;
2826 // A version for the smaller set of tail call registers.
2827 let neverHasSideEffects = 1 in
2828 def MOVr_TC : AsI1<0b1101, (outs tcGPR:$Rd), (ins tcGPR:$Rm), DPFrm,
2829 IIC_iMOVr, "mov", "\t$Rd, $Rm", []>, UnaryDP {
2833 let Inst{11-4} = 0b00000000;
2836 let Inst{15-12} = Rd;
2839 def MOVsr : AsI1<0b1101, (outs GPRnopc:$Rd), (ins shift_so_reg_reg:$src),
2840 DPSoRegRegFrm, IIC_iMOVsr,
2841 "mov", "\t$Rd, $src",
2842 [(set GPRnopc:$Rd, shift_so_reg_reg:$src)]>, UnaryDP {
2845 let Inst{15-12} = Rd;
2846 let Inst{19-16} = 0b0000;
2847 let Inst{11-8} = src{11-8};
2849 let Inst{6-5} = src{6-5};
2851 let Inst{3-0} = src{3-0};
2855 def MOVsi : AsI1<0b1101, (outs GPR:$Rd), (ins shift_so_reg_imm:$src),
2856 DPSoRegImmFrm, IIC_iMOVsr,
2857 "mov", "\t$Rd, $src", [(set GPR:$Rd, shift_so_reg_imm:$src)]>,
2861 let Inst{15-12} = Rd;
2862 let Inst{19-16} = 0b0000;
2863 let Inst{11-5} = src{11-5};
2865 let Inst{3-0} = src{3-0};
2869 let isReMaterializable = 1, isAsCheapAsAMove = 1, isMoveImm = 1 in
2870 def MOVi : AsI1<0b1101, (outs GPR:$Rd), (ins so_imm:$imm), DPFrm, IIC_iMOVi,
2871 "mov", "\t$Rd, $imm", [(set GPR:$Rd, so_imm:$imm)]>, UnaryDP {
2875 let Inst{15-12} = Rd;
2876 let Inst{19-16} = 0b0000;
2877 let Inst{11-0} = imm;
2880 let isReMaterializable = 1, isAsCheapAsAMove = 1, isMoveImm = 1 in
2881 def MOVi16 : AI1<0b1000, (outs GPR:$Rd), (ins imm0_65535_expr:$imm),
2883 "movw", "\t$Rd, $imm",
2884 [(set GPR:$Rd, imm0_65535:$imm)]>,
2885 Requires<[IsARM, HasV6T2]>, UnaryDP {
2888 let Inst{15-12} = Rd;
2889 let Inst{11-0} = imm{11-0};
2890 let Inst{19-16} = imm{15-12};
2893 let DecoderMethod = "DecodeArmMOVTWInstruction";
2896 def : InstAlias<"mov${p} $Rd, $imm",
2897 (MOVi16 GPR:$Rd, imm0_65535_expr:$imm, pred:$p)>,
2900 def MOVi16_ga_pcrel : PseudoInst<(outs GPR:$Rd),
2901 (ins i32imm:$addr, pclabel:$id), IIC_iMOVi, []>;
2903 let Constraints = "$src = $Rd" in {
2904 def MOVTi16 : AI1<0b1010, (outs GPRnopc:$Rd),
2905 (ins GPR:$src, imm0_65535_expr:$imm),
2907 "movt", "\t$Rd, $imm",
2909 (or (and GPR:$src, 0xffff),
2910 lo16AllZero:$imm))]>, UnaryDP,
2911 Requires<[IsARM, HasV6T2]> {
2914 let Inst{15-12} = Rd;
2915 let Inst{11-0} = imm{11-0};
2916 let Inst{19-16} = imm{15-12};
2919 let DecoderMethod = "DecodeArmMOVTWInstruction";
2922 def MOVTi16_ga_pcrel : PseudoInst<(outs GPR:$Rd),
2923 (ins GPR:$src, i32imm:$addr, pclabel:$id), IIC_iMOVi, []>;
2927 def : ARMPat<(or GPR:$src, 0xffff0000), (MOVTi16 GPR:$src, 0xffff)>,
2928 Requires<[IsARM, HasV6T2]>;
2930 let Uses = [CPSR] in
2931 def RRX: PseudoInst<(outs GPR:$Rd), (ins GPR:$Rm), IIC_iMOVsi,
2932 [(set GPR:$Rd, (ARMrrx GPR:$Rm))]>, UnaryDP,
2935 // These aren't really mov instructions, but we have to define them this way
2936 // due to flag operands.
2938 let Defs = [CPSR] in {
2939 def MOVsrl_flag : PseudoInst<(outs GPR:$dst), (ins GPR:$src), IIC_iMOVsi,
2940 [(set GPR:$dst, (ARMsrl_flag GPR:$src))]>, UnaryDP,
2942 def MOVsra_flag : PseudoInst<(outs GPR:$dst), (ins GPR:$src), IIC_iMOVsi,
2943 [(set GPR:$dst, (ARMsra_flag GPR:$src))]>, UnaryDP,
2947 //===----------------------------------------------------------------------===//
2948 // Extend Instructions.
2953 def SXTB : AI_ext_rrot<0b01101010,
2954 "sxtb", UnOpFrag<(sext_inreg node:$Src, i8)>>;
2955 def SXTH : AI_ext_rrot<0b01101011,
2956 "sxth", UnOpFrag<(sext_inreg node:$Src, i16)>>;
2958 def SXTAB : AI_exta_rrot<0b01101010,
2959 "sxtab", BinOpFrag<(add node:$LHS, (sext_inreg node:$RHS, i8))>>;
2960 def SXTAH : AI_exta_rrot<0b01101011,
2961 "sxtah", BinOpFrag<(add node:$LHS, (sext_inreg node:$RHS,i16))>>;
2963 def SXTB16 : AI_ext_rrot_np<0b01101000, "sxtb16">;
2965 def SXTAB16 : AI_exta_rrot_np<0b01101000, "sxtab16">;
2969 let AddedComplexity = 16 in {
2970 def UXTB : AI_ext_rrot<0b01101110,
2971 "uxtb" , UnOpFrag<(and node:$Src, 0x000000FF)>>;
2972 def UXTH : AI_ext_rrot<0b01101111,
2973 "uxth" , UnOpFrag<(and node:$Src, 0x0000FFFF)>>;
2974 def UXTB16 : AI_ext_rrot<0b01101100,
2975 "uxtb16", UnOpFrag<(and node:$Src, 0x00FF00FF)>>;
2977 // FIXME: This pattern incorrectly assumes the shl operator is a rotate.
2978 // The transformation should probably be done as a combiner action
2979 // instead so we can include a check for masking back in the upper
2980 // eight bits of the source into the lower eight bits of the result.
2981 //def : ARMV6Pat<(and (shl GPR:$Src, (i32 8)), 0xFF00FF),
2982 // (UXTB16r_rot GPR:$Src, 3)>;
2983 def : ARMV6Pat<(and (srl GPR:$Src, (i32 8)), 0xFF00FF),
2984 (UXTB16 GPR:$Src, 1)>;
2986 def UXTAB : AI_exta_rrot<0b01101110, "uxtab",
2987 BinOpFrag<(add node:$LHS, (and node:$RHS, 0x00FF))>>;
2988 def UXTAH : AI_exta_rrot<0b01101111, "uxtah",
2989 BinOpFrag<(add node:$LHS, (and node:$RHS, 0xFFFF))>>;
2992 // This isn't safe in general, the add is two 16-bit units, not a 32-bit add.
2993 def UXTAB16 : AI_exta_rrot_np<0b01101100, "uxtab16">;
2996 def SBFX : I<(outs GPRnopc:$Rd),
2997 (ins GPRnopc:$Rn, imm0_31:$lsb, imm1_32:$width),
2998 AddrMode1, 4, IndexModeNone, DPFrm, IIC_iUNAsi,
2999 "sbfx", "\t$Rd, $Rn, $lsb, $width", "", []>,
3000 Requires<[IsARM, HasV6T2]> {
3005 let Inst{27-21} = 0b0111101;
3006 let Inst{6-4} = 0b101;
3007 let Inst{20-16} = width;
3008 let Inst{15-12} = Rd;
3009 let Inst{11-7} = lsb;
3013 def UBFX : I<(outs GPR:$Rd),
3014 (ins GPR:$Rn, imm0_31:$lsb, imm1_32:$width),
3015 AddrMode1, 4, IndexModeNone, DPFrm, IIC_iUNAsi,
3016 "ubfx", "\t$Rd, $Rn, $lsb, $width", "", []>,
3017 Requires<[IsARM, HasV6T2]> {
3022 let Inst{27-21} = 0b0111111;
3023 let Inst{6-4} = 0b101;
3024 let Inst{20-16} = width;
3025 let Inst{15-12} = Rd;
3026 let Inst{11-7} = lsb;
3030 //===----------------------------------------------------------------------===//
3031 // Arithmetic Instructions.
3034 defm ADD : AsI1_bin_irs<0b0100, "add",
3035 IIC_iALUi, IIC_iALUr, IIC_iALUsr,
3036 BinOpFrag<(add node:$LHS, node:$RHS)>, "ADD", 1>;
3037 defm SUB : AsI1_bin_irs<0b0010, "sub",
3038 IIC_iALUi, IIC_iALUr, IIC_iALUsr,
3039 BinOpFrag<(sub node:$LHS, node:$RHS)>, "SUB">;
3041 // ADD and SUB with 's' bit set.
3043 // Currently, ADDS/SUBS are pseudo opcodes that exist only in the
3044 // selection DAG. They are "lowered" to real ADD/SUB opcodes by
3045 // AdjustInstrPostInstrSelection where we determine whether or not to
3046 // set the "s" bit based on CPSR liveness.
3048 // FIXME: Eliminate ADDS/SUBS pseudo opcodes after adding tablegen
3049 // support for an optional CPSR definition that corresponds to the DAG
3050 // node's second value. We can then eliminate the implicit def of CPSR.
3051 defm ADDS : AsI1_bin_s_irs<IIC_iALUi, IIC_iALUr, IIC_iALUsr,
3052 BinOpFrag<(ARMaddc node:$LHS, node:$RHS)>, 1>;
3053 defm SUBS : AsI1_bin_s_irs<IIC_iALUi, IIC_iALUr, IIC_iALUsr,
3054 BinOpFrag<(ARMsubc node:$LHS, node:$RHS)>>;
3056 defm ADC : AI1_adde_sube_irs<0b0101, "adc",
3057 BinOpWithFlagFrag<(ARMadde node:$LHS, node:$RHS, node:$FLAG)>,
3059 defm SBC : AI1_adde_sube_irs<0b0110, "sbc",
3060 BinOpWithFlagFrag<(ARMsube node:$LHS, node:$RHS, node:$FLAG)>,
3063 defm RSB : AsI1_rbin_irs <0b0011, "rsb",
3064 IIC_iALUi, IIC_iALUr, IIC_iALUsr,
3065 BinOpFrag<(sub node:$LHS, node:$RHS)>, "RSB">;
3067 // FIXME: Eliminate them if we can write def : Pat patterns which defines
3068 // CPSR and the implicit def of CPSR is not needed.
3069 defm RSBS : AsI1_rbin_s_is<IIC_iALUi, IIC_iALUr, IIC_iALUsr,
3070 BinOpFrag<(ARMsubc node:$LHS, node:$RHS)>>;
3072 defm RSC : AI1_rsc_irs<0b0111, "rsc",
3073 BinOpWithFlagFrag<(ARMsube node:$LHS, node:$RHS, node:$FLAG)>,
3076 // (sub X, imm) gets canonicalized to (add X, -imm). Match this form.
3077 // The assume-no-carry-in form uses the negation of the input since add/sub
3078 // assume opposite meanings of the carry flag (i.e., carry == !borrow).
3079 // See the definition of AddWithCarry() in the ARM ARM A2.2.1 for the gory
3081 def : ARMPat<(add GPR:$src, so_imm_neg:$imm),
3082 (SUBri GPR:$src, so_imm_neg:$imm)>;
3083 def : ARMPat<(ARMaddc GPR:$src, so_imm_neg:$imm),
3084 (SUBSri GPR:$src, so_imm_neg:$imm)>;
3086 // The with-carry-in form matches bitwise not instead of the negation.
3087 // Effectively, the inverse interpretation of the carry flag already accounts
3088 // for part of the negation.
3089 def : ARMPat<(ARMadde GPR:$src, so_imm_not:$imm, CPSR),
3090 (SBCri GPR:$src, so_imm_not:$imm)>;
3092 // Note: These are implemented in C++ code, because they have to generate
3093 // ADD/SUBrs instructions, which use a complex pattern that a xform function
3095 // (mul X, 2^n+1) -> (add (X << n), X)
3096 // (mul X, 2^n-1) -> (rsb X, (X << n))
3098 // ARM Arithmetic Instruction
3099 // GPR:$dst = GPR:$a op GPR:$b
3100 class AAI<bits<8> op27_20, bits<8> op11_4, string opc,
3101 list<dag> pattern = [],
3102 dag iops = (ins GPRnopc:$Rn, GPRnopc:$Rm),
3103 string asm = "\t$Rd, $Rn, $Rm">
3104 : AI<(outs GPRnopc:$Rd), iops, DPFrm, IIC_iALUr, opc, asm, pattern> {
3108 let Inst{27-20} = op27_20;
3109 let Inst{11-4} = op11_4;
3110 let Inst{19-16} = Rn;
3111 let Inst{15-12} = Rd;
3114 let Unpredictable{11-8} = 0b1111;
3117 // Saturating add/subtract
3119 def QADD : AAI<0b00010000, 0b00000101, "qadd",
3120 [(set GPRnopc:$Rd, (int_arm_qadd GPRnopc:$Rm, GPRnopc:$Rn))],
3121 (ins GPRnopc:$Rm, GPRnopc:$Rn), "\t$Rd, $Rm, $Rn">;
3122 def QSUB : AAI<0b00010010, 0b00000101, "qsub",
3123 [(set GPRnopc:$Rd, (int_arm_qsub GPRnopc:$Rm, GPRnopc:$Rn))],
3124 (ins GPRnopc:$Rm, GPRnopc:$Rn), "\t$Rd, $Rm, $Rn">;
3125 def QDADD : AAI<0b00010100, 0b00000101, "qdadd", [],
3126 (ins GPRnopc:$Rm, GPRnopc:$Rn),
3128 def QDSUB : AAI<0b00010110, 0b00000101, "qdsub", [],
3129 (ins GPRnopc:$Rm, GPRnopc:$Rn),
3132 def QADD16 : AAI<0b01100010, 0b11110001, "qadd16">;
3133 def QADD8 : AAI<0b01100010, 0b11111001, "qadd8">;
3134 def QASX : AAI<0b01100010, 0b11110011, "qasx">;
3135 def QSAX : AAI<0b01100010, 0b11110101, "qsax">;
3136 def QSUB16 : AAI<0b01100010, 0b11110111, "qsub16">;
3137 def QSUB8 : AAI<0b01100010, 0b11111111, "qsub8">;
3138 def UQADD16 : AAI<0b01100110, 0b11110001, "uqadd16">;
3139 def UQADD8 : AAI<0b01100110, 0b11111001, "uqadd8">;
3140 def UQASX : AAI<0b01100110, 0b11110011, "uqasx">;
3141 def UQSAX : AAI<0b01100110, 0b11110101, "uqsax">;
3142 def UQSUB16 : AAI<0b01100110, 0b11110111, "uqsub16">;
3143 def UQSUB8 : AAI<0b01100110, 0b11111111, "uqsub8">;
3145 // Signed/Unsigned add/subtract
3147 def SASX : AAI<0b01100001, 0b11110011, "sasx">;
3148 def SADD16 : AAI<0b01100001, 0b11110001, "sadd16">;
3149 def SADD8 : AAI<0b01100001, 0b11111001, "sadd8">;
3150 def SSAX : AAI<0b01100001, 0b11110101, "ssax">;
3151 def SSUB16 : AAI<0b01100001, 0b11110111, "ssub16">;
3152 def SSUB8 : AAI<0b01100001, 0b11111111, "ssub8">;
3153 def UASX : AAI<0b01100101, 0b11110011, "uasx">;
3154 def UADD16 : AAI<0b01100101, 0b11110001, "uadd16">;
3155 def UADD8 : AAI<0b01100101, 0b11111001, "uadd8">;
3156 def USAX : AAI<0b01100101, 0b11110101, "usax">;
3157 def USUB16 : AAI<0b01100101, 0b11110111, "usub16">;
3158 def USUB8 : AAI<0b01100101, 0b11111111, "usub8">;
3160 // Signed/Unsigned halving add/subtract
3162 def SHASX : AAI<0b01100011, 0b11110011, "shasx">;
3163 def SHADD16 : AAI<0b01100011, 0b11110001, "shadd16">;
3164 def SHADD8 : AAI<0b01100011, 0b11111001, "shadd8">;
3165 def SHSAX : AAI<0b01100011, 0b11110101, "shsax">;
3166 def SHSUB16 : AAI<0b01100011, 0b11110111, "shsub16">;
3167 def SHSUB8 : AAI<0b01100011, 0b11111111, "shsub8">;
3168 def UHASX : AAI<0b01100111, 0b11110011, "uhasx">;
3169 def UHADD16 : AAI<0b01100111, 0b11110001, "uhadd16">;
3170 def UHADD8 : AAI<0b01100111, 0b11111001, "uhadd8">;
3171 def UHSAX : AAI<0b01100111, 0b11110101, "uhsax">;
3172 def UHSUB16 : AAI<0b01100111, 0b11110111, "uhsub16">;
3173 def UHSUB8 : AAI<0b01100111, 0b11111111, "uhsub8">;
3175 // Unsigned Sum of Absolute Differences [and Accumulate].
3177 def USAD8 : AI<(outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm),
3178 MulFrm /* for convenience */, NoItinerary, "usad8",
3179 "\t$Rd, $Rn, $Rm", []>,
3180 Requires<[IsARM, HasV6]> {
3184 let Inst{27-20} = 0b01111000;
3185 let Inst{15-12} = 0b1111;
3186 let Inst{7-4} = 0b0001;
3187 let Inst{19-16} = Rd;
3188 let Inst{11-8} = Rm;
3191 def USADA8 : AI<(outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm, GPR:$Ra),
3192 MulFrm /* for convenience */, NoItinerary, "usada8",
3193 "\t$Rd, $Rn, $Rm, $Ra", []>,
3194 Requires<[IsARM, HasV6]> {
3199 let Inst{27-20} = 0b01111000;
3200 let Inst{7-4} = 0b0001;
3201 let Inst{19-16} = Rd;
3202 let Inst{15-12} = Ra;
3203 let Inst{11-8} = Rm;
3207 // Signed/Unsigned saturate
3209 def SSAT : AI<(outs GPRnopc:$Rd),
3210 (ins imm1_32:$sat_imm, GPRnopc:$Rn, shift_imm:$sh),
3211 SatFrm, NoItinerary, "ssat", "\t$Rd, $sat_imm, $Rn$sh", []> {
3216 let Inst{27-21} = 0b0110101;
3217 let Inst{5-4} = 0b01;
3218 let Inst{20-16} = sat_imm;
3219 let Inst{15-12} = Rd;
3220 let Inst{11-7} = sh{4-0};
3221 let Inst{6} = sh{5};
3225 def SSAT16 : AI<(outs GPRnopc:$Rd),
3226 (ins imm1_16:$sat_imm, GPRnopc:$Rn), SatFrm,
3227 NoItinerary, "ssat16", "\t$Rd, $sat_imm, $Rn", []> {
3231 let Inst{27-20} = 0b01101010;
3232 let Inst{11-4} = 0b11110011;
3233 let Inst{15-12} = Rd;
3234 let Inst{19-16} = sat_imm;
3238 def USAT : AI<(outs GPRnopc:$Rd),
3239 (ins imm0_31:$sat_imm, GPRnopc:$Rn, shift_imm:$sh),
3240 SatFrm, NoItinerary, "usat", "\t$Rd, $sat_imm, $Rn$sh", []> {
3245 let Inst{27-21} = 0b0110111;
3246 let Inst{5-4} = 0b01;
3247 let Inst{15-12} = Rd;
3248 let Inst{11-7} = sh{4-0};
3249 let Inst{6} = sh{5};
3250 let Inst{20-16} = sat_imm;
3254 def USAT16 : AI<(outs GPRnopc:$Rd),
3255 (ins imm0_15:$sat_imm, GPRnopc:$Rn), SatFrm,
3256 NoItinerary, "usat16", "\t$Rd, $sat_imm, $Rn", []> {
3260 let Inst{27-20} = 0b01101110;
3261 let Inst{11-4} = 0b11110011;
3262 let Inst{15-12} = Rd;
3263 let Inst{19-16} = sat_imm;
3267 def : ARMV6Pat<(int_arm_ssat GPRnopc:$a, imm:$pos),
3268 (SSAT imm:$pos, GPRnopc:$a, 0)>;
3269 def : ARMV6Pat<(int_arm_usat GPRnopc:$a, imm:$pos),
3270 (USAT imm:$pos, GPRnopc:$a, 0)>;
3272 //===----------------------------------------------------------------------===//
3273 // Bitwise Instructions.
3276 defm AND : AsI1_bin_irs<0b0000, "and",
3277 IIC_iBITi, IIC_iBITr, IIC_iBITsr,
3278 BinOpFrag<(and node:$LHS, node:$RHS)>, "AND", 1>;
3279 defm ORR : AsI1_bin_irs<0b1100, "orr",
3280 IIC_iBITi, IIC_iBITr, IIC_iBITsr,
3281 BinOpFrag<(or node:$LHS, node:$RHS)>, "ORR", 1>;
3282 defm EOR : AsI1_bin_irs<0b0001, "eor",
3283 IIC_iBITi, IIC_iBITr, IIC_iBITsr,
3284 BinOpFrag<(xor node:$LHS, node:$RHS)>, "EOR", 1>;
3285 defm BIC : AsI1_bin_irs<0b1110, "bic",
3286 IIC_iBITi, IIC_iBITr, IIC_iBITsr,
3287 BinOpFrag<(and node:$LHS, (not node:$RHS))>, "BIC">;
3289 // FIXME: bf_inv_mask_imm should be two operands, the lsb and the msb, just
3290 // like in the actual instruction encoding. The complexity of mapping the mask
3291 // to the lsb/msb pair should be handled by ISel, not encapsulated in the
3292 // instruction description.
3293 def BFC : I<(outs GPR:$Rd), (ins GPR:$src, bf_inv_mask_imm:$imm),
3294 AddrMode1, 4, IndexModeNone, DPFrm, IIC_iUNAsi,
3295 "bfc", "\t$Rd, $imm", "$src = $Rd",
3296 [(set GPR:$Rd, (and GPR:$src, bf_inv_mask_imm:$imm))]>,
3297 Requires<[IsARM, HasV6T2]> {
3300 let Inst{27-21} = 0b0111110;
3301 let Inst{6-0} = 0b0011111;
3302 let Inst{15-12} = Rd;
3303 let Inst{11-7} = imm{4-0}; // lsb
3304 let Inst{20-16} = imm{9-5}; // msb
3307 // A8.6.18 BFI - Bitfield insert (Encoding A1)
3308 def BFI:I<(outs GPRnopc:$Rd), (ins GPRnopc:$src, GPR:$Rn, bf_inv_mask_imm:$imm),
3309 AddrMode1, 4, IndexModeNone, DPFrm, IIC_iUNAsi,
3310 "bfi", "\t$Rd, $Rn, $imm", "$src = $Rd",
3311 [(set GPRnopc:$Rd, (ARMbfi GPRnopc:$src, GPR:$Rn,
3312 bf_inv_mask_imm:$imm))]>,
3313 Requires<[IsARM, HasV6T2]> {
3317 let Inst{27-21} = 0b0111110;
3318 let Inst{6-4} = 0b001; // Rn: Inst{3-0} != 15
3319 let Inst{15-12} = Rd;
3320 let Inst{11-7} = imm{4-0}; // lsb
3321 let Inst{20-16} = imm{9-5}; // width
3325 def MVNr : AsI1<0b1111, (outs GPR:$Rd), (ins GPR:$Rm), DPFrm, IIC_iMVNr,
3326 "mvn", "\t$Rd, $Rm",
3327 [(set GPR:$Rd, (not GPR:$Rm))]>, UnaryDP {
3331 let Inst{19-16} = 0b0000;
3332 let Inst{11-4} = 0b00000000;
3333 let Inst{15-12} = Rd;
3336 def MVNsi : AsI1<0b1111, (outs GPR:$Rd), (ins so_reg_imm:$shift),
3337 DPSoRegImmFrm, IIC_iMVNsr, "mvn", "\t$Rd, $shift",
3338 [(set GPR:$Rd, (not so_reg_imm:$shift))]>, UnaryDP {
3342 let Inst{19-16} = 0b0000;
3343 let Inst{15-12} = Rd;
3344 let Inst{11-5} = shift{11-5};
3346 let Inst{3-0} = shift{3-0};
3348 def MVNsr : AsI1<0b1111, (outs GPR:$Rd), (ins so_reg_reg:$shift),
3349 DPSoRegRegFrm, IIC_iMVNsr, "mvn", "\t$Rd, $shift",
3350 [(set GPR:$Rd, (not so_reg_reg:$shift))]>, UnaryDP {
3354 let Inst{19-16} = 0b0000;
3355 let Inst{15-12} = Rd;
3356 let Inst{11-8} = shift{11-8};
3358 let Inst{6-5} = shift{6-5};
3360 let Inst{3-0} = shift{3-0};
3362 let isReMaterializable = 1, isAsCheapAsAMove = 1, isMoveImm = 1 in
3363 def MVNi : AsI1<0b1111, (outs GPR:$Rd), (ins so_imm:$imm), DPFrm,
3364 IIC_iMVNi, "mvn", "\t$Rd, $imm",
3365 [(set GPR:$Rd, so_imm_not:$imm)]>,UnaryDP {
3369 let Inst{19-16} = 0b0000;
3370 let Inst{15-12} = Rd;
3371 let Inst{11-0} = imm;
3374 def : ARMPat<(and GPR:$src, so_imm_not:$imm),
3375 (BICri GPR:$src, so_imm_not:$imm)>;
3377 //===----------------------------------------------------------------------===//
3378 // Multiply Instructions.
3380 class AsMul1I32<bits<7> opcod, dag oops, dag iops, InstrItinClass itin,
3381 string opc, string asm, list<dag> pattern>
3382 : AsMul1I<opcod, oops, iops, itin, opc, asm, pattern> {
3386 let Inst{19-16} = Rd;
3387 let Inst{11-8} = Rm;
3390 class AsMul1I64<bits<7> opcod, dag oops, dag iops, InstrItinClass itin,
3391 string opc, string asm, list<dag> pattern>
3392 : AsMul1I<opcod, oops, iops, itin, opc, asm, pattern> {
3397 let Inst{19-16} = RdHi;
3398 let Inst{15-12} = RdLo;
3399 let Inst{11-8} = Rm;
3403 // FIXME: The v5 pseudos are only necessary for the additional Constraint
3404 // property. Remove them when it's possible to add those properties
3405 // on an individual MachineInstr, not just an instuction description.
3406 let isCommutable = 1, TwoOperandAliasConstraint = "$Rn = $Rd" in {
3407 def MUL : AsMul1I32<0b0000000, (outs GPRnopc:$Rd),
3408 (ins GPRnopc:$Rn, GPRnopc:$Rm),
3409 IIC_iMUL32, "mul", "\t$Rd, $Rn, $Rm",
3410 [(set GPRnopc:$Rd, (mul GPRnopc:$Rn, GPRnopc:$Rm))]>,
3411 Requires<[IsARM, HasV6]> {
3412 let Inst{15-12} = 0b0000;
3413 let Unpredictable{15-12} = 0b1111;
3416 let Constraints = "@earlyclobber $Rd" in
3417 def MULv5: ARMPseudoExpand<(outs GPRnopc:$Rd), (ins GPRnopc:$Rn, GPRnopc:$Rm,
3418 pred:$p, cc_out:$s),
3420 [(set GPRnopc:$Rd, (mul GPRnopc:$Rn, GPRnopc:$Rm))],
3421 (MUL GPRnopc:$Rd, GPRnopc:$Rn, GPRnopc:$Rm, pred:$p, cc_out:$s)>,
3422 Requires<[IsARM, NoV6]>;
3425 def MLA : AsMul1I32<0b0000001, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm, GPR:$Ra),
3426 IIC_iMAC32, "mla", "\t$Rd, $Rn, $Rm, $Ra",
3427 [(set GPR:$Rd, (add (mul GPR:$Rn, GPR:$Rm), GPR:$Ra))]>,
3428 Requires<[IsARM, HasV6]> {
3430 let Inst{15-12} = Ra;
3433 let Constraints = "@earlyclobber $Rd" in
3434 def MLAv5: ARMPseudoExpand<(outs GPR:$Rd),
3435 (ins GPR:$Rn, GPR:$Rm, GPR:$Ra, pred:$p, cc_out:$s),
3437 [(set GPR:$Rd, (add (mul GPR:$Rn, GPR:$Rm), GPR:$Ra))],
3438 (MLA GPR:$Rd, GPR:$Rn, GPR:$Rm, GPR:$Ra, pred:$p, cc_out:$s)>,
3439 Requires<[IsARM, NoV6]>;
3441 def MLS : AMul1I<0b0000011, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm, GPR:$Ra),
3442 IIC_iMAC32, "mls", "\t$Rd, $Rn, $Rm, $Ra",
3443 [(set GPR:$Rd, (sub GPR:$Ra, (mul GPR:$Rn, GPR:$Rm)))]>,
3444 Requires<[IsARM, HasV6T2]> {
3449 let Inst{19-16} = Rd;
3450 let Inst{15-12} = Ra;
3451 let Inst{11-8} = Rm;
3455 // Extra precision multiplies with low / high results
3456 let neverHasSideEffects = 1 in {
3457 let isCommutable = 1 in {
3458 def SMULL : AsMul1I64<0b0000110, (outs GPR:$RdLo, GPR:$RdHi),
3459 (ins GPR:$Rn, GPR:$Rm), IIC_iMUL64,
3460 "smull", "\t$RdLo, $RdHi, $Rn, $Rm", []>,
3461 Requires<[IsARM, HasV6]>;
3463 def UMULL : AsMul1I64<0b0000100, (outs GPR:$RdLo, GPR:$RdHi),
3464 (ins GPR:$Rn, GPR:$Rm), IIC_iMUL64,
3465 "umull", "\t$RdLo, $RdHi, $Rn, $Rm", []>,
3466 Requires<[IsARM, HasV6]>;
3468 let Constraints = "@earlyclobber $RdLo,@earlyclobber $RdHi" in {
3469 def SMULLv5 : ARMPseudoExpand<(outs GPR:$RdLo, GPR:$RdHi),
3470 (ins GPR:$Rn, GPR:$Rm, pred:$p, cc_out:$s),
3472 (SMULL GPR:$RdLo, GPR:$RdHi, GPR:$Rn, GPR:$Rm, pred:$p, cc_out:$s)>,
3473 Requires<[IsARM, NoV6]>;
3475 def UMULLv5 : ARMPseudoExpand<(outs GPR:$RdLo, GPR:$RdHi),
3476 (ins GPR:$Rn, GPR:$Rm, pred:$p, cc_out:$s),
3478 (UMULL GPR:$RdLo, GPR:$RdHi, GPR:$Rn, GPR:$Rm, pred:$p, cc_out:$s)>,
3479 Requires<[IsARM, NoV6]>;
3483 // Multiply + accumulate
3484 def SMLAL : AsMul1I64<0b0000111, (outs GPR:$RdLo, GPR:$RdHi),
3485 (ins GPR:$Rn, GPR:$Rm), IIC_iMAC64,
3486 "smlal", "\t$RdLo, $RdHi, $Rn, $Rm", []>,
3487 Requires<[IsARM, HasV6]>;
3488 def UMLAL : AsMul1I64<0b0000101, (outs GPR:$RdLo, GPR:$RdHi),
3489 (ins GPR:$Rn, GPR:$Rm), IIC_iMAC64,
3490 "umlal", "\t$RdLo, $RdHi, $Rn, $Rm", []>,
3491 Requires<[IsARM, HasV6]>;
3493 def UMAAL : AMul1I <0b0000010, (outs GPR:$RdLo, GPR:$RdHi),
3494 (ins GPR:$Rn, GPR:$Rm), IIC_iMAC64,
3495 "umaal", "\t$RdLo, $RdHi, $Rn, $Rm", []>,
3496 Requires<[IsARM, HasV6]> {
3501 let Inst{19-16} = RdHi;
3502 let Inst{15-12} = RdLo;
3503 let Inst{11-8} = Rm;
3507 let Constraints = "@earlyclobber $RdLo,@earlyclobber $RdHi" in {
3508 def SMLALv5 : ARMPseudoExpand<(outs GPR:$RdLo, GPR:$RdHi),
3509 (ins GPR:$Rn, GPR:$Rm, pred:$p, cc_out:$s),
3511 (SMLAL GPR:$RdLo, GPR:$RdHi, GPR:$Rn, GPR:$Rm, pred:$p, cc_out:$s)>,
3512 Requires<[IsARM, NoV6]>;
3513 def UMLALv5 : ARMPseudoExpand<(outs GPR:$RdLo, GPR:$RdHi),
3514 (ins GPR:$Rn, GPR:$Rm, pred:$p, cc_out:$s),
3516 (UMLAL GPR:$RdLo, GPR:$RdHi, GPR:$Rn, GPR:$Rm, pred:$p, cc_out:$s)>,
3517 Requires<[IsARM, NoV6]>;
3518 def UMAALv5 : ARMPseudoExpand<(outs GPR:$RdLo, GPR:$RdHi),
3519 (ins GPR:$Rn, GPR:$Rm, pred:$p),
3521 (UMAAL GPR:$RdLo, GPR:$RdHi, GPR:$Rn, GPR:$Rm, pred:$p)>,
3522 Requires<[IsARM, NoV6]>;
3525 } // neverHasSideEffects
3527 // Most significant word multiply
3528 def SMMUL : AMul2I <0b0111010, 0b0001, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm),
3529 IIC_iMUL32, "smmul", "\t$Rd, $Rn, $Rm",
3530 [(set GPR:$Rd, (mulhs GPR:$Rn, GPR:$Rm))]>,
3531 Requires<[IsARM, HasV6]> {
3532 let Inst{15-12} = 0b1111;
3535 def SMMULR : AMul2I <0b0111010, 0b0011, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm),
3536 IIC_iMUL32, "smmulr", "\t$Rd, $Rn, $Rm", []>,
3537 Requires<[IsARM, HasV6]> {
3538 let Inst{15-12} = 0b1111;
3541 def SMMLA : AMul2Ia <0b0111010, 0b0001, (outs GPR:$Rd),
3542 (ins GPR:$Rn, GPR:$Rm, GPR:$Ra),
3543 IIC_iMAC32, "smmla", "\t$Rd, $Rn, $Rm, $Ra",
3544 [(set GPR:$Rd, (add (mulhs GPR:$Rn, GPR:$Rm), GPR:$Ra))]>,
3545 Requires<[IsARM, HasV6]>;
3547 def SMMLAR : AMul2Ia <0b0111010, 0b0011, (outs GPR:$Rd),
3548 (ins GPR:$Rn, GPR:$Rm, GPR:$Ra),
3549 IIC_iMAC32, "smmlar", "\t$Rd, $Rn, $Rm, $Ra", []>,
3550 Requires<[IsARM, HasV6]>;
3552 def SMMLS : AMul2Ia <0b0111010, 0b1101, (outs GPR:$Rd),
3553 (ins GPR:$Rn, GPR:$Rm, GPR:$Ra),
3554 IIC_iMAC32, "smmls", "\t$Rd, $Rn, $Rm, $Ra",
3555 [(set GPR:$Rd, (sub GPR:$Ra, (mulhs GPR:$Rn, GPR:$Rm)))]>,
3556 Requires<[IsARM, HasV6]>;
3558 def SMMLSR : AMul2Ia <0b0111010, 0b1111, (outs GPR:$Rd),
3559 (ins GPR:$Rn, GPR:$Rm, GPR:$Ra),
3560 IIC_iMAC32, "smmlsr", "\t$Rd, $Rn, $Rm, $Ra", []>,
3561 Requires<[IsARM, HasV6]>;
3563 multiclass AI_smul<string opc, PatFrag opnode> {
3564 def BB : AMulxyI<0b0001011, 0b00, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm),
3565 IIC_iMUL16, !strconcat(opc, "bb"), "\t$Rd, $Rn, $Rm",
3566 [(set GPR:$Rd, (opnode (sext_inreg GPR:$Rn, i16),
3567 (sext_inreg GPR:$Rm, i16)))]>,
3568 Requires<[IsARM, HasV5TE]>;
3570 def BT : AMulxyI<0b0001011, 0b10, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm),
3571 IIC_iMUL16, !strconcat(opc, "bt"), "\t$Rd, $Rn, $Rm",
3572 [(set GPR:$Rd, (opnode (sext_inreg GPR:$Rn, i16),
3573 (sra GPR:$Rm, (i32 16))))]>,
3574 Requires<[IsARM, HasV5TE]>;
3576 def TB : AMulxyI<0b0001011, 0b01, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm),
3577 IIC_iMUL16, !strconcat(opc, "tb"), "\t$Rd, $Rn, $Rm",
3578 [(set GPR:$Rd, (opnode (sra GPR:$Rn, (i32 16)),
3579 (sext_inreg GPR:$Rm, i16)))]>,
3580 Requires<[IsARM, HasV5TE]>;
3582 def TT : AMulxyI<0b0001011, 0b11, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm),
3583 IIC_iMUL16, !strconcat(opc, "tt"), "\t$Rd, $Rn, $Rm",
3584 [(set GPR:$Rd, (opnode (sra GPR:$Rn, (i32 16)),
3585 (sra GPR:$Rm, (i32 16))))]>,
3586 Requires<[IsARM, HasV5TE]>;
3588 def WB : AMulxyI<0b0001001, 0b01, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm),
3589 IIC_iMUL16, !strconcat(opc, "wb"), "\t$Rd, $Rn, $Rm",
3590 [(set GPR:$Rd, (sra (opnode GPR:$Rn,
3591 (sext_inreg GPR:$Rm, i16)), (i32 16)))]>,
3592 Requires<[IsARM, HasV5TE]>;
3594 def WT : AMulxyI<0b0001001, 0b11, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm),
3595 IIC_iMUL16, !strconcat(opc, "wt"), "\t$Rd, $Rn, $Rm",
3596 [(set GPR:$Rd, (sra (opnode GPR:$Rn,
3597 (sra GPR:$Rm, (i32 16))), (i32 16)))]>,
3598 Requires<[IsARM, HasV5TE]>;
3602 multiclass AI_smla<string opc, PatFrag opnode> {
3603 let DecoderMethod = "DecodeSMLAInstruction" in {
3604 def BB : AMulxyIa<0b0001000, 0b00, (outs GPRnopc:$Rd),
3605 (ins GPRnopc:$Rn, GPRnopc:$Rm, GPR:$Ra),
3606 IIC_iMAC16, !strconcat(opc, "bb"), "\t$Rd, $Rn, $Rm, $Ra",
3607 [(set GPRnopc:$Rd, (add GPR:$Ra,
3608 (opnode (sext_inreg GPRnopc:$Rn, i16),
3609 (sext_inreg GPRnopc:$Rm, i16))))]>,
3610 Requires<[IsARM, HasV5TE]>;
3612 def BT : AMulxyIa<0b0001000, 0b10, (outs GPRnopc:$Rd),
3613 (ins GPRnopc:$Rn, GPRnopc:$Rm, GPR:$Ra),
3614 IIC_iMAC16, !strconcat(opc, "bt"), "\t$Rd, $Rn, $Rm, $Ra",
3616 (add GPR:$Ra, (opnode (sext_inreg GPRnopc:$Rn, i16),
3617 (sra GPRnopc:$Rm, (i32 16)))))]>,
3618 Requires<[IsARM, HasV5TE]>;
3620 def TB : AMulxyIa<0b0001000, 0b01, (outs GPRnopc:$Rd),
3621 (ins GPRnopc:$Rn, GPRnopc:$Rm, GPR:$Ra),
3622 IIC_iMAC16, !strconcat(opc, "tb"), "\t$Rd, $Rn, $Rm, $Ra",
3624 (add GPR:$Ra, (opnode (sra GPRnopc:$Rn, (i32 16)),
3625 (sext_inreg GPRnopc:$Rm, i16))))]>,
3626 Requires<[IsARM, HasV5TE]>;
3628 def TT : AMulxyIa<0b0001000, 0b11, (outs GPRnopc:$Rd),
3629 (ins GPRnopc:$Rn, GPRnopc:$Rm, GPR:$Ra),
3630 IIC_iMAC16, !strconcat(opc, "tt"), "\t$Rd, $Rn, $Rm, $Ra",
3632 (add GPR:$Ra, (opnode (sra GPRnopc:$Rn, (i32 16)),
3633 (sra GPRnopc:$Rm, (i32 16)))))]>,
3634 Requires<[IsARM, HasV5TE]>;
3636 def WB : AMulxyIa<0b0001001, 0b00, (outs GPRnopc:$Rd),
3637 (ins GPRnopc:$Rn, GPRnopc:$Rm, GPR:$Ra),
3638 IIC_iMAC16, !strconcat(opc, "wb"), "\t$Rd, $Rn, $Rm, $Ra",
3640 (add GPR:$Ra, (sra (opnode GPRnopc:$Rn,
3641 (sext_inreg GPRnopc:$Rm, i16)), (i32 16))))]>,
3642 Requires<[IsARM, HasV5TE]>;
3644 def WT : AMulxyIa<0b0001001, 0b10, (outs GPRnopc:$Rd),
3645 (ins GPRnopc:$Rn, GPRnopc:$Rm, GPR:$Ra),
3646 IIC_iMAC16, !strconcat(opc, "wt"), "\t$Rd, $Rn, $Rm, $Ra",
3648 (add GPR:$Ra, (sra (opnode GPRnopc:$Rn,
3649 (sra GPRnopc:$Rm, (i32 16))), (i32 16))))]>,
3650 Requires<[IsARM, HasV5TE]>;
3654 defm SMUL : AI_smul<"smul", BinOpFrag<(mul node:$LHS, node:$RHS)>>;
3655 defm SMLA : AI_smla<"smla", BinOpFrag<(mul node:$LHS, node:$RHS)>>;
3657 // Halfword multiply accumulate long: SMLAL<x><y>.
3658 def SMLALBB : AMulxyI64<0b0001010, 0b00, (outs GPRnopc:$RdLo, GPRnopc:$RdHi),
3659 (ins GPRnopc:$Rn, GPRnopc:$Rm),
3660 IIC_iMAC64, "smlalbb", "\t$RdLo, $RdHi, $Rn, $Rm", []>,
3661 Requires<[IsARM, HasV5TE]>;
3663 def SMLALBT : AMulxyI64<0b0001010, 0b10, (outs GPRnopc:$RdLo, GPRnopc:$RdHi),
3664 (ins GPRnopc:$Rn, GPRnopc:$Rm),
3665 IIC_iMAC64, "smlalbt", "\t$RdLo, $RdHi, $Rn, $Rm", []>,
3666 Requires<[IsARM, HasV5TE]>;
3668 def SMLALTB : AMulxyI64<0b0001010, 0b01, (outs GPRnopc:$RdLo, GPRnopc:$RdHi),
3669 (ins GPRnopc:$Rn, GPRnopc:$Rm),
3670 IIC_iMAC64, "smlaltb", "\t$RdLo, $RdHi, $Rn, $Rm", []>,
3671 Requires<[IsARM, HasV5TE]>;
3673 def SMLALTT : AMulxyI64<0b0001010, 0b11, (outs GPRnopc:$RdLo, GPRnopc:$RdHi),
3674 (ins GPRnopc:$Rn, GPRnopc:$Rm),
3675 IIC_iMAC64, "smlaltt", "\t$RdLo, $RdHi, $Rn, $Rm", []>,
3676 Requires<[IsARM, HasV5TE]>;
3678 // Helper class for AI_smld.
3679 class AMulDualIbase<bit long, bit sub, bit swap, dag oops, dag iops,
3680 InstrItinClass itin, string opc, string asm>
3681 : AI<oops, iops, MulFrm, itin, opc, asm, []>, Requires<[IsARM, HasV6]> {
3684 let Inst{27-23} = 0b01110;
3685 let Inst{22} = long;
3686 let Inst{21-20} = 0b00;
3687 let Inst{11-8} = Rm;
3694 class AMulDualI<bit long, bit sub, bit swap, dag oops, dag iops,
3695 InstrItinClass itin, string opc, string asm>
3696 : AMulDualIbase<long, sub, swap, oops, iops, itin, opc, asm> {
3698 let Inst{15-12} = 0b1111;
3699 let Inst{19-16} = Rd;
3701 class AMulDualIa<bit long, bit sub, bit swap, dag oops, dag iops,
3702 InstrItinClass itin, string opc, string asm>
3703 : AMulDualIbase<long, sub, swap, oops, iops, itin, opc, asm> {
3706 let Inst{19-16} = Rd;
3707 let Inst{15-12} = Ra;
3709 class AMulDualI64<bit long, bit sub, bit swap, dag oops, dag iops,
3710 InstrItinClass itin, string opc, string asm>
3711 : AMulDualIbase<long, sub, swap, oops, iops, itin, opc, asm> {
3714 let Inst{19-16} = RdHi;
3715 let Inst{15-12} = RdLo;
3718 multiclass AI_smld<bit sub, string opc> {
3720 def D : AMulDualIa<0, sub, 0, (outs GPRnopc:$Rd),
3721 (ins GPRnopc:$Rn, GPRnopc:$Rm, GPR:$Ra),
3722 NoItinerary, !strconcat(opc, "d"), "\t$Rd, $Rn, $Rm, $Ra">;
3724 def DX: AMulDualIa<0, sub, 1, (outs GPRnopc:$Rd),
3725 (ins GPRnopc:$Rn, GPRnopc:$Rm, GPR:$Ra),
3726 NoItinerary, !strconcat(opc, "dx"), "\t$Rd, $Rn, $Rm, $Ra">;
3728 def LD: AMulDualI64<1, sub, 0, (outs GPRnopc:$RdLo, GPRnopc:$RdHi),
3729 (ins GPRnopc:$Rn, GPRnopc:$Rm), NoItinerary,
3730 !strconcat(opc, "ld"), "\t$RdLo, $RdHi, $Rn, $Rm">;
3732 def LDX : AMulDualI64<1, sub, 1, (outs GPRnopc:$RdLo, GPRnopc:$RdHi),
3733 (ins GPRnopc:$Rn, GPRnopc:$Rm), NoItinerary,
3734 !strconcat(opc, "ldx"),"\t$RdLo, $RdHi, $Rn, $Rm">;
3738 defm SMLA : AI_smld<0, "smla">;
3739 defm SMLS : AI_smld<1, "smls">;
3741 multiclass AI_sdml<bit sub, string opc> {
3743 def D:AMulDualI<0, sub, 0, (outs GPRnopc:$Rd), (ins GPRnopc:$Rn, GPRnopc:$Rm),
3744 NoItinerary, !strconcat(opc, "d"), "\t$Rd, $Rn, $Rm">;
3745 def DX:AMulDualI<0, sub, 1, (outs GPRnopc:$Rd),(ins GPRnopc:$Rn, GPRnopc:$Rm),
3746 NoItinerary, !strconcat(opc, "dx"), "\t$Rd, $Rn, $Rm">;
3749 defm SMUA : AI_sdml<0, "smua">;
3750 defm SMUS : AI_sdml<1, "smus">;
3752 //===----------------------------------------------------------------------===//
3753 // Misc. Arithmetic Instructions.
3756 def CLZ : AMiscA1I<0b000010110, 0b0001, (outs GPR:$Rd), (ins GPR:$Rm),
3757 IIC_iUNAr, "clz", "\t$Rd, $Rm",
3758 [(set GPR:$Rd, (ctlz GPR:$Rm))]>, Requires<[IsARM, HasV5T]>;
3760 def RBIT : AMiscA1I<0b01101111, 0b0011, (outs GPR:$Rd), (ins GPR:$Rm),
3761 IIC_iUNAr, "rbit", "\t$Rd, $Rm",
3762 [(set GPR:$Rd, (ARMrbit GPR:$Rm))]>,
3763 Requires<[IsARM, HasV6T2]>;
3765 def REV : AMiscA1I<0b01101011, 0b0011, (outs GPR:$Rd), (ins GPR:$Rm),
3766 IIC_iUNAr, "rev", "\t$Rd, $Rm",
3767 [(set GPR:$Rd, (bswap GPR:$Rm))]>, Requires<[IsARM, HasV6]>;
3769 let AddedComplexity = 5 in
3770 def REV16 : AMiscA1I<0b01101011, 0b1011, (outs GPR:$Rd), (ins GPR:$Rm),
3771 IIC_iUNAr, "rev16", "\t$Rd, $Rm",
3772 [(set GPR:$Rd, (rotr (bswap GPR:$Rm), (i32 16)))]>,
3773 Requires<[IsARM, HasV6]>;
3775 let AddedComplexity = 5 in
3776 def REVSH : AMiscA1I<0b01101111, 0b1011, (outs GPR:$Rd), (ins GPR:$Rm),
3777 IIC_iUNAr, "revsh", "\t$Rd, $Rm",
3778 [(set GPR:$Rd, (sra (bswap GPR:$Rm), (i32 16)))]>,
3779 Requires<[IsARM, HasV6]>;
3781 def : ARMV6Pat<(or (sra (shl GPR:$Rm, (i32 24)), (i32 16)),
3782 (and (srl GPR:$Rm, (i32 8)), 0xFF)),
3785 def PKHBT : APKHI<0b01101000, 0, (outs GPRnopc:$Rd),
3786 (ins GPRnopc:$Rn, GPRnopc:$Rm, pkh_lsl_amt:$sh),
3787 IIC_iALUsi, "pkhbt", "\t$Rd, $Rn, $Rm$sh",
3788 [(set GPRnopc:$Rd, (or (and GPRnopc:$Rn, 0xFFFF),
3789 (and (shl GPRnopc:$Rm, pkh_lsl_amt:$sh),
3791 Requires<[IsARM, HasV6]>;
3793 // Alternate cases for PKHBT where identities eliminate some nodes.
3794 def : ARMV6Pat<(or (and GPRnopc:$Rn, 0xFFFF), (and GPRnopc:$Rm, 0xFFFF0000)),
3795 (PKHBT GPRnopc:$Rn, GPRnopc:$Rm, 0)>;
3796 def : ARMV6Pat<(or (and GPRnopc:$Rn, 0xFFFF), (shl GPRnopc:$Rm, imm16_31:$sh)),
3797 (PKHBT GPRnopc:$Rn, GPRnopc:$Rm, imm16_31:$sh)>;
3799 // Note: Shifts of 1-15 bits will be transformed to srl instead of sra and
3800 // will match the pattern below.
3801 def PKHTB : APKHI<0b01101000, 1, (outs GPRnopc:$Rd),
3802 (ins GPRnopc:$Rn, GPRnopc:$Rm, pkh_asr_amt:$sh),
3803 IIC_iBITsi, "pkhtb", "\t$Rd, $Rn, $Rm$sh",
3804 [(set GPRnopc:$Rd, (or (and GPRnopc:$Rn, 0xFFFF0000),
3805 (and (sra GPRnopc:$Rm, pkh_asr_amt:$sh),
3807 Requires<[IsARM, HasV6]>;
3809 // Alternate cases for PKHTB where identities eliminate some nodes. Note that
3810 // a shift amount of 0 is *not legal* here, it is PKHBT instead.
3811 def : ARMV6Pat<(or (and GPRnopc:$src1, 0xFFFF0000),
3812 (srl GPRnopc:$src2, imm16_31:$sh)),
3813 (PKHTB GPRnopc:$src1, GPRnopc:$src2, imm16_31:$sh)>;
3814 def : ARMV6Pat<(or (and GPRnopc:$src1, 0xFFFF0000),
3815 (and (srl GPRnopc:$src2, imm1_15:$sh), 0xFFFF)),
3816 (PKHTB GPRnopc:$src1, GPRnopc:$src2, imm1_15:$sh)>;
3818 //===----------------------------------------------------------------------===//
3819 // Comparison Instructions...
3822 defm CMP : AI1_cmp_irs<0b1010, "cmp",
3823 IIC_iCMPi, IIC_iCMPr, IIC_iCMPsr,
3824 BinOpFrag<(ARMcmp node:$LHS, node:$RHS)>>;
3826 // ARMcmpZ can re-use the above instruction definitions.
3827 def : ARMPat<(ARMcmpZ GPR:$src, so_imm:$imm),
3828 (CMPri GPR:$src, so_imm:$imm)>;
3829 def : ARMPat<(ARMcmpZ GPR:$src, GPR:$rhs),
3830 (CMPrr GPR:$src, GPR:$rhs)>;
3831 def : ARMPat<(ARMcmpZ GPR:$src, so_reg_imm:$rhs),
3832 (CMPrsi GPR:$src, so_reg_imm:$rhs)>;
3833 def : ARMPat<(ARMcmpZ GPR:$src, so_reg_reg:$rhs),
3834 (CMPrsr GPR:$src, so_reg_reg:$rhs)>;
3836 // FIXME: We have to be careful when using the CMN instruction and comparison
3837 // with 0. One would expect these two pieces of code should give identical
3853 // However, the CMN gives the *opposite* result when r1 is 0. This is because
3854 // the carry flag is set in the CMP case but not in the CMN case. In short, the
3855 // CMP instruction doesn't perform a truncate of the (logical) NOT of 0 plus the
3856 // value of r0 and the carry bit (because the "carry bit" parameter to
3857 // AddWithCarry is defined as 1 in this case, the carry flag will always be set
3858 // when r0 >= 0). The CMN instruction doesn't perform a NOT of 0 so there is
3859 // never a "carry" when this AddWithCarry is performed (because the "carry bit"
3860 // parameter to AddWithCarry is defined as 0).
3862 // When x is 0 and unsigned:
3866 // ~x + 1 = 0x1 0000 0000
3867 // (-x = 0) != (0x1 0000 0000 = ~x + 1)
3869 // Therefore, we should disable CMN when comparing against zero, until we can
3870 // limit when the CMN instruction is used (when we know that the RHS is not 0 or
3871 // when it's a comparison which doesn't look at the 'carry' flag).
3873 // (See the ARM docs for the "AddWithCarry" pseudo-code.)
3875 // This is related to <rdar://problem/7569620>.
3877 //defm CMN : AI1_cmp_irs<0b1011, "cmn",
3878 // BinOpFrag<(ARMcmp node:$LHS,(ineg node:$RHS))>>;
3880 // Note that TST/TEQ don't set all the same flags that CMP does!
3881 defm TST : AI1_cmp_irs<0b1000, "tst",
3882 IIC_iTSTi, IIC_iTSTr, IIC_iTSTsr,
3883 BinOpFrag<(ARMcmpZ (and_su node:$LHS, node:$RHS), 0)>, 1>;
3884 defm TEQ : AI1_cmp_irs<0b1001, "teq",
3885 IIC_iTSTi, IIC_iTSTr, IIC_iTSTsr,
3886 BinOpFrag<(ARMcmpZ (xor_su node:$LHS, node:$RHS), 0)>, 1>;
3888 defm CMNz : AI1_cmp_irs<0b1011, "cmn",
3889 IIC_iCMPi, IIC_iCMPr, IIC_iCMPsr,
3890 BinOpFrag<(ARMcmpZ node:$LHS,(ineg node:$RHS))>>;
3892 //def : ARMPat<(ARMcmp GPR:$src, so_imm_neg:$imm),
3893 // (CMNri GPR:$src, so_imm_neg:$imm)>;
3895 def : ARMPat<(ARMcmpZ GPR:$src, so_imm_neg:$imm),
3896 (CMNzri GPR:$src, so_imm_neg:$imm)>;
3898 // Pseudo i64 compares for some floating point compares.
3899 let usesCustomInserter = 1, isBranch = 1, isTerminator = 1,
3901 def BCCi64 : PseudoInst<(outs),
3902 (ins i32imm:$cc, GPR:$lhs1, GPR:$lhs2, GPR:$rhs1, GPR:$rhs2, brtarget:$dst),
3904 [(ARMBcci64 imm:$cc, GPR:$lhs1, GPR:$lhs2, GPR:$rhs1, GPR:$rhs2, bb:$dst)]>;
3906 def BCCZi64 : PseudoInst<(outs),
3907 (ins i32imm:$cc, GPR:$lhs1, GPR:$lhs2, brtarget:$dst), IIC_Br,
3908 [(ARMBcci64 imm:$cc, GPR:$lhs1, GPR:$lhs2, 0, 0, bb:$dst)]>;
3909 } // usesCustomInserter
3912 // Conditional moves
3913 // FIXME: should be able to write a pattern for ARMcmov, but can't use
3914 // a two-value operand where a dag node expects two operands. :(
3915 let neverHasSideEffects = 1 in {
3917 let isCommutable = 1 in
3918 def MOVCCr : ARMPseudoInst<(outs GPR:$Rd), (ins GPR:$false, GPR:$Rm, pred:$p),
3920 [/*(set GPR:$Rd, (ARMcmov GPR:$false, GPR:$Rm, imm:$cc, CCR:$ccr))*/]>,
3921 RegConstraint<"$false = $Rd">;
3923 def MOVCCsi : ARMPseudoInst<(outs GPR:$Rd),
3924 (ins GPR:$false, so_reg_imm:$shift, pred:$p),
3926 [/*(set GPR:$Rd, (ARMcmov GPR:$false, so_reg_imm:$shift,
3927 imm:$cc, CCR:$ccr))*/]>,
3928 RegConstraint<"$false = $Rd">;
3929 def MOVCCsr : ARMPseudoInst<(outs GPR:$Rd),
3930 (ins GPR:$false, so_reg_reg:$shift, pred:$p),
3932 [/*(set GPR:$Rd, (ARMcmov GPR:$false, so_reg_reg:$shift,
3933 imm:$cc, CCR:$ccr))*/]>,
3934 RegConstraint<"$false = $Rd">;
3937 let isMoveImm = 1 in
3938 def MOVCCi16 : ARMPseudoInst<(outs GPR:$Rd),
3939 (ins GPR:$false, imm0_65535_expr:$imm, pred:$p),
3942 RegConstraint<"$false = $Rd">, Requires<[IsARM, HasV6T2]>;
3944 let isMoveImm = 1 in
3945 def MOVCCi : ARMPseudoInst<(outs GPR:$Rd),
3946 (ins GPR:$false, so_imm:$imm, pred:$p),
3948 [/*(set GPR:$Rd, (ARMcmov GPR:$false, so_imm:$imm, imm:$cc, CCR:$ccr))*/]>,
3949 RegConstraint<"$false = $Rd">;
3951 // Two instruction predicate mov immediate.
3952 let isMoveImm = 1 in
3953 def MOVCCi32imm : ARMPseudoInst<(outs GPR:$Rd),
3954 (ins GPR:$false, i32imm:$src, pred:$p),
3955 8, IIC_iCMOVix2, []>, RegConstraint<"$false = $Rd">;
3957 let isMoveImm = 1 in
3958 def MVNCCi : ARMPseudoInst<(outs GPR:$Rd),
3959 (ins GPR:$false, so_imm:$imm, pred:$p),
3961 [/*(set GPR:$Rd, (ARMcmov GPR:$false, so_imm_not:$imm, imm:$cc, CCR:$ccr))*/]>,
3962 RegConstraint<"$false = $Rd">;
3964 // Conditional instructions
3965 multiclass AsI1_bincc_irs<Instruction iri, Instruction irr, Instruction irsi,
3967 InstrItinClass iii, InstrItinClass iir,
3968 InstrItinClass iis> {
3969 def ri : ARMPseudoExpand<(outs GPR:$Rd),
3970 (ins GPR:$Rn, so_imm:$imm, pred:$p, cc_out:$s),
3972 (iri GPR:$Rd, GPR:$Rn, so_imm:$imm, pred:$p, cc_out:$s)>,
3973 RegConstraint<"$Rn = $Rd">;
3974 def rr : ARMPseudoExpand<(outs GPR:$Rd),
3975 (ins GPR:$Rn, GPR:$Rm, pred:$p, cc_out:$s),
3977 (irr GPR:$Rd, GPR:$Rn, GPR:$Rm, pred:$p, cc_out:$s)>,
3978 RegConstraint<"$Rn = $Rd">;
3979 def rsi : ARMPseudoExpand<(outs GPR:$Rd),
3980 (ins GPR:$Rn, so_reg_imm:$shift, pred:$p, cc_out:$s),
3982 (irsi GPR:$Rd, GPR:$Rn, so_reg_imm:$shift, pred:$p, cc_out:$s)>,
3983 RegConstraint<"$Rn = $Rd">;
3984 def rsr : ARMPseudoExpand<(outs GPRnopc:$Rd),
3985 (ins GPRnopc:$Rn, so_reg_reg:$shift, pred:$p, cc_out:$s),
3987 (irsr GPR:$Rd, GPR:$Rn, so_reg_reg:$shift, pred:$p, cc_out:$s)>,
3988 RegConstraint<"$Rn = $Rd">;
3991 defm ANDCC : AsI1_bincc_irs<ANDri, ANDrr, ANDrsi, ANDrsr,
3992 IIC_iBITi, IIC_iBITr, IIC_iBITsr>;
3993 defm ORRCC : AsI1_bincc_irs<ORRri, ORRrr, ORRrsi, ORRrsr,
3994 IIC_iBITi, IIC_iBITr, IIC_iBITsr>;
3995 defm EORCC : AsI1_bincc_irs<EORri, EORrr, EORrsi, EORrsr,
3996 IIC_iBITi, IIC_iBITr, IIC_iBITsr>;
3998 } // neverHasSideEffects
4001 //===----------------------------------------------------------------------===//
4002 // Atomic operations intrinsics
4005 def MemBarrierOptOperand : AsmOperandClass {
4006 let Name = "MemBarrierOpt";
4007 let ParserMethod = "parseMemBarrierOptOperand";
4009 def memb_opt : Operand<i32> {
4010 let PrintMethod = "printMemBOption";
4011 let ParserMatchClass = MemBarrierOptOperand;
4012 let DecoderMethod = "DecodeMemBarrierOption";
4015 // memory barriers protect the atomic sequences
4016 let hasSideEffects = 1 in {
4017 def DMB : AInoP<(outs), (ins memb_opt:$opt), MiscFrm, NoItinerary,
4018 "dmb", "\t$opt", [(ARMMemBarrier (i32 imm:$opt))]>,
4019 Requires<[IsARM, HasDB]> {
4021 let Inst{31-4} = 0xf57ff05;
4022 let Inst{3-0} = opt;
4026 def DSB : AInoP<(outs), (ins memb_opt:$opt), MiscFrm, NoItinerary,
4027 "dsb", "\t$opt", []>,
4028 Requires<[IsARM, HasDB]> {
4030 let Inst{31-4} = 0xf57ff04;
4031 let Inst{3-0} = opt;
4034 // ISB has only full system option
4035 def ISB : AInoP<(outs), (ins memb_opt:$opt), MiscFrm, NoItinerary,
4036 "isb", "\t$opt", []>,
4037 Requires<[IsARM, HasDB]> {
4039 let Inst{31-4} = 0xf57ff06;
4040 let Inst{3-0} = opt;
4043 // Pseudo instruction that combines movs + predicated rsbmi
4044 // to implement integer ABS
4045 let usesCustomInserter = 1, Defs = [CPSR] in {
4046 def ABS : ARMPseudoInst<
4047 (outs GPR:$dst), (ins GPR:$src),
4048 8, NoItinerary, []>;
4051 let usesCustomInserter = 1 in {
4052 let Defs = [CPSR] in {
4053 def ATOMIC_LOAD_ADD_I8 : PseudoInst<
4054 (outs GPR:$dst), (ins GPR:$ptr, GPR:$incr), NoItinerary,
4055 [(set GPR:$dst, (atomic_load_add_8 GPR:$ptr, GPR:$incr))]>;
4056 def ATOMIC_LOAD_SUB_I8 : PseudoInst<
4057 (outs GPR:$dst), (ins GPR:$ptr, GPR:$incr), NoItinerary,
4058 [(set GPR:$dst, (atomic_load_sub_8 GPR:$ptr, GPR:$incr))]>;
4059 def ATOMIC_LOAD_AND_I8 : PseudoInst<
4060 (outs GPR:$dst), (ins GPR:$ptr, GPR:$incr), NoItinerary,
4061 [(set GPR:$dst, (atomic_load_and_8 GPR:$ptr, GPR:$incr))]>;
4062 def ATOMIC_LOAD_OR_I8 : PseudoInst<
4063 (outs GPR:$dst), (ins GPR:$ptr, GPR:$incr), NoItinerary,
4064 [(set GPR:$dst, (atomic_load_or_8 GPR:$ptr, GPR:$incr))]>;
4065 def ATOMIC_LOAD_XOR_I8 : PseudoInst<
4066 (outs GPR:$dst), (ins GPR:$ptr, GPR:$incr), NoItinerary,
4067 [(set GPR:$dst, (atomic_load_xor_8 GPR:$ptr, GPR:$incr))]>;
4068 def ATOMIC_LOAD_NAND_I8 : PseudoInst<
4069 (outs GPR:$dst), (ins GPR:$ptr, GPR:$incr), NoItinerary,
4070 [(set GPR:$dst, (atomic_load_nand_8 GPR:$ptr, GPR:$incr))]>;
4071 def ATOMIC_LOAD_MIN_I8 : PseudoInst<
4072 (outs GPR:$dst), (ins GPR:$ptr, GPR:$val), NoItinerary,
4073 [(set GPR:$dst, (atomic_load_min_8 GPR:$ptr, GPR:$val))]>;
4074 def ATOMIC_LOAD_MAX_I8 : PseudoInst<
4075 (outs GPR:$dst), (ins GPR:$ptr, GPR:$val), NoItinerary,
4076 [(set GPR:$dst, (atomic_load_max_8 GPR:$ptr, GPR:$val))]>;
4077 def ATOMIC_LOAD_UMIN_I8 : PseudoInst<
4078 (outs GPR:$dst), (ins GPR:$ptr, GPR:$val), NoItinerary,
4079 [(set GPR:$dst, (atomic_load_umin_8 GPR:$ptr, GPR:$val))]>;
4080 def ATOMIC_LOAD_UMAX_I8 : PseudoInst<
4081 (outs GPR:$dst), (ins GPR:$ptr, GPR:$val), NoItinerary,
4082 [(set GPR:$dst, (atomic_load_umax_8 GPR:$ptr, GPR:$val))]>;
4083 def ATOMIC_LOAD_ADD_I16 : PseudoInst<
4084 (outs GPR:$dst), (ins GPR:$ptr, GPR:$incr), NoItinerary,
4085 [(set GPR:$dst, (atomic_load_add_16 GPR:$ptr, GPR:$incr))]>;
4086 def ATOMIC_LOAD_SUB_I16 : PseudoInst<
4087 (outs GPR:$dst), (ins GPR:$ptr, GPR:$incr), NoItinerary,
4088 [(set GPR:$dst, (atomic_load_sub_16 GPR:$ptr, GPR:$incr))]>;
4089 def ATOMIC_LOAD_AND_I16 : PseudoInst<
4090 (outs GPR:$dst), (ins GPR:$ptr, GPR:$incr), NoItinerary,
4091 [(set GPR:$dst, (atomic_load_and_16 GPR:$ptr, GPR:$incr))]>;
4092 def ATOMIC_LOAD_OR_I16 : PseudoInst<
4093 (outs GPR:$dst), (ins GPR:$ptr, GPR:$incr), NoItinerary,
4094 [(set GPR:$dst, (atomic_load_or_16 GPR:$ptr, GPR:$incr))]>;
4095 def ATOMIC_LOAD_XOR_I16 : PseudoInst<
4096 (outs GPR:$dst), (ins GPR:$ptr, GPR:$incr), NoItinerary,
4097 [(set GPR:$dst, (atomic_load_xor_16 GPR:$ptr, GPR:$incr))]>;
4098 def ATOMIC_LOAD_NAND_I16 : PseudoInst<
4099 (outs GPR:$dst), (ins GPR:$ptr, GPR:$incr), NoItinerary,
4100 [(set GPR:$dst, (atomic_load_nand_16 GPR:$ptr, GPR:$incr))]>;
4101 def ATOMIC_LOAD_MIN_I16 : PseudoInst<
4102 (outs GPR:$dst), (ins GPR:$ptr, GPR:$val), NoItinerary,
4103 [(set GPR:$dst, (atomic_load_min_16 GPR:$ptr, GPR:$val))]>;
4104 def ATOMIC_LOAD_MAX_I16 : PseudoInst<
4105 (outs GPR:$dst), (ins GPR:$ptr, GPR:$val), NoItinerary,
4106 [(set GPR:$dst, (atomic_load_max_16 GPR:$ptr, GPR:$val))]>;
4107 def ATOMIC_LOAD_UMIN_I16 : PseudoInst<
4108 (outs GPR:$dst), (ins GPR:$ptr, GPR:$val), NoItinerary,
4109 [(set GPR:$dst, (atomic_load_umin_16 GPR:$ptr, GPR:$val))]>;
4110 def ATOMIC_LOAD_UMAX_I16 : PseudoInst<
4111 (outs GPR:$dst), (ins GPR:$ptr, GPR:$val), NoItinerary,
4112 [(set GPR:$dst, (atomic_load_umax_16 GPR:$ptr, GPR:$val))]>;
4113 def ATOMIC_LOAD_ADD_I32 : PseudoInst<
4114 (outs GPR:$dst), (ins GPR:$ptr, GPR:$incr), NoItinerary,
4115 [(set GPR:$dst, (atomic_load_add_32 GPR:$ptr, GPR:$incr))]>;
4116 def ATOMIC_LOAD_SUB_I32 : PseudoInst<
4117 (outs GPR:$dst), (ins GPR:$ptr, GPR:$incr), NoItinerary,
4118 [(set GPR:$dst, (atomic_load_sub_32 GPR:$ptr, GPR:$incr))]>;
4119 def ATOMIC_LOAD_AND_I32 : PseudoInst<
4120 (outs GPR:$dst), (ins GPR:$ptr, GPR:$incr), NoItinerary,
4121 [(set GPR:$dst, (atomic_load_and_32 GPR:$ptr, GPR:$incr))]>;
4122 def ATOMIC_LOAD_OR_I32 : PseudoInst<
4123 (outs GPR:$dst), (ins GPR:$ptr, GPR:$incr), NoItinerary,
4124 [(set GPR:$dst, (atomic_load_or_32 GPR:$ptr, GPR:$incr))]>;
4125 def ATOMIC_LOAD_XOR_I32 : PseudoInst<
4126 (outs GPR:$dst), (ins GPR:$ptr, GPR:$incr), NoItinerary,
4127 [(set GPR:$dst, (atomic_load_xor_32 GPR:$ptr, GPR:$incr))]>;
4128 def ATOMIC_LOAD_NAND_I32 : PseudoInst<
4129 (outs GPR:$dst), (ins GPR:$ptr, GPR:$incr), NoItinerary,
4130 [(set GPR:$dst, (atomic_load_nand_32 GPR:$ptr, GPR:$incr))]>;
4131 def ATOMIC_LOAD_MIN_I32 : PseudoInst<
4132 (outs GPR:$dst), (ins GPR:$ptr, GPR:$val), NoItinerary,
4133 [(set GPR:$dst, (atomic_load_min_32 GPR:$ptr, GPR:$val))]>;
4134 def ATOMIC_LOAD_MAX_I32 : PseudoInst<
4135 (outs GPR:$dst), (ins GPR:$ptr, GPR:$val), NoItinerary,
4136 [(set GPR:$dst, (atomic_load_max_32 GPR:$ptr, GPR:$val))]>;
4137 def ATOMIC_LOAD_UMIN_I32 : PseudoInst<
4138 (outs GPR:$dst), (ins GPR:$ptr, GPR:$val), NoItinerary,
4139 [(set GPR:$dst, (atomic_load_umin_32 GPR:$ptr, GPR:$val))]>;
4140 def ATOMIC_LOAD_UMAX_I32 : PseudoInst<
4141 (outs GPR:$dst), (ins GPR:$ptr, GPR:$val), NoItinerary,
4142 [(set GPR:$dst, (atomic_load_umax_32 GPR:$ptr, GPR:$val))]>;
4144 def ATOMIC_SWAP_I8 : PseudoInst<
4145 (outs GPR:$dst), (ins GPR:$ptr, GPR:$new), NoItinerary,
4146 [(set GPR:$dst, (atomic_swap_8 GPR:$ptr, GPR:$new))]>;
4147 def ATOMIC_SWAP_I16 : PseudoInst<
4148 (outs GPR:$dst), (ins GPR:$ptr, GPR:$new), NoItinerary,
4149 [(set GPR:$dst, (atomic_swap_16 GPR:$ptr, GPR:$new))]>;
4150 def ATOMIC_SWAP_I32 : PseudoInst<
4151 (outs GPR:$dst), (ins GPR:$ptr, GPR:$new), NoItinerary,
4152 [(set GPR:$dst, (atomic_swap_32 GPR:$ptr, GPR:$new))]>;
4154 def ATOMIC_CMP_SWAP_I8 : PseudoInst<
4155 (outs GPR:$dst), (ins GPR:$ptr, GPR:$old, GPR:$new), NoItinerary,
4156 [(set GPR:$dst, (atomic_cmp_swap_8 GPR:$ptr, GPR:$old, GPR:$new))]>;
4157 def ATOMIC_CMP_SWAP_I16 : PseudoInst<
4158 (outs GPR:$dst), (ins GPR:$ptr, GPR:$old, GPR:$new), NoItinerary,
4159 [(set GPR:$dst, (atomic_cmp_swap_16 GPR:$ptr, GPR:$old, GPR:$new))]>;
4160 def ATOMIC_CMP_SWAP_I32 : PseudoInst<
4161 (outs GPR:$dst), (ins GPR:$ptr, GPR:$old, GPR:$new), NoItinerary,
4162 [(set GPR:$dst, (atomic_cmp_swap_32 GPR:$ptr, GPR:$old, GPR:$new))]>;
4166 let mayLoad = 1 in {
4167 def LDREXB : AIldrex<0b10, (outs GPR:$Rt), (ins addr_offset_none:$addr),
4169 "ldrexb", "\t$Rt, $addr", []>;
4170 def LDREXH : AIldrex<0b11, (outs GPR:$Rt), (ins addr_offset_none:$addr),
4171 NoItinerary, "ldrexh", "\t$Rt, $addr", []>;
4172 def LDREX : AIldrex<0b00, (outs GPR:$Rt), (ins addr_offset_none:$addr),
4173 NoItinerary, "ldrex", "\t$Rt, $addr", []>;
4174 let hasExtraDefRegAllocReq = 1 in
4175 def LDREXD: AIldrex<0b01, (outs GPR:$Rt, GPR:$Rt2),(ins addr_offset_none:$addr),
4176 NoItinerary, "ldrexd", "\t$Rt, $Rt2, $addr", []> {
4177 let DecoderMethod = "DecodeDoubleRegLoad";
4181 let mayStore = 1, Constraints = "@earlyclobber $Rd" in {
4182 def STREXB: AIstrex<0b10, (outs GPR:$Rd), (ins GPR:$Rt, addr_offset_none:$addr),
4183 NoItinerary, "strexb", "\t$Rd, $Rt, $addr", []>;
4184 def STREXH: AIstrex<0b11, (outs GPR:$Rd), (ins GPR:$Rt, addr_offset_none:$addr),
4185 NoItinerary, "strexh", "\t$Rd, $Rt, $addr", []>;
4186 def STREX : AIstrex<0b00, (outs GPR:$Rd), (ins GPR:$Rt, addr_offset_none:$addr),
4187 NoItinerary, "strex", "\t$Rd, $Rt, $addr", []>;
4188 let hasExtraSrcRegAllocReq = 1 in
4189 def STREXD : AIstrex<0b01, (outs GPR:$Rd),
4190 (ins GPR:$Rt, GPR:$Rt2, addr_offset_none:$addr),
4191 NoItinerary, "strexd", "\t$Rd, $Rt, $Rt2, $addr", []> {
4192 let DecoderMethod = "DecodeDoubleRegStore";
4197 def CLREX : AXI<(outs), (ins), MiscFrm, NoItinerary, "clrex", []>,
4198 Requires<[IsARM, HasV7]> {
4199 let Inst{31-0} = 0b11110101011111111111000000011111;
4202 // SWP/SWPB are deprecated in V6/V7.
4203 let mayLoad = 1, mayStore = 1 in {
4204 def SWP : AIswp<0, (outs GPRnopc:$Rt),
4205 (ins GPRnopc:$Rt2, addr_offset_none:$addr), "swp", []>;
4206 def SWPB: AIswp<1, (outs GPRnopc:$Rt),
4207 (ins GPRnopc:$Rt2, addr_offset_none:$addr), "swpb", []>;
4210 //===----------------------------------------------------------------------===//
4211 // Coprocessor Instructions.
4214 def CDP : ABI<0b1110, (outs), (ins p_imm:$cop, imm0_15:$opc1,
4215 c_imm:$CRd, c_imm:$CRn, c_imm:$CRm, imm0_7:$opc2),
4216 NoItinerary, "cdp", "\t$cop, $opc1, $CRd, $CRn, $CRm, $opc2",
4217 [(int_arm_cdp imm:$cop, imm:$opc1, imm:$CRd, imm:$CRn,
4218 imm:$CRm, imm:$opc2)]> {
4226 let Inst{3-0} = CRm;
4228 let Inst{7-5} = opc2;
4229 let Inst{11-8} = cop;
4230 let Inst{15-12} = CRd;
4231 let Inst{19-16} = CRn;
4232 let Inst{23-20} = opc1;
4235 def CDP2 : ABXI<0b1110, (outs), (ins pf_imm:$cop, imm0_15:$opc1,
4236 c_imm:$CRd, c_imm:$CRn, c_imm:$CRm, imm0_7:$opc2),
4237 NoItinerary, "cdp2\t$cop, $opc1, $CRd, $CRn, $CRm, $opc2",
4238 [(int_arm_cdp2 imm:$cop, imm:$opc1, imm:$CRd, imm:$CRn,
4239 imm:$CRm, imm:$opc2)]> {
4240 let Inst{31-28} = 0b1111;
4248 let Inst{3-0} = CRm;
4250 let Inst{7-5} = opc2;
4251 let Inst{11-8} = cop;
4252 let Inst{15-12} = CRd;
4253 let Inst{19-16} = CRn;
4254 let Inst{23-20} = opc1;
4257 class ACI<dag oops, dag iops, string opc, string asm,
4258 IndexMode im = IndexModeNone>
4259 : I<oops, iops, AddrModeNone, 4, im, BrFrm, NoItinerary,
4261 let Inst{27-25} = 0b110;
4263 class ACInoP<dag oops, dag iops, string opc, string asm,
4264 IndexMode im = IndexModeNone>
4265 : InoP<oops, iops, AddrModeNone, 4, im, BrFrm, NoItinerary,
4267 let Inst{31-28} = 0b1111;
4268 let Inst{27-25} = 0b110;
4270 multiclass LdStCop<bit load, bit Dbit, string asm> {
4271 def _OFFSET : ACI<(outs), (ins p_imm:$cop, c_imm:$CRd, addrmode5:$addr),
4272 asm, "\t$cop, $CRd, $addr"> {
4276 let Inst{24} = 1; // P = 1
4277 let Inst{23} = addr{8};
4278 let Inst{22} = Dbit;
4279 let Inst{21} = 0; // W = 0
4280 let Inst{20} = load;
4281 let Inst{19-16} = addr{12-9};
4282 let Inst{15-12} = CRd;
4283 let Inst{11-8} = cop;
4284 let Inst{7-0} = addr{7-0};
4285 let DecoderMethod = "DecodeCopMemInstruction";
4287 def _PRE : ACI<(outs), (ins p_imm:$cop, c_imm:$CRd, addrmode5:$addr),
4288 asm, "\t$cop, $CRd, $addr!", IndexModePre> {
4292 let Inst{24} = 1; // P = 1
4293 let Inst{23} = addr{8};
4294 let Inst{22} = Dbit;
4295 let Inst{21} = 1; // W = 1
4296 let Inst{20} = load;
4297 let Inst{19-16} = addr{12-9};
4298 let Inst{15-12} = CRd;
4299 let Inst{11-8} = cop;
4300 let Inst{7-0} = addr{7-0};
4301 let DecoderMethod = "DecodeCopMemInstruction";
4303 def _POST: ACI<(outs), (ins p_imm:$cop, c_imm:$CRd, addr_offset_none:$addr,
4304 postidx_imm8s4:$offset),
4305 asm, "\t$cop, $CRd, $addr, $offset", IndexModePost> {
4310 let Inst{24} = 0; // P = 0
4311 let Inst{23} = offset{8};
4312 let Inst{22} = Dbit;
4313 let Inst{21} = 1; // W = 1
4314 let Inst{20} = load;
4315 let Inst{19-16} = addr;
4316 let Inst{15-12} = CRd;
4317 let Inst{11-8} = cop;
4318 let Inst{7-0} = offset{7-0};
4319 let DecoderMethod = "DecodeCopMemInstruction";
4321 def _OPTION : ACI<(outs),
4322 (ins p_imm:$cop, c_imm:$CRd, addr_offset_none:$addr,
4323 coproc_option_imm:$option),
4324 asm, "\t$cop, $CRd, $addr, $option"> {
4329 let Inst{24} = 0; // P = 0
4330 let Inst{23} = 1; // U = 1
4331 let Inst{22} = Dbit;
4332 let Inst{21} = 0; // W = 0
4333 let Inst{20} = load;
4334 let Inst{19-16} = addr;
4335 let Inst{15-12} = CRd;
4336 let Inst{11-8} = cop;
4337 let Inst{7-0} = option;
4338 let DecoderMethod = "DecodeCopMemInstruction";
4341 multiclass LdSt2Cop<bit load, bit Dbit, string asm> {
4342 def _OFFSET : ACInoP<(outs), (ins p_imm:$cop, c_imm:$CRd, addrmode5:$addr),
4343 asm, "\t$cop, $CRd, $addr"> {
4347 let Inst{24} = 1; // P = 1
4348 let Inst{23} = addr{8};
4349 let Inst{22} = Dbit;
4350 let Inst{21} = 0; // W = 0
4351 let Inst{20} = load;
4352 let Inst{19-16} = addr{12-9};
4353 let Inst{15-12} = CRd;
4354 let Inst{11-8} = cop;
4355 let Inst{7-0} = addr{7-0};
4356 let DecoderMethod = "DecodeCopMemInstruction";
4358 def _PRE : ACInoP<(outs), (ins p_imm:$cop, c_imm:$CRd, addrmode5:$addr),
4359 asm, "\t$cop, $CRd, $addr!", IndexModePre> {
4363 let Inst{24} = 1; // P = 1
4364 let Inst{23} = addr{8};
4365 let Inst{22} = Dbit;
4366 let Inst{21} = 1; // W = 1
4367 let Inst{20} = load;
4368 let Inst{19-16} = addr{12-9};
4369 let Inst{15-12} = CRd;
4370 let Inst{11-8} = cop;
4371 let Inst{7-0} = addr{7-0};
4372 let DecoderMethod = "DecodeCopMemInstruction";
4374 def _POST: ACInoP<(outs), (ins p_imm:$cop, c_imm:$CRd, addr_offset_none:$addr,
4375 postidx_imm8s4:$offset),
4376 asm, "\t$cop, $CRd, $addr, $offset", IndexModePost> {
4381 let Inst{24} = 0; // P = 0
4382 let Inst{23} = offset{8};
4383 let Inst{22} = Dbit;
4384 let Inst{21} = 1; // W = 1
4385 let Inst{20} = load;
4386 let Inst{19-16} = addr;
4387 let Inst{15-12} = CRd;
4388 let Inst{11-8} = cop;
4389 let Inst{7-0} = offset{7-0};
4390 let DecoderMethod = "DecodeCopMemInstruction";
4392 def _OPTION : ACInoP<(outs),
4393 (ins p_imm:$cop, c_imm:$CRd, addr_offset_none:$addr,
4394 coproc_option_imm:$option),
4395 asm, "\t$cop, $CRd, $addr, $option"> {
4400 let Inst{24} = 0; // P = 0
4401 let Inst{23} = 1; // U = 1
4402 let Inst{22} = Dbit;
4403 let Inst{21} = 0; // W = 0
4404 let Inst{20} = load;
4405 let Inst{19-16} = addr;
4406 let Inst{15-12} = CRd;
4407 let Inst{11-8} = cop;
4408 let Inst{7-0} = option;
4409 let DecoderMethod = "DecodeCopMemInstruction";
4413 defm LDC : LdStCop <1, 0, "ldc">;
4414 defm LDCL : LdStCop <1, 1, "ldcl">;
4415 defm STC : LdStCop <0, 0, "stc">;
4416 defm STCL : LdStCop <0, 1, "stcl">;
4417 defm LDC2 : LdSt2Cop<1, 0, "ldc2">;
4418 defm LDC2L : LdSt2Cop<1, 1, "ldc2l">;
4419 defm STC2 : LdSt2Cop<0, 0, "stc2">;
4420 defm STC2L : LdSt2Cop<0, 1, "stc2l">;
4422 //===----------------------------------------------------------------------===//
4423 // Move between coprocessor and ARM core register.
4426 class MovRCopro<string opc, bit direction, dag oops, dag iops,
4428 : ABI<0b1110, oops, iops, NoItinerary, opc,
4429 "\t$cop, $opc1, $Rt, $CRn, $CRm, $opc2", pattern> {
4430 let Inst{20} = direction;
4440 let Inst{15-12} = Rt;
4441 let Inst{11-8} = cop;
4442 let Inst{23-21} = opc1;
4443 let Inst{7-5} = opc2;
4444 let Inst{3-0} = CRm;
4445 let Inst{19-16} = CRn;
4448 def MCR : MovRCopro<"mcr", 0 /* from ARM core register to coprocessor */,
4450 (ins p_imm:$cop, imm0_7:$opc1, GPR:$Rt, c_imm:$CRn,
4451 c_imm:$CRm, imm0_7:$opc2),
4452 [(int_arm_mcr imm:$cop, imm:$opc1, GPR:$Rt, imm:$CRn,
4453 imm:$CRm, imm:$opc2)]>;
4454 def : ARMInstAlias<"mcr${p} $cop, $opc1, $Rt, $CRn, $CRm",
4455 (MCR p_imm:$cop, imm0_7:$opc1, GPR:$Rt, c_imm:$CRn,
4456 c_imm:$CRm, 0, pred:$p)>;
4457 def MRC : MovRCopro<"mrc", 1 /* from coprocessor to ARM core register */,
4459 (ins p_imm:$cop, imm0_7:$opc1, c_imm:$CRn, c_imm:$CRm,
4461 def : ARMInstAlias<"mrc${p} $cop, $opc1, $Rt, $CRn, $CRm",
4462 (MRC GPR:$Rt, p_imm:$cop, imm0_7:$opc1, c_imm:$CRn,
4463 c_imm:$CRm, 0, pred:$p)>;
4465 def : ARMPat<(int_arm_mrc imm:$cop, imm:$opc1, imm:$CRn, imm:$CRm, imm:$opc2),
4466 (MRC imm:$cop, imm:$opc1, imm:$CRn, imm:$CRm, imm:$opc2)>;
4468 class MovRCopro2<string opc, bit direction, dag oops, dag iops,
4470 : ABXI<0b1110, oops, iops, NoItinerary,
4471 !strconcat(opc, "\t$cop, $opc1, $Rt, $CRn, $CRm, $opc2"), pattern> {
4472 let Inst{31-28} = 0b1111;
4473 let Inst{20} = direction;
4483 let Inst{15-12} = Rt;
4484 let Inst{11-8} = cop;
4485 let Inst{23-21} = opc1;
4486 let Inst{7-5} = opc2;
4487 let Inst{3-0} = CRm;
4488 let Inst{19-16} = CRn;
4491 def MCR2 : MovRCopro2<"mcr2", 0 /* from ARM core register to coprocessor */,
4493 (ins p_imm:$cop, imm0_7:$opc1, GPR:$Rt, c_imm:$CRn,
4494 c_imm:$CRm, imm0_7:$opc2),
4495 [(int_arm_mcr2 imm:$cop, imm:$opc1, GPR:$Rt, imm:$CRn,
4496 imm:$CRm, imm:$opc2)]>;
4497 def : ARMInstAlias<"mcr2$ $cop, $opc1, $Rt, $CRn, $CRm",
4498 (MCR2 p_imm:$cop, imm0_7:$opc1, GPR:$Rt, c_imm:$CRn,
4500 def MRC2 : MovRCopro2<"mrc2", 1 /* from coprocessor to ARM core register */,
4502 (ins p_imm:$cop, imm0_7:$opc1, c_imm:$CRn, c_imm:$CRm,
4504 def : ARMInstAlias<"mrc2$ $cop, $opc1, $Rt, $CRn, $CRm",
4505 (MRC2 GPR:$Rt, p_imm:$cop, imm0_7:$opc1, c_imm:$CRn,
4508 def : ARMV5TPat<(int_arm_mrc2 imm:$cop, imm:$opc1, imm:$CRn,
4509 imm:$CRm, imm:$opc2),
4510 (MRC2 imm:$cop, imm:$opc1, imm:$CRn, imm:$CRm, imm:$opc2)>;
4512 class MovRRCopro<string opc, bit direction, list<dag> pattern = []>
4513 : ABI<0b1100, (outs), (ins p_imm:$cop, imm0_15:$opc1,
4514 GPRnopc:$Rt, GPRnopc:$Rt2, c_imm:$CRm),
4515 NoItinerary, opc, "\t$cop, $opc1, $Rt, $Rt2, $CRm", pattern> {
4516 let Inst{23-21} = 0b010;
4517 let Inst{20} = direction;
4525 let Inst{15-12} = Rt;
4526 let Inst{19-16} = Rt2;
4527 let Inst{11-8} = cop;
4528 let Inst{7-4} = opc1;
4529 let Inst{3-0} = CRm;
4532 def MCRR : MovRRCopro<"mcrr", 0 /* from ARM core register to coprocessor */,
4533 [(int_arm_mcrr imm:$cop, imm:$opc1, GPRnopc:$Rt,
4534 GPRnopc:$Rt2, imm:$CRm)]>;
4535 def MRRC : MovRRCopro<"mrrc", 1 /* from coprocessor to ARM core register */>;
4537 class MovRRCopro2<string opc, bit direction, list<dag> pattern = []>
4538 : ABXI<0b1100, (outs), (ins p_imm:$cop, imm0_15:$opc1,
4539 GPRnopc:$Rt, GPRnopc:$Rt2, c_imm:$CRm), NoItinerary,
4540 !strconcat(opc, "\t$cop, $opc1, $Rt, $Rt2, $CRm"), pattern> {
4541 let Inst{31-28} = 0b1111;
4542 let Inst{23-21} = 0b010;
4543 let Inst{20} = direction;
4551 let Inst{15-12} = Rt;
4552 let Inst{19-16} = Rt2;
4553 let Inst{11-8} = cop;
4554 let Inst{7-4} = opc1;
4555 let Inst{3-0} = CRm;
4557 let DecoderMethod = "DecodeMRRC2";
4560 def MCRR2 : MovRRCopro2<"mcrr2", 0 /* from ARM core register to coprocessor */,
4561 [(int_arm_mcrr2 imm:$cop, imm:$opc1, GPRnopc:$Rt,
4562 GPRnopc:$Rt2, imm:$CRm)]>;
4563 def MRRC2 : MovRRCopro2<"mrrc2", 1 /* from coprocessor to ARM core register */>;
4565 //===----------------------------------------------------------------------===//
4566 // Move between special register and ARM core register
4569 // Move to ARM core register from Special Register
4570 def MRS : ABI<0b0001, (outs GPRnopc:$Rd), (ins), NoItinerary,
4571 "mrs", "\t$Rd, apsr", []> {
4573 let Inst{23-16} = 0b00001111;
4574 let Unpredictable{19-17} = 0b111;
4576 let Inst{15-12} = Rd;
4578 let Inst{11-0} = 0b000000000000;
4579 let Unpredictable{11-0} = 0b110100001111;
4582 def : InstAlias<"mrs${p} $Rd, cpsr", (MRS GPRnopc:$Rd, pred:$p)>,
4585 // The MRSsys instruction is the MRS instruction from the ARM ARM,
4586 // section B9.3.9, with the R bit set to 1.
4587 def MRSsys : ABI<0b0001, (outs GPRnopc:$Rd), (ins), NoItinerary,
4588 "mrs", "\t$Rd, spsr", []> {
4590 let Inst{23-16} = 0b01001111;
4591 let Unpredictable{19-16} = 0b1111;
4593 let Inst{15-12} = Rd;
4595 let Inst{11-0} = 0b000000000000;
4596 let Unpredictable{11-0} = 0b110100001111;
4599 // Move from ARM core register to Special Register
4601 // No need to have both system and application versions, the encodings are the
4602 // same and the assembly parser has no way to distinguish between them. The mask
4603 // operand contains the special register (R Bit) in bit 4 and bits 3-0 contains
4604 // the mask with the fields to be accessed in the special register.
4605 def MSR : ABI<0b0001, (outs), (ins msr_mask:$mask, GPR:$Rn), NoItinerary,
4606 "msr", "\t$mask, $Rn", []> {
4611 let Inst{22} = mask{4}; // R bit
4612 let Inst{21-20} = 0b10;
4613 let Inst{19-16} = mask{3-0};
4614 let Inst{15-12} = 0b1111;
4615 let Inst{11-4} = 0b00000000;
4619 def MSRi : ABI<0b0011, (outs), (ins msr_mask:$mask, so_imm:$a), NoItinerary,
4620 "msr", "\t$mask, $a", []> {
4625 let Inst{22} = mask{4}; // R bit
4626 let Inst{21-20} = 0b10;
4627 let Inst{19-16} = mask{3-0};
4628 let Inst{15-12} = 0b1111;
4632 //===----------------------------------------------------------------------===//
4636 // __aeabi_read_tp preserves the registers r1-r3.
4637 // This is a pseudo inst so that we can get the encoding right,
4638 // complete with fixup for the aeabi_read_tp function.
4640 Defs = [R0, R12, LR, CPSR], Uses = [SP] in {
4641 def TPsoft : PseudoInst<(outs), (ins), IIC_Br,
4642 [(set R0, ARMthread_pointer)]>;
4645 //===----------------------------------------------------------------------===//
4646 // SJLJ Exception handling intrinsics
4647 // eh_sjlj_setjmp() is an instruction sequence to store the return
4648 // address and save #0 in R0 for the non-longjmp case.
4649 // Since by its nature we may be coming from some other function to get
4650 // here, and we're using the stack frame for the containing function to
4651 // save/restore registers, we can't keep anything live in regs across
4652 // the eh_sjlj_setjmp(), else it will almost certainly have been tromped upon
4653 // when we get here from a longjmp(). We force everything out of registers
4654 // except for our own input by listing the relevant registers in Defs. By
4655 // doing so, we also cause the prologue/epilogue code to actively preserve
4656 // all of the callee-saved resgisters, which is exactly what we want.
4657 // A constant value is passed in $val, and we use the location as a scratch.
4659 // These are pseudo-instructions and are lowered to individual MC-insts, so
4660 // no encoding information is necessary.
4662 [ R0, R1, R2, R3, R4, R5, R6, R7, R8, R9, R10, R11, R12, LR, CPSR,
4663 Q0, Q1, Q2, Q3, Q4, Q5, Q6, Q7, Q8, Q9, Q10, Q11, Q12, Q13, Q14, Q15 ],
4664 hasSideEffects = 1, isBarrier = 1, usesCustomInserter = 1 in {
4665 def Int_eh_sjlj_setjmp : PseudoInst<(outs), (ins GPR:$src, GPR:$val),
4667 [(set R0, (ARMeh_sjlj_setjmp GPR:$src, GPR:$val))]>,
4668 Requires<[IsARM, HasVFP2]>;
4672 [ R0, R1, R2, R3, R4, R5, R6, R7, R8, R9, R10, R11, R12, LR, CPSR ],
4673 hasSideEffects = 1, isBarrier = 1, usesCustomInserter = 1 in {
4674 def Int_eh_sjlj_setjmp_nofp : PseudoInst<(outs), (ins GPR:$src, GPR:$val),
4676 [(set R0, (ARMeh_sjlj_setjmp GPR:$src, GPR:$val))]>,
4677 Requires<[IsARM, NoVFP]>;
4680 // FIXME: Non-IOS version(s)
4681 let isBarrier = 1, hasSideEffects = 1, isTerminator = 1,
4682 Defs = [ R7, LR, SP ] in {
4683 def Int_eh_sjlj_longjmp : PseudoInst<(outs), (ins GPR:$src, GPR:$scratch),
4685 [(ARMeh_sjlj_longjmp GPR:$src, GPR:$scratch)]>,
4686 Requires<[IsARM, IsIOS]>;
4689 // eh.sjlj.dispatchsetup pseudo-instructions.
4690 // These pseudos are used for both ARM and Thumb2. Any differences are
4691 // handled when the pseudo is expanded (which happens before any passes
4692 // that need the instruction size).
4694 [ R0, R1, R2, R3, R4, R5, R6, R7, R8, R9, R10, R11, R12, LR, CPSR,
4695 Q0, Q1, Q2, Q3, Q4, Q5, Q6, Q7, Q8, Q9, Q10, Q11, Q12, Q13, Q14, Q15 ],
4697 def Int_eh_sjlj_dispatchsetup : PseudoInst<(outs), (ins), NoItinerary, []>;
4700 [ R0, R1, R2, R3, R4, R5, R6, R7, R8, R9, R10, R11, R12, LR, CPSR ],
4702 def Int_eh_sjlj_dispatchsetup_nofp : PseudoInst<(outs), (ins), NoItinerary, []>;
4705 //===----------------------------------------------------------------------===//
4706 // Non-Instruction Patterns
4709 // ARMv4 indirect branch using (MOVr PC, dst)
4710 let isBranch = 1, isTerminator = 1, isBarrier = 1, isIndirectBranch = 1 in
4711 def MOVPCRX : ARMPseudoExpand<(outs), (ins GPR:$dst),
4712 4, IIC_Br, [(brind GPR:$dst)],
4713 (MOVr PC, GPR:$dst, (ops 14, zero_reg), zero_reg)>,
4714 Requires<[IsARM, NoV4T]>;
4716 // Large immediate handling.
4718 // 32-bit immediate using two piece so_imms or movw + movt.
4719 // This is a single pseudo instruction, the benefit is that it can be remat'd
4720 // as a single unit instead of having to handle reg inputs.
4721 // FIXME: Remove this when we can do generalized remat.
4722 let isReMaterializable = 1, isMoveImm = 1 in
4723 def MOVi32imm : PseudoInst<(outs GPR:$dst), (ins i32imm:$src), IIC_iMOVix2,
4724 [(set GPR:$dst, (arm_i32imm:$src))]>,
4727 // Pseudo instruction that combines movw + movt + add pc (if PIC).
4728 // It also makes it possible to rematerialize the instructions.
4729 // FIXME: Remove this when we can do generalized remat and when machine licm
4730 // can properly the instructions.
4731 let isReMaterializable = 1 in {
4732 def MOV_ga_pcrel : PseudoInst<(outs GPR:$dst), (ins i32imm:$addr),
4734 [(set GPR:$dst, (ARMWrapperPIC tglobaladdr:$addr))]>,
4735 Requires<[IsARM, UseMovt]>;
4737 def MOV_ga_dyn : PseudoInst<(outs GPR:$dst), (ins i32imm:$addr),
4739 [(set GPR:$dst, (ARMWrapperDYN tglobaladdr:$addr))]>,
4740 Requires<[IsARM, UseMovt]>;
4742 let AddedComplexity = 10 in
4743 def MOV_ga_pcrel_ldr : PseudoInst<(outs GPR:$dst), (ins i32imm:$addr),
4745 [(set GPR:$dst, (load (ARMWrapperPIC tglobaladdr:$addr)))]>,
4746 Requires<[IsARM, UseMovt]>;
4747 } // isReMaterializable
4749 // ConstantPool, GlobalAddress, and JumpTable
4750 def : ARMPat<(ARMWrapper tglobaladdr :$dst), (LEApcrel tglobaladdr :$dst)>,
4751 Requires<[IsARM, DontUseMovt]>;
4752 def : ARMPat<(ARMWrapper tconstpool :$dst), (LEApcrel tconstpool :$dst)>;
4753 def : ARMPat<(ARMWrapper tglobaladdr :$dst), (MOVi32imm tglobaladdr :$dst)>,
4754 Requires<[IsARM, UseMovt]>;
4755 def : ARMPat<(ARMWrapperJT tjumptable:$dst, imm:$id),
4756 (LEApcrelJT tjumptable:$dst, imm:$id)>;
4758 // TODO: add,sub,and, 3-instr forms?
4760 // Tail calls. These patterns also apply to Thumb mode.
4761 def : Pat<(ARMtcret tcGPR:$dst), (TCRETURNri tcGPR:$dst)>;
4762 def : Pat<(ARMtcret (i32 tglobaladdr:$dst)), (TCRETURNdi texternalsym:$dst)>;
4763 def : Pat<(ARMtcret (i32 texternalsym:$dst)), (TCRETURNdi texternalsym:$dst)>;
4766 def : ARMPat<(ARMcall texternalsym:$func), (BL texternalsym:$func)>;
4767 def : ARMPat<(ARMcall_nolink texternalsym:$func),
4768 (BMOVPCB_CALL texternalsym:$func)>;
4770 // zextload i1 -> zextload i8
4771 def : ARMPat<(zextloadi1 addrmode_imm12:$addr), (LDRBi12 addrmode_imm12:$addr)>;
4772 def : ARMPat<(zextloadi1 ldst_so_reg:$addr), (LDRBrs ldst_so_reg:$addr)>;
4774 // extload -> zextload
4775 def : ARMPat<(extloadi1 addrmode_imm12:$addr), (LDRBi12 addrmode_imm12:$addr)>;
4776 def : ARMPat<(extloadi1 ldst_so_reg:$addr), (LDRBrs ldst_so_reg:$addr)>;
4777 def : ARMPat<(extloadi8 addrmode_imm12:$addr), (LDRBi12 addrmode_imm12:$addr)>;
4778 def : ARMPat<(extloadi8 ldst_so_reg:$addr), (LDRBrs ldst_so_reg:$addr)>;
4780 def : ARMPat<(extloadi16 addrmode3:$addr), (LDRH addrmode3:$addr)>;
4782 def : ARMPat<(extloadi8 addrmodepc:$addr), (PICLDRB addrmodepc:$addr)>;
4783 def : ARMPat<(extloadi16 addrmodepc:$addr), (PICLDRH addrmodepc:$addr)>;
4786 def : ARMV5TEPat<(mul (sra (shl GPR:$a, (i32 16)), (i32 16)),
4787 (sra (shl GPR:$b, (i32 16)), (i32 16))),
4788 (SMULBB GPR:$a, GPR:$b)>;
4789 def : ARMV5TEPat<(mul sext_16_node:$a, sext_16_node:$b),
4790 (SMULBB GPR:$a, GPR:$b)>;
4791 def : ARMV5TEPat<(mul (sra (shl GPR:$a, (i32 16)), (i32 16)),
4792 (sra GPR:$b, (i32 16))),
4793 (SMULBT GPR:$a, GPR:$b)>;
4794 def : ARMV5TEPat<(mul sext_16_node:$a, (sra GPR:$b, (i32 16))),
4795 (SMULBT GPR:$a, GPR:$b)>;
4796 def : ARMV5TEPat<(mul (sra GPR:$a, (i32 16)),
4797 (sra (shl GPR:$b, (i32 16)), (i32 16))),
4798 (SMULTB GPR:$a, GPR:$b)>;
4799 def : ARMV5TEPat<(mul (sra GPR:$a, (i32 16)), sext_16_node:$b),
4800 (SMULTB GPR:$a, GPR:$b)>;
4801 def : ARMV5TEPat<(sra (mul GPR:$a, (sra (shl GPR:$b, (i32 16)), (i32 16))),
4803 (SMULWB GPR:$a, GPR:$b)>;
4804 def : ARMV5TEPat<(sra (mul GPR:$a, sext_16_node:$b), (i32 16)),
4805 (SMULWB GPR:$a, GPR:$b)>;
4807 def : ARMV5TEPat<(add GPR:$acc,
4808 (mul (sra (shl GPR:$a, (i32 16)), (i32 16)),
4809 (sra (shl GPR:$b, (i32 16)), (i32 16)))),
4810 (SMLABB GPR:$a, GPR:$b, GPR:$acc)>;
4811 def : ARMV5TEPat<(add GPR:$acc,
4812 (mul sext_16_node:$a, sext_16_node:$b)),
4813 (SMLABB GPR:$a, GPR:$b, GPR:$acc)>;
4814 def : ARMV5TEPat<(add GPR:$acc,
4815 (mul (sra (shl GPR:$a, (i32 16)), (i32 16)),
4816 (sra GPR:$b, (i32 16)))),
4817 (SMLABT GPR:$a, GPR:$b, GPR:$acc)>;
4818 def : ARMV5TEPat<(add GPR:$acc,
4819 (mul sext_16_node:$a, (sra GPR:$b, (i32 16)))),
4820 (SMLABT GPR:$a, GPR:$b, GPR:$acc)>;
4821 def : ARMV5TEPat<(add GPR:$acc,
4822 (mul (sra GPR:$a, (i32 16)),
4823 (sra (shl GPR:$b, (i32 16)), (i32 16)))),
4824 (SMLATB GPR:$a, GPR:$b, GPR:$acc)>;
4825 def : ARMV5TEPat<(add GPR:$acc,
4826 (mul (sra GPR:$a, (i32 16)), sext_16_node:$b)),
4827 (SMLATB GPR:$a, GPR:$b, GPR:$acc)>;
4828 def : ARMV5TEPat<(add GPR:$acc,
4829 (sra (mul GPR:$a, (sra (shl GPR:$b, (i32 16)), (i32 16))),
4831 (SMLAWB GPR:$a, GPR:$b, GPR:$acc)>;
4832 def : ARMV5TEPat<(add GPR:$acc,
4833 (sra (mul GPR:$a, sext_16_node:$b), (i32 16))),
4834 (SMLAWB GPR:$a, GPR:$b, GPR:$acc)>;
4837 // Pre-v7 uses MCR for synchronization barriers.
4838 def : ARMPat<(ARMMemBarrierMCR GPR:$zero), (MCR 15, 0, GPR:$zero, 7, 10, 5)>,
4839 Requires<[IsARM, HasV6]>;
4841 // SXT/UXT with no rotate
4842 let AddedComplexity = 16 in {
4843 def : ARMV6Pat<(and GPR:$Src, 0x000000FF), (UXTB GPR:$Src, 0)>;
4844 def : ARMV6Pat<(and GPR:$Src, 0x0000FFFF), (UXTH GPR:$Src, 0)>;
4845 def : ARMV6Pat<(and GPR:$Src, 0x00FF00FF), (UXTB16 GPR:$Src, 0)>;
4846 def : ARMV6Pat<(add GPR:$Rn, (and GPR:$Rm, 0x00FF)),
4847 (UXTAB GPR:$Rn, GPR:$Rm, 0)>;
4848 def : ARMV6Pat<(add GPR:$Rn, (and GPR:$Rm, 0xFFFF)),
4849 (UXTAH GPR:$Rn, GPR:$Rm, 0)>;
4852 def : ARMV6Pat<(sext_inreg GPR:$Src, i8), (SXTB GPR:$Src, 0)>;
4853 def : ARMV6Pat<(sext_inreg GPR:$Src, i16), (SXTH GPR:$Src, 0)>;
4855 def : ARMV6Pat<(add GPR:$Rn, (sext_inreg GPRnopc:$Rm, i8)),
4856 (SXTAB GPR:$Rn, GPRnopc:$Rm, 0)>;
4857 def : ARMV6Pat<(add GPR:$Rn, (sext_inreg GPRnopc:$Rm, i16)),
4858 (SXTAH GPR:$Rn, GPRnopc:$Rm, 0)>;
4860 // Atomic load/store patterns
4861 def : ARMPat<(atomic_load_8 ldst_so_reg:$src),
4862 (LDRBrs ldst_so_reg:$src)>;
4863 def : ARMPat<(atomic_load_8 addrmode_imm12:$src),
4864 (LDRBi12 addrmode_imm12:$src)>;
4865 def : ARMPat<(atomic_load_16 addrmode3:$src),
4866 (LDRH addrmode3:$src)>;
4867 def : ARMPat<(atomic_load_32 ldst_so_reg:$src),
4868 (LDRrs ldst_so_reg:$src)>;
4869 def : ARMPat<(atomic_load_32 addrmode_imm12:$src),
4870 (LDRi12 addrmode_imm12:$src)>;
4871 def : ARMPat<(atomic_store_8 ldst_so_reg:$ptr, GPR:$val),
4872 (STRBrs GPR:$val, ldst_so_reg:$ptr)>;
4873 def : ARMPat<(atomic_store_8 addrmode_imm12:$ptr, GPR:$val),
4874 (STRBi12 GPR:$val, addrmode_imm12:$ptr)>;
4875 def : ARMPat<(atomic_store_16 addrmode3:$ptr, GPR:$val),
4876 (STRH GPR:$val, addrmode3:$ptr)>;
4877 def : ARMPat<(atomic_store_32 ldst_so_reg:$ptr, GPR:$val),
4878 (STRrs GPR:$val, ldst_so_reg:$ptr)>;
4879 def : ARMPat<(atomic_store_32 addrmode_imm12:$ptr, GPR:$val),
4880 (STRi12 GPR:$val, addrmode_imm12:$ptr)>;
4883 //===----------------------------------------------------------------------===//
4887 include "ARMInstrThumb.td"
4889 //===----------------------------------------------------------------------===//
4893 include "ARMInstrThumb2.td"
4895 //===----------------------------------------------------------------------===//
4896 // Floating Point Support
4899 include "ARMInstrVFP.td"
4901 //===----------------------------------------------------------------------===//
4902 // Advanced SIMD (NEON) Support
4905 include "ARMInstrNEON.td"
4907 //===----------------------------------------------------------------------===//
4908 // Assembler aliases
4912 def : InstAlias<"dmb", (DMB 0xf)>, Requires<[IsARM, HasDB]>;
4913 def : InstAlias<"dsb", (DSB 0xf)>, Requires<[IsARM, HasDB]>;
4914 def : InstAlias<"isb", (ISB 0xf)>, Requires<[IsARM, HasDB]>;
4916 // System instructions
4917 def : MnemonicAlias<"swi", "svc">;
4919 // Load / Store Multiple
4920 def : MnemonicAlias<"ldmfd", "ldm">;
4921 def : MnemonicAlias<"ldmia", "ldm">;
4922 def : MnemonicAlias<"ldmea", "ldmdb">;
4923 def : MnemonicAlias<"stmfd", "stmdb">;
4924 def : MnemonicAlias<"stmia", "stm">;
4925 def : MnemonicAlias<"stmea", "stm">;
4927 // PKHBT/PKHTB with default shift amount. PKHTB is equivalent to PKHBT when the
4928 // shift amount is zero (i.e., unspecified).
4929 def : InstAlias<"pkhbt${p} $Rd, $Rn, $Rm",
4930 (PKHBT GPRnopc:$Rd, GPRnopc:$Rn, GPRnopc:$Rm, 0, pred:$p)>,
4931 Requires<[IsARM, HasV6]>;
4932 def : InstAlias<"pkhtb${p} $Rd, $Rn, $Rm",
4933 (PKHBT GPRnopc:$Rd, GPRnopc:$Rn, GPRnopc:$Rm, 0, pred:$p)>,
4934 Requires<[IsARM, HasV6]>;
4936 // PUSH/POP aliases for STM/LDM
4937 def : ARMInstAlias<"push${p} $regs", (STMDB_UPD SP, pred:$p, reglist:$regs)>;
4938 def : ARMInstAlias<"pop${p} $regs", (LDMIA_UPD SP, pred:$p, reglist:$regs)>;
4940 // SSAT/USAT optional shift operand.
4941 def : ARMInstAlias<"ssat${p} $Rd, $sat_imm, $Rn",
4942 (SSAT GPRnopc:$Rd, imm1_32:$sat_imm, GPRnopc:$Rn, 0, pred:$p)>;
4943 def : ARMInstAlias<"usat${p} $Rd, $sat_imm, $Rn",
4944 (USAT GPRnopc:$Rd, imm0_31:$sat_imm, GPRnopc:$Rn, 0, pred:$p)>;
4947 // Extend instruction optional rotate operand.
4948 def : ARMInstAlias<"sxtab${p} $Rd, $Rn, $Rm",
4949 (SXTAB GPRnopc:$Rd, GPR:$Rn, GPRnopc:$Rm, 0, pred:$p)>;
4950 def : ARMInstAlias<"sxtah${p} $Rd, $Rn, $Rm",
4951 (SXTAH GPRnopc:$Rd, GPR:$Rn, GPRnopc:$Rm, 0, pred:$p)>;
4952 def : ARMInstAlias<"sxtab16${p} $Rd, $Rn, $Rm",
4953 (SXTAB16 GPRnopc:$Rd, GPR:$Rn, GPRnopc:$Rm, 0, pred:$p)>;
4954 def : ARMInstAlias<"sxtb${p} $Rd, $Rm",
4955 (SXTB GPRnopc:$Rd, GPRnopc:$Rm, 0, pred:$p)>;
4956 def : ARMInstAlias<"sxtb16${p} $Rd, $Rm",
4957 (SXTB16 GPRnopc:$Rd, GPRnopc:$Rm, 0, pred:$p)>;
4958 def : ARMInstAlias<"sxth${p} $Rd, $Rm",
4959 (SXTH GPRnopc:$Rd, GPRnopc:$Rm, 0, pred:$p)>;
4961 def : ARMInstAlias<"uxtab${p} $Rd, $Rn, $Rm",
4962 (UXTAB GPRnopc:$Rd, GPR:$Rn, GPRnopc:$Rm, 0, pred:$p)>;
4963 def : ARMInstAlias<"uxtah${p} $Rd, $Rn, $Rm",
4964 (UXTAH GPRnopc:$Rd, GPR:$Rn, GPRnopc:$Rm, 0, pred:$p)>;
4965 def : ARMInstAlias<"uxtab16${p} $Rd, $Rn, $Rm",
4966 (UXTAB16 GPRnopc:$Rd, GPR:$Rn, GPRnopc:$Rm, 0, pred:$p)>;
4967 def : ARMInstAlias<"uxtb${p} $Rd, $Rm",
4968 (UXTB GPRnopc:$Rd, GPRnopc:$Rm, 0, pred:$p)>;
4969 def : ARMInstAlias<"uxtb16${p} $Rd, $Rm",
4970 (UXTB16 GPRnopc:$Rd, GPRnopc:$Rm, 0, pred:$p)>;
4971 def : ARMInstAlias<"uxth${p} $Rd, $Rm",
4972 (UXTH GPRnopc:$Rd, GPRnopc:$Rm, 0, pred:$p)>;
4976 def : MnemonicAlias<"rfefa", "rfeda">;
4977 def : MnemonicAlias<"rfeea", "rfedb">;
4978 def : MnemonicAlias<"rfefd", "rfeia">;
4979 def : MnemonicAlias<"rfeed", "rfeib">;
4980 def : MnemonicAlias<"rfe", "rfeia">;
4983 def : MnemonicAlias<"srsfa", "srsda">;
4984 def : MnemonicAlias<"srsea", "srsdb">;
4985 def : MnemonicAlias<"srsfd", "srsia">;
4986 def : MnemonicAlias<"srsed", "srsib">;
4987 def : MnemonicAlias<"srs", "srsia">;
4990 def : MnemonicAlias<"qsubaddx", "qsax">;
4992 def : MnemonicAlias<"saddsubx", "sasx">;
4993 // SHASX == SHADDSUBX
4994 def : MnemonicAlias<"shaddsubx", "shasx">;
4995 // SHSAX == SHSUBADDX
4996 def : MnemonicAlias<"shsubaddx", "shsax">;
4998 def : MnemonicAlias<"ssubaddx", "ssax">;
5000 def : MnemonicAlias<"uaddsubx", "uasx">;
5001 // UHASX == UHADDSUBX
5002 def : MnemonicAlias<"uhaddsubx", "uhasx">;
5003 // UHSAX == UHSUBADDX
5004 def : MnemonicAlias<"uhsubaddx", "uhsax">;
5005 // UQASX == UQADDSUBX
5006 def : MnemonicAlias<"uqaddsubx", "uqasx">;
5007 // UQSAX == UQSUBADDX
5008 def : MnemonicAlias<"uqsubaddx", "uqsax">;
5010 def : MnemonicAlias<"usubaddx", "usax">;
5012 // "mov Rd, so_imm_not" can be handled via "mvn" in assembly, just like
5014 def : ARMInstAlias<"mov${s}${p} $Rd, $imm",
5015 (MVNi rGPR:$Rd, so_imm_not:$imm, pred:$p, cc_out:$s)>;
5016 def : ARMInstAlias<"mvn${s}${p} $Rd, $imm",
5017 (MOVi rGPR:$Rd, so_imm_not:$imm, pred:$p, cc_out:$s)>;
5018 // Same for AND <--> BIC
5019 def : ARMInstAlias<"bic${s}${p} $Rd, $Rn, $imm",
5020 (ANDri rGPR:$Rd, rGPR:$Rn, so_imm_not:$imm,
5021 pred:$p, cc_out:$s)>;
5022 def : ARMInstAlias<"bic${s}${p} $Rdn, $imm",
5023 (ANDri rGPR:$Rdn, rGPR:$Rdn, so_imm_not:$imm,
5024 pred:$p, cc_out:$s)>;
5025 def : ARMInstAlias<"and${s}${p} $Rd, $Rn, $imm",
5026 (BICri rGPR:$Rd, rGPR:$Rn, so_imm_not:$imm,
5027 pred:$p, cc_out:$s)>;
5028 def : ARMInstAlias<"and${s}${p} $Rdn, $imm",
5029 (BICri rGPR:$Rdn, rGPR:$Rdn, so_imm_not:$imm,
5030 pred:$p, cc_out:$s)>;
5032 // Likewise, "add Rd, so_imm_neg" -> sub
5033 def : ARMInstAlias<"add${s}${p} $Rd, $Rn, $imm",
5034 (SUBri GPR:$Rd, GPR:$Rn, so_imm_neg:$imm, pred:$p, cc_out:$s)>;
5035 def : ARMInstAlias<"add${s}${p} $Rd, $imm",
5036 (SUBri GPR:$Rd, GPR:$Rd, so_imm_neg:$imm, pred:$p, cc_out:$s)>;
5037 // Same for CMP <--> CMN via so_imm_neg
5038 def : ARMInstAlias<"cmp${p} $Rd, $imm",
5039 (CMNzri rGPR:$Rd, so_imm_neg:$imm, pred:$p)>;
5040 def : ARMInstAlias<"cmn${p} $Rd, $imm",
5041 (CMPri rGPR:$Rd, so_imm_neg:$imm, pred:$p)>;
5043 // The shifter forms of the MOV instruction are aliased to the ASR, LSL,
5044 // LSR, ROR, and RRX instructions.
5045 // FIXME: We need C++ parser hooks to map the alias to the MOV
5046 // encoding. It seems we should be able to do that sort of thing
5047 // in tblgen, but it could get ugly.
5048 let TwoOperandAliasConstraint = "$Rm = $Rd" in {
5049 def ASRi : ARMAsmPseudo<"asr${s}${p} $Rd, $Rm, $imm",
5050 (ins GPR:$Rd, GPR:$Rm, imm0_32:$imm, pred:$p,
5052 def LSRi : ARMAsmPseudo<"lsr${s}${p} $Rd, $Rm, $imm",
5053 (ins GPR:$Rd, GPR:$Rm, imm0_32:$imm, pred:$p,
5055 def LSLi : ARMAsmPseudo<"lsl${s}${p} $Rd, $Rm, $imm",
5056 (ins GPR:$Rd, GPR:$Rm, imm0_31:$imm, pred:$p,
5058 def RORi : ARMAsmPseudo<"ror${s}${p} $Rd, $Rm, $imm",
5059 (ins GPR:$Rd, GPR:$Rm, imm0_31:$imm, pred:$p,
5062 def RRXi : ARMAsmPseudo<"rrx${s}${p} $Rd, $Rm",
5063 (ins GPRnopc:$Rd, GPRnopc:$Rm, pred:$p, cc_out:$s)>;
5064 let TwoOperandAliasConstraint = "$Rn = $Rd" in {
5065 def ASRr : ARMAsmPseudo<"asr${s}${p} $Rd, $Rn, $Rm",
5066 (ins GPRnopc:$Rd, GPRnopc:$Rn, GPRnopc:$Rm, pred:$p,
5068 def LSRr : ARMAsmPseudo<"lsr${s}${p} $Rd, $Rn, $Rm",
5069 (ins GPRnopc:$Rd, GPRnopc:$Rn, GPRnopc:$Rm, pred:$p,
5071 def LSLr : ARMAsmPseudo<"lsl${s}${p} $Rd, $Rn, $Rm",
5072 (ins GPRnopc:$Rd, GPRnopc:$Rn, GPRnopc:$Rm, pred:$p,
5074 def RORr : ARMAsmPseudo<"ror${s}${p} $Rd, $Rn, $Rm",
5075 (ins GPRnopc:$Rd, GPRnopc:$Rn, GPRnopc:$Rm, pred:$p,
5079 // "neg" is and alias for "rsb rd, rn, #0"
5080 def : ARMInstAlias<"neg${s}${p} $Rd, $Rm",
5081 (RSBri GPR:$Rd, GPR:$Rm, 0, pred:$p, cc_out:$s)>;
5083 // Pre-v6, 'mov r0, r0' was used as a NOP encoding.
5084 def : InstAlias<"nop${p}", (MOVr R0, R0, pred:$p, zero_reg)>,
5085 Requires<[IsARM, NoV6]>;
5087 // UMULL/SMULL are available on all arches, but the instruction definitions
5088 // need difference constraints pre-v6. Use these aliases for the assembly
5089 // parsing on pre-v6.
5090 def : InstAlias<"smull${s}${p} $RdLo, $RdHi, $Rn, $Rm",
5091 (SMULL GPR:$RdLo, GPR:$RdHi, GPR:$Rn, GPR:$Rm, pred:$p, cc_out:$s)>,
5092 Requires<[IsARM, NoV6]>;
5093 def : InstAlias<"umull${s}${p} $RdLo, $RdHi, $Rn, $Rm",
5094 (UMULL GPR:$RdLo, GPR:$RdHi, GPR:$Rn, GPR:$Rm, pred:$p, cc_out:$s)>,
5095 Requires<[IsARM, NoV6]>;
5097 // 'it' blocks in ARM mode just validate the predicates. The IT itself
5099 def ITasm : ARMAsmPseudo<"it$mask $cc", (ins it_pred:$cc, it_mask:$mask)>;