1 //===- ARMInstrInfo.td - Target Description for ARM Target -*- tablegen -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file describes the ARM instructions in TableGen format.
12 //===----------------------------------------------------------------------===//
14 //===----------------------------------------------------------------------===//
15 // ARM specific DAG Nodes.
19 def SDT_ARMCallSeqStart : SDCallSeqStart<[ SDTCisVT<0, i32> ]>;
20 def SDT_ARMCallSeqEnd : SDCallSeqEnd<[ SDTCisVT<0, i32>, SDTCisVT<1, i32> ]>;
22 def SDT_ARMSaveCallPC : SDTypeProfile<0, 1, []>;
24 def SDT_ARMcall : SDTypeProfile<0, -1, [SDTCisPtrTy<0>]>;
26 def SDT_ARMCMov : SDTypeProfile<1, 3,
27 [SDTCisSameAs<0, 1>, SDTCisSameAs<0, 2>,
30 def SDT_ARMBrcond : SDTypeProfile<0, 2,
31 [SDTCisVT<0, OtherVT>, SDTCisVT<1, i32>]>;
33 def SDT_ARMBrJT : SDTypeProfile<0, 3,
34 [SDTCisPtrTy<0>, SDTCisVT<1, i32>,
37 def SDT_ARMBr2JT : SDTypeProfile<0, 4,
38 [SDTCisPtrTy<0>, SDTCisVT<1, i32>,
39 SDTCisVT<2, i32>, SDTCisVT<3, i32>]>;
41 def SDT_ARMBCC_i64 : SDTypeProfile<0, 6,
43 SDTCisVT<1, i32>, SDTCisVT<2, i32>,
44 SDTCisVT<3, i32>, SDTCisVT<4, i32>,
45 SDTCisVT<5, OtherVT>]>;
47 def SDT_ARMAnd : SDTypeProfile<1, 2,
48 [SDTCisVT<0, i32>, SDTCisVT<1, i32>,
51 def SDT_ARMCmp : SDTypeProfile<0, 2, [SDTCisSameAs<0, 1>]>;
53 def SDT_ARMPICAdd : SDTypeProfile<1, 2, [SDTCisSameAs<0, 1>,
54 SDTCisPtrTy<1>, SDTCisVT<2, i32>]>;
56 def SDT_ARMThreadPointer : SDTypeProfile<1, 0, [SDTCisPtrTy<0>]>;
57 def SDT_ARMEH_SJLJ_Setjmp : SDTypeProfile<1, 2, [SDTCisInt<0>, SDTCisPtrTy<1>,
59 def SDT_ARMEH_SJLJ_Longjmp: SDTypeProfile<0, 2, [SDTCisPtrTy<0>, SDTCisInt<1>]>;
61 def SDT_ARMEH_SJLJ_DispatchSetup: SDTypeProfile<0, 0, []>;
63 def SDT_ARMMEMBARRIER : SDTypeProfile<0, 1, [SDTCisInt<0>]>;
65 def SDT_ARMTCRET : SDTypeProfile<0, 1, [SDTCisPtrTy<0>]>;
67 def SDT_ARMBFI : SDTypeProfile<1, 3, [SDTCisVT<0, i32>, SDTCisVT<1, i32>,
68 SDTCisVT<2, i32>, SDTCisVT<3, i32>]>;
71 def ARMWrapper : SDNode<"ARMISD::Wrapper", SDTIntUnaryOp>;
72 def ARMWrapperDYN : SDNode<"ARMISD::WrapperDYN", SDTIntUnaryOp>;
73 def ARMWrapperPIC : SDNode<"ARMISD::WrapperPIC", SDTIntUnaryOp>;
74 def ARMWrapperJT : SDNode<"ARMISD::WrapperJT", SDTIntBinOp>;
76 def ARMcallseq_start : SDNode<"ISD::CALLSEQ_START", SDT_ARMCallSeqStart,
77 [SDNPHasChain, SDNPOutGlue]>;
78 def ARMcallseq_end : SDNode<"ISD::CALLSEQ_END", SDT_ARMCallSeqEnd,
79 [SDNPHasChain, SDNPOptInGlue, SDNPOutGlue]>;
81 def ARMcall : SDNode<"ARMISD::CALL", SDT_ARMcall,
82 [SDNPHasChain, SDNPOptInGlue, SDNPOutGlue,
84 def ARMcall_pred : SDNode<"ARMISD::CALL_PRED", SDT_ARMcall,
85 [SDNPHasChain, SDNPOptInGlue, SDNPOutGlue,
87 def ARMcall_nolink : SDNode<"ARMISD::CALL_NOLINK", SDT_ARMcall,
88 [SDNPHasChain, SDNPOptInGlue, SDNPOutGlue,
91 def ARMretflag : SDNode<"ARMISD::RET_FLAG", SDTNone,
92 [SDNPHasChain, SDNPOptInGlue]>;
94 def ARMcmov : SDNode<"ARMISD::CMOV", SDT_ARMCMov,
97 def ARMbrcond : SDNode<"ARMISD::BRCOND", SDT_ARMBrcond,
98 [SDNPHasChain, SDNPInGlue, SDNPOutGlue]>;
100 def ARMbrjt : SDNode<"ARMISD::BR_JT", SDT_ARMBrJT,
102 def ARMbr2jt : SDNode<"ARMISD::BR2_JT", SDT_ARMBr2JT,
105 def ARMBcci64 : SDNode<"ARMISD::BCC_i64", SDT_ARMBCC_i64,
108 def ARMcmp : SDNode<"ARMISD::CMP", SDT_ARMCmp,
111 def ARMcmpZ : SDNode<"ARMISD::CMPZ", SDT_ARMCmp,
112 [SDNPOutGlue, SDNPCommutative]>;
114 def ARMpic_add : SDNode<"ARMISD::PIC_ADD", SDT_ARMPICAdd>;
116 def ARMsrl_flag : SDNode<"ARMISD::SRL_FLAG", SDTIntUnaryOp, [SDNPOutGlue]>;
117 def ARMsra_flag : SDNode<"ARMISD::SRA_FLAG", SDTIntUnaryOp, [SDNPOutGlue]>;
118 def ARMrrx : SDNode<"ARMISD::RRX" , SDTIntUnaryOp, [SDNPInGlue ]>;
120 def ARMthread_pointer: SDNode<"ARMISD::THREAD_POINTER", SDT_ARMThreadPointer>;
121 def ARMeh_sjlj_setjmp: SDNode<"ARMISD::EH_SJLJ_SETJMP",
122 SDT_ARMEH_SJLJ_Setjmp, [SDNPHasChain]>;
123 def ARMeh_sjlj_longjmp: SDNode<"ARMISD::EH_SJLJ_LONGJMP",
124 SDT_ARMEH_SJLJ_Longjmp, [SDNPHasChain]>;
125 def ARMeh_sjlj_dispatchsetup: SDNode<"ARMISD::EH_SJLJ_DISPATCHSETUP",
126 SDT_ARMEH_SJLJ_DispatchSetup, [SDNPHasChain]>;
129 def ARMMemBarrier : SDNode<"ARMISD::MEMBARRIER", SDT_ARMMEMBARRIER,
131 def ARMMemBarrierMCR : SDNode<"ARMISD::MEMBARRIER_MCR", SDT_ARMMEMBARRIER,
133 def ARMPreload : SDNode<"ARMISD::PRELOAD", SDTPrefetch,
134 [SDNPHasChain, SDNPMayLoad, SDNPMayStore]>;
136 def ARMrbit : SDNode<"ARMISD::RBIT", SDTIntUnaryOp>;
138 def ARMtcret : SDNode<"ARMISD::TC_RETURN", SDT_ARMTCRET,
139 [SDNPHasChain, SDNPOptInGlue, SDNPVariadic]>;
142 def ARMbfi : SDNode<"ARMISD::BFI", SDT_ARMBFI>;
144 //===----------------------------------------------------------------------===//
145 // ARM Instruction Predicate Definitions.
147 def HasV4T : Predicate<"Subtarget->hasV4TOps()">, AssemblerPredicate;
148 def NoV4T : Predicate<"!Subtarget->hasV4TOps()">;
149 def HasV5T : Predicate<"Subtarget->hasV5TOps()">;
150 def HasV5TE : Predicate<"Subtarget->hasV5TEOps()">, AssemblerPredicate;
151 def HasV6 : Predicate<"Subtarget->hasV6Ops()">, AssemblerPredicate;
152 def NoV6 : Predicate<"!Subtarget->hasV6Ops()">;
153 def HasV6T2 : Predicate<"Subtarget->hasV6T2Ops()">, AssemblerPredicate;
154 def NoV6T2 : Predicate<"!Subtarget->hasV6T2Ops()">;
155 def HasV7 : Predicate<"Subtarget->hasV7Ops()">, AssemblerPredicate;
156 def NoVFP : Predicate<"!Subtarget->hasVFP2()">;
157 def HasVFP2 : Predicate<"Subtarget->hasVFP2()">, AssemblerPredicate;
158 def HasVFP3 : Predicate<"Subtarget->hasVFP3()">, AssemblerPredicate;
159 def HasNEON : Predicate<"Subtarget->hasNEON()">, AssemblerPredicate;
160 def HasFP16 : Predicate<"Subtarget->hasFP16()">, AssemblerPredicate;
161 def HasDivide : Predicate<"Subtarget->hasDivide()">, AssemblerPredicate;
162 def HasT2ExtractPack : Predicate<"Subtarget->hasT2ExtractPack()">,
164 def HasDB : Predicate<"Subtarget->hasDataBarrier()">,
166 def HasMP : Predicate<"Subtarget->hasMPExtension()">,
168 def UseNEONForFP : Predicate<"Subtarget->useNEONForSinglePrecisionFP()">;
169 def DontUseNEONForFP : Predicate<"!Subtarget->useNEONForSinglePrecisionFP()">;
170 def IsThumb : Predicate<"Subtarget->isThumb()">, AssemblerPredicate;
171 def IsThumb1Only : Predicate<"Subtarget->isThumb1Only()">;
172 def IsThumb2 : Predicate<"Subtarget->isThumb2()">, AssemblerPredicate;
173 def IsARM : Predicate<"!Subtarget->isThumb()">, AssemblerPredicate;
174 def IsDarwin : Predicate<"Subtarget->isTargetDarwin()">;
175 def IsNotDarwin : Predicate<"!Subtarget->isTargetDarwin()">;
177 // FIXME: Eventually this will be just "hasV6T2Ops".
178 def UseMovt : Predicate<"Subtarget->useMovt()">;
179 def DontUseMovt : Predicate<"!Subtarget->useMovt()">;
180 def UseFPVMLx : Predicate<"Subtarget->useFPVMLx()">;
182 //===----------------------------------------------------------------------===//
183 // ARM Flag Definitions.
185 class RegConstraint<string C> {
186 string Constraints = C;
189 //===----------------------------------------------------------------------===//
190 // ARM specific transformation functions and pattern fragments.
193 // so_imm_neg_XFORM - Return a so_imm value packed into the format described for
194 // so_imm_neg def below.
195 def so_imm_neg_XFORM : SDNodeXForm<imm, [{
196 return CurDAG->getTargetConstant(-(int)N->getZExtValue(), MVT::i32);
199 // so_imm_not_XFORM - Return a so_imm value packed into the format described for
200 // so_imm_not def below.
201 def so_imm_not_XFORM : SDNodeXForm<imm, [{
202 return CurDAG->getTargetConstant(~(int)N->getZExtValue(), MVT::i32);
205 /// imm1_15 predicate - True if the 32-bit immediate is in the range [1,15].
206 def imm1_15 : ImmLeaf<i32, [{
207 return (int32_t)Imm >= 1 && (int32_t)Imm < 16;
210 /// imm16_31 predicate - True if the 32-bit immediate is in the range [16,31].
211 def imm16_31 : ImmLeaf<i32, [{
212 return (int32_t)Imm >= 16 && (int32_t)Imm < 32;
217 return ARM_AM::getSOImmVal(-(uint32_t)N->getZExtValue()) != -1;
218 }], so_imm_neg_XFORM>;
222 return ARM_AM::getSOImmVal(~(uint32_t)N->getZExtValue()) != -1;
223 }], so_imm_not_XFORM>;
225 // sext_16_node predicate - True if the SDNode is sign-extended 16 or more bits.
226 def sext_16_node : PatLeaf<(i32 GPR:$a), [{
227 return CurDAG->ComputeNumSignBits(SDValue(N,0)) >= 17;
230 /// Split a 32-bit immediate into two 16 bit parts.
231 def hi16 : SDNodeXForm<imm, [{
232 return CurDAG->getTargetConstant((uint32_t)N->getZExtValue() >> 16, MVT::i32);
235 def lo16AllZero : PatLeaf<(i32 imm), [{
236 // Returns true if all low 16-bits are 0.
237 return (((uint32_t)N->getZExtValue()) & 0xFFFFUL) == 0;
240 /// imm0_65535 predicate - True if the 32-bit immediate is in the range
242 def imm0_65535 : ImmLeaf<i32, [{
243 return Imm >= 0 && Imm < 65536;
246 class BinOpFrag<dag res> : PatFrag<(ops node:$LHS, node:$RHS), res>;
247 class UnOpFrag <dag res> : PatFrag<(ops node:$Src), res>;
249 /// adde and sube predicates - True based on whether the carry flag output
250 /// will be needed or not.
251 def adde_dead_carry :
252 PatFrag<(ops node:$LHS, node:$RHS), (adde node:$LHS, node:$RHS),
253 [{return !N->hasAnyUseOfValue(1);}]>;
254 def sube_dead_carry :
255 PatFrag<(ops node:$LHS, node:$RHS), (sube node:$LHS, node:$RHS),
256 [{return !N->hasAnyUseOfValue(1);}]>;
257 def adde_live_carry :
258 PatFrag<(ops node:$LHS, node:$RHS), (adde node:$LHS, node:$RHS),
259 [{return N->hasAnyUseOfValue(1);}]>;
260 def sube_live_carry :
261 PatFrag<(ops node:$LHS, node:$RHS), (sube node:$LHS, node:$RHS),
262 [{return N->hasAnyUseOfValue(1);}]>;
264 // An 'and' node with a single use.
265 def and_su : PatFrag<(ops node:$lhs, node:$rhs), (and node:$lhs, node:$rhs), [{
266 return N->hasOneUse();
269 // An 'xor' node with a single use.
270 def xor_su : PatFrag<(ops node:$lhs, node:$rhs), (xor node:$lhs, node:$rhs), [{
271 return N->hasOneUse();
274 // An 'fmul' node with a single use.
275 def fmul_su : PatFrag<(ops node:$lhs, node:$rhs), (fmul node:$lhs, node:$rhs),[{
276 return N->hasOneUse();
279 // An 'fadd' node which checks for single non-hazardous use.
280 def fadd_mlx : PatFrag<(ops node:$lhs, node:$rhs),(fadd node:$lhs, node:$rhs),[{
281 return hasNoVMLxHazardUse(N);
284 // An 'fsub' node which checks for single non-hazardous use.
285 def fsub_mlx : PatFrag<(ops node:$lhs, node:$rhs),(fsub node:$lhs, node:$rhs),[{
286 return hasNoVMLxHazardUse(N);
289 //===----------------------------------------------------------------------===//
290 // Operand Definitions.
294 // FIXME: rename brtarget to t2_brtarget
295 def brtarget : Operand<OtherVT> {
296 let EncoderMethod = "getBranchTargetOpValue";
299 // FIXME: get rid of this one?
300 def uncondbrtarget : Operand<OtherVT> {
301 let EncoderMethod = "getUnconditionalBranchTargetOpValue";
304 // Branch target for ARM. Handles conditional/unconditional
305 def br_target : Operand<OtherVT> {
306 let EncoderMethod = "getARMBranchTargetOpValue";
310 // FIXME: rename bltarget to t2_bl_target?
311 def bltarget : Operand<i32> {
312 // Encoded the same as branch targets.
313 let EncoderMethod = "getBranchTargetOpValue";
316 // Call target for ARM. Handles conditional/unconditional
317 // FIXME: rename bl_target to t2_bltarget?
318 def bl_target : Operand<i32> {
319 // Encoded the same as branch targets.
320 let EncoderMethod = "getARMBranchTargetOpValue";
324 // A list of registers separated by comma. Used by load/store multiple.
325 def RegListAsmOperand : AsmOperandClass {
326 let Name = "RegList";
327 let SuperClasses = [];
330 def DPRRegListAsmOperand : AsmOperandClass {
331 let Name = "DPRRegList";
332 let SuperClasses = [];
335 def SPRRegListAsmOperand : AsmOperandClass {
336 let Name = "SPRRegList";
337 let SuperClasses = [];
340 def reglist : Operand<i32> {
341 let EncoderMethod = "getRegisterListOpValue";
342 let ParserMatchClass = RegListAsmOperand;
343 let PrintMethod = "printRegisterList";
346 def dpr_reglist : Operand<i32> {
347 let EncoderMethod = "getRegisterListOpValue";
348 let ParserMatchClass = DPRRegListAsmOperand;
349 let PrintMethod = "printRegisterList";
352 def spr_reglist : Operand<i32> {
353 let EncoderMethod = "getRegisterListOpValue";
354 let ParserMatchClass = SPRRegListAsmOperand;
355 let PrintMethod = "printRegisterList";
358 // An operand for the CONSTPOOL_ENTRY pseudo-instruction.
359 def cpinst_operand : Operand<i32> {
360 let PrintMethod = "printCPInstOperand";
364 def pclabel : Operand<i32> {
365 let PrintMethod = "printPCLabel";
368 // ADR instruction labels.
369 def adrlabel : Operand<i32> {
370 let EncoderMethod = "getAdrLabelOpValue";
373 def neon_vcvt_imm32 : Operand<i32> {
374 let EncoderMethod = "getNEONVcvtImm32OpValue";
377 // rot_imm: An integer that encodes a rotate amount. Must be 8, 16, or 24.
378 def rot_imm : Operand<i32>, ImmLeaf<i32, [{
379 int32_t v = (int32_t)Imm;
380 return v == 8 || v == 16 || v == 24; }]> {
381 let EncoderMethod = "getRotImmOpValue";
384 def ShifterAsmOperand : AsmOperandClass {
385 let Name = "Shifter";
386 let SuperClasses = [];
389 // shift_imm: An integer that encodes a shift amount and the type of shift
390 // (currently either asr or lsl) using the same encoding used for the
391 // immediates in so_reg operands.
392 def shift_imm : Operand<i32> {
393 let PrintMethod = "printShiftImmOperand";
394 let ParserMatchClass = ShifterAsmOperand;
397 // shifter_operand operands: so_reg and so_imm.
398 def so_reg : Operand<i32>, // reg reg imm
399 ComplexPattern<i32, 3, "SelectShifterOperandReg",
400 [shl,srl,sra,rotr]> {
401 let EncoderMethod = "getSORegOpValue";
402 let PrintMethod = "printSORegOperand";
403 let MIOperandInfo = (ops GPR, GPR, shift_imm);
405 def shift_so_reg : Operand<i32>, // reg reg imm
406 ComplexPattern<i32, 3, "SelectShiftShifterOperandReg",
407 [shl,srl,sra,rotr]> {
408 let EncoderMethod = "getSORegOpValue";
409 let PrintMethod = "printSORegOperand";
410 let MIOperandInfo = (ops GPR, GPR, shift_imm);
413 // so_imm - Match a 32-bit shifter_operand immediate operand, which is an
414 // 8-bit immediate rotated by an arbitrary number of bits.
415 def so_imm : Operand<i32>, PatLeaf<(imm), [{ return Pred_so_imm(N); }]> {
416 let EncoderMethod = "getSOImmOpValue";
417 let PrintMethod = "printSOImmOperand";
420 // Break so_imm's up into two pieces. This handles immediates with up to 16
421 // bits set in them. This uses so_imm2part to match and so_imm2part_[12] to
422 // get the first/second pieces.
423 def so_imm2part : PatLeaf<(imm), [{
424 return ARM_AM::isSOImmTwoPartVal((unsigned)N->getZExtValue());
427 /// arm_i32imm - True for +V6T2, or true only if so_imm2part is true.
429 def arm_i32imm : PatLeaf<(imm), [{
430 if (Subtarget->hasV6T2Ops())
432 return ARM_AM::isSOImmTwoPartVal((unsigned)N->getZExtValue());
435 /// imm0_31 predicate - True if the 32-bit immediate is in the range [0,31].
436 def imm0_31 : Operand<i32>, ImmLeaf<i32, [{
437 return Imm >= 0 && Imm < 32;
440 /// imm0_31_m1 - Matches and prints like imm0_31, but encodes as 'value - 1'.
441 def imm0_31_m1 : Operand<i32>, ImmLeaf<i32, [{
442 return Imm >= 0 && Imm < 32;
444 let EncoderMethod = "getImmMinusOneOpValue";
447 // i32imm_hilo16 - For movt/movw - sets the MC Encoder method.
448 // The imm is split into imm{15-12}, imm{11-0}
450 def i32imm_hilo16 : Operand<i32> {
451 let EncoderMethod = "getHiLo16ImmOpValue";
454 /// bf_inv_mask_imm predicate - An AND mask to clear an arbitrary width bitfield
456 def bf_inv_mask_imm : Operand<i32>,
458 return ARM::isBitFieldInvertedMask(N->getZExtValue());
460 let EncoderMethod = "getBitfieldInvertedMaskOpValue";
461 let PrintMethod = "printBitfieldInvMaskImmOperand";
464 /// lsb_pos_imm - position of the lsb bit, used by BFI4p and t2BFI4p
465 def lsb_pos_imm : Operand<i32>, ImmLeaf<i32, [{
466 return isInt<5>(Imm);
469 /// width_imm - number of bits to be copied, used by BFI4p and t2BFI4p
470 def width_imm : Operand<i32>, ImmLeaf<i32, [{
471 return Imm > 0 && Imm <= 32;
473 let EncoderMethod = "getMsbOpValue";
476 // Define ARM specific addressing modes.
478 def MemMode2AsmOperand : AsmOperandClass {
479 let Name = "MemMode2";
480 let SuperClasses = [];
481 let ParserMethod = "tryParseMemMode2Operand";
484 def MemMode3AsmOperand : AsmOperandClass {
485 let Name = "MemMode3";
486 let SuperClasses = [];
487 let ParserMethod = "tryParseMemMode3Operand";
490 // addrmode_imm12 := reg +/- imm12
492 def addrmode_imm12 : Operand<i32>,
493 ComplexPattern<i32, 2, "SelectAddrModeImm12", []> {
494 // 12-bit immediate operand. Note that instructions using this encode
495 // #0 and #-0 differently. We flag #-0 as the magic value INT32_MIN. All other
496 // immediate values are as normal.
498 let EncoderMethod = "getAddrModeImm12OpValue";
499 let PrintMethod = "printAddrModeImm12Operand";
500 let MIOperandInfo = (ops GPR:$base, i32imm:$offsimm);
502 // ldst_so_reg := reg +/- reg shop imm
504 def ldst_so_reg : Operand<i32>,
505 ComplexPattern<i32, 3, "SelectLdStSOReg", []> {
506 let EncoderMethod = "getLdStSORegOpValue";
507 // FIXME: Simplify the printer
508 let PrintMethod = "printAddrMode2Operand";
509 let MIOperandInfo = (ops GPR:$base, GPR:$offsreg, i32imm:$offsimm);
512 // addrmode2 := reg +/- imm12
513 // := reg +/- reg shop imm
515 def addrmode2 : Operand<i32>,
516 ComplexPattern<i32, 3, "SelectAddrMode2", []> {
517 let EncoderMethod = "getAddrMode2OpValue";
518 let PrintMethod = "printAddrMode2Operand";
519 let ParserMatchClass = MemMode2AsmOperand;
520 let MIOperandInfo = (ops GPR:$base, GPR:$offsreg, i32imm:$offsimm);
523 def am2offset : Operand<i32>,
524 ComplexPattern<i32, 2, "SelectAddrMode2Offset",
525 [], [SDNPWantRoot]> {
526 let EncoderMethod = "getAddrMode2OffsetOpValue";
527 let PrintMethod = "printAddrMode2OffsetOperand";
528 let MIOperandInfo = (ops GPR, i32imm);
531 // addrmode3 := reg +/- reg
532 // addrmode3 := reg +/- imm8
534 def addrmode3 : Operand<i32>,
535 ComplexPattern<i32, 3, "SelectAddrMode3", []> {
536 let EncoderMethod = "getAddrMode3OpValue";
537 let PrintMethod = "printAddrMode3Operand";
538 let ParserMatchClass = MemMode3AsmOperand;
539 let MIOperandInfo = (ops GPR:$base, GPR:$offsreg, i32imm:$offsimm);
542 def am3offset : Operand<i32>,
543 ComplexPattern<i32, 2, "SelectAddrMode3Offset",
544 [], [SDNPWantRoot]> {
545 let EncoderMethod = "getAddrMode3OffsetOpValue";
546 let PrintMethod = "printAddrMode3OffsetOperand";
547 let MIOperandInfo = (ops GPR, i32imm);
550 // ldstm_mode := {ia, ib, da, db}
552 def ldstm_mode : OptionalDefOperand<OtherVT, (ops i32), (ops (i32 1))> {
553 let EncoderMethod = "getLdStmModeOpValue";
554 let PrintMethod = "printLdStmModeOperand";
557 def MemMode5AsmOperand : AsmOperandClass {
558 let Name = "MemMode5";
559 let SuperClasses = [];
562 // addrmode5 := reg +/- imm8*4
564 def addrmode5 : Operand<i32>,
565 ComplexPattern<i32, 2, "SelectAddrMode5", []> {
566 let PrintMethod = "printAddrMode5Operand";
567 let MIOperandInfo = (ops GPR:$base, i32imm);
568 let ParserMatchClass = MemMode5AsmOperand;
569 let EncoderMethod = "getAddrMode5OpValue";
572 // addrmode6 := reg with optional alignment
574 def addrmode6 : Operand<i32>,
575 ComplexPattern<i32, 2, "SelectAddrMode6", [], [SDNPWantParent]>{
576 let PrintMethod = "printAddrMode6Operand";
577 let MIOperandInfo = (ops GPR:$addr, i32imm);
578 let EncoderMethod = "getAddrMode6AddressOpValue";
581 def am6offset : Operand<i32>,
582 ComplexPattern<i32, 1, "SelectAddrMode6Offset",
583 [], [SDNPWantRoot]> {
584 let PrintMethod = "printAddrMode6OffsetOperand";
585 let MIOperandInfo = (ops GPR);
586 let EncoderMethod = "getAddrMode6OffsetOpValue";
589 // Special version of addrmode6 to handle alignment encoding for VLD-dup
590 // instructions, specifically VLD4-dup.
591 def addrmode6dup : Operand<i32>,
592 ComplexPattern<i32, 2, "SelectAddrMode6", [], [SDNPWantParent]>{
593 let PrintMethod = "printAddrMode6Operand";
594 let MIOperandInfo = (ops GPR:$addr, i32imm);
595 let EncoderMethod = "getAddrMode6DupAddressOpValue";
598 // addrmodepc := pc + reg
600 def addrmodepc : Operand<i32>,
601 ComplexPattern<i32, 2, "SelectAddrModePC", []> {
602 let PrintMethod = "printAddrModePCOperand";
603 let MIOperandInfo = (ops GPR, i32imm);
606 def MemMode7AsmOperand : AsmOperandClass {
607 let Name = "MemMode7";
608 let SuperClasses = [];
612 // Used by load/store exclusive instructions. Useful to enable right assembly
613 // parsing and printing. Not used for any codegen matching.
615 def addrmode7 : Operand<i32> {
616 let PrintMethod = "printAddrMode7Operand";
617 let MIOperandInfo = (ops GPR);
618 let ParserMatchClass = MemMode7AsmOperand;
621 def nohash_imm : Operand<i32> {
622 let PrintMethod = "printNoHashImmediate";
625 def CoprocNumAsmOperand : AsmOperandClass {
626 let Name = "CoprocNum";
627 let SuperClasses = [];
628 let ParserMethod = "tryParseCoprocNumOperand";
631 def CoprocRegAsmOperand : AsmOperandClass {
632 let Name = "CoprocReg";
633 let SuperClasses = [];
634 let ParserMethod = "tryParseCoprocRegOperand";
637 def p_imm : Operand<i32> {
638 let PrintMethod = "printPImmediate";
639 let ParserMatchClass = CoprocNumAsmOperand;
642 def c_imm : Operand<i32> {
643 let PrintMethod = "printCImmediate";
644 let ParserMatchClass = CoprocRegAsmOperand;
647 //===----------------------------------------------------------------------===//
649 include "ARMInstrFormats.td"
651 //===----------------------------------------------------------------------===//
652 // Multiclass helpers...
655 /// AsI1_bin_irs - Defines a set of (op r, {so_imm|r|so_reg}) patterns for a
656 /// binop that produces a value.
657 multiclass AsI1_bin_irs<bits<4> opcod, string opc,
658 InstrItinClass iii, InstrItinClass iir, InstrItinClass iis,
659 PatFrag opnode, bit Commutable = 0> {
660 // The register-immediate version is re-materializable. This is useful
661 // in particular for taking the address of a local.
662 let isReMaterializable = 1 in {
663 def ri : AsI1<opcod, (outs GPR:$Rd), (ins GPR:$Rn, so_imm:$imm), DPFrm,
664 iii, opc, "\t$Rd, $Rn, $imm",
665 [(set GPR:$Rd, (opnode GPR:$Rn, so_imm:$imm))]> {
670 let Inst{19-16} = Rn;
671 let Inst{15-12} = Rd;
672 let Inst{11-0} = imm;
675 def rr : AsI1<opcod, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm), DPFrm,
676 iir, opc, "\t$Rd, $Rn, $Rm",
677 [(set GPR:$Rd, (opnode GPR:$Rn, GPR:$Rm))]> {
682 let isCommutable = Commutable;
683 let Inst{19-16} = Rn;
684 let Inst{15-12} = Rd;
685 let Inst{11-4} = 0b00000000;
688 def rs : AsI1<opcod, (outs GPR:$Rd), (ins GPR:$Rn, so_reg:$shift), DPSoRegFrm,
689 iis, opc, "\t$Rd, $Rn, $shift",
690 [(set GPR:$Rd, (opnode GPR:$Rn, so_reg:$shift))]> {
695 let Inst{19-16} = Rn;
696 let Inst{15-12} = Rd;
697 let Inst{11-0} = shift;
701 /// AI1_bin_s_irs - Similar to AsI1_bin_irs except it sets the 's' bit so the
702 /// instruction modifies the CPSR register.
703 let isCodeGenOnly = 1, Defs = [CPSR] in {
704 multiclass AI1_bin_s_irs<bits<4> opcod, string opc,
705 InstrItinClass iii, InstrItinClass iir, InstrItinClass iis,
706 PatFrag opnode, bit Commutable = 0> {
707 def ri : AI1<opcod, (outs GPR:$Rd), (ins GPR:$Rn, so_imm:$imm), DPFrm,
708 iii, opc, "\t$Rd, $Rn, $imm",
709 [(set GPR:$Rd, (opnode GPR:$Rn, so_imm:$imm))]> {
715 let Inst{19-16} = Rn;
716 let Inst{15-12} = Rd;
717 let Inst{11-0} = imm;
719 def rr : AI1<opcod, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm), DPFrm,
720 iir, opc, "\t$Rd, $Rn, $Rm",
721 [(set GPR:$Rd, (opnode GPR:$Rn, GPR:$Rm))]> {
725 let isCommutable = Commutable;
728 let Inst{19-16} = Rn;
729 let Inst{15-12} = Rd;
730 let Inst{11-4} = 0b00000000;
733 def rs : AI1<opcod, (outs GPR:$Rd), (ins GPR:$Rn, so_reg:$shift), DPSoRegFrm,
734 iis, opc, "\t$Rd, $Rn, $shift",
735 [(set GPR:$Rd, (opnode GPR:$Rn, so_reg:$shift))]> {
741 let Inst{19-16} = Rn;
742 let Inst{15-12} = Rd;
743 let Inst{11-0} = shift;
748 /// AI1_cmp_irs - Defines a set of (op r, {so_imm|r|so_reg}) cmp / test
749 /// patterns. Similar to AsI1_bin_irs except the instruction does not produce
750 /// a explicit result, only implicitly set CPSR.
751 let isCompare = 1, Defs = [CPSR] in {
752 multiclass AI1_cmp_irs<bits<4> opcod, string opc,
753 InstrItinClass iii, InstrItinClass iir, InstrItinClass iis,
754 PatFrag opnode, bit Commutable = 0> {
755 def ri : AI1<opcod, (outs), (ins GPR:$Rn, so_imm:$imm), DPFrm, iii,
757 [(opnode GPR:$Rn, so_imm:$imm)]> {
762 let Inst{19-16} = Rn;
763 let Inst{15-12} = 0b0000;
764 let Inst{11-0} = imm;
766 def rr : AI1<opcod, (outs), (ins GPR:$Rn, GPR:$Rm), DPFrm, iir,
768 [(opnode GPR:$Rn, GPR:$Rm)]> {
771 let isCommutable = Commutable;
774 let Inst{19-16} = Rn;
775 let Inst{15-12} = 0b0000;
776 let Inst{11-4} = 0b00000000;
779 def rs : AI1<opcod, (outs), (ins GPR:$Rn, so_reg:$shift), DPSoRegFrm, iis,
780 opc, "\t$Rn, $shift",
781 [(opnode GPR:$Rn, so_reg:$shift)]> {
786 let Inst{19-16} = Rn;
787 let Inst{15-12} = 0b0000;
788 let Inst{11-0} = shift;
793 /// AI_ext_rrot - A unary operation with two forms: one whose operand is a
794 /// register and one whose operand is a register rotated by 8/16/24.
795 /// FIXME: Remove the 'r' variant. Its rot_imm is zero.
796 multiclass AI_ext_rrot<bits<8> opcod, string opc, PatFrag opnode> {
797 def r : AExtI<opcod, (outs GPR:$Rd), (ins GPR:$Rm),
798 IIC_iEXTr, opc, "\t$Rd, $Rm",
799 [(set GPR:$Rd, (opnode GPR:$Rm))]>,
800 Requires<[IsARM, HasV6]> {
803 let Inst{19-16} = 0b1111;
804 let Inst{15-12} = Rd;
805 let Inst{11-10} = 0b00;
808 def r_rot : AExtI<opcod, (outs GPR:$Rd), (ins GPR:$Rm, rot_imm:$rot),
809 IIC_iEXTr, opc, "\t$Rd, $Rm, ror $rot",
810 [(set GPR:$Rd, (opnode (rotr GPR:$Rm, rot_imm:$rot)))]>,
811 Requires<[IsARM, HasV6]> {
815 let Inst{19-16} = 0b1111;
816 let Inst{15-12} = Rd;
817 let Inst{11-10} = rot;
822 multiclass AI_ext_rrot_np<bits<8> opcod, string opc> {
823 def r : AExtI<opcod, (outs GPR:$Rd), (ins GPR:$Rm),
824 IIC_iEXTr, opc, "\t$Rd, $Rm",
825 [/* For disassembly only; pattern left blank */]>,
826 Requires<[IsARM, HasV6]> {
827 let Inst{19-16} = 0b1111;
828 let Inst{11-10} = 0b00;
830 def r_rot : AExtI<opcod, (outs GPR:$Rd), (ins GPR:$Rm, rot_imm:$rot),
831 IIC_iEXTr, opc, "\t$Rd, $Rm, ror $rot",
832 [/* For disassembly only; pattern left blank */]>,
833 Requires<[IsARM, HasV6]> {
835 let Inst{19-16} = 0b1111;
836 let Inst{11-10} = rot;
840 /// AI_exta_rrot - A binary operation with two forms: one whose operand is a
841 /// register and one whose operand is a register rotated by 8/16/24.
842 multiclass AI_exta_rrot<bits<8> opcod, string opc, PatFrag opnode> {
843 def rr : AExtI<opcod, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm),
844 IIC_iEXTAr, opc, "\t$Rd, $Rn, $Rm",
845 [(set GPR:$Rd, (opnode GPR:$Rn, GPR:$Rm))]>,
846 Requires<[IsARM, HasV6]> {
850 let Inst{19-16} = Rn;
851 let Inst{15-12} = Rd;
852 let Inst{11-10} = 0b00;
853 let Inst{9-4} = 0b000111;
856 def rr_rot : AExtI<opcod, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm,
858 IIC_iEXTAr, opc, "\t$Rd, $Rn, $Rm, ror $rot",
859 [(set GPR:$Rd, (opnode GPR:$Rn,
860 (rotr GPR:$Rm, rot_imm:$rot)))]>,
861 Requires<[IsARM, HasV6]> {
866 let Inst{19-16} = Rn;
867 let Inst{15-12} = Rd;
868 let Inst{11-10} = rot;
869 let Inst{9-4} = 0b000111;
874 // For disassembly only.
875 multiclass AI_exta_rrot_np<bits<8> opcod, string opc> {
876 def rr : AExtI<opcod, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm),
877 IIC_iEXTAr, opc, "\t$Rd, $Rn, $Rm",
878 [/* For disassembly only; pattern left blank */]>,
879 Requires<[IsARM, HasV6]> {
880 let Inst{11-10} = 0b00;
882 def rr_rot : AExtI<opcod, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm,
884 IIC_iEXTAr, opc, "\t$Rd, $Rn, $Rm, ror $rot",
885 [/* For disassembly only; pattern left blank */]>,
886 Requires<[IsARM, HasV6]> {
889 let Inst{19-16} = Rn;
890 let Inst{11-10} = rot;
894 /// AI1_adde_sube_irs - Define instructions and patterns for adde and sube.
895 let Uses = [CPSR] in {
896 multiclass AI1_adde_sube_irs<bits<4> opcod, string opc, PatFrag opnode,
897 bit Commutable = 0> {
898 def ri : AsI1<opcod, (outs GPR:$Rd), (ins GPR:$Rn, so_imm:$imm),
899 DPFrm, IIC_iALUi, opc, "\t$Rd, $Rn, $imm",
900 [(set GPR:$Rd, (opnode GPR:$Rn, so_imm:$imm))]>,
906 let Inst{15-12} = Rd;
907 let Inst{19-16} = Rn;
908 let Inst{11-0} = imm;
910 def rr : AsI1<opcod, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm),
911 DPFrm, IIC_iALUr, opc, "\t$Rd, $Rn, $Rm",
912 [(set GPR:$Rd, (opnode GPR:$Rn, GPR:$Rm))]>,
917 let Inst{11-4} = 0b00000000;
919 let isCommutable = Commutable;
921 let Inst{15-12} = Rd;
922 let Inst{19-16} = Rn;
924 def rs : AsI1<opcod, (outs GPR:$Rd), (ins GPR:$Rn, so_reg:$shift),
925 DPSoRegFrm, IIC_iALUsr, opc, "\t$Rd, $Rn, $shift",
926 [(set GPR:$Rd, (opnode GPR:$Rn, so_reg:$shift))]>,
932 let Inst{11-0} = shift;
933 let Inst{15-12} = Rd;
934 let Inst{19-16} = Rn;
939 // Carry setting variants
940 // NOTE: CPSR def omitted because it will be handled by the custom inserter.
941 let usesCustomInserter = 1 in {
942 multiclass AI1_adde_sube_s_irs<PatFrag opnode, bit Commutable = 0> {
943 def ri : ARMPseudoInst<(outs GPR:$Rd), (ins GPR:$Rn, so_imm:$imm),
944 Size4Bytes, IIC_iALUi,
945 [(set GPR:$Rd, (opnode GPR:$Rn, so_imm:$imm))]>;
946 def rr : ARMPseudoInst<(outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm),
947 Size4Bytes, IIC_iALUr,
948 [(set GPR:$Rd, (opnode GPR:$Rn, GPR:$Rm))]> {
949 let isCommutable = Commutable;
951 def rs : ARMPseudoInst<(outs GPR:$Rd), (ins GPR:$Rn, so_reg:$shift),
952 Size4Bytes, IIC_iALUsr,
953 [(set GPR:$Rd, (opnode GPR:$Rn, so_reg:$shift))]>;
957 let canFoldAsLoad = 1, isReMaterializable = 1 in {
958 multiclass AI_ldr1<bit isByte, string opc, InstrItinClass iii,
959 InstrItinClass iir, PatFrag opnode> {
960 // Note: We use the complex addrmode_imm12 rather than just an input
961 // GPR and a constrained immediate so that we can use this to match
962 // frame index references and avoid matching constant pool references.
963 def i12: AI2ldst<0b010, 1, isByte, (outs GPR:$Rt), (ins addrmode_imm12:$addr),
964 AddrMode_i12, LdFrm, iii, opc, "\t$Rt, $addr",
965 [(set GPR:$Rt, (opnode addrmode_imm12:$addr))]> {
968 let Inst{23} = addr{12}; // U (add = ('U' == 1))
969 let Inst{19-16} = addr{16-13}; // Rn
970 let Inst{15-12} = Rt;
971 let Inst{11-0} = addr{11-0}; // imm12
973 def rs : AI2ldst<0b011, 1, isByte, (outs GPR:$Rt), (ins ldst_so_reg:$shift),
974 AddrModeNone, LdFrm, iir, opc, "\t$Rt, $shift",
975 [(set GPR:$Rt, (opnode ldst_so_reg:$shift))]> {
978 let shift{4} = 0; // Inst{4} = 0
979 let Inst{23} = shift{12}; // U (add = ('U' == 1))
980 let Inst{19-16} = shift{16-13}; // Rn
981 let Inst{15-12} = Rt;
982 let Inst{11-0} = shift{11-0};
987 multiclass AI_str1<bit isByte, string opc, InstrItinClass iii,
988 InstrItinClass iir, PatFrag opnode> {
989 // Note: We use the complex addrmode_imm12 rather than just an input
990 // GPR and a constrained immediate so that we can use this to match
991 // frame index references and avoid matching constant pool references.
992 def i12 : AI2ldst<0b010, 0, isByte, (outs),
993 (ins GPR:$Rt, addrmode_imm12:$addr),
994 AddrMode_i12, StFrm, iii, opc, "\t$Rt, $addr",
995 [(opnode GPR:$Rt, addrmode_imm12:$addr)]> {
998 let Inst{23} = addr{12}; // U (add = ('U' == 1))
999 let Inst{19-16} = addr{16-13}; // Rn
1000 let Inst{15-12} = Rt;
1001 let Inst{11-0} = addr{11-0}; // imm12
1003 def rs : AI2ldst<0b011, 0, isByte, (outs), (ins GPR:$Rt, ldst_so_reg:$shift),
1004 AddrModeNone, StFrm, iir, opc, "\t$Rt, $shift",
1005 [(opnode GPR:$Rt, ldst_so_reg:$shift)]> {
1008 let shift{4} = 0; // Inst{4} = 0
1009 let Inst{23} = shift{12}; // U (add = ('U' == 1))
1010 let Inst{19-16} = shift{16-13}; // Rn
1011 let Inst{15-12} = Rt;
1012 let Inst{11-0} = shift{11-0};
1015 //===----------------------------------------------------------------------===//
1017 //===----------------------------------------------------------------------===//
1019 //===----------------------------------------------------------------------===//
1020 // Miscellaneous Instructions.
1023 /// CONSTPOOL_ENTRY - This instruction represents a floating constant pool in
1024 /// the function. The first operand is the ID# for this instruction, the second
1025 /// is the index into the MachineConstantPool that this is, the third is the
1026 /// size in bytes of this constant pool entry.
1027 let neverHasSideEffects = 1, isNotDuplicable = 1 in
1028 def CONSTPOOL_ENTRY :
1029 PseudoInst<(outs), (ins cpinst_operand:$instid, cpinst_operand:$cpidx,
1030 i32imm:$size), NoItinerary, []>;
1032 // FIXME: Marking these as hasSideEffects is necessary to prevent machine DCE
1033 // from removing one half of the matched pairs. That breaks PEI, which assumes
1034 // these will always be in pairs, and asserts if it finds otherwise. Better way?
1035 let Defs = [SP], Uses = [SP], hasSideEffects = 1 in {
1036 def ADJCALLSTACKUP :
1037 PseudoInst<(outs), (ins i32imm:$amt1, i32imm:$amt2, pred:$p), NoItinerary,
1038 [(ARMcallseq_end timm:$amt1, timm:$amt2)]>;
1040 def ADJCALLSTACKDOWN :
1041 PseudoInst<(outs), (ins i32imm:$amt, pred:$p), NoItinerary,
1042 [(ARMcallseq_start timm:$amt)]>;
1045 def NOP : AI<(outs), (ins), MiscFrm, NoItinerary, "nop", "",
1046 [/* For disassembly only; pattern left blank */]>,
1047 Requires<[IsARM, HasV6T2]> {
1048 let Inst{27-16} = 0b001100100000;
1049 let Inst{15-8} = 0b11110000;
1050 let Inst{7-0} = 0b00000000;
1053 def YIELD : AI<(outs), (ins), MiscFrm, NoItinerary, "yield", "",
1054 [/* For disassembly only; pattern left blank */]>,
1055 Requires<[IsARM, HasV6T2]> {
1056 let Inst{27-16} = 0b001100100000;
1057 let Inst{15-8} = 0b11110000;
1058 let Inst{7-0} = 0b00000001;
1061 def WFE : AI<(outs), (ins), MiscFrm, NoItinerary, "wfe", "",
1062 [/* For disassembly only; pattern left blank */]>,
1063 Requires<[IsARM, HasV6T2]> {
1064 let Inst{27-16} = 0b001100100000;
1065 let Inst{15-8} = 0b11110000;
1066 let Inst{7-0} = 0b00000010;
1069 def WFI : AI<(outs), (ins), MiscFrm, NoItinerary, "wfi", "",
1070 [/* For disassembly only; pattern left blank */]>,
1071 Requires<[IsARM, HasV6T2]> {
1072 let Inst{27-16} = 0b001100100000;
1073 let Inst{15-8} = 0b11110000;
1074 let Inst{7-0} = 0b00000011;
1077 def SEL : AI<(outs GPR:$dst), (ins GPR:$a, GPR:$b), DPFrm, NoItinerary, "sel",
1079 [/* For disassembly only; pattern left blank */]>,
1080 Requires<[IsARM, HasV6]> {
1085 let Inst{15-12} = Rd;
1086 let Inst{19-16} = Rn;
1087 let Inst{27-20} = 0b01101000;
1088 let Inst{7-4} = 0b1011;
1089 let Inst{11-8} = 0b1111;
1092 def SEV : AI<(outs), (ins), MiscFrm, NoItinerary, "sev", "",
1093 [/* For disassembly only; pattern left blank */]>,
1094 Requires<[IsARM, HasV6T2]> {
1095 let Inst{27-16} = 0b001100100000;
1096 let Inst{15-8} = 0b11110000;
1097 let Inst{7-0} = 0b00000100;
1100 // The i32imm operand $val can be used by a debugger to store more information
1101 // about the breakpoint.
1102 def BKPT : AI<(outs), (ins i32imm:$val), MiscFrm, NoItinerary, "bkpt", "\t$val",
1103 [/* For disassembly only; pattern left blank */]>,
1106 let Inst{3-0} = val{3-0};
1107 let Inst{19-8} = val{15-4};
1108 let Inst{27-20} = 0b00010010;
1109 let Inst{7-4} = 0b0111;
1112 // Change Processor State is a system instruction -- for disassembly and
1114 // FIXME: Since the asm parser has currently no clean way to handle optional
1115 // operands, create 3 versions of the same instruction. Once there's a clean
1116 // framework to represent optional operands, change this behavior.
1117 class CPS<dag iops, string asm_ops>
1118 : AXI<(outs), iops, MiscFrm, NoItinerary, !strconcat("cps", asm_ops),
1119 [/* For disassembly only; pattern left blank */]>, Requires<[IsARM]> {
1125 let Inst{31-28} = 0b1111;
1126 let Inst{27-20} = 0b00010000;
1127 let Inst{19-18} = imod;
1128 let Inst{17} = M; // Enabled if mode is set;
1130 let Inst{8-6} = iflags;
1132 let Inst{4-0} = mode;
1136 def CPS3p : CPS<(ins imod_op:$imod, iflags_op:$iflags, i32imm:$mode),
1137 "$imod\t$iflags, $mode">;
1138 let mode = 0, M = 0 in
1139 def CPS2p : CPS<(ins imod_op:$imod, iflags_op:$iflags), "$imod\t$iflags">;
1141 let imod = 0, iflags = 0, M = 1 in
1142 def CPS1p : CPS<(ins i32imm:$mode), "\t$mode">;
1144 // Preload signals the memory system of possible future data/instruction access.
1145 // These are for disassembly only.
1146 multiclass APreLoad<bits<1> read, bits<1> data, string opc> {
1148 def i12 : AXI<(outs), (ins addrmode_imm12:$addr), MiscFrm, IIC_Preload,
1149 !strconcat(opc, "\t$addr"),
1150 [(ARMPreload addrmode_imm12:$addr, (i32 read), (i32 data))]> {
1153 let Inst{31-26} = 0b111101;
1154 let Inst{25} = 0; // 0 for immediate form
1155 let Inst{24} = data;
1156 let Inst{23} = addr{12}; // U (add = ('U' == 1))
1157 let Inst{22} = read;
1158 let Inst{21-20} = 0b01;
1159 let Inst{19-16} = addr{16-13}; // Rn
1160 let Inst{15-12} = 0b1111;
1161 let Inst{11-0} = addr{11-0}; // imm12
1164 def rs : AXI<(outs), (ins ldst_so_reg:$shift), MiscFrm, IIC_Preload,
1165 !strconcat(opc, "\t$shift"),
1166 [(ARMPreload ldst_so_reg:$shift, (i32 read), (i32 data))]> {
1168 let Inst{31-26} = 0b111101;
1169 let Inst{25} = 1; // 1 for register form
1170 let Inst{24} = data;
1171 let Inst{23} = shift{12}; // U (add = ('U' == 1))
1172 let Inst{22} = read;
1173 let Inst{21-20} = 0b01;
1174 let Inst{19-16} = shift{16-13}; // Rn
1175 let Inst{15-12} = 0b1111;
1176 let Inst{11-0} = shift{11-0};
1180 defm PLD : APreLoad<1, 1, "pld">, Requires<[IsARM]>;
1181 defm PLDW : APreLoad<0, 1, "pldw">, Requires<[IsARM,HasV7,HasMP]>;
1182 defm PLI : APreLoad<1, 0, "pli">, Requires<[IsARM,HasV7]>;
1184 def SETEND : AXI<(outs),(ins setend_op:$end), MiscFrm, NoItinerary,
1186 [/* For disassembly only; pattern left blank */]>,
1189 let Inst{31-10} = 0b1111000100000001000000;
1194 def DBG : AI<(outs), (ins i32imm:$opt), MiscFrm, NoItinerary, "dbg", "\t$opt",
1195 [/* For disassembly only; pattern left blank */]>,
1196 Requires<[IsARM, HasV7]> {
1198 let Inst{27-4} = 0b001100100000111100001111;
1199 let Inst{3-0} = opt;
1202 // A5.4 Permanently UNDEFINED instructions.
1203 let isBarrier = 1, isTerminator = 1 in
1204 def TRAP : AXI<(outs), (ins), MiscFrm, NoItinerary,
1207 let Inst = 0xe7ffdefe;
1210 // Address computation and loads and stores in PIC mode.
1211 let isNotDuplicable = 1 in {
1212 def PICADD : ARMPseudoInst<(outs GPR:$dst), (ins GPR:$a, pclabel:$cp, pred:$p),
1213 Size4Bytes, IIC_iALUr,
1214 [(set GPR:$dst, (ARMpic_add GPR:$a, imm:$cp))]>;
1216 let AddedComplexity = 10 in {
1217 def PICLDR : ARMPseudoInst<(outs GPR:$dst), (ins addrmodepc:$addr, pred:$p),
1218 Size4Bytes, IIC_iLoad_r,
1219 [(set GPR:$dst, (load addrmodepc:$addr))]>;
1221 def PICLDRH : ARMPseudoInst<(outs GPR:$Rt), (ins addrmodepc:$addr, pred:$p),
1222 Size4Bytes, IIC_iLoad_bh_r,
1223 [(set GPR:$Rt, (zextloadi16 addrmodepc:$addr))]>;
1225 def PICLDRB : ARMPseudoInst<(outs GPR:$Rt), (ins addrmodepc:$addr, pred:$p),
1226 Size4Bytes, IIC_iLoad_bh_r,
1227 [(set GPR:$Rt, (zextloadi8 addrmodepc:$addr))]>;
1229 def PICLDRSH : ARMPseudoInst<(outs GPR:$Rt), (ins addrmodepc:$addr, pred:$p),
1230 Size4Bytes, IIC_iLoad_bh_r,
1231 [(set GPR:$Rt, (sextloadi16 addrmodepc:$addr))]>;
1233 def PICLDRSB : ARMPseudoInst<(outs GPR:$Rt), (ins addrmodepc:$addr, pred:$p),
1234 Size4Bytes, IIC_iLoad_bh_r,
1235 [(set GPR:$Rt, (sextloadi8 addrmodepc:$addr))]>;
1237 let AddedComplexity = 10 in {
1238 def PICSTR : ARMPseudoInst<(outs), (ins GPR:$src, addrmodepc:$addr, pred:$p),
1239 Size4Bytes, IIC_iStore_r, [(store GPR:$src, addrmodepc:$addr)]>;
1241 def PICSTRH : ARMPseudoInst<(outs), (ins GPR:$src, addrmodepc:$addr, pred:$p),
1242 Size4Bytes, IIC_iStore_bh_r, [(truncstorei16 GPR:$src,
1243 addrmodepc:$addr)]>;
1245 def PICSTRB : ARMPseudoInst<(outs), (ins GPR:$src, addrmodepc:$addr, pred:$p),
1246 Size4Bytes, IIC_iStore_bh_r, [(truncstorei8 GPR:$src, addrmodepc:$addr)]>;
1248 } // isNotDuplicable = 1
1251 // LEApcrel - Load a pc-relative address into a register without offending the
1253 let neverHasSideEffects = 1, isReMaterializable = 1 in
1254 // The 'adr' mnemonic encodes differently if the label is before or after
1255 // the instruction. The {24-21} opcode bits are set by the fixup, as we don't
1256 // know until then which form of the instruction will be used.
1257 def ADR : AI1<{0,?,?,0}, (outs GPR:$Rd), (ins adrlabel:$label),
1258 MiscFrm, IIC_iALUi, "adr", "\t$Rd, #$label", []> {
1261 let Inst{27-25} = 0b001;
1263 let Inst{19-16} = 0b1111;
1264 let Inst{15-12} = Rd;
1265 let Inst{11-0} = label;
1267 def LEApcrel : ARMPseudoInst<(outs GPR:$Rd), (ins i32imm:$label, pred:$p),
1268 Size4Bytes, IIC_iALUi, []>;
1270 def LEApcrelJT : ARMPseudoInst<(outs GPR:$Rd),
1271 (ins i32imm:$label, nohash_imm:$id, pred:$p),
1272 Size4Bytes, IIC_iALUi, []>;
1274 //===----------------------------------------------------------------------===//
1275 // Control Flow Instructions.
1278 let isReturn = 1, isTerminator = 1, isBarrier = 1 in {
1280 def BX_RET : AI<(outs), (ins), BrMiscFrm, IIC_Br,
1281 "bx", "\tlr", [(ARMretflag)]>,
1282 Requires<[IsARM, HasV4T]> {
1283 let Inst{27-0} = 0b0001001011111111111100011110;
1287 def MOVPCLR : AI<(outs), (ins), BrMiscFrm, IIC_Br,
1288 "mov", "\tpc, lr", [(ARMretflag)]>,
1289 Requires<[IsARM, NoV4T]> {
1290 let Inst{27-0} = 0b0001101000001111000000001110;
1294 // Indirect branches
1295 let isBranch = 1, isTerminator = 1, isBarrier = 1, isIndirectBranch = 1 in {
1297 def BX : AXI<(outs), (ins GPR:$dst), BrMiscFrm, IIC_Br, "bx\t$dst",
1298 [(brind GPR:$dst)]>,
1299 Requires<[IsARM, HasV4T]> {
1301 let Inst{31-4} = 0b1110000100101111111111110001;
1302 let Inst{3-0} = dst;
1306 // FIXME: We would really like to define this as a vanilla ARMPat like:
1307 // ARMPat<(brind GPR:$dst), (MOVr PC, GPR:$dst)>
1308 // With that, however, we can't set isBranch, isTerminator, etc..
1309 def MOVPCRX : ARMPseudoInst<(outs), (ins GPR:$dst),
1310 Size4Bytes, IIC_Br, [(brind GPR:$dst)]>,
1311 Requires<[IsARM, NoV4T]>;
1314 // All calls clobber the non-callee saved registers. SP is marked as
1315 // a use to prevent stack-pointer assignments that appear immediately
1316 // before calls from potentially appearing dead.
1318 // On non-Darwin platforms R9 is callee-saved.
1319 // FIXME: Do we really need a non-predicated version? If so, it should
1320 // at least be a pseudo instruction expanding to the predicated version
1321 // at MC lowering time.
1322 Defs = [R0, R1, R2, R3, R12, LR,
1323 D0, D1, D2, D3, D4, D5, D6, D7,
1324 D16, D17, D18, D19, D20, D21, D22, D23,
1325 D24, D25, D26, D27, D28, D29, D30, D31, CPSR, FPSCR],
1327 def BL : ABXI<0b1011, (outs), (ins bl_target:$func, variable_ops),
1328 IIC_Br, "bl\t$func",
1329 [(ARMcall tglobaladdr:$func)]>,
1330 Requires<[IsARM, IsNotDarwin]> {
1331 let Inst{31-28} = 0b1110;
1333 let Inst{23-0} = func;
1336 def BL_pred : ABI<0b1011, (outs), (ins bl_target:$func, variable_ops),
1337 IIC_Br, "bl", "\t$func",
1338 [(ARMcall_pred tglobaladdr:$func)]>,
1339 Requires<[IsARM, IsNotDarwin]> {
1341 let Inst{23-0} = func;
1345 def BLX : AXI<(outs), (ins GPR:$func, variable_ops), BrMiscFrm,
1346 IIC_Br, "blx\t$func",
1347 [(ARMcall GPR:$func)]>,
1348 Requires<[IsARM, HasV5T, IsNotDarwin]> {
1350 let Inst{31-4} = 0b1110000100101111111111110011;
1351 let Inst{3-0} = func;
1354 def BLX_pred : AI<(outs), (ins GPR:$func, variable_ops), BrMiscFrm,
1355 IIC_Br, "blx", "\t$func",
1356 [(ARMcall_pred GPR:$func)]>,
1357 Requires<[IsARM, HasV5T, IsNotDarwin]> {
1359 let Inst{27-4} = 0b000100101111111111110011;
1360 let Inst{3-0} = func;
1364 // Note: Restrict $func to the tGPR regclass to prevent it being in LR.
1365 def BX_CALL : ARMPseudoInst<(outs), (ins tGPR:$func, variable_ops),
1366 Size8Bytes, IIC_Br, [(ARMcall_nolink tGPR:$func)]>,
1367 Requires<[IsARM, HasV4T, IsNotDarwin]>;
1370 def BMOVPCRX_CALL : ARMPseudoInst<(outs), (ins tGPR:$func, variable_ops),
1371 Size8Bytes, IIC_Br, [(ARMcall_nolink tGPR:$func)]>,
1372 Requires<[IsARM, NoV4T, IsNotDarwin]>;
1376 // On Darwin R9 is call-clobbered.
1377 // R7 is marked as a use to prevent frame-pointer assignments from being
1378 // moved above / below calls.
1379 Defs = [R0, R1, R2, R3, R9, R12, LR,
1380 D0, D1, D2, D3, D4, D5, D6, D7,
1381 D16, D17, D18, D19, D20, D21, D22, D23,
1382 D24, D25, D26, D27, D28, D29, D30, D31, CPSR, FPSCR],
1383 Uses = [R7, SP] in {
1384 def BLr9 : ARMPseudoInst<(outs), (ins bltarget:$func, variable_ops),
1386 [(ARMcall tglobaladdr:$func)]>, Requires<[IsARM, IsDarwin]>;
1388 def BLr9_pred : ARMPseudoInst<(outs),
1389 (ins bltarget:$func, pred:$p, variable_ops),
1391 [(ARMcall_pred tglobaladdr:$func)]>,
1392 Requires<[IsARM, IsDarwin]>;
1395 def BLXr9 : ARMPseudoInst<(outs), (ins GPR:$func, variable_ops),
1397 [(ARMcall GPR:$func)]>, Requires<[IsARM, HasV5T, IsDarwin]>;
1399 def BLXr9_pred: ARMPseudoInst<(outs), (ins GPR:$func, pred:$p, variable_ops),
1401 [(ARMcall_pred GPR:$func)]>,
1402 Requires<[IsARM, HasV5T, IsDarwin]>;
1405 // Note: Restrict $func to the tGPR regclass to prevent it being in LR.
1406 def BXr9_CALL : ARMPseudoInst<(outs), (ins tGPR:$func, variable_ops),
1407 Size8Bytes, IIC_Br, [(ARMcall_nolink tGPR:$func)]>,
1408 Requires<[IsARM, HasV4T, IsDarwin]>;
1411 def BMOVPCRXr9_CALL : ARMPseudoInst<(outs), (ins tGPR:$func, variable_ops),
1412 Size8Bytes, IIC_Br, [(ARMcall_nolink tGPR:$func)]>,
1413 Requires<[IsARM, NoV4T, IsDarwin]>;
1418 // FIXME: The Thumb versions of these should live in ARMInstrThumb.td
1419 let isCall = 1, isTerminator = 1, isReturn = 1, isBarrier = 1 in {
1421 let Defs = [R0, R1, R2, R3, R9, R12,
1422 D0, D1, D2, D3, D4, D5, D6, D7,
1423 D16, D17, D18, D19, D20, D21, D22, D23, D24, D25, D26,
1424 D27, D28, D29, D30, D31, PC],
1426 def TCRETURNdi : PseudoInst<(outs), (ins i32imm:$dst, variable_ops),
1427 IIC_Br, []>, Requires<[IsDarwin]>;
1429 def TCRETURNri : PseudoInst<(outs), (ins tcGPR:$dst, variable_ops),
1430 IIC_Br, []>, Requires<[IsDarwin]>;
1432 def TAILJMPd : ARMPseudoInst<(outs), (ins brtarget:$dst, variable_ops),
1434 []>, Requires<[IsARM, IsDarwin]>;
1436 def tTAILJMPd: tPseudoInst<(outs), (ins brtarget:$dst, variable_ops),
1438 []>, Requires<[IsThumb, IsDarwin]>;
1440 def TAILJMPr : ARMPseudoInst<(outs), (ins tcGPR:$dst, variable_ops),
1442 []>, Requires<[IsARM, IsDarwin]>;
1444 def tTAILJMPr : tPseudoInst<(outs), (ins tcGPR:$dst, variable_ops),
1446 []>, Requires<[IsThumb, IsDarwin]>;
1449 // Non-Darwin versions (the difference is R9).
1450 let Defs = [R0, R1, R2, R3, R12,
1451 D0, D1, D2, D3, D4, D5, D6, D7,
1452 D16, D17, D18, D19, D20, D21, D22, D23, D24, D25, D26,
1453 D27, D28, D29, D30, D31, PC],
1455 def TCRETURNdiND : PseudoInst<(outs), (ins i32imm:$dst, variable_ops),
1456 IIC_Br, []>, Requires<[IsNotDarwin]>;
1458 def TCRETURNriND : PseudoInst<(outs), (ins tcGPR:$dst, variable_ops),
1459 IIC_Br, []>, Requires<[IsNotDarwin]>;
1461 def TAILJMPdND : ARMPseudoInst<(outs), (ins brtarget:$dst, variable_ops),
1463 []>, Requires<[IsARM, IsNotDarwin]>;
1465 def tTAILJMPdND : tPseudoInst<(outs), (ins brtarget:$dst, variable_ops),
1467 []>, Requires<[IsThumb, IsNotDarwin]>;
1469 def TAILJMPrND : ARMPseudoInst<(outs), (ins tcGPR:$dst, variable_ops),
1471 []>, Requires<[IsARM, IsNotDarwin]>;
1472 def tTAILJMPrND : tPseudoInst<(outs), (ins tcGPR:$dst, variable_ops),
1474 []>, Requires<[IsThumb, IsNotDarwin]>;
1478 let isBranch = 1, isTerminator = 1 in {
1479 // B is "predicable" since it's just a Bcc with an 'always' condition.
1480 let isBarrier = 1 in {
1481 let isPredicable = 1 in
1482 // FIXME: We shouldn't need this pseudo at all. Just using Bcc directly
1483 // should be sufficient.
1484 def B : ARMPseudoInst<(outs), (ins brtarget:$target), Size4Bytes, IIC_Br,
1487 let isNotDuplicable = 1, isIndirectBranch = 1 in {
1488 def BR_JTr : ARMPseudoInst<(outs),
1489 (ins GPR:$target, i32imm:$jt, i32imm:$id),
1490 SizeSpecial, IIC_Br,
1491 [(ARMbrjt GPR:$target, tjumptable:$jt, imm:$id)]>;
1492 // FIXME: This shouldn't use the generic "addrmode2," but rather be split
1493 // into i12 and rs suffixed versions.
1494 def BR_JTm : ARMPseudoInst<(outs),
1495 (ins addrmode2:$target, i32imm:$jt, i32imm:$id),
1496 SizeSpecial, IIC_Br,
1497 [(ARMbrjt (i32 (load addrmode2:$target)), tjumptable:$jt,
1499 def BR_JTadd : ARMPseudoInst<(outs),
1500 (ins GPR:$target, GPR:$idx, i32imm:$jt, i32imm:$id),
1501 SizeSpecial, IIC_Br,
1502 [(ARMbrjt (add GPR:$target, GPR:$idx), tjumptable:$jt,
1504 } // isNotDuplicable = 1, isIndirectBranch = 1
1507 // FIXME: should be able to write a pattern for ARMBrcond, but can't use
1508 // a two-value operand where a dag node expects two operands. :(
1509 def Bcc : ABI<0b1010, (outs), (ins br_target:$target),
1510 IIC_Br, "b", "\t$target",
1511 [/*(ARMbrcond bb:$target, imm:$cc, CCR:$ccr)*/]> {
1513 let Inst{23-0} = target;
1517 // BLX (immediate) -- for disassembly only
1518 def BLXi : AXI<(outs), (ins br_target:$target), BrMiscFrm, NoItinerary,
1519 "blx\t$target", [/* pattern left blank */]>,
1520 Requires<[IsARM, HasV5T]> {
1521 let Inst{31-25} = 0b1111101;
1523 let Inst{23-0} = target{24-1};
1524 let Inst{24} = target{0};
1527 // Branch and Exchange Jazelle -- for disassembly only
1528 def BXJ : ABI<0b0001, (outs), (ins GPR:$func), NoItinerary, "bxj", "\t$func",
1529 [/* For disassembly only; pattern left blank */]> {
1530 let Inst{23-20} = 0b0010;
1531 //let Inst{19-8} = 0xfff;
1532 let Inst{7-4} = 0b0010;
1535 // Secure Monitor Call is a system instruction -- for disassembly only
1536 def SMC : ABI<0b0001, (outs), (ins i32imm:$opt), NoItinerary, "smc", "\t$opt",
1537 [/* For disassembly only; pattern left blank */]> {
1539 let Inst{23-4} = 0b01100000000000000111;
1540 let Inst{3-0} = opt;
1543 // Supervisor Call (Software Interrupt) -- for disassembly only
1544 let isCall = 1, Uses = [SP] in {
1545 def SVC : ABI<0b1111, (outs), (ins i32imm:$svc), IIC_Br, "svc", "\t$svc",
1546 [/* For disassembly only; pattern left blank */]> {
1548 let Inst{23-0} = svc;
1551 def : MnemonicAlias<"swi", "svc">;
1553 // Store Return State is a system instruction -- for disassembly only
1554 let isCodeGenOnly = 1 in { // FIXME: This should not use submode!
1555 def SRSW : ABXI<{1,0,0,?}, (outs), (ins ldstm_mode:$amode, i32imm:$mode),
1556 NoItinerary, "srs${amode}\tsp!, $mode",
1557 [/* For disassembly only; pattern left blank */]> {
1558 let Inst{31-28} = 0b1111;
1559 let Inst{22-20} = 0b110; // W = 1
1560 let Inst{19-8} = 0xd05;
1561 let Inst{7-5} = 0b000;
1564 def SRS : ABXI<{1,0,0,?}, (outs), (ins ldstm_mode:$amode, i32imm:$mode),
1565 NoItinerary, "srs${amode}\tsp, $mode",
1566 [/* For disassembly only; pattern left blank */]> {
1567 let Inst{31-28} = 0b1111;
1568 let Inst{22-20} = 0b100; // W = 0
1569 let Inst{19-8} = 0xd05;
1570 let Inst{7-5} = 0b000;
1573 // Return From Exception is a system instruction -- for disassembly only
1574 def RFEW : ABXI<{1,0,0,?}, (outs), (ins ldstm_mode:$amode, GPR:$base),
1575 NoItinerary, "rfe${amode}\t$base!",
1576 [/* For disassembly only; pattern left blank */]> {
1577 let Inst{31-28} = 0b1111;
1578 let Inst{22-20} = 0b011; // W = 1
1579 let Inst{15-0} = 0x0a00;
1582 def RFE : ABXI<{1,0,0,?}, (outs), (ins ldstm_mode:$amode, GPR:$base),
1583 NoItinerary, "rfe${amode}\t$base",
1584 [/* For disassembly only; pattern left blank */]> {
1585 let Inst{31-28} = 0b1111;
1586 let Inst{22-20} = 0b001; // W = 0
1587 let Inst{15-0} = 0x0a00;
1589 } // isCodeGenOnly = 1
1591 //===----------------------------------------------------------------------===//
1592 // Load / store Instructions.
1598 defm LDR : AI_ldr1<0, "ldr", IIC_iLoad_r, IIC_iLoad_si,
1599 UnOpFrag<(load node:$Src)>>;
1600 defm LDRB : AI_ldr1<1, "ldrb", IIC_iLoad_bh_r, IIC_iLoad_bh_si,
1601 UnOpFrag<(zextloadi8 node:$Src)>>;
1602 defm STR : AI_str1<0, "str", IIC_iStore_r, IIC_iStore_si,
1603 BinOpFrag<(store node:$LHS, node:$RHS)>>;
1604 defm STRB : AI_str1<1, "strb", IIC_iStore_bh_r, IIC_iStore_bh_si,
1605 BinOpFrag<(truncstorei8 node:$LHS, node:$RHS)>>;
1607 // Special LDR for loads from non-pc-relative constpools.
1608 let canFoldAsLoad = 1, mayLoad = 1, neverHasSideEffects = 1,
1609 isReMaterializable = 1 in
1610 def LDRcp : AI2ldst<0b010, 1, 0, (outs GPR:$Rt), (ins addrmode_imm12:$addr),
1611 AddrMode_i12, LdFrm, IIC_iLoad_r, "ldr", "\t$Rt, $addr",
1615 let Inst{23} = addr{12}; // U (add = ('U' == 1))
1616 let Inst{19-16} = 0b1111;
1617 let Inst{15-12} = Rt;
1618 let Inst{11-0} = addr{11-0}; // imm12
1621 // Loads with zero extension
1622 def LDRH : AI3ld<0b1011, 1, (outs GPR:$Rt), (ins addrmode3:$addr), LdMiscFrm,
1623 IIC_iLoad_bh_r, "ldrh", "\t$Rt, $addr",
1624 [(set GPR:$Rt, (zextloadi16 addrmode3:$addr))]>;
1626 // Loads with sign extension
1627 def LDRSH : AI3ld<0b1111, 1, (outs GPR:$Rt), (ins addrmode3:$addr), LdMiscFrm,
1628 IIC_iLoad_bh_r, "ldrsh", "\t$Rt, $addr",
1629 [(set GPR:$Rt, (sextloadi16 addrmode3:$addr))]>;
1631 def LDRSB : AI3ld<0b1101, 1, (outs GPR:$Rt), (ins addrmode3:$addr), LdMiscFrm,
1632 IIC_iLoad_bh_r, "ldrsb", "\t$Rt, $addr",
1633 [(set GPR:$Rt, (sextloadi8 addrmode3:$addr))]>;
1635 let mayLoad = 1, neverHasSideEffects = 1, hasExtraDefRegAllocReq = 1 in {
1637 def LDRD : AI3ld<0b1101, 0, (outs GPR:$Rd, GPR:$dst2),
1638 (ins addrmode3:$addr), LdMiscFrm,
1639 IIC_iLoad_d_r, "ldrd", "\t$Rd, $dst2, $addr",
1640 []>, Requires<[IsARM, HasV5TE]>;
1644 multiclass AI2_ldridx<bit isByte, string opc, InstrItinClass itin> {
1645 def _PRE : AI2ldstidx<1, isByte, 1, (outs GPR:$Rt, GPR:$Rn_wb),
1646 (ins addrmode2:$addr), IndexModePre, LdFrm, itin,
1647 opc, "\t$Rt, $addr!", "$addr.base = $Rn_wb", []> {
1649 // {13} 1 == Rm, 0 == imm12
1653 let Inst{25} = addr{13};
1654 let Inst{23} = addr{12};
1655 let Inst{19-16} = addr{17-14};
1656 let Inst{11-0} = addr{11-0};
1657 let AsmMatchConverter = "CvtLdWriteBackRegAddrMode2";
1659 def _POST : AI2ldstidx<1, isByte, 0, (outs GPR:$Rt, GPR:$Rn_wb),
1660 (ins GPR:$Rn, am2offset:$offset),
1661 IndexModePost, LdFrm, itin,
1662 opc, "\t$Rt, [$Rn], $offset", "$Rn = $Rn_wb", []> {
1663 // {13} 1 == Rm, 0 == imm12
1668 let Inst{25} = offset{13};
1669 let Inst{23} = offset{12};
1670 let Inst{19-16} = Rn;
1671 let Inst{11-0} = offset{11-0};
1675 let mayLoad = 1, neverHasSideEffects = 1 in {
1676 defm LDR : AI2_ldridx<0, "ldr", IIC_iLoad_ru>;
1677 defm LDRB : AI2_ldridx<1, "ldrb", IIC_iLoad_bh_ru>;
1680 multiclass AI3_ldridx<bits<4> op, bit op20, string opc, InstrItinClass itin> {
1681 def _PRE : AI3ldstidx<op, op20, 1, 1, (outs GPR:$Rt, GPR:$Rn_wb),
1682 (ins addrmode3:$addr), IndexModePre,
1684 opc, "\t$Rt, $addr!", "$addr.base = $Rn_wb", []> {
1686 let Inst{23} = addr{8}; // U bit
1687 let Inst{22} = addr{13}; // 1 == imm8, 0 == Rm
1688 let Inst{19-16} = addr{12-9}; // Rn
1689 let Inst{11-8} = addr{7-4}; // imm7_4/zero
1690 let Inst{3-0} = addr{3-0}; // imm3_0/Rm
1692 def _POST : AI3ldstidx<op, op20, 1, 0, (outs GPR:$Rt, GPR:$Rn_wb),
1693 (ins GPR:$Rn, am3offset:$offset), IndexModePost,
1695 opc, "\t$Rt, [$Rn], $offset", "$Rn = $Rn_wb", []> {
1698 let Inst{23} = offset{8}; // U bit
1699 let Inst{22} = offset{9}; // 1 == imm8, 0 == Rm
1700 let Inst{19-16} = Rn;
1701 let Inst{11-8} = offset{7-4}; // imm7_4/zero
1702 let Inst{3-0} = offset{3-0}; // imm3_0/Rm
1706 let mayLoad = 1, neverHasSideEffects = 1 in {
1707 defm LDRH : AI3_ldridx<0b1011, 1, "ldrh", IIC_iLoad_bh_ru>;
1708 defm LDRSH : AI3_ldridx<0b1111, 1, "ldrsh", IIC_iLoad_bh_ru>;
1709 defm LDRSB : AI3_ldridx<0b1101, 1, "ldrsb", IIC_iLoad_bh_ru>;
1710 let hasExtraDefRegAllocReq = 1 in {
1711 def LDRD_PRE : AI3ldstidx<0b1101, 0, 1, 1, (outs GPR:$Rt, GPR:$Rt2, GPR:$Rn_wb),
1712 (ins addrmode3:$addr), IndexModePre,
1713 LdMiscFrm, IIC_iLoad_d_ru,
1714 "ldrd", "\t$Rt, $Rt2, $addr!",
1715 "$addr.base = $Rn_wb", []> {
1717 let Inst{23} = addr{8}; // U bit
1718 let Inst{22} = addr{13}; // 1 == imm8, 0 == Rm
1719 let Inst{19-16} = addr{12-9}; // Rn
1720 let Inst{11-8} = addr{7-4}; // imm7_4/zero
1721 let Inst{3-0} = addr{3-0}; // imm3_0/Rm
1723 def LDRD_POST: AI3ldstidx<0b1101, 0, 1, 0, (outs GPR:$Rt, GPR:$Rt2, GPR:$Rn_wb),
1724 (ins GPR:$Rn, am3offset:$offset), IndexModePost,
1725 LdMiscFrm, IIC_iLoad_d_ru,
1726 "ldrd", "\t$Rt, $Rt2, [$Rn], $offset",
1727 "$Rn = $Rn_wb", []> {
1730 let Inst{23} = offset{8}; // U bit
1731 let Inst{22} = offset{9}; // 1 == imm8, 0 == Rm
1732 let Inst{19-16} = Rn;
1733 let Inst{11-8} = offset{7-4}; // imm7_4/zero
1734 let Inst{3-0} = offset{3-0}; // imm3_0/Rm
1736 } // hasExtraDefRegAllocReq = 1
1737 } // mayLoad = 1, neverHasSideEffects = 1
1739 // LDRT, LDRBT, LDRSBT, LDRHT, LDRSHT are for disassembly only.
1740 let mayLoad = 1, neverHasSideEffects = 1 in {
1741 def LDRT : AI2ldstidx<1, 0, 0, (outs GPR:$Rt, GPR:$base_wb),
1742 (ins addrmode2:$addr), IndexModePost, LdFrm, IIC_iLoad_ru,
1743 "ldrt", "\t$Rt, $addr", "$addr.base = $base_wb", []> {
1745 // {13} 1 == Rm, 0 == imm12
1749 let Inst{25} = addr{13};
1750 let Inst{23} = addr{12};
1751 let Inst{21} = 1; // overwrite
1752 let Inst{19-16} = addr{17-14};
1753 let Inst{11-0} = addr{11-0};
1754 let AsmMatchConverter = "CvtLdWriteBackRegAddrMode2";
1756 def LDRBT : AI2ldstidx<1, 1, 0, (outs GPR:$Rt, GPR:$base_wb),
1757 (ins addrmode2:$addr), IndexModePost, LdFrm, IIC_iLoad_bh_ru,
1758 "ldrbt", "\t$Rt, $addr", "$addr.base = $base_wb", []> {
1760 // {13} 1 == Rm, 0 == imm12
1764 let Inst{25} = addr{13};
1765 let Inst{23} = addr{12};
1766 let Inst{21} = 1; // overwrite
1767 let Inst{19-16} = addr{17-14};
1768 let Inst{11-0} = addr{11-0};
1769 let AsmMatchConverter = "CvtLdWriteBackRegAddrMode2";
1771 def LDRSBT : AI3ldstidxT<0b1101, 1, 1, 0, (outs GPR:$Rt, GPR:$base_wb),
1772 (ins addrmode3:$addr), IndexModePost, LdMiscFrm, IIC_iLoad_bh_ru,
1773 "ldrsbt", "\t$Rt, $addr", "$addr.base = $base_wb", []> {
1774 let Inst{21} = 1; // overwrite
1776 def LDRHT : AI3ldstidxT<0b1011, 1, 1, 0, (outs GPR:$Rt, GPR:$base_wb),
1777 (ins addrmode3:$addr), IndexModePost, LdMiscFrm, IIC_iLoad_bh_ru,
1778 "ldrht", "\t$Rt, $addr", "$addr.base = $base_wb", []> {
1779 let Inst{21} = 1; // overwrite
1781 def LDRSHT : AI3ldstidxT<0b1111, 1, 1, 0, (outs GPR:$Rt, GPR:$base_wb),
1782 (ins addrmode3:$addr), IndexModePost, LdMiscFrm, IIC_iLoad_bh_ru,
1783 "ldrsht", "\t$Rt, $addr", "$addr.base = $base_wb", []> {
1784 let Inst{21} = 1; // overwrite
1790 // Stores with truncate
1791 def STRH : AI3str<0b1011, (outs), (ins GPR:$Rt, addrmode3:$addr), StMiscFrm,
1792 IIC_iStore_bh_r, "strh", "\t$Rt, $addr",
1793 [(truncstorei16 GPR:$Rt, addrmode3:$addr)]>;
1796 let mayStore = 1, neverHasSideEffects = 1, hasExtraSrcRegAllocReq = 1 in
1797 def STRD : AI3str<0b1111, (outs), (ins GPR:$Rt, GPR:$src2, addrmode3:$addr),
1798 StMiscFrm, IIC_iStore_d_r,
1799 "strd", "\t$Rt, $src2, $addr", []>, Requires<[IsARM, HasV5TE]>;
1802 def STR_PRE : AI2stridx<0, 1, (outs GPR:$Rn_wb),
1803 (ins GPR:$Rt, GPR:$Rn, am2offset:$offset),
1804 IndexModePre, StFrm, IIC_iStore_ru,
1805 "str", "\t$Rt, [$Rn, $offset]!",
1806 "$Rn = $Rn_wb,@earlyclobber $Rn_wb",
1808 (pre_store GPR:$Rt, GPR:$Rn, am2offset:$offset))]>;
1810 def STR_POST : AI2stridx<0, 0, (outs GPR:$Rn_wb),
1811 (ins GPR:$Rt, GPR:$Rn, am2offset:$offset),
1812 IndexModePost, StFrm, IIC_iStore_ru,
1813 "str", "\t$Rt, [$Rn], $offset",
1814 "$Rn = $Rn_wb,@earlyclobber $Rn_wb",
1816 (post_store GPR:$Rt, GPR:$Rn, am2offset:$offset))]>;
1818 def STRB_PRE : AI2stridx<1, 1, (outs GPR:$Rn_wb),
1819 (ins GPR:$Rt, GPR:$Rn, am2offset:$offset),
1820 IndexModePre, StFrm, IIC_iStore_bh_ru,
1821 "strb", "\t$Rt, [$Rn, $offset]!",
1822 "$Rn = $Rn_wb,@earlyclobber $Rn_wb",
1823 [(set GPR:$Rn_wb, (pre_truncsti8 GPR:$Rt,
1824 GPR:$Rn, am2offset:$offset))]>;
1825 def STRB_POST: AI2stridx<1, 0, (outs GPR:$Rn_wb),
1826 (ins GPR:$Rt, GPR:$Rn, am2offset:$offset),
1827 IndexModePost, StFrm, IIC_iStore_bh_ru,
1828 "strb", "\t$Rt, [$Rn], $offset",
1829 "$Rn = $Rn_wb,@earlyclobber $Rn_wb",
1830 [(set GPR:$Rn_wb, (post_truncsti8 GPR:$Rt,
1831 GPR:$Rn, am2offset:$offset))]>;
1833 def STRH_PRE : AI3stridx<0b1011, 0, 1, (outs GPR:$Rn_wb),
1834 (ins GPR:$Rt, GPR:$Rn, am3offset:$offset),
1835 IndexModePre, StMiscFrm, IIC_iStore_ru,
1836 "strh", "\t$Rt, [$Rn, $offset]!",
1837 "$Rn = $Rn_wb,@earlyclobber $Rn_wb",
1839 (pre_truncsti16 GPR:$Rt, GPR:$Rn, am3offset:$offset))]>;
1841 def STRH_POST: AI3stridx<0b1011, 0, 0, (outs GPR:$Rn_wb),
1842 (ins GPR:$Rt, GPR:$Rn, am3offset:$offset),
1843 IndexModePost, StMiscFrm, IIC_iStore_bh_ru,
1844 "strh", "\t$Rt, [$Rn], $offset",
1845 "$Rn = $Rn_wb,@earlyclobber $Rn_wb",
1846 [(set GPR:$Rn_wb, (post_truncsti16 GPR:$Rt,
1847 GPR:$Rn, am3offset:$offset))]>;
1849 // For disassembly only
1850 let mayStore = 1, neverHasSideEffects = 1, hasExtraSrcRegAllocReq = 1 in {
1851 def STRD_PRE : AI3stdpr<(outs GPR:$base_wb),
1852 (ins GPR:$src1, GPR:$src2, GPR:$base, am3offset:$offset),
1853 StMiscFrm, IIC_iStore_d_ru,
1854 "strd", "\t$src1, $src2, [$base, $offset]!",
1855 "$base = $base_wb", []>;
1857 // For disassembly only
1858 def STRD_POST: AI3stdpo<(outs GPR:$base_wb),
1859 (ins GPR:$src1, GPR:$src2, GPR:$base, am3offset:$offset),
1860 StMiscFrm, IIC_iStore_d_ru,
1861 "strd", "\t$src1, $src2, [$base], $offset",
1862 "$base = $base_wb", []>;
1863 } // mayStore = 1, neverHasSideEffects = 1, hasExtraSrcRegAllocReq = 1
1865 // STRT, STRBT, and STRHT are for disassembly only.
1867 def STRT : AI2stridxT<0, 0, (outs GPR:$Rn_wb), (ins GPR:$Rt, addrmode2:$addr),
1868 IndexModePost, StFrm, IIC_iStore_ru,
1869 "strt", "\t$Rt, $addr", "$addr.base = $Rn_wb",
1870 [/* For disassembly only; pattern left blank */]> {
1871 let Inst{21} = 1; // overwrite
1872 let AsmMatchConverter = "CvtStWriteBackRegAddrMode2";
1875 def STRBT : AI2stridxT<1, 0, (outs GPR:$Rn_wb), (ins GPR:$Rt, addrmode2:$addr),
1876 IndexModePost, StFrm, IIC_iStore_bh_ru,
1877 "strbt", "\t$Rt, $addr", "$addr.base = $Rn_wb",
1878 [/* For disassembly only; pattern left blank */]> {
1879 let Inst{21} = 1; // overwrite
1880 let AsmMatchConverter = "CvtStWriteBackRegAddrMode2";
1883 def STRHT: AI3sthpo<(outs GPR:$base_wb), (ins GPR:$Rt, addrmode3:$addr),
1884 StMiscFrm, IIC_iStore_bh_ru,
1885 "strht", "\t$Rt, $addr", "$addr.base = $base_wb",
1886 [/* For disassembly only; pattern left blank */]> {
1887 let Inst{21} = 1; // overwrite
1888 let AsmMatchConverter = "CvtStWriteBackRegAddrMode3";
1891 //===----------------------------------------------------------------------===//
1892 // Load / store multiple Instructions.
1895 multiclass arm_ldst_mult<string asm, bit L_bit, Format f,
1896 InstrItinClass itin, InstrItinClass itin_upd> {
1898 AXI4<(outs), (ins GPR:$Rn, pred:$p, reglist:$regs, variable_ops),
1899 IndexModeNone, f, itin,
1900 !strconcat(asm, "ia${p}\t$Rn, $regs"), "", []> {
1901 let Inst{24-23} = 0b01; // Increment After
1902 let Inst{21} = 0; // No writeback
1903 let Inst{20} = L_bit;
1906 AXI4<(outs GPR:$wb), (ins GPR:$Rn, pred:$p, reglist:$regs, variable_ops),
1907 IndexModeUpd, f, itin_upd,
1908 !strconcat(asm, "ia${p}\t$Rn!, $regs"), "$Rn = $wb", []> {
1909 let Inst{24-23} = 0b01; // Increment After
1910 let Inst{21} = 1; // Writeback
1911 let Inst{20} = L_bit;
1914 AXI4<(outs), (ins GPR:$Rn, pred:$p, reglist:$regs, variable_ops),
1915 IndexModeNone, f, itin,
1916 !strconcat(asm, "da${p}\t$Rn, $regs"), "", []> {
1917 let Inst{24-23} = 0b00; // Decrement After
1918 let Inst{21} = 0; // No writeback
1919 let Inst{20} = L_bit;
1922 AXI4<(outs GPR:$wb), (ins GPR:$Rn, pred:$p, reglist:$regs, variable_ops),
1923 IndexModeUpd, f, itin_upd,
1924 !strconcat(asm, "da${p}\t$Rn!, $regs"), "$Rn = $wb", []> {
1925 let Inst{24-23} = 0b00; // Decrement After
1926 let Inst{21} = 1; // Writeback
1927 let Inst{20} = L_bit;
1930 AXI4<(outs), (ins GPR:$Rn, pred:$p, reglist:$regs, variable_ops),
1931 IndexModeNone, f, itin,
1932 !strconcat(asm, "db${p}\t$Rn, $regs"), "", []> {
1933 let Inst{24-23} = 0b10; // Decrement Before
1934 let Inst{21} = 0; // No writeback
1935 let Inst{20} = L_bit;
1938 AXI4<(outs GPR:$wb), (ins GPR:$Rn, pred:$p, reglist:$regs, variable_ops),
1939 IndexModeUpd, f, itin_upd,
1940 !strconcat(asm, "db${p}\t$Rn!, $regs"), "$Rn = $wb", []> {
1941 let Inst{24-23} = 0b10; // Decrement Before
1942 let Inst{21} = 1; // Writeback
1943 let Inst{20} = L_bit;
1946 AXI4<(outs), (ins GPR:$Rn, pred:$p, reglist:$regs, variable_ops),
1947 IndexModeNone, f, itin,
1948 !strconcat(asm, "ib${p}\t$Rn, $regs"), "", []> {
1949 let Inst{24-23} = 0b11; // Increment Before
1950 let Inst{21} = 0; // No writeback
1951 let Inst{20} = L_bit;
1954 AXI4<(outs GPR:$wb), (ins GPR:$Rn, pred:$p, reglist:$regs, variable_ops),
1955 IndexModeUpd, f, itin_upd,
1956 !strconcat(asm, "ib${p}\t$Rn!, $regs"), "$Rn = $wb", []> {
1957 let Inst{24-23} = 0b11; // Increment Before
1958 let Inst{21} = 1; // Writeback
1959 let Inst{20} = L_bit;
1963 let neverHasSideEffects = 1 in {
1965 let mayLoad = 1, hasExtraDefRegAllocReq = 1 in
1966 defm LDM : arm_ldst_mult<"ldm", 1, LdStMulFrm, IIC_iLoad_m, IIC_iLoad_mu>;
1968 let mayStore = 1, hasExtraSrcRegAllocReq = 1 in
1969 defm STM : arm_ldst_mult<"stm", 0, LdStMulFrm, IIC_iStore_m, IIC_iStore_mu>;
1971 } // neverHasSideEffects
1973 // Load / Store Multiple Mnemonic Aliases
1974 def : MnemonicAlias<"ldm", "ldmia">;
1975 def : MnemonicAlias<"stm", "stmia">;
1977 // FIXME: remove when we have a way to marking a MI with these properties.
1978 // FIXME: Should pc be an implicit operand like PICADD, etc?
1979 let isReturn = 1, isTerminator = 1, isBarrier = 1, mayLoad = 1,
1980 hasExtraDefRegAllocReq = 1, isCodeGenOnly = 1 in
1981 def LDMIA_RET : ARMPseudoInst<(outs GPR:$wb), (ins GPR:$Rn, pred:$p,
1982 reglist:$regs, variable_ops),
1983 Size4Bytes, IIC_iLoad_mBr, []>,
1984 RegConstraint<"$Rn = $wb">;
1986 //===----------------------------------------------------------------------===//
1987 // Move Instructions.
1990 let neverHasSideEffects = 1 in
1991 def MOVr : AsI1<0b1101, (outs GPR:$Rd), (ins GPR:$Rm), DPFrm, IIC_iMOVr,
1992 "mov", "\t$Rd, $Rm", []>, UnaryDP {
1996 let Inst{19-16} = 0b0000;
1997 let Inst{11-4} = 0b00000000;
2000 let Inst{15-12} = Rd;
2003 // A version for the smaller set of tail call registers.
2004 let neverHasSideEffects = 1 in
2005 def MOVr_TC : AsI1<0b1101, (outs tcGPR:$Rd), (ins tcGPR:$Rm), DPFrm,
2006 IIC_iMOVr, "mov", "\t$Rd, $Rm", []>, UnaryDP {
2010 let Inst{11-4} = 0b00000000;
2013 let Inst{15-12} = Rd;
2016 def MOVs : AsI1<0b1101, (outs GPR:$Rd), (ins shift_so_reg:$src),
2017 DPSoRegFrm, IIC_iMOVsr,
2018 "mov", "\t$Rd, $src", [(set GPR:$Rd, shift_so_reg:$src)]>,
2022 let Inst{15-12} = Rd;
2023 let Inst{19-16} = 0b0000;
2024 let Inst{11-0} = src;
2028 let isReMaterializable = 1, isAsCheapAsAMove = 1, isMoveImm = 1 in
2029 def MOVi : AsI1<0b1101, (outs GPR:$Rd), (ins so_imm:$imm), DPFrm, IIC_iMOVi,
2030 "mov", "\t$Rd, $imm", [(set GPR:$Rd, so_imm:$imm)]>, UnaryDP {
2034 let Inst{15-12} = Rd;
2035 let Inst{19-16} = 0b0000;
2036 let Inst{11-0} = imm;
2039 let isReMaterializable = 1, isAsCheapAsAMove = 1, isMoveImm = 1 in
2040 def MOVi16 : AI1<0b1000, (outs GPR:$Rd), (ins i32imm_hilo16:$imm),
2042 "movw", "\t$Rd, $imm",
2043 [(set GPR:$Rd, imm0_65535:$imm)]>,
2044 Requires<[IsARM, HasV6T2]>, UnaryDP {
2047 let Inst{15-12} = Rd;
2048 let Inst{11-0} = imm{11-0};
2049 let Inst{19-16} = imm{15-12};
2054 def MOVi16_ga_pcrel : PseudoInst<(outs GPR:$Rd),
2055 (ins i32imm:$addr, pclabel:$id), IIC_iMOVi, []>;
2057 let Constraints = "$src = $Rd" in {
2058 def MOVTi16 : AI1<0b1010, (outs GPR:$Rd), (ins GPR:$src, i32imm_hilo16:$imm),
2060 "movt", "\t$Rd, $imm",
2062 (or (and GPR:$src, 0xffff),
2063 lo16AllZero:$imm))]>, UnaryDP,
2064 Requires<[IsARM, HasV6T2]> {
2067 let Inst{15-12} = Rd;
2068 let Inst{11-0} = imm{11-0};
2069 let Inst{19-16} = imm{15-12};
2074 def MOVTi16_ga_pcrel : PseudoInst<(outs GPR:$Rd),
2075 (ins GPR:$src, i32imm:$addr, pclabel:$id), IIC_iMOVi, []>;
2079 def : ARMPat<(or GPR:$src, 0xffff0000), (MOVTi16 GPR:$src, 0xffff)>,
2080 Requires<[IsARM, HasV6T2]>;
2082 let Uses = [CPSR] in
2083 def RRX: PseudoInst<(outs GPR:$Rd), (ins GPR:$Rm), IIC_iMOVsi,
2084 [(set GPR:$Rd, (ARMrrx GPR:$Rm))]>, UnaryDP,
2087 // These aren't really mov instructions, but we have to define them this way
2088 // due to flag operands.
2090 let Defs = [CPSR] in {
2091 def MOVsrl_flag : PseudoInst<(outs GPR:$dst), (ins GPR:$src), IIC_iMOVsi,
2092 [(set GPR:$dst, (ARMsrl_flag GPR:$src))]>, UnaryDP,
2094 def MOVsra_flag : PseudoInst<(outs GPR:$dst), (ins GPR:$src), IIC_iMOVsi,
2095 [(set GPR:$dst, (ARMsra_flag GPR:$src))]>, UnaryDP,
2099 //===----------------------------------------------------------------------===//
2100 // Extend Instructions.
2105 defm SXTB : AI_ext_rrot<0b01101010,
2106 "sxtb", UnOpFrag<(sext_inreg node:$Src, i8)>>;
2107 defm SXTH : AI_ext_rrot<0b01101011,
2108 "sxth", UnOpFrag<(sext_inreg node:$Src, i16)>>;
2110 defm SXTAB : AI_exta_rrot<0b01101010,
2111 "sxtab", BinOpFrag<(add node:$LHS, (sext_inreg node:$RHS, i8))>>;
2112 defm SXTAH : AI_exta_rrot<0b01101011,
2113 "sxtah", BinOpFrag<(add node:$LHS, (sext_inreg node:$RHS,i16))>>;
2115 // For disassembly only
2116 defm SXTB16 : AI_ext_rrot_np<0b01101000, "sxtb16">;
2118 // For disassembly only
2119 defm SXTAB16 : AI_exta_rrot_np<0b01101000, "sxtab16">;
2123 let AddedComplexity = 16 in {
2124 defm UXTB : AI_ext_rrot<0b01101110,
2125 "uxtb" , UnOpFrag<(and node:$Src, 0x000000FF)>>;
2126 defm UXTH : AI_ext_rrot<0b01101111,
2127 "uxth" , UnOpFrag<(and node:$Src, 0x0000FFFF)>>;
2128 defm UXTB16 : AI_ext_rrot<0b01101100,
2129 "uxtb16", UnOpFrag<(and node:$Src, 0x00FF00FF)>>;
2131 // FIXME: This pattern incorrectly assumes the shl operator is a rotate.
2132 // The transformation should probably be done as a combiner action
2133 // instead so we can include a check for masking back in the upper
2134 // eight bits of the source into the lower eight bits of the result.
2135 //def : ARMV6Pat<(and (shl GPR:$Src, (i32 8)), 0xFF00FF),
2136 // (UXTB16r_rot GPR:$Src, 24)>;
2137 def : ARMV6Pat<(and (srl GPR:$Src, (i32 8)), 0xFF00FF),
2138 (UXTB16r_rot GPR:$Src, 8)>;
2140 defm UXTAB : AI_exta_rrot<0b01101110, "uxtab",
2141 BinOpFrag<(add node:$LHS, (and node:$RHS, 0x00FF))>>;
2142 defm UXTAH : AI_exta_rrot<0b01101111, "uxtah",
2143 BinOpFrag<(add node:$LHS, (and node:$RHS, 0xFFFF))>>;
2146 // This isn't safe in general, the add is two 16-bit units, not a 32-bit add.
2147 // For disassembly only
2148 defm UXTAB16 : AI_exta_rrot_np<0b01101100, "uxtab16">;
2151 def SBFX : I<(outs GPR:$Rd),
2152 (ins GPR:$Rn, imm0_31:$lsb, imm0_31_m1:$width),
2153 AddrMode1, Size4Bytes, IndexModeNone, DPFrm, IIC_iUNAsi,
2154 "sbfx", "\t$Rd, $Rn, $lsb, $width", "", []>,
2155 Requires<[IsARM, HasV6T2]> {
2160 let Inst{27-21} = 0b0111101;
2161 let Inst{6-4} = 0b101;
2162 let Inst{20-16} = width;
2163 let Inst{15-12} = Rd;
2164 let Inst{11-7} = lsb;
2168 def UBFX : I<(outs GPR:$Rd),
2169 (ins GPR:$Rn, imm0_31:$lsb, imm0_31_m1:$width),
2170 AddrMode1, Size4Bytes, IndexModeNone, DPFrm, IIC_iUNAsi,
2171 "ubfx", "\t$Rd, $Rn, $lsb, $width", "", []>,
2172 Requires<[IsARM, HasV6T2]> {
2177 let Inst{27-21} = 0b0111111;
2178 let Inst{6-4} = 0b101;
2179 let Inst{20-16} = width;
2180 let Inst{15-12} = Rd;
2181 let Inst{11-7} = lsb;
2185 //===----------------------------------------------------------------------===//
2186 // Arithmetic Instructions.
2189 defm ADD : AsI1_bin_irs<0b0100, "add",
2190 IIC_iALUi, IIC_iALUr, IIC_iALUsr,
2191 BinOpFrag<(add node:$LHS, node:$RHS)>, 1>;
2192 defm SUB : AsI1_bin_irs<0b0010, "sub",
2193 IIC_iALUi, IIC_iALUr, IIC_iALUsr,
2194 BinOpFrag<(sub node:$LHS, node:$RHS)>>;
2196 // ADD and SUB with 's' bit set.
2197 defm ADDS : AI1_bin_s_irs<0b0100, "adds",
2198 IIC_iALUi, IIC_iALUr, IIC_iALUsr,
2199 BinOpFrag<(addc node:$LHS, node:$RHS)>, 1>;
2200 defm SUBS : AI1_bin_s_irs<0b0010, "subs",
2201 IIC_iALUi, IIC_iALUr, IIC_iALUsr,
2202 BinOpFrag<(subc node:$LHS, node:$RHS)>>;
2204 defm ADC : AI1_adde_sube_irs<0b0101, "adc",
2205 BinOpFrag<(adde_dead_carry node:$LHS, node:$RHS)>, 1>;
2206 defm SBC : AI1_adde_sube_irs<0b0110, "sbc",
2207 BinOpFrag<(sube_dead_carry node:$LHS, node:$RHS)>>;
2209 // ADC and SUBC with 's' bit set.
2210 let usesCustomInserter = 1 in {
2211 defm ADCS : AI1_adde_sube_s_irs<
2212 BinOpFrag<(adde_live_carry node:$LHS, node:$RHS)>, 1>;
2213 defm SBCS : AI1_adde_sube_s_irs<
2214 BinOpFrag<(sube_live_carry node:$LHS, node:$RHS) >>;
2217 def RSBri : AsI1<0b0011, (outs GPR:$Rd), (ins GPR:$Rn, so_imm:$imm), DPFrm,
2218 IIC_iALUi, "rsb", "\t$Rd, $Rn, $imm",
2219 [(set GPR:$Rd, (sub so_imm:$imm, GPR:$Rn))]> {
2224 let Inst{15-12} = Rd;
2225 let Inst{19-16} = Rn;
2226 let Inst{11-0} = imm;
2229 // The reg/reg form is only defined for the disassembler; for codegen it is
2230 // equivalent to SUBrr.
2231 def RSBrr : AsI1<0b0011, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm), DPFrm,
2232 IIC_iALUr, "rsb", "\t$Rd, $Rn, $Rm",
2233 [/* For disassembly only; pattern left blank */]> {
2237 let Inst{11-4} = 0b00000000;
2240 let Inst{15-12} = Rd;
2241 let Inst{19-16} = Rn;
2244 def RSBrs : AsI1<0b0011, (outs GPR:$Rd), (ins GPR:$Rn, so_reg:$shift),
2245 DPSoRegFrm, IIC_iALUsr, "rsb", "\t$Rd, $Rn, $shift",
2246 [(set GPR:$Rd, (sub so_reg:$shift, GPR:$Rn))]> {
2251 let Inst{11-0} = shift;
2252 let Inst{15-12} = Rd;
2253 let Inst{19-16} = Rn;
2256 // RSB with 's' bit set.
2257 // NOTE: CPSR def omitted because it will be handled by the custom inserter.
2258 let usesCustomInserter = 1 in {
2259 def RSBSri : ARMPseudoInst<(outs GPR:$Rd), (ins GPR:$Rn, so_imm:$imm),
2260 Size4Bytes, IIC_iALUi,
2261 [(set GPR:$Rd, (subc so_imm:$imm, GPR:$Rn))]>;
2262 def RSBSrr : ARMPseudoInst<(outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm),
2263 Size4Bytes, IIC_iALUr,
2264 [/* For disassembly only; pattern left blank */]>;
2265 def RSBSrs : ARMPseudoInst<(outs GPR:$Rd), (ins GPR:$Rn, so_reg:$shift),
2266 Size4Bytes, IIC_iALUsr,
2267 [(set GPR:$Rd, (subc so_reg:$shift, GPR:$Rn))]>;
2270 let Uses = [CPSR] in {
2271 def RSCri : AsI1<0b0111, (outs GPR:$Rd), (ins GPR:$Rn, so_imm:$imm),
2272 DPFrm, IIC_iALUi, "rsc", "\t$Rd, $Rn, $imm",
2273 [(set GPR:$Rd, (sube_dead_carry so_imm:$imm, GPR:$Rn))]>,
2279 let Inst{15-12} = Rd;
2280 let Inst{19-16} = Rn;
2281 let Inst{11-0} = imm;
2283 // The reg/reg form is only defined for the disassembler; for codegen it is
2284 // equivalent to SUBrr.
2285 def RSCrr : AsI1<0b0111, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm),
2286 DPFrm, IIC_iALUr, "rsc", "\t$Rd, $Rn, $Rm",
2287 [/* For disassembly only; pattern left blank */]> {
2291 let Inst{11-4} = 0b00000000;
2294 let Inst{15-12} = Rd;
2295 let Inst{19-16} = Rn;
2297 def RSCrs : AsI1<0b0111, (outs GPR:$Rd), (ins GPR:$Rn, so_reg:$shift),
2298 DPSoRegFrm, IIC_iALUsr, "rsc", "\t$Rd, $Rn, $shift",
2299 [(set GPR:$Rd, (sube_dead_carry so_reg:$shift, GPR:$Rn))]>,
2305 let Inst{11-0} = shift;
2306 let Inst{15-12} = Rd;
2307 let Inst{19-16} = Rn;
2311 // NOTE: CPSR def omitted because it will be handled by the custom inserter.
2312 let usesCustomInserter = 1, Uses = [CPSR] in {
2313 def RSCSri : ARMPseudoInst<(outs GPR:$Rd), (ins GPR:$Rn, so_imm:$imm),
2314 Size4Bytes, IIC_iALUi,
2315 [(set GPR:$Rd, (sube_dead_carry so_imm:$imm, GPR:$Rn))]>;
2316 def RSCSrs : ARMPseudoInst<(outs GPR:$Rd), (ins GPR:$Rn, so_reg:$shift),
2317 Size4Bytes, IIC_iALUsr,
2318 [(set GPR:$Rd, (sube_dead_carry so_reg:$shift, GPR:$Rn))]>;
2321 // (sub X, imm) gets canonicalized to (add X, -imm). Match this form.
2322 // The assume-no-carry-in form uses the negation of the input since add/sub
2323 // assume opposite meanings of the carry flag (i.e., carry == !borrow).
2324 // See the definition of AddWithCarry() in the ARM ARM A2.2.1 for the gory
2326 def : ARMPat<(add GPR:$src, so_imm_neg:$imm),
2327 (SUBri GPR:$src, so_imm_neg:$imm)>;
2328 def : ARMPat<(addc GPR:$src, so_imm_neg:$imm),
2329 (SUBSri GPR:$src, so_imm_neg:$imm)>;
2330 // The with-carry-in form matches bitwise not instead of the negation.
2331 // Effectively, the inverse interpretation of the carry flag already accounts
2332 // for part of the negation.
2333 def : ARMPat<(adde_dead_carry GPR:$src, so_imm_not:$imm),
2334 (SBCri GPR:$src, so_imm_not:$imm)>;
2335 def : ARMPat<(adde_live_carry GPR:$src, so_imm_not:$imm),
2336 (SBCSri GPR:$src, so_imm_not:$imm)>;
2338 // Note: These are implemented in C++ code, because they have to generate
2339 // ADD/SUBrs instructions, which use a complex pattern that a xform function
2341 // (mul X, 2^n+1) -> (add (X << n), X)
2342 // (mul X, 2^n-1) -> (rsb X, (X << n))
2344 // ARM Arithmetic Instruction -- for disassembly only
2345 // GPR:$dst = GPR:$a op GPR:$b
2346 class AAI<bits<8> op27_20, bits<8> op11_4, string opc,
2347 list<dag> pattern = [/* For disassembly only; pattern left blank */],
2348 dag iops = (ins GPR:$Rn, GPR:$Rm), string asm = "\t$Rd, $Rn, $Rm">
2349 : AI<(outs GPR:$Rd), iops, DPFrm, IIC_iALUr, opc, asm, pattern> {
2353 let Inst{27-20} = op27_20;
2354 let Inst{11-4} = op11_4;
2355 let Inst{19-16} = Rn;
2356 let Inst{15-12} = Rd;
2360 // Saturating add/subtract -- for disassembly only
2362 def QADD : AAI<0b00010000, 0b00000101, "qadd",
2363 [(set GPR:$Rd, (int_arm_qadd GPR:$Rm, GPR:$Rn))],
2364 (ins GPR:$Rm, GPR:$Rn), "\t$Rd, $Rm, $Rn">;
2365 def QSUB : AAI<0b00010010, 0b00000101, "qsub",
2366 [(set GPR:$Rd, (int_arm_qsub GPR:$Rm, GPR:$Rn))],
2367 (ins GPR:$Rm, GPR:$Rn), "\t$Rd, $Rm, $Rn">;
2368 def QDADD : AAI<0b00010100, 0b00000101, "qdadd", [], (ins GPR:$Rm, GPR:$Rn),
2370 def QDSUB : AAI<0b00010110, 0b00000101, "qdsub", [], (ins GPR:$Rm, GPR:$Rn),
2373 def QADD16 : AAI<0b01100010, 0b11110001, "qadd16">;
2374 def QADD8 : AAI<0b01100010, 0b11111001, "qadd8">;
2375 def QASX : AAI<0b01100010, 0b11110011, "qasx">;
2376 def QSAX : AAI<0b01100010, 0b11110101, "qsax">;
2377 def QSUB16 : AAI<0b01100010, 0b11110111, "qsub16">;
2378 def QSUB8 : AAI<0b01100010, 0b11111111, "qsub8">;
2379 def UQADD16 : AAI<0b01100110, 0b11110001, "uqadd16">;
2380 def UQADD8 : AAI<0b01100110, 0b11111001, "uqadd8">;
2381 def UQASX : AAI<0b01100110, 0b11110011, "uqasx">;
2382 def UQSAX : AAI<0b01100110, 0b11110101, "uqsax">;
2383 def UQSUB16 : AAI<0b01100110, 0b11110111, "uqsub16">;
2384 def UQSUB8 : AAI<0b01100110, 0b11111111, "uqsub8">;
2386 // Signed/Unsigned add/subtract -- for disassembly only
2388 def SASX : AAI<0b01100001, 0b11110011, "sasx">;
2389 def SADD16 : AAI<0b01100001, 0b11110001, "sadd16">;
2390 def SADD8 : AAI<0b01100001, 0b11111001, "sadd8">;
2391 def SSAX : AAI<0b01100001, 0b11110101, "ssax">;
2392 def SSUB16 : AAI<0b01100001, 0b11110111, "ssub16">;
2393 def SSUB8 : AAI<0b01100001, 0b11111111, "ssub8">;
2394 def UASX : AAI<0b01100101, 0b11110011, "uasx">;
2395 def UADD16 : AAI<0b01100101, 0b11110001, "uadd16">;
2396 def UADD8 : AAI<0b01100101, 0b11111001, "uadd8">;
2397 def USAX : AAI<0b01100101, 0b11110101, "usax">;
2398 def USUB16 : AAI<0b01100101, 0b11110111, "usub16">;
2399 def USUB8 : AAI<0b01100101, 0b11111111, "usub8">;
2401 // Signed/Unsigned halving add/subtract -- for disassembly only
2403 def SHASX : AAI<0b01100011, 0b11110011, "shasx">;
2404 def SHADD16 : AAI<0b01100011, 0b11110001, "shadd16">;
2405 def SHADD8 : AAI<0b01100011, 0b11111001, "shadd8">;
2406 def SHSAX : AAI<0b01100011, 0b11110101, "shsax">;
2407 def SHSUB16 : AAI<0b01100011, 0b11110111, "shsub16">;
2408 def SHSUB8 : AAI<0b01100011, 0b11111111, "shsub8">;
2409 def UHASX : AAI<0b01100111, 0b11110011, "uhasx">;
2410 def UHADD16 : AAI<0b01100111, 0b11110001, "uhadd16">;
2411 def UHADD8 : AAI<0b01100111, 0b11111001, "uhadd8">;
2412 def UHSAX : AAI<0b01100111, 0b11110101, "uhsax">;
2413 def UHSUB16 : AAI<0b01100111, 0b11110111, "uhsub16">;
2414 def UHSUB8 : AAI<0b01100111, 0b11111111, "uhsub8">;
2416 // Unsigned Sum of Absolute Differences [and Accumulate] -- for disassembly only
2418 def USAD8 : AI<(outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm),
2419 MulFrm /* for convenience */, NoItinerary, "usad8",
2420 "\t$Rd, $Rn, $Rm", []>,
2421 Requires<[IsARM, HasV6]> {
2425 let Inst{27-20} = 0b01111000;
2426 let Inst{15-12} = 0b1111;
2427 let Inst{7-4} = 0b0001;
2428 let Inst{19-16} = Rd;
2429 let Inst{11-8} = Rm;
2432 def USADA8 : AI<(outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm, GPR:$Ra),
2433 MulFrm /* for convenience */, NoItinerary, "usada8",
2434 "\t$Rd, $Rn, $Rm, $Ra", []>,
2435 Requires<[IsARM, HasV6]> {
2440 let Inst{27-20} = 0b01111000;
2441 let Inst{7-4} = 0b0001;
2442 let Inst{19-16} = Rd;
2443 let Inst{15-12} = Ra;
2444 let Inst{11-8} = Rm;
2448 // Signed/Unsigned saturate -- for disassembly only
2450 def SSAT : AI<(outs GPR:$Rd), (ins i32imm:$sat_imm, GPR:$a, shift_imm:$sh),
2451 SatFrm, NoItinerary, "ssat", "\t$Rd, $sat_imm, $a$sh",
2452 [/* For disassembly only; pattern left blank */]> {
2457 let Inst{27-21} = 0b0110101;
2458 let Inst{5-4} = 0b01;
2459 let Inst{20-16} = sat_imm;
2460 let Inst{15-12} = Rd;
2461 let Inst{11-7} = sh{7-3};
2462 let Inst{6} = sh{0};
2466 def SSAT16 : AI<(outs GPR:$Rd), (ins i32imm:$sat_imm, GPR:$Rn), SatFrm,
2467 NoItinerary, "ssat16", "\t$Rd, $sat_imm, $Rn",
2468 [/* For disassembly only; pattern left blank */]> {
2472 let Inst{27-20} = 0b01101010;
2473 let Inst{11-4} = 0b11110011;
2474 let Inst{15-12} = Rd;
2475 let Inst{19-16} = sat_imm;
2479 def USAT : AI<(outs GPR:$Rd), (ins i32imm:$sat_imm, GPR:$a, shift_imm:$sh),
2480 SatFrm, NoItinerary, "usat", "\t$Rd, $sat_imm, $a$sh",
2481 [/* For disassembly only; pattern left blank */]> {
2486 let Inst{27-21} = 0b0110111;
2487 let Inst{5-4} = 0b01;
2488 let Inst{15-12} = Rd;
2489 let Inst{11-7} = sh{7-3};
2490 let Inst{6} = sh{0};
2491 let Inst{20-16} = sat_imm;
2495 def USAT16 : AI<(outs GPR:$Rd), (ins i32imm:$sat_imm, GPR:$a), SatFrm,
2496 NoItinerary, "usat16", "\t$Rd, $sat_imm, $a",
2497 [/* For disassembly only; pattern left blank */]> {
2501 let Inst{27-20} = 0b01101110;
2502 let Inst{11-4} = 0b11110011;
2503 let Inst{15-12} = Rd;
2504 let Inst{19-16} = sat_imm;
2508 def : ARMV6Pat<(int_arm_ssat GPR:$a, imm:$pos), (SSAT imm:$pos, GPR:$a, 0)>;
2509 def : ARMV6Pat<(int_arm_usat GPR:$a, imm:$pos), (USAT imm:$pos, GPR:$a, 0)>;
2511 //===----------------------------------------------------------------------===//
2512 // Bitwise Instructions.
2515 defm AND : AsI1_bin_irs<0b0000, "and",
2516 IIC_iBITi, IIC_iBITr, IIC_iBITsr,
2517 BinOpFrag<(and node:$LHS, node:$RHS)>, 1>;
2518 defm ORR : AsI1_bin_irs<0b1100, "orr",
2519 IIC_iBITi, IIC_iBITr, IIC_iBITsr,
2520 BinOpFrag<(or node:$LHS, node:$RHS)>, 1>;
2521 defm EOR : AsI1_bin_irs<0b0001, "eor",
2522 IIC_iBITi, IIC_iBITr, IIC_iBITsr,
2523 BinOpFrag<(xor node:$LHS, node:$RHS)>, 1>;
2524 defm BIC : AsI1_bin_irs<0b1110, "bic",
2525 IIC_iBITi, IIC_iBITr, IIC_iBITsr,
2526 BinOpFrag<(and node:$LHS, (not node:$RHS))>>;
2528 def BFC : I<(outs GPR:$Rd), (ins GPR:$src, bf_inv_mask_imm:$imm),
2529 AddrMode1, Size4Bytes, IndexModeNone, DPFrm, IIC_iUNAsi,
2530 "bfc", "\t$Rd, $imm", "$src = $Rd",
2531 [(set GPR:$Rd, (and GPR:$src, bf_inv_mask_imm:$imm))]>,
2532 Requires<[IsARM, HasV6T2]> {
2535 let Inst{27-21} = 0b0111110;
2536 let Inst{6-0} = 0b0011111;
2537 let Inst{15-12} = Rd;
2538 let Inst{11-7} = imm{4-0}; // lsb
2539 let Inst{20-16} = imm{9-5}; // width
2542 // A8.6.18 BFI - Bitfield insert (Encoding A1)
2543 def BFI : I<(outs GPR:$Rd), (ins GPR:$src, GPR:$Rn, bf_inv_mask_imm:$imm),
2544 AddrMode1, Size4Bytes, IndexModeNone, DPFrm, IIC_iUNAsi,
2545 "bfi", "\t$Rd, $Rn, $imm", "$src = $Rd",
2546 [(set GPR:$Rd, (ARMbfi GPR:$src, GPR:$Rn,
2547 bf_inv_mask_imm:$imm))]>,
2548 Requires<[IsARM, HasV6T2]> {
2552 let Inst{27-21} = 0b0111110;
2553 let Inst{6-4} = 0b001; // Rn: Inst{3-0} != 15
2554 let Inst{15-12} = Rd;
2555 let Inst{11-7} = imm{4-0}; // lsb
2556 let Inst{20-16} = imm{9-5}; // width
2560 // GNU as only supports this form of bfi (w/ 4 arguments)
2561 let isAsmParserOnly = 1 in
2562 def BFI4p : I<(outs GPR:$Rd), (ins GPR:$src, GPR:$Rn,
2563 lsb_pos_imm:$lsb, width_imm:$width),
2564 AddrMode1, Size4Bytes, IndexModeNone, DPFrm, IIC_iUNAsi,
2565 "bfi", "\t$Rd, $Rn, $lsb, $width", "$src = $Rd",
2566 []>, Requires<[IsARM, HasV6T2]> {
2571 let Inst{27-21} = 0b0111110;
2572 let Inst{6-4} = 0b001; // Rn: Inst{3-0} != 15
2573 let Inst{15-12} = Rd;
2574 let Inst{11-7} = lsb;
2575 let Inst{20-16} = width; // Custom encoder => lsb+width-1
2579 def MVNr : AsI1<0b1111, (outs GPR:$Rd), (ins GPR:$Rm), DPFrm, IIC_iMVNr,
2580 "mvn", "\t$Rd, $Rm",
2581 [(set GPR:$Rd, (not GPR:$Rm))]>, UnaryDP {
2585 let Inst{19-16} = 0b0000;
2586 let Inst{11-4} = 0b00000000;
2587 let Inst{15-12} = Rd;
2590 def MVNs : AsI1<0b1111, (outs GPR:$Rd), (ins so_reg:$shift), DPSoRegFrm,
2591 IIC_iMVNsr, "mvn", "\t$Rd, $shift",
2592 [(set GPR:$Rd, (not so_reg:$shift))]>, UnaryDP {
2596 let Inst{19-16} = 0b0000;
2597 let Inst{15-12} = Rd;
2598 let Inst{11-0} = shift;
2600 let isReMaterializable = 1, isAsCheapAsAMove = 1, isMoveImm = 1 in
2601 def MVNi : AsI1<0b1111, (outs GPR:$Rd), (ins so_imm:$imm), DPFrm,
2602 IIC_iMVNi, "mvn", "\t$Rd, $imm",
2603 [(set GPR:$Rd, so_imm_not:$imm)]>,UnaryDP {
2607 let Inst{19-16} = 0b0000;
2608 let Inst{15-12} = Rd;
2609 let Inst{11-0} = imm;
2612 def : ARMPat<(and GPR:$src, so_imm_not:$imm),
2613 (BICri GPR:$src, so_imm_not:$imm)>;
2615 //===----------------------------------------------------------------------===//
2616 // Multiply Instructions.
2618 class AsMul1I32<bits<7> opcod, dag oops, dag iops, InstrItinClass itin,
2619 string opc, string asm, list<dag> pattern>
2620 : AsMul1I<opcod, oops, iops, itin, opc, asm, pattern> {
2624 let Inst{19-16} = Rd;
2625 let Inst{11-8} = Rm;
2628 class AsMul1I64<bits<7> opcod, dag oops, dag iops, InstrItinClass itin,
2629 string opc, string asm, list<dag> pattern>
2630 : AsMul1I<opcod, oops, iops, itin, opc, asm, pattern> {
2635 let Inst{19-16} = RdHi;
2636 let Inst{15-12} = RdLo;
2637 let Inst{11-8} = Rm;
2641 let isCommutable = 1 in {
2642 let Constraints = "@earlyclobber $Rd" in
2643 def MULv5: ARMPseudoInst<(outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm,
2644 pred:$p, cc_out:$s),
2645 Size4Bytes, IIC_iMUL32,
2646 [(set GPR:$Rd, (mul GPR:$Rn, GPR:$Rm))]>,
2647 Requires<[IsARM, NoV6]>;
2649 def MUL : AsMul1I32<0b0000000, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm),
2650 IIC_iMUL32, "mul", "\t$Rd, $Rn, $Rm",
2651 [(set GPR:$Rd, (mul GPR:$Rn, GPR:$Rm))]>,
2652 Requires<[IsARM, HasV6]> {
2653 let Inst{15-12} = 0b0000;
2657 let Constraints = "@earlyclobber $Rd" in
2658 def MLAv5: ARMPseudoInst<(outs GPR:$Rd),
2659 (ins GPR:$Rn, GPR:$Rm, GPR:$Ra, pred:$p, cc_out:$s),
2660 Size4Bytes, IIC_iMAC32,
2661 [(set GPR:$Rd, (add (mul GPR:$Rn, GPR:$Rm), GPR:$Ra))]>,
2662 Requires<[IsARM, NoV6]> {
2664 let Inst{15-12} = Ra;
2666 def MLA : AsMul1I32<0b0000001, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm, GPR:$Ra),
2667 IIC_iMAC32, "mla", "\t$Rd, $Rn, $Rm, $Ra",
2668 [(set GPR:$Rd, (add (mul GPR:$Rn, GPR:$Rm), GPR:$Ra))]>,
2669 Requires<[IsARM, HasV6]> {
2671 let Inst{15-12} = Ra;
2674 def MLS : AMul1I<0b0000011, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm, GPR:$Ra),
2675 IIC_iMAC32, "mls", "\t$Rd, $Rn, $Rm, $Ra",
2676 [(set GPR:$Rd, (sub GPR:$Ra, (mul GPR:$Rn, GPR:$Rm)))]>,
2677 Requires<[IsARM, HasV6T2]> {
2682 let Inst{19-16} = Rd;
2683 let Inst{15-12} = Ra;
2684 let Inst{11-8} = Rm;
2688 // Extra precision multiplies with low / high results
2690 let neverHasSideEffects = 1 in {
2691 let isCommutable = 1 in {
2692 let Constraints = "@earlyclobber $RdLo,@earlyclobber $RdHi" in {
2693 def SMULLv5 : ARMPseudoInst<(outs GPR:$RdLo, GPR:$RdHi),
2694 (ins GPR:$Rn, GPR:$Rm, pred:$p, cc_out:$s),
2695 Size4Bytes, IIC_iMUL64, []>,
2696 Requires<[IsARM, NoV6]>;
2698 def UMULLv5 : ARMPseudoInst<(outs GPR:$RdLo, GPR:$RdHi),
2699 (ins GPR:$Rn, GPR:$Rm, pred:$p, cc_out:$s),
2700 Size4Bytes, IIC_iMUL64, []>,
2701 Requires<[IsARM, NoV6]>;
2704 def SMULL : AsMul1I64<0b0000110, (outs GPR:$RdLo, GPR:$RdHi),
2705 (ins GPR:$Rn, GPR:$Rm), IIC_iMUL64,
2706 "smull", "\t$RdLo, $RdHi, $Rn, $Rm", []>,
2707 Requires<[IsARM, HasV6]>;
2709 def UMULL : AsMul1I64<0b0000100, (outs GPR:$RdLo, GPR:$RdHi),
2710 (ins GPR:$Rn, GPR:$Rm), IIC_iMUL64,
2711 "umull", "\t$RdLo, $RdHi, $Rn, $Rm", []>,
2712 Requires<[IsARM, HasV6]>;
2715 // Multiply + accumulate
2716 let Constraints = "@earlyclobber $RdLo,@earlyclobber $RdHi" in {
2717 def SMLALv5 : ARMPseudoInst<(outs GPR:$RdLo, GPR:$RdHi),
2718 (ins GPR:$Rn, GPR:$Rm, pred:$p, cc_out:$s),
2719 Size4Bytes, IIC_iMAC64, []>,
2720 Requires<[IsARM, NoV6]>;
2721 def UMLALv5 : ARMPseudoInst<(outs GPR:$RdLo, GPR:$RdHi),
2722 (ins GPR:$Rn, GPR:$Rm, pred:$p, cc_out:$s),
2723 Size4Bytes, IIC_iMAC64, []>,
2724 Requires<[IsARM, NoV6]>;
2725 def UMAALv5 : ARMPseudoInst<(outs GPR:$RdLo, GPR:$RdHi),
2726 (ins GPR:$Rn, GPR:$Rm, pred:$p, cc_out:$s),
2727 Size4Bytes, IIC_iMAC64, []>,
2728 Requires<[IsARM, NoV6]>;
2732 def SMLAL : AsMul1I64<0b0000111, (outs GPR:$RdLo, GPR:$RdHi),
2733 (ins GPR:$Rn, GPR:$Rm), IIC_iMAC64,
2734 "smlal", "\t$RdLo, $RdHi, $Rn, $Rm", []>,
2735 Requires<[IsARM, HasV6]>;
2736 def UMLAL : AsMul1I64<0b0000101, (outs GPR:$RdLo, GPR:$RdHi),
2737 (ins GPR:$Rn, GPR:$Rm), IIC_iMAC64,
2738 "umlal", "\t$RdLo, $RdHi, $Rn, $Rm", []>,
2739 Requires<[IsARM, HasV6]>;
2741 def UMAAL : AMul1I <0b0000010, (outs GPR:$RdLo, GPR:$RdHi),
2742 (ins GPR:$Rn, GPR:$Rm), IIC_iMAC64,
2743 "umaal", "\t$RdLo, $RdHi, $Rn, $Rm", []>,
2744 Requires<[IsARM, HasV6]> {
2749 let Inst{19-16} = RdLo;
2750 let Inst{15-12} = RdHi;
2751 let Inst{11-8} = Rm;
2754 } // neverHasSideEffects
2756 // Most significant word multiply
2757 def SMMUL : AMul2I <0b0111010, 0b0001, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm),
2758 IIC_iMUL32, "smmul", "\t$Rd, $Rn, $Rm",
2759 [(set GPR:$Rd, (mulhs GPR:$Rn, GPR:$Rm))]>,
2760 Requires<[IsARM, HasV6]> {
2761 let Inst{15-12} = 0b1111;
2764 def SMMULR : AMul2I <0b0111010, 0b0011, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm),
2765 IIC_iMUL32, "smmulr", "\t$Rd, $Rn, $Rm",
2766 [/* For disassembly only; pattern left blank */]>,
2767 Requires<[IsARM, HasV6]> {
2768 let Inst{15-12} = 0b1111;
2771 def SMMLA : AMul2Ia <0b0111010, 0b0001, (outs GPR:$Rd),
2772 (ins GPR:$Rn, GPR:$Rm, GPR:$Ra),
2773 IIC_iMAC32, "smmla", "\t$Rd, $Rn, $Rm, $Ra",
2774 [(set GPR:$Rd, (add (mulhs GPR:$Rn, GPR:$Rm), GPR:$Ra))]>,
2775 Requires<[IsARM, HasV6]>;
2777 def SMMLAR : AMul2Ia <0b0111010, 0b0011, (outs GPR:$Rd),
2778 (ins GPR:$Rn, GPR:$Rm, GPR:$Ra),
2779 IIC_iMAC32, "smmlar", "\t$Rd, $Rn, $Rm, $Ra",
2780 [/* For disassembly only; pattern left blank */]>,
2781 Requires<[IsARM, HasV6]>;
2783 def SMMLS : AMul2Ia <0b0111010, 0b1101, (outs GPR:$Rd),
2784 (ins GPR:$Rn, GPR:$Rm, GPR:$Ra),
2785 IIC_iMAC32, "smmls", "\t$Rd, $Rn, $Rm, $Ra",
2786 [(set GPR:$Rd, (sub GPR:$Ra, (mulhs GPR:$Rn, GPR:$Rm)))]>,
2787 Requires<[IsARM, HasV6]>;
2789 def SMMLSR : AMul2Ia <0b0111010, 0b1111, (outs GPR:$Rd),
2790 (ins GPR:$Rn, GPR:$Rm, GPR:$Ra),
2791 IIC_iMAC32, "smmlsr", "\t$Rd, $Rn, $Rm, $Ra",
2792 [/* For disassembly only; pattern left blank */]>,
2793 Requires<[IsARM, HasV6]>;
2795 multiclass AI_smul<string opc, PatFrag opnode> {
2796 def BB : AMulxyI<0b0001011, 0b00, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm),
2797 IIC_iMUL16, !strconcat(opc, "bb"), "\t$Rd, $Rn, $Rm",
2798 [(set GPR:$Rd, (opnode (sext_inreg GPR:$Rn, i16),
2799 (sext_inreg GPR:$Rm, i16)))]>,
2800 Requires<[IsARM, HasV5TE]>;
2802 def BT : AMulxyI<0b0001011, 0b10, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm),
2803 IIC_iMUL16, !strconcat(opc, "bt"), "\t$Rd, $Rn, $Rm",
2804 [(set GPR:$Rd, (opnode (sext_inreg GPR:$Rn, i16),
2805 (sra GPR:$Rm, (i32 16))))]>,
2806 Requires<[IsARM, HasV5TE]>;
2808 def TB : AMulxyI<0b0001011, 0b01, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm),
2809 IIC_iMUL16, !strconcat(opc, "tb"), "\t$Rd, $Rn, $Rm",
2810 [(set GPR:$Rd, (opnode (sra GPR:$Rn, (i32 16)),
2811 (sext_inreg GPR:$Rm, i16)))]>,
2812 Requires<[IsARM, HasV5TE]>;
2814 def TT : AMulxyI<0b0001011, 0b11, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm),
2815 IIC_iMUL16, !strconcat(opc, "tt"), "\t$Rd, $Rn, $Rm",
2816 [(set GPR:$Rd, (opnode (sra GPR:$Rn, (i32 16)),
2817 (sra GPR:$Rm, (i32 16))))]>,
2818 Requires<[IsARM, HasV5TE]>;
2820 def WB : AMulxyI<0b0001001, 0b01, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm),
2821 IIC_iMUL16, !strconcat(opc, "wb"), "\t$Rd, $Rn, $Rm",
2822 [(set GPR:$Rd, (sra (opnode GPR:$Rn,
2823 (sext_inreg GPR:$Rm, i16)), (i32 16)))]>,
2824 Requires<[IsARM, HasV5TE]>;
2826 def WT : AMulxyI<0b0001001, 0b11, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm),
2827 IIC_iMUL16, !strconcat(opc, "wt"), "\t$Rd, $Rn, $Rm",
2828 [(set GPR:$Rd, (sra (opnode GPR:$Rn,
2829 (sra GPR:$Rm, (i32 16))), (i32 16)))]>,
2830 Requires<[IsARM, HasV5TE]>;
2834 multiclass AI_smla<string opc, PatFrag opnode> {
2835 def BB : AMulxyIa<0b0001000, 0b00, (outs GPR:$Rd),
2836 (ins GPR:$Rn, GPR:$Rm, GPR:$Ra),
2837 IIC_iMAC16, !strconcat(opc, "bb"), "\t$Rd, $Rn, $Rm, $Ra",
2838 [(set GPR:$Rd, (add GPR:$Ra,
2839 (opnode (sext_inreg GPR:$Rn, i16),
2840 (sext_inreg GPR:$Rm, i16))))]>,
2841 Requires<[IsARM, HasV5TE]>;
2843 def BT : AMulxyIa<0b0001000, 0b10, (outs GPR:$Rd),
2844 (ins GPR:$Rn, GPR:$Rm, GPR:$Ra),
2845 IIC_iMAC16, !strconcat(opc, "bt"), "\t$Rd, $Rn, $Rm, $Ra",
2846 [(set GPR:$Rd, (add GPR:$Ra, (opnode (sext_inreg GPR:$Rn, i16),
2847 (sra GPR:$Rm, (i32 16)))))]>,
2848 Requires<[IsARM, HasV5TE]>;
2850 def TB : AMulxyIa<0b0001000, 0b01, (outs GPR:$Rd),
2851 (ins GPR:$Rn, GPR:$Rm, GPR:$Ra),
2852 IIC_iMAC16, !strconcat(opc, "tb"), "\t$Rd, $Rn, $Rm, $Ra",
2853 [(set GPR:$Rd, (add GPR:$Ra, (opnode (sra GPR:$Rn, (i32 16)),
2854 (sext_inreg GPR:$Rm, i16))))]>,
2855 Requires<[IsARM, HasV5TE]>;
2857 def TT : AMulxyIa<0b0001000, 0b11, (outs GPR:$Rd),
2858 (ins GPR:$Rn, GPR:$Rm, GPR:$Ra),
2859 IIC_iMAC16, !strconcat(opc, "tt"), "\t$Rd, $Rn, $Rm, $Ra",
2860 [(set GPR:$Rd, (add GPR:$Ra, (opnode (sra GPR:$Rn, (i32 16)),
2861 (sra GPR:$Rm, (i32 16)))))]>,
2862 Requires<[IsARM, HasV5TE]>;
2864 def WB : AMulxyIa<0b0001001, 0b00, (outs GPR:$Rd),
2865 (ins GPR:$Rn, GPR:$Rm, GPR:$Ra),
2866 IIC_iMAC16, !strconcat(opc, "wb"), "\t$Rd, $Rn, $Rm, $Ra",
2867 [(set GPR:$Rd, (add GPR:$Ra, (sra (opnode GPR:$Rn,
2868 (sext_inreg GPR:$Rm, i16)), (i32 16))))]>,
2869 Requires<[IsARM, HasV5TE]>;
2871 def WT : AMulxyIa<0b0001001, 0b10, (outs GPR:$Rd),
2872 (ins GPR:$Rn, GPR:$Rm, GPR:$Ra),
2873 IIC_iMAC16, !strconcat(opc, "wt"), "\t$Rd, $Rn, $Rm, $Ra",
2874 [(set GPR:$Rd, (add GPR:$Ra, (sra (opnode GPR:$Rn,
2875 (sra GPR:$Rm, (i32 16))), (i32 16))))]>,
2876 Requires<[IsARM, HasV5TE]>;
2879 defm SMUL : AI_smul<"smul", BinOpFrag<(mul node:$LHS, node:$RHS)>>;
2880 defm SMLA : AI_smla<"smla", BinOpFrag<(mul node:$LHS, node:$RHS)>>;
2882 // Halfword multiply accumulate long: SMLAL<x><y> -- for disassembly only
2883 def SMLALBB : AMulxyI64<0b0001010, 0b00, (outs GPR:$RdLo, GPR:$RdHi),
2884 (ins GPR:$Rn, GPR:$Rm),
2885 IIC_iMAC64, "smlalbb", "\t$RdLo, $RdHi, $Rn, $Rm",
2886 [/* For disassembly only; pattern left blank */]>,
2887 Requires<[IsARM, HasV5TE]>;
2889 def SMLALBT : AMulxyI64<0b0001010, 0b10, (outs GPR:$RdLo, GPR:$RdHi),
2890 (ins GPR:$Rn, GPR:$Rm),
2891 IIC_iMAC64, "smlalbt", "\t$RdLo, $RdHi, $Rn, $Rm",
2892 [/* For disassembly only; pattern left blank */]>,
2893 Requires<[IsARM, HasV5TE]>;
2895 def SMLALTB : AMulxyI64<0b0001010, 0b01, (outs GPR:$RdLo, GPR:$RdHi),
2896 (ins GPR:$Rn, GPR:$Rm),
2897 IIC_iMAC64, "smlaltb", "\t$RdLo, $RdHi, $Rn, $Rm",
2898 [/* For disassembly only; pattern left blank */]>,
2899 Requires<[IsARM, HasV5TE]>;
2901 def SMLALTT : AMulxyI64<0b0001010, 0b11, (outs GPR:$RdLo, GPR:$RdHi),
2902 (ins GPR:$Rn, GPR:$Rm),
2903 IIC_iMAC64, "smlaltt", "\t$RdLo, $RdHi, $Rn, $Rm",
2904 [/* For disassembly only; pattern left blank */]>,
2905 Requires<[IsARM, HasV5TE]>;
2907 // Helper class for AI_smld -- for disassembly only
2908 class AMulDualIbase<bit long, bit sub, bit swap, dag oops, dag iops,
2909 InstrItinClass itin, string opc, string asm>
2910 : AI<oops, iops, MulFrm, itin, opc, asm, []>, Requires<[IsARM, HasV6]> {
2917 let Inst{21-20} = 0b00;
2918 let Inst{22} = long;
2919 let Inst{27-23} = 0b01110;
2920 let Inst{11-8} = Rm;
2923 class AMulDualI<bit long, bit sub, bit swap, dag oops, dag iops,
2924 InstrItinClass itin, string opc, string asm>
2925 : AMulDualIbase<long, sub, swap, oops, iops, itin, opc, asm> {
2927 let Inst{15-12} = 0b1111;
2928 let Inst{19-16} = Rd;
2930 class AMulDualIa<bit long, bit sub, bit swap, dag oops, dag iops,
2931 InstrItinClass itin, string opc, string asm>
2932 : AMulDualIbase<long, sub, swap, oops, iops, itin, opc, asm> {
2934 let Inst{15-12} = Ra;
2936 class AMulDualI64<bit long, bit sub, bit swap, dag oops, dag iops,
2937 InstrItinClass itin, string opc, string asm>
2938 : AMulDualIbase<long, sub, swap, oops, iops, itin, opc, asm> {
2941 let Inst{19-16} = RdHi;
2942 let Inst{15-12} = RdLo;
2945 multiclass AI_smld<bit sub, string opc> {
2947 def D : AMulDualIa<0, sub, 0, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm, GPR:$Ra),
2948 NoItinerary, !strconcat(opc, "d"), "\t$Rd, $Rn, $Rm, $Ra">;
2950 def DX: AMulDualIa<0, sub, 1, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm, GPR:$Ra),
2951 NoItinerary, !strconcat(opc, "dx"), "\t$Rd, $Rn, $Rm, $Ra">;
2953 def LD: AMulDualI64<1, sub, 0, (outs GPR:$RdLo,GPR:$RdHi),
2954 (ins GPR:$Rn, GPR:$Rm), NoItinerary,
2955 !strconcat(opc, "ld"), "\t$RdLo, $RdHi, $Rn, $Rm">;
2957 def LDX : AMulDualI64<1, sub, 1, (outs GPR:$RdLo,GPR:$RdHi),
2958 (ins GPR:$Rn, GPR:$Rm), NoItinerary,
2959 !strconcat(opc, "ldx"),"\t$RdLo, $RdHi, $Rn, $Rm">;
2963 defm SMLA : AI_smld<0, "smla">;
2964 defm SMLS : AI_smld<1, "smls">;
2966 multiclass AI_sdml<bit sub, string opc> {
2968 def D : AMulDualI<0, sub, 0, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm),
2969 NoItinerary, !strconcat(opc, "d"), "\t$Rd, $Rn, $Rm">;
2970 def DX : AMulDualI<0, sub, 1, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm),
2971 NoItinerary, !strconcat(opc, "dx"), "\t$Rd, $Rn, $Rm">;
2974 defm SMUA : AI_sdml<0, "smua">;
2975 defm SMUS : AI_sdml<1, "smus">;
2977 //===----------------------------------------------------------------------===//
2978 // Misc. Arithmetic Instructions.
2981 def CLZ : AMiscA1I<0b000010110, 0b0001, (outs GPR:$Rd), (ins GPR:$Rm),
2982 IIC_iUNAr, "clz", "\t$Rd, $Rm",
2983 [(set GPR:$Rd, (ctlz GPR:$Rm))]>, Requires<[IsARM, HasV5T]>;
2985 def RBIT : AMiscA1I<0b01101111, 0b0011, (outs GPR:$Rd), (ins GPR:$Rm),
2986 IIC_iUNAr, "rbit", "\t$Rd, $Rm",
2987 [(set GPR:$Rd, (ARMrbit GPR:$Rm))]>,
2988 Requires<[IsARM, HasV6T2]>;
2990 def REV : AMiscA1I<0b01101011, 0b0011, (outs GPR:$Rd), (ins GPR:$Rm),
2991 IIC_iUNAr, "rev", "\t$Rd, $Rm",
2992 [(set GPR:$Rd, (bswap GPR:$Rm))]>, Requires<[IsARM, HasV6]>;
2994 def REV16 : AMiscA1I<0b01101011, 0b1011, (outs GPR:$Rd), (ins GPR:$Rm),
2995 IIC_iUNAr, "rev16", "\t$Rd, $Rm",
2997 (or (and (srl GPR:$Rm, (i32 8)), 0xFF),
2998 (or (and (shl GPR:$Rm, (i32 8)), 0xFF00),
2999 (or (and (srl GPR:$Rm, (i32 8)), 0xFF0000),
3000 (and (shl GPR:$Rm, (i32 8)), 0xFF000000)))))]>,
3001 Requires<[IsARM, HasV6]>;
3003 def REVSH : AMiscA1I<0b01101111, 0b1011, (outs GPR:$Rd), (ins GPR:$Rm),
3004 IIC_iUNAr, "revsh", "\t$Rd, $Rm",
3007 (or (srl GPR:$Rm, (i32 8)),
3008 (shl GPR:$Rm, (i32 8))), i16))]>,
3009 Requires<[IsARM, HasV6]>;
3011 def : ARMV6Pat<(sext_inreg (or (srl (and GPR:$Rm, 0xFF00), (i32 8)),
3012 (shl GPR:$Rm, (i32 8))), i16),
3015 // Need the AddedComplexity or else MOVs + REV would be chosen.
3016 let AddedComplexity = 5 in
3017 def : ARMV6Pat<(sra (bswap GPR:$Rm), (i32 16)), (REVSH GPR:$Rm)>;
3019 def lsl_shift_imm : SDNodeXForm<imm, [{
3020 unsigned Sh = ARM_AM::getSORegOpc(ARM_AM::lsl, N->getZExtValue());
3021 return CurDAG->getTargetConstant(Sh, MVT::i32);
3024 def lsl_amt : ImmLeaf<i32, [{
3025 return Imm > 0 && Imm < 32;
3028 def PKHBT : APKHI<0b01101000, 0, (outs GPR:$Rd),
3029 (ins GPR:$Rn, GPR:$Rm, shift_imm:$sh),
3030 IIC_iALUsi, "pkhbt", "\t$Rd, $Rn, $Rm$sh",
3031 [(set GPR:$Rd, (or (and GPR:$Rn, 0xFFFF),
3032 (and (shl GPR:$Rm, lsl_amt:$sh),
3034 Requires<[IsARM, HasV6]>;
3036 // Alternate cases for PKHBT where identities eliminate some nodes.
3037 def : ARMV6Pat<(or (and GPR:$Rn, 0xFFFF), (and GPR:$Rm, 0xFFFF0000)),
3038 (PKHBT GPR:$Rn, GPR:$Rm, 0)>;
3039 def : ARMV6Pat<(or (and GPR:$Rn, 0xFFFF), (shl GPR:$Rm, imm16_31:$sh)),
3040 (PKHBT GPR:$Rn, GPR:$Rm, (lsl_shift_imm imm16_31:$sh))>;
3042 def asr_shift_imm : SDNodeXForm<imm, [{
3043 unsigned Sh = ARM_AM::getSORegOpc(ARM_AM::asr, N->getZExtValue());
3044 return CurDAG->getTargetConstant(Sh, MVT::i32);
3047 def asr_amt : ImmLeaf<i32, [{
3048 return Imm > 0 && Imm <= 32;
3051 // Note: Shifts of 1-15 bits will be transformed to srl instead of sra and
3052 // will match the pattern below.
3053 def PKHTB : APKHI<0b01101000, 1, (outs GPR:$Rd),
3054 (ins GPR:$Rn, GPR:$Rm, shift_imm:$sh),
3055 IIC_iBITsi, "pkhtb", "\t$Rd, $Rn, $Rm$sh",
3056 [(set GPR:$Rd, (or (and GPR:$Rn, 0xFFFF0000),
3057 (and (sra GPR:$Rm, asr_amt:$sh),
3059 Requires<[IsARM, HasV6]>;
3061 // Alternate cases for PKHTB where identities eliminate some nodes. Note that
3062 // a shift amount of 0 is *not legal* here, it is PKHBT instead.
3063 def : ARMV6Pat<(or (and GPR:$src1, 0xFFFF0000), (srl GPR:$src2, imm16_31:$sh)),
3064 (PKHTB GPR:$src1, GPR:$src2, (asr_shift_imm imm16_31:$sh))>;
3065 def : ARMV6Pat<(or (and GPR:$src1, 0xFFFF0000),
3066 (and (srl GPR:$src2, imm1_15:$sh), 0xFFFF)),
3067 (PKHTB GPR:$src1, GPR:$src2, (asr_shift_imm imm1_15:$sh))>;
3069 //===----------------------------------------------------------------------===//
3070 // Comparison Instructions...
3073 defm CMP : AI1_cmp_irs<0b1010, "cmp",
3074 IIC_iCMPi, IIC_iCMPr, IIC_iCMPsr,
3075 BinOpFrag<(ARMcmp node:$LHS, node:$RHS)>>;
3077 // ARMcmpZ can re-use the above instruction definitions.
3078 def : ARMPat<(ARMcmpZ GPR:$src, so_imm:$imm),
3079 (CMPri GPR:$src, so_imm:$imm)>;
3080 def : ARMPat<(ARMcmpZ GPR:$src, GPR:$rhs),
3081 (CMPrr GPR:$src, GPR:$rhs)>;
3082 def : ARMPat<(ARMcmpZ GPR:$src, so_reg:$rhs),
3083 (CMPrs GPR:$src, so_reg:$rhs)>;
3085 // FIXME: We have to be careful when using the CMN instruction and comparison
3086 // with 0. One would expect these two pieces of code should give identical
3102 // However, the CMN gives the *opposite* result when r1 is 0. This is because
3103 // the carry flag is set in the CMP case but not in the CMN case. In short, the
3104 // CMP instruction doesn't perform a truncate of the (logical) NOT of 0 plus the
3105 // value of r0 and the carry bit (because the "carry bit" parameter to
3106 // AddWithCarry is defined as 1 in this case, the carry flag will always be set
3107 // when r0 >= 0). The CMN instruction doesn't perform a NOT of 0 so there is
3108 // never a "carry" when this AddWithCarry is performed (because the "carry bit"
3109 // parameter to AddWithCarry is defined as 0).
3111 // When x is 0 and unsigned:
3115 // ~x + 1 = 0x1 0000 0000
3116 // (-x = 0) != (0x1 0000 0000 = ~x + 1)
3118 // Therefore, we should disable CMN when comparing against zero, until we can
3119 // limit when the CMN instruction is used (when we know that the RHS is not 0 or
3120 // when it's a comparison which doesn't look at the 'carry' flag).
3122 // (See the ARM docs for the "AddWithCarry" pseudo-code.)
3124 // This is related to <rdar://problem/7569620>.
3126 //defm CMN : AI1_cmp_irs<0b1011, "cmn",
3127 // BinOpFrag<(ARMcmp node:$LHS,(ineg node:$RHS))>>;
3129 // Note that TST/TEQ don't set all the same flags that CMP does!
3130 defm TST : AI1_cmp_irs<0b1000, "tst",
3131 IIC_iTSTi, IIC_iTSTr, IIC_iTSTsr,
3132 BinOpFrag<(ARMcmpZ (and_su node:$LHS, node:$RHS), 0)>, 1>;
3133 defm TEQ : AI1_cmp_irs<0b1001, "teq",
3134 IIC_iTSTi, IIC_iTSTr, IIC_iTSTsr,
3135 BinOpFrag<(ARMcmpZ (xor_su node:$LHS, node:$RHS), 0)>, 1>;
3137 defm CMNz : AI1_cmp_irs<0b1011, "cmn",
3138 IIC_iCMPi, IIC_iCMPr, IIC_iCMPsr,
3139 BinOpFrag<(ARMcmpZ node:$LHS,(ineg node:$RHS))>>;
3141 //def : ARMPat<(ARMcmp GPR:$src, so_imm_neg:$imm),
3142 // (CMNri GPR:$src, so_imm_neg:$imm)>;
3144 def : ARMPat<(ARMcmpZ GPR:$src, so_imm_neg:$imm),
3145 (CMNzri GPR:$src, so_imm_neg:$imm)>;
3147 // Pseudo i64 compares for some floating point compares.
3148 let usesCustomInserter = 1, isBranch = 1, isTerminator = 1,
3150 def BCCi64 : PseudoInst<(outs),
3151 (ins i32imm:$cc, GPR:$lhs1, GPR:$lhs2, GPR:$rhs1, GPR:$rhs2, brtarget:$dst),
3153 [(ARMBcci64 imm:$cc, GPR:$lhs1, GPR:$lhs2, GPR:$rhs1, GPR:$rhs2, bb:$dst)]>;
3155 def BCCZi64 : PseudoInst<(outs),
3156 (ins i32imm:$cc, GPR:$lhs1, GPR:$lhs2, brtarget:$dst), IIC_Br,
3157 [(ARMBcci64 imm:$cc, GPR:$lhs1, GPR:$lhs2, 0, 0, bb:$dst)]>;
3158 } // usesCustomInserter
3161 // Conditional moves
3162 // FIXME: should be able to write a pattern for ARMcmov, but can't use
3163 // a two-value operand where a dag node expects two operands. :(
3164 let neverHasSideEffects = 1 in {
3165 def MOVCCr : ARMPseudoInst<(outs GPR:$Rd), (ins GPR:$false, GPR:$Rm, pred:$p),
3166 Size4Bytes, IIC_iCMOVr,
3167 [/*(set GPR:$Rd, (ARMcmov GPR:$false, GPR:$Rm, imm:$cc, CCR:$ccr))*/]>,
3168 RegConstraint<"$false = $Rd">;
3169 def MOVCCs : ARMPseudoInst<(outs GPR:$Rd),
3170 (ins GPR:$false, so_reg:$shift, pred:$p),
3171 Size4Bytes, IIC_iCMOVsr,
3172 [/*(set GPR:$Rd, (ARMcmov GPR:$false, so_reg:$shift, imm:$cc, CCR:$ccr))*/]>,
3173 RegConstraint<"$false = $Rd">;
3175 let isMoveImm = 1 in
3176 def MOVCCi16 : ARMPseudoInst<(outs GPR:$Rd),
3177 (ins GPR:$false, i32imm_hilo16:$imm, pred:$p),
3178 Size4Bytes, IIC_iMOVi,
3180 RegConstraint<"$false = $Rd">, Requires<[IsARM, HasV6T2]>;
3182 let isMoveImm = 1 in
3183 def MOVCCi : ARMPseudoInst<(outs GPR:$Rd),
3184 (ins GPR:$false, so_imm:$imm, pred:$p),
3185 Size4Bytes, IIC_iCMOVi,
3186 [/*(set GPR:$Rd, (ARMcmov GPR:$false, so_imm:$imm, imm:$cc, CCR:$ccr))*/]>,
3187 RegConstraint<"$false = $Rd">;
3189 // Two instruction predicate mov immediate.
3190 let isMoveImm = 1 in
3191 def MOVCCi32imm : ARMPseudoInst<(outs GPR:$Rd),
3192 (ins GPR:$false, i32imm:$src, pred:$p),
3193 Size8Bytes, IIC_iCMOVix2, []>, RegConstraint<"$false = $Rd">;
3195 let isMoveImm = 1 in
3196 def MVNCCi : ARMPseudoInst<(outs GPR:$Rd),
3197 (ins GPR:$false, so_imm:$imm, pred:$p),
3198 Size4Bytes, IIC_iCMOVi,
3199 [/*(set GPR:$Rd, (ARMcmov GPR:$false, so_imm_not:$imm, imm:$cc, CCR:$ccr))*/]>,
3200 RegConstraint<"$false = $Rd">;
3201 } // neverHasSideEffects
3203 //===----------------------------------------------------------------------===//
3204 // Atomic operations intrinsics
3207 def memb_opt : Operand<i32> {
3208 let PrintMethod = "printMemBOption";
3209 let ParserMatchClass = MemBarrierOptOperand;
3212 // memory barriers protect the atomic sequences
3213 let hasSideEffects = 1 in {
3214 def DMB : AInoP<(outs), (ins memb_opt:$opt), MiscFrm, NoItinerary,
3215 "dmb", "\t$opt", [(ARMMemBarrier (i32 imm:$opt))]>,
3216 Requires<[IsARM, HasDB]> {
3218 let Inst{31-4} = 0xf57ff05;
3219 let Inst{3-0} = opt;
3223 def DSB : AInoP<(outs), (ins memb_opt:$opt), MiscFrm, NoItinerary,
3225 [/* For disassembly only; pattern left blank */]>,
3226 Requires<[IsARM, HasDB]> {
3228 let Inst{31-4} = 0xf57ff04;
3229 let Inst{3-0} = opt;
3232 // ISB has only full system option -- for disassembly only
3233 def ISB : AInoP<(outs), (ins), MiscFrm, NoItinerary, "isb", "", []>,
3234 Requires<[IsARM, HasDB]> {
3235 let Inst{31-4} = 0xf57ff06;
3236 let Inst{3-0} = 0b1111;
3239 let usesCustomInserter = 1 in {
3240 let Uses = [CPSR] in {
3241 def ATOMIC_LOAD_ADD_I8 : PseudoInst<
3242 (outs GPR:$dst), (ins GPR:$ptr, GPR:$incr), NoItinerary,
3243 [(set GPR:$dst, (atomic_load_add_8 GPR:$ptr, GPR:$incr))]>;
3244 def ATOMIC_LOAD_SUB_I8 : PseudoInst<
3245 (outs GPR:$dst), (ins GPR:$ptr, GPR:$incr), NoItinerary,
3246 [(set GPR:$dst, (atomic_load_sub_8 GPR:$ptr, GPR:$incr))]>;
3247 def ATOMIC_LOAD_AND_I8 : PseudoInst<
3248 (outs GPR:$dst), (ins GPR:$ptr, GPR:$incr), NoItinerary,
3249 [(set GPR:$dst, (atomic_load_and_8 GPR:$ptr, GPR:$incr))]>;
3250 def ATOMIC_LOAD_OR_I8 : PseudoInst<
3251 (outs GPR:$dst), (ins GPR:$ptr, GPR:$incr), NoItinerary,
3252 [(set GPR:$dst, (atomic_load_or_8 GPR:$ptr, GPR:$incr))]>;
3253 def ATOMIC_LOAD_XOR_I8 : PseudoInst<
3254 (outs GPR:$dst), (ins GPR:$ptr, GPR:$incr), NoItinerary,
3255 [(set GPR:$dst, (atomic_load_xor_8 GPR:$ptr, GPR:$incr))]>;
3256 def ATOMIC_LOAD_NAND_I8 : PseudoInst<
3257 (outs GPR:$dst), (ins GPR:$ptr, GPR:$incr), NoItinerary,
3258 [(set GPR:$dst, (atomic_load_nand_8 GPR:$ptr, GPR:$incr))]>;
3259 def ATOMIC_LOAD_MIN_I8 : PseudoInst<
3260 (outs GPR:$dst), (ins GPR:$ptr, GPR:$val), NoItinerary,
3261 [(set GPR:$dst, (atomic_load_min_8 GPR:$ptr, GPR:$val))]>;
3262 def ATOMIC_LOAD_MAX_I8 : PseudoInst<
3263 (outs GPR:$dst), (ins GPR:$ptr, GPR:$val), NoItinerary,
3264 [(set GPR:$dst, (atomic_load_max_8 GPR:$ptr, GPR:$val))]>;
3265 def ATOMIC_LOAD_UMIN_I8 : PseudoInst<
3266 (outs GPR:$dst), (ins GPR:$ptr, GPR:$val), NoItinerary,
3267 [(set GPR:$dst, (atomic_load_min_8 GPR:$ptr, GPR:$val))]>;
3268 def ATOMIC_LOAD_UMAX_I8 : PseudoInst<
3269 (outs GPR:$dst), (ins GPR:$ptr, GPR:$val), NoItinerary,
3270 [(set GPR:$dst, (atomic_load_max_8 GPR:$ptr, GPR:$val))]>;
3271 def ATOMIC_LOAD_ADD_I16 : PseudoInst<
3272 (outs GPR:$dst), (ins GPR:$ptr, GPR:$incr), NoItinerary,
3273 [(set GPR:$dst, (atomic_load_add_16 GPR:$ptr, GPR:$incr))]>;
3274 def ATOMIC_LOAD_SUB_I16 : PseudoInst<
3275 (outs GPR:$dst), (ins GPR:$ptr, GPR:$incr), NoItinerary,
3276 [(set GPR:$dst, (atomic_load_sub_16 GPR:$ptr, GPR:$incr))]>;
3277 def ATOMIC_LOAD_AND_I16 : PseudoInst<
3278 (outs GPR:$dst), (ins GPR:$ptr, GPR:$incr), NoItinerary,
3279 [(set GPR:$dst, (atomic_load_and_16 GPR:$ptr, GPR:$incr))]>;
3280 def ATOMIC_LOAD_OR_I16 : PseudoInst<
3281 (outs GPR:$dst), (ins GPR:$ptr, GPR:$incr), NoItinerary,
3282 [(set GPR:$dst, (atomic_load_or_16 GPR:$ptr, GPR:$incr))]>;
3283 def ATOMIC_LOAD_XOR_I16 : PseudoInst<
3284 (outs GPR:$dst), (ins GPR:$ptr, GPR:$incr), NoItinerary,
3285 [(set GPR:$dst, (atomic_load_xor_16 GPR:$ptr, GPR:$incr))]>;
3286 def ATOMIC_LOAD_NAND_I16 : PseudoInst<
3287 (outs GPR:$dst), (ins GPR:$ptr, GPR:$incr), NoItinerary,
3288 [(set GPR:$dst, (atomic_load_nand_16 GPR:$ptr, GPR:$incr))]>;
3289 def ATOMIC_LOAD_MIN_I16 : PseudoInst<
3290 (outs GPR:$dst), (ins GPR:$ptr, GPR:$val), NoItinerary,
3291 [(set GPR:$dst, (atomic_load_min_16 GPR:$ptr, GPR:$val))]>;
3292 def ATOMIC_LOAD_MAX_I16 : PseudoInst<
3293 (outs GPR:$dst), (ins GPR:$ptr, GPR:$val), NoItinerary,
3294 [(set GPR:$dst, (atomic_load_max_16 GPR:$ptr, GPR:$val))]>;
3295 def ATOMIC_LOAD_UMIN_I16 : PseudoInst<
3296 (outs GPR:$dst), (ins GPR:$ptr, GPR:$val), NoItinerary,
3297 [(set GPR:$dst, (atomic_load_min_16 GPR:$ptr, GPR:$val))]>;
3298 def ATOMIC_LOAD_UMAX_I16 : PseudoInst<
3299 (outs GPR:$dst), (ins GPR:$ptr, GPR:$val), NoItinerary,
3300 [(set GPR:$dst, (atomic_load_max_16 GPR:$ptr, GPR:$val))]>;
3301 def ATOMIC_LOAD_ADD_I32 : PseudoInst<
3302 (outs GPR:$dst), (ins GPR:$ptr, GPR:$incr), NoItinerary,
3303 [(set GPR:$dst, (atomic_load_add_32 GPR:$ptr, GPR:$incr))]>;
3304 def ATOMIC_LOAD_SUB_I32 : PseudoInst<
3305 (outs GPR:$dst), (ins GPR:$ptr, GPR:$incr), NoItinerary,
3306 [(set GPR:$dst, (atomic_load_sub_32 GPR:$ptr, GPR:$incr))]>;
3307 def ATOMIC_LOAD_AND_I32 : PseudoInst<
3308 (outs GPR:$dst), (ins GPR:$ptr, GPR:$incr), NoItinerary,
3309 [(set GPR:$dst, (atomic_load_and_32 GPR:$ptr, GPR:$incr))]>;
3310 def ATOMIC_LOAD_OR_I32 : PseudoInst<
3311 (outs GPR:$dst), (ins GPR:$ptr, GPR:$incr), NoItinerary,
3312 [(set GPR:$dst, (atomic_load_or_32 GPR:$ptr, GPR:$incr))]>;
3313 def ATOMIC_LOAD_XOR_I32 : PseudoInst<
3314 (outs GPR:$dst), (ins GPR:$ptr, GPR:$incr), NoItinerary,
3315 [(set GPR:$dst, (atomic_load_xor_32 GPR:$ptr, GPR:$incr))]>;
3316 def ATOMIC_LOAD_NAND_I32 : PseudoInst<
3317 (outs GPR:$dst), (ins GPR:$ptr, GPR:$incr), NoItinerary,
3318 [(set GPR:$dst, (atomic_load_nand_32 GPR:$ptr, GPR:$incr))]>;
3319 def ATOMIC_LOAD_MIN_I32 : PseudoInst<
3320 (outs GPR:$dst), (ins GPR:$ptr, GPR:$val), NoItinerary,
3321 [(set GPR:$dst, (atomic_load_min_32 GPR:$ptr, GPR:$val))]>;
3322 def ATOMIC_LOAD_MAX_I32 : PseudoInst<
3323 (outs GPR:$dst), (ins GPR:$ptr, GPR:$val), NoItinerary,
3324 [(set GPR:$dst, (atomic_load_max_32 GPR:$ptr, GPR:$val))]>;
3325 def ATOMIC_LOAD_UMIN_I32 : PseudoInst<
3326 (outs GPR:$dst), (ins GPR:$ptr, GPR:$val), NoItinerary,
3327 [(set GPR:$dst, (atomic_load_min_32 GPR:$ptr, GPR:$val))]>;
3328 def ATOMIC_LOAD_UMAX_I32 : PseudoInst<
3329 (outs GPR:$dst), (ins GPR:$ptr, GPR:$val), NoItinerary,
3330 [(set GPR:$dst, (atomic_load_max_32 GPR:$ptr, GPR:$val))]>;
3332 def ATOMIC_SWAP_I8 : PseudoInst<
3333 (outs GPR:$dst), (ins GPR:$ptr, GPR:$new), NoItinerary,
3334 [(set GPR:$dst, (atomic_swap_8 GPR:$ptr, GPR:$new))]>;
3335 def ATOMIC_SWAP_I16 : PseudoInst<
3336 (outs GPR:$dst), (ins GPR:$ptr, GPR:$new), NoItinerary,
3337 [(set GPR:$dst, (atomic_swap_16 GPR:$ptr, GPR:$new))]>;
3338 def ATOMIC_SWAP_I32 : PseudoInst<
3339 (outs GPR:$dst), (ins GPR:$ptr, GPR:$new), NoItinerary,
3340 [(set GPR:$dst, (atomic_swap_32 GPR:$ptr, GPR:$new))]>;
3342 def ATOMIC_CMP_SWAP_I8 : PseudoInst<
3343 (outs GPR:$dst), (ins GPR:$ptr, GPR:$old, GPR:$new), NoItinerary,
3344 [(set GPR:$dst, (atomic_cmp_swap_8 GPR:$ptr, GPR:$old, GPR:$new))]>;
3345 def ATOMIC_CMP_SWAP_I16 : PseudoInst<
3346 (outs GPR:$dst), (ins GPR:$ptr, GPR:$old, GPR:$new), NoItinerary,
3347 [(set GPR:$dst, (atomic_cmp_swap_16 GPR:$ptr, GPR:$old, GPR:$new))]>;
3348 def ATOMIC_CMP_SWAP_I32 : PseudoInst<
3349 (outs GPR:$dst), (ins GPR:$ptr, GPR:$old, GPR:$new), NoItinerary,
3350 [(set GPR:$dst, (atomic_cmp_swap_32 GPR:$ptr, GPR:$old, GPR:$new))]>;
3354 let mayLoad = 1 in {
3355 def LDREXB : AIldrex<0b10, (outs GPR:$Rt), (ins addrmode7:$addr), NoItinerary,
3356 "ldrexb", "\t$Rt, $addr", []>;
3357 def LDREXH : AIldrex<0b11, (outs GPR:$Rt), (ins addrmode7:$addr), NoItinerary,
3358 "ldrexh", "\t$Rt, $addr", []>;
3359 def LDREX : AIldrex<0b00, (outs GPR:$Rt), (ins addrmode7:$addr), NoItinerary,
3360 "ldrex", "\t$Rt, $addr", []>;
3361 def LDREXD : AIldrex<0b01, (outs GPR:$Rt, GPR:$Rt2), (ins addrmode7:$addr),
3362 NoItinerary, "ldrexd", "\t$Rt, $Rt2, $addr", []>;
3365 let mayStore = 1, Constraints = "@earlyclobber $Rd" in {
3366 def STREXB : AIstrex<0b10, (outs GPR:$Rd), (ins GPR:$Rt, addrmode7:$addr),
3367 NoItinerary, "strexb", "\t$Rd, $Rt, $addr", []>;
3368 def STREXH : AIstrex<0b11, (outs GPR:$Rd), (ins GPR:$Rt, addrmode7:$addr),
3369 NoItinerary, "strexh", "\t$Rd, $Rt, $addr", []>;
3370 def STREX : AIstrex<0b00, (outs GPR:$Rd), (ins GPR:$Rt, addrmode7:$addr),
3371 NoItinerary, "strex", "\t$Rd, $Rt, $addr", []>;
3372 def STREXD : AIstrex<0b01, (outs GPR:$Rd),
3373 (ins GPR:$Rt, GPR:$Rt2, addrmode7:$addr),
3374 NoItinerary, "strexd", "\t$Rd, $Rt, $Rt2, $addr", []>;
3377 // Clear-Exclusive is for disassembly only.
3378 def CLREX : AXI<(outs), (ins), MiscFrm, NoItinerary, "clrex",
3379 [/* For disassembly only; pattern left blank */]>,
3380 Requires<[IsARM, HasV7]> {
3381 let Inst{31-0} = 0b11110101011111111111000000011111;
3384 // SWP/SWPB are deprecated in V6/V7 and for disassembly only.
3385 let mayLoad = 1 in {
3386 def SWP : AIswp<0, (outs GPR:$Rt), (ins GPR:$Rt2, GPR:$Rn), "swp",
3387 [/* For disassembly only; pattern left blank */]>;
3388 def SWPB : AIswp<1, (outs GPR:$Rt), (ins GPR:$Rt2, GPR:$Rn), "swpb",
3389 [/* For disassembly only; pattern left blank */]>;
3392 //===----------------------------------------------------------------------===//
3393 // Coprocessor Instructions.
3396 def CDP : ABI<0b1110, (outs), (ins p_imm:$cop, i32imm:$opc1,
3397 c_imm:$CRd, c_imm:$CRn, c_imm:$CRm, i32imm:$opc2),
3398 NoItinerary, "cdp", "\t$cop, $opc1, $CRd, $CRn, $CRm, $opc2",
3399 [/* For disassembly only; pattern left blank */]> {
3407 let Inst{3-0} = CRm;
3409 let Inst{7-5} = opc2;
3410 let Inst{11-8} = cop;
3411 let Inst{15-12} = CRd;
3412 let Inst{19-16} = CRn;
3413 let Inst{23-20} = opc1;
3416 def CDP2 : ABXI<0b1110, (outs), (ins p_imm:$cop, i32imm:$opc1,
3417 c_imm:$CRd, c_imm:$CRn, c_imm:$CRm, i32imm:$opc2),
3418 NoItinerary, "cdp2\t$cop, $opc1, $CRd, $CRn, $CRm, $opc2",
3419 [/* For disassembly only; pattern left blank */]> {
3420 let Inst{31-28} = 0b1111;
3428 let Inst{3-0} = CRm;
3430 let Inst{7-5} = opc2;
3431 let Inst{11-8} = cop;
3432 let Inst{15-12} = CRd;
3433 let Inst{19-16} = CRn;
3434 let Inst{23-20} = opc1;
3437 class ACI<dag oops, dag iops, string opc, string asm,
3438 IndexMode im = IndexModeNone>
3439 : InoP<oops, iops, AddrModeNone, Size4Bytes, im, BrFrm, NoItinerary,
3440 opc, asm, "", [/* For disassembly only; pattern left blank */]> {
3441 let Inst{27-25} = 0b110;
3444 multiclass LdStCop<bits<4> op31_28, bit load, dag ops, string opc, string cond>{
3446 def _OFFSET : ACI<(outs),
3447 !con((ins nohash_imm:$cop, nohash_imm:$CRd, addrmode2:$addr), ops),
3448 !strconcat(opc, cond), "\tp$cop, cr$CRd, $addr"> {
3449 let Inst{31-28} = op31_28;
3450 let Inst{24} = 1; // P = 1
3451 let Inst{21} = 0; // W = 0
3452 let Inst{22} = 0; // D = 0
3453 let Inst{20} = load;
3456 def _PRE : ACI<(outs),
3457 !con((ins nohash_imm:$cop, nohash_imm:$CRd, addrmode2:$addr), ops),
3458 !strconcat(opc, cond), "\tp$cop, cr$CRd, $addr!", IndexModePre> {
3459 let Inst{31-28} = op31_28;
3460 let Inst{24} = 1; // P = 1
3461 let Inst{21} = 1; // W = 1
3462 let Inst{22} = 0; // D = 0
3463 let Inst{20} = load;
3466 def _POST : ACI<(outs),
3467 !con((ins nohash_imm:$cop, nohash_imm:$CRd, addrmode2:$addr), ops),
3468 !strconcat(opc, cond), "\tp$cop, cr$CRd, $addr", IndexModePost> {
3469 let Inst{31-28} = op31_28;
3470 let Inst{24} = 0; // P = 0
3471 let Inst{21} = 1; // W = 1
3472 let Inst{22} = 0; // D = 0
3473 let Inst{20} = load;
3476 def _OPTION : ACI<(outs),
3477 !con((ins nohash_imm:$cop,nohash_imm:$CRd,GPR:$base, nohash_imm:$option),
3479 !strconcat(opc, cond), "\tp$cop, cr$CRd, [$base], \\{$option\\}"> {
3480 let Inst{31-28} = op31_28;
3481 let Inst{24} = 0; // P = 0
3482 let Inst{23} = 1; // U = 1
3483 let Inst{21} = 0; // W = 0
3484 let Inst{22} = 0; // D = 0
3485 let Inst{20} = load;
3488 def L_OFFSET : ACI<(outs),
3489 !con((ins nohash_imm:$cop, nohash_imm:$CRd, addrmode2:$addr), ops),
3490 !strconcat(!strconcat(opc, "l"), cond), "\tp$cop, cr$CRd, $addr"> {
3491 let Inst{31-28} = op31_28;
3492 let Inst{24} = 1; // P = 1
3493 let Inst{21} = 0; // W = 0
3494 let Inst{22} = 1; // D = 1
3495 let Inst{20} = load;
3498 def L_PRE : ACI<(outs),
3499 !con((ins nohash_imm:$cop, nohash_imm:$CRd, addrmode2:$addr), ops),
3500 !strconcat(!strconcat(opc, "l"), cond), "\tp$cop, cr$CRd, $addr!",
3502 let Inst{31-28} = op31_28;
3503 let Inst{24} = 1; // P = 1
3504 let Inst{21} = 1; // W = 1
3505 let Inst{22} = 1; // D = 1
3506 let Inst{20} = load;
3509 def L_POST : ACI<(outs),
3510 !con((ins nohash_imm:$cop, nohash_imm:$CRd, addrmode2:$addr), ops),
3511 !strconcat(!strconcat(opc, "l"), cond), "\tp$cop, cr$CRd, $addr",
3513 let Inst{31-28} = op31_28;
3514 let Inst{24} = 0; // P = 0
3515 let Inst{21} = 1; // W = 1
3516 let Inst{22} = 1; // D = 1
3517 let Inst{20} = load;
3520 def L_OPTION : ACI<(outs),
3521 !con((ins nohash_imm:$cop, nohash_imm:$CRd,GPR:$base,nohash_imm:$option),
3523 !strconcat(!strconcat(opc, "l"), cond),
3524 "\tp$cop, cr$CRd, [$base], \\{$option\\}"> {
3525 let Inst{31-28} = op31_28;
3526 let Inst{24} = 0; // P = 0
3527 let Inst{23} = 1; // U = 1
3528 let Inst{21} = 0; // W = 0
3529 let Inst{22} = 1; // D = 1
3530 let Inst{20} = load;
3534 defm LDC : LdStCop<{?,?,?,?}, 1, (ins pred:$p), "ldc", "${p}">;
3535 defm LDC2 : LdStCop<0b1111, 1, (ins), "ldc2", "">;
3536 defm STC : LdStCop<{?,?,?,?}, 0, (ins pred:$p), "stc", "${p}">;
3537 defm STC2 : LdStCop<0b1111, 0, (ins), "stc2", "">;
3539 //===----------------------------------------------------------------------===//
3540 // Move between coprocessor and ARM core register -- for disassembly only
3543 class MovRCopro<string opc, bit direction, dag oops, dag iops>
3544 : ABI<0b1110, oops, iops, NoItinerary, opc,
3545 "\t$cop, $opc1, $Rt, $CRn, $CRm, $opc2",
3546 [/* For disassembly only; pattern left blank */]> {
3547 let Inst{20} = direction;
3557 let Inst{15-12} = Rt;
3558 let Inst{11-8} = cop;
3559 let Inst{23-21} = opc1;
3560 let Inst{7-5} = opc2;
3561 let Inst{3-0} = CRm;
3562 let Inst{19-16} = CRn;
3565 def MCR : MovRCopro<"mcr", 0 /* from ARM core register to coprocessor */,
3566 (outs), (ins p_imm:$cop, i32imm:$opc1,
3567 GPR:$Rt, c_imm:$CRn, c_imm:$CRm,
3569 def MRC : MovRCopro<"mrc", 1 /* from coprocessor to ARM core register */,
3570 (outs GPR:$Rt), (ins p_imm:$cop, i32imm:$opc1,
3571 c_imm:$CRn, c_imm:$CRm, i32imm:$opc2)>;
3573 class MovRCopro2<string opc, bit direction, dag oops, dag iops>
3574 : ABXI<0b1110, oops, iops, NoItinerary,
3575 !strconcat(opc, "\t$cop, $opc1, $Rt, $CRn, $CRm, $opc2"),
3576 [/* For disassembly only; pattern left blank */]> {
3577 let Inst{31-28} = 0b1111;
3578 let Inst{20} = direction;
3588 let Inst{15-12} = Rt;
3589 let Inst{11-8} = cop;
3590 let Inst{23-21} = opc1;
3591 let Inst{7-5} = opc2;
3592 let Inst{3-0} = CRm;
3593 let Inst{19-16} = CRn;
3596 def MCR2 : MovRCopro2<"mcr2", 0 /* from ARM core register to coprocessor */,
3597 (outs), (ins p_imm:$cop, i32imm:$opc1,
3598 GPR:$Rt, c_imm:$CRn, c_imm:$CRm,
3600 def MRC2 : MovRCopro2<"mrc2", 1 /* from coprocessor to ARM core register */,
3601 (outs GPR:$Rt), (ins p_imm:$cop, i32imm:$opc1,
3602 c_imm:$CRn, c_imm:$CRm,
3605 class MovRRCopro<string opc, bit direction>
3606 : ABI<0b1100, (outs), (ins p_imm:$cop, i32imm:$opc1,
3607 GPR:$Rt, GPR:$Rt2, c_imm:$CRm),
3608 NoItinerary, opc, "\t$cop, $opc1, $Rt, $Rt2, $CRm",
3609 [/* For disassembly only; pattern left blank */]> {
3610 let Inst{23-21} = 0b010;
3611 let Inst{20} = direction;
3619 let Inst{15-12} = Rt;
3620 let Inst{19-16} = Rt2;
3621 let Inst{11-8} = cop;
3622 let Inst{7-4} = opc1;
3623 let Inst{3-0} = CRm;
3626 def MCRR : MovRRCopro<"mcrr", 0 /* from ARM core register to coprocessor */>;
3627 def MRRC : MovRRCopro<"mrrc", 1 /* from coprocessor to ARM core register */>;
3629 class MovRRCopro2<string opc, bit direction>
3630 : ABXI<0b1100, (outs), (ins p_imm:$cop, i32imm:$opc1,
3631 GPR:$Rt, GPR:$Rt2, c_imm:$CRm),
3632 NoItinerary, !strconcat(opc, "\t$cop, $opc1, $Rt, $Rt2, $CRm"),
3633 [/* For disassembly only; pattern left blank */]> {
3634 let Inst{31-28} = 0b1111;
3635 let Inst{23-21} = 0b010;
3636 let Inst{20} = direction;
3644 let Inst{15-12} = Rt;
3645 let Inst{19-16} = Rt2;
3646 let Inst{11-8} = cop;
3647 let Inst{7-4} = opc1;
3648 let Inst{3-0} = CRm;
3651 def MCRR2 : MovRRCopro2<"mcrr2", 0 /* from ARM core register to coprocessor */>;
3652 def MRRC2 : MovRRCopro2<"mrrc2", 1 /* from coprocessor to ARM core register */>;
3654 //===----------------------------------------------------------------------===//
3655 // Move between special register and ARM core register -- for disassembly only
3658 // Move to ARM core register from Special Register
3659 def MRS : ABI<0b0001, (outs GPR:$Rd), (ins), NoItinerary, "mrs", "\t$Rd, cpsr",
3660 [/* For disassembly only; pattern left blank */]> {
3662 let Inst{23-16} = 0b00001111;
3663 let Inst{15-12} = Rd;
3664 let Inst{7-4} = 0b0000;
3667 def MRSsys : ABI<0b0001, (outs GPR:$Rd), (ins), NoItinerary,"mrs","\t$Rd, spsr",
3668 [/* For disassembly only; pattern left blank */]> {
3670 let Inst{23-16} = 0b01001111;
3671 let Inst{15-12} = Rd;
3672 let Inst{7-4} = 0b0000;
3675 // Move from ARM core register to Special Register
3677 // No need to have both system and application versions, the encodings are the
3678 // same and the assembly parser has no way to distinguish between them. The mask
3679 // operand contains the special register (R Bit) in bit 4 and bits 3-0 contains
3680 // the mask with the fields to be accessed in the special register.
3681 def MSR : ABI<0b0001, (outs), (ins msr_mask:$mask, GPR:$Rn), NoItinerary,
3682 "msr", "\t$mask, $Rn",
3683 [/* For disassembly only; pattern left blank */]> {
3688 let Inst{22} = mask{4}; // R bit
3689 let Inst{21-20} = 0b10;
3690 let Inst{19-16} = mask{3-0};
3691 let Inst{15-12} = 0b1111;
3692 let Inst{11-4} = 0b00000000;
3696 def MSRi : ABI<0b0011, (outs), (ins msr_mask:$mask, so_imm:$a), NoItinerary,
3697 "msr", "\t$mask, $a",
3698 [/* For disassembly only; pattern left blank */]> {
3703 let Inst{22} = mask{4}; // R bit
3704 let Inst{21-20} = 0b10;
3705 let Inst{19-16} = mask{3-0};
3706 let Inst{15-12} = 0b1111;
3710 //===----------------------------------------------------------------------===//
3714 // __aeabi_read_tp preserves the registers r1-r3.
3715 // This is a pseudo inst so that we can get the encoding right,
3716 // complete with fixup for the aeabi_read_tp function.
3718 Defs = [R0, R12, LR, CPSR], Uses = [SP] in {
3719 def TPsoft : PseudoInst<(outs), (ins), IIC_Br,
3720 [(set R0, ARMthread_pointer)]>;
3723 //===----------------------------------------------------------------------===//
3724 // SJLJ Exception handling intrinsics
3725 // eh_sjlj_setjmp() is an instruction sequence to store the return
3726 // address and save #0 in R0 for the non-longjmp case.
3727 // Since by its nature we may be coming from some other function to get
3728 // here, and we're using the stack frame for the containing function to
3729 // save/restore registers, we can't keep anything live in regs across
3730 // the eh_sjlj_setjmp(), else it will almost certainly have been tromped upon
3731 // when we get here from a longjmp(). We force everything out of registers
3732 // except for our own input by listing the relevant registers in Defs. By
3733 // doing so, we also cause the prologue/epilogue code to actively preserve
3734 // all of the callee-saved resgisters, which is exactly what we want.
3735 // A constant value is passed in $val, and we use the location as a scratch.
3737 // These are pseudo-instructions and are lowered to individual MC-insts, so
3738 // no encoding information is necessary.
3740 [ R0, R1, R2, R3, R4, R5, R6, R7, R8, R9, R10, R11, R12, LR, D0,
3741 D1, D2, D3, D4, D5, D6, D7, D8, D9, D10, D11, D12, D13, D14, D15,
3742 D16, D17, D18, D19, D20, D21, D22, D23, D24, D25, D26, D27, D28, D29, D30,
3743 D31 ], hasSideEffects = 1, isBarrier = 1 in {
3744 def Int_eh_sjlj_setjmp : PseudoInst<(outs), (ins GPR:$src, GPR:$val),
3746 [(set R0, (ARMeh_sjlj_setjmp GPR:$src, GPR:$val))]>,
3747 Requires<[IsARM, HasVFP2]>;
3751 [ R0, R1, R2, R3, R4, R5, R6, R7, R8, R9, R10, R11, R12, LR ],
3752 hasSideEffects = 1, isBarrier = 1 in {
3753 def Int_eh_sjlj_setjmp_nofp : PseudoInst<(outs), (ins GPR:$src, GPR:$val),
3755 [(set R0, (ARMeh_sjlj_setjmp GPR:$src, GPR:$val))]>,
3756 Requires<[IsARM, NoVFP]>;
3759 // FIXME: Non-Darwin version(s)
3760 let isBarrier = 1, hasSideEffects = 1, isTerminator = 1,
3761 Defs = [ R7, LR, SP ] in {
3762 def Int_eh_sjlj_longjmp : PseudoInst<(outs), (ins GPR:$src, GPR:$scratch),
3764 [(ARMeh_sjlj_longjmp GPR:$src, GPR:$scratch)]>,
3765 Requires<[IsARM, IsDarwin]>;
3768 // eh.sjlj.dispatchsetup pseudo-instruction.
3769 // This pseudo is used for ARM, Thumb1 and Thumb2. Any differences are
3770 // handled when the pseudo is expanded (which happens before any passes
3771 // that need the instruction size).
3772 let isBarrier = 1, hasSideEffects = 1 in
3773 def Int_eh_sjlj_dispatchsetup :
3774 PseudoInst<(outs), (ins), NoItinerary,
3775 [(ARMeh_sjlj_dispatchsetup)]>,
3776 Requires<[IsDarwin]>;
3778 //===----------------------------------------------------------------------===//
3779 // Non-Instruction Patterns
3782 // Large immediate handling.
3784 // 32-bit immediate using two piece so_imms or movw + movt.
3785 // This is a single pseudo instruction, the benefit is that it can be remat'd
3786 // as a single unit instead of having to handle reg inputs.
3787 // FIXME: Remove this when we can do generalized remat.
3788 let isReMaterializable = 1, isMoveImm = 1 in
3789 def MOVi32imm : PseudoInst<(outs GPR:$dst), (ins i32imm:$src), IIC_iMOVix2,
3790 [(set GPR:$dst, (arm_i32imm:$src))]>,
3793 // Pseudo instruction that combines movw + movt + add pc (if PIC).
3794 // It also makes it possible to rematerialize the instructions.
3795 // FIXME: Remove this when we can do generalized remat and when machine licm
3796 // can properly the instructions.
3797 let isReMaterializable = 1 in {
3798 def MOV_ga_pcrel : PseudoInst<(outs GPR:$dst), (ins i32imm:$addr),
3800 [(set GPR:$dst, (ARMWrapperPIC tglobaladdr:$addr))]>,
3801 Requires<[IsARM, UseMovt]>;
3803 def MOV_ga_dyn : PseudoInst<(outs GPR:$dst), (ins i32imm:$addr),
3805 [(set GPR:$dst, (ARMWrapperDYN tglobaladdr:$addr))]>,
3806 Requires<[IsARM, UseMovt]>;
3808 let AddedComplexity = 10 in
3809 def MOV_ga_pcrel_ldr : PseudoInst<(outs GPR:$dst), (ins i32imm:$addr),
3811 [(set GPR:$dst, (load (ARMWrapperPIC tglobaladdr:$addr)))]>,
3812 Requires<[IsARM, UseMovt]>;
3813 } // isReMaterializable
3815 // ConstantPool, GlobalAddress, and JumpTable
3816 def : ARMPat<(ARMWrapper tglobaladdr :$dst), (LEApcrel tglobaladdr :$dst)>,
3817 Requires<[IsARM, DontUseMovt]>;
3818 def : ARMPat<(ARMWrapper tconstpool :$dst), (LEApcrel tconstpool :$dst)>;
3819 def : ARMPat<(ARMWrapper tglobaladdr :$dst), (MOVi32imm tglobaladdr :$dst)>,
3820 Requires<[IsARM, UseMovt]>;
3821 def : ARMPat<(ARMWrapperJT tjumptable:$dst, imm:$id),
3822 (LEApcrelJT tjumptable:$dst, imm:$id)>;
3824 // TODO: add,sub,and, 3-instr forms?
3827 def : ARMPat<(ARMtcret tcGPR:$dst),
3828 (TCRETURNri tcGPR:$dst)>, Requires<[IsDarwin]>;
3830 def : ARMPat<(ARMtcret (i32 tglobaladdr:$dst)),
3831 (TCRETURNdi texternalsym:$dst)>, Requires<[IsDarwin]>;
3833 def : ARMPat<(ARMtcret (i32 texternalsym:$dst)),
3834 (TCRETURNdi texternalsym:$dst)>, Requires<[IsDarwin]>;
3836 def : ARMPat<(ARMtcret tcGPR:$dst),
3837 (TCRETURNriND tcGPR:$dst)>, Requires<[IsNotDarwin]>;
3839 def : ARMPat<(ARMtcret (i32 tglobaladdr:$dst)),
3840 (TCRETURNdiND texternalsym:$dst)>, Requires<[IsNotDarwin]>;
3842 def : ARMPat<(ARMtcret (i32 texternalsym:$dst)),
3843 (TCRETURNdiND texternalsym:$dst)>, Requires<[IsNotDarwin]>;
3846 def : ARMPat<(ARMcall texternalsym:$func), (BL texternalsym:$func)>,
3847 Requires<[IsARM, IsNotDarwin]>;
3848 def : ARMPat<(ARMcall texternalsym:$func), (BLr9 texternalsym:$func)>,
3849 Requires<[IsARM, IsDarwin]>;
3851 // zextload i1 -> zextload i8
3852 def : ARMPat<(zextloadi1 addrmode_imm12:$addr), (LDRBi12 addrmode_imm12:$addr)>;
3853 def : ARMPat<(zextloadi1 ldst_so_reg:$addr), (LDRBrs ldst_so_reg:$addr)>;
3855 // extload -> zextload
3856 def : ARMPat<(extloadi1 addrmode_imm12:$addr), (LDRBi12 addrmode_imm12:$addr)>;
3857 def : ARMPat<(extloadi1 ldst_so_reg:$addr), (LDRBrs ldst_so_reg:$addr)>;
3858 def : ARMPat<(extloadi8 addrmode_imm12:$addr), (LDRBi12 addrmode_imm12:$addr)>;
3859 def : ARMPat<(extloadi8 ldst_so_reg:$addr), (LDRBrs ldst_so_reg:$addr)>;
3861 def : ARMPat<(extloadi16 addrmode3:$addr), (LDRH addrmode3:$addr)>;
3863 def : ARMPat<(extloadi8 addrmodepc:$addr), (PICLDRB addrmodepc:$addr)>;
3864 def : ARMPat<(extloadi16 addrmodepc:$addr), (PICLDRH addrmodepc:$addr)>;
3867 def : ARMV5TEPat<(mul (sra (shl GPR:$a, (i32 16)), (i32 16)),
3868 (sra (shl GPR:$b, (i32 16)), (i32 16))),
3869 (SMULBB GPR:$a, GPR:$b)>;
3870 def : ARMV5TEPat<(mul sext_16_node:$a, sext_16_node:$b),
3871 (SMULBB GPR:$a, GPR:$b)>;
3872 def : ARMV5TEPat<(mul (sra (shl GPR:$a, (i32 16)), (i32 16)),
3873 (sra GPR:$b, (i32 16))),
3874 (SMULBT GPR:$a, GPR:$b)>;
3875 def : ARMV5TEPat<(mul sext_16_node:$a, (sra GPR:$b, (i32 16))),
3876 (SMULBT GPR:$a, GPR:$b)>;
3877 def : ARMV5TEPat<(mul (sra GPR:$a, (i32 16)),
3878 (sra (shl GPR:$b, (i32 16)), (i32 16))),
3879 (SMULTB GPR:$a, GPR:$b)>;
3880 def : ARMV5TEPat<(mul (sra GPR:$a, (i32 16)), sext_16_node:$b),
3881 (SMULTB GPR:$a, GPR:$b)>;
3882 def : ARMV5TEPat<(sra (mul GPR:$a, (sra (shl GPR:$b, (i32 16)), (i32 16))),
3884 (SMULWB GPR:$a, GPR:$b)>;
3885 def : ARMV5TEPat<(sra (mul GPR:$a, sext_16_node:$b), (i32 16)),
3886 (SMULWB GPR:$a, GPR:$b)>;
3888 def : ARMV5TEPat<(add GPR:$acc,
3889 (mul (sra (shl GPR:$a, (i32 16)), (i32 16)),
3890 (sra (shl GPR:$b, (i32 16)), (i32 16)))),
3891 (SMLABB GPR:$a, GPR:$b, GPR:$acc)>;
3892 def : ARMV5TEPat<(add GPR:$acc,
3893 (mul sext_16_node:$a, sext_16_node:$b)),
3894 (SMLABB GPR:$a, GPR:$b, GPR:$acc)>;
3895 def : ARMV5TEPat<(add GPR:$acc,
3896 (mul (sra (shl GPR:$a, (i32 16)), (i32 16)),
3897 (sra GPR:$b, (i32 16)))),
3898 (SMLABT GPR:$a, GPR:$b, GPR:$acc)>;
3899 def : ARMV5TEPat<(add GPR:$acc,
3900 (mul sext_16_node:$a, (sra GPR:$b, (i32 16)))),
3901 (SMLABT GPR:$a, GPR:$b, GPR:$acc)>;
3902 def : ARMV5TEPat<(add GPR:$acc,
3903 (mul (sra GPR:$a, (i32 16)),
3904 (sra (shl GPR:$b, (i32 16)), (i32 16)))),
3905 (SMLATB GPR:$a, GPR:$b, GPR:$acc)>;
3906 def : ARMV5TEPat<(add GPR:$acc,
3907 (mul (sra GPR:$a, (i32 16)), sext_16_node:$b)),
3908 (SMLATB GPR:$a, GPR:$b, GPR:$acc)>;
3909 def : ARMV5TEPat<(add GPR:$acc,
3910 (sra (mul GPR:$a, (sra (shl GPR:$b, (i32 16)), (i32 16))),
3912 (SMLAWB GPR:$a, GPR:$b, GPR:$acc)>;
3913 def : ARMV5TEPat<(add GPR:$acc,
3914 (sra (mul GPR:$a, sext_16_node:$b), (i32 16))),
3915 (SMLAWB GPR:$a, GPR:$b, GPR:$acc)>;
3918 // Pre-v7 uses MCR for synchronization barriers.
3919 def : ARMPat<(ARMMemBarrierMCR GPR:$zero), (MCR 15, 0, GPR:$zero, 7, 10, 5)>,
3920 Requires<[IsARM, HasV6]>;
3923 //===----------------------------------------------------------------------===//
3927 include "ARMInstrThumb.td"
3929 //===----------------------------------------------------------------------===//
3933 include "ARMInstrThumb2.td"
3935 //===----------------------------------------------------------------------===//
3936 // Floating Point Support
3939 include "ARMInstrVFP.td"
3941 //===----------------------------------------------------------------------===//
3942 // Advanced SIMD (NEON) Support
3945 include "ARMInstrNEON.td"