1 //===- ARMInstrInfo.td - Target Description for ARM Target -*- tablegen -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file describes the ARM instructions in TableGen format.
12 //===----------------------------------------------------------------------===//
14 //===----------------------------------------------------------------------===//
15 // ARM specific DAG Nodes.
19 def SDT_ARMCallSeqStart : SDCallSeqStart<[ SDTCisVT<0, i32> ]>;
20 def SDT_ARMCallSeqEnd : SDCallSeqEnd<[ SDTCisVT<0, i32>, SDTCisVT<1, i32> ]>;
22 def SDT_ARMSaveCallPC : SDTypeProfile<0, 1, []>;
24 def SDT_ARMcall : SDTypeProfile<0, -1, [SDTCisPtrTy<0>]>;
26 def SDT_ARMCMov : SDTypeProfile<1, 3,
27 [SDTCisSameAs<0, 1>, SDTCisSameAs<0, 2>,
30 def SDT_ARMBrcond : SDTypeProfile<0, 2,
31 [SDTCisVT<0, OtherVT>, SDTCisVT<1, i32>]>;
33 def SDT_ARMBrJT : SDTypeProfile<0, 3,
34 [SDTCisPtrTy<0>, SDTCisVT<1, i32>,
37 def SDT_ARMBr2JT : SDTypeProfile<0, 4,
38 [SDTCisPtrTy<0>, SDTCisVT<1, i32>,
39 SDTCisVT<2, i32>, SDTCisVT<3, i32>]>;
41 def SDT_ARMBCC_i64 : SDTypeProfile<0, 6,
43 SDTCisVT<1, i32>, SDTCisVT<2, i32>,
44 SDTCisVT<3, i32>, SDTCisVT<4, i32>,
45 SDTCisVT<5, OtherVT>]>;
47 def SDT_ARMAnd : SDTypeProfile<1, 2,
48 [SDTCisVT<0, i32>, SDTCisVT<1, i32>,
51 def SDT_ARMCmp : SDTypeProfile<0, 2, [SDTCisSameAs<0, 1>]>;
53 def SDT_ARMPICAdd : SDTypeProfile<1, 2, [SDTCisSameAs<0, 1>,
54 SDTCisPtrTy<1>, SDTCisVT<2, i32>]>;
56 def SDT_ARMThreadPointer : SDTypeProfile<1, 0, [SDTCisPtrTy<0>]>;
57 def SDT_ARMEH_SJLJ_Setjmp : SDTypeProfile<1, 2, [SDTCisInt<0>, SDTCisPtrTy<1>,
59 def SDT_ARMEH_SJLJ_Longjmp: SDTypeProfile<0, 2, [SDTCisPtrTy<0>, SDTCisInt<1>]>;
61 def SDT_ARMEH_SJLJ_DispatchSetup: SDTypeProfile<0, 1, [SDTCisInt<0>]>;
63 def SDT_ARMMEMBARRIER : SDTypeProfile<0, 1, [SDTCisInt<0>]>;
65 def SDT_ARMPREFETCH : SDTypeProfile<0, 3, [SDTCisPtrTy<0>, SDTCisSameAs<1, 2>,
68 def SDT_ARMTCRET : SDTypeProfile<0, 1, [SDTCisPtrTy<0>]>;
70 def SDT_ARMBFI : SDTypeProfile<1, 3, [SDTCisVT<0, i32>, SDTCisVT<1, i32>,
71 SDTCisVT<2, i32>, SDTCisVT<3, i32>]>;
74 def ARMWrapper : SDNode<"ARMISD::Wrapper", SDTIntUnaryOp>;
75 def ARMWrapperDYN : SDNode<"ARMISD::WrapperDYN", SDTIntUnaryOp>;
76 def ARMWrapperPIC : SDNode<"ARMISD::WrapperPIC", SDTIntUnaryOp>;
77 def ARMWrapperJT : SDNode<"ARMISD::WrapperJT", SDTIntBinOp>;
79 def ARMcallseq_start : SDNode<"ISD::CALLSEQ_START", SDT_ARMCallSeqStart,
80 [SDNPHasChain, SDNPOutGlue]>;
81 def ARMcallseq_end : SDNode<"ISD::CALLSEQ_END", SDT_ARMCallSeqEnd,
82 [SDNPHasChain, SDNPOptInGlue, SDNPOutGlue]>;
84 def ARMcall : SDNode<"ARMISD::CALL", SDT_ARMcall,
85 [SDNPHasChain, SDNPOptInGlue, SDNPOutGlue,
87 def ARMcall_pred : SDNode<"ARMISD::CALL_PRED", SDT_ARMcall,
88 [SDNPHasChain, SDNPOptInGlue, SDNPOutGlue,
90 def ARMcall_nolink : SDNode<"ARMISD::CALL_NOLINK", SDT_ARMcall,
91 [SDNPHasChain, SDNPOptInGlue, SDNPOutGlue,
94 def ARMretflag : SDNode<"ARMISD::RET_FLAG", SDTNone,
95 [SDNPHasChain, SDNPOptInGlue]>;
97 def ARMcmov : SDNode<"ARMISD::CMOV", SDT_ARMCMov,
100 def ARMbrcond : SDNode<"ARMISD::BRCOND", SDT_ARMBrcond,
101 [SDNPHasChain, SDNPInGlue, SDNPOutGlue]>;
103 def ARMbrjt : SDNode<"ARMISD::BR_JT", SDT_ARMBrJT,
105 def ARMbr2jt : SDNode<"ARMISD::BR2_JT", SDT_ARMBr2JT,
108 def ARMBcci64 : SDNode<"ARMISD::BCC_i64", SDT_ARMBCC_i64,
111 def ARMcmp : SDNode<"ARMISD::CMP", SDT_ARMCmp,
114 def ARMcmpZ : SDNode<"ARMISD::CMPZ", SDT_ARMCmp,
115 [SDNPOutGlue, SDNPCommutative]>;
117 def ARMpic_add : SDNode<"ARMISD::PIC_ADD", SDT_ARMPICAdd>;
119 def ARMsrl_flag : SDNode<"ARMISD::SRL_FLAG", SDTIntUnaryOp, [SDNPOutGlue]>;
120 def ARMsra_flag : SDNode<"ARMISD::SRA_FLAG", SDTIntUnaryOp, [SDNPOutGlue]>;
121 def ARMrrx : SDNode<"ARMISD::RRX" , SDTIntUnaryOp, [SDNPInGlue ]>;
123 def ARMthread_pointer: SDNode<"ARMISD::THREAD_POINTER", SDT_ARMThreadPointer>;
124 def ARMeh_sjlj_setjmp: SDNode<"ARMISD::EH_SJLJ_SETJMP",
125 SDT_ARMEH_SJLJ_Setjmp, [SDNPHasChain]>;
126 def ARMeh_sjlj_longjmp: SDNode<"ARMISD::EH_SJLJ_LONGJMP",
127 SDT_ARMEH_SJLJ_Longjmp, [SDNPHasChain]>;
128 def ARMeh_sjlj_dispatchsetup: SDNode<"ARMISD::EH_SJLJ_DISPATCHSETUP",
129 SDT_ARMEH_SJLJ_DispatchSetup, [SDNPHasChain]>;
132 def ARMMemBarrier : SDNode<"ARMISD::MEMBARRIER", SDT_ARMMEMBARRIER,
134 def ARMMemBarrierMCR : SDNode<"ARMISD::MEMBARRIER_MCR", SDT_ARMMEMBARRIER,
136 def ARMPreload : SDNode<"ARMISD::PRELOAD", SDT_ARMPREFETCH,
137 [SDNPHasChain, SDNPMayLoad, SDNPMayStore]>;
139 def ARMrbit : SDNode<"ARMISD::RBIT", SDTIntUnaryOp>;
141 def ARMtcret : SDNode<"ARMISD::TC_RETURN", SDT_ARMTCRET,
142 [SDNPHasChain, SDNPOptInGlue, SDNPVariadic]>;
145 def ARMbfi : SDNode<"ARMISD::BFI", SDT_ARMBFI>;
147 //===----------------------------------------------------------------------===//
148 // ARM Instruction Predicate Definitions.
150 def HasV4T : Predicate<"Subtarget->hasV4TOps()">,
151 AssemblerPredicate<"HasV4TOps">;
152 def NoV4T : Predicate<"!Subtarget->hasV4TOps()">;
153 def HasV5T : Predicate<"Subtarget->hasV5TOps()">;
154 def HasV5TE : Predicate<"Subtarget->hasV5TEOps()">,
155 AssemblerPredicate<"HasV5TEOps">;
156 def HasV6 : Predicate<"Subtarget->hasV6Ops()">,
157 AssemblerPredicate<"HasV6Ops">;
158 def NoV6 : Predicate<"!Subtarget->hasV6Ops()">;
159 def HasV6T2 : Predicate<"Subtarget->hasV6T2Ops()">,
160 AssemblerPredicate<"HasV6T2Ops">;
161 def NoV6T2 : Predicate<"!Subtarget->hasV6T2Ops()">;
162 def HasV7 : Predicate<"Subtarget->hasV7Ops()">,
163 AssemblerPredicate<"HasV7Ops">;
164 def NoVFP : Predicate<"!Subtarget->hasVFP2()">;
165 def HasVFP2 : Predicate<"Subtarget->hasVFP2()">,
166 AssemblerPredicate<"FeatureVFP2">;
167 def HasVFP3 : Predicate<"Subtarget->hasVFP3()">,
168 AssemblerPredicate<"FeatureVFP3">;
169 def HasNEON : Predicate<"Subtarget->hasNEON()">,
170 AssemblerPredicate<"FeatureNEON">;
171 def HasFP16 : Predicate<"Subtarget->hasFP16()">,
172 AssemblerPredicate<"FeatureFP16">;
173 def HasDivide : Predicate<"Subtarget->hasDivide()">,
174 AssemblerPredicate<"FeatureHWDiv">;
175 def HasT2ExtractPack : Predicate<"Subtarget->hasT2ExtractPack()">,
176 AssemblerPredicate<"FeatureT2XtPk">;
177 def HasThumb2DSP : Predicate<"Subtarget->hasThumb2DSP()">,
178 AssemblerPredicate<"FeatureDSPThumb2">;
179 def HasDB : Predicate<"Subtarget->hasDataBarrier()">,
180 AssemblerPredicate<"FeatureDB">;
181 def HasMP : Predicate<"Subtarget->hasMPExtension()">,
182 AssemblerPredicate<"FeatureMP">;
183 def UseNEONForFP : Predicate<"Subtarget->useNEONForSinglePrecisionFP()">;
184 def DontUseNEONForFP : Predicate<"!Subtarget->useNEONForSinglePrecisionFP()">;
185 def IsThumb : Predicate<"Subtarget->isThumb()">,
186 AssemblerPredicate<"ModeThumb">;
187 def IsThumb1Only : Predicate<"Subtarget->isThumb1Only()">;
188 def IsThumb2 : Predicate<"Subtarget->isThumb2()">,
189 AssemblerPredicate<"ModeThumb,FeatureThumb2">;
190 def IsARM : Predicate<"!Subtarget->isThumb()">,
191 AssemblerPredicate<"!ModeThumb">;
192 def IsDarwin : Predicate<"Subtarget->isTargetDarwin()">;
193 def IsNotDarwin : Predicate<"!Subtarget->isTargetDarwin()">;
195 // FIXME: Eventually this will be just "hasV6T2Ops".
196 def UseMovt : Predicate<"Subtarget->useMovt()">;
197 def DontUseMovt : Predicate<"!Subtarget->useMovt()">;
198 def UseFPVMLx : Predicate<"Subtarget->useFPVMLx()">;
200 //===----------------------------------------------------------------------===//
201 // ARM Flag Definitions.
203 class RegConstraint<string C> {
204 string Constraints = C;
207 //===----------------------------------------------------------------------===//
208 // ARM specific transformation functions and pattern fragments.
211 // so_imm_neg_XFORM - Return a so_imm value packed into the format described for
212 // so_imm_neg def below.
213 def so_imm_neg_XFORM : SDNodeXForm<imm, [{
214 return CurDAG->getTargetConstant(-(int)N->getZExtValue(), MVT::i32);
217 // so_imm_not_XFORM - Return a so_imm value packed into the format described for
218 // so_imm_not def below.
219 def so_imm_not_XFORM : SDNodeXForm<imm, [{
220 return CurDAG->getTargetConstant(~(int)N->getZExtValue(), MVT::i32);
223 /// imm1_15 predicate - True if the 32-bit immediate is in the range [1,15].
224 def imm1_15 : ImmLeaf<i32, [{
225 return (int32_t)Imm >= 1 && (int32_t)Imm < 16;
228 /// imm16_31 predicate - True if the 32-bit immediate is in the range [16,31].
229 def imm16_31 : ImmLeaf<i32, [{
230 return (int32_t)Imm >= 16 && (int32_t)Imm < 32;
235 return ARM_AM::getSOImmVal(-(uint32_t)N->getZExtValue()) != -1;
236 }], so_imm_neg_XFORM>;
240 return ARM_AM::getSOImmVal(~(uint32_t)N->getZExtValue()) != -1;
241 }], so_imm_not_XFORM>;
243 // sext_16_node predicate - True if the SDNode is sign-extended 16 or more bits.
244 def sext_16_node : PatLeaf<(i32 GPR:$a), [{
245 return CurDAG->ComputeNumSignBits(SDValue(N,0)) >= 17;
248 /// Split a 32-bit immediate into two 16 bit parts.
249 def hi16 : SDNodeXForm<imm, [{
250 return CurDAG->getTargetConstant((uint32_t)N->getZExtValue() >> 16, MVT::i32);
253 def lo16AllZero : PatLeaf<(i32 imm), [{
254 // Returns true if all low 16-bits are 0.
255 return (((uint32_t)N->getZExtValue()) & 0xFFFFUL) == 0;
258 /// imm0_65535 - An immediate is in the range [0.65535].
259 def Imm0_65535AsmOperand: AsmOperandClass { let Name = "Imm0_65535"; }
260 def imm0_65535 : Operand<i32>, ImmLeaf<i32, [{
261 return Imm >= 0 && Imm < 65536;
263 let ParserMatchClass = Imm0_65535AsmOperand;
266 class BinOpFrag<dag res> : PatFrag<(ops node:$LHS, node:$RHS), res>;
267 class UnOpFrag <dag res> : PatFrag<(ops node:$Src), res>;
269 /// adde and sube predicates - True based on whether the carry flag output
270 /// will be needed or not.
271 def adde_dead_carry :
272 PatFrag<(ops node:$LHS, node:$RHS), (adde node:$LHS, node:$RHS),
273 [{return !N->hasAnyUseOfValue(1);}]>;
274 def sube_dead_carry :
275 PatFrag<(ops node:$LHS, node:$RHS), (sube node:$LHS, node:$RHS),
276 [{return !N->hasAnyUseOfValue(1);}]>;
277 def adde_live_carry :
278 PatFrag<(ops node:$LHS, node:$RHS), (adde node:$LHS, node:$RHS),
279 [{return N->hasAnyUseOfValue(1);}]>;
280 def sube_live_carry :
281 PatFrag<(ops node:$LHS, node:$RHS), (sube node:$LHS, node:$RHS),
282 [{return N->hasAnyUseOfValue(1);}]>;
284 // An 'and' node with a single use.
285 def and_su : PatFrag<(ops node:$lhs, node:$rhs), (and node:$lhs, node:$rhs), [{
286 return N->hasOneUse();
289 // An 'xor' node with a single use.
290 def xor_su : PatFrag<(ops node:$lhs, node:$rhs), (xor node:$lhs, node:$rhs), [{
291 return N->hasOneUse();
294 // An 'fmul' node with a single use.
295 def fmul_su : PatFrag<(ops node:$lhs, node:$rhs), (fmul node:$lhs, node:$rhs),[{
296 return N->hasOneUse();
299 // An 'fadd' node which checks for single non-hazardous use.
300 def fadd_mlx : PatFrag<(ops node:$lhs, node:$rhs),(fadd node:$lhs, node:$rhs),[{
301 return hasNoVMLxHazardUse(N);
304 // An 'fsub' node which checks for single non-hazardous use.
305 def fsub_mlx : PatFrag<(ops node:$lhs, node:$rhs),(fsub node:$lhs, node:$rhs),[{
306 return hasNoVMLxHazardUse(N);
309 //===----------------------------------------------------------------------===//
310 // Operand Definitions.
314 // FIXME: rename brtarget to t2_brtarget
315 def brtarget : Operand<OtherVT> {
316 let EncoderMethod = "getBranchTargetOpValue";
317 let OperandType = "OPERAND_PCREL";
320 // FIXME: get rid of this one?
321 def uncondbrtarget : Operand<OtherVT> {
322 let EncoderMethod = "getUnconditionalBranchTargetOpValue";
323 let OperandType = "OPERAND_PCREL";
326 // Branch target for ARM. Handles conditional/unconditional
327 def br_target : Operand<OtherVT> {
328 let EncoderMethod = "getARMBranchTargetOpValue";
329 let OperandType = "OPERAND_PCREL";
333 // FIXME: rename bltarget to t2_bl_target?
334 def bltarget : Operand<i32> {
335 // Encoded the same as branch targets.
336 let EncoderMethod = "getBranchTargetOpValue";
337 let OperandType = "OPERAND_PCREL";
340 // Call target for ARM. Handles conditional/unconditional
341 // FIXME: rename bl_target to t2_bltarget?
342 def bl_target : Operand<i32> {
343 // Encoded the same as branch targets.
344 let EncoderMethod = "getARMBranchTargetOpValue";
345 let OperandType = "OPERAND_PCREL";
349 // A list of registers separated by comma. Used by load/store multiple.
350 def RegListAsmOperand : AsmOperandClass { let Name = "RegList"; }
351 def reglist : Operand<i32> {
352 let EncoderMethod = "getRegisterListOpValue";
353 let ParserMatchClass = RegListAsmOperand;
354 let PrintMethod = "printRegisterList";
357 def DPRRegListAsmOperand : AsmOperandClass { let Name = "DPRRegList"; }
358 def dpr_reglist : Operand<i32> {
359 let EncoderMethod = "getRegisterListOpValue";
360 let ParserMatchClass = DPRRegListAsmOperand;
361 let PrintMethod = "printRegisterList";
364 def SPRRegListAsmOperand : AsmOperandClass { let Name = "SPRRegList"; }
365 def spr_reglist : Operand<i32> {
366 let EncoderMethod = "getRegisterListOpValue";
367 let ParserMatchClass = SPRRegListAsmOperand;
368 let PrintMethod = "printRegisterList";
371 // An operand for the CONSTPOOL_ENTRY pseudo-instruction.
372 def cpinst_operand : Operand<i32> {
373 let PrintMethod = "printCPInstOperand";
377 def pclabel : Operand<i32> {
378 let PrintMethod = "printPCLabel";
381 // ADR instruction labels.
382 def adrlabel : Operand<i32> {
383 let EncoderMethod = "getAdrLabelOpValue";
386 def neon_vcvt_imm32 : Operand<i32> {
387 let EncoderMethod = "getNEONVcvtImm32OpValue";
390 // rot_imm: An integer that encodes a rotate amount. Must be 8, 16, or 24.
391 def rot_imm_XFORM: SDNodeXForm<imm, [{
392 switch (N->getZExtValue()){
394 case 0: return CurDAG->getTargetConstant(0, MVT::i32);
395 case 8: return CurDAG->getTargetConstant(1, MVT::i32);
396 case 16: return CurDAG->getTargetConstant(2, MVT::i32);
397 case 24: return CurDAG->getTargetConstant(3, MVT::i32);
400 def rot_imm : Operand<i32>, PatLeaf<(i32 imm), [{
401 int32_t v = N->getZExtValue();
402 return v == 8 || v == 16 || v == 24; }],
404 let PrintMethod = "printRotImmOperand";
407 // shift_imm: An integer that encodes a shift amount and the type of shift
408 // (asr or lsl). The 6-bit immediate encodes as:
411 // {4-0} imm5 shift amount.
412 // asr #32 encoded as imm5 == 0.
413 def ShifterImmAsmOperand : AsmOperandClass {
414 let Name = "ShifterImm";
415 let ParserMethod = "parseShifterImm";
417 def shift_imm : Operand<i32> {
418 let PrintMethod = "printShiftImmOperand";
419 let ParserMatchClass = ShifterImmAsmOperand;
422 // shifter_operand operands: so_reg_reg, so_reg_imm, and so_imm.
423 def ShiftedRegAsmOperand : AsmOperandClass { let Name = "RegShiftedReg"; }
424 def so_reg_reg : Operand<i32>, // reg reg imm
425 ComplexPattern<i32, 3, "SelectRegShifterOperand",
426 [shl, srl, sra, rotr]> {
427 let EncoderMethod = "getSORegRegOpValue";
428 let PrintMethod = "printSORegRegOperand";
429 let ParserMatchClass = ShiftedRegAsmOperand;
430 let MIOperandInfo = (ops GPR, GPR, i32imm);
433 def ShiftedImmAsmOperand : AsmOperandClass { let Name = "RegShiftedImm"; }
434 def so_reg_imm : Operand<i32>, // reg imm
435 ComplexPattern<i32, 2, "SelectImmShifterOperand",
436 [shl, srl, sra, rotr]> {
437 let EncoderMethod = "getSORegImmOpValue";
438 let PrintMethod = "printSORegImmOperand";
439 let ParserMatchClass = ShiftedImmAsmOperand;
440 let MIOperandInfo = (ops GPR, i32imm);
443 // FIXME: Does this need to be distinct from so_reg?
444 def shift_so_reg_reg : Operand<i32>, // reg reg imm
445 ComplexPattern<i32, 3, "SelectShiftRegShifterOperand",
446 [shl,srl,sra,rotr]> {
447 let EncoderMethod = "getSORegRegOpValue";
448 let PrintMethod = "printSORegRegOperand";
449 let MIOperandInfo = (ops GPR, GPR, i32imm);
452 // FIXME: Does this need to be distinct from so_reg?
453 def shift_so_reg_imm : Operand<i32>, // reg reg imm
454 ComplexPattern<i32, 2, "SelectShiftImmShifterOperand",
455 [shl,srl,sra,rotr]> {
456 let EncoderMethod = "getSORegImmOpValue";
457 let PrintMethod = "printSORegImmOperand";
458 let MIOperandInfo = (ops GPR, i32imm);
462 // so_imm - Match a 32-bit shifter_operand immediate operand, which is an
463 // 8-bit immediate rotated by an arbitrary number of bits.
464 def SOImmAsmOperand: AsmOperandClass { let Name = "ARMSOImm"; }
465 def so_imm : Operand<i32>, ImmLeaf<i32, [{
466 return ARM_AM::getSOImmVal(Imm) != -1;
468 let EncoderMethod = "getSOImmOpValue";
469 let ParserMatchClass = SOImmAsmOperand;
472 // Break so_imm's up into two pieces. This handles immediates with up to 16
473 // bits set in them. This uses so_imm2part to match and so_imm2part_[12] to
474 // get the first/second pieces.
475 def so_imm2part : PatLeaf<(imm), [{
476 return ARM_AM::isSOImmTwoPartVal((unsigned)N->getZExtValue());
479 /// arm_i32imm - True for +V6T2, or true only if so_imm2part is true.
481 def arm_i32imm : PatLeaf<(imm), [{
482 if (Subtarget->hasV6T2Ops())
484 return ARM_AM::isSOImmTwoPartVal((unsigned)N->getZExtValue());
487 /// imm0_7 predicate - Immediate in the range [0,31].
488 def Imm0_7AsmOperand: AsmOperandClass { let Name = "Imm0_7"; }
489 def imm0_7 : Operand<i32>, ImmLeaf<i32, [{
490 return Imm >= 0 && Imm < 8;
492 let ParserMatchClass = Imm0_7AsmOperand;
495 /// imm0_15 predicate - Immediate in the range [0,31].
496 def Imm0_15AsmOperand: AsmOperandClass { let Name = "Imm0_15"; }
497 def imm0_15 : Operand<i32>, ImmLeaf<i32, [{
498 return Imm >= 0 && Imm < 16;
500 let ParserMatchClass = Imm0_15AsmOperand;
503 /// imm0_31 predicate - True if the 32-bit immediate is in the range [0,31].
504 def Imm0_31AsmOperand: AsmOperandClass { let Name = "Imm0_31"; }
505 def imm0_31 : Operand<i32>, ImmLeaf<i32, [{
506 return Imm >= 0 && Imm < 32;
508 let ParserMatchClass = Imm0_31AsmOperand;
511 /// imm0_31_m1 - Matches and prints like imm0_31, but encodes as 'value - 1'.
512 def imm0_31_m1 : Operand<i32>, ImmLeaf<i32, [{
513 return Imm >= 0 && Imm < 32;
515 let EncoderMethod = "getImmMinusOneOpValue";
516 let DecoderMethod = "DecodeImmMinusOneOperand";
519 // imm0_65535_expr - For movt/movw - 16-bit immediate that can also reference
520 // a relocatable expression.
522 // FIXME: This really needs a Thumb version separate from the ARM version.
523 // While the range is the same, and can thus use the same match class,
524 // the encoding is different so it should have a different encoder method.
525 def Imm0_65535ExprAsmOperand: AsmOperandClass { let Name = "Imm0_65535Expr"; }
526 def imm0_65535_expr : Operand<i32> {
527 let EncoderMethod = "getHiLo16ImmOpValue";
528 let ParserMatchClass = Imm0_65535ExprAsmOperand;
531 /// imm24b - True if the 32-bit immediate is encodable in 24 bits.
532 def Imm24bitAsmOperand: AsmOperandClass { let Name = "Imm24bit"; }
533 def imm24b : Operand<i32>, ImmLeaf<i32, [{
534 return Imm >= 0 && Imm <= 0xffffff;
536 let ParserMatchClass = Imm24bitAsmOperand;
540 /// bf_inv_mask_imm predicate - An AND mask to clear an arbitrary width bitfield
542 def bf_inv_mask_imm : Operand<i32>,
544 return ARM::isBitFieldInvertedMask(N->getZExtValue());
546 let EncoderMethod = "getBitfieldInvertedMaskOpValue";
547 let PrintMethod = "printBitfieldInvMaskImmOperand";
550 /// lsb_pos_imm - position of the lsb bit, used by BFI4p and t2BFI4p
551 def lsb_pos_imm : Operand<i32>, ImmLeaf<i32, [{
552 return isInt<5>(Imm);
555 /// width_imm - number of bits to be copied, used by BFI4p and t2BFI4p
556 def width_imm : Operand<i32>, ImmLeaf<i32, [{
557 return Imm > 0 && Imm <= 32;
559 let EncoderMethod = "getMsbOpValue";
562 def imm1_32_XFORM: SDNodeXForm<imm, [{
563 return CurDAG->getTargetConstant((int)N->getZExtValue() - 1, MVT::i32);
565 def Imm1_32AsmOperand: AsmOperandClass { let Name = "Imm1_32"; }
566 def imm1_32 : Operand<i32>, PatLeaf<(imm), [{ return Imm > 0 && Imm <= 32; }],
568 let PrintMethod = "printImmPlusOneOperand";
569 let ParserMatchClass = Imm1_32AsmOperand;
572 def imm1_16_XFORM: SDNodeXForm<imm, [{
573 return CurDAG->getTargetConstant((int)N->getZExtValue() - 1, MVT::i32);
575 def Imm1_16AsmOperand: AsmOperandClass { let Name = "Imm1_16"; }
576 def imm1_16 : Operand<i32>, PatLeaf<(imm), [{ return Imm > 0 && Imm <= 16; }],
578 let PrintMethod = "printImmPlusOneOperand";
579 let ParserMatchClass = Imm1_16AsmOperand;
582 // Define ARM specific addressing modes.
583 // addrmode_imm12 := reg +/- imm12
585 def addrmode_imm12 : Operand<i32>,
586 ComplexPattern<i32, 2, "SelectAddrModeImm12", []> {
587 // 12-bit immediate operand. Note that instructions using this encode
588 // #0 and #-0 differently. We flag #-0 as the magic value INT32_MIN. All other
589 // immediate values are as normal.
591 let EncoderMethod = "getAddrModeImm12OpValue";
592 let PrintMethod = "printAddrModeImm12Operand";
593 let MIOperandInfo = (ops GPR:$base, i32imm:$offsimm);
595 // ldst_so_reg := reg +/- reg shop imm
597 def ldst_so_reg : Operand<i32>,
598 ComplexPattern<i32, 3, "SelectLdStSOReg", []> {
599 let EncoderMethod = "getLdStSORegOpValue";
600 // FIXME: Simplify the printer
601 let PrintMethod = "printAddrMode2Operand";
602 let MIOperandInfo = (ops GPR:$base, GPR:$offsreg, i32imm:$offsimm);
605 // addrmode2 := reg +/- imm12
606 // := reg +/- reg shop imm
608 def MemMode2AsmOperand : AsmOperandClass {
609 let Name = "MemMode2";
610 let ParserMethod = "parseMemMode2Operand";
612 def addrmode2 : Operand<i32>,
613 ComplexPattern<i32, 3, "SelectAddrMode2", []> {
614 let EncoderMethod = "getAddrMode2OpValue";
615 let PrintMethod = "printAddrMode2Operand";
616 let ParserMatchClass = MemMode2AsmOperand;
617 let MIOperandInfo = (ops GPR:$base, GPR:$offsreg, i32imm:$offsimm);
620 def am2offset_reg : Operand<i32>,
621 ComplexPattern<i32, 2, "SelectAddrMode2OffsetReg",
622 [], [SDNPWantRoot]> {
623 let EncoderMethod = "getAddrMode2OffsetOpValue";
624 let PrintMethod = "printAddrMode2OffsetOperand";
625 let MIOperandInfo = (ops GPR, i32imm);
628 def am2offset_imm : Operand<i32>,
629 ComplexPattern<i32, 2, "SelectAddrMode2OffsetImm",
630 [], [SDNPWantRoot]> {
631 let EncoderMethod = "getAddrMode2OffsetOpValue";
632 let PrintMethod = "printAddrMode2OffsetOperand";
633 let MIOperandInfo = (ops GPR, i32imm);
637 // addrmode3 := reg +/- reg
638 // addrmode3 := reg +/- imm8
640 def MemMode3AsmOperand : AsmOperandClass {
641 let Name = "MemMode3";
642 let ParserMethod = "parseMemMode3Operand";
644 def addrmode3 : Operand<i32>,
645 ComplexPattern<i32, 3, "SelectAddrMode3", []> {
646 let EncoderMethod = "getAddrMode3OpValue";
647 let PrintMethod = "printAddrMode3Operand";
648 let ParserMatchClass = MemMode3AsmOperand;
649 let MIOperandInfo = (ops GPR:$base, GPR:$offsreg, i32imm:$offsimm);
652 def am3offset : Operand<i32>,
653 ComplexPattern<i32, 2, "SelectAddrMode3Offset",
654 [], [SDNPWantRoot]> {
655 let EncoderMethod = "getAddrMode3OffsetOpValue";
656 let PrintMethod = "printAddrMode3OffsetOperand";
657 let MIOperandInfo = (ops GPR, i32imm);
660 // ldstm_mode := {ia, ib, da, db}
662 def ldstm_mode : OptionalDefOperand<OtherVT, (ops i32), (ops (i32 1))> {
663 let EncoderMethod = "getLdStmModeOpValue";
664 let PrintMethod = "printLdStmModeOperand";
667 // addrmode5 := reg +/- imm8*4
669 def MemMode5AsmOperand : AsmOperandClass { let Name = "MemMode5"; }
670 def addrmode5 : Operand<i32>,
671 ComplexPattern<i32, 2, "SelectAddrMode5", []> {
672 let PrintMethod = "printAddrMode5Operand";
673 let MIOperandInfo = (ops GPR:$base, i32imm);
674 let ParserMatchClass = MemMode5AsmOperand;
675 let EncoderMethod = "getAddrMode5OpValue";
678 // addrmode6 := reg with optional alignment
680 def addrmode6 : Operand<i32>,
681 ComplexPattern<i32, 2, "SelectAddrMode6", [], [SDNPWantParent]>{
682 let PrintMethod = "printAddrMode6Operand";
683 let MIOperandInfo = (ops GPR:$addr, i32imm);
684 let EncoderMethod = "getAddrMode6AddressOpValue";
687 def am6offset : Operand<i32>,
688 ComplexPattern<i32, 1, "SelectAddrMode6Offset",
689 [], [SDNPWantRoot]> {
690 let PrintMethod = "printAddrMode6OffsetOperand";
691 let MIOperandInfo = (ops GPR);
692 let EncoderMethod = "getAddrMode6OffsetOpValue";
695 // Special version of addrmode6 to handle alignment encoding for VST1/VLD1
696 // (single element from one lane) for size 32.
697 def addrmode6oneL32 : Operand<i32>,
698 ComplexPattern<i32, 2, "SelectAddrMode6", [], [SDNPWantParent]>{
699 let PrintMethod = "printAddrMode6Operand";
700 let MIOperandInfo = (ops GPR:$addr, i32imm);
701 let EncoderMethod = "getAddrMode6OneLane32AddressOpValue";
704 // Special version of addrmode6 to handle alignment encoding for VLD-dup
705 // instructions, specifically VLD4-dup.
706 def addrmode6dup : Operand<i32>,
707 ComplexPattern<i32, 2, "SelectAddrMode6", [], [SDNPWantParent]>{
708 let PrintMethod = "printAddrMode6Operand";
709 let MIOperandInfo = (ops GPR:$addr, i32imm);
710 let EncoderMethod = "getAddrMode6DupAddressOpValue";
713 // addrmodepc := pc + reg
715 def addrmodepc : Operand<i32>,
716 ComplexPattern<i32, 2, "SelectAddrModePC", []> {
717 let PrintMethod = "printAddrModePCOperand";
718 let MIOperandInfo = (ops GPR, i32imm);
722 // Used by load/store exclusive instructions. Useful to enable right assembly
723 // parsing and printing. Not used for any codegen matching.
725 def MemMode7AsmOperand : AsmOperandClass { let Name = "MemMode7"; }
726 def addrmode7 : Operand<i32> {
727 let PrintMethod = "printAddrMode7Operand";
728 let MIOperandInfo = (ops GPR);
729 let ParserMatchClass = MemMode7AsmOperand;
732 def nohash_imm : Operand<i32> {
733 let PrintMethod = "printNoHashImmediate";
736 def CoprocNumAsmOperand : AsmOperandClass {
737 let Name = "CoprocNum";
738 let ParserMethod = "parseCoprocNumOperand";
740 def p_imm : Operand<i32> {
741 let PrintMethod = "printPImmediate";
742 let ParserMatchClass = CoprocNumAsmOperand;
745 def CoprocRegAsmOperand : AsmOperandClass {
746 let Name = "CoprocReg";
747 let ParserMethod = "parseCoprocRegOperand";
749 def c_imm : Operand<i32> {
750 let PrintMethod = "printCImmediate";
751 let ParserMatchClass = CoprocRegAsmOperand;
754 //===----------------------------------------------------------------------===//
756 include "ARMInstrFormats.td"
758 //===----------------------------------------------------------------------===//
759 // Multiclass helpers...
762 /// AsI1_bin_irs - Defines a set of (op r, {so_imm|r|so_reg}) patterns for a
763 /// binop that produces a value.
764 multiclass AsI1_bin_irs<bits<4> opcod, string opc,
765 InstrItinClass iii, InstrItinClass iir, InstrItinClass iis,
766 PatFrag opnode, string baseOpc, bit Commutable = 0> {
767 // The register-immediate version is re-materializable. This is useful
768 // in particular for taking the address of a local.
769 let isReMaterializable = 1 in {
770 def ri : AsI1<opcod, (outs GPR:$Rd), (ins GPR:$Rn, so_imm:$imm), DPFrm,
771 iii, opc, "\t$Rd, $Rn, $imm",
772 [(set GPR:$Rd, (opnode GPR:$Rn, so_imm:$imm))]> {
777 let Inst{19-16} = Rn;
778 let Inst{15-12} = Rd;
779 let Inst{11-0} = imm;
782 def rr : AsI1<opcod, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm), DPFrm,
783 iir, opc, "\t$Rd, $Rn, $Rm",
784 [(set GPR:$Rd, (opnode GPR:$Rn, GPR:$Rm))]> {
789 let isCommutable = Commutable;
790 let Inst{19-16} = Rn;
791 let Inst{15-12} = Rd;
792 let Inst{11-4} = 0b00000000;
796 def rsi : AsI1<opcod, (outs GPR:$Rd),
797 (ins GPR:$Rn, so_reg_imm:$shift), DPSoRegImmFrm,
798 iis, opc, "\t$Rd, $Rn, $shift",
799 [(set GPR:$Rd, (opnode GPR:$Rn, so_reg_imm:$shift))]> {
804 let Inst{19-16} = Rn;
805 let Inst{15-12} = Rd;
806 let Inst{11-5} = shift{11-5};
808 let Inst{3-0} = shift{3-0};
811 def rsr : AsI1<opcod, (outs GPR:$Rd),
812 (ins GPR:$Rn, so_reg_reg:$shift), DPSoRegRegFrm,
813 iis, opc, "\t$Rd, $Rn, $shift",
814 [(set GPR:$Rd, (opnode GPR:$Rn, so_reg_reg:$shift))]> {
819 let Inst{19-16} = Rn;
820 let Inst{15-12} = Rd;
821 let Inst{11-8} = shift{11-8};
823 let Inst{6-5} = shift{6-5};
825 let Inst{3-0} = shift{3-0};
828 // Assembly aliases for optional destination operand when it's the same
829 // as the source operand.
830 def : InstAlias<!strconcat(opc, "${s}${p} $Rdn, $imm"),
831 (!cast<Instruction>(!strconcat(baseOpc, "ri")) GPR:$Rdn, GPR:$Rdn,
832 so_imm:$imm, pred:$p,
835 def : InstAlias<!strconcat(opc, "${s}${p} $Rdn, $Rm"),
836 (!cast<Instruction>(!strconcat(baseOpc, "rr")) GPR:$Rdn, GPR:$Rdn,
840 def : InstAlias<!strconcat(opc, "${s}${p} $Rdn, $shift"),
841 (!cast<Instruction>(!strconcat(baseOpc, "rsi")) GPR:$Rdn, GPR:$Rdn,
842 so_reg_imm:$shift, pred:$p,
845 def : InstAlias<!strconcat(opc, "${s}${p} $Rdn, $shift"),
846 (!cast<Instruction>(!strconcat(baseOpc, "rsr")) GPR:$Rdn, GPR:$Rdn,
847 so_reg_reg:$shift, pred:$p,
853 /// AI1_bin_s_irs - Similar to AsI1_bin_irs except it sets the 's' bit so the
854 /// instruction modifies the CPSR register.
855 let isCodeGenOnly = 1, Defs = [CPSR] in {
856 multiclass AI1_bin_s_irs<bits<4> opcod, string opc,
857 InstrItinClass iii, InstrItinClass iir, InstrItinClass iis,
858 PatFrag opnode, bit Commutable = 0> {
859 def ri : AI1<opcod, (outs GPR:$Rd), (ins GPR:$Rn, so_imm:$imm), DPFrm,
860 iii, opc, "\t$Rd, $Rn, $imm",
861 [(set GPR:$Rd, (opnode GPR:$Rn, so_imm:$imm))]> {
867 let Inst{19-16} = Rn;
868 let Inst{15-12} = Rd;
869 let Inst{11-0} = imm;
871 def rr : AI1<opcod, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm), DPFrm,
872 iir, opc, "\t$Rd, $Rn, $Rm",
873 [(set GPR:$Rd, (opnode GPR:$Rn, GPR:$Rm))]> {
877 let isCommutable = Commutable;
880 let Inst{19-16} = Rn;
881 let Inst{15-12} = Rd;
882 let Inst{11-4} = 0b00000000;
885 def rsi : AI1<opcod, (outs GPR:$Rd),
886 (ins GPR:$Rn, so_reg_imm:$shift), DPSoRegImmFrm,
887 iis, opc, "\t$Rd, $Rn, $shift",
888 [(set GPR:$Rd, (opnode GPR:$Rn, so_reg_imm:$shift))]> {
894 let Inst{19-16} = Rn;
895 let Inst{15-12} = Rd;
896 let Inst{11-5} = shift{11-5};
898 let Inst{3-0} = shift{3-0};
901 def rsr : AI1<opcod, (outs GPR:$Rd),
902 (ins GPR:$Rn, so_reg_reg:$shift), DPSoRegRegFrm,
903 iis, opc, "\t$Rd, $Rn, $shift",
904 [(set GPR:$Rd, (opnode GPR:$Rn, so_reg_reg:$shift))]> {
910 let Inst{19-16} = Rn;
911 let Inst{15-12} = Rd;
912 let Inst{11-8} = shift{11-8};
914 let Inst{6-5} = shift{6-5};
916 let Inst{3-0} = shift{3-0};
921 /// AI1_cmp_irs - Defines a set of (op r, {so_imm|r|so_reg}) cmp / test
922 /// patterns. Similar to AsI1_bin_irs except the instruction does not produce
923 /// a explicit result, only implicitly set CPSR.
924 let isCompare = 1, Defs = [CPSR] in {
925 multiclass AI1_cmp_irs<bits<4> opcod, string opc,
926 InstrItinClass iii, InstrItinClass iir, InstrItinClass iis,
927 PatFrag opnode, bit Commutable = 0> {
928 def ri : AI1<opcod, (outs), (ins GPR:$Rn, so_imm:$imm), DPFrm, iii,
930 [(opnode GPR:$Rn, so_imm:$imm)]> {
935 let Inst{19-16} = Rn;
936 let Inst{15-12} = 0b0000;
937 let Inst{11-0} = imm;
939 def rr : AI1<opcod, (outs), (ins GPR:$Rn, GPR:$Rm), DPFrm, iir,
941 [(opnode GPR:$Rn, GPR:$Rm)]> {
944 let isCommutable = Commutable;
947 let Inst{19-16} = Rn;
948 let Inst{15-12} = 0b0000;
949 let Inst{11-4} = 0b00000000;
952 def rsi : AI1<opcod, (outs),
953 (ins GPR:$Rn, so_reg_imm:$shift), DPSoRegImmFrm, iis,
954 opc, "\t$Rn, $shift",
955 [(opnode GPR:$Rn, so_reg_imm:$shift)]> {
960 let Inst{19-16} = Rn;
961 let Inst{15-12} = 0b0000;
962 let Inst{11-5} = shift{11-5};
964 let Inst{3-0} = shift{3-0};
966 def rsr : AI1<opcod, (outs),
967 (ins GPR:$Rn, so_reg_reg:$shift), DPSoRegRegFrm, iis,
968 opc, "\t$Rn, $shift",
969 [(opnode GPR:$Rn, so_reg_reg:$shift)]> {
974 let Inst{19-16} = Rn;
975 let Inst{15-12} = 0b0000;
976 let Inst{11-8} = shift{11-8};
978 let Inst{6-5} = shift{6-5};
980 let Inst{3-0} = shift{3-0};
986 /// AI_ext_rrot - A unary operation with two forms: one whose operand is a
987 /// register and one whose operand is a register rotated by 8/16/24.
988 /// FIXME: Remove the 'r' variant. Its rot_imm is zero.
989 class AI_ext_rrot<bits<8> opcod, string opc, PatFrag opnode>
990 : AExtI<opcod, (outs GPR:$Rd), (ins GPR:$Rm, rot_imm:$rot),
991 IIC_iEXTr, opc, "\t$Rd, $Rm$rot",
992 [(set GPR:$Rd, (opnode (rotr GPR:$Rm, rot_imm:$rot)))]>,
993 Requires<[IsARM, HasV6]> {
997 let Inst{19-16} = 0b1111;
998 let Inst{15-12} = Rd;
999 let Inst{11-10} = rot;
1003 class AI_ext_rrot_np<bits<8> opcod, string opc>
1004 : AExtI<opcod, (outs GPR:$Rd), (ins GPR:$Rm, rot_imm:$rot),
1005 IIC_iEXTr, opc, "\t$Rd, $Rm$rot", []>,
1006 Requires<[IsARM, HasV6]> {
1008 let Inst{19-16} = 0b1111;
1009 let Inst{11-10} = rot;
1012 /// AI_exta_rrot - A binary operation with two forms: one whose operand is a
1013 /// register and one whose operand is a register rotated by 8/16/24.
1014 class AI_exta_rrot<bits<8> opcod, string opc, PatFrag opnode>
1015 : AExtI<opcod, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm, rot_imm:$rot),
1016 IIC_iEXTAr, opc, "\t$Rd, $Rn, $Rm$rot",
1017 [(set GPR:$Rd, (opnode GPR:$Rn, (rotr GPR:$Rm, rot_imm:$rot)))]>,
1018 Requires<[IsARM, HasV6]> {
1023 let Inst{19-16} = Rn;
1024 let Inst{15-12} = Rd;
1025 let Inst{11-10} = rot;
1026 let Inst{9-4} = 0b000111;
1030 class AI_exta_rrot_np<bits<8> opcod, string opc>
1031 : AExtI<opcod, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm, rot_imm:$rot),
1032 IIC_iEXTAr, opc, "\t$Rd, $Rn, $Rm$rot", []>,
1033 Requires<[IsARM, HasV6]> {
1036 let Inst{19-16} = Rn;
1037 let Inst{11-10} = rot;
1040 /// AI1_adde_sube_irs - Define instructions and patterns for adde and sube.
1041 multiclass AI1_adde_sube_irs<bits<4> opcod, string opc, PatFrag opnode,
1042 string baseOpc, bit Commutable = 0> {
1043 let Uses = [CPSR] in {
1044 def ri : AsI1<opcod, (outs GPR:$Rd), (ins GPR:$Rn, so_imm:$imm),
1045 DPFrm, IIC_iALUi, opc, "\t$Rd, $Rn, $imm",
1046 [(set GPR:$Rd, (opnode GPR:$Rn, so_imm:$imm))]>,
1052 let Inst{15-12} = Rd;
1053 let Inst{19-16} = Rn;
1054 let Inst{11-0} = imm;
1056 def rr : AsI1<opcod, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm),
1057 DPFrm, IIC_iALUr, opc, "\t$Rd, $Rn, $Rm",
1058 [(set GPR:$Rd, (opnode GPR:$Rn, GPR:$Rm))]>,
1063 let Inst{11-4} = 0b00000000;
1065 let isCommutable = Commutable;
1067 let Inst{15-12} = Rd;
1068 let Inst{19-16} = Rn;
1070 def rsi : AsI1<opcod, (outs GPR:$Rd),
1071 (ins GPR:$Rn, so_reg_imm:$shift),
1072 DPSoRegImmFrm, IIC_iALUsr, opc, "\t$Rd, $Rn, $shift",
1073 [(set GPR:$Rd, (opnode GPR:$Rn, so_reg_imm:$shift))]>,
1079 let Inst{19-16} = Rn;
1080 let Inst{15-12} = Rd;
1081 let Inst{11-5} = shift{11-5};
1083 let Inst{3-0} = shift{3-0};
1085 def rsr : AsI1<opcod, (outs GPR:$Rd),
1086 (ins GPR:$Rn, so_reg_reg:$shift),
1087 DPSoRegRegFrm, IIC_iALUsr, opc, "\t$Rd, $Rn, $shift",
1088 [(set GPR:$Rd, (opnode GPR:$Rn, so_reg_reg:$shift))]>,
1094 let Inst{19-16} = Rn;
1095 let Inst{15-12} = Rd;
1096 let Inst{11-8} = shift{11-8};
1098 let Inst{6-5} = shift{6-5};
1100 let Inst{3-0} = shift{3-0};
1103 // Assembly aliases for optional destination operand when it's the same
1104 // as the source operand.
1105 def : InstAlias<!strconcat(opc, "${s}${p} $Rdn, $imm"),
1106 (!cast<Instruction>(!strconcat(baseOpc, "ri")) GPR:$Rdn, GPR:$Rdn,
1107 so_imm:$imm, pred:$p,
1110 def : InstAlias<!strconcat(opc, "${s}${p} $Rdn, $Rm"),
1111 (!cast<Instruction>(!strconcat(baseOpc, "rr")) GPR:$Rdn, GPR:$Rdn,
1115 def : InstAlias<!strconcat(opc, "${s}${p} $Rdn, $shift"),
1116 (!cast<Instruction>(!strconcat(baseOpc, "rsi")) GPR:$Rdn, GPR:$Rdn,
1117 so_reg_imm:$shift, pred:$p,
1120 def : InstAlias<!strconcat(opc, "${s}${p} $Rdn, $shift"),
1121 (!cast<Instruction>(!strconcat(baseOpc, "rsr")) GPR:$Rdn, GPR:$Rdn,
1122 so_reg_reg:$shift, pred:$p,
1127 // Carry setting variants
1128 // NOTE: CPSR def omitted because it will be handled by the custom inserter.
1129 let usesCustomInserter = 1 in {
1130 multiclass AI1_adde_sube_s_irs<PatFrag opnode, bit Commutable = 0> {
1131 def ri : ARMPseudoInst<(outs GPR:$Rd), (ins GPR:$Rn, so_imm:$imm),
1133 [(set GPR:$Rd, (opnode GPR:$Rn, so_imm:$imm))]>;
1134 def rr : ARMPseudoInst<(outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm),
1136 [(set GPR:$Rd, (opnode GPR:$Rn, GPR:$Rm))]> {
1137 let isCommutable = Commutable;
1139 def rsi : ARMPseudoInst<(outs GPR:$Rd), (ins GPR:$Rn, so_reg_imm:$shift),
1141 [(set GPR:$Rd, (opnode GPR:$Rn, so_reg_imm:$shift))]>;
1142 def rsr : ARMPseudoInst<(outs GPR:$Rd), (ins GPR:$Rn, so_reg_reg:$shift),
1144 [(set GPR:$Rd, (opnode GPR:$Rn, so_reg_reg:$shift))]>;
1148 let canFoldAsLoad = 1, isReMaterializable = 1 in {
1149 multiclass AI_ldr1<bit isByte, string opc, InstrItinClass iii,
1150 InstrItinClass iir, PatFrag opnode> {
1151 // Note: We use the complex addrmode_imm12 rather than just an input
1152 // GPR and a constrained immediate so that we can use this to match
1153 // frame index references and avoid matching constant pool references.
1154 def i12: AI2ldst<0b010, 1, isByte, (outs GPR:$Rt), (ins addrmode_imm12:$addr),
1155 AddrMode_i12, LdFrm, iii, opc, "\t$Rt, $addr",
1156 [(set GPR:$Rt, (opnode addrmode_imm12:$addr))]> {
1159 let Inst{23} = addr{12}; // U (add = ('U' == 1))
1160 let Inst{19-16} = addr{16-13}; // Rn
1161 let Inst{15-12} = Rt;
1162 let Inst{11-0} = addr{11-0}; // imm12
1164 def rs : AI2ldst<0b011, 1, isByte, (outs GPR:$Rt), (ins ldst_so_reg:$shift),
1165 AddrModeNone, LdFrm, iir, opc, "\t$Rt, $shift",
1166 [(set GPR:$Rt, (opnode ldst_so_reg:$shift))]> {
1169 let shift{4} = 0; // Inst{4} = 0
1170 let Inst{23} = shift{12}; // U (add = ('U' == 1))
1171 let Inst{19-16} = shift{16-13}; // Rn
1172 let Inst{15-12} = Rt;
1173 let Inst{11-0} = shift{11-0};
1178 multiclass AI_str1<bit isByte, string opc, InstrItinClass iii,
1179 InstrItinClass iir, PatFrag opnode> {
1180 // Note: We use the complex addrmode_imm12 rather than just an input
1181 // GPR and a constrained immediate so that we can use this to match
1182 // frame index references and avoid matching constant pool references.
1183 def i12 : AI2ldst<0b010, 0, isByte, (outs),
1184 (ins GPR:$Rt, addrmode_imm12:$addr),
1185 AddrMode_i12, StFrm, iii, opc, "\t$Rt, $addr",
1186 [(opnode GPR:$Rt, addrmode_imm12:$addr)]> {
1189 let Inst{23} = addr{12}; // U (add = ('U' == 1))
1190 let Inst{19-16} = addr{16-13}; // Rn
1191 let Inst{15-12} = Rt;
1192 let Inst{11-0} = addr{11-0}; // imm12
1194 def rs : AI2ldst<0b011, 0, isByte, (outs), (ins GPR:$Rt, ldst_so_reg:$shift),
1195 AddrModeNone, StFrm, iir, opc, "\t$Rt, $shift",
1196 [(opnode GPR:$Rt, ldst_so_reg:$shift)]> {
1199 let shift{4} = 0; // Inst{4} = 0
1200 let Inst{23} = shift{12}; // U (add = ('U' == 1))
1201 let Inst{19-16} = shift{16-13}; // Rn
1202 let Inst{15-12} = Rt;
1203 let Inst{11-0} = shift{11-0};
1206 //===----------------------------------------------------------------------===//
1208 //===----------------------------------------------------------------------===//
1210 //===----------------------------------------------------------------------===//
1211 // Miscellaneous Instructions.
1214 /// CONSTPOOL_ENTRY - This instruction represents a floating constant pool in
1215 /// the function. The first operand is the ID# for this instruction, the second
1216 /// is the index into the MachineConstantPool that this is, the third is the
1217 /// size in bytes of this constant pool entry.
1218 let neverHasSideEffects = 1, isNotDuplicable = 1 in
1219 def CONSTPOOL_ENTRY :
1220 PseudoInst<(outs), (ins cpinst_operand:$instid, cpinst_operand:$cpidx,
1221 i32imm:$size), NoItinerary, []>;
1223 // FIXME: Marking these as hasSideEffects is necessary to prevent machine DCE
1224 // from removing one half of the matched pairs. That breaks PEI, which assumes
1225 // these will always be in pairs, and asserts if it finds otherwise. Better way?
1226 let Defs = [SP], Uses = [SP], hasSideEffects = 1 in {
1227 def ADJCALLSTACKUP :
1228 PseudoInst<(outs), (ins i32imm:$amt1, i32imm:$amt2, pred:$p), NoItinerary,
1229 [(ARMcallseq_end timm:$amt1, timm:$amt2)]>;
1231 def ADJCALLSTACKDOWN :
1232 PseudoInst<(outs), (ins i32imm:$amt, pred:$p), NoItinerary,
1233 [(ARMcallseq_start timm:$amt)]>;
1236 def NOP : AI<(outs), (ins), MiscFrm, NoItinerary, "nop", "",
1237 [/* For disassembly only; pattern left blank */]>,
1238 Requires<[IsARM, HasV6T2]> {
1239 let Inst{27-16} = 0b001100100000;
1240 let Inst{15-8} = 0b11110000;
1241 let Inst{7-0} = 0b00000000;
1244 def YIELD : AI<(outs), (ins), MiscFrm, NoItinerary, "yield", "",
1245 [/* For disassembly only; pattern left blank */]>,
1246 Requires<[IsARM, HasV6T2]> {
1247 let Inst{27-16} = 0b001100100000;
1248 let Inst{15-8} = 0b11110000;
1249 let Inst{7-0} = 0b00000001;
1252 def WFE : AI<(outs), (ins), MiscFrm, NoItinerary, "wfe", "",
1253 [/* For disassembly only; pattern left blank */]>,
1254 Requires<[IsARM, HasV6T2]> {
1255 let Inst{27-16} = 0b001100100000;
1256 let Inst{15-8} = 0b11110000;
1257 let Inst{7-0} = 0b00000010;
1260 def WFI : AI<(outs), (ins), MiscFrm, NoItinerary, "wfi", "",
1261 [/* For disassembly only; pattern left blank */]>,
1262 Requires<[IsARM, HasV6T2]> {
1263 let Inst{27-16} = 0b001100100000;
1264 let Inst{15-8} = 0b11110000;
1265 let Inst{7-0} = 0b00000011;
1268 def SEL : AI<(outs GPR:$dst), (ins GPR:$a, GPR:$b), DPFrm, NoItinerary, "sel",
1269 "\t$dst, $a, $b", []>, Requires<[IsARM, HasV6]> {
1274 let Inst{15-12} = Rd;
1275 let Inst{19-16} = Rn;
1276 let Inst{27-20} = 0b01101000;
1277 let Inst{7-4} = 0b1011;
1278 let Inst{11-8} = 0b1111;
1281 def SEV : AI<(outs), (ins), MiscFrm, NoItinerary, "sev", "",
1282 []>, Requires<[IsARM, HasV6T2]> {
1283 let Inst{27-16} = 0b001100100000;
1284 let Inst{15-8} = 0b11110000;
1285 let Inst{7-0} = 0b00000100;
1288 // The i32imm operand $val can be used by a debugger to store more information
1289 // about the breakpoint.
1290 def BKPT : AI<(outs), (ins imm0_65535:$val), MiscFrm, NoItinerary,
1291 "bkpt", "\t$val", []>, Requires<[IsARM]> {
1293 let Inst{3-0} = val{3-0};
1294 let Inst{19-8} = val{15-4};
1295 let Inst{27-20} = 0b00010010;
1296 let Inst{7-4} = 0b0111;
1299 // Change Processor State is a system instruction -- for disassembly and
1301 // FIXME: Since the asm parser has currently no clean way to handle optional
1302 // operands, create 3 versions of the same instruction. Once there's a clean
1303 // framework to represent optional operands, change this behavior.
1304 class CPS<dag iops, string asm_ops>
1305 : AXI<(outs), iops, MiscFrm, NoItinerary, !strconcat("cps", asm_ops),
1306 [/* For disassembly only; pattern left blank */]>, Requires<[IsARM]> {
1312 let Inst{31-28} = 0b1111;
1313 let Inst{27-20} = 0b00010000;
1314 let Inst{19-18} = imod;
1315 let Inst{17} = M; // Enabled if mode is set;
1317 let Inst{8-6} = iflags;
1319 let Inst{4-0} = mode;
1323 def CPS3p : CPS<(ins imod_op:$imod, iflags_op:$iflags, i32imm:$mode),
1324 "$imod\t$iflags, $mode">;
1325 let mode = 0, M = 0 in
1326 def CPS2p : CPS<(ins imod_op:$imod, iflags_op:$iflags), "$imod\t$iflags">;
1328 let imod = 0, iflags = 0, M = 1 in
1329 def CPS1p : CPS<(ins i32imm:$mode), "\t$mode">;
1331 // Preload signals the memory system of possible future data/instruction access.
1332 // These are for disassembly only.
1333 multiclass APreLoad<bits<1> read, bits<1> data, string opc> {
1335 def i12 : AXI<(outs), (ins addrmode_imm12:$addr), MiscFrm, IIC_Preload,
1336 !strconcat(opc, "\t$addr"),
1337 [(ARMPreload addrmode_imm12:$addr, (i32 read), (i32 data))]> {
1340 let Inst{31-26} = 0b111101;
1341 let Inst{25} = 0; // 0 for immediate form
1342 let Inst{24} = data;
1343 let Inst{23} = addr{12}; // U (add = ('U' == 1))
1344 let Inst{22} = read;
1345 let Inst{21-20} = 0b01;
1346 let Inst{19-16} = addr{16-13}; // Rn
1347 let Inst{15-12} = 0b1111;
1348 let Inst{11-0} = addr{11-0}; // imm12
1351 def rs : AXI<(outs), (ins ldst_so_reg:$shift), MiscFrm, IIC_Preload,
1352 !strconcat(opc, "\t$shift"),
1353 [(ARMPreload ldst_so_reg:$shift, (i32 read), (i32 data))]> {
1355 let Inst{31-26} = 0b111101;
1356 let Inst{25} = 1; // 1 for register form
1357 let Inst{24} = data;
1358 let Inst{23} = shift{12}; // U (add = ('U' == 1))
1359 let Inst{22} = read;
1360 let Inst{21-20} = 0b01;
1361 let Inst{19-16} = shift{16-13}; // Rn
1362 let Inst{15-12} = 0b1111;
1363 let Inst{11-0} = shift{11-0};
1367 defm PLD : APreLoad<1, 1, "pld">, Requires<[IsARM]>;
1368 defm PLDW : APreLoad<0, 1, "pldw">, Requires<[IsARM,HasV7,HasMP]>;
1369 defm PLI : APreLoad<1, 0, "pli">, Requires<[IsARM,HasV7]>;
1371 def SETEND : AXI<(outs), (ins setend_op:$end), MiscFrm, NoItinerary,
1372 "setend\t$end", []>, Requires<[IsARM]> {
1374 let Inst{31-10} = 0b1111000100000001000000;
1379 def DBG : AI<(outs), (ins imm0_15:$opt), MiscFrm, NoItinerary, "dbg", "\t$opt",
1380 []>, Requires<[IsARM, HasV7]> {
1382 let Inst{27-4} = 0b001100100000111100001111;
1383 let Inst{3-0} = opt;
1386 // A5.4 Permanently UNDEFINED instructions.
1387 let isBarrier = 1, isTerminator = 1 in
1388 def TRAP : AXI<(outs), (ins), MiscFrm, NoItinerary,
1391 let Inst = 0xe7ffdefe;
1394 // Address computation and loads and stores in PIC mode.
1395 let isNotDuplicable = 1 in {
1396 def PICADD : ARMPseudoInst<(outs GPR:$dst), (ins GPR:$a, pclabel:$cp, pred:$p),
1398 [(set GPR:$dst, (ARMpic_add GPR:$a, imm:$cp))]>;
1400 let AddedComplexity = 10 in {
1401 def PICLDR : ARMPseudoInst<(outs GPR:$dst), (ins addrmodepc:$addr, pred:$p),
1403 [(set GPR:$dst, (load addrmodepc:$addr))]>;
1405 def PICLDRH : ARMPseudoInst<(outs GPR:$Rt), (ins addrmodepc:$addr, pred:$p),
1407 [(set GPR:$Rt, (zextloadi16 addrmodepc:$addr))]>;
1409 def PICLDRB : ARMPseudoInst<(outs GPR:$Rt), (ins addrmodepc:$addr, pred:$p),
1411 [(set GPR:$Rt, (zextloadi8 addrmodepc:$addr))]>;
1413 def PICLDRSH : ARMPseudoInst<(outs GPR:$Rt), (ins addrmodepc:$addr, pred:$p),
1415 [(set GPR:$Rt, (sextloadi16 addrmodepc:$addr))]>;
1417 def PICLDRSB : ARMPseudoInst<(outs GPR:$Rt), (ins addrmodepc:$addr, pred:$p),
1419 [(set GPR:$Rt, (sextloadi8 addrmodepc:$addr))]>;
1421 let AddedComplexity = 10 in {
1422 def PICSTR : ARMPseudoInst<(outs), (ins GPR:$src, addrmodepc:$addr, pred:$p),
1423 4, IIC_iStore_r, [(store GPR:$src, addrmodepc:$addr)]>;
1425 def PICSTRH : ARMPseudoInst<(outs), (ins GPR:$src, addrmodepc:$addr, pred:$p),
1426 4, IIC_iStore_bh_r, [(truncstorei16 GPR:$src,
1427 addrmodepc:$addr)]>;
1429 def PICSTRB : ARMPseudoInst<(outs), (ins GPR:$src, addrmodepc:$addr, pred:$p),
1430 4, IIC_iStore_bh_r, [(truncstorei8 GPR:$src, addrmodepc:$addr)]>;
1432 } // isNotDuplicable = 1
1435 // LEApcrel - Load a pc-relative address into a register without offending the
1437 let neverHasSideEffects = 1, isReMaterializable = 1 in
1438 // The 'adr' mnemonic encodes differently if the label is before or after
1439 // the instruction. The {24-21} opcode bits are set by the fixup, as we don't
1440 // know until then which form of the instruction will be used.
1441 def ADR : AI1<{0,?,?,0}, (outs GPR:$Rd), (ins adrlabel:$label),
1442 MiscFrm, IIC_iALUi, "adr", "\t$Rd, #$label", []> {
1445 let Inst{27-25} = 0b001;
1447 let Inst{19-16} = 0b1111;
1448 let Inst{15-12} = Rd;
1449 let Inst{11-0} = label;
1451 def LEApcrel : ARMPseudoInst<(outs GPR:$Rd), (ins i32imm:$label, pred:$p),
1454 def LEApcrelJT : ARMPseudoInst<(outs GPR:$Rd),
1455 (ins i32imm:$label, nohash_imm:$id, pred:$p),
1458 //===----------------------------------------------------------------------===//
1459 // Control Flow Instructions.
1462 let isReturn = 1, isTerminator = 1, isBarrier = 1 in {
1464 def BX_RET : AI<(outs), (ins), BrMiscFrm, IIC_Br,
1465 "bx", "\tlr", [(ARMretflag)]>,
1466 Requires<[IsARM, HasV4T]> {
1467 let Inst{27-0} = 0b0001001011111111111100011110;
1471 def MOVPCLR : AI<(outs), (ins), BrMiscFrm, IIC_Br,
1472 "mov", "\tpc, lr", [(ARMretflag)]>,
1473 Requires<[IsARM, NoV4T]> {
1474 let Inst{27-0} = 0b0001101000001111000000001110;
1478 // Indirect branches
1479 let isBranch = 1, isTerminator = 1, isBarrier = 1, isIndirectBranch = 1 in {
1481 def BX : AXI<(outs), (ins GPR:$dst), BrMiscFrm, IIC_Br, "bx\t$dst",
1482 [(brind GPR:$dst)]>,
1483 Requires<[IsARM, HasV4T]> {
1485 let Inst{31-4} = 0b1110000100101111111111110001;
1486 let Inst{3-0} = dst;
1489 def BX_pred : AI<(outs), (ins GPR:$dst), BrMiscFrm, IIC_Br,
1490 "bx", "\t$dst", [/* pattern left blank */]>,
1491 Requires<[IsARM, HasV4T]> {
1493 let Inst{27-4} = 0b000100101111111111110001;
1494 let Inst{3-0} = dst;
1498 // All calls clobber the non-callee saved registers. SP is marked as
1499 // a use to prevent stack-pointer assignments that appear immediately
1500 // before calls from potentially appearing dead.
1502 // On non-Darwin platforms R9 is callee-saved.
1503 // FIXME: Do we really need a non-predicated version? If so, it should
1504 // at least be a pseudo instruction expanding to the predicated version
1505 // at MC lowering time.
1506 Defs = [R0, R1, R2, R3, R12, LR, QQQQ0, QQQQ2, QQQQ3, CPSR, FPSCR],
1508 def BL : ABXI<0b1011, (outs), (ins bl_target:$func, variable_ops),
1509 IIC_Br, "bl\t$func",
1510 [(ARMcall tglobaladdr:$func)]>,
1511 Requires<[IsARM, IsNotDarwin]> {
1512 let Inst{31-28} = 0b1110;
1514 let Inst{23-0} = func;
1517 def BL_pred : ABI<0b1011, (outs), (ins bl_target:$func, variable_ops),
1518 IIC_Br, "bl", "\t$func",
1519 [(ARMcall_pred tglobaladdr:$func)]>,
1520 Requires<[IsARM, IsNotDarwin]> {
1522 let Inst{23-0} = func;
1526 def BLX : AXI<(outs), (ins GPR:$func, variable_ops), BrMiscFrm,
1527 IIC_Br, "blx\t$func",
1528 [(ARMcall GPR:$func)]>,
1529 Requires<[IsARM, HasV5T, IsNotDarwin]> {
1531 let Inst{31-4} = 0b1110000100101111111111110011;
1532 let Inst{3-0} = func;
1535 def BLX_pred : AI<(outs), (ins GPR:$func, variable_ops), BrMiscFrm,
1536 IIC_Br, "blx", "\t$func",
1537 [(ARMcall_pred GPR:$func)]>,
1538 Requires<[IsARM, HasV5T, IsNotDarwin]> {
1540 let Inst{27-4} = 0b000100101111111111110011;
1541 let Inst{3-0} = func;
1545 // Note: Restrict $func to the tGPR regclass to prevent it being in LR.
1546 def BX_CALL : ARMPseudoInst<(outs), (ins tGPR:$func, variable_ops),
1547 8, IIC_Br, [(ARMcall_nolink tGPR:$func)]>,
1548 Requires<[IsARM, HasV4T, IsNotDarwin]>;
1551 def BMOVPCRX_CALL : ARMPseudoInst<(outs), (ins tGPR:$func, variable_ops),
1552 8, IIC_Br, [(ARMcall_nolink tGPR:$func)]>,
1553 Requires<[IsARM, NoV4T, IsNotDarwin]>;
1557 // On Darwin R9 is call-clobbered.
1558 // R7 is marked as a use to prevent frame-pointer assignments from being
1559 // moved above / below calls.
1560 Defs = [R0, R1, R2, R3, R9, R12, LR, QQQQ0, QQQQ2, QQQQ3, CPSR, FPSCR],
1561 Uses = [R7, SP] in {
1562 def BLr9 : ARMPseudoExpand<(outs), (ins bl_target:$func, variable_ops),
1564 [(ARMcall tglobaladdr:$func)], (BL bl_target:$func)>,
1565 Requires<[IsARM, IsDarwin]>;
1567 def BLr9_pred : ARMPseudoExpand<(outs),
1568 (ins bl_target:$func, pred:$p, variable_ops),
1570 [(ARMcall_pred tglobaladdr:$func)],
1571 (BL_pred bl_target:$func, pred:$p)>,
1572 Requires<[IsARM, IsDarwin]>;
1575 def BLXr9 : ARMPseudoExpand<(outs), (ins GPR:$func, variable_ops),
1577 [(ARMcall GPR:$func)],
1579 Requires<[IsARM, HasV5T, IsDarwin]>;
1581 def BLXr9_pred: ARMPseudoExpand<(outs), (ins GPR:$func, pred:$p,variable_ops),
1583 [(ARMcall_pred GPR:$func)],
1584 (BLX_pred GPR:$func, pred:$p)>,
1585 Requires<[IsARM, HasV5T, IsDarwin]>;
1588 // Note: Restrict $func to the tGPR regclass to prevent it being in LR.
1589 def BXr9_CALL : ARMPseudoInst<(outs), (ins tGPR:$func, variable_ops),
1590 8, IIC_Br, [(ARMcall_nolink tGPR:$func)]>,
1591 Requires<[IsARM, HasV4T, IsDarwin]>;
1594 def BMOVPCRXr9_CALL : ARMPseudoInst<(outs), (ins tGPR:$func, variable_ops),
1595 8, IIC_Br, [(ARMcall_nolink tGPR:$func)]>,
1596 Requires<[IsARM, NoV4T, IsDarwin]>;
1599 let isBranch = 1, isTerminator = 1 in {
1600 // FIXME: should be able to write a pattern for ARMBrcond, but can't use
1601 // a two-value operand where a dag node expects two operands. :(
1602 def Bcc : ABI<0b1010, (outs), (ins br_target:$target),
1603 IIC_Br, "b", "\t$target",
1604 [/*(ARMbrcond bb:$target, imm:$cc, CCR:$ccr)*/]> {
1606 let Inst{23-0} = target;
1609 let isBarrier = 1 in {
1610 // B is "predicable" since it's just a Bcc with an 'always' condition.
1611 let isPredicable = 1 in
1612 // FIXME: We shouldn't need this pseudo at all. Just using Bcc directly
1613 // should be sufficient.
1614 // FIXME: Is B really a Barrier? That doesn't seem right.
1615 def B : ARMPseudoExpand<(outs), (ins br_target:$target), 4, IIC_Br,
1616 [(br bb:$target)], (Bcc br_target:$target, (ops 14, zero_reg))>;
1618 let isNotDuplicable = 1, isIndirectBranch = 1 in {
1619 def BR_JTr : ARMPseudoInst<(outs),
1620 (ins GPR:$target, i32imm:$jt, i32imm:$id),
1622 [(ARMbrjt GPR:$target, tjumptable:$jt, imm:$id)]>;
1623 // FIXME: This shouldn't use the generic "addrmode2," but rather be split
1624 // into i12 and rs suffixed versions.
1625 def BR_JTm : ARMPseudoInst<(outs),
1626 (ins addrmode2:$target, i32imm:$jt, i32imm:$id),
1628 [(ARMbrjt (i32 (load addrmode2:$target)), tjumptable:$jt,
1630 def BR_JTadd : ARMPseudoInst<(outs),
1631 (ins GPR:$target, GPR:$idx, i32imm:$jt, i32imm:$id),
1633 [(ARMbrjt (add GPR:$target, GPR:$idx), tjumptable:$jt,
1635 } // isNotDuplicable = 1, isIndirectBranch = 1
1640 // BLX (immediate) -- for disassembly only
1641 def BLXi : AXI<(outs), (ins br_target:$target), BrMiscFrm, NoItinerary,
1642 "blx\t$target", [/* pattern left blank */]>,
1643 Requires<[IsARM, HasV5T]> {
1644 let Inst{31-25} = 0b1111101;
1646 let Inst{23-0} = target{24-1};
1647 let Inst{24} = target{0};
1650 // Branch and Exchange Jazelle
1651 def BXJ : ABI<0b0001, (outs), (ins GPR:$func), NoItinerary, "bxj", "\t$func",
1652 [/* pattern left blank */]> {
1654 let Inst{23-20} = 0b0010;
1655 let Inst{19-8} = 0xfff;
1656 let Inst{7-4} = 0b0010;
1657 let Inst{3-0} = func;
1662 let isCall = 1, isTerminator = 1, isReturn = 1, isBarrier = 1 in {
1664 let Defs = [R0, R1, R2, R3, R9, R12, QQQQ0, QQQQ2, QQQQ3, PC],
1666 def TCRETURNdi : PseudoInst<(outs), (ins i32imm:$dst, variable_ops),
1667 IIC_Br, []>, Requires<[IsDarwin]>;
1669 def TCRETURNri : PseudoInst<(outs), (ins tcGPR:$dst, variable_ops),
1670 IIC_Br, []>, Requires<[IsDarwin]>;
1672 def TAILJMPd : ARMPseudoExpand<(outs), (ins br_target:$dst, variable_ops),
1674 (Bcc br_target:$dst, (ops 14, zero_reg))>,
1675 Requires<[IsARM, IsDarwin]>;
1677 def TAILJMPr : ARMPseudoExpand<(outs), (ins tcGPR:$dst, variable_ops),
1680 Requires<[IsARM, IsDarwin]>;
1684 // Non-Darwin versions (the difference is R9).
1685 let Defs = [R0, R1, R2, R3, R12, QQQQ0, QQQQ2, QQQQ3, PC],
1687 def TCRETURNdiND : PseudoInst<(outs), (ins i32imm:$dst, variable_ops),
1688 IIC_Br, []>, Requires<[IsNotDarwin]>;
1690 def TCRETURNriND : PseudoInst<(outs), (ins tcGPR:$dst, variable_ops),
1691 IIC_Br, []>, Requires<[IsNotDarwin]>;
1693 def TAILJMPdND : ARMPseudoExpand<(outs), (ins brtarget:$dst, variable_ops),
1695 (Bcc br_target:$dst, (ops 14, zero_reg))>,
1696 Requires<[IsARM, IsNotDarwin]>;
1698 def TAILJMPrND : ARMPseudoExpand<(outs), (ins tcGPR:$dst, variable_ops),
1701 Requires<[IsARM, IsNotDarwin]>;
1709 // Secure Monitor Call is a system instruction -- for disassembly only
1710 def SMC : ABI<0b0001, (outs), (ins imm0_15:$opt), NoItinerary, "smc", "\t$opt",
1713 let Inst{23-4} = 0b01100000000000000111;
1714 let Inst{3-0} = opt;
1717 // Supervisor Call (Software Interrupt)
1718 let isCall = 1, Uses = [SP] in {
1719 def SVC : ABI<0b1111, (outs), (ins imm24b:$svc), IIC_Br, "svc", "\t$svc", []> {
1721 let Inst{23-0} = svc;
1725 // Store Return State is a system instruction -- for disassembly only
1726 let isCodeGenOnly = 1 in { // FIXME: This should not use submode!
1727 def SRSW : ABXI<{1,0,0,?}, (outs), (ins ldstm_mode:$amode, i32imm:$mode),
1728 NoItinerary, "srs${amode}\tsp!, $mode",
1729 [/* For disassembly only; pattern left blank */]> {
1730 let Inst{31-28} = 0b1111;
1731 let Inst{22-20} = 0b110; // W = 1
1732 let Inst{19-8} = 0xd05;
1733 let Inst{7-5} = 0b000;
1736 def SRS : ABXI<{1,0,0,?}, (outs), (ins ldstm_mode:$amode, i32imm:$mode),
1737 NoItinerary, "srs${amode}\tsp, $mode",
1738 [/* For disassembly only; pattern left blank */]> {
1739 let Inst{31-28} = 0b1111;
1740 let Inst{22-20} = 0b100; // W = 0
1741 let Inst{19-8} = 0xd05;
1742 let Inst{7-5} = 0b000;
1745 // Return From Exception is a system instruction -- for disassembly only
1746 def RFEW : ABXI<{1,0,0,?}, (outs), (ins ldstm_mode:$amode, GPR:$base),
1747 NoItinerary, "rfe${amode}\t$base!",
1748 [/* For disassembly only; pattern left blank */]> {
1749 let Inst{31-28} = 0b1111;
1750 let Inst{22-20} = 0b011; // W = 1
1751 let Inst{15-0} = 0x0a00;
1754 def RFE : ABXI<{1,0,0,?}, (outs), (ins ldstm_mode:$amode, GPR:$base),
1755 NoItinerary, "rfe${amode}\t$base",
1756 [/* For disassembly only; pattern left blank */]> {
1757 let Inst{31-28} = 0b1111;
1758 let Inst{22-20} = 0b001; // W = 0
1759 let Inst{15-0} = 0x0a00;
1761 } // isCodeGenOnly = 1
1763 //===----------------------------------------------------------------------===//
1764 // Load / store Instructions.
1770 defm LDR : AI_ldr1<0, "ldr", IIC_iLoad_r, IIC_iLoad_si,
1771 UnOpFrag<(load node:$Src)>>;
1772 defm LDRB : AI_ldr1<1, "ldrb", IIC_iLoad_bh_r, IIC_iLoad_bh_si,
1773 UnOpFrag<(zextloadi8 node:$Src)>>;
1774 defm STR : AI_str1<0, "str", IIC_iStore_r, IIC_iStore_si,
1775 BinOpFrag<(store node:$LHS, node:$RHS)>>;
1776 defm STRB : AI_str1<1, "strb", IIC_iStore_bh_r, IIC_iStore_bh_si,
1777 BinOpFrag<(truncstorei8 node:$LHS, node:$RHS)>>;
1779 // Special LDR for loads from non-pc-relative constpools.
1780 let canFoldAsLoad = 1, mayLoad = 1, neverHasSideEffects = 1,
1781 isReMaterializable = 1 in
1782 def LDRcp : AI2ldst<0b010, 1, 0, (outs GPR:$Rt), (ins addrmode_imm12:$addr),
1783 AddrMode_i12, LdFrm, IIC_iLoad_r, "ldr", "\t$Rt, $addr",
1787 let Inst{23} = addr{12}; // U (add = ('U' == 1))
1788 let Inst{19-16} = 0b1111;
1789 let Inst{15-12} = Rt;
1790 let Inst{11-0} = addr{11-0}; // imm12
1793 // Loads with zero extension
1794 def LDRH : AI3ld<0b1011, 1, (outs GPR:$Rt), (ins addrmode3:$addr), LdMiscFrm,
1795 IIC_iLoad_bh_r, "ldrh", "\t$Rt, $addr",
1796 [(set GPR:$Rt, (zextloadi16 addrmode3:$addr))]>;
1798 // Loads with sign extension
1799 def LDRSH : AI3ld<0b1111, 1, (outs GPR:$Rt), (ins addrmode3:$addr), LdMiscFrm,
1800 IIC_iLoad_bh_r, "ldrsh", "\t$Rt, $addr",
1801 [(set GPR:$Rt, (sextloadi16 addrmode3:$addr))]>;
1803 def LDRSB : AI3ld<0b1101, 1, (outs GPR:$Rt), (ins addrmode3:$addr), LdMiscFrm,
1804 IIC_iLoad_bh_r, "ldrsb", "\t$Rt, $addr",
1805 [(set GPR:$Rt, (sextloadi8 addrmode3:$addr))]>;
1807 let mayLoad = 1, neverHasSideEffects = 1, hasExtraDefRegAllocReq = 1 in {
1809 def LDRD : AI3ld<0b1101, 0, (outs GPR:$Rd, GPR:$dst2),
1810 (ins addrmode3:$addr), LdMiscFrm,
1811 IIC_iLoad_d_r, "ldrd", "\t$Rd, $dst2, $addr",
1812 []>, Requires<[IsARM, HasV5TE]>;
1816 multiclass AI2_ldridx<bit isByte, string opc, InstrItinClass itin> {
1817 def _PRE : AI2ldstidx<1, isByte, 1, (outs GPR:$Rt, GPR:$Rn_wb),
1818 (ins addrmode2:$addr), IndexModePre, LdFrm, itin,
1819 opc, "\t$Rt, $addr!", "$addr.base = $Rn_wb", []> {
1825 let Inst{25} = addr{13};
1826 let Inst{23} = addr{12};
1827 let Inst{19-16} = addr{17-14};
1828 let Inst{11-0} = addr{11-0};
1829 let AsmMatchConverter = "cvtLdWriteBackRegAddrMode2";
1832 def _POST_REG : AI2ldstidx<1, isByte, 0, (outs GPR:$Rt, GPR:$Rn_wb),
1833 (ins GPR:$Rn, am2offset_reg:$offset),
1834 IndexModePost, LdFrm, itin,
1835 opc, "\t$Rt, [$Rn], $offset", "$Rn = $Rn_wb", []> {
1841 let Inst{23} = offset{12};
1842 let Inst{19-16} = Rn;
1843 let Inst{11-0} = offset{11-0};
1844 let DecoderMethod = "DecodeAddrMode2IdxInstruction";
1847 def _POST_IMM : AI2ldstidx<1, isByte, 0, (outs GPR:$Rt, GPR:$Rn_wb),
1848 (ins GPR:$Rn, am2offset_imm:$offset),
1849 IndexModePost, LdFrm, itin,
1850 opc, "\t$Rt, [$Rn], $offset", "$Rn = $Rn_wb", []> {
1856 let Inst{23} = offset{12};
1857 let Inst{19-16} = Rn;
1858 let Inst{11-0} = offset{11-0};
1859 let DecoderMethod = "DecodeAddrMode2IdxInstruction";
1863 let mayLoad = 1, neverHasSideEffects = 1 in {
1864 defm LDR : AI2_ldridx<0, "ldr", IIC_iLoad_ru>;
1865 defm LDRB : AI2_ldridx<1, "ldrb", IIC_iLoad_bh_ru>;
1868 multiclass AI3_ldridx<bits<4> op, bit op20, string opc, InstrItinClass itin> {
1869 def _PRE : AI3ldstidx<op, op20, 1, 1, (outs GPR:$Rt, GPR:$Rn_wb),
1870 (ins addrmode3:$addr), IndexModePre,
1872 opc, "\t$Rt, $addr!", "$addr.base = $Rn_wb", []> {
1874 let Inst{23} = addr{8}; // U bit
1875 let Inst{22} = addr{13}; // 1 == imm8, 0 == Rm
1876 let Inst{19-16} = addr{12-9}; // Rn
1877 let Inst{11-8} = addr{7-4}; // imm7_4/zero
1878 let Inst{3-0} = addr{3-0}; // imm3_0/Rm
1880 def _POST : AI3ldstidx<op, op20, 1, 0, (outs GPR:$Rt, GPR:$Rn_wb),
1881 (ins GPR:$Rn, am3offset:$offset), IndexModePost,
1883 opc, "\t$Rt, [$Rn], $offset", "$Rn = $Rn_wb", []> {
1886 let Inst{23} = offset{8}; // U bit
1887 let Inst{22} = offset{9}; // 1 == imm8, 0 == Rm
1888 let Inst{19-16} = Rn;
1889 let Inst{11-8} = offset{7-4}; // imm7_4/zero
1890 let Inst{3-0} = offset{3-0}; // imm3_0/Rm
1894 let mayLoad = 1, neverHasSideEffects = 1 in {
1895 defm LDRH : AI3_ldridx<0b1011, 1, "ldrh", IIC_iLoad_bh_ru>;
1896 defm LDRSH : AI3_ldridx<0b1111, 1, "ldrsh", IIC_iLoad_bh_ru>;
1897 defm LDRSB : AI3_ldridx<0b1101, 1, "ldrsb", IIC_iLoad_bh_ru>;
1898 let hasExtraDefRegAllocReq = 1 in {
1899 def LDRD_PRE : AI3ldstidx<0b1101, 0, 1, 1, (outs GPR:$Rt, GPR:$Rt2, GPR:$Rn_wb),
1900 (ins addrmode3:$addr), IndexModePre,
1901 LdMiscFrm, IIC_iLoad_d_ru,
1902 "ldrd", "\t$Rt, $Rt2, $addr!",
1903 "$addr.base = $Rn_wb", []> {
1905 let Inst{23} = addr{8}; // U bit
1906 let Inst{22} = addr{13}; // 1 == imm8, 0 == Rm
1907 let Inst{19-16} = addr{12-9}; // Rn
1908 let Inst{11-8} = addr{7-4}; // imm7_4/zero
1909 let Inst{3-0} = addr{3-0}; // imm3_0/Rm
1911 def LDRD_POST: AI3ldstidx<0b1101, 0, 1, 0, (outs GPR:$Rt, GPR:$Rt2, GPR:$Rn_wb),
1912 (ins GPR:$Rn, am3offset:$offset), IndexModePost,
1913 LdMiscFrm, IIC_iLoad_d_ru,
1914 "ldrd", "\t$Rt, $Rt2, [$Rn], $offset",
1915 "$Rn = $Rn_wb", []> {
1918 let Inst{23} = offset{8}; // U bit
1919 let Inst{22} = offset{9}; // 1 == imm8, 0 == Rm
1920 let Inst{19-16} = Rn;
1921 let Inst{11-8} = offset{7-4}; // imm7_4/zero
1922 let Inst{3-0} = offset{3-0}; // imm3_0/Rm
1924 } // hasExtraDefRegAllocReq = 1
1925 } // mayLoad = 1, neverHasSideEffects = 1
1927 // LDRT, LDRBT, LDRSBT, LDRHT, LDRSHT are for disassembly only.
1928 let mayLoad = 1, neverHasSideEffects = 1 in {
1929 def LDRT : AI2ldstidx<1, 0, 0, (outs GPR:$Rt, GPR:$base_wb),
1930 (ins addrmode2:$addr), IndexModePost, LdFrm, IIC_iLoad_ru,
1931 "ldrt", "\t$Rt, $addr", "$addr.base = $base_wb", []> {
1933 // {13} 1 == Rm, 0 == imm12
1937 let Inst{25} = addr{13};
1938 let Inst{23} = addr{12};
1939 let Inst{21} = 1; // overwrite
1940 let Inst{19-16} = addr{17-14};
1941 let Inst{11-0} = addr{11-0};
1942 let AsmMatchConverter = "cvtLdWriteBackRegAddrMode2";
1944 def LDRBT : AI2ldstidx<1, 1, 0, (outs GPR:$Rt, GPR:$base_wb),
1945 (ins addrmode2:$addr), IndexModePost, LdFrm, IIC_iLoad_bh_ru,
1946 "ldrbt", "\t$Rt, $addr", "$addr.base = $base_wb", []> {
1948 // {13} 1 == Rm, 0 == imm12
1952 let Inst{25} = addr{13};
1953 let Inst{23} = addr{12};
1954 let Inst{21} = 1; // overwrite
1955 let Inst{19-16} = addr{17-14};
1956 let Inst{11-0} = addr{11-0};
1957 let AsmMatchConverter = "cvtLdWriteBackRegAddrMode2";
1959 def LDRSBT : AI3ldstidxT<0b1101, 1, 1, 0, (outs GPR:$Rt, GPR:$base_wb),
1960 (ins addrmode3:$addr), IndexModePost, LdMiscFrm, IIC_iLoad_bh_ru,
1961 "ldrsbt", "\t$Rt, $addr", "$addr.base = $base_wb", []> {
1962 let Inst{21} = 1; // overwrite
1964 def LDRHT : AI3ldstidxT<0b1011, 1, 1, 0, (outs GPR:$Rt, GPR:$base_wb),
1965 (ins addrmode3:$addr), IndexModePost, LdMiscFrm, IIC_iLoad_bh_ru,
1966 "ldrht", "\t$Rt, $addr", "$addr.base = $base_wb", []> {
1967 let Inst{21} = 1; // overwrite
1969 def LDRSHT : AI3ldstidxT<0b1111, 1, 1, 0, (outs GPR:$Rt, GPR:$base_wb),
1970 (ins addrmode3:$addr), IndexModePost, LdMiscFrm, IIC_iLoad_bh_ru,
1971 "ldrsht", "\t$Rt, $addr", "$addr.base = $base_wb", []> {
1972 let Inst{21} = 1; // overwrite
1978 // Stores with truncate
1979 def STRH : AI3str<0b1011, (outs), (ins GPR:$Rt, addrmode3:$addr), StMiscFrm,
1980 IIC_iStore_bh_r, "strh", "\t$Rt, $addr",
1981 [(truncstorei16 GPR:$Rt, addrmode3:$addr)]>;
1984 let mayStore = 1, neverHasSideEffects = 1, hasExtraSrcRegAllocReq = 1 in
1985 def STRD : AI3str<0b1111, (outs), (ins GPR:$Rt, GPR:$src2, addrmode3:$addr),
1986 StMiscFrm, IIC_iStore_d_r,
1987 "strd", "\t$Rt, $src2, $addr", []>, Requires<[IsARM, HasV5TE]>;
1990 def STR_PRE_REG : AI2stridx_reg<0, 1, (outs GPR:$Rn_wb),
1991 (ins GPR:$Rt, GPR:$Rn, am2offset_reg:$offset),
1992 IndexModePre, StFrm, IIC_iStore_ru,
1993 "str", "\t$Rt, [$Rn, $offset]!",
1994 "$Rn = $Rn_wb,@earlyclobber $Rn_wb",
1996 (pre_store GPR:$Rt, GPR:$Rn, am2offset_reg:$offset))]>;
1997 def STR_PRE_IMM : AI2stridx_imm<0, 1, (outs GPR:$Rn_wb),
1998 (ins GPR:$Rt, GPR:$Rn, am2offset_imm:$offset),
1999 IndexModePre, StFrm, IIC_iStore_ru,
2000 "str", "\t$Rt, [$Rn, $offset]!",
2001 "$Rn = $Rn_wb,@earlyclobber $Rn_wb",
2003 (pre_store GPR:$Rt, GPR:$Rn, am2offset_imm:$offset))]>;
2007 def STR_POST_REG : AI2stridx_reg<0, 0, (outs GPR:$Rn_wb),
2008 (ins GPR:$Rt, GPR:$Rn, am2offset_reg:$offset),
2009 IndexModePost, StFrm, IIC_iStore_ru,
2010 "str", "\t$Rt, [$Rn], $offset",
2011 "$Rn = $Rn_wb,@earlyclobber $Rn_wb",
2013 (post_store GPR:$Rt, GPR:$Rn, am2offset_reg:$offset))]>;
2014 def STR_POST_IMM : AI2stridx_imm<0, 0, (outs GPR:$Rn_wb),
2015 (ins GPR:$Rt, GPR:$Rn, am2offset_imm:$offset),
2016 IndexModePost, StFrm, IIC_iStore_ru,
2017 "str", "\t$Rt, [$Rn], $offset",
2018 "$Rn = $Rn_wb,@earlyclobber $Rn_wb",
2020 (post_store GPR:$Rt, GPR:$Rn, am2offset_imm:$offset))]>;
2023 def STRB_PRE_REG : AI2stridx_reg<1, 1, (outs GPR:$Rn_wb),
2024 (ins GPR:$Rt, GPR:$Rn, am2offset_reg:$offset),
2025 IndexModePre, StFrm, IIC_iStore_bh_ru,
2026 "strb", "\t$Rt, [$Rn, $offset]!",
2027 "$Rn = $Rn_wb,@earlyclobber $Rn_wb",
2028 [(set GPR:$Rn_wb, (pre_truncsti8 GPR:$Rt,
2029 GPR:$Rn, am2offset_reg:$offset))]>;
2030 def STRB_PRE_IMM : AI2stridx_imm<1, 1, (outs GPR:$Rn_wb),
2031 (ins GPR:$Rt, GPR:$Rn, am2offset_imm:$offset),
2032 IndexModePre, StFrm, IIC_iStore_bh_ru,
2033 "strb", "\t$Rt, [$Rn, $offset]!",
2034 "$Rn = $Rn_wb,@earlyclobber $Rn_wb",
2035 [(set GPR:$Rn_wb, (pre_truncsti8 GPR:$Rt,
2036 GPR:$Rn, am2offset_imm:$offset))]>;
2038 def STRB_POST_REG: AI2stridx_reg<1, 0, (outs GPR:$Rn_wb),
2039 (ins GPR:$Rt, GPR:$Rn, am2offset_reg:$offset),
2040 IndexModePost, StFrm, IIC_iStore_bh_ru,
2041 "strb", "\t$Rt, [$Rn], $offset",
2042 "$Rn = $Rn_wb,@earlyclobber $Rn_wb",
2043 [(set GPR:$Rn_wb, (post_truncsti8 GPR:$Rt,
2044 GPR:$Rn, am2offset_reg:$offset))]>;
2045 def STRB_POST_IMM: AI2stridx_imm<1, 0, (outs GPR:$Rn_wb),
2046 (ins GPR:$Rt, GPR:$Rn, am2offset_imm:$offset),
2047 IndexModePost, StFrm, IIC_iStore_bh_ru,
2048 "strb", "\t$Rt, [$Rn], $offset",
2049 "$Rn = $Rn_wb,@earlyclobber $Rn_wb",
2050 [(set GPR:$Rn_wb, (post_truncsti8 GPR:$Rt,
2051 GPR:$Rn, am2offset_imm:$offset))]>;
2054 def STRH_PRE : AI3stridx<0b1011, 0, 1, (outs GPR:$Rn_wb),
2055 (ins GPR:$Rt, GPR:$Rn, am3offset:$offset),
2056 IndexModePre, StMiscFrm, IIC_iStore_ru,
2057 "strh", "\t$Rt, [$Rn, $offset]!",
2058 "$Rn = $Rn_wb,@earlyclobber $Rn_wb",
2060 (pre_truncsti16 GPR:$Rt, GPR:$Rn, am3offset:$offset))]>;
2062 def STRH_POST: AI3stridx<0b1011, 0, 0, (outs GPR:$Rn_wb),
2063 (ins GPR:$Rt, GPR:$Rn, am3offset:$offset),
2064 IndexModePost, StMiscFrm, IIC_iStore_bh_ru,
2065 "strh", "\t$Rt, [$Rn], $offset",
2066 "$Rn = $Rn_wb,@earlyclobber $Rn_wb",
2067 [(set GPR:$Rn_wb, (post_truncsti16 GPR:$Rt,
2068 GPR:$Rn, am3offset:$offset))]>;
2070 // For disassembly only
2071 let mayStore = 1, neverHasSideEffects = 1, hasExtraSrcRegAllocReq = 1 in {
2072 def STRD_PRE : AI3stdpr<(outs GPR:$base_wb),
2073 (ins GPR:$src1, GPR:$src2, GPR:$base, am3offset:$offset),
2074 StMiscFrm, IIC_iStore_d_ru,
2075 "strd", "\t$src1, $src2, [$base, $offset]!",
2076 "$base = $base_wb", []>;
2078 // For disassembly only
2079 def STRD_POST: AI3stdpo<(outs GPR:$base_wb),
2080 (ins GPR:$src1, GPR:$src2, GPR:$base, am3offset:$offset),
2081 StMiscFrm, IIC_iStore_d_ru,
2082 "strd", "\t$src1, $src2, [$base], $offset",
2083 "$base = $base_wb", []>;
2084 } // mayStore = 1, neverHasSideEffects = 1, hasExtraSrcRegAllocReq = 1
2086 // STRT, STRBT, and STRHT are for disassembly only.
2088 def STRT : AI2stridxT<0, 0, (outs GPR:$Rn_wb), (ins GPR:$Rt, addrmode2:$addr),
2089 IndexModePost, StFrm, IIC_iStore_ru,
2090 "strt", "\t$Rt, $addr", "$addr.base = $Rn_wb",
2091 [/* For disassembly only; pattern left blank */]> {
2092 let Inst{21} = 1; // overwrite
2093 let AsmMatchConverter = "cvtStWriteBackRegAddrMode2";
2096 def STRBT : AI2stridxT<1, 0, (outs GPR:$Rn_wb), (ins GPR:$Rt, addrmode2:$addr),
2097 IndexModePost, StFrm, IIC_iStore_bh_ru,
2098 "strbt", "\t$Rt, $addr", "$addr.base = $Rn_wb",
2099 [/* For disassembly only; pattern left blank */]> {
2100 let Inst{21} = 1; // overwrite
2101 let AsmMatchConverter = "cvtStWriteBackRegAddrMode2";
2104 def STRHT: AI3sthpo<(outs GPR:$base_wb), (ins GPR:$Rt, addrmode3:$addr),
2105 StMiscFrm, IIC_iStore_bh_ru,
2106 "strht", "\t$Rt, $addr", "$addr.base = $base_wb",
2107 [/* For disassembly only; pattern left blank */]> {
2108 let Inst{21} = 1; // overwrite
2109 let AsmMatchConverter = "cvtStWriteBackRegAddrMode3";
2112 //===----------------------------------------------------------------------===//
2113 // Load / store multiple Instructions.
2116 multiclass arm_ldst_mult<string asm, bit L_bit, Format f,
2117 InstrItinClass itin, InstrItinClass itin_upd> {
2118 // IA is the default, so no need for an explicit suffix on the
2119 // mnemonic here. Without it is the cannonical spelling.
2121 AXI4<(outs), (ins GPR:$Rn, pred:$p, reglist:$regs, variable_ops),
2122 IndexModeNone, f, itin,
2123 !strconcat(asm, "${p}\t$Rn, $regs"), "", []> {
2124 let Inst{24-23} = 0b01; // Increment After
2125 let Inst{21} = 0; // No writeback
2126 let Inst{20} = L_bit;
2129 AXI4<(outs GPR:$wb), (ins GPR:$Rn, pred:$p, reglist:$regs, variable_ops),
2130 IndexModeUpd, f, itin_upd,
2131 !strconcat(asm, "${p}\t$Rn!, $regs"), "$Rn = $wb", []> {
2132 let Inst{24-23} = 0b01; // Increment After
2133 let Inst{21} = 1; // Writeback
2134 let Inst{20} = L_bit;
2137 AXI4<(outs), (ins GPR:$Rn, pred:$p, reglist:$regs, variable_ops),
2138 IndexModeNone, f, itin,
2139 !strconcat(asm, "da${p}\t$Rn, $regs"), "", []> {
2140 let Inst{24-23} = 0b00; // Decrement After
2141 let Inst{21} = 0; // No writeback
2142 let Inst{20} = L_bit;
2145 AXI4<(outs GPR:$wb), (ins GPR:$Rn, pred:$p, reglist:$regs, variable_ops),
2146 IndexModeUpd, f, itin_upd,
2147 !strconcat(asm, "da${p}\t$Rn!, $regs"), "$Rn = $wb", []> {
2148 let Inst{24-23} = 0b00; // Decrement After
2149 let Inst{21} = 1; // Writeback
2150 let Inst{20} = L_bit;
2153 AXI4<(outs), (ins GPR:$Rn, pred:$p, reglist:$regs, variable_ops),
2154 IndexModeNone, f, itin,
2155 !strconcat(asm, "db${p}\t$Rn, $regs"), "", []> {
2156 let Inst{24-23} = 0b10; // Decrement Before
2157 let Inst{21} = 0; // No writeback
2158 let Inst{20} = L_bit;
2161 AXI4<(outs GPR:$wb), (ins GPR:$Rn, pred:$p, reglist:$regs, variable_ops),
2162 IndexModeUpd, f, itin_upd,
2163 !strconcat(asm, "db${p}\t$Rn!, $regs"), "$Rn = $wb", []> {
2164 let Inst{24-23} = 0b10; // Decrement Before
2165 let Inst{21} = 1; // Writeback
2166 let Inst{20} = L_bit;
2169 AXI4<(outs), (ins GPR:$Rn, pred:$p, reglist:$regs, variable_ops),
2170 IndexModeNone, f, itin,
2171 !strconcat(asm, "ib${p}\t$Rn, $regs"), "", []> {
2172 let Inst{24-23} = 0b11; // Increment Before
2173 let Inst{21} = 0; // No writeback
2174 let Inst{20} = L_bit;
2177 AXI4<(outs GPR:$wb), (ins GPR:$Rn, pred:$p, reglist:$regs, variable_ops),
2178 IndexModeUpd, f, itin_upd,
2179 !strconcat(asm, "ib${p}\t$Rn!, $regs"), "$Rn = $wb", []> {
2180 let Inst{24-23} = 0b11; // Increment Before
2181 let Inst{21} = 1; // Writeback
2182 let Inst{20} = L_bit;
2186 let neverHasSideEffects = 1 in {
2188 let mayLoad = 1, hasExtraDefRegAllocReq = 1 in
2189 defm LDM : arm_ldst_mult<"ldm", 1, LdStMulFrm, IIC_iLoad_m, IIC_iLoad_mu>;
2191 let mayStore = 1, hasExtraSrcRegAllocReq = 1 in
2192 defm STM : arm_ldst_mult<"stm", 0, LdStMulFrm, IIC_iStore_m, IIC_iStore_mu>;
2194 } // neverHasSideEffects
2196 // FIXME: remove when we have a way to marking a MI with these properties.
2197 // FIXME: Should pc be an implicit operand like PICADD, etc?
2198 let isReturn = 1, isTerminator = 1, isBarrier = 1, mayLoad = 1,
2199 hasExtraDefRegAllocReq = 1, isCodeGenOnly = 1 in
2200 def LDMIA_RET : ARMPseudoExpand<(outs GPR:$wb), (ins GPR:$Rn, pred:$p,
2201 reglist:$regs, variable_ops),
2202 4, IIC_iLoad_mBr, [],
2203 (LDMIA_UPD GPR:$wb, GPR:$Rn, pred:$p, reglist:$regs)>,
2204 RegConstraint<"$Rn = $wb">;
2206 //===----------------------------------------------------------------------===//
2207 // Move Instructions.
2210 let neverHasSideEffects = 1 in
2211 def MOVr : AsI1<0b1101, (outs GPR:$Rd), (ins GPR:$Rm), DPFrm, IIC_iMOVr,
2212 "mov", "\t$Rd, $Rm", []>, UnaryDP {
2216 let Inst{19-16} = 0b0000;
2217 let Inst{11-4} = 0b00000000;
2220 let Inst{15-12} = Rd;
2223 // A version for the smaller set of tail call registers.
2224 let neverHasSideEffects = 1 in
2225 def MOVr_TC : AsI1<0b1101, (outs tcGPR:$Rd), (ins tcGPR:$Rm), DPFrm,
2226 IIC_iMOVr, "mov", "\t$Rd, $Rm", []>, UnaryDP {
2230 let Inst{11-4} = 0b00000000;
2233 let Inst{15-12} = Rd;
2236 def MOVsr : AsI1<0b1101, (outs GPR:$Rd), (ins shift_so_reg_reg:$src),
2237 DPSoRegRegFrm, IIC_iMOVsr,
2238 "mov", "\t$Rd, $src", [(set GPR:$Rd, shift_so_reg_reg:$src)]>,
2242 let Inst{15-12} = Rd;
2243 let Inst{19-16} = 0b0000;
2244 let Inst{11-8} = src{11-8};
2246 let Inst{6-5} = src{6-5};
2248 let Inst{3-0} = src{3-0};
2252 def MOVsi : AsI1<0b1101, (outs GPR:$Rd), (ins shift_so_reg_imm:$src),
2253 DPSoRegImmFrm, IIC_iMOVsr,
2254 "mov", "\t$Rd, $src", [(set GPR:$Rd, shift_so_reg_imm:$src)]>,
2258 let Inst{15-12} = Rd;
2259 let Inst{19-16} = 0b0000;
2260 let Inst{11-5} = src{11-5};
2262 let Inst{3-0} = src{3-0};
2268 let isReMaterializable = 1, isAsCheapAsAMove = 1, isMoveImm = 1 in
2269 def MOVi : AsI1<0b1101, (outs GPR:$Rd), (ins so_imm:$imm), DPFrm, IIC_iMOVi,
2270 "mov", "\t$Rd, $imm", [(set GPR:$Rd, so_imm:$imm)]>, UnaryDP {
2274 let Inst{15-12} = Rd;
2275 let Inst{19-16} = 0b0000;
2276 let Inst{11-0} = imm;
2279 let isReMaterializable = 1, isAsCheapAsAMove = 1, isMoveImm = 1 in
2280 def MOVi16 : AI1<0b1000, (outs GPR:$Rd), (ins imm0_65535_expr:$imm),
2282 "movw", "\t$Rd, $imm",
2283 [(set GPR:$Rd, imm0_65535:$imm)]>,
2284 Requires<[IsARM, HasV6T2]>, UnaryDP {
2287 let Inst{15-12} = Rd;
2288 let Inst{11-0} = imm{11-0};
2289 let Inst{19-16} = imm{15-12};
2294 def : InstAlias<"mov${p} $Rd, $imm",
2295 (MOVi16 GPR:$Rd, imm0_65535_expr:$imm, pred:$p)>,
2298 def MOVi16_ga_pcrel : PseudoInst<(outs GPR:$Rd),
2299 (ins i32imm:$addr, pclabel:$id), IIC_iMOVi, []>;
2301 let Constraints = "$src = $Rd" in {
2302 def MOVTi16 : AI1<0b1010, (outs GPR:$Rd), (ins GPR:$src, imm0_65535_expr:$imm),
2304 "movt", "\t$Rd, $imm",
2306 (or (and GPR:$src, 0xffff),
2307 lo16AllZero:$imm))]>, UnaryDP,
2308 Requires<[IsARM, HasV6T2]> {
2311 let Inst{15-12} = Rd;
2312 let Inst{11-0} = imm{11-0};
2313 let Inst{19-16} = imm{15-12};
2318 def MOVTi16_ga_pcrel : PseudoInst<(outs GPR:$Rd),
2319 (ins GPR:$src, i32imm:$addr, pclabel:$id), IIC_iMOVi, []>;
2323 def : ARMPat<(or GPR:$src, 0xffff0000), (MOVTi16 GPR:$src, 0xffff)>,
2324 Requires<[IsARM, HasV6T2]>;
2326 let Uses = [CPSR] in
2327 def RRX: PseudoInst<(outs GPR:$Rd), (ins GPR:$Rm), IIC_iMOVsi,
2328 [(set GPR:$Rd, (ARMrrx GPR:$Rm))]>, UnaryDP,
2331 // These aren't really mov instructions, but we have to define them this way
2332 // due to flag operands.
2334 let Defs = [CPSR] in {
2335 def MOVsrl_flag : PseudoInst<(outs GPR:$dst), (ins GPR:$src), IIC_iMOVsi,
2336 [(set GPR:$dst, (ARMsrl_flag GPR:$src))]>, UnaryDP,
2338 def MOVsra_flag : PseudoInst<(outs GPR:$dst), (ins GPR:$src), IIC_iMOVsi,
2339 [(set GPR:$dst, (ARMsra_flag GPR:$src))]>, UnaryDP,
2343 //===----------------------------------------------------------------------===//
2344 // Extend Instructions.
2349 def SXTB : AI_ext_rrot<0b01101010,
2350 "sxtb", UnOpFrag<(sext_inreg node:$Src, i8)>>;
2351 def SXTH : AI_ext_rrot<0b01101011,
2352 "sxth", UnOpFrag<(sext_inreg node:$Src, i16)>>;
2354 def SXTAB : AI_exta_rrot<0b01101010,
2355 "sxtab", BinOpFrag<(add node:$LHS, (sext_inreg node:$RHS, i8))>>;
2356 def SXTAH : AI_exta_rrot<0b01101011,
2357 "sxtah", BinOpFrag<(add node:$LHS, (sext_inreg node:$RHS,i16))>>;
2359 def SXTB16 : AI_ext_rrot_np<0b01101000, "sxtb16">;
2361 def SXTAB16 : AI_exta_rrot_np<0b01101000, "sxtab16">;
2365 let AddedComplexity = 16 in {
2366 def UXTB : AI_ext_rrot<0b01101110,
2367 "uxtb" , UnOpFrag<(and node:$Src, 0x000000FF)>>;
2368 def UXTH : AI_ext_rrot<0b01101111,
2369 "uxth" , UnOpFrag<(and node:$Src, 0x0000FFFF)>>;
2370 def UXTB16 : AI_ext_rrot<0b01101100,
2371 "uxtb16", UnOpFrag<(and node:$Src, 0x00FF00FF)>>;
2373 // FIXME: This pattern incorrectly assumes the shl operator is a rotate.
2374 // The transformation should probably be done as a combiner action
2375 // instead so we can include a check for masking back in the upper
2376 // eight bits of the source into the lower eight bits of the result.
2377 //def : ARMV6Pat<(and (shl GPR:$Src, (i32 8)), 0xFF00FF),
2378 // (UXTB16r_rot GPR:$Src, 3)>;
2379 def : ARMV6Pat<(and (srl GPR:$Src, (i32 8)), 0xFF00FF),
2380 (UXTB16 GPR:$Src, 1)>;
2382 def UXTAB : AI_exta_rrot<0b01101110, "uxtab",
2383 BinOpFrag<(add node:$LHS, (and node:$RHS, 0x00FF))>>;
2384 def UXTAH : AI_exta_rrot<0b01101111, "uxtah",
2385 BinOpFrag<(add node:$LHS, (and node:$RHS, 0xFFFF))>>;
2388 // This isn't safe in general, the add is two 16-bit units, not a 32-bit add.
2389 def UXTAB16 : AI_exta_rrot_np<0b01101100, "uxtab16">;
2392 def SBFX : I<(outs GPR:$Rd),
2393 (ins GPR:$Rn, imm0_31:$lsb, imm0_31_m1:$width),
2394 AddrMode1, 4, IndexModeNone, DPFrm, IIC_iUNAsi,
2395 "sbfx", "\t$Rd, $Rn, $lsb, $width", "", []>,
2396 Requires<[IsARM, HasV6T2]> {
2401 let Inst{27-21} = 0b0111101;
2402 let Inst{6-4} = 0b101;
2403 let Inst{20-16} = width;
2404 let Inst{15-12} = Rd;
2405 let Inst{11-7} = lsb;
2409 def UBFX : I<(outs GPR:$Rd),
2410 (ins GPR:$Rn, imm0_31:$lsb, imm0_31_m1:$width),
2411 AddrMode1, 4, IndexModeNone, DPFrm, IIC_iUNAsi,
2412 "ubfx", "\t$Rd, $Rn, $lsb, $width", "", []>,
2413 Requires<[IsARM, HasV6T2]> {
2418 let Inst{27-21} = 0b0111111;
2419 let Inst{6-4} = 0b101;
2420 let Inst{20-16} = width;
2421 let Inst{15-12} = Rd;
2422 let Inst{11-7} = lsb;
2426 //===----------------------------------------------------------------------===//
2427 // Arithmetic Instructions.
2430 defm ADD : AsI1_bin_irs<0b0100, "add",
2431 IIC_iALUi, IIC_iALUr, IIC_iALUsr,
2432 BinOpFrag<(add node:$LHS, node:$RHS)>, "ADD", 1>;
2433 defm SUB : AsI1_bin_irs<0b0010, "sub",
2434 IIC_iALUi, IIC_iALUr, IIC_iALUsr,
2435 BinOpFrag<(sub node:$LHS, node:$RHS)>, "SUB">;
2437 // ADD and SUB with 's' bit set.
2438 defm ADDS : AI1_bin_s_irs<0b0100, "adds",
2439 IIC_iALUi, IIC_iALUr, IIC_iALUsr,
2440 BinOpFrag<(addc node:$LHS, node:$RHS)>, 1>;
2441 defm SUBS : AI1_bin_s_irs<0b0010, "subs",
2442 IIC_iALUi, IIC_iALUr, IIC_iALUsr,
2443 BinOpFrag<(subc node:$LHS, node:$RHS)>>;
2445 defm ADC : AI1_adde_sube_irs<0b0101, "adc",
2446 BinOpFrag<(adde_dead_carry node:$LHS, node:$RHS)>,
2448 defm SBC : AI1_adde_sube_irs<0b0110, "sbc",
2449 BinOpFrag<(sube_dead_carry node:$LHS, node:$RHS)>,
2452 // ADC and SUBC with 's' bit set.
2453 let usesCustomInserter = 1 in {
2454 defm ADCS : AI1_adde_sube_s_irs<
2455 BinOpFrag<(adde_live_carry node:$LHS, node:$RHS)>, 1>;
2456 defm SBCS : AI1_adde_sube_s_irs<
2457 BinOpFrag<(sube_live_carry node:$LHS, node:$RHS) >>;
2460 def RSBri : AsI1<0b0011, (outs GPR:$Rd), (ins GPR:$Rn, so_imm:$imm), DPFrm,
2461 IIC_iALUi, "rsb", "\t$Rd, $Rn, $imm",
2462 [(set GPR:$Rd, (sub so_imm:$imm, GPR:$Rn))]> {
2467 let Inst{15-12} = Rd;
2468 let Inst{19-16} = Rn;
2469 let Inst{11-0} = imm;
2472 // The reg/reg form is only defined for the disassembler; for codegen it is
2473 // equivalent to SUBrr.
2474 def RSBrr : AsI1<0b0011, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm), DPFrm,
2475 IIC_iALUr, "rsb", "\t$Rd, $Rn, $Rm",
2476 [/* For disassembly only; pattern left blank */]> {
2480 let Inst{11-4} = 0b00000000;
2483 let Inst{15-12} = Rd;
2484 let Inst{19-16} = Rn;
2487 def RSBrsi : AsI1<0b0011, (outs GPR:$Rd), (ins GPR:$Rn, so_reg_imm:$shift),
2488 DPSoRegImmFrm, IIC_iALUsr, "rsb", "\t$Rd, $Rn, $shift",
2489 [(set GPR:$Rd, (sub so_reg_imm:$shift, GPR:$Rn))]> {
2494 let Inst{19-16} = Rn;
2495 let Inst{15-12} = Rd;
2496 let Inst{11-5} = shift{11-5};
2498 let Inst{3-0} = shift{3-0};
2501 def RSBrsr : AsI1<0b0011, (outs GPR:$Rd), (ins GPR:$Rn, so_reg_reg:$shift),
2502 DPSoRegRegFrm, IIC_iALUsr, "rsb", "\t$Rd, $Rn, $shift",
2503 [(set GPR:$Rd, (sub so_reg_reg:$shift, GPR:$Rn))]> {
2508 let Inst{19-16} = Rn;
2509 let Inst{15-12} = Rd;
2510 let Inst{11-8} = shift{11-8};
2512 let Inst{6-5} = shift{6-5};
2514 let Inst{3-0} = shift{3-0};
2517 // RSB with 's' bit set.
2518 // NOTE: CPSR def omitted because it will be handled by the custom inserter.
2519 let usesCustomInserter = 1 in {
2520 def RSBSri : ARMPseudoInst<(outs GPR:$Rd), (ins GPR:$Rn, so_imm:$imm),
2522 [(set GPR:$Rd, (subc so_imm:$imm, GPR:$Rn))]>;
2523 def RSBSrr : ARMPseudoInst<(outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm),
2525 [/* For disassembly only; pattern left blank */]>;
2526 def RSBSrsi : ARMPseudoInst<(outs GPR:$Rd), (ins GPR:$Rn, so_reg_imm:$shift),
2528 [(set GPR:$Rd, (subc so_reg_imm:$shift, GPR:$Rn))]>;
2529 def RSBSrsr : ARMPseudoInst<(outs GPR:$Rd), (ins GPR:$Rn, so_reg_reg:$shift),
2531 [(set GPR:$Rd, (subc so_reg_reg:$shift, GPR:$Rn))]>;
2534 let Uses = [CPSR] in {
2535 def RSCri : AsI1<0b0111, (outs GPR:$Rd), (ins GPR:$Rn, so_imm:$imm),
2536 DPFrm, IIC_iALUi, "rsc", "\t$Rd, $Rn, $imm",
2537 [(set GPR:$Rd, (sube_dead_carry so_imm:$imm, GPR:$Rn))]>,
2543 let Inst{15-12} = Rd;
2544 let Inst{19-16} = Rn;
2545 let Inst{11-0} = imm;
2547 // The reg/reg form is only defined for the disassembler; for codegen it is
2548 // equivalent to SUBrr.
2549 def RSCrr : AsI1<0b0111, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm),
2550 DPFrm, IIC_iALUr, "rsc", "\t$Rd, $Rn, $Rm",
2551 [/* For disassembly only; pattern left blank */]> {
2555 let Inst{11-4} = 0b00000000;
2558 let Inst{15-12} = Rd;
2559 let Inst{19-16} = Rn;
2561 def RSCrsi : AsI1<0b0111, (outs GPR:$Rd), (ins GPR:$Rn, so_reg_imm:$shift),
2562 DPSoRegImmFrm, IIC_iALUsr, "rsc", "\t$Rd, $Rn, $shift",
2563 [(set GPR:$Rd, (sube_dead_carry so_reg_imm:$shift, GPR:$Rn))]>,
2569 let Inst{19-16} = Rn;
2570 let Inst{15-12} = Rd;
2571 let Inst{11-5} = shift{11-5};
2573 let Inst{3-0} = shift{3-0};
2575 def RSCrsr : AsI1<0b0111, (outs GPR:$Rd), (ins GPR:$Rn, so_reg_reg:$shift),
2576 DPSoRegRegFrm, IIC_iALUsr, "rsc", "\t$Rd, $Rn, $shift",
2577 [(set GPR:$Rd, (sube_dead_carry so_reg_reg:$shift, GPR:$Rn))]>,
2583 let Inst{19-16} = Rn;
2584 let Inst{15-12} = Rd;
2585 let Inst{11-8} = shift{11-8};
2587 let Inst{6-5} = shift{6-5};
2589 let Inst{3-0} = shift{3-0};
2594 // NOTE: CPSR def omitted because it will be handled by the custom inserter.
2595 let usesCustomInserter = 1, Uses = [CPSR] in {
2596 def RSCSri : ARMPseudoInst<(outs GPR:$Rd), (ins GPR:$Rn, so_imm:$imm),
2598 [(set GPR:$Rd, (sube_dead_carry so_imm:$imm, GPR:$Rn))]>;
2599 def RSCSrsi : ARMPseudoInst<(outs GPR:$Rd), (ins GPR:$Rn, so_reg_imm:$shift),
2601 [(set GPR:$Rd, (sube_dead_carry so_reg_imm:$shift, GPR:$Rn))]>;
2602 def RSCSrsr : ARMPseudoInst<(outs GPR:$Rd), (ins GPR:$Rn, so_reg_reg:$shift),
2604 [(set GPR:$Rd, (sube_dead_carry so_reg_reg:$shift, GPR:$Rn))]>;
2607 // (sub X, imm) gets canonicalized to (add X, -imm). Match this form.
2608 // The assume-no-carry-in form uses the negation of the input since add/sub
2609 // assume opposite meanings of the carry flag (i.e., carry == !borrow).
2610 // See the definition of AddWithCarry() in the ARM ARM A2.2.1 for the gory
2612 def : ARMPat<(add GPR:$src, so_imm_neg:$imm),
2613 (SUBri GPR:$src, so_imm_neg:$imm)>;
2614 def : ARMPat<(addc GPR:$src, so_imm_neg:$imm),
2615 (SUBSri GPR:$src, so_imm_neg:$imm)>;
2616 // The with-carry-in form matches bitwise not instead of the negation.
2617 // Effectively, the inverse interpretation of the carry flag already accounts
2618 // for part of the negation.
2619 def : ARMPat<(adde_dead_carry GPR:$src, so_imm_not:$imm),
2620 (SBCri GPR:$src, so_imm_not:$imm)>;
2621 def : ARMPat<(adde_live_carry GPR:$src, so_imm_not:$imm),
2622 (SBCSri GPR:$src, so_imm_not:$imm)>;
2624 // Note: These are implemented in C++ code, because they have to generate
2625 // ADD/SUBrs instructions, which use a complex pattern that a xform function
2627 // (mul X, 2^n+1) -> (add (X << n), X)
2628 // (mul X, 2^n-1) -> (rsb X, (X << n))
2630 // ARM Arithmetic Instruction
2631 // GPR:$dst = GPR:$a op GPR:$b
2632 class AAI<bits<8> op27_20, bits<8> op11_4, string opc,
2633 list<dag> pattern = [],
2634 dag iops = (ins GPR:$Rn, GPR:$Rm), string asm = "\t$Rd, $Rn, $Rm">
2635 : AI<(outs GPR:$Rd), iops, DPFrm, IIC_iALUr, opc, asm, pattern> {
2639 let Inst{27-20} = op27_20;
2640 let Inst{11-4} = op11_4;
2641 let Inst{19-16} = Rn;
2642 let Inst{15-12} = Rd;
2646 // Saturating add/subtract
2648 def QADD : AAI<0b00010000, 0b00000101, "qadd",
2649 [(set GPR:$Rd, (int_arm_qadd GPR:$Rm, GPR:$Rn))],
2650 (ins GPR:$Rm, GPR:$Rn), "\t$Rd, $Rm, $Rn">;
2651 def QSUB : AAI<0b00010010, 0b00000101, "qsub",
2652 [(set GPR:$Rd, (int_arm_qsub GPR:$Rm, GPR:$Rn))],
2653 (ins GPR:$Rm, GPR:$Rn), "\t$Rd, $Rm, $Rn">;
2654 def QDADD : AAI<0b00010100, 0b00000101, "qdadd", [], (ins GPR:$Rm, GPR:$Rn),
2656 def QDSUB : AAI<0b00010110, 0b00000101, "qdsub", [], (ins GPR:$Rm, GPR:$Rn),
2659 def QADD16 : AAI<0b01100010, 0b11110001, "qadd16">;
2660 def QADD8 : AAI<0b01100010, 0b11111001, "qadd8">;
2661 def QASX : AAI<0b01100010, 0b11110011, "qasx">;
2662 def QSAX : AAI<0b01100010, 0b11110101, "qsax">;
2663 def QSUB16 : AAI<0b01100010, 0b11110111, "qsub16">;
2664 def QSUB8 : AAI<0b01100010, 0b11111111, "qsub8">;
2665 def UQADD16 : AAI<0b01100110, 0b11110001, "uqadd16">;
2666 def UQADD8 : AAI<0b01100110, 0b11111001, "uqadd8">;
2667 def UQASX : AAI<0b01100110, 0b11110011, "uqasx">;
2668 def UQSAX : AAI<0b01100110, 0b11110101, "uqsax">;
2669 def UQSUB16 : AAI<0b01100110, 0b11110111, "uqsub16">;
2670 def UQSUB8 : AAI<0b01100110, 0b11111111, "uqsub8">;
2672 // Signed/Unsigned add/subtract
2674 def SASX : AAI<0b01100001, 0b11110011, "sasx">;
2675 def SADD16 : AAI<0b01100001, 0b11110001, "sadd16">;
2676 def SADD8 : AAI<0b01100001, 0b11111001, "sadd8">;
2677 def SSAX : AAI<0b01100001, 0b11110101, "ssax">;
2678 def SSUB16 : AAI<0b01100001, 0b11110111, "ssub16">;
2679 def SSUB8 : AAI<0b01100001, 0b11111111, "ssub8">;
2680 def UASX : AAI<0b01100101, 0b11110011, "uasx">;
2681 def UADD16 : AAI<0b01100101, 0b11110001, "uadd16">;
2682 def UADD8 : AAI<0b01100101, 0b11111001, "uadd8">;
2683 def USAX : AAI<0b01100101, 0b11110101, "usax">;
2684 def USUB16 : AAI<0b01100101, 0b11110111, "usub16">;
2685 def USUB8 : AAI<0b01100101, 0b11111111, "usub8">;
2687 // Signed/Unsigned halving add/subtract
2689 def SHASX : AAI<0b01100011, 0b11110011, "shasx">;
2690 def SHADD16 : AAI<0b01100011, 0b11110001, "shadd16">;
2691 def SHADD8 : AAI<0b01100011, 0b11111001, "shadd8">;
2692 def SHSAX : AAI<0b01100011, 0b11110101, "shsax">;
2693 def SHSUB16 : AAI<0b01100011, 0b11110111, "shsub16">;
2694 def SHSUB8 : AAI<0b01100011, 0b11111111, "shsub8">;
2695 def UHASX : AAI<0b01100111, 0b11110011, "uhasx">;
2696 def UHADD16 : AAI<0b01100111, 0b11110001, "uhadd16">;
2697 def UHADD8 : AAI<0b01100111, 0b11111001, "uhadd8">;
2698 def UHSAX : AAI<0b01100111, 0b11110101, "uhsax">;
2699 def UHSUB16 : AAI<0b01100111, 0b11110111, "uhsub16">;
2700 def UHSUB8 : AAI<0b01100111, 0b11111111, "uhsub8">;
2702 // Unsigned Sum of Absolute Differences [and Accumulate] -- for disassembly only
2704 def USAD8 : AI<(outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm),
2705 MulFrm /* for convenience */, NoItinerary, "usad8",
2706 "\t$Rd, $Rn, $Rm", []>,
2707 Requires<[IsARM, HasV6]> {
2711 let Inst{27-20} = 0b01111000;
2712 let Inst{15-12} = 0b1111;
2713 let Inst{7-4} = 0b0001;
2714 let Inst{19-16} = Rd;
2715 let Inst{11-8} = Rm;
2718 def USADA8 : AI<(outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm, GPR:$Ra),
2719 MulFrm /* for convenience */, NoItinerary, "usada8",
2720 "\t$Rd, $Rn, $Rm, $Ra", []>,
2721 Requires<[IsARM, HasV6]> {
2726 let Inst{27-20} = 0b01111000;
2727 let Inst{7-4} = 0b0001;
2728 let Inst{19-16} = Rd;
2729 let Inst{15-12} = Ra;
2730 let Inst{11-8} = Rm;
2734 // Signed/Unsigned saturate -- for disassembly only
2736 def SSAT : AI<(outs GPR:$Rd), (ins imm1_32:$sat_imm, GPR:$Rn, shift_imm:$sh),
2737 SatFrm, NoItinerary, "ssat", "\t$Rd, $sat_imm, $Rn$sh", []> {
2742 let Inst{27-21} = 0b0110101;
2743 let Inst{5-4} = 0b01;
2744 let Inst{20-16} = sat_imm;
2745 let Inst{15-12} = Rd;
2746 let Inst{11-7} = sh{4-0};
2747 let Inst{6} = sh{5};
2751 def SSAT16 : AI<(outs GPR:$Rd), (ins imm1_16:$sat_imm, GPR:$Rn), SatFrm,
2752 NoItinerary, "ssat16", "\t$Rd, $sat_imm, $Rn", []> {
2756 let Inst{27-20} = 0b01101010;
2757 let Inst{11-4} = 0b11110011;
2758 let Inst{15-12} = Rd;
2759 let Inst{19-16} = sat_imm;
2763 def USAT : AI<(outs GPR:$Rd), (ins i32imm:$sat_imm, GPR:$Rn, shift_imm:$sh),
2764 SatFrm, NoItinerary, "usat", "\t$Rd, $sat_imm, $Rn$sh", []> {
2769 let Inst{27-21} = 0b0110111;
2770 let Inst{5-4} = 0b01;
2771 let Inst{15-12} = Rd;
2772 let Inst{11-7} = sh{4-0};
2773 let Inst{6} = sh{5};
2774 let Inst{20-16} = sat_imm;
2778 def USAT16 : AI<(outs GPR:$Rd), (ins i32imm:$sat_imm, GPR:$a), SatFrm,
2779 NoItinerary, "usat16", "\t$Rd, $sat_imm, $a",
2780 [/* For disassembly only; pattern left blank */]> {
2784 let Inst{27-20} = 0b01101110;
2785 let Inst{11-4} = 0b11110011;
2786 let Inst{15-12} = Rd;
2787 let Inst{19-16} = sat_imm;
2791 def : ARMV6Pat<(int_arm_ssat GPR:$a, imm:$pos), (SSAT imm:$pos, GPR:$a, 0)>;
2792 def : ARMV6Pat<(int_arm_usat GPR:$a, imm:$pos), (USAT imm:$pos, GPR:$a, 0)>;
2794 //===----------------------------------------------------------------------===//
2795 // Bitwise Instructions.
2798 defm AND : AsI1_bin_irs<0b0000, "and",
2799 IIC_iBITi, IIC_iBITr, IIC_iBITsr,
2800 BinOpFrag<(and node:$LHS, node:$RHS)>, "AND", 1>;
2801 defm ORR : AsI1_bin_irs<0b1100, "orr",
2802 IIC_iBITi, IIC_iBITr, IIC_iBITsr,
2803 BinOpFrag<(or node:$LHS, node:$RHS)>, "ORR", 1>;
2804 defm EOR : AsI1_bin_irs<0b0001, "eor",
2805 IIC_iBITi, IIC_iBITr, IIC_iBITsr,
2806 BinOpFrag<(xor node:$LHS, node:$RHS)>, "EOR", 1>;
2807 defm BIC : AsI1_bin_irs<0b1110, "bic",
2808 IIC_iBITi, IIC_iBITr, IIC_iBITsr,
2809 BinOpFrag<(and node:$LHS, (not node:$RHS))>, "BIC">;
2811 def BFC : I<(outs GPR:$Rd), (ins GPR:$src, bf_inv_mask_imm:$imm),
2812 AddrMode1, 4, IndexModeNone, DPFrm, IIC_iUNAsi,
2813 "bfc", "\t$Rd, $imm", "$src = $Rd",
2814 [(set GPR:$Rd, (and GPR:$src, bf_inv_mask_imm:$imm))]>,
2815 Requires<[IsARM, HasV6T2]> {
2818 let Inst{27-21} = 0b0111110;
2819 let Inst{6-0} = 0b0011111;
2820 let Inst{15-12} = Rd;
2821 let Inst{11-7} = imm{4-0}; // lsb
2822 let Inst{20-16} = imm{9-5}; // width
2825 // A8.6.18 BFI - Bitfield insert (Encoding A1)
2826 def BFI : I<(outs GPR:$Rd), (ins GPR:$src, GPR:$Rn, bf_inv_mask_imm:$imm),
2827 AddrMode1, 4, IndexModeNone, DPFrm, IIC_iUNAsi,
2828 "bfi", "\t$Rd, $Rn, $imm", "$src = $Rd",
2829 [(set GPR:$Rd, (ARMbfi GPR:$src, GPR:$Rn,
2830 bf_inv_mask_imm:$imm))]>,
2831 Requires<[IsARM, HasV6T2]> {
2835 let Inst{27-21} = 0b0111110;
2836 let Inst{6-4} = 0b001; // Rn: Inst{3-0} != 15
2837 let Inst{15-12} = Rd;
2838 let Inst{11-7} = imm{4-0}; // lsb
2839 let Inst{20-16} = imm{9-5}; // width
2843 // GNU as only supports this form of bfi (w/ 4 arguments)
2844 let isAsmParserOnly = 1 in
2845 def BFI4p : I<(outs GPR:$Rd), (ins GPR:$src, GPR:$Rn,
2846 lsb_pos_imm:$lsb, width_imm:$width),
2847 AddrMode1, 4, IndexModeNone, DPFrm, IIC_iUNAsi,
2848 "bfi", "\t$Rd, $Rn, $lsb, $width", "$src = $Rd",
2849 []>, Requires<[IsARM, HasV6T2]> {
2854 let Inst{27-21} = 0b0111110;
2855 let Inst{6-4} = 0b001; // Rn: Inst{3-0} != 15
2856 let Inst{15-12} = Rd;
2857 let Inst{11-7} = lsb;
2858 let Inst{20-16} = width; // Custom encoder => lsb+width-1
2862 def MVNr : AsI1<0b1111, (outs GPR:$Rd), (ins GPR:$Rm), DPFrm, IIC_iMVNr,
2863 "mvn", "\t$Rd, $Rm",
2864 [(set GPR:$Rd, (not GPR:$Rm))]>, UnaryDP {
2868 let Inst{19-16} = 0b0000;
2869 let Inst{11-4} = 0b00000000;
2870 let Inst{15-12} = Rd;
2873 def MVNsi : AsI1<0b1111, (outs GPR:$Rd), (ins so_reg_imm:$shift), DPSoRegImmFrm,
2874 IIC_iMVNsr, "mvn", "\t$Rd, $shift",
2875 [(set GPR:$Rd, (not so_reg_imm:$shift))]>, UnaryDP {
2879 let Inst{19-16} = 0b0000;
2880 let Inst{15-12} = Rd;
2881 let Inst{11-5} = shift{11-5};
2883 let Inst{3-0} = shift{3-0};
2885 def MVNsr : AsI1<0b1111, (outs GPR:$Rd), (ins so_reg_reg:$shift), DPSoRegRegFrm,
2886 IIC_iMVNsr, "mvn", "\t$Rd, $shift",
2887 [(set GPR:$Rd, (not so_reg_reg:$shift))]>, UnaryDP {
2891 let Inst{19-16} = 0b0000;
2892 let Inst{15-12} = Rd;
2893 let Inst{11-8} = shift{11-8};
2895 let Inst{6-5} = shift{6-5};
2897 let Inst{3-0} = shift{3-0};
2899 let isReMaterializable = 1, isAsCheapAsAMove = 1, isMoveImm = 1 in
2900 def MVNi : AsI1<0b1111, (outs GPR:$Rd), (ins so_imm:$imm), DPFrm,
2901 IIC_iMVNi, "mvn", "\t$Rd, $imm",
2902 [(set GPR:$Rd, so_imm_not:$imm)]>,UnaryDP {
2906 let Inst{19-16} = 0b0000;
2907 let Inst{15-12} = Rd;
2908 let Inst{11-0} = imm;
2911 def : ARMPat<(and GPR:$src, so_imm_not:$imm),
2912 (BICri GPR:$src, so_imm_not:$imm)>;
2914 //===----------------------------------------------------------------------===//
2915 // Multiply Instructions.
2917 class AsMul1I32<bits<7> opcod, dag oops, dag iops, InstrItinClass itin,
2918 string opc, string asm, list<dag> pattern>
2919 : AsMul1I<opcod, oops, iops, itin, opc, asm, pattern> {
2923 let Inst{19-16} = Rd;
2924 let Inst{11-8} = Rm;
2927 class AsMul1I64<bits<7> opcod, dag oops, dag iops, InstrItinClass itin,
2928 string opc, string asm, list<dag> pattern>
2929 : AsMul1I<opcod, oops, iops, itin, opc, asm, pattern> {
2934 let Inst{19-16} = RdHi;
2935 let Inst{15-12} = RdLo;
2936 let Inst{11-8} = Rm;
2940 // FIXME: The v5 pseudos are only necessary for the additional Constraint
2941 // property. Remove them when it's possible to add those properties
2942 // on an individual MachineInstr, not just an instuction description.
2943 let isCommutable = 1 in {
2944 def MUL : AsMul1I32<0b0000000, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm),
2945 IIC_iMUL32, "mul", "\t$Rd, $Rn, $Rm",
2946 [(set GPR:$Rd, (mul GPR:$Rn, GPR:$Rm))]>,
2947 Requires<[IsARM, HasV6]> {
2948 let Inst{15-12} = 0b0000;
2951 let Constraints = "@earlyclobber $Rd" in
2952 def MULv5: ARMPseudoExpand<(outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm,
2953 pred:$p, cc_out:$s),
2955 [(set GPR:$Rd, (mul GPR:$Rn, GPR:$Rm))],
2956 (MUL GPR:$Rd, GPR:$Rn, GPR:$Rm, pred:$p, cc_out:$s)>,
2957 Requires<[IsARM, NoV6]>;
2960 def MLA : AsMul1I32<0b0000001, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm, GPR:$Ra),
2961 IIC_iMAC32, "mla", "\t$Rd, $Rn, $Rm, $Ra",
2962 [(set GPR:$Rd, (add (mul GPR:$Rn, GPR:$Rm), GPR:$Ra))]>,
2963 Requires<[IsARM, HasV6]> {
2965 let Inst{15-12} = Ra;
2968 let Constraints = "@earlyclobber $Rd" in
2969 def MLAv5: ARMPseudoExpand<(outs GPR:$Rd),
2970 (ins GPR:$Rn, GPR:$Rm, GPR:$Ra, pred:$p, cc_out:$s),
2972 [(set GPR:$Rd, (add (mul GPR:$Rn, GPR:$Rm), GPR:$Ra))],
2973 (MLA GPR:$Rd, GPR:$Rn, GPR:$Rm, GPR:$Ra, pred:$p, cc_out:$s)>,
2974 Requires<[IsARM, NoV6]>;
2976 def MLS : AMul1I<0b0000011, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm, GPR:$Ra),
2977 IIC_iMAC32, "mls", "\t$Rd, $Rn, $Rm, $Ra",
2978 [(set GPR:$Rd, (sub GPR:$Ra, (mul GPR:$Rn, GPR:$Rm)))]>,
2979 Requires<[IsARM, HasV6T2]> {
2984 let Inst{19-16} = Rd;
2985 let Inst{15-12} = Ra;
2986 let Inst{11-8} = Rm;
2990 // Extra precision multiplies with low / high results
2991 let neverHasSideEffects = 1 in {
2992 let isCommutable = 1 in {
2993 def SMULL : AsMul1I64<0b0000110, (outs GPR:$RdLo, GPR:$RdHi),
2994 (ins GPR:$Rn, GPR:$Rm), IIC_iMUL64,
2995 "smull", "\t$RdLo, $RdHi, $Rn, $Rm", []>,
2996 Requires<[IsARM, HasV6]>;
2998 def UMULL : AsMul1I64<0b0000100, (outs GPR:$RdLo, GPR:$RdHi),
2999 (ins GPR:$Rn, GPR:$Rm), IIC_iMUL64,
3000 "umull", "\t$RdLo, $RdHi, $Rn, $Rm", []>,
3001 Requires<[IsARM, HasV6]>;
3003 let Constraints = "@earlyclobber $RdLo,@earlyclobber $RdHi" in {
3004 def SMULLv5 : ARMPseudoExpand<(outs GPR:$RdLo, GPR:$RdHi),
3005 (ins GPR:$Rn, GPR:$Rm, pred:$p, cc_out:$s),
3007 (SMULL GPR:$RdLo, GPR:$RdHi, GPR:$Rn, GPR:$Rm, pred:$p, cc_out:$s)>,
3008 Requires<[IsARM, NoV6]>;
3010 def UMULLv5 : ARMPseudoExpand<(outs GPR:$RdLo, GPR:$RdHi),
3011 (ins GPR:$Rn, GPR:$Rm, pred:$p, cc_out:$s),
3013 (UMULL GPR:$RdLo, GPR:$RdHi, GPR:$Rn, GPR:$Rm, pred:$p, cc_out:$s)>,
3014 Requires<[IsARM, NoV6]>;
3018 // Multiply + accumulate
3019 def SMLAL : AsMul1I64<0b0000111, (outs GPR:$RdLo, GPR:$RdHi),
3020 (ins GPR:$Rn, GPR:$Rm), IIC_iMAC64,
3021 "smlal", "\t$RdLo, $RdHi, $Rn, $Rm", []>,
3022 Requires<[IsARM, HasV6]>;
3023 def UMLAL : AsMul1I64<0b0000101, (outs GPR:$RdLo, GPR:$RdHi),
3024 (ins GPR:$Rn, GPR:$Rm), IIC_iMAC64,
3025 "umlal", "\t$RdLo, $RdHi, $Rn, $Rm", []>,
3026 Requires<[IsARM, HasV6]>;
3028 def UMAAL : AMul1I <0b0000010, (outs GPR:$RdLo, GPR:$RdHi),
3029 (ins GPR:$Rn, GPR:$Rm), IIC_iMAC64,
3030 "umaal", "\t$RdLo, $RdHi, $Rn, $Rm", []>,
3031 Requires<[IsARM, HasV6]> {
3036 let Inst{19-16} = RdLo;
3037 let Inst{15-12} = RdHi;
3038 let Inst{11-8} = Rm;
3042 let Constraints = "@earlyclobber $RdLo,@earlyclobber $RdHi" in {
3043 def SMLALv5 : ARMPseudoExpand<(outs GPR:$RdLo, GPR:$RdHi),
3044 (ins GPR:$Rn, GPR:$Rm, pred:$p, cc_out:$s),
3046 (SMLAL GPR:$RdLo, GPR:$RdHi, GPR:$Rn, GPR:$Rm, pred:$p, cc_out:$s)>,
3047 Requires<[IsARM, NoV6]>;
3048 def UMLALv5 : ARMPseudoExpand<(outs GPR:$RdLo, GPR:$RdHi),
3049 (ins GPR:$Rn, GPR:$Rm, pred:$p, cc_out:$s),
3051 (UMLAL GPR:$RdLo, GPR:$RdHi, GPR:$Rn, GPR:$Rm, pred:$p, cc_out:$s)>,
3052 Requires<[IsARM, NoV6]>;
3053 def UMAALv5 : ARMPseudoExpand<(outs GPR:$RdLo, GPR:$RdHi),
3054 (ins GPR:$Rn, GPR:$Rm, pred:$p),
3056 (UMAAL GPR:$RdLo, GPR:$RdHi, GPR:$Rn, GPR:$Rm, pred:$p)>,
3057 Requires<[IsARM, NoV6]>;
3060 } // neverHasSideEffects
3062 // Most significant word multiply
3063 def SMMUL : AMul2I <0b0111010, 0b0001, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm),
3064 IIC_iMUL32, "smmul", "\t$Rd, $Rn, $Rm",
3065 [(set GPR:$Rd, (mulhs GPR:$Rn, GPR:$Rm))]>,
3066 Requires<[IsARM, HasV6]> {
3067 let Inst{15-12} = 0b1111;
3070 def SMMULR : AMul2I <0b0111010, 0b0011, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm),
3071 IIC_iMUL32, "smmulr", "\t$Rd, $Rn, $Rm",
3072 [/* For disassembly only; pattern left blank */]>,
3073 Requires<[IsARM, HasV6]> {
3074 let Inst{15-12} = 0b1111;
3077 def SMMLA : AMul2Ia <0b0111010, 0b0001, (outs GPR:$Rd),
3078 (ins GPR:$Rn, GPR:$Rm, GPR:$Ra),
3079 IIC_iMAC32, "smmla", "\t$Rd, $Rn, $Rm, $Ra",
3080 [(set GPR:$Rd, (add (mulhs GPR:$Rn, GPR:$Rm), GPR:$Ra))]>,
3081 Requires<[IsARM, HasV6]>;
3083 def SMMLAR : AMul2Ia <0b0111010, 0b0011, (outs GPR:$Rd),
3084 (ins GPR:$Rn, GPR:$Rm, GPR:$Ra),
3085 IIC_iMAC32, "smmlar", "\t$Rd, $Rn, $Rm, $Ra",
3086 [/* For disassembly only; pattern left blank */]>,
3087 Requires<[IsARM, HasV6]>;
3089 def SMMLS : AMul2Ia <0b0111010, 0b1101, (outs GPR:$Rd),
3090 (ins GPR:$Rn, GPR:$Rm, GPR:$Ra),
3091 IIC_iMAC32, "smmls", "\t$Rd, $Rn, $Rm, $Ra",
3092 [(set GPR:$Rd, (sub GPR:$Ra, (mulhs GPR:$Rn, GPR:$Rm)))]>,
3093 Requires<[IsARM, HasV6]>;
3095 def SMMLSR : AMul2Ia <0b0111010, 0b1111, (outs GPR:$Rd),
3096 (ins GPR:$Rn, GPR:$Rm, GPR:$Ra),
3097 IIC_iMAC32, "smmlsr", "\t$Rd, $Rn, $Rm, $Ra",
3098 [/* For disassembly only; pattern left blank */]>,
3099 Requires<[IsARM, HasV6]>;
3101 multiclass AI_smul<string opc, PatFrag opnode> {
3102 def BB : AMulxyI<0b0001011, 0b00, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm),
3103 IIC_iMUL16, !strconcat(opc, "bb"), "\t$Rd, $Rn, $Rm",
3104 [(set GPR:$Rd, (opnode (sext_inreg GPR:$Rn, i16),
3105 (sext_inreg GPR:$Rm, i16)))]>,
3106 Requires<[IsARM, HasV5TE]>;
3108 def BT : AMulxyI<0b0001011, 0b10, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm),
3109 IIC_iMUL16, !strconcat(opc, "bt"), "\t$Rd, $Rn, $Rm",
3110 [(set GPR:$Rd, (opnode (sext_inreg GPR:$Rn, i16),
3111 (sra GPR:$Rm, (i32 16))))]>,
3112 Requires<[IsARM, HasV5TE]>;
3114 def TB : AMulxyI<0b0001011, 0b01, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm),
3115 IIC_iMUL16, !strconcat(opc, "tb"), "\t$Rd, $Rn, $Rm",
3116 [(set GPR:$Rd, (opnode (sra GPR:$Rn, (i32 16)),
3117 (sext_inreg GPR:$Rm, i16)))]>,
3118 Requires<[IsARM, HasV5TE]>;
3120 def TT : AMulxyI<0b0001011, 0b11, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm),
3121 IIC_iMUL16, !strconcat(opc, "tt"), "\t$Rd, $Rn, $Rm",
3122 [(set GPR:$Rd, (opnode (sra GPR:$Rn, (i32 16)),
3123 (sra GPR:$Rm, (i32 16))))]>,
3124 Requires<[IsARM, HasV5TE]>;
3126 def WB : AMulxyI<0b0001001, 0b01, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm),
3127 IIC_iMUL16, !strconcat(opc, "wb"), "\t$Rd, $Rn, $Rm",
3128 [(set GPR:$Rd, (sra (opnode GPR:$Rn,
3129 (sext_inreg GPR:$Rm, i16)), (i32 16)))]>,
3130 Requires<[IsARM, HasV5TE]>;
3132 def WT : AMulxyI<0b0001001, 0b11, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm),
3133 IIC_iMUL16, !strconcat(opc, "wt"), "\t$Rd, $Rn, $Rm",
3134 [(set GPR:$Rd, (sra (opnode GPR:$Rn,
3135 (sra GPR:$Rm, (i32 16))), (i32 16)))]>,
3136 Requires<[IsARM, HasV5TE]>;
3140 multiclass AI_smla<string opc, PatFrag opnode> {
3141 def BB : AMulxyIa<0b0001000, 0b00, (outs GPR:$Rd),
3142 (ins GPR:$Rn, GPR:$Rm, GPR:$Ra),
3143 IIC_iMAC16, !strconcat(opc, "bb"), "\t$Rd, $Rn, $Rm, $Ra",
3144 [(set GPR:$Rd, (add GPR:$Ra,
3145 (opnode (sext_inreg GPR:$Rn, i16),
3146 (sext_inreg GPR:$Rm, i16))))]>,
3147 Requires<[IsARM, HasV5TE]>;
3149 def BT : AMulxyIa<0b0001000, 0b10, (outs GPR:$Rd),
3150 (ins GPR:$Rn, GPR:$Rm, GPR:$Ra),
3151 IIC_iMAC16, !strconcat(opc, "bt"), "\t$Rd, $Rn, $Rm, $Ra",
3152 [(set GPR:$Rd, (add GPR:$Ra, (opnode (sext_inreg GPR:$Rn, i16),
3153 (sra GPR:$Rm, (i32 16)))))]>,
3154 Requires<[IsARM, HasV5TE]>;
3156 def TB : AMulxyIa<0b0001000, 0b01, (outs GPR:$Rd),
3157 (ins GPR:$Rn, GPR:$Rm, GPR:$Ra),
3158 IIC_iMAC16, !strconcat(opc, "tb"), "\t$Rd, $Rn, $Rm, $Ra",
3159 [(set GPR:$Rd, (add GPR:$Ra, (opnode (sra GPR:$Rn, (i32 16)),
3160 (sext_inreg GPR:$Rm, i16))))]>,
3161 Requires<[IsARM, HasV5TE]>;
3163 def TT : AMulxyIa<0b0001000, 0b11, (outs GPR:$Rd),
3164 (ins GPR:$Rn, GPR:$Rm, GPR:$Ra),
3165 IIC_iMAC16, !strconcat(opc, "tt"), "\t$Rd, $Rn, $Rm, $Ra",
3166 [(set GPR:$Rd, (add GPR:$Ra, (opnode (sra GPR:$Rn, (i32 16)),
3167 (sra GPR:$Rm, (i32 16)))))]>,
3168 Requires<[IsARM, HasV5TE]>;
3170 def WB : AMulxyIa<0b0001001, 0b00, (outs GPR:$Rd),
3171 (ins GPR:$Rn, GPR:$Rm, GPR:$Ra),
3172 IIC_iMAC16, !strconcat(opc, "wb"), "\t$Rd, $Rn, $Rm, $Ra",
3173 [(set GPR:$Rd, (add GPR:$Ra, (sra (opnode GPR:$Rn,
3174 (sext_inreg GPR:$Rm, i16)), (i32 16))))]>,
3175 Requires<[IsARM, HasV5TE]>;
3177 def WT : AMulxyIa<0b0001001, 0b10, (outs GPR:$Rd),
3178 (ins GPR:$Rn, GPR:$Rm, GPR:$Ra),
3179 IIC_iMAC16, !strconcat(opc, "wt"), "\t$Rd, $Rn, $Rm, $Ra",
3180 [(set GPR:$Rd, (add GPR:$Ra, (sra (opnode GPR:$Rn,
3181 (sra GPR:$Rm, (i32 16))), (i32 16))))]>,
3182 Requires<[IsARM, HasV5TE]>;
3185 defm SMUL : AI_smul<"smul", BinOpFrag<(mul node:$LHS, node:$RHS)>>;
3186 defm SMLA : AI_smla<"smla", BinOpFrag<(mul node:$LHS, node:$RHS)>>;
3188 // Halfword multiply accumulate long: SMLAL<x><y> -- for disassembly only
3189 def SMLALBB : AMulxyI64<0b0001010, 0b00, (outs GPR:$RdLo, GPR:$RdHi),
3190 (ins GPR:$Rn, GPR:$Rm),
3191 IIC_iMAC64, "smlalbb", "\t$RdLo, $RdHi, $Rn, $Rm",
3192 [/* For disassembly only; pattern left blank */]>,
3193 Requires<[IsARM, HasV5TE]>;
3195 def SMLALBT : AMulxyI64<0b0001010, 0b10, (outs GPR:$RdLo, GPR:$RdHi),
3196 (ins GPR:$Rn, GPR:$Rm),
3197 IIC_iMAC64, "smlalbt", "\t$RdLo, $RdHi, $Rn, $Rm",
3198 [/* For disassembly only; pattern left blank */]>,
3199 Requires<[IsARM, HasV5TE]>;
3201 def SMLALTB : AMulxyI64<0b0001010, 0b01, (outs GPR:$RdLo, GPR:$RdHi),
3202 (ins GPR:$Rn, GPR:$Rm),
3203 IIC_iMAC64, "smlaltb", "\t$RdLo, $RdHi, $Rn, $Rm",
3204 [/* For disassembly only; pattern left blank */]>,
3205 Requires<[IsARM, HasV5TE]>;
3207 def SMLALTT : AMulxyI64<0b0001010, 0b11, (outs GPR:$RdLo, GPR:$RdHi),
3208 (ins GPR:$Rn, GPR:$Rm),
3209 IIC_iMAC64, "smlaltt", "\t$RdLo, $RdHi, $Rn, $Rm",
3210 [/* For disassembly only; pattern left blank */]>,
3211 Requires<[IsARM, HasV5TE]>;
3213 // Helper class for AI_smld -- for disassembly only
3214 class AMulDualIbase<bit long, bit sub, bit swap, dag oops, dag iops,
3215 InstrItinClass itin, string opc, string asm>
3216 : AI<oops, iops, MulFrm, itin, opc, asm, []>, Requires<[IsARM, HasV6]> {
3219 let Inst{27-23} = 0b01110;
3220 let Inst{22} = long;
3221 let Inst{21-20} = 0b00;
3222 let Inst{11-8} = Rm;
3229 class AMulDualI<bit long, bit sub, bit swap, dag oops, dag iops,
3230 InstrItinClass itin, string opc, string asm>
3231 : AMulDualIbase<long, sub, swap, oops, iops, itin, opc, asm> {
3233 let Inst{15-12} = 0b1111;
3234 let Inst{19-16} = Rd;
3236 class AMulDualIa<bit long, bit sub, bit swap, dag oops, dag iops,
3237 InstrItinClass itin, string opc, string asm>
3238 : AMulDualIbase<long, sub, swap, oops, iops, itin, opc, asm> {
3241 let Inst{19-16} = Rd;
3242 let Inst{15-12} = Ra;
3244 class AMulDualI64<bit long, bit sub, bit swap, dag oops, dag iops,
3245 InstrItinClass itin, string opc, string asm>
3246 : AMulDualIbase<long, sub, swap, oops, iops, itin, opc, asm> {
3249 let Inst{19-16} = RdHi;
3250 let Inst{15-12} = RdLo;
3253 multiclass AI_smld<bit sub, string opc> {
3255 def D : AMulDualIa<0, sub, 0, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm, GPR:$Ra),
3256 NoItinerary, !strconcat(opc, "d"), "\t$Rd, $Rn, $Rm, $Ra">;
3258 def DX: AMulDualIa<0, sub, 1, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm, GPR:$Ra),
3259 NoItinerary, !strconcat(opc, "dx"), "\t$Rd, $Rn, $Rm, $Ra">;
3261 def LD: AMulDualI64<1, sub, 0, (outs GPR:$RdLo,GPR:$RdHi),
3262 (ins GPR:$Rn, GPR:$Rm), NoItinerary,
3263 !strconcat(opc, "ld"), "\t$RdLo, $RdHi, $Rn, $Rm">;
3265 def LDX : AMulDualI64<1, sub, 1, (outs GPR:$RdLo,GPR:$RdHi),
3266 (ins GPR:$Rn, GPR:$Rm), NoItinerary,
3267 !strconcat(opc, "ldx"),"\t$RdLo, $RdHi, $Rn, $Rm">;
3271 defm SMLA : AI_smld<0, "smla">;
3272 defm SMLS : AI_smld<1, "smls">;
3274 multiclass AI_sdml<bit sub, string opc> {
3276 def D : AMulDualI<0, sub, 0, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm),
3277 NoItinerary, !strconcat(opc, "d"), "\t$Rd, $Rn, $Rm">;
3278 def DX : AMulDualI<0, sub, 1, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm),
3279 NoItinerary, !strconcat(opc, "dx"), "\t$Rd, $Rn, $Rm">;
3282 defm SMUA : AI_sdml<0, "smua">;
3283 defm SMUS : AI_sdml<1, "smus">;
3285 //===----------------------------------------------------------------------===//
3286 // Misc. Arithmetic Instructions.
3289 def CLZ : AMiscA1I<0b000010110, 0b0001, (outs GPR:$Rd), (ins GPR:$Rm),
3290 IIC_iUNAr, "clz", "\t$Rd, $Rm",
3291 [(set GPR:$Rd, (ctlz GPR:$Rm))]>, Requires<[IsARM, HasV5T]>;
3293 def RBIT : AMiscA1I<0b01101111, 0b0011, (outs GPR:$Rd), (ins GPR:$Rm),
3294 IIC_iUNAr, "rbit", "\t$Rd, $Rm",
3295 [(set GPR:$Rd, (ARMrbit GPR:$Rm))]>,
3296 Requires<[IsARM, HasV6T2]>;
3298 def REV : AMiscA1I<0b01101011, 0b0011, (outs GPR:$Rd), (ins GPR:$Rm),
3299 IIC_iUNAr, "rev", "\t$Rd, $Rm",
3300 [(set GPR:$Rd, (bswap GPR:$Rm))]>, Requires<[IsARM, HasV6]>;
3302 let AddedComplexity = 5 in
3303 def REV16 : AMiscA1I<0b01101011, 0b1011, (outs GPR:$Rd), (ins GPR:$Rm),
3304 IIC_iUNAr, "rev16", "\t$Rd, $Rm",
3305 [(set GPR:$Rd, (rotr (bswap GPR:$Rm), (i32 16)))]>,
3306 Requires<[IsARM, HasV6]>;
3308 let AddedComplexity = 5 in
3309 def REVSH : AMiscA1I<0b01101111, 0b1011, (outs GPR:$Rd), (ins GPR:$Rm),
3310 IIC_iUNAr, "revsh", "\t$Rd, $Rm",
3311 [(set GPR:$Rd, (sra (bswap GPR:$Rm), (i32 16)))]>,
3312 Requires<[IsARM, HasV6]>;
3314 def : ARMV6Pat<(or (sra (shl GPR:$Rm, (i32 24)), (i32 16)),
3315 (and (srl GPR:$Rm, (i32 8)), 0xFF)),
3318 def PKHBT : APKHI<0b01101000, 0, (outs GPR:$Rd),
3319 (ins GPR:$Rn, GPR:$Rm, pkh_lsl_amt:$sh),
3320 IIC_iALUsi, "pkhbt", "\t$Rd, $Rn, $Rm$sh",
3321 [(set GPR:$Rd, (or (and GPR:$Rn, 0xFFFF),
3322 (and (shl GPR:$Rm, pkh_lsl_amt:$sh),
3324 Requires<[IsARM, HasV6]>;
3326 // Alternate cases for PKHBT where identities eliminate some nodes.
3327 def : ARMV6Pat<(or (and GPR:$Rn, 0xFFFF), (and GPR:$Rm, 0xFFFF0000)),
3328 (PKHBT GPR:$Rn, GPR:$Rm, 0)>;
3329 def : ARMV6Pat<(or (and GPR:$Rn, 0xFFFF), (shl GPR:$Rm, imm16_31:$sh)),
3330 (PKHBT GPR:$Rn, GPR:$Rm, imm16_31:$sh)>;
3332 // Note: Shifts of 1-15 bits will be transformed to srl instead of sra and
3333 // will match the pattern below.
3334 def PKHTB : APKHI<0b01101000, 1, (outs GPR:$Rd),
3335 (ins GPR:$Rn, GPR:$Rm, pkh_asr_amt:$sh),
3336 IIC_iBITsi, "pkhtb", "\t$Rd, $Rn, $Rm$sh",
3337 [(set GPR:$Rd, (or (and GPR:$Rn, 0xFFFF0000),
3338 (and (sra GPR:$Rm, pkh_asr_amt:$sh),
3340 Requires<[IsARM, HasV6]>;
3342 // Alternate cases for PKHTB where identities eliminate some nodes. Note that
3343 // a shift amount of 0 is *not legal* here, it is PKHBT instead.
3344 def : ARMV6Pat<(or (and GPR:$src1, 0xFFFF0000), (srl GPR:$src2, imm16_31:$sh)),
3345 (PKHTB GPR:$src1, GPR:$src2, imm16_31:$sh)>;
3346 def : ARMV6Pat<(or (and GPR:$src1, 0xFFFF0000),
3347 (and (srl GPR:$src2, imm1_15:$sh), 0xFFFF)),
3348 (PKHTB GPR:$src1, GPR:$src2, imm1_15:$sh)>;
3350 //===----------------------------------------------------------------------===//
3351 // Comparison Instructions...
3354 defm CMP : AI1_cmp_irs<0b1010, "cmp",
3355 IIC_iCMPi, IIC_iCMPr, IIC_iCMPsr,
3356 BinOpFrag<(ARMcmp node:$LHS, node:$RHS)>>;
3358 // ARMcmpZ can re-use the above instruction definitions.
3359 def : ARMPat<(ARMcmpZ GPR:$src, so_imm:$imm),
3360 (CMPri GPR:$src, so_imm:$imm)>;
3361 def : ARMPat<(ARMcmpZ GPR:$src, GPR:$rhs),
3362 (CMPrr GPR:$src, GPR:$rhs)>;
3363 def : ARMPat<(ARMcmpZ GPR:$src, so_reg_imm:$rhs),
3364 (CMPrsi GPR:$src, so_reg_imm:$rhs)>;
3365 def : ARMPat<(ARMcmpZ GPR:$src, so_reg_reg:$rhs),
3366 (CMPrsr GPR:$src, so_reg_reg:$rhs)>;
3368 // FIXME: We have to be careful when using the CMN instruction and comparison
3369 // with 0. One would expect these two pieces of code should give identical
3385 // However, the CMN gives the *opposite* result when r1 is 0. This is because
3386 // the carry flag is set in the CMP case but not in the CMN case. In short, the
3387 // CMP instruction doesn't perform a truncate of the (logical) NOT of 0 plus the
3388 // value of r0 and the carry bit (because the "carry bit" parameter to
3389 // AddWithCarry is defined as 1 in this case, the carry flag will always be set
3390 // when r0 >= 0). The CMN instruction doesn't perform a NOT of 0 so there is
3391 // never a "carry" when this AddWithCarry is performed (because the "carry bit"
3392 // parameter to AddWithCarry is defined as 0).
3394 // When x is 0 and unsigned:
3398 // ~x + 1 = 0x1 0000 0000
3399 // (-x = 0) != (0x1 0000 0000 = ~x + 1)
3401 // Therefore, we should disable CMN when comparing against zero, until we can
3402 // limit when the CMN instruction is used (when we know that the RHS is not 0 or
3403 // when it's a comparison which doesn't look at the 'carry' flag).
3405 // (See the ARM docs for the "AddWithCarry" pseudo-code.)
3407 // This is related to <rdar://problem/7569620>.
3409 //defm CMN : AI1_cmp_irs<0b1011, "cmn",
3410 // BinOpFrag<(ARMcmp node:$LHS,(ineg node:$RHS))>>;
3412 // Note that TST/TEQ don't set all the same flags that CMP does!
3413 defm TST : AI1_cmp_irs<0b1000, "tst",
3414 IIC_iTSTi, IIC_iTSTr, IIC_iTSTsr,
3415 BinOpFrag<(ARMcmpZ (and_su node:$LHS, node:$RHS), 0)>, 1>;
3416 defm TEQ : AI1_cmp_irs<0b1001, "teq",
3417 IIC_iTSTi, IIC_iTSTr, IIC_iTSTsr,
3418 BinOpFrag<(ARMcmpZ (xor_su node:$LHS, node:$RHS), 0)>, 1>;
3420 defm CMNz : AI1_cmp_irs<0b1011, "cmn",
3421 IIC_iCMPi, IIC_iCMPr, IIC_iCMPsr,
3422 BinOpFrag<(ARMcmpZ node:$LHS,(ineg node:$RHS))>>;
3424 //def : ARMPat<(ARMcmp GPR:$src, so_imm_neg:$imm),
3425 // (CMNri GPR:$src, so_imm_neg:$imm)>;
3427 def : ARMPat<(ARMcmpZ GPR:$src, so_imm_neg:$imm),
3428 (CMNzri GPR:$src, so_imm_neg:$imm)>;
3430 // Pseudo i64 compares for some floating point compares.
3431 let usesCustomInserter = 1, isBranch = 1, isTerminator = 1,
3433 def BCCi64 : PseudoInst<(outs),
3434 (ins i32imm:$cc, GPR:$lhs1, GPR:$lhs2, GPR:$rhs1, GPR:$rhs2, brtarget:$dst),
3436 [(ARMBcci64 imm:$cc, GPR:$lhs1, GPR:$lhs2, GPR:$rhs1, GPR:$rhs2, bb:$dst)]>;
3438 def BCCZi64 : PseudoInst<(outs),
3439 (ins i32imm:$cc, GPR:$lhs1, GPR:$lhs2, brtarget:$dst), IIC_Br,
3440 [(ARMBcci64 imm:$cc, GPR:$lhs1, GPR:$lhs2, 0, 0, bb:$dst)]>;
3441 } // usesCustomInserter
3444 // Conditional moves
3445 // FIXME: should be able to write a pattern for ARMcmov, but can't use
3446 // a two-value operand where a dag node expects two operands. :(
3447 let neverHasSideEffects = 1 in {
3448 def MOVCCr : ARMPseudoInst<(outs GPR:$Rd), (ins GPR:$false, GPR:$Rm, pred:$p),
3450 [/*(set GPR:$Rd, (ARMcmov GPR:$false, GPR:$Rm, imm:$cc, CCR:$ccr))*/]>,
3451 RegConstraint<"$false = $Rd">;
3452 def MOVCCsi : ARMPseudoInst<(outs GPR:$Rd),
3453 (ins GPR:$false, so_reg_imm:$shift, pred:$p),
3455 [/*(set GPR:$Rd, (ARMcmov GPR:$false, so_reg_imm:$shift, imm:$cc, CCR:$ccr))*/]>,
3456 RegConstraint<"$false = $Rd">;
3457 def MOVCCsr : ARMPseudoInst<(outs GPR:$Rd),
3458 (ins GPR:$false, so_reg_reg:$shift, pred:$p),
3460 [/*(set GPR:$Rd, (ARMcmov GPR:$false, so_reg_reg:$shift, imm:$cc, CCR:$ccr))*/]>,
3461 RegConstraint<"$false = $Rd">;
3464 let isMoveImm = 1 in
3465 def MOVCCi16 : ARMPseudoInst<(outs GPR:$Rd),
3466 (ins GPR:$false, imm0_65535_expr:$imm, pred:$p),
3469 RegConstraint<"$false = $Rd">, Requires<[IsARM, HasV6T2]>;
3471 let isMoveImm = 1 in
3472 def MOVCCi : ARMPseudoInst<(outs GPR:$Rd),
3473 (ins GPR:$false, so_imm:$imm, pred:$p),
3475 [/*(set GPR:$Rd, (ARMcmov GPR:$false, so_imm:$imm, imm:$cc, CCR:$ccr))*/]>,
3476 RegConstraint<"$false = $Rd">;
3478 // Two instruction predicate mov immediate.
3479 let isMoveImm = 1 in
3480 def MOVCCi32imm : ARMPseudoInst<(outs GPR:$Rd),
3481 (ins GPR:$false, i32imm:$src, pred:$p),
3482 8, IIC_iCMOVix2, []>, RegConstraint<"$false = $Rd">;
3484 let isMoveImm = 1 in
3485 def MVNCCi : ARMPseudoInst<(outs GPR:$Rd),
3486 (ins GPR:$false, so_imm:$imm, pred:$p),
3488 [/*(set GPR:$Rd, (ARMcmov GPR:$false, so_imm_not:$imm, imm:$cc, CCR:$ccr))*/]>,
3489 RegConstraint<"$false = $Rd">;
3490 } // neverHasSideEffects
3492 //===----------------------------------------------------------------------===//
3493 // Atomic operations intrinsics
3496 def MemBarrierOptOperand : AsmOperandClass {
3497 let Name = "MemBarrierOpt";
3498 let ParserMethod = "parseMemBarrierOptOperand";
3500 def memb_opt : Operand<i32> {
3501 let PrintMethod = "printMemBOption";
3502 let ParserMatchClass = MemBarrierOptOperand;
3505 // memory barriers protect the atomic sequences
3506 let hasSideEffects = 1 in {
3507 def DMB : AInoP<(outs), (ins memb_opt:$opt), MiscFrm, NoItinerary,
3508 "dmb", "\t$opt", [(ARMMemBarrier (i32 imm:$opt))]>,
3509 Requires<[IsARM, HasDB]> {
3511 let Inst{31-4} = 0xf57ff05;
3512 let Inst{3-0} = opt;
3516 def DSB : AInoP<(outs), (ins memb_opt:$opt), MiscFrm, NoItinerary,
3517 "dsb", "\t$opt", []>,
3518 Requires<[IsARM, HasDB]> {
3520 let Inst{31-4} = 0xf57ff04;
3521 let Inst{3-0} = opt;
3524 // ISB has only full system option
3525 def ISB : AInoP<(outs), (ins memb_opt:$opt), MiscFrm, NoItinerary,
3526 "isb", "\t$opt", []>,
3527 Requires<[IsARM, HasDB]> {
3529 let Inst{31-4} = 0xf57ff06;
3530 let Inst{3-0} = opt;
3533 let usesCustomInserter = 1 in {
3534 let Uses = [CPSR] in {
3535 def ATOMIC_LOAD_ADD_I8 : PseudoInst<
3536 (outs GPR:$dst), (ins GPR:$ptr, GPR:$incr), NoItinerary,
3537 [(set GPR:$dst, (atomic_load_add_8 GPR:$ptr, GPR:$incr))]>;
3538 def ATOMIC_LOAD_SUB_I8 : PseudoInst<
3539 (outs GPR:$dst), (ins GPR:$ptr, GPR:$incr), NoItinerary,
3540 [(set GPR:$dst, (atomic_load_sub_8 GPR:$ptr, GPR:$incr))]>;
3541 def ATOMIC_LOAD_AND_I8 : PseudoInst<
3542 (outs GPR:$dst), (ins GPR:$ptr, GPR:$incr), NoItinerary,
3543 [(set GPR:$dst, (atomic_load_and_8 GPR:$ptr, GPR:$incr))]>;
3544 def ATOMIC_LOAD_OR_I8 : PseudoInst<
3545 (outs GPR:$dst), (ins GPR:$ptr, GPR:$incr), NoItinerary,
3546 [(set GPR:$dst, (atomic_load_or_8 GPR:$ptr, GPR:$incr))]>;
3547 def ATOMIC_LOAD_XOR_I8 : PseudoInst<
3548 (outs GPR:$dst), (ins GPR:$ptr, GPR:$incr), NoItinerary,
3549 [(set GPR:$dst, (atomic_load_xor_8 GPR:$ptr, GPR:$incr))]>;
3550 def ATOMIC_LOAD_NAND_I8 : PseudoInst<
3551 (outs GPR:$dst), (ins GPR:$ptr, GPR:$incr), NoItinerary,
3552 [(set GPR:$dst, (atomic_load_nand_8 GPR:$ptr, GPR:$incr))]>;
3553 def ATOMIC_LOAD_MIN_I8 : PseudoInst<
3554 (outs GPR:$dst), (ins GPR:$ptr, GPR:$val), NoItinerary,
3555 [(set GPR:$dst, (atomic_load_min_8 GPR:$ptr, GPR:$val))]>;
3556 def ATOMIC_LOAD_MAX_I8 : PseudoInst<
3557 (outs GPR:$dst), (ins GPR:$ptr, GPR:$val), NoItinerary,
3558 [(set GPR:$dst, (atomic_load_max_8 GPR:$ptr, GPR:$val))]>;
3559 def ATOMIC_LOAD_UMIN_I8 : PseudoInst<
3560 (outs GPR:$dst), (ins GPR:$ptr, GPR:$val), NoItinerary,
3561 [(set GPR:$dst, (atomic_load_min_8 GPR:$ptr, GPR:$val))]>;
3562 def ATOMIC_LOAD_UMAX_I8 : PseudoInst<
3563 (outs GPR:$dst), (ins GPR:$ptr, GPR:$val), NoItinerary,
3564 [(set GPR:$dst, (atomic_load_max_8 GPR:$ptr, GPR:$val))]>;
3565 def ATOMIC_LOAD_ADD_I16 : PseudoInst<
3566 (outs GPR:$dst), (ins GPR:$ptr, GPR:$incr), NoItinerary,
3567 [(set GPR:$dst, (atomic_load_add_16 GPR:$ptr, GPR:$incr))]>;
3568 def ATOMIC_LOAD_SUB_I16 : PseudoInst<
3569 (outs GPR:$dst), (ins GPR:$ptr, GPR:$incr), NoItinerary,
3570 [(set GPR:$dst, (atomic_load_sub_16 GPR:$ptr, GPR:$incr))]>;
3571 def ATOMIC_LOAD_AND_I16 : PseudoInst<
3572 (outs GPR:$dst), (ins GPR:$ptr, GPR:$incr), NoItinerary,
3573 [(set GPR:$dst, (atomic_load_and_16 GPR:$ptr, GPR:$incr))]>;
3574 def ATOMIC_LOAD_OR_I16 : PseudoInst<
3575 (outs GPR:$dst), (ins GPR:$ptr, GPR:$incr), NoItinerary,
3576 [(set GPR:$dst, (atomic_load_or_16 GPR:$ptr, GPR:$incr))]>;
3577 def ATOMIC_LOAD_XOR_I16 : PseudoInst<
3578 (outs GPR:$dst), (ins GPR:$ptr, GPR:$incr), NoItinerary,
3579 [(set GPR:$dst, (atomic_load_xor_16 GPR:$ptr, GPR:$incr))]>;
3580 def ATOMIC_LOAD_NAND_I16 : PseudoInst<
3581 (outs GPR:$dst), (ins GPR:$ptr, GPR:$incr), NoItinerary,
3582 [(set GPR:$dst, (atomic_load_nand_16 GPR:$ptr, GPR:$incr))]>;
3583 def ATOMIC_LOAD_MIN_I16 : PseudoInst<
3584 (outs GPR:$dst), (ins GPR:$ptr, GPR:$val), NoItinerary,
3585 [(set GPR:$dst, (atomic_load_min_16 GPR:$ptr, GPR:$val))]>;
3586 def ATOMIC_LOAD_MAX_I16 : PseudoInst<
3587 (outs GPR:$dst), (ins GPR:$ptr, GPR:$val), NoItinerary,
3588 [(set GPR:$dst, (atomic_load_max_16 GPR:$ptr, GPR:$val))]>;
3589 def ATOMIC_LOAD_UMIN_I16 : PseudoInst<
3590 (outs GPR:$dst), (ins GPR:$ptr, GPR:$val), NoItinerary,
3591 [(set GPR:$dst, (atomic_load_min_16 GPR:$ptr, GPR:$val))]>;
3592 def ATOMIC_LOAD_UMAX_I16 : PseudoInst<
3593 (outs GPR:$dst), (ins GPR:$ptr, GPR:$val), NoItinerary,
3594 [(set GPR:$dst, (atomic_load_max_16 GPR:$ptr, GPR:$val))]>;
3595 def ATOMIC_LOAD_ADD_I32 : PseudoInst<
3596 (outs GPR:$dst), (ins GPR:$ptr, GPR:$incr), NoItinerary,
3597 [(set GPR:$dst, (atomic_load_add_32 GPR:$ptr, GPR:$incr))]>;
3598 def ATOMIC_LOAD_SUB_I32 : PseudoInst<
3599 (outs GPR:$dst), (ins GPR:$ptr, GPR:$incr), NoItinerary,
3600 [(set GPR:$dst, (atomic_load_sub_32 GPR:$ptr, GPR:$incr))]>;
3601 def ATOMIC_LOAD_AND_I32 : PseudoInst<
3602 (outs GPR:$dst), (ins GPR:$ptr, GPR:$incr), NoItinerary,
3603 [(set GPR:$dst, (atomic_load_and_32 GPR:$ptr, GPR:$incr))]>;
3604 def ATOMIC_LOAD_OR_I32 : PseudoInst<
3605 (outs GPR:$dst), (ins GPR:$ptr, GPR:$incr), NoItinerary,
3606 [(set GPR:$dst, (atomic_load_or_32 GPR:$ptr, GPR:$incr))]>;
3607 def ATOMIC_LOAD_XOR_I32 : PseudoInst<
3608 (outs GPR:$dst), (ins GPR:$ptr, GPR:$incr), NoItinerary,
3609 [(set GPR:$dst, (atomic_load_xor_32 GPR:$ptr, GPR:$incr))]>;
3610 def ATOMIC_LOAD_NAND_I32 : PseudoInst<
3611 (outs GPR:$dst), (ins GPR:$ptr, GPR:$incr), NoItinerary,
3612 [(set GPR:$dst, (atomic_load_nand_32 GPR:$ptr, GPR:$incr))]>;
3613 def ATOMIC_LOAD_MIN_I32 : PseudoInst<
3614 (outs GPR:$dst), (ins GPR:$ptr, GPR:$val), NoItinerary,
3615 [(set GPR:$dst, (atomic_load_min_32 GPR:$ptr, GPR:$val))]>;
3616 def ATOMIC_LOAD_MAX_I32 : PseudoInst<
3617 (outs GPR:$dst), (ins GPR:$ptr, GPR:$val), NoItinerary,
3618 [(set GPR:$dst, (atomic_load_max_32 GPR:$ptr, GPR:$val))]>;
3619 def ATOMIC_LOAD_UMIN_I32 : PseudoInst<
3620 (outs GPR:$dst), (ins GPR:$ptr, GPR:$val), NoItinerary,
3621 [(set GPR:$dst, (atomic_load_min_32 GPR:$ptr, GPR:$val))]>;
3622 def ATOMIC_LOAD_UMAX_I32 : PseudoInst<
3623 (outs GPR:$dst), (ins GPR:$ptr, GPR:$val), NoItinerary,
3624 [(set GPR:$dst, (atomic_load_max_32 GPR:$ptr, GPR:$val))]>;
3626 def ATOMIC_SWAP_I8 : PseudoInst<
3627 (outs GPR:$dst), (ins GPR:$ptr, GPR:$new), NoItinerary,
3628 [(set GPR:$dst, (atomic_swap_8 GPR:$ptr, GPR:$new))]>;
3629 def ATOMIC_SWAP_I16 : PseudoInst<
3630 (outs GPR:$dst), (ins GPR:$ptr, GPR:$new), NoItinerary,
3631 [(set GPR:$dst, (atomic_swap_16 GPR:$ptr, GPR:$new))]>;
3632 def ATOMIC_SWAP_I32 : PseudoInst<
3633 (outs GPR:$dst), (ins GPR:$ptr, GPR:$new), NoItinerary,
3634 [(set GPR:$dst, (atomic_swap_32 GPR:$ptr, GPR:$new))]>;
3636 def ATOMIC_CMP_SWAP_I8 : PseudoInst<
3637 (outs GPR:$dst), (ins GPR:$ptr, GPR:$old, GPR:$new), NoItinerary,
3638 [(set GPR:$dst, (atomic_cmp_swap_8 GPR:$ptr, GPR:$old, GPR:$new))]>;
3639 def ATOMIC_CMP_SWAP_I16 : PseudoInst<
3640 (outs GPR:$dst), (ins GPR:$ptr, GPR:$old, GPR:$new), NoItinerary,
3641 [(set GPR:$dst, (atomic_cmp_swap_16 GPR:$ptr, GPR:$old, GPR:$new))]>;
3642 def ATOMIC_CMP_SWAP_I32 : PseudoInst<
3643 (outs GPR:$dst), (ins GPR:$ptr, GPR:$old, GPR:$new), NoItinerary,
3644 [(set GPR:$dst, (atomic_cmp_swap_32 GPR:$ptr, GPR:$old, GPR:$new))]>;
3648 let mayLoad = 1 in {
3649 def LDREXB : AIldrex<0b10, (outs GPR:$Rt), (ins addrmode7:$addr), NoItinerary,
3650 "ldrexb", "\t$Rt, $addr", []>;
3651 def LDREXH : AIldrex<0b11, (outs GPR:$Rt), (ins addrmode7:$addr), NoItinerary,
3652 "ldrexh", "\t$Rt, $addr", []>;
3653 def LDREX : AIldrex<0b00, (outs GPR:$Rt), (ins addrmode7:$addr), NoItinerary,
3654 "ldrex", "\t$Rt, $addr", []>;
3655 let hasExtraDefRegAllocReq = 1 in
3656 def LDREXD : AIldrex<0b01, (outs GPR:$Rt, GPR:$Rt2), (ins addrmode7:$addr),
3657 NoItinerary, "ldrexd", "\t$Rt, $Rt2, $addr", []>;
3660 let mayStore = 1, Constraints = "@earlyclobber $Rd" in {
3661 def STREXB : AIstrex<0b10, (outs GPR:$Rd), (ins GPR:$Rt, addrmode7:$addr),
3662 NoItinerary, "strexb", "\t$Rd, $Rt, $addr", []>;
3663 def STREXH : AIstrex<0b11, (outs GPR:$Rd), (ins GPR:$Rt, addrmode7:$addr),
3664 NoItinerary, "strexh", "\t$Rd, $Rt, $addr", []>;
3665 def STREX : AIstrex<0b00, (outs GPR:$Rd), (ins GPR:$Rt, addrmode7:$addr),
3666 NoItinerary, "strex", "\t$Rd, $Rt, $addr", []>;
3669 let hasExtraSrcRegAllocReq = 1, Constraints = "@earlyclobber $Rd" in
3670 def STREXD : AIstrex<0b01, (outs GPR:$Rd),
3671 (ins GPR:$Rt, GPR:$Rt2, addrmode7:$addr),
3672 NoItinerary, "strexd", "\t$Rd, $Rt, $Rt2, $addr", []>;
3674 // Clear-Exclusive is for disassembly only.
3675 def CLREX : AXI<(outs), (ins), MiscFrm, NoItinerary, "clrex",
3676 [/* For disassembly only; pattern left blank */]>,
3677 Requires<[IsARM, HasV7]> {
3678 let Inst{31-0} = 0b11110101011111111111000000011111;
3681 // SWP/SWPB are deprecated in V6/V7.
3682 let mayLoad = 1, mayStore = 1 in {
3683 def SWP : AIswp<0, (outs GPR:$Rt), (ins GPR:$Rt2, addrmode7:$addr), "swp", []>;
3684 def SWPB: AIswp<1, (outs GPR:$Rt), (ins GPR:$Rt2, addrmode7:$addr), "swpb", []>;
3687 //===----------------------------------------------------------------------===//
3688 // Coprocessor Instructions.
3691 def CDP : ABI<0b1110, (outs), (ins p_imm:$cop, imm0_15:$opc1,
3692 c_imm:$CRd, c_imm:$CRn, c_imm:$CRm, imm0_7:$opc2),
3693 NoItinerary, "cdp", "\t$cop, $opc1, $CRd, $CRn, $CRm, $opc2",
3694 [(int_arm_cdp imm:$cop, imm:$opc1, imm:$CRd, imm:$CRn,
3695 imm:$CRm, imm:$opc2)]> {
3703 let Inst{3-0} = CRm;
3705 let Inst{7-5} = opc2;
3706 let Inst{11-8} = cop;
3707 let Inst{15-12} = CRd;
3708 let Inst{19-16} = CRn;
3709 let Inst{23-20} = opc1;
3712 def CDP2 : ABXI<0b1110, (outs), (ins p_imm:$cop, imm0_15:$opc1,
3713 c_imm:$CRd, c_imm:$CRn, c_imm:$CRm, imm0_7:$opc2),
3714 NoItinerary, "cdp2\t$cop, $opc1, $CRd, $CRn, $CRm, $opc2",
3715 [(int_arm_cdp2 imm:$cop, imm:$opc1, imm:$CRd, imm:$CRn,
3716 imm:$CRm, imm:$opc2)]> {
3717 let Inst{31-28} = 0b1111;
3725 let Inst{3-0} = CRm;
3727 let Inst{7-5} = opc2;
3728 let Inst{11-8} = cop;
3729 let Inst{15-12} = CRd;
3730 let Inst{19-16} = CRn;
3731 let Inst{23-20} = opc1;
3734 class ACI<dag oops, dag iops, string opc, string asm,
3735 IndexMode im = IndexModeNone>
3736 : InoP<oops, iops, AddrModeNone, 4, im, BrFrm, NoItinerary,
3737 opc, asm, "", [/* For disassembly only; pattern left blank */]> {
3738 let Inst{27-25} = 0b110;
3741 multiclass LdStCop<bits<4> op31_28, bit load, dag ops, string opc, string cond>{
3743 def _OFFSET : ACI<(outs),
3744 !con((ins nohash_imm:$cop, nohash_imm:$CRd, addrmode2:$addr), ops),
3745 !strconcat(opc, cond), "\tp$cop, cr$CRd, $addr"> {
3746 let Inst{31-28} = op31_28;
3747 let Inst{24} = 1; // P = 1
3748 let Inst{21} = 0; // W = 0
3749 let Inst{22} = 0; // D = 0
3750 let Inst{20} = load;
3753 def _PRE : ACI<(outs),
3754 !con((ins nohash_imm:$cop, nohash_imm:$CRd, addrmode2:$addr), ops),
3755 !strconcat(opc, cond), "\tp$cop, cr$CRd, $addr!", IndexModePre> {
3756 let Inst{31-28} = op31_28;
3757 let Inst{24} = 1; // P = 1
3758 let Inst{21} = 1; // W = 1
3759 let Inst{22} = 0; // D = 0
3760 let Inst{20} = load;
3763 def _POST : ACI<(outs),
3764 !con((ins nohash_imm:$cop, nohash_imm:$CRd, addrmode2:$addr), ops),
3765 !strconcat(opc, cond), "\tp$cop, cr$CRd, $addr", IndexModePost> {
3766 let Inst{31-28} = op31_28;
3767 let Inst{24} = 0; // P = 0
3768 let Inst{21} = 1; // W = 1
3769 let Inst{22} = 0; // D = 0
3770 let Inst{20} = load;
3773 def _OPTION : ACI<(outs),
3774 !con((ins nohash_imm:$cop,nohash_imm:$CRd,GPR:$base, nohash_imm:$option),
3776 !strconcat(opc, cond), "\tp$cop, cr$CRd, [$base], \\{$option\\}"> {
3777 let Inst{31-28} = op31_28;
3778 let Inst{24} = 0; // P = 0
3779 let Inst{23} = 1; // U = 1
3780 let Inst{21} = 0; // W = 0
3781 let Inst{22} = 0; // D = 0
3782 let Inst{20} = load;
3785 def L_OFFSET : ACI<(outs),
3786 !con((ins nohash_imm:$cop, nohash_imm:$CRd, addrmode2:$addr), ops),
3787 !strconcat(!strconcat(opc, "l"), cond), "\tp$cop, cr$CRd, $addr"> {
3788 let Inst{31-28} = op31_28;
3789 let Inst{24} = 1; // P = 1
3790 let Inst{21} = 0; // W = 0
3791 let Inst{22} = 1; // D = 1
3792 let Inst{20} = load;
3795 def L_PRE : ACI<(outs),
3796 !con((ins nohash_imm:$cop, nohash_imm:$CRd, addrmode2:$addr), ops),
3797 !strconcat(!strconcat(opc, "l"), cond), "\tp$cop, cr$CRd, $addr!",
3799 let Inst{31-28} = op31_28;
3800 let Inst{24} = 1; // P = 1
3801 let Inst{21} = 1; // W = 1
3802 let Inst{22} = 1; // D = 1
3803 let Inst{20} = load;
3806 def L_POST : ACI<(outs),
3807 !con((ins nohash_imm:$cop, nohash_imm:$CRd, addrmode2:$addr), ops),
3808 !strconcat(!strconcat(opc, "l"), cond), "\tp$cop, cr$CRd, $addr",
3810 let Inst{31-28} = op31_28;
3811 let Inst{24} = 0; // P = 0
3812 let Inst{21} = 1; // W = 1
3813 let Inst{22} = 1; // D = 1
3814 let Inst{20} = load;
3817 def L_OPTION : ACI<(outs),
3818 !con((ins nohash_imm:$cop, nohash_imm:$CRd,GPR:$base,nohash_imm:$option),
3820 !strconcat(!strconcat(opc, "l"), cond),
3821 "\tp$cop, cr$CRd, [$base], \\{$option\\}"> {
3822 let Inst{31-28} = op31_28;
3823 let Inst{24} = 0; // P = 0
3824 let Inst{23} = 1; // U = 1
3825 let Inst{21} = 0; // W = 0
3826 let Inst{22} = 1; // D = 1
3827 let Inst{20} = load;
3831 defm LDC : LdStCop<{?,?,?,?}, 1, (ins pred:$p), "ldc", "${p}">;
3832 defm LDC2 : LdStCop<0b1111, 1, (ins), "ldc2", "">;
3833 defm STC : LdStCop<{?,?,?,?}, 0, (ins pred:$p), "stc", "${p}">;
3834 defm STC2 : LdStCop<0b1111, 0, (ins), "stc2", "">;
3836 //===----------------------------------------------------------------------===//
3837 // Move between coprocessor and ARM core register -- for disassembly only
3840 class MovRCopro<string opc, bit direction, dag oops, dag iops,
3842 : ABI<0b1110, oops, iops, NoItinerary, opc,
3843 "\t$cop, $opc1, $Rt, $CRn, $CRm, $opc2", pattern> {
3844 let Inst{20} = direction;
3854 let Inst{15-12} = Rt;
3855 let Inst{11-8} = cop;
3856 let Inst{23-21} = opc1;
3857 let Inst{7-5} = opc2;
3858 let Inst{3-0} = CRm;
3859 let Inst{19-16} = CRn;
3862 def MCR : MovRCopro<"mcr", 0 /* from ARM core register to coprocessor */,
3864 (ins p_imm:$cop, imm0_7:$opc1, GPR:$Rt, c_imm:$CRn,
3865 c_imm:$CRm, imm0_7:$opc2),
3866 [(int_arm_mcr imm:$cop, imm:$opc1, GPR:$Rt, imm:$CRn,
3867 imm:$CRm, imm:$opc2)]>;
3868 def MRC : MovRCopro<"mrc", 1 /* from coprocessor to ARM core register */,
3870 (ins p_imm:$cop, imm0_7:$opc1, c_imm:$CRn, c_imm:$CRm,
3873 def : ARMPat<(int_arm_mrc imm:$cop, imm:$opc1, imm:$CRn, imm:$CRm, imm:$opc2),
3874 (MRC imm:$cop, imm:$opc1, imm:$CRn, imm:$CRm, imm:$opc2)>;
3876 class MovRCopro2<string opc, bit direction, dag oops, dag iops,
3878 : ABXI<0b1110, oops, iops, NoItinerary,
3879 !strconcat(opc, "\t$cop, $opc1, $Rt, $CRn, $CRm, $opc2"), pattern> {
3880 let Inst{31-28} = 0b1111;
3881 let Inst{20} = direction;
3891 let Inst{15-12} = Rt;
3892 let Inst{11-8} = cop;
3893 let Inst{23-21} = opc1;
3894 let Inst{7-5} = opc2;
3895 let Inst{3-0} = CRm;
3896 let Inst{19-16} = CRn;
3899 def MCR2 : MovRCopro2<"mcr2", 0 /* from ARM core register to coprocessor */,
3901 (ins p_imm:$cop, imm0_7:$opc1, GPR:$Rt, c_imm:$CRn,
3902 c_imm:$CRm, imm0_7:$opc2),
3903 [(int_arm_mcr2 imm:$cop, imm:$opc1, GPR:$Rt, imm:$CRn,
3904 imm:$CRm, imm:$opc2)]>;
3905 def MRC2 : MovRCopro2<"mrc2", 1 /* from coprocessor to ARM core register */,
3907 (ins p_imm:$cop, imm0_7:$opc1, c_imm:$CRn, c_imm:$CRm,
3910 def : ARMV5TPat<(int_arm_mrc2 imm:$cop, imm:$opc1, imm:$CRn,
3911 imm:$CRm, imm:$opc2),
3912 (MRC2 imm:$cop, imm:$opc1, imm:$CRn, imm:$CRm, imm:$opc2)>;
3914 class MovRRCopro<string opc, bit direction,
3915 list<dag> pattern = [/* For disassembly only */]>
3916 : ABI<0b1100, (outs), (ins p_imm:$cop, imm0_15:$opc1,
3917 GPR:$Rt, GPR:$Rt2, c_imm:$CRm),
3918 NoItinerary, opc, "\t$cop, $opc1, $Rt, $Rt2, $CRm", pattern> {
3919 let Inst{23-21} = 0b010;
3920 let Inst{20} = direction;
3928 let Inst{15-12} = Rt;
3929 let Inst{19-16} = Rt2;
3930 let Inst{11-8} = cop;
3931 let Inst{7-4} = opc1;
3932 let Inst{3-0} = CRm;
3935 def MCRR : MovRRCopro<"mcrr", 0 /* from ARM core register to coprocessor */,
3936 [(int_arm_mcrr imm:$cop, imm:$opc1, GPR:$Rt, GPR:$Rt2,
3938 def MRRC : MovRRCopro<"mrrc", 1 /* from coprocessor to ARM core register */>;
3940 class MovRRCopro2<string opc, bit direction,
3941 list<dag> pattern = [/* For disassembly only */]>
3942 : ABXI<0b1100, (outs), (ins p_imm:$cop, imm0_15:$opc1,
3943 GPR:$Rt, GPR:$Rt2, c_imm:$CRm), NoItinerary,
3944 !strconcat(opc, "\t$cop, $opc1, $Rt, $Rt2, $CRm"), pattern> {
3945 let Inst{31-28} = 0b1111;
3946 let Inst{23-21} = 0b010;
3947 let Inst{20} = direction;
3955 let Inst{15-12} = Rt;
3956 let Inst{19-16} = Rt2;
3957 let Inst{11-8} = cop;
3958 let Inst{7-4} = opc1;
3959 let Inst{3-0} = CRm;
3962 def MCRR2 : MovRRCopro2<"mcrr2", 0 /* from ARM core register to coprocessor */,
3963 [(int_arm_mcrr2 imm:$cop, imm:$opc1, GPR:$Rt, GPR:$Rt2,
3965 def MRRC2 : MovRRCopro2<"mrrc2", 1 /* from coprocessor to ARM core register */>;
3967 //===----------------------------------------------------------------------===//
3968 // Move between special register and ARM core register
3971 // Move to ARM core register from Special Register
3972 def MRS : ABI<0b0001, (outs GPR:$Rd), (ins), NoItinerary,
3973 "mrs", "\t$Rd, apsr", []> {
3975 let Inst{23-16} = 0b00001111;
3976 let Inst{15-12} = Rd;
3977 let Inst{7-4} = 0b0000;
3980 def : InstAlias<"mrs${p} $Rd, cpsr", (MRS GPR:$Rd, pred:$p)>, Requires<[IsARM]>;
3982 def MRSsys : ABI<0b0001, (outs GPR:$Rd), (ins), NoItinerary,
3983 "mrs", "\t$Rd, spsr", []> {
3985 let Inst{23-16} = 0b01001111;
3986 let Inst{15-12} = Rd;
3987 let Inst{7-4} = 0b0000;
3990 // Move from ARM core register to Special Register
3992 // No need to have both system and application versions, the encodings are the
3993 // same and the assembly parser has no way to distinguish between them. The mask
3994 // operand contains the special register (R Bit) in bit 4 and bits 3-0 contains
3995 // the mask with the fields to be accessed in the special register.
3996 def MSR : ABI<0b0001, (outs), (ins msr_mask:$mask, GPR:$Rn), NoItinerary,
3997 "msr", "\t$mask, $Rn", []> {
4002 let Inst{22} = mask{4}; // R bit
4003 let Inst{21-20} = 0b10;
4004 let Inst{19-16} = mask{3-0};
4005 let Inst{15-12} = 0b1111;
4006 let Inst{11-4} = 0b00000000;
4010 def MSRi : ABI<0b0011, (outs), (ins msr_mask:$mask, so_imm:$a), NoItinerary,
4011 "msr", "\t$mask, $a", []> {
4016 let Inst{22} = mask{4}; // R bit
4017 let Inst{21-20} = 0b10;
4018 let Inst{19-16} = mask{3-0};
4019 let Inst{15-12} = 0b1111;
4023 //===----------------------------------------------------------------------===//
4027 // __aeabi_read_tp preserves the registers r1-r3.
4028 // This is a pseudo inst so that we can get the encoding right,
4029 // complete with fixup for the aeabi_read_tp function.
4031 Defs = [R0, R12, LR, CPSR], Uses = [SP] in {
4032 def TPsoft : PseudoInst<(outs), (ins), IIC_Br,
4033 [(set R0, ARMthread_pointer)]>;
4036 //===----------------------------------------------------------------------===//
4037 // SJLJ Exception handling intrinsics
4038 // eh_sjlj_setjmp() is an instruction sequence to store the return
4039 // address and save #0 in R0 for the non-longjmp case.
4040 // Since by its nature we may be coming from some other function to get
4041 // here, and we're using the stack frame for the containing function to
4042 // save/restore registers, we can't keep anything live in regs across
4043 // the eh_sjlj_setjmp(), else it will almost certainly have been tromped upon
4044 // when we get here from a longjmp(). We force everything out of registers
4045 // except for our own input by listing the relevant registers in Defs. By
4046 // doing so, we also cause the prologue/epilogue code to actively preserve
4047 // all of the callee-saved resgisters, which is exactly what we want.
4048 // A constant value is passed in $val, and we use the location as a scratch.
4050 // These are pseudo-instructions and are lowered to individual MC-insts, so
4051 // no encoding information is necessary.
4053 [ R0, R1, R2, R3, R4, R5, R6, R7, R8, R9, R10, R11, R12, LR, CPSR,
4054 QQQQ0, QQQQ1, QQQQ2, QQQQ3 ], hasSideEffects = 1, isBarrier = 1 in {
4055 def Int_eh_sjlj_setjmp : PseudoInst<(outs), (ins GPR:$src, GPR:$val),
4057 [(set R0, (ARMeh_sjlj_setjmp GPR:$src, GPR:$val))]>,
4058 Requires<[IsARM, HasVFP2]>;
4062 [ R0, R1, R2, R3, R4, R5, R6, R7, R8, R9, R10, R11, R12, LR, CPSR ],
4063 hasSideEffects = 1, isBarrier = 1 in {
4064 def Int_eh_sjlj_setjmp_nofp : PseudoInst<(outs), (ins GPR:$src, GPR:$val),
4066 [(set R0, (ARMeh_sjlj_setjmp GPR:$src, GPR:$val))]>,
4067 Requires<[IsARM, NoVFP]>;
4070 // FIXME: Non-Darwin version(s)
4071 let isBarrier = 1, hasSideEffects = 1, isTerminator = 1,
4072 Defs = [ R7, LR, SP ] in {
4073 def Int_eh_sjlj_longjmp : PseudoInst<(outs), (ins GPR:$src, GPR:$scratch),
4075 [(ARMeh_sjlj_longjmp GPR:$src, GPR:$scratch)]>,
4076 Requires<[IsARM, IsDarwin]>;
4079 // eh.sjlj.dispatchsetup pseudo-instruction.
4080 // This pseudo is used for ARM, Thumb1 and Thumb2. Any differences are
4081 // handled when the pseudo is expanded (which happens before any passes
4082 // that need the instruction size).
4083 let isBarrier = 1, hasSideEffects = 1 in
4084 def Int_eh_sjlj_dispatchsetup :
4085 PseudoInst<(outs), (ins GPR:$src), NoItinerary,
4086 [(ARMeh_sjlj_dispatchsetup GPR:$src)]>,
4087 Requires<[IsDarwin]>;
4089 //===----------------------------------------------------------------------===//
4090 // Non-Instruction Patterns
4093 // ARMv4 indirect branch using (MOVr PC, dst)
4094 let isBranch = 1, isTerminator = 1, isBarrier = 1, isIndirectBranch = 1 in
4095 def MOVPCRX : ARMPseudoExpand<(outs), (ins GPR:$dst),
4096 4, IIC_Br, [(brind GPR:$dst)],
4097 (MOVr PC, GPR:$dst, (ops 14, zero_reg), zero_reg)>,
4098 Requires<[IsARM, NoV4T]>;
4100 // Large immediate handling.
4102 // 32-bit immediate using two piece so_imms or movw + movt.
4103 // This is a single pseudo instruction, the benefit is that it can be remat'd
4104 // as a single unit instead of having to handle reg inputs.
4105 // FIXME: Remove this when we can do generalized remat.
4106 let isReMaterializable = 1, isMoveImm = 1 in
4107 def MOVi32imm : PseudoInst<(outs GPR:$dst), (ins i32imm:$src), IIC_iMOVix2,
4108 [(set GPR:$dst, (arm_i32imm:$src))]>,
4111 // Pseudo instruction that combines movw + movt + add pc (if PIC).
4112 // It also makes it possible to rematerialize the instructions.
4113 // FIXME: Remove this when we can do generalized remat and when machine licm
4114 // can properly the instructions.
4115 let isReMaterializable = 1 in {
4116 def MOV_ga_pcrel : PseudoInst<(outs GPR:$dst), (ins i32imm:$addr),
4118 [(set GPR:$dst, (ARMWrapperPIC tglobaladdr:$addr))]>,
4119 Requires<[IsARM, UseMovt]>;
4121 def MOV_ga_dyn : PseudoInst<(outs GPR:$dst), (ins i32imm:$addr),
4123 [(set GPR:$dst, (ARMWrapperDYN tglobaladdr:$addr))]>,
4124 Requires<[IsARM, UseMovt]>;
4126 let AddedComplexity = 10 in
4127 def MOV_ga_pcrel_ldr : PseudoInst<(outs GPR:$dst), (ins i32imm:$addr),
4129 [(set GPR:$dst, (load (ARMWrapperPIC tglobaladdr:$addr)))]>,
4130 Requires<[IsARM, UseMovt]>;
4131 } // isReMaterializable
4133 // ConstantPool, GlobalAddress, and JumpTable
4134 def : ARMPat<(ARMWrapper tglobaladdr :$dst), (LEApcrel tglobaladdr :$dst)>,
4135 Requires<[IsARM, DontUseMovt]>;
4136 def : ARMPat<(ARMWrapper tconstpool :$dst), (LEApcrel tconstpool :$dst)>;
4137 def : ARMPat<(ARMWrapper tglobaladdr :$dst), (MOVi32imm tglobaladdr :$dst)>,
4138 Requires<[IsARM, UseMovt]>;
4139 def : ARMPat<(ARMWrapperJT tjumptable:$dst, imm:$id),
4140 (LEApcrelJT tjumptable:$dst, imm:$id)>;
4142 // TODO: add,sub,and, 3-instr forms?
4145 def : ARMPat<(ARMtcret tcGPR:$dst),
4146 (TCRETURNri tcGPR:$dst)>, Requires<[IsDarwin]>;
4148 def : ARMPat<(ARMtcret (i32 tglobaladdr:$dst)),
4149 (TCRETURNdi texternalsym:$dst)>, Requires<[IsDarwin]>;
4151 def : ARMPat<(ARMtcret (i32 texternalsym:$dst)),
4152 (TCRETURNdi texternalsym:$dst)>, Requires<[IsDarwin]>;
4154 def : ARMPat<(ARMtcret tcGPR:$dst),
4155 (TCRETURNriND tcGPR:$dst)>, Requires<[IsNotDarwin]>;
4157 def : ARMPat<(ARMtcret (i32 tglobaladdr:$dst)),
4158 (TCRETURNdiND texternalsym:$dst)>, Requires<[IsNotDarwin]>;
4160 def : ARMPat<(ARMtcret (i32 texternalsym:$dst)),
4161 (TCRETURNdiND texternalsym:$dst)>, Requires<[IsNotDarwin]>;
4164 def : ARMPat<(ARMcall texternalsym:$func), (BL texternalsym:$func)>,
4165 Requires<[IsARM, IsNotDarwin]>;
4166 def : ARMPat<(ARMcall texternalsym:$func), (BLr9 texternalsym:$func)>,
4167 Requires<[IsARM, IsDarwin]>;
4169 // zextload i1 -> zextload i8
4170 def : ARMPat<(zextloadi1 addrmode_imm12:$addr), (LDRBi12 addrmode_imm12:$addr)>;
4171 def : ARMPat<(zextloadi1 ldst_so_reg:$addr), (LDRBrs ldst_so_reg:$addr)>;
4173 // extload -> zextload
4174 def : ARMPat<(extloadi1 addrmode_imm12:$addr), (LDRBi12 addrmode_imm12:$addr)>;
4175 def : ARMPat<(extloadi1 ldst_so_reg:$addr), (LDRBrs ldst_so_reg:$addr)>;
4176 def : ARMPat<(extloadi8 addrmode_imm12:$addr), (LDRBi12 addrmode_imm12:$addr)>;
4177 def : ARMPat<(extloadi8 ldst_so_reg:$addr), (LDRBrs ldst_so_reg:$addr)>;
4179 def : ARMPat<(extloadi16 addrmode3:$addr), (LDRH addrmode3:$addr)>;
4181 def : ARMPat<(extloadi8 addrmodepc:$addr), (PICLDRB addrmodepc:$addr)>;
4182 def : ARMPat<(extloadi16 addrmodepc:$addr), (PICLDRH addrmodepc:$addr)>;
4185 def : ARMV5TEPat<(mul (sra (shl GPR:$a, (i32 16)), (i32 16)),
4186 (sra (shl GPR:$b, (i32 16)), (i32 16))),
4187 (SMULBB GPR:$a, GPR:$b)>;
4188 def : ARMV5TEPat<(mul sext_16_node:$a, sext_16_node:$b),
4189 (SMULBB GPR:$a, GPR:$b)>;
4190 def : ARMV5TEPat<(mul (sra (shl GPR:$a, (i32 16)), (i32 16)),
4191 (sra GPR:$b, (i32 16))),
4192 (SMULBT GPR:$a, GPR:$b)>;
4193 def : ARMV5TEPat<(mul sext_16_node:$a, (sra GPR:$b, (i32 16))),
4194 (SMULBT GPR:$a, GPR:$b)>;
4195 def : ARMV5TEPat<(mul (sra GPR:$a, (i32 16)),
4196 (sra (shl GPR:$b, (i32 16)), (i32 16))),
4197 (SMULTB GPR:$a, GPR:$b)>;
4198 def : ARMV5TEPat<(mul (sra GPR:$a, (i32 16)), sext_16_node:$b),
4199 (SMULTB GPR:$a, GPR:$b)>;
4200 def : ARMV5TEPat<(sra (mul GPR:$a, (sra (shl GPR:$b, (i32 16)), (i32 16))),
4202 (SMULWB GPR:$a, GPR:$b)>;
4203 def : ARMV5TEPat<(sra (mul GPR:$a, sext_16_node:$b), (i32 16)),
4204 (SMULWB GPR:$a, GPR:$b)>;
4206 def : ARMV5TEPat<(add GPR:$acc,
4207 (mul (sra (shl GPR:$a, (i32 16)), (i32 16)),
4208 (sra (shl GPR:$b, (i32 16)), (i32 16)))),
4209 (SMLABB GPR:$a, GPR:$b, GPR:$acc)>;
4210 def : ARMV5TEPat<(add GPR:$acc,
4211 (mul sext_16_node:$a, sext_16_node:$b)),
4212 (SMLABB GPR:$a, GPR:$b, GPR:$acc)>;
4213 def : ARMV5TEPat<(add GPR:$acc,
4214 (mul (sra (shl GPR:$a, (i32 16)), (i32 16)),
4215 (sra GPR:$b, (i32 16)))),
4216 (SMLABT GPR:$a, GPR:$b, GPR:$acc)>;
4217 def : ARMV5TEPat<(add GPR:$acc,
4218 (mul sext_16_node:$a, (sra GPR:$b, (i32 16)))),
4219 (SMLABT GPR:$a, GPR:$b, GPR:$acc)>;
4220 def : ARMV5TEPat<(add GPR:$acc,
4221 (mul (sra GPR:$a, (i32 16)),
4222 (sra (shl GPR:$b, (i32 16)), (i32 16)))),
4223 (SMLATB GPR:$a, GPR:$b, GPR:$acc)>;
4224 def : ARMV5TEPat<(add GPR:$acc,
4225 (mul (sra GPR:$a, (i32 16)), sext_16_node:$b)),
4226 (SMLATB GPR:$a, GPR:$b, GPR:$acc)>;
4227 def : ARMV5TEPat<(add GPR:$acc,
4228 (sra (mul GPR:$a, (sra (shl GPR:$b, (i32 16)), (i32 16))),
4230 (SMLAWB GPR:$a, GPR:$b, GPR:$acc)>;
4231 def : ARMV5TEPat<(add GPR:$acc,
4232 (sra (mul GPR:$a, sext_16_node:$b), (i32 16))),
4233 (SMLAWB GPR:$a, GPR:$b, GPR:$acc)>;
4236 // Pre-v7 uses MCR for synchronization barriers.
4237 def : ARMPat<(ARMMemBarrierMCR GPR:$zero), (MCR 15, 0, GPR:$zero, 7, 10, 5)>,
4238 Requires<[IsARM, HasV6]>;
4240 // SXT/UXT with no rotate
4241 let AddedComplexity = 16 in {
4242 def : ARMV6Pat<(and GPR:$Src, 0x000000FF), (UXTB GPR:$Src, 0)>;
4243 def : ARMV6Pat<(and GPR:$Src, 0x0000FFFF), (UXTH GPR:$Src, 0)>;
4244 def : ARMV6Pat<(and GPR:$Src, 0x00FF00FF), (UXTB16 GPR:$Src, 0)>;
4245 def : ARMV6Pat<(add GPR:$Rn, (and GPR:$Rm, 0x00FF)),
4246 (UXTAB GPR:$Rn, GPR:$Rm, 0)>;
4247 def : ARMV6Pat<(add GPR:$Rn, (and GPR:$Rm, 0xFFFF)),
4248 (UXTAH GPR:$Rn, GPR:$Rm, 0)>;
4251 def : ARMV6Pat<(sext_inreg GPR:$Src, i8), (SXTB GPR:$Src, 0)>;
4252 def : ARMV6Pat<(sext_inreg GPR:$Src, i16), (SXTH GPR:$Src, 0)>;
4254 def : ARMV6Pat<(add GPR:$Rn, (sext_inreg GPR:$Rm, i8)),
4255 (SXTAB GPR:$Rn, GPR:$Rm, 0)>;
4256 def : ARMV6Pat<(add GPR:$Rn, (sext_inreg GPR:$Rm, i16)),
4257 (SXTAH GPR:$Rn, GPR:$Rm, 0)>;
4259 //===----------------------------------------------------------------------===//
4263 include "ARMInstrThumb.td"
4265 //===----------------------------------------------------------------------===//
4269 include "ARMInstrThumb2.td"
4271 //===----------------------------------------------------------------------===//
4272 // Floating Point Support
4275 include "ARMInstrVFP.td"
4277 //===----------------------------------------------------------------------===//
4278 // Advanced SIMD (NEON) Support
4281 include "ARMInstrNEON.td"
4283 //===----------------------------------------------------------------------===//
4284 // Assembler aliases
4288 def : InstAlias<"dmb", (DMB 0xf)>, Requires<[IsARM, HasDB]>;
4289 def : InstAlias<"dsb", (DSB 0xf)>, Requires<[IsARM, HasDB]>;
4290 def : InstAlias<"isb", (ISB 0xf)>, Requires<[IsARM, HasDB]>;
4292 // System instructions
4293 def : MnemonicAlias<"swi", "svc">;
4295 // Load / Store Multiple
4296 def : MnemonicAlias<"ldmfd", "ldm">;
4297 def : MnemonicAlias<"ldmia", "ldm">;
4298 def : MnemonicAlias<"stmfd", "stmdb">;
4299 def : MnemonicAlias<"stmia", "stm">;
4300 def : MnemonicAlias<"stmea", "stm">;
4302 // PKHBT/PKHTB with default shift amount. PKHTB is equivalent to PKHBT when the
4303 // shift amount is zero (i.e., unspecified).
4304 def : InstAlias<"pkhbt${p} $Rd, $Rn, $Rm",
4305 (PKHBT GPR:$Rd, GPR:$Rn, GPR:$Rm, 0, pred:$p)>;
4306 def : InstAlias<"pkhtb${p} $Rd, $Rn, $Rm",
4307 (PKHBT GPR:$Rd, GPR:$Rn, GPR:$Rm, 0, pred:$p)>;
4309 // PUSH/POP aliases for STM/LDM
4310 def : InstAlias<"push${p} $regs",
4311 (STMDB_UPD SP, pred:$p, reglist:$regs)>;
4312 def : InstAlias<"pop${p} $regs",
4313 (LDMIA_UPD SP, pred:$p, reglist:$regs)>;
4315 // RSB two-operand forms (optional explicit destination operand)
4316 def : InstAlias<"rsb${s}${p} $Rdn, $imm",
4317 (RSBri GPR:$Rdn, GPR:$Rdn, so_imm:$imm, pred:$p, cc_out:$s)>,
4319 def : InstAlias<"rsb${s}${p} $Rdn, $Rm",
4320 (RSBrr GPR:$Rdn, GPR:$Rdn, GPR:$Rm, pred:$p, cc_out:$s)>,
4322 def : InstAlias<"rsb${s}${p} $Rdn, $shift",
4323 (RSBrsi GPR:$Rdn, GPR:$Rdn, so_reg_imm:$shift, pred:$p,
4324 cc_out:$s)>, Requires<[IsARM]>;
4325 def : InstAlias<"rsb${s}${p} $Rdn, $shift",
4326 (RSBrsr GPR:$Rdn, GPR:$Rdn, so_reg_reg:$shift, pred:$p,
4327 cc_out:$s)>, Requires<[IsARM]>;
4328 // RSC two-operand forms (optional explicit destination operand)
4329 def : InstAlias<"rsc${s}${p} $Rdn, $imm",
4330 (RSCri GPR:$Rdn, GPR:$Rdn, so_imm:$imm, pred:$p, cc_out:$s)>,
4332 def : InstAlias<"rsc${s}${p} $Rdn, $Rm",
4333 (RSCrr GPR:$Rdn, GPR:$Rdn, GPR:$Rm, pred:$p, cc_out:$s)>,
4335 def : InstAlias<"rsc${s}${p} $Rdn, $shift",
4336 (RSCrsi GPR:$Rdn, GPR:$Rdn, so_reg_imm:$shift, pred:$p,
4337 cc_out:$s)>, Requires<[IsARM]>;
4338 def : InstAlias<"rsc${s}${p} $Rdn, $shift",
4339 (RSCrsr GPR:$Rdn, GPR:$Rdn, so_reg_reg:$shift, pred:$p,
4340 cc_out:$s)>, Requires<[IsARM]>;
4342 // SSAT optional shift operand.
4343 def : InstAlias<"ssat${p} $Rd, $sat_imm, $Rn",
4344 (SSAT GPR:$Rd, imm1_32:$sat_imm, GPR:$Rn, 0, pred:$p)>;
4347 // Extend instruction optional rotate operand.
4348 def : InstAlias<"sxtab${p} $Rd, $Rn, $Rm",
4349 (SXTAB GPR:$Rd, GPR:$Rn, GPR:$Rm, 0, pred:$p)>;
4350 def : InstAlias<"sxtah${p} $Rd, $Rn, $Rm",
4351 (SXTAH GPR:$Rd, GPR:$Rn, GPR:$Rm, 0, pred:$p)>;
4352 def : InstAlias<"sxtab16${p} $Rd, $Rn, $Rm",
4353 (SXTAB16 GPR:$Rd, GPR:$Rn, GPR:$Rm, 0, pred:$p)>;
4354 def : InstAlias<"sxtb${p} $Rd, $Rm", (SXTB GPR:$Rd, GPR:$Rm, 0, pred:$p)>;
4355 def : InstAlias<"sxtb16${p} $Rd, $Rm", (SXTB16 GPR:$Rd, GPR:$Rm, 0, pred:$p)>;
4356 def : InstAlias<"sxth${p} $Rd, $Rm", (SXTH GPR:$Rd, GPR:$Rm, 0, pred:$p)>;
4358 def : InstAlias<"uxtab${p} $Rd, $Rn, $Rm",
4359 (UXTAB GPR:$Rd, GPR:$Rn, GPR:$Rm, 0, pred:$p)>;
4360 def : InstAlias<"uxtah${p} $Rd, $Rn, $Rm",
4361 (UXTAH GPR:$Rd, GPR:$Rn, GPR:$Rm, 0, pred:$p)>;
4362 def : InstAlias<"uxtab16${p} $Rd, $Rn, $Rm",
4363 (UXTAB16 GPR:$Rd, GPR:$Rn, GPR:$Rm, 0, pred:$p)>;
4364 def : InstAlias<"uxtb${p} $Rd, $Rm", (UXTB GPR:$Rd, GPR:$Rm, 0, pred:$p)>;
4365 def : InstAlias<"uxtb16${p} $Rd, $Rm", (UXTB16 GPR:$Rd, GPR:$Rm, 0, pred:$p)>;
4366 def : InstAlias<"uxth${p} $Rd, $Rm", (UXTH GPR:$Rd, GPR:$Rm, 0, pred:$p)>;