1 //===- ARMInstrInfo.td - Target Description for ARM Target -*- tablegen -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file describes the ARM instructions in TableGen format.
12 //===----------------------------------------------------------------------===//
14 //===----------------------------------------------------------------------===//
15 // ARM specific DAG Nodes.
19 def SDT_ARMCallSeqStart : SDCallSeqStart<[ SDTCisVT<0, i32> ]>;
20 def SDT_ARMCallSeqEnd : SDCallSeqEnd<[ SDTCisVT<0, i32>, SDTCisVT<1, i32> ]>;
22 def SDT_ARMSaveCallPC : SDTypeProfile<0, 1, []>;
24 def SDT_ARMcall : SDTypeProfile<0, -1, [SDTCisInt<0>]>;
26 def SDT_ARMCMov : SDTypeProfile<1, 3,
27 [SDTCisSameAs<0, 1>, SDTCisSameAs<0, 2>,
30 def SDT_ARMBrcond : SDTypeProfile<0, 2,
31 [SDTCisVT<0, OtherVT>, SDTCisVT<1, i32>]>;
33 def SDT_ARMBrJT : SDTypeProfile<0, 3,
34 [SDTCisPtrTy<0>, SDTCisVT<1, i32>,
37 def SDT_ARMCmp : SDTypeProfile<0, 2, [SDTCisSameAs<0, 1>]>;
39 def SDT_ARMPICAdd : SDTypeProfile<1, 2, [SDTCisSameAs<0, 1>,
40 SDTCisPtrTy<1>, SDTCisVT<2, i32>]>;
42 def SDT_ARMThreadPointer : SDTypeProfile<1, 0, [SDTCisPtrTy<0>]>;
45 def ARMWrapper : SDNode<"ARMISD::Wrapper", SDTIntUnaryOp>;
46 def ARMWrapperJT : SDNode<"ARMISD::WrapperJT", SDTIntBinOp>;
48 def ARMcallseq_start : SDNode<"ISD::CALLSEQ_START", SDT_ARMCallSeqStart,
49 [SDNPHasChain, SDNPOutFlag]>;
50 def ARMcallseq_end : SDNode<"ISD::CALLSEQ_END", SDT_ARMCallSeqEnd,
51 [SDNPHasChain, SDNPOptInFlag, SDNPOutFlag]>;
53 def ARMcall : SDNode<"ARMISD::CALL", SDT_ARMcall,
54 [SDNPHasChain, SDNPOptInFlag, SDNPOutFlag]>;
55 def ARMcall_pred : SDNode<"ARMISD::CALL_PRED", SDT_ARMcall,
56 [SDNPHasChain, SDNPOptInFlag, SDNPOutFlag]>;
57 def ARMcall_nolink : SDNode<"ARMISD::CALL_NOLINK", SDT_ARMcall,
58 [SDNPHasChain, SDNPOptInFlag, SDNPOutFlag]>;
60 def ARMretflag : SDNode<"ARMISD::RET_FLAG", SDTRet,
61 [SDNPHasChain, SDNPOptInFlag]>;
63 def ARMcmov : SDNode<"ARMISD::CMOV", SDT_ARMCMov,
65 def ARMcneg : SDNode<"ARMISD::CNEG", SDT_ARMCMov,
68 def ARMbrcond : SDNode<"ARMISD::BRCOND", SDT_ARMBrcond,
69 [SDNPHasChain, SDNPInFlag, SDNPOutFlag]>;
71 def ARMbrjt : SDNode<"ARMISD::BR_JT", SDT_ARMBrJT,
74 def ARMcmp : SDNode<"ARMISD::CMP", SDT_ARMCmp,
77 def ARMcmpNZ : SDNode<"ARMISD::CMPNZ", SDT_ARMCmp,
80 def ARMpic_add : SDNode<"ARMISD::PIC_ADD", SDT_ARMPICAdd>;
82 def ARMsrl_flag : SDNode<"ARMISD::SRL_FLAG", SDTIntUnaryOp, [SDNPOutFlag]>;
83 def ARMsra_flag : SDNode<"ARMISD::SRA_FLAG", SDTIntUnaryOp, [SDNPOutFlag]>;
84 def ARMrrx : SDNode<"ARMISD::RRX" , SDTIntUnaryOp, [SDNPInFlag ]>;
86 def ARMthread_pointer: SDNode<"ARMISD::THREAD_POINTER", SDT_ARMThreadPointer>;
88 //===----------------------------------------------------------------------===//
89 // ARM Instruction Predicate Definitions.
91 def HasV5T : Predicate<"Subtarget->hasV5TOps()">;
92 def HasV5TE : Predicate<"Subtarget->hasV5TEOps()">;
93 def HasV6 : Predicate<"Subtarget->hasV6Ops()">;
94 def IsThumb : Predicate<"Subtarget->isThumb()">;
95 def IsARM : Predicate<"!Subtarget->isThumb()">;
97 //===----------------------------------------------------------------------===//
98 // ARM Flag Definitions.
100 class RegConstraint<string C> {
101 string Constraints = C;
104 //===----------------------------------------------------------------------===//
105 // ARM specific transformation functions and pattern fragments.
108 // so_imm_XFORM - Return a so_imm value packed into the format described for
110 def so_imm_XFORM : SDNodeXForm<imm, [{
111 return CurDAG->getTargetConstant(ARM_AM::getSOImmVal(N->getValue()),
115 // so_imm_neg_XFORM - Return a so_imm value packed into the format described for
116 // so_imm_neg def below.
117 def so_imm_neg_XFORM : SDNodeXForm<imm, [{
118 return CurDAG->getTargetConstant(ARM_AM::getSOImmVal(-(int)N->getValue()),
122 // so_imm_not_XFORM - Return a so_imm value packed into the format described for
123 // so_imm_not def below.
124 def so_imm_not_XFORM : SDNodeXForm<imm, [{
125 return CurDAG->getTargetConstant(ARM_AM::getSOImmVal(~(int)N->getValue()),
129 // rot_imm predicate - True if the 32-bit immediate is equal to 8, 16, or 24.
130 def rot_imm : PatLeaf<(i32 imm), [{
131 int32_t v = (int32_t)N->getValue();
132 return v == 8 || v == 16 || v == 24;
135 /// imm1_15 predicate - True if the 32-bit immediate is in the range [1,15].
136 def imm1_15 : PatLeaf<(i32 imm), [{
137 return (int32_t)N->getValue() >= 1 && (int32_t)N->getValue() < 16;
140 /// imm16_31 predicate - True if the 32-bit immediate is in the range [16,31].
141 def imm16_31 : PatLeaf<(i32 imm), [{
142 return (int32_t)N->getValue() >= 16 && (int32_t)N->getValue() < 32;
146 PatLeaf<(imm), [{ return ARM_AM::getSOImmVal(-(int)N->getValue()) != -1; }],
150 PatLeaf<(imm), [{ return ARM_AM::getSOImmVal(~(int)N->getValue()) != -1; }],
153 // sext_16_node predicate - True if the SDNode is sign-extended 16 or more bits.
154 def sext_16_node : PatLeaf<(i32 GPR:$a), [{
155 return CurDAG->ComputeNumSignBits(SDOperand(N,0)) >= 17;
160 //===----------------------------------------------------------------------===//
161 // Operand Definitions.
165 def brtarget : Operand<OtherVT>;
167 // A list of registers separated by comma. Used by load/store multiple.
168 def reglist : Operand<i32> {
169 let PrintMethod = "printRegisterList";
172 // An operand for the CONSTPOOL_ENTRY pseudo-instruction.
173 def cpinst_operand : Operand<i32> {
174 let PrintMethod = "printCPInstOperand";
177 def jtblock_operand : Operand<i32> {
178 let PrintMethod = "printJTBlockOperand";
182 def pclabel : Operand<i32> {
183 let PrintMethod = "printPCLabel";
186 // shifter_operand operands: so_reg and so_imm.
187 def so_reg : Operand<i32>, // reg reg imm
188 ComplexPattern<i32, 3, "SelectShifterOperandReg",
189 [shl,srl,sra,rotr]> {
190 let PrintMethod = "printSORegOperand";
191 let MIOperandInfo = (ops GPR, GPR, i32imm);
194 // so_imm - Match a 32-bit shifter_operand immediate operand, which is an
195 // 8-bit immediate rotated by an arbitrary number of bits. so_imm values are
196 // represented in the imm field in the same 12-bit form that they are encoded
197 // into so_imm instructions: the 8-bit immediate is the least significant bits
198 // [bits 0-7], the 4-bit shift amount is the next 4 bits [bits 8-11].
199 def so_imm : Operand<i32>,
201 [{ return ARM_AM::getSOImmVal(N->getValue()) != -1; }],
203 let PrintMethod = "printSOImmOperand";
206 // Break so_imm's up into two pieces. This handles immediates with up to 16
207 // bits set in them. This uses so_imm2part to match and so_imm2part_[12] to
208 // get the first/second pieces.
209 def so_imm2part : Operand<i32>,
211 [{ return ARM_AM::isSOImmTwoPartVal((unsigned)N->getValue()); }]> {
212 let PrintMethod = "printSOImm2PartOperand";
215 def so_imm2part_1 : SDNodeXForm<imm, [{
216 unsigned V = ARM_AM::getSOImmTwoPartFirst((unsigned)N->getValue());
217 return CurDAG->getTargetConstant(ARM_AM::getSOImmVal(V), MVT::i32);
220 def so_imm2part_2 : SDNodeXForm<imm, [{
221 unsigned V = ARM_AM::getSOImmTwoPartSecond((unsigned)N->getValue());
222 return CurDAG->getTargetConstant(ARM_AM::getSOImmVal(V), MVT::i32);
226 // Define ARM specific addressing modes.
228 // addrmode2 := reg +/- reg shop imm
229 // addrmode2 := reg +/- imm12
231 def addrmode2 : Operand<i32>,
232 ComplexPattern<i32, 3, "SelectAddrMode2", []> {
233 let PrintMethod = "printAddrMode2Operand";
234 let MIOperandInfo = (ops GPR:$base, GPR:$offsreg, i32imm:$offsimm);
237 def am2offset : Operand<i32>,
238 ComplexPattern<i32, 2, "SelectAddrMode2Offset", []> {
239 let PrintMethod = "printAddrMode2OffsetOperand";
240 let MIOperandInfo = (ops GPR, i32imm);
243 // addrmode3 := reg +/- reg
244 // addrmode3 := reg +/- imm8
246 def addrmode3 : Operand<i32>,
247 ComplexPattern<i32, 3, "SelectAddrMode3", []> {
248 let PrintMethod = "printAddrMode3Operand";
249 let MIOperandInfo = (ops GPR:$base, GPR:$offsreg, i32imm:$offsimm);
252 def am3offset : Operand<i32>,
253 ComplexPattern<i32, 2, "SelectAddrMode3Offset", []> {
254 let PrintMethod = "printAddrMode3OffsetOperand";
255 let MIOperandInfo = (ops GPR, i32imm);
258 // addrmode4 := reg, <mode|W>
260 def addrmode4 : Operand<i32>,
261 ComplexPattern<i32, 2, "", []> {
262 let PrintMethod = "printAddrMode4Operand";
263 let MIOperandInfo = (ops GPR, i32imm);
266 // addrmode5 := reg +/- imm8*4
268 def addrmode5 : Operand<i32>,
269 ComplexPattern<i32, 2, "SelectAddrMode5", []> {
270 let PrintMethod = "printAddrMode5Operand";
271 let MIOperandInfo = (ops GPR, i32imm);
274 // addrmodepc := pc + reg
276 def addrmodepc : Operand<i32>,
277 ComplexPattern<i32, 2, "SelectAddrModePC", []> {
278 let PrintMethod = "printAddrModePCOperand";
279 let MIOperandInfo = (ops GPR, i32imm);
282 // ARM Predicate operand. Default to 14 = always (AL). Second part is CC
283 // register whose default is 0 (no register).
284 def pred : PredicateOperand<OtherVT, (ops i32imm, CCR),
285 (ops (i32 14), (i32 zero_reg))> {
286 let PrintMethod = "printPredicateOperand";
289 // Conditional code result for instructions whose 's' bit is set, e.g. subs.
291 def cc_out : OptionalDefOperand<OtherVT, (ops CCR), (ops (i32 zero_reg))> {
292 let PrintMethod = "printSBitModifierOperand";
295 //===----------------------------------------------------------------------===//
296 // ARM Instruction flags. These need to match ARMInstrInfo.h.
300 class AddrMode<bits<4> val> {
303 def AddrModeNone : AddrMode<0>;
304 def AddrMode1 : AddrMode<1>;
305 def AddrMode2 : AddrMode<2>;
306 def AddrMode3 : AddrMode<3>;
307 def AddrMode4 : AddrMode<4>;
308 def AddrMode5 : AddrMode<5>;
309 def AddrModeT1 : AddrMode<6>;
310 def AddrModeT2 : AddrMode<7>;
311 def AddrModeT4 : AddrMode<8>;
312 def AddrModeTs : AddrMode<9>;
315 class SizeFlagVal<bits<3> val> {
318 def SizeInvalid : SizeFlagVal<0>; // Unset.
319 def SizeSpecial : SizeFlagVal<1>; // Pseudo or special.
320 def Size8Bytes : SizeFlagVal<2>;
321 def Size4Bytes : SizeFlagVal<3>;
322 def Size2Bytes : SizeFlagVal<4>;
324 // Load / store index mode.
325 class IndexMode<bits<2> val> {
328 def IndexModeNone : IndexMode<0>;
329 def IndexModePre : IndexMode<1>;
330 def IndexModePost : IndexMode<2>;
332 //===----------------------------------------------------------------------===//
333 // ARM Instruction Format Definitions.
336 // Format specifies the encoding used by the instruction. This is part of the
337 // ad-hoc solution used to emit machine instruction encodings by our machine
339 class Format<bits<5> val> {
343 def Pseudo : Format<1>;
344 def MulFrm : Format<2>;
345 def MulSMLAW : Format<3>;
346 def MulSMULW : Format<4>;
347 def MulSMLA : Format<5>;
348 def MulSMUL : Format<6>;
349 def Branch : Format<7>;
350 def BranchMisc : Format<8>;
352 def DPRdIm : Format<9>;
353 def DPRdReg : Format<10>;
354 def DPRdSoReg : Format<11>;
355 def DPRdMisc : Format<12>;
356 def DPRnIm : Format<13>;
357 def DPRnReg : Format<14>;
358 def DPRnSoReg : Format<15>;
359 def DPRIm : Format<16>;
360 def DPRReg : Format<17>;
361 def DPRSoReg : Format<18>;
362 def DPRImS : Format<19>;
363 def DPRRegS : Format<20>;
364 def DPRSoRegS : Format<21>;
366 def LdFrm : Format<22>;
367 def StFrm : Format<23>;
369 def ArithMisc : Format<24>;
370 def ThumbFrm : Format<25>;
371 def VFPFrm : Format<26>;
375 //===----------------------------------------------------------------------===//
377 // ARM Instruction templates.
380 // ARMPat - Same as Pat<>, but requires that the compiler be in ARM mode.
381 class ARMPat<dag pattern, dag result> : Pat<pattern, result> {
382 list<Predicate> Predicates = [IsARM];
384 class ARMV5TEPat<dag pattern, dag result> : Pat<pattern, result> {
385 list<Predicate> Predicates = [IsARM, HasV5TE];
387 class ARMV6Pat<dag pattern, dag result> : Pat<pattern, result> {
388 list<Predicate> Predicates = [IsARM, HasV6];
391 class InstARM<bits<4> opcod, AddrMode am, SizeFlagVal sz, IndexMode im,
392 Format f, string cstr>
394 let Namespace = "ARM";
396 bits<4> Opcode = opcod;
398 bits<4> AddrModeBits = AM.Value;
401 bits<3> SizeFlag = SZ.Value;
404 bits<2> IndexModeBits = IM.Value;
407 bits<5> Form = F.Value;
409 let Constraints = cstr;
412 class PseudoInst<dag oops, dag iops, string asm, list<dag> pattern>
413 : InstARM<0, AddrModeNone, SizeSpecial, IndexModeNone, Pseudo, ""> {
414 let OutOperandList = oops;
415 let InOperandList = iops;
417 let Pattern = pattern;
420 // Almost all ARM instructions are predicable.
421 class I<bits<4> opcod, dag oops, dag iops, AddrMode am, SizeFlagVal sz,
422 IndexMode im, Format f, string opc, string asm, string cstr,
424 : InstARM<opcod, am, sz, im, f, cstr> {
425 let OutOperandList = oops;
426 let InOperandList = !con(iops, (ops pred:$p));
427 let AsmString = !strconcat(opc, !strconcat("${p}", asm));
428 let Pattern = pattern;
429 list<Predicate> Predicates = [IsARM];
432 // Same as I except it can optionally modify CPSR. Note it's modeled as
433 // an input operand since by default it's a zero register. It will
434 // become an implicit def once it's "flipped".
435 class sI<bits<4> opcod, dag oops, dag iops, AddrMode am, SizeFlagVal sz,
436 IndexMode im, Format f, string opc, string asm, string cstr,
438 : InstARM<opcod, am, sz, im, f, cstr> {
439 let OutOperandList = oops;
440 let InOperandList = !con(iops, (ops pred:$p, cc_out:$s));
441 let AsmString = !strconcat(opc, !strconcat("${p}${s}", asm));
442 let Pattern = pattern;
443 list<Predicate> Predicates = [IsARM];
446 class AI<bits<4> opcod, dag oops, dag iops, Format f, string opc,
447 string asm, list<dag> pattern>
448 : I<opcod, oops, iops, AddrModeNone, Size4Bytes, IndexModeNone, f, opc,
450 class AsI<bits<4> opcod, dag oops, dag iops, Format f, string opc,
451 string asm, list<dag> pattern>
452 : sI<opcod, oops, iops, AddrModeNone, Size4Bytes, IndexModeNone, f, opc,
454 class AI1<bits<4> opcod, dag oops, dag iops, Format f, string opc,
455 string asm, list<dag> pattern>
456 : I<opcod, oops, iops, AddrMode1, Size4Bytes, IndexModeNone, f, opc,
458 class AsI1<bits<4> opcod, dag oops, dag iops, Format f, string opc,
459 string asm, list<dag> pattern>
460 : sI<opcod, oops, iops, AddrMode1, Size4Bytes, IndexModeNone, f, opc,
462 class AI2<bits<4> opcod, dag oops, dag iops, Format f, string opc,
463 string asm, list<dag> pattern>
464 : I<opcod, oops, iops, AddrMode2, Size4Bytes, IndexModeNone, f, opc,
466 class AI3<bits<4> opcod, dag oops, dag iops, Format f, string opc,
467 string asm, list<dag> pattern>
468 : I<opcod, oops, iops, AddrMode3, Size4Bytes, IndexModeNone, f, opc,
470 class AI4<bits<4> opcod, dag oops, dag iops, Format f, string opc,
471 string asm, list<dag> pattern>
472 : I<opcod, oops, iops, AddrMode4, Size4Bytes, IndexModeNone, f, opc,
474 class AI1x2<bits<4> opcod, dag oops, dag iops, Format f, string opc,
475 string asm, list<dag> pattern>
476 : I<opcod, oops, iops, AddrMode1, Size8Bytes, IndexModeNone, f, opc,
480 class AI2pr<bits<4> opcod, dag oops, dag iops, Format f, string opc,
481 string asm, string cstr, list<dag> pattern>
482 : I<opcod, oops, iops, AddrMode2, Size4Bytes, IndexModePre, f, opc,
484 class AI3pr<bits<4> opcod, dag oops, dag iops, Format f, string opc,
485 string asm, string cstr, list<dag> pattern>
486 : I<opcod, oops, iops, AddrMode3, Size4Bytes, IndexModePre, f, opc,
490 class AI2po<bits<4> opcod, dag oops, dag iops, Format f, string opc,
491 string asm, string cstr, list<dag> pattern>
492 : I<opcod, oops, iops, AddrMode2, Size4Bytes, IndexModePost, f, opc,
494 class AI3po<bits<4> opcod, dag oops, dag iops, Format f, string opc,
495 string asm, string cstr, list<dag> pattern>
496 : I<opcod, oops, iops, AddrMode3, Size4Bytes, IndexModePost, f, opc,
500 class BinOpFrag<dag res> : PatFrag<(ops node:$LHS, node:$RHS), res>;
501 class UnOpFrag <dag res> : PatFrag<(ops node:$Src), res>;
504 /// AI1_bin_irs - Defines a set of (op r, {so_imm|r|so_reg}) patterns for a
505 /// binop that produces a value.
506 multiclass AsI1_bin_irs<bits<4> opcod, string opc, PatFrag opnode> {
507 def ri : AsI1<opcod, (outs GPR:$dst), (ins GPR:$a, so_imm:$b), DPRIm,
508 opc, " $dst, $a, $b",
509 [(set GPR:$dst, (opnode GPR:$a, so_imm:$b))]>;
510 def rr : AsI1<opcod, (outs GPR:$dst), (ins GPR:$a, GPR:$b), DPRReg,
511 opc, " $dst, $a, $b",
512 [(set GPR:$dst, (opnode GPR:$a, GPR:$b))]>;
513 def rs : AsI1<opcod, (outs GPR:$dst), (ins GPR:$a, so_reg:$b), DPRSoReg,
514 opc, " $dst, $a, $b",
515 [(set GPR:$dst, (opnode GPR:$a, so_reg:$b))]>;
518 /// ASI1_bin_s_irs - Similar to AsI1_bin_irs except it sets the 's' bit so the
519 /// instruction modifies the CSPR register.
520 let Defs = [CPSR] in {
521 multiclass ASI1_bin_s_irs<bits<4> opcod, string opc, PatFrag opnode> {
522 def ri : AI1<opcod, (outs GPR:$dst), (ins GPR:$a, so_imm:$b), DPRImS,
523 opc, "s $dst, $a, $b",
524 [(set GPR:$dst, (opnode GPR:$a, so_imm:$b))]>;
525 def rr : AI1<opcod, (outs GPR:$dst), (ins GPR:$a, GPR:$b), DPRRegS,
526 opc, "s $dst, $a, $b",
527 [(set GPR:$dst, (opnode GPR:$a, GPR:$b))]>;
528 def rs : AI1<opcod, (outs GPR:$dst), (ins GPR:$a, so_reg:$b), DPRSoRegS,
529 opc, "s $dst, $a, $b",
530 [(set GPR:$dst, (opnode GPR:$a, so_reg:$b))]>;
534 /// AI1_cmp_irs - Defines a set of (op r, {so_imm|r|so_reg}) cmp / test
535 /// patterns. Similar to AsI1_bin_irs except the instruction does not produce
536 /// a explicit result, only implicitly set CPSR.
537 let Defs = [CPSR] in {
538 multiclass AI1_cmp_irs<bits<4> opcod, string opc, PatFrag opnode> {
539 def ri : AI1<opcod, (outs), (ins GPR:$a, so_imm:$b), DPRnIm,
541 [(opnode GPR:$a, so_imm:$b)]>;
542 def rr : AI1<opcod, (outs), (ins GPR:$a, GPR:$b), DPRnReg,
544 [(opnode GPR:$a, GPR:$b)]>;
545 def rs : AI1<opcod, (outs), (ins GPR:$a, so_reg:$b), DPRnSoReg,
547 [(opnode GPR:$a, so_reg:$b)]>;
551 /// AI_unary_rrot - A unary operation with two forms: one whose operand is a
552 /// register and one whose operand is a register rotated by 8/16/24.
553 multiclass AI_unary_rrot<bits<4> opcod, string opc, PatFrag opnode> {
554 def r : AI<opcod, (outs GPR:$dst), (ins GPR:$Src), Pseudo,
556 [(set GPR:$dst, (opnode GPR:$Src))]>, Requires<[IsARM, HasV6]>;
557 def r_rot : AI<opcod, (outs GPR:$dst), (ins GPR:$Src, i32imm:$rot), Pseudo,
558 opc, " $dst, $Src, ror $rot",
559 [(set GPR:$dst, (opnode (rotr GPR:$Src, rot_imm:$rot)))]>,
560 Requires<[IsARM, HasV6]>;
563 /// AI_bin_rrot - A binary operation with two forms: one whose operand is a
564 /// register and one whose operand is a register rotated by 8/16/24.
565 multiclass AI_bin_rrot<bits<4> opcod, string opc, PatFrag opnode> {
566 def rr : AI<opcod, (outs GPR:$dst), (ins GPR:$LHS, GPR:$RHS),
567 Pseudo, opc, " $dst, $LHS, $RHS",
568 [(set GPR:$dst, (opnode GPR:$LHS, GPR:$RHS))]>,
569 Requires<[IsARM, HasV6]>;
570 def rr_rot : AI<opcod, (outs GPR:$dst), (ins GPR:$LHS, GPR:$RHS, i32imm:$rot),
571 Pseudo, opc, " $dst, $LHS, $RHS, ror $rot",
572 [(set GPR:$dst, (opnode GPR:$LHS,
573 (rotr GPR:$RHS, rot_imm:$rot)))]>,
574 Requires<[IsARM, HasV6]>;
578 class XI<bits<4> opcod, dag oops, dag iops, AddrMode am, SizeFlagVal sz,
579 IndexMode im, Format f, string asm, string cstr, list<dag> pattern>
580 : InstARM<opcod, am, sz, im, f, cstr> {
581 let OutOperandList = oops;
582 let InOperandList = iops;
584 let Pattern = pattern;
585 list<Predicate> Predicates = [IsARM];
588 class AXI<bits<4> opcod, dag oops, dag iops, Format f, string asm,
590 : XI<opcod, oops, iops, AddrModeNone, Size4Bytes, IndexModeNone, f, asm,
592 class AXI1<bits<4> opcod, dag oops, dag iops, Format f, string asm,
594 : XI<opcod, oops, iops, AddrMode1, Size4Bytes, IndexModeNone, f, asm,
596 class AXI2<bits<4> opcod, dag oops, dag iops, Format f, string asm,
598 : XI<opcod, oops, iops, AddrMode2, Size4Bytes, IndexModeNone, f, asm,
600 class AXI3<bits<4> opcod, dag oops, dag iops, Format f, string asm,
602 : XI<opcod, oops, iops, AddrMode3, Size4Bytes, IndexModeNone, f, asm,
604 class AXI4<bits<4> opcod, dag oops, dag iops, Format f, string asm,
606 : XI<opcod, oops, iops, AddrMode4, Size4Bytes, IndexModeNone, f, asm,
609 class AXIx2<bits<4> opcod, dag oops, dag iops, Format f, string asm,
611 : XI<opcod, oops, iops, AddrModeNone, Size8Bytes, IndexModeNone, f, asm,
614 // BR_JT instructions
615 class JTI<bits<4> opcod, dag oops, dag iops, string asm, list<dag> pattern>
616 : XI<opcod, oops, iops, AddrModeNone, SizeSpecial, IndexModeNone, BranchMisc,
618 class JTI1<bits<4> opcod, dag oops, dag iops, string asm, list<dag> pattern>
619 : XI<opcod, oops, iops, AddrMode1, SizeSpecial, IndexModeNone, BranchMisc,
621 class JTI2<bits<4> opcod, dag oops, dag iops, string asm, list<dag> pattern>
622 : XI<opcod, oops, iops, AddrMode2, SizeSpecial, IndexModeNone, BranchMisc,
625 /// AsXI1_bin_c_irs - Same as AsI1_bin_irs but without the predicate operand and
626 /// setting carry bit. But it can optionally set CPSR.
627 let Uses = [CPSR] in {
628 multiclass AsXI1_bin_c_irs<bits<4> opcod, string opc, PatFrag opnode> {
629 def ri : AXI1<opcod, (outs GPR:$dst), (ins GPR:$a, so_imm:$b, cc_out:$s),
630 DPRIm, !strconcat(opc, "${s} $dst, $a, $b"),
631 [(set GPR:$dst, (opnode GPR:$a, so_imm:$b))]>;
632 def rr : AXI1<opcod, (outs GPR:$dst), (ins GPR:$a, GPR:$b, cc_out:$s),
633 DPRReg, !strconcat(opc, "${s} $dst, $a, $b"),
634 [(set GPR:$dst, (opnode GPR:$a, GPR:$b))]>;
635 def rs : AXI1<opcod, (outs GPR:$dst), (ins GPR:$a, so_reg:$b, cc_out:$s),
636 DPRSoReg, !strconcat(opc, "${s} $dst, $a, $b"),
637 [(set GPR:$dst, (opnode GPR:$a, so_reg:$b))]>;
641 //===----------------------------------------------------------------------===//
643 //===----------------------------------------------------------------------===//
645 //===----------------------------------------------------------------------===//
646 // Miscellaneous Instructions.
648 let isImplicitDef = 1 in
649 def IMPLICIT_DEF_GPR :
650 PseudoInst<(outs GPR:$rD), (ins pred:$p),
651 "@ IMPLICIT_DEF_GPR $rD",
652 [(set GPR:$rD, (undef))]>;
655 /// CONSTPOOL_ENTRY - This instruction represents a floating constant pool in
656 /// the function. The first operand is the ID# for this instruction, the second
657 /// is the index into the MachineConstantPool that this is, the third is the
658 /// size in bytes of this constant pool entry.
659 let isNotDuplicable = 1 in
660 def CONSTPOOL_ENTRY :
661 PseudoInst<(outs), (ins cpinst_operand:$instid, cpinst_operand:$cpidx,
663 "${instid:label} ${cpidx:cpentry}", []>;
665 let Defs = [SP], Uses = [SP] in {
667 PseudoInst<(outs), (ins i32imm:$amt1, i32imm:$amt2, pred:$p),
668 "@ ADJCALLSTACKUP $amt1",
669 [(ARMcallseq_end imm:$amt1, imm:$amt2)]>;
671 def ADJCALLSTACKDOWN :
672 PseudoInst<(outs), (ins i32imm:$amt, pred:$p),
673 "@ ADJCALLSTACKDOWN $amt",
674 [(ARMcallseq_start imm:$amt)]>;
678 PseudoInst<(outs), (ins i32imm:$line, i32imm:$col, i32imm:$file),
679 ".loc $file, $line, $col",
680 [(dwarf_loc (i32 imm:$line), (i32 imm:$col), (i32 imm:$file))]>;
682 let isNotDuplicable = 1 in {
683 def PICADD : AXI1<0x0, (outs GPR:$dst), (ins GPR:$a, pclabel:$cp, pred:$p),
684 Pseudo, "$cp:\n\tadd$p $dst, pc, $a",
685 [(set GPR:$dst, (ARMpic_add GPR:$a, imm:$cp))]>;
687 let isSimpleLoad = 1, AddedComplexity = 10 in {
688 def PICLD : AXI2<0x0, (outs GPR:$dst), (ins addrmodepc:$addr, pred:$p),
689 Pseudo, "${addr:label}:\n\tldr$p $dst, $addr",
690 [(set GPR:$dst, (load addrmodepc:$addr))]>;
692 def PICLDZH : AXI3<0x0, (outs GPR:$dst), (ins addrmodepc:$addr, pred:$p),
693 Pseudo, "${addr:label}:\n\tldr${p}h $dst, $addr",
694 [(set GPR:$dst, (zextloadi16 addrmodepc:$addr))]>;
696 def PICLDZB : AXI2<0x0, (outs GPR:$dst), (ins addrmodepc:$addr, pred:$p),
697 Pseudo, "${addr:label}:\n\tldr${p}b $dst, $addr",
698 [(set GPR:$dst, (zextloadi8 addrmodepc:$addr))]>;
700 def PICLDH : AXI3<0x0, (outs GPR:$dst), (ins addrmodepc:$addr, pred:$p),
701 Pseudo, "${addr:label}:\n\tldr${p}h $dst, $addr",
702 [(set GPR:$dst, (extloadi16 addrmodepc:$addr))]>;
704 def PICLDB : AXI2<0x0, (outs GPR:$dst), (ins addrmodepc:$addr, pred:$p),
705 Pseudo, "${addr:label}:\n\tldr${p}b $dst, $addr",
706 [(set GPR:$dst, (extloadi8 addrmodepc:$addr))]>;
708 def PICLDSH : AXI3<0x0, (outs GPR:$dst), (ins addrmodepc:$addr, pred:$p),
709 Pseudo, "${addr:label}:\n\tldr${p}sh $dst, $addr",
710 [(set GPR:$dst, (sextloadi16 addrmodepc:$addr))]>;
712 def PICLDSB : AXI3<0x0, (outs GPR:$dst), (ins addrmodepc:$addr, pred:$p),
713 Pseudo, "${addr:label}:\n\tldr${p}sb $dst, $addr",
714 [(set GPR:$dst, (sextloadi8 addrmodepc:$addr))]>;
716 let AddedComplexity = 10 in {
717 def PICSTR : AXI2<0x0, (outs), (ins GPR:$src, addrmodepc:$addr, pred:$p),
718 Pseudo, "${addr:label}:\n\tstr$p $src, $addr",
719 [(store GPR:$src, addrmodepc:$addr)]>;
721 def PICSTRH : AXI3<0x0, (outs), (ins GPR:$src, addrmodepc:$addr, pred:$p),
722 Pseudo, "${addr:label}:\n\tstr${p}h $src, $addr",
723 [(truncstorei16 GPR:$src, addrmodepc:$addr)]>;
725 def PICSTRB : AXI2<0x0, (outs), (ins GPR:$src, addrmodepc:$addr, pred:$p),
726 Pseudo, "${addr:label}:\n\tstr${p}b $src, $addr",
727 [(truncstorei8 GPR:$src, addrmodepc:$addr)]>;
731 //===----------------------------------------------------------------------===//
732 // Control Flow Instructions.
735 let isReturn = 1, isTerminator = 1 in
736 def BX_RET : AI<0x1, (outs), (ins), BranchMisc, "bx", " lr", [(ARMretflag)]>;
738 // FIXME: remove when we have a way to marking a MI with these properties.
739 // FIXME: $dst1 should be a def. But the extra ops must be in the end of the
741 let isSimpleLoad = 1, isReturn = 1, isTerminator = 1 in
742 def LDM_RET : AXI4<0x0, (outs),
743 (ins addrmode4:$addr, pred:$p, reglist:$dst1, variable_ops),
744 LdFrm, "ldm${p}${addr:submode} $addr, $dst1",
748 Defs = [R0, R1, R2, R3, R12, LR,
749 D0, D1, D2, D3, D4, D5, D6, D7, CPSR] in {
750 def BL : AXI<0xB, (outs), (ins i32imm:$func, variable_ops), Branch,
752 [(ARMcall tglobaladdr:$func)]>;
754 def BL_pred : AI<0xB, (outs), (ins i32imm:$func, variable_ops),
755 Branch, "bl", " ${func:call}",
756 [(ARMcall_pred tglobaladdr:$func)]>;
759 def BLX : AXI<0x2, (outs), (ins GPR:$func, variable_ops), BranchMisc,
761 [(ARMcall GPR:$func)]>, Requires<[IsARM, HasV5T]>;
764 def BX : AXIx2<0x0, (outs), (ins GPR:$func, variable_ops),
765 BranchMisc, "mov lr, pc\n\tbx $func",
766 [(ARMcall_nolink GPR:$func)]>;
770 let isBranch = 1, isTerminator = 1 in {
771 // B is "predicable" since it can be xformed into a Bcc.
772 let isBarrier = 1 in {
773 let isPredicable = 1 in
774 def B : AXI<0xA, (outs), (ins brtarget:$target), Branch, "b $target",
777 let isNotDuplicable = 1, isIndirectBranch = 1 in {
778 def BR_JTr : JTI<0x0, (outs), (ins GPR:$target, jtblock_operand:$jt, i32imm:$id),
779 "mov pc, $target \n$jt",
780 [(ARMbrjt GPR:$target, tjumptable:$jt, imm:$id)]>;
781 def BR_JTm : JTI2<0x0, (outs), (ins addrmode2:$target, jtblock_operand:$jt, i32imm:$id),
782 "ldr pc, $target \n$jt",
783 [(ARMbrjt (i32 (load addrmode2:$target)), tjumptable:$jt,
785 def BR_JTadd : JTI1<0x0, (outs), (ins GPR:$target, GPR:$idx, jtblock_operand:$jt,
787 "add pc, $target, $idx \n$jt",
788 [(ARMbrjt (add GPR:$target, GPR:$idx), tjumptable:$jt,
793 // FIXME: should be able to write a pattern for ARMBrcond, but can't use
794 // a two-value operand where a dag node expects two operands. :(
795 def Bcc : AI<0xA, (outs), (ins brtarget:$target), Branch,
797 [/*(ARMbrcond bb:$target, imm:$cc, CCR:$ccr)*/]>;
800 //===----------------------------------------------------------------------===//
801 // Load / store Instructions.
805 let isSimpleLoad = 1 in {
806 def LDR : AI2<0x0, (outs GPR:$dst), (ins addrmode2:$addr), LdFrm,
807 "ldr", " $dst, $addr",
808 [(set GPR:$dst, (load addrmode2:$addr))]>;
810 // Special LDR for loads from non-pc-relative constpools.
811 let isReMaterializable = 1 in
812 def LDRcp : AI2<0x0, (outs GPR:$dst), (ins addrmode2:$addr), LdFrm,
813 "ldr", " $dst, $addr", []>;
815 // Loads with zero extension
816 def LDRH : AI3<0xB, (outs GPR:$dst), (ins addrmode3:$addr), LdFrm,
817 "ldr", "h $dst, $addr",
818 [(set GPR:$dst, (zextloadi16 addrmode3:$addr))]>;
820 def LDRB : AI2<0x1, (outs GPR:$dst), (ins addrmode2:$addr), LdFrm,
821 "ldr", "b $dst, $addr",
822 [(set GPR:$dst, (zextloadi8 addrmode2:$addr))]>;
824 // Loads with sign extension
825 def LDRSH : AI3<0xE, (outs GPR:$dst), (ins addrmode3:$addr), LdFrm,
826 "ldr", "sh $dst, $addr",
827 [(set GPR:$dst, (sextloadi16 addrmode3:$addr))]>;
829 def LDRSB : AI3<0xD, (outs GPR:$dst), (ins addrmode3:$addr), LdFrm,
830 "ldr", "sb $dst, $addr",
831 [(set GPR:$dst, (sextloadi8 addrmode3:$addr))]>;
834 def LDRD : AI3<0xD, (outs GPR:$dst), (ins addrmode3:$addr), LdFrm,
835 "ldr", "d $dst, $addr",
836 []>, Requires<[IsARM, HasV5T]>;
839 def LDR_PRE : AI2pr<0x0, (outs GPR:$dst, GPR:$base_wb),
840 (ins addrmode2:$addr), LdFrm,
841 "ldr", " $dst, $addr!", "$addr.base = $base_wb", []>;
843 def LDR_POST : AI2po<0x0, (outs GPR:$dst, GPR:$base_wb),
844 (ins GPR:$base, am2offset:$offset), LdFrm,
845 "ldr", " $dst, [$base], $offset", "$base = $base_wb", []>;
847 def LDRH_PRE : AI3pr<0xB, (outs GPR:$dst, GPR:$base_wb),
848 (ins addrmode3:$addr), LdFrm,
849 "ldr", "h $dst, $addr!", "$addr.base = $base_wb", []>;
851 def LDRH_POST : AI3po<0xB, (outs GPR:$dst, GPR:$base_wb),
852 (ins GPR:$base,am3offset:$offset), LdFrm,
853 "ldr", "h $dst, [$base], $offset", "$base = $base_wb", []>;
855 def LDRB_PRE : AI2pr<0x1, (outs GPR:$dst, GPR:$base_wb),
856 (ins addrmode2:$addr), LdFrm,
857 "ldr", "b $dst, $addr!", "$addr.base = $base_wb", []>;
859 def LDRB_POST : AI2po<0x1, (outs GPR:$dst, GPR:$base_wb),
860 (ins GPR:$base,am2offset:$offset), LdFrm,
861 "ldr", "b $dst, [$base], $offset", "$base = $base_wb", []>;
863 def LDRSH_PRE : AI3pr<0xE, (outs GPR:$dst, GPR:$base_wb),
864 (ins addrmode3:$addr), LdFrm,
865 "ldr", "sh $dst, $addr!", "$addr.base = $base_wb", []>;
867 def LDRSH_POST: AI3po<0xE, (outs GPR:$dst, GPR:$base_wb),
868 (ins GPR:$base,am3offset:$offset), LdFrm,
869 "ldr", "sh $dst, [$base], $offset", "$base = $base_wb", []>;
871 def LDRSB_PRE : AI3pr<0xD, (outs GPR:$dst, GPR:$base_wb),
872 (ins addrmode3:$addr), LdFrm,
873 "ldr", "sb $dst, $addr!", "$addr.base = $base_wb", []>;
875 def LDRSB_POST: AI3po<0xD, (outs GPR:$dst, GPR:$base_wb),
876 (ins GPR:$base,am3offset:$offset), LdFrm,
877 "ldr", "sb $dst, [$base], $offset", "$base = $base_wb", []>;
881 def STR : AI2<0x0, (outs), (ins GPR:$src, addrmode2:$addr), StFrm,
882 "str", " $src, $addr",
883 [(store GPR:$src, addrmode2:$addr)]>;
885 // Stores with truncate
886 def STRH : AI3<0xB, (outs), (ins GPR:$src, addrmode3:$addr), StFrm,
887 "str", "h $src, $addr",
888 [(truncstorei16 GPR:$src, addrmode3:$addr)]>;
890 def STRB : AI2<0x1, (outs), (ins GPR:$src, addrmode2:$addr), StFrm,
891 "str", "b $src, $addr",
892 [(truncstorei8 GPR:$src, addrmode2:$addr)]>;
896 def STRD : AI3<0xF, (outs), (ins GPR:$src, addrmode3:$addr), StFrm,
897 "str", "d $src, $addr",
898 []>, Requires<[IsARM, HasV5T]>;
901 def STR_PRE : AI2pr<0x0, (outs GPR:$base_wb),
902 (ins GPR:$src, GPR:$base, am2offset:$offset), StFrm,
903 "str", " $src, [$base, $offset]!", "$base = $base_wb",
905 (pre_store GPR:$src, GPR:$base, am2offset:$offset))]>;
907 def STR_POST : AI2po<0x0, (outs GPR:$base_wb),
908 (ins GPR:$src, GPR:$base,am2offset:$offset), StFrm,
909 "str", " $src, [$base], $offset", "$base = $base_wb",
911 (post_store GPR:$src, GPR:$base, am2offset:$offset))]>;
913 def STRH_PRE : AI3pr<0xB, (outs GPR:$base_wb),
914 (ins GPR:$src, GPR:$base,am3offset:$offset), StFrm,
915 "str", "h $src, [$base, $offset]!", "$base = $base_wb",
917 (pre_truncsti16 GPR:$src, GPR:$base,am3offset:$offset))]>;
919 def STRH_POST: AI3po<0xB, (outs GPR:$base_wb),
920 (ins GPR:$src, GPR:$base,am3offset:$offset), StFrm,
921 "str", "h $src, [$base], $offset", "$base = $base_wb",
922 [(set GPR:$base_wb, (post_truncsti16 GPR:$src,
923 GPR:$base, am3offset:$offset))]>;
925 def STRB_PRE : AI2pr<0x1, (outs GPR:$base_wb),
926 (ins GPR:$src, GPR:$base,am2offset:$offset), StFrm,
927 "str", "b $src, [$base, $offset]!", "$base = $base_wb",
928 [(set GPR:$base_wb, (pre_truncsti8 GPR:$src,
929 GPR:$base, am2offset:$offset))]>;
931 def STRB_POST: AI2po<0x1, (outs GPR:$base_wb),
932 (ins GPR:$src, GPR:$base,am2offset:$offset), StFrm,
933 "str", "b $src, [$base], $offset", "$base = $base_wb",
934 [(set GPR:$base_wb, (post_truncsti8 GPR:$src,
935 GPR:$base, am2offset:$offset))]>;
937 //===----------------------------------------------------------------------===//
938 // Load / store multiple Instructions.
941 // FIXME: $dst1 should be a def.
942 let isSimpleLoad = 1 in
943 def LDM : AXI4<0x0, (outs),
944 (ins addrmode4:$addr, pred:$p, reglist:$dst1, variable_ops),
945 LdFrm, "ldm${p}${addr:submode} $addr, $dst1",
949 def STM : AXI4<0x0, (outs),
950 (ins addrmode4:$addr, pred:$p, reglist:$src1, variable_ops),
951 StFrm, "stm${p}${addr:submode} $addr, $src1",
954 //===----------------------------------------------------------------------===//
955 // Move Instructions.
958 def MOVr : AsI1<0xD, (outs GPR:$dst), (ins GPR:$src), DPRdReg,
959 "mov", " $dst, $src", []>;
960 def MOVs : AsI1<0xD, (outs GPR:$dst), (ins so_reg:$src), DPRdSoReg,
961 "mov", " $dst, $src", [(set GPR:$dst, so_reg:$src)]>;
963 let isReMaterializable = 1 in
964 def MOVi : AsI1<0xD, (outs GPR:$dst), (ins so_imm:$src), DPRdIm,
965 "mov", " $dst, $src", [(set GPR:$dst, so_imm:$src)]>;
967 def MOVrx : AsI1<0xD, (outs GPR:$dst), (ins GPR:$src), DPRdMisc,
968 "mov", " $dst, $src, rrx",
969 [(set GPR:$dst, (ARMrrx GPR:$src))]>;
971 // These aren't really mov instructions, but we have to define them this way
972 // due to flag operands.
974 let Defs = [CPSR] in {
975 def MOVsrl_flag : AI1<0xD, (outs GPR:$dst), (ins GPR:$src), DPRdMisc,
976 "mov", "s $dst, $src, lsr #1",
977 [(set GPR:$dst, (ARMsrl_flag GPR:$src))]>;
978 def MOVsra_flag : AI1<0xD, (outs GPR:$dst), (ins GPR:$src), DPRdMisc,
979 "mov", "s $dst, $src, asr #1",
980 [(set GPR:$dst, (ARMsra_flag GPR:$src))]>;
983 //===----------------------------------------------------------------------===//
984 // Extend Instructions.
989 defm SXTB : AI_unary_rrot<0x0, "sxtb", UnOpFrag<(sext_inreg node:$Src, i8)>>;
990 defm SXTH : AI_unary_rrot<0x0, "sxth", UnOpFrag<(sext_inreg node:$Src, i16)>>;
992 defm SXTAB : AI_bin_rrot<0x0, "sxtab",
993 BinOpFrag<(add node:$LHS, (sext_inreg node:$RHS, i8))>>;
994 defm SXTAH : AI_bin_rrot<0x0, "sxtah",
995 BinOpFrag<(add node:$LHS, (sext_inreg node:$RHS,i16))>>;
997 // TODO: SXT(A){B|H}16
1001 let AddedComplexity = 16 in {
1002 defm UXTB : AI_unary_rrot<0x0, "uxtb" , UnOpFrag<(and node:$Src, 0x000000FF)>>;
1003 defm UXTH : AI_unary_rrot<0x0, "uxth" , UnOpFrag<(and node:$Src, 0x0000FFFF)>>;
1004 defm UXTB16 : AI_unary_rrot<0x0, "uxtb16", UnOpFrag<(and node:$Src, 0x00FF00FF)>>;
1006 def : ARMV6Pat<(and (shl GPR:$Src, 8), 0xFF00FF),
1007 (UXTB16r_rot GPR:$Src, 24)>;
1008 def : ARMV6Pat<(and (srl GPR:$Src, 8), 0xFF00FF),
1009 (UXTB16r_rot GPR:$Src, 8)>;
1011 defm UXTAB : AI_bin_rrot<0x0, "uxtab",
1012 BinOpFrag<(add node:$LHS, (and node:$RHS, 0x00FF))>>;
1013 defm UXTAH : AI_bin_rrot<0x0, "uxtah",
1014 BinOpFrag<(add node:$LHS, (and node:$RHS, 0xFFFF))>>;
1017 // This isn't safe in general, the add is two 16-bit units, not a 32-bit add.
1018 //defm UXTAB16 : xxx<"uxtab16", 0xff00ff>;
1020 // TODO: UXT(A){B|H}16
1022 //===----------------------------------------------------------------------===//
1023 // Arithmetic Instructions.
1026 defm ADD : AsI1_bin_irs<0x4, "add", BinOpFrag<(add node:$LHS, node:$RHS)>>;
1027 defm SUB : AsI1_bin_irs<0x2, "sub", BinOpFrag<(sub node:$LHS, node:$RHS)>>;
1029 // ADD and SUB with 's' bit set.
1030 defm ADDS : ASI1_bin_s_irs<0x4, "add", BinOpFrag<(addc node:$LHS, node:$RHS)>>;
1031 defm SUBS : ASI1_bin_s_irs<0x2, "sub", BinOpFrag<(subc node:$LHS, node:$RHS)>>;
1033 // FIXME: Do not allow ADC / SBC to be predicated for now.
1034 defm ADC : AsXI1_bin_c_irs<0x5, "adc", BinOpFrag<(adde node:$LHS, node:$RHS)>>;
1035 defm SBC : AsXI1_bin_c_irs<0x6, "sbc", BinOpFrag<(sube node:$LHS, node:$RHS)>>;
1037 // These don't define reg/reg forms, because they are handled above.
1038 def RSBri : AsI1<0x3, (outs GPR:$dst), (ins GPR:$a, so_imm:$b), DPRIm,
1039 "rsb", " $dst, $a, $b",
1040 [(set GPR:$dst, (sub so_imm:$b, GPR:$a))]>;
1042 def RSBrs : AsI1<0x3, (outs GPR:$dst), (ins GPR:$a, so_reg:$b), DPRSoReg,
1043 "rsb", " $dst, $a, $b",
1044 [(set GPR:$dst, (sub so_reg:$b, GPR:$a))]>;
1046 // RSB with 's' bit set.
1047 let Defs = [CPSR] in {
1048 def RSBSri : AI1<0x3, (outs GPR:$dst), (ins GPR:$a, so_imm:$b), DPRIm,
1049 "rsb", "s $dst, $a, $b",
1050 [(set GPR:$dst, (subc so_imm:$b, GPR:$a))]>;
1051 def RSBSrs : AI1<0x3, (outs GPR:$dst), (ins GPR:$a, so_reg:$b), DPRSoReg,
1052 "rsb", "s $dst, $a, $b",
1053 [(set GPR:$dst, (subc so_reg:$b, GPR:$a))]>;
1056 // FIXME: Do not allow RSC to be predicated for now. But they can set CPSR.
1057 let Uses = [CPSR] in {
1058 def RSCri : AXI1<0x7, (outs GPR:$dst), (ins GPR:$a, so_imm:$b, cc_out:$s),
1059 DPRIm, "rsc${s} $dst, $a, $b",
1060 [(set GPR:$dst, (sube so_imm:$b, GPR:$a))]>;
1061 def RSCrs : AXI1<0x7, (outs GPR:$dst), (ins GPR:$a, so_reg:$b, cc_out:$s),
1062 DPRSoReg, "rsc${s} $dst, $a, $b",
1063 [(set GPR:$dst, (sube so_reg:$b, GPR:$a))]>;
1066 // (sub X, imm) gets canonicalized to (add X, -imm). Match this form.
1067 def : ARMPat<(add GPR:$src, so_imm_neg:$imm),
1068 (SUBri GPR:$src, so_imm_neg:$imm)>;
1070 //def : ARMPat<(addc GPR:$src, so_imm_neg:$imm),
1071 // (SUBSri GPR:$src, so_imm_neg:$imm)>;
1072 //def : ARMPat<(adde GPR:$src, so_imm_neg:$imm),
1073 // (SBCri GPR:$src, so_imm_neg:$imm)>;
1075 // Note: These are implemented in C++ code, because they have to generate
1076 // ADD/SUBrs instructions, which use a complex pattern that a xform function
1078 // (mul X, 2^n+1) -> (add (X << n), X)
1079 // (mul X, 2^n-1) -> (rsb X, (X << n))
1082 //===----------------------------------------------------------------------===//
1083 // Bitwise Instructions.
1086 defm AND : AsI1_bin_irs<0x0, "and", BinOpFrag<(and node:$LHS, node:$RHS)>>;
1087 defm ORR : AsI1_bin_irs<0xC, "orr", BinOpFrag<(or node:$LHS, node:$RHS)>>;
1088 defm EOR : AsI1_bin_irs<0x1, "eor", BinOpFrag<(xor node:$LHS, node:$RHS)>>;
1089 defm BIC : AsI1_bin_irs<0xE, "bic", BinOpFrag<(and node:$LHS, (not node:$RHS))>>;
1091 def MVNr : AsI<0xE, (outs GPR:$dst), (ins GPR:$src), DPRdReg,
1092 "mvn", " $dst, $src", [(set GPR:$dst, (not GPR:$src))]>;
1093 def MVNs : AsI<0xE, (outs GPR:$dst), (ins so_reg:$src), DPRdSoReg,
1094 "mvn", " $dst, $src", [(set GPR:$dst, (not so_reg:$src))]>;
1095 let isReMaterializable = 1 in
1096 def MVNi : AsI<0xE, (outs GPR:$dst), (ins so_imm:$imm), DPRdIm,
1097 "mvn", " $dst, $imm", [(set GPR:$dst, so_imm_not:$imm)]>;
1099 def : ARMPat<(and GPR:$src, so_imm_not:$imm),
1100 (BICri GPR:$src, so_imm_not:$imm)>;
1102 //===----------------------------------------------------------------------===//
1103 // Multiply Instructions.
1106 def MUL : AsI<0x0, (outs GPR:$dst), (ins GPR:$a, GPR:$b), MulFrm,
1107 "mul", " $dst, $a, $b",
1108 [(set GPR:$dst, (mul GPR:$a, GPR:$b))]>;
1110 def MLA : AsI<0x2, (outs GPR:$dst), (ins GPR:$a, GPR:$b, GPR:$c),
1111 MulFrm, "mla", " $dst, $a, $b, $c",
1112 [(set GPR:$dst, (add (mul GPR:$a, GPR:$b), GPR:$c))]>;
1114 // Extra precision multiplies with low / high results
1115 def SMULL : AsI<0xC, (outs GPR:$ldst, GPR:$hdst), (ins GPR:$a, GPR:$b),
1116 MulFrm, "smull", " $ldst, $hdst, $a, $b", []>;
1118 def UMULL : AsI<0x8, (outs GPR:$ldst, GPR:$hdst), (ins GPR:$a, GPR:$b),
1119 MulFrm, "umull", " $ldst, $hdst, $a, $b", []>;
1121 // Multiply + accumulate
1122 def SMLAL : AsI<0xE, (outs GPR:$ldst, GPR:$hdst), (ins GPR:$a, GPR:$b),
1123 MulFrm, "smlal", " $ldst, $hdst, $a, $b", []>;
1125 def UMLAL : AsI<0xA, (outs GPR:$ldst, GPR:$hdst), (ins GPR:$a, GPR:$b),
1126 MulFrm, "umlal", " $ldst, $hdst, $a, $b", []>;
1128 def UMAAL : AI<0x0, (outs GPR:$ldst, GPR:$hdst), (ins GPR:$a, GPR:$b), MulFrm,
1129 "umaal", " $ldst, $hdst, $a, $b", []>,
1130 Requires<[IsARM, HasV6]>;
1132 // Most significant word multiply
1133 def SMMUL : AI<0x0, (outs GPR:$dst), (ins GPR:$a, GPR:$b), MulFrm,
1134 "smmul", " $dst, $a, $b",
1135 [(set GPR:$dst, (mulhs GPR:$a, GPR:$b))]>,
1136 Requires<[IsARM, HasV6]>;
1138 def SMMLA : AI<0x0, (outs GPR:$dst), (ins GPR:$a, GPR:$b, GPR:$c), MulFrm,
1139 "smmla", " $dst, $a, $b, $c",
1140 [(set GPR:$dst, (add (mulhs GPR:$a, GPR:$b), GPR:$c))]>,
1141 Requires<[IsARM, HasV6]>;
1144 def SMMLS : AI<0x0, (outs GPR:$dst), (ins GPR:$a, GPR:$b, GPR:$c), MulFrm,
1145 "smmls", " $dst, $a, $b, $c",
1146 [(set GPR:$dst, (sub GPR:$c, (mulhs GPR:$a, GPR:$b)))]>,
1147 Requires<[IsARM, HasV6]>;
1149 multiclass AI_smul<string opc, PatFrag opnode> {
1150 def BB : AI<0x8, (outs GPR:$dst), (ins GPR:$a, GPR:$b), MulSMUL,
1151 !strconcat(opc, "bb"), " $dst, $a, $b",
1152 [(set GPR:$dst, (opnode (sext_inreg GPR:$a, i16),
1153 (sext_inreg GPR:$b, i16)))]>,
1154 Requires<[IsARM, HasV5TE]>;
1156 def BT : AI<0xC, (outs GPR:$dst), (ins GPR:$a, GPR:$b), MulSMUL,
1157 !strconcat(opc, "bt"), " $dst, $a, $b",
1158 [(set GPR:$dst, (opnode (sext_inreg GPR:$a, i16),
1159 (sra GPR:$b, 16)))]>,
1160 Requires<[IsARM, HasV5TE]>;
1162 def TB : AI<0xA, (outs GPR:$dst), (ins GPR:$a, GPR:$b), MulSMUL,
1163 !strconcat(opc, "tb"), " $dst, $a, $b",
1164 [(set GPR:$dst, (opnode (sra GPR:$a, 16),
1165 (sext_inreg GPR:$b, i16)))]>,
1166 Requires<[IsARM, HasV5TE]>;
1168 def TT : AI<0xE, (outs GPR:$dst), (ins GPR:$a, GPR:$b), MulSMUL,
1169 !strconcat(opc, "tt"), " $dst, $a, $b",
1170 [(set GPR:$dst, (opnode (sra GPR:$a, 16),
1171 (sra GPR:$b, 16)))]>,
1172 Requires<[IsARM, HasV5TE]>;
1174 def WB : AI<0xA, (outs GPR:$dst), (ins GPR:$a, GPR:$b), MulSMULW,
1175 !strconcat(opc, "wb"), " $dst, $a, $b",
1176 [(set GPR:$dst, (sra (opnode GPR:$a,
1177 (sext_inreg GPR:$b, i16)), 16))]>,
1178 Requires<[IsARM, HasV5TE]>;
1180 def WT : AI<0xE, (outs GPR:$dst), (ins GPR:$a, GPR:$b), MulSMULW,
1181 !strconcat(opc, "wt"), " $dst, $a, $b",
1182 [(set GPR:$dst, (sra (opnode GPR:$a,
1183 (sra GPR:$b, 16)), 16))]>,
1184 Requires<[IsARM, HasV5TE]>;
1188 multiclass AI_smla<string opc, PatFrag opnode> {
1189 def BB : AI<0x8, (outs GPR:$dst), (ins GPR:$a, GPR:$b, GPR:$acc), MulSMLA,
1190 !strconcat(opc, "bb"), " $dst, $a, $b, $acc",
1191 [(set GPR:$dst, (add GPR:$acc,
1192 (opnode (sext_inreg GPR:$a, i16),
1193 (sext_inreg GPR:$b, i16))))]>,
1194 Requires<[IsARM, HasV5TE]>;
1196 def BT : AI<0xC, (outs GPR:$dst), (ins GPR:$a, GPR:$b, GPR:$acc), MulSMLA,
1197 !strconcat(opc, "bt"), " $dst, $a, $b, $acc",
1198 [(set GPR:$dst, (add GPR:$acc, (opnode (sext_inreg GPR:$a, i16),
1199 (sra GPR:$b, 16))))]>,
1200 Requires<[IsARM, HasV5TE]>;
1202 def TB : AI<0xA, (outs GPR:$dst), (ins GPR:$a, GPR:$b, GPR:$acc), MulSMLA,
1203 !strconcat(opc, "tb"), " $dst, $a, $b, $acc",
1204 [(set GPR:$dst, (add GPR:$acc, (opnode (sra GPR:$a, 16),
1205 (sext_inreg GPR:$b, i16))))]>,
1206 Requires<[IsARM, HasV5TE]>;
1208 def TT : AI<0xE, (outs GPR:$dst), (ins GPR:$a, GPR:$b, GPR:$acc), MulSMLA,
1209 !strconcat(opc, "tt"), " $dst, $a, $b, $acc",
1210 [(set GPR:$dst, (add GPR:$acc, (opnode (sra GPR:$a, 16),
1211 (sra GPR:$b, 16))))]>,
1212 Requires<[IsARM, HasV5TE]>;
1214 def WB : AI<0xA, (outs GPR:$dst), (ins GPR:$a, GPR:$b, GPR:$acc), MulSMLAW,
1215 !strconcat(opc, "wb"), " $dst, $a, $b, $acc",
1216 [(set GPR:$dst, (add GPR:$acc, (sra (opnode GPR:$a,
1217 (sext_inreg GPR:$b, i16)), 16)))]>,
1218 Requires<[IsARM, HasV5TE]>;
1220 def WT : AI<0xE, (outs GPR:$dst), (ins GPR:$a, GPR:$b, GPR:$acc), MulSMLAW,
1221 !strconcat(opc, "wt"), " $dst, $a, $b, $acc",
1222 [(set GPR:$dst, (add GPR:$acc, (sra (opnode GPR:$a,
1223 (sra GPR:$b, 16)), 16)))]>,
1224 Requires<[IsARM, HasV5TE]>;
1227 defm SMUL : AI_smul<"smul", BinOpFrag<(mul node:$LHS, node:$RHS)>>;
1228 defm SMLA : AI_smla<"smla", BinOpFrag<(mul node:$LHS, node:$RHS)>>;
1230 // TODO: Halfword multiple accumulate long: SMLAL<x><y>
1231 // TODO: Dual halfword multiple: SMUAD, SMUSD, SMLAD, SMLSD, SMLALD, SMLSLD
1233 //===----------------------------------------------------------------------===//
1234 // Misc. Arithmetic Instructions.
1237 def CLZ : AI<0x0, (outs GPR:$dst), (ins GPR:$src), ArithMisc,
1238 "clz", " $dst, $src",
1239 [(set GPR:$dst, (ctlz GPR:$src))]>, Requires<[IsARM, HasV5T]>;
1241 def REV : AI<0x0, (outs GPR:$dst), (ins GPR:$src), ArithMisc,
1242 "rev", " $dst, $src",
1243 [(set GPR:$dst, (bswap GPR:$src))]>, Requires<[IsARM, HasV6]>;
1245 def REV16 : AI<0x0, (outs GPR:$dst), (ins GPR:$src), ArithMisc,
1246 "rev16", " $dst, $src",
1248 (or (and (srl GPR:$src, 8), 0xFF),
1249 (or (and (shl GPR:$src, 8), 0xFF00),
1250 (or (and (srl GPR:$src, 8), 0xFF0000),
1251 (and (shl GPR:$src, 8), 0xFF000000)))))]>,
1252 Requires<[IsARM, HasV6]>;
1254 def REVSH : AI<0x0, (outs GPR:$dst), (ins GPR:$src), ArithMisc,
1255 "revsh", " $dst, $src",
1258 (or (srl (and GPR:$src, 0xFF00), 8),
1259 (shl GPR:$src, 8)), i16))]>,
1260 Requires<[IsARM, HasV6]>;
1262 def PKHBT : AI<0x0, (outs GPR:$dst), (ins GPR:$src1, GPR:$src2, i32imm:$shamt),
1263 Pseudo, "pkhbt", " $dst, $src1, $src2, LSL $shamt",
1264 [(set GPR:$dst, (or (and GPR:$src1, 0xFFFF),
1265 (and (shl GPR:$src2, (i32 imm:$shamt)),
1267 Requires<[IsARM, HasV6]>;
1269 // Alternate cases for PKHBT where identities eliminate some nodes.
1270 def : ARMV6Pat<(or (and GPR:$src1, 0xFFFF), (and GPR:$src2, 0xFFFF0000)),
1271 (PKHBT GPR:$src1, GPR:$src2, 0)>;
1272 def : ARMV6Pat<(or (and GPR:$src1, 0xFFFF), (shl GPR:$src2, imm16_31:$shamt)),
1273 (PKHBT GPR:$src1, GPR:$src2, imm16_31:$shamt)>;
1276 def PKHTB : AI<0x0, (outs GPR:$dst), (ins GPR:$src1, GPR:$src2, i32imm:$shamt),
1277 Pseudo, "pkhtb", " $dst, $src1, $src2, ASR $shamt",
1278 [(set GPR:$dst, (or (and GPR:$src1, 0xFFFF0000),
1279 (and (sra GPR:$src2, imm16_31:$shamt),
1280 0xFFFF)))]>, Requires<[IsARM, HasV6]>;
1282 // Alternate cases for PKHTB where identities eliminate some nodes. Note that
1283 // a shift amount of 0 is *not legal* here, it is PKHBT instead.
1284 def : ARMV6Pat<(or (and GPR:$src1, 0xFFFF0000), (srl GPR:$src2, 16)),
1285 (PKHTB GPR:$src1, GPR:$src2, 16)>;
1286 def : ARMV6Pat<(or (and GPR:$src1, 0xFFFF0000),
1287 (and (srl GPR:$src2, imm1_15:$shamt), 0xFFFF)),
1288 (PKHTB GPR:$src1, GPR:$src2, imm1_15:$shamt)>;
1291 //===----------------------------------------------------------------------===//
1292 // Comparison Instructions...
1295 defm CMP : AI1_cmp_irs<0xA, "cmp",
1296 BinOpFrag<(ARMcmp node:$LHS, node:$RHS)>>;
1297 defm CMN : AI1_cmp_irs<0xB, "cmn",
1298 BinOpFrag<(ARMcmp node:$LHS,(ineg node:$RHS))>>;
1300 // Note that TST/TEQ don't set all the same flags that CMP does!
1301 defm TST : AI1_cmp_irs<0x8, "tst",
1302 BinOpFrag<(ARMcmpNZ (and node:$LHS, node:$RHS), 0)>>;
1303 defm TEQ : AI1_cmp_irs<0x9, "teq",
1304 BinOpFrag<(ARMcmpNZ (xor node:$LHS, node:$RHS), 0)>>;
1306 defm CMPnz : AI1_cmp_irs<0xA, "cmp",
1307 BinOpFrag<(ARMcmpNZ node:$LHS, node:$RHS)>>;
1308 defm CMNnz : AI1_cmp_irs<0xA, "cmn",
1309 BinOpFrag<(ARMcmpNZ node:$LHS,(ineg node:$RHS))>>;
1311 def : ARMPat<(ARMcmp GPR:$src, so_imm_neg:$imm),
1312 (CMNri GPR:$src, so_imm_neg:$imm)>;
1314 def : ARMPat<(ARMcmpNZ GPR:$src, so_imm_neg:$imm),
1315 (CMNri GPR:$src, so_imm_neg:$imm)>;
1318 // Conditional moves
1319 // FIXME: should be able to write a pattern for ARMcmov, but can't use
1320 // a two-value operand where a dag node expects two operands. :(
1321 def MOVCCr : AI<0xD, (outs GPR:$dst), (ins GPR:$false, GPR:$true),
1322 DPRdReg, "mov", " $dst, $true",
1323 [/*(set GPR:$dst, (ARMcmov GPR:$false, GPR:$true, imm:$cc, CCR:$ccr))*/]>,
1324 RegConstraint<"$false = $dst">;
1326 def MOVCCs : AI<0xD, (outs GPR:$dst), (ins GPR:$false, so_reg:$true),
1327 DPRdSoReg, "mov", " $dst, $true",
1328 [/*(set GPR:$dst, (ARMcmov GPR:$false, so_reg:$true, imm:$cc, CCR:$ccr))*/]>,
1329 RegConstraint<"$false = $dst">;
1331 def MOVCCi : AI<0xD, (outs GPR:$dst), (ins GPR:$false, so_imm:$true),
1332 DPRdIm, "mov", " $dst, $true",
1333 [/*(set GPR:$dst, (ARMcmov GPR:$false, so_imm:$true, imm:$cc, CCR:$ccr))*/]>,
1334 RegConstraint<"$false = $dst">;
1337 // LEApcrel - Load a pc-relative address into a register without offending the
1339 def LEApcrel : AXI1<0x0, (outs GPR:$dst), (ins i32imm:$label, pred:$p), Pseudo,
1340 !strconcat(!strconcat(".set PCRELV${:uid}, ($label-(",
1341 "${:private}PCRELL${:uid}+8))\n"),
1342 !strconcat("${:private}PCRELL${:uid}:\n\t",
1343 "add$p $dst, pc, #PCRELV${:uid}")),
1346 def LEApcrelJT : AXI1<0x0, (outs GPR:$dst), (ins i32imm:$label, i32imm:$id, pred:$p),
1348 !strconcat(!strconcat(".set PCRELV${:uid}, (${label}_${id:no_hash}-(",
1349 "${:private}PCRELL${:uid}+8))\n"),
1350 !strconcat("${:private}PCRELL${:uid}:\n\t",
1351 "add$p $dst, pc, #PCRELV${:uid}")),
1354 //===----------------------------------------------------------------------===//
1358 // __aeabi_read_tp preserves the registers r1-r3.
1360 Defs = [R0, R12, LR, CPSR] in {
1361 def TPsoft : AXI<0x0, (outs), (ins), BranchMisc,
1362 "bl __aeabi_read_tp",
1363 [(set R0, ARMthread_pointer)]>;
1366 //===----------------------------------------------------------------------===//
1367 // Non-Instruction Patterns
1370 // ConstantPool, GlobalAddress, and JumpTable
1371 def : ARMPat<(ARMWrapper tglobaladdr :$dst), (LEApcrel tglobaladdr :$dst)>;
1372 def : ARMPat<(ARMWrapper tconstpool :$dst), (LEApcrel tconstpool :$dst)>;
1373 def : ARMPat<(ARMWrapperJT tjumptable:$dst, imm:$id),
1374 (LEApcrelJT tjumptable:$dst, imm:$id)>;
1376 // Large immediate handling.
1378 // Two piece so_imms.
1379 let isReMaterializable = 1 in
1380 def MOVi2pieces : AI1x2<0x0, (outs GPR:$dst), (ins so_imm2part:$src), DPRdMisc,
1381 "mov", " $dst, $src",
1382 [(set GPR:$dst, so_imm2part:$src)]>;
1384 def : ARMPat<(or GPR:$LHS, so_imm2part:$RHS),
1385 (ORRri (ORRri GPR:$LHS, (so_imm2part_1 imm:$RHS)),
1386 (so_imm2part_2 imm:$RHS))>;
1387 def : ARMPat<(xor GPR:$LHS, so_imm2part:$RHS),
1388 (EORri (EORri GPR:$LHS, (so_imm2part_1 imm:$RHS)),
1389 (so_imm2part_2 imm:$RHS))>;
1391 // TODO: add,sub,and, 3-instr forms?
1395 def : ARMPat<(ARMcall texternalsym:$func), (BL texternalsym:$func)>;
1397 // zextload i1 -> zextload i8
1398 def : ARMPat<(zextloadi1 addrmode2:$addr), (LDRB addrmode2:$addr)>;
1400 // extload -> zextload
1401 def : ARMPat<(extloadi1 addrmode2:$addr), (LDRB addrmode2:$addr)>;
1402 def : ARMPat<(extloadi8 addrmode2:$addr), (LDRB addrmode2:$addr)>;
1403 def : ARMPat<(extloadi16 addrmode3:$addr), (LDRH addrmode3:$addr)>;
1405 // truncstore i1 -> truncstore i8
1406 def : ARMPat<(truncstorei1 GPR:$src, addrmode2:$dst),
1407 (STRB GPR:$src, addrmode2:$dst)>;
1408 def : ARMPat<(pre_truncsti1 GPR:$src, GPR:$base, am2offset:$offset),
1409 (STRB_PRE GPR:$src, GPR:$base, am2offset:$offset)>;
1410 def : ARMPat<(post_truncsti1 GPR:$src, GPR:$base, am2offset:$offset),
1411 (STRB_POST GPR:$src, GPR:$base, am2offset:$offset)>;
1414 def : ARMV5TEPat<(mul (sra (shl GPR:$a, 16), 16), (sra (shl GPR:$b, 16), 16)),
1415 (SMULBB GPR:$a, GPR:$b)>;
1416 def : ARMV5TEPat<(mul sext_16_node:$a, sext_16_node:$b),
1417 (SMULBB GPR:$a, GPR:$b)>;
1418 def : ARMV5TEPat<(mul (sra (shl GPR:$a, 16), 16), (sra GPR:$b, 16)),
1419 (SMULBT GPR:$a, GPR:$b)>;
1420 def : ARMV5TEPat<(mul sext_16_node:$a, (sra GPR:$b, 16)),
1421 (SMULBT GPR:$a, GPR:$b)>;
1422 def : ARMV5TEPat<(mul (sra GPR:$a, 16), (sra (shl GPR:$b, 16), 16)),
1423 (SMULTB GPR:$a, GPR:$b)>;
1424 def : ARMV5TEPat<(mul (sra GPR:$a, 16), sext_16_node:$b),
1425 (SMULTB GPR:$a, GPR:$b)>;
1426 def : ARMV5TEPat<(sra (mul GPR:$a, (sra (shl GPR:$b, 16), 16)), 16),
1427 (SMULWB GPR:$a, GPR:$b)>;
1428 def : ARMV5TEPat<(sra (mul GPR:$a, sext_16_node:$b), 16),
1429 (SMULWB GPR:$a, GPR:$b)>;
1431 def : ARMV5TEPat<(add GPR:$acc,
1432 (mul (sra (shl GPR:$a, 16), 16),
1433 (sra (shl GPR:$b, 16), 16))),
1434 (SMLABB GPR:$a, GPR:$b, GPR:$acc)>;
1435 def : ARMV5TEPat<(add GPR:$acc,
1436 (mul sext_16_node:$a, sext_16_node:$b)),
1437 (SMLABB GPR:$a, GPR:$b, GPR:$acc)>;
1438 def : ARMV5TEPat<(add GPR:$acc,
1439 (mul (sra (shl GPR:$a, 16), 16), (sra GPR:$b, 16))),
1440 (SMLABT GPR:$a, GPR:$b, GPR:$acc)>;
1441 def : ARMV5TEPat<(add GPR:$acc,
1442 (mul sext_16_node:$a, (sra GPR:$b, 16))),
1443 (SMLABT GPR:$a, GPR:$b, GPR:$acc)>;
1444 def : ARMV5TEPat<(add GPR:$acc,
1445 (mul (sra GPR:$a, 16), (sra (shl GPR:$b, 16), 16))),
1446 (SMLATB GPR:$a, GPR:$b, GPR:$acc)>;
1447 def : ARMV5TEPat<(add GPR:$acc,
1448 (mul (sra GPR:$a, 16), sext_16_node:$b)),
1449 (SMLATB GPR:$a, GPR:$b, GPR:$acc)>;
1450 def : ARMV5TEPat<(add GPR:$acc,
1451 (sra (mul GPR:$a, (sra (shl GPR:$b, 16), 16)), 16)),
1452 (SMLAWB GPR:$a, GPR:$b, GPR:$acc)>;
1453 def : ARMV5TEPat<(add GPR:$acc,
1454 (sra (mul GPR:$a, sext_16_node:$b), 16)),
1455 (SMLAWB GPR:$a, GPR:$b, GPR:$acc)>;
1457 //===----------------------------------------------------------------------===//
1461 include "ARMInstrThumb.td"
1463 //===----------------------------------------------------------------------===//
1464 // Floating Point Support
1467 include "ARMInstrVFP.td"