1 //===- ARMInstrInfo.td - Target Description for ARM Target -*- tablegen -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file describes the ARM instructions in TableGen format.
12 //===----------------------------------------------------------------------===//
14 //===----------------------------------------------------------------------===//
15 // ARM specific DAG Nodes.
19 def SDT_ARMCallSeqStart : SDCallSeqStart<[ SDTCisVT<0, i32> ]>;
20 def SDT_ARMCallSeqEnd : SDCallSeqEnd<[ SDTCisVT<0, i32>, SDTCisVT<1, i32> ]>;
21 def SDT_ARMStructByVal : SDTypeProfile<0, 4,
22 [SDTCisVT<0, i32>, SDTCisVT<1, i32>,
23 SDTCisVT<2, i32>, SDTCisVT<3, i32>]>;
25 def SDT_ARMSaveCallPC : SDTypeProfile<0, 1, []>;
27 def SDT_ARMcall : SDTypeProfile<0, -1, [SDTCisPtrTy<0>]>;
29 def SDT_ARMCMov : SDTypeProfile<1, 3,
30 [SDTCisSameAs<0, 1>, SDTCisSameAs<0, 2>,
33 def SDT_ARMBrcond : SDTypeProfile<0, 2,
34 [SDTCisVT<0, OtherVT>, SDTCisVT<1, i32>]>;
36 def SDT_ARMBrJT : SDTypeProfile<0, 3,
37 [SDTCisPtrTy<0>, SDTCisVT<1, i32>,
40 def SDT_ARMBr2JT : SDTypeProfile<0, 4,
41 [SDTCisPtrTy<0>, SDTCisVT<1, i32>,
42 SDTCisVT<2, i32>, SDTCisVT<3, i32>]>;
44 def SDT_ARMBCC_i64 : SDTypeProfile<0, 6,
46 SDTCisVT<1, i32>, SDTCisVT<2, i32>,
47 SDTCisVT<3, i32>, SDTCisVT<4, i32>,
48 SDTCisVT<5, OtherVT>]>;
50 def SDT_ARMAnd : SDTypeProfile<1, 2,
51 [SDTCisVT<0, i32>, SDTCisVT<1, i32>,
54 def SDT_ARMCmp : SDTypeProfile<0, 2, [SDTCisSameAs<0, 1>]>;
56 def SDT_ARMPICAdd : SDTypeProfile<1, 2, [SDTCisSameAs<0, 1>,
57 SDTCisPtrTy<1>, SDTCisVT<2, i32>]>;
59 def SDT_ARMThreadPointer : SDTypeProfile<1, 0, [SDTCisPtrTy<0>]>;
60 def SDT_ARMEH_SJLJ_Setjmp : SDTypeProfile<1, 2, [SDTCisInt<0>, SDTCisPtrTy<1>,
62 def SDT_ARMEH_SJLJ_Longjmp: SDTypeProfile<0, 2, [SDTCisPtrTy<0>, SDTCisInt<1>]>;
64 def SDT_ARMMEMBARRIER : SDTypeProfile<0, 1, [SDTCisInt<0>]>;
66 def SDT_ARMPREFETCH : SDTypeProfile<0, 3, [SDTCisPtrTy<0>, SDTCisSameAs<1, 2>,
69 def SDT_ARMTCRET : SDTypeProfile<0, 1, [SDTCisPtrTy<0>]>;
71 def SDT_ARMBFI : SDTypeProfile<1, 3, [SDTCisVT<0, i32>, SDTCisVT<1, i32>,
72 SDTCisVT<2, i32>, SDTCisVT<3, i32>]>;
74 def SDTBinaryArithWithFlags : SDTypeProfile<2, 2,
77 SDTCisInt<0>, SDTCisVT<1, i32>]>;
79 // SDTBinaryArithWithFlagsInOut - RES1, CPSR = op LHS, RHS, CPSR
80 def SDTBinaryArithWithFlagsInOut : SDTypeProfile<2, 3,
87 def ARMWrapper : SDNode<"ARMISD::Wrapper", SDTIntUnaryOp>;
88 def ARMWrapperDYN : SDNode<"ARMISD::WrapperDYN", SDTIntUnaryOp>;
89 def ARMWrapperPIC : SDNode<"ARMISD::WrapperPIC", SDTIntUnaryOp>;
90 def ARMWrapperJT : SDNode<"ARMISD::WrapperJT", SDTIntBinOp>;
92 def ARMcallseq_start : SDNode<"ISD::CALLSEQ_START", SDT_ARMCallSeqStart,
93 [SDNPHasChain, SDNPSideEffect, SDNPOutGlue]>;
94 def ARMcallseq_end : SDNode<"ISD::CALLSEQ_END", SDT_ARMCallSeqEnd,
95 [SDNPHasChain, SDNPSideEffect,
96 SDNPOptInGlue, SDNPOutGlue]>;
97 def ARMcopystructbyval : SDNode<"ARMISD::COPY_STRUCT_BYVAL" ,
99 [SDNPHasChain, SDNPInGlue, SDNPOutGlue,
100 SDNPMayStore, SDNPMayLoad]>;
102 def ARMcall : SDNode<"ARMISD::CALL", SDT_ARMcall,
103 [SDNPHasChain, SDNPOptInGlue, SDNPOutGlue,
105 def ARMcall_pred : SDNode<"ARMISD::CALL_PRED", SDT_ARMcall,
106 [SDNPHasChain, SDNPOptInGlue, SDNPOutGlue,
108 def ARMcall_nolink : SDNode<"ARMISD::CALL_NOLINK", SDT_ARMcall,
109 [SDNPHasChain, SDNPOptInGlue, SDNPOutGlue,
112 def ARMretflag : SDNode<"ARMISD::RET_FLAG", SDTNone,
113 [SDNPHasChain, SDNPOptInGlue]>;
115 def ARMcmov : SDNode<"ARMISD::CMOV", SDT_ARMCMov,
118 def ARMbrcond : SDNode<"ARMISD::BRCOND", SDT_ARMBrcond,
119 [SDNPHasChain, SDNPInGlue, SDNPOutGlue]>;
121 def ARMbrjt : SDNode<"ARMISD::BR_JT", SDT_ARMBrJT,
123 def ARMbr2jt : SDNode<"ARMISD::BR2_JT", SDT_ARMBr2JT,
126 def ARMBcci64 : SDNode<"ARMISD::BCC_i64", SDT_ARMBCC_i64,
129 def ARMcmp : SDNode<"ARMISD::CMP", SDT_ARMCmp,
132 def ARMcmn : SDNode<"ARMISD::CMN", SDT_ARMCmp,
135 def ARMcmpZ : SDNode<"ARMISD::CMPZ", SDT_ARMCmp,
136 [SDNPOutGlue, SDNPCommutative]>;
138 def ARMpic_add : SDNode<"ARMISD::PIC_ADD", SDT_ARMPICAdd>;
140 def ARMsrl_flag : SDNode<"ARMISD::SRL_FLAG", SDTIntUnaryOp, [SDNPOutGlue]>;
141 def ARMsra_flag : SDNode<"ARMISD::SRA_FLAG", SDTIntUnaryOp, [SDNPOutGlue]>;
142 def ARMrrx : SDNode<"ARMISD::RRX" , SDTIntUnaryOp, [SDNPInGlue ]>;
144 def ARMaddc : SDNode<"ARMISD::ADDC", SDTBinaryArithWithFlags,
146 def ARMsubc : SDNode<"ARMISD::SUBC", SDTBinaryArithWithFlags>;
147 def ARMadde : SDNode<"ARMISD::ADDE", SDTBinaryArithWithFlagsInOut>;
148 def ARMsube : SDNode<"ARMISD::SUBE", SDTBinaryArithWithFlagsInOut>;
150 def ARMthread_pointer: SDNode<"ARMISD::THREAD_POINTER", SDT_ARMThreadPointer>;
151 def ARMeh_sjlj_setjmp: SDNode<"ARMISD::EH_SJLJ_SETJMP",
152 SDT_ARMEH_SJLJ_Setjmp,
153 [SDNPHasChain, SDNPSideEffect]>;
154 def ARMeh_sjlj_longjmp: SDNode<"ARMISD::EH_SJLJ_LONGJMP",
155 SDT_ARMEH_SJLJ_Longjmp,
156 [SDNPHasChain, SDNPSideEffect]>;
158 def ARMMemBarrier : SDNode<"ARMISD::MEMBARRIER", SDT_ARMMEMBARRIER,
159 [SDNPHasChain, SDNPSideEffect]>;
160 def ARMMemBarrierMCR : SDNode<"ARMISD::MEMBARRIER_MCR", SDT_ARMMEMBARRIER,
161 [SDNPHasChain, SDNPSideEffect]>;
162 def ARMPreload : SDNode<"ARMISD::PRELOAD", SDT_ARMPREFETCH,
163 [SDNPHasChain, SDNPMayLoad, SDNPMayStore]>;
165 def ARMrbit : SDNode<"ARMISD::RBIT", SDTIntUnaryOp>;
167 def ARMtcret : SDNode<"ARMISD::TC_RETURN", SDT_ARMTCRET,
168 [SDNPHasChain, SDNPOptInGlue, SDNPVariadic]>;
171 def ARMbfi : SDNode<"ARMISD::BFI", SDT_ARMBFI>;
173 //===----------------------------------------------------------------------===//
174 // ARM Instruction Predicate Definitions.
176 def HasV4T : Predicate<"Subtarget->hasV4TOps()">,
177 AssemblerPredicate<"HasV4TOps", "armv4t">;
178 def NoV4T : Predicate<"!Subtarget->hasV4TOps()">;
179 def HasV5T : Predicate<"Subtarget->hasV5TOps()">;
180 def HasV5TE : Predicate<"Subtarget->hasV5TEOps()">,
181 AssemblerPredicate<"HasV5TEOps", "armv5te">;
182 def HasV6 : Predicate<"Subtarget->hasV6Ops()">,
183 AssemblerPredicate<"HasV6Ops", "armv6">;
184 def NoV6 : Predicate<"!Subtarget->hasV6Ops()">;
185 def HasV6T2 : Predicate<"Subtarget->hasV6T2Ops()">,
186 AssemblerPredicate<"HasV6T2Ops", "armv6t2">;
187 def NoV6T2 : Predicate<"!Subtarget->hasV6T2Ops()">;
188 def HasV7 : Predicate<"Subtarget->hasV7Ops()">,
189 AssemblerPredicate<"HasV7Ops", "armv7">;
190 def NoVFP : Predicate<"!Subtarget->hasVFP2()">;
191 def HasVFP2 : Predicate<"Subtarget->hasVFP2()">,
192 AssemblerPredicate<"FeatureVFP2", "VFP2">;
193 def HasVFP3 : Predicate<"Subtarget->hasVFP3()">,
194 AssemblerPredicate<"FeatureVFP3", "VFP3">;
195 def HasVFP4 : Predicate<"Subtarget->hasVFP4()">,
196 AssemblerPredicate<"FeatureVFP4", "VFP4">;
197 def HasNEON : Predicate<"Subtarget->hasNEON()">,
198 AssemblerPredicate<"FeatureNEON", "NEON">;
199 def HasFP16 : Predicate<"Subtarget->hasFP16()">,
200 AssemblerPredicate<"FeatureFP16","half-float">;
201 def HasDivide : Predicate<"Subtarget->hasDivide()">,
202 AssemblerPredicate<"FeatureHWDiv", "divide">;
203 def HasT2ExtractPack : Predicate<"Subtarget->hasT2ExtractPack()">,
204 AssemblerPredicate<"FeatureT2XtPk",
206 def HasThumb2DSP : Predicate<"Subtarget->hasThumb2DSP()">,
207 AssemblerPredicate<"FeatureDSPThumb2",
209 def HasDB : Predicate<"Subtarget->hasDataBarrier()">,
210 AssemblerPredicate<"FeatureDB",
212 def HasMP : Predicate<"Subtarget->hasMPExtension()">,
213 AssemblerPredicate<"FeatureMP",
215 def UseNEONForFP : Predicate<"Subtarget->useNEONForSinglePrecisionFP()">;
216 def DontUseNEONForFP : Predicate<"!Subtarget->useNEONForSinglePrecisionFP()">;
217 def IsThumb : Predicate<"Subtarget->isThumb()">,
218 AssemblerPredicate<"ModeThumb", "thumb">;
219 def IsThumb1Only : Predicate<"Subtarget->isThumb1Only()">;
220 def IsThumb2 : Predicate<"Subtarget->isThumb2()">,
221 AssemblerPredicate<"ModeThumb,FeatureThumb2",
223 def IsMClass : Predicate<"Subtarget->isMClass()">,
224 AssemblerPredicate<"FeatureMClass", "armv7m">;
225 def IsARClass : Predicate<"!Subtarget->isMClass()">,
226 AssemblerPredicate<"!FeatureMClass",
228 def IsARM : Predicate<"!Subtarget->isThumb()">,
229 AssemblerPredicate<"!ModeThumb", "arm-mode">;
230 def IsIOS : Predicate<"Subtarget->isTargetIOS()">;
231 def IsNotIOS : Predicate<"!Subtarget->isTargetIOS()">;
232 def IsNaCl : Predicate<"Subtarget->isTargetNaCl()">;
234 // FIXME: Eventually this will be just "hasV6T2Ops".
235 def UseMovt : Predicate<"Subtarget->useMovt()">;
236 def DontUseMovt : Predicate<"!Subtarget->useMovt()">;
237 def UseFPVMLx : Predicate<"Subtarget->useFPVMLx()">;
239 // Prefer fused MAC for fp mul + add over fp VMLA / VMLS if they are available.
240 // But only select them if more precision in FP computation is allowed.
241 // Do not use them for Darwin platforms.
242 def UseFusedMAC : Predicate<"(TM.Options.AllowFPOpFusion =="
243 " FPOpFusion::Fast) && "
244 "!Subtarget->isTargetDarwin()">;
245 def DontUseFusedMAC : Predicate<"!Subtarget->hasVFP4() || "
246 "Subtarget->isTargetDarwin()">;
248 def IsLE : Predicate<"TLI.isLittleEndian()">;
249 def IsBE : Predicate<"TLI.isBigEndian()">;
251 //===----------------------------------------------------------------------===//
252 // ARM Flag Definitions.
254 class RegConstraint<string C> {
255 string Constraints = C;
258 //===----------------------------------------------------------------------===//
259 // ARM specific transformation functions and pattern fragments.
262 // imm_neg_XFORM - Return a imm value packed into the format described for
263 // imm_neg defs below.
264 def imm_neg_XFORM : SDNodeXForm<imm, [{
265 return CurDAG->getTargetConstant(-(int)N->getZExtValue(), MVT::i32);
268 // so_imm_not_XFORM - Return a so_imm value packed into the format described for
269 // so_imm_not def below.
270 def so_imm_not_XFORM : SDNodeXForm<imm, [{
271 return CurDAG->getTargetConstant(~(int)N->getZExtValue(), MVT::i32);
274 /// imm16_31 predicate - True if the 32-bit immediate is in the range [16,31].
275 def imm16_31 : ImmLeaf<i32, [{
276 return (int32_t)Imm >= 16 && (int32_t)Imm < 32;
279 def so_imm_neg_asmoperand : AsmOperandClass { let Name = "ARMSOImmNeg"; }
280 def so_imm_neg : Operand<i32>, PatLeaf<(imm), [{
281 unsigned Value = -(unsigned)N->getZExtValue();
282 return Value && ARM_AM::getSOImmVal(Value) != -1;
284 let ParserMatchClass = so_imm_neg_asmoperand;
287 // Note: this pattern doesn't require an encoder method and such, as it's
288 // only used on aliases (Pat<> and InstAlias<>). The actual encoding
289 // is handled by the destination instructions, which use so_imm.
290 def so_imm_not_asmoperand : AsmOperandClass { let Name = "ARMSOImmNot"; }
291 def so_imm_not : Operand<i32>, PatLeaf<(imm), [{
292 return ARM_AM::getSOImmVal(~(uint32_t)N->getZExtValue()) != -1;
293 }], so_imm_not_XFORM> {
294 let ParserMatchClass = so_imm_not_asmoperand;
297 // sext_16_node predicate - True if the SDNode is sign-extended 16 or more bits.
298 def sext_16_node : PatLeaf<(i32 GPR:$a), [{
299 return CurDAG->ComputeNumSignBits(SDValue(N,0)) >= 17;
302 /// Split a 32-bit immediate into two 16 bit parts.
303 def hi16 : SDNodeXForm<imm, [{
304 return CurDAG->getTargetConstant((uint32_t)N->getZExtValue() >> 16, MVT::i32);
307 def lo16AllZero : PatLeaf<(i32 imm), [{
308 // Returns true if all low 16-bits are 0.
309 return (((uint32_t)N->getZExtValue()) & 0xFFFFUL) == 0;
312 class BinOpWithFlagFrag<dag res> :
313 PatFrag<(ops node:$LHS, node:$RHS, node:$FLAG), res>;
314 class BinOpFrag<dag res> : PatFrag<(ops node:$LHS, node:$RHS), res>;
315 class UnOpFrag <dag res> : PatFrag<(ops node:$Src), res>;
317 // An 'and' node with a single use.
318 def and_su : PatFrag<(ops node:$lhs, node:$rhs), (and node:$lhs, node:$rhs), [{
319 return N->hasOneUse();
322 // An 'xor' node with a single use.
323 def xor_su : PatFrag<(ops node:$lhs, node:$rhs), (xor node:$lhs, node:$rhs), [{
324 return N->hasOneUse();
327 // An 'fmul' node with a single use.
328 def fmul_su : PatFrag<(ops node:$lhs, node:$rhs), (fmul node:$lhs, node:$rhs),[{
329 return N->hasOneUse();
332 // An 'fadd' node which checks for single non-hazardous use.
333 def fadd_mlx : PatFrag<(ops node:$lhs, node:$rhs),(fadd node:$lhs, node:$rhs),[{
334 return hasNoVMLxHazardUse(N);
337 // An 'fsub' node which checks for single non-hazardous use.
338 def fsub_mlx : PatFrag<(ops node:$lhs, node:$rhs),(fsub node:$lhs, node:$rhs),[{
339 return hasNoVMLxHazardUse(N);
342 //===----------------------------------------------------------------------===//
343 // Operand Definitions.
346 // Immediate operands with a shared generic asm render method.
347 class ImmAsmOperand : AsmOperandClass { let RenderMethod = "addImmOperands"; }
350 // FIXME: rename brtarget to t2_brtarget
351 def brtarget : Operand<OtherVT> {
352 let EncoderMethod = "getBranchTargetOpValue";
353 let OperandType = "OPERAND_PCREL";
354 let DecoderMethod = "DecodeT2BROperand";
357 // FIXME: get rid of this one?
358 def uncondbrtarget : Operand<OtherVT> {
359 let EncoderMethod = "getUnconditionalBranchTargetOpValue";
360 let OperandType = "OPERAND_PCREL";
363 // Branch target for ARM. Handles conditional/unconditional
364 def br_target : Operand<OtherVT> {
365 let EncoderMethod = "getARMBranchTargetOpValue";
366 let OperandType = "OPERAND_PCREL";
370 // FIXME: rename bltarget to t2_bl_target?
371 def bltarget : Operand<i32> {
372 // Encoded the same as branch targets.
373 let EncoderMethod = "getBranchTargetOpValue";
374 let OperandType = "OPERAND_PCREL";
377 // Call target for ARM. Handles conditional/unconditional
378 // FIXME: rename bl_target to t2_bltarget?
379 def bl_target : Operand<i32> {
380 let EncoderMethod = "getARMBLTargetOpValue";
381 let OperandType = "OPERAND_PCREL";
384 def blx_target : Operand<i32> {
385 let EncoderMethod = "getARMBLXTargetOpValue";
386 let OperandType = "OPERAND_PCREL";
389 // A list of registers separated by comma. Used by load/store multiple.
390 def RegListAsmOperand : AsmOperandClass { let Name = "RegList"; }
391 def reglist : Operand<i32> {
392 let EncoderMethod = "getRegisterListOpValue";
393 let ParserMatchClass = RegListAsmOperand;
394 let PrintMethod = "printRegisterList";
395 let DecoderMethod = "DecodeRegListOperand";
398 def DPRRegListAsmOperand : AsmOperandClass { let Name = "DPRRegList"; }
399 def dpr_reglist : Operand<i32> {
400 let EncoderMethod = "getRegisterListOpValue";
401 let ParserMatchClass = DPRRegListAsmOperand;
402 let PrintMethod = "printRegisterList";
403 let DecoderMethod = "DecodeDPRRegListOperand";
406 def SPRRegListAsmOperand : AsmOperandClass { let Name = "SPRRegList"; }
407 def spr_reglist : Operand<i32> {
408 let EncoderMethod = "getRegisterListOpValue";
409 let ParserMatchClass = SPRRegListAsmOperand;
410 let PrintMethod = "printRegisterList";
411 let DecoderMethod = "DecodeSPRRegListOperand";
414 // An operand for the CONSTPOOL_ENTRY pseudo-instruction.
415 def cpinst_operand : Operand<i32> {
416 let PrintMethod = "printCPInstOperand";
420 def pclabel : Operand<i32> {
421 let PrintMethod = "printPCLabel";
424 // ADR instruction labels.
425 def AdrLabelAsmOperand : AsmOperandClass { let Name = "AdrLabel"; }
426 def adrlabel : Operand<i32> {
427 let EncoderMethod = "getAdrLabelOpValue";
428 let ParserMatchClass = AdrLabelAsmOperand;
429 let PrintMethod = "printAdrLabelOperand";
432 def neon_vcvt_imm32 : Operand<i32> {
433 let EncoderMethod = "getNEONVcvtImm32OpValue";
434 let DecoderMethod = "DecodeVCVTImmOperand";
437 // rot_imm: An integer that encodes a rotate amount. Must be 8, 16, or 24.
438 def rot_imm_XFORM: SDNodeXForm<imm, [{
439 switch (N->getZExtValue()){
441 case 0: return CurDAG->getTargetConstant(0, MVT::i32);
442 case 8: return CurDAG->getTargetConstant(1, MVT::i32);
443 case 16: return CurDAG->getTargetConstant(2, MVT::i32);
444 case 24: return CurDAG->getTargetConstant(3, MVT::i32);
447 def RotImmAsmOperand : AsmOperandClass {
449 let ParserMethod = "parseRotImm";
451 def rot_imm : Operand<i32>, PatLeaf<(i32 imm), [{
452 int32_t v = N->getZExtValue();
453 return v == 8 || v == 16 || v == 24; }],
455 let PrintMethod = "printRotImmOperand";
456 let ParserMatchClass = RotImmAsmOperand;
459 // shift_imm: An integer that encodes a shift amount and the type of shift
460 // (asr or lsl). The 6-bit immediate encodes as:
463 // {4-0} imm5 shift amount.
464 // asr #32 encoded as imm5 == 0.
465 def ShifterImmAsmOperand : AsmOperandClass {
466 let Name = "ShifterImm";
467 let ParserMethod = "parseShifterImm";
469 def shift_imm : Operand<i32> {
470 let PrintMethod = "printShiftImmOperand";
471 let ParserMatchClass = ShifterImmAsmOperand;
474 // shifter_operand operands: so_reg_reg, so_reg_imm, and so_imm.
475 def ShiftedRegAsmOperand : AsmOperandClass { let Name = "RegShiftedReg"; }
476 def so_reg_reg : Operand<i32>, // reg reg imm
477 ComplexPattern<i32, 3, "SelectRegShifterOperand",
478 [shl, srl, sra, rotr]> {
479 let EncoderMethod = "getSORegRegOpValue";
480 let PrintMethod = "printSORegRegOperand";
481 let DecoderMethod = "DecodeSORegRegOperand";
482 let ParserMatchClass = ShiftedRegAsmOperand;
483 let MIOperandInfo = (ops GPRnopc, GPRnopc, i32imm);
486 def ShiftedImmAsmOperand : AsmOperandClass { let Name = "RegShiftedImm"; }
487 def so_reg_imm : Operand<i32>, // reg imm
488 ComplexPattern<i32, 2, "SelectImmShifterOperand",
489 [shl, srl, sra, rotr]> {
490 let EncoderMethod = "getSORegImmOpValue";
491 let PrintMethod = "printSORegImmOperand";
492 let DecoderMethod = "DecodeSORegImmOperand";
493 let ParserMatchClass = ShiftedImmAsmOperand;
494 let MIOperandInfo = (ops GPR, i32imm);
497 // FIXME: Does this need to be distinct from so_reg?
498 def shift_so_reg_reg : Operand<i32>, // reg reg imm
499 ComplexPattern<i32, 3, "SelectShiftRegShifterOperand",
500 [shl,srl,sra,rotr]> {
501 let EncoderMethod = "getSORegRegOpValue";
502 let PrintMethod = "printSORegRegOperand";
503 let DecoderMethod = "DecodeSORegRegOperand";
504 let ParserMatchClass = ShiftedRegAsmOperand;
505 let MIOperandInfo = (ops GPR, GPR, i32imm);
508 // FIXME: Does this need to be distinct from so_reg?
509 def shift_so_reg_imm : Operand<i32>, // reg reg imm
510 ComplexPattern<i32, 2, "SelectShiftImmShifterOperand",
511 [shl,srl,sra,rotr]> {
512 let EncoderMethod = "getSORegImmOpValue";
513 let PrintMethod = "printSORegImmOperand";
514 let DecoderMethod = "DecodeSORegImmOperand";
515 let ParserMatchClass = ShiftedImmAsmOperand;
516 let MIOperandInfo = (ops GPR, i32imm);
520 // so_imm - Match a 32-bit shifter_operand immediate operand, which is an
521 // 8-bit immediate rotated by an arbitrary number of bits.
522 def SOImmAsmOperand: ImmAsmOperand { let Name = "ARMSOImm"; }
523 def so_imm : Operand<i32>, ImmLeaf<i32, [{
524 return ARM_AM::getSOImmVal(Imm) != -1;
526 let EncoderMethod = "getSOImmOpValue";
527 let ParserMatchClass = SOImmAsmOperand;
528 let DecoderMethod = "DecodeSOImmOperand";
531 // Break so_imm's up into two pieces. This handles immediates with up to 16
532 // bits set in them. This uses so_imm2part to match and so_imm2part_[12] to
533 // get the first/second pieces.
534 def so_imm2part : PatLeaf<(imm), [{
535 return ARM_AM::isSOImmTwoPartVal((unsigned)N->getZExtValue());
538 /// arm_i32imm - True for +V6T2, or true only if so_imm2part is true.
540 def arm_i32imm : PatLeaf<(imm), [{
541 if (Subtarget->hasV6T2Ops())
543 return ARM_AM::isSOImmTwoPartVal((unsigned)N->getZExtValue());
546 /// imm0_1 predicate - Immediate in the range [0,1].
547 def Imm0_1AsmOperand: ImmAsmOperand { let Name = "Imm0_1"; }
548 def imm0_1 : Operand<i32> { let ParserMatchClass = Imm0_1AsmOperand; }
550 /// imm0_3 predicate - Immediate in the range [0,3].
551 def Imm0_3AsmOperand: ImmAsmOperand { let Name = "Imm0_3"; }
552 def imm0_3 : Operand<i32> { let ParserMatchClass = Imm0_3AsmOperand; }
554 /// imm0_7 predicate - Immediate in the range [0,7].
555 def Imm0_7AsmOperand: ImmAsmOperand { let Name = "Imm0_7"; }
556 def imm0_7 : Operand<i32>, ImmLeaf<i32, [{
557 return Imm >= 0 && Imm < 8;
559 let ParserMatchClass = Imm0_7AsmOperand;
562 /// imm8 predicate - Immediate is exactly 8.
563 def Imm8AsmOperand: ImmAsmOperand { let Name = "Imm8"; }
564 def imm8 : Operand<i32>, ImmLeaf<i32, [{ return Imm == 8; }]> {
565 let ParserMatchClass = Imm8AsmOperand;
568 /// imm16 predicate - Immediate is exactly 16.
569 def Imm16AsmOperand: ImmAsmOperand { let Name = "Imm16"; }
570 def imm16 : Operand<i32>, ImmLeaf<i32, [{ return Imm == 16; }]> {
571 let ParserMatchClass = Imm16AsmOperand;
574 /// imm32 predicate - Immediate is exactly 32.
575 def Imm32AsmOperand: ImmAsmOperand { let Name = "Imm32"; }
576 def imm32 : Operand<i32>, ImmLeaf<i32, [{ return Imm == 32; }]> {
577 let ParserMatchClass = Imm32AsmOperand;
580 /// imm1_7 predicate - Immediate in the range [1,7].
581 def Imm1_7AsmOperand: ImmAsmOperand { let Name = "Imm1_7"; }
582 def imm1_7 : Operand<i32>, ImmLeaf<i32, [{ return Imm > 0 && Imm < 8; }]> {
583 let ParserMatchClass = Imm1_7AsmOperand;
586 /// imm1_15 predicate - Immediate in the range [1,15].
587 def Imm1_15AsmOperand: ImmAsmOperand { let Name = "Imm1_15"; }
588 def imm1_15 : Operand<i32>, ImmLeaf<i32, [{ return Imm > 0 && Imm < 16; }]> {
589 let ParserMatchClass = Imm1_15AsmOperand;
592 /// imm1_31 predicate - Immediate in the range [1,31].
593 def Imm1_31AsmOperand: ImmAsmOperand { let Name = "Imm1_31"; }
594 def imm1_31 : Operand<i32>, ImmLeaf<i32, [{ return Imm > 0 && Imm < 32; }]> {
595 let ParserMatchClass = Imm1_31AsmOperand;
598 /// imm0_15 predicate - Immediate in the range [0,15].
599 def Imm0_15AsmOperand: ImmAsmOperand {
600 let Name = "Imm0_15";
601 let DiagnosticType = "ImmRange0_15";
603 def imm0_15 : Operand<i32>, ImmLeaf<i32, [{
604 return Imm >= 0 && Imm < 16;
606 let ParserMatchClass = Imm0_15AsmOperand;
609 /// imm0_31 predicate - True if the 32-bit immediate is in the range [0,31].
610 def Imm0_31AsmOperand: ImmAsmOperand { let Name = "Imm0_31"; }
611 def imm0_31 : Operand<i32>, ImmLeaf<i32, [{
612 return Imm >= 0 && Imm < 32;
614 let ParserMatchClass = Imm0_31AsmOperand;
617 /// imm0_32 predicate - True if the 32-bit immediate is in the range [0,32].
618 def Imm0_32AsmOperand: ImmAsmOperand { let Name = "Imm0_32"; }
619 def imm0_32 : Operand<i32>, ImmLeaf<i32, [{
620 return Imm >= 0 && Imm < 32;
622 let ParserMatchClass = Imm0_32AsmOperand;
625 /// imm0_63 predicate - True if the 32-bit immediate is in the range [0,63].
626 def Imm0_63AsmOperand: ImmAsmOperand { let Name = "Imm0_63"; }
627 def imm0_63 : Operand<i32>, ImmLeaf<i32, [{
628 return Imm >= 0 && Imm < 64;
630 let ParserMatchClass = Imm0_63AsmOperand;
633 /// imm0_255 predicate - Immediate in the range [0,255].
634 def Imm0_255AsmOperand : ImmAsmOperand { let Name = "Imm0_255"; }
635 def imm0_255 : Operand<i32>, ImmLeaf<i32, [{ return Imm >= 0 && Imm < 256; }]> {
636 let ParserMatchClass = Imm0_255AsmOperand;
639 /// imm0_65535 - An immediate is in the range [0.65535].
640 def Imm0_65535AsmOperand: ImmAsmOperand { let Name = "Imm0_65535"; }
641 def imm0_65535 : Operand<i32>, ImmLeaf<i32, [{
642 return Imm >= 0 && Imm < 65536;
644 let ParserMatchClass = Imm0_65535AsmOperand;
647 // imm0_65535_neg - An immediate whose negative value is in the range [0.65535].
648 def imm0_65535_neg : Operand<i32>, ImmLeaf<i32, [{
649 return -Imm >= 0 && -Imm < 65536;
652 // imm0_65535_expr - For movt/movw - 16-bit immediate that can also reference
653 // a relocatable expression.
655 // FIXME: This really needs a Thumb version separate from the ARM version.
656 // While the range is the same, and can thus use the same match class,
657 // the encoding is different so it should have a different encoder method.
658 def Imm0_65535ExprAsmOperand: ImmAsmOperand { let Name = "Imm0_65535Expr"; }
659 def imm0_65535_expr : Operand<i32> {
660 let EncoderMethod = "getHiLo16ImmOpValue";
661 let ParserMatchClass = Imm0_65535ExprAsmOperand;
664 /// imm24b - True if the 32-bit immediate is encodable in 24 bits.
665 def Imm24bitAsmOperand: ImmAsmOperand { let Name = "Imm24bit"; }
666 def imm24b : Operand<i32>, ImmLeaf<i32, [{
667 return Imm >= 0 && Imm <= 0xffffff;
669 let ParserMatchClass = Imm24bitAsmOperand;
673 /// bf_inv_mask_imm predicate - An AND mask to clear an arbitrary width bitfield
675 def BitfieldAsmOperand : AsmOperandClass {
676 let Name = "Bitfield";
677 let ParserMethod = "parseBitfield";
680 def bf_inv_mask_imm : Operand<i32>,
682 return ARM::isBitFieldInvertedMask(N->getZExtValue());
684 let EncoderMethod = "getBitfieldInvertedMaskOpValue";
685 let PrintMethod = "printBitfieldInvMaskImmOperand";
686 let DecoderMethod = "DecodeBitfieldMaskOperand";
687 let ParserMatchClass = BitfieldAsmOperand;
690 def imm1_32_XFORM: SDNodeXForm<imm, [{
691 return CurDAG->getTargetConstant((int)N->getZExtValue() - 1, MVT::i32);
693 def Imm1_32AsmOperand: AsmOperandClass { let Name = "Imm1_32"; }
694 def imm1_32 : Operand<i32>, PatLeaf<(imm), [{
695 uint64_t Imm = N->getZExtValue();
696 return Imm > 0 && Imm <= 32;
699 let PrintMethod = "printImmPlusOneOperand";
700 let ParserMatchClass = Imm1_32AsmOperand;
703 def imm1_16_XFORM: SDNodeXForm<imm, [{
704 return CurDAG->getTargetConstant((int)N->getZExtValue() - 1, MVT::i32);
706 def Imm1_16AsmOperand: AsmOperandClass { let Name = "Imm1_16"; }
707 def imm1_16 : Operand<i32>, PatLeaf<(imm), [{ return Imm > 0 && Imm <= 16; }],
709 let PrintMethod = "printImmPlusOneOperand";
710 let ParserMatchClass = Imm1_16AsmOperand;
713 // Define ARM specific addressing modes.
714 // addrmode_imm12 := reg +/- imm12
716 def MemImm12OffsetAsmOperand : AsmOperandClass { let Name = "MemImm12Offset"; }
717 def addrmode_imm12 : Operand<i32>,
718 ComplexPattern<i32, 2, "SelectAddrModeImm12", []> {
719 // 12-bit immediate operand. Note that instructions using this encode
720 // #0 and #-0 differently. We flag #-0 as the magic value INT32_MIN. All other
721 // immediate values are as normal.
723 let EncoderMethod = "getAddrModeImm12OpValue";
724 let PrintMethod = "printAddrModeImm12Operand";
725 let DecoderMethod = "DecodeAddrModeImm12Operand";
726 let ParserMatchClass = MemImm12OffsetAsmOperand;
727 let MIOperandInfo = (ops GPR:$base, i32imm:$offsimm);
729 // ldst_so_reg := reg +/- reg shop imm
731 def MemRegOffsetAsmOperand : AsmOperandClass { let Name = "MemRegOffset"; }
732 def ldst_so_reg : Operand<i32>,
733 ComplexPattern<i32, 3, "SelectLdStSOReg", []> {
734 let EncoderMethod = "getLdStSORegOpValue";
735 // FIXME: Simplify the printer
736 let PrintMethod = "printAddrMode2Operand";
737 let DecoderMethod = "DecodeSORegMemOperand";
738 let ParserMatchClass = MemRegOffsetAsmOperand;
739 let MIOperandInfo = (ops GPR:$base, GPRnopc:$offsreg, i32imm:$shift);
742 // postidx_imm8 := +/- [0,255]
745 // {8} 1 is imm8 is non-negative. 0 otherwise.
746 // {7-0} [0,255] imm8 value.
747 def PostIdxImm8AsmOperand : AsmOperandClass { let Name = "PostIdxImm8"; }
748 def postidx_imm8 : Operand<i32> {
749 let PrintMethod = "printPostIdxImm8Operand";
750 let ParserMatchClass = PostIdxImm8AsmOperand;
751 let MIOperandInfo = (ops i32imm);
754 // postidx_imm8s4 := +/- [0,1020]
757 // {8} 1 is imm8 is non-negative. 0 otherwise.
758 // {7-0} [0,255] imm8 value, scaled by 4.
759 def PostIdxImm8s4AsmOperand : AsmOperandClass { let Name = "PostIdxImm8s4"; }
760 def postidx_imm8s4 : Operand<i32> {
761 let PrintMethod = "printPostIdxImm8s4Operand";
762 let ParserMatchClass = PostIdxImm8s4AsmOperand;
763 let MIOperandInfo = (ops i32imm);
767 // postidx_reg := +/- reg
769 def PostIdxRegAsmOperand : AsmOperandClass {
770 let Name = "PostIdxReg";
771 let ParserMethod = "parsePostIdxReg";
773 def postidx_reg : Operand<i32> {
774 let EncoderMethod = "getPostIdxRegOpValue";
775 let DecoderMethod = "DecodePostIdxReg";
776 let PrintMethod = "printPostIdxRegOperand";
777 let ParserMatchClass = PostIdxRegAsmOperand;
778 let MIOperandInfo = (ops GPRnopc, i32imm);
782 // addrmode2 := reg +/- imm12
783 // := reg +/- reg shop imm
785 // FIXME: addrmode2 should be refactored the rest of the way to always
786 // use explicit imm vs. reg versions above (addrmode_imm12 and ldst_so_reg).
787 def AddrMode2AsmOperand : AsmOperandClass { let Name = "AddrMode2"; }
788 def addrmode2 : Operand<i32>,
789 ComplexPattern<i32, 3, "SelectAddrMode2", []> {
790 let EncoderMethod = "getAddrMode2OpValue";
791 let PrintMethod = "printAddrMode2Operand";
792 let ParserMatchClass = AddrMode2AsmOperand;
793 let MIOperandInfo = (ops GPR:$base, GPR:$offsreg, i32imm:$offsimm);
796 def PostIdxRegShiftedAsmOperand : AsmOperandClass {
797 let Name = "PostIdxRegShifted";
798 let ParserMethod = "parsePostIdxReg";
800 def am2offset_reg : Operand<i32>,
801 ComplexPattern<i32, 2, "SelectAddrMode2OffsetReg",
802 [], [SDNPWantRoot]> {
803 let EncoderMethod = "getAddrMode2OffsetOpValue";
804 let PrintMethod = "printAddrMode2OffsetOperand";
805 // When using this for assembly, it's always as a post-index offset.
806 let ParserMatchClass = PostIdxRegShiftedAsmOperand;
807 let MIOperandInfo = (ops GPRnopc, i32imm);
810 // FIXME: am2offset_imm should only need the immediate, not the GPR. Having
811 // the GPR is purely vestigal at this point.
812 def AM2OffsetImmAsmOperand : AsmOperandClass { let Name = "AM2OffsetImm"; }
813 def am2offset_imm : Operand<i32>,
814 ComplexPattern<i32, 2, "SelectAddrMode2OffsetImm",
815 [], [SDNPWantRoot]> {
816 let EncoderMethod = "getAddrMode2OffsetOpValue";
817 let PrintMethod = "printAddrMode2OffsetOperand";
818 let ParserMatchClass = AM2OffsetImmAsmOperand;
819 let MIOperandInfo = (ops GPRnopc, i32imm);
823 // addrmode3 := reg +/- reg
824 // addrmode3 := reg +/- imm8
826 // FIXME: split into imm vs. reg versions.
827 def AddrMode3AsmOperand : AsmOperandClass { let Name = "AddrMode3"; }
828 def addrmode3 : Operand<i32>,
829 ComplexPattern<i32, 3, "SelectAddrMode3", []> {
830 let EncoderMethod = "getAddrMode3OpValue";
831 let PrintMethod = "printAddrMode3Operand";
832 let ParserMatchClass = AddrMode3AsmOperand;
833 let MIOperandInfo = (ops GPR:$base, GPR:$offsreg, i32imm:$offsimm);
836 // FIXME: split into imm vs. reg versions.
837 // FIXME: parser method to handle +/- register.
838 def AM3OffsetAsmOperand : AsmOperandClass {
839 let Name = "AM3Offset";
840 let ParserMethod = "parseAM3Offset";
842 def am3offset : Operand<i32>,
843 ComplexPattern<i32, 2, "SelectAddrMode3Offset",
844 [], [SDNPWantRoot]> {
845 let EncoderMethod = "getAddrMode3OffsetOpValue";
846 let PrintMethod = "printAddrMode3OffsetOperand";
847 let ParserMatchClass = AM3OffsetAsmOperand;
848 let MIOperandInfo = (ops GPR, i32imm);
851 // ldstm_mode := {ia, ib, da, db}
853 def ldstm_mode : OptionalDefOperand<OtherVT, (ops i32), (ops (i32 1))> {
854 let EncoderMethod = "getLdStmModeOpValue";
855 let PrintMethod = "printLdStmModeOperand";
858 // addrmode5 := reg +/- imm8*4
860 def AddrMode5AsmOperand : AsmOperandClass { let Name = "AddrMode5"; }
861 def addrmode5 : Operand<i32>,
862 ComplexPattern<i32, 2, "SelectAddrMode5", []> {
863 let PrintMethod = "printAddrMode5Operand";
864 let EncoderMethod = "getAddrMode5OpValue";
865 let DecoderMethod = "DecodeAddrMode5Operand";
866 let ParserMatchClass = AddrMode5AsmOperand;
867 let MIOperandInfo = (ops GPR:$base, i32imm);
870 // addrmode6 := reg with optional alignment
872 def AddrMode6AsmOperand : AsmOperandClass { let Name = "AlignedMemory"; }
873 def addrmode6 : Operand<i32>,
874 ComplexPattern<i32, 2, "SelectAddrMode6", [], [SDNPWantParent]>{
875 let PrintMethod = "printAddrMode6Operand";
876 let MIOperandInfo = (ops GPR:$addr, i32imm:$align);
877 let EncoderMethod = "getAddrMode6AddressOpValue";
878 let DecoderMethod = "DecodeAddrMode6Operand";
879 let ParserMatchClass = AddrMode6AsmOperand;
882 def am6offset : Operand<i32>,
883 ComplexPattern<i32, 1, "SelectAddrMode6Offset",
884 [], [SDNPWantRoot]> {
885 let PrintMethod = "printAddrMode6OffsetOperand";
886 let MIOperandInfo = (ops GPR);
887 let EncoderMethod = "getAddrMode6OffsetOpValue";
888 let DecoderMethod = "DecodeGPRRegisterClass";
891 // Special version of addrmode6 to handle alignment encoding for VST1/VLD1
892 // (single element from one lane) for size 32.
893 def addrmode6oneL32 : Operand<i32>,
894 ComplexPattern<i32, 2, "SelectAddrMode6", [], [SDNPWantParent]>{
895 let PrintMethod = "printAddrMode6Operand";
896 let MIOperandInfo = (ops GPR:$addr, i32imm);
897 let EncoderMethod = "getAddrMode6OneLane32AddressOpValue";
900 // Special version of addrmode6 to handle alignment encoding for VLD-dup
901 // instructions, specifically VLD4-dup.
902 def addrmode6dup : Operand<i32>,
903 ComplexPattern<i32, 2, "SelectAddrMode6", [], [SDNPWantParent]>{
904 let PrintMethod = "printAddrMode6Operand";
905 let MIOperandInfo = (ops GPR:$addr, i32imm);
906 let EncoderMethod = "getAddrMode6DupAddressOpValue";
907 // FIXME: This is close, but not quite right. The alignment specifier is
909 let ParserMatchClass = AddrMode6AsmOperand;
912 // addrmodepc := pc + reg
914 def addrmodepc : Operand<i32>,
915 ComplexPattern<i32, 2, "SelectAddrModePC", []> {
916 let PrintMethod = "printAddrModePCOperand";
917 let MIOperandInfo = (ops GPR, i32imm);
920 // addr_offset_none := reg
922 def MemNoOffsetAsmOperand : AsmOperandClass { let Name = "MemNoOffset"; }
923 def addr_offset_none : Operand<i32>,
924 ComplexPattern<i32, 1, "SelectAddrOffsetNone", []> {
925 let PrintMethod = "printAddrMode7Operand";
926 let DecoderMethod = "DecodeAddrMode7Operand";
927 let ParserMatchClass = MemNoOffsetAsmOperand;
928 let MIOperandInfo = (ops GPR:$base);
931 def nohash_imm : Operand<i32> {
932 let PrintMethod = "printNoHashImmediate";
935 def CoprocNumAsmOperand : AsmOperandClass {
936 let Name = "CoprocNum";
937 let ParserMethod = "parseCoprocNumOperand";
939 def p_imm : Operand<i32> {
940 let PrintMethod = "printPImmediate";
941 let ParserMatchClass = CoprocNumAsmOperand;
942 let DecoderMethod = "DecodeCoprocessor";
945 def pf_imm : Operand<i32> {
946 let PrintMethod = "printPImmediate";
947 let ParserMatchClass = CoprocNumAsmOperand;
950 def CoprocRegAsmOperand : AsmOperandClass {
951 let Name = "CoprocReg";
952 let ParserMethod = "parseCoprocRegOperand";
954 def c_imm : Operand<i32> {
955 let PrintMethod = "printCImmediate";
956 let ParserMatchClass = CoprocRegAsmOperand;
958 def CoprocOptionAsmOperand : AsmOperandClass {
959 let Name = "CoprocOption";
960 let ParserMethod = "parseCoprocOptionOperand";
962 def coproc_option_imm : Operand<i32> {
963 let PrintMethod = "printCoprocOptionImm";
964 let ParserMatchClass = CoprocOptionAsmOperand;
967 //===----------------------------------------------------------------------===//
969 include "ARMInstrFormats.td"
971 //===----------------------------------------------------------------------===//
972 // Multiclass helpers...
975 /// AsI1_bin_irs - Defines a set of (op r, {so_imm|r|so_reg}) patterns for a
976 /// binop that produces a value.
977 let TwoOperandAliasConstraint = "$Rn = $Rd" in
978 multiclass AsI1_bin_irs<bits<4> opcod, string opc,
979 InstrItinClass iii, InstrItinClass iir, InstrItinClass iis,
980 PatFrag opnode, bit Commutable = 0> {
981 // The register-immediate version is re-materializable. This is useful
982 // in particular for taking the address of a local.
983 let isReMaterializable = 1 in {
984 def ri : AsI1<opcod, (outs GPR:$Rd), (ins GPR:$Rn, so_imm:$imm), DPFrm,
985 iii, opc, "\t$Rd, $Rn, $imm",
986 [(set GPR:$Rd, (opnode GPR:$Rn, so_imm:$imm))]> {
991 let Inst{19-16} = Rn;
992 let Inst{15-12} = Rd;
993 let Inst{11-0} = imm;
996 def rr : AsI1<opcod, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm), DPFrm,
997 iir, opc, "\t$Rd, $Rn, $Rm",
998 [(set GPR:$Rd, (opnode GPR:$Rn, GPR:$Rm))]> {
1003 let isCommutable = Commutable;
1004 let Inst{19-16} = Rn;
1005 let Inst{15-12} = Rd;
1006 let Inst{11-4} = 0b00000000;
1010 def rsi : AsI1<opcod, (outs GPR:$Rd),
1011 (ins GPR:$Rn, so_reg_imm:$shift), DPSoRegImmFrm,
1012 iis, opc, "\t$Rd, $Rn, $shift",
1013 [(set GPR:$Rd, (opnode GPR:$Rn, so_reg_imm:$shift))]> {
1018 let Inst{19-16} = Rn;
1019 let Inst{15-12} = Rd;
1020 let Inst{11-5} = shift{11-5};
1022 let Inst{3-0} = shift{3-0};
1025 def rsr : AsI1<opcod, (outs GPR:$Rd),
1026 (ins GPR:$Rn, so_reg_reg:$shift), DPSoRegRegFrm,
1027 iis, opc, "\t$Rd, $Rn, $shift",
1028 [(set GPR:$Rd, (opnode GPR:$Rn, so_reg_reg:$shift))]> {
1033 let Inst{19-16} = Rn;
1034 let Inst{15-12} = Rd;
1035 let Inst{11-8} = shift{11-8};
1037 let Inst{6-5} = shift{6-5};
1039 let Inst{3-0} = shift{3-0};
1043 /// AsI1_rbin_irs - Same as AsI1_bin_irs except the order of operands are
1044 /// reversed. The 'rr' form is only defined for the disassembler; for codegen
1045 /// it is equivalent to the AsI1_bin_irs counterpart.
1046 let TwoOperandAliasConstraint = "$Rn = $Rd" in
1047 multiclass AsI1_rbin_irs<bits<4> opcod, string opc,
1048 InstrItinClass iii, InstrItinClass iir, InstrItinClass iis,
1049 PatFrag opnode, bit Commutable = 0> {
1050 // The register-immediate version is re-materializable. This is useful
1051 // in particular for taking the address of a local.
1052 let isReMaterializable = 1 in {
1053 def ri : AsI1<opcod, (outs GPR:$Rd), (ins GPR:$Rn, so_imm:$imm), DPFrm,
1054 iii, opc, "\t$Rd, $Rn, $imm",
1055 [(set GPR:$Rd, (opnode so_imm:$imm, GPR:$Rn))]> {
1060 let Inst{19-16} = Rn;
1061 let Inst{15-12} = Rd;
1062 let Inst{11-0} = imm;
1065 def rr : AsI1<opcod, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm), DPFrm,
1066 iir, opc, "\t$Rd, $Rn, $Rm",
1067 [/* pattern left blank */]> {
1071 let Inst{11-4} = 0b00000000;
1074 let Inst{15-12} = Rd;
1075 let Inst{19-16} = Rn;
1078 def rsi : AsI1<opcod, (outs GPR:$Rd),
1079 (ins GPR:$Rn, so_reg_imm:$shift), DPSoRegImmFrm,
1080 iis, opc, "\t$Rd, $Rn, $shift",
1081 [(set GPR:$Rd, (opnode so_reg_imm:$shift, GPR:$Rn))]> {
1086 let Inst{19-16} = Rn;
1087 let Inst{15-12} = Rd;
1088 let Inst{11-5} = shift{11-5};
1090 let Inst{3-0} = shift{3-0};
1093 def rsr : AsI1<opcod, (outs GPR:$Rd),
1094 (ins GPR:$Rn, so_reg_reg:$shift), DPSoRegRegFrm,
1095 iis, opc, "\t$Rd, $Rn, $shift",
1096 [(set GPR:$Rd, (opnode so_reg_reg:$shift, GPR:$Rn))]> {
1101 let Inst{19-16} = Rn;
1102 let Inst{15-12} = Rd;
1103 let Inst{11-8} = shift{11-8};
1105 let Inst{6-5} = shift{6-5};
1107 let Inst{3-0} = shift{3-0};
1111 /// AsI1_bin_s_irs - Same as AsI1_bin_irs except it sets the 's' bit by default.
1113 /// These opcodes will be converted to the real non-S opcodes by
1114 /// AdjustInstrPostInstrSelection after giving them an optional CPSR operand.
1115 let hasPostISelHook = 1, Defs = [CPSR] in {
1116 multiclass AsI1_bin_s_irs<InstrItinClass iii, InstrItinClass iir,
1117 InstrItinClass iis, PatFrag opnode,
1118 bit Commutable = 0> {
1119 def ri : ARMPseudoInst<(outs GPR:$Rd), (ins GPR:$Rn, so_imm:$imm, pred:$p),
1121 [(set GPR:$Rd, CPSR, (opnode GPR:$Rn, so_imm:$imm))]>;
1123 def rr : ARMPseudoInst<(outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm, pred:$p),
1125 [(set GPR:$Rd, CPSR, (opnode GPR:$Rn, GPR:$Rm))]> {
1126 let isCommutable = Commutable;
1128 def rsi : ARMPseudoInst<(outs GPR:$Rd),
1129 (ins GPR:$Rn, so_reg_imm:$shift, pred:$p),
1131 [(set GPR:$Rd, CPSR, (opnode GPR:$Rn,
1132 so_reg_imm:$shift))]>;
1134 def rsr : ARMPseudoInst<(outs GPR:$Rd),
1135 (ins GPR:$Rn, so_reg_reg:$shift, pred:$p),
1137 [(set GPR:$Rd, CPSR, (opnode GPR:$Rn,
1138 so_reg_reg:$shift))]>;
1142 /// AsI1_rbin_s_is - Same as AsI1_bin_s_irs, except selection DAG
1143 /// operands are reversed.
1144 let hasPostISelHook = 1, Defs = [CPSR] in {
1145 multiclass AsI1_rbin_s_is<InstrItinClass iii, InstrItinClass iir,
1146 InstrItinClass iis, PatFrag opnode,
1147 bit Commutable = 0> {
1148 def ri : ARMPseudoInst<(outs GPR:$Rd), (ins GPR:$Rn, so_imm:$imm, pred:$p),
1150 [(set GPR:$Rd, CPSR, (opnode so_imm:$imm, GPR:$Rn))]>;
1152 def rsi : ARMPseudoInst<(outs GPR:$Rd),
1153 (ins GPR:$Rn, so_reg_imm:$shift, pred:$p),
1155 [(set GPR:$Rd, CPSR, (opnode so_reg_imm:$shift,
1158 def rsr : ARMPseudoInst<(outs GPR:$Rd),
1159 (ins GPR:$Rn, so_reg_reg:$shift, pred:$p),
1161 [(set GPR:$Rd, CPSR, (opnode so_reg_reg:$shift,
1166 /// AI1_cmp_irs - Defines a set of (op r, {so_imm|r|so_reg}) cmp / test
1167 /// patterns. Similar to AsI1_bin_irs except the instruction does not produce
1168 /// a explicit result, only implicitly set CPSR.
1169 let isCompare = 1, Defs = [CPSR] in {
1170 multiclass AI1_cmp_irs<bits<4> opcod, string opc,
1171 InstrItinClass iii, InstrItinClass iir, InstrItinClass iis,
1172 PatFrag opnode, bit Commutable = 0> {
1173 def ri : AI1<opcod, (outs), (ins GPR:$Rn, so_imm:$imm), DPFrm, iii,
1175 [(opnode GPR:$Rn, so_imm:$imm)]> {
1180 let Inst{19-16} = Rn;
1181 let Inst{15-12} = 0b0000;
1182 let Inst{11-0} = imm;
1184 let Unpredictable{15-12} = 0b1111;
1186 def rr : AI1<opcod, (outs), (ins GPR:$Rn, GPR:$Rm), DPFrm, iir,
1188 [(opnode GPR:$Rn, GPR:$Rm)]> {
1191 let isCommutable = Commutable;
1194 let Inst{19-16} = Rn;
1195 let Inst{15-12} = 0b0000;
1196 let Inst{11-4} = 0b00000000;
1199 let Unpredictable{15-12} = 0b1111;
1201 def rsi : AI1<opcod, (outs),
1202 (ins GPR:$Rn, so_reg_imm:$shift), DPSoRegImmFrm, iis,
1203 opc, "\t$Rn, $shift",
1204 [(opnode GPR:$Rn, so_reg_imm:$shift)]> {
1209 let Inst{19-16} = Rn;
1210 let Inst{15-12} = 0b0000;
1211 let Inst{11-5} = shift{11-5};
1213 let Inst{3-0} = shift{3-0};
1215 let Unpredictable{15-12} = 0b1111;
1217 def rsr : AI1<opcod, (outs),
1218 (ins GPRnopc:$Rn, so_reg_reg:$shift), DPSoRegRegFrm, iis,
1219 opc, "\t$Rn, $shift",
1220 [(opnode GPRnopc:$Rn, so_reg_reg:$shift)]> {
1225 let Inst{19-16} = Rn;
1226 let Inst{15-12} = 0b0000;
1227 let Inst{11-8} = shift{11-8};
1229 let Inst{6-5} = shift{6-5};
1231 let Inst{3-0} = shift{3-0};
1233 let Unpredictable{15-12} = 0b1111;
1239 /// AI_ext_rrot - A unary operation with two forms: one whose operand is a
1240 /// register and one whose operand is a register rotated by 8/16/24.
1241 /// FIXME: Remove the 'r' variant. Its rot_imm is zero.
1242 class AI_ext_rrot<bits<8> opcod, string opc, PatFrag opnode>
1243 : AExtI<opcod, (outs GPRnopc:$Rd), (ins GPRnopc:$Rm, rot_imm:$rot),
1244 IIC_iEXTr, opc, "\t$Rd, $Rm$rot",
1245 [(set GPRnopc:$Rd, (opnode (rotr GPRnopc:$Rm, rot_imm:$rot)))]>,
1246 Requires<[IsARM, HasV6]> {
1250 let Inst{19-16} = 0b1111;
1251 let Inst{15-12} = Rd;
1252 let Inst{11-10} = rot;
1256 class AI_ext_rrot_np<bits<8> opcod, string opc>
1257 : AExtI<opcod, (outs GPRnopc:$Rd), (ins GPRnopc:$Rm, rot_imm:$rot),
1258 IIC_iEXTr, opc, "\t$Rd, $Rm$rot", []>,
1259 Requires<[IsARM, HasV6]> {
1261 let Inst{19-16} = 0b1111;
1262 let Inst{11-10} = rot;
1265 /// AI_exta_rrot - A binary operation with two forms: one whose operand is a
1266 /// register and one whose operand is a register rotated by 8/16/24.
1267 class AI_exta_rrot<bits<8> opcod, string opc, PatFrag opnode>
1268 : AExtI<opcod, (outs GPRnopc:$Rd), (ins GPR:$Rn, GPRnopc:$Rm, rot_imm:$rot),
1269 IIC_iEXTAr, opc, "\t$Rd, $Rn, $Rm$rot",
1270 [(set GPRnopc:$Rd, (opnode GPR:$Rn,
1271 (rotr GPRnopc:$Rm, rot_imm:$rot)))]>,
1272 Requires<[IsARM, HasV6]> {
1277 let Inst{19-16} = Rn;
1278 let Inst{15-12} = Rd;
1279 let Inst{11-10} = rot;
1280 let Inst{9-4} = 0b000111;
1284 class AI_exta_rrot_np<bits<8> opcod, string opc>
1285 : AExtI<opcod, (outs GPRnopc:$Rd), (ins GPR:$Rn, GPRnopc:$Rm, rot_imm:$rot),
1286 IIC_iEXTAr, opc, "\t$Rd, $Rn, $Rm$rot", []>,
1287 Requires<[IsARM, HasV6]> {
1290 let Inst{19-16} = Rn;
1291 let Inst{11-10} = rot;
1294 /// AI1_adde_sube_irs - Define instructions and patterns for adde and sube.
1295 let TwoOperandAliasConstraint = "$Rn = $Rd" in
1296 multiclass AI1_adde_sube_irs<bits<4> opcod, string opc, PatFrag opnode,
1297 bit Commutable = 0> {
1298 let hasPostISelHook = 1, Defs = [CPSR], Uses = [CPSR] in {
1299 def ri : AsI1<opcod, (outs GPR:$Rd), (ins GPR:$Rn, so_imm:$imm),
1300 DPFrm, IIC_iALUi, opc, "\t$Rd, $Rn, $imm",
1301 [(set GPR:$Rd, CPSR, (opnode GPR:$Rn, so_imm:$imm, CPSR))]>,
1307 let Inst{15-12} = Rd;
1308 let Inst{19-16} = Rn;
1309 let Inst{11-0} = imm;
1311 def rr : AsI1<opcod, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm),
1312 DPFrm, IIC_iALUr, opc, "\t$Rd, $Rn, $Rm",
1313 [(set GPR:$Rd, CPSR, (opnode GPR:$Rn, GPR:$Rm, CPSR))]>,
1318 let Inst{11-4} = 0b00000000;
1320 let isCommutable = Commutable;
1322 let Inst{15-12} = Rd;
1323 let Inst{19-16} = Rn;
1325 def rsi : AsI1<opcod, (outs GPR:$Rd),
1326 (ins GPR:$Rn, so_reg_imm:$shift),
1327 DPSoRegImmFrm, IIC_iALUsr, opc, "\t$Rd, $Rn, $shift",
1328 [(set GPR:$Rd, CPSR, (opnode GPR:$Rn, so_reg_imm:$shift, CPSR))]>,
1334 let Inst{19-16} = Rn;
1335 let Inst{15-12} = Rd;
1336 let Inst{11-5} = shift{11-5};
1338 let Inst{3-0} = shift{3-0};
1340 def rsr : AsI1<opcod, (outs GPRnopc:$Rd),
1341 (ins GPRnopc:$Rn, so_reg_reg:$shift),
1342 DPSoRegRegFrm, IIC_iALUsr, opc, "\t$Rd, $Rn, $shift",
1343 [(set GPRnopc:$Rd, CPSR,
1344 (opnode GPRnopc:$Rn, so_reg_reg:$shift, CPSR))]>,
1350 let Inst{19-16} = Rn;
1351 let Inst{15-12} = Rd;
1352 let Inst{11-8} = shift{11-8};
1354 let Inst{6-5} = shift{6-5};
1356 let Inst{3-0} = shift{3-0};
1361 /// AI1_rsc_irs - Define instructions and patterns for rsc
1362 let TwoOperandAliasConstraint = "$Rn = $Rd" in
1363 multiclass AI1_rsc_irs<bits<4> opcod, string opc, PatFrag opnode> {
1364 let hasPostISelHook = 1, Defs = [CPSR], Uses = [CPSR] in {
1365 def ri : AsI1<opcod, (outs GPR:$Rd), (ins GPR:$Rn, so_imm:$imm),
1366 DPFrm, IIC_iALUi, opc, "\t$Rd, $Rn, $imm",
1367 [(set GPR:$Rd, CPSR, (opnode so_imm:$imm, GPR:$Rn, CPSR))]>,
1373 let Inst{15-12} = Rd;
1374 let Inst{19-16} = Rn;
1375 let Inst{11-0} = imm;
1377 def rr : AsI1<opcod, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm),
1378 DPFrm, IIC_iALUr, opc, "\t$Rd, $Rn, $Rm",
1379 [/* pattern left blank */]> {
1383 let Inst{11-4} = 0b00000000;
1386 let Inst{15-12} = Rd;
1387 let Inst{19-16} = Rn;
1389 def rsi : AsI1<opcod, (outs GPR:$Rd), (ins GPR:$Rn, so_reg_imm:$shift),
1390 DPSoRegImmFrm, IIC_iALUsr, opc, "\t$Rd, $Rn, $shift",
1391 [(set GPR:$Rd, CPSR, (opnode so_reg_imm:$shift, GPR:$Rn, CPSR))]>,
1397 let Inst{19-16} = Rn;
1398 let Inst{15-12} = Rd;
1399 let Inst{11-5} = shift{11-5};
1401 let Inst{3-0} = shift{3-0};
1403 def rsr : AsI1<opcod, (outs GPR:$Rd), (ins GPR:$Rn, so_reg_reg:$shift),
1404 DPSoRegRegFrm, IIC_iALUsr, opc, "\t$Rd, $Rn, $shift",
1405 [(set GPR:$Rd, CPSR, (opnode so_reg_reg:$shift, GPR:$Rn, CPSR))]>,
1411 let Inst{19-16} = Rn;
1412 let Inst{15-12} = Rd;
1413 let Inst{11-8} = shift{11-8};
1415 let Inst{6-5} = shift{6-5};
1417 let Inst{3-0} = shift{3-0};
1422 let canFoldAsLoad = 1, isReMaterializable = 1 in {
1423 multiclass AI_ldr1<bit isByte, string opc, InstrItinClass iii,
1424 InstrItinClass iir, PatFrag opnode> {
1425 // Note: We use the complex addrmode_imm12 rather than just an input
1426 // GPR and a constrained immediate so that we can use this to match
1427 // frame index references and avoid matching constant pool references.
1428 def i12: AI2ldst<0b010, 1, isByte, (outs GPR:$Rt), (ins addrmode_imm12:$addr),
1429 AddrMode_i12, LdFrm, iii, opc, "\t$Rt, $addr",
1430 [(set GPR:$Rt, (opnode addrmode_imm12:$addr))]> {
1433 let Inst{23} = addr{12}; // U (add = ('U' == 1))
1434 let Inst{19-16} = addr{16-13}; // Rn
1435 let Inst{15-12} = Rt;
1436 let Inst{11-0} = addr{11-0}; // imm12
1438 def rs : AI2ldst<0b011, 1, isByte, (outs GPR:$Rt), (ins ldst_so_reg:$shift),
1439 AddrModeNone, LdFrm, iir, opc, "\t$Rt, $shift",
1440 [(set GPR:$Rt, (opnode ldst_so_reg:$shift))]> {
1443 let shift{4} = 0; // Inst{4} = 0
1444 let Inst{23} = shift{12}; // U (add = ('U' == 1))
1445 let Inst{19-16} = shift{16-13}; // Rn
1446 let Inst{15-12} = Rt;
1447 let Inst{11-0} = shift{11-0};
1452 let canFoldAsLoad = 1, isReMaterializable = 1 in {
1453 multiclass AI_ldr1nopc<bit isByte, string opc, InstrItinClass iii,
1454 InstrItinClass iir, PatFrag opnode> {
1455 // Note: We use the complex addrmode_imm12 rather than just an input
1456 // GPR and a constrained immediate so that we can use this to match
1457 // frame index references and avoid matching constant pool references.
1458 def i12: AI2ldst<0b010, 1, isByte, (outs GPRnopc:$Rt),
1459 (ins addrmode_imm12:$addr),
1460 AddrMode_i12, LdFrm, iii, opc, "\t$Rt, $addr",
1461 [(set GPRnopc:$Rt, (opnode addrmode_imm12:$addr))]> {
1464 let Inst{23} = addr{12}; // U (add = ('U' == 1))
1465 let Inst{19-16} = addr{16-13}; // Rn
1466 let Inst{15-12} = Rt;
1467 let Inst{11-0} = addr{11-0}; // imm12
1469 def rs : AI2ldst<0b011, 1, isByte, (outs GPRnopc:$Rt),
1470 (ins ldst_so_reg:$shift),
1471 AddrModeNone, LdFrm, iir, opc, "\t$Rt, $shift",
1472 [(set GPRnopc:$Rt, (opnode ldst_so_reg:$shift))]> {
1475 let shift{4} = 0; // Inst{4} = 0
1476 let Inst{23} = shift{12}; // U (add = ('U' == 1))
1477 let Inst{19-16} = shift{16-13}; // Rn
1478 let Inst{15-12} = Rt;
1479 let Inst{11-0} = shift{11-0};
1485 multiclass AI_str1<bit isByte, string opc, InstrItinClass iii,
1486 InstrItinClass iir, PatFrag opnode> {
1487 // Note: We use the complex addrmode_imm12 rather than just an input
1488 // GPR and a constrained immediate so that we can use this to match
1489 // frame index references and avoid matching constant pool references.
1490 def i12 : AI2ldst<0b010, 0, isByte, (outs),
1491 (ins GPR:$Rt, addrmode_imm12:$addr),
1492 AddrMode_i12, StFrm, iii, opc, "\t$Rt, $addr",
1493 [(opnode GPR:$Rt, addrmode_imm12:$addr)]> {
1496 let Inst{23} = addr{12}; // U (add = ('U' == 1))
1497 let Inst{19-16} = addr{16-13}; // Rn
1498 let Inst{15-12} = Rt;
1499 let Inst{11-0} = addr{11-0}; // imm12
1501 def rs : AI2ldst<0b011, 0, isByte, (outs), (ins GPR:$Rt, ldst_so_reg:$shift),
1502 AddrModeNone, StFrm, iir, opc, "\t$Rt, $shift",
1503 [(opnode GPR:$Rt, ldst_so_reg:$shift)]> {
1506 let shift{4} = 0; // Inst{4} = 0
1507 let Inst{23} = shift{12}; // U (add = ('U' == 1))
1508 let Inst{19-16} = shift{16-13}; // Rn
1509 let Inst{15-12} = Rt;
1510 let Inst{11-0} = shift{11-0};
1514 multiclass AI_str1nopc<bit isByte, string opc, InstrItinClass iii,
1515 InstrItinClass iir, PatFrag opnode> {
1516 // Note: We use the complex addrmode_imm12 rather than just an input
1517 // GPR and a constrained immediate so that we can use this to match
1518 // frame index references and avoid matching constant pool references.
1519 def i12 : AI2ldst<0b010, 0, isByte, (outs),
1520 (ins GPRnopc:$Rt, addrmode_imm12:$addr),
1521 AddrMode_i12, StFrm, iii, opc, "\t$Rt, $addr",
1522 [(opnode GPRnopc:$Rt, addrmode_imm12:$addr)]> {
1525 let Inst{23} = addr{12}; // U (add = ('U' == 1))
1526 let Inst{19-16} = addr{16-13}; // Rn
1527 let Inst{15-12} = Rt;
1528 let Inst{11-0} = addr{11-0}; // imm12
1530 def rs : AI2ldst<0b011, 0, isByte, (outs),
1531 (ins GPRnopc:$Rt, ldst_so_reg:$shift),
1532 AddrModeNone, StFrm, iir, opc, "\t$Rt, $shift",
1533 [(opnode GPRnopc:$Rt, ldst_so_reg:$shift)]> {
1536 let shift{4} = 0; // Inst{4} = 0
1537 let Inst{23} = shift{12}; // U (add = ('U' == 1))
1538 let Inst{19-16} = shift{16-13}; // Rn
1539 let Inst{15-12} = Rt;
1540 let Inst{11-0} = shift{11-0};
1545 //===----------------------------------------------------------------------===//
1547 //===----------------------------------------------------------------------===//
1549 //===----------------------------------------------------------------------===//
1550 // Miscellaneous Instructions.
1553 /// CONSTPOOL_ENTRY - This instruction represents a floating constant pool in
1554 /// the function. The first operand is the ID# for this instruction, the second
1555 /// is the index into the MachineConstantPool that this is, the third is the
1556 /// size in bytes of this constant pool entry.
1557 let neverHasSideEffects = 1, isNotDuplicable = 1 in
1558 def CONSTPOOL_ENTRY :
1559 PseudoInst<(outs), (ins cpinst_operand:$instid, cpinst_operand:$cpidx,
1560 i32imm:$size), NoItinerary, []>;
1562 // FIXME: Marking these as hasSideEffects is necessary to prevent machine DCE
1563 // from removing one half of the matched pairs. That breaks PEI, which assumes
1564 // these will always be in pairs, and asserts if it finds otherwise. Better way?
1565 let Defs = [SP], Uses = [SP], hasSideEffects = 1 in {
1566 def ADJCALLSTACKUP :
1567 PseudoInst<(outs), (ins i32imm:$amt1, i32imm:$amt2, pred:$p), NoItinerary,
1568 [(ARMcallseq_end timm:$amt1, timm:$amt2)]>;
1570 def ADJCALLSTACKDOWN :
1571 PseudoInst<(outs), (ins i32imm:$amt, pred:$p), NoItinerary,
1572 [(ARMcallseq_start timm:$amt)]>;
1575 // Atomic pseudo-insts which will be lowered to ldrexd/strexd loops.
1576 // (These pseudos use a hand-written selection code).
1577 let usesCustomInserter = 1, Defs = [CPSR], mayLoad = 1, mayStore = 1 in {
1578 def ATOMOR6432 : PseudoInst<(outs GPR:$dst1, GPR:$dst2),
1579 (ins GPR:$addr, GPR:$src1, GPR:$src2),
1581 def ATOMXOR6432 : PseudoInst<(outs GPR:$dst1, GPR:$dst2),
1582 (ins GPR:$addr, GPR:$src1, GPR:$src2),
1584 def ATOMADD6432 : PseudoInst<(outs GPR:$dst1, GPR:$dst2),
1585 (ins GPR:$addr, GPR:$src1, GPR:$src2),
1587 def ATOMSUB6432 : PseudoInst<(outs GPR:$dst1, GPR:$dst2),
1588 (ins GPR:$addr, GPR:$src1, GPR:$src2),
1590 def ATOMNAND6432 : PseudoInst<(outs GPR:$dst1, GPR:$dst2),
1591 (ins GPR:$addr, GPR:$src1, GPR:$src2),
1593 def ATOMAND6432 : PseudoInst<(outs GPR:$dst1, GPR:$dst2),
1594 (ins GPR:$addr, GPR:$src1, GPR:$src2),
1596 def ATOMSWAP6432 : PseudoInst<(outs GPR:$dst1, GPR:$dst2),
1597 (ins GPR:$addr, GPR:$src1, GPR:$src2),
1599 def ATOMCMPXCHG6432 : PseudoInst<(outs GPR:$dst1, GPR:$dst2),
1600 (ins GPR:$addr, GPR:$cmp1, GPR:$cmp2,
1601 GPR:$set1, GPR:$set2),
1605 def HINT : AI<(outs), (ins imm0_255:$imm), MiscFrm, NoItinerary,
1606 "hint", "\t$imm", []>, Requires<[IsARM, HasV6]> {
1608 let Inst{27-8} = 0b00110010000011110000;
1609 let Inst{7-0} = imm;
1612 def : InstAlias<"nop$p", (HINT 0, pred:$p)>, Requires<[IsARM, HasV6T2]>;
1613 def : InstAlias<"yield$p", (HINT 1, pred:$p)>, Requires<[IsARM, HasV6T2]>;
1614 def : InstAlias<"wfe$p", (HINT 2, pred:$p)>, Requires<[IsARM, HasV6T2]>;
1615 def : InstAlias<"wfi$p", (HINT 3, pred:$p)>, Requires<[IsARM, HasV6T2]>;
1616 def : InstAlias<"sev$p", (HINT 4, pred:$p)>, Requires<[IsARM, HasV6T2]>;
1618 def SEL : AI<(outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm), DPFrm, NoItinerary, "sel",
1619 "\t$Rd, $Rn, $Rm", []>, Requires<[IsARM, HasV6]> {
1624 let Inst{15-12} = Rd;
1625 let Inst{19-16} = Rn;
1626 let Inst{27-20} = 0b01101000;
1627 let Inst{7-4} = 0b1011;
1628 let Inst{11-8} = 0b1111;
1629 let Unpredictable{11-8} = 0b1111;
1632 // The 16-bit operand $val can be used by a debugger to store more information
1633 // about the breakpoint.
1634 def BKPT : AI<(outs), (ins imm0_65535:$val), MiscFrm, NoItinerary,
1635 "bkpt", "\t$val", []>, Requires<[IsARM]> {
1637 let Inst{3-0} = val{3-0};
1638 let Inst{19-8} = val{15-4};
1639 let Inst{27-20} = 0b00010010;
1640 let Inst{7-4} = 0b0111;
1643 // Change Processor State
1644 // FIXME: We should use InstAlias to handle the optional operands.
1645 class CPS<dag iops, string asm_ops>
1646 : AXI<(outs), iops, MiscFrm, NoItinerary, !strconcat("cps", asm_ops),
1647 []>, Requires<[IsARM]> {
1653 let Inst{31-28} = 0b1111;
1654 let Inst{27-20} = 0b00010000;
1655 let Inst{19-18} = imod;
1656 let Inst{17} = M; // Enabled if mode is set;
1657 let Inst{16-9} = 0b00000000;
1658 let Inst{8-6} = iflags;
1660 let Inst{4-0} = mode;
1663 let DecoderMethod = "DecodeCPSInstruction" in {
1665 def CPS3p : CPS<(ins imod_op:$imod, iflags_op:$iflags, imm0_31:$mode),
1666 "$imod\t$iflags, $mode">;
1667 let mode = 0, M = 0 in
1668 def CPS2p : CPS<(ins imod_op:$imod, iflags_op:$iflags), "$imod\t$iflags">;
1670 let imod = 0, iflags = 0, M = 1 in
1671 def CPS1p : CPS<(ins imm0_31:$mode), "\t$mode">;
1674 // Preload signals the memory system of possible future data/instruction access.
1675 multiclass APreLoad<bits<1> read, bits<1> data, string opc> {
1677 def i12 : AXI<(outs), (ins addrmode_imm12:$addr), MiscFrm, IIC_Preload,
1678 !strconcat(opc, "\t$addr"),
1679 [(ARMPreload addrmode_imm12:$addr, (i32 read), (i32 data))]> {
1682 let Inst{31-26} = 0b111101;
1683 let Inst{25} = 0; // 0 for immediate form
1684 let Inst{24} = data;
1685 let Inst{23} = addr{12}; // U (add = ('U' == 1))
1686 let Inst{22} = read;
1687 let Inst{21-20} = 0b01;
1688 let Inst{19-16} = addr{16-13}; // Rn
1689 let Inst{15-12} = 0b1111;
1690 let Inst{11-0} = addr{11-0}; // imm12
1693 def rs : AXI<(outs), (ins ldst_so_reg:$shift), MiscFrm, IIC_Preload,
1694 !strconcat(opc, "\t$shift"),
1695 [(ARMPreload ldst_so_reg:$shift, (i32 read), (i32 data))]> {
1697 let Inst{31-26} = 0b111101;
1698 let Inst{25} = 1; // 1 for register form
1699 let Inst{24} = data;
1700 let Inst{23} = shift{12}; // U (add = ('U' == 1))
1701 let Inst{22} = read;
1702 let Inst{21-20} = 0b01;
1703 let Inst{19-16} = shift{16-13}; // Rn
1704 let Inst{15-12} = 0b1111;
1705 let Inst{11-0} = shift{11-0};
1710 defm PLD : APreLoad<1, 1, "pld">, Requires<[IsARM]>;
1711 defm PLDW : APreLoad<0, 1, "pldw">, Requires<[IsARM,HasV7,HasMP]>;
1712 defm PLI : APreLoad<1, 0, "pli">, Requires<[IsARM,HasV7]>;
1714 def SETEND : AXI<(outs), (ins setend_op:$end), MiscFrm, NoItinerary,
1715 "setend\t$end", []>, Requires<[IsARM]> {
1717 let Inst{31-10} = 0b1111000100000001000000;
1722 def DBG : AI<(outs), (ins imm0_15:$opt), MiscFrm, NoItinerary, "dbg", "\t$opt",
1723 []>, Requires<[IsARM, HasV7]> {
1725 let Inst{27-4} = 0b001100100000111100001111;
1726 let Inst{3-0} = opt;
1729 // A5.4 Permanently UNDEFINED instructions.
1730 let isBarrier = 1, isTerminator = 1 in
1731 def TRAP : AXI<(outs), (ins), MiscFrm, NoItinerary,
1734 let Inst = 0xe7ffdefe;
1737 // Address computation and loads and stores in PIC mode.
1738 let isNotDuplicable = 1 in {
1739 def PICADD : ARMPseudoInst<(outs GPR:$dst), (ins GPR:$a, pclabel:$cp, pred:$p),
1741 [(set GPR:$dst, (ARMpic_add GPR:$a, imm:$cp))]>;
1743 let AddedComplexity = 10 in {
1744 def PICLDR : ARMPseudoInst<(outs GPR:$dst), (ins addrmodepc:$addr, pred:$p),
1746 [(set GPR:$dst, (load addrmodepc:$addr))]>;
1748 def PICLDRH : ARMPseudoInst<(outs GPR:$Rt), (ins addrmodepc:$addr, pred:$p),
1750 [(set GPR:$Rt, (zextloadi16 addrmodepc:$addr))]>;
1752 def PICLDRB : ARMPseudoInst<(outs GPR:$Rt), (ins addrmodepc:$addr, pred:$p),
1754 [(set GPR:$Rt, (zextloadi8 addrmodepc:$addr))]>;
1756 def PICLDRSH : ARMPseudoInst<(outs GPR:$Rt), (ins addrmodepc:$addr, pred:$p),
1758 [(set GPR:$Rt, (sextloadi16 addrmodepc:$addr))]>;
1760 def PICLDRSB : ARMPseudoInst<(outs GPR:$Rt), (ins addrmodepc:$addr, pred:$p),
1762 [(set GPR:$Rt, (sextloadi8 addrmodepc:$addr))]>;
1764 let AddedComplexity = 10 in {
1765 def PICSTR : ARMPseudoInst<(outs), (ins GPR:$src, addrmodepc:$addr, pred:$p),
1766 4, IIC_iStore_r, [(store GPR:$src, addrmodepc:$addr)]>;
1768 def PICSTRH : ARMPseudoInst<(outs), (ins GPR:$src, addrmodepc:$addr, pred:$p),
1769 4, IIC_iStore_bh_r, [(truncstorei16 GPR:$src,
1770 addrmodepc:$addr)]>;
1772 def PICSTRB : ARMPseudoInst<(outs), (ins GPR:$src, addrmodepc:$addr, pred:$p),
1773 4, IIC_iStore_bh_r, [(truncstorei8 GPR:$src, addrmodepc:$addr)]>;
1775 } // isNotDuplicable = 1
1778 // LEApcrel - Load a pc-relative address into a register without offending the
1780 let neverHasSideEffects = 1, isReMaterializable = 1 in
1781 // The 'adr' mnemonic encodes differently if the label is before or after
1782 // the instruction. The {24-21} opcode bits are set by the fixup, as we don't
1783 // know until then which form of the instruction will be used.
1784 def ADR : AI1<{0,?,?,0}, (outs GPR:$Rd), (ins adrlabel:$label),
1785 MiscFrm, IIC_iALUi, "adr", "\t$Rd, $label", []> {
1788 let Inst{27-25} = 0b001;
1790 let Inst{23-22} = label{13-12};
1793 let Inst{19-16} = 0b1111;
1794 let Inst{15-12} = Rd;
1795 let Inst{11-0} = label{11-0};
1798 let hasSideEffects = 1 in {
1799 def LEApcrel : ARMPseudoInst<(outs GPR:$Rd), (ins i32imm:$label, pred:$p),
1802 def LEApcrelJT : ARMPseudoInst<(outs GPR:$Rd),
1803 (ins i32imm:$label, nohash_imm:$id, pred:$p),
1807 //===----------------------------------------------------------------------===//
1808 // Control Flow Instructions.
1811 let isReturn = 1, isTerminator = 1, isBarrier = 1 in {
1813 def BX_RET : AI<(outs), (ins), BrMiscFrm, IIC_Br,
1814 "bx", "\tlr", [(ARMretflag)]>,
1815 Requires<[IsARM, HasV4T]> {
1816 let Inst{27-0} = 0b0001001011111111111100011110;
1820 def MOVPCLR : AI<(outs), (ins), BrMiscFrm, IIC_Br,
1821 "mov", "\tpc, lr", [(ARMretflag)]>,
1822 Requires<[IsARM, NoV4T]> {
1823 let Inst{27-0} = 0b0001101000001111000000001110;
1827 // Indirect branches
1828 let isBranch = 1, isTerminator = 1, isBarrier = 1, isIndirectBranch = 1 in {
1830 def BX : AXI<(outs), (ins GPR:$dst), BrMiscFrm, IIC_Br, "bx\t$dst",
1831 [(brind GPR:$dst)]>,
1832 Requires<[IsARM, HasV4T]> {
1834 let Inst{31-4} = 0b1110000100101111111111110001;
1835 let Inst{3-0} = dst;
1838 def BX_pred : AI<(outs), (ins GPR:$dst), BrMiscFrm, IIC_Br,
1839 "bx", "\t$dst", [/* pattern left blank */]>,
1840 Requires<[IsARM, HasV4T]> {
1842 let Inst{27-4} = 0b000100101111111111110001;
1843 let Inst{3-0} = dst;
1847 // SP is marked as a use to prevent stack-pointer assignments that appear
1848 // immediately before calls from potentially appearing dead.
1850 // FIXME: Do we really need a non-predicated version? If so, it should
1851 // at least be a pseudo instruction expanding to the predicated version
1852 // at MC lowering time.
1853 Defs = [LR], Uses = [SP] in {
1854 def BL : ABXI<0b1011, (outs), (ins bl_target:$func),
1855 IIC_Br, "bl\t$func",
1856 [(ARMcall tglobaladdr:$func)]>,
1858 let Inst{31-28} = 0b1110;
1860 let Inst{23-0} = func;
1861 let DecoderMethod = "DecodeBranchImmInstruction";
1864 def BL_pred : ABI<0b1011, (outs), (ins bl_target:$func),
1865 IIC_Br, "bl", "\t$func",
1866 [(ARMcall_pred tglobaladdr:$func)]>,
1869 let Inst{23-0} = func;
1870 let DecoderMethod = "DecodeBranchImmInstruction";
1874 def BLX : AXI<(outs), (ins GPR:$func), BrMiscFrm,
1875 IIC_Br, "blx\t$func",
1876 [(ARMcall GPR:$func)]>,
1877 Requires<[IsARM, HasV5T]> {
1879 let Inst{31-4} = 0b1110000100101111111111110011;
1880 let Inst{3-0} = func;
1883 def BLX_pred : AI<(outs), (ins GPR:$func), BrMiscFrm,
1884 IIC_Br, "blx", "\t$func",
1885 [(ARMcall_pred GPR:$func)]>,
1886 Requires<[IsARM, HasV5T]> {
1888 let Inst{27-4} = 0b000100101111111111110011;
1889 let Inst{3-0} = func;
1893 // Note: Restrict $func to the tGPR regclass to prevent it being in LR.
1894 def BX_CALL : ARMPseudoInst<(outs), (ins tGPR:$func),
1895 8, IIC_Br, [(ARMcall_nolink tGPR:$func)]>,
1896 Requires<[IsARM, HasV4T]>;
1899 def BMOVPCRX_CALL : ARMPseudoInst<(outs), (ins tGPR:$func),
1900 8, IIC_Br, [(ARMcall_nolink tGPR:$func)]>,
1901 Requires<[IsARM, NoV4T]>;
1903 // mov lr, pc; b if callee is marked noreturn to avoid confusing the
1904 // return stack predictor.
1905 def BMOVPCB_CALL : ARMPseudoInst<(outs), (ins bl_target:$func),
1906 8, IIC_Br, [(ARMcall_nolink tglobaladdr:$func)]>,
1910 let isBranch = 1, isTerminator = 1 in {
1911 // FIXME: should be able to write a pattern for ARMBrcond, but can't use
1912 // a two-value operand where a dag node expects two operands. :(
1913 def Bcc : ABI<0b1010, (outs), (ins br_target:$target),
1914 IIC_Br, "b", "\t$target",
1915 [/*(ARMbrcond bb:$target, imm:$cc, CCR:$ccr)*/]> {
1917 let Inst{23-0} = target;
1918 let DecoderMethod = "DecodeBranchImmInstruction";
1921 let isBarrier = 1 in {
1922 // B is "predicable" since it's just a Bcc with an 'always' condition.
1923 let isPredicable = 1 in
1924 // FIXME: We shouldn't need this pseudo at all. Just using Bcc directly
1925 // should be sufficient.
1926 // FIXME: Is B really a Barrier? That doesn't seem right.
1927 def B : ARMPseudoExpand<(outs), (ins br_target:$target), 4, IIC_Br,
1928 [(br bb:$target)], (Bcc br_target:$target, (ops 14, zero_reg))>;
1930 let isNotDuplicable = 1, isIndirectBranch = 1 in {
1931 def BR_JTr : ARMPseudoInst<(outs),
1932 (ins GPR:$target, i32imm:$jt, i32imm:$id),
1934 [(ARMbrjt GPR:$target, tjumptable:$jt, imm:$id)]>;
1935 // FIXME: This shouldn't use the generic "addrmode2," but rather be split
1936 // into i12 and rs suffixed versions.
1937 def BR_JTm : ARMPseudoInst<(outs),
1938 (ins addrmode2:$target, i32imm:$jt, i32imm:$id),
1940 [(ARMbrjt (i32 (load addrmode2:$target)), tjumptable:$jt,
1942 def BR_JTadd : ARMPseudoInst<(outs),
1943 (ins GPR:$target, GPR:$idx, i32imm:$jt, i32imm:$id),
1945 [(ARMbrjt (add GPR:$target, GPR:$idx), tjumptable:$jt,
1947 } // isNotDuplicable = 1, isIndirectBranch = 1
1953 def BLXi : AXI<(outs), (ins blx_target:$target), BrMiscFrm, NoItinerary,
1954 "blx\t$target", []>,
1955 Requires<[IsARM, HasV5T]> {
1956 let Inst{31-25} = 0b1111101;
1958 let Inst{23-0} = target{24-1};
1959 let Inst{24} = target{0};
1962 // Branch and Exchange Jazelle
1963 def BXJ : ABI<0b0001, (outs), (ins GPR:$func), NoItinerary, "bxj", "\t$func",
1964 [/* pattern left blank */]> {
1966 let Inst{23-20} = 0b0010;
1967 let Inst{19-8} = 0xfff;
1968 let Inst{7-4} = 0b0010;
1969 let Inst{3-0} = func;
1974 let isCall = 1, isTerminator = 1, isReturn = 1, isBarrier = 1, Uses = [SP] in {
1975 def TCRETURNdi : PseudoInst<(outs), (ins i32imm:$dst), IIC_Br, []>;
1977 def TCRETURNri : PseudoInst<(outs), (ins tcGPR:$dst), IIC_Br, []>;
1979 def TAILJMPd : ARMPseudoExpand<(outs), (ins br_target:$dst),
1981 (Bcc br_target:$dst, (ops 14, zero_reg))>,
1984 def TAILJMPr : ARMPseudoExpand<(outs), (ins tcGPR:$dst),
1990 // Secure Monitor Call is a system instruction.
1991 def SMC : ABI<0b0001, (outs), (ins imm0_15:$opt), NoItinerary, "smc", "\t$opt",
1994 let Inst{23-4} = 0b01100000000000000111;
1995 let Inst{3-0} = opt;
1998 // Supervisor Call (Software Interrupt)
1999 let isCall = 1, Uses = [SP] in {
2000 def SVC : ABI<0b1111, (outs), (ins imm24b:$svc), IIC_Br, "svc", "\t$svc", []> {
2002 let Inst{23-0} = svc;
2006 // Store Return State
2007 class SRSI<bit wb, string asm>
2008 : XI<(outs), (ins imm0_31:$mode), AddrModeNone, 4, IndexModeNone, BrFrm,
2009 NoItinerary, asm, "", []> {
2011 let Inst{31-28} = 0b1111;
2012 let Inst{27-25} = 0b100;
2016 let Inst{19-16} = 0b1101; // SP
2017 let Inst{15-5} = 0b00000101000;
2018 let Inst{4-0} = mode;
2021 def SRSDA : SRSI<0, "srsda\tsp, $mode"> {
2022 let Inst{24-23} = 0;
2024 def SRSDA_UPD : SRSI<1, "srsda\tsp!, $mode"> {
2025 let Inst{24-23} = 0;
2027 def SRSDB : SRSI<0, "srsdb\tsp, $mode"> {
2028 let Inst{24-23} = 0b10;
2030 def SRSDB_UPD : SRSI<1, "srsdb\tsp!, $mode"> {
2031 let Inst{24-23} = 0b10;
2033 def SRSIA : SRSI<0, "srsia\tsp, $mode"> {
2034 let Inst{24-23} = 0b01;
2036 def SRSIA_UPD : SRSI<1, "srsia\tsp!, $mode"> {
2037 let Inst{24-23} = 0b01;
2039 def SRSIB : SRSI<0, "srsib\tsp, $mode"> {
2040 let Inst{24-23} = 0b11;
2042 def SRSIB_UPD : SRSI<1, "srsib\tsp!, $mode"> {
2043 let Inst{24-23} = 0b11;
2046 // Return From Exception
2047 class RFEI<bit wb, string asm>
2048 : XI<(outs), (ins GPR:$Rn), AddrModeNone, 4, IndexModeNone, BrFrm,
2049 NoItinerary, asm, "", []> {
2051 let Inst{31-28} = 0b1111;
2052 let Inst{27-25} = 0b100;
2056 let Inst{19-16} = Rn;
2057 let Inst{15-0} = 0xa00;
2060 def RFEDA : RFEI<0, "rfeda\t$Rn"> {
2061 let Inst{24-23} = 0;
2063 def RFEDA_UPD : RFEI<1, "rfeda\t$Rn!"> {
2064 let Inst{24-23} = 0;
2066 def RFEDB : RFEI<0, "rfedb\t$Rn"> {
2067 let Inst{24-23} = 0b10;
2069 def RFEDB_UPD : RFEI<1, "rfedb\t$Rn!"> {
2070 let Inst{24-23} = 0b10;
2072 def RFEIA : RFEI<0, "rfeia\t$Rn"> {
2073 let Inst{24-23} = 0b01;
2075 def RFEIA_UPD : RFEI<1, "rfeia\t$Rn!"> {
2076 let Inst{24-23} = 0b01;
2078 def RFEIB : RFEI<0, "rfeib\t$Rn"> {
2079 let Inst{24-23} = 0b11;
2081 def RFEIB_UPD : RFEI<1, "rfeib\t$Rn!"> {
2082 let Inst{24-23} = 0b11;
2085 //===----------------------------------------------------------------------===//
2086 // Load / Store Instructions.
2092 defm LDR : AI_ldr1<0, "ldr", IIC_iLoad_r, IIC_iLoad_si,
2093 UnOpFrag<(load node:$Src)>>;
2094 defm LDRB : AI_ldr1nopc<1, "ldrb", IIC_iLoad_bh_r, IIC_iLoad_bh_si,
2095 UnOpFrag<(zextloadi8 node:$Src)>>;
2096 defm STR : AI_str1<0, "str", IIC_iStore_r, IIC_iStore_si,
2097 BinOpFrag<(store node:$LHS, node:$RHS)>>;
2098 defm STRB : AI_str1nopc<1, "strb", IIC_iStore_bh_r, IIC_iStore_bh_si,
2099 BinOpFrag<(truncstorei8 node:$LHS, node:$RHS)>>;
2101 // Special LDR for loads from non-pc-relative constpools.
2102 let canFoldAsLoad = 1, mayLoad = 1, neverHasSideEffects = 1,
2103 isReMaterializable = 1, isCodeGenOnly = 1 in
2104 def LDRcp : AI2ldst<0b010, 1, 0, (outs GPR:$Rt), (ins addrmode_imm12:$addr),
2105 AddrMode_i12, LdFrm, IIC_iLoad_r, "ldr", "\t$Rt, $addr",
2109 let Inst{23} = addr{12}; // U (add = ('U' == 1))
2110 let Inst{19-16} = 0b1111;
2111 let Inst{15-12} = Rt;
2112 let Inst{11-0} = addr{11-0}; // imm12
2115 // Loads with zero extension
2116 def LDRH : AI3ld<0b1011, 1, (outs GPR:$Rt), (ins addrmode3:$addr), LdMiscFrm,
2117 IIC_iLoad_bh_r, "ldrh", "\t$Rt, $addr",
2118 [(set GPR:$Rt, (zextloadi16 addrmode3:$addr))]>;
2120 // Loads with sign extension
2121 def LDRSH : AI3ld<0b1111, 1, (outs GPR:$Rt), (ins addrmode3:$addr), LdMiscFrm,
2122 IIC_iLoad_bh_r, "ldrsh", "\t$Rt, $addr",
2123 [(set GPR:$Rt, (sextloadi16 addrmode3:$addr))]>;
2125 def LDRSB : AI3ld<0b1101, 1, (outs GPR:$Rt), (ins addrmode3:$addr), LdMiscFrm,
2126 IIC_iLoad_bh_r, "ldrsb", "\t$Rt, $addr",
2127 [(set GPR:$Rt, (sextloadi8 addrmode3:$addr))]>;
2129 let mayLoad = 1, neverHasSideEffects = 1, hasExtraDefRegAllocReq = 1 in {
2131 def LDRD : AI3ld<0b1101, 0, (outs GPR:$Rd, GPR:$dst2),
2132 (ins addrmode3:$addr), LdMiscFrm,
2133 IIC_iLoad_d_r, "ldrd", "\t$Rd, $dst2, $addr",
2134 []>, Requires<[IsARM, HasV5TE]>;
2138 multiclass AI2_ldridx<bit isByte, string opc,
2139 InstrItinClass iii, InstrItinClass iir> {
2140 def _PRE_IMM : AI2ldstidx<1, isByte, 1, (outs GPR:$Rt, GPR:$Rn_wb),
2141 (ins addrmode_imm12:$addr), IndexModePre, LdFrm, iii,
2142 opc, "\t$Rt, $addr!", "$addr.base = $Rn_wb", []> {
2145 let Inst{23} = addr{12};
2146 let Inst{19-16} = addr{16-13};
2147 let Inst{11-0} = addr{11-0};
2148 let DecoderMethod = "DecodeLDRPreImm";
2149 let AsmMatchConverter = "cvtLdWriteBackRegAddrModeImm12";
2152 def _PRE_REG : AI2ldstidx<1, isByte, 1, (outs GPR:$Rt, GPR:$Rn_wb),
2153 (ins ldst_so_reg:$addr), IndexModePre, LdFrm, iir,
2154 opc, "\t$Rt, $addr!", "$addr.base = $Rn_wb", []> {
2157 let Inst{23} = addr{12};
2158 let Inst{19-16} = addr{16-13};
2159 let Inst{11-0} = addr{11-0};
2161 let DecoderMethod = "DecodeLDRPreReg";
2162 let AsmMatchConverter = "cvtLdWriteBackRegAddrMode2";
2165 def _POST_REG : AI2ldstidx<1, isByte, 0, (outs GPR:$Rt, GPR:$Rn_wb),
2166 (ins addr_offset_none:$addr, am2offset_reg:$offset),
2167 IndexModePost, LdFrm, iir,
2168 opc, "\t$Rt, $addr, $offset",
2169 "$addr.base = $Rn_wb", []> {
2175 let Inst{23} = offset{12};
2176 let Inst{19-16} = addr;
2177 let Inst{11-0} = offset{11-0};
2179 let DecoderMethod = "DecodeAddrMode2IdxInstruction";
2182 def _POST_IMM : AI2ldstidx<1, isByte, 0, (outs GPR:$Rt, GPR:$Rn_wb),
2183 (ins addr_offset_none:$addr, am2offset_imm:$offset),
2184 IndexModePost, LdFrm, iii,
2185 opc, "\t$Rt, $addr, $offset",
2186 "$addr.base = $Rn_wb", []> {
2192 let Inst{23} = offset{12};
2193 let Inst{19-16} = addr;
2194 let Inst{11-0} = offset{11-0};
2196 let DecoderMethod = "DecodeAddrMode2IdxInstruction";
2201 let mayLoad = 1, neverHasSideEffects = 1 in {
2202 // FIXME: for LDR_PRE_REG etc. the itineray should be either IIC_iLoad_ru or
2203 // IIC_iLoad_siu depending on whether it the offset register is shifted.
2204 defm LDR : AI2_ldridx<0, "ldr", IIC_iLoad_iu, IIC_iLoad_ru>;
2205 defm LDRB : AI2_ldridx<1, "ldrb", IIC_iLoad_bh_iu, IIC_iLoad_bh_ru>;
2208 multiclass AI3_ldridx<bits<4> op, string opc, InstrItinClass itin> {
2209 def _PRE : AI3ldstidx<op, 1, 1, (outs GPR:$Rt, GPR:$Rn_wb),
2210 (ins addrmode3:$addr), IndexModePre,
2212 opc, "\t$Rt, $addr!", "$addr.base = $Rn_wb", []> {
2214 let Inst{23} = addr{8}; // U bit
2215 let Inst{22} = addr{13}; // 1 == imm8, 0 == Rm
2216 let Inst{19-16} = addr{12-9}; // Rn
2217 let Inst{11-8} = addr{7-4}; // imm7_4/zero
2218 let Inst{3-0} = addr{3-0}; // imm3_0/Rm
2219 let AsmMatchConverter = "cvtLdWriteBackRegAddrMode3";
2220 let DecoderMethod = "DecodeAddrMode3Instruction";
2222 def _POST : AI3ldstidx<op, 1, 0, (outs GPR:$Rt, GPR:$Rn_wb),
2223 (ins addr_offset_none:$addr, am3offset:$offset),
2224 IndexModePost, LdMiscFrm, itin,
2225 opc, "\t$Rt, $addr, $offset", "$addr.base = $Rn_wb",
2229 let Inst{23} = offset{8}; // U bit
2230 let Inst{22} = offset{9}; // 1 == imm8, 0 == Rm
2231 let Inst{19-16} = addr;
2232 let Inst{11-8} = offset{7-4}; // imm7_4/zero
2233 let Inst{3-0} = offset{3-0}; // imm3_0/Rm
2234 let DecoderMethod = "DecodeAddrMode3Instruction";
2238 let mayLoad = 1, neverHasSideEffects = 1 in {
2239 defm LDRH : AI3_ldridx<0b1011, "ldrh", IIC_iLoad_bh_ru>;
2240 defm LDRSH : AI3_ldridx<0b1111, "ldrsh", IIC_iLoad_bh_ru>;
2241 defm LDRSB : AI3_ldridx<0b1101, "ldrsb", IIC_iLoad_bh_ru>;
2242 let hasExtraDefRegAllocReq = 1 in {
2243 def LDRD_PRE : AI3ldstidx<0b1101, 0, 1, (outs GPR:$Rt, GPR:$Rt2, GPR:$Rn_wb),
2244 (ins addrmode3:$addr), IndexModePre,
2245 LdMiscFrm, IIC_iLoad_d_ru,
2246 "ldrd", "\t$Rt, $Rt2, $addr!",
2247 "$addr.base = $Rn_wb", []> {
2249 let Inst{23} = addr{8}; // U bit
2250 let Inst{22} = addr{13}; // 1 == imm8, 0 == Rm
2251 let Inst{19-16} = addr{12-9}; // Rn
2252 let Inst{11-8} = addr{7-4}; // imm7_4/zero
2253 let Inst{3-0} = addr{3-0}; // imm3_0/Rm
2254 let DecoderMethod = "DecodeAddrMode3Instruction";
2255 let AsmMatchConverter = "cvtLdrdPre";
2257 def LDRD_POST: AI3ldstidx<0b1101, 0, 0, (outs GPR:$Rt, GPR:$Rt2, GPR:$Rn_wb),
2258 (ins addr_offset_none:$addr, am3offset:$offset),
2259 IndexModePost, LdMiscFrm, IIC_iLoad_d_ru,
2260 "ldrd", "\t$Rt, $Rt2, $addr, $offset",
2261 "$addr.base = $Rn_wb", []> {
2264 let Inst{23} = offset{8}; // U bit
2265 let Inst{22} = offset{9}; // 1 == imm8, 0 == Rm
2266 let Inst{19-16} = addr;
2267 let Inst{11-8} = offset{7-4}; // imm7_4/zero
2268 let Inst{3-0} = offset{3-0}; // imm3_0/Rm
2269 let DecoderMethod = "DecodeAddrMode3Instruction";
2271 } // hasExtraDefRegAllocReq = 1
2272 } // mayLoad = 1, neverHasSideEffects = 1
2274 // LDRT, LDRBT, LDRSBT, LDRHT, LDRSHT.
2275 let mayLoad = 1, neverHasSideEffects = 1 in {
2276 def LDRT_POST_REG : AI2ldstidx<1, 0, 0, (outs GPR:$Rt, GPR:$Rn_wb),
2277 (ins addr_offset_none:$addr, am2offset_reg:$offset),
2278 IndexModePost, LdFrm, IIC_iLoad_ru,
2279 "ldrt", "\t$Rt, $addr, $offset",
2280 "$addr.base = $Rn_wb", []> {
2286 let Inst{23} = offset{12};
2287 let Inst{21} = 1; // overwrite
2288 let Inst{19-16} = addr;
2289 let Inst{11-5} = offset{11-5};
2291 let Inst{3-0} = offset{3-0};
2292 let DecoderMethod = "DecodeAddrMode2IdxInstruction";
2295 def LDRT_POST_IMM : AI2ldstidx<1, 0, 0, (outs GPR:$Rt, GPR:$Rn_wb),
2296 (ins addr_offset_none:$addr, am2offset_imm:$offset),
2297 IndexModePost, LdFrm, IIC_iLoad_ru,
2298 "ldrt", "\t$Rt, $addr, $offset",
2299 "$addr.base = $Rn_wb", []> {
2305 let Inst{23} = offset{12};
2306 let Inst{21} = 1; // overwrite
2307 let Inst{19-16} = addr;
2308 let Inst{11-0} = offset{11-0};
2309 let DecoderMethod = "DecodeAddrMode2IdxInstruction";
2312 def LDRBT_POST_REG : AI2ldstidx<1, 1, 0, (outs GPR:$Rt, GPR:$Rn_wb),
2313 (ins addr_offset_none:$addr, am2offset_reg:$offset),
2314 IndexModePost, LdFrm, IIC_iLoad_bh_ru,
2315 "ldrbt", "\t$Rt, $addr, $offset",
2316 "$addr.base = $Rn_wb", []> {
2322 let Inst{23} = offset{12};
2323 let Inst{21} = 1; // overwrite
2324 let Inst{19-16} = addr;
2325 let Inst{11-5} = offset{11-5};
2327 let Inst{3-0} = offset{3-0};
2328 let DecoderMethod = "DecodeAddrMode2IdxInstruction";
2331 def LDRBT_POST_IMM : AI2ldstidx<1, 1, 0, (outs GPR:$Rt, GPR:$Rn_wb),
2332 (ins addr_offset_none:$addr, am2offset_imm:$offset),
2333 IndexModePost, LdFrm, IIC_iLoad_bh_ru,
2334 "ldrbt", "\t$Rt, $addr, $offset",
2335 "$addr.base = $Rn_wb", []> {
2341 let Inst{23} = offset{12};
2342 let Inst{21} = 1; // overwrite
2343 let Inst{19-16} = addr;
2344 let Inst{11-0} = offset{11-0};
2345 let DecoderMethod = "DecodeAddrMode2IdxInstruction";
2348 multiclass AI3ldrT<bits<4> op, string opc> {
2349 def i : AI3ldstidxT<op, 1, (outs GPR:$Rt, GPR:$base_wb),
2350 (ins addr_offset_none:$addr, postidx_imm8:$offset),
2351 IndexModePost, LdMiscFrm, IIC_iLoad_bh_ru, opc,
2352 "\t$Rt, $addr, $offset", "$addr.base = $base_wb", []> {
2354 let Inst{23} = offset{8};
2356 let Inst{11-8} = offset{7-4};
2357 let Inst{3-0} = offset{3-0};
2358 let AsmMatchConverter = "cvtLdExtTWriteBackImm";
2360 def r : AI3ldstidxT<op, 1, (outs GPRnopc:$Rt, GPRnopc:$base_wb),
2361 (ins addr_offset_none:$addr, postidx_reg:$Rm),
2362 IndexModePost, LdMiscFrm, IIC_iLoad_bh_ru, opc,
2363 "\t$Rt, $addr, $Rm", "$addr.base = $base_wb", []> {
2365 let Inst{23} = Rm{4};
2368 let Unpredictable{11-8} = 0b1111;
2369 let Inst{3-0} = Rm{3-0};
2370 let AsmMatchConverter = "cvtLdExtTWriteBackReg";
2371 let DecoderMethod = "DecodeLDR";
2375 defm LDRSBT : AI3ldrT<0b1101, "ldrsbt">;
2376 defm LDRHT : AI3ldrT<0b1011, "ldrht">;
2377 defm LDRSHT : AI3ldrT<0b1111, "ldrsht">;
2382 // Stores with truncate
2383 def STRH : AI3str<0b1011, (outs), (ins GPR:$Rt, addrmode3:$addr), StMiscFrm,
2384 IIC_iStore_bh_r, "strh", "\t$Rt, $addr",
2385 [(truncstorei16 GPR:$Rt, addrmode3:$addr)]>;
2388 let mayStore = 1, neverHasSideEffects = 1, hasExtraSrcRegAllocReq = 1 in
2389 def STRD : AI3str<0b1111, (outs), (ins GPR:$Rt, GPR:$src2, addrmode3:$addr),
2390 StMiscFrm, IIC_iStore_d_r,
2391 "strd", "\t$Rt, $src2, $addr", []>,
2392 Requires<[IsARM, HasV5TE]> {
2397 multiclass AI2_stridx<bit isByte, string opc,
2398 InstrItinClass iii, InstrItinClass iir> {
2399 def _PRE_IMM : AI2ldstidx<0, isByte, 1, (outs GPR:$Rn_wb),
2400 (ins GPR:$Rt, addrmode_imm12:$addr), IndexModePre,
2402 opc, "\t$Rt, $addr!", "$addr.base = $Rn_wb", []> {
2405 let Inst{23} = addr{12}; // U (add = ('U' == 1))
2406 let Inst{19-16} = addr{16-13}; // Rn
2407 let Inst{11-0} = addr{11-0}; // imm12
2408 let AsmMatchConverter = "cvtStWriteBackRegAddrModeImm12";
2409 let DecoderMethod = "DecodeSTRPreImm";
2412 def _PRE_REG : AI2ldstidx<0, isByte, 1, (outs GPR:$Rn_wb),
2413 (ins GPR:$Rt, ldst_so_reg:$addr),
2414 IndexModePre, StFrm, iir,
2415 opc, "\t$Rt, $addr!", "$addr.base = $Rn_wb", []> {
2418 let Inst{23} = addr{12}; // U (add = ('U' == 1))
2419 let Inst{19-16} = addr{16-13}; // Rn
2420 let Inst{11-0} = addr{11-0};
2421 let Inst{4} = 0; // Inst{4} = 0
2422 let AsmMatchConverter = "cvtStWriteBackRegAddrMode2";
2423 let DecoderMethod = "DecodeSTRPreReg";
2425 def _POST_REG : AI2ldstidx<0, isByte, 0, (outs GPR:$Rn_wb),
2426 (ins GPR:$Rt, addr_offset_none:$addr, am2offset_reg:$offset),
2427 IndexModePost, StFrm, iir,
2428 opc, "\t$Rt, $addr, $offset",
2429 "$addr.base = $Rn_wb", []> {
2435 let Inst{23} = offset{12};
2436 let Inst{19-16} = addr;
2437 let Inst{11-0} = offset{11-0};
2440 let DecoderMethod = "DecodeAddrMode2IdxInstruction";
2443 def _POST_IMM : AI2ldstidx<0, isByte, 0, (outs GPR:$Rn_wb),
2444 (ins GPR:$Rt, addr_offset_none:$addr, am2offset_imm:$offset),
2445 IndexModePost, StFrm, iii,
2446 opc, "\t$Rt, $addr, $offset",
2447 "$addr.base = $Rn_wb", []> {
2453 let Inst{23} = offset{12};
2454 let Inst{19-16} = addr;
2455 let Inst{11-0} = offset{11-0};
2457 let DecoderMethod = "DecodeAddrMode2IdxInstruction";
2461 let mayStore = 1, neverHasSideEffects = 1 in {
2462 // FIXME: for STR_PRE_REG etc. the itineray should be either IIC_iStore_ru or
2463 // IIC_iStore_siu depending on whether it the offset register is shifted.
2464 defm STR : AI2_stridx<0, "str", IIC_iStore_iu, IIC_iStore_ru>;
2465 defm STRB : AI2_stridx<1, "strb", IIC_iStore_bh_iu, IIC_iStore_bh_ru>;
2468 def : ARMPat<(post_store GPR:$Rt, addr_offset_none:$addr,
2469 am2offset_reg:$offset),
2470 (STR_POST_REG GPR:$Rt, addr_offset_none:$addr,
2471 am2offset_reg:$offset)>;
2472 def : ARMPat<(post_store GPR:$Rt, addr_offset_none:$addr,
2473 am2offset_imm:$offset),
2474 (STR_POST_IMM GPR:$Rt, addr_offset_none:$addr,
2475 am2offset_imm:$offset)>;
2476 def : ARMPat<(post_truncsti8 GPR:$Rt, addr_offset_none:$addr,
2477 am2offset_reg:$offset),
2478 (STRB_POST_REG GPR:$Rt, addr_offset_none:$addr,
2479 am2offset_reg:$offset)>;
2480 def : ARMPat<(post_truncsti8 GPR:$Rt, addr_offset_none:$addr,
2481 am2offset_imm:$offset),
2482 (STRB_POST_IMM GPR:$Rt, addr_offset_none:$addr,
2483 am2offset_imm:$offset)>;
2485 // Pseudo-instructions for pattern matching the pre-indexed stores. We can't
2486 // put the patterns on the instruction definitions directly as ISel wants
2487 // the address base and offset to be separate operands, not a single
2488 // complex operand like we represent the instructions themselves. The
2489 // pseudos map between the two.
2490 let usesCustomInserter = 1,
2491 Constraints = "$Rn = $Rn_wb,@earlyclobber $Rn_wb" in {
2492 def STRi_preidx: ARMPseudoInst<(outs GPR:$Rn_wb),
2493 (ins GPR:$Rt, GPR:$Rn, am2offset_imm:$offset, pred:$p),
2496 (pre_store GPR:$Rt, GPR:$Rn, am2offset_imm:$offset))]>;
2497 def STRr_preidx: ARMPseudoInst<(outs GPR:$Rn_wb),
2498 (ins GPR:$Rt, GPR:$Rn, am2offset_reg:$offset, pred:$p),
2501 (pre_store GPR:$Rt, GPR:$Rn, am2offset_reg:$offset))]>;
2502 def STRBi_preidx: ARMPseudoInst<(outs GPR:$Rn_wb),
2503 (ins GPR:$Rt, GPR:$Rn, am2offset_imm:$offset, pred:$p),
2506 (pre_truncsti8 GPR:$Rt, GPR:$Rn, am2offset_imm:$offset))]>;
2507 def STRBr_preidx: ARMPseudoInst<(outs GPR:$Rn_wb),
2508 (ins GPR:$Rt, GPR:$Rn, am2offset_reg:$offset, pred:$p),
2511 (pre_truncsti8 GPR:$Rt, GPR:$Rn, am2offset_reg:$offset))]>;
2512 def STRH_preidx: ARMPseudoInst<(outs GPR:$Rn_wb),
2513 (ins GPR:$Rt, GPR:$Rn, am3offset:$offset, pred:$p),
2516 (pre_truncsti16 GPR:$Rt, GPR:$Rn, am3offset:$offset))]>;
2521 def STRH_PRE : AI3ldstidx<0b1011, 0, 1, (outs GPR:$Rn_wb),
2522 (ins GPR:$Rt, addrmode3:$addr), IndexModePre,
2523 StMiscFrm, IIC_iStore_bh_ru,
2524 "strh", "\t$Rt, $addr!", "$addr.base = $Rn_wb", []> {
2526 let Inst{23} = addr{8}; // U bit
2527 let Inst{22} = addr{13}; // 1 == imm8, 0 == Rm
2528 let Inst{19-16} = addr{12-9}; // Rn
2529 let Inst{11-8} = addr{7-4}; // imm7_4/zero
2530 let Inst{3-0} = addr{3-0}; // imm3_0/Rm
2531 let AsmMatchConverter = "cvtStWriteBackRegAddrMode3";
2532 let DecoderMethod = "DecodeAddrMode3Instruction";
2535 def STRH_POST : AI3ldstidx<0b1011, 0, 0, (outs GPR:$Rn_wb),
2536 (ins GPR:$Rt, addr_offset_none:$addr, am3offset:$offset),
2537 IndexModePost, StMiscFrm, IIC_iStore_bh_ru,
2538 "strh", "\t$Rt, $addr, $offset", "$addr.base = $Rn_wb",
2539 [(set GPR:$Rn_wb, (post_truncsti16 GPR:$Rt,
2540 addr_offset_none:$addr,
2541 am3offset:$offset))]> {
2544 let Inst{23} = offset{8}; // U bit
2545 let Inst{22} = offset{9}; // 1 == imm8, 0 == Rm
2546 let Inst{19-16} = addr;
2547 let Inst{11-8} = offset{7-4}; // imm7_4/zero
2548 let Inst{3-0} = offset{3-0}; // imm3_0/Rm
2549 let DecoderMethod = "DecodeAddrMode3Instruction";
2552 let mayStore = 1, neverHasSideEffects = 1, hasExtraSrcRegAllocReq = 1 in {
2553 def STRD_PRE : AI3ldstidx<0b1111, 0, 1, (outs GPR:$Rn_wb),
2554 (ins GPR:$Rt, GPR:$Rt2, addrmode3:$addr),
2555 IndexModePre, StMiscFrm, IIC_iStore_d_ru,
2556 "strd", "\t$Rt, $Rt2, $addr!",
2557 "$addr.base = $Rn_wb", []> {
2559 let Inst{23} = addr{8}; // U bit
2560 let Inst{22} = addr{13}; // 1 == imm8, 0 == Rm
2561 let Inst{19-16} = addr{12-9}; // Rn
2562 let Inst{11-8} = addr{7-4}; // imm7_4/zero
2563 let Inst{3-0} = addr{3-0}; // imm3_0/Rm
2564 let DecoderMethod = "DecodeAddrMode3Instruction";
2565 let AsmMatchConverter = "cvtStrdPre";
2568 def STRD_POST: AI3ldstidx<0b1111, 0, 0, (outs GPR:$Rn_wb),
2569 (ins GPR:$Rt, GPR:$Rt2, addr_offset_none:$addr,
2571 IndexModePost, StMiscFrm, IIC_iStore_d_ru,
2572 "strd", "\t$Rt, $Rt2, $addr, $offset",
2573 "$addr.base = $Rn_wb", []> {
2576 let Inst{23} = offset{8}; // U bit
2577 let Inst{22} = offset{9}; // 1 == imm8, 0 == Rm
2578 let Inst{19-16} = addr;
2579 let Inst{11-8} = offset{7-4}; // imm7_4/zero
2580 let Inst{3-0} = offset{3-0}; // imm3_0/Rm
2581 let DecoderMethod = "DecodeAddrMode3Instruction";
2583 } // mayStore = 1, neverHasSideEffects = 1, hasExtraSrcRegAllocReq = 1
2585 // STRT, STRBT, and STRHT
2587 def STRBT_POST_REG : AI2ldstidx<0, 1, 0, (outs GPR:$Rn_wb),
2588 (ins GPR:$Rt, addr_offset_none:$addr, am2offset_reg:$offset),
2589 IndexModePost, StFrm, IIC_iStore_bh_ru,
2590 "strbt", "\t$Rt, $addr, $offset",
2591 "$addr.base = $Rn_wb", []> {
2597 let Inst{23} = offset{12};
2598 let Inst{21} = 1; // overwrite
2599 let Inst{19-16} = addr;
2600 let Inst{11-5} = offset{11-5};
2602 let Inst{3-0} = offset{3-0};
2603 let DecoderMethod = "DecodeAddrMode2IdxInstruction";
2606 def STRBT_POST_IMM : AI2ldstidx<0, 1, 0, (outs GPR:$Rn_wb),
2607 (ins GPR:$Rt, addr_offset_none:$addr, am2offset_imm:$offset),
2608 IndexModePost, StFrm, IIC_iStore_bh_ru,
2609 "strbt", "\t$Rt, $addr, $offset",
2610 "$addr.base = $Rn_wb", []> {
2616 let Inst{23} = offset{12};
2617 let Inst{21} = 1; // overwrite
2618 let Inst{19-16} = addr;
2619 let Inst{11-0} = offset{11-0};
2620 let DecoderMethod = "DecodeAddrMode2IdxInstruction";
2623 let mayStore = 1, neverHasSideEffects = 1 in {
2624 def STRT_POST_REG : AI2ldstidx<0, 0, 0, (outs GPR:$Rn_wb),
2625 (ins GPR:$Rt, addr_offset_none:$addr, am2offset_reg:$offset),
2626 IndexModePost, StFrm, IIC_iStore_ru,
2627 "strt", "\t$Rt, $addr, $offset",
2628 "$addr.base = $Rn_wb", []> {
2634 let Inst{23} = offset{12};
2635 let Inst{21} = 1; // overwrite
2636 let Inst{19-16} = addr;
2637 let Inst{11-5} = offset{11-5};
2639 let Inst{3-0} = offset{3-0};
2640 let DecoderMethod = "DecodeAddrMode2IdxInstruction";
2643 def STRT_POST_IMM : AI2ldstidx<0, 0, 0, (outs GPR:$Rn_wb),
2644 (ins GPR:$Rt, addr_offset_none:$addr, am2offset_imm:$offset),
2645 IndexModePost, StFrm, IIC_iStore_ru,
2646 "strt", "\t$Rt, $addr, $offset",
2647 "$addr.base = $Rn_wb", []> {
2653 let Inst{23} = offset{12};
2654 let Inst{21} = 1; // overwrite
2655 let Inst{19-16} = addr;
2656 let Inst{11-0} = offset{11-0};
2657 let DecoderMethod = "DecodeAddrMode2IdxInstruction";
2662 multiclass AI3strT<bits<4> op, string opc> {
2663 def i : AI3ldstidxT<op, 0, (outs GPR:$base_wb),
2664 (ins GPR:$Rt, addr_offset_none:$addr, postidx_imm8:$offset),
2665 IndexModePost, StMiscFrm, IIC_iStore_bh_ru, opc,
2666 "\t$Rt, $addr, $offset", "$addr.base = $base_wb", []> {
2668 let Inst{23} = offset{8};
2670 let Inst{11-8} = offset{7-4};
2671 let Inst{3-0} = offset{3-0};
2672 let AsmMatchConverter = "cvtStExtTWriteBackImm";
2674 def r : AI3ldstidxT<op, 0, (outs GPR:$base_wb),
2675 (ins GPR:$Rt, addr_offset_none:$addr, postidx_reg:$Rm),
2676 IndexModePost, StMiscFrm, IIC_iStore_bh_ru, opc,
2677 "\t$Rt, $addr, $Rm", "$addr.base = $base_wb", []> {
2679 let Inst{23} = Rm{4};
2682 let Inst{3-0} = Rm{3-0};
2683 let AsmMatchConverter = "cvtStExtTWriteBackReg";
2688 defm STRHT : AI3strT<0b1011, "strht">;
2691 //===----------------------------------------------------------------------===//
2692 // Load / store multiple Instructions.
2695 multiclass arm_ldst_mult<string asm, string sfx, bit L_bit, bit P_bit, Format f,
2696 InstrItinClass itin, InstrItinClass itin_upd> {
2697 // IA is the default, so no need for an explicit suffix on the
2698 // mnemonic here. Without it is the canonical spelling.
2700 AXI4<(outs), (ins GPR:$Rn, pred:$p, reglist:$regs, variable_ops),
2701 IndexModeNone, f, itin,
2702 !strconcat(asm, "${p}\t$Rn, $regs", sfx), "", []> {
2703 let Inst{24-23} = 0b01; // Increment After
2704 let Inst{22} = P_bit;
2705 let Inst{21} = 0; // No writeback
2706 let Inst{20} = L_bit;
2709 AXI4<(outs GPR:$wb), (ins GPR:$Rn, pred:$p, reglist:$regs, variable_ops),
2710 IndexModeUpd, f, itin_upd,
2711 !strconcat(asm, "${p}\t$Rn!, $regs", sfx), "$Rn = $wb", []> {
2712 let Inst{24-23} = 0b01; // Increment After
2713 let Inst{22} = P_bit;
2714 let Inst{21} = 1; // Writeback
2715 let Inst{20} = L_bit;
2717 let DecoderMethod = "DecodeMemMultipleWritebackInstruction";
2720 AXI4<(outs), (ins GPR:$Rn, pred:$p, reglist:$regs, variable_ops),
2721 IndexModeNone, f, itin,
2722 !strconcat(asm, "da${p}\t$Rn, $regs", sfx), "", []> {
2723 let Inst{24-23} = 0b00; // Decrement After
2724 let Inst{22} = P_bit;
2725 let Inst{21} = 0; // No writeback
2726 let Inst{20} = L_bit;
2729 AXI4<(outs GPR:$wb), (ins GPR:$Rn, pred:$p, reglist:$regs, variable_ops),
2730 IndexModeUpd, f, itin_upd,
2731 !strconcat(asm, "da${p}\t$Rn!, $regs", sfx), "$Rn = $wb", []> {
2732 let Inst{24-23} = 0b00; // Decrement After
2733 let Inst{22} = P_bit;
2734 let Inst{21} = 1; // Writeback
2735 let Inst{20} = L_bit;
2737 let DecoderMethod = "DecodeMemMultipleWritebackInstruction";
2740 AXI4<(outs), (ins GPR:$Rn, pred:$p, reglist:$regs, variable_ops),
2741 IndexModeNone, f, itin,
2742 !strconcat(asm, "db${p}\t$Rn, $regs", sfx), "", []> {
2743 let Inst{24-23} = 0b10; // Decrement Before
2744 let Inst{22} = P_bit;
2745 let Inst{21} = 0; // No writeback
2746 let Inst{20} = L_bit;
2749 AXI4<(outs GPR:$wb), (ins GPR:$Rn, pred:$p, reglist:$regs, variable_ops),
2750 IndexModeUpd, f, itin_upd,
2751 !strconcat(asm, "db${p}\t$Rn!, $regs", sfx), "$Rn = $wb", []> {
2752 let Inst{24-23} = 0b10; // Decrement Before
2753 let Inst{22} = P_bit;
2754 let Inst{21} = 1; // Writeback
2755 let Inst{20} = L_bit;
2757 let DecoderMethod = "DecodeMemMultipleWritebackInstruction";
2760 AXI4<(outs), (ins GPR:$Rn, pred:$p, reglist:$regs, variable_ops),
2761 IndexModeNone, f, itin,
2762 !strconcat(asm, "ib${p}\t$Rn, $regs", sfx), "", []> {
2763 let Inst{24-23} = 0b11; // Increment Before
2764 let Inst{22} = P_bit;
2765 let Inst{21} = 0; // No writeback
2766 let Inst{20} = L_bit;
2769 AXI4<(outs GPR:$wb), (ins GPR:$Rn, pred:$p, reglist:$regs, variable_ops),
2770 IndexModeUpd, f, itin_upd,
2771 !strconcat(asm, "ib${p}\t$Rn!, $regs", sfx), "$Rn = $wb", []> {
2772 let Inst{24-23} = 0b11; // Increment Before
2773 let Inst{22} = P_bit;
2774 let Inst{21} = 1; // Writeback
2775 let Inst{20} = L_bit;
2777 let DecoderMethod = "DecodeMemMultipleWritebackInstruction";
2781 let neverHasSideEffects = 1 in {
2783 let mayLoad = 1, hasExtraDefRegAllocReq = 1 in
2784 defm LDM : arm_ldst_mult<"ldm", "", 1, 0, LdStMulFrm, IIC_iLoad_m,
2787 let mayStore = 1, hasExtraSrcRegAllocReq = 1 in
2788 defm STM : arm_ldst_mult<"stm", "", 0, 0, LdStMulFrm, IIC_iStore_m,
2791 } // neverHasSideEffects
2793 // FIXME: remove when we have a way to marking a MI with these properties.
2794 // FIXME: Should pc be an implicit operand like PICADD, etc?
2795 let isReturn = 1, isTerminator = 1, isBarrier = 1, mayLoad = 1,
2796 hasExtraDefRegAllocReq = 1, isCodeGenOnly = 1 in
2797 def LDMIA_RET : ARMPseudoExpand<(outs GPR:$wb), (ins GPR:$Rn, pred:$p,
2798 reglist:$regs, variable_ops),
2799 4, IIC_iLoad_mBr, [],
2800 (LDMIA_UPD GPR:$wb, GPR:$Rn, pred:$p, reglist:$regs)>,
2801 RegConstraint<"$Rn = $wb">;
2803 let mayLoad = 1, hasExtraDefRegAllocReq = 1 in
2804 defm sysLDM : arm_ldst_mult<"ldm", " ^", 1, 1, LdStMulFrm, IIC_iLoad_m,
2807 let mayStore = 1, hasExtraSrcRegAllocReq = 1 in
2808 defm sysSTM : arm_ldst_mult<"stm", " ^", 0, 1, LdStMulFrm, IIC_iStore_m,
2813 //===----------------------------------------------------------------------===//
2814 // Move Instructions.
2817 let neverHasSideEffects = 1 in
2818 def MOVr : AsI1<0b1101, (outs GPR:$Rd), (ins GPR:$Rm), DPFrm, IIC_iMOVr,
2819 "mov", "\t$Rd, $Rm", []>, UnaryDP {
2823 let Inst{19-16} = 0b0000;
2824 let Inst{11-4} = 0b00000000;
2827 let Inst{15-12} = Rd;
2830 // A version for the smaller set of tail call registers.
2831 let neverHasSideEffects = 1 in
2832 def MOVr_TC : AsI1<0b1101, (outs tcGPR:$Rd), (ins tcGPR:$Rm), DPFrm,
2833 IIC_iMOVr, "mov", "\t$Rd, $Rm", []>, UnaryDP {
2837 let Inst{11-4} = 0b00000000;
2840 let Inst{15-12} = Rd;
2843 def MOVsr : AsI1<0b1101, (outs GPRnopc:$Rd), (ins shift_so_reg_reg:$src),
2844 DPSoRegRegFrm, IIC_iMOVsr,
2845 "mov", "\t$Rd, $src",
2846 [(set GPRnopc:$Rd, shift_so_reg_reg:$src)]>, UnaryDP {
2849 let Inst{15-12} = Rd;
2850 let Inst{19-16} = 0b0000;
2851 let Inst{11-8} = src{11-8};
2853 let Inst{6-5} = src{6-5};
2855 let Inst{3-0} = src{3-0};
2859 def MOVsi : AsI1<0b1101, (outs GPR:$Rd), (ins shift_so_reg_imm:$src),
2860 DPSoRegImmFrm, IIC_iMOVsr,
2861 "mov", "\t$Rd, $src", [(set GPR:$Rd, shift_so_reg_imm:$src)]>,
2865 let Inst{15-12} = Rd;
2866 let Inst{19-16} = 0b0000;
2867 let Inst{11-5} = src{11-5};
2869 let Inst{3-0} = src{3-0};
2873 let isReMaterializable = 1, isAsCheapAsAMove = 1, isMoveImm = 1 in
2874 def MOVi : AsI1<0b1101, (outs GPR:$Rd), (ins so_imm:$imm), DPFrm, IIC_iMOVi,
2875 "mov", "\t$Rd, $imm", [(set GPR:$Rd, so_imm:$imm)]>, UnaryDP {
2879 let Inst{15-12} = Rd;
2880 let Inst{19-16} = 0b0000;
2881 let Inst{11-0} = imm;
2884 let isReMaterializable = 1, isAsCheapAsAMove = 1, isMoveImm = 1 in
2885 def MOVi16 : AI1<0b1000, (outs GPR:$Rd), (ins imm0_65535_expr:$imm),
2887 "movw", "\t$Rd, $imm",
2888 [(set GPR:$Rd, imm0_65535:$imm)]>,
2889 Requires<[IsARM, HasV6T2]>, UnaryDP {
2892 let Inst{15-12} = Rd;
2893 let Inst{11-0} = imm{11-0};
2894 let Inst{19-16} = imm{15-12};
2897 let DecoderMethod = "DecodeArmMOVTWInstruction";
2900 def : InstAlias<"mov${p} $Rd, $imm",
2901 (MOVi16 GPR:$Rd, imm0_65535_expr:$imm, pred:$p)>,
2904 def MOVi16_ga_pcrel : PseudoInst<(outs GPR:$Rd),
2905 (ins i32imm:$addr, pclabel:$id), IIC_iMOVi, []>;
2907 let Constraints = "$src = $Rd" in {
2908 def MOVTi16 : AI1<0b1010, (outs GPRnopc:$Rd),
2909 (ins GPR:$src, imm0_65535_expr:$imm),
2911 "movt", "\t$Rd, $imm",
2913 (or (and GPR:$src, 0xffff),
2914 lo16AllZero:$imm))]>, UnaryDP,
2915 Requires<[IsARM, HasV6T2]> {
2918 let Inst{15-12} = Rd;
2919 let Inst{11-0} = imm{11-0};
2920 let Inst{19-16} = imm{15-12};
2923 let DecoderMethod = "DecodeArmMOVTWInstruction";
2926 def MOVTi16_ga_pcrel : PseudoInst<(outs GPR:$Rd),
2927 (ins GPR:$src, i32imm:$addr, pclabel:$id), IIC_iMOVi, []>;
2931 def : ARMPat<(or GPR:$src, 0xffff0000), (MOVTi16 GPR:$src, 0xffff)>,
2932 Requires<[IsARM, HasV6T2]>;
2934 let Uses = [CPSR] in
2935 def RRX: PseudoInst<(outs GPR:$Rd), (ins GPR:$Rm), IIC_iMOVsi,
2936 [(set GPR:$Rd, (ARMrrx GPR:$Rm))]>, UnaryDP,
2939 // These aren't really mov instructions, but we have to define them this way
2940 // due to flag operands.
2942 let Defs = [CPSR] in {
2943 def MOVsrl_flag : PseudoInst<(outs GPR:$dst), (ins GPR:$src), IIC_iMOVsi,
2944 [(set GPR:$dst, (ARMsrl_flag GPR:$src))]>, UnaryDP,
2946 def MOVsra_flag : PseudoInst<(outs GPR:$dst), (ins GPR:$src), IIC_iMOVsi,
2947 [(set GPR:$dst, (ARMsra_flag GPR:$src))]>, UnaryDP,
2951 //===----------------------------------------------------------------------===//
2952 // Extend Instructions.
2957 def SXTB : AI_ext_rrot<0b01101010,
2958 "sxtb", UnOpFrag<(sext_inreg node:$Src, i8)>>;
2959 def SXTH : AI_ext_rrot<0b01101011,
2960 "sxth", UnOpFrag<(sext_inreg node:$Src, i16)>>;
2962 def SXTAB : AI_exta_rrot<0b01101010,
2963 "sxtab", BinOpFrag<(add node:$LHS, (sext_inreg node:$RHS, i8))>>;
2964 def SXTAH : AI_exta_rrot<0b01101011,
2965 "sxtah", BinOpFrag<(add node:$LHS, (sext_inreg node:$RHS,i16))>>;
2967 def SXTB16 : AI_ext_rrot_np<0b01101000, "sxtb16">;
2969 def SXTAB16 : AI_exta_rrot_np<0b01101000, "sxtab16">;
2973 let AddedComplexity = 16 in {
2974 def UXTB : AI_ext_rrot<0b01101110,
2975 "uxtb" , UnOpFrag<(and node:$Src, 0x000000FF)>>;
2976 def UXTH : AI_ext_rrot<0b01101111,
2977 "uxth" , UnOpFrag<(and node:$Src, 0x0000FFFF)>>;
2978 def UXTB16 : AI_ext_rrot<0b01101100,
2979 "uxtb16", UnOpFrag<(and node:$Src, 0x00FF00FF)>>;
2981 // FIXME: This pattern incorrectly assumes the shl operator is a rotate.
2982 // The transformation should probably be done as a combiner action
2983 // instead so we can include a check for masking back in the upper
2984 // eight bits of the source into the lower eight bits of the result.
2985 //def : ARMV6Pat<(and (shl GPR:$Src, (i32 8)), 0xFF00FF),
2986 // (UXTB16r_rot GPR:$Src, 3)>;
2987 def : ARMV6Pat<(and (srl GPR:$Src, (i32 8)), 0xFF00FF),
2988 (UXTB16 GPR:$Src, 1)>;
2990 def UXTAB : AI_exta_rrot<0b01101110, "uxtab",
2991 BinOpFrag<(add node:$LHS, (and node:$RHS, 0x00FF))>>;
2992 def UXTAH : AI_exta_rrot<0b01101111, "uxtah",
2993 BinOpFrag<(add node:$LHS, (and node:$RHS, 0xFFFF))>>;
2996 // This isn't safe in general, the add is two 16-bit units, not a 32-bit add.
2997 def UXTAB16 : AI_exta_rrot_np<0b01101100, "uxtab16">;
3000 def SBFX : I<(outs GPRnopc:$Rd),
3001 (ins GPRnopc:$Rn, imm0_31:$lsb, imm1_32:$width),
3002 AddrMode1, 4, IndexModeNone, DPFrm, IIC_iUNAsi,
3003 "sbfx", "\t$Rd, $Rn, $lsb, $width", "", []>,
3004 Requires<[IsARM, HasV6T2]> {
3009 let Inst{27-21} = 0b0111101;
3010 let Inst{6-4} = 0b101;
3011 let Inst{20-16} = width;
3012 let Inst{15-12} = Rd;
3013 let Inst{11-7} = lsb;
3017 def UBFX : I<(outs GPR:$Rd),
3018 (ins GPR:$Rn, imm0_31:$lsb, imm1_32:$width),
3019 AddrMode1, 4, IndexModeNone, DPFrm, IIC_iUNAsi,
3020 "ubfx", "\t$Rd, $Rn, $lsb, $width", "", []>,
3021 Requires<[IsARM, HasV6T2]> {
3026 let Inst{27-21} = 0b0111111;
3027 let Inst{6-4} = 0b101;
3028 let Inst{20-16} = width;
3029 let Inst{15-12} = Rd;
3030 let Inst{11-7} = lsb;
3034 //===----------------------------------------------------------------------===//
3035 // Arithmetic Instructions.
3038 defm ADD : AsI1_bin_irs<0b0100, "add",
3039 IIC_iALUi, IIC_iALUr, IIC_iALUsr,
3040 BinOpFrag<(add node:$LHS, node:$RHS)>, 1>;
3041 defm SUB : AsI1_bin_irs<0b0010, "sub",
3042 IIC_iALUi, IIC_iALUr, IIC_iALUsr,
3043 BinOpFrag<(sub node:$LHS, node:$RHS)>>;
3045 // ADD and SUB with 's' bit set.
3047 // Currently, ADDS/SUBS are pseudo opcodes that exist only in the
3048 // selection DAG. They are "lowered" to real ADD/SUB opcodes by
3049 // AdjustInstrPostInstrSelection where we determine whether or not to
3050 // set the "s" bit based on CPSR liveness.
3052 // FIXME: Eliminate ADDS/SUBS pseudo opcodes after adding tablegen
3053 // support for an optional CPSR definition that corresponds to the DAG
3054 // node's second value. We can then eliminate the implicit def of CPSR.
3055 defm ADDS : AsI1_bin_s_irs<IIC_iALUi, IIC_iALUr, IIC_iALUsr,
3056 BinOpFrag<(ARMaddc node:$LHS, node:$RHS)>, 1>;
3057 defm SUBS : AsI1_bin_s_irs<IIC_iALUi, IIC_iALUr, IIC_iALUsr,
3058 BinOpFrag<(ARMsubc node:$LHS, node:$RHS)>>;
3060 defm ADC : AI1_adde_sube_irs<0b0101, "adc",
3061 BinOpWithFlagFrag<(ARMadde node:$LHS, node:$RHS, node:$FLAG)>, 1>;
3062 defm SBC : AI1_adde_sube_irs<0b0110, "sbc",
3063 BinOpWithFlagFrag<(ARMsube node:$LHS, node:$RHS, node:$FLAG)>>;
3065 defm RSB : AsI1_rbin_irs<0b0011, "rsb",
3066 IIC_iALUi, IIC_iALUr, IIC_iALUsr,
3067 BinOpFrag<(sub node:$LHS, node:$RHS)>>;
3069 // FIXME: Eliminate them if we can write def : Pat patterns which defines
3070 // CPSR and the implicit def of CPSR is not needed.
3071 defm RSBS : AsI1_rbin_s_is<IIC_iALUi, IIC_iALUr, IIC_iALUsr,
3072 BinOpFrag<(ARMsubc node:$LHS, node:$RHS)>>;
3074 defm RSC : AI1_rsc_irs<0b0111, "rsc",
3075 BinOpWithFlagFrag<(ARMsube node:$LHS, node:$RHS, node:$FLAG)>>;
3077 // (sub X, imm) gets canonicalized to (add X, -imm). Match this form.
3078 // The assume-no-carry-in form uses the negation of the input since add/sub
3079 // assume opposite meanings of the carry flag (i.e., carry == !borrow).
3080 // See the definition of AddWithCarry() in the ARM ARM A2.2.1 for the gory
3082 def : ARMPat<(add GPR:$src, so_imm_neg:$imm),
3083 (SUBri GPR:$src, so_imm_neg:$imm)>;
3084 def : ARMPat<(ARMaddc GPR:$src, so_imm_neg:$imm),
3085 (SUBSri GPR:$src, so_imm_neg:$imm)>;
3087 def : ARMPat<(add GPR:$src, imm0_65535_neg:$imm),
3088 (SUBrr GPR:$src, (MOVi16 (imm_neg_XFORM imm:$imm)))>;
3089 def : ARMPat<(ARMaddc GPR:$src, imm0_65535_neg:$imm),
3090 (SUBSrr GPR:$src, (MOVi16 (imm_neg_XFORM imm:$imm)))>;
3092 // The with-carry-in form matches bitwise not instead of the negation.
3093 // Effectively, the inverse interpretation of the carry flag already accounts
3094 // for part of the negation.
3095 def : ARMPat<(ARMadde GPR:$src, so_imm_not:$imm, CPSR),
3096 (SBCri GPR:$src, so_imm_not:$imm)>;
3098 // Note: These are implemented in C++ code, because they have to generate
3099 // ADD/SUBrs instructions, which use a complex pattern that a xform function
3101 // (mul X, 2^n+1) -> (add (X << n), X)
3102 // (mul X, 2^n-1) -> (rsb X, (X << n))
3104 // ARM Arithmetic Instruction
3105 // GPR:$dst = GPR:$a op GPR:$b
3106 class AAI<bits<8> op27_20, bits<8> op11_4, string opc,
3107 list<dag> pattern = [],
3108 dag iops = (ins GPRnopc:$Rn, GPRnopc:$Rm),
3109 string asm = "\t$Rd, $Rn, $Rm">
3110 : AI<(outs GPRnopc:$Rd), iops, DPFrm, IIC_iALUr, opc, asm, pattern> {
3114 let Inst{27-20} = op27_20;
3115 let Inst{11-4} = op11_4;
3116 let Inst{19-16} = Rn;
3117 let Inst{15-12} = Rd;
3120 let Unpredictable{11-8} = 0b1111;
3123 // Saturating add/subtract
3125 def QADD : AAI<0b00010000, 0b00000101, "qadd",
3126 [(set GPRnopc:$Rd, (int_arm_qadd GPRnopc:$Rm, GPRnopc:$Rn))],
3127 (ins GPRnopc:$Rm, GPRnopc:$Rn), "\t$Rd, $Rm, $Rn">;
3128 def QSUB : AAI<0b00010010, 0b00000101, "qsub",
3129 [(set GPRnopc:$Rd, (int_arm_qsub GPRnopc:$Rm, GPRnopc:$Rn))],
3130 (ins GPRnopc:$Rm, GPRnopc:$Rn), "\t$Rd, $Rm, $Rn">;
3131 def QDADD : AAI<0b00010100, 0b00000101, "qdadd", [],
3132 (ins GPRnopc:$Rm, GPRnopc:$Rn),
3134 def QDSUB : AAI<0b00010110, 0b00000101, "qdsub", [],
3135 (ins GPRnopc:$Rm, GPRnopc:$Rn),
3138 def QADD16 : AAI<0b01100010, 0b11110001, "qadd16">;
3139 def QADD8 : AAI<0b01100010, 0b11111001, "qadd8">;
3140 def QASX : AAI<0b01100010, 0b11110011, "qasx">;
3141 def QSAX : AAI<0b01100010, 0b11110101, "qsax">;
3142 def QSUB16 : AAI<0b01100010, 0b11110111, "qsub16">;
3143 def QSUB8 : AAI<0b01100010, 0b11111111, "qsub8">;
3144 def UQADD16 : AAI<0b01100110, 0b11110001, "uqadd16">;
3145 def UQADD8 : AAI<0b01100110, 0b11111001, "uqadd8">;
3146 def UQASX : AAI<0b01100110, 0b11110011, "uqasx">;
3147 def UQSAX : AAI<0b01100110, 0b11110101, "uqsax">;
3148 def UQSUB16 : AAI<0b01100110, 0b11110111, "uqsub16">;
3149 def UQSUB8 : AAI<0b01100110, 0b11111111, "uqsub8">;
3151 // Signed/Unsigned add/subtract
3153 def SASX : AAI<0b01100001, 0b11110011, "sasx">;
3154 def SADD16 : AAI<0b01100001, 0b11110001, "sadd16">;
3155 def SADD8 : AAI<0b01100001, 0b11111001, "sadd8">;
3156 def SSAX : AAI<0b01100001, 0b11110101, "ssax">;
3157 def SSUB16 : AAI<0b01100001, 0b11110111, "ssub16">;
3158 def SSUB8 : AAI<0b01100001, 0b11111111, "ssub8">;
3159 def UASX : AAI<0b01100101, 0b11110011, "uasx">;
3160 def UADD16 : AAI<0b01100101, 0b11110001, "uadd16">;
3161 def UADD8 : AAI<0b01100101, 0b11111001, "uadd8">;
3162 def USAX : AAI<0b01100101, 0b11110101, "usax">;
3163 def USUB16 : AAI<0b01100101, 0b11110111, "usub16">;
3164 def USUB8 : AAI<0b01100101, 0b11111111, "usub8">;
3166 // Signed/Unsigned halving add/subtract
3168 def SHASX : AAI<0b01100011, 0b11110011, "shasx">;
3169 def SHADD16 : AAI<0b01100011, 0b11110001, "shadd16">;
3170 def SHADD8 : AAI<0b01100011, 0b11111001, "shadd8">;
3171 def SHSAX : AAI<0b01100011, 0b11110101, "shsax">;
3172 def SHSUB16 : AAI<0b01100011, 0b11110111, "shsub16">;
3173 def SHSUB8 : AAI<0b01100011, 0b11111111, "shsub8">;
3174 def UHASX : AAI<0b01100111, 0b11110011, "uhasx">;
3175 def UHADD16 : AAI<0b01100111, 0b11110001, "uhadd16">;
3176 def UHADD8 : AAI<0b01100111, 0b11111001, "uhadd8">;
3177 def UHSAX : AAI<0b01100111, 0b11110101, "uhsax">;
3178 def UHSUB16 : AAI<0b01100111, 0b11110111, "uhsub16">;
3179 def UHSUB8 : AAI<0b01100111, 0b11111111, "uhsub8">;
3181 // Unsigned Sum of Absolute Differences [and Accumulate].
3183 def USAD8 : AI<(outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm),
3184 MulFrm /* for convenience */, NoItinerary, "usad8",
3185 "\t$Rd, $Rn, $Rm", []>,
3186 Requires<[IsARM, HasV6]> {
3190 let Inst{27-20} = 0b01111000;
3191 let Inst{15-12} = 0b1111;
3192 let Inst{7-4} = 0b0001;
3193 let Inst{19-16} = Rd;
3194 let Inst{11-8} = Rm;
3197 def USADA8 : AI<(outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm, GPR:$Ra),
3198 MulFrm /* for convenience */, NoItinerary, "usada8",
3199 "\t$Rd, $Rn, $Rm, $Ra", []>,
3200 Requires<[IsARM, HasV6]> {
3205 let Inst{27-20} = 0b01111000;
3206 let Inst{7-4} = 0b0001;
3207 let Inst{19-16} = Rd;
3208 let Inst{15-12} = Ra;
3209 let Inst{11-8} = Rm;
3213 // Signed/Unsigned saturate
3215 def SSAT : AI<(outs GPRnopc:$Rd),
3216 (ins imm1_32:$sat_imm, GPRnopc:$Rn, shift_imm:$sh),
3217 SatFrm, NoItinerary, "ssat", "\t$Rd, $sat_imm, $Rn$sh", []> {
3222 let Inst{27-21} = 0b0110101;
3223 let Inst{5-4} = 0b01;
3224 let Inst{20-16} = sat_imm;
3225 let Inst{15-12} = Rd;
3226 let Inst{11-7} = sh{4-0};
3227 let Inst{6} = sh{5};
3231 def SSAT16 : AI<(outs GPRnopc:$Rd),
3232 (ins imm1_16:$sat_imm, GPRnopc:$Rn), SatFrm,
3233 NoItinerary, "ssat16", "\t$Rd, $sat_imm, $Rn", []> {
3237 let Inst{27-20} = 0b01101010;
3238 let Inst{11-4} = 0b11110011;
3239 let Inst{15-12} = Rd;
3240 let Inst{19-16} = sat_imm;
3244 def USAT : AI<(outs GPRnopc:$Rd),
3245 (ins imm0_31:$sat_imm, GPRnopc:$Rn, shift_imm:$sh),
3246 SatFrm, NoItinerary, "usat", "\t$Rd, $sat_imm, $Rn$sh", []> {
3251 let Inst{27-21} = 0b0110111;
3252 let Inst{5-4} = 0b01;
3253 let Inst{15-12} = Rd;
3254 let Inst{11-7} = sh{4-0};
3255 let Inst{6} = sh{5};
3256 let Inst{20-16} = sat_imm;
3260 def USAT16 : AI<(outs GPRnopc:$Rd),
3261 (ins imm0_15:$sat_imm, GPRnopc:$Rn), SatFrm,
3262 NoItinerary, "usat16", "\t$Rd, $sat_imm, $Rn", []> {
3266 let Inst{27-20} = 0b01101110;
3267 let Inst{11-4} = 0b11110011;
3268 let Inst{15-12} = Rd;
3269 let Inst{19-16} = sat_imm;
3273 def : ARMV6Pat<(int_arm_ssat GPRnopc:$a, imm:$pos),
3274 (SSAT imm:$pos, GPRnopc:$a, 0)>;
3275 def : ARMV6Pat<(int_arm_usat GPRnopc:$a, imm:$pos),
3276 (USAT imm:$pos, GPRnopc:$a, 0)>;
3278 //===----------------------------------------------------------------------===//
3279 // Bitwise Instructions.
3282 defm AND : AsI1_bin_irs<0b0000, "and",
3283 IIC_iBITi, IIC_iBITr, IIC_iBITsr,
3284 BinOpFrag<(and node:$LHS, node:$RHS)>, 1>;
3285 defm ORR : AsI1_bin_irs<0b1100, "orr",
3286 IIC_iBITi, IIC_iBITr, IIC_iBITsr,
3287 BinOpFrag<(or node:$LHS, node:$RHS)>, 1>;
3288 defm EOR : AsI1_bin_irs<0b0001, "eor",
3289 IIC_iBITi, IIC_iBITr, IIC_iBITsr,
3290 BinOpFrag<(xor node:$LHS, node:$RHS)>, 1>;
3291 defm BIC : AsI1_bin_irs<0b1110, "bic",
3292 IIC_iBITi, IIC_iBITr, IIC_iBITsr,
3293 BinOpFrag<(and node:$LHS, (not node:$RHS))>>;
3295 // FIXME: bf_inv_mask_imm should be two operands, the lsb and the msb, just
3296 // like in the actual instruction encoding. The complexity of mapping the mask
3297 // to the lsb/msb pair should be handled by ISel, not encapsulated in the
3298 // instruction description.
3299 def BFC : I<(outs GPR:$Rd), (ins GPR:$src, bf_inv_mask_imm:$imm),
3300 AddrMode1, 4, IndexModeNone, DPFrm, IIC_iUNAsi,
3301 "bfc", "\t$Rd, $imm", "$src = $Rd",
3302 [(set GPR:$Rd, (and GPR:$src, bf_inv_mask_imm:$imm))]>,
3303 Requires<[IsARM, HasV6T2]> {
3306 let Inst{27-21} = 0b0111110;
3307 let Inst{6-0} = 0b0011111;
3308 let Inst{15-12} = Rd;
3309 let Inst{11-7} = imm{4-0}; // lsb
3310 let Inst{20-16} = imm{9-5}; // msb
3313 // A8.6.18 BFI - Bitfield insert (Encoding A1)
3314 def BFI:I<(outs GPRnopc:$Rd), (ins GPRnopc:$src, GPR:$Rn, bf_inv_mask_imm:$imm),
3315 AddrMode1, 4, IndexModeNone, DPFrm, IIC_iUNAsi,
3316 "bfi", "\t$Rd, $Rn, $imm", "$src = $Rd",
3317 [(set GPRnopc:$Rd, (ARMbfi GPRnopc:$src, GPR:$Rn,
3318 bf_inv_mask_imm:$imm))]>,
3319 Requires<[IsARM, HasV6T2]> {
3323 let Inst{27-21} = 0b0111110;
3324 let Inst{6-4} = 0b001; // Rn: Inst{3-0} != 15
3325 let Inst{15-12} = Rd;
3326 let Inst{11-7} = imm{4-0}; // lsb
3327 let Inst{20-16} = imm{9-5}; // width
3331 def MVNr : AsI1<0b1111, (outs GPR:$Rd), (ins GPR:$Rm), DPFrm, IIC_iMVNr,
3332 "mvn", "\t$Rd, $Rm",
3333 [(set GPR:$Rd, (not GPR:$Rm))]>, UnaryDP {
3337 let Inst{19-16} = 0b0000;
3338 let Inst{11-4} = 0b00000000;
3339 let Inst{15-12} = Rd;
3342 def MVNsi : AsI1<0b1111, (outs GPR:$Rd), (ins so_reg_imm:$shift),
3343 DPSoRegImmFrm, IIC_iMVNsr, "mvn", "\t$Rd, $shift",
3344 [(set GPR:$Rd, (not so_reg_imm:$shift))]>, UnaryDP {
3348 let Inst{19-16} = 0b0000;
3349 let Inst{15-12} = Rd;
3350 let Inst{11-5} = shift{11-5};
3352 let Inst{3-0} = shift{3-0};
3354 def MVNsr : AsI1<0b1111, (outs GPR:$Rd), (ins so_reg_reg:$shift),
3355 DPSoRegRegFrm, IIC_iMVNsr, "mvn", "\t$Rd, $shift",
3356 [(set GPR:$Rd, (not so_reg_reg:$shift))]>, UnaryDP {
3360 let Inst{19-16} = 0b0000;
3361 let Inst{15-12} = Rd;
3362 let Inst{11-8} = shift{11-8};
3364 let Inst{6-5} = shift{6-5};
3366 let Inst{3-0} = shift{3-0};
3368 let isReMaterializable = 1, isAsCheapAsAMove = 1, isMoveImm = 1 in
3369 def MVNi : AsI1<0b1111, (outs GPR:$Rd), (ins so_imm:$imm), DPFrm,
3370 IIC_iMVNi, "mvn", "\t$Rd, $imm",
3371 [(set GPR:$Rd, so_imm_not:$imm)]>,UnaryDP {
3375 let Inst{19-16} = 0b0000;
3376 let Inst{15-12} = Rd;
3377 let Inst{11-0} = imm;
3380 def : ARMPat<(and GPR:$src, so_imm_not:$imm),
3381 (BICri GPR:$src, so_imm_not:$imm)>;
3383 //===----------------------------------------------------------------------===//
3384 // Multiply Instructions.
3386 class AsMul1I32<bits<7> opcod, dag oops, dag iops, InstrItinClass itin,
3387 string opc, string asm, list<dag> pattern>
3388 : AsMul1I<opcod, oops, iops, itin, opc, asm, pattern> {
3392 let Inst{19-16} = Rd;
3393 let Inst{11-8} = Rm;
3396 class AsMul1I64<bits<7> opcod, dag oops, dag iops, InstrItinClass itin,
3397 string opc, string asm, list<dag> pattern>
3398 : AsMul1I<opcod, oops, iops, itin, opc, asm, pattern> {
3403 let Inst{19-16} = RdHi;
3404 let Inst{15-12} = RdLo;
3405 let Inst{11-8} = Rm;
3409 // FIXME: The v5 pseudos are only necessary for the additional Constraint
3410 // property. Remove them when it's possible to add those properties
3411 // on an individual MachineInstr, not just an instruction description.
3412 let isCommutable = 1, TwoOperandAliasConstraint = "$Rn = $Rd" in {
3413 def MUL : AsMul1I32<0b0000000, (outs GPRnopc:$Rd),
3414 (ins GPRnopc:$Rn, GPRnopc:$Rm),
3415 IIC_iMUL32, "mul", "\t$Rd, $Rn, $Rm",
3416 [(set GPRnopc:$Rd, (mul GPRnopc:$Rn, GPRnopc:$Rm))]>,
3417 Requires<[IsARM, HasV6]> {
3418 let Inst{15-12} = 0b0000;
3419 let Unpredictable{15-12} = 0b1111;
3422 let Constraints = "@earlyclobber $Rd" in
3423 def MULv5: ARMPseudoExpand<(outs GPRnopc:$Rd), (ins GPRnopc:$Rn, GPRnopc:$Rm,
3424 pred:$p, cc_out:$s),
3426 [(set GPRnopc:$Rd, (mul GPRnopc:$Rn, GPRnopc:$Rm))],
3427 (MUL GPRnopc:$Rd, GPRnopc:$Rn, GPRnopc:$Rm, pred:$p, cc_out:$s)>,
3428 Requires<[IsARM, NoV6]>;
3431 def MLA : AsMul1I32<0b0000001, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm, GPR:$Ra),
3432 IIC_iMAC32, "mla", "\t$Rd, $Rn, $Rm, $Ra",
3433 [(set GPR:$Rd, (add (mul GPR:$Rn, GPR:$Rm), GPR:$Ra))]>,
3434 Requires<[IsARM, HasV6]> {
3436 let Inst{15-12} = Ra;
3439 let Constraints = "@earlyclobber $Rd" in
3440 def MLAv5: ARMPseudoExpand<(outs GPR:$Rd),
3441 (ins GPR:$Rn, GPR:$Rm, GPR:$Ra, pred:$p, cc_out:$s),
3443 [(set GPR:$Rd, (add (mul GPR:$Rn, GPR:$Rm), GPR:$Ra))],
3444 (MLA GPR:$Rd, GPR:$Rn, GPR:$Rm, GPR:$Ra, pred:$p, cc_out:$s)>,
3445 Requires<[IsARM, NoV6]>;
3447 def MLS : AMul1I<0b0000011, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm, GPR:$Ra),
3448 IIC_iMAC32, "mls", "\t$Rd, $Rn, $Rm, $Ra",
3449 [(set GPR:$Rd, (sub GPR:$Ra, (mul GPR:$Rn, GPR:$Rm)))]>,
3450 Requires<[IsARM, HasV6T2]> {
3455 let Inst{19-16} = Rd;
3456 let Inst{15-12} = Ra;
3457 let Inst{11-8} = Rm;
3461 // Extra precision multiplies with low / high results
3462 let neverHasSideEffects = 1 in {
3463 let isCommutable = 1 in {
3464 def SMULL : AsMul1I64<0b0000110, (outs GPR:$RdLo, GPR:$RdHi),
3465 (ins GPR:$Rn, GPR:$Rm), IIC_iMUL64,
3466 "smull", "\t$RdLo, $RdHi, $Rn, $Rm", []>,
3467 Requires<[IsARM, HasV6]>;
3469 def UMULL : AsMul1I64<0b0000100, (outs GPR:$RdLo, GPR:$RdHi),
3470 (ins GPR:$Rn, GPR:$Rm), IIC_iMUL64,
3471 "umull", "\t$RdLo, $RdHi, $Rn, $Rm", []>,
3472 Requires<[IsARM, HasV6]>;
3474 let Constraints = "@earlyclobber $RdLo,@earlyclobber $RdHi" in {
3475 def SMULLv5 : ARMPseudoExpand<(outs GPR:$RdLo, GPR:$RdHi),
3476 (ins GPR:$Rn, GPR:$Rm, pred:$p, cc_out:$s),
3478 (SMULL GPR:$RdLo, GPR:$RdHi, GPR:$Rn, GPR:$Rm, pred:$p, cc_out:$s)>,
3479 Requires<[IsARM, NoV6]>;
3481 def UMULLv5 : ARMPseudoExpand<(outs GPR:$RdLo, GPR:$RdHi),
3482 (ins GPR:$Rn, GPR:$Rm, pred:$p, cc_out:$s),
3484 (UMULL GPR:$RdLo, GPR:$RdHi, GPR:$Rn, GPR:$Rm, pred:$p, cc_out:$s)>,
3485 Requires<[IsARM, NoV6]>;
3489 // Multiply + accumulate
3490 def SMLAL : AsMul1I64<0b0000111, (outs GPR:$RdLo, GPR:$RdHi),
3491 (ins GPR:$Rn, GPR:$Rm), IIC_iMAC64,
3492 "smlal", "\t$RdLo, $RdHi, $Rn, $Rm", []>,
3493 Requires<[IsARM, HasV6]>;
3494 def UMLAL : AsMul1I64<0b0000101, (outs GPR:$RdLo, GPR:$RdHi),
3495 (ins GPR:$Rn, GPR:$Rm), IIC_iMAC64,
3496 "umlal", "\t$RdLo, $RdHi, $Rn, $Rm", []>,
3497 Requires<[IsARM, HasV6]>;
3499 def UMAAL : AMul1I <0b0000010, (outs GPR:$RdLo, GPR:$RdHi),
3500 (ins GPR:$Rn, GPR:$Rm), IIC_iMAC64,
3501 "umaal", "\t$RdLo, $RdHi, $Rn, $Rm", []>,
3502 Requires<[IsARM, HasV6]> {
3507 let Inst{19-16} = RdHi;
3508 let Inst{15-12} = RdLo;
3509 let Inst{11-8} = Rm;
3513 let Constraints = "@earlyclobber $RdLo,@earlyclobber $RdHi" in {
3514 def SMLALv5 : ARMPseudoExpand<(outs GPR:$RdLo, GPR:$RdHi),
3515 (ins GPR:$Rn, GPR:$Rm, pred:$p, cc_out:$s),
3517 (SMLAL GPR:$RdLo, GPR:$RdHi, GPR:$Rn, GPR:$Rm, pred:$p, cc_out:$s)>,
3518 Requires<[IsARM, NoV6]>;
3519 def UMLALv5 : ARMPseudoExpand<(outs GPR:$RdLo, GPR:$RdHi),
3520 (ins GPR:$Rn, GPR:$Rm, pred:$p, cc_out:$s),
3522 (UMLAL GPR:$RdLo, GPR:$RdHi, GPR:$Rn, GPR:$Rm, pred:$p, cc_out:$s)>,
3523 Requires<[IsARM, NoV6]>;
3524 def UMAALv5 : ARMPseudoExpand<(outs GPR:$RdLo, GPR:$RdHi),
3525 (ins GPR:$Rn, GPR:$Rm, pred:$p),
3527 (UMAAL GPR:$RdLo, GPR:$RdHi, GPR:$Rn, GPR:$Rm, pred:$p)>,
3528 Requires<[IsARM, NoV6]>;
3531 } // neverHasSideEffects
3533 // Most significant word multiply
3534 def SMMUL : AMul2I <0b0111010, 0b0001, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm),
3535 IIC_iMUL32, "smmul", "\t$Rd, $Rn, $Rm",
3536 [(set GPR:$Rd, (mulhs GPR:$Rn, GPR:$Rm))]>,
3537 Requires<[IsARM, HasV6]> {
3538 let Inst{15-12} = 0b1111;
3541 def SMMULR : AMul2I <0b0111010, 0b0011, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm),
3542 IIC_iMUL32, "smmulr", "\t$Rd, $Rn, $Rm", []>,
3543 Requires<[IsARM, HasV6]> {
3544 let Inst{15-12} = 0b1111;
3547 def SMMLA : AMul2Ia <0b0111010, 0b0001, (outs GPR:$Rd),
3548 (ins GPR:$Rn, GPR:$Rm, GPR:$Ra),
3549 IIC_iMAC32, "smmla", "\t$Rd, $Rn, $Rm, $Ra",
3550 [(set GPR:$Rd, (add (mulhs GPR:$Rn, GPR:$Rm), GPR:$Ra))]>,
3551 Requires<[IsARM, HasV6]>;
3553 def SMMLAR : AMul2Ia <0b0111010, 0b0011, (outs GPR:$Rd),
3554 (ins GPR:$Rn, GPR:$Rm, GPR:$Ra),
3555 IIC_iMAC32, "smmlar", "\t$Rd, $Rn, $Rm, $Ra", []>,
3556 Requires<[IsARM, HasV6]>;
3558 def SMMLS : AMul2Ia <0b0111010, 0b1101, (outs GPR:$Rd),
3559 (ins GPR:$Rn, GPR:$Rm, GPR:$Ra),
3560 IIC_iMAC32, "smmls", "\t$Rd, $Rn, $Rm, $Ra", []>,
3561 Requires<[IsARM, HasV6]>;
3563 def SMMLSR : AMul2Ia <0b0111010, 0b1111, (outs GPR:$Rd),
3564 (ins GPR:$Rn, GPR:$Rm, GPR:$Ra),
3565 IIC_iMAC32, "smmlsr", "\t$Rd, $Rn, $Rm, $Ra", []>,
3566 Requires<[IsARM, HasV6]>;
3568 multiclass AI_smul<string opc, PatFrag opnode> {
3569 def BB : AMulxyI<0b0001011, 0b00, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm),
3570 IIC_iMUL16, !strconcat(opc, "bb"), "\t$Rd, $Rn, $Rm",
3571 [(set GPR:$Rd, (opnode (sext_inreg GPR:$Rn, i16),
3572 (sext_inreg GPR:$Rm, i16)))]>,
3573 Requires<[IsARM, HasV5TE]>;
3575 def BT : AMulxyI<0b0001011, 0b10, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm),
3576 IIC_iMUL16, !strconcat(opc, "bt"), "\t$Rd, $Rn, $Rm",
3577 [(set GPR:$Rd, (opnode (sext_inreg GPR:$Rn, i16),
3578 (sra GPR:$Rm, (i32 16))))]>,
3579 Requires<[IsARM, HasV5TE]>;
3581 def TB : AMulxyI<0b0001011, 0b01, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm),
3582 IIC_iMUL16, !strconcat(opc, "tb"), "\t$Rd, $Rn, $Rm",
3583 [(set GPR:$Rd, (opnode (sra GPR:$Rn, (i32 16)),
3584 (sext_inreg GPR:$Rm, i16)))]>,
3585 Requires<[IsARM, HasV5TE]>;
3587 def TT : AMulxyI<0b0001011, 0b11, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm),
3588 IIC_iMUL16, !strconcat(opc, "tt"), "\t$Rd, $Rn, $Rm",
3589 [(set GPR:$Rd, (opnode (sra GPR:$Rn, (i32 16)),
3590 (sra GPR:$Rm, (i32 16))))]>,
3591 Requires<[IsARM, HasV5TE]>;
3593 def WB : AMulxyI<0b0001001, 0b01, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm),
3594 IIC_iMUL16, !strconcat(opc, "wb"), "\t$Rd, $Rn, $Rm",
3595 [(set GPR:$Rd, (sra (opnode GPR:$Rn,
3596 (sext_inreg GPR:$Rm, i16)), (i32 16)))]>,
3597 Requires<[IsARM, HasV5TE]>;
3599 def WT : AMulxyI<0b0001001, 0b11, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm),
3600 IIC_iMUL16, !strconcat(opc, "wt"), "\t$Rd, $Rn, $Rm",
3601 [(set GPR:$Rd, (sra (opnode GPR:$Rn,
3602 (sra GPR:$Rm, (i32 16))), (i32 16)))]>,
3603 Requires<[IsARM, HasV5TE]>;
3607 multiclass AI_smla<string opc, PatFrag opnode> {
3608 let DecoderMethod = "DecodeSMLAInstruction" in {
3609 def BB : AMulxyIa<0b0001000, 0b00, (outs GPRnopc:$Rd),
3610 (ins GPRnopc:$Rn, GPRnopc:$Rm, GPR:$Ra),
3611 IIC_iMAC16, !strconcat(opc, "bb"), "\t$Rd, $Rn, $Rm, $Ra",
3612 [(set GPRnopc:$Rd, (add GPR:$Ra,
3613 (opnode (sext_inreg GPRnopc:$Rn, i16),
3614 (sext_inreg GPRnopc:$Rm, i16))))]>,
3615 Requires<[IsARM, HasV5TE]>;
3617 def BT : AMulxyIa<0b0001000, 0b10, (outs GPRnopc:$Rd),
3618 (ins GPRnopc:$Rn, GPRnopc:$Rm, GPR:$Ra),
3619 IIC_iMAC16, !strconcat(opc, "bt"), "\t$Rd, $Rn, $Rm, $Ra",
3621 (add GPR:$Ra, (opnode (sext_inreg GPRnopc:$Rn, i16),
3622 (sra GPRnopc:$Rm, (i32 16)))))]>,
3623 Requires<[IsARM, HasV5TE]>;
3625 def TB : AMulxyIa<0b0001000, 0b01, (outs GPRnopc:$Rd),
3626 (ins GPRnopc:$Rn, GPRnopc:$Rm, GPR:$Ra),
3627 IIC_iMAC16, !strconcat(opc, "tb"), "\t$Rd, $Rn, $Rm, $Ra",
3629 (add GPR:$Ra, (opnode (sra GPRnopc:$Rn, (i32 16)),
3630 (sext_inreg GPRnopc:$Rm, i16))))]>,
3631 Requires<[IsARM, HasV5TE]>;
3633 def TT : AMulxyIa<0b0001000, 0b11, (outs GPRnopc:$Rd),
3634 (ins GPRnopc:$Rn, GPRnopc:$Rm, GPR:$Ra),
3635 IIC_iMAC16, !strconcat(opc, "tt"), "\t$Rd, $Rn, $Rm, $Ra",
3637 (add GPR:$Ra, (opnode (sra GPRnopc:$Rn, (i32 16)),
3638 (sra GPRnopc:$Rm, (i32 16)))))]>,
3639 Requires<[IsARM, HasV5TE]>;
3641 def WB : AMulxyIa<0b0001001, 0b00, (outs GPRnopc:$Rd),
3642 (ins GPRnopc:$Rn, GPRnopc:$Rm, GPR:$Ra),
3643 IIC_iMAC16, !strconcat(opc, "wb"), "\t$Rd, $Rn, $Rm, $Ra",
3645 (add GPR:$Ra, (sra (opnode GPRnopc:$Rn,
3646 (sext_inreg GPRnopc:$Rm, i16)), (i32 16))))]>,
3647 Requires<[IsARM, HasV5TE]>;
3649 def WT : AMulxyIa<0b0001001, 0b10, (outs GPRnopc:$Rd),
3650 (ins GPRnopc:$Rn, GPRnopc:$Rm, GPR:$Ra),
3651 IIC_iMAC16, !strconcat(opc, "wt"), "\t$Rd, $Rn, $Rm, $Ra",
3653 (add GPR:$Ra, (sra (opnode GPRnopc:$Rn,
3654 (sra GPRnopc:$Rm, (i32 16))), (i32 16))))]>,
3655 Requires<[IsARM, HasV5TE]>;
3659 defm SMUL : AI_smul<"smul", BinOpFrag<(mul node:$LHS, node:$RHS)>>;
3660 defm SMLA : AI_smla<"smla", BinOpFrag<(mul node:$LHS, node:$RHS)>>;
3662 // Halfword multiply accumulate long: SMLAL<x><y>.
3663 def SMLALBB : AMulxyI64<0b0001010, 0b00, (outs GPRnopc:$RdLo, GPRnopc:$RdHi),
3664 (ins GPRnopc:$Rn, GPRnopc:$Rm),
3665 IIC_iMAC64, "smlalbb", "\t$RdLo, $RdHi, $Rn, $Rm", []>,
3666 Requires<[IsARM, HasV5TE]>;
3668 def SMLALBT : AMulxyI64<0b0001010, 0b10, (outs GPRnopc:$RdLo, GPRnopc:$RdHi),
3669 (ins GPRnopc:$Rn, GPRnopc:$Rm),
3670 IIC_iMAC64, "smlalbt", "\t$RdLo, $RdHi, $Rn, $Rm", []>,
3671 Requires<[IsARM, HasV5TE]>;
3673 def SMLALTB : AMulxyI64<0b0001010, 0b01, (outs GPRnopc:$RdLo, GPRnopc:$RdHi),
3674 (ins GPRnopc:$Rn, GPRnopc:$Rm),
3675 IIC_iMAC64, "smlaltb", "\t$RdLo, $RdHi, $Rn, $Rm", []>,
3676 Requires<[IsARM, HasV5TE]>;
3678 def SMLALTT : AMulxyI64<0b0001010, 0b11, (outs GPRnopc:$RdLo, GPRnopc:$RdHi),
3679 (ins GPRnopc:$Rn, GPRnopc:$Rm),
3680 IIC_iMAC64, "smlaltt", "\t$RdLo, $RdHi, $Rn, $Rm", []>,
3681 Requires<[IsARM, HasV5TE]>;
3683 // Helper class for AI_smld.
3684 class AMulDualIbase<bit long, bit sub, bit swap, dag oops, dag iops,
3685 InstrItinClass itin, string opc, string asm>
3686 : AI<oops, iops, MulFrm, itin, opc, asm, []>, Requires<[IsARM, HasV6]> {
3689 let Inst{27-23} = 0b01110;
3690 let Inst{22} = long;
3691 let Inst{21-20} = 0b00;
3692 let Inst{11-8} = Rm;
3699 class AMulDualI<bit long, bit sub, bit swap, dag oops, dag iops,
3700 InstrItinClass itin, string opc, string asm>
3701 : AMulDualIbase<long, sub, swap, oops, iops, itin, opc, asm> {
3703 let Inst{15-12} = 0b1111;
3704 let Inst{19-16} = Rd;
3706 class AMulDualIa<bit long, bit sub, bit swap, dag oops, dag iops,
3707 InstrItinClass itin, string opc, string asm>
3708 : AMulDualIbase<long, sub, swap, oops, iops, itin, opc, asm> {
3711 let Inst{19-16} = Rd;
3712 let Inst{15-12} = Ra;
3714 class AMulDualI64<bit long, bit sub, bit swap, dag oops, dag iops,
3715 InstrItinClass itin, string opc, string asm>
3716 : AMulDualIbase<long, sub, swap, oops, iops, itin, opc, asm> {
3719 let Inst{19-16} = RdHi;
3720 let Inst{15-12} = RdLo;
3723 multiclass AI_smld<bit sub, string opc> {
3725 def D : AMulDualIa<0, sub, 0, (outs GPRnopc:$Rd),
3726 (ins GPRnopc:$Rn, GPRnopc:$Rm, GPR:$Ra),
3727 NoItinerary, !strconcat(opc, "d"), "\t$Rd, $Rn, $Rm, $Ra">;
3729 def DX: AMulDualIa<0, sub, 1, (outs GPRnopc:$Rd),
3730 (ins GPRnopc:$Rn, GPRnopc:$Rm, GPR:$Ra),
3731 NoItinerary, !strconcat(opc, "dx"), "\t$Rd, $Rn, $Rm, $Ra">;
3733 def LD: AMulDualI64<1, sub, 0, (outs GPRnopc:$RdLo, GPRnopc:$RdHi),
3734 (ins GPRnopc:$Rn, GPRnopc:$Rm), NoItinerary,
3735 !strconcat(opc, "ld"), "\t$RdLo, $RdHi, $Rn, $Rm">;
3737 def LDX : AMulDualI64<1, sub, 1, (outs GPRnopc:$RdLo, GPRnopc:$RdHi),
3738 (ins GPRnopc:$Rn, GPRnopc:$Rm), NoItinerary,
3739 !strconcat(opc, "ldx"),"\t$RdLo, $RdHi, $Rn, $Rm">;
3743 defm SMLA : AI_smld<0, "smla">;
3744 defm SMLS : AI_smld<1, "smls">;
3746 multiclass AI_sdml<bit sub, string opc> {
3748 def D:AMulDualI<0, sub, 0, (outs GPRnopc:$Rd), (ins GPRnopc:$Rn, GPRnopc:$Rm),
3749 NoItinerary, !strconcat(opc, "d"), "\t$Rd, $Rn, $Rm">;
3750 def DX:AMulDualI<0, sub, 1, (outs GPRnopc:$Rd),(ins GPRnopc:$Rn, GPRnopc:$Rm),
3751 NoItinerary, !strconcat(opc, "dx"), "\t$Rd, $Rn, $Rm">;
3754 defm SMUA : AI_sdml<0, "smua">;
3755 defm SMUS : AI_sdml<1, "smus">;
3757 //===----------------------------------------------------------------------===//
3758 // Misc. Arithmetic Instructions.
3761 def CLZ : AMiscA1I<0b000010110, 0b0001, (outs GPR:$Rd), (ins GPR:$Rm),
3762 IIC_iUNAr, "clz", "\t$Rd, $Rm",
3763 [(set GPR:$Rd, (ctlz GPR:$Rm))]>, Requires<[IsARM, HasV5T]>;
3765 def RBIT : AMiscA1I<0b01101111, 0b0011, (outs GPR:$Rd), (ins GPR:$Rm),
3766 IIC_iUNAr, "rbit", "\t$Rd, $Rm",
3767 [(set GPR:$Rd, (ARMrbit GPR:$Rm))]>,
3768 Requires<[IsARM, HasV6T2]>;
3770 def REV : AMiscA1I<0b01101011, 0b0011, (outs GPR:$Rd), (ins GPR:$Rm),
3771 IIC_iUNAr, "rev", "\t$Rd, $Rm",
3772 [(set GPR:$Rd, (bswap GPR:$Rm))]>, Requires<[IsARM, HasV6]>;
3774 let AddedComplexity = 5 in
3775 def REV16 : AMiscA1I<0b01101011, 0b1011, (outs GPR:$Rd), (ins GPR:$Rm),
3776 IIC_iUNAr, "rev16", "\t$Rd, $Rm",
3777 [(set GPR:$Rd, (rotr (bswap GPR:$Rm), (i32 16)))]>,
3778 Requires<[IsARM, HasV6]>;
3780 let AddedComplexity = 5 in
3781 def REVSH : AMiscA1I<0b01101111, 0b1011, (outs GPR:$Rd), (ins GPR:$Rm),
3782 IIC_iUNAr, "revsh", "\t$Rd, $Rm",
3783 [(set GPR:$Rd, (sra (bswap GPR:$Rm), (i32 16)))]>,
3784 Requires<[IsARM, HasV6]>;
3786 def : ARMV6Pat<(or (sra (shl GPR:$Rm, (i32 24)), (i32 16)),
3787 (and (srl GPR:$Rm, (i32 8)), 0xFF)),
3790 def PKHBT : APKHI<0b01101000, 0, (outs GPRnopc:$Rd),
3791 (ins GPRnopc:$Rn, GPRnopc:$Rm, pkh_lsl_amt:$sh),
3792 IIC_iALUsi, "pkhbt", "\t$Rd, $Rn, $Rm$sh",
3793 [(set GPRnopc:$Rd, (or (and GPRnopc:$Rn, 0xFFFF),
3794 (and (shl GPRnopc:$Rm, pkh_lsl_amt:$sh),
3796 Requires<[IsARM, HasV6]>;
3798 // Alternate cases for PKHBT where identities eliminate some nodes.
3799 def : ARMV6Pat<(or (and GPRnopc:$Rn, 0xFFFF), (and GPRnopc:$Rm, 0xFFFF0000)),
3800 (PKHBT GPRnopc:$Rn, GPRnopc:$Rm, 0)>;
3801 def : ARMV6Pat<(or (and GPRnopc:$Rn, 0xFFFF), (shl GPRnopc:$Rm, imm16_31:$sh)),
3802 (PKHBT GPRnopc:$Rn, GPRnopc:$Rm, imm16_31:$sh)>;
3804 // Note: Shifts of 1-15 bits will be transformed to srl instead of sra and
3805 // will match the pattern below.
3806 def PKHTB : APKHI<0b01101000, 1, (outs GPRnopc:$Rd),
3807 (ins GPRnopc:$Rn, GPRnopc:$Rm, pkh_asr_amt:$sh),
3808 IIC_iBITsi, "pkhtb", "\t$Rd, $Rn, $Rm$sh",
3809 [(set GPRnopc:$Rd, (or (and GPRnopc:$Rn, 0xFFFF0000),
3810 (and (sra GPRnopc:$Rm, pkh_asr_amt:$sh),
3812 Requires<[IsARM, HasV6]>;
3814 // Alternate cases for PKHTB where identities eliminate some nodes. Note that
3815 // a shift amount of 0 is *not legal* here, it is PKHBT instead.
3816 def : ARMV6Pat<(or (and GPRnopc:$src1, 0xFFFF0000),
3817 (srl GPRnopc:$src2, imm16_31:$sh)),
3818 (PKHTB GPRnopc:$src1, GPRnopc:$src2, imm16_31:$sh)>;
3819 def : ARMV6Pat<(or (and GPRnopc:$src1, 0xFFFF0000),
3820 (and (srl GPRnopc:$src2, imm1_15:$sh), 0xFFFF)),
3821 (PKHTB GPRnopc:$src1, GPRnopc:$src2, imm1_15:$sh)>;
3823 //===----------------------------------------------------------------------===//
3824 // Comparison Instructions...
3827 defm CMP : AI1_cmp_irs<0b1010, "cmp",
3828 IIC_iCMPi, IIC_iCMPr, IIC_iCMPsr,
3829 BinOpFrag<(ARMcmp node:$LHS, node:$RHS)>>;
3831 // ARMcmpZ can re-use the above instruction definitions.
3832 def : ARMPat<(ARMcmpZ GPR:$src, so_imm:$imm),
3833 (CMPri GPR:$src, so_imm:$imm)>;
3834 def : ARMPat<(ARMcmpZ GPR:$src, GPR:$rhs),
3835 (CMPrr GPR:$src, GPR:$rhs)>;
3836 def : ARMPat<(ARMcmpZ GPR:$src, so_reg_imm:$rhs),
3837 (CMPrsi GPR:$src, so_reg_imm:$rhs)>;
3838 def : ARMPat<(ARMcmpZ GPR:$src, so_reg_reg:$rhs),
3839 (CMPrsr GPR:$src, so_reg_reg:$rhs)>;
3841 // CMN register-integer
3842 let isCompare = 1, Defs = [CPSR] in {
3843 def CMNri : AI1<0b1011, (outs), (ins GPR:$Rn, so_imm:$imm), DPFrm, IIC_iCMPi,
3844 "cmn", "\t$Rn, $imm",
3845 [(ARMcmn GPR:$Rn, so_imm:$imm)]> {
3850 let Inst{19-16} = Rn;
3851 let Inst{15-12} = 0b0000;
3852 let Inst{11-0} = imm;
3854 let Unpredictable{15-12} = 0b1111;
3857 // CMN register-register/shift
3858 def CMNzrr : AI1<0b1011, (outs), (ins GPR:$Rn, GPR:$Rm), DPFrm, IIC_iCMPr,
3859 "cmn", "\t$Rn, $Rm",
3860 [(BinOpFrag<(ARMcmpZ node:$LHS,(ineg node:$RHS))>
3861 GPR:$Rn, GPR:$Rm)]> {
3864 let isCommutable = 1;
3867 let Inst{19-16} = Rn;
3868 let Inst{15-12} = 0b0000;
3869 let Inst{11-4} = 0b00000000;
3872 let Unpredictable{15-12} = 0b1111;
3875 def CMNzrsi : AI1<0b1011, (outs),
3876 (ins GPR:$Rn, so_reg_imm:$shift), DPSoRegImmFrm, IIC_iCMPsr,
3877 "cmn", "\t$Rn, $shift",
3878 [(BinOpFrag<(ARMcmpZ node:$LHS,(ineg node:$RHS))>
3879 GPR:$Rn, so_reg_imm:$shift)]> {
3884 let Inst{19-16} = Rn;
3885 let Inst{15-12} = 0b0000;
3886 let Inst{11-5} = shift{11-5};
3888 let Inst{3-0} = shift{3-0};
3890 let Unpredictable{15-12} = 0b1111;
3893 def CMNzrsr : AI1<0b1011, (outs),
3894 (ins GPRnopc:$Rn, so_reg_reg:$shift), DPSoRegRegFrm, IIC_iCMPsr,
3895 "cmn", "\t$Rn, $shift",
3896 [(BinOpFrag<(ARMcmpZ node:$LHS,(ineg node:$RHS))>
3897 GPRnopc:$Rn, so_reg_reg:$shift)]> {
3902 let Inst{19-16} = Rn;
3903 let Inst{15-12} = 0b0000;
3904 let Inst{11-8} = shift{11-8};
3906 let Inst{6-5} = shift{6-5};
3908 let Inst{3-0} = shift{3-0};
3910 let Unpredictable{15-12} = 0b1111;
3915 def : ARMPat<(ARMcmp GPR:$src, so_imm_neg:$imm),
3916 (CMNri GPR:$src, so_imm_neg:$imm)>;
3918 def : ARMPat<(ARMcmpZ GPR:$src, so_imm_neg:$imm),
3919 (CMNri GPR:$src, so_imm_neg:$imm)>;
3921 // Note that TST/TEQ don't set all the same flags that CMP does!
3922 defm TST : AI1_cmp_irs<0b1000, "tst",
3923 IIC_iTSTi, IIC_iTSTr, IIC_iTSTsr,
3924 BinOpFrag<(ARMcmpZ (and_su node:$LHS, node:$RHS), 0)>, 1>;
3925 defm TEQ : AI1_cmp_irs<0b1001, "teq",
3926 IIC_iTSTi, IIC_iTSTr, IIC_iTSTsr,
3927 BinOpFrag<(ARMcmpZ (xor_su node:$LHS, node:$RHS), 0)>, 1>;
3929 // Pseudo i64 compares for some floating point compares.
3930 let usesCustomInserter = 1, isBranch = 1, isTerminator = 1,
3932 def BCCi64 : PseudoInst<(outs),
3933 (ins i32imm:$cc, GPR:$lhs1, GPR:$lhs2, GPR:$rhs1, GPR:$rhs2, brtarget:$dst),
3935 [(ARMBcci64 imm:$cc, GPR:$lhs1, GPR:$lhs2, GPR:$rhs1, GPR:$rhs2, bb:$dst)]>;
3937 def BCCZi64 : PseudoInst<(outs),
3938 (ins i32imm:$cc, GPR:$lhs1, GPR:$lhs2, brtarget:$dst), IIC_Br,
3939 [(ARMBcci64 imm:$cc, GPR:$lhs1, GPR:$lhs2, 0, 0, bb:$dst)]>;
3940 } // usesCustomInserter
3943 // Conditional moves
3944 // FIXME: should be able to write a pattern for ARMcmov, but can't use
3945 // a two-value operand where a dag node expects two operands. :(
3946 let neverHasSideEffects = 1 in {
3948 let isCommutable = 1, isSelect = 1 in
3949 def MOVCCr : ARMPseudoInst<(outs GPR:$Rd), (ins GPR:$false, GPR:$Rm, pred:$p),
3951 [/*(set GPR:$Rd, (ARMcmov GPR:$false, GPR:$Rm, imm:$cc, CCR:$ccr))*/]>,
3952 RegConstraint<"$false = $Rd">;
3954 def MOVCCsi : ARMPseudoInst<(outs GPR:$Rd),
3955 (ins GPR:$false, so_reg_imm:$shift, pred:$p),
3957 [/*(set GPR:$Rd, (ARMcmov GPR:$false, so_reg_imm:$shift,
3958 imm:$cc, CCR:$ccr))*/]>,
3959 RegConstraint<"$false = $Rd">;
3960 def MOVCCsr : ARMPseudoInst<(outs GPR:$Rd),
3961 (ins GPR:$false, so_reg_reg:$shift, pred:$p),
3963 [/*(set GPR:$Rd, (ARMcmov GPR:$false, so_reg_reg:$shift,
3964 imm:$cc, CCR:$ccr))*/]>,
3965 RegConstraint<"$false = $Rd">;
3968 let isMoveImm = 1 in
3969 def MOVCCi16 : ARMPseudoInst<(outs GPR:$Rd),
3970 (ins GPR:$false, imm0_65535_expr:$imm, pred:$p),
3973 RegConstraint<"$false = $Rd">, Requires<[IsARM, HasV6T2]>;
3975 let isMoveImm = 1 in
3976 def MOVCCi : ARMPseudoInst<(outs GPR:$Rd),
3977 (ins GPR:$false, so_imm:$imm, pred:$p),
3979 [/*(set GPR:$Rd, (ARMcmov GPR:$false, so_imm:$imm, imm:$cc, CCR:$ccr))*/]>,
3980 RegConstraint<"$false = $Rd">;
3982 // Two instruction predicate mov immediate.
3983 let isMoveImm = 1 in
3984 def MOVCCi32imm : ARMPseudoInst<(outs GPR:$Rd),
3985 (ins GPR:$false, i32imm:$src, pred:$p),
3986 8, IIC_iCMOVix2, []>, RegConstraint<"$false = $Rd">;
3988 let isMoveImm = 1 in
3989 def MVNCCi : ARMPseudoInst<(outs GPR:$Rd),
3990 (ins GPR:$false, so_imm:$imm, pred:$p),
3992 [/*(set GPR:$Rd, (ARMcmov GPR:$false, so_imm_not:$imm, imm:$cc, CCR:$ccr))*/]>,
3993 RegConstraint<"$false = $Rd">;
3995 // Conditional instructions
3996 multiclass AsI1_bincc_irs<Instruction iri, Instruction irr, Instruction irsi,
3998 InstrItinClass iii, InstrItinClass iir,
3999 InstrItinClass iis> {
4000 def ri : ARMPseudoExpand<(outs GPR:$Rd),
4001 (ins GPR:$Rfalse, GPR:$Rn, so_imm:$imm,
4002 pred:$p, cc_out:$s),
4004 (iri GPR:$Rd, GPR:$Rn, so_imm:$imm, pred:$p, cc_out:$s)>,
4005 RegConstraint<"$Rfalse = $Rd">;
4006 def rr : ARMPseudoExpand<(outs GPR:$Rd),
4007 (ins GPR:$Rfalse, GPR:$Rn, GPR:$Rm,
4008 pred:$p, cc_out:$s),
4010 (irr GPR:$Rd, GPR:$Rn, GPR:$Rm, pred:$p, cc_out:$s)>,
4011 RegConstraint<"$Rfalse = $Rd">;
4012 def rsi : ARMPseudoExpand<(outs GPR:$Rd),
4013 (ins GPR:$Rfalse, GPR:$Rn, so_reg_imm:$shift,
4014 pred:$p, cc_out:$s),
4016 (irsi GPR:$Rd, GPR:$Rn, so_reg_imm:$shift, pred:$p, cc_out:$s)>,
4017 RegConstraint<"$Rfalse = $Rd">;
4018 def rsr : ARMPseudoExpand<(outs GPRnopc:$Rd),
4019 (ins GPRnopc:$Rfalse, GPRnopc:$Rn, so_reg_reg:$shift,
4020 pred:$p, cc_out:$s),
4022 (irsr GPR:$Rd, GPR:$Rn, so_reg_reg:$shift, pred:$p, cc_out:$s)>,
4023 RegConstraint<"$Rfalse = $Rd">;
4026 defm ANDCC : AsI1_bincc_irs<ANDri, ANDrr, ANDrsi, ANDrsr,
4027 IIC_iBITi, IIC_iBITr, IIC_iBITsr>;
4028 defm ORRCC : AsI1_bincc_irs<ORRri, ORRrr, ORRrsi, ORRrsr,
4029 IIC_iBITi, IIC_iBITr, IIC_iBITsr>;
4030 defm EORCC : AsI1_bincc_irs<EORri, EORrr, EORrsi, EORrsr,
4031 IIC_iBITi, IIC_iBITr, IIC_iBITsr>;
4032 defm ADDCC : AsI1_bincc_irs<ADDri, ADDrr, ADDrsi, ADDrsr,
4033 IIC_iBITi, IIC_iBITr, IIC_iBITsr>;
4034 defm SUBCC : AsI1_bincc_irs<SUBri, SUBrr, SUBrsi, SUBrsr,
4035 IIC_iBITi, IIC_iBITr, IIC_iBITsr>;
4037 } // neverHasSideEffects
4040 //===----------------------------------------------------------------------===//
4041 // Atomic operations intrinsics
4044 def MemBarrierOptOperand : AsmOperandClass {
4045 let Name = "MemBarrierOpt";
4046 let ParserMethod = "parseMemBarrierOptOperand";
4048 def memb_opt : Operand<i32> {
4049 let PrintMethod = "printMemBOption";
4050 let ParserMatchClass = MemBarrierOptOperand;
4051 let DecoderMethod = "DecodeMemBarrierOption";
4054 // memory barriers protect the atomic sequences
4055 let hasSideEffects = 1 in {
4056 def DMB : AInoP<(outs), (ins memb_opt:$opt), MiscFrm, NoItinerary,
4057 "dmb", "\t$opt", [(ARMMemBarrier (i32 imm:$opt))]>,
4058 Requires<[IsARM, HasDB]> {
4060 let Inst{31-4} = 0xf57ff05;
4061 let Inst{3-0} = opt;
4065 def DSB : AInoP<(outs), (ins memb_opt:$opt), MiscFrm, NoItinerary,
4066 "dsb", "\t$opt", []>,
4067 Requires<[IsARM, HasDB]> {
4069 let Inst{31-4} = 0xf57ff04;
4070 let Inst{3-0} = opt;
4073 // ISB has only full system option
4074 def ISB : AInoP<(outs), (ins memb_opt:$opt), MiscFrm, NoItinerary,
4075 "isb", "\t$opt", []>,
4076 Requires<[IsARM, HasDB]> {
4078 let Inst{31-4} = 0xf57ff06;
4079 let Inst{3-0} = opt;
4082 // Pseudo instruction that combines movs + predicated rsbmi
4083 // to implement integer ABS
4084 let usesCustomInserter = 1, Defs = [CPSR] in
4085 def ABS : ARMPseudoInst<(outs GPR:$dst), (ins GPR:$src), 8, NoItinerary, []>;
4087 let usesCustomInserter = 1 in {
4088 let Defs = [CPSR] in {
4089 def ATOMIC_LOAD_ADD_I8 : PseudoInst<
4090 (outs GPR:$dst), (ins GPR:$ptr, GPR:$incr), NoItinerary,
4091 [(set GPR:$dst, (atomic_load_add_8 GPR:$ptr, GPR:$incr))]>;
4092 def ATOMIC_LOAD_SUB_I8 : PseudoInst<
4093 (outs GPR:$dst), (ins GPR:$ptr, GPR:$incr), NoItinerary,
4094 [(set GPR:$dst, (atomic_load_sub_8 GPR:$ptr, GPR:$incr))]>;
4095 def ATOMIC_LOAD_AND_I8 : PseudoInst<
4096 (outs GPR:$dst), (ins GPR:$ptr, GPR:$incr), NoItinerary,
4097 [(set GPR:$dst, (atomic_load_and_8 GPR:$ptr, GPR:$incr))]>;
4098 def ATOMIC_LOAD_OR_I8 : PseudoInst<
4099 (outs GPR:$dst), (ins GPR:$ptr, GPR:$incr), NoItinerary,
4100 [(set GPR:$dst, (atomic_load_or_8 GPR:$ptr, GPR:$incr))]>;
4101 def ATOMIC_LOAD_XOR_I8 : PseudoInst<
4102 (outs GPR:$dst), (ins GPR:$ptr, GPR:$incr), NoItinerary,
4103 [(set GPR:$dst, (atomic_load_xor_8 GPR:$ptr, GPR:$incr))]>;
4104 def ATOMIC_LOAD_NAND_I8 : PseudoInst<
4105 (outs GPR:$dst), (ins GPR:$ptr, GPR:$incr), NoItinerary,
4106 [(set GPR:$dst, (atomic_load_nand_8 GPR:$ptr, GPR:$incr))]>;
4107 def ATOMIC_LOAD_MIN_I8 : PseudoInst<
4108 (outs GPR:$dst), (ins GPR:$ptr, GPR:$val), NoItinerary,
4109 [(set GPR:$dst, (atomic_load_min_8 GPR:$ptr, GPR:$val))]>;
4110 def ATOMIC_LOAD_MAX_I8 : PseudoInst<
4111 (outs GPR:$dst), (ins GPR:$ptr, GPR:$val), NoItinerary,
4112 [(set GPR:$dst, (atomic_load_max_8 GPR:$ptr, GPR:$val))]>;
4113 def ATOMIC_LOAD_UMIN_I8 : PseudoInst<
4114 (outs GPR:$dst), (ins GPR:$ptr, GPR:$val), NoItinerary,
4115 [(set GPR:$dst, (atomic_load_umin_8 GPR:$ptr, GPR:$val))]>;
4116 def ATOMIC_LOAD_UMAX_I8 : PseudoInst<
4117 (outs GPR:$dst), (ins GPR:$ptr, GPR:$val), NoItinerary,
4118 [(set GPR:$dst, (atomic_load_umax_8 GPR:$ptr, GPR:$val))]>;
4119 def ATOMIC_LOAD_ADD_I16 : PseudoInst<
4120 (outs GPR:$dst), (ins GPR:$ptr, GPR:$incr), NoItinerary,
4121 [(set GPR:$dst, (atomic_load_add_16 GPR:$ptr, GPR:$incr))]>;
4122 def ATOMIC_LOAD_SUB_I16 : PseudoInst<
4123 (outs GPR:$dst), (ins GPR:$ptr, GPR:$incr), NoItinerary,
4124 [(set GPR:$dst, (atomic_load_sub_16 GPR:$ptr, GPR:$incr))]>;
4125 def ATOMIC_LOAD_AND_I16 : PseudoInst<
4126 (outs GPR:$dst), (ins GPR:$ptr, GPR:$incr), NoItinerary,
4127 [(set GPR:$dst, (atomic_load_and_16 GPR:$ptr, GPR:$incr))]>;
4128 def ATOMIC_LOAD_OR_I16 : PseudoInst<
4129 (outs GPR:$dst), (ins GPR:$ptr, GPR:$incr), NoItinerary,
4130 [(set GPR:$dst, (atomic_load_or_16 GPR:$ptr, GPR:$incr))]>;
4131 def ATOMIC_LOAD_XOR_I16 : PseudoInst<
4132 (outs GPR:$dst), (ins GPR:$ptr, GPR:$incr), NoItinerary,
4133 [(set GPR:$dst, (atomic_load_xor_16 GPR:$ptr, GPR:$incr))]>;
4134 def ATOMIC_LOAD_NAND_I16 : PseudoInst<
4135 (outs GPR:$dst), (ins GPR:$ptr, GPR:$incr), NoItinerary,
4136 [(set GPR:$dst, (atomic_load_nand_16 GPR:$ptr, GPR:$incr))]>;
4137 def ATOMIC_LOAD_MIN_I16 : PseudoInst<
4138 (outs GPR:$dst), (ins GPR:$ptr, GPR:$val), NoItinerary,
4139 [(set GPR:$dst, (atomic_load_min_16 GPR:$ptr, GPR:$val))]>;
4140 def ATOMIC_LOAD_MAX_I16 : PseudoInst<
4141 (outs GPR:$dst), (ins GPR:$ptr, GPR:$val), NoItinerary,
4142 [(set GPR:$dst, (atomic_load_max_16 GPR:$ptr, GPR:$val))]>;
4143 def ATOMIC_LOAD_UMIN_I16 : PseudoInst<
4144 (outs GPR:$dst), (ins GPR:$ptr, GPR:$val), NoItinerary,
4145 [(set GPR:$dst, (atomic_load_umin_16 GPR:$ptr, GPR:$val))]>;
4146 def ATOMIC_LOAD_UMAX_I16 : PseudoInst<
4147 (outs GPR:$dst), (ins GPR:$ptr, GPR:$val), NoItinerary,
4148 [(set GPR:$dst, (atomic_load_umax_16 GPR:$ptr, GPR:$val))]>;
4149 def ATOMIC_LOAD_ADD_I32 : PseudoInst<
4150 (outs GPR:$dst), (ins GPR:$ptr, GPR:$incr), NoItinerary,
4151 [(set GPR:$dst, (atomic_load_add_32 GPR:$ptr, GPR:$incr))]>;
4152 def ATOMIC_LOAD_SUB_I32 : PseudoInst<
4153 (outs GPR:$dst), (ins GPR:$ptr, GPR:$incr), NoItinerary,
4154 [(set GPR:$dst, (atomic_load_sub_32 GPR:$ptr, GPR:$incr))]>;
4155 def ATOMIC_LOAD_AND_I32 : PseudoInst<
4156 (outs GPR:$dst), (ins GPR:$ptr, GPR:$incr), NoItinerary,
4157 [(set GPR:$dst, (atomic_load_and_32 GPR:$ptr, GPR:$incr))]>;
4158 def ATOMIC_LOAD_OR_I32 : PseudoInst<
4159 (outs GPR:$dst), (ins GPR:$ptr, GPR:$incr), NoItinerary,
4160 [(set GPR:$dst, (atomic_load_or_32 GPR:$ptr, GPR:$incr))]>;
4161 def ATOMIC_LOAD_XOR_I32 : PseudoInst<
4162 (outs GPR:$dst), (ins GPR:$ptr, GPR:$incr), NoItinerary,
4163 [(set GPR:$dst, (atomic_load_xor_32 GPR:$ptr, GPR:$incr))]>;
4164 def ATOMIC_LOAD_NAND_I32 : PseudoInst<
4165 (outs GPR:$dst), (ins GPR:$ptr, GPR:$incr), NoItinerary,
4166 [(set GPR:$dst, (atomic_load_nand_32 GPR:$ptr, GPR:$incr))]>;
4167 def ATOMIC_LOAD_MIN_I32 : PseudoInst<
4168 (outs GPR:$dst), (ins GPR:$ptr, GPR:$val), NoItinerary,
4169 [(set GPR:$dst, (atomic_load_min_32 GPR:$ptr, GPR:$val))]>;
4170 def ATOMIC_LOAD_MAX_I32 : PseudoInst<
4171 (outs GPR:$dst), (ins GPR:$ptr, GPR:$val), NoItinerary,
4172 [(set GPR:$dst, (atomic_load_max_32 GPR:$ptr, GPR:$val))]>;
4173 def ATOMIC_LOAD_UMIN_I32 : PseudoInst<
4174 (outs GPR:$dst), (ins GPR:$ptr, GPR:$val), NoItinerary,
4175 [(set GPR:$dst, (atomic_load_umin_32 GPR:$ptr, GPR:$val))]>;
4176 def ATOMIC_LOAD_UMAX_I32 : PseudoInst<
4177 (outs GPR:$dst), (ins GPR:$ptr, GPR:$val), NoItinerary,
4178 [(set GPR:$dst, (atomic_load_umax_32 GPR:$ptr, GPR:$val))]>;
4180 def ATOMIC_SWAP_I8 : PseudoInst<
4181 (outs GPR:$dst), (ins GPR:$ptr, GPR:$new), NoItinerary,
4182 [(set GPR:$dst, (atomic_swap_8 GPR:$ptr, GPR:$new))]>;
4183 def ATOMIC_SWAP_I16 : PseudoInst<
4184 (outs GPR:$dst), (ins GPR:$ptr, GPR:$new), NoItinerary,
4185 [(set GPR:$dst, (atomic_swap_16 GPR:$ptr, GPR:$new))]>;
4186 def ATOMIC_SWAP_I32 : PseudoInst<
4187 (outs GPR:$dst), (ins GPR:$ptr, GPR:$new), NoItinerary,
4188 [(set GPR:$dst, (atomic_swap_32 GPR:$ptr, GPR:$new))]>;
4190 def ATOMIC_CMP_SWAP_I8 : PseudoInst<
4191 (outs GPR:$dst), (ins GPR:$ptr, GPR:$old, GPR:$new), NoItinerary,
4192 [(set GPR:$dst, (atomic_cmp_swap_8 GPR:$ptr, GPR:$old, GPR:$new))]>;
4193 def ATOMIC_CMP_SWAP_I16 : PseudoInst<
4194 (outs GPR:$dst), (ins GPR:$ptr, GPR:$old, GPR:$new), NoItinerary,
4195 [(set GPR:$dst, (atomic_cmp_swap_16 GPR:$ptr, GPR:$old, GPR:$new))]>;
4196 def ATOMIC_CMP_SWAP_I32 : PseudoInst<
4197 (outs GPR:$dst), (ins GPR:$ptr, GPR:$old, GPR:$new), NoItinerary,
4198 [(set GPR:$dst, (atomic_cmp_swap_32 GPR:$ptr, GPR:$old, GPR:$new))]>;
4202 let usesCustomInserter = 1 in {
4203 def COPY_STRUCT_BYVAL_I32 : PseudoInst<
4204 (outs), (ins GPR:$dst, GPR:$src, i32imm:$size, i32imm:$alignment),
4206 [(ARMcopystructbyval GPR:$dst, GPR:$src, imm:$size, imm:$alignment)]>;
4209 let mayLoad = 1 in {
4210 def LDREXB : AIldrex<0b10, (outs GPR:$Rt), (ins addr_offset_none:$addr),
4212 "ldrexb", "\t$Rt, $addr", []>;
4213 def LDREXH : AIldrex<0b11, (outs GPR:$Rt), (ins addr_offset_none:$addr),
4214 NoItinerary, "ldrexh", "\t$Rt, $addr", []>;
4215 def LDREX : AIldrex<0b00, (outs GPR:$Rt), (ins addr_offset_none:$addr),
4216 NoItinerary, "ldrex", "\t$Rt, $addr", []>;
4217 let hasExtraDefRegAllocReq = 1 in
4218 def LDREXD: AIldrex<0b01, (outs GPR:$Rt, GPR:$Rt2),(ins addr_offset_none:$addr),
4219 NoItinerary, "ldrexd", "\t$Rt, $Rt2, $addr", []> {
4220 let DecoderMethod = "DecodeDoubleRegLoad";
4224 let mayStore = 1, Constraints = "@earlyclobber $Rd" in {
4225 def STREXB: AIstrex<0b10, (outs GPR:$Rd), (ins GPR:$Rt, addr_offset_none:$addr),
4226 NoItinerary, "strexb", "\t$Rd, $Rt, $addr", []>;
4227 def STREXH: AIstrex<0b11, (outs GPR:$Rd), (ins GPR:$Rt, addr_offset_none:$addr),
4228 NoItinerary, "strexh", "\t$Rd, $Rt, $addr", []>;
4229 def STREX : AIstrex<0b00, (outs GPR:$Rd), (ins GPR:$Rt, addr_offset_none:$addr),
4230 NoItinerary, "strex", "\t$Rd, $Rt, $addr", []>;
4231 let hasExtraSrcRegAllocReq = 1 in
4232 def STREXD : AIstrex<0b01, (outs GPR:$Rd),
4233 (ins GPR:$Rt, GPR:$Rt2, addr_offset_none:$addr),
4234 NoItinerary, "strexd", "\t$Rd, $Rt, $Rt2, $addr", []> {
4235 let DecoderMethod = "DecodeDoubleRegStore";
4240 def CLREX : AXI<(outs), (ins), MiscFrm, NoItinerary, "clrex", []>,
4241 Requires<[IsARM, HasV7]> {
4242 let Inst{31-0} = 0b11110101011111111111000000011111;
4245 // SWP/SWPB are deprecated in V6/V7.
4246 let mayLoad = 1, mayStore = 1 in {
4247 def SWP : AIswp<0, (outs GPRnopc:$Rt),
4248 (ins GPRnopc:$Rt2, addr_offset_none:$addr), "swp", []>;
4249 def SWPB: AIswp<1, (outs GPRnopc:$Rt),
4250 (ins GPRnopc:$Rt2, addr_offset_none:$addr), "swpb", []>;
4253 //===----------------------------------------------------------------------===//
4254 // Coprocessor Instructions.
4257 def CDP : ABI<0b1110, (outs), (ins p_imm:$cop, imm0_15:$opc1,
4258 c_imm:$CRd, c_imm:$CRn, c_imm:$CRm, imm0_7:$opc2),
4259 NoItinerary, "cdp", "\t$cop, $opc1, $CRd, $CRn, $CRm, $opc2",
4260 [(int_arm_cdp imm:$cop, imm:$opc1, imm:$CRd, imm:$CRn,
4261 imm:$CRm, imm:$opc2)]> {
4269 let Inst{3-0} = CRm;
4271 let Inst{7-5} = opc2;
4272 let Inst{11-8} = cop;
4273 let Inst{15-12} = CRd;
4274 let Inst{19-16} = CRn;
4275 let Inst{23-20} = opc1;
4278 def CDP2 : ABXI<0b1110, (outs), (ins pf_imm:$cop, imm0_15:$opc1,
4279 c_imm:$CRd, c_imm:$CRn, c_imm:$CRm, imm0_7:$opc2),
4280 NoItinerary, "cdp2\t$cop, $opc1, $CRd, $CRn, $CRm, $opc2",
4281 [(int_arm_cdp2 imm:$cop, imm:$opc1, imm:$CRd, imm:$CRn,
4282 imm:$CRm, imm:$opc2)]> {
4283 let Inst{31-28} = 0b1111;
4291 let Inst{3-0} = CRm;
4293 let Inst{7-5} = opc2;
4294 let Inst{11-8} = cop;
4295 let Inst{15-12} = CRd;
4296 let Inst{19-16} = CRn;
4297 let Inst{23-20} = opc1;
4300 class ACI<dag oops, dag iops, string opc, string asm,
4301 IndexMode im = IndexModeNone>
4302 : I<oops, iops, AddrModeNone, 4, im, BrFrm, NoItinerary,
4304 let Inst{27-25} = 0b110;
4306 class ACInoP<dag oops, dag iops, string opc, string asm,
4307 IndexMode im = IndexModeNone>
4308 : InoP<oops, iops, AddrModeNone, 4, im, BrFrm, NoItinerary,
4310 let Inst{31-28} = 0b1111;
4311 let Inst{27-25} = 0b110;
4313 multiclass LdStCop<bit load, bit Dbit, string asm> {
4314 def _OFFSET : ACI<(outs), (ins p_imm:$cop, c_imm:$CRd, addrmode5:$addr),
4315 asm, "\t$cop, $CRd, $addr"> {
4319 let Inst{24} = 1; // P = 1
4320 let Inst{23} = addr{8};
4321 let Inst{22} = Dbit;
4322 let Inst{21} = 0; // W = 0
4323 let Inst{20} = load;
4324 let Inst{19-16} = addr{12-9};
4325 let Inst{15-12} = CRd;
4326 let Inst{11-8} = cop;
4327 let Inst{7-0} = addr{7-0};
4328 let DecoderMethod = "DecodeCopMemInstruction";
4330 def _PRE : ACI<(outs), (ins p_imm:$cop, c_imm:$CRd, addrmode5:$addr),
4331 asm, "\t$cop, $CRd, $addr!", IndexModePre> {
4335 let Inst{24} = 1; // P = 1
4336 let Inst{23} = addr{8};
4337 let Inst{22} = Dbit;
4338 let Inst{21} = 1; // W = 1
4339 let Inst{20} = load;
4340 let Inst{19-16} = addr{12-9};
4341 let Inst{15-12} = CRd;
4342 let Inst{11-8} = cop;
4343 let Inst{7-0} = addr{7-0};
4344 let DecoderMethod = "DecodeCopMemInstruction";
4346 def _POST: ACI<(outs), (ins p_imm:$cop, c_imm:$CRd, addr_offset_none:$addr,
4347 postidx_imm8s4:$offset),
4348 asm, "\t$cop, $CRd, $addr, $offset", IndexModePost> {
4353 let Inst{24} = 0; // P = 0
4354 let Inst{23} = offset{8};
4355 let Inst{22} = Dbit;
4356 let Inst{21} = 1; // W = 1
4357 let Inst{20} = load;
4358 let Inst{19-16} = addr;
4359 let Inst{15-12} = CRd;
4360 let Inst{11-8} = cop;
4361 let Inst{7-0} = offset{7-0};
4362 let DecoderMethod = "DecodeCopMemInstruction";
4364 def _OPTION : ACI<(outs),
4365 (ins p_imm:$cop, c_imm:$CRd, addr_offset_none:$addr,
4366 coproc_option_imm:$option),
4367 asm, "\t$cop, $CRd, $addr, $option"> {
4372 let Inst{24} = 0; // P = 0
4373 let Inst{23} = 1; // U = 1
4374 let Inst{22} = Dbit;
4375 let Inst{21} = 0; // W = 0
4376 let Inst{20} = load;
4377 let Inst{19-16} = addr;
4378 let Inst{15-12} = CRd;
4379 let Inst{11-8} = cop;
4380 let Inst{7-0} = option;
4381 let DecoderMethod = "DecodeCopMemInstruction";
4384 multiclass LdSt2Cop<bit load, bit Dbit, string asm> {
4385 def _OFFSET : ACInoP<(outs), (ins p_imm:$cop, c_imm:$CRd, addrmode5:$addr),
4386 asm, "\t$cop, $CRd, $addr"> {
4390 let Inst{24} = 1; // P = 1
4391 let Inst{23} = addr{8};
4392 let Inst{22} = Dbit;
4393 let Inst{21} = 0; // W = 0
4394 let Inst{20} = load;
4395 let Inst{19-16} = addr{12-9};
4396 let Inst{15-12} = CRd;
4397 let Inst{11-8} = cop;
4398 let Inst{7-0} = addr{7-0};
4399 let DecoderMethod = "DecodeCopMemInstruction";
4401 def _PRE : ACInoP<(outs), (ins p_imm:$cop, c_imm:$CRd, addrmode5:$addr),
4402 asm, "\t$cop, $CRd, $addr!", IndexModePre> {
4406 let Inst{24} = 1; // P = 1
4407 let Inst{23} = addr{8};
4408 let Inst{22} = Dbit;
4409 let Inst{21} = 1; // W = 1
4410 let Inst{20} = load;
4411 let Inst{19-16} = addr{12-9};
4412 let Inst{15-12} = CRd;
4413 let Inst{11-8} = cop;
4414 let Inst{7-0} = addr{7-0};
4415 let DecoderMethod = "DecodeCopMemInstruction";
4417 def _POST: ACInoP<(outs), (ins p_imm:$cop, c_imm:$CRd, addr_offset_none:$addr,
4418 postidx_imm8s4:$offset),
4419 asm, "\t$cop, $CRd, $addr, $offset", IndexModePost> {
4424 let Inst{24} = 0; // P = 0
4425 let Inst{23} = offset{8};
4426 let Inst{22} = Dbit;
4427 let Inst{21} = 1; // W = 1
4428 let Inst{20} = load;
4429 let Inst{19-16} = addr;
4430 let Inst{15-12} = CRd;
4431 let Inst{11-8} = cop;
4432 let Inst{7-0} = offset{7-0};
4433 let DecoderMethod = "DecodeCopMemInstruction";
4435 def _OPTION : ACInoP<(outs),
4436 (ins p_imm:$cop, c_imm:$CRd, addr_offset_none:$addr,
4437 coproc_option_imm:$option),
4438 asm, "\t$cop, $CRd, $addr, $option"> {
4443 let Inst{24} = 0; // P = 0
4444 let Inst{23} = 1; // U = 1
4445 let Inst{22} = Dbit;
4446 let Inst{21} = 0; // W = 0
4447 let Inst{20} = load;
4448 let Inst{19-16} = addr;
4449 let Inst{15-12} = CRd;
4450 let Inst{11-8} = cop;
4451 let Inst{7-0} = option;
4452 let DecoderMethod = "DecodeCopMemInstruction";
4456 defm LDC : LdStCop <1, 0, "ldc">;
4457 defm LDCL : LdStCop <1, 1, "ldcl">;
4458 defm STC : LdStCop <0, 0, "stc">;
4459 defm STCL : LdStCop <0, 1, "stcl">;
4460 defm LDC2 : LdSt2Cop<1, 0, "ldc2">;
4461 defm LDC2L : LdSt2Cop<1, 1, "ldc2l">;
4462 defm STC2 : LdSt2Cop<0, 0, "stc2">;
4463 defm STC2L : LdSt2Cop<0, 1, "stc2l">;
4465 //===----------------------------------------------------------------------===//
4466 // Move between coprocessor and ARM core register.
4469 class MovRCopro<string opc, bit direction, dag oops, dag iops,
4471 : ABI<0b1110, oops, iops, NoItinerary, opc,
4472 "\t$cop, $opc1, $Rt, $CRn, $CRm, $opc2", pattern> {
4473 let Inst{20} = direction;
4483 let Inst{15-12} = Rt;
4484 let Inst{11-8} = cop;
4485 let Inst{23-21} = opc1;
4486 let Inst{7-5} = opc2;
4487 let Inst{3-0} = CRm;
4488 let Inst{19-16} = CRn;
4491 def MCR : MovRCopro<"mcr", 0 /* from ARM core register to coprocessor */,
4493 (ins p_imm:$cop, imm0_7:$opc1, GPR:$Rt, c_imm:$CRn,
4494 c_imm:$CRm, imm0_7:$opc2),
4495 [(int_arm_mcr imm:$cop, imm:$opc1, GPR:$Rt, imm:$CRn,
4496 imm:$CRm, imm:$opc2)]>;
4497 def : ARMInstAlias<"mcr${p} $cop, $opc1, $Rt, $CRn, $CRm",
4498 (MCR p_imm:$cop, imm0_7:$opc1, GPR:$Rt, c_imm:$CRn,
4499 c_imm:$CRm, 0, pred:$p)>;
4500 def MRC : MovRCopro<"mrc", 1 /* from coprocessor to ARM core register */,
4502 (ins p_imm:$cop, imm0_7:$opc1, c_imm:$CRn, c_imm:$CRm,
4504 def : ARMInstAlias<"mrc${p} $cop, $opc1, $Rt, $CRn, $CRm",
4505 (MRC GPR:$Rt, p_imm:$cop, imm0_7:$opc1, c_imm:$CRn,
4506 c_imm:$CRm, 0, pred:$p)>;
4508 def : ARMPat<(int_arm_mrc imm:$cop, imm:$opc1, imm:$CRn, imm:$CRm, imm:$opc2),
4509 (MRC imm:$cop, imm:$opc1, imm:$CRn, imm:$CRm, imm:$opc2)>;
4511 class MovRCopro2<string opc, bit direction, dag oops, dag iops,
4513 : ABXI<0b1110, oops, iops, NoItinerary,
4514 !strconcat(opc, "\t$cop, $opc1, $Rt, $CRn, $CRm, $opc2"), pattern> {
4515 let Inst{31-28} = 0b1111;
4516 let Inst{20} = direction;
4526 let Inst{15-12} = Rt;
4527 let Inst{11-8} = cop;
4528 let Inst{23-21} = opc1;
4529 let Inst{7-5} = opc2;
4530 let Inst{3-0} = CRm;
4531 let Inst{19-16} = CRn;
4534 def MCR2 : MovRCopro2<"mcr2", 0 /* from ARM core register to coprocessor */,
4536 (ins p_imm:$cop, imm0_7:$opc1, GPR:$Rt, c_imm:$CRn,
4537 c_imm:$CRm, imm0_7:$opc2),
4538 [(int_arm_mcr2 imm:$cop, imm:$opc1, GPR:$Rt, imm:$CRn,
4539 imm:$CRm, imm:$opc2)]>;
4540 def : ARMInstAlias<"mcr2$ $cop, $opc1, $Rt, $CRn, $CRm",
4541 (MCR2 p_imm:$cop, imm0_7:$opc1, GPR:$Rt, c_imm:$CRn,
4543 def MRC2 : MovRCopro2<"mrc2", 1 /* from coprocessor to ARM core register */,
4545 (ins p_imm:$cop, imm0_7:$opc1, c_imm:$CRn, c_imm:$CRm,
4547 def : ARMInstAlias<"mrc2$ $cop, $opc1, $Rt, $CRn, $CRm",
4548 (MRC2 GPR:$Rt, p_imm:$cop, imm0_7:$opc1, c_imm:$CRn,
4551 def : ARMV5TPat<(int_arm_mrc2 imm:$cop, imm:$opc1, imm:$CRn,
4552 imm:$CRm, imm:$opc2),
4553 (MRC2 imm:$cop, imm:$opc1, imm:$CRn, imm:$CRm, imm:$opc2)>;
4555 class MovRRCopro<string opc, bit direction, list<dag> pattern = []>
4556 : ABI<0b1100, (outs), (ins p_imm:$cop, imm0_15:$opc1,
4557 GPRnopc:$Rt, GPRnopc:$Rt2, c_imm:$CRm),
4558 NoItinerary, opc, "\t$cop, $opc1, $Rt, $Rt2, $CRm", pattern> {
4559 let Inst{23-21} = 0b010;
4560 let Inst{20} = direction;
4568 let Inst{15-12} = Rt;
4569 let Inst{19-16} = Rt2;
4570 let Inst{11-8} = cop;
4571 let Inst{7-4} = opc1;
4572 let Inst{3-0} = CRm;
4575 def MCRR : MovRRCopro<"mcrr", 0 /* from ARM core register to coprocessor */,
4576 [(int_arm_mcrr imm:$cop, imm:$opc1, GPRnopc:$Rt,
4577 GPRnopc:$Rt2, imm:$CRm)]>;
4578 def MRRC : MovRRCopro<"mrrc", 1 /* from coprocessor to ARM core register */>;
4580 class MovRRCopro2<string opc, bit direction, list<dag> pattern = []>
4581 : ABXI<0b1100, (outs), (ins p_imm:$cop, imm0_15:$opc1,
4582 GPRnopc:$Rt, GPRnopc:$Rt2, c_imm:$CRm), NoItinerary,
4583 !strconcat(opc, "\t$cop, $opc1, $Rt, $Rt2, $CRm"), pattern> {
4584 let Inst{31-28} = 0b1111;
4585 let Inst{23-21} = 0b010;
4586 let Inst{20} = direction;
4594 let Inst{15-12} = Rt;
4595 let Inst{19-16} = Rt2;
4596 let Inst{11-8} = cop;
4597 let Inst{7-4} = opc1;
4598 let Inst{3-0} = CRm;
4600 let DecoderMethod = "DecodeMRRC2";
4603 def MCRR2 : MovRRCopro2<"mcrr2", 0 /* from ARM core register to coprocessor */,
4604 [(int_arm_mcrr2 imm:$cop, imm:$opc1, GPRnopc:$Rt,
4605 GPRnopc:$Rt2, imm:$CRm)]>;
4606 def MRRC2 : MovRRCopro2<"mrrc2", 1 /* from coprocessor to ARM core register */>;
4608 //===----------------------------------------------------------------------===//
4609 // Move between special register and ARM core register
4612 // Move to ARM core register from Special Register
4613 def MRS : ABI<0b0001, (outs GPRnopc:$Rd), (ins), NoItinerary,
4614 "mrs", "\t$Rd, apsr", []> {
4616 let Inst{23-16} = 0b00001111;
4617 let Unpredictable{19-17} = 0b111;
4619 let Inst{15-12} = Rd;
4621 let Inst{11-0} = 0b000000000000;
4622 let Unpredictable{11-0} = 0b110100001111;
4625 def : InstAlias<"mrs${p} $Rd, cpsr", (MRS GPRnopc:$Rd, pred:$p)>,
4628 // The MRSsys instruction is the MRS instruction from the ARM ARM,
4629 // section B9.3.9, with the R bit set to 1.
4630 def MRSsys : ABI<0b0001, (outs GPRnopc:$Rd), (ins), NoItinerary,
4631 "mrs", "\t$Rd, spsr", []> {
4633 let Inst{23-16} = 0b01001111;
4634 let Unpredictable{19-16} = 0b1111;
4636 let Inst{15-12} = Rd;
4638 let Inst{11-0} = 0b000000000000;
4639 let Unpredictable{11-0} = 0b110100001111;
4642 // Move from ARM core register to Special Register
4644 // No need to have both system and application versions, the encodings are the
4645 // same and the assembly parser has no way to distinguish between them. The mask
4646 // operand contains the special register (R Bit) in bit 4 and bits 3-0 contains
4647 // the mask with the fields to be accessed in the special register.
4648 def MSR : ABI<0b0001, (outs), (ins msr_mask:$mask, GPR:$Rn), NoItinerary,
4649 "msr", "\t$mask, $Rn", []> {
4654 let Inst{22} = mask{4}; // R bit
4655 let Inst{21-20} = 0b10;
4656 let Inst{19-16} = mask{3-0};
4657 let Inst{15-12} = 0b1111;
4658 let Inst{11-4} = 0b00000000;
4662 def MSRi : ABI<0b0011, (outs), (ins msr_mask:$mask, so_imm:$a), NoItinerary,
4663 "msr", "\t$mask, $a", []> {
4668 let Inst{22} = mask{4}; // R bit
4669 let Inst{21-20} = 0b10;
4670 let Inst{19-16} = mask{3-0};
4671 let Inst{15-12} = 0b1111;
4675 //===----------------------------------------------------------------------===//
4679 // __aeabi_read_tp preserves the registers r1-r3.
4680 // This is a pseudo inst so that we can get the encoding right,
4681 // complete with fixup for the aeabi_read_tp function.
4683 Defs = [R0, R12, LR, CPSR], Uses = [SP] in {
4684 def TPsoft : PseudoInst<(outs), (ins), IIC_Br,
4685 [(set R0, ARMthread_pointer)]>;
4688 //===----------------------------------------------------------------------===//
4689 // SJLJ Exception handling intrinsics
4690 // eh_sjlj_setjmp() is an instruction sequence to store the return
4691 // address and save #0 in R0 for the non-longjmp case.
4692 // Since by its nature we may be coming from some other function to get
4693 // here, and we're using the stack frame for the containing function to
4694 // save/restore registers, we can't keep anything live in regs across
4695 // the eh_sjlj_setjmp(), else it will almost certainly have been tromped upon
4696 // when we get here from a longjmp(). We force everything out of registers
4697 // except for our own input by listing the relevant registers in Defs. By
4698 // doing so, we also cause the prologue/epilogue code to actively preserve
4699 // all of the callee-saved resgisters, which is exactly what we want.
4700 // A constant value is passed in $val, and we use the location as a scratch.
4702 // These are pseudo-instructions and are lowered to individual MC-insts, so
4703 // no encoding information is necessary.
4705 [ R0, R1, R2, R3, R4, R5, R6, R7, R8, R9, R10, R11, R12, LR, CPSR,
4706 Q0, Q1, Q2, Q3, Q4, Q5, Q6, Q7, Q8, Q9, Q10, Q11, Q12, Q13, Q14, Q15 ],
4707 hasSideEffects = 1, isBarrier = 1, usesCustomInserter = 1 in {
4708 def Int_eh_sjlj_setjmp : PseudoInst<(outs), (ins GPR:$src, GPR:$val),
4710 [(set R0, (ARMeh_sjlj_setjmp GPR:$src, GPR:$val))]>,
4711 Requires<[IsARM, HasVFP2]>;
4715 [ R0, R1, R2, R3, R4, R5, R6, R7, R8, R9, R10, R11, R12, LR, CPSR ],
4716 hasSideEffects = 1, isBarrier = 1, usesCustomInserter = 1 in {
4717 def Int_eh_sjlj_setjmp_nofp : PseudoInst<(outs), (ins GPR:$src, GPR:$val),
4719 [(set R0, (ARMeh_sjlj_setjmp GPR:$src, GPR:$val))]>,
4720 Requires<[IsARM, NoVFP]>;
4723 // FIXME: Non-IOS version(s)
4724 let isBarrier = 1, hasSideEffects = 1, isTerminator = 1,
4725 Defs = [ R7, LR, SP ] in {
4726 def Int_eh_sjlj_longjmp : PseudoInst<(outs), (ins GPR:$src, GPR:$scratch),
4728 [(ARMeh_sjlj_longjmp GPR:$src, GPR:$scratch)]>,
4729 Requires<[IsARM, IsIOS]>;
4732 // eh.sjlj.dispatchsetup pseudo-instructions.
4733 // These pseudos are used for both ARM and Thumb2. Any differences are
4734 // handled when the pseudo is expanded (which happens before any passes
4735 // that need the instruction size).
4737 [ R0, R1, R2, R3, R4, R5, R6, R7, R8, R9, R10, R11, R12, LR, CPSR,
4738 Q0, Q1, Q2, Q3, Q4, Q5, Q6, Q7, Q8, Q9, Q10, Q11, Q12, Q13, Q14, Q15 ],
4740 def Int_eh_sjlj_dispatchsetup : PseudoInst<(outs), (ins), NoItinerary, []>;
4743 [ R0, R1, R2, R3, R4, R5, R6, R7, R8, R9, R10, R11, R12, LR, CPSR ],
4745 def Int_eh_sjlj_dispatchsetup_nofp : PseudoInst<(outs), (ins), NoItinerary, []>;
4748 //===----------------------------------------------------------------------===//
4749 // Non-Instruction Patterns
4752 // ARMv4 indirect branch using (MOVr PC, dst)
4753 let isBranch = 1, isTerminator = 1, isBarrier = 1, isIndirectBranch = 1 in
4754 def MOVPCRX : ARMPseudoExpand<(outs), (ins GPR:$dst),
4755 4, IIC_Br, [(brind GPR:$dst)],
4756 (MOVr PC, GPR:$dst, (ops 14, zero_reg), zero_reg)>,
4757 Requires<[IsARM, NoV4T]>;
4759 // Large immediate handling.
4761 // 32-bit immediate using two piece so_imms or movw + movt.
4762 // This is a single pseudo instruction, the benefit is that it can be remat'd
4763 // as a single unit instead of having to handle reg inputs.
4764 // FIXME: Remove this when we can do generalized remat.
4765 let isReMaterializable = 1, isMoveImm = 1 in
4766 def MOVi32imm : PseudoInst<(outs GPR:$dst), (ins i32imm:$src), IIC_iMOVix2,
4767 [(set GPR:$dst, (arm_i32imm:$src))]>,
4770 // Pseudo instruction that combines movw + movt + add pc (if PIC).
4771 // It also makes it possible to rematerialize the instructions.
4772 // FIXME: Remove this when we can do generalized remat and when machine licm
4773 // can properly the instructions.
4774 let isReMaterializable = 1 in {
4775 def MOV_ga_pcrel : PseudoInst<(outs GPR:$dst), (ins i32imm:$addr),
4777 [(set GPR:$dst, (ARMWrapperPIC tglobaladdr:$addr))]>,
4778 Requires<[IsARM, UseMovt]>;
4780 def MOV_ga_dyn : PseudoInst<(outs GPR:$dst), (ins i32imm:$addr),
4782 [(set GPR:$dst, (ARMWrapperDYN tglobaladdr:$addr))]>,
4783 Requires<[IsARM, UseMovt]>;
4785 let AddedComplexity = 10 in
4786 def MOV_ga_pcrel_ldr : PseudoInst<(outs GPR:$dst), (ins i32imm:$addr),
4788 [(set GPR:$dst, (load (ARMWrapperPIC tglobaladdr:$addr)))]>,
4789 Requires<[IsARM, UseMovt]>;
4790 } // isReMaterializable
4792 // ConstantPool, GlobalAddress, and JumpTable
4793 def : ARMPat<(ARMWrapper tglobaladdr :$dst), (LEApcrel tglobaladdr :$dst)>,
4794 Requires<[IsARM, DontUseMovt]>;
4795 def : ARMPat<(ARMWrapper tconstpool :$dst), (LEApcrel tconstpool :$dst)>;
4796 def : ARMPat<(ARMWrapper tglobaladdr :$dst), (MOVi32imm tglobaladdr :$dst)>,
4797 Requires<[IsARM, UseMovt]>;
4798 def : ARMPat<(ARMWrapperJT tjumptable:$dst, imm:$id),
4799 (LEApcrelJT tjumptable:$dst, imm:$id)>;
4801 // TODO: add,sub,and, 3-instr forms?
4803 // Tail calls. These patterns also apply to Thumb mode.
4804 def : Pat<(ARMtcret tcGPR:$dst), (TCRETURNri tcGPR:$dst)>;
4805 def : Pat<(ARMtcret (i32 tglobaladdr:$dst)), (TCRETURNdi texternalsym:$dst)>;
4806 def : Pat<(ARMtcret (i32 texternalsym:$dst)), (TCRETURNdi texternalsym:$dst)>;
4809 def : ARMPat<(ARMcall texternalsym:$func), (BL texternalsym:$func)>;
4810 def : ARMPat<(ARMcall_nolink texternalsym:$func),
4811 (BMOVPCB_CALL texternalsym:$func)>;
4813 // zextload i1 -> zextload i8
4814 def : ARMPat<(zextloadi1 addrmode_imm12:$addr), (LDRBi12 addrmode_imm12:$addr)>;
4815 def : ARMPat<(zextloadi1 ldst_so_reg:$addr), (LDRBrs ldst_so_reg:$addr)>;
4817 // extload -> zextload
4818 def : ARMPat<(extloadi1 addrmode_imm12:$addr), (LDRBi12 addrmode_imm12:$addr)>;
4819 def : ARMPat<(extloadi1 ldst_so_reg:$addr), (LDRBrs ldst_so_reg:$addr)>;
4820 def : ARMPat<(extloadi8 addrmode_imm12:$addr), (LDRBi12 addrmode_imm12:$addr)>;
4821 def : ARMPat<(extloadi8 ldst_so_reg:$addr), (LDRBrs ldst_so_reg:$addr)>;
4823 def : ARMPat<(extloadi16 addrmode3:$addr), (LDRH addrmode3:$addr)>;
4825 def : ARMPat<(extloadi8 addrmodepc:$addr), (PICLDRB addrmodepc:$addr)>;
4826 def : ARMPat<(extloadi16 addrmodepc:$addr), (PICLDRH addrmodepc:$addr)>;
4829 def : ARMV5TEPat<(mul (sra (shl GPR:$a, (i32 16)), (i32 16)),
4830 (sra (shl GPR:$b, (i32 16)), (i32 16))),
4831 (SMULBB GPR:$a, GPR:$b)>;
4832 def : ARMV5TEPat<(mul sext_16_node:$a, sext_16_node:$b),
4833 (SMULBB GPR:$a, GPR:$b)>;
4834 def : ARMV5TEPat<(mul (sra (shl GPR:$a, (i32 16)), (i32 16)),
4835 (sra GPR:$b, (i32 16))),
4836 (SMULBT GPR:$a, GPR:$b)>;
4837 def : ARMV5TEPat<(mul sext_16_node:$a, (sra GPR:$b, (i32 16))),
4838 (SMULBT GPR:$a, GPR:$b)>;
4839 def : ARMV5TEPat<(mul (sra GPR:$a, (i32 16)),
4840 (sra (shl GPR:$b, (i32 16)), (i32 16))),
4841 (SMULTB GPR:$a, GPR:$b)>;
4842 def : ARMV5TEPat<(mul (sra GPR:$a, (i32 16)), sext_16_node:$b),
4843 (SMULTB GPR:$a, GPR:$b)>;
4844 def : ARMV5TEPat<(sra (mul GPR:$a, (sra (shl GPR:$b, (i32 16)), (i32 16))),
4846 (SMULWB GPR:$a, GPR:$b)>;
4847 def : ARMV5TEPat<(sra (mul GPR:$a, sext_16_node:$b), (i32 16)),
4848 (SMULWB GPR:$a, GPR:$b)>;
4850 def : ARMV5TEPat<(add GPR:$acc,
4851 (mul (sra (shl GPR:$a, (i32 16)), (i32 16)),
4852 (sra (shl GPR:$b, (i32 16)), (i32 16)))),
4853 (SMLABB GPR:$a, GPR:$b, GPR:$acc)>;
4854 def : ARMV5TEPat<(add GPR:$acc,
4855 (mul sext_16_node:$a, sext_16_node:$b)),
4856 (SMLABB GPR:$a, GPR:$b, GPR:$acc)>;
4857 def : ARMV5TEPat<(add GPR:$acc,
4858 (mul (sra (shl GPR:$a, (i32 16)), (i32 16)),
4859 (sra GPR:$b, (i32 16)))),
4860 (SMLABT GPR:$a, GPR:$b, GPR:$acc)>;
4861 def : ARMV5TEPat<(add GPR:$acc,
4862 (mul sext_16_node:$a, (sra GPR:$b, (i32 16)))),
4863 (SMLABT GPR:$a, GPR:$b, GPR:$acc)>;
4864 def : ARMV5TEPat<(add GPR:$acc,
4865 (mul (sra GPR:$a, (i32 16)),
4866 (sra (shl GPR:$b, (i32 16)), (i32 16)))),
4867 (SMLATB GPR:$a, GPR:$b, GPR:$acc)>;
4868 def : ARMV5TEPat<(add GPR:$acc,
4869 (mul (sra GPR:$a, (i32 16)), sext_16_node:$b)),
4870 (SMLATB GPR:$a, GPR:$b, GPR:$acc)>;
4871 def : ARMV5TEPat<(add GPR:$acc,
4872 (sra (mul GPR:$a, (sra (shl GPR:$b, (i32 16)), (i32 16))),
4874 (SMLAWB GPR:$a, GPR:$b, GPR:$acc)>;
4875 def : ARMV5TEPat<(add GPR:$acc,
4876 (sra (mul GPR:$a, sext_16_node:$b), (i32 16))),
4877 (SMLAWB GPR:$a, GPR:$b, GPR:$acc)>;
4880 // Pre-v7 uses MCR for synchronization barriers.
4881 def : ARMPat<(ARMMemBarrierMCR GPR:$zero), (MCR 15, 0, GPR:$zero, 7, 10, 5)>,
4882 Requires<[IsARM, HasV6]>;
4884 // SXT/UXT with no rotate
4885 let AddedComplexity = 16 in {
4886 def : ARMV6Pat<(and GPR:$Src, 0x000000FF), (UXTB GPR:$Src, 0)>;
4887 def : ARMV6Pat<(and GPR:$Src, 0x0000FFFF), (UXTH GPR:$Src, 0)>;
4888 def : ARMV6Pat<(and GPR:$Src, 0x00FF00FF), (UXTB16 GPR:$Src, 0)>;
4889 def : ARMV6Pat<(add GPR:$Rn, (and GPR:$Rm, 0x00FF)),
4890 (UXTAB GPR:$Rn, GPR:$Rm, 0)>;
4891 def : ARMV6Pat<(add GPR:$Rn, (and GPR:$Rm, 0xFFFF)),
4892 (UXTAH GPR:$Rn, GPR:$Rm, 0)>;
4895 def : ARMV6Pat<(sext_inreg GPR:$Src, i8), (SXTB GPR:$Src, 0)>;
4896 def : ARMV6Pat<(sext_inreg GPR:$Src, i16), (SXTH GPR:$Src, 0)>;
4898 def : ARMV6Pat<(add GPR:$Rn, (sext_inreg GPRnopc:$Rm, i8)),
4899 (SXTAB GPR:$Rn, GPRnopc:$Rm, 0)>;
4900 def : ARMV6Pat<(add GPR:$Rn, (sext_inreg GPRnopc:$Rm, i16)),
4901 (SXTAH GPR:$Rn, GPRnopc:$Rm, 0)>;
4903 // Atomic load/store patterns
4904 def : ARMPat<(atomic_load_8 ldst_so_reg:$src),
4905 (LDRBrs ldst_so_reg:$src)>;
4906 def : ARMPat<(atomic_load_8 addrmode_imm12:$src),
4907 (LDRBi12 addrmode_imm12:$src)>;
4908 def : ARMPat<(atomic_load_16 addrmode3:$src),
4909 (LDRH addrmode3:$src)>;
4910 def : ARMPat<(atomic_load_32 ldst_so_reg:$src),
4911 (LDRrs ldst_so_reg:$src)>;
4912 def : ARMPat<(atomic_load_32 addrmode_imm12:$src),
4913 (LDRi12 addrmode_imm12:$src)>;
4914 def : ARMPat<(atomic_store_8 ldst_so_reg:$ptr, GPR:$val),
4915 (STRBrs GPR:$val, ldst_so_reg:$ptr)>;
4916 def : ARMPat<(atomic_store_8 addrmode_imm12:$ptr, GPR:$val),
4917 (STRBi12 GPR:$val, addrmode_imm12:$ptr)>;
4918 def : ARMPat<(atomic_store_16 addrmode3:$ptr, GPR:$val),
4919 (STRH GPR:$val, addrmode3:$ptr)>;
4920 def : ARMPat<(atomic_store_32 ldst_so_reg:$ptr, GPR:$val),
4921 (STRrs GPR:$val, ldst_so_reg:$ptr)>;
4922 def : ARMPat<(atomic_store_32 addrmode_imm12:$ptr, GPR:$val),
4923 (STRi12 GPR:$val, addrmode_imm12:$ptr)>;
4926 //===----------------------------------------------------------------------===//
4930 include "ARMInstrThumb.td"
4932 //===----------------------------------------------------------------------===//
4936 include "ARMInstrThumb2.td"
4938 //===----------------------------------------------------------------------===//
4939 // Floating Point Support
4942 include "ARMInstrVFP.td"
4944 //===----------------------------------------------------------------------===//
4945 // Advanced SIMD (NEON) Support
4948 include "ARMInstrNEON.td"
4950 //===----------------------------------------------------------------------===//
4951 // Assembler aliases
4955 def : InstAlias<"dmb", (DMB 0xf)>, Requires<[IsARM, HasDB]>;
4956 def : InstAlias<"dsb", (DSB 0xf)>, Requires<[IsARM, HasDB]>;
4957 def : InstAlias<"isb", (ISB 0xf)>, Requires<[IsARM, HasDB]>;
4959 // System instructions
4960 def : MnemonicAlias<"swi", "svc">;
4962 // Load / Store Multiple
4963 def : MnemonicAlias<"ldmfd", "ldm">;
4964 def : MnemonicAlias<"ldmia", "ldm">;
4965 def : MnemonicAlias<"ldmea", "ldmdb">;
4966 def : MnemonicAlias<"stmfd", "stmdb">;
4967 def : MnemonicAlias<"stmia", "stm">;
4968 def : MnemonicAlias<"stmea", "stm">;
4970 // PKHBT/PKHTB with default shift amount. PKHTB is equivalent to PKHBT when the
4971 // shift amount is zero (i.e., unspecified).
4972 def : InstAlias<"pkhbt${p} $Rd, $Rn, $Rm",
4973 (PKHBT GPRnopc:$Rd, GPRnopc:$Rn, GPRnopc:$Rm, 0, pred:$p)>,
4974 Requires<[IsARM, HasV6]>;
4975 def : InstAlias<"pkhtb${p} $Rd, $Rn, $Rm",
4976 (PKHBT GPRnopc:$Rd, GPRnopc:$Rn, GPRnopc:$Rm, 0, pred:$p)>,
4977 Requires<[IsARM, HasV6]>;
4979 // PUSH/POP aliases for STM/LDM
4980 def : ARMInstAlias<"push${p} $regs", (STMDB_UPD SP, pred:$p, reglist:$regs)>;
4981 def : ARMInstAlias<"pop${p} $regs", (LDMIA_UPD SP, pred:$p, reglist:$regs)>;
4983 // SSAT/USAT optional shift operand.
4984 def : ARMInstAlias<"ssat${p} $Rd, $sat_imm, $Rn",
4985 (SSAT GPRnopc:$Rd, imm1_32:$sat_imm, GPRnopc:$Rn, 0, pred:$p)>;
4986 def : ARMInstAlias<"usat${p} $Rd, $sat_imm, $Rn",
4987 (USAT GPRnopc:$Rd, imm0_31:$sat_imm, GPRnopc:$Rn, 0, pred:$p)>;
4990 // Extend instruction optional rotate operand.
4991 def : ARMInstAlias<"sxtab${p} $Rd, $Rn, $Rm",
4992 (SXTAB GPRnopc:$Rd, GPR:$Rn, GPRnopc:$Rm, 0, pred:$p)>;
4993 def : ARMInstAlias<"sxtah${p} $Rd, $Rn, $Rm",
4994 (SXTAH GPRnopc:$Rd, GPR:$Rn, GPRnopc:$Rm, 0, pred:$p)>;
4995 def : ARMInstAlias<"sxtab16${p} $Rd, $Rn, $Rm",
4996 (SXTAB16 GPRnopc:$Rd, GPR:$Rn, GPRnopc:$Rm, 0, pred:$p)>;
4997 def : ARMInstAlias<"sxtb${p} $Rd, $Rm",
4998 (SXTB GPRnopc:$Rd, GPRnopc:$Rm, 0, pred:$p)>;
4999 def : ARMInstAlias<"sxtb16${p} $Rd, $Rm",
5000 (SXTB16 GPRnopc:$Rd, GPRnopc:$Rm, 0, pred:$p)>;
5001 def : ARMInstAlias<"sxth${p} $Rd, $Rm",
5002 (SXTH GPRnopc:$Rd, GPRnopc:$Rm, 0, pred:$p)>;
5004 def : ARMInstAlias<"uxtab${p} $Rd, $Rn, $Rm",
5005 (UXTAB GPRnopc:$Rd, GPR:$Rn, GPRnopc:$Rm, 0, pred:$p)>;
5006 def : ARMInstAlias<"uxtah${p} $Rd, $Rn, $Rm",
5007 (UXTAH GPRnopc:$Rd, GPR:$Rn, GPRnopc:$Rm, 0, pred:$p)>;
5008 def : ARMInstAlias<"uxtab16${p} $Rd, $Rn, $Rm",
5009 (UXTAB16 GPRnopc:$Rd, GPR:$Rn, GPRnopc:$Rm, 0, pred:$p)>;
5010 def : ARMInstAlias<"uxtb${p} $Rd, $Rm",
5011 (UXTB GPRnopc:$Rd, GPRnopc:$Rm, 0, pred:$p)>;
5012 def : ARMInstAlias<"uxtb16${p} $Rd, $Rm",
5013 (UXTB16 GPRnopc:$Rd, GPRnopc:$Rm, 0, pred:$p)>;
5014 def : ARMInstAlias<"uxth${p} $Rd, $Rm",
5015 (UXTH GPRnopc:$Rd, GPRnopc:$Rm, 0, pred:$p)>;
5019 def : MnemonicAlias<"rfefa", "rfeda">;
5020 def : MnemonicAlias<"rfeea", "rfedb">;
5021 def : MnemonicAlias<"rfefd", "rfeia">;
5022 def : MnemonicAlias<"rfeed", "rfeib">;
5023 def : MnemonicAlias<"rfe", "rfeia">;
5026 def : MnemonicAlias<"srsfa", "srsda">;
5027 def : MnemonicAlias<"srsea", "srsdb">;
5028 def : MnemonicAlias<"srsfd", "srsia">;
5029 def : MnemonicAlias<"srsed", "srsib">;
5030 def : MnemonicAlias<"srs", "srsia">;
5033 def : MnemonicAlias<"qsubaddx", "qsax">;
5035 def : MnemonicAlias<"saddsubx", "sasx">;
5036 // SHASX == SHADDSUBX
5037 def : MnemonicAlias<"shaddsubx", "shasx">;
5038 // SHSAX == SHSUBADDX
5039 def : MnemonicAlias<"shsubaddx", "shsax">;
5041 def : MnemonicAlias<"ssubaddx", "ssax">;
5043 def : MnemonicAlias<"uaddsubx", "uasx">;
5044 // UHASX == UHADDSUBX
5045 def : MnemonicAlias<"uhaddsubx", "uhasx">;
5046 // UHSAX == UHSUBADDX
5047 def : MnemonicAlias<"uhsubaddx", "uhsax">;
5048 // UQASX == UQADDSUBX
5049 def : MnemonicAlias<"uqaddsubx", "uqasx">;
5050 // UQSAX == UQSUBADDX
5051 def : MnemonicAlias<"uqsubaddx", "uqsax">;
5053 def : MnemonicAlias<"usubaddx", "usax">;
5055 // "mov Rd, so_imm_not" can be handled via "mvn" in assembly, just like
5057 def : ARMInstAlias<"mov${s}${p} $Rd, $imm",
5058 (MVNi rGPR:$Rd, so_imm_not:$imm, pred:$p, cc_out:$s)>;
5059 def : ARMInstAlias<"mvn${s}${p} $Rd, $imm",
5060 (MOVi rGPR:$Rd, so_imm_not:$imm, pred:$p, cc_out:$s)>;
5061 // Same for AND <--> BIC
5062 def : ARMInstAlias<"bic${s}${p} $Rd, $Rn, $imm",
5063 (ANDri rGPR:$Rd, rGPR:$Rn, so_imm_not:$imm,
5064 pred:$p, cc_out:$s)>;
5065 def : ARMInstAlias<"bic${s}${p} $Rdn, $imm",
5066 (ANDri rGPR:$Rdn, rGPR:$Rdn, so_imm_not:$imm,
5067 pred:$p, cc_out:$s)>;
5068 def : ARMInstAlias<"and${s}${p} $Rd, $Rn, $imm",
5069 (BICri rGPR:$Rd, rGPR:$Rn, so_imm_not:$imm,
5070 pred:$p, cc_out:$s)>;
5071 def : ARMInstAlias<"and${s}${p} $Rdn, $imm",
5072 (BICri rGPR:$Rdn, rGPR:$Rdn, so_imm_not:$imm,
5073 pred:$p, cc_out:$s)>;
5075 // Likewise, "add Rd, so_imm_neg" -> sub
5076 def : ARMInstAlias<"add${s}${p} $Rd, $Rn, $imm",
5077 (SUBri GPR:$Rd, GPR:$Rn, so_imm_neg:$imm, pred:$p, cc_out:$s)>;
5078 def : ARMInstAlias<"add${s}${p} $Rd, $imm",
5079 (SUBri GPR:$Rd, GPR:$Rd, so_imm_neg:$imm, pred:$p, cc_out:$s)>;
5080 // Same for CMP <--> CMN via so_imm_neg
5081 def : ARMInstAlias<"cmp${p} $Rd, $imm",
5082 (CMNri rGPR:$Rd, so_imm_neg:$imm, pred:$p)>;
5083 def : ARMInstAlias<"cmn${p} $Rd, $imm",
5084 (CMPri rGPR:$Rd, so_imm_neg:$imm, pred:$p)>;
5086 // The shifter forms of the MOV instruction are aliased to the ASR, LSL,
5087 // LSR, ROR, and RRX instructions.
5088 // FIXME: We need C++ parser hooks to map the alias to the MOV
5089 // encoding. It seems we should be able to do that sort of thing
5090 // in tblgen, but it could get ugly.
5091 let TwoOperandAliasConstraint = "$Rm = $Rd" in {
5092 def ASRi : ARMAsmPseudo<"asr${s}${p} $Rd, $Rm, $imm",
5093 (ins GPR:$Rd, GPR:$Rm, imm0_32:$imm, pred:$p,
5095 def LSRi : ARMAsmPseudo<"lsr${s}${p} $Rd, $Rm, $imm",
5096 (ins GPR:$Rd, GPR:$Rm, imm0_32:$imm, pred:$p,
5098 def LSLi : ARMAsmPseudo<"lsl${s}${p} $Rd, $Rm, $imm",
5099 (ins GPR:$Rd, GPR:$Rm, imm0_31:$imm, pred:$p,
5101 def RORi : ARMAsmPseudo<"ror${s}${p} $Rd, $Rm, $imm",
5102 (ins GPR:$Rd, GPR:$Rm, imm0_31:$imm, pred:$p,
5105 def RRXi : ARMAsmPseudo<"rrx${s}${p} $Rd, $Rm",
5106 (ins GPRnopc:$Rd, GPRnopc:$Rm, pred:$p, cc_out:$s)>;
5107 let TwoOperandAliasConstraint = "$Rn = $Rd" in {
5108 def ASRr : ARMAsmPseudo<"asr${s}${p} $Rd, $Rn, $Rm",
5109 (ins GPRnopc:$Rd, GPRnopc:$Rn, GPRnopc:$Rm, pred:$p,
5111 def LSRr : ARMAsmPseudo<"lsr${s}${p} $Rd, $Rn, $Rm",
5112 (ins GPRnopc:$Rd, GPRnopc:$Rn, GPRnopc:$Rm, pred:$p,
5114 def LSLr : ARMAsmPseudo<"lsl${s}${p} $Rd, $Rn, $Rm",
5115 (ins GPRnopc:$Rd, GPRnopc:$Rn, GPRnopc:$Rm, pred:$p,
5117 def RORr : ARMAsmPseudo<"ror${s}${p} $Rd, $Rn, $Rm",
5118 (ins GPRnopc:$Rd, GPRnopc:$Rn, GPRnopc:$Rm, pred:$p,
5122 // "neg" is and alias for "rsb rd, rn, #0"
5123 def : ARMInstAlias<"neg${s}${p} $Rd, $Rm",
5124 (RSBri GPR:$Rd, GPR:$Rm, 0, pred:$p, cc_out:$s)>;
5126 // Pre-v6, 'mov r0, r0' was used as a NOP encoding.
5127 def : InstAlias<"nop${p}", (MOVr R0, R0, pred:$p, zero_reg)>,
5128 Requires<[IsARM, NoV6]>;
5130 // UMULL/SMULL are available on all arches, but the instruction definitions
5131 // need difference constraints pre-v6. Use these aliases for the assembly
5132 // parsing on pre-v6.
5133 def : InstAlias<"smull${s}${p} $RdLo, $RdHi, $Rn, $Rm",
5134 (SMULL GPR:$RdLo, GPR:$RdHi, GPR:$Rn, GPR:$Rm, pred:$p, cc_out:$s)>,
5135 Requires<[IsARM, NoV6]>;
5136 def : InstAlias<"umull${s}${p} $RdLo, $RdHi, $Rn, $Rm",
5137 (UMULL GPR:$RdLo, GPR:$RdHi, GPR:$Rn, GPR:$Rm, pred:$p, cc_out:$s)>,
5138 Requires<[IsARM, NoV6]>;
5140 // 'it' blocks in ARM mode just validate the predicates. The IT itself
5142 def ITasm : ARMAsmPseudo<"it$mask $cc", (ins it_pred:$cc, it_mask:$mask)>;