1 //===- ARMInstrInfo.td - Target Description for ARM Target -*- tablegen -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file describes the ARM instructions in TableGen format.
12 //===----------------------------------------------------------------------===//
14 //===----------------------------------------------------------------------===//
15 // ARM specific DAG Nodes.
19 def SDT_ARMCallSeqStart : SDCallSeqStart<[ SDTCisVT<0, i32> ]>;
20 def SDT_ARMCallSeqEnd : SDCallSeqEnd<[ SDTCisVT<0, i32>, SDTCisVT<1, i32> ]>;
22 def SDT_ARMSaveCallPC : SDTypeProfile<0, 1, []>;
24 def SDT_ARMcall : SDTypeProfile<0, -1, [SDTCisPtrTy<0>]>;
26 def SDT_ARMCMov : SDTypeProfile<1, 3,
27 [SDTCisSameAs<0, 1>, SDTCisSameAs<0, 2>,
30 def SDT_ARMBrcond : SDTypeProfile<0, 2,
31 [SDTCisVT<0, OtherVT>, SDTCisVT<1, i32>]>;
33 def SDT_ARMBrJT : SDTypeProfile<0, 3,
34 [SDTCisPtrTy<0>, SDTCisVT<1, i32>,
37 def SDT_ARMBr2JT : SDTypeProfile<0, 4,
38 [SDTCisPtrTy<0>, SDTCisVT<1, i32>,
39 SDTCisVT<2, i32>, SDTCisVT<3, i32>]>;
41 def SDT_ARMBCC_i64 : SDTypeProfile<0, 6,
43 SDTCisVT<1, i32>, SDTCisVT<2, i32>,
44 SDTCisVT<3, i32>, SDTCisVT<4, i32>,
45 SDTCisVT<5, OtherVT>]>;
47 def SDT_ARMAnd : SDTypeProfile<1, 2,
48 [SDTCisVT<0, i32>, SDTCisVT<1, i32>,
51 def SDT_ARMCmp : SDTypeProfile<0, 2, [SDTCisSameAs<0, 1>]>;
53 def SDT_ARMPICAdd : SDTypeProfile<1, 2, [SDTCisSameAs<0, 1>,
54 SDTCisPtrTy<1>, SDTCisVT<2, i32>]>;
56 def SDT_ARMThreadPointer : SDTypeProfile<1, 0, [SDTCisPtrTy<0>]>;
57 def SDT_ARMEH_SJLJ_Setjmp : SDTypeProfile<1, 2, [SDTCisInt<0>, SDTCisPtrTy<1>,
59 def SDT_ARMEH_SJLJ_Longjmp: SDTypeProfile<0, 2, [SDTCisPtrTy<0>, SDTCisInt<1>]>;
61 def SDT_ARMEH_SJLJ_DispatchSetup: SDTypeProfile<0, 1, [SDTCisPtrTy<0>]>;
63 def SDT_ARMMEMBARRIER : SDTypeProfile<0, 1, [SDTCisInt<0>]>;
65 def SDT_ARMTCRET : SDTypeProfile<0, 1, [SDTCisPtrTy<0>]>;
67 def SDT_ARMBFI : SDTypeProfile<1, 3, [SDTCisVT<0, i32>, SDTCisVT<1, i32>,
68 SDTCisVT<2, i32>, SDTCisVT<3, i32>]>;
71 def ARMWrapper : SDNode<"ARMISD::Wrapper", SDTIntUnaryOp>;
72 def ARMWrapperDYN : SDNode<"ARMISD::WrapperDYN", SDTIntUnaryOp>;
73 def ARMWrapperPIC : SDNode<"ARMISD::WrapperPIC", SDTIntUnaryOp>;
74 def ARMWrapperJT : SDNode<"ARMISD::WrapperJT", SDTIntBinOp>;
76 def ARMcallseq_start : SDNode<"ISD::CALLSEQ_START", SDT_ARMCallSeqStart,
77 [SDNPHasChain, SDNPOutGlue]>;
78 def ARMcallseq_end : SDNode<"ISD::CALLSEQ_END", SDT_ARMCallSeqEnd,
79 [SDNPHasChain, SDNPOptInGlue, SDNPOutGlue]>;
81 def ARMcall : SDNode<"ARMISD::CALL", SDT_ARMcall,
82 [SDNPHasChain, SDNPOptInGlue, SDNPOutGlue,
84 def ARMcall_pred : SDNode<"ARMISD::CALL_PRED", SDT_ARMcall,
85 [SDNPHasChain, SDNPOptInGlue, SDNPOutGlue,
87 def ARMcall_nolink : SDNode<"ARMISD::CALL_NOLINK", SDT_ARMcall,
88 [SDNPHasChain, SDNPOptInGlue, SDNPOutGlue,
91 def ARMretflag : SDNode<"ARMISD::RET_FLAG", SDTNone,
92 [SDNPHasChain, SDNPOptInGlue]>;
94 def ARMcmov : SDNode<"ARMISD::CMOV", SDT_ARMCMov,
97 def ARMbrcond : SDNode<"ARMISD::BRCOND", SDT_ARMBrcond,
98 [SDNPHasChain, SDNPInGlue, SDNPOutGlue]>;
100 def ARMbrjt : SDNode<"ARMISD::BR_JT", SDT_ARMBrJT,
102 def ARMbr2jt : SDNode<"ARMISD::BR2_JT", SDT_ARMBr2JT,
105 def ARMBcci64 : SDNode<"ARMISD::BCC_i64", SDT_ARMBCC_i64,
108 def ARMcmp : SDNode<"ARMISD::CMP", SDT_ARMCmp,
111 def ARMcmpZ : SDNode<"ARMISD::CMPZ", SDT_ARMCmp,
112 [SDNPOutGlue, SDNPCommutative]>;
114 def ARMpic_add : SDNode<"ARMISD::PIC_ADD", SDT_ARMPICAdd>;
116 def ARMsrl_flag : SDNode<"ARMISD::SRL_FLAG", SDTIntUnaryOp, [SDNPOutGlue]>;
117 def ARMsra_flag : SDNode<"ARMISD::SRA_FLAG", SDTIntUnaryOp, [SDNPOutGlue]>;
118 def ARMrrx : SDNode<"ARMISD::RRX" , SDTIntUnaryOp, [SDNPInGlue ]>;
120 def ARMthread_pointer: SDNode<"ARMISD::THREAD_POINTER", SDT_ARMThreadPointer>;
121 def ARMeh_sjlj_setjmp: SDNode<"ARMISD::EH_SJLJ_SETJMP",
122 SDT_ARMEH_SJLJ_Setjmp, [SDNPHasChain]>;
123 def ARMeh_sjlj_longjmp: SDNode<"ARMISD::EH_SJLJ_LONGJMP",
124 SDT_ARMEH_SJLJ_Longjmp, [SDNPHasChain]>;
125 def ARMeh_sjlj_dispatchsetup: SDNode<"ARMISD::EH_SJLJ_DISPATCHSETUP",
126 SDT_ARMEH_SJLJ_DispatchSetup, [SDNPHasChain]>;
129 def ARMMemBarrier : SDNode<"ARMISD::MEMBARRIER", SDT_ARMMEMBARRIER,
131 def ARMMemBarrierMCR : SDNode<"ARMISD::MEMBARRIER_MCR", SDT_ARMMEMBARRIER,
133 def ARMPreload : SDNode<"ARMISD::PRELOAD", SDTPrefetch,
134 [SDNPHasChain, SDNPMayLoad, SDNPMayStore]>;
136 def ARMrbit : SDNode<"ARMISD::RBIT", SDTIntUnaryOp>;
138 def ARMtcret : SDNode<"ARMISD::TC_RETURN", SDT_ARMTCRET,
139 [SDNPHasChain, SDNPOptInGlue, SDNPVariadic]>;
142 def ARMbfi : SDNode<"ARMISD::BFI", SDT_ARMBFI>;
144 //===----------------------------------------------------------------------===//
145 // ARM Instruction Predicate Definitions.
147 def HasV4T : Predicate<"Subtarget->hasV4TOps()">, AssemblerPredicate;
148 def NoV4T : Predicate<"!Subtarget->hasV4TOps()">;
149 def HasV5T : Predicate<"Subtarget->hasV5TOps()">;
150 def HasV5TE : Predicate<"Subtarget->hasV5TEOps()">, AssemblerPredicate;
151 def HasV6 : Predicate<"Subtarget->hasV6Ops()">, AssemblerPredicate;
152 def NoV6 : Predicate<"!Subtarget->hasV6Ops()">;
153 def HasV6T2 : Predicate<"Subtarget->hasV6T2Ops()">, AssemblerPredicate;
154 def NoV6T2 : Predicate<"!Subtarget->hasV6T2Ops()">;
155 def HasV7 : Predicate<"Subtarget->hasV7Ops()">, AssemblerPredicate;
156 def NoVFP : Predicate<"!Subtarget->hasVFP2()">;
157 def HasVFP2 : Predicate<"Subtarget->hasVFP2()">, AssemblerPredicate;
158 def HasVFP3 : Predicate<"Subtarget->hasVFP3()">, AssemblerPredicate;
159 def HasNEON : Predicate<"Subtarget->hasNEON()">, AssemblerPredicate;
160 def HasFP16 : Predicate<"Subtarget->hasFP16()">, AssemblerPredicate;
161 def HasDivide : Predicate<"Subtarget->hasDivide()">, AssemblerPredicate;
162 def HasT2ExtractPack : Predicate<"Subtarget->hasT2ExtractPack()">,
164 def HasDB : Predicate<"Subtarget->hasDataBarrier()">,
166 def HasMP : Predicate<"Subtarget->hasMPExtension()">,
168 def UseNEONForFP : Predicate<"Subtarget->useNEONForSinglePrecisionFP()">;
169 def DontUseNEONForFP : Predicate<"!Subtarget->useNEONForSinglePrecisionFP()">;
170 def IsThumb : Predicate<"Subtarget->isThumb()">, AssemblerPredicate;
171 def IsThumb1Only : Predicate<"Subtarget->isThumb1Only()">;
172 def IsThumb2 : Predicate<"Subtarget->isThumb2()">, AssemblerPredicate;
173 def IsARM : Predicate<"!Subtarget->isThumb()">, AssemblerPredicate;
174 def IsDarwin : Predicate<"Subtarget->isTargetDarwin()">;
175 def IsNotDarwin : Predicate<"!Subtarget->isTargetDarwin()">;
177 // FIXME: Eventually this will be just "hasV6T2Ops".
178 def UseMovt : Predicate<"Subtarget->useMovt()">;
179 def DontUseMovt : Predicate<"!Subtarget->useMovt()">;
180 def UseFPVMLx : Predicate<"Subtarget->useFPVMLx()">;
182 //===----------------------------------------------------------------------===//
183 // ARM Flag Definitions.
185 class RegConstraint<string C> {
186 string Constraints = C;
189 //===----------------------------------------------------------------------===//
190 // ARM specific transformation functions and pattern fragments.
193 // so_imm_neg_XFORM - Return a so_imm value packed into the format described for
194 // so_imm_neg def below.
195 def so_imm_neg_XFORM : SDNodeXForm<imm, [{
196 return CurDAG->getTargetConstant(-(int)N->getZExtValue(), MVT::i32);
199 // so_imm_not_XFORM - Return a so_imm value packed into the format described for
200 // so_imm_not def below.
201 def so_imm_not_XFORM : SDNodeXForm<imm, [{
202 return CurDAG->getTargetConstant(~(int)N->getZExtValue(), MVT::i32);
205 /// imm1_15 predicate - True if the 32-bit immediate is in the range [1,15].
206 def imm1_15 : PatLeaf<(i32 imm), [{
207 return (int32_t)N->getZExtValue() >= 1 && (int32_t)N->getZExtValue() < 16;
210 /// imm16_31 predicate - True if the 32-bit immediate is in the range [16,31].
211 def imm16_31 : PatLeaf<(i32 imm), [{
212 return (int32_t)N->getZExtValue() >= 16 && (int32_t)N->getZExtValue() < 32;
217 return ARM_AM::getSOImmVal(-(uint32_t)N->getZExtValue()) != -1;
218 }], so_imm_neg_XFORM>;
222 return ARM_AM::getSOImmVal(~(uint32_t)N->getZExtValue()) != -1;
223 }], so_imm_not_XFORM>;
225 // sext_16_node predicate - True if the SDNode is sign-extended 16 or more bits.
226 def sext_16_node : PatLeaf<(i32 GPR:$a), [{
227 return CurDAG->ComputeNumSignBits(SDValue(N,0)) >= 17;
230 /// Split a 32-bit immediate into two 16 bit parts.
231 def hi16 : SDNodeXForm<imm, [{
232 return CurDAG->getTargetConstant((uint32_t)N->getZExtValue() >> 16, MVT::i32);
235 def lo16AllZero : PatLeaf<(i32 imm), [{
236 // Returns true if all low 16-bits are 0.
237 return (((uint32_t)N->getZExtValue()) & 0xFFFFUL) == 0;
240 /// imm0_65535 predicate - True if the 32-bit immediate is in the range
242 def imm0_65535 : PatLeaf<(i32 imm), [{
243 return (uint32_t)N->getZExtValue() < 65536;
246 class BinOpFrag<dag res> : PatFrag<(ops node:$LHS, node:$RHS), res>;
247 class UnOpFrag <dag res> : PatFrag<(ops node:$Src), res>;
249 /// adde and sube predicates - True based on whether the carry flag output
250 /// will be needed or not.
251 def adde_dead_carry :
252 PatFrag<(ops node:$LHS, node:$RHS), (adde node:$LHS, node:$RHS),
253 [{return !N->hasAnyUseOfValue(1);}]>;
254 def sube_dead_carry :
255 PatFrag<(ops node:$LHS, node:$RHS), (sube node:$LHS, node:$RHS),
256 [{return !N->hasAnyUseOfValue(1);}]>;
257 def adde_live_carry :
258 PatFrag<(ops node:$LHS, node:$RHS), (adde node:$LHS, node:$RHS),
259 [{return N->hasAnyUseOfValue(1);}]>;
260 def sube_live_carry :
261 PatFrag<(ops node:$LHS, node:$RHS), (sube node:$LHS, node:$RHS),
262 [{return N->hasAnyUseOfValue(1);}]>;
264 // An 'and' node with a single use.
265 def and_su : PatFrag<(ops node:$lhs, node:$rhs), (and node:$lhs, node:$rhs), [{
266 return N->hasOneUse();
269 // An 'xor' node with a single use.
270 def xor_su : PatFrag<(ops node:$lhs, node:$rhs), (xor node:$lhs, node:$rhs), [{
271 return N->hasOneUse();
274 // An 'fmul' node with a single use.
275 def fmul_su : PatFrag<(ops node:$lhs, node:$rhs), (fmul node:$lhs, node:$rhs),[{
276 return N->hasOneUse();
279 // An 'fadd' node which checks for single non-hazardous use.
280 def fadd_mlx : PatFrag<(ops node:$lhs, node:$rhs),(fadd node:$lhs, node:$rhs),[{
281 return hasNoVMLxHazardUse(N);
284 // An 'fsub' node which checks for single non-hazardous use.
285 def fsub_mlx : PatFrag<(ops node:$lhs, node:$rhs),(fsub node:$lhs, node:$rhs),[{
286 return hasNoVMLxHazardUse(N);
289 //===----------------------------------------------------------------------===//
290 // Operand Definitions.
294 // FIXME: rename brtarget to t2_brtarget
295 def brtarget : Operand<OtherVT> {
296 let EncoderMethod = "getBranchTargetOpValue";
299 // FIXME: get rid of this one?
300 def uncondbrtarget : Operand<OtherVT> {
301 let EncoderMethod = "getUnconditionalBranchTargetOpValue";
304 // Branch target for ARM. Handles conditional/unconditional
305 def br_target : Operand<OtherVT> {
306 let EncoderMethod = "getARMBranchTargetOpValue";
310 // FIXME: rename bltarget to t2_bl_target?
311 def bltarget : Operand<i32> {
312 // Encoded the same as branch targets.
313 let EncoderMethod = "getBranchTargetOpValue";
316 // Call target for ARM. Handles conditional/unconditional
317 // FIXME: rename bl_target to t2_bltarget?
318 def bl_target : Operand<i32> {
319 // Encoded the same as branch targets.
320 let EncoderMethod = "getARMBranchTargetOpValue";
324 // A list of registers separated by comma. Used by load/store multiple.
325 def RegListAsmOperand : AsmOperandClass {
326 let Name = "RegList";
327 let SuperClasses = [];
330 def DPRRegListAsmOperand : AsmOperandClass {
331 let Name = "DPRRegList";
332 let SuperClasses = [];
335 def SPRRegListAsmOperand : AsmOperandClass {
336 let Name = "SPRRegList";
337 let SuperClasses = [];
340 def reglist : Operand<i32> {
341 let EncoderMethod = "getRegisterListOpValue";
342 let ParserMatchClass = RegListAsmOperand;
343 let PrintMethod = "printRegisterList";
346 def dpr_reglist : Operand<i32> {
347 let EncoderMethod = "getRegisterListOpValue";
348 let ParserMatchClass = DPRRegListAsmOperand;
349 let PrintMethod = "printRegisterList";
352 def spr_reglist : Operand<i32> {
353 let EncoderMethod = "getRegisterListOpValue";
354 let ParserMatchClass = SPRRegListAsmOperand;
355 let PrintMethod = "printRegisterList";
358 // An operand for the CONSTPOOL_ENTRY pseudo-instruction.
359 def cpinst_operand : Operand<i32> {
360 let PrintMethod = "printCPInstOperand";
364 def pclabel : Operand<i32> {
365 let PrintMethod = "printPCLabel";
368 // ADR instruction labels.
369 def adrlabel : Operand<i32> {
370 let EncoderMethod = "getAdrLabelOpValue";
373 def neon_vcvt_imm32 : Operand<i32> {
374 let EncoderMethod = "getNEONVcvtImm32OpValue";
377 // rot_imm: An integer that encodes a rotate amount. Must be 8, 16, or 24.
378 def rot_imm : Operand<i32>, PatLeaf<(i32 imm), [{
379 int32_t v = (int32_t)N->getZExtValue();
380 return v == 8 || v == 16 || v == 24; }]> {
381 let EncoderMethod = "getRotImmOpValue";
384 def ShifterAsmOperand : AsmOperandClass {
385 let Name = "Shifter";
386 let SuperClasses = [];
389 // shift_imm: An integer that encodes a shift amount and the type of shift
390 // (currently either asr or lsl) using the same encoding used for the
391 // immediates in so_reg operands.
392 def shift_imm : Operand<i32> {
393 let PrintMethod = "printShiftImmOperand";
394 let ParserMatchClass = ShifterAsmOperand;
397 // shifter_operand operands: so_reg and so_imm.
398 def so_reg : Operand<i32>, // reg reg imm
399 ComplexPattern<i32, 3, "SelectShifterOperandReg",
400 [shl,srl,sra,rotr]> {
401 let EncoderMethod = "getSORegOpValue";
402 let PrintMethod = "printSORegOperand";
403 let MIOperandInfo = (ops GPR, GPR, shift_imm);
405 def shift_so_reg : Operand<i32>, // reg reg imm
406 ComplexPattern<i32, 3, "SelectShiftShifterOperandReg",
407 [shl,srl,sra,rotr]> {
408 let EncoderMethod = "getSORegOpValue";
409 let PrintMethod = "printSORegOperand";
410 let MIOperandInfo = (ops GPR, GPR, shift_imm);
413 // so_imm - Match a 32-bit shifter_operand immediate operand, which is an
414 // 8-bit immediate rotated by an arbitrary number of bits.
415 def so_imm : Operand<i32>, PatLeaf<(imm), [{ return Pred_so_imm(N); }]> {
416 let EncoderMethod = "getSOImmOpValue";
417 let PrintMethod = "printSOImmOperand";
420 // Break so_imm's up into two pieces. This handles immediates with up to 16
421 // bits set in them. This uses so_imm2part to match and so_imm2part_[12] to
422 // get the first/second pieces.
423 def so_imm2part : PatLeaf<(imm), [{
424 return ARM_AM::isSOImmTwoPartVal((unsigned)N->getZExtValue());
427 /// arm_i32imm - True for +V6T2, or true only if so_imm2part is true.
429 def arm_i32imm : PatLeaf<(imm), [{
430 if (Subtarget->hasV6T2Ops())
432 return ARM_AM::isSOImmTwoPartVal((unsigned)N->getZExtValue());
435 /// imm0_31 predicate - True if the 32-bit immediate is in the range [0,31].
436 def imm0_31 : Operand<i32>, PatLeaf<(imm), [{
437 return (int32_t)N->getZExtValue() < 32;
440 /// imm0_31_m1 - Matches and prints like imm0_31, but encodes as 'value - 1'.
441 def imm0_31_m1 : Operand<i32>, PatLeaf<(imm), [{
442 return (int32_t)N->getZExtValue() < 32;
444 let EncoderMethod = "getImmMinusOneOpValue";
447 // i32imm_hilo16 - For movt/movw - sets the MC Encoder method.
448 // The imm is split into imm{15-12}, imm{11-0}
450 def i32imm_hilo16 : Operand<i32> {
451 let EncoderMethod = "getHiLo16ImmOpValue";
454 /// bf_inv_mask_imm predicate - An AND mask to clear an arbitrary width bitfield
456 def bf_inv_mask_imm : Operand<i32>,
458 return ARM::isBitFieldInvertedMask(N->getZExtValue());
460 let EncoderMethod = "getBitfieldInvertedMaskOpValue";
461 let PrintMethod = "printBitfieldInvMaskImmOperand";
464 /// lsb_pos_imm - position of the lsb bit, used by BFI4p and t2BFI4p
465 def lsb_pos_imm : Operand<i32>, PatLeaf<(imm), [{
466 return isInt<5>(N->getSExtValue());
469 /// width_imm - number of bits to be copied, used by BFI4p and t2BFI4p
470 def width_imm : Operand<i32>, PatLeaf<(imm), [{
471 return N->getSExtValue() > 0 && N->getSExtValue() <= 32;
473 let EncoderMethod = "getMsbOpValue";
476 // Define ARM specific addressing modes.
479 // addrmode_imm12 := reg +/- imm12
481 def addrmode_imm12 : Operand<i32>,
482 ComplexPattern<i32, 2, "SelectAddrModeImm12", []> {
483 // 12-bit immediate operand. Note that instructions using this encode
484 // #0 and #-0 differently. We flag #-0 as the magic value INT32_MIN. All other
485 // immediate values are as normal.
487 let EncoderMethod = "getAddrModeImm12OpValue";
488 let PrintMethod = "printAddrModeImm12Operand";
489 let MIOperandInfo = (ops GPR:$base, i32imm:$offsimm);
491 // ldst_so_reg := reg +/- reg shop imm
493 def ldst_so_reg : Operand<i32>,
494 ComplexPattern<i32, 3, "SelectLdStSOReg", []> {
495 let EncoderMethod = "getLdStSORegOpValue";
496 // FIXME: Simplify the printer
497 let PrintMethod = "printAddrMode2Operand";
498 let MIOperandInfo = (ops GPR:$base, GPR:$offsreg, i32imm:$offsimm);
501 // addrmode2 := reg +/- imm12
502 // := reg +/- reg shop imm
504 def addrmode2 : Operand<i32>,
505 ComplexPattern<i32, 3, "SelectAddrMode2", []> {
506 let EncoderMethod = "getAddrMode2OpValue";
507 let PrintMethod = "printAddrMode2Operand";
508 let MIOperandInfo = (ops GPR:$base, GPR:$offsreg, i32imm:$offsimm);
511 def am2offset : Operand<i32>,
512 ComplexPattern<i32, 2, "SelectAddrMode2Offset",
513 [], [SDNPWantRoot]> {
514 let EncoderMethod = "getAddrMode2OffsetOpValue";
515 let PrintMethod = "printAddrMode2OffsetOperand";
516 let MIOperandInfo = (ops GPR, i32imm);
519 // addrmode3 := reg +/- reg
520 // addrmode3 := reg +/- imm8
522 def addrmode3 : Operand<i32>,
523 ComplexPattern<i32, 3, "SelectAddrMode3", []> {
524 let EncoderMethod = "getAddrMode3OpValue";
525 let PrintMethod = "printAddrMode3Operand";
526 let MIOperandInfo = (ops GPR:$base, GPR:$offsreg, i32imm:$offsimm);
529 def am3offset : Operand<i32>,
530 ComplexPattern<i32, 2, "SelectAddrMode3Offset",
531 [], [SDNPWantRoot]> {
532 let EncoderMethod = "getAddrMode3OffsetOpValue";
533 let PrintMethod = "printAddrMode3OffsetOperand";
534 let MIOperandInfo = (ops GPR, i32imm);
537 // ldstm_mode := {ia, ib, da, db}
539 def ldstm_mode : OptionalDefOperand<OtherVT, (ops i32), (ops (i32 1))> {
540 let EncoderMethod = "getLdStmModeOpValue";
541 let PrintMethod = "printLdStmModeOperand";
544 def MemMode5AsmOperand : AsmOperandClass {
545 let Name = "MemMode5";
546 let SuperClasses = [];
549 // addrmode5 := reg +/- imm8*4
551 def addrmode5 : Operand<i32>,
552 ComplexPattern<i32, 2, "SelectAddrMode5", []> {
553 let PrintMethod = "printAddrMode5Operand";
554 let MIOperandInfo = (ops GPR:$base, i32imm);
555 let ParserMatchClass = MemMode5AsmOperand;
556 let EncoderMethod = "getAddrMode5OpValue";
559 // addrmode6 := reg with optional alignment
561 def addrmode6 : Operand<i32>,
562 ComplexPattern<i32, 2, "SelectAddrMode6", [], [SDNPWantParent]>{
563 let PrintMethod = "printAddrMode6Operand";
564 let MIOperandInfo = (ops GPR:$addr, i32imm);
565 let EncoderMethod = "getAddrMode6AddressOpValue";
568 def am6offset : Operand<i32>,
569 ComplexPattern<i32, 1, "SelectAddrMode6Offset",
570 [], [SDNPWantRoot]> {
571 let PrintMethod = "printAddrMode6OffsetOperand";
572 let MIOperandInfo = (ops GPR);
573 let EncoderMethod = "getAddrMode6OffsetOpValue";
576 // Special version of addrmode6 to handle alignment encoding for VLD-dup
577 // instructions, specifically VLD4-dup.
578 def addrmode6dup : Operand<i32>,
579 ComplexPattern<i32, 2, "SelectAddrMode6", [], [SDNPWantParent]>{
580 let PrintMethod = "printAddrMode6Operand";
581 let MIOperandInfo = (ops GPR:$addr, i32imm);
582 let EncoderMethod = "getAddrMode6DupAddressOpValue";
585 // addrmodepc := pc + reg
587 def addrmodepc : Operand<i32>,
588 ComplexPattern<i32, 2, "SelectAddrModePC", []> {
589 let PrintMethod = "printAddrModePCOperand";
590 let MIOperandInfo = (ops GPR, i32imm);
593 def MemMode7AsmOperand : AsmOperandClass {
594 let Name = "MemMode7";
595 let SuperClasses = [];
599 // Used by load/store exclusive instructions. Useful to enable right assembly
600 // parsing and printing. Not used for any codegen matching.
602 def addrmode7 : Operand<i32> {
603 let PrintMethod = "printAddrMode7Operand";
604 let MIOperandInfo = (ops GPR);
605 let ParserMatchClass = MemMode7AsmOperand;
608 def nohash_imm : Operand<i32> {
609 let PrintMethod = "printNoHashImmediate";
612 def CoprocNumAsmOperand : AsmOperandClass {
613 let Name = "CoprocNum";
614 let SuperClasses = [];
615 let ParserMethod = "tryParseCoprocNumOperand";
618 def CoprocRegAsmOperand : AsmOperandClass {
619 let Name = "CoprocReg";
620 let SuperClasses = [];
621 let ParserMethod = "tryParseCoprocRegOperand";
624 def p_imm : Operand<i32> {
625 let PrintMethod = "printPImmediate";
626 let ParserMatchClass = CoprocNumAsmOperand;
629 def c_imm : Operand<i32> {
630 let PrintMethod = "printCImmediate";
631 let ParserMatchClass = CoprocRegAsmOperand;
634 //===----------------------------------------------------------------------===//
636 include "ARMInstrFormats.td"
638 //===----------------------------------------------------------------------===//
639 // Multiclass helpers...
642 /// AsI1_bin_irs - Defines a set of (op r, {so_imm|r|so_reg}) patterns for a
643 /// binop that produces a value.
644 multiclass AsI1_bin_irs<bits<4> opcod, string opc,
645 InstrItinClass iii, InstrItinClass iir, InstrItinClass iis,
646 PatFrag opnode, bit Commutable = 0> {
647 // The register-immediate version is re-materializable. This is useful
648 // in particular for taking the address of a local.
649 let isReMaterializable = 1 in {
650 def ri : AsI1<opcod, (outs GPR:$Rd), (ins GPR:$Rn, so_imm:$imm), DPFrm,
651 iii, opc, "\t$Rd, $Rn, $imm",
652 [(set GPR:$Rd, (opnode GPR:$Rn, so_imm:$imm))]> {
657 let Inst{19-16} = Rn;
658 let Inst{15-12} = Rd;
659 let Inst{11-0} = imm;
662 def rr : AsI1<opcod, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm), DPFrm,
663 iir, opc, "\t$Rd, $Rn, $Rm",
664 [(set GPR:$Rd, (opnode GPR:$Rn, GPR:$Rm))]> {
669 let isCommutable = Commutable;
670 let Inst{19-16} = Rn;
671 let Inst{15-12} = Rd;
672 let Inst{11-4} = 0b00000000;
675 def rs : AsI1<opcod, (outs GPR:$Rd), (ins GPR:$Rn, so_reg:$shift), DPSoRegFrm,
676 iis, opc, "\t$Rd, $Rn, $shift",
677 [(set GPR:$Rd, (opnode GPR:$Rn, so_reg:$shift))]> {
682 let Inst{19-16} = Rn;
683 let Inst{15-12} = Rd;
684 let Inst{11-0} = shift;
688 /// AI1_bin_s_irs - Similar to AsI1_bin_irs except it sets the 's' bit so the
689 /// instruction modifies the CPSR register.
690 let isCodeGenOnly = 1, Defs = [CPSR] in {
691 multiclass AI1_bin_s_irs<bits<4> opcod, string opc,
692 InstrItinClass iii, InstrItinClass iir, InstrItinClass iis,
693 PatFrag opnode, bit Commutable = 0> {
694 def ri : AI1<opcod, (outs GPR:$Rd), (ins GPR:$Rn, so_imm:$imm), DPFrm,
695 iii, opc, "\t$Rd, $Rn, $imm",
696 [(set GPR:$Rd, (opnode GPR:$Rn, so_imm:$imm))]> {
702 let Inst{19-16} = Rn;
703 let Inst{15-12} = Rd;
704 let Inst{11-0} = imm;
706 def rr : AI1<opcod, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm), DPFrm,
707 iir, opc, "\t$Rd, $Rn, $Rm",
708 [(set GPR:$Rd, (opnode GPR:$Rn, GPR:$Rm))]> {
712 let isCommutable = Commutable;
715 let Inst{19-16} = Rn;
716 let Inst{15-12} = Rd;
717 let Inst{11-4} = 0b00000000;
720 def rs : AI1<opcod, (outs GPR:$Rd), (ins GPR:$Rn, so_reg:$shift), DPSoRegFrm,
721 iis, opc, "\t$Rd, $Rn, $shift",
722 [(set GPR:$Rd, (opnode GPR:$Rn, so_reg:$shift))]> {
728 let Inst{19-16} = Rn;
729 let Inst{15-12} = Rd;
730 let Inst{11-0} = shift;
735 /// AI1_cmp_irs - Defines a set of (op r, {so_imm|r|so_reg}) cmp / test
736 /// patterns. Similar to AsI1_bin_irs except the instruction does not produce
737 /// a explicit result, only implicitly set CPSR.
738 let isCompare = 1, Defs = [CPSR] in {
739 multiclass AI1_cmp_irs<bits<4> opcod, string opc,
740 InstrItinClass iii, InstrItinClass iir, InstrItinClass iis,
741 PatFrag opnode, bit Commutable = 0> {
742 def ri : AI1<opcod, (outs), (ins GPR:$Rn, so_imm:$imm), DPFrm, iii,
744 [(opnode GPR:$Rn, so_imm:$imm)]> {
749 let Inst{19-16} = Rn;
750 let Inst{15-12} = 0b0000;
751 let Inst{11-0} = imm;
753 def rr : AI1<opcod, (outs), (ins GPR:$Rn, GPR:$Rm), DPFrm, iir,
755 [(opnode GPR:$Rn, GPR:$Rm)]> {
758 let isCommutable = Commutable;
761 let Inst{19-16} = Rn;
762 let Inst{15-12} = 0b0000;
763 let Inst{11-4} = 0b00000000;
766 def rs : AI1<opcod, (outs), (ins GPR:$Rn, so_reg:$shift), DPSoRegFrm, iis,
767 opc, "\t$Rn, $shift",
768 [(opnode GPR:$Rn, so_reg:$shift)]> {
773 let Inst{19-16} = Rn;
774 let Inst{15-12} = 0b0000;
775 let Inst{11-0} = shift;
780 /// AI_ext_rrot - A unary operation with two forms: one whose operand is a
781 /// register and one whose operand is a register rotated by 8/16/24.
782 /// FIXME: Remove the 'r' variant. Its rot_imm is zero.
783 multiclass AI_ext_rrot<bits<8> opcod, string opc, PatFrag opnode> {
784 def r : AExtI<opcod, (outs GPR:$Rd), (ins GPR:$Rm),
785 IIC_iEXTr, opc, "\t$Rd, $Rm",
786 [(set GPR:$Rd, (opnode GPR:$Rm))]>,
787 Requires<[IsARM, HasV6]> {
790 let Inst{19-16} = 0b1111;
791 let Inst{15-12} = Rd;
792 let Inst{11-10} = 0b00;
795 def r_rot : AExtI<opcod, (outs GPR:$Rd), (ins GPR:$Rm, rot_imm:$rot),
796 IIC_iEXTr, opc, "\t$Rd, $Rm, ror $rot",
797 [(set GPR:$Rd, (opnode (rotr GPR:$Rm, rot_imm:$rot)))]>,
798 Requires<[IsARM, HasV6]> {
802 let Inst{19-16} = 0b1111;
803 let Inst{15-12} = Rd;
804 let Inst{11-10} = rot;
809 multiclass AI_ext_rrot_np<bits<8> opcod, string opc> {
810 def r : AExtI<opcod, (outs GPR:$Rd), (ins GPR:$Rm),
811 IIC_iEXTr, opc, "\t$Rd, $Rm",
812 [/* For disassembly only; pattern left blank */]>,
813 Requires<[IsARM, HasV6]> {
814 let Inst{19-16} = 0b1111;
815 let Inst{11-10} = 0b00;
817 def r_rot : AExtI<opcod, (outs GPR:$Rd), (ins GPR:$Rm, rot_imm:$rot),
818 IIC_iEXTr, opc, "\t$Rd, $Rm, ror $rot",
819 [/* For disassembly only; pattern left blank */]>,
820 Requires<[IsARM, HasV6]> {
822 let Inst{19-16} = 0b1111;
823 let Inst{11-10} = rot;
827 /// AI_exta_rrot - A binary operation with two forms: one whose operand is a
828 /// register and one whose operand is a register rotated by 8/16/24.
829 multiclass AI_exta_rrot<bits<8> opcod, string opc, PatFrag opnode> {
830 def rr : AExtI<opcod, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm),
831 IIC_iEXTAr, opc, "\t$Rd, $Rn, $Rm",
832 [(set GPR:$Rd, (opnode GPR:$Rn, GPR:$Rm))]>,
833 Requires<[IsARM, HasV6]> {
837 let Inst{19-16} = Rn;
838 let Inst{15-12} = Rd;
839 let Inst{11-10} = 0b00;
840 let Inst{9-4} = 0b000111;
843 def rr_rot : AExtI<opcod, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm,
845 IIC_iEXTAr, opc, "\t$Rd, $Rn, $Rm, ror $rot",
846 [(set GPR:$Rd, (opnode GPR:$Rn,
847 (rotr GPR:$Rm, rot_imm:$rot)))]>,
848 Requires<[IsARM, HasV6]> {
853 let Inst{19-16} = Rn;
854 let Inst{15-12} = Rd;
855 let Inst{11-10} = rot;
856 let Inst{9-4} = 0b000111;
861 // For disassembly only.
862 multiclass AI_exta_rrot_np<bits<8> opcod, string opc> {
863 def rr : AExtI<opcod, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm),
864 IIC_iEXTAr, opc, "\t$Rd, $Rn, $Rm",
865 [/* For disassembly only; pattern left blank */]>,
866 Requires<[IsARM, HasV6]> {
867 let Inst{11-10} = 0b00;
869 def rr_rot : AExtI<opcod, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm,
871 IIC_iEXTAr, opc, "\t$Rd, $Rn, $Rm, ror $rot",
872 [/* For disassembly only; pattern left blank */]>,
873 Requires<[IsARM, HasV6]> {
876 let Inst{19-16} = Rn;
877 let Inst{11-10} = rot;
881 /// AI1_adde_sube_irs - Define instructions and patterns for adde and sube.
882 let Uses = [CPSR] in {
883 multiclass AI1_adde_sube_irs<bits<4> opcod, string opc, PatFrag opnode,
884 bit Commutable = 0> {
885 def ri : AsI1<opcod, (outs GPR:$Rd), (ins GPR:$Rn, so_imm:$imm),
886 DPFrm, IIC_iALUi, opc, "\t$Rd, $Rn, $imm",
887 [(set GPR:$Rd, (opnode GPR:$Rn, so_imm:$imm))]>,
893 let Inst{15-12} = Rd;
894 let Inst{19-16} = Rn;
895 let Inst{11-0} = imm;
897 def rr : AsI1<opcod, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm),
898 DPFrm, IIC_iALUr, opc, "\t$Rd, $Rn, $Rm",
899 [(set GPR:$Rd, (opnode GPR:$Rn, GPR:$Rm))]>,
904 let Inst{11-4} = 0b00000000;
906 let isCommutable = Commutable;
908 let Inst{15-12} = Rd;
909 let Inst{19-16} = Rn;
911 def rs : AsI1<opcod, (outs GPR:$Rd), (ins GPR:$Rn, so_reg:$shift),
912 DPSoRegFrm, IIC_iALUsr, opc, "\t$Rd, $Rn, $shift",
913 [(set GPR:$Rd, (opnode GPR:$Rn, so_reg:$shift))]>,
919 let Inst{11-0} = shift;
920 let Inst{15-12} = Rd;
921 let Inst{19-16} = Rn;
924 // Carry setting variants
925 let isCodeGenOnly = 1, Defs = [CPSR] in {
926 multiclass AI1_adde_sube_s_irs<bits<4> opcod, string opc, PatFrag opnode,
927 bit Commutable = 0> {
928 def Sri : AXI1<opcod, (outs GPR:$Rd), (ins GPR:$Rn, so_imm:$imm),
929 DPFrm, IIC_iALUi, !strconcat(opc, "\t$Rd, $Rn, $imm"),
930 [(set GPR:$Rd, (opnode GPR:$Rn, so_imm:$imm))]>,
935 let Inst{15-12} = Rd;
936 let Inst{19-16} = Rn;
937 let Inst{11-0} = imm;
941 def Srr : AXI1<opcod, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm),
942 DPFrm, IIC_iALUr, !strconcat(opc, "\t$Rd, $Rn, $Rm"),
943 [(set GPR:$Rd, (opnode GPR:$Rn, GPR:$Rm))]>,
948 let Inst{11-4} = 0b00000000;
949 let isCommutable = Commutable;
951 let Inst{15-12} = Rd;
952 let Inst{19-16} = Rn;
956 def Srs : AXI1<opcod, (outs GPR:$Rd), (ins GPR:$Rn, so_reg:$shift),
957 DPSoRegFrm, IIC_iALUsr, !strconcat(opc, "\t$Rd, $Rn, $shift"),
958 [(set GPR:$Rd, (opnode GPR:$Rn, so_reg:$shift))]>,
963 let Inst{11-0} = shift;
964 let Inst{15-12} = Rd;
965 let Inst{19-16} = Rn;
973 let canFoldAsLoad = 1, isReMaterializable = 1 in {
974 multiclass AI_ldr1<bit isByte, string opc, InstrItinClass iii,
975 InstrItinClass iir, PatFrag opnode> {
976 // Note: We use the complex addrmode_imm12 rather than just an input
977 // GPR and a constrained immediate so that we can use this to match
978 // frame index references and avoid matching constant pool references.
979 def i12: AI2ldst<0b010, 1, isByte, (outs GPR:$Rt), (ins addrmode_imm12:$addr),
980 AddrMode_i12, LdFrm, iii, opc, "\t$Rt, $addr",
981 [(set GPR:$Rt, (opnode addrmode_imm12:$addr))]> {
984 let Inst{23} = addr{12}; // U (add = ('U' == 1))
985 let Inst{19-16} = addr{16-13}; // Rn
986 let Inst{15-12} = Rt;
987 let Inst{11-0} = addr{11-0}; // imm12
989 def rs : AI2ldst<0b011, 1, isByte, (outs GPR:$Rt), (ins ldst_so_reg:$shift),
990 AddrModeNone, LdFrm, iir, opc, "\t$Rt, $shift",
991 [(set GPR:$Rt, (opnode ldst_so_reg:$shift))]> {
994 let Inst{23} = shift{12}; // U (add = ('U' == 1))
995 let Inst{19-16} = shift{16-13}; // Rn
996 let Inst{15-12} = Rt;
997 let Inst{11-0} = shift{11-0};
1002 multiclass AI_str1<bit isByte, string opc, InstrItinClass iii,
1003 InstrItinClass iir, PatFrag opnode> {
1004 // Note: We use the complex addrmode_imm12 rather than just an input
1005 // GPR and a constrained immediate so that we can use this to match
1006 // frame index references and avoid matching constant pool references.
1007 def i12 : AI2ldst<0b010, 0, isByte, (outs),
1008 (ins GPR:$Rt, addrmode_imm12:$addr),
1009 AddrMode_i12, StFrm, iii, opc, "\t$Rt, $addr",
1010 [(opnode GPR:$Rt, addrmode_imm12:$addr)]> {
1013 let Inst{23} = addr{12}; // U (add = ('U' == 1))
1014 let Inst{19-16} = addr{16-13}; // Rn
1015 let Inst{15-12} = Rt;
1016 let Inst{11-0} = addr{11-0}; // imm12
1018 def rs : AI2ldst<0b011, 0, isByte, (outs), (ins GPR:$Rt, ldst_so_reg:$shift),
1019 AddrModeNone, StFrm, iir, opc, "\t$Rt, $shift",
1020 [(opnode GPR:$Rt, ldst_so_reg:$shift)]> {
1023 let Inst{23} = shift{12}; // U (add = ('U' == 1))
1024 let Inst{19-16} = shift{16-13}; // Rn
1025 let Inst{15-12} = Rt;
1026 let Inst{11-0} = shift{11-0};
1029 //===----------------------------------------------------------------------===//
1031 //===----------------------------------------------------------------------===//
1033 //===----------------------------------------------------------------------===//
1034 // Miscellaneous Instructions.
1037 /// CONSTPOOL_ENTRY - This instruction represents a floating constant pool in
1038 /// the function. The first operand is the ID# for this instruction, the second
1039 /// is the index into the MachineConstantPool that this is, the third is the
1040 /// size in bytes of this constant pool entry.
1041 let neverHasSideEffects = 1, isNotDuplicable = 1 in
1042 def CONSTPOOL_ENTRY :
1043 PseudoInst<(outs), (ins cpinst_operand:$instid, cpinst_operand:$cpidx,
1044 i32imm:$size), NoItinerary, []>;
1046 // FIXME: Marking these as hasSideEffects is necessary to prevent machine DCE
1047 // from removing one half of the matched pairs. That breaks PEI, which assumes
1048 // these will always be in pairs, and asserts if it finds otherwise. Better way?
1049 let Defs = [SP], Uses = [SP], hasSideEffects = 1 in {
1050 def ADJCALLSTACKUP :
1051 PseudoInst<(outs), (ins i32imm:$amt1, i32imm:$amt2, pred:$p), NoItinerary,
1052 [(ARMcallseq_end timm:$amt1, timm:$amt2)]>;
1054 def ADJCALLSTACKDOWN :
1055 PseudoInst<(outs), (ins i32imm:$amt, pred:$p), NoItinerary,
1056 [(ARMcallseq_start timm:$amt)]>;
1059 def NOP : AI<(outs), (ins), MiscFrm, NoItinerary, "nop", "",
1060 [/* For disassembly only; pattern left blank */]>,
1061 Requires<[IsARM, HasV6T2]> {
1062 let Inst{27-16} = 0b001100100000;
1063 let Inst{15-8} = 0b11110000;
1064 let Inst{7-0} = 0b00000000;
1067 def YIELD : AI<(outs), (ins), MiscFrm, NoItinerary, "yield", "",
1068 [/* For disassembly only; pattern left blank */]>,
1069 Requires<[IsARM, HasV6T2]> {
1070 let Inst{27-16} = 0b001100100000;
1071 let Inst{15-8} = 0b11110000;
1072 let Inst{7-0} = 0b00000001;
1075 def WFE : AI<(outs), (ins), MiscFrm, NoItinerary, "wfe", "",
1076 [/* For disassembly only; pattern left blank */]>,
1077 Requires<[IsARM, HasV6T2]> {
1078 let Inst{27-16} = 0b001100100000;
1079 let Inst{15-8} = 0b11110000;
1080 let Inst{7-0} = 0b00000010;
1083 def WFI : AI<(outs), (ins), MiscFrm, NoItinerary, "wfi", "",
1084 [/* For disassembly only; pattern left blank */]>,
1085 Requires<[IsARM, HasV6T2]> {
1086 let Inst{27-16} = 0b001100100000;
1087 let Inst{15-8} = 0b11110000;
1088 let Inst{7-0} = 0b00000011;
1091 def SEL : AI<(outs GPR:$dst), (ins GPR:$a, GPR:$b), DPFrm, NoItinerary, "sel",
1093 [/* For disassembly only; pattern left blank */]>,
1094 Requires<[IsARM, HasV6]> {
1099 let Inst{15-12} = Rd;
1100 let Inst{19-16} = Rn;
1101 let Inst{27-20} = 0b01101000;
1102 let Inst{7-4} = 0b1011;
1103 let Inst{11-8} = 0b1111;
1106 def SEV : AI<(outs), (ins), MiscFrm, NoItinerary, "sev", "",
1107 [/* For disassembly only; pattern left blank */]>,
1108 Requires<[IsARM, HasV6T2]> {
1109 let Inst{27-16} = 0b001100100000;
1110 let Inst{15-8} = 0b11110000;
1111 let Inst{7-0} = 0b00000100;
1114 // The i32imm operand $val can be used by a debugger to store more information
1115 // about the breakpoint.
1116 def BKPT : AI<(outs), (ins i32imm:$val), MiscFrm, NoItinerary, "bkpt", "\t$val",
1117 [/* For disassembly only; pattern left blank */]>,
1120 let Inst{3-0} = val{3-0};
1121 let Inst{19-8} = val{15-4};
1122 let Inst{27-20} = 0b00010010;
1123 let Inst{7-4} = 0b0111;
1126 // Change Processor State is a system instruction -- for disassembly and
1128 // FIXME: Since the asm parser has currently no clean way to handle optional
1129 // operands, create 3 versions of the same instruction. Once there's a clean
1130 // framework to represent optional operands, change this behavior.
1131 class CPS<dag iops, string asm_ops>
1132 : AXI<(outs), iops, MiscFrm, NoItinerary, !strconcat("cps", asm_ops),
1133 [/* For disassembly only; pattern left blank */]>, Requires<[IsARM]> {
1139 let Inst{31-28} = 0b1111;
1140 let Inst{27-20} = 0b00010000;
1141 let Inst{19-18} = imod;
1142 let Inst{17} = M; // Enabled if mode is set;
1144 let Inst{8-6} = iflags;
1146 let Inst{4-0} = mode;
1150 def CPS3p : CPS<(ins imod_op:$imod, iflags_op:$iflags, i32imm:$mode),
1151 "$imod\t$iflags, $mode">;
1152 let mode = 0, M = 0 in
1153 def CPS2p : CPS<(ins imod_op:$imod, iflags_op:$iflags), "$imod\t$iflags">;
1155 let imod = 0, iflags = 0, M = 1 in
1156 def CPS1p : CPS<(ins i32imm:$mode), "\t$mode">;
1158 // Preload signals the memory system of possible future data/instruction access.
1159 // These are for disassembly only.
1160 multiclass APreLoad<bits<1> read, bits<1> data, string opc> {
1162 def i12 : AXI<(outs), (ins addrmode_imm12:$addr), MiscFrm, IIC_Preload,
1163 !strconcat(opc, "\t$addr"),
1164 [(ARMPreload addrmode_imm12:$addr, (i32 read), (i32 data))]> {
1167 let Inst{31-26} = 0b111101;
1168 let Inst{25} = 0; // 0 for immediate form
1169 let Inst{24} = data;
1170 let Inst{23} = addr{12}; // U (add = ('U' == 1))
1171 let Inst{22} = read;
1172 let Inst{21-20} = 0b01;
1173 let Inst{19-16} = addr{16-13}; // Rn
1174 let Inst{15-12} = 0b1111;
1175 let Inst{11-0} = addr{11-0}; // imm12
1178 def rs : AXI<(outs), (ins ldst_so_reg:$shift), MiscFrm, IIC_Preload,
1179 !strconcat(opc, "\t$shift"),
1180 [(ARMPreload ldst_so_reg:$shift, (i32 read), (i32 data))]> {
1182 let Inst{31-26} = 0b111101;
1183 let Inst{25} = 1; // 1 for register form
1184 let Inst{24} = data;
1185 let Inst{23} = shift{12}; // U (add = ('U' == 1))
1186 let Inst{22} = read;
1187 let Inst{21-20} = 0b01;
1188 let Inst{19-16} = shift{16-13}; // Rn
1189 let Inst{15-12} = 0b1111;
1190 let Inst{11-0} = shift{11-0};
1194 defm PLD : APreLoad<1, 1, "pld">, Requires<[IsARM]>;
1195 defm PLDW : APreLoad<0, 1, "pldw">, Requires<[IsARM,HasV7,HasMP]>;
1196 defm PLI : APreLoad<1, 0, "pli">, Requires<[IsARM,HasV7]>;
1198 def SETEND : AXI<(outs),(ins setend_op:$end), MiscFrm, NoItinerary,
1200 [/* For disassembly only; pattern left blank */]>,
1203 let Inst{31-10} = 0b1111000100000001000000;
1208 def DBG : AI<(outs), (ins i32imm:$opt), MiscFrm, NoItinerary, "dbg", "\t$opt",
1209 [/* For disassembly only; pattern left blank */]>,
1210 Requires<[IsARM, HasV7]> {
1212 let Inst{27-4} = 0b001100100000111100001111;
1213 let Inst{3-0} = opt;
1216 // A5.4 Permanently UNDEFINED instructions.
1217 let isBarrier = 1, isTerminator = 1 in
1218 def TRAP : AXI<(outs), (ins), MiscFrm, NoItinerary,
1221 let Inst = 0xe7ffdefe;
1224 // Address computation and loads and stores in PIC mode.
1225 let isNotDuplicable = 1 in {
1226 def PICADD : ARMPseudoInst<(outs GPR:$dst), (ins GPR:$a, pclabel:$cp, pred:$p),
1227 Size4Bytes, IIC_iALUr,
1228 [(set GPR:$dst, (ARMpic_add GPR:$a, imm:$cp))]>;
1230 let AddedComplexity = 10 in {
1231 def PICLDR : ARMPseudoInst<(outs GPR:$dst), (ins addrmodepc:$addr, pred:$p),
1232 Size4Bytes, IIC_iLoad_r,
1233 [(set GPR:$dst, (load addrmodepc:$addr))]>;
1235 def PICLDRH : ARMPseudoInst<(outs GPR:$Rt), (ins addrmodepc:$addr, pred:$p),
1236 Size4Bytes, IIC_iLoad_bh_r,
1237 [(set GPR:$Rt, (zextloadi16 addrmodepc:$addr))]>;
1239 def PICLDRB : ARMPseudoInst<(outs GPR:$Rt), (ins addrmodepc:$addr, pred:$p),
1240 Size4Bytes, IIC_iLoad_bh_r,
1241 [(set GPR:$Rt, (zextloadi8 addrmodepc:$addr))]>;
1243 def PICLDRSH : ARMPseudoInst<(outs GPR:$Rt), (ins addrmodepc:$addr, pred:$p),
1244 Size4Bytes, IIC_iLoad_bh_r,
1245 [(set GPR:$Rt, (sextloadi16 addrmodepc:$addr))]>;
1247 def PICLDRSB : ARMPseudoInst<(outs GPR:$Rt), (ins addrmodepc:$addr, pred:$p),
1248 Size4Bytes, IIC_iLoad_bh_r,
1249 [(set GPR:$Rt, (sextloadi8 addrmodepc:$addr))]>;
1251 let AddedComplexity = 10 in {
1252 def PICSTR : ARMPseudoInst<(outs), (ins GPR:$src, addrmodepc:$addr, pred:$p),
1253 Size4Bytes, IIC_iStore_r, [(store GPR:$src, addrmodepc:$addr)]>;
1255 def PICSTRH : ARMPseudoInst<(outs), (ins GPR:$src, addrmodepc:$addr, pred:$p),
1256 Size4Bytes, IIC_iStore_bh_r, [(truncstorei16 GPR:$src,
1257 addrmodepc:$addr)]>;
1259 def PICSTRB : ARMPseudoInst<(outs), (ins GPR:$src, addrmodepc:$addr, pred:$p),
1260 Size4Bytes, IIC_iStore_bh_r, [(truncstorei8 GPR:$src, addrmodepc:$addr)]>;
1262 } // isNotDuplicable = 1
1265 // LEApcrel - Load a pc-relative address into a register without offending the
1267 let neverHasSideEffects = 1, isReMaterializable = 1 in
1268 // The 'adr' mnemonic encodes differently if the label is before or after
1269 // the instruction. The {24-21} opcode bits are set by the fixup, as we don't
1270 // know until then which form of the instruction will be used.
1271 def ADR : AI1<{0,?,?,0}, (outs GPR:$Rd), (ins adrlabel:$label),
1272 MiscFrm, IIC_iALUi, "adr", "\t$Rd, #$label", []> {
1275 let Inst{27-25} = 0b001;
1277 let Inst{19-16} = 0b1111;
1278 let Inst{15-12} = Rd;
1279 let Inst{11-0} = label;
1281 def LEApcrel : ARMPseudoInst<(outs GPR:$Rd), (ins i32imm:$label, pred:$p),
1282 Size4Bytes, IIC_iALUi, []>;
1284 def LEApcrelJT : ARMPseudoInst<(outs GPR:$Rd),
1285 (ins i32imm:$label, nohash_imm:$id, pred:$p),
1286 Size4Bytes, IIC_iALUi, []>;
1288 //===----------------------------------------------------------------------===//
1289 // Control Flow Instructions.
1292 let isReturn = 1, isTerminator = 1, isBarrier = 1 in {
1294 def BX_RET : AI<(outs), (ins), BrMiscFrm, IIC_Br,
1295 "bx", "\tlr", [(ARMretflag)]>,
1296 Requires<[IsARM, HasV4T]> {
1297 let Inst{27-0} = 0b0001001011111111111100011110;
1301 def MOVPCLR : AI<(outs), (ins), BrMiscFrm, IIC_Br,
1302 "mov", "\tpc, lr", [(ARMretflag)]>,
1303 Requires<[IsARM, NoV4T]> {
1304 let Inst{27-0} = 0b0001101000001111000000001110;
1308 // Indirect branches
1309 let isBranch = 1, isTerminator = 1, isBarrier = 1, isIndirectBranch = 1 in {
1311 def BX : AXI<(outs), (ins GPR:$dst), BrMiscFrm, IIC_Br, "bx\t$dst",
1312 [(brind GPR:$dst)]>,
1313 Requires<[IsARM, HasV4T]> {
1315 let Inst{31-4} = 0b1110000100101111111111110001;
1316 let Inst{3-0} = dst;
1320 // FIXME: We would really like to define this as a vanilla ARMPat like:
1321 // ARMPat<(brind GPR:$dst), (MOVr PC, GPR:$dst)>
1322 // With that, however, we can't set isBranch, isTerminator, etc..
1323 def MOVPCRX : ARMPseudoInst<(outs), (ins GPR:$dst),
1324 Size4Bytes, IIC_Br, [(brind GPR:$dst)]>,
1325 Requires<[IsARM, NoV4T]>;
1328 // All calls clobber the non-callee saved registers. SP is marked as
1329 // a use to prevent stack-pointer assignments that appear immediately
1330 // before calls from potentially appearing dead.
1332 // On non-Darwin platforms R9 is callee-saved.
1333 // FIXME: Do we really need a non-predicated version? If so, it should
1334 // at least be a pseudo instruction expanding to the predicated version
1335 // at MC lowering time.
1336 Defs = [R0, R1, R2, R3, R12, LR,
1337 D0, D1, D2, D3, D4, D5, D6, D7,
1338 D16, D17, D18, D19, D20, D21, D22, D23,
1339 D24, D25, D26, D27, D28, D29, D30, D31, CPSR, FPSCR],
1341 def BL : ABXI<0b1011, (outs), (ins bl_target:$func, variable_ops),
1342 IIC_Br, "bl\t$func",
1343 [(ARMcall tglobaladdr:$func)]>,
1344 Requires<[IsARM, IsNotDarwin]> {
1345 let Inst{31-28} = 0b1110;
1347 let Inst{23-0} = func;
1350 def BL_pred : ABI<0b1011, (outs), (ins bl_target:$func, variable_ops),
1351 IIC_Br, "bl", "\t$func",
1352 [(ARMcall_pred tglobaladdr:$func)]>,
1353 Requires<[IsARM, IsNotDarwin]> {
1355 let Inst{23-0} = func;
1359 def BLX : AXI<(outs), (ins GPR:$func, variable_ops), BrMiscFrm,
1360 IIC_Br, "blx\t$func",
1361 [(ARMcall GPR:$func)]>,
1362 Requires<[IsARM, HasV5T, IsNotDarwin]> {
1364 let Inst{31-4} = 0b1110000100101111111111110011;
1365 let Inst{3-0} = func;
1368 def BLX_pred : AI<(outs), (ins GPR:$func, variable_ops), BrMiscFrm,
1369 IIC_Br, "blx", "\t$func",
1370 [(ARMcall_pred GPR:$func)]>,
1371 Requires<[IsARM, HasV5T, IsNotDarwin]> {
1373 let Inst{27-4} = 0b000100101111111111110011;
1374 let Inst{3-0} = func;
1378 // Note: Restrict $func to the tGPR regclass to prevent it being in LR.
1379 def BX_CALL : ARMPseudoInst<(outs), (ins tGPR:$func, variable_ops),
1380 Size8Bytes, IIC_Br, [(ARMcall_nolink tGPR:$func)]>,
1381 Requires<[IsARM, HasV4T, IsNotDarwin]>;
1384 def BMOVPCRX_CALL : ARMPseudoInst<(outs), (ins tGPR:$func, variable_ops),
1385 Size8Bytes, IIC_Br, [(ARMcall_nolink tGPR:$func)]>,
1386 Requires<[IsARM, NoV4T, IsNotDarwin]>;
1390 // On Darwin R9 is call-clobbered.
1391 // R7 is marked as a use to prevent frame-pointer assignments from being
1392 // moved above / below calls.
1393 Defs = [R0, R1, R2, R3, R9, R12, LR,
1394 D0, D1, D2, D3, D4, D5, D6, D7,
1395 D16, D17, D18, D19, D20, D21, D22, D23,
1396 D24, D25, D26, D27, D28, D29, D30, D31, CPSR, FPSCR],
1397 Uses = [R7, SP] in {
1398 def BLr9 : ARMPseudoInst<(outs), (ins bltarget:$func, variable_ops),
1400 [(ARMcall tglobaladdr:$func)]>, Requires<[IsARM, IsDarwin]>;
1402 def BLr9_pred : ARMPseudoInst<(outs),
1403 (ins bltarget:$func, pred:$p, variable_ops),
1405 [(ARMcall_pred tglobaladdr:$func)]>,
1406 Requires<[IsARM, IsDarwin]>;
1409 def BLXr9 : ARMPseudoInst<(outs), (ins GPR:$func, variable_ops),
1411 [(ARMcall GPR:$func)]>, Requires<[IsARM, HasV5T, IsDarwin]>;
1413 def BLXr9_pred: ARMPseudoInst<(outs), (ins GPR:$func, pred:$p, variable_ops),
1415 [(ARMcall_pred GPR:$func)]>,
1416 Requires<[IsARM, HasV5T, IsDarwin]>;
1419 // Note: Restrict $func to the tGPR regclass to prevent it being in LR.
1420 def BXr9_CALL : ARMPseudoInst<(outs), (ins tGPR:$func, variable_ops),
1421 Size8Bytes, IIC_Br, [(ARMcall_nolink tGPR:$func)]>,
1422 Requires<[IsARM, HasV4T, IsDarwin]>;
1425 def BMOVPCRXr9_CALL : ARMPseudoInst<(outs), (ins tGPR:$func, variable_ops),
1426 Size8Bytes, IIC_Br, [(ARMcall_nolink tGPR:$func)]>,
1427 Requires<[IsARM, NoV4T, IsDarwin]>;
1432 // FIXME: The Thumb versions of these should live in ARMInstrThumb.td
1433 let isCall = 1, isTerminator = 1, isReturn = 1, isBarrier = 1 in {
1435 let Defs = [R0, R1, R2, R3, R9, R12,
1436 D0, D1, D2, D3, D4, D5, D6, D7,
1437 D16, D17, D18, D19, D20, D21, D22, D23, D24, D25, D26,
1438 D27, D28, D29, D30, D31, PC],
1440 def TCRETURNdi : PseudoInst<(outs), (ins i32imm:$dst, variable_ops),
1441 IIC_Br, []>, Requires<[IsDarwin]>;
1443 def TCRETURNri : PseudoInst<(outs), (ins tcGPR:$dst, variable_ops),
1444 IIC_Br, []>, Requires<[IsDarwin]>;
1446 def TAILJMPd : ARMPseudoInst<(outs), (ins brtarget:$dst, variable_ops),
1448 []>, Requires<[IsARM, IsDarwin]>;
1450 def tTAILJMPd: tPseudoInst<(outs), (ins brtarget:$dst, variable_ops),
1452 []>, Requires<[IsThumb, IsDarwin]>;
1454 def TAILJMPr : ARMPseudoInst<(outs), (ins tcGPR:$dst, variable_ops),
1456 []>, Requires<[IsARM, IsDarwin]>;
1458 def tTAILJMPr : tPseudoInst<(outs), (ins tcGPR:$dst, variable_ops),
1460 []>, Requires<[IsThumb, IsDarwin]>;
1463 // Non-Darwin versions (the difference is R9).
1464 let Defs = [R0, R1, R2, R3, R12,
1465 D0, D1, D2, D3, D4, D5, D6, D7,
1466 D16, D17, D18, D19, D20, D21, D22, D23, D24, D25, D26,
1467 D27, D28, D29, D30, D31, PC],
1469 def TCRETURNdiND : PseudoInst<(outs), (ins i32imm:$dst, variable_ops),
1470 IIC_Br, []>, Requires<[IsNotDarwin]>;
1472 def TCRETURNriND : PseudoInst<(outs), (ins tcGPR:$dst, variable_ops),
1473 IIC_Br, []>, Requires<[IsNotDarwin]>;
1475 def TAILJMPdND : ARMPseudoInst<(outs), (ins brtarget:$dst, variable_ops),
1477 []>, Requires<[IsARM, IsNotDarwin]>;
1479 def tTAILJMPdND : tPseudoInst<(outs), (ins brtarget:$dst, variable_ops),
1481 []>, Requires<[IsThumb, IsNotDarwin]>;
1483 def TAILJMPrND : ARMPseudoInst<(outs), (ins tcGPR:$dst, variable_ops),
1485 []>, Requires<[IsARM, IsNotDarwin]>;
1486 def tTAILJMPrND : tPseudoInst<(outs), (ins tcGPR:$dst, variable_ops),
1488 []>, Requires<[IsThumb, IsNotDarwin]>;
1492 let isBranch = 1, isTerminator = 1 in {
1493 // B is "predicable" since it's just a Bcc with an 'always' condition.
1494 let isBarrier = 1 in {
1495 let isPredicable = 1 in
1496 // FIXME: We shouldn't need this pseudo at all. Just using Bcc directly
1497 // should be sufficient.
1498 def B : ARMPseudoInst<(outs), (ins brtarget:$target), Size4Bytes, IIC_Br,
1501 let isNotDuplicable = 1, isIndirectBranch = 1 in {
1502 def BR_JTr : ARMPseudoInst<(outs),
1503 (ins GPR:$target, i32imm:$jt, i32imm:$id),
1504 SizeSpecial, IIC_Br,
1505 [(ARMbrjt GPR:$target, tjumptable:$jt, imm:$id)]>;
1506 // FIXME: This shouldn't use the generic "addrmode2," but rather be split
1507 // into i12 and rs suffixed versions.
1508 def BR_JTm : ARMPseudoInst<(outs),
1509 (ins addrmode2:$target, i32imm:$jt, i32imm:$id),
1510 SizeSpecial, IIC_Br,
1511 [(ARMbrjt (i32 (load addrmode2:$target)), tjumptable:$jt,
1513 def BR_JTadd : ARMPseudoInst<(outs),
1514 (ins GPR:$target, GPR:$idx, i32imm:$jt, i32imm:$id),
1515 SizeSpecial, IIC_Br,
1516 [(ARMbrjt (add GPR:$target, GPR:$idx), tjumptable:$jt,
1518 } // isNotDuplicable = 1, isIndirectBranch = 1
1521 // FIXME: should be able to write a pattern for ARMBrcond, but can't use
1522 // a two-value operand where a dag node expects two operands. :(
1523 def Bcc : ABI<0b1010, (outs), (ins br_target:$target),
1524 IIC_Br, "b", "\t$target",
1525 [/*(ARMbrcond bb:$target, imm:$cc, CCR:$ccr)*/]> {
1527 let Inst{23-0} = target;
1531 // BLX (immediate) -- for disassembly only
1532 def BLXi : AXI<(outs), (ins br_target:$target), BrMiscFrm, NoItinerary,
1533 "blx\t$target", [/* pattern left blank */]>,
1534 Requires<[IsARM, HasV5T]> {
1535 let Inst{31-25} = 0b1111101;
1537 let Inst{23-0} = target{24-1};
1538 let Inst{24} = target{0};
1541 // Branch and Exchange Jazelle -- for disassembly only
1542 def BXJ : ABI<0b0001, (outs), (ins GPR:$func), NoItinerary, "bxj", "\t$func",
1543 [/* For disassembly only; pattern left blank */]> {
1544 let Inst{23-20} = 0b0010;
1545 //let Inst{19-8} = 0xfff;
1546 let Inst{7-4} = 0b0010;
1549 // Secure Monitor Call is a system instruction -- for disassembly only
1550 def SMC : ABI<0b0001, (outs), (ins i32imm:$opt), NoItinerary, "smc", "\t$opt",
1551 [/* For disassembly only; pattern left blank */]> {
1553 let Inst{23-4} = 0b01100000000000000111;
1554 let Inst{3-0} = opt;
1557 // Supervisor Call (Software Interrupt) -- for disassembly only
1558 let isCall = 1, Uses = [SP] in {
1559 def SVC : ABI<0b1111, (outs), (ins i32imm:$svc), IIC_Br, "svc", "\t$svc",
1560 [/* For disassembly only; pattern left blank */]> {
1562 let Inst{23-0} = svc;
1565 def : MnemonicAlias<"swi", "svc">;
1567 // Store Return State is a system instruction -- for disassembly only
1568 let isCodeGenOnly = 1 in { // FIXME: This should not use submode!
1569 def SRSW : ABXI<{1,0,0,?}, (outs), (ins ldstm_mode:$amode, i32imm:$mode),
1570 NoItinerary, "srs${amode}\tsp!, $mode",
1571 [/* For disassembly only; pattern left blank */]> {
1572 let Inst{31-28} = 0b1111;
1573 let Inst{22-20} = 0b110; // W = 1
1576 def SRS : ABXI<{1,0,0,?}, (outs), (ins ldstm_mode:$amode, i32imm:$mode),
1577 NoItinerary, "srs${amode}\tsp, $mode",
1578 [/* For disassembly only; pattern left blank */]> {
1579 let Inst{31-28} = 0b1111;
1580 let Inst{22-20} = 0b100; // W = 0
1583 // Return From Exception is a system instruction -- for disassembly only
1584 def RFEW : ABXI<{1,0,0,?}, (outs), (ins ldstm_mode:$amode, GPR:$base),
1585 NoItinerary, "rfe${amode}\t$base!",
1586 [/* For disassembly only; pattern left blank */]> {
1587 let Inst{31-28} = 0b1111;
1588 let Inst{22-20} = 0b011; // W = 1
1591 def RFE : ABXI<{1,0,0,?}, (outs), (ins ldstm_mode:$amode, GPR:$base),
1592 NoItinerary, "rfe${amode}\t$base",
1593 [/* For disassembly only; pattern left blank */]> {
1594 let Inst{31-28} = 0b1111;
1595 let Inst{22-20} = 0b001; // W = 0
1597 } // isCodeGenOnly = 1
1599 //===----------------------------------------------------------------------===//
1600 // Load / store Instructions.
1606 defm LDR : AI_ldr1<0, "ldr", IIC_iLoad_r, IIC_iLoad_si,
1607 UnOpFrag<(load node:$Src)>>;
1608 defm LDRB : AI_ldr1<1, "ldrb", IIC_iLoad_bh_r, IIC_iLoad_bh_si,
1609 UnOpFrag<(zextloadi8 node:$Src)>>;
1610 defm STR : AI_str1<0, "str", IIC_iStore_r, IIC_iStore_si,
1611 BinOpFrag<(store node:$LHS, node:$RHS)>>;
1612 defm STRB : AI_str1<1, "strb", IIC_iStore_bh_r, IIC_iStore_bh_si,
1613 BinOpFrag<(truncstorei8 node:$LHS, node:$RHS)>>;
1615 // Special LDR for loads from non-pc-relative constpools.
1616 let canFoldAsLoad = 1, mayLoad = 1, neverHasSideEffects = 1,
1617 isReMaterializable = 1 in
1618 def LDRcp : AI2ldst<0b010, 1, 0, (outs GPR:$Rt), (ins addrmode_imm12:$addr),
1619 AddrMode_i12, LdFrm, IIC_iLoad_r, "ldr", "\t$Rt, $addr",
1623 let Inst{23} = addr{12}; // U (add = ('U' == 1))
1624 let Inst{19-16} = 0b1111;
1625 let Inst{15-12} = Rt;
1626 let Inst{11-0} = addr{11-0}; // imm12
1629 // Loads with zero extension
1630 def LDRH : AI3ld<0b1011, 1, (outs GPR:$Rt), (ins addrmode3:$addr), LdMiscFrm,
1631 IIC_iLoad_bh_r, "ldrh", "\t$Rt, $addr",
1632 [(set GPR:$Rt, (zextloadi16 addrmode3:$addr))]>;
1634 // Loads with sign extension
1635 def LDRSH : AI3ld<0b1111, 1, (outs GPR:$Rt), (ins addrmode3:$addr), LdMiscFrm,
1636 IIC_iLoad_bh_r, "ldrsh", "\t$Rt, $addr",
1637 [(set GPR:$Rt, (sextloadi16 addrmode3:$addr))]>;
1639 def LDRSB : AI3ld<0b1101, 1, (outs GPR:$Rt), (ins addrmode3:$addr), LdMiscFrm,
1640 IIC_iLoad_bh_r, "ldrsb", "\t$Rt, $addr",
1641 [(set GPR:$Rt, (sextloadi8 addrmode3:$addr))]>;
1643 let mayLoad = 1, neverHasSideEffects = 1, hasExtraDefRegAllocReq = 1,
1644 isCodeGenOnly = 1 in { // $dst2 doesn't exist in asmstring?
1645 // FIXME: $dst2 isn't in the asm string as it's implied by $Rd (dst2 = Rd+1)
1646 // how to represent that such that tblgen is happy and we don't
1647 // mark this codegen only?
1649 def LDRD : AI3ld<0b1101, 0, (outs GPR:$Rd, GPR:$dst2),
1650 (ins addrmode3:$addr), LdMiscFrm,
1651 IIC_iLoad_d_r, "ldrd", "\t$Rd, $addr",
1652 []>, Requires<[IsARM, HasV5TE]>;
1656 multiclass AI2_ldridx<bit isByte, string opc, InstrItinClass itin> {
1657 def _PRE : AI2ldstidx<1, isByte, 1, (outs GPR:$Rt, GPR:$Rn_wb),
1658 (ins addrmode2:$addr), IndexModePre, LdFrm, itin,
1659 opc, "\t$Rt, $addr!", "$addr.base = $Rn_wb", []> {
1661 // {13} 1 == Rm, 0 == imm12
1665 let Inst{25} = addr{13};
1666 let Inst{23} = addr{12};
1667 let Inst{19-16} = addr{17-14};
1668 let Inst{11-0} = addr{11-0};
1670 def _POST : AI2ldstidx<1, isByte, 0, (outs GPR:$Rt, GPR:$Rn_wb),
1671 (ins GPR:$Rn, am2offset:$offset),
1672 IndexModePost, LdFrm, itin,
1673 opc, "\t$Rt, [$Rn], $offset", "$Rn = $Rn_wb", []> {
1674 // {13} 1 == Rm, 0 == imm12
1679 let Inst{25} = offset{13};
1680 let Inst{23} = offset{12};
1681 let Inst{19-16} = Rn;
1682 let Inst{11-0} = offset{11-0};
1686 let mayLoad = 1, neverHasSideEffects = 1 in {
1687 defm LDR : AI2_ldridx<0, "ldr", IIC_iLoad_ru>;
1688 defm LDRB : AI2_ldridx<1, "ldrb", IIC_iLoad_bh_ru>;
1691 multiclass AI3_ldridx<bits<4> op, bit op20, string opc, InstrItinClass itin> {
1692 def _PRE : AI3ldstidx<op, op20, 1, 1, (outs GPR:$Rt, GPR:$Rn_wb),
1693 (ins addrmode3:$addr), IndexModePre,
1695 opc, "\t$Rt, $addr!", "$addr.base = $Rn_wb", []> {
1697 let Inst{23} = addr{8}; // U bit
1698 let Inst{22} = addr{13}; // 1 == imm8, 0 == Rm
1699 let Inst{19-16} = addr{12-9}; // Rn
1700 let Inst{11-8} = addr{7-4}; // imm7_4/zero
1701 let Inst{3-0} = addr{3-0}; // imm3_0/Rm
1703 def _POST : AI3ldstidx<op, op20, 1, 0, (outs GPR:$Rt, GPR:$Rn_wb),
1704 (ins GPR:$Rn, am3offset:$offset), IndexModePost,
1706 opc, "\t$Rt, [$Rn], $offset", "$Rn = $Rn_wb", []> {
1709 let Inst{23} = offset{8}; // U bit
1710 let Inst{22} = offset{9}; // 1 == imm8, 0 == Rm
1711 let Inst{19-16} = Rn;
1712 let Inst{11-8} = offset{7-4}; // imm7_4/zero
1713 let Inst{3-0} = offset{3-0}; // imm3_0/Rm
1717 let mayLoad = 1, neverHasSideEffects = 1 in {
1718 defm LDRH : AI3_ldridx<0b1011, 1, "ldrh", IIC_iLoad_bh_ru>;
1719 defm LDRSH : AI3_ldridx<0b1111, 1, "ldrsh", IIC_iLoad_bh_ru>;
1720 defm LDRSB : AI3_ldridx<0b1101, 1, "ldrsb", IIC_iLoad_bh_ru>;
1721 let hasExtraDefRegAllocReq = 1, isCodeGenOnly = 1 in
1722 defm LDRD : AI3_ldridx<0b1101, 0, "ldrd", IIC_iLoad_d_ru>;
1723 } // mayLoad = 1, neverHasSideEffects = 1
1725 // LDRT, LDRBT, LDRSBT, LDRHT, LDRSHT are for disassembly only.
1726 let mayLoad = 1, neverHasSideEffects = 1 in {
1727 def LDRT : AI2ldstidx<1, 0, 0, (outs GPR:$dst, GPR:$base_wb),
1728 (ins GPR:$base, am2offset:$offset), IndexModePost,
1729 LdFrm, IIC_iLoad_ru,
1730 "ldrt", "\t$dst, [$base], $offset", "$base = $base_wb", []> {
1731 let Inst{21} = 1; // overwrite
1733 def LDRBT : AI2ldstidx<1, 1, 0, (outs GPR:$dst, GPR:$base_wb),
1734 (ins GPR:$base, am2offset:$offset), IndexModePost,
1735 LdFrm, IIC_iLoad_bh_ru,
1736 "ldrbt", "\t$dst, [$base], $offset", "$base = $base_wb", []> {
1737 let Inst{21} = 1; // overwrite
1739 def LDRSBT : AI3ldstidx<0b1101, 1, 1, 0, (outs GPR:$dst, GPR:$base_wb),
1740 (ins GPR:$base, am3offset:$offset), IndexModePost,
1741 LdMiscFrm, IIC_iLoad_bh_ru,
1742 "ldrsbt", "\t$dst, [$base], $offset", "$base = $base_wb", []> {
1743 let Inst{21} = 1; // overwrite
1745 def LDRHT : AI3ldstidx<0b1011, 1, 1, 0, (outs GPR:$dst, GPR:$base_wb),
1746 (ins GPR:$base, am3offset:$offset), IndexModePost,
1747 LdMiscFrm, IIC_iLoad_bh_ru,
1748 "ldrht", "\t$dst, [$base], $offset", "$base = $base_wb", []> {
1749 let Inst{21} = 1; // overwrite
1751 def LDRSHT : AI3ldstidx<0b1111, 1, 1, 0, (outs GPR:$dst, GPR:$base_wb),
1752 (ins GPR:$base, am3offset:$offset), IndexModePost,
1753 LdMiscFrm, IIC_iLoad_bh_ru,
1754 "ldrsht", "\t$dst, [$base], $offset", "$base = $base_wb", []> {
1755 let Inst{21} = 1; // overwrite
1761 // Stores with truncate
1762 def STRH : AI3str<0b1011, (outs), (ins GPR:$Rt, addrmode3:$addr), StMiscFrm,
1763 IIC_iStore_bh_r, "strh", "\t$Rt, $addr",
1764 [(truncstorei16 GPR:$Rt, addrmode3:$addr)]>;
1767 let mayStore = 1, neverHasSideEffects = 1, hasExtraSrcRegAllocReq = 1,
1768 isCodeGenOnly = 1 in // $src2 doesn't exist in asm string
1769 def STRD : AI3str<0b1111, (outs), (ins GPR:$src1, GPR:$src2, addrmode3:$addr),
1770 StMiscFrm, IIC_iStore_d_r,
1771 "strd", "\t$src1, $addr", []>, Requires<[IsARM, HasV5TE]>;
1774 def STR_PRE : AI2stridx<0, 1, (outs GPR:$Rn_wb),
1775 (ins GPR:$Rt, GPR:$Rn, am2offset:$offset),
1776 IndexModePre, StFrm, IIC_iStore_ru,
1777 "str", "\t$Rt, [$Rn, $offset]!", "$Rn = $Rn_wb",
1779 (pre_store GPR:$Rt, GPR:$Rn, am2offset:$offset))]>;
1781 def STR_POST : AI2stridx<0, 0, (outs GPR:$Rn_wb),
1782 (ins GPR:$Rt, GPR:$Rn, am2offset:$offset),
1783 IndexModePost, StFrm, IIC_iStore_ru,
1784 "str", "\t$Rt, [$Rn], $offset", "$Rn = $Rn_wb",
1786 (post_store GPR:$Rt, GPR:$Rn, am2offset:$offset))]>;
1788 def STRB_PRE : AI2stridx<1, 1, (outs GPR:$Rn_wb),
1789 (ins GPR:$Rt, GPR:$Rn, am2offset:$offset),
1790 IndexModePre, StFrm, IIC_iStore_bh_ru,
1791 "strb", "\t$Rt, [$Rn, $offset]!", "$Rn = $Rn_wb",
1792 [(set GPR:$Rn_wb, (pre_truncsti8 GPR:$Rt,
1793 GPR:$Rn, am2offset:$offset))]>;
1794 def STRB_POST: AI2stridx<1, 0, (outs GPR:$Rn_wb),
1795 (ins GPR:$Rt, GPR:$Rn, am2offset:$offset),
1796 IndexModePost, StFrm, IIC_iStore_bh_ru,
1797 "strb", "\t$Rt, [$Rn], $offset", "$Rn = $Rn_wb",
1798 [(set GPR:$Rn_wb, (post_truncsti8 GPR:$Rt,
1799 GPR:$Rn, am2offset:$offset))]>;
1801 def STRH_PRE : AI3stridx<0b1011, 0, 1, (outs GPR:$Rn_wb),
1802 (ins GPR:$Rt, GPR:$Rn, am3offset:$offset),
1803 IndexModePre, StMiscFrm, IIC_iStore_ru,
1804 "strh", "\t$Rt, [$Rn, $offset]!", "$Rn = $Rn_wb",
1806 (pre_truncsti16 GPR:$Rt, GPR:$Rn, am3offset:$offset))]>;
1808 def STRH_POST: AI3stridx<0b1011, 0, 0, (outs GPR:$Rn_wb),
1809 (ins GPR:$Rt, GPR:$Rn, am3offset:$offset),
1810 IndexModePost, StMiscFrm, IIC_iStore_bh_ru,
1811 "strh", "\t$Rt, [$Rn], $offset", "$Rn = $Rn_wb",
1812 [(set GPR:$Rn_wb, (post_truncsti16 GPR:$Rt,
1813 GPR:$Rn, am3offset:$offset))]>;
1815 // For disassembly only
1816 def STRD_PRE : AI3stdpr<(outs GPR:$base_wb),
1817 (ins GPR:$src1, GPR:$src2, GPR:$base, am3offset:$offset),
1818 StMiscFrm, IIC_iStore_d_ru,
1819 "strd", "\t$src1, $src2, [$base, $offset]!",
1820 "$base = $base_wb", []>;
1822 // For disassembly only
1823 def STRD_POST: AI3stdpo<(outs GPR:$base_wb),
1824 (ins GPR:$src1, GPR:$src2, GPR:$base, am3offset:$offset),
1825 StMiscFrm, IIC_iStore_d_ru,
1826 "strd", "\t$src1, $src2, [$base], $offset",
1827 "$base = $base_wb", []>;
1829 // STRT, STRBT, and STRHT are for disassembly only.
1831 def STRT : AI2stridx<0, 0, (outs GPR:$Rn_wb),
1832 (ins GPR:$Rt, GPR:$Rn,am2offset:$offset),
1833 IndexModePost, StFrm, IIC_iStore_ru,
1834 "strt", "\t$Rt, [$Rn], $offset", "$Rn = $Rn_wb",
1835 [/* For disassembly only; pattern left blank */]> {
1836 let Inst{21} = 1; // overwrite
1839 def STRBT : AI2stridx<1, 0, (outs GPR:$Rn_wb),
1840 (ins GPR:$Rt, GPR:$Rn, am2offset:$offset),
1841 IndexModePost, StFrm, IIC_iStore_bh_ru,
1842 "strbt", "\t$Rt, [$Rn], $offset", "$Rn = $Rn_wb",
1843 [/* For disassembly only; pattern left blank */]> {
1844 let Inst{21} = 1; // overwrite
1847 def STRHT: AI3sthpo<(outs GPR:$base_wb),
1848 (ins GPR:$src, GPR:$base,am3offset:$offset),
1849 StMiscFrm, IIC_iStore_bh_ru,
1850 "strht", "\t$src, [$base], $offset", "$base = $base_wb",
1851 [/* For disassembly only; pattern left blank */]> {
1852 let Inst{21} = 1; // overwrite
1855 //===----------------------------------------------------------------------===//
1856 // Load / store multiple Instructions.
1859 multiclass arm_ldst_mult<string asm, bit L_bit, Format f,
1860 InstrItinClass itin, InstrItinClass itin_upd> {
1862 AXI4<(outs), (ins GPR:$Rn, pred:$p, reglist:$regs, variable_ops),
1863 IndexModeNone, f, itin,
1864 !strconcat(asm, "ia${p}\t$Rn, $regs"), "", []> {
1865 let Inst{24-23} = 0b01; // Increment After
1866 let Inst{21} = 0; // No writeback
1867 let Inst{20} = L_bit;
1870 AXI4<(outs GPR:$wb), (ins GPR:$Rn, pred:$p, reglist:$regs, variable_ops),
1871 IndexModeUpd, f, itin_upd,
1872 !strconcat(asm, "ia${p}\t$Rn!, $regs"), "$Rn = $wb", []> {
1873 let Inst{24-23} = 0b01; // Increment After
1874 let Inst{21} = 1; // Writeback
1875 let Inst{20} = L_bit;
1878 AXI4<(outs), (ins GPR:$Rn, pred:$p, reglist:$regs, variable_ops),
1879 IndexModeNone, f, itin,
1880 !strconcat(asm, "da${p}\t$Rn, $regs"), "", []> {
1881 let Inst{24-23} = 0b00; // Decrement After
1882 let Inst{21} = 0; // No writeback
1883 let Inst{20} = L_bit;
1886 AXI4<(outs GPR:$wb), (ins GPR:$Rn, pred:$p, reglist:$regs, variable_ops),
1887 IndexModeUpd, f, itin_upd,
1888 !strconcat(asm, "da${p}\t$Rn!, $regs"), "$Rn = $wb", []> {
1889 let Inst{24-23} = 0b00; // Decrement After
1890 let Inst{21} = 1; // Writeback
1891 let Inst{20} = L_bit;
1894 AXI4<(outs), (ins GPR:$Rn, pred:$p, reglist:$regs, variable_ops),
1895 IndexModeNone, f, itin,
1896 !strconcat(asm, "db${p}\t$Rn, $regs"), "", []> {
1897 let Inst{24-23} = 0b10; // Decrement Before
1898 let Inst{21} = 0; // No writeback
1899 let Inst{20} = L_bit;
1902 AXI4<(outs GPR:$wb), (ins GPR:$Rn, pred:$p, reglist:$regs, variable_ops),
1903 IndexModeUpd, f, itin_upd,
1904 !strconcat(asm, "db${p}\t$Rn!, $regs"), "$Rn = $wb", []> {
1905 let Inst{24-23} = 0b10; // Decrement Before
1906 let Inst{21} = 1; // Writeback
1907 let Inst{20} = L_bit;
1910 AXI4<(outs), (ins GPR:$Rn, pred:$p, reglist:$regs, variable_ops),
1911 IndexModeNone, f, itin,
1912 !strconcat(asm, "ib${p}\t$Rn, $regs"), "", []> {
1913 let Inst{24-23} = 0b11; // Increment Before
1914 let Inst{21} = 0; // No writeback
1915 let Inst{20} = L_bit;
1918 AXI4<(outs GPR:$wb), (ins GPR:$Rn, pred:$p, reglist:$regs, variable_ops),
1919 IndexModeUpd, f, itin_upd,
1920 !strconcat(asm, "ib${p}\t$Rn!, $regs"), "$Rn = $wb", []> {
1921 let Inst{24-23} = 0b11; // Increment Before
1922 let Inst{21} = 1; // Writeback
1923 let Inst{20} = L_bit;
1927 let neverHasSideEffects = 1 in {
1929 let mayLoad = 1, hasExtraDefRegAllocReq = 1 in
1930 defm LDM : arm_ldst_mult<"ldm", 1, LdStMulFrm, IIC_iLoad_m, IIC_iLoad_mu>;
1932 let mayStore = 1, hasExtraSrcRegAllocReq = 1 in
1933 defm STM : arm_ldst_mult<"stm", 0, LdStMulFrm, IIC_iStore_m, IIC_iStore_mu>;
1935 } // neverHasSideEffects
1937 // Load / Store Multiple Mnemonic Aliases
1938 def : MnemonicAlias<"ldm", "ldmia">;
1939 def : MnemonicAlias<"stm", "stmia">;
1941 // FIXME: remove when we have a way to marking a MI with these properties.
1942 // FIXME: Should pc be an implicit operand like PICADD, etc?
1943 let isReturn = 1, isTerminator = 1, isBarrier = 1, mayLoad = 1,
1944 hasExtraDefRegAllocReq = 1, isCodeGenOnly = 1 in
1945 def LDMIA_RET : ARMPseudoInst<(outs GPR:$wb), (ins GPR:$Rn, pred:$p,
1946 reglist:$regs, variable_ops),
1947 Size4Bytes, IIC_iLoad_mBr, []>,
1948 RegConstraint<"$Rn = $wb">;
1950 //===----------------------------------------------------------------------===//
1951 // Move Instructions.
1954 let neverHasSideEffects = 1 in
1955 def MOVr : AsI1<0b1101, (outs GPR:$Rd), (ins GPR:$Rm), DPFrm, IIC_iMOVr,
1956 "mov", "\t$Rd, $Rm", []>, UnaryDP {
1960 let Inst{11-4} = 0b00000000;
1963 let Inst{15-12} = Rd;
1966 // A version for the smaller set of tail call registers.
1967 let neverHasSideEffects = 1 in
1968 def MOVr_TC : AsI1<0b1101, (outs tcGPR:$Rd), (ins tcGPR:$Rm), DPFrm,
1969 IIC_iMOVr, "mov", "\t$Rd, $Rm", []>, UnaryDP {
1973 let Inst{11-4} = 0b00000000;
1976 let Inst{15-12} = Rd;
1979 def MOVs : AsI1<0b1101, (outs GPR:$Rd), (ins shift_so_reg:$src),
1980 DPSoRegFrm, IIC_iMOVsr,
1981 "mov", "\t$Rd, $src", [(set GPR:$Rd, shift_so_reg:$src)]>,
1985 let Inst{15-12} = Rd;
1986 let Inst{11-0} = src;
1990 let isReMaterializable = 1, isAsCheapAsAMove = 1, isMoveImm = 1 in
1991 def MOVi : AsI1<0b1101, (outs GPR:$Rd), (ins so_imm:$imm), DPFrm, IIC_iMOVi,
1992 "mov", "\t$Rd, $imm", [(set GPR:$Rd, so_imm:$imm)]>, UnaryDP {
1996 let Inst{15-12} = Rd;
1997 let Inst{19-16} = 0b0000;
1998 let Inst{11-0} = imm;
2001 let isReMaterializable = 1, isAsCheapAsAMove = 1, isMoveImm = 1 in
2002 def MOVi16 : AI1<0b1000, (outs GPR:$Rd), (ins i32imm_hilo16:$imm),
2004 "movw", "\t$Rd, $imm",
2005 [(set GPR:$Rd, imm0_65535:$imm)]>,
2006 Requires<[IsARM, HasV6T2]>, UnaryDP {
2009 let Inst{15-12} = Rd;
2010 let Inst{11-0} = imm{11-0};
2011 let Inst{19-16} = imm{15-12};
2016 def MOVi16_ga_pcrel : PseudoInst<(outs GPR:$Rd),
2017 (ins i32imm:$addr, pclabel:$id), IIC_iMOVi, []>;
2019 let Constraints = "$src = $Rd" in {
2020 def MOVTi16 : AI1<0b1010, (outs GPR:$Rd), (ins GPR:$src, i32imm_hilo16:$imm),
2022 "movt", "\t$Rd, $imm",
2024 (or (and GPR:$src, 0xffff),
2025 lo16AllZero:$imm))]>, UnaryDP,
2026 Requires<[IsARM, HasV6T2]> {
2029 let Inst{15-12} = Rd;
2030 let Inst{11-0} = imm{11-0};
2031 let Inst{19-16} = imm{15-12};
2036 def MOVTi16_ga_pcrel : PseudoInst<(outs GPR:$Rd),
2037 (ins GPR:$src, i32imm:$addr, pclabel:$id), IIC_iMOVi, []>;
2041 def : ARMPat<(or GPR:$src, 0xffff0000), (MOVTi16 GPR:$src, 0xffff)>,
2042 Requires<[IsARM, HasV6T2]>;
2044 let Uses = [CPSR] in
2045 def RRX: PseudoInst<(outs GPR:$Rd), (ins GPR:$Rm), IIC_iMOVsi,
2046 [(set GPR:$Rd, (ARMrrx GPR:$Rm))]>, UnaryDP,
2049 // These aren't really mov instructions, but we have to define them this way
2050 // due to flag operands.
2052 let Defs = [CPSR] in {
2053 def MOVsrl_flag : PseudoInst<(outs GPR:$dst), (ins GPR:$src), IIC_iMOVsi,
2054 [(set GPR:$dst, (ARMsrl_flag GPR:$src))]>, UnaryDP,
2056 def MOVsra_flag : PseudoInst<(outs GPR:$dst), (ins GPR:$src), IIC_iMOVsi,
2057 [(set GPR:$dst, (ARMsra_flag GPR:$src))]>, UnaryDP,
2061 //===----------------------------------------------------------------------===//
2062 // Extend Instructions.
2067 defm SXTB : AI_ext_rrot<0b01101010,
2068 "sxtb", UnOpFrag<(sext_inreg node:$Src, i8)>>;
2069 defm SXTH : AI_ext_rrot<0b01101011,
2070 "sxth", UnOpFrag<(sext_inreg node:$Src, i16)>>;
2072 defm SXTAB : AI_exta_rrot<0b01101010,
2073 "sxtab", BinOpFrag<(add node:$LHS, (sext_inreg node:$RHS, i8))>>;
2074 defm SXTAH : AI_exta_rrot<0b01101011,
2075 "sxtah", BinOpFrag<(add node:$LHS, (sext_inreg node:$RHS,i16))>>;
2077 // For disassembly only
2078 defm SXTB16 : AI_ext_rrot_np<0b01101000, "sxtb16">;
2080 // For disassembly only
2081 defm SXTAB16 : AI_exta_rrot_np<0b01101000, "sxtab16">;
2085 let AddedComplexity = 16 in {
2086 defm UXTB : AI_ext_rrot<0b01101110,
2087 "uxtb" , UnOpFrag<(and node:$Src, 0x000000FF)>>;
2088 defm UXTH : AI_ext_rrot<0b01101111,
2089 "uxth" , UnOpFrag<(and node:$Src, 0x0000FFFF)>>;
2090 defm UXTB16 : AI_ext_rrot<0b01101100,
2091 "uxtb16", UnOpFrag<(and node:$Src, 0x00FF00FF)>>;
2093 // FIXME: This pattern incorrectly assumes the shl operator is a rotate.
2094 // The transformation should probably be done as a combiner action
2095 // instead so we can include a check for masking back in the upper
2096 // eight bits of the source into the lower eight bits of the result.
2097 //def : ARMV6Pat<(and (shl GPR:$Src, (i32 8)), 0xFF00FF),
2098 // (UXTB16r_rot GPR:$Src, 24)>;
2099 def : ARMV6Pat<(and (srl GPR:$Src, (i32 8)), 0xFF00FF),
2100 (UXTB16r_rot GPR:$Src, 8)>;
2102 defm UXTAB : AI_exta_rrot<0b01101110, "uxtab",
2103 BinOpFrag<(add node:$LHS, (and node:$RHS, 0x00FF))>>;
2104 defm UXTAH : AI_exta_rrot<0b01101111, "uxtah",
2105 BinOpFrag<(add node:$LHS, (and node:$RHS, 0xFFFF))>>;
2108 // This isn't safe in general, the add is two 16-bit units, not a 32-bit add.
2109 // For disassembly only
2110 defm UXTAB16 : AI_exta_rrot_np<0b01101100, "uxtab16">;
2113 def SBFX : I<(outs GPR:$Rd),
2114 (ins GPR:$Rn, imm0_31:$lsb, imm0_31_m1:$width),
2115 AddrMode1, Size4Bytes, IndexModeNone, DPFrm, IIC_iUNAsi,
2116 "sbfx", "\t$Rd, $Rn, $lsb, $width", "", []>,
2117 Requires<[IsARM, HasV6T2]> {
2122 let Inst{27-21} = 0b0111101;
2123 let Inst{6-4} = 0b101;
2124 let Inst{20-16} = width;
2125 let Inst{15-12} = Rd;
2126 let Inst{11-7} = lsb;
2130 def UBFX : I<(outs GPR:$Rd),
2131 (ins GPR:$Rn, imm0_31:$lsb, imm0_31_m1:$width),
2132 AddrMode1, Size4Bytes, IndexModeNone, DPFrm, IIC_iUNAsi,
2133 "ubfx", "\t$Rd, $Rn, $lsb, $width", "", []>,
2134 Requires<[IsARM, HasV6T2]> {
2139 let Inst{27-21} = 0b0111111;
2140 let Inst{6-4} = 0b101;
2141 let Inst{20-16} = width;
2142 let Inst{15-12} = Rd;
2143 let Inst{11-7} = lsb;
2147 //===----------------------------------------------------------------------===//
2148 // Arithmetic Instructions.
2151 defm ADD : AsI1_bin_irs<0b0100, "add",
2152 IIC_iALUi, IIC_iALUr, IIC_iALUsr,
2153 BinOpFrag<(add node:$LHS, node:$RHS)>, 1>;
2154 defm SUB : AsI1_bin_irs<0b0010, "sub",
2155 IIC_iALUi, IIC_iALUr, IIC_iALUsr,
2156 BinOpFrag<(sub node:$LHS, node:$RHS)>>;
2158 // ADD and SUB with 's' bit set.
2159 defm ADDS : AI1_bin_s_irs<0b0100, "adds",
2160 IIC_iALUi, IIC_iALUr, IIC_iALUsr,
2161 BinOpFrag<(addc node:$LHS, node:$RHS)>, 1>;
2162 defm SUBS : AI1_bin_s_irs<0b0010, "subs",
2163 IIC_iALUi, IIC_iALUr, IIC_iALUsr,
2164 BinOpFrag<(subc node:$LHS, node:$RHS)>>;
2166 defm ADC : AI1_adde_sube_irs<0b0101, "adc",
2167 BinOpFrag<(adde_dead_carry node:$LHS, node:$RHS)>, 1>;
2168 defm SBC : AI1_adde_sube_irs<0b0110, "sbc",
2169 BinOpFrag<(sube_dead_carry node:$LHS, node:$RHS)>>;
2171 // ADC and SUBC with 's' bit set.
2172 defm ADCS : AI1_adde_sube_s_irs<0b0101, "adcs",
2173 BinOpFrag<(adde_live_carry node:$LHS, node:$RHS)>, 1>;
2174 defm SBCS : AI1_adde_sube_s_irs<0b0110, "sbcs",
2175 BinOpFrag<(sube_live_carry node:$LHS, node:$RHS) >>;
2177 def RSBri : AsI1<0b0011, (outs GPR:$Rd), (ins GPR:$Rn, so_imm:$imm), DPFrm,
2178 IIC_iALUi, "rsb", "\t$Rd, $Rn, $imm",
2179 [(set GPR:$Rd, (sub so_imm:$imm, GPR:$Rn))]> {
2184 let Inst{15-12} = Rd;
2185 let Inst{19-16} = Rn;
2186 let Inst{11-0} = imm;
2189 // The reg/reg form is only defined for the disassembler; for codegen it is
2190 // equivalent to SUBrr.
2191 def RSBrr : AsI1<0b0011, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm), DPFrm,
2192 IIC_iALUr, "rsb", "\t$Rd, $Rn, $Rm",
2193 [/* For disassembly only; pattern left blank */]> {
2197 let Inst{11-4} = 0b00000000;
2200 let Inst{15-12} = Rd;
2201 let Inst{19-16} = Rn;
2204 def RSBrs : AsI1<0b0011, (outs GPR:$Rd), (ins GPR:$Rn, so_reg:$shift),
2205 DPSoRegFrm, IIC_iALUsr, "rsb", "\t$Rd, $Rn, $shift",
2206 [(set GPR:$Rd, (sub so_reg:$shift, GPR:$Rn))]> {
2211 let Inst{11-0} = shift;
2212 let Inst{15-12} = Rd;
2213 let Inst{19-16} = Rn;
2216 // RSB with 's' bit set.
2217 let isCodeGenOnly = 1, Defs = [CPSR] in {
2218 def RSBSri : AI1<0b0011, (outs GPR:$Rd), (ins GPR:$Rn, so_imm:$imm), DPFrm,
2219 IIC_iALUi, "rsbs", "\t$Rd, $Rn, $imm",
2220 [(set GPR:$Rd, (subc so_imm:$imm, GPR:$Rn))]> {
2226 let Inst{15-12} = Rd;
2227 let Inst{19-16} = Rn;
2228 let Inst{11-0} = imm;
2230 def RSBSrr : AI1<0b0011, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm), DPFrm,
2231 IIC_iALUr, "rsbs", "\t$Rd, $Rn, $Rm",
2232 [/* For disassembly only; pattern left blank */]> {
2236 let Inst{11-4} = 0b00000000;
2240 let Inst{15-12} = Rd;
2241 let Inst{19-16} = Rn;
2243 def RSBSrs : AI1<0b0011, (outs GPR:$Rd), (ins GPR:$Rn, so_reg:$shift),
2244 DPSoRegFrm, IIC_iALUsr, "rsbs", "\t$Rd, $Rn, $shift",
2245 [(set GPR:$Rd, (subc so_reg:$shift, GPR:$Rn))]> {
2251 let Inst{11-0} = shift;
2252 let Inst{15-12} = Rd;
2253 let Inst{19-16} = Rn;
2257 let Uses = [CPSR] in {
2258 def RSCri : AsI1<0b0111, (outs GPR:$Rd), (ins GPR:$Rn, so_imm:$imm),
2259 DPFrm, IIC_iALUi, "rsc", "\t$Rd, $Rn, $imm",
2260 [(set GPR:$Rd, (sube_dead_carry so_imm:$imm, GPR:$Rn))]>,
2266 let Inst{15-12} = Rd;
2267 let Inst{19-16} = Rn;
2268 let Inst{11-0} = imm;
2270 // The reg/reg form is only defined for the disassembler; for codegen it is
2271 // equivalent to SUBrr.
2272 def RSCrr : AsI1<0b0111, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm),
2273 DPFrm, IIC_iALUr, "rsc", "\t$Rd, $Rn, $Rm",
2274 [/* For disassembly only; pattern left blank */]> {
2278 let Inst{11-4} = 0b00000000;
2281 let Inst{15-12} = Rd;
2282 let Inst{19-16} = Rn;
2284 def RSCrs : AsI1<0b0111, (outs GPR:$Rd), (ins GPR:$Rn, so_reg:$shift),
2285 DPSoRegFrm, IIC_iALUsr, "rsc", "\t$Rd, $Rn, $shift",
2286 [(set GPR:$Rd, (sube_dead_carry so_reg:$shift, GPR:$Rn))]>,
2292 let Inst{11-0} = shift;
2293 let Inst{15-12} = Rd;
2294 let Inst{19-16} = Rn;
2298 // FIXME: Allow these to be predicated.
2299 let isCodeGenOnly = 1, Defs = [CPSR], Uses = [CPSR] in {
2300 def RSCSri : AXI1<0b0111, (outs GPR:$Rd), (ins GPR:$Rn, so_imm:$imm),
2301 DPFrm, IIC_iALUi, "rscs\t$Rd, $Rn, $imm",
2302 [(set GPR:$Rd, (sube_dead_carry so_imm:$imm, GPR:$Rn))]>,
2309 let Inst{15-12} = Rd;
2310 let Inst{19-16} = Rn;
2311 let Inst{11-0} = imm;
2313 def RSCSrs : AXI1<0b0111, (outs GPR:$Rd), (ins GPR:$Rn, so_reg:$shift),
2314 DPSoRegFrm, IIC_iALUsr, "rscs\t$Rd, $Rn, $shift",
2315 [(set GPR:$Rd, (sube_dead_carry so_reg:$shift, GPR:$Rn))]>,
2322 let Inst{11-0} = shift;
2323 let Inst{15-12} = Rd;
2324 let Inst{19-16} = Rn;
2328 // (sub X, imm) gets canonicalized to (add X, -imm). Match this form.
2329 // The assume-no-carry-in form uses the negation of the input since add/sub
2330 // assume opposite meanings of the carry flag (i.e., carry == !borrow).
2331 // See the definition of AddWithCarry() in the ARM ARM A2.2.1 for the gory
2333 def : ARMPat<(add GPR:$src, so_imm_neg:$imm),
2334 (SUBri GPR:$src, so_imm_neg:$imm)>;
2335 def : ARMPat<(addc GPR:$src, so_imm_neg:$imm),
2336 (SUBSri GPR:$src, so_imm_neg:$imm)>;
2337 // The with-carry-in form matches bitwise not instead of the negation.
2338 // Effectively, the inverse interpretation of the carry flag already accounts
2339 // for part of the negation.
2340 def : ARMPat<(adde GPR:$src, so_imm_not:$imm),
2341 (SBCri GPR:$src, so_imm_not:$imm)>;
2343 // Note: These are implemented in C++ code, because they have to generate
2344 // ADD/SUBrs instructions, which use a complex pattern that a xform function
2346 // (mul X, 2^n+1) -> (add (X << n), X)
2347 // (mul X, 2^n-1) -> (rsb X, (X << n))
2349 // ARM Arithmetic Instruction -- for disassembly only
2350 // GPR:$dst = GPR:$a op GPR:$b
2351 class AAI<bits<8> op27_20, bits<8> op11_4, string opc,
2352 list<dag> pattern = [/* For disassembly only; pattern left blank */],
2353 dag iops = (ins GPR:$Rn, GPR:$Rm), string asm = "\t$Rd, $Rn, $Rm">
2354 : AI<(outs GPR:$Rd), iops, DPFrm, IIC_iALUr, opc, asm, pattern> {
2358 let Inst{27-20} = op27_20;
2359 let Inst{11-4} = op11_4;
2360 let Inst{19-16} = Rn;
2361 let Inst{15-12} = Rd;
2365 // Saturating add/subtract -- for disassembly only
2367 def QADD : AAI<0b00010000, 0b00000101, "qadd",
2368 [(set GPR:$Rd, (int_arm_qadd GPR:$Rm, GPR:$Rn))],
2369 (ins GPR:$Rm, GPR:$Rn), "\t$Rd, $Rm, $Rn">;
2370 def QSUB : AAI<0b00010010, 0b00000101, "qsub",
2371 [(set GPR:$Rd, (int_arm_qsub GPR:$Rm, GPR:$Rn))],
2372 (ins GPR:$Rm, GPR:$Rn), "\t$Rd, $Rm, $Rn">;
2373 def QDADD : AAI<0b00010100, 0b00000101, "qdadd", [], (ins GPR:$Rm, GPR:$Rn),
2375 def QDSUB : AAI<0b00010110, 0b00000101, "qdsub", [], (ins GPR:$Rm, GPR:$Rn),
2378 def QADD16 : AAI<0b01100010, 0b11110001, "qadd16">;
2379 def QADD8 : AAI<0b01100010, 0b11111001, "qadd8">;
2380 def QASX : AAI<0b01100010, 0b11110011, "qasx">;
2381 def QSAX : AAI<0b01100010, 0b11110101, "qsax">;
2382 def QSUB16 : AAI<0b01100010, 0b11110111, "qsub16">;
2383 def QSUB8 : AAI<0b01100010, 0b11111111, "qsub8">;
2384 def UQADD16 : AAI<0b01100110, 0b11110001, "uqadd16">;
2385 def UQADD8 : AAI<0b01100110, 0b11111001, "uqadd8">;
2386 def UQASX : AAI<0b01100110, 0b11110011, "uqasx">;
2387 def UQSAX : AAI<0b01100110, 0b11110101, "uqsax">;
2388 def UQSUB16 : AAI<0b01100110, 0b11110111, "uqsub16">;
2389 def UQSUB8 : AAI<0b01100110, 0b11111111, "uqsub8">;
2391 // Signed/Unsigned add/subtract -- for disassembly only
2393 def SASX : AAI<0b01100001, 0b11110011, "sasx">;
2394 def SADD16 : AAI<0b01100001, 0b11110001, "sadd16">;
2395 def SADD8 : AAI<0b01100001, 0b11111001, "sadd8">;
2396 def SSAX : AAI<0b01100001, 0b11110101, "ssax">;
2397 def SSUB16 : AAI<0b01100001, 0b11110111, "ssub16">;
2398 def SSUB8 : AAI<0b01100001, 0b11111111, "ssub8">;
2399 def UASX : AAI<0b01100101, 0b11110011, "uasx">;
2400 def UADD16 : AAI<0b01100101, 0b11110001, "uadd16">;
2401 def UADD8 : AAI<0b01100101, 0b11111001, "uadd8">;
2402 def USAX : AAI<0b01100101, 0b11110101, "usax">;
2403 def USUB16 : AAI<0b01100101, 0b11110111, "usub16">;
2404 def USUB8 : AAI<0b01100101, 0b11111111, "usub8">;
2406 // Signed/Unsigned halving add/subtract -- for disassembly only
2408 def SHASX : AAI<0b01100011, 0b11110011, "shasx">;
2409 def SHADD16 : AAI<0b01100011, 0b11110001, "shadd16">;
2410 def SHADD8 : AAI<0b01100011, 0b11111001, "shadd8">;
2411 def SHSAX : AAI<0b01100011, 0b11110101, "shsax">;
2412 def SHSUB16 : AAI<0b01100011, 0b11110111, "shsub16">;
2413 def SHSUB8 : AAI<0b01100011, 0b11111111, "shsub8">;
2414 def UHASX : AAI<0b01100111, 0b11110011, "uhasx">;
2415 def UHADD16 : AAI<0b01100111, 0b11110001, "uhadd16">;
2416 def UHADD8 : AAI<0b01100111, 0b11111001, "uhadd8">;
2417 def UHSAX : AAI<0b01100111, 0b11110101, "uhsax">;
2418 def UHSUB16 : AAI<0b01100111, 0b11110111, "uhsub16">;
2419 def UHSUB8 : AAI<0b01100111, 0b11111111, "uhsub8">;
2421 // Unsigned Sum of Absolute Differences [and Accumulate] -- for disassembly only
2423 def USAD8 : AI<(outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm),
2424 MulFrm /* for convenience */, NoItinerary, "usad8",
2425 "\t$Rd, $Rn, $Rm", []>,
2426 Requires<[IsARM, HasV6]> {
2430 let Inst{27-20} = 0b01111000;
2431 let Inst{15-12} = 0b1111;
2432 let Inst{7-4} = 0b0001;
2433 let Inst{19-16} = Rd;
2434 let Inst{11-8} = Rm;
2437 def USADA8 : AI<(outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm, GPR:$Ra),
2438 MulFrm /* for convenience */, NoItinerary, "usada8",
2439 "\t$Rd, $Rn, $Rm, $Ra", []>,
2440 Requires<[IsARM, HasV6]> {
2445 let Inst{27-20} = 0b01111000;
2446 let Inst{7-4} = 0b0001;
2447 let Inst{19-16} = Rd;
2448 let Inst{15-12} = Ra;
2449 let Inst{11-8} = Rm;
2453 // Signed/Unsigned saturate -- for disassembly only
2455 def SSAT : AI<(outs GPR:$Rd), (ins i32imm:$sat_imm, GPR:$a, shift_imm:$sh),
2456 SatFrm, NoItinerary, "ssat", "\t$Rd, $sat_imm, $a$sh",
2457 [/* For disassembly only; pattern left blank */]> {
2462 let Inst{27-21} = 0b0110101;
2463 let Inst{5-4} = 0b01;
2464 let Inst{20-16} = sat_imm;
2465 let Inst{15-12} = Rd;
2466 let Inst{11-7} = sh{7-3};
2467 let Inst{6} = sh{0};
2471 def SSAT16 : AI<(outs GPR:$Rd), (ins i32imm:$sat_imm, GPR:$Rn), SatFrm,
2472 NoItinerary, "ssat16", "\t$Rd, $sat_imm, $Rn",
2473 [/* For disassembly only; pattern left blank */]> {
2477 let Inst{27-20} = 0b01101010;
2478 let Inst{11-4} = 0b11110011;
2479 let Inst{15-12} = Rd;
2480 let Inst{19-16} = sat_imm;
2484 def USAT : AI<(outs GPR:$Rd), (ins i32imm:$sat_imm, GPR:$a, shift_imm:$sh),
2485 SatFrm, NoItinerary, "usat", "\t$Rd, $sat_imm, $a$sh",
2486 [/* For disassembly only; pattern left blank */]> {
2491 let Inst{27-21} = 0b0110111;
2492 let Inst{5-4} = 0b01;
2493 let Inst{15-12} = Rd;
2494 let Inst{11-7} = sh{7-3};
2495 let Inst{6} = sh{0};
2496 let Inst{20-16} = sat_imm;
2500 def USAT16 : AI<(outs GPR:$Rd), (ins i32imm:$sat_imm, GPR:$a), SatFrm,
2501 NoItinerary, "usat16", "\t$Rd, $sat_imm, $a",
2502 [/* For disassembly only; pattern left blank */]> {
2506 let Inst{27-20} = 0b01101110;
2507 let Inst{11-4} = 0b11110011;
2508 let Inst{15-12} = Rd;
2509 let Inst{19-16} = sat_imm;
2513 def : ARMV6Pat<(int_arm_ssat GPR:$a, imm:$pos), (SSAT imm:$pos, GPR:$a, 0)>;
2514 def : ARMV6Pat<(int_arm_usat GPR:$a, imm:$pos), (USAT imm:$pos, GPR:$a, 0)>;
2516 //===----------------------------------------------------------------------===//
2517 // Bitwise Instructions.
2520 defm AND : AsI1_bin_irs<0b0000, "and",
2521 IIC_iBITi, IIC_iBITr, IIC_iBITsr,
2522 BinOpFrag<(and node:$LHS, node:$RHS)>, 1>;
2523 defm ORR : AsI1_bin_irs<0b1100, "orr",
2524 IIC_iBITi, IIC_iBITr, IIC_iBITsr,
2525 BinOpFrag<(or node:$LHS, node:$RHS)>, 1>;
2526 defm EOR : AsI1_bin_irs<0b0001, "eor",
2527 IIC_iBITi, IIC_iBITr, IIC_iBITsr,
2528 BinOpFrag<(xor node:$LHS, node:$RHS)>, 1>;
2529 defm BIC : AsI1_bin_irs<0b1110, "bic",
2530 IIC_iBITi, IIC_iBITr, IIC_iBITsr,
2531 BinOpFrag<(and node:$LHS, (not node:$RHS))>>;
2533 def BFC : I<(outs GPR:$Rd), (ins GPR:$src, bf_inv_mask_imm:$imm),
2534 AddrMode1, Size4Bytes, IndexModeNone, DPFrm, IIC_iUNAsi,
2535 "bfc", "\t$Rd, $imm", "$src = $Rd",
2536 [(set GPR:$Rd, (and GPR:$src, bf_inv_mask_imm:$imm))]>,
2537 Requires<[IsARM, HasV6T2]> {
2540 let Inst{27-21} = 0b0111110;
2541 let Inst{6-0} = 0b0011111;
2542 let Inst{15-12} = Rd;
2543 let Inst{11-7} = imm{4-0}; // lsb
2544 let Inst{20-16} = imm{9-5}; // width
2547 // A8.6.18 BFI - Bitfield insert (Encoding A1)
2548 def BFI : I<(outs GPR:$Rd), (ins GPR:$src, GPR:$Rn, bf_inv_mask_imm:$imm),
2549 AddrMode1, Size4Bytes, IndexModeNone, DPFrm, IIC_iUNAsi,
2550 "bfi", "\t$Rd, $Rn, $imm", "$src = $Rd",
2551 [(set GPR:$Rd, (ARMbfi GPR:$src, GPR:$Rn,
2552 bf_inv_mask_imm:$imm))]>,
2553 Requires<[IsARM, HasV6T2]> {
2557 let Inst{27-21} = 0b0111110;
2558 let Inst{6-4} = 0b001; // Rn: Inst{3-0} != 15
2559 let Inst{15-12} = Rd;
2560 let Inst{11-7} = imm{4-0}; // lsb
2561 let Inst{20-16} = imm{9-5}; // width
2565 // GNU as only supports this form of bfi (w/ 4 arguments)
2566 let isAsmParserOnly = 1 in
2567 def BFI4p : I<(outs GPR:$Rd), (ins GPR:$src, GPR:$Rn,
2568 lsb_pos_imm:$lsb, width_imm:$width),
2569 AddrMode1, Size4Bytes, IndexModeNone, DPFrm, IIC_iUNAsi,
2570 "bfi", "\t$Rd, $Rn, $lsb, $width", "$src = $Rd",
2571 []>, Requires<[IsARM, HasV6T2]> {
2576 let Inst{27-21} = 0b0111110;
2577 let Inst{6-4} = 0b001; // Rn: Inst{3-0} != 15
2578 let Inst{15-12} = Rd;
2579 let Inst{11-7} = lsb;
2580 let Inst{20-16} = width; // Custom encoder => lsb+width-1
2584 def MVNr : AsI1<0b1111, (outs GPR:$Rd), (ins GPR:$Rm), DPFrm, IIC_iMVNr,
2585 "mvn", "\t$Rd, $Rm",
2586 [(set GPR:$Rd, (not GPR:$Rm))]>, UnaryDP {
2590 let Inst{19-16} = 0b0000;
2591 let Inst{11-4} = 0b00000000;
2592 let Inst{15-12} = Rd;
2595 def MVNs : AsI1<0b1111, (outs GPR:$Rd), (ins so_reg:$shift), DPSoRegFrm,
2596 IIC_iMVNsr, "mvn", "\t$Rd, $shift",
2597 [(set GPR:$Rd, (not so_reg:$shift))]>, UnaryDP {
2601 let Inst{19-16} = 0b0000;
2602 let Inst{15-12} = Rd;
2603 let Inst{11-0} = shift;
2605 let isReMaterializable = 1, isAsCheapAsAMove = 1, isMoveImm = 1 in
2606 def MVNi : AsI1<0b1111, (outs GPR:$Rd), (ins so_imm:$imm), DPFrm,
2607 IIC_iMVNi, "mvn", "\t$Rd, $imm",
2608 [(set GPR:$Rd, so_imm_not:$imm)]>,UnaryDP {
2612 let Inst{19-16} = 0b0000;
2613 let Inst{15-12} = Rd;
2614 let Inst{11-0} = imm;
2617 def : ARMPat<(and GPR:$src, so_imm_not:$imm),
2618 (BICri GPR:$src, so_imm_not:$imm)>;
2620 //===----------------------------------------------------------------------===//
2621 // Multiply Instructions.
2623 class AsMul1I32<bits<7> opcod, dag oops, dag iops, InstrItinClass itin,
2624 string opc, string asm, list<dag> pattern>
2625 : AsMul1I<opcod, oops, iops, itin, opc, asm, pattern> {
2629 let Inst{19-16} = Rd;
2630 let Inst{11-8} = Rm;
2633 class AsMul1I64<bits<7> opcod, dag oops, dag iops, InstrItinClass itin,
2634 string opc, string asm, list<dag> pattern>
2635 : AsMul1I<opcod, oops, iops, itin, opc, asm, pattern> {
2640 let Inst{19-16} = RdHi;
2641 let Inst{15-12} = RdLo;
2642 let Inst{11-8} = Rm;
2646 let isCommutable = 1 in {
2647 let Constraints = "@earlyclobber $Rd" in
2648 def MULv5: ARMPseudoInst<(outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm,
2649 pred:$p, cc_out:$s),
2650 Size4Bytes, IIC_iMUL32,
2651 [(set GPR:$Rd, (mul GPR:$Rn, GPR:$Rm))]>,
2652 Requires<[IsARM, NoV6]>;
2654 def MUL : AsMul1I32<0b0000000, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm),
2655 IIC_iMUL32, "mul", "\t$Rd, $Rn, $Rm",
2656 [(set GPR:$Rd, (mul GPR:$Rn, GPR:$Rm))]>,
2657 Requires<[IsARM, HasV6]>;
2660 let Constraints = "@earlyclobber $Rd" in
2661 def MLAv5: ARMPseudoInst<(outs GPR:$Rd),
2662 (ins GPR:$Rn, GPR:$Rm, GPR:$Ra, pred:$p, cc_out:$s),
2663 Size4Bytes, IIC_iMAC32,
2664 [(set GPR:$Rd, (add (mul GPR:$Rn, GPR:$Rm), GPR:$Ra))]>,
2665 Requires<[IsARM, NoV6]> {
2667 let Inst{15-12} = Ra;
2669 def MLA : AsMul1I32<0b0000001, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm, GPR:$Ra),
2670 IIC_iMAC32, "mla", "\t$Rd, $Rn, $Rm, $Ra",
2671 [(set GPR:$Rd, (add (mul GPR:$Rn, GPR:$Rm), GPR:$Ra))]>,
2672 Requires<[IsARM, HasV6]> {
2674 let Inst{15-12} = Ra;
2677 def MLS : AMul1I<0b0000011, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm, GPR:$Ra),
2678 IIC_iMAC32, "mls", "\t$Rd, $Rn, $Rm, $Ra",
2679 [(set GPR:$Rd, (sub GPR:$Ra, (mul GPR:$Rn, GPR:$Rm)))]>,
2680 Requires<[IsARM, HasV6T2]> {
2685 let Inst{19-16} = Rd;
2686 let Inst{15-12} = Ra;
2687 let Inst{11-8} = Rm;
2691 // Extra precision multiplies with low / high results
2693 let neverHasSideEffects = 1 in {
2694 let isCommutable = 1 in {
2695 let Constraints = "@earlyclobber $RdLo,@earlyclobber $RdHi" in {
2696 def SMULLv5 : ARMPseudoInst<(outs GPR:$RdLo, GPR:$RdHi),
2697 (ins GPR:$Rn, GPR:$Rm, pred:$p, cc_out:$s),
2698 Size4Bytes, IIC_iMUL64, []>,
2699 Requires<[IsARM, NoV6]>;
2701 def UMULLv5 : ARMPseudoInst<(outs GPR:$RdLo, GPR:$RdHi),
2702 (ins GPR:$Rn, GPR:$Rm, pred:$p, cc_out:$s),
2703 Size4Bytes, IIC_iMUL64, []>,
2704 Requires<[IsARM, NoV6]>;
2707 def SMULL : AsMul1I64<0b0000110, (outs GPR:$RdLo, GPR:$RdHi),
2708 (ins GPR:$Rn, GPR:$Rm), IIC_iMUL64,
2709 "smull", "\t$RdLo, $RdHi, $Rn, $Rm", []>,
2710 Requires<[IsARM, HasV6]>;
2712 def UMULL : AsMul1I64<0b0000100, (outs GPR:$RdLo, GPR:$RdHi),
2713 (ins GPR:$Rn, GPR:$Rm), IIC_iMUL64,
2714 "umull", "\t$RdLo, $RdHi, $Rn, $Rm", []>,
2715 Requires<[IsARM, HasV6]>;
2718 // Multiply + accumulate
2719 let Constraints = "@earlyclobber $RdLo,@earlyclobber $RdHi" in {
2720 def SMLALv5 : ARMPseudoInst<(outs GPR:$RdLo, GPR:$RdHi),
2721 (ins GPR:$Rn, GPR:$Rm, pred:$p, cc_out:$s),
2722 Size4Bytes, IIC_iMAC64, []>,
2723 Requires<[IsARM, NoV6]>;
2724 def UMLALv5 : ARMPseudoInst<(outs GPR:$RdLo, GPR:$RdHi),
2725 (ins GPR:$Rn, GPR:$Rm, pred:$p, cc_out:$s),
2726 Size4Bytes, IIC_iMAC64, []>,
2727 Requires<[IsARM, NoV6]>;
2728 def UMAALv5 : ARMPseudoInst<(outs GPR:$RdLo, GPR:$RdHi),
2729 (ins GPR:$Rn, GPR:$Rm, pred:$p, cc_out:$s),
2730 Size4Bytes, IIC_iMAC64, []>,
2731 Requires<[IsARM, NoV6]>;
2735 def SMLAL : AsMul1I64<0b0000111, (outs GPR:$RdLo, GPR:$RdHi),
2736 (ins GPR:$Rn, GPR:$Rm), IIC_iMAC64,
2737 "smlal", "\t$RdLo, $RdHi, $Rn, $Rm", []>,
2738 Requires<[IsARM, HasV6]>;
2739 def UMLAL : AsMul1I64<0b0000101, (outs GPR:$RdLo, GPR:$RdHi),
2740 (ins GPR:$Rn, GPR:$Rm), IIC_iMAC64,
2741 "umlal", "\t$RdLo, $RdHi, $Rn, $Rm", []>,
2742 Requires<[IsARM, HasV6]>;
2744 def UMAAL : AMul1I <0b0000010, (outs GPR:$RdLo, GPR:$RdHi),
2745 (ins GPR:$Rn, GPR:$Rm), IIC_iMAC64,
2746 "umaal", "\t$RdLo, $RdHi, $Rn, $Rm", []>,
2747 Requires<[IsARM, HasV6]> {
2752 let Inst{19-16} = RdLo;
2753 let Inst{15-12} = RdHi;
2754 let Inst{11-8} = Rm;
2757 } // neverHasSideEffects
2759 // Most significant word multiply
2760 def SMMUL : AMul2I <0b0111010, 0b0001, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm),
2761 IIC_iMUL32, "smmul", "\t$Rd, $Rn, $Rm",
2762 [(set GPR:$Rd, (mulhs GPR:$Rn, GPR:$Rm))]>,
2763 Requires<[IsARM, HasV6]> {
2764 let Inst{15-12} = 0b1111;
2767 def SMMULR : AMul2I <0b0111010, 0b0011, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm),
2768 IIC_iMUL32, "smmulr", "\t$Rd, $Rn, $Rm",
2769 [/* For disassembly only; pattern left blank */]>,
2770 Requires<[IsARM, HasV6]> {
2771 let Inst{15-12} = 0b1111;
2774 def SMMLA : AMul2Ia <0b0111010, 0b0001, (outs GPR:$Rd),
2775 (ins GPR:$Rn, GPR:$Rm, GPR:$Ra),
2776 IIC_iMAC32, "smmla", "\t$Rd, $Rn, $Rm, $Ra",
2777 [(set GPR:$Rd, (add (mulhs GPR:$Rn, GPR:$Rm), GPR:$Ra))]>,
2778 Requires<[IsARM, HasV6]>;
2780 def SMMLAR : AMul2Ia <0b0111010, 0b0011, (outs GPR:$Rd),
2781 (ins GPR:$Rn, GPR:$Rm, GPR:$Ra),
2782 IIC_iMAC32, "smmlar", "\t$Rd, $Rn, $Rm, $Ra",
2783 [/* For disassembly only; pattern left blank */]>,
2784 Requires<[IsARM, HasV6]>;
2786 def SMMLS : AMul2Ia <0b0111010, 0b1101, (outs GPR:$Rd),
2787 (ins GPR:$Rn, GPR:$Rm, GPR:$Ra),
2788 IIC_iMAC32, "smmls", "\t$Rd, $Rn, $Rm, $Ra",
2789 [(set GPR:$Rd, (sub GPR:$Ra, (mulhs GPR:$Rn, GPR:$Rm)))]>,
2790 Requires<[IsARM, HasV6]>;
2792 def SMMLSR : AMul2Ia <0b0111010, 0b1111, (outs GPR:$Rd),
2793 (ins GPR:$Rn, GPR:$Rm, GPR:$Ra),
2794 IIC_iMAC32, "smmlsr", "\t$Rd, $Rn, $Rm, $Ra",
2795 [/* For disassembly only; pattern left blank */]>,
2796 Requires<[IsARM, HasV6]>;
2798 multiclass AI_smul<string opc, PatFrag opnode> {
2799 def BB : AMulxyI<0b0001011, 0b00, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm),
2800 IIC_iMUL16, !strconcat(opc, "bb"), "\t$Rd, $Rn, $Rm",
2801 [(set GPR:$Rd, (opnode (sext_inreg GPR:$Rn, i16),
2802 (sext_inreg GPR:$Rm, i16)))]>,
2803 Requires<[IsARM, HasV5TE]>;
2805 def BT : AMulxyI<0b0001011, 0b10, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm),
2806 IIC_iMUL16, !strconcat(opc, "bt"), "\t$Rd, $Rn, $Rm",
2807 [(set GPR:$Rd, (opnode (sext_inreg GPR:$Rn, i16),
2808 (sra GPR:$Rm, (i32 16))))]>,
2809 Requires<[IsARM, HasV5TE]>;
2811 def TB : AMulxyI<0b0001011, 0b01, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm),
2812 IIC_iMUL16, !strconcat(opc, "tb"), "\t$Rd, $Rn, $Rm",
2813 [(set GPR:$Rd, (opnode (sra GPR:$Rn, (i32 16)),
2814 (sext_inreg GPR:$Rm, i16)))]>,
2815 Requires<[IsARM, HasV5TE]>;
2817 def TT : AMulxyI<0b0001011, 0b11, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm),
2818 IIC_iMUL16, !strconcat(opc, "tt"), "\t$Rd, $Rn, $Rm",
2819 [(set GPR:$Rd, (opnode (sra GPR:$Rn, (i32 16)),
2820 (sra GPR:$Rm, (i32 16))))]>,
2821 Requires<[IsARM, HasV5TE]>;
2823 def WB : AMulxyI<0b0001001, 0b01, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm),
2824 IIC_iMUL16, !strconcat(opc, "wb"), "\t$Rd, $Rn, $Rm",
2825 [(set GPR:$Rd, (sra (opnode GPR:$Rn,
2826 (sext_inreg GPR:$Rm, i16)), (i32 16)))]>,
2827 Requires<[IsARM, HasV5TE]>;
2829 def WT : AMulxyI<0b0001001, 0b11, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm),
2830 IIC_iMUL16, !strconcat(opc, "wt"), "\t$Rd, $Rn, $Rm",
2831 [(set GPR:$Rd, (sra (opnode GPR:$Rn,
2832 (sra GPR:$Rm, (i32 16))), (i32 16)))]>,
2833 Requires<[IsARM, HasV5TE]>;
2837 multiclass AI_smla<string opc, PatFrag opnode> {
2838 def BB : AMulxyIa<0b0001000, 0b00, (outs GPR:$Rd),
2839 (ins GPR:$Rn, GPR:$Rm, GPR:$Ra),
2840 IIC_iMAC16, !strconcat(opc, "bb"), "\t$Rd, $Rn, $Rm, $Ra",
2841 [(set GPR:$Rd, (add GPR:$Ra,
2842 (opnode (sext_inreg GPR:$Rn, i16),
2843 (sext_inreg GPR:$Rm, i16))))]>,
2844 Requires<[IsARM, HasV5TE]>;
2846 def BT : AMulxyIa<0b0001000, 0b10, (outs GPR:$Rd),
2847 (ins GPR:$Rn, GPR:$Rm, GPR:$Ra),
2848 IIC_iMAC16, !strconcat(opc, "bt"), "\t$Rd, $Rn, $Rm, $Ra",
2849 [(set GPR:$Rd, (add GPR:$Ra, (opnode (sext_inreg GPR:$Rn, i16),
2850 (sra GPR:$Rm, (i32 16)))))]>,
2851 Requires<[IsARM, HasV5TE]>;
2853 def TB : AMulxyIa<0b0001000, 0b01, (outs GPR:$Rd),
2854 (ins GPR:$Rn, GPR:$Rm, GPR:$Ra),
2855 IIC_iMAC16, !strconcat(opc, "tb"), "\t$Rd, $Rn, $Rm, $Ra",
2856 [(set GPR:$Rd, (add GPR:$Ra, (opnode (sra GPR:$Rn, (i32 16)),
2857 (sext_inreg GPR:$Rm, i16))))]>,
2858 Requires<[IsARM, HasV5TE]>;
2860 def TT : AMulxyIa<0b0001000, 0b11, (outs GPR:$Rd),
2861 (ins GPR:$Rn, GPR:$Rm, GPR:$Ra),
2862 IIC_iMAC16, !strconcat(opc, "tt"), "\t$Rd, $Rn, $Rm, $Ra",
2863 [(set GPR:$Rd, (add GPR:$Ra, (opnode (sra GPR:$Rn, (i32 16)),
2864 (sra GPR:$Rm, (i32 16)))))]>,
2865 Requires<[IsARM, HasV5TE]>;
2867 def WB : AMulxyIa<0b0001001, 0b00, (outs GPR:$Rd),
2868 (ins GPR:$Rn, GPR:$Rm, GPR:$Ra),
2869 IIC_iMAC16, !strconcat(opc, "wb"), "\t$Rd, $Rn, $Rm, $Ra",
2870 [(set GPR:$Rd, (add GPR:$Ra, (sra (opnode GPR:$Rn,
2871 (sext_inreg GPR:$Rm, i16)), (i32 16))))]>,
2872 Requires<[IsARM, HasV5TE]>;
2874 def WT : AMulxyIa<0b0001001, 0b10, (outs GPR:$Rd),
2875 (ins GPR:$Rn, GPR:$Rm, GPR:$Ra),
2876 IIC_iMAC16, !strconcat(opc, "wt"), "\t$Rd, $Rn, $Rm, $Ra",
2877 [(set GPR:$Rd, (add GPR:$Ra, (sra (opnode GPR:$Rn,
2878 (sra GPR:$Rm, (i32 16))), (i32 16))))]>,
2879 Requires<[IsARM, HasV5TE]>;
2882 defm SMUL : AI_smul<"smul", BinOpFrag<(mul node:$LHS, node:$RHS)>>;
2883 defm SMLA : AI_smla<"smla", BinOpFrag<(mul node:$LHS, node:$RHS)>>;
2885 // Halfword multiply accumulate long: SMLAL<x><y> -- for disassembly only
2886 def SMLALBB : AMulxyI64<0b0001010, 0b00, (outs GPR:$RdLo, GPR:$RdHi),
2887 (ins GPR:$Rn, GPR:$Rm),
2888 IIC_iMAC64, "smlalbb", "\t$RdLo, $RdHi, $Rn, $Rm",
2889 [/* For disassembly only; pattern left blank */]>,
2890 Requires<[IsARM, HasV5TE]>;
2892 def SMLALBT : AMulxyI64<0b0001010, 0b10, (outs GPR:$RdLo, GPR:$RdHi),
2893 (ins GPR:$Rn, GPR:$Rm),
2894 IIC_iMAC64, "smlalbt", "\t$RdLo, $RdHi, $Rn, $Rm",
2895 [/* For disassembly only; pattern left blank */]>,
2896 Requires<[IsARM, HasV5TE]>;
2898 def SMLALTB : AMulxyI64<0b0001010, 0b01, (outs GPR:$RdLo, GPR:$RdHi),
2899 (ins GPR:$Rn, GPR:$Rm),
2900 IIC_iMAC64, "smlaltb", "\t$RdLo, $RdHi, $Rn, $Rm",
2901 [/* For disassembly only; pattern left blank */]>,
2902 Requires<[IsARM, HasV5TE]>;
2904 def SMLALTT : AMulxyI64<0b0001010, 0b11, (outs GPR:$RdLo, GPR:$RdHi),
2905 (ins GPR:$Rn, GPR:$Rm),
2906 IIC_iMAC64, "smlaltt", "\t$RdLo, $RdHi, $Rn, $Rm",
2907 [/* For disassembly only; pattern left blank */]>,
2908 Requires<[IsARM, HasV5TE]>;
2910 // Helper class for AI_smld -- for disassembly only
2911 class AMulDualIbase<bit long, bit sub, bit swap, dag oops, dag iops,
2912 InstrItinClass itin, string opc, string asm>
2913 : AI<oops, iops, MulFrm, itin, opc, asm, []>, Requires<[IsARM, HasV6]> {
2920 let Inst{21-20} = 0b00;
2921 let Inst{22} = long;
2922 let Inst{27-23} = 0b01110;
2923 let Inst{11-8} = Rm;
2926 class AMulDualI<bit long, bit sub, bit swap, dag oops, dag iops,
2927 InstrItinClass itin, string opc, string asm>
2928 : AMulDualIbase<long, sub, swap, oops, iops, itin, opc, asm> {
2930 let Inst{15-12} = 0b1111;
2931 let Inst{19-16} = Rd;
2933 class AMulDualIa<bit long, bit sub, bit swap, dag oops, dag iops,
2934 InstrItinClass itin, string opc, string asm>
2935 : AMulDualIbase<long, sub, swap, oops, iops, itin, opc, asm> {
2937 let Inst{15-12} = Ra;
2939 class AMulDualI64<bit long, bit sub, bit swap, dag oops, dag iops,
2940 InstrItinClass itin, string opc, string asm>
2941 : AMulDualIbase<long, sub, swap, oops, iops, itin, opc, asm> {
2944 let Inst{19-16} = RdHi;
2945 let Inst{15-12} = RdLo;
2948 multiclass AI_smld<bit sub, string opc> {
2950 def D : AMulDualIa<0, sub, 0, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm, GPR:$Ra),
2951 NoItinerary, !strconcat(opc, "d"), "\t$Rd, $Rn, $Rm, $Ra">;
2953 def DX: AMulDualIa<0, sub, 1, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm, GPR:$Ra),
2954 NoItinerary, !strconcat(opc, "dx"), "\t$Rd, $Rn, $Rm, $Ra">;
2956 def LD: AMulDualI64<1, sub, 0, (outs GPR:$RdLo,GPR:$RdHi),
2957 (ins GPR:$Rn, GPR:$Rm), NoItinerary,
2958 !strconcat(opc, "ld"), "\t$RdLo, $RdHi, $Rn, $Rm">;
2960 def LDX : AMulDualI64<1, sub, 1, (outs GPR:$RdLo,GPR:$RdHi),
2961 (ins GPR:$Rn, GPR:$Rm), NoItinerary,
2962 !strconcat(opc, "ldx"),"\t$RdLo, $RdHi, $Rn, $Rm">;
2966 defm SMLA : AI_smld<0, "smla">;
2967 defm SMLS : AI_smld<1, "smls">;
2969 multiclass AI_sdml<bit sub, string opc> {
2971 def D : AMulDualI<0, sub, 0, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm),
2972 NoItinerary, !strconcat(opc, "d"), "\t$Rd, $Rn, $Rm">;
2973 def DX : AMulDualI<0, sub, 1, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm),
2974 NoItinerary, !strconcat(opc, "dx"), "\t$Rd, $Rn, $Rm">;
2977 defm SMUA : AI_sdml<0, "smua">;
2978 defm SMUS : AI_sdml<1, "smus">;
2980 //===----------------------------------------------------------------------===//
2981 // Misc. Arithmetic Instructions.
2984 def CLZ : AMiscA1I<0b000010110, 0b0001, (outs GPR:$Rd), (ins GPR:$Rm),
2985 IIC_iUNAr, "clz", "\t$Rd, $Rm",
2986 [(set GPR:$Rd, (ctlz GPR:$Rm))]>, Requires<[IsARM, HasV5T]>;
2988 def RBIT : AMiscA1I<0b01101111, 0b0011, (outs GPR:$Rd), (ins GPR:$Rm),
2989 IIC_iUNAr, "rbit", "\t$Rd, $Rm",
2990 [(set GPR:$Rd, (ARMrbit GPR:$Rm))]>,
2991 Requires<[IsARM, HasV6T2]>;
2993 def REV : AMiscA1I<0b01101011, 0b0011, (outs GPR:$Rd), (ins GPR:$Rm),
2994 IIC_iUNAr, "rev", "\t$Rd, $Rm",
2995 [(set GPR:$Rd, (bswap GPR:$Rm))]>, Requires<[IsARM, HasV6]>;
2997 def REV16 : AMiscA1I<0b01101011, 0b1011, (outs GPR:$Rd), (ins GPR:$Rm),
2998 IIC_iUNAr, "rev16", "\t$Rd, $Rm",
3000 (or (and (srl GPR:$Rm, (i32 8)), 0xFF),
3001 (or (and (shl GPR:$Rm, (i32 8)), 0xFF00),
3002 (or (and (srl GPR:$Rm, (i32 8)), 0xFF0000),
3003 (and (shl GPR:$Rm, (i32 8)), 0xFF000000)))))]>,
3004 Requires<[IsARM, HasV6]>;
3006 def REVSH : AMiscA1I<0b01101111, 0b1011, (outs GPR:$Rd), (ins GPR:$Rm),
3007 IIC_iUNAr, "revsh", "\t$Rd, $Rm",
3010 (or (srl GPR:$Rm, (i32 8)),
3011 (shl GPR:$Rm, (i32 8))), i16))]>,
3012 Requires<[IsARM, HasV6]>;
3014 def : ARMV6Pat<(sext_inreg (or (srl (and GPR:$Rm, 0xFF00), (i32 8)),
3015 (shl GPR:$Rm, (i32 8))), i16),
3018 // Need the AddedComplexity or else MOVs + REV would be chosen.
3019 let AddedComplexity = 5 in
3020 def : ARMV6Pat<(sra (bswap GPR:$Rm), (i32 16)), (REVSH GPR:$Rm)>;
3022 def lsl_shift_imm : SDNodeXForm<imm, [{
3023 unsigned Sh = ARM_AM::getSORegOpc(ARM_AM::lsl, N->getZExtValue());
3024 return CurDAG->getTargetConstant(Sh, MVT::i32);
3027 def lsl_amt : PatLeaf<(i32 imm), [{
3028 return (N->getZExtValue() < 32);
3031 def PKHBT : APKHI<0b01101000, 0, (outs GPR:$Rd),
3032 (ins GPR:$Rn, GPR:$Rm, shift_imm:$sh),
3033 IIC_iALUsi, "pkhbt", "\t$Rd, $Rn, $Rm$sh",
3034 [(set GPR:$Rd, (or (and GPR:$Rn, 0xFFFF),
3035 (and (shl GPR:$Rm, lsl_amt:$sh),
3037 Requires<[IsARM, HasV6]>;
3039 // Alternate cases for PKHBT where identities eliminate some nodes.
3040 def : ARMV6Pat<(or (and GPR:$Rn, 0xFFFF), (and GPR:$Rm, 0xFFFF0000)),
3041 (PKHBT GPR:$Rn, GPR:$Rm, 0)>;
3042 def : ARMV6Pat<(or (and GPR:$Rn, 0xFFFF), (shl GPR:$Rm, imm16_31:$sh)),
3043 (PKHBT GPR:$Rn, GPR:$Rm, (lsl_shift_imm imm16_31:$sh))>;
3045 def asr_shift_imm : SDNodeXForm<imm, [{
3046 unsigned Sh = ARM_AM::getSORegOpc(ARM_AM::asr, N->getZExtValue());
3047 return CurDAG->getTargetConstant(Sh, MVT::i32);
3050 def asr_amt : PatLeaf<(i32 imm), [{
3051 return (N->getZExtValue() <= 32);
3054 // Note: Shifts of 1-15 bits will be transformed to srl instead of sra and
3055 // will match the pattern below.
3056 def PKHTB : APKHI<0b01101000, 1, (outs GPR:$Rd),
3057 (ins GPR:$Rn, GPR:$Rm, shift_imm:$sh),
3058 IIC_iBITsi, "pkhtb", "\t$Rd, $Rn, $Rm$sh",
3059 [(set GPR:$Rd, (or (and GPR:$Rn, 0xFFFF0000),
3060 (and (sra GPR:$Rm, asr_amt:$sh),
3062 Requires<[IsARM, HasV6]>;
3064 // Alternate cases for PKHTB where identities eliminate some nodes. Note that
3065 // a shift amount of 0 is *not legal* here, it is PKHBT instead.
3066 def : ARMV6Pat<(or (and GPR:$src1, 0xFFFF0000), (srl GPR:$src2, imm16_31:$sh)),
3067 (PKHTB GPR:$src1, GPR:$src2, (asr_shift_imm imm16_31:$sh))>;
3068 def : ARMV6Pat<(or (and GPR:$src1, 0xFFFF0000),
3069 (and (srl GPR:$src2, imm1_15:$sh), 0xFFFF)),
3070 (PKHTB GPR:$src1, GPR:$src2, (asr_shift_imm imm1_15:$sh))>;
3072 //===----------------------------------------------------------------------===//
3073 // Comparison Instructions...
3076 defm CMP : AI1_cmp_irs<0b1010, "cmp",
3077 IIC_iCMPi, IIC_iCMPr, IIC_iCMPsr,
3078 BinOpFrag<(ARMcmp node:$LHS, node:$RHS)>>;
3080 // ARMcmpZ can re-use the above instruction definitions.
3081 def : ARMPat<(ARMcmpZ GPR:$src, so_imm:$imm),
3082 (CMPri GPR:$src, so_imm:$imm)>;
3083 def : ARMPat<(ARMcmpZ GPR:$src, GPR:$rhs),
3084 (CMPrr GPR:$src, GPR:$rhs)>;
3085 def : ARMPat<(ARMcmpZ GPR:$src, so_reg:$rhs),
3086 (CMPrs GPR:$src, so_reg:$rhs)>;
3088 // FIXME: We have to be careful when using the CMN instruction and comparison
3089 // with 0. One would expect these two pieces of code should give identical
3105 // However, the CMN gives the *opposite* result when r1 is 0. This is because
3106 // the carry flag is set in the CMP case but not in the CMN case. In short, the
3107 // CMP instruction doesn't perform a truncate of the (logical) NOT of 0 plus the
3108 // value of r0 and the carry bit (because the "carry bit" parameter to
3109 // AddWithCarry is defined as 1 in this case, the carry flag will always be set
3110 // when r0 >= 0). The CMN instruction doesn't perform a NOT of 0 so there is
3111 // never a "carry" when this AddWithCarry is performed (because the "carry bit"
3112 // parameter to AddWithCarry is defined as 0).
3114 // When x is 0 and unsigned:
3118 // ~x + 1 = 0x1 0000 0000
3119 // (-x = 0) != (0x1 0000 0000 = ~x + 1)
3121 // Therefore, we should disable CMN when comparing against zero, until we can
3122 // limit when the CMN instruction is used (when we know that the RHS is not 0 or
3123 // when it's a comparison which doesn't look at the 'carry' flag).
3125 // (See the ARM docs for the "AddWithCarry" pseudo-code.)
3127 // This is related to <rdar://problem/7569620>.
3129 //defm CMN : AI1_cmp_irs<0b1011, "cmn",
3130 // BinOpFrag<(ARMcmp node:$LHS,(ineg node:$RHS))>>;
3132 // Note that TST/TEQ don't set all the same flags that CMP does!
3133 defm TST : AI1_cmp_irs<0b1000, "tst",
3134 IIC_iTSTi, IIC_iTSTr, IIC_iTSTsr,
3135 BinOpFrag<(ARMcmpZ (and_su node:$LHS, node:$RHS), 0)>, 1>;
3136 defm TEQ : AI1_cmp_irs<0b1001, "teq",
3137 IIC_iTSTi, IIC_iTSTr, IIC_iTSTsr,
3138 BinOpFrag<(ARMcmpZ (xor_su node:$LHS, node:$RHS), 0)>, 1>;
3140 defm CMNz : AI1_cmp_irs<0b1011, "cmn",
3141 IIC_iCMPi, IIC_iCMPr, IIC_iCMPsr,
3142 BinOpFrag<(ARMcmpZ node:$LHS,(ineg node:$RHS))>>;
3144 //def : ARMPat<(ARMcmp GPR:$src, so_imm_neg:$imm),
3145 // (CMNri GPR:$src, so_imm_neg:$imm)>;
3147 def : ARMPat<(ARMcmpZ GPR:$src, so_imm_neg:$imm),
3148 (CMNzri GPR:$src, so_imm_neg:$imm)>;
3150 // Pseudo i64 compares for some floating point compares.
3151 let usesCustomInserter = 1, isBranch = 1, isTerminator = 1,
3153 def BCCi64 : PseudoInst<(outs),
3154 (ins i32imm:$cc, GPR:$lhs1, GPR:$lhs2, GPR:$rhs1, GPR:$rhs2, brtarget:$dst),
3156 [(ARMBcci64 imm:$cc, GPR:$lhs1, GPR:$lhs2, GPR:$rhs1, GPR:$rhs2, bb:$dst)]>;
3158 def BCCZi64 : PseudoInst<(outs),
3159 (ins i32imm:$cc, GPR:$lhs1, GPR:$lhs2, brtarget:$dst), IIC_Br,
3160 [(ARMBcci64 imm:$cc, GPR:$lhs1, GPR:$lhs2, 0, 0, bb:$dst)]>;
3161 } // usesCustomInserter
3164 // Conditional moves
3165 // FIXME: should be able to write a pattern for ARMcmov, but can't use
3166 // a two-value operand where a dag node expects two operands. :(
3167 let neverHasSideEffects = 1 in {
3168 def MOVCCr : ARMPseudoInst<(outs GPR:$Rd), (ins GPR:$false, GPR:$Rm, pred:$p),
3169 Size4Bytes, IIC_iCMOVr,
3170 [/*(set GPR:$Rd, (ARMcmov GPR:$false, GPR:$Rm, imm:$cc, CCR:$ccr))*/]>,
3171 RegConstraint<"$false = $Rd">;
3172 def MOVCCs : ARMPseudoInst<(outs GPR:$Rd),
3173 (ins GPR:$false, so_reg:$shift, pred:$p),
3174 Size4Bytes, IIC_iCMOVsr,
3175 [/*(set GPR:$Rd, (ARMcmov GPR:$false, so_reg:$shift, imm:$cc, CCR:$ccr))*/]>,
3176 RegConstraint<"$false = $Rd">;
3178 let isMoveImm = 1 in
3179 def MOVCCi16 : ARMPseudoInst<(outs GPR:$Rd),
3180 (ins GPR:$false, i32imm_hilo16:$imm, pred:$p),
3181 Size4Bytes, IIC_iMOVi,
3183 RegConstraint<"$false = $Rd">, Requires<[IsARM, HasV6T2]>;
3185 let isMoveImm = 1 in
3186 def MOVCCi : ARMPseudoInst<(outs GPR:$Rd),
3187 (ins GPR:$false, so_imm:$imm, pred:$p),
3188 Size4Bytes, IIC_iCMOVi,
3189 [/*(set GPR:$Rd, (ARMcmov GPR:$false, so_imm:$imm, imm:$cc, CCR:$ccr))*/]>,
3190 RegConstraint<"$false = $Rd">;
3192 // Two instruction predicate mov immediate.
3193 let isMoveImm = 1 in
3194 def MOVCCi32imm : ARMPseudoInst<(outs GPR:$Rd),
3195 (ins GPR:$false, i32imm:$src, pred:$p),
3196 Size8Bytes, IIC_iCMOVix2, []>, RegConstraint<"$false = $Rd">;
3198 let isMoveImm = 1 in
3199 def MVNCCi : ARMPseudoInst<(outs GPR:$Rd),
3200 (ins GPR:$false, so_imm:$imm, pred:$p),
3201 Size4Bytes, IIC_iCMOVi,
3202 [/*(set GPR:$Rd, (ARMcmov GPR:$false, so_imm_not:$imm, imm:$cc, CCR:$ccr))*/]>,
3203 RegConstraint<"$false = $Rd">;
3204 } // neverHasSideEffects
3206 //===----------------------------------------------------------------------===//
3207 // Atomic operations intrinsics
3210 def memb_opt : Operand<i32> {
3211 let PrintMethod = "printMemBOption";
3212 let ParserMatchClass = MemBarrierOptOperand;
3215 // memory barriers protect the atomic sequences
3216 let hasSideEffects = 1 in {
3217 def DMB : AInoP<(outs), (ins memb_opt:$opt), MiscFrm, NoItinerary,
3218 "dmb", "\t$opt", [(ARMMemBarrier (i32 imm:$opt))]>,
3219 Requires<[IsARM, HasDB]> {
3221 let Inst{31-4} = 0xf57ff05;
3222 let Inst{3-0} = opt;
3226 def DSB : AInoP<(outs), (ins memb_opt:$opt), MiscFrm, NoItinerary,
3228 [/* For disassembly only; pattern left blank */]>,
3229 Requires<[IsARM, HasDB]> {
3231 let Inst{31-4} = 0xf57ff04;
3232 let Inst{3-0} = opt;
3235 // ISB has only full system option -- for disassembly only
3236 def ISB : AInoP<(outs), (ins), MiscFrm, NoItinerary, "isb", "", []>,
3237 Requires<[IsARM, HasDB]> {
3238 let Inst{31-4} = 0xf57ff06;
3239 let Inst{3-0} = 0b1111;
3242 let usesCustomInserter = 1 in {
3243 let Uses = [CPSR] in {
3244 def ATOMIC_LOAD_ADD_I8 : PseudoInst<
3245 (outs GPR:$dst), (ins GPR:$ptr, GPR:$incr), NoItinerary,
3246 [(set GPR:$dst, (atomic_load_add_8 GPR:$ptr, GPR:$incr))]>;
3247 def ATOMIC_LOAD_SUB_I8 : PseudoInst<
3248 (outs GPR:$dst), (ins GPR:$ptr, GPR:$incr), NoItinerary,
3249 [(set GPR:$dst, (atomic_load_sub_8 GPR:$ptr, GPR:$incr))]>;
3250 def ATOMIC_LOAD_AND_I8 : PseudoInst<
3251 (outs GPR:$dst), (ins GPR:$ptr, GPR:$incr), NoItinerary,
3252 [(set GPR:$dst, (atomic_load_and_8 GPR:$ptr, GPR:$incr))]>;
3253 def ATOMIC_LOAD_OR_I8 : PseudoInst<
3254 (outs GPR:$dst), (ins GPR:$ptr, GPR:$incr), NoItinerary,
3255 [(set GPR:$dst, (atomic_load_or_8 GPR:$ptr, GPR:$incr))]>;
3256 def ATOMIC_LOAD_XOR_I8 : PseudoInst<
3257 (outs GPR:$dst), (ins GPR:$ptr, GPR:$incr), NoItinerary,
3258 [(set GPR:$dst, (atomic_load_xor_8 GPR:$ptr, GPR:$incr))]>;
3259 def ATOMIC_LOAD_NAND_I8 : PseudoInst<
3260 (outs GPR:$dst), (ins GPR:$ptr, GPR:$incr), NoItinerary,
3261 [(set GPR:$dst, (atomic_load_nand_8 GPR:$ptr, GPR:$incr))]>;
3262 def ATOMIC_LOAD_ADD_I16 : PseudoInst<
3263 (outs GPR:$dst), (ins GPR:$ptr, GPR:$incr), NoItinerary,
3264 [(set GPR:$dst, (atomic_load_add_16 GPR:$ptr, GPR:$incr))]>;
3265 def ATOMIC_LOAD_SUB_I16 : PseudoInst<
3266 (outs GPR:$dst), (ins GPR:$ptr, GPR:$incr), NoItinerary,
3267 [(set GPR:$dst, (atomic_load_sub_16 GPR:$ptr, GPR:$incr))]>;
3268 def ATOMIC_LOAD_AND_I16 : PseudoInst<
3269 (outs GPR:$dst), (ins GPR:$ptr, GPR:$incr), NoItinerary,
3270 [(set GPR:$dst, (atomic_load_and_16 GPR:$ptr, GPR:$incr))]>;
3271 def ATOMIC_LOAD_OR_I16 : PseudoInst<
3272 (outs GPR:$dst), (ins GPR:$ptr, GPR:$incr), NoItinerary,
3273 [(set GPR:$dst, (atomic_load_or_16 GPR:$ptr, GPR:$incr))]>;
3274 def ATOMIC_LOAD_XOR_I16 : PseudoInst<
3275 (outs GPR:$dst), (ins GPR:$ptr, GPR:$incr), NoItinerary,
3276 [(set GPR:$dst, (atomic_load_xor_16 GPR:$ptr, GPR:$incr))]>;
3277 def ATOMIC_LOAD_NAND_I16 : PseudoInst<
3278 (outs GPR:$dst), (ins GPR:$ptr, GPR:$incr), NoItinerary,
3279 [(set GPR:$dst, (atomic_load_nand_16 GPR:$ptr, GPR:$incr))]>;
3280 def ATOMIC_LOAD_ADD_I32 : PseudoInst<
3281 (outs GPR:$dst), (ins GPR:$ptr, GPR:$incr), NoItinerary,
3282 [(set GPR:$dst, (atomic_load_add_32 GPR:$ptr, GPR:$incr))]>;
3283 def ATOMIC_LOAD_SUB_I32 : PseudoInst<
3284 (outs GPR:$dst), (ins GPR:$ptr, GPR:$incr), NoItinerary,
3285 [(set GPR:$dst, (atomic_load_sub_32 GPR:$ptr, GPR:$incr))]>;
3286 def ATOMIC_LOAD_AND_I32 : PseudoInst<
3287 (outs GPR:$dst), (ins GPR:$ptr, GPR:$incr), NoItinerary,
3288 [(set GPR:$dst, (atomic_load_and_32 GPR:$ptr, GPR:$incr))]>;
3289 def ATOMIC_LOAD_OR_I32 : PseudoInst<
3290 (outs GPR:$dst), (ins GPR:$ptr, GPR:$incr), NoItinerary,
3291 [(set GPR:$dst, (atomic_load_or_32 GPR:$ptr, GPR:$incr))]>;
3292 def ATOMIC_LOAD_XOR_I32 : PseudoInst<
3293 (outs GPR:$dst), (ins GPR:$ptr, GPR:$incr), NoItinerary,
3294 [(set GPR:$dst, (atomic_load_xor_32 GPR:$ptr, GPR:$incr))]>;
3295 def ATOMIC_LOAD_NAND_I32 : PseudoInst<
3296 (outs GPR:$dst), (ins GPR:$ptr, GPR:$incr), NoItinerary,
3297 [(set GPR:$dst, (atomic_load_nand_32 GPR:$ptr, GPR:$incr))]>;
3299 def ATOMIC_SWAP_I8 : PseudoInst<
3300 (outs GPR:$dst), (ins GPR:$ptr, GPR:$new), NoItinerary,
3301 [(set GPR:$dst, (atomic_swap_8 GPR:$ptr, GPR:$new))]>;
3302 def ATOMIC_SWAP_I16 : PseudoInst<
3303 (outs GPR:$dst), (ins GPR:$ptr, GPR:$new), NoItinerary,
3304 [(set GPR:$dst, (atomic_swap_16 GPR:$ptr, GPR:$new))]>;
3305 def ATOMIC_SWAP_I32 : PseudoInst<
3306 (outs GPR:$dst), (ins GPR:$ptr, GPR:$new), NoItinerary,
3307 [(set GPR:$dst, (atomic_swap_32 GPR:$ptr, GPR:$new))]>;
3309 def ATOMIC_CMP_SWAP_I8 : PseudoInst<
3310 (outs GPR:$dst), (ins GPR:$ptr, GPR:$old, GPR:$new), NoItinerary,
3311 [(set GPR:$dst, (atomic_cmp_swap_8 GPR:$ptr, GPR:$old, GPR:$new))]>;
3312 def ATOMIC_CMP_SWAP_I16 : PseudoInst<
3313 (outs GPR:$dst), (ins GPR:$ptr, GPR:$old, GPR:$new), NoItinerary,
3314 [(set GPR:$dst, (atomic_cmp_swap_16 GPR:$ptr, GPR:$old, GPR:$new))]>;
3315 def ATOMIC_CMP_SWAP_I32 : PseudoInst<
3316 (outs GPR:$dst), (ins GPR:$ptr, GPR:$old, GPR:$new), NoItinerary,
3317 [(set GPR:$dst, (atomic_cmp_swap_32 GPR:$ptr, GPR:$old, GPR:$new))]>;
3321 let mayLoad = 1 in {
3322 def LDREXB : AIldrex<0b10, (outs GPR:$Rt), (ins addrmode7:$addr), NoItinerary,
3323 "ldrexb", "\t$Rt, $addr", []>;
3324 def LDREXH : AIldrex<0b11, (outs GPR:$Rt), (ins addrmode7:$addr), NoItinerary,
3325 "ldrexh", "\t$Rt, $addr", []>;
3326 def LDREX : AIldrex<0b00, (outs GPR:$Rt), (ins addrmode7:$addr), NoItinerary,
3327 "ldrex", "\t$Rt, $addr", []>;
3328 def LDREXD : AIldrex<0b01, (outs GPR:$Rt, GPR:$Rt2), (ins addrmode7:$addr),
3329 NoItinerary, "ldrexd", "\t$Rt, $Rt2, $addr", []>;
3332 let mayStore = 1, Constraints = "@earlyclobber $Rd" in {
3333 def STREXB : AIstrex<0b10, (outs GPR:$Rd), (ins GPR:$Rt, addrmode7:$addr),
3334 NoItinerary, "strexb", "\t$Rd, $Rt, $addr", []>;
3335 def STREXH : AIstrex<0b11, (outs GPR:$Rd), (ins GPR:$Rt, addrmode7:$addr),
3336 NoItinerary, "strexh", "\t$Rd, $Rt, $addr", []>;
3337 def STREX : AIstrex<0b00, (outs GPR:$Rd), (ins GPR:$Rt, addrmode7:$addr),
3338 NoItinerary, "strex", "\t$Rd, $Rt, $addr", []>;
3339 def STREXD : AIstrex<0b01, (outs GPR:$Rd),
3340 (ins GPR:$Rt, GPR:$Rt2, addrmode7:$addr),
3341 NoItinerary, "strexd", "\t$Rd, $Rt, $Rt2, $addr", []>;
3344 // Clear-Exclusive is for disassembly only.
3345 def CLREX : AXI<(outs), (ins), MiscFrm, NoItinerary, "clrex",
3346 [/* For disassembly only; pattern left blank */]>,
3347 Requires<[IsARM, HasV7]> {
3348 let Inst{31-0} = 0b11110101011111111111000000011111;
3351 // SWP/SWPB are deprecated in V6/V7 and for disassembly only.
3352 let mayLoad = 1 in {
3353 def SWP : AIswp<0, (outs GPR:$Rt), (ins GPR:$Rt2, GPR:$Rn), "swp",
3354 [/* For disassembly only; pattern left blank */]>;
3355 def SWPB : AIswp<1, (outs GPR:$Rt), (ins GPR:$Rt2, GPR:$Rn), "swpb",
3356 [/* For disassembly only; pattern left blank */]>;
3359 //===----------------------------------------------------------------------===//
3360 // Coprocessor Instructions.
3363 def CDP : ABI<0b1110, (outs), (ins p_imm:$cop, i32imm:$opc1,
3364 c_imm:$CRd, c_imm:$CRn, c_imm:$CRm, i32imm:$opc2),
3365 NoItinerary, "cdp", "\t$cop, $opc1, $CRd, $CRn, $CRm, $opc2",
3366 [/* For disassembly only; pattern left blank */]> {
3374 let Inst{3-0} = CRm;
3376 let Inst{7-5} = opc2;
3377 let Inst{11-8} = cop;
3378 let Inst{15-12} = CRd;
3379 let Inst{19-16} = CRn;
3380 let Inst{23-20} = opc1;
3383 def CDP2 : ABXI<0b1110, (outs), (ins p_imm:$cop, i32imm:$opc1,
3384 c_imm:$CRd, c_imm:$CRn, c_imm:$CRm, i32imm:$opc2),
3385 NoItinerary, "cdp2\t$cop, $opc1, $CRd, $CRn, $CRm, $opc2",
3386 [/* For disassembly only; pattern left blank */]> {
3387 let Inst{31-28} = 0b1111;
3395 let Inst{3-0} = CRm;
3397 let Inst{7-5} = opc2;
3398 let Inst{11-8} = cop;
3399 let Inst{15-12} = CRd;
3400 let Inst{19-16} = CRn;
3401 let Inst{23-20} = opc1;
3404 class ACI<dag oops, dag iops, string opc, string asm>
3405 : I<oops, iops, AddrModeNone, Size4Bytes, IndexModeNone, BrFrm, NoItinerary,
3406 opc, asm, "", [/* For disassembly only; pattern left blank */]> {
3407 let Inst{27-25} = 0b110;
3410 multiclass LdStCop<bits<4> op31_28, bit load, string opc> {
3412 def _OFFSET : ACI<(outs),
3413 (ins nohash_imm:$cop, nohash_imm:$CRd, addrmode2:$addr),
3414 opc, "\tp$cop, cr$CRd, $addr"> {
3415 let Inst{31-28} = op31_28;
3416 let Inst{24} = 1; // P = 1
3417 let Inst{21} = 0; // W = 0
3418 let Inst{22} = 0; // D = 0
3419 let Inst{20} = load;
3422 def _PRE : ACI<(outs),
3423 (ins nohash_imm:$cop, nohash_imm:$CRd, addrmode2:$addr),
3424 opc, "\tp$cop, cr$CRd, $addr!"> {
3425 let Inst{31-28} = op31_28;
3426 let Inst{24} = 1; // P = 1
3427 let Inst{21} = 1; // W = 1
3428 let Inst{22} = 0; // D = 0
3429 let Inst{20} = load;
3432 def _POST : ACI<(outs),
3433 (ins nohash_imm:$cop, nohash_imm:$CRd, GPR:$base, am2offset:$offset),
3434 opc, "\tp$cop, cr$CRd, [$base], $offset"> {
3435 let Inst{31-28} = op31_28;
3436 let Inst{24} = 0; // P = 0
3437 let Inst{21} = 1; // W = 1
3438 let Inst{22} = 0; // D = 0
3439 let Inst{20} = load;
3442 def _OPTION : ACI<(outs),
3443 (ins nohash_imm:$cop, nohash_imm:$CRd, GPR:$base, nohash_imm:$option),
3444 opc, "\tp$cop, cr$CRd, [$base], \\{$option\\}"> {
3445 let Inst{31-28} = op31_28;
3446 let Inst{24} = 0; // P = 0
3447 let Inst{23} = 1; // U = 1
3448 let Inst{21} = 0; // W = 0
3449 let Inst{22} = 0; // D = 0
3450 let Inst{20} = load;
3453 def L_OFFSET : ACI<(outs),
3454 (ins nohash_imm:$cop, nohash_imm:$CRd, addrmode2:$addr),
3455 !strconcat(opc, "l"), "\tp$cop, cr$CRd, $addr"> {
3456 let Inst{31-28} = op31_28;
3457 let Inst{24} = 1; // P = 1
3458 let Inst{21} = 0; // W = 0
3459 let Inst{22} = 1; // D = 1
3460 let Inst{20} = load;
3463 def L_PRE : ACI<(outs),
3464 (ins nohash_imm:$cop, nohash_imm:$CRd, addrmode2:$addr),
3465 !strconcat(opc, "l"), "\tp$cop, cr$CRd, $addr!"> {
3466 let Inst{31-28} = op31_28;
3467 let Inst{24} = 1; // P = 1
3468 let Inst{21} = 1; // W = 1
3469 let Inst{22} = 1; // D = 1
3470 let Inst{20} = load;
3473 def L_POST : ACI<(outs),
3474 (ins nohash_imm:$cop, nohash_imm:$CRd, GPR:$base, am2offset:$offset),
3475 !strconcat(opc, "l"), "\tp$cop, cr$CRd, [$base], $offset"> {
3476 let Inst{31-28} = op31_28;
3477 let Inst{24} = 0; // P = 0
3478 let Inst{21} = 1; // W = 1
3479 let Inst{22} = 1; // D = 1
3480 let Inst{20} = load;
3483 def L_OPTION : ACI<(outs),
3484 (ins nohash_imm:$cop, nohash_imm:$CRd, GPR:$base, nohash_imm:$option),
3485 !strconcat(opc, "l"), "\tp$cop, cr$CRd, [$base], \\{$option\\}"> {
3486 let Inst{31-28} = op31_28;
3487 let Inst{24} = 0; // P = 0
3488 let Inst{23} = 1; // U = 1
3489 let Inst{21} = 0; // W = 0
3490 let Inst{22} = 1; // D = 1
3491 let Inst{20} = load;
3495 defm LDC : LdStCop<{?,?,?,?}, 1, "ldc">;
3496 defm LDC2 : LdStCop<0b1111, 1, "ldc2">;
3497 defm STC : LdStCop<{?,?,?,?}, 0, "stc">;
3498 defm STC2 : LdStCop<0b1111, 0, "stc2">;
3500 //===----------------------------------------------------------------------===//
3501 // Move between coprocessor and ARM core register -- for disassembly only
3504 class MovRCopro<string opc, bit direction, dag oops, dag iops>
3505 : ABI<0b1110, oops, iops, NoItinerary, opc,
3506 "\t$cop, $opc1, $Rt, $CRn, $CRm, $opc2",
3507 [/* For disassembly only; pattern left blank */]> {
3508 let Inst{20} = direction;
3518 let Inst{15-12} = Rt;
3519 let Inst{11-8} = cop;
3520 let Inst{23-21} = opc1;
3521 let Inst{7-5} = opc2;
3522 let Inst{3-0} = CRm;
3523 let Inst{19-16} = CRn;
3526 def MCR : MovRCopro<"mcr", 0 /* from ARM core register to coprocessor */,
3527 (outs), (ins p_imm:$cop, i32imm:$opc1,
3528 GPR:$Rt, c_imm:$CRn, c_imm:$CRm,
3530 def MRC : MovRCopro<"mrc", 1 /* from coprocessor to ARM core register */,
3531 (outs GPR:$Rt), (ins p_imm:$cop, i32imm:$opc1,
3532 c_imm:$CRn, c_imm:$CRm, i32imm:$opc2)>;
3534 class MovRCopro2<string opc, bit direction, dag oops, dag iops>
3535 : ABXI<0b1110, oops, iops, NoItinerary,
3536 !strconcat(opc, "\t$cop, $opc1, $Rt, $CRn, $CRm, $opc2"),
3537 [/* For disassembly only; pattern left blank */]> {
3538 let Inst{31-28} = 0b1111;
3539 let Inst{20} = direction;
3549 let Inst{15-12} = Rt;
3550 let Inst{11-8} = cop;
3551 let Inst{23-21} = opc1;
3552 let Inst{7-5} = opc2;
3553 let Inst{3-0} = CRm;
3554 let Inst{19-16} = CRn;
3557 def MCR2 : MovRCopro2<"mcr2", 0 /* from ARM core register to coprocessor */,
3558 (outs), (ins p_imm:$cop, i32imm:$opc1,
3559 GPR:$Rt, c_imm:$CRn, c_imm:$CRm,
3561 def MRC2 : MovRCopro2<"mrc2", 1 /* from coprocessor to ARM core register */,
3562 (outs GPR:$Rt), (ins p_imm:$cop, i32imm:$opc1,
3563 c_imm:$CRn, c_imm:$CRm,
3566 class MovRRCopro<string opc, bit direction>
3567 : ABI<0b1100, (outs), (ins p_imm:$cop, i32imm:$opc1,
3568 GPR:$Rt, GPR:$Rt2, c_imm:$CRm),
3569 NoItinerary, opc, "\t$cop, $opc1, $Rt, $Rt2, $CRm",
3570 [/* For disassembly only; pattern left blank */]> {
3571 let Inst{23-21} = 0b010;
3572 let Inst{20} = direction;
3580 let Inst{15-12} = Rt;
3581 let Inst{19-16} = Rt2;
3582 let Inst{11-8} = cop;
3583 let Inst{7-4} = opc1;
3584 let Inst{3-0} = CRm;
3587 def MCRR : MovRRCopro<"mcrr", 0 /* from ARM core register to coprocessor */>;
3588 def MRRC : MovRRCopro<"mrrc", 1 /* from coprocessor to ARM core register */>;
3590 class MovRRCopro2<string opc, bit direction>
3591 : ABXI<0b1100, (outs), (ins p_imm:$cop, i32imm:$opc1,
3592 GPR:$Rt, GPR:$Rt2, c_imm:$CRm),
3593 NoItinerary, !strconcat(opc, "\t$cop, $opc1, $Rt, $Rt2, $CRm"),
3594 [/* For disassembly only; pattern left blank */]> {
3595 let Inst{31-28} = 0b1111;
3596 let Inst{23-21} = 0b010;
3597 let Inst{20} = direction;
3605 let Inst{15-12} = Rt;
3606 let Inst{19-16} = Rt2;
3607 let Inst{11-8} = cop;
3608 let Inst{7-4} = opc1;
3609 let Inst{3-0} = CRm;
3612 def MCRR2 : MovRRCopro2<"mcrr2", 0 /* from ARM core register to coprocessor */>;
3613 def MRRC2 : MovRRCopro2<"mrrc2", 1 /* from coprocessor to ARM core register */>;
3615 //===----------------------------------------------------------------------===//
3616 // Move between special register and ARM core register -- for disassembly only
3619 // Move to ARM core register from Special Register
3620 def MRS : ABI<0b0001, (outs GPR:$Rd), (ins), NoItinerary, "mrs", "\t$Rd, cpsr",
3621 [/* For disassembly only; pattern left blank */]> {
3623 let Inst{23-16} = 0b00001111;
3624 let Inst{15-12} = Rd;
3625 let Inst{7-4} = 0b0000;
3628 def MRSsys : ABI<0b0001, (outs GPR:$Rd), (ins), NoItinerary,"mrs","\t$Rd, spsr",
3629 [/* For disassembly only; pattern left blank */]> {
3631 let Inst{23-16} = 0b01001111;
3632 let Inst{15-12} = Rd;
3633 let Inst{7-4} = 0b0000;
3636 // Move from ARM core register to Special Register
3638 // No need to have both system and application versions, the encodings are the
3639 // same and the assembly parser has no way to distinguish between them. The mask
3640 // operand contains the special register (R Bit) in bit 4 and bits 3-0 contains
3641 // the mask with the fields to be accessed in the special register.
3642 def MSR : ABI<0b0001, (outs), (ins msr_mask:$mask, GPR:$Rn), NoItinerary,
3643 "msr", "\t$mask, $Rn",
3644 [/* For disassembly only; pattern left blank */]> {
3649 let Inst{22} = mask{4}; // R bit
3650 let Inst{21-20} = 0b10;
3651 let Inst{19-16} = mask{3-0};
3652 let Inst{15-12} = 0b1111;
3653 let Inst{11-4} = 0b00000000;
3657 def MSRi : ABI<0b0011, (outs), (ins msr_mask:$mask, so_imm:$a), NoItinerary,
3658 "msr", "\t$mask, $a",
3659 [/* For disassembly only; pattern left blank */]> {
3664 let Inst{22} = mask{4}; // R bit
3665 let Inst{21-20} = 0b10;
3666 let Inst{19-16} = mask{3-0};
3667 let Inst{15-12} = 0b1111;
3671 //===----------------------------------------------------------------------===//
3675 // __aeabi_read_tp preserves the registers r1-r3.
3676 // This is a pseudo inst so that we can get the encoding right,
3677 // complete with fixup for the aeabi_read_tp function.
3679 Defs = [R0, R12, LR, CPSR], Uses = [SP] in {
3680 def TPsoft : PseudoInst<(outs), (ins), IIC_Br,
3681 [(set R0, ARMthread_pointer)]>;
3684 //===----------------------------------------------------------------------===//
3685 // SJLJ Exception handling intrinsics
3686 // eh_sjlj_setjmp() is an instruction sequence to store the return
3687 // address and save #0 in R0 for the non-longjmp case.
3688 // Since by its nature we may be coming from some other function to get
3689 // here, and we're using the stack frame for the containing function to
3690 // save/restore registers, we can't keep anything live in regs across
3691 // the eh_sjlj_setjmp(), else it will almost certainly have been tromped upon
3692 // when we get here from a longjmp(). We force everthing out of registers
3693 // except for our own input by listing the relevant registers in Defs. By
3694 // doing so, we also cause the prologue/epilogue code to actively preserve
3695 // all of the callee-saved resgisters, which is exactly what we want.
3696 // A constant value is passed in $val, and we use the location as a scratch.
3698 // These are pseudo-instructions and are lowered to individual MC-insts, so
3699 // no encoding information is necessary.
3701 [ R0, R1, R2, R3, R4, R5, R6, R7, R8, R9, R10, R11, R12, LR, D0,
3702 D1, D2, D3, D4, D5, D6, D7, D8, D9, D10, D11, D12, D13, D14, D15,
3703 D16, D17, D18, D19, D20, D21, D22, D23, D24, D25, D26, D27, D28, D29, D30,
3704 D31 ], hasSideEffects = 1, isBarrier = 1 in {
3705 def Int_eh_sjlj_setjmp : PseudoInst<(outs), (ins GPR:$src, GPR:$val),
3707 [(set R0, (ARMeh_sjlj_setjmp GPR:$src, GPR:$val))]>,
3708 Requires<[IsARM, HasVFP2]>;
3712 [ R0, R1, R2, R3, R4, R5, R6, R7, R8, R9, R10, R11, R12, LR ],
3713 hasSideEffects = 1, isBarrier = 1 in {
3714 def Int_eh_sjlj_setjmp_nofp : PseudoInst<(outs), (ins GPR:$src, GPR:$val),
3716 [(set R0, (ARMeh_sjlj_setjmp GPR:$src, GPR:$val))]>,
3717 Requires<[IsARM, NoVFP]>;
3720 // FIXME: Non-Darwin version(s)
3721 let isBarrier = 1, hasSideEffects = 1, isTerminator = 1,
3722 Defs = [ R7, LR, SP ] in {
3723 def Int_eh_sjlj_longjmp : PseudoInst<(outs), (ins GPR:$src, GPR:$scratch),
3725 [(ARMeh_sjlj_longjmp GPR:$src, GPR:$scratch)]>,
3726 Requires<[IsARM, IsDarwin]>;
3729 // eh.sjlj.dispatchsetup pseudo-instruction.
3730 // This pseudo is used for ARM, Thumb1 and Thumb2. Any differences are
3731 // handled when the pseudo is expanded (which happens before any passes
3732 // that need the instruction size).
3733 let isBarrier = 1, hasSideEffects = 1 in
3734 def Int_eh_sjlj_dispatchsetup :
3735 PseudoInst<(outs), (ins GPR:$src), NoItinerary,
3736 [(ARMeh_sjlj_dispatchsetup GPR:$src)]>,
3737 Requires<[IsDarwin]>;
3739 //===----------------------------------------------------------------------===//
3740 // Non-Instruction Patterns
3743 // Large immediate handling.
3745 // 32-bit immediate using two piece so_imms or movw + movt.
3746 // This is a single pseudo instruction, the benefit is that it can be remat'd
3747 // as a single unit instead of having to handle reg inputs.
3748 // FIXME: Remove this when we can do generalized remat.
3749 let isReMaterializable = 1, isMoveImm = 1 in
3750 def MOVi32imm : PseudoInst<(outs GPR:$dst), (ins i32imm:$src), IIC_iMOVix2,
3751 [(set GPR:$dst, (arm_i32imm:$src))]>,
3754 // Pseudo instruction that combines movw + movt + add pc (if PIC).
3755 // It also makes it possible to rematerialize the instructions.
3756 // FIXME: Remove this when we can do generalized remat and when machine licm
3757 // can properly the instructions.
3758 let isReMaterializable = 1 in {
3759 def MOV_ga_pcrel : PseudoInst<(outs GPR:$dst), (ins i32imm:$addr),
3761 [(set GPR:$dst, (ARMWrapperPIC tglobaladdr:$addr))]>,
3762 Requires<[IsARM, UseMovt]>;
3764 def MOV_ga_dyn : PseudoInst<(outs GPR:$dst), (ins i32imm:$addr),
3766 [(set GPR:$dst, (ARMWrapperDYN tglobaladdr:$addr))]>,
3767 Requires<[IsARM, UseMovt]>;
3769 let AddedComplexity = 10 in
3770 def MOV_ga_pcrel_ldr : PseudoInst<(outs GPR:$dst), (ins i32imm:$addr),
3772 [(set GPR:$dst, (load (ARMWrapperPIC tglobaladdr:$addr)))]>,
3773 Requires<[IsARM, UseMovt]>;
3774 } // isReMaterializable
3776 // ConstantPool, GlobalAddress, and JumpTable
3777 def : ARMPat<(ARMWrapper tglobaladdr :$dst), (LEApcrel tglobaladdr :$dst)>,
3778 Requires<[IsARM, DontUseMovt]>;
3779 def : ARMPat<(ARMWrapper tconstpool :$dst), (LEApcrel tconstpool :$dst)>;
3780 def : ARMPat<(ARMWrapper tglobaladdr :$dst), (MOVi32imm tglobaladdr :$dst)>,
3781 Requires<[IsARM, UseMovt]>;
3782 def : ARMPat<(ARMWrapperJT tjumptable:$dst, imm:$id),
3783 (LEApcrelJT tjumptable:$dst, imm:$id)>;
3785 // TODO: add,sub,and, 3-instr forms?
3788 def : ARMPat<(ARMtcret tcGPR:$dst),
3789 (TCRETURNri tcGPR:$dst)>, Requires<[IsDarwin]>;
3791 def : ARMPat<(ARMtcret (i32 tglobaladdr:$dst)),
3792 (TCRETURNdi texternalsym:$dst)>, Requires<[IsDarwin]>;
3794 def : ARMPat<(ARMtcret (i32 texternalsym:$dst)),
3795 (TCRETURNdi texternalsym:$dst)>, Requires<[IsDarwin]>;
3797 def : ARMPat<(ARMtcret tcGPR:$dst),
3798 (TCRETURNriND tcGPR:$dst)>, Requires<[IsNotDarwin]>;
3800 def : ARMPat<(ARMtcret (i32 tglobaladdr:$dst)),
3801 (TCRETURNdiND texternalsym:$dst)>, Requires<[IsNotDarwin]>;
3803 def : ARMPat<(ARMtcret (i32 texternalsym:$dst)),
3804 (TCRETURNdiND texternalsym:$dst)>, Requires<[IsNotDarwin]>;
3807 def : ARMPat<(ARMcall texternalsym:$func), (BL texternalsym:$func)>,
3808 Requires<[IsARM, IsNotDarwin]>;
3809 def : ARMPat<(ARMcall texternalsym:$func), (BLr9 texternalsym:$func)>,
3810 Requires<[IsARM, IsDarwin]>;
3812 // zextload i1 -> zextload i8
3813 def : ARMPat<(zextloadi1 addrmode_imm12:$addr), (LDRBi12 addrmode_imm12:$addr)>;
3814 def : ARMPat<(zextloadi1 ldst_so_reg:$addr), (LDRBrs ldst_so_reg:$addr)>;
3816 // extload -> zextload
3817 def : ARMPat<(extloadi1 addrmode_imm12:$addr), (LDRBi12 addrmode_imm12:$addr)>;
3818 def : ARMPat<(extloadi1 ldst_so_reg:$addr), (LDRBrs ldst_so_reg:$addr)>;
3819 def : ARMPat<(extloadi8 addrmode_imm12:$addr), (LDRBi12 addrmode_imm12:$addr)>;
3820 def : ARMPat<(extloadi8 ldst_so_reg:$addr), (LDRBrs ldst_so_reg:$addr)>;
3822 def : ARMPat<(extloadi16 addrmode3:$addr), (LDRH addrmode3:$addr)>;
3824 def : ARMPat<(extloadi8 addrmodepc:$addr), (PICLDRB addrmodepc:$addr)>;
3825 def : ARMPat<(extloadi16 addrmodepc:$addr), (PICLDRH addrmodepc:$addr)>;
3828 def : ARMV5TEPat<(mul (sra (shl GPR:$a, (i32 16)), (i32 16)),
3829 (sra (shl GPR:$b, (i32 16)), (i32 16))),
3830 (SMULBB GPR:$a, GPR:$b)>;
3831 def : ARMV5TEPat<(mul sext_16_node:$a, sext_16_node:$b),
3832 (SMULBB GPR:$a, GPR:$b)>;
3833 def : ARMV5TEPat<(mul (sra (shl GPR:$a, (i32 16)), (i32 16)),
3834 (sra GPR:$b, (i32 16))),
3835 (SMULBT GPR:$a, GPR:$b)>;
3836 def : ARMV5TEPat<(mul sext_16_node:$a, (sra GPR:$b, (i32 16))),
3837 (SMULBT GPR:$a, GPR:$b)>;
3838 def : ARMV5TEPat<(mul (sra GPR:$a, (i32 16)),
3839 (sra (shl GPR:$b, (i32 16)), (i32 16))),
3840 (SMULTB GPR:$a, GPR:$b)>;
3841 def : ARMV5TEPat<(mul (sra GPR:$a, (i32 16)), sext_16_node:$b),
3842 (SMULTB GPR:$a, GPR:$b)>;
3843 def : ARMV5TEPat<(sra (mul GPR:$a, (sra (shl GPR:$b, (i32 16)), (i32 16))),
3845 (SMULWB GPR:$a, GPR:$b)>;
3846 def : ARMV5TEPat<(sra (mul GPR:$a, sext_16_node:$b), (i32 16)),
3847 (SMULWB GPR:$a, GPR:$b)>;
3849 def : ARMV5TEPat<(add GPR:$acc,
3850 (mul (sra (shl GPR:$a, (i32 16)), (i32 16)),
3851 (sra (shl GPR:$b, (i32 16)), (i32 16)))),
3852 (SMLABB GPR:$a, GPR:$b, GPR:$acc)>;
3853 def : ARMV5TEPat<(add GPR:$acc,
3854 (mul sext_16_node:$a, sext_16_node:$b)),
3855 (SMLABB GPR:$a, GPR:$b, GPR:$acc)>;
3856 def : ARMV5TEPat<(add GPR:$acc,
3857 (mul (sra (shl GPR:$a, (i32 16)), (i32 16)),
3858 (sra GPR:$b, (i32 16)))),
3859 (SMLABT GPR:$a, GPR:$b, GPR:$acc)>;
3860 def : ARMV5TEPat<(add GPR:$acc,
3861 (mul sext_16_node:$a, (sra GPR:$b, (i32 16)))),
3862 (SMLABT GPR:$a, GPR:$b, GPR:$acc)>;
3863 def : ARMV5TEPat<(add GPR:$acc,
3864 (mul (sra GPR:$a, (i32 16)),
3865 (sra (shl GPR:$b, (i32 16)), (i32 16)))),
3866 (SMLATB GPR:$a, GPR:$b, GPR:$acc)>;
3867 def : ARMV5TEPat<(add GPR:$acc,
3868 (mul (sra GPR:$a, (i32 16)), sext_16_node:$b)),
3869 (SMLATB GPR:$a, GPR:$b, GPR:$acc)>;
3870 def : ARMV5TEPat<(add GPR:$acc,
3871 (sra (mul GPR:$a, (sra (shl GPR:$b, (i32 16)), (i32 16))),
3873 (SMLAWB GPR:$a, GPR:$b, GPR:$acc)>;
3874 def : ARMV5TEPat<(add GPR:$acc,
3875 (sra (mul GPR:$a, sext_16_node:$b), (i32 16))),
3876 (SMLAWB GPR:$a, GPR:$b, GPR:$acc)>;
3879 // Pre-v7 uses MCR for synchronization barriers.
3880 def : ARMPat<(ARMMemBarrierMCR GPR:$zero), (MCR 15, 0, GPR:$zero, 7, 10, 5)>,
3881 Requires<[IsARM, HasV6]>;
3884 //===----------------------------------------------------------------------===//
3888 include "ARMInstrThumb.td"
3890 //===----------------------------------------------------------------------===//
3894 include "ARMInstrThumb2.td"
3896 //===----------------------------------------------------------------------===//
3897 // Floating Point Support
3900 include "ARMInstrVFP.td"
3902 //===----------------------------------------------------------------------===//
3903 // Advanced SIMD (NEON) Support
3906 include "ARMInstrNEON.td"