1 //===- ARMInstrInfo.td - Target Description for ARM Target -*- tablegen -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file describes the ARM instructions in TableGen format.
12 //===----------------------------------------------------------------------===//
14 //===----------------------------------------------------------------------===//
15 // ARM specific DAG Nodes.
19 def SDT_ARMCallSeqStart : SDCallSeqStart<[ SDTCisVT<0, i32> ]>;
20 def SDT_ARMCallSeqEnd : SDCallSeqEnd<[ SDTCisVT<0, i32>, SDTCisVT<1, i32> ]>;
22 def SDT_ARMSaveCallPC : SDTypeProfile<0, 1, []>;
24 def SDT_ARMcall : SDTypeProfile<0, -1, [SDTCisPtrTy<0>]>;
26 def SDT_ARMCMov : SDTypeProfile<1, 3,
27 [SDTCisSameAs<0, 1>, SDTCisSameAs<0, 2>,
30 def SDT_ARMBrcond : SDTypeProfile<0, 2,
31 [SDTCisVT<0, OtherVT>, SDTCisVT<1, i32>]>;
33 def SDT_ARMBrJT : SDTypeProfile<0, 3,
34 [SDTCisPtrTy<0>, SDTCisVT<1, i32>,
37 def SDT_ARMBr2JT : SDTypeProfile<0, 4,
38 [SDTCisPtrTy<0>, SDTCisVT<1, i32>,
39 SDTCisVT<2, i32>, SDTCisVT<3, i32>]>;
41 def SDT_ARMBCC_i64 : SDTypeProfile<0, 6,
43 SDTCisVT<1, i32>, SDTCisVT<2, i32>,
44 SDTCisVT<3, i32>, SDTCisVT<4, i32>,
45 SDTCisVT<5, OtherVT>]>;
47 def SDT_ARMAnd : SDTypeProfile<1, 2,
48 [SDTCisVT<0, i32>, SDTCisVT<1, i32>,
51 def SDT_ARMCmp : SDTypeProfile<0, 2, [SDTCisSameAs<0, 1>]>;
53 def SDT_ARMPICAdd : SDTypeProfile<1, 2, [SDTCisSameAs<0, 1>,
54 SDTCisPtrTy<1>, SDTCisVT<2, i32>]>;
56 def SDT_ARMThreadPointer : SDTypeProfile<1, 0, [SDTCisPtrTy<0>]>;
57 def SDT_ARMEH_SJLJ_Setjmp : SDTypeProfile<1, 2, [SDTCisInt<0>, SDTCisPtrTy<1>,
59 def SDT_ARMEH_SJLJ_Longjmp: SDTypeProfile<0, 2, [SDTCisPtrTy<0>, SDTCisInt<1>]>;
61 def SDT_ARMEH_SJLJ_DispatchSetup: SDTypeProfile<0, 1, [SDTCisPtrTy<0>]>;
63 def SDT_ARMMEMBARRIER : SDTypeProfile<0, 1, [SDTCisInt<0>]>;
65 def SDT_ARMTCRET : SDTypeProfile<0, 1, [SDTCisPtrTy<0>]>;
67 def SDT_ARMBFI : SDTypeProfile<1, 3, [SDTCisVT<0, i32>, SDTCisVT<1, i32>,
68 SDTCisVT<2, i32>, SDTCisVT<3, i32>]>;
71 def ARMWrapper : SDNode<"ARMISD::Wrapper", SDTIntUnaryOp>;
72 def ARMWrapperJT : SDNode<"ARMISD::WrapperJT", SDTIntBinOp>;
74 def ARMcallseq_start : SDNode<"ISD::CALLSEQ_START", SDT_ARMCallSeqStart,
75 [SDNPHasChain, SDNPOutFlag]>;
76 def ARMcallseq_end : SDNode<"ISD::CALLSEQ_END", SDT_ARMCallSeqEnd,
77 [SDNPHasChain, SDNPOptInFlag, SDNPOutFlag]>;
79 def ARMcall : SDNode<"ARMISD::CALL", SDT_ARMcall,
80 [SDNPHasChain, SDNPOptInFlag, SDNPOutFlag,
82 def ARMcall_pred : SDNode<"ARMISD::CALL_PRED", SDT_ARMcall,
83 [SDNPHasChain, SDNPOptInFlag, SDNPOutFlag,
85 def ARMcall_nolink : SDNode<"ARMISD::CALL_NOLINK", SDT_ARMcall,
86 [SDNPHasChain, SDNPOptInFlag, SDNPOutFlag,
89 def ARMretflag : SDNode<"ARMISD::RET_FLAG", SDTNone,
90 [SDNPHasChain, SDNPOptInFlag]>;
92 def ARMcmov : SDNode<"ARMISD::CMOV", SDT_ARMCMov,
94 def ARMcneg : SDNode<"ARMISD::CNEG", SDT_ARMCMov,
97 def ARMbrcond : SDNode<"ARMISD::BRCOND", SDT_ARMBrcond,
98 [SDNPHasChain, SDNPInFlag, SDNPOutFlag]>;
100 def ARMbrjt : SDNode<"ARMISD::BR_JT", SDT_ARMBrJT,
102 def ARMbr2jt : SDNode<"ARMISD::BR2_JT", SDT_ARMBr2JT,
105 def ARMBcci64 : SDNode<"ARMISD::BCC_i64", SDT_ARMBCC_i64,
108 def ARMcmp : SDNode<"ARMISD::CMP", SDT_ARMCmp,
111 def ARMcmpZ : SDNode<"ARMISD::CMPZ", SDT_ARMCmp,
112 [SDNPOutFlag, SDNPCommutative]>;
114 def ARMpic_add : SDNode<"ARMISD::PIC_ADD", SDT_ARMPICAdd>;
116 def ARMsrl_flag : SDNode<"ARMISD::SRL_FLAG", SDTIntUnaryOp, [SDNPOutFlag]>;
117 def ARMsra_flag : SDNode<"ARMISD::SRA_FLAG", SDTIntUnaryOp, [SDNPOutFlag]>;
118 def ARMrrx : SDNode<"ARMISD::RRX" , SDTIntUnaryOp, [SDNPInFlag ]>;
120 def ARMthread_pointer: SDNode<"ARMISD::THREAD_POINTER", SDT_ARMThreadPointer>;
121 def ARMeh_sjlj_setjmp: SDNode<"ARMISD::EH_SJLJ_SETJMP",
122 SDT_ARMEH_SJLJ_Setjmp, [SDNPHasChain]>;
123 def ARMeh_sjlj_longjmp: SDNode<"ARMISD::EH_SJLJ_LONGJMP",
124 SDT_ARMEH_SJLJ_Longjmp, [SDNPHasChain]>;
125 def ARMeh_sjlj_dispatchsetup: SDNode<"ARMISD::EH_SJLJ_DISPATCHSETUP",
126 SDT_ARMEH_SJLJ_DispatchSetup, [SDNPHasChain]>;
129 def ARMMemBarrier : SDNode<"ARMISD::MEMBARRIER", SDT_ARMMEMBARRIER,
131 def ARMMemBarrierMCR : SDNode<"ARMISD::MEMBARRIER_MCR", SDT_ARMMEMBARRIER,
133 def ARMPreload : SDNode<"ARMISD::PRELOAD", SDTPrefetch,
134 [SDNPHasChain, SDNPMayLoad, SDNPMayStore]>;
136 def ARMrbit : SDNode<"ARMISD::RBIT", SDTIntUnaryOp>;
138 def ARMtcret : SDNode<"ARMISD::TC_RETURN", SDT_ARMTCRET,
139 [SDNPHasChain, SDNPOptInFlag, SDNPVariadic]>;
142 def ARMbfi : SDNode<"ARMISD::BFI", SDT_ARMBFI>;
144 //===----------------------------------------------------------------------===//
145 // ARM Instruction Predicate Definitions.
147 def HasV4T : Predicate<"Subtarget->hasV4TOps()">, AssemblerPredicate;
148 def NoV4T : Predicate<"!Subtarget->hasV4TOps()">;
149 def HasV5T : Predicate<"Subtarget->hasV5TOps()">;
150 def HasV5TE : Predicate<"Subtarget->hasV5TEOps()">, AssemblerPredicate;
151 def HasV6 : Predicate<"Subtarget->hasV6Ops()">, AssemblerPredicate;
152 def HasV6T2 : Predicate<"Subtarget->hasV6T2Ops()">, AssemblerPredicate;
153 def NoV6T2 : Predicate<"!Subtarget->hasV6T2Ops()">;
154 def HasV7 : Predicate<"Subtarget->hasV7Ops()">, AssemblerPredicate;
155 def NoVFP : Predicate<"!Subtarget->hasVFP2()">;
156 def HasVFP2 : Predicate<"Subtarget->hasVFP2()">, AssemblerPredicate;
157 def HasVFP3 : Predicate<"Subtarget->hasVFP3()">, AssemblerPredicate;
158 def HasNEON : Predicate<"Subtarget->hasNEON()">, AssemblerPredicate;
159 def HasDivide : Predicate<"Subtarget->hasDivide()">, AssemblerPredicate;
160 def HasT2ExtractPack : Predicate<"Subtarget->hasT2ExtractPack()">,
162 def HasDB : Predicate<"Subtarget->hasDataBarrier()">,
164 def HasMP : Predicate<"Subtarget->hasMPExtension()">,
166 def UseNEONForFP : Predicate<"Subtarget->useNEONForSinglePrecisionFP()">;
167 def DontUseNEONForFP : Predicate<"!Subtarget->useNEONForSinglePrecisionFP()">;
168 def IsThumb : Predicate<"Subtarget->isThumb()">, AssemblerPredicate;
169 def IsThumb1Only : Predicate<"Subtarget->isThumb1Only()">;
170 def IsThumb2 : Predicate<"Subtarget->isThumb2()">, AssemblerPredicate;
171 def IsARM : Predicate<"!Subtarget->isThumb()">, AssemblerPredicate;
172 def IsDarwin : Predicate<"Subtarget->isTargetDarwin()">;
173 def IsNotDarwin : Predicate<"!Subtarget->isTargetDarwin()">;
175 // FIXME: Eventually this will be just "hasV6T2Ops".
176 def UseMovt : Predicate<"Subtarget->useMovt()">;
177 def DontUseMovt : Predicate<"!Subtarget->useMovt()">;
178 def UseVMLx : Predicate<"Subtarget->useVMLx()">;
180 //===----------------------------------------------------------------------===//
181 // ARM Flag Definitions.
183 class RegConstraint<string C> {
184 string Constraints = C;
187 //===----------------------------------------------------------------------===//
188 // ARM specific transformation functions and pattern fragments.
191 // so_imm_neg_XFORM - Return a so_imm value packed into the format described for
192 // so_imm_neg def below.
193 def so_imm_neg_XFORM : SDNodeXForm<imm, [{
194 return CurDAG->getTargetConstant(-(int)N->getZExtValue(), MVT::i32);
197 // so_imm_not_XFORM - Return a so_imm value packed into the format described for
198 // so_imm_not def below.
199 def so_imm_not_XFORM : SDNodeXForm<imm, [{
200 return CurDAG->getTargetConstant(~(int)N->getZExtValue(), MVT::i32);
203 /// imm1_15 predicate - True if the 32-bit immediate is in the range [1,15].
204 def imm1_15 : PatLeaf<(i32 imm), [{
205 return (int32_t)N->getZExtValue() >= 1 && (int32_t)N->getZExtValue() < 16;
208 /// imm16_31 predicate - True if the 32-bit immediate is in the range [16,31].
209 def imm16_31 : PatLeaf<(i32 imm), [{
210 return (int32_t)N->getZExtValue() >= 16 && (int32_t)N->getZExtValue() < 32;
215 return ARM_AM::getSOImmVal(-(int)N->getZExtValue()) != -1;
216 }], so_imm_neg_XFORM>;
220 return ARM_AM::getSOImmVal(~(int)N->getZExtValue()) != -1;
221 }], so_imm_not_XFORM>;
223 // sext_16_node predicate - True if the SDNode is sign-extended 16 or more bits.
224 def sext_16_node : PatLeaf<(i32 GPR:$a), [{
225 return CurDAG->ComputeNumSignBits(SDValue(N,0)) >= 17;
228 /// bf_inv_mask_imm predicate - An AND mask to clear an arbitrary width bitfield
230 def bf_inv_mask_imm : Operand<i32>,
232 return ARM::isBitFieldInvertedMask(N->getZExtValue());
234 string EncoderMethod = "getBitfieldInvertedMaskOpValue";
235 let PrintMethod = "printBitfieldInvMaskImmOperand";
238 /// Split a 32-bit immediate into two 16 bit parts.
239 def hi16 : SDNodeXForm<imm, [{
240 return CurDAG->getTargetConstant((uint32_t)N->getZExtValue() >> 16, MVT::i32);
243 def lo16AllZero : PatLeaf<(i32 imm), [{
244 // Returns true if all low 16-bits are 0.
245 return (((uint32_t)N->getZExtValue()) & 0xFFFFUL) == 0;
248 /// imm0_65535 predicate - True if the 32-bit immediate is in the range
250 def imm0_65535 : PatLeaf<(i32 imm), [{
251 return (uint32_t)N->getZExtValue() < 65536;
254 class BinOpFrag<dag res> : PatFrag<(ops node:$LHS, node:$RHS), res>;
255 class UnOpFrag <dag res> : PatFrag<(ops node:$Src), res>;
257 /// adde and sube predicates - True based on whether the carry flag output
258 /// will be needed or not.
259 def adde_dead_carry :
260 PatFrag<(ops node:$LHS, node:$RHS), (adde node:$LHS, node:$RHS),
261 [{return !N->hasAnyUseOfValue(1);}]>;
262 def sube_dead_carry :
263 PatFrag<(ops node:$LHS, node:$RHS), (sube node:$LHS, node:$RHS),
264 [{return !N->hasAnyUseOfValue(1);}]>;
265 def adde_live_carry :
266 PatFrag<(ops node:$LHS, node:$RHS), (adde node:$LHS, node:$RHS),
267 [{return N->hasAnyUseOfValue(1);}]>;
268 def sube_live_carry :
269 PatFrag<(ops node:$LHS, node:$RHS), (sube node:$LHS, node:$RHS),
270 [{return N->hasAnyUseOfValue(1);}]>;
272 //===----------------------------------------------------------------------===//
273 // Operand Definitions.
277 def brtarget : Operand<OtherVT>;
279 // A list of registers separated by comma. Used by load/store multiple.
280 def reglist : Operand<i32> {
281 string EncoderMethod = "getRegisterListOpValue";
282 let PrintMethod = "printRegisterList";
285 def RegListAsmOperand : AsmOperandClass {
286 let Name = "RegList";
287 let SuperClasses = [];
290 // An operand for the CONSTPOOL_ENTRY pseudo-instruction.
291 def cpinst_operand : Operand<i32> {
292 let PrintMethod = "printCPInstOperand";
295 def jtblock_operand : Operand<i32> {
296 let PrintMethod = "printJTBlockOperand";
298 def jt2block_operand : Operand<i32> {
299 let PrintMethod = "printJT2BlockOperand";
303 def pclabel : Operand<i32> {
304 let PrintMethod = "printPCLabel";
307 def neon_vcvt_imm32 : Operand<i32> {
308 string EncoderMethod = "getNEONVcvtImm32OpValue";
311 // rot_imm: An integer that encodes a rotate amount. Must be 8, 16, or 24.
312 def rot_imm : Operand<i32>, PatLeaf<(i32 imm), [{
313 int32_t v = (int32_t)N->getZExtValue();
314 return v == 8 || v == 16 || v == 24; }]> {
315 string EncoderMethod = "getRotImmOpValue";
318 // shift_imm: An integer that encodes a shift amount and the type of shift
319 // (currently either asr or lsl) using the same encoding used for the
320 // immediates in so_reg operands.
321 def shift_imm : Operand<i32> {
322 let PrintMethod = "printShiftImmOperand";
325 // shifter_operand operands: so_reg and so_imm.
326 def so_reg : Operand<i32>, // reg reg imm
327 ComplexPattern<i32, 3, "SelectShifterOperandReg",
328 [shl,srl,sra,rotr]> {
329 string EncoderMethod = "getSORegOpValue";
330 let PrintMethod = "printSORegOperand";
331 let MIOperandInfo = (ops GPR, GPR, i32imm);
333 def shift_so_reg : Operand<i32>, // reg reg imm
334 ComplexPattern<i32, 3, "SelectShiftShifterOperandReg",
335 [shl,srl,sra,rotr]> {
336 string EncoderMethod = "getSORegOpValue";
337 let PrintMethod = "printSORegOperand";
338 let MIOperandInfo = (ops GPR, GPR, i32imm);
341 // so_imm - Match a 32-bit shifter_operand immediate operand, which is an
342 // 8-bit immediate rotated by an arbitrary number of bits. so_imm values are
343 // represented in the imm field in the same 12-bit form that they are encoded
344 // into so_imm instructions: the 8-bit immediate is the least significant bits
345 // [bits 0-7], the 4-bit shift amount is the next 4 bits [bits 8-11].
346 def so_imm : Operand<i32>, PatLeaf<(imm), [{ return Pred_so_imm(N); }]> {
347 string EncoderMethod = "getSOImmOpValue";
348 let PrintMethod = "printSOImmOperand";
351 // Break so_imm's up into two pieces. This handles immediates with up to 16
352 // bits set in them. This uses so_imm2part to match and so_imm2part_[12] to
353 // get the first/second pieces.
354 def so_imm2part : Operand<i32>,
356 return ARM_AM::isSOImmTwoPartVal((unsigned)N->getZExtValue());
358 let PrintMethod = "printSOImm2PartOperand";
361 def so_imm2part_1 : SDNodeXForm<imm, [{
362 unsigned V = ARM_AM::getSOImmTwoPartFirst((unsigned)N->getZExtValue());
363 return CurDAG->getTargetConstant(V, MVT::i32);
366 def so_imm2part_2 : SDNodeXForm<imm, [{
367 unsigned V = ARM_AM::getSOImmTwoPartSecond((unsigned)N->getZExtValue());
368 return CurDAG->getTargetConstant(V, MVT::i32);
371 def so_neg_imm2part : Operand<i32>, PatLeaf<(imm), [{
372 return ARM_AM::isSOImmTwoPartVal(-(int)N->getZExtValue());
374 let PrintMethod = "printSOImm2PartOperand";
377 def so_neg_imm2part_1 : SDNodeXForm<imm, [{
378 unsigned V = ARM_AM::getSOImmTwoPartFirst(-(int)N->getZExtValue());
379 return CurDAG->getTargetConstant(V, MVT::i32);
382 def so_neg_imm2part_2 : SDNodeXForm<imm, [{
383 unsigned V = ARM_AM::getSOImmTwoPartSecond(-(int)N->getZExtValue());
384 return CurDAG->getTargetConstant(V, MVT::i32);
387 /// imm0_31 predicate - True if the 32-bit immediate is in the range [0,31].
388 def imm0_31 : Operand<i32>, PatLeaf<(imm), [{
389 return (int32_t)N->getZExtValue() < 32;
392 /// imm0_31_m1 - Matches and prints like imm0_31, but encodes as 'value - 1'.
393 def imm0_31_m1 : Operand<i32>, PatLeaf<(imm), [{
394 return (int32_t)N->getZExtValue() < 32;
396 string EncoderMethod = "getImmMinusOneOpValue";
399 // Define ARM specific addressing modes.
402 // addrmode_imm12 := reg +/- imm12
404 def addrmode_imm12 : Operand<i32>,
405 ComplexPattern<i32, 2, "SelectAddrModeImm12", []> {
406 // 12-bit immediate operand. Note that instructions using this encode
407 // #0 and #-0 differently. We flag #-0 as the magic value INT32_MIN. All other
408 // immediate values are as normal.
410 string EncoderMethod = "getAddrModeImm12OpValue";
411 let PrintMethod = "printAddrModeImm12Operand";
412 let MIOperandInfo = (ops GPR:$base, i32imm:$offsimm);
414 // ldst_so_reg := reg +/- reg shop imm
416 def ldst_so_reg : Operand<i32>,
417 ComplexPattern<i32, 3, "SelectLdStSOReg", []> {
418 // FIXME: Simplify the printer
419 // FIXME: Add EncoderMethod for this addressing mode
420 let PrintMethod = "printAddrMode2Operand";
421 let MIOperandInfo = (ops GPR:$base, GPR:$offsreg, i32imm:$offsimm);
424 // addrmode2 := reg +/- imm12
425 // := reg +/- reg shop imm
427 def addrmode2 : Operand<i32>,
428 ComplexPattern<i32, 3, "SelectAddrMode2", []> {
429 let PrintMethod = "printAddrMode2Operand";
430 let MIOperandInfo = (ops GPR:$base, GPR:$offsreg, i32imm:$offsimm);
433 def am2offset : Operand<i32>,
434 ComplexPattern<i32, 2, "SelectAddrMode2Offset",
435 [], [SDNPWantRoot]> {
436 let PrintMethod = "printAddrMode2OffsetOperand";
437 let MIOperandInfo = (ops GPR, i32imm);
440 // addrmode3 := reg +/- reg
441 // addrmode3 := reg +/- imm8
443 def addrmode3 : Operand<i32>,
444 ComplexPattern<i32, 3, "SelectAddrMode3", []> {
445 let PrintMethod = "printAddrMode3Operand";
446 let MIOperandInfo = (ops GPR:$base, GPR:$offsreg, i32imm:$offsimm);
449 def am3offset : Operand<i32>,
450 ComplexPattern<i32, 2, "SelectAddrMode3Offset",
451 [], [SDNPWantRoot]> {
452 let PrintMethod = "printAddrMode3OffsetOperand";
453 let MIOperandInfo = (ops GPR, i32imm);
456 // ldstm_mode := {ia, ib, da, db}
458 def ldstm_mode : OptionalDefOperand<OtherVT, (ops i32), (ops (i32 1))> {
459 let PrintMethod = "printLdStmModeOperand";
462 def MemMode5AsmOperand : AsmOperandClass {
463 let Name = "MemMode5";
464 let SuperClasses = [];
467 // addrmode5 := reg +/- imm8*4
469 def addrmode5 : Operand<i32>,
470 ComplexPattern<i32, 2, "SelectAddrMode5", []> {
471 let PrintMethod = "printAddrMode5Operand";
472 let MIOperandInfo = (ops GPR:$base, i32imm);
473 let ParserMatchClass = MemMode5AsmOperand;
474 string EncoderMethod = "getAddrMode5OpValue";
477 // addrmode6 := reg with optional writeback
479 def addrmode6 : Operand<i32>,
480 ComplexPattern<i32, 2, "SelectAddrMode6", [], [SDNPWantParent]>{
481 let PrintMethod = "printAddrMode6Operand";
482 let MIOperandInfo = (ops GPR:$addr, i32imm);
483 string EncoderMethod = "getAddrMode6AddressOpValue";
486 def am6offset : Operand<i32> {
487 let PrintMethod = "printAddrMode6OffsetOperand";
488 let MIOperandInfo = (ops GPR);
489 string EncoderMethod = "getAddrMode6OffsetOpValue";
492 // addrmodepc := pc + reg
494 def addrmodepc : Operand<i32>,
495 ComplexPattern<i32, 2, "SelectAddrModePC", []> {
496 let PrintMethod = "printAddrModePCOperand";
497 let MIOperandInfo = (ops GPR, i32imm);
500 def nohash_imm : Operand<i32> {
501 let PrintMethod = "printNoHashImmediate";
504 //===----------------------------------------------------------------------===//
506 include "ARMInstrFormats.td"
508 //===----------------------------------------------------------------------===//
509 // Multiclass helpers...
512 /// AsI1_bin_irs - Defines a set of (op r, {so_imm|r|so_reg}) patterns for a
513 /// binop that produces a value.
514 multiclass AsI1_bin_irs<bits<4> opcod, string opc,
515 InstrItinClass iii, InstrItinClass iir, InstrItinClass iis,
516 PatFrag opnode, bit Commutable = 0> {
517 // The register-immediate version is re-materializable. This is useful
518 // in particular for taking the address of a local.
519 let isReMaterializable = 1 in {
520 def ri : AsI1<opcod, (outs GPR:$Rd), (ins GPR:$Rn, so_imm:$imm), DPFrm,
521 iii, opc, "\t$Rd, $Rn, $imm",
522 [(set GPR:$Rd, (opnode GPR:$Rn, so_imm:$imm))]> {
527 let Inst{19-16} = Rn;
528 let Inst{15-12} = Rd;
529 let Inst{11-0} = imm;
532 def rr : AsI1<opcod, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm), DPFrm,
533 iir, opc, "\t$Rd, $Rn, $Rm",
534 [(set GPR:$Rd, (opnode GPR:$Rn, GPR:$Rm))]> {
539 let isCommutable = Commutable;
540 let Inst{19-16} = Rn;
541 let Inst{15-12} = Rd;
542 let Inst{11-4} = 0b00000000;
545 def rs : AsI1<opcod, (outs GPR:$Rd), (ins GPR:$Rn, so_reg:$shift), DPSoRegFrm,
546 iis, opc, "\t$Rd, $Rn, $shift",
547 [(set GPR:$Rd, (opnode GPR:$Rn, so_reg:$shift))]> {
552 let Inst{19-16} = Rn;
553 let Inst{15-12} = Rd;
554 let Inst{11-0} = shift;
558 /// AI1_bin_s_irs - Similar to AsI1_bin_irs except it sets the 's' bit so the
559 /// instruction modifies the CPSR register.
560 let Defs = [CPSR] in {
561 multiclass AI1_bin_s_irs<bits<4> opcod, string opc,
562 InstrItinClass iii, InstrItinClass iir, InstrItinClass iis,
563 PatFrag opnode, bit Commutable = 0> {
564 def ri : AI1<opcod, (outs GPR:$Rd), (ins GPR:$Rn, so_imm:$imm), DPFrm,
565 iii, opc, "\t$Rd, $Rn, $imm",
566 [(set GPR:$Rd, (opnode GPR:$Rn, so_imm:$imm))]> {
572 let Inst{19-16} = Rn;
573 let Inst{15-12} = Rd;
574 let Inst{11-0} = imm;
576 def rr : AI1<opcod, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm), DPFrm,
577 iir, opc, "\t$Rd, $Rn, $Rm",
578 [(set GPR:$Rd, (opnode GPR:$Rn, GPR:$Rm))]> {
582 let isCommutable = Commutable;
585 let Inst{19-16} = Rn;
586 let Inst{15-12} = Rd;
587 let Inst{11-4} = 0b00000000;
590 def rs : AI1<opcod, (outs GPR:$Rd), (ins GPR:$Rn, so_reg:$shift), DPSoRegFrm,
591 iis, opc, "\t$Rd, $Rn, $shift",
592 [(set GPR:$Rd, (opnode GPR:$Rn, so_reg:$shift))]> {
598 let Inst{19-16} = Rn;
599 let Inst{15-12} = Rd;
600 let Inst{11-0} = shift;
605 /// AI1_cmp_irs - Defines a set of (op r, {so_imm|r|so_reg}) cmp / test
606 /// patterns. Similar to AsI1_bin_irs except the instruction does not produce
607 /// a explicit result, only implicitly set CPSR.
608 let isCompare = 1, Defs = [CPSR] in {
609 multiclass AI1_cmp_irs<bits<4> opcod, string opc,
610 InstrItinClass iii, InstrItinClass iir, InstrItinClass iis,
611 PatFrag opnode, bit Commutable = 0> {
612 def ri : AI1<opcod, (outs), (ins GPR:$Rn, so_imm:$imm), DPFrm, iii,
614 [(opnode GPR:$Rn, so_imm:$imm)]> {
619 let Inst{19-16} = Rn;
620 let Inst{15-12} = 0b0000;
621 let Inst{11-0} = imm;
623 def rr : AI1<opcod, (outs), (ins GPR:$Rn, GPR:$Rm), DPFrm, iir,
625 [(opnode GPR:$Rn, GPR:$Rm)]> {
628 let isCommutable = Commutable;
631 let Inst{19-16} = Rn;
632 let Inst{15-12} = 0b0000;
633 let Inst{11-4} = 0b00000000;
636 def rs : AI1<opcod, (outs), (ins GPR:$Rn, so_reg:$shift), DPSoRegFrm, iis,
637 opc, "\t$Rn, $shift",
638 [(opnode GPR:$Rn, so_reg:$shift)]> {
643 let Inst{19-16} = Rn;
644 let Inst{15-12} = 0b0000;
645 let Inst{11-0} = shift;
650 /// AI_ext_rrot - A unary operation with two forms: one whose operand is a
651 /// register and one whose operand is a register rotated by 8/16/24.
652 /// FIXME: Remove the 'r' variant. Its rot_imm is zero.
653 multiclass AI_ext_rrot<bits<8> opcod, string opc, PatFrag opnode> {
654 def r : AExtI<opcod, (outs GPR:$Rd), (ins GPR:$Rm),
655 IIC_iEXTr, opc, "\t$Rd, $Rm",
656 [(set GPR:$Rd, (opnode GPR:$Rm))]>,
657 Requires<[IsARM, HasV6]> {
660 let Inst{19-16} = 0b1111;
661 let Inst{15-12} = Rd;
662 let Inst{11-10} = 0b00;
665 def r_rot : AExtI<opcod, (outs GPR:$Rd), (ins GPR:$Rm, rot_imm:$rot),
666 IIC_iEXTr, opc, "\t$Rd, $Rm, ror $rot",
667 [(set GPR:$Rd, (opnode (rotr GPR:$Rm, rot_imm:$rot)))]>,
668 Requires<[IsARM, HasV6]> {
672 let Inst{19-16} = 0b1111;
673 let Inst{15-12} = Rd;
674 let Inst{11-10} = rot;
679 multiclass AI_ext_rrot_np<bits<8> opcod, string opc> {
680 def r : AExtI<opcod, (outs GPR:$Rd), (ins GPR:$Rm),
681 IIC_iEXTr, opc, "\t$Rd, $Rm",
682 [/* For disassembly only; pattern left blank */]>,
683 Requires<[IsARM, HasV6]> {
684 let Inst{19-16} = 0b1111;
685 let Inst{11-10} = 0b00;
687 def r_rot : AExtI<opcod, (outs GPR:$Rd), (ins GPR:$Rm, rot_imm:$rot),
688 IIC_iEXTr, opc, "\t$Rd, $Rm, ror $rot",
689 [/* For disassembly only; pattern left blank */]>,
690 Requires<[IsARM, HasV6]> {
692 let Inst{19-16} = 0b1111;
693 let Inst{11-10} = rot;
697 /// AI_exta_rrot - A binary operation with two forms: one whose operand is a
698 /// register and one whose operand is a register rotated by 8/16/24.
699 multiclass AI_exta_rrot<bits<8> opcod, string opc, PatFrag opnode> {
700 def rr : AExtI<opcod, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm),
701 IIC_iEXTAr, opc, "\t$Rd, $Rn, $Rm",
702 [(set GPR:$Rd, (opnode GPR:$Rn, GPR:$Rm))]>,
703 Requires<[IsARM, HasV6]> {
704 let Inst{11-10} = 0b00;
706 def rr_rot : AExtI<opcod, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm,
708 IIC_iEXTAr, opc, "\t$Rd, $Rn, $Rm, ror $rot",
709 [(set GPR:$Rd, (opnode GPR:$Rn,
710 (rotr GPR:$Rm, rot_imm:$rot)))]>,
711 Requires<[IsARM, HasV6]> {
714 let Inst{19-16} = Rn;
715 let Inst{11-10} = rot;
719 // For disassembly only.
720 multiclass AI_exta_rrot_np<bits<8> opcod, string opc> {
721 def rr : AExtI<opcod, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm),
722 IIC_iEXTAr, opc, "\t$Rd, $Rn, $Rm",
723 [/* For disassembly only; pattern left blank */]>,
724 Requires<[IsARM, HasV6]> {
725 let Inst{11-10} = 0b00;
727 def rr_rot : AExtI<opcod, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm,
729 IIC_iEXTAr, opc, "\t$Rd, $Rn, $Rm, ror $rot",
730 [/* For disassembly only; pattern left blank */]>,
731 Requires<[IsARM, HasV6]> {
734 let Inst{19-16} = Rn;
735 let Inst{11-10} = rot;
739 /// AI1_adde_sube_irs - Define instructions and patterns for adde and sube.
740 let Uses = [CPSR] in {
741 multiclass AI1_adde_sube_irs<bits<4> opcod, string opc, PatFrag opnode,
742 bit Commutable = 0> {
743 def ri : AsI1<opcod, (outs GPR:$Rd), (ins GPR:$Rn, so_imm:$imm),
744 DPFrm, IIC_iALUi, opc, "\t$Rd, $Rn, $imm",
745 [(set GPR:$Rd, (opnode GPR:$Rn, so_imm:$imm))]>,
751 let Inst{15-12} = Rd;
752 let Inst{19-16} = Rn;
753 let Inst{11-0} = imm;
755 def rr : AsI1<opcod, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm),
756 DPFrm, IIC_iALUr, opc, "\t$Rd, $Rn, $Rm",
757 [(set GPR:$Rd, (opnode GPR:$Rn, GPR:$Rm))]>,
762 let Inst{11-4} = 0b00000000;
764 let isCommutable = Commutable;
766 let Inst{15-12} = Rd;
767 let Inst{19-16} = Rn;
769 def rs : AsI1<opcod, (outs GPR:$Rd), (ins GPR:$Rn, so_reg:$shift),
770 DPSoRegFrm, IIC_iALUsr, opc, "\t$Rd, $Rn, $shift",
771 [(set GPR:$Rd, (opnode GPR:$Rn, so_reg:$shift))]>,
777 let Inst{11-0} = shift;
778 let Inst{15-12} = Rd;
779 let Inst{19-16} = Rn;
782 // Carry setting variants
783 let Defs = [CPSR] in {
784 multiclass AI1_adde_sube_s_irs<bits<4> opcod, string opc, PatFrag opnode,
785 bit Commutable = 0> {
786 def Sri : AXI1<opcod, (outs GPR:$Rd), (ins GPR:$Rn, so_imm:$imm),
787 DPFrm, IIC_iALUi, !strconcat(opc, "\t$Rd, $Rn, $imm"),
788 [(set GPR:$Rd, (opnode GPR:$Rn, so_imm:$imm))]>,
793 let Inst{15-12} = Rd;
794 let Inst{19-16} = Rn;
795 let Inst{11-0} = imm;
799 def Srr : AXI1<opcod, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm),
800 DPFrm, IIC_iALUr, !strconcat(opc, "\t$Rd, $Rn, $Rm"),
801 [(set GPR:$Rd, (opnode GPR:$Rn, GPR:$Rm))]>,
806 let Inst{11-4} = 0b00000000;
807 let isCommutable = Commutable;
809 let Inst{15-12} = Rd;
810 let Inst{19-16} = Rn;
814 def Srs : AXI1<opcod, (outs GPR:$Rd), (ins GPR:$Rn, so_reg:$shift),
815 DPSoRegFrm, IIC_iALUsr, !strconcat(opc, "\t$Rd, $Rn, $shift"),
816 [(set GPR:$Rd, (opnode GPR:$Rn, so_reg:$shift))]>,
821 let Inst{11-0} = shift;
822 let Inst{15-12} = Rd;
823 let Inst{19-16} = Rn;
831 let canFoldAsLoad = 1, isReMaterializable = 1 in {
832 multiclass AI_ldr1<bit opc22, string opc, InstrItinClass iii,
833 InstrItinClass iir, PatFrag opnode> {
834 // Note: We use the complex addrmode_imm12 rather than just an input
835 // GPR and a constrained immediate so that we can use this to match
836 // frame index references and avoid matching constant pool references.
837 def i12 : AIldst1<0b010, opc22, 1, (outs GPR:$Rt), (ins addrmode_imm12:$addr),
838 AddrMode_i12, LdFrm, iii, opc, "\t$Rt, $addr",
839 [(set GPR:$Rt, (opnode addrmode_imm12:$addr))]> {
842 let Inst{23} = addr{12}; // U (add = ('U' == 1))
843 let Inst{19-16} = addr{16-13}; // Rn
844 let Inst{15-12} = Rt;
845 let Inst{11-0} = addr{11-0}; // imm12
847 def rs : AIldst1<0b011, opc22, 1, (outs GPR:$Rt), (ins ldst_so_reg:$shift),
848 AddrModeNone, LdFrm, iir, opc, "\t$Rt, $shift",
849 [(set GPR:$Rt, (opnode ldst_so_reg:$shift))]> {
852 let Inst{23} = shift{12}; // U (add = ('U' == 1))
853 let Inst{19-16} = shift{16-13}; // Rn
854 let Inst{11-0} = shift{11-0};
859 multiclass AI_str1<bit opc22, string opc, InstrItinClass iii,
860 InstrItinClass iir, PatFrag opnode> {
861 // Note: We use the complex addrmode_imm12 rather than just an input
862 // GPR and a constrained immediate so that we can use this to match
863 // frame index references and avoid matching constant pool references.
864 def i12 : AIldst1<0b010, opc22, 0, (outs),
865 (ins GPR:$Rt, addrmode_imm12:$addr),
866 AddrMode_i12, StFrm, iii, opc, "\t$Rt, $addr",
867 [(opnode GPR:$Rt, addrmode_imm12:$addr)]> {
870 let Inst{23} = addr{12}; // U (add = ('U' == 1))
871 let Inst{19-16} = addr{16-13}; // Rn
872 let Inst{15-12} = Rt;
873 let Inst{11-0} = addr{11-0}; // imm12
875 def rs : AIldst1<0b011, opc22, 0, (outs), (ins GPR:$Rt, ldst_so_reg:$shift),
876 AddrModeNone, StFrm, iir, opc, "\t$Rt, $shift",
877 [(opnode GPR:$Rt, ldst_so_reg:$shift)]> {
880 let Inst{23} = shift{12}; // U (add = ('U' == 1))
881 let Inst{19-16} = shift{16-13}; // Rn
882 let Inst{11-0} = shift{11-0};
885 //===----------------------------------------------------------------------===//
887 //===----------------------------------------------------------------------===//
889 //===----------------------------------------------------------------------===//
890 // Miscellaneous Instructions.
893 /// CONSTPOOL_ENTRY - This instruction represents a floating constant pool in
894 /// the function. The first operand is the ID# for this instruction, the second
895 /// is the index into the MachineConstantPool that this is, the third is the
896 /// size in bytes of this constant pool entry.
897 let neverHasSideEffects = 1, isNotDuplicable = 1 in
898 def CONSTPOOL_ENTRY :
899 PseudoInst<(outs), (ins cpinst_operand:$instid, cpinst_operand:$cpidx,
900 i32imm:$size), NoItinerary, "", []>;
902 // FIXME: Marking these as hasSideEffects is necessary to prevent machine DCE
903 // from removing one half of the matched pairs. That breaks PEI, which assumes
904 // these will always be in pairs, and asserts if it finds otherwise. Better way?
905 let Defs = [SP], Uses = [SP], hasSideEffects = 1 in {
907 PseudoInst<(outs), (ins i32imm:$amt1, i32imm:$amt2, pred:$p), NoItinerary, "",
908 [(ARMcallseq_end timm:$amt1, timm:$amt2)]>;
910 def ADJCALLSTACKDOWN :
911 PseudoInst<(outs), (ins i32imm:$amt, pred:$p), NoItinerary, "",
912 [(ARMcallseq_start timm:$amt)]>;
915 def NOP : AI<(outs), (ins), MiscFrm, NoItinerary, "nop", "",
916 [/* For disassembly only; pattern left blank */]>,
917 Requires<[IsARM, HasV6T2]> {
918 let Inst{27-16} = 0b001100100000;
919 let Inst{15-8} = 0b11110000;
920 let Inst{7-0} = 0b00000000;
923 def YIELD : AI<(outs), (ins), MiscFrm, NoItinerary, "yield", "",
924 [/* For disassembly only; pattern left blank */]>,
925 Requires<[IsARM, HasV6T2]> {
926 let Inst{27-16} = 0b001100100000;
927 let Inst{15-8} = 0b11110000;
928 let Inst{7-0} = 0b00000001;
931 def WFE : AI<(outs), (ins), MiscFrm, NoItinerary, "wfe", "",
932 [/* For disassembly only; pattern left blank */]>,
933 Requires<[IsARM, HasV6T2]> {
934 let Inst{27-16} = 0b001100100000;
935 let Inst{15-8} = 0b11110000;
936 let Inst{7-0} = 0b00000010;
939 def WFI : AI<(outs), (ins), MiscFrm, NoItinerary, "wfi", "",
940 [/* For disassembly only; pattern left blank */]>,
941 Requires<[IsARM, HasV6T2]> {
942 let Inst{27-16} = 0b001100100000;
943 let Inst{15-8} = 0b11110000;
944 let Inst{7-0} = 0b00000011;
947 def SEL : AI<(outs GPR:$dst), (ins GPR:$a, GPR:$b), DPFrm, NoItinerary, "sel",
949 [/* For disassembly only; pattern left blank */]>,
950 Requires<[IsARM, HasV6]> {
955 let Inst{15-12} = Rd;
956 let Inst{19-16} = Rn;
957 let Inst{27-20} = 0b01101000;
958 let Inst{7-4} = 0b1011;
959 let Inst{11-8} = 0b1111;
962 def SEV : AI<(outs), (ins), MiscFrm, NoItinerary, "sev", "",
963 [/* For disassembly only; pattern left blank */]>,
964 Requires<[IsARM, HasV6T2]> {
965 let Inst{27-16} = 0b001100100000;
966 let Inst{15-8} = 0b11110000;
967 let Inst{7-0} = 0b00000100;
970 // The i32imm operand $val can be used by a debugger to store more information
971 // about the breakpoint.
972 def BKPT : AI<(outs), (ins i32imm:$val), MiscFrm, NoItinerary, "bkpt", "\t$val",
973 [/* For disassembly only; pattern left blank */]>,
976 let Inst{3-0} = val{3-0};
977 let Inst{19-8} = val{15-4};
978 let Inst{27-20} = 0b00010010;
979 let Inst{7-4} = 0b0111;
982 // Change Processor State is a system instruction -- for disassembly only.
983 // The singleton $opt operand contains the following information:
984 // opt{4-0} = mode from Inst{4-0}
985 // opt{5} = changemode from Inst{17}
986 // opt{8-6} = AIF from Inst{8-6}
987 // opt{10-9} = imod from Inst{19-18} with 0b10 as enable and 0b11 as disable
988 // FIXME: Integrated assembler will need these split out.
989 def CPS : AXI<(outs), (ins cps_opt:$opt), MiscFrm, NoItinerary, "cps$opt",
990 [/* For disassembly only; pattern left blank */]>,
992 let Inst{31-28} = 0b1111;
993 let Inst{27-20} = 0b00010000;
998 // Preload signals the memory system of possible future data/instruction access.
999 // These are for disassembly only.
1000 multiclass APreLoad<bits<1> read, bits<1> data, string opc> {
1002 def i12 : AXI<(outs), (ins addrmode_imm12:$addr), MiscFrm, IIC_Preload,
1003 !strconcat(opc, "\t$addr"),
1004 [(ARMPreload addrmode_imm12:$addr, (i32 read), (i32 data))]> {
1007 let Inst{31-26} = 0b111101;
1008 let Inst{25} = 0; // 0 for immediate form
1009 let Inst{24} = data;
1010 let Inst{23} = addr{12}; // U (add = ('U' == 1))
1011 let Inst{22} = read;
1012 let Inst{21-20} = 0b01;
1013 let Inst{19-16} = addr{16-13}; // Rn
1014 let Inst{15-12} = Rt;
1015 let Inst{11-0} = addr{11-0}; // imm12
1018 def rs : AXI<(outs), (ins ldst_so_reg:$shift), MiscFrm, IIC_Preload,
1019 !strconcat(opc, "\t$shift"),
1020 [(ARMPreload ldst_so_reg:$shift, (i32 read), (i32 data))]> {
1023 let Inst{31-26} = 0b111101;
1024 let Inst{25} = 1; // 1 for register form
1025 let Inst{24} = data;
1026 let Inst{23} = shift{12}; // U (add = ('U' == 1))
1027 let Inst{22} = read;
1028 let Inst{21-20} = 0b01;
1029 let Inst{19-16} = shift{16-13}; // Rn
1030 let Inst{11-0} = shift{11-0};
1034 defm PLD : APreLoad<1, 1, "pld">, Requires<[IsARM]>;
1035 defm PLDW : APreLoad<0, 1, "pldw">, Requires<[IsARM,HasV7,HasMP]>;
1036 defm PLI : APreLoad<1, 0, "pli">, Requires<[IsARM,HasV7]>;
1038 def SETEND : AXI<(outs),(ins setend_op:$end), MiscFrm, NoItinerary,
1040 [/* For disassembly only; pattern left blank */]>,
1043 let Inst{31-10} = 0b1111000100000001000000;
1048 def DBG : AI<(outs), (ins i32imm:$opt), MiscFrm, NoItinerary, "dbg", "\t$opt",
1049 [/* For disassembly only; pattern left blank */]>,
1050 Requires<[IsARM, HasV7]> {
1052 let Inst{27-4} = 0b001100100000111100001111;
1053 let Inst{3-0} = opt;
1056 // A5.4 Permanently UNDEFINED instructions.
1057 let isBarrier = 1, isTerminator = 1 in
1058 def TRAP : AXI<(outs), (ins), MiscFrm, NoItinerary,
1061 let Inst{27-25} = 0b011;
1062 let Inst{24-20} = 0b11111;
1063 let Inst{7-5} = 0b111;
1067 // Address computation and loads and stores in PIC mode.
1068 // FIXME: These PIC insn patterns are pseudos, but derive from the normal insn
1069 // classes (AXI1, et.al.) and so have encoding information and such,
1070 // which is suboptimal. Once the rest of the code emitter (including
1071 // JIT) is MC-ized we should look at refactoring these into true
1072 // pseudos. As is, the encoding information ends up being ignored,
1073 // as these instructions are lowered to individual MC-insts.
1074 let isNotDuplicable = 1 in {
1075 def PICADD : AXI1<0b0100, (outs GPR:$dst), (ins GPR:$a, pclabel:$cp, pred:$p),
1076 Pseudo, IIC_iALUr, "",
1077 [(set GPR:$dst, (ARMpic_add GPR:$a, imm:$cp))]>;
1079 let AddedComplexity = 10 in {
1080 def PICLDR : AXI2ldw<(outs GPR:$dst), (ins addrmodepc:$addr, pred:$p),
1081 Pseudo, IIC_iLoad_r, "",
1082 [(set GPR:$dst, (load addrmodepc:$addr))]>;
1084 def PICLDRH : AXI3ldh<(outs GPR:$dst), (ins addrmodepc:$addr, pred:$p),
1085 Pseudo, IIC_iLoad_bh_r, "",
1086 [(set GPR:$dst, (zextloadi16 addrmodepc:$addr))]>;
1088 def PICLDRB : AXI2ldb<(outs GPR:$dst), (ins addrmodepc:$addr, pred:$p),
1089 Pseudo, IIC_iLoad_bh_r, "",
1090 [(set GPR:$dst, (zextloadi8 addrmodepc:$addr))]>;
1092 def PICLDRSH : AXI3ldsh<(outs GPR:$dst), (ins addrmodepc:$addr, pred:$p),
1093 Pseudo, IIC_iLoad_bh_r, "",
1094 [(set GPR:$dst, (sextloadi16 addrmodepc:$addr))]>;
1096 def PICLDRSB : AXI3ldsb<(outs GPR:$dst), (ins addrmodepc:$addr, pred:$p),
1097 Pseudo, IIC_iLoad_bh_r, "",
1098 [(set GPR:$dst, (sextloadi8 addrmodepc:$addr))]>;
1100 let AddedComplexity = 10 in {
1101 def PICSTR : AXI2stw<(outs), (ins GPR:$src, addrmodepc:$addr, pred:$p),
1102 Pseudo, IIC_iStore_r, "",
1103 [(store GPR:$src, addrmodepc:$addr)]>;
1105 def PICSTRH : AXI3sth<(outs), (ins GPR:$src, addrmodepc:$addr, pred:$p),
1106 Pseudo, IIC_iStore_bh_r, "",
1107 [(truncstorei16 GPR:$src, addrmodepc:$addr)]>;
1109 def PICSTRB : AXI2stb<(outs), (ins GPR:$src, addrmodepc:$addr, pred:$p),
1110 Pseudo, IIC_iStore_bh_r, "",
1111 [(truncstorei8 GPR:$src, addrmodepc:$addr)]>;
1113 } // isNotDuplicable = 1
1116 // LEApcrel - Load a pc-relative address into a register without offending the
1118 // FIXME: These are marked as pseudos, but they're really not(?). They're just
1119 // the ADR instruction. Is this the right way to handle that? They need
1120 // encoding information regardless.
1121 let neverHasSideEffects = 1 in {
1122 let isReMaterializable = 1 in
1123 def LEApcrel : AXI1<0x0, (outs GPR:$dst), (ins i32imm:$label, pred:$p),
1125 "adr$p\t$dst, #$label", []>;
1127 } // neverHasSideEffects
1128 def LEApcrelJT : AXI1<0x0, (outs GPR:$dst),
1129 (ins i32imm:$label, nohash_imm:$id, pred:$p),
1131 "adr$p\t$dst, #${label}_${id}", []> {
1135 //===----------------------------------------------------------------------===//
1136 // Control Flow Instructions.
1139 let isReturn = 1, isTerminator = 1, isBarrier = 1 in {
1141 def BX_RET : AI<(outs), (ins), BrMiscFrm, IIC_Br,
1142 "bx", "\tlr", [(ARMretflag)]>,
1143 Requires<[IsARM, HasV4T]> {
1144 let Inst{27-0} = 0b0001001011111111111100011110;
1148 def MOVPCLR : AI<(outs), (ins), BrMiscFrm, IIC_Br,
1149 "mov", "\tpc, lr", [(ARMretflag)]>,
1150 Requires<[IsARM, NoV4T]> {
1151 let Inst{27-0} = 0b0001101000001111000000001110;
1155 // Indirect branches
1156 let isBranch = 1, isTerminator = 1, isBarrier = 1, isIndirectBranch = 1 in {
1158 def BRIND : AXI<(outs), (ins GPR:$dst), BrMiscFrm, IIC_Br, "bx\t$dst",
1159 [(brind GPR:$dst)]>,
1160 Requires<[IsARM, HasV4T]> {
1162 let Inst{31-4} = 0b1110000100101111111111110001;
1163 let Inst{3-0} = dst;
1167 def MOVPCRX : AXI<(outs), (ins GPR:$dst), BrMiscFrm, IIC_Br, "mov\tpc, $dst",
1168 [(brind GPR:$dst)]>,
1169 Requires<[IsARM, NoV4T]> {
1171 let Inst{31-4} = 0b1110000110100000111100000000;
1172 let Inst{3-0} = dst;
1176 // FIXME: remove when we have a way to marking a MI with these properties.
1177 // FIXME: Should pc be an implicit operand like PICADD, etc?
1178 let isReturn = 1, isTerminator = 1, isBarrier = 1, mayLoad = 1,
1179 hasExtraDefRegAllocReq = 1, isCodeGenOnly = 1 in
1180 def LDM_RET : AXI4ld<(outs GPR:$wb), (ins GPR:$Rn, ldstm_mode:$mode, pred:$p,
1181 reglist:$dsts, variable_ops),
1182 IndexModeUpd, LdStMulFrm, IIC_iLoad_mBr,
1183 "ldm${mode}${p}\t$Rn!, $dsts",
1186 // On non-Darwin platforms R9 is callee-saved.
1188 Defs = [R0, R1, R2, R3, R12, LR,
1189 D0, D1, D2, D3, D4, D5, D6, D7,
1190 D16, D17, D18, D19, D20, D21, D22, D23,
1191 D24, D25, D26, D27, D28, D29, D30, D31, CPSR, FPSCR] in {
1192 def BL : ABXI<0b1011, (outs), (ins i32imm:$func, variable_ops),
1193 IIC_Br, "bl\t$func",
1194 [(ARMcall tglobaladdr:$func)]>,
1195 Requires<[IsARM, IsNotDarwin]> {
1196 let Inst{31-28} = 0b1110;
1197 // FIXME: Encoding info for $func. Needs fixups bits.
1200 def BL_pred : ABI<0b1011, (outs), (ins i32imm:$func, variable_ops),
1201 IIC_Br, "bl", "\t$func",
1202 [(ARMcall_pred tglobaladdr:$func)]>,
1203 Requires<[IsARM, IsNotDarwin]>;
1206 def BLX : AXI<(outs), (ins GPR:$func, variable_ops), BrMiscFrm,
1207 IIC_Br, "blx\t$func",
1208 [(ARMcall GPR:$func)]>,
1209 Requires<[IsARM, HasV5T, IsNotDarwin]> {
1211 let Inst{27-4} = 0b000100101111111111110011;
1212 let Inst{3-0} = func;
1216 // Note: Restrict $func to the tGPR regclass to prevent it being in LR.
1217 def BX : ABXIx2<(outs), (ins tGPR:$func, variable_ops),
1218 IIC_Br, "mov\tlr, pc\n\tbx\t$func",
1219 [(ARMcall_nolink tGPR:$func)]>,
1220 Requires<[IsARM, HasV4T, IsNotDarwin]> {
1222 let Inst{27-4} = 0b000100101111111111110001;
1223 let Inst{3-0} = func;
1227 def BMOVPCRX : ABXIx2<(outs), (ins tGPR:$func, variable_ops),
1228 IIC_Br, "mov\tlr, pc\n\tmov\tpc, $func",
1229 [(ARMcall_nolink tGPR:$func)]>,
1230 Requires<[IsARM, NoV4T, IsNotDarwin]> {
1232 let Inst{27-4} = 0b000110100000111100000000;
1233 let Inst{3-0} = func;
1237 // On Darwin R9 is call-clobbered.
1239 Defs = [R0, R1, R2, R3, R9, R12, LR,
1240 D0, D1, D2, D3, D4, D5, D6, D7,
1241 D16, D17, D18, D19, D20, D21, D22, D23,
1242 D24, D25, D26, D27, D28, D29, D30, D31, CPSR, FPSCR] in {
1243 def BLr9 : ABXI<0b1011, (outs), (ins i32imm:$func, variable_ops),
1244 IIC_Br, "bl\t$func",
1245 [(ARMcall tglobaladdr:$func)]>, Requires<[IsARM, IsDarwin]> {
1246 let Inst{31-28} = 0b1110;
1247 // FIXME: Encoding info for $func. Needs fixups bits.
1250 def BLr9_pred : ABI<0b1011, (outs), (ins i32imm:$func, variable_ops),
1251 IIC_Br, "bl", "\t$func",
1252 [(ARMcall_pred tglobaladdr:$func)]>,
1253 Requires<[IsARM, IsDarwin]>;
1256 def BLXr9 : AXI<(outs), (ins GPR:$func, variable_ops), BrMiscFrm,
1257 IIC_Br, "blx\t$func",
1258 [(ARMcall GPR:$func)]>, Requires<[IsARM, HasV5T, IsDarwin]> {
1260 let Inst{27-4} = 0b000100101111111111110011;
1261 let Inst{3-0} = func;
1265 // Note: Restrict $func to the tGPR regclass to prevent it being in LR.
1266 def BXr9 : ABXIx2<(outs), (ins tGPR:$func, variable_ops),
1267 IIC_Br, "mov\tlr, pc\n\tbx\t$func",
1268 [(ARMcall_nolink tGPR:$func)]>,
1269 Requires<[IsARM, HasV4T, IsDarwin]> {
1271 let Inst{27-4} = 0b000100101111111111110001;
1272 let Inst{3-0} = func;
1276 def BMOVPCRXr9 : ABXIx2<(outs), (ins tGPR:$func, variable_ops),
1277 IIC_Br, "mov\tlr, pc\n\tmov\tpc, $func",
1278 [(ARMcall_nolink tGPR:$func)]>,
1279 Requires<[IsARM, NoV4T, IsDarwin]> {
1281 let Inst{27-4} = 0b000110100000111100000000;
1282 let Inst{3-0} = func;
1288 // FIXME: These should probably be xformed into the non-TC versions of the
1289 // instructions as part of MC lowering.
1290 let isCall = 1, isTerminator = 1, isReturn = 1, isBarrier = 1 in {
1292 let Defs = [R0, R1, R2, R3, R9, R12,
1293 D0, D1, D2, D3, D4, D5, D6, D7,
1294 D16, D17, D18, D19, D20, D21, D22, D23, D24, D25, D26,
1295 D27, D28, D29, D30, D31, PC],
1297 def TCRETURNdi : AInoP<(outs), (ins i32imm:$dst, variable_ops),
1299 "@TC_RETURN","\t$dst", []>, Requires<[IsDarwin]>;
1301 def TCRETURNri : AInoP<(outs), (ins tcGPR:$dst, variable_ops),
1303 "@TC_RETURN","\t$dst", []>, Requires<[IsDarwin]>;
1305 def TAILJMPd : ABXI<0b1010, (outs), (ins brtarget:$dst, variable_ops),
1306 IIC_Br, "b\t$dst @ TAILCALL",
1307 []>, Requires<[IsDarwin]>;
1309 def TAILJMPdt: ABXI<0b1010, (outs), (ins brtarget:$dst, variable_ops),
1310 IIC_Br, "b.w\t$dst @ TAILCALL",
1311 []>, Requires<[IsDarwin]>;
1313 def TAILJMPr : AXI<(outs), (ins tcGPR:$dst, variable_ops),
1314 BrMiscFrm, IIC_Br, "bx\t$dst @ TAILCALL",
1315 []>, Requires<[IsDarwin]> {
1317 let Inst{31-4} = 0b1110000100101111111111110001;
1318 let Inst{3-0} = dst;
1322 // Non-Darwin versions (the difference is R9).
1323 let Defs = [R0, R1, R2, R3, R12,
1324 D0, D1, D2, D3, D4, D5, D6, D7,
1325 D16, D17, D18, D19, D20, D21, D22, D23, D24, D25, D26,
1326 D27, D28, D29, D30, D31, PC],
1328 def TCRETURNdiND : AInoP<(outs), (ins i32imm:$dst, variable_ops),
1330 "@TC_RETURN","\t$dst", []>, Requires<[IsNotDarwin]>;
1332 def TCRETURNriND : AInoP<(outs), (ins tcGPR:$dst, variable_ops),
1334 "@TC_RETURN","\t$dst", []>, Requires<[IsNotDarwin]>;
1336 def TAILJMPdND : ABXI<0b1010, (outs), (ins brtarget:$dst, variable_ops),
1337 IIC_Br, "b\t$dst @ TAILCALL",
1338 []>, Requires<[IsARM, IsNotDarwin]>;
1340 def TAILJMPdNDt : ABXI<0b1010, (outs), (ins brtarget:$dst, variable_ops),
1341 IIC_Br, "b.w\t$dst @ TAILCALL",
1342 []>, Requires<[IsThumb, IsNotDarwin]>;
1344 def TAILJMPrND : AXI<(outs), (ins tcGPR:$dst, variable_ops),
1345 BrMiscFrm, IIC_Br, "bx\t$dst @ TAILCALL",
1346 []>, Requires<[IsNotDarwin]> {
1348 let Inst{31-4} = 0b1110000100101111111111110001;
1349 let Inst{3-0} = dst;
1354 let isBranch = 1, isTerminator = 1 in {
1355 // B is "predicable" since it can be xformed into a Bcc.
1356 let isBarrier = 1 in {
1357 let isPredicable = 1 in
1358 def B : ABXI<0b1010, (outs), (ins brtarget:$target), IIC_Br,
1359 "b\t$target", [(br bb:$target)]>;
1361 let isNotDuplicable = 1, isIndirectBranch = 1,
1362 // FIXME: $imm field is not specified by asm string. Mark as cgonly.
1363 isCodeGenOnly = 1 in {
1364 def BR_JTr : JTI<(outs), (ins GPR:$target, jtblock_operand:$jt, i32imm:$id),
1365 IIC_Br, "mov\tpc, $target$jt",
1366 [(ARMbrjt GPR:$target, tjumptable:$jt, imm:$id)]> {
1367 let Inst{11-4} = 0b00000000;
1368 let Inst{15-12} = 0b1111;
1369 let Inst{20} = 0; // S Bit
1370 let Inst{24-21} = 0b1101;
1371 let Inst{27-25} = 0b000;
1373 def BR_JTm : JTI<(outs),
1374 (ins addrmode2:$target, jtblock_operand:$jt, i32imm:$id),
1375 IIC_Br, "ldr\tpc, $target$jt",
1376 [(ARMbrjt (i32 (load addrmode2:$target)), tjumptable:$jt,
1378 let Inst{15-12} = 0b1111;
1379 let Inst{20} = 1; // L bit
1380 let Inst{21} = 0; // W bit
1381 let Inst{22} = 0; // B bit
1382 let Inst{24} = 1; // P bit
1383 let Inst{27-25} = 0b011;
1385 def BR_JTadd : JTI<(outs),
1386 (ins GPR:$target, GPR:$idx, jtblock_operand:$jt, i32imm:$id),
1387 IIC_Br, "add\tpc, $target, $idx$jt",
1388 [(ARMbrjt (add GPR:$target, GPR:$idx), tjumptable:$jt,
1390 let Inst{15-12} = 0b1111;
1391 let Inst{20} = 0; // S bit
1392 let Inst{24-21} = 0b0100;
1393 let Inst{27-25} = 0b000;
1395 } // isNotDuplicable = 1, isIndirectBranch = 1
1398 // FIXME: should be able to write a pattern for ARMBrcond, but can't use
1399 // a two-value operand where a dag node expects two operands. :(
1400 def Bcc : ABI<0b1010, (outs), (ins brtarget:$target),
1401 IIC_Br, "b", "\t$target",
1402 [/*(ARMbrcond bb:$target, imm:$cc, CCR:$ccr)*/]>;
1405 // Branch and Exchange Jazelle -- for disassembly only
1406 def BXJ : ABI<0b0001, (outs), (ins GPR:$func), NoItinerary, "bxj", "\t$func",
1407 [/* For disassembly only; pattern left blank */]> {
1408 let Inst{23-20} = 0b0010;
1409 //let Inst{19-8} = 0xfff;
1410 let Inst{7-4} = 0b0010;
1413 // Secure Monitor Call is a system instruction -- for disassembly only
1414 def SMC : ABI<0b0001, (outs), (ins i32imm:$opt), NoItinerary, "smc", "\t$opt",
1415 [/* For disassembly only; pattern left blank */]> {
1417 let Inst{23-4} = 0b01100000000000000111;
1418 let Inst{3-0} = opt;
1421 // Supervisor Call (Software Interrupt) -- for disassembly only
1423 def SVC : ABI<0b1111, (outs), (ins i32imm:$svc), IIC_Br, "svc", "\t$svc",
1424 [/* For disassembly only; pattern left blank */]> {
1426 let Inst{23-0} = svc;
1430 // Store Return State is a system instruction -- for disassembly only
1431 let isCodeGenOnly = 1 in { // FIXME: This should not use submode!
1432 def SRSW : ABXI<{1,0,0,?}, (outs), (ins ldstm_mode:$amode, i32imm:$mode),
1433 NoItinerary, "srs${amode}\tsp!, $mode",
1434 [/* For disassembly only; pattern left blank */]> {
1435 let Inst{31-28} = 0b1111;
1436 let Inst{22-20} = 0b110; // W = 1
1439 def SRS : ABXI<{1,0,0,?}, (outs), (ins ldstm_mode:$amode, i32imm:$mode),
1440 NoItinerary, "srs${amode}\tsp, $mode",
1441 [/* For disassembly only; pattern left blank */]> {
1442 let Inst{31-28} = 0b1111;
1443 let Inst{22-20} = 0b100; // W = 0
1446 // Return From Exception is a system instruction -- for disassembly only
1447 def RFEW : ABXI<{1,0,0,?}, (outs), (ins ldstm_mode:$amode, GPR:$base),
1448 NoItinerary, "rfe${amode}\t$base!",
1449 [/* For disassembly only; pattern left blank */]> {
1450 let Inst{31-28} = 0b1111;
1451 let Inst{22-20} = 0b011; // W = 1
1454 def RFE : ABXI<{1,0,0,?}, (outs), (ins ldstm_mode:$amode, GPR:$base),
1455 NoItinerary, "rfe${amode}\t$base",
1456 [/* For disassembly only; pattern left blank */]> {
1457 let Inst{31-28} = 0b1111;
1458 let Inst{22-20} = 0b001; // W = 0
1460 } // isCodeGenOnly = 1
1462 //===----------------------------------------------------------------------===//
1463 // Load / store Instructions.
1469 defm LDR : AI_ldr1<0, "ldr", IIC_iLoad_r, IIC_iLoad_si,
1470 UnOpFrag<(load node:$Src)>>;
1471 defm LDRB : AI_ldr1<1, "ldrb", IIC_iLoad_bh_r, IIC_iLoad_bh_si,
1472 UnOpFrag<(zextloadi8 node:$Src)>>;
1473 defm STR : AI_str1<0, "str", IIC_iStore_r, IIC_iStore_si,
1474 BinOpFrag<(store node:$LHS, node:$RHS)>>;
1475 defm STRB : AI_str1<1, "strb", IIC_iStore_bh_r, IIC_iStore_bh_si,
1476 BinOpFrag<(truncstorei8 node:$LHS, node:$RHS)>>;
1478 // Special LDR for loads from non-pc-relative constpools.
1479 let canFoldAsLoad = 1, mayLoad = 1, neverHasSideEffects = 1,
1480 isReMaterializable = 1 in
1481 def LDRcp : AIldst1<0b010, 0, 1, (outs GPR:$Rt), (ins addrmode_imm12:$addr),
1482 AddrMode_i12, LdFrm, IIC_iLoad_r, "ldr", "\t$Rt, $addr", []> {
1485 let Inst{23} = addr{12}; // U (add = ('U' == 1))
1486 let Inst{19-16} = 0b1111;
1487 let Inst{15-12} = Rt;
1488 let Inst{11-0} = addr{11-0}; // imm12
1491 // Loads with zero extension
1492 def LDRH : AI3ldh<(outs GPR:$dst), (ins addrmode3:$addr), LdMiscFrm,
1493 IIC_iLoad_bh_r, "ldrh", "\t$dst, $addr",
1494 [(set GPR:$dst, (zextloadi16 addrmode3:$addr))]>;
1496 // Loads with sign extension
1497 def LDRSH : AI3ldsh<(outs GPR:$dst), (ins addrmode3:$addr), LdMiscFrm,
1498 IIC_iLoad_bh_r, "ldrsh", "\t$dst, $addr",
1499 [(set GPR:$dst, (sextloadi16 addrmode3:$addr))]>;
1501 def LDRSB : AI3ldsb<(outs GPR:$dst), (ins addrmode3:$addr), LdMiscFrm,
1502 IIC_iLoad_bh_r, "ldrsb", "\t$dst, $addr",
1503 [(set GPR:$dst, (sextloadi8 addrmode3:$addr))]>;
1505 let mayLoad = 1, neverHasSideEffects = 1, hasExtraDefRegAllocReq = 1,
1506 isCodeGenOnly = 1 in { // $dst2 doesn't exist in asmstring?
1508 def LDRD : AI3ldd<(outs GPR:$dst1, GPR:$dst2), (ins addrmode3:$addr), LdMiscFrm,
1509 IIC_iLoad_d_r, "ldrd", "\t$dst1, $addr",
1510 []>, Requires<[IsARM, HasV5TE]>;
1513 def LDR_PRE : AI2ldwpr<(outs GPR:$dst, GPR:$base_wb),
1514 (ins addrmode2:$addr), LdFrm, IIC_iLoad_ru,
1515 "ldr", "\t$dst, $addr!", "$addr.base = $base_wb", []>;
1517 def LDR_POST : AI2ldwpo<(outs GPR:$dst, GPR:$base_wb),
1518 (ins GPR:$base, am2offset:$offset), LdFrm, IIC_iLoad_ru,
1519 "ldr", "\t$dst, [$base], $offset", "$base = $base_wb", []>;
1521 def LDRH_PRE : AI3ldhpr<(outs GPR:$dst, GPR:$base_wb),
1522 (ins addrmode3:$addr), LdMiscFrm, IIC_iLoad_bh_ru,
1523 "ldrh", "\t$dst, $addr!", "$addr.base = $base_wb", []>;
1525 def LDRH_POST : AI3ldhpo<(outs GPR:$dst, GPR:$base_wb),
1526 (ins GPR:$base,am3offset:$offset), LdMiscFrm, IIC_iLoad_bh_ru,
1527 "ldrh", "\t$dst, [$base], $offset", "$base = $base_wb", []>;
1529 def LDRB_PRE : AI2ldbpr<(outs GPR:$dst, GPR:$base_wb),
1530 (ins addrmode2:$addr), LdFrm, IIC_iLoad_bh_ru,
1531 "ldrb", "\t$dst, $addr!", "$addr.base = $base_wb", []>;
1533 def LDRB_POST : AI2ldbpo<(outs GPR:$dst, GPR:$base_wb),
1534 (ins GPR:$base,am2offset:$offset), LdFrm, IIC_iLoad_bh_ru,
1535 "ldrb", "\t$dst, [$base], $offset", "$base = $base_wb", []>;
1537 def LDRSH_PRE : AI3ldshpr<(outs GPR:$dst, GPR:$base_wb),
1538 (ins addrmode3:$addr), LdMiscFrm, IIC_iLoad_bh_ru,
1539 "ldrsh", "\t$dst, $addr!", "$addr.base = $base_wb", []>;
1541 def LDRSH_POST: AI3ldshpo<(outs GPR:$dst, GPR:$base_wb),
1542 (ins GPR:$base,am3offset:$offset), LdMiscFrm, IIC_iLoad_bh_ru,
1543 "ldrsh", "\t$dst, [$base], $offset", "$base = $base_wb", []>;
1545 def LDRSB_PRE : AI3ldsbpr<(outs GPR:$dst, GPR:$base_wb),
1546 (ins addrmode3:$addr), LdMiscFrm, IIC_iLoad_bh_ru,
1547 "ldrsb", "\t$dst, $addr!", "$addr.base = $base_wb", []>;
1549 def LDRSB_POST: AI3ldsbpo<(outs GPR:$dst, GPR:$base_wb),
1550 (ins GPR:$base,am3offset:$offset), LdMiscFrm, IIC_iLoad_ru,
1551 "ldrsb", "\t$dst, [$base], $offset", "$base = $base_wb", []>;
1553 // For disassembly only
1554 def LDRD_PRE : AI3lddpr<(outs GPR:$dst1, GPR:$dst2, GPR:$base_wb),
1555 (ins addrmode3:$addr), LdMiscFrm, IIC_iLoad_d_ru,
1556 "ldrd", "\t$dst1, $dst2, $addr!", "$addr.base = $base_wb", []>,
1557 Requires<[IsARM, HasV5TE]>;
1559 // For disassembly only
1560 def LDRD_POST : AI3lddpo<(outs GPR:$dst1, GPR:$dst2, GPR:$base_wb),
1561 (ins GPR:$base,am3offset:$offset), LdMiscFrm, IIC_iLoad_d_ru,
1562 "ldrd", "\t$dst1, $dst2, [$base], $offset", "$base = $base_wb", []>,
1563 Requires<[IsARM, HasV5TE]>;
1565 } // mayLoad = 1, neverHasSideEffects = 1, hasExtraDefRegAllocReq = 1
1567 // LDRT, LDRBT, LDRSBT, LDRHT, LDRSHT are for disassembly only.
1569 def LDRT : AI2ldwpo<(outs GPR:$dst, GPR:$base_wb),
1570 (ins GPR:$base, am2offset:$offset), LdFrm, IIC_iLoad_ru,
1571 "ldrt", "\t$dst, [$base], $offset", "$base = $base_wb", []> {
1572 let Inst{21} = 1; // overwrite
1575 def LDRBT : AI2ldbpo<(outs GPR:$dst, GPR:$base_wb),
1576 (ins GPR:$base,am2offset:$offset), LdFrm, IIC_iLoad_bh_ru,
1577 "ldrbt", "\t$dst, [$base], $offset", "$base = $base_wb", []> {
1578 let Inst{21} = 1; // overwrite
1581 def LDRSBT : AI3ldsbpo<(outs GPR:$dst, GPR:$base_wb),
1582 (ins GPR:$base,am3offset:$offset), LdMiscFrm, IIC_iLoad_bh_ru,
1583 "ldrsbt", "\t$dst, [$base], $offset", "$base = $base_wb", []> {
1584 let Inst{21} = 1; // overwrite
1587 def LDRHT : AI3ldhpo<(outs GPR:$dst, GPR:$base_wb),
1588 (ins GPR:$base, am3offset:$offset), LdMiscFrm, IIC_iLoad_bh_ru,
1589 "ldrht", "\t$dst, [$base], $offset", "$base = $base_wb", []> {
1590 let Inst{21} = 1; // overwrite
1593 def LDRSHT : AI3ldshpo<(outs GPR:$dst, GPR:$base_wb),
1594 (ins GPR:$base,am3offset:$offset), LdMiscFrm, IIC_iLoad_bh_ru,
1595 "ldrsht", "\t$dst, [$base], $offset", "$base = $base_wb", []> {
1596 let Inst{21} = 1; // overwrite
1601 // Stores with truncate
1602 def STRH : AI3sth<(outs), (ins GPR:$src, addrmode3:$addr), StMiscFrm,
1603 IIC_iStore_bh_r, "strh", "\t$src, $addr",
1604 [(truncstorei16 GPR:$src, addrmode3:$addr)]>;
1607 let mayStore = 1, neverHasSideEffects = 1, hasExtraSrcRegAllocReq = 1,
1608 isCodeGenOnly = 1 in // $src2 doesn't exist in asm string
1609 def STRD : AI3std<(outs), (ins GPR:$src1, GPR:$src2, addrmode3:$addr),
1610 StMiscFrm, IIC_iStore_d_r,
1611 "strd", "\t$src1, $addr", []>, Requires<[IsARM, HasV5TE]>;
1614 def STR_PRE : AI2stwpr<(outs GPR:$base_wb),
1615 (ins GPR:$src, GPR:$base, am2offset:$offset),
1616 StFrm, IIC_iStore_ru,
1617 "str", "\t$src, [$base, $offset]!", "$base = $base_wb",
1619 (pre_store GPR:$src, GPR:$base, am2offset:$offset))]>;
1621 def STR_POST : AI2stwpo<(outs GPR:$base_wb),
1622 (ins GPR:$src, GPR:$base,am2offset:$offset),
1623 StFrm, IIC_iStore_ru,
1624 "str", "\t$src, [$base], $offset", "$base = $base_wb",
1626 (post_store GPR:$src, GPR:$base, am2offset:$offset))]>;
1628 def STRH_PRE : AI3sthpr<(outs GPR:$base_wb),
1629 (ins GPR:$src, GPR:$base,am3offset:$offset),
1630 StMiscFrm, IIC_iStore_ru,
1631 "strh", "\t$src, [$base, $offset]!", "$base = $base_wb",
1633 (pre_truncsti16 GPR:$src, GPR:$base,am3offset:$offset))]>;
1635 def STRH_POST: AI3sthpo<(outs GPR:$base_wb),
1636 (ins GPR:$src, GPR:$base,am3offset:$offset),
1637 StMiscFrm, IIC_iStore_bh_ru,
1638 "strh", "\t$src, [$base], $offset", "$base = $base_wb",
1639 [(set GPR:$base_wb, (post_truncsti16 GPR:$src,
1640 GPR:$base, am3offset:$offset))]>;
1642 def STRB_PRE : AI2stbpr<(outs GPR:$base_wb),
1643 (ins GPR:$src, GPR:$base,am2offset:$offset),
1644 StFrm, IIC_iStore_bh_ru,
1645 "strb", "\t$src, [$base, $offset]!", "$base = $base_wb",
1646 [(set GPR:$base_wb, (pre_truncsti8 GPR:$src,
1647 GPR:$base, am2offset:$offset))]>;
1649 def STRB_POST: AI2stbpo<(outs GPR:$base_wb),
1650 (ins GPR:$src, GPR:$base,am2offset:$offset),
1651 StFrm, IIC_iStore_bh_ru,
1652 "strb", "\t$src, [$base], $offset", "$base = $base_wb",
1653 [(set GPR:$base_wb, (post_truncsti8 GPR:$src,
1654 GPR:$base, am2offset:$offset))]>;
1656 // For disassembly only
1657 def STRD_PRE : AI3stdpr<(outs GPR:$base_wb),
1658 (ins GPR:$src1, GPR:$src2, GPR:$base, am3offset:$offset),
1659 StMiscFrm, IIC_iStore_d_ru,
1660 "strd", "\t$src1, $src2, [$base, $offset]!",
1661 "$base = $base_wb", []>;
1663 // For disassembly only
1664 def STRD_POST: AI3stdpo<(outs GPR:$base_wb),
1665 (ins GPR:$src1, GPR:$src2, GPR:$base, am3offset:$offset),
1666 StMiscFrm, IIC_iStore_d_ru,
1667 "strd", "\t$src1, $src2, [$base], $offset",
1668 "$base = $base_wb", []>;
1670 // STRT, STRBT, and STRHT are for disassembly only.
1672 def STRT : AI2stwpo<(outs GPR:$base_wb),
1673 (ins GPR:$src, GPR:$base,am2offset:$offset),
1674 StFrm, IIC_iStore_ru,
1675 "strt", "\t$src, [$base], $offset", "$base = $base_wb",
1676 [/* For disassembly only; pattern left blank */]> {
1677 let Inst{21} = 1; // overwrite
1680 def STRBT : AI2stbpo<(outs GPR:$base_wb),
1681 (ins GPR:$src, GPR:$base,am2offset:$offset),
1682 StFrm, IIC_iStore_bh_ru,
1683 "strbt", "\t$src, [$base], $offset", "$base = $base_wb",
1684 [/* For disassembly only; pattern left blank */]> {
1685 let Inst{21} = 1; // overwrite
1688 def STRHT: AI3sthpo<(outs GPR:$base_wb),
1689 (ins GPR:$src, GPR:$base,am3offset:$offset),
1690 StMiscFrm, IIC_iStore_bh_ru,
1691 "strht", "\t$src, [$base], $offset", "$base = $base_wb",
1692 [/* For disassembly only; pattern left blank */]> {
1693 let Inst{21} = 1; // overwrite
1696 //===----------------------------------------------------------------------===//
1697 // Load / store multiple Instructions.
1700 let mayLoad = 1, neverHasSideEffects = 1, hasExtraDefRegAllocReq = 1,
1701 isCodeGenOnly = 1 in {
1702 def LDM : AXI4ld<(outs), (ins GPR:$Rn, ldstm_mode:$amode, pred:$p,
1703 reglist:$dsts, variable_ops),
1704 IndexModeNone, LdStMulFrm, IIC_iLoad_m,
1705 "ldm${amode}${p}\t$Rn, $dsts", "", []>;
1707 def LDM_UPD : AXI4ld<(outs GPR:$wb), (ins GPR:$Rn, ldstm_mode:$amode, pred:$p,
1708 reglist:$dsts, variable_ops),
1709 IndexModeUpd, LdStMulFrm, IIC_iLoad_mu,
1710 "ldm${amode}${p}\t$Rn!, $dsts",
1712 } // mayLoad, neverHasSideEffects, hasExtraDefRegAllocReq
1714 let mayStore = 1, neverHasSideEffects = 1, hasExtraSrcRegAllocReq = 1,
1715 isCodeGenOnly = 1 in {
1716 def STM : AXI4st<(outs), (ins GPR:$Rn, ldstm_mode:$amode, pred:$p,
1717 reglist:$srcs, variable_ops),
1718 IndexModeNone, LdStMulFrm, IIC_iStore_m,
1719 "stm${amode}${p}\t$Rn, $srcs", "", []>;
1721 def STM_UPD : AXI4st<(outs GPR:$wb), (ins GPR:$Rn, ldstm_mode:$amode, pred:$p,
1722 reglist:$srcs, variable_ops),
1723 IndexModeUpd, LdStMulFrm, IIC_iStore_mu,
1724 "stm${amode}${p}\t$Rn!, $srcs",
1726 } // mayStore, neverHasSideEffects, hasExtraSrcRegAllocReq
1728 //===----------------------------------------------------------------------===//
1729 // Move Instructions.
1732 let neverHasSideEffects = 1 in
1733 def MOVr : AsI1<0b1101, (outs GPR:$Rd), (ins GPR:$Rm), DPFrm, IIC_iMOVr,
1734 "mov", "\t$Rd, $Rm", []>, UnaryDP {
1738 let Inst{11-4} = 0b00000000;
1741 let Inst{15-12} = Rd;
1744 // A version for the smaller set of tail call registers.
1745 let neverHasSideEffects = 1 in
1746 def MOVr_TC : AsI1<0b1101, (outs tcGPR:$Rd), (ins tcGPR:$Rm), DPFrm,
1747 IIC_iMOVr, "mov", "\t$Rd, $Rm", []>, UnaryDP {
1751 let Inst{11-4} = 0b00000000;
1754 let Inst{15-12} = Rd;
1757 def MOVs : AsI1<0b1101, (outs GPR:$Rd), (ins shift_so_reg:$src),
1758 DPSoRegFrm, IIC_iMOVsr,
1759 "mov", "\t$Rd, $src", [(set GPR:$Rd, shift_so_reg:$src)]>,
1763 let Inst{15-12} = Rd;
1764 let Inst{11-0} = src;
1768 let isReMaterializable = 1, isAsCheapAsAMove = 1 in
1769 def MOVi : AsI1<0b1101, (outs GPR:$Rd), (ins so_imm:$imm), DPFrm, IIC_iMOVi,
1770 "mov", "\t$Rd, $imm", [(set GPR:$Rd, so_imm:$imm)]>, UnaryDP {
1774 let Inst{15-12} = Rd;
1775 let Inst{19-16} = 0b0000;
1776 let Inst{11-0} = imm;
1779 let isReMaterializable = 1, isAsCheapAsAMove = 1 in
1780 def MOVi16 : AI1<0b1000, (outs GPR:$Rd), (ins i32imm:$imm),
1782 "movw", "\t$Rd, $imm",
1783 [(set GPR:$Rd, imm0_65535:$imm)]>,
1784 Requires<[IsARM, HasV6T2]>, UnaryDP {
1787 let Inst{15-12} = Rd;
1788 let Inst{11-0} = imm{11-0};
1789 let Inst{19-16} = imm{15-12};
1794 let Constraints = "$src = $Rd" in
1795 def MOVTi16 : AI1<0b1010, (outs GPR:$Rd), (ins GPR:$src, i32imm:$imm),
1797 "movt", "\t$Rd, $imm",
1799 (or (and GPR:$src, 0xffff),
1800 lo16AllZero:$imm))]>, UnaryDP,
1801 Requires<[IsARM, HasV6T2]> {
1804 let Inst{15-12} = Rd;
1805 let Inst{11-0} = imm{11-0};
1806 let Inst{19-16} = imm{15-12};
1811 def : ARMPat<(or GPR:$src, 0xffff0000), (MOVTi16 GPR:$src, 0xffff)>,
1812 Requires<[IsARM, HasV6T2]>;
1814 let Uses = [CPSR] in
1815 def RRX: PseudoInst<(outs GPR:$Rd), (ins GPR:$Rm), IIC_iMOVsi, "",
1816 [(set GPR:$Rd, (ARMrrx GPR:$Rm))]>, UnaryDP,
1819 // These aren't really mov instructions, but we have to define them this way
1820 // due to flag operands.
1822 let Defs = [CPSR] in {
1823 def MOVsrl_flag : PseudoInst<(outs GPR:$dst), (ins GPR:$src), IIC_iMOVsi, "",
1824 [(set GPR:$dst, (ARMsrl_flag GPR:$src))]>, UnaryDP,
1826 def MOVsra_flag : PseudoInst<(outs GPR:$dst), (ins GPR:$src), IIC_iMOVsi, "",
1827 [(set GPR:$dst, (ARMsra_flag GPR:$src))]>, UnaryDP,
1831 //===----------------------------------------------------------------------===//
1832 // Extend Instructions.
1837 defm SXTB : AI_ext_rrot<0b01101010,
1838 "sxtb", UnOpFrag<(sext_inreg node:$Src, i8)>>;
1839 defm SXTH : AI_ext_rrot<0b01101011,
1840 "sxth", UnOpFrag<(sext_inreg node:$Src, i16)>>;
1842 defm SXTAB : AI_exta_rrot<0b01101010,
1843 "sxtab", BinOpFrag<(add node:$LHS, (sext_inreg node:$RHS, i8))>>;
1844 defm SXTAH : AI_exta_rrot<0b01101011,
1845 "sxtah", BinOpFrag<(add node:$LHS, (sext_inreg node:$RHS,i16))>>;
1847 // For disassembly only
1848 defm SXTB16 : AI_ext_rrot_np<0b01101000, "sxtb16">;
1850 // For disassembly only
1851 defm SXTAB16 : AI_exta_rrot_np<0b01101000, "sxtab16">;
1855 let AddedComplexity = 16 in {
1856 defm UXTB : AI_ext_rrot<0b01101110,
1857 "uxtb" , UnOpFrag<(and node:$Src, 0x000000FF)>>;
1858 defm UXTH : AI_ext_rrot<0b01101111,
1859 "uxth" , UnOpFrag<(and node:$Src, 0x0000FFFF)>>;
1860 defm UXTB16 : AI_ext_rrot<0b01101100,
1861 "uxtb16", UnOpFrag<(and node:$Src, 0x00FF00FF)>>;
1863 // FIXME: This pattern incorrectly assumes the shl operator is a rotate.
1864 // The transformation should probably be done as a combiner action
1865 // instead so we can include a check for masking back in the upper
1866 // eight bits of the source into the lower eight bits of the result.
1867 //def : ARMV6Pat<(and (shl GPR:$Src, (i32 8)), 0xFF00FF),
1868 // (UXTB16r_rot GPR:$Src, 24)>;
1869 def : ARMV6Pat<(and (srl GPR:$Src, (i32 8)), 0xFF00FF),
1870 (UXTB16r_rot GPR:$Src, 8)>;
1872 defm UXTAB : AI_exta_rrot<0b01101110, "uxtab",
1873 BinOpFrag<(add node:$LHS, (and node:$RHS, 0x00FF))>>;
1874 defm UXTAH : AI_exta_rrot<0b01101111, "uxtah",
1875 BinOpFrag<(add node:$LHS, (and node:$RHS, 0xFFFF))>>;
1878 // This isn't safe in general, the add is two 16-bit units, not a 32-bit add.
1879 // For disassembly only
1880 defm UXTAB16 : AI_exta_rrot_np<0b01101100, "uxtab16">;
1883 def SBFX : I<(outs GPR:$Rd),
1884 (ins GPR:$Rn, imm0_31:$lsb, imm0_31_m1:$width),
1885 AddrMode1, Size4Bytes, IndexModeNone, DPFrm, IIC_iUNAsi,
1886 "sbfx", "\t$Rd, $Rn, $lsb, $width", "", []>,
1887 Requires<[IsARM, HasV6T2]> {
1892 let Inst{27-21} = 0b0111101;
1893 let Inst{6-4} = 0b101;
1894 let Inst{20-16} = width;
1895 let Inst{15-12} = Rd;
1896 let Inst{11-7} = lsb;
1900 def UBFX : I<(outs GPR:$Rd),
1901 (ins GPR:$Rn, imm0_31:$lsb, imm0_31_m1:$width),
1902 AddrMode1, Size4Bytes, IndexModeNone, DPFrm, IIC_iUNAsi,
1903 "ubfx", "\t$Rd, $Rn, $lsb, $width", "", []>,
1904 Requires<[IsARM, HasV6T2]> {
1909 let Inst{27-21} = 0b0111111;
1910 let Inst{6-4} = 0b101;
1911 let Inst{20-16} = width;
1912 let Inst{15-12} = Rd;
1913 let Inst{11-7} = lsb;
1917 //===----------------------------------------------------------------------===//
1918 // Arithmetic Instructions.
1921 defm ADD : AsI1_bin_irs<0b0100, "add",
1922 IIC_iALUi, IIC_iALUr, IIC_iALUsr,
1923 BinOpFrag<(add node:$LHS, node:$RHS)>, 1>;
1924 defm SUB : AsI1_bin_irs<0b0010, "sub",
1925 IIC_iALUi, IIC_iALUr, IIC_iALUsr,
1926 BinOpFrag<(sub node:$LHS, node:$RHS)>>;
1928 // ADD and SUB with 's' bit set.
1929 defm ADDS : AI1_bin_s_irs<0b0100, "adds",
1930 IIC_iALUi, IIC_iALUr, IIC_iALUsr,
1931 BinOpFrag<(addc node:$LHS, node:$RHS)>, 1>;
1932 defm SUBS : AI1_bin_s_irs<0b0010, "subs",
1933 IIC_iALUi, IIC_iALUr, IIC_iALUsr,
1934 BinOpFrag<(subc node:$LHS, node:$RHS)>>;
1936 defm ADC : AI1_adde_sube_irs<0b0101, "adc",
1937 BinOpFrag<(adde_dead_carry node:$LHS, node:$RHS)>, 1>;
1938 defm SBC : AI1_adde_sube_irs<0b0110, "sbc",
1939 BinOpFrag<(sube_dead_carry node:$LHS, node:$RHS)>>;
1940 defm ADCS : AI1_adde_sube_s_irs<0b0101, "adcs",
1941 BinOpFrag<(adde_live_carry node:$LHS, node:$RHS)>, 1>;
1942 defm SBCS : AI1_adde_sube_s_irs<0b0110, "sbcs",
1943 BinOpFrag<(sube_live_carry node:$LHS, node:$RHS) >>;
1945 def RSBri : AsI1<0b0011, (outs GPR:$Rd), (ins GPR:$Rn, so_imm:$imm), DPFrm,
1946 IIC_iALUi, "rsb", "\t$Rd, $Rn, $imm",
1947 [(set GPR:$Rd, (sub so_imm:$imm, GPR:$Rn))]> {
1952 let Inst{15-12} = Rd;
1953 let Inst{19-16} = Rn;
1954 let Inst{11-0} = imm;
1957 // The reg/reg form is only defined for the disassembler; for codegen it is
1958 // equivalent to SUBrr.
1959 def RSBrr : AsI1<0b0011, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm), DPFrm,
1960 IIC_iALUr, "rsb", "\t$Rd, $Rn, $Rm",
1961 [/* For disassembly only; pattern left blank */]> {
1965 let Inst{11-4} = 0b00000000;
1968 let Inst{15-12} = Rd;
1969 let Inst{19-16} = Rn;
1972 def RSBrs : AsI1<0b0011, (outs GPR:$Rd), (ins GPR:$Rn, so_reg:$shift),
1973 DPSoRegFrm, IIC_iALUsr, "rsb", "\t$Rd, $Rn, $shift",
1974 [(set GPR:$Rd, (sub so_reg:$shift, GPR:$Rn))]> {
1979 let Inst{11-0} = shift;
1980 let Inst{15-12} = Rd;
1981 let Inst{19-16} = Rn;
1984 // RSB with 's' bit set.
1985 let Defs = [CPSR] in {
1986 def RSBSri : AI1<0b0011, (outs GPR:$Rd), (ins GPR:$Rn, so_imm:$imm), DPFrm,
1987 IIC_iALUi, "rsbs", "\t$Rd, $Rn, $imm",
1988 [(set GPR:$Rd, (subc so_imm:$imm, GPR:$Rn))]> {
1994 let Inst{15-12} = Rd;
1995 let Inst{19-16} = Rn;
1996 let Inst{11-0} = imm;
1998 def RSBSrs : AI1<0b0011, (outs GPR:$Rd), (ins GPR:$Rn, so_reg:$shift),
1999 DPSoRegFrm, IIC_iALUsr, "rsbs", "\t$Rd, $Rn, $shift",
2000 [(set GPR:$Rd, (subc so_reg:$shift, GPR:$Rn))]> {
2006 let Inst{11-0} = shift;
2007 let Inst{15-12} = Rd;
2008 let Inst{19-16} = Rn;
2012 let Uses = [CPSR] in {
2013 def RSCri : AsI1<0b0111, (outs GPR:$Rd), (ins GPR:$Rn, so_imm:$imm),
2014 DPFrm, IIC_iALUi, "rsc", "\t$Rd, $Rn, $imm",
2015 [(set GPR:$Rd, (sube_dead_carry so_imm:$imm, GPR:$Rn))]>,
2021 let Inst{15-12} = Rd;
2022 let Inst{19-16} = Rn;
2023 let Inst{11-0} = imm;
2025 // The reg/reg form is only defined for the disassembler; for codegen it is
2026 // equivalent to SUBrr.
2027 def RSCrr : AsI1<0b0111, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm),
2028 DPFrm, IIC_iALUr, "rsc", "\t$Rd, $Rn, $Rm",
2029 [/* For disassembly only; pattern left blank */]> {
2033 let Inst{11-4} = 0b00000000;
2036 let Inst{15-12} = Rd;
2037 let Inst{19-16} = Rn;
2039 def RSCrs : AsI1<0b0111, (outs GPR:$Rd), (ins GPR:$Rn, so_reg:$shift),
2040 DPSoRegFrm, IIC_iALUsr, "rsc", "\t$Rd, $Rn, $shift",
2041 [(set GPR:$Rd, (sube_dead_carry so_reg:$shift, GPR:$Rn))]>,
2047 let Inst{11-0} = shift;
2048 let Inst{15-12} = Rd;
2049 let Inst{19-16} = Rn;
2053 // FIXME: Allow these to be predicated.
2054 let Defs = [CPSR], Uses = [CPSR] in {
2055 def RSCSri : AXI1<0b0111, (outs GPR:$Rd), (ins GPR:$Rn, so_imm:$imm),
2056 DPFrm, IIC_iALUi, "rscs\t$Rd, $Rn, $imm",
2057 [(set GPR:$Rd, (sube_dead_carry so_imm:$imm, GPR:$Rn))]>,
2064 let Inst{15-12} = Rd;
2065 let Inst{19-16} = Rn;
2066 let Inst{11-0} = imm;
2068 def RSCSrs : AXI1<0b0111, (outs GPR:$Rd), (ins GPR:$Rn, so_reg:$shift),
2069 DPSoRegFrm, IIC_iALUsr, "rscs\t$Rd, $Rn, $shift",
2070 [(set GPR:$Rd, (sube_dead_carry so_reg:$shift, GPR:$Rn))]>,
2077 let Inst{11-0} = shift;
2078 let Inst{15-12} = Rd;
2079 let Inst{19-16} = Rn;
2083 // (sub X, imm) gets canonicalized to (add X, -imm). Match this form.
2084 // The assume-no-carry-in form uses the negation of the input since add/sub
2085 // assume opposite meanings of the carry flag (i.e., carry == !borrow).
2086 // See the definition of AddWithCarry() in the ARM ARM A2.2.1 for the gory
2088 def : ARMPat<(add GPR:$src, so_imm_neg:$imm),
2089 (SUBri GPR:$src, so_imm_neg:$imm)>;
2090 def : ARMPat<(addc GPR:$src, so_imm_neg:$imm),
2091 (SUBSri GPR:$src, so_imm_neg:$imm)>;
2092 // The with-carry-in form matches bitwise not instead of the negation.
2093 // Effectively, the inverse interpretation of the carry flag already accounts
2094 // for part of the negation.
2095 def : ARMPat<(adde GPR:$src, so_imm_not:$imm),
2096 (SBCri GPR:$src, so_imm_not:$imm)>;
2098 // Note: These are implemented in C++ code, because they have to generate
2099 // ADD/SUBrs instructions, which use a complex pattern that a xform function
2101 // (mul X, 2^n+1) -> (add (X << n), X)
2102 // (mul X, 2^n-1) -> (rsb X, (X << n))
2104 // ARM Arithmetic Instruction -- for disassembly only
2105 // GPR:$dst = GPR:$a op GPR:$b
2106 class AAI<bits<8> op27_20, bits<8> op11_4, string opc,
2107 list<dag> pattern = [/* For disassembly only; pattern left blank */]>
2108 : AI<(outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm), DPFrm, IIC_iALUr,
2109 opc, "\t$Rd, $Rn, $Rm", pattern> {
2113 let Inst{27-20} = op27_20;
2114 let Inst{11-4} = op11_4;
2115 let Inst{19-16} = Rn;
2116 let Inst{15-12} = Rd;
2120 // Saturating add/subtract -- for disassembly only
2122 def QADD : AAI<0b00010000, 0b00000101, "qadd",
2123 [(set GPR:$Rd, (int_arm_qadd GPR:$Rn, GPR:$Rm))]>;
2124 def QSUB : AAI<0b00010010, 0b00000101, "qsub",
2125 [(set GPR:$Rd, (int_arm_qsub GPR:$Rn, GPR:$Rm))]>;
2126 def QDADD : AAI<0b00010100, 0b00000101, "qdadd">;
2127 def QDSUB : AAI<0b00010110, 0b00000101, "qdsub">;
2129 def QADD16 : AAI<0b01100010, 0b11110001, "qadd16">;
2130 def QADD8 : AAI<0b01100010, 0b11111001, "qadd8">;
2131 def QASX : AAI<0b01100010, 0b11110011, "qasx">;
2132 def QSAX : AAI<0b01100010, 0b11110101, "qsax">;
2133 def QSUB16 : AAI<0b01100010, 0b11110111, "qsub16">;
2134 def QSUB8 : AAI<0b01100010, 0b11111111, "qsub8">;
2135 def UQADD16 : AAI<0b01100110, 0b11110001, "uqadd16">;
2136 def UQADD8 : AAI<0b01100110, 0b11111001, "uqadd8">;
2137 def UQASX : AAI<0b01100110, 0b11110011, "uqasx">;
2138 def UQSAX : AAI<0b01100110, 0b11110101, "uqsax">;
2139 def UQSUB16 : AAI<0b01100110, 0b11110111, "uqsub16">;
2140 def UQSUB8 : AAI<0b01100110, 0b11111111, "uqsub8">;
2142 // Signed/Unsigned add/subtract -- for disassembly only
2144 def SASX : AAI<0b01100001, 0b11110011, "sasx">;
2145 def SADD16 : AAI<0b01100001, 0b11110001, "sadd16">;
2146 def SADD8 : AAI<0b01100001, 0b11111001, "sadd8">;
2147 def SSAX : AAI<0b01100001, 0b11110101, "ssax">;
2148 def SSUB16 : AAI<0b01100001, 0b11110111, "ssub16">;
2149 def SSUB8 : AAI<0b01100001, 0b11111111, "ssub8">;
2150 def UASX : AAI<0b01100101, 0b11110011, "uasx">;
2151 def UADD16 : AAI<0b01100101, 0b11110001, "uadd16">;
2152 def UADD8 : AAI<0b01100101, 0b11111001, "uadd8">;
2153 def USAX : AAI<0b01100101, 0b11110101, "usax">;
2154 def USUB16 : AAI<0b01100101, 0b11110111, "usub16">;
2155 def USUB8 : AAI<0b01100101, 0b11111111, "usub8">;
2157 // Signed/Unsigned halving add/subtract -- for disassembly only
2159 def SHASX : AAI<0b01100011, 0b11110011, "shasx">;
2160 def SHADD16 : AAI<0b01100011, 0b11110001, "shadd16">;
2161 def SHADD8 : AAI<0b01100011, 0b11111001, "shadd8">;
2162 def SHSAX : AAI<0b01100011, 0b11110101, "shsax">;
2163 def SHSUB16 : AAI<0b01100011, 0b11110111, "shsub16">;
2164 def SHSUB8 : AAI<0b01100011, 0b11111111, "shsub8">;
2165 def UHASX : AAI<0b01100111, 0b11110011, "uhasx">;
2166 def UHADD16 : AAI<0b01100111, 0b11110001, "uhadd16">;
2167 def UHADD8 : AAI<0b01100111, 0b11111001, "uhadd8">;
2168 def UHSAX : AAI<0b01100111, 0b11110101, "uhsax">;
2169 def UHSUB16 : AAI<0b01100111, 0b11110111, "uhsub16">;
2170 def UHSUB8 : AAI<0b01100111, 0b11111111, "uhsub8">;
2172 // Unsigned Sum of Absolute Differences [and Accumulate] -- for disassembly only
2174 def USAD8 : AI<(outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm),
2175 MulFrm /* for convenience */, NoItinerary, "usad8",
2176 "\t$Rd, $Rn, $Rm", []>,
2177 Requires<[IsARM, HasV6]> {
2181 let Inst{27-20} = 0b01111000;
2182 let Inst{15-12} = 0b1111;
2183 let Inst{7-4} = 0b0001;
2184 let Inst{19-16} = Rd;
2185 let Inst{11-8} = Rm;
2188 def USADA8 : AI<(outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm, GPR:$Ra),
2189 MulFrm /* for convenience */, NoItinerary, "usada8",
2190 "\t$Rd, $Rn, $Rm, $Ra", []>,
2191 Requires<[IsARM, HasV6]> {
2196 let Inst{27-20} = 0b01111000;
2197 let Inst{7-4} = 0b0001;
2198 let Inst{19-16} = Rd;
2199 let Inst{15-12} = Ra;
2200 let Inst{11-8} = Rm;
2204 // Signed/Unsigned saturate -- for disassembly only
2206 def SSAT : AI<(outs GPR:$Rd), (ins i32imm:$sat_imm, GPR:$a, shift_imm:$sh),
2207 SatFrm, NoItinerary, "ssat", "\t$Rd, $sat_imm, $a$sh",
2208 [/* For disassembly only; pattern left blank */]> {
2213 let Inst{27-21} = 0b0110101;
2214 let Inst{5-4} = 0b01;
2215 let Inst{20-16} = sat_imm;
2216 let Inst{15-12} = Rd;
2217 let Inst{11-7} = sh{7-3};
2218 let Inst{6} = sh{0};
2222 def SSAT16 : AI<(outs GPR:$Rd), (ins i32imm:$sat_imm, GPR:$Rn), SatFrm,
2223 NoItinerary, "ssat16", "\t$Rd, $sat_imm, $Rn",
2224 [/* For disassembly only; pattern left blank */]> {
2228 let Inst{27-20} = 0b01101010;
2229 let Inst{11-4} = 0b11110011;
2230 let Inst{15-12} = Rd;
2231 let Inst{19-16} = sat_imm;
2235 def USAT : AI<(outs GPR:$Rd), (ins i32imm:$sat_imm, GPR:$a, shift_imm:$sh),
2236 SatFrm, NoItinerary, "usat", "\t$Rd, $sat_imm, $a$sh",
2237 [/* For disassembly only; pattern left blank */]> {
2242 let Inst{27-21} = 0b0110111;
2243 let Inst{5-4} = 0b01;
2244 let Inst{15-12} = Rd;
2245 let Inst{11-7} = sh{7-3};
2246 let Inst{6} = sh{0};
2247 let Inst{20-16} = sat_imm;
2251 def USAT16 : AI<(outs GPR:$Rd), (ins i32imm:$sat_imm, GPR:$a), SatFrm,
2252 NoItinerary, "usat16", "\t$Rd, $sat_imm, $a",
2253 [/* For disassembly only; pattern left blank */]> {
2257 let Inst{27-20} = 0b01101110;
2258 let Inst{11-4} = 0b11110011;
2259 let Inst{15-12} = Rd;
2260 let Inst{19-16} = sat_imm;
2264 def : ARMV6Pat<(int_arm_ssat GPR:$a, imm:$pos), (SSAT imm:$pos, GPR:$a, 0)>;
2265 def : ARMV6Pat<(int_arm_usat GPR:$a, imm:$pos), (USAT imm:$pos, GPR:$a, 0)>;
2267 //===----------------------------------------------------------------------===//
2268 // Bitwise Instructions.
2271 defm AND : AsI1_bin_irs<0b0000, "and",
2272 IIC_iBITi, IIC_iBITr, IIC_iBITsr,
2273 BinOpFrag<(and node:$LHS, node:$RHS)>, 1>;
2274 defm ORR : AsI1_bin_irs<0b1100, "orr",
2275 IIC_iBITi, IIC_iBITr, IIC_iBITsr,
2276 BinOpFrag<(or node:$LHS, node:$RHS)>, 1>;
2277 defm EOR : AsI1_bin_irs<0b0001, "eor",
2278 IIC_iBITi, IIC_iBITr, IIC_iBITsr,
2279 BinOpFrag<(xor node:$LHS, node:$RHS)>, 1>;
2280 defm BIC : AsI1_bin_irs<0b1110, "bic",
2281 IIC_iBITi, IIC_iBITr, IIC_iBITsr,
2282 BinOpFrag<(and node:$LHS, (not node:$RHS))>>;
2284 def BFC : I<(outs GPR:$Rd), (ins GPR:$src, bf_inv_mask_imm:$imm),
2285 AddrMode1, Size4Bytes, IndexModeNone, DPFrm, IIC_iUNAsi,
2286 "bfc", "\t$Rd, $imm", "$src = $Rd",
2287 [(set GPR:$Rd, (and GPR:$src, bf_inv_mask_imm:$imm))]>,
2288 Requires<[IsARM, HasV6T2]> {
2291 let Inst{27-21} = 0b0111110;
2292 let Inst{6-0} = 0b0011111;
2293 let Inst{15-12} = Rd;
2294 let Inst{11-7} = imm{4-0}; // lsb
2295 let Inst{20-16} = imm{9-5}; // width
2298 // A8.6.18 BFI - Bitfield insert (Encoding A1)
2299 def BFI : I<(outs GPR:$Rd), (ins GPR:$src, GPR:$Rn, bf_inv_mask_imm:$imm),
2300 AddrMode1, Size4Bytes, IndexModeNone, DPFrm, IIC_iUNAsi,
2301 "bfi", "\t$Rd, $Rn, $imm", "$src = $Rd",
2302 [(set GPR:$Rd, (ARMbfi GPR:$src, GPR:$Rn,
2303 bf_inv_mask_imm:$imm))]>,
2304 Requires<[IsARM, HasV6T2]> {
2308 let Inst{27-21} = 0b0111110;
2309 let Inst{6-4} = 0b001; // Rn: Inst{3-0} != 15
2310 let Inst{15-12} = Rd;
2311 let Inst{11-7} = imm{4-0}; // lsb
2312 let Inst{20-16} = imm{9-5}; // width
2316 def MVNr : AsI1<0b1111, (outs GPR:$Rd), (ins GPR:$Rm), DPFrm, IIC_iMVNr,
2317 "mvn", "\t$Rd, $Rm",
2318 [(set GPR:$Rd, (not GPR:$Rm))]>, UnaryDP {
2322 let Inst{19-16} = 0b0000;
2323 let Inst{11-4} = 0b00000000;
2324 let Inst{15-12} = Rd;
2327 def MVNs : AsI1<0b1111, (outs GPR:$Rd), (ins so_reg:$shift), DPSoRegFrm,
2328 IIC_iMVNsr, "mvn", "\t$Rd, $shift",
2329 [(set GPR:$Rd, (not so_reg:$shift))]>, UnaryDP {
2334 let Inst{19-16} = 0b0000;
2335 let Inst{15-12} = Rd;
2336 let Inst{11-0} = shift;
2338 let isReMaterializable = 1, isAsCheapAsAMove = 1 in
2339 def MVNi : AsI1<0b1111, (outs GPR:$Rd), (ins so_imm:$imm), DPFrm,
2340 IIC_iMVNi, "mvn", "\t$Rd, $imm",
2341 [(set GPR:$Rd, so_imm_not:$imm)]>,UnaryDP {
2346 let Inst{19-16} = 0b0000;
2347 let Inst{15-12} = Rd;
2348 let Inst{11-0} = imm;
2351 def : ARMPat<(and GPR:$src, so_imm_not:$imm),
2352 (BICri GPR:$src, so_imm_not:$imm)>;
2354 //===----------------------------------------------------------------------===//
2355 // Multiply Instructions.
2357 class AsMul1I32<bits<7> opcod, dag oops, dag iops, InstrItinClass itin,
2358 string opc, string asm, list<dag> pattern>
2359 : AsMul1I<opcod, oops, iops, itin, opc, asm, pattern> {
2363 let Inst{19-16} = Rd;
2364 let Inst{11-8} = Rm;
2367 class AsMul1I64<bits<7> opcod, dag oops, dag iops, InstrItinClass itin,
2368 string opc, string asm, list<dag> pattern>
2369 : AsMul1I<opcod, oops, iops, itin, opc, asm, pattern> {
2374 let Inst{19-16} = RdHi;
2375 let Inst{15-12} = RdLo;
2376 let Inst{11-8} = Rm;
2380 let isCommutable = 1 in
2381 def MUL : AsMul1I32<0b0000000, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm),
2382 IIC_iMUL32, "mul", "\t$Rd, $Rn, $Rm",
2383 [(set GPR:$Rd, (mul GPR:$Rn, GPR:$Rm))]>;
2385 def MLA : AsMul1I32<0b0000001, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm, GPR:$Ra),
2386 IIC_iMAC32, "mla", "\t$Rd, $Rn, $Rm, $Ra",
2387 [(set GPR:$Rd, (add (mul GPR:$Rn, GPR:$Rm), GPR:$Ra))]> {
2389 let Inst{15-12} = Ra;
2392 def MLS : AMul1I<0b0000011, (outs GPR:$dst), (ins GPR:$a, GPR:$b, GPR:$c),
2393 IIC_iMAC32, "mls", "\t$dst, $a, $b, $c",
2394 [(set GPR:$dst, (sub GPR:$c, (mul GPR:$a, GPR:$b)))]>,
2395 Requires<[IsARM, HasV6T2]> {
2399 let Inst{19-16} = Rd;
2400 let Inst{11-8} = Rm;
2404 // Extra precision multiplies with low / high results
2406 let neverHasSideEffects = 1 in {
2407 let isCommutable = 1 in {
2408 def SMULL : AsMul1I64<0b0000110, (outs GPR:$RdLo, GPR:$RdHi),
2409 (ins GPR:$Rn, GPR:$Rm), IIC_iMUL64,
2410 "smull", "\t$RdLo, $RdHi, $Rn, $Rm", []>;
2412 def UMULL : AsMul1I64<0b0000100, (outs GPR:$RdLo, GPR:$RdHi),
2413 (ins GPR:$Rn, GPR:$Rm), IIC_iMUL64,
2414 "umull", "\t$RdLo, $RdHi, $Rn, $Rm", []>;
2417 // Multiply + accumulate
2418 def SMLAL : AsMul1I64<0b0000111, (outs GPR:$RdLo, GPR:$RdHi),
2419 (ins GPR:$Rn, GPR:$Rm), IIC_iMAC64,
2420 "smlal", "\t$RdLo, $RdHi, $Rn, $Rm", []>;
2422 def UMLAL : AsMul1I64<0b0000101, (outs GPR:$RdLo, GPR:$RdHi),
2423 (ins GPR:$Rn, GPR:$Rm), IIC_iMAC64,
2424 "umlal", "\t$RdLo, $RdHi, $Rn, $Rm", []>;
2426 def UMAAL : AMul1I <0b0000010, (outs GPR:$RdLo, GPR:$RdHi),
2427 (ins GPR:$Rn, GPR:$Rm), IIC_iMAC64,
2428 "umaal", "\t$RdLo, $RdHi, $Rn, $Rm", []>,
2429 Requires<[IsARM, HasV6]> {
2434 let Inst{19-16} = RdLo;
2435 let Inst{15-12} = RdHi;
2436 let Inst{11-8} = Rm;
2439 } // neverHasSideEffects
2441 // Most significant word multiply
2442 def SMMUL : AMul2I <0b0111010, 0b0001, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm),
2443 IIC_iMUL32, "smmul", "\t$Rd, $Rn, $Rm",
2444 [(set GPR:$Rd, (mulhs GPR:$Rn, GPR:$Rm))]>,
2445 Requires<[IsARM, HasV6]> {
2446 let Inst{15-12} = 0b1111;
2449 def SMMULR : AMul2I <0b0111010, 0b0011, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm),
2450 IIC_iMUL32, "smmulr", "\t$Rd, $Rn, $Rm",
2451 [/* For disassembly only; pattern left blank */]>,
2452 Requires<[IsARM, HasV6]> {
2453 let Inst{15-12} = 0b1111;
2456 def SMMLA : AMul2Ia <0b0111010, 0b0001, (outs GPR:$Rd),
2457 (ins GPR:$Rn, GPR:$Rm, GPR:$Ra),
2458 IIC_iMAC32, "smmla", "\t$Rd, $Rn, $Rm, $Ra",
2459 [(set GPR:$Rd, (add (mulhs GPR:$Rn, GPR:$Rm), GPR:$Ra))]>,
2460 Requires<[IsARM, HasV6]>;
2462 def SMMLAR : AMul2Ia <0b0111010, 0b0011, (outs GPR:$Rd),
2463 (ins GPR:$Rn, GPR:$Rm, GPR:$Ra),
2464 IIC_iMAC32, "smmlar", "\t$Rd, $Rn, $Rm, $Ra",
2465 [/* For disassembly only; pattern left blank */]>,
2466 Requires<[IsARM, HasV6]>;
2468 def SMMLS : AMul2Ia <0b0111010, 0b1101, (outs GPR:$Rd),
2469 (ins GPR:$Rn, GPR:$Rm, GPR:$Ra),
2470 IIC_iMAC32, "smmls", "\t$Rd, $Rn, $Rm, $Ra",
2471 [(set GPR:$Rd, (sub GPR:$Ra, (mulhs GPR:$Rn, GPR:$Rm)))]>,
2472 Requires<[IsARM, HasV6]>;
2474 def SMMLSR : AMul2Ia <0b0111010, 0b1111, (outs GPR:$Rd),
2475 (ins GPR:$Rn, GPR:$Rm, GPR:$Ra),
2476 IIC_iMAC32, "smmlsr", "\t$Rd, $Rn, $Rm, $Ra",
2477 [/* For disassembly only; pattern left blank */]>,
2478 Requires<[IsARM, HasV6]>;
2480 multiclass AI_smul<string opc, PatFrag opnode> {
2481 def BB : AMulxyI<0b0001011, 0b00, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm),
2482 IIC_iMUL16, !strconcat(opc, "bb"), "\t$Rd, $Rn, $Rm",
2483 [(set GPR:$Rd, (opnode (sext_inreg GPR:$Rn, i16),
2484 (sext_inreg GPR:$Rm, i16)))]>,
2485 Requires<[IsARM, HasV5TE]>;
2487 def BT : AMulxyI<0b0001011, 0b10, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm),
2488 IIC_iMUL16, !strconcat(opc, "bt"), "\t$Rd, $Rn, $Rm",
2489 [(set GPR:$Rd, (opnode (sext_inreg GPR:$Rn, i16),
2490 (sra GPR:$Rm, (i32 16))))]>,
2491 Requires<[IsARM, HasV5TE]>;
2493 def TB : AMulxyI<0b0001011, 0b01, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm),
2494 IIC_iMUL16, !strconcat(opc, "tb"), "\t$Rd, $Rn, $Rm",
2495 [(set GPR:$Rd, (opnode (sra GPR:$Rn, (i32 16)),
2496 (sext_inreg GPR:$Rm, i16)))]>,
2497 Requires<[IsARM, HasV5TE]>;
2499 def TT : AMulxyI<0b0001011, 0b11, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm),
2500 IIC_iMUL16, !strconcat(opc, "tt"), "\t$Rd, $Rn, $Rm",
2501 [(set GPR:$Rd, (opnode (sra GPR:$Rn, (i32 16)),
2502 (sra GPR:$Rm, (i32 16))))]>,
2503 Requires<[IsARM, HasV5TE]>;
2505 def WB : AMulxyI<0b0001001, 0b01, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm),
2506 IIC_iMUL16, !strconcat(opc, "wb"), "\t$Rd, $Rn, $Rm",
2507 [(set GPR:$Rd, (sra (opnode GPR:$Rn,
2508 (sext_inreg GPR:$Rm, i16)), (i32 16)))]>,
2509 Requires<[IsARM, HasV5TE]>;
2511 def WT : AMulxyI<0b0001001, 0b11, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm),
2512 IIC_iMUL16, !strconcat(opc, "wt"), "\t$Rd, $Rn, $Rm",
2513 [(set GPR:$Rd, (sra (opnode GPR:$Rn,
2514 (sra GPR:$Rm, (i32 16))), (i32 16)))]>,
2515 Requires<[IsARM, HasV5TE]>;
2519 multiclass AI_smla<string opc, PatFrag opnode> {
2520 def BB : AMulxyI<0b0001000, 0b00, (outs GPR:$Rd),
2521 (ins GPR:$Rn, GPR:$Rm, GPR:$Ra),
2522 IIC_iMAC16, !strconcat(opc, "bb"), "\t$Rd, $Rn, $Rm, $Ra",
2523 [(set GPR:$Rd, (add GPR:$Ra,
2524 (opnode (sext_inreg GPR:$Rn, i16),
2525 (sext_inreg GPR:$Rm, i16))))]>,
2526 Requires<[IsARM, HasV5TE]>;
2528 def BT : AMulxyI<0b0001000, 0b10, (outs GPR:$Rd),
2529 (ins GPR:$Rn, GPR:$Rm, GPR:$Ra),
2530 IIC_iMAC16, !strconcat(opc, "bt"), "\t$Rd, $Rn, $Rm, $Ra",
2531 [(set GPR:$Rd, (add GPR:$Ra, (opnode (sext_inreg GPR:$Rn, i16),
2532 (sra GPR:$Rm, (i32 16)))))]>,
2533 Requires<[IsARM, HasV5TE]>;
2535 def TB : AMulxyI<0b0001000, 0b01, (outs GPR:$Rd),
2536 (ins GPR:$Rn, GPR:$Rm, GPR:$Ra),
2537 IIC_iMAC16, !strconcat(opc, "tb"), "\t$Rd, $Rn, $Rm, $Ra",
2538 [(set GPR:$Rd, (add GPR:$Ra, (opnode (sra GPR:$Rn, (i32 16)),
2539 (sext_inreg GPR:$Rm, i16))))]>,
2540 Requires<[IsARM, HasV5TE]>;
2542 def TT : AMulxyI<0b0001000, 0b11, (outs GPR:$Rd),
2543 (ins GPR:$Rn, GPR:$Rm, GPR:$Ra),
2544 IIC_iMAC16, !strconcat(opc, "tt"), "\t$Rd, $Rn, $Rm, $Ra",
2545 [(set GPR:$Rd, (add GPR:$Ra, (opnode (sra GPR:$Rn, (i32 16)),
2546 (sra GPR:$Rm, (i32 16)))))]>,
2547 Requires<[IsARM, HasV5TE]>;
2549 def WB : AMulxyI<0b0001001, 0b00, (outs GPR:$Rd),
2550 (ins GPR:$Rn, GPR:$Rm, GPR:$Ra),
2551 IIC_iMAC16, !strconcat(opc, "wb"), "\t$Rd, $Rn, $Rm, $Ra",
2552 [(set GPR:$Rd, (add GPR:$Ra, (sra (opnode GPR:$Rn,
2553 (sext_inreg GPR:$Rm, i16)), (i32 16))))]>,
2554 Requires<[IsARM, HasV5TE]>;
2556 def WT : AMulxyI<0b0001001, 0b10, (outs GPR:$Rd),
2557 (ins GPR:$Rn, GPR:$Rm, GPR:$Ra),
2558 IIC_iMAC16, !strconcat(opc, "wt"), "\t$Rd, $Rn, $Rm, $Ra",
2559 [(set GPR:$Rd, (add GPR:$Ra, (sra (opnode GPR:$Rn,
2560 (sra GPR:$Rm, (i32 16))), (i32 16))))]>,
2561 Requires<[IsARM, HasV5TE]>;
2564 defm SMUL : AI_smul<"smul", BinOpFrag<(mul node:$LHS, node:$RHS)>>;
2565 defm SMLA : AI_smla<"smla", BinOpFrag<(mul node:$LHS, node:$RHS)>>;
2567 // Halfword multiply accumulate long: SMLAL<x><y> -- for disassembly only
2568 def SMLALBB : AMulxyI64<0b0001010, 0b00, (outs GPR:$RdLo, GPR:$RdHi),
2569 (ins GPR:$Rn, GPR:$Rm),
2570 IIC_iMAC64, "smlalbb", "\t$RdLo, $RdHi, $Rn, $Rm",
2571 [/* For disassembly only; pattern left blank */]>,
2572 Requires<[IsARM, HasV5TE]>;
2574 def SMLALBT : AMulxyI64<0b0001010, 0b10, (outs GPR:$RdLo, GPR:$RdHi),
2575 (ins GPR:$Rn, GPR:$Rm),
2576 IIC_iMAC64, "smlalbt", "\t$RdLo, $RdHi, $Rn, $Rm",
2577 [/* For disassembly only; pattern left blank */]>,
2578 Requires<[IsARM, HasV5TE]>;
2580 def SMLALTB : AMulxyI64<0b0001010, 0b01, (outs GPR:$RdLo, GPR:$RdHi),
2581 (ins GPR:$Rn, GPR:$Rm),
2582 IIC_iMAC64, "smlaltb", "\t$RdLo, $RdHi, $Rn, $Rm",
2583 [/* For disassembly only; pattern left blank */]>,
2584 Requires<[IsARM, HasV5TE]>;
2586 def SMLALTT : AMulxyI64<0b0001010, 0b11, (outs GPR:$RdLo, GPR:$RdHi),
2587 (ins GPR:$Rn, GPR:$Rm),
2588 IIC_iMAC64, "smlaltt", "\t$RdLo, $RdHi, $Rn, $Rm",
2589 [/* For disassembly only; pattern left blank */]>,
2590 Requires<[IsARM, HasV5TE]>;
2592 // Helper class for AI_smld -- for disassembly only
2593 class AMulDualIbase<bit long, bit sub, bit swap, dag oops, dag iops,
2594 InstrItinClass itin, string opc, string asm>
2595 : AI<oops, iops, MulFrm, itin, opc, asm, []>, Requires<[IsARM, HasV6]> {
2602 let Inst{21-20} = 0b00;
2603 let Inst{22} = long;
2604 let Inst{27-23} = 0b01110;
2605 let Inst{11-8} = Rm;
2608 class AMulDualI<bit long, bit sub, bit swap, dag oops, dag iops,
2609 InstrItinClass itin, string opc, string asm>
2610 : AMulDualIbase<long, sub, swap, oops, iops, itin, opc, asm> {
2612 let Inst{15-12} = 0b1111;
2613 let Inst{19-16} = Rd;
2615 class AMulDualIa<bit long, bit sub, bit swap, dag oops, dag iops,
2616 InstrItinClass itin, string opc, string asm>
2617 : AMulDualIbase<long, sub, swap, oops, iops, itin, opc, asm> {
2619 let Inst{15-12} = Ra;
2621 class AMulDualI64<bit long, bit sub, bit swap, dag oops, dag iops,
2622 InstrItinClass itin, string opc, string asm>
2623 : AMulDualIbase<long, sub, swap, oops, iops, itin, opc, asm> {
2626 let Inst{19-16} = RdHi;
2627 let Inst{15-12} = RdLo;
2630 multiclass AI_smld<bit sub, string opc> {
2632 def D : AMulDualIa<0, sub, 0, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm, GPR:$Ra),
2633 NoItinerary, !strconcat(opc, "d"), "\t$Rd, $Rn, $Rm, $Ra">;
2635 def DX: AMulDualIa<0, sub, 1, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm, GPR:$Ra),
2636 NoItinerary, !strconcat(opc, "dx"), "\t$Rd, $Rn, $Rm, $Ra">;
2638 def LD: AMulDualI64<1, sub, 0, (outs GPR:$RdLo,GPR:$RdHi),
2639 (ins GPR:$Rn, GPR:$Rm), NoItinerary,
2640 !strconcat(opc, "ld"), "\t$RdLo, $RdHi, $Rn, $Rm">;
2642 def LDX : AMulDualI64<1, sub, 1, (outs GPR:$RdLo,GPR:$RdHi),
2643 (ins GPR:$Rn, GPR:$Rm), NoItinerary,
2644 !strconcat(opc, "ldx"),"\t$RdLo, $RdHi, $Rn, $Rm">;
2648 defm SMLA : AI_smld<0, "smla">;
2649 defm SMLS : AI_smld<1, "smls">;
2651 multiclass AI_sdml<bit sub, string opc> {
2653 def D : AMulDualI<0, sub, 0, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm),
2654 NoItinerary, !strconcat(opc, "d"), "\t$Rd, $Rn, $Rm">;
2655 def DX : AMulDualI<0, sub, 1, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm),
2656 NoItinerary, !strconcat(opc, "dx"), "\t$Rd, $Rn, $Rm">;
2659 defm SMUA : AI_sdml<0, "smua">;
2660 defm SMUS : AI_sdml<1, "smus">;
2662 //===----------------------------------------------------------------------===//
2663 // Misc. Arithmetic Instructions.
2666 def CLZ : AMiscA1I<0b000010110, 0b0001, (outs GPR:$Rd), (ins GPR:$Rm),
2667 IIC_iUNAr, "clz", "\t$Rd, $Rm",
2668 [(set GPR:$Rd, (ctlz GPR:$Rm))]>, Requires<[IsARM, HasV5T]>;
2670 def RBIT : AMiscA1I<0b01101111, 0b0011, (outs GPR:$Rd), (ins GPR:$Rm),
2671 IIC_iUNAr, "rbit", "\t$Rd, $Rm",
2672 [(set GPR:$Rd, (ARMrbit GPR:$Rm))]>,
2673 Requires<[IsARM, HasV6T2]>;
2675 def REV : AMiscA1I<0b01101011, 0b0011, (outs GPR:$Rd), (ins GPR:$Rm),
2676 IIC_iUNAr, "rev", "\t$Rd, $Rm",
2677 [(set GPR:$Rd, (bswap GPR:$Rm))]>, Requires<[IsARM, HasV6]>;
2679 def REV16 : AMiscA1I<0b01101011, 0b1011, (outs GPR:$Rd), (ins GPR:$Rm),
2680 IIC_iUNAr, "rev16", "\t$Rd, $Rm",
2682 (or (and (srl GPR:$Rm, (i32 8)), 0xFF),
2683 (or (and (shl GPR:$Rm, (i32 8)), 0xFF00),
2684 (or (and (srl GPR:$Rm, (i32 8)), 0xFF0000),
2685 (and (shl GPR:$Rm, (i32 8)), 0xFF000000)))))]>,
2686 Requires<[IsARM, HasV6]>;
2688 def REVSH : AMiscA1I<0b01101111, 0b1011, (outs GPR:$Rd), (ins GPR:$Rm),
2689 IIC_iUNAr, "revsh", "\t$Rd, $Rm",
2692 (or (srl (and GPR:$Rm, 0xFF00), (i32 8)),
2693 (shl GPR:$Rm, (i32 8))), i16))]>,
2694 Requires<[IsARM, HasV6]>;
2696 def lsl_shift_imm : SDNodeXForm<imm, [{
2697 unsigned Sh = ARM_AM::getSORegOpc(ARM_AM::lsl, N->getZExtValue());
2698 return CurDAG->getTargetConstant(Sh, MVT::i32);
2701 def lsl_amt : PatLeaf<(i32 imm), [{
2702 return (N->getZExtValue() < 32);
2705 def PKHBT : APKHI<0b01101000, 0, (outs GPR:$Rd),
2706 (ins GPR:$Rn, GPR:$Rm, shift_imm:$sh),
2707 IIC_iALUsi, "pkhbt", "\t$Rd, $Rn, $Rm$sh",
2708 [(set GPR:$Rd, (or (and GPR:$Rn, 0xFFFF),
2709 (and (shl GPR:$Rm, lsl_amt:$sh),
2711 Requires<[IsARM, HasV6]>;
2713 // Alternate cases for PKHBT where identities eliminate some nodes.
2714 def : ARMV6Pat<(or (and GPR:$Rn, 0xFFFF), (and GPR:$Rm, 0xFFFF0000)),
2715 (PKHBT GPR:$Rn, GPR:$Rm, 0)>;
2716 def : ARMV6Pat<(or (and GPR:$Rn, 0xFFFF), (shl GPR:$Rm, imm16_31:$sh)),
2717 (PKHBT GPR:$Rn, GPR:$Rm, (lsl_shift_imm imm16_31:$sh))>;
2719 def asr_shift_imm : SDNodeXForm<imm, [{
2720 unsigned Sh = ARM_AM::getSORegOpc(ARM_AM::asr, N->getZExtValue());
2721 return CurDAG->getTargetConstant(Sh, MVT::i32);
2724 def asr_amt : PatLeaf<(i32 imm), [{
2725 return (N->getZExtValue() <= 32);
2728 // Note: Shifts of 1-15 bits will be transformed to srl instead of sra and
2729 // will match the pattern below.
2730 def PKHTB : APKHI<0b01101000, 1, (outs GPR:$Rd),
2731 (ins GPR:$Rn, GPR:$Rm, shift_imm:$sh),
2732 IIC_iBITsi, "pkhtb", "\t$Rd, $Rn, $Rm$sh",
2733 [(set GPR:$Rd, (or (and GPR:$Rn, 0xFFFF0000),
2734 (and (sra GPR:$Rm, asr_amt:$sh),
2736 Requires<[IsARM, HasV6]>;
2738 // Alternate cases for PKHTB where identities eliminate some nodes. Note that
2739 // a shift amount of 0 is *not legal* here, it is PKHBT instead.
2740 def : ARMV6Pat<(or (and GPR:$src1, 0xFFFF0000), (srl GPR:$src2, imm16_31:$sh)),
2741 (PKHTB GPR:$src1, GPR:$src2, (asr_shift_imm imm16_31:$sh))>;
2742 def : ARMV6Pat<(or (and GPR:$src1, 0xFFFF0000),
2743 (and (srl GPR:$src2, imm1_15:$sh), 0xFFFF)),
2744 (PKHTB GPR:$src1, GPR:$src2, (asr_shift_imm imm1_15:$sh))>;
2746 //===----------------------------------------------------------------------===//
2747 // Comparison Instructions...
2750 defm CMP : AI1_cmp_irs<0b1010, "cmp",
2751 IIC_iCMPi, IIC_iCMPr, IIC_iCMPsr,
2752 BinOpFrag<(ARMcmp node:$LHS, node:$RHS)>>;
2754 // FIXME: We have to be careful when using the CMN instruction and comparison
2755 // with 0. One would expect these two pieces of code should give identical
2771 // However, the CMN gives the *opposite* result when r1 is 0. This is because
2772 // the carry flag is set in the CMP case but not in the CMN case. In short, the
2773 // CMP instruction doesn't perform a truncate of the (logical) NOT of 0 plus the
2774 // value of r0 and the carry bit (because the "carry bit" parameter to
2775 // AddWithCarry is defined as 1 in this case, the carry flag will always be set
2776 // when r0 >= 0). The CMN instruction doesn't perform a NOT of 0 so there is
2777 // never a "carry" when this AddWithCarry is performed (because the "carry bit"
2778 // parameter to AddWithCarry is defined as 0).
2780 // When x is 0 and unsigned:
2784 // ~x + 1 = 0x1 0000 0000
2785 // (-x = 0) != (0x1 0000 0000 = ~x + 1)
2787 // Therefore, we should disable CMN when comparing against zero, until we can
2788 // limit when the CMN instruction is used (when we know that the RHS is not 0 or
2789 // when it's a comparison which doesn't look at the 'carry' flag).
2791 // (See the ARM docs for the "AddWithCarry" pseudo-code.)
2793 // This is related to <rdar://problem/7569620>.
2795 //defm CMN : AI1_cmp_irs<0b1011, "cmn",
2796 // BinOpFrag<(ARMcmp node:$LHS,(ineg node:$RHS))>>;
2798 // Note that TST/TEQ don't set all the same flags that CMP does!
2799 defm TST : AI1_cmp_irs<0b1000, "tst",
2800 IIC_iTSTi, IIC_iTSTr, IIC_iTSTsr,
2801 BinOpFrag<(ARMcmpZ (and node:$LHS, node:$RHS), 0)>, 1>;
2802 defm TEQ : AI1_cmp_irs<0b1001, "teq",
2803 IIC_iTSTi, IIC_iTSTr, IIC_iTSTsr,
2804 BinOpFrag<(ARMcmpZ (xor node:$LHS, node:$RHS), 0)>, 1>;
2806 defm CMPz : AI1_cmp_irs<0b1010, "cmp",
2807 IIC_iCMPi, IIC_iCMPr, IIC_iCMPsr,
2808 BinOpFrag<(ARMcmpZ node:$LHS, node:$RHS)>>;
2809 defm CMNz : AI1_cmp_irs<0b1011, "cmn",
2810 IIC_iCMPi, IIC_iCMPr, IIC_iCMPsr,
2811 BinOpFrag<(ARMcmpZ node:$LHS,(ineg node:$RHS))>>;
2813 //def : ARMPat<(ARMcmp GPR:$src, so_imm_neg:$imm),
2814 // (CMNri GPR:$src, so_imm_neg:$imm)>;
2816 def : ARMPat<(ARMcmpZ GPR:$src, so_imm_neg:$imm),
2817 (CMNzri GPR:$src, so_imm_neg:$imm)>;
2819 // Pseudo i64 compares for some floating point compares.
2820 let usesCustomInserter = 1, isBranch = 1, isTerminator = 1,
2822 def BCCi64 : PseudoInst<(outs),
2823 (ins i32imm:$cc, GPR:$lhs1, GPR:$lhs2, GPR:$rhs1, GPR:$rhs2, brtarget:$dst),
2825 [(ARMBcci64 imm:$cc, GPR:$lhs1, GPR:$lhs2, GPR:$rhs1, GPR:$rhs2, bb:$dst)]>;
2827 def BCCZi64 : PseudoInst<(outs),
2828 (ins i32imm:$cc, GPR:$lhs1, GPR:$lhs2, brtarget:$dst), IIC_Br, "",
2829 [(ARMBcci64 imm:$cc, GPR:$lhs1, GPR:$lhs2, 0, 0, bb:$dst)]>;
2830 } // usesCustomInserter
2833 // Conditional moves
2834 // FIXME: should be able to write a pattern for ARMcmov, but can't use
2835 // a two-value operand where a dag node expects two operands. :(
2836 // FIXME: These should all be pseudo-instructions that get expanded to
2837 // the normal MOV instructions. That would fix the dependency on
2838 // special casing them in tblgen.
2839 let neverHasSideEffects = 1 in {
2840 def MOVCCr : AI1<0b1101, (outs GPR:$Rd), (ins GPR:$false, GPR:$Rm), DPFrm,
2841 IIC_iCMOVr, "mov", "\t$Rd, $Rm",
2842 [/*(set GPR:$Rd, (ARMcmov GPR:$false, GPR:$Rm, imm:$cc, CCR:$ccr))*/]>,
2843 RegConstraint<"$false = $Rd">, UnaryDP {
2848 let Inst{15-12} = Rd;
2849 let Inst{11-4} = 0b00000000;
2853 def MOVCCs : AI1<0b1101, (outs GPR:$Rd),
2854 (ins GPR:$false, so_reg:$shift), DPSoRegFrm, IIC_iCMOVsr,
2855 "mov", "\t$Rd, $shift",
2856 [/*(set GPR:$Rd, (ARMcmov GPR:$false, so_reg:$shift, imm:$cc, CCR:$ccr))*/]>,
2857 RegConstraint<"$false = $Rd">, UnaryDP {
2863 let Inst{19-16} = Rn;
2864 let Inst{15-12} = Rd;
2865 let Inst{11-0} = shift;
2868 def MOVCCi16 : AI1<0b1000, (outs GPR:$Rd), (ins GPR:$false, i32imm:$imm),
2870 "movw", "\t$Rd, $imm",
2872 RegConstraint<"$false = $Rd">, Requires<[IsARM, HasV6T2]>,
2878 let Inst{19-16} = imm{15-12};
2879 let Inst{15-12} = Rd;
2880 let Inst{11-0} = imm{11-0};
2883 def MOVCCi : AI1<0b1101, (outs GPR:$Rd),
2884 (ins GPR:$false, so_imm:$imm), DPFrm, IIC_iCMOVi,
2885 "mov", "\t$Rd, $imm",
2886 [/*(set GPR:$Rd, (ARMcmov GPR:$false, so_imm:$imm, imm:$cc, CCR:$ccr))*/]>,
2887 RegConstraint<"$false = $Rd">, UnaryDP {
2892 let Inst{19-16} = 0b0000;
2893 let Inst{15-12} = Rd;
2894 let Inst{11-0} = imm;
2896 } // neverHasSideEffects
2898 //===----------------------------------------------------------------------===//
2899 // Atomic operations intrinsics
2902 def memb_opt : Operand<i32> {
2903 let PrintMethod = "printMemBOption";
2906 // memory barriers protect the atomic sequences
2907 let hasSideEffects = 1 in {
2908 def DMB : AInoP<(outs), (ins memb_opt:$opt), MiscFrm, NoItinerary,
2909 "dmb", "\t$opt", [(ARMMemBarrier (i32 imm:$opt))]>,
2910 Requires<[IsARM, HasDB]> {
2912 let Inst{31-4} = 0xf57ff05;
2913 let Inst{3-0} = opt;
2916 def DMB_MCR : AInoP<(outs), (ins GPR:$zero), MiscFrm, NoItinerary,
2917 "mcr", "\tp15, 0, $zero, c7, c10, 5",
2918 [(ARMMemBarrierMCR GPR:$zero)]>,
2919 Requires<[IsARM, HasV6]> {
2920 // FIXME: add encoding
2924 def DSB : AInoP<(outs), (ins memb_opt:$opt), MiscFrm, NoItinerary,
2926 [/* For disassembly only; pattern left blank */]>,
2927 Requires<[IsARM, HasDB]> {
2929 let Inst{31-4} = 0xf57ff04;
2930 let Inst{3-0} = opt;
2933 // ISB has only full system option -- for disassembly only
2934 def ISB : AInoP<(outs), (ins), MiscFrm, NoItinerary, "isb", "", []>,
2935 Requires<[IsARM, HasDB]> {
2936 let Inst{31-4} = 0xf57ff06;
2937 let Inst{3-0} = 0b1111;
2940 let usesCustomInserter = 1 in {
2941 let Uses = [CPSR] in {
2942 def ATOMIC_LOAD_ADD_I8 : PseudoInst<
2943 (outs GPR:$dst), (ins GPR:$ptr, GPR:$incr), NoItinerary, "",
2944 [(set GPR:$dst, (atomic_load_add_8 GPR:$ptr, GPR:$incr))]>;
2945 def ATOMIC_LOAD_SUB_I8 : PseudoInst<
2946 (outs GPR:$dst), (ins GPR:$ptr, GPR:$incr), NoItinerary, "",
2947 [(set GPR:$dst, (atomic_load_sub_8 GPR:$ptr, GPR:$incr))]>;
2948 def ATOMIC_LOAD_AND_I8 : PseudoInst<
2949 (outs GPR:$dst), (ins GPR:$ptr, GPR:$incr), NoItinerary, "",
2950 [(set GPR:$dst, (atomic_load_and_8 GPR:$ptr, GPR:$incr))]>;
2951 def ATOMIC_LOAD_OR_I8 : PseudoInst<
2952 (outs GPR:$dst), (ins GPR:$ptr, GPR:$incr), NoItinerary, "",
2953 [(set GPR:$dst, (atomic_load_or_8 GPR:$ptr, GPR:$incr))]>;
2954 def ATOMIC_LOAD_XOR_I8 : PseudoInst<
2955 (outs GPR:$dst), (ins GPR:$ptr, GPR:$incr), NoItinerary, "",
2956 [(set GPR:$dst, (atomic_load_xor_8 GPR:$ptr, GPR:$incr))]>;
2957 def ATOMIC_LOAD_NAND_I8 : PseudoInst<
2958 (outs GPR:$dst), (ins GPR:$ptr, GPR:$incr), NoItinerary, "",
2959 [(set GPR:$dst, (atomic_load_nand_8 GPR:$ptr, GPR:$incr))]>;
2960 def ATOMIC_LOAD_ADD_I16 : PseudoInst<
2961 (outs GPR:$dst), (ins GPR:$ptr, GPR:$incr), NoItinerary, "",
2962 [(set GPR:$dst, (atomic_load_add_16 GPR:$ptr, GPR:$incr))]>;
2963 def ATOMIC_LOAD_SUB_I16 : PseudoInst<
2964 (outs GPR:$dst), (ins GPR:$ptr, GPR:$incr), NoItinerary, "",
2965 [(set GPR:$dst, (atomic_load_sub_16 GPR:$ptr, GPR:$incr))]>;
2966 def ATOMIC_LOAD_AND_I16 : PseudoInst<
2967 (outs GPR:$dst), (ins GPR:$ptr, GPR:$incr), NoItinerary, "",
2968 [(set GPR:$dst, (atomic_load_and_16 GPR:$ptr, GPR:$incr))]>;
2969 def ATOMIC_LOAD_OR_I16 : PseudoInst<
2970 (outs GPR:$dst), (ins GPR:$ptr, GPR:$incr), NoItinerary, "",
2971 [(set GPR:$dst, (atomic_load_or_16 GPR:$ptr, GPR:$incr))]>;
2972 def ATOMIC_LOAD_XOR_I16 : PseudoInst<
2973 (outs GPR:$dst), (ins GPR:$ptr, GPR:$incr), NoItinerary, "",
2974 [(set GPR:$dst, (atomic_load_xor_16 GPR:$ptr, GPR:$incr))]>;
2975 def ATOMIC_LOAD_NAND_I16 : PseudoInst<
2976 (outs GPR:$dst), (ins GPR:$ptr, GPR:$incr), NoItinerary, "",
2977 [(set GPR:$dst, (atomic_load_nand_16 GPR:$ptr, GPR:$incr))]>;
2978 def ATOMIC_LOAD_ADD_I32 : PseudoInst<
2979 (outs GPR:$dst), (ins GPR:$ptr, GPR:$incr), NoItinerary, "",
2980 [(set GPR:$dst, (atomic_load_add_32 GPR:$ptr, GPR:$incr))]>;
2981 def ATOMIC_LOAD_SUB_I32 : PseudoInst<
2982 (outs GPR:$dst), (ins GPR:$ptr, GPR:$incr), NoItinerary, "",
2983 [(set GPR:$dst, (atomic_load_sub_32 GPR:$ptr, GPR:$incr))]>;
2984 def ATOMIC_LOAD_AND_I32 : PseudoInst<
2985 (outs GPR:$dst), (ins GPR:$ptr, GPR:$incr), NoItinerary, "",
2986 [(set GPR:$dst, (atomic_load_and_32 GPR:$ptr, GPR:$incr))]>;
2987 def ATOMIC_LOAD_OR_I32 : PseudoInst<
2988 (outs GPR:$dst), (ins GPR:$ptr, GPR:$incr), NoItinerary, "",
2989 [(set GPR:$dst, (atomic_load_or_32 GPR:$ptr, GPR:$incr))]>;
2990 def ATOMIC_LOAD_XOR_I32 : PseudoInst<
2991 (outs GPR:$dst), (ins GPR:$ptr, GPR:$incr), NoItinerary, "",
2992 [(set GPR:$dst, (atomic_load_xor_32 GPR:$ptr, GPR:$incr))]>;
2993 def ATOMIC_LOAD_NAND_I32 : PseudoInst<
2994 (outs GPR:$dst), (ins GPR:$ptr, GPR:$incr), NoItinerary, "",
2995 [(set GPR:$dst, (atomic_load_nand_32 GPR:$ptr, GPR:$incr))]>;
2997 def ATOMIC_SWAP_I8 : PseudoInst<
2998 (outs GPR:$dst), (ins GPR:$ptr, GPR:$new), NoItinerary, "",
2999 [(set GPR:$dst, (atomic_swap_8 GPR:$ptr, GPR:$new))]>;
3000 def ATOMIC_SWAP_I16 : PseudoInst<
3001 (outs GPR:$dst), (ins GPR:$ptr, GPR:$new), NoItinerary, "",
3002 [(set GPR:$dst, (atomic_swap_16 GPR:$ptr, GPR:$new))]>;
3003 def ATOMIC_SWAP_I32 : PseudoInst<
3004 (outs GPR:$dst), (ins GPR:$ptr, GPR:$new), NoItinerary, "",
3005 [(set GPR:$dst, (atomic_swap_32 GPR:$ptr, GPR:$new))]>;
3007 def ATOMIC_CMP_SWAP_I8 : PseudoInst<
3008 (outs GPR:$dst), (ins GPR:$ptr, GPR:$old, GPR:$new), NoItinerary, "",
3009 [(set GPR:$dst, (atomic_cmp_swap_8 GPR:$ptr, GPR:$old, GPR:$new))]>;
3010 def ATOMIC_CMP_SWAP_I16 : PseudoInst<
3011 (outs GPR:$dst), (ins GPR:$ptr, GPR:$old, GPR:$new), NoItinerary, "",
3012 [(set GPR:$dst, (atomic_cmp_swap_16 GPR:$ptr, GPR:$old, GPR:$new))]>;
3013 def ATOMIC_CMP_SWAP_I32 : PseudoInst<
3014 (outs GPR:$dst), (ins GPR:$ptr, GPR:$old, GPR:$new), NoItinerary, "",
3015 [(set GPR:$dst, (atomic_cmp_swap_32 GPR:$ptr, GPR:$old, GPR:$new))]>;
3019 let mayLoad = 1 in {
3020 def LDREXB : AIldrex<0b10, (outs GPR:$Rt), (ins GPR:$Rn), NoItinerary,
3021 "ldrexb", "\t$Rt, [$Rn]",
3023 def LDREXH : AIldrex<0b11, (outs GPR:$Rt), (ins GPR:$Rn), NoItinerary,
3024 "ldrexh", "\t$Rt, [$Rn]",
3026 def LDREX : AIldrex<0b00, (outs GPR:$Rt), (ins GPR:$Rn), NoItinerary,
3027 "ldrex", "\t$Rt, [$Rn]",
3029 def LDREXD : AIldrex<0b01, (outs GPR:$Rt, GPR:$Rt2), (ins GPR:$Rn),
3031 "ldrexd", "\t$Rt, $Rt2, [$Rn]",
3035 let mayStore = 1, Constraints = "@earlyclobber $Rd" in {
3036 def STREXB : AIstrex<0b10, (outs GPR:$Rd), (ins GPR:$src, GPR:$Rn),
3038 "strexb", "\t$Rd, $src, [$Rn]",
3040 def STREXH : AIstrex<0b11, (outs GPR:$Rd), (ins GPR:$Rt, GPR:$Rn),
3042 "strexh", "\t$Rd, $Rt, [$Rn]",
3044 def STREX : AIstrex<0b00, (outs GPR:$Rd), (ins GPR:$Rt, GPR:$Rn),
3046 "strex", "\t$Rd, $Rt, [$Rn]",
3048 def STREXD : AIstrex<0b01, (outs GPR:$Rd),
3049 (ins GPR:$Rt, GPR:$Rt2, GPR:$Rn),
3051 "strexd", "\t$Rd, $Rt, $Rt2, [$Rn]",
3055 // Clear-Exclusive is for disassembly only.
3056 def CLREX : AXI<(outs), (ins), MiscFrm, NoItinerary, "clrex",
3057 [/* For disassembly only; pattern left blank */]>,
3058 Requires<[IsARM, HasV7]> {
3059 let Inst{31-0} = 0b11110101011111111111000000011111;
3062 // SWP/SWPB are deprecated in V6/V7 and for disassembly only.
3063 let mayLoad = 1 in {
3064 def SWP : AIswp<0, (outs GPR:$Rt), (ins GPR:$Rt2, GPR:$Rn), "swp",
3065 [/* For disassembly only; pattern left blank */]>;
3066 def SWPB : AIswp<1, (outs GPR:$Rt), (ins GPR:$Rt2, GPR:$Rn), "swpb",
3067 [/* For disassembly only; pattern left blank */]>;
3070 //===----------------------------------------------------------------------===//
3074 // __aeabi_read_tp preserves the registers r1-r3.
3075 // FIXME: This needs to be a pseudo of some sort so that we can get the
3076 // encoding right, complete with fixup for the aeabi_read_tp function.
3078 Defs = [R0, R12, LR, CPSR] in {
3079 def TPsoft : ABXI<0b1011, (outs), (ins), IIC_Br,
3080 "bl\t__aeabi_read_tp",
3081 [(set R0, ARMthread_pointer)]>;
3084 //===----------------------------------------------------------------------===//
3085 // SJLJ Exception handling intrinsics
3086 // eh_sjlj_setjmp() is an instruction sequence to store the return
3087 // address and save #0 in R0 for the non-longjmp case.
3088 // Since by its nature we may be coming from some other function to get
3089 // here, and we're using the stack frame for the containing function to
3090 // save/restore registers, we can't keep anything live in regs across
3091 // the eh_sjlj_setjmp(), else it will almost certainly have been tromped upon
3092 // when we get here from a longjmp(). We force everthing out of registers
3093 // except for our own input by listing the relevant registers in Defs. By
3094 // doing so, we also cause the prologue/epilogue code to actively preserve
3095 // all of the callee-saved resgisters, which is exactly what we want.
3096 // A constant value is passed in $val, and we use the location as a scratch.
3098 // These are pseudo-instructions and are lowered to individual MC-insts, so
3099 // no encoding information is necessary.
3101 [ R0, R1, R2, R3, R4, R5, R6, R7, R8, R9, R10, R11, R12, LR, D0,
3102 D1, D2, D3, D4, D5, D6, D7, D8, D9, D10, D11, D12, D13, D14, D15,
3103 D16, D17, D18, D19, D20, D21, D22, D23, D24, D25, D26, D27, D28, D29, D30,
3104 D31 ], hasSideEffects = 1, isBarrier = 1 in {
3105 def Int_eh_sjlj_setjmp : XI<(outs), (ins GPR:$src, GPR:$val),
3106 AddrModeNone, SizeSpecial, IndexModeNone,
3107 Pseudo, NoItinerary, "", "",
3108 [(set R0, (ARMeh_sjlj_setjmp GPR:$src, GPR:$val))]>,
3109 Requires<[IsARM, HasVFP2]>;
3113 [ R0, R1, R2, R3, R4, R5, R6, R7, R8, R9, R10, R11, R12, LR ],
3114 hasSideEffects = 1, isBarrier = 1 in {
3115 def Int_eh_sjlj_setjmp_nofp : XI<(outs), (ins GPR:$src, GPR:$val),
3116 AddrModeNone, SizeSpecial, IndexModeNone,
3117 Pseudo, NoItinerary, "", "",
3118 [(set R0, (ARMeh_sjlj_setjmp GPR:$src, GPR:$val))]>,
3119 Requires<[IsARM, NoVFP]>;
3122 // FIXME: Non-Darwin version(s)
3123 let isBarrier = 1, hasSideEffects = 1, isTerminator = 1,
3124 Defs = [ R7, LR, SP ] in {
3125 def Int_eh_sjlj_longjmp : XI<(outs), (ins GPR:$src, GPR:$scratch),
3126 AddrModeNone, SizeSpecial, IndexModeNone,
3127 Pseudo, NoItinerary, "", "",
3128 [(ARMeh_sjlj_longjmp GPR:$src, GPR:$scratch)]>,
3129 Requires<[IsARM, IsDarwin]>;
3132 // eh.sjlj.dispatchsetup pseudo-instruction.
3133 // This pseudo is used for ARM, Thumb1 and Thumb2. Any differences are
3134 // handled when the pseudo is expanded (which happens before any passes
3135 // that need the instruction size).
3136 let isBarrier = 1, hasSideEffects = 1 in
3137 def Int_eh_sjlj_dispatchsetup :
3138 PseudoInst<(outs), (ins GPR:$src), NoItinerary, "",
3139 [(ARMeh_sjlj_dispatchsetup GPR:$src)]>,
3140 Requires<[IsDarwin]>;
3142 //===----------------------------------------------------------------------===//
3143 // Non-Instruction Patterns
3146 // Large immediate handling.
3148 // Two piece so_imms.
3149 // FIXME: Remove this when we can do generalized remat.
3150 let isReMaterializable = 1 in
3151 def MOVi2pieces : PseudoInst<(outs GPR:$dst), (ins so_imm2part:$src),
3153 [(set GPR:$dst, (so_imm2part:$src))]>,
3154 Requires<[IsARM, NoV6T2]>;
3156 def : ARMPat<(or GPR:$LHS, so_imm2part:$RHS),
3157 (ORRri (ORRri GPR:$LHS, (so_imm2part_1 imm:$RHS)),
3158 (so_imm2part_2 imm:$RHS))>;
3159 def : ARMPat<(xor GPR:$LHS, so_imm2part:$RHS),
3160 (EORri (EORri GPR:$LHS, (so_imm2part_1 imm:$RHS)),
3161 (so_imm2part_2 imm:$RHS))>;
3162 def : ARMPat<(add GPR:$LHS, so_imm2part:$RHS),
3163 (ADDri (ADDri GPR:$LHS, (so_imm2part_1 imm:$RHS)),
3164 (so_imm2part_2 imm:$RHS))>;
3165 def : ARMPat<(add GPR:$LHS, so_neg_imm2part:$RHS),
3166 (SUBri (SUBri GPR:$LHS, (so_neg_imm2part_1 imm:$RHS)),
3167 (so_neg_imm2part_2 imm:$RHS))>;
3169 // 32-bit immediate using movw + movt.
3170 // This is a single pseudo instruction, the benefit is that it can be remat'd
3171 // as a single unit instead of having to handle reg inputs.
3172 // FIXME: Remove this when we can do generalized remat.
3173 let isReMaterializable = 1 in
3174 def MOVi32imm : PseudoInst<(outs GPR:$dst), (ins i32imm:$src), IIC_iMOVix2, "",
3175 [(set GPR:$dst, (i32 imm:$src))]>,
3176 Requires<[IsARM, HasV6T2]>;
3178 // ConstantPool, GlobalAddress, and JumpTable
3179 def : ARMPat<(ARMWrapper tglobaladdr :$dst), (LEApcrel tglobaladdr :$dst)>,
3180 Requires<[IsARM, DontUseMovt]>;
3181 def : ARMPat<(ARMWrapper tconstpool :$dst), (LEApcrel tconstpool :$dst)>;
3182 def : ARMPat<(ARMWrapper tglobaladdr :$dst), (MOVi32imm tglobaladdr :$dst)>,
3183 Requires<[IsARM, UseMovt]>;
3184 def : ARMPat<(ARMWrapperJT tjumptable:$dst, imm:$id),
3185 (LEApcrelJT tjumptable:$dst, imm:$id)>;
3187 // TODO: add,sub,and, 3-instr forms?
3190 def : ARMPat<(ARMtcret tcGPR:$dst),
3191 (TCRETURNri tcGPR:$dst)>, Requires<[IsDarwin]>;
3193 def : ARMPat<(ARMtcret (i32 tglobaladdr:$dst)),
3194 (TCRETURNdi texternalsym:$dst)>, Requires<[IsDarwin]>;
3196 def : ARMPat<(ARMtcret (i32 texternalsym:$dst)),
3197 (TCRETURNdi texternalsym:$dst)>, Requires<[IsDarwin]>;
3199 def : ARMPat<(ARMtcret tcGPR:$dst),
3200 (TCRETURNriND tcGPR:$dst)>, Requires<[IsNotDarwin]>;
3202 def : ARMPat<(ARMtcret (i32 tglobaladdr:$dst)),
3203 (TCRETURNdiND texternalsym:$dst)>, Requires<[IsNotDarwin]>;
3205 def : ARMPat<(ARMtcret (i32 texternalsym:$dst)),
3206 (TCRETURNdiND texternalsym:$dst)>, Requires<[IsNotDarwin]>;
3209 def : ARMPat<(ARMcall texternalsym:$func), (BL texternalsym:$func)>,
3210 Requires<[IsARM, IsNotDarwin]>;
3211 def : ARMPat<(ARMcall texternalsym:$func), (BLr9 texternalsym:$func)>,
3212 Requires<[IsARM, IsDarwin]>;
3214 // zextload i1 -> zextload i8
3215 def : ARMPat<(zextloadi1 addrmode_imm12:$addr), (LDRBi12 addrmode_imm12:$addr)>;
3216 def : ARMPat<(zextloadi1 ldst_so_reg:$addr), (LDRBrs ldst_so_reg:$addr)>;
3218 // extload -> zextload
3219 def : ARMPat<(extloadi1 addrmode_imm12:$addr), (LDRBi12 addrmode_imm12:$addr)>;
3220 def : ARMPat<(extloadi1 ldst_so_reg:$addr), (LDRBrs ldst_so_reg:$addr)>;
3221 def : ARMPat<(extloadi8 addrmode_imm12:$addr), (LDRBi12 addrmode_imm12:$addr)>;
3222 def : ARMPat<(extloadi8 ldst_so_reg:$addr), (LDRBrs ldst_so_reg:$addr)>;
3224 def : ARMPat<(extloadi16 addrmode3:$addr), (LDRH addrmode3:$addr)>;
3226 def : ARMPat<(extloadi8 addrmodepc:$addr), (PICLDRB addrmodepc:$addr)>;
3227 def : ARMPat<(extloadi16 addrmodepc:$addr), (PICLDRH addrmodepc:$addr)>;
3230 def : ARMV5TEPat<(mul (sra (shl GPR:$a, (i32 16)), (i32 16)),
3231 (sra (shl GPR:$b, (i32 16)), (i32 16))),
3232 (SMULBB GPR:$a, GPR:$b)>;
3233 def : ARMV5TEPat<(mul sext_16_node:$a, sext_16_node:$b),
3234 (SMULBB GPR:$a, GPR:$b)>;
3235 def : ARMV5TEPat<(mul (sra (shl GPR:$a, (i32 16)), (i32 16)),
3236 (sra GPR:$b, (i32 16))),
3237 (SMULBT GPR:$a, GPR:$b)>;
3238 def : ARMV5TEPat<(mul sext_16_node:$a, (sra GPR:$b, (i32 16))),
3239 (SMULBT GPR:$a, GPR:$b)>;
3240 def : ARMV5TEPat<(mul (sra GPR:$a, (i32 16)),
3241 (sra (shl GPR:$b, (i32 16)), (i32 16))),
3242 (SMULTB GPR:$a, GPR:$b)>;
3243 def : ARMV5TEPat<(mul (sra GPR:$a, (i32 16)), sext_16_node:$b),
3244 (SMULTB GPR:$a, GPR:$b)>;
3245 def : ARMV5TEPat<(sra (mul GPR:$a, (sra (shl GPR:$b, (i32 16)), (i32 16))),
3247 (SMULWB GPR:$a, GPR:$b)>;
3248 def : ARMV5TEPat<(sra (mul GPR:$a, sext_16_node:$b), (i32 16)),
3249 (SMULWB GPR:$a, GPR:$b)>;
3251 def : ARMV5TEPat<(add GPR:$acc,
3252 (mul (sra (shl GPR:$a, (i32 16)), (i32 16)),
3253 (sra (shl GPR:$b, (i32 16)), (i32 16)))),
3254 (SMLABB GPR:$a, GPR:$b, GPR:$acc)>;
3255 def : ARMV5TEPat<(add GPR:$acc,
3256 (mul sext_16_node:$a, sext_16_node:$b)),
3257 (SMLABB GPR:$a, GPR:$b, GPR:$acc)>;
3258 def : ARMV5TEPat<(add GPR:$acc,
3259 (mul (sra (shl GPR:$a, (i32 16)), (i32 16)),
3260 (sra GPR:$b, (i32 16)))),
3261 (SMLABT GPR:$a, GPR:$b, GPR:$acc)>;
3262 def : ARMV5TEPat<(add GPR:$acc,
3263 (mul sext_16_node:$a, (sra GPR:$b, (i32 16)))),
3264 (SMLABT GPR:$a, GPR:$b, GPR:$acc)>;
3265 def : ARMV5TEPat<(add GPR:$acc,
3266 (mul (sra GPR:$a, (i32 16)),
3267 (sra (shl GPR:$b, (i32 16)), (i32 16)))),
3268 (SMLATB GPR:$a, GPR:$b, GPR:$acc)>;
3269 def : ARMV5TEPat<(add GPR:$acc,
3270 (mul (sra GPR:$a, (i32 16)), sext_16_node:$b)),
3271 (SMLATB GPR:$a, GPR:$b, GPR:$acc)>;
3272 def : ARMV5TEPat<(add GPR:$acc,
3273 (sra (mul GPR:$a, (sra (shl GPR:$b, (i32 16)), (i32 16))),
3275 (SMLAWB GPR:$a, GPR:$b, GPR:$acc)>;
3276 def : ARMV5TEPat<(add GPR:$acc,
3277 (sra (mul GPR:$a, sext_16_node:$b), (i32 16))),
3278 (SMLAWB GPR:$a, GPR:$b, GPR:$acc)>;
3280 //===----------------------------------------------------------------------===//
3284 include "ARMInstrThumb.td"
3286 //===----------------------------------------------------------------------===//
3290 include "ARMInstrThumb2.td"
3292 //===----------------------------------------------------------------------===//
3293 // Floating Point Support
3296 include "ARMInstrVFP.td"
3298 //===----------------------------------------------------------------------===//
3299 // Advanced SIMD (NEON) Support
3302 include "ARMInstrNEON.td"
3304 //===----------------------------------------------------------------------===//
3305 // Coprocessor Instructions. For disassembly only.
3308 def CDP : ABI<0b1110, (outs), (ins nohash_imm:$cop, i32imm:$opc1,
3309 nohash_imm:$CRd, nohash_imm:$CRn, nohash_imm:$CRm, i32imm:$opc2),
3310 NoItinerary, "cdp", "\tp$cop, $opc1, cr$CRd, cr$CRn, cr$CRm, $opc2",
3311 [/* For disassembly only; pattern left blank */]> {
3315 def CDP2 : ABXI<0b1110, (outs), (ins nohash_imm:$cop, i32imm:$opc1,
3316 nohash_imm:$CRd, nohash_imm:$CRn, nohash_imm:$CRm, i32imm:$opc2),
3317 NoItinerary, "cdp2\tp$cop, $opc1, cr$CRd, cr$CRn, cr$CRm, $opc2",
3318 [/* For disassembly only; pattern left blank */]> {
3319 let Inst{31-28} = 0b1111;
3323 class ACI<dag oops, dag iops, string opc, string asm>
3324 : I<oops, iops, AddrModeNone, Size4Bytes, IndexModeNone, BrFrm, NoItinerary,
3325 opc, asm, "", [/* For disassembly only; pattern left blank */]> {
3326 let Inst{27-25} = 0b110;
3329 multiclass LdStCop<bits<4> op31_28, bit load, string opc> {
3331 def _OFFSET : ACI<(outs),
3332 (ins nohash_imm:$cop, nohash_imm:$CRd, addrmode2:$addr),
3333 opc, "\tp$cop, cr$CRd, $addr"> {
3334 let Inst{31-28} = op31_28;
3335 let Inst{24} = 1; // P = 1
3336 let Inst{21} = 0; // W = 0
3337 let Inst{22} = 0; // D = 0
3338 let Inst{20} = load;
3341 def _PRE : ACI<(outs),
3342 (ins nohash_imm:$cop, nohash_imm:$CRd, addrmode2:$addr),
3343 opc, "\tp$cop, cr$CRd, $addr!"> {
3344 let Inst{31-28} = op31_28;
3345 let Inst{24} = 1; // P = 1
3346 let Inst{21} = 1; // W = 1
3347 let Inst{22} = 0; // D = 0
3348 let Inst{20} = load;
3351 def _POST : ACI<(outs),
3352 (ins nohash_imm:$cop, nohash_imm:$CRd, GPR:$base, am2offset:$offset),
3353 opc, "\tp$cop, cr$CRd, [$base], $offset"> {
3354 let Inst{31-28} = op31_28;
3355 let Inst{24} = 0; // P = 0
3356 let Inst{21} = 1; // W = 1
3357 let Inst{22} = 0; // D = 0
3358 let Inst{20} = load;
3361 def _OPTION : ACI<(outs),
3362 (ins nohash_imm:$cop, nohash_imm:$CRd, GPR:$base, i32imm:$option),
3363 opc, "\tp$cop, cr$CRd, [$base], $option"> {
3364 let Inst{31-28} = op31_28;
3365 let Inst{24} = 0; // P = 0
3366 let Inst{23} = 1; // U = 1
3367 let Inst{21} = 0; // W = 0
3368 let Inst{22} = 0; // D = 0
3369 let Inst{20} = load;
3372 def L_OFFSET : ACI<(outs),
3373 (ins nohash_imm:$cop, nohash_imm:$CRd, addrmode2:$addr),
3374 !strconcat(opc, "l"), "\tp$cop, cr$CRd, $addr"> {
3375 let Inst{31-28} = op31_28;
3376 let Inst{24} = 1; // P = 1
3377 let Inst{21} = 0; // W = 0
3378 let Inst{22} = 1; // D = 1
3379 let Inst{20} = load;
3382 def L_PRE : ACI<(outs),
3383 (ins nohash_imm:$cop, nohash_imm:$CRd, addrmode2:$addr),
3384 !strconcat(opc, "l"), "\tp$cop, cr$CRd, $addr!"> {
3385 let Inst{31-28} = op31_28;
3386 let Inst{24} = 1; // P = 1
3387 let Inst{21} = 1; // W = 1
3388 let Inst{22} = 1; // D = 1
3389 let Inst{20} = load;
3392 def L_POST : ACI<(outs),
3393 (ins nohash_imm:$cop, nohash_imm:$CRd, GPR:$base, am2offset:$offset),
3394 !strconcat(opc, "l"), "\tp$cop, cr$CRd, [$base], $offset"> {
3395 let Inst{31-28} = op31_28;
3396 let Inst{24} = 0; // P = 0
3397 let Inst{21} = 1; // W = 1
3398 let Inst{22} = 1; // D = 1
3399 let Inst{20} = load;
3402 def L_OPTION : ACI<(outs),
3403 (ins nohash_imm:$cop, nohash_imm:$CRd, GPR:$base, nohash_imm:$option),
3404 !strconcat(opc, "l"), "\tp$cop, cr$CRd, [$base], $option"> {
3405 let Inst{31-28} = op31_28;
3406 let Inst{24} = 0; // P = 0
3407 let Inst{23} = 1; // U = 1
3408 let Inst{21} = 0; // W = 0
3409 let Inst{22} = 1; // D = 1
3410 let Inst{20} = load;
3414 defm LDC : LdStCop<{?,?,?,?}, 1, "ldc">;
3415 defm LDC2 : LdStCop<0b1111, 1, "ldc2">;
3416 defm STC : LdStCop<{?,?,?,?}, 0, "stc">;
3417 defm STC2 : LdStCop<0b1111, 0, "stc2">;
3419 def MCR : ABI<0b1110, (outs), (ins nohash_imm:$cop, i32imm:$opc1,
3420 GPR:$Rt, nohash_imm:$CRn, nohash_imm:$CRm, i32imm:$opc2),
3421 NoItinerary, "mcr", "\tp$cop, $opc1, $Rt, cr$CRn, cr$CRm, $opc2",
3422 [/* For disassembly only; pattern left blank */]> {
3427 def MCR2 : ABXI<0b1110, (outs), (ins nohash_imm:$cop, i32imm:$opc1,
3428 GPR:$Rt, nohash_imm:$CRn, nohash_imm:$CRm, i32imm:$opc2),
3429 NoItinerary, "mcr2\tp$cop, $opc1, $Rt, cr$CRn, cr$CRm, $opc2",
3430 [/* For disassembly only; pattern left blank */]> {
3431 let Inst{31-28} = 0b1111;
3436 def MRC : ABI<0b1110, (outs), (ins nohash_imm:$cop, i32imm:$opc1,
3437 GPR:$Rt, nohash_imm:$CRn, nohash_imm:$CRm, i32imm:$opc2),
3438 NoItinerary, "mrc", "\tp$cop, $opc1, $Rt, cr$CRn, cr$CRm, $opc2",
3439 [/* For disassembly only; pattern left blank */]> {
3444 def MRC2 : ABXI<0b1110, (outs), (ins nohash_imm:$cop, i32imm:$opc1,
3445 GPR:$Rt, nohash_imm:$CRn, nohash_imm:$CRm, i32imm:$opc2),
3446 NoItinerary, "mrc2\tp$cop, $opc1, $Rt, cr$CRn, cr$CRm, $opc2",
3447 [/* For disassembly only; pattern left blank */]> {
3448 let Inst{31-28} = 0b1111;
3453 def MCRR : ABI<0b1100, (outs), (ins nohash_imm:$cop, i32imm:$opc,
3454 GPR:$Rt, GPR:$Rt2, nohash_imm:$CRm),
3455 NoItinerary, "mcrr", "\tp$cop, $opc, $Rt, $Rt2, cr$CRm",
3456 [/* For disassembly only; pattern left blank */]> {
3457 let Inst{23-20} = 0b0100;
3460 def MCRR2 : ABXI<0b1100, (outs), (ins nohash_imm:$cop, i32imm:$opc,
3461 GPR:$Rt, GPR:$Rt2, nohash_imm:$CRm),
3462 NoItinerary, "mcrr2\tp$cop, $opc, $Rt, $Rt2, cr$CRm",
3463 [/* For disassembly only; pattern left blank */]> {
3464 let Inst{31-28} = 0b1111;
3465 let Inst{23-20} = 0b0100;
3468 def MRRC : ABI<0b1100, (outs), (ins nohash_imm:$cop, i32imm:$opc,
3469 GPR:$Rt, GPR:$Rt2, nohash_imm:$CRm),
3470 NoItinerary, "mrrc", "\tp$cop, $opc, $Rt, $Rt2, cr$CRm",
3471 [/* For disassembly only; pattern left blank */]> {
3472 let Inst{23-20} = 0b0101;
3475 def MRRC2 : ABXI<0b1100, (outs), (ins nohash_imm:$cop, i32imm:$opc,
3476 GPR:$Rt, GPR:$Rt2, nohash_imm:$CRm),
3477 NoItinerary, "mrrc2\tp$cop, $opc, $Rt, $Rt2, cr$CRm",
3478 [/* For disassembly only; pattern left blank */]> {
3479 let Inst{31-28} = 0b1111;
3480 let Inst{23-20} = 0b0101;
3483 //===----------------------------------------------------------------------===//
3484 // Move between special register and ARM core register -- for disassembly only
3487 def MRS : ABI<0b0001,(outs GPR:$dst),(ins), NoItinerary, "mrs", "\t$dst, cpsr",
3488 [/* For disassembly only; pattern left blank */]> {
3489 let Inst{23-20} = 0b0000;
3490 let Inst{7-4} = 0b0000;
3493 def MRSsys : ABI<0b0001,(outs GPR:$dst),(ins), NoItinerary,"mrs","\t$dst, spsr",
3494 [/* For disassembly only; pattern left blank */]> {
3495 let Inst{23-20} = 0b0100;
3496 let Inst{7-4} = 0b0000;
3499 def MSR : ABI<0b0001, (outs), (ins GPR:$src, msr_mask:$mask), NoItinerary,
3500 "msr", "\tcpsr$mask, $src",
3501 [/* For disassembly only; pattern left blank */]> {
3502 let Inst{23-20} = 0b0010;
3503 let Inst{7-4} = 0b0000;
3506 def MSRi : ABI<0b0011, (outs), (ins so_imm:$a, msr_mask:$mask), NoItinerary,
3507 "msr", "\tcpsr$mask, $a",
3508 [/* For disassembly only; pattern left blank */]> {
3509 let Inst{23-20} = 0b0010;
3510 let Inst{7-4} = 0b0000;
3513 def MSRsys : ABI<0b0001, (outs), (ins GPR:$src, msr_mask:$mask), NoItinerary,
3514 "msr", "\tspsr$mask, $src",
3515 [/* For disassembly only; pattern left blank */]> {
3516 let Inst{23-20} = 0b0110;
3517 let Inst{7-4} = 0b0000;
3520 def MSRsysi : ABI<0b0011, (outs), (ins so_imm:$a, msr_mask:$mask), NoItinerary,
3521 "msr", "\tspsr$mask, $a",
3522 [/* For disassembly only; pattern left blank */]> {
3523 let Inst{23-20} = 0b0110;
3524 let Inst{7-4} = 0b0000;