1 //===- ARMInstrInfo.td - Target Description for ARM Target -*- tablegen -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file describes the ARM instructions in TableGen format.
12 //===----------------------------------------------------------------------===//
14 //===----------------------------------------------------------------------===//
15 // ARM specific DAG Nodes.
19 def SDT_ARMCallSeqStart : SDCallSeqStart<[ SDTCisVT<0, i32> ]>;
20 def SDT_ARMCallSeqEnd : SDCallSeqEnd<[ SDTCisVT<0, i32>, SDTCisVT<1, i32> ]>;
22 def SDT_ARMSaveCallPC : SDTypeProfile<0, 1, []>;
24 def SDT_ARMcall : SDTypeProfile<0, -1, [SDTCisPtrTy<0>]>;
26 def SDT_ARMCMov : SDTypeProfile<1, 3,
27 [SDTCisSameAs<0, 1>, SDTCisSameAs<0, 2>,
30 def SDT_ARMBrcond : SDTypeProfile<0, 2,
31 [SDTCisVT<0, OtherVT>, SDTCisVT<1, i32>]>;
33 def SDT_ARMBrJT : SDTypeProfile<0, 3,
34 [SDTCisPtrTy<0>, SDTCisVT<1, i32>,
37 def SDT_ARMBr2JT : SDTypeProfile<0, 4,
38 [SDTCisPtrTy<0>, SDTCisVT<1, i32>,
39 SDTCisVT<2, i32>, SDTCisVT<3, i32>]>;
41 def SDT_ARMBCC_i64 : SDTypeProfile<0, 6,
43 SDTCisVT<1, i32>, SDTCisVT<2, i32>,
44 SDTCisVT<3, i32>, SDTCisVT<4, i32>,
45 SDTCisVT<5, OtherVT>]>;
47 def SDT_ARMAnd : SDTypeProfile<1, 2,
48 [SDTCisVT<0, i32>, SDTCisVT<1, i32>,
51 def SDT_ARMCmp : SDTypeProfile<0, 2, [SDTCisSameAs<0, 1>]>;
53 def SDT_ARMPICAdd : SDTypeProfile<1, 2, [SDTCisSameAs<0, 1>,
54 SDTCisPtrTy<1>, SDTCisVT<2, i32>]>;
56 def SDT_ARMThreadPointer : SDTypeProfile<1, 0, [SDTCisPtrTy<0>]>;
57 def SDT_ARMEH_SJLJ_Setjmp : SDTypeProfile<1, 2, [SDTCisInt<0>, SDTCisPtrTy<1>,
59 def SDT_ARMEH_SJLJ_Longjmp: SDTypeProfile<0, 2, [SDTCisPtrTy<0>, SDTCisInt<1>]>;
61 def SDT_ARMMEMBARRIER : SDTypeProfile<0, 1, [SDTCisInt<0>]>;
63 def SDT_ARMPREFETCH : SDTypeProfile<0, 3, [SDTCisPtrTy<0>, SDTCisSameAs<1, 2>,
66 def SDT_ARMTCRET : SDTypeProfile<0, 1, [SDTCisPtrTy<0>]>;
68 def SDT_ARMBFI : SDTypeProfile<1, 3, [SDTCisVT<0, i32>, SDTCisVT<1, i32>,
69 SDTCisVT<2, i32>, SDTCisVT<3, i32>]>;
71 def SDTBinaryArithWithFlags : SDTypeProfile<2, 2,
74 SDTCisInt<0>, SDTCisVT<1, i32>]>;
76 // SDTBinaryArithWithFlagsInOut - RES1, CPSR = op LHS, RHS, CPSR
77 def SDTBinaryArithWithFlagsInOut : SDTypeProfile<2, 3,
84 def ARMWrapper : SDNode<"ARMISD::Wrapper", SDTIntUnaryOp>;
85 def ARMWrapperDYN : SDNode<"ARMISD::WrapperDYN", SDTIntUnaryOp>;
86 def ARMWrapperPIC : SDNode<"ARMISD::WrapperPIC", SDTIntUnaryOp>;
87 def ARMWrapperJT : SDNode<"ARMISD::WrapperJT", SDTIntBinOp>;
89 def ARMcallseq_start : SDNode<"ISD::CALLSEQ_START", SDT_ARMCallSeqStart,
90 [SDNPHasChain, SDNPOutGlue]>;
91 def ARMcallseq_end : SDNode<"ISD::CALLSEQ_END", SDT_ARMCallSeqEnd,
92 [SDNPHasChain, SDNPOptInGlue, SDNPOutGlue]>;
94 def ARMcall : SDNode<"ARMISD::CALL", SDT_ARMcall,
95 [SDNPHasChain, SDNPOptInGlue, SDNPOutGlue,
97 def ARMcall_pred : SDNode<"ARMISD::CALL_PRED", SDT_ARMcall,
98 [SDNPHasChain, SDNPOptInGlue, SDNPOutGlue,
100 def ARMcall_nolink : SDNode<"ARMISD::CALL_NOLINK", SDT_ARMcall,
101 [SDNPHasChain, SDNPOptInGlue, SDNPOutGlue,
104 def ARMretflag : SDNode<"ARMISD::RET_FLAG", SDTNone,
105 [SDNPHasChain, SDNPOptInGlue]>;
107 def ARMcmov : SDNode<"ARMISD::CMOV", SDT_ARMCMov,
110 def ARMbrcond : SDNode<"ARMISD::BRCOND", SDT_ARMBrcond,
111 [SDNPHasChain, SDNPInGlue, SDNPOutGlue]>;
113 def ARMbrjt : SDNode<"ARMISD::BR_JT", SDT_ARMBrJT,
115 def ARMbr2jt : SDNode<"ARMISD::BR2_JT", SDT_ARMBr2JT,
118 def ARMBcci64 : SDNode<"ARMISD::BCC_i64", SDT_ARMBCC_i64,
121 def ARMcmp : SDNode<"ARMISD::CMP", SDT_ARMCmp,
124 def ARMcmpZ : SDNode<"ARMISD::CMPZ", SDT_ARMCmp,
125 [SDNPOutGlue, SDNPCommutative]>;
127 def ARMpic_add : SDNode<"ARMISD::PIC_ADD", SDT_ARMPICAdd>;
129 def ARMsrl_flag : SDNode<"ARMISD::SRL_FLAG", SDTIntUnaryOp, [SDNPOutGlue]>;
130 def ARMsra_flag : SDNode<"ARMISD::SRA_FLAG", SDTIntUnaryOp, [SDNPOutGlue]>;
131 def ARMrrx : SDNode<"ARMISD::RRX" , SDTIntUnaryOp, [SDNPInGlue ]>;
133 def ARMaddc : SDNode<"ARMISD::ADDC", SDTBinaryArithWithFlags,
135 def ARMsubc : SDNode<"ARMISD::SUBC", SDTBinaryArithWithFlags>;
136 def ARMadde : SDNode<"ARMISD::ADDE", SDTBinaryArithWithFlagsInOut>;
137 def ARMsube : SDNode<"ARMISD::SUBE", SDTBinaryArithWithFlagsInOut>;
139 def ARMthread_pointer: SDNode<"ARMISD::THREAD_POINTER", SDT_ARMThreadPointer>;
140 def ARMeh_sjlj_setjmp: SDNode<"ARMISD::EH_SJLJ_SETJMP",
141 SDT_ARMEH_SJLJ_Setjmp, [SDNPHasChain]>;
142 def ARMeh_sjlj_longjmp: SDNode<"ARMISD::EH_SJLJ_LONGJMP",
143 SDT_ARMEH_SJLJ_Longjmp, [SDNPHasChain]>;
145 def ARMMemBarrier : SDNode<"ARMISD::MEMBARRIER", SDT_ARMMEMBARRIER,
147 def ARMMemBarrierMCR : SDNode<"ARMISD::MEMBARRIER_MCR", SDT_ARMMEMBARRIER,
149 def ARMPreload : SDNode<"ARMISD::PRELOAD", SDT_ARMPREFETCH,
150 [SDNPHasChain, SDNPMayLoad, SDNPMayStore]>;
152 def ARMrbit : SDNode<"ARMISD::RBIT", SDTIntUnaryOp>;
154 def ARMtcret : SDNode<"ARMISD::TC_RETURN", SDT_ARMTCRET,
155 [SDNPHasChain, SDNPOptInGlue, SDNPVariadic]>;
158 def ARMbfi : SDNode<"ARMISD::BFI", SDT_ARMBFI>;
160 //===----------------------------------------------------------------------===//
161 // ARM Instruction Predicate Definitions.
163 def HasV4T : Predicate<"Subtarget->hasV4TOps()">,
164 AssemblerPredicate<"HasV4TOps">;
165 def NoV4T : Predicate<"!Subtarget->hasV4TOps()">;
166 def HasV5T : Predicate<"Subtarget->hasV5TOps()">;
167 def HasV5TE : Predicate<"Subtarget->hasV5TEOps()">,
168 AssemblerPredicate<"HasV5TEOps">;
169 def HasV6 : Predicate<"Subtarget->hasV6Ops()">,
170 AssemblerPredicate<"HasV6Ops">;
171 def NoV6 : Predicate<"!Subtarget->hasV6Ops()">;
172 def HasV6T2 : Predicate<"Subtarget->hasV6T2Ops()">,
173 AssemblerPredicate<"HasV6T2Ops">;
174 def NoV6T2 : Predicate<"!Subtarget->hasV6T2Ops()">;
175 def HasV7 : Predicate<"Subtarget->hasV7Ops()">,
176 AssemblerPredicate<"HasV7Ops">;
177 def NoVFP : Predicate<"!Subtarget->hasVFP2()">;
178 def HasVFP2 : Predicate<"Subtarget->hasVFP2()">,
179 AssemblerPredicate<"FeatureVFP2">;
180 def HasVFP3 : Predicate<"Subtarget->hasVFP3()">,
181 AssemblerPredicate<"FeatureVFP3">;
182 def HasNEON : Predicate<"Subtarget->hasNEON()">,
183 AssemblerPredicate<"FeatureNEON">;
184 def HasFP16 : Predicate<"Subtarget->hasFP16()">,
185 AssemblerPredicate<"FeatureFP16">;
186 def HasDivide : Predicate<"Subtarget->hasDivide()">,
187 AssemblerPredicate<"FeatureHWDiv">;
188 def HasT2ExtractPack : Predicate<"Subtarget->hasT2ExtractPack()">,
189 AssemblerPredicate<"FeatureT2XtPk">;
190 def HasThumb2DSP : Predicate<"Subtarget->hasThumb2DSP()">,
191 AssemblerPredicate<"FeatureDSPThumb2">;
192 def HasDB : Predicate<"Subtarget->hasDataBarrier()">,
193 AssemblerPredicate<"FeatureDB">;
194 def HasMP : Predicate<"Subtarget->hasMPExtension()">,
195 AssemblerPredicate<"FeatureMP">;
196 def UseNEONForFP : Predicate<"Subtarget->useNEONForSinglePrecisionFP()">;
197 def DontUseNEONForFP : Predicate<"!Subtarget->useNEONForSinglePrecisionFP()">;
198 def IsThumb : Predicate<"Subtarget->isThumb()">,
199 AssemblerPredicate<"ModeThumb">;
200 def IsThumb1Only : Predicate<"Subtarget->isThumb1Only()">;
201 def IsThumb2 : Predicate<"Subtarget->isThumb2()">,
202 AssemblerPredicate<"ModeThumb,FeatureThumb2">;
203 def IsMClass : Predicate<"Subtarget->isMClass()">,
204 AssemblerPredicate<"FeatureMClass">;
205 def IsARClass : Predicate<"!Subtarget->isMClass()">,
206 AssemblerPredicate<"!FeatureMClass">;
207 def IsARM : Predicate<"!Subtarget->isThumb()">,
208 AssemblerPredicate<"!ModeThumb">;
209 def IsIOS : Predicate<"Subtarget->isTargetIOS()">;
210 def IsNotIOS : Predicate<"!Subtarget->isTargetIOS()">;
211 def IsNaCl : Predicate<"Subtarget->isTargetNaCl()">;
213 // FIXME: Eventually this will be just "hasV6T2Ops".
214 def UseMovt : Predicate<"Subtarget->useMovt()">;
215 def DontUseMovt : Predicate<"!Subtarget->useMovt()">;
216 def UseFPVMLx : Predicate<"Subtarget->useFPVMLx()">;
218 //===----------------------------------------------------------------------===//
219 // ARM Flag Definitions.
221 class RegConstraint<string C> {
222 string Constraints = C;
225 //===----------------------------------------------------------------------===//
226 // ARM specific transformation functions and pattern fragments.
229 // so_imm_neg_XFORM - Return a so_imm value packed into the format described for
230 // so_imm_neg def below.
231 def so_imm_neg_XFORM : SDNodeXForm<imm, [{
232 return CurDAG->getTargetConstant(-(int)N->getZExtValue(), MVT::i32);
235 // so_imm_not_XFORM - Return a so_imm value packed into the format described for
236 // so_imm_not def below.
237 def so_imm_not_XFORM : SDNodeXForm<imm, [{
238 return CurDAG->getTargetConstant(~(int)N->getZExtValue(), MVT::i32);
241 /// imm16_31 predicate - True if the 32-bit immediate is in the range [16,31].
242 def imm16_31 : ImmLeaf<i32, [{
243 return (int32_t)Imm >= 16 && (int32_t)Imm < 32;
246 def so_imm_neg_asmoperand : AsmOperandClass { let Name = "ARMSOImmNeg"; }
247 def so_imm_neg : Operand<i32>, PatLeaf<(imm), [{
248 return ARM_AM::getSOImmVal(-(uint32_t)N->getZExtValue()) != -1;
249 }], so_imm_neg_XFORM> {
250 let ParserMatchClass = so_imm_neg_asmoperand;
253 // Note: this pattern doesn't require an encoder method and such, as it's
254 // only used on aliases (Pat<> and InstAlias<>). The actual encoding
255 // is handled by the destination instructions, which use so_imm.
256 def so_imm_not_asmoperand : AsmOperandClass { let Name = "ARMSOImmNot"; }
257 def so_imm_not : Operand<i32>, PatLeaf<(imm), [{
258 return ARM_AM::getSOImmVal(~(uint32_t)N->getZExtValue()) != -1;
259 }], so_imm_not_XFORM> {
260 let ParserMatchClass = so_imm_not_asmoperand;
263 // sext_16_node predicate - True if the SDNode is sign-extended 16 or more bits.
264 def sext_16_node : PatLeaf<(i32 GPR:$a), [{
265 return CurDAG->ComputeNumSignBits(SDValue(N,0)) >= 17;
268 /// Split a 32-bit immediate into two 16 bit parts.
269 def hi16 : SDNodeXForm<imm, [{
270 return CurDAG->getTargetConstant((uint32_t)N->getZExtValue() >> 16, MVT::i32);
273 def lo16AllZero : PatLeaf<(i32 imm), [{
274 // Returns true if all low 16-bits are 0.
275 return (((uint32_t)N->getZExtValue()) & 0xFFFFUL) == 0;
278 class BinOpWithFlagFrag<dag res> :
279 PatFrag<(ops node:$LHS, node:$RHS, node:$FLAG), res>;
280 class BinOpFrag<dag res> : PatFrag<(ops node:$LHS, node:$RHS), res>;
281 class UnOpFrag <dag res> : PatFrag<(ops node:$Src), res>;
283 // An 'and' node with a single use.
284 def and_su : PatFrag<(ops node:$lhs, node:$rhs), (and node:$lhs, node:$rhs), [{
285 return N->hasOneUse();
288 // An 'xor' node with a single use.
289 def xor_su : PatFrag<(ops node:$lhs, node:$rhs), (xor node:$lhs, node:$rhs), [{
290 return N->hasOneUse();
293 // An 'fmul' node with a single use.
294 def fmul_su : PatFrag<(ops node:$lhs, node:$rhs), (fmul node:$lhs, node:$rhs),[{
295 return N->hasOneUse();
298 // An 'fadd' node which checks for single non-hazardous use.
299 def fadd_mlx : PatFrag<(ops node:$lhs, node:$rhs),(fadd node:$lhs, node:$rhs),[{
300 return hasNoVMLxHazardUse(N);
303 // An 'fsub' node which checks for single non-hazardous use.
304 def fsub_mlx : PatFrag<(ops node:$lhs, node:$rhs),(fsub node:$lhs, node:$rhs),[{
305 return hasNoVMLxHazardUse(N);
308 //===----------------------------------------------------------------------===//
309 // Operand Definitions.
312 // Immediate operands with a shared generic asm render method.
313 class ImmAsmOperand : AsmOperandClass { let RenderMethod = "addImmOperands"; }
316 // FIXME: rename brtarget to t2_brtarget
317 def brtarget : Operand<OtherVT> {
318 let EncoderMethod = "getBranchTargetOpValue";
319 let OperandType = "OPERAND_PCREL";
320 let DecoderMethod = "DecodeT2BROperand";
323 // FIXME: get rid of this one?
324 def uncondbrtarget : Operand<OtherVT> {
325 let EncoderMethod = "getUnconditionalBranchTargetOpValue";
326 let OperandType = "OPERAND_PCREL";
329 // Branch target for ARM. Handles conditional/unconditional
330 def br_target : Operand<OtherVT> {
331 let EncoderMethod = "getARMBranchTargetOpValue";
332 let OperandType = "OPERAND_PCREL";
336 // FIXME: rename bltarget to t2_bl_target?
337 def bltarget : Operand<i32> {
338 // Encoded the same as branch targets.
339 let EncoderMethod = "getBranchTargetOpValue";
340 let OperandType = "OPERAND_PCREL";
343 // Call target for ARM. Handles conditional/unconditional
344 // FIXME: rename bl_target to t2_bltarget?
345 def bl_target : Operand<i32> {
346 // Encoded the same as branch targets.
347 let EncoderMethod = "getARMBranchTargetOpValue";
348 let OperandType = "OPERAND_PCREL";
351 def blx_target : Operand<i32> {
352 // Encoded the same as branch targets.
353 let EncoderMethod = "getARMBLXTargetOpValue";
354 let OperandType = "OPERAND_PCREL";
357 // A list of registers separated by comma. Used by load/store multiple.
358 def RegListAsmOperand : AsmOperandClass { let Name = "RegList"; }
359 def reglist : Operand<i32> {
360 let EncoderMethod = "getRegisterListOpValue";
361 let ParserMatchClass = RegListAsmOperand;
362 let PrintMethod = "printRegisterList";
363 let DecoderMethod = "DecodeRegListOperand";
366 def DPRRegListAsmOperand : AsmOperandClass { let Name = "DPRRegList"; }
367 def dpr_reglist : Operand<i32> {
368 let EncoderMethod = "getRegisterListOpValue";
369 let ParserMatchClass = DPRRegListAsmOperand;
370 let PrintMethod = "printRegisterList";
371 let DecoderMethod = "DecodeDPRRegListOperand";
374 def SPRRegListAsmOperand : AsmOperandClass { let Name = "SPRRegList"; }
375 def spr_reglist : Operand<i32> {
376 let EncoderMethod = "getRegisterListOpValue";
377 let ParserMatchClass = SPRRegListAsmOperand;
378 let PrintMethod = "printRegisterList";
379 let DecoderMethod = "DecodeSPRRegListOperand";
382 // An operand for the CONSTPOOL_ENTRY pseudo-instruction.
383 def cpinst_operand : Operand<i32> {
384 let PrintMethod = "printCPInstOperand";
388 def pclabel : Operand<i32> {
389 let PrintMethod = "printPCLabel";
392 // ADR instruction labels.
393 def adrlabel : Operand<i32> {
394 let EncoderMethod = "getAdrLabelOpValue";
397 def neon_vcvt_imm32 : Operand<i32> {
398 let EncoderMethod = "getNEONVcvtImm32OpValue";
399 let DecoderMethod = "DecodeVCVTImmOperand";
402 // rot_imm: An integer that encodes a rotate amount. Must be 8, 16, or 24.
403 def rot_imm_XFORM: SDNodeXForm<imm, [{
404 switch (N->getZExtValue()){
406 case 0: return CurDAG->getTargetConstant(0, MVT::i32);
407 case 8: return CurDAG->getTargetConstant(1, MVT::i32);
408 case 16: return CurDAG->getTargetConstant(2, MVT::i32);
409 case 24: return CurDAG->getTargetConstant(3, MVT::i32);
412 def RotImmAsmOperand : AsmOperandClass {
414 let ParserMethod = "parseRotImm";
416 def rot_imm : Operand<i32>, PatLeaf<(i32 imm), [{
417 int32_t v = N->getZExtValue();
418 return v == 8 || v == 16 || v == 24; }],
420 let PrintMethod = "printRotImmOperand";
421 let ParserMatchClass = RotImmAsmOperand;
424 // shift_imm: An integer that encodes a shift amount and the type of shift
425 // (asr or lsl). The 6-bit immediate encodes as:
428 // {4-0} imm5 shift amount.
429 // asr #32 encoded as imm5 == 0.
430 def ShifterImmAsmOperand : AsmOperandClass {
431 let Name = "ShifterImm";
432 let ParserMethod = "parseShifterImm";
434 def shift_imm : Operand<i32> {
435 let PrintMethod = "printShiftImmOperand";
436 let ParserMatchClass = ShifterImmAsmOperand;
439 // shifter_operand operands: so_reg_reg, so_reg_imm, and so_imm.
440 def ShiftedRegAsmOperand : AsmOperandClass { let Name = "RegShiftedReg"; }
441 def so_reg_reg : Operand<i32>, // reg reg imm
442 ComplexPattern<i32, 3, "SelectRegShifterOperand",
443 [shl, srl, sra, rotr]> {
444 let EncoderMethod = "getSORegRegOpValue";
445 let PrintMethod = "printSORegRegOperand";
446 let DecoderMethod = "DecodeSORegRegOperand";
447 let ParserMatchClass = ShiftedRegAsmOperand;
448 let MIOperandInfo = (ops GPRnopc, GPRnopc, i32imm);
451 def ShiftedImmAsmOperand : AsmOperandClass { let Name = "RegShiftedImm"; }
452 def so_reg_imm : Operand<i32>, // reg imm
453 ComplexPattern<i32, 2, "SelectImmShifterOperand",
454 [shl, srl, sra, rotr]> {
455 let EncoderMethod = "getSORegImmOpValue";
456 let PrintMethod = "printSORegImmOperand";
457 let DecoderMethod = "DecodeSORegImmOperand";
458 let ParserMatchClass = ShiftedImmAsmOperand;
459 let MIOperandInfo = (ops GPR, i32imm);
462 // FIXME: Does this need to be distinct from so_reg?
463 def shift_so_reg_reg : Operand<i32>, // reg reg imm
464 ComplexPattern<i32, 3, "SelectShiftRegShifterOperand",
465 [shl,srl,sra,rotr]> {
466 let EncoderMethod = "getSORegRegOpValue";
467 let PrintMethod = "printSORegRegOperand";
468 let DecoderMethod = "DecodeSORegRegOperand";
469 let ParserMatchClass = ShiftedRegAsmOperand;
470 let MIOperandInfo = (ops GPR, GPR, i32imm);
473 // FIXME: Does this need to be distinct from so_reg?
474 def shift_so_reg_imm : Operand<i32>, // reg reg imm
475 ComplexPattern<i32, 2, "SelectShiftImmShifterOperand",
476 [shl,srl,sra,rotr]> {
477 let EncoderMethod = "getSORegImmOpValue";
478 let PrintMethod = "printSORegImmOperand";
479 let DecoderMethod = "DecodeSORegImmOperand";
480 let ParserMatchClass = ShiftedImmAsmOperand;
481 let MIOperandInfo = (ops GPR, i32imm);
485 // so_imm - Match a 32-bit shifter_operand immediate operand, which is an
486 // 8-bit immediate rotated by an arbitrary number of bits.
487 def SOImmAsmOperand: ImmAsmOperand { let Name = "ARMSOImm"; }
488 def so_imm : Operand<i32>, ImmLeaf<i32, [{
489 return ARM_AM::getSOImmVal(Imm) != -1;
491 let EncoderMethod = "getSOImmOpValue";
492 let ParserMatchClass = SOImmAsmOperand;
493 let DecoderMethod = "DecodeSOImmOperand";
496 // Break so_imm's up into two pieces. This handles immediates with up to 16
497 // bits set in them. This uses so_imm2part to match and so_imm2part_[12] to
498 // get the first/second pieces.
499 def so_imm2part : PatLeaf<(imm), [{
500 return ARM_AM::isSOImmTwoPartVal((unsigned)N->getZExtValue());
503 /// arm_i32imm - True for +V6T2, or true only if so_imm2part is true.
505 def arm_i32imm : PatLeaf<(imm), [{
506 if (Subtarget->hasV6T2Ops())
508 return ARM_AM::isSOImmTwoPartVal((unsigned)N->getZExtValue());
511 /// imm0_1 predicate - Immediate in the range [0,1].
512 def Imm0_1AsmOperand: ImmAsmOperand { let Name = "Imm0_1"; }
513 def imm0_1 : Operand<i32> { let ParserMatchClass = Imm0_1AsmOperand; }
515 /// imm0_3 predicate - Immediate in the range [0,3].
516 def Imm0_3AsmOperand: ImmAsmOperand { let Name = "Imm0_3"; }
517 def imm0_3 : Operand<i32> { let ParserMatchClass = Imm0_3AsmOperand; }
519 /// imm0_7 predicate - Immediate in the range [0,7].
520 def Imm0_7AsmOperand: ImmAsmOperand { let Name = "Imm0_7"; }
521 def imm0_7 : Operand<i32>, ImmLeaf<i32, [{
522 return Imm >= 0 && Imm < 8;
524 let ParserMatchClass = Imm0_7AsmOperand;
527 /// imm8 predicate - Immediate is exactly 8.
528 def Imm8AsmOperand: ImmAsmOperand { let Name = "Imm8"; }
529 def imm8 : Operand<i32>, ImmLeaf<i32, [{ return Imm == 8; }]> {
530 let ParserMatchClass = Imm8AsmOperand;
533 /// imm16 predicate - Immediate is exactly 16.
534 def Imm16AsmOperand: ImmAsmOperand { let Name = "Imm16"; }
535 def imm16 : Operand<i32>, ImmLeaf<i32, [{ return Imm == 16; }]> {
536 let ParserMatchClass = Imm16AsmOperand;
539 /// imm32 predicate - Immediate is exactly 32.
540 def Imm32AsmOperand: ImmAsmOperand { let Name = "Imm32"; }
541 def imm32 : Operand<i32>, ImmLeaf<i32, [{ return Imm == 32; }]> {
542 let ParserMatchClass = Imm32AsmOperand;
545 /// imm1_7 predicate - Immediate in the range [1,7].
546 def Imm1_7AsmOperand: ImmAsmOperand { let Name = "Imm1_7"; }
547 def imm1_7 : Operand<i32>, ImmLeaf<i32, [{ return Imm > 0 && Imm < 8; }]> {
548 let ParserMatchClass = Imm1_7AsmOperand;
551 /// imm1_15 predicate - Immediate in the range [1,15].
552 def Imm1_15AsmOperand: ImmAsmOperand { let Name = "Imm1_15"; }
553 def imm1_15 : Operand<i32>, ImmLeaf<i32, [{ return Imm > 0 && Imm < 16; }]> {
554 let ParserMatchClass = Imm1_15AsmOperand;
557 /// imm1_31 predicate - Immediate in the range [1,31].
558 def Imm1_31AsmOperand: ImmAsmOperand { let Name = "Imm1_31"; }
559 def imm1_31 : Operand<i32>, ImmLeaf<i32, [{ return Imm > 0 && Imm < 32; }]> {
560 let ParserMatchClass = Imm1_31AsmOperand;
563 /// imm0_15 predicate - Immediate in the range [0,15].
564 def Imm0_15AsmOperand: ImmAsmOperand { let Name = "Imm0_15"; }
565 def imm0_15 : Operand<i32>, ImmLeaf<i32, [{
566 return Imm >= 0 && Imm < 16;
568 let ParserMatchClass = Imm0_15AsmOperand;
571 /// imm0_31 predicate - True if the 32-bit immediate is in the range [0,31].
572 def Imm0_31AsmOperand: ImmAsmOperand { let Name = "Imm0_31"; }
573 def imm0_31 : Operand<i32>, ImmLeaf<i32, [{
574 return Imm >= 0 && Imm < 32;
576 let ParserMatchClass = Imm0_31AsmOperand;
579 /// imm0_32 predicate - True if the 32-bit immediate is in the range [0,32].
580 def Imm0_32AsmOperand: ImmAsmOperand { let Name = "Imm0_32"; }
581 def imm0_32 : Operand<i32>, ImmLeaf<i32, [{
582 return Imm >= 0 && Imm < 32;
584 let ParserMatchClass = Imm0_32AsmOperand;
587 /// imm0_63 predicate - True if the 32-bit immediate is in the range [0,63].
588 def Imm0_63AsmOperand: ImmAsmOperand { let Name = "Imm0_63"; }
589 def imm0_63 : Operand<i32>, ImmLeaf<i32, [{
590 return Imm >= 0 && Imm < 64;
592 let ParserMatchClass = Imm0_63AsmOperand;
595 /// imm0_255 predicate - Immediate in the range [0,255].
596 def Imm0_255AsmOperand : ImmAsmOperand { let Name = "Imm0_255"; }
597 def imm0_255 : Operand<i32>, ImmLeaf<i32, [{ return Imm >= 0 && Imm < 256; }]> {
598 let ParserMatchClass = Imm0_255AsmOperand;
601 /// imm0_65535 - An immediate is in the range [0.65535].
602 def Imm0_65535AsmOperand: ImmAsmOperand { let Name = "Imm0_65535"; }
603 def imm0_65535 : Operand<i32>, ImmLeaf<i32, [{
604 return Imm >= 0 && Imm < 65536;
606 let ParserMatchClass = Imm0_65535AsmOperand;
609 // imm0_65535_expr - For movt/movw - 16-bit immediate that can also reference
610 // a relocatable expression.
612 // FIXME: This really needs a Thumb version separate from the ARM version.
613 // While the range is the same, and can thus use the same match class,
614 // the encoding is different so it should have a different encoder method.
615 def Imm0_65535ExprAsmOperand: ImmAsmOperand { let Name = "Imm0_65535Expr"; }
616 def imm0_65535_expr : Operand<i32> {
617 let EncoderMethod = "getHiLo16ImmOpValue";
618 let ParserMatchClass = Imm0_65535ExprAsmOperand;
621 /// imm24b - True if the 32-bit immediate is encodable in 24 bits.
622 def Imm24bitAsmOperand: ImmAsmOperand { let Name = "Imm24bit"; }
623 def imm24b : Operand<i32>, ImmLeaf<i32, [{
624 return Imm >= 0 && Imm <= 0xffffff;
626 let ParserMatchClass = Imm24bitAsmOperand;
630 /// bf_inv_mask_imm predicate - An AND mask to clear an arbitrary width bitfield
632 def BitfieldAsmOperand : AsmOperandClass {
633 let Name = "Bitfield";
634 let ParserMethod = "parseBitfield";
636 def bf_inv_mask_imm : Operand<i32>,
638 return ARM::isBitFieldInvertedMask(N->getZExtValue());
640 let EncoderMethod = "getBitfieldInvertedMaskOpValue";
641 let PrintMethod = "printBitfieldInvMaskImmOperand";
642 let DecoderMethod = "DecodeBitfieldMaskOperand";
643 let ParserMatchClass = BitfieldAsmOperand;
646 def imm1_32_XFORM: SDNodeXForm<imm, [{
647 return CurDAG->getTargetConstant((int)N->getZExtValue() - 1, MVT::i32);
649 def Imm1_32AsmOperand: AsmOperandClass { let Name = "Imm1_32"; }
650 def imm1_32 : Operand<i32>, PatLeaf<(imm), [{
651 uint64_t Imm = N->getZExtValue();
652 return Imm > 0 && Imm <= 32;
655 let PrintMethod = "printImmPlusOneOperand";
656 let ParserMatchClass = Imm1_32AsmOperand;
659 def imm1_16_XFORM: SDNodeXForm<imm, [{
660 return CurDAG->getTargetConstant((int)N->getZExtValue() - 1, MVT::i32);
662 def Imm1_16AsmOperand: AsmOperandClass { let Name = "Imm1_16"; }
663 def imm1_16 : Operand<i32>, PatLeaf<(imm), [{ return Imm > 0 && Imm <= 16; }],
665 let PrintMethod = "printImmPlusOneOperand";
666 let ParserMatchClass = Imm1_16AsmOperand;
669 // Define ARM specific addressing modes.
670 // addrmode_imm12 := reg +/- imm12
672 def MemImm12OffsetAsmOperand : AsmOperandClass { let Name = "MemImm12Offset"; }
673 def addrmode_imm12 : Operand<i32>,
674 ComplexPattern<i32, 2, "SelectAddrModeImm12", []> {
675 // 12-bit immediate operand. Note that instructions using this encode
676 // #0 and #-0 differently. We flag #-0 as the magic value INT32_MIN. All other
677 // immediate values are as normal.
679 let EncoderMethod = "getAddrModeImm12OpValue";
680 let PrintMethod = "printAddrModeImm12Operand";
681 let DecoderMethod = "DecodeAddrModeImm12Operand";
682 let ParserMatchClass = MemImm12OffsetAsmOperand;
683 let MIOperandInfo = (ops GPR:$base, i32imm:$offsimm);
685 // ldst_so_reg := reg +/- reg shop imm
687 def MemRegOffsetAsmOperand : AsmOperandClass { let Name = "MemRegOffset"; }
688 def ldst_so_reg : Operand<i32>,
689 ComplexPattern<i32, 3, "SelectLdStSOReg", []> {
690 let EncoderMethod = "getLdStSORegOpValue";
691 // FIXME: Simplify the printer
692 let PrintMethod = "printAddrMode2Operand";
693 let DecoderMethod = "DecodeSORegMemOperand";
694 let ParserMatchClass = MemRegOffsetAsmOperand;
695 let MIOperandInfo = (ops GPR:$base, GPRnopc:$offsreg, i32imm:$shift);
698 // postidx_imm8 := +/- [0,255]
701 // {8} 1 is imm8 is non-negative. 0 otherwise.
702 // {7-0} [0,255] imm8 value.
703 def PostIdxImm8AsmOperand : AsmOperandClass { let Name = "PostIdxImm8"; }
704 def postidx_imm8 : Operand<i32> {
705 let PrintMethod = "printPostIdxImm8Operand";
706 let ParserMatchClass = PostIdxImm8AsmOperand;
707 let MIOperandInfo = (ops i32imm);
710 // postidx_imm8s4 := +/- [0,1020]
713 // {8} 1 is imm8 is non-negative. 0 otherwise.
714 // {7-0} [0,255] imm8 value, scaled by 4.
715 def PostIdxImm8s4AsmOperand : AsmOperandClass { let Name = "PostIdxImm8s4"; }
716 def postidx_imm8s4 : Operand<i32> {
717 let PrintMethod = "printPostIdxImm8s4Operand";
718 let ParserMatchClass = PostIdxImm8s4AsmOperand;
719 let MIOperandInfo = (ops i32imm);
723 // postidx_reg := +/- reg
725 def PostIdxRegAsmOperand : AsmOperandClass {
726 let Name = "PostIdxReg";
727 let ParserMethod = "parsePostIdxReg";
729 def postidx_reg : Operand<i32> {
730 let EncoderMethod = "getPostIdxRegOpValue";
731 let DecoderMethod = "DecodePostIdxReg";
732 let PrintMethod = "printPostIdxRegOperand";
733 let ParserMatchClass = PostIdxRegAsmOperand;
734 let MIOperandInfo = (ops GPR, i32imm);
738 // addrmode2 := reg +/- imm12
739 // := reg +/- reg shop imm
741 // FIXME: addrmode2 should be refactored the rest of the way to always
742 // use explicit imm vs. reg versions above (addrmode_imm12 and ldst_so_reg).
743 def AddrMode2AsmOperand : AsmOperandClass { let Name = "AddrMode2"; }
744 def addrmode2 : Operand<i32>,
745 ComplexPattern<i32, 3, "SelectAddrMode2", []> {
746 let EncoderMethod = "getAddrMode2OpValue";
747 let PrintMethod = "printAddrMode2Operand";
748 let ParserMatchClass = AddrMode2AsmOperand;
749 let MIOperandInfo = (ops GPR:$base, GPR:$offsreg, i32imm:$offsimm);
752 def PostIdxRegShiftedAsmOperand : AsmOperandClass {
753 let Name = "PostIdxRegShifted";
754 let ParserMethod = "parsePostIdxReg";
756 def am2offset_reg : Operand<i32>,
757 ComplexPattern<i32, 2, "SelectAddrMode2OffsetReg",
758 [], [SDNPWantRoot]> {
759 let EncoderMethod = "getAddrMode2OffsetOpValue";
760 let PrintMethod = "printAddrMode2OffsetOperand";
761 // When using this for assembly, it's always as a post-index offset.
762 let ParserMatchClass = PostIdxRegShiftedAsmOperand;
763 let MIOperandInfo = (ops GPR, i32imm);
766 // FIXME: am2offset_imm should only need the immediate, not the GPR. Having
767 // the GPR is purely vestigal at this point.
768 def AM2OffsetImmAsmOperand : AsmOperandClass { let Name = "AM2OffsetImm"; }
769 def am2offset_imm : Operand<i32>,
770 ComplexPattern<i32, 2, "SelectAddrMode2OffsetImm",
771 [], [SDNPWantRoot]> {
772 let EncoderMethod = "getAddrMode2OffsetOpValue";
773 let PrintMethod = "printAddrMode2OffsetOperand";
774 let ParserMatchClass = AM2OffsetImmAsmOperand;
775 let MIOperandInfo = (ops GPR, i32imm);
779 // addrmode3 := reg +/- reg
780 // addrmode3 := reg +/- imm8
782 // FIXME: split into imm vs. reg versions.
783 def AddrMode3AsmOperand : AsmOperandClass { let Name = "AddrMode3"; }
784 def addrmode3 : Operand<i32>,
785 ComplexPattern<i32, 3, "SelectAddrMode3", []> {
786 let EncoderMethod = "getAddrMode3OpValue";
787 let PrintMethod = "printAddrMode3Operand";
788 let ParserMatchClass = AddrMode3AsmOperand;
789 let MIOperandInfo = (ops GPR:$base, GPR:$offsreg, i32imm:$offsimm);
792 // FIXME: split into imm vs. reg versions.
793 // FIXME: parser method to handle +/- register.
794 def AM3OffsetAsmOperand : AsmOperandClass {
795 let Name = "AM3Offset";
796 let ParserMethod = "parseAM3Offset";
798 def am3offset : Operand<i32>,
799 ComplexPattern<i32, 2, "SelectAddrMode3Offset",
800 [], [SDNPWantRoot]> {
801 let EncoderMethod = "getAddrMode3OffsetOpValue";
802 let PrintMethod = "printAddrMode3OffsetOperand";
803 let ParserMatchClass = AM3OffsetAsmOperand;
804 let MIOperandInfo = (ops GPR, i32imm);
807 // ldstm_mode := {ia, ib, da, db}
809 def ldstm_mode : OptionalDefOperand<OtherVT, (ops i32), (ops (i32 1))> {
810 let EncoderMethod = "getLdStmModeOpValue";
811 let PrintMethod = "printLdStmModeOperand";
814 // addrmode5 := reg +/- imm8*4
816 def AddrMode5AsmOperand : AsmOperandClass { let Name = "AddrMode5"; }
817 def addrmode5 : Operand<i32>,
818 ComplexPattern<i32, 2, "SelectAddrMode5", []> {
819 let PrintMethod = "printAddrMode5Operand";
820 let EncoderMethod = "getAddrMode5OpValue";
821 let DecoderMethod = "DecodeAddrMode5Operand";
822 let ParserMatchClass = AddrMode5AsmOperand;
823 let MIOperandInfo = (ops GPR:$base, i32imm);
826 // addrmode6 := reg with optional alignment
828 def AddrMode6AsmOperand : AsmOperandClass { let Name = "AlignedMemory"; }
829 def addrmode6 : Operand<i32>,
830 ComplexPattern<i32, 2, "SelectAddrMode6", [], [SDNPWantParent]>{
831 let PrintMethod = "printAddrMode6Operand";
832 let MIOperandInfo = (ops GPR:$addr, i32imm:$align);
833 let EncoderMethod = "getAddrMode6AddressOpValue";
834 let DecoderMethod = "DecodeAddrMode6Operand";
835 let ParserMatchClass = AddrMode6AsmOperand;
838 def am6offset : Operand<i32>,
839 ComplexPattern<i32, 1, "SelectAddrMode6Offset",
840 [], [SDNPWantRoot]> {
841 let PrintMethod = "printAddrMode6OffsetOperand";
842 let MIOperandInfo = (ops GPR);
843 let EncoderMethod = "getAddrMode6OffsetOpValue";
844 let DecoderMethod = "DecodeGPRRegisterClass";
847 // Special version of addrmode6 to handle alignment encoding for VST1/VLD1
848 // (single element from one lane) for size 32.
849 def addrmode6oneL32 : Operand<i32>,
850 ComplexPattern<i32, 2, "SelectAddrMode6", [], [SDNPWantParent]>{
851 let PrintMethod = "printAddrMode6Operand";
852 let MIOperandInfo = (ops GPR:$addr, i32imm);
853 let EncoderMethod = "getAddrMode6OneLane32AddressOpValue";
856 // Special version of addrmode6 to handle alignment encoding for VLD-dup
857 // instructions, specifically VLD4-dup.
858 def addrmode6dup : Operand<i32>,
859 ComplexPattern<i32, 2, "SelectAddrMode6", [], [SDNPWantParent]>{
860 let PrintMethod = "printAddrMode6Operand";
861 let MIOperandInfo = (ops GPR:$addr, i32imm);
862 let EncoderMethod = "getAddrMode6DupAddressOpValue";
863 // FIXME: This is close, but not quite right. The alignment specifier is
865 let ParserMatchClass = AddrMode6AsmOperand;
868 // addrmodepc := pc + reg
870 def addrmodepc : Operand<i32>,
871 ComplexPattern<i32, 2, "SelectAddrModePC", []> {
872 let PrintMethod = "printAddrModePCOperand";
873 let MIOperandInfo = (ops GPR, i32imm);
876 // addr_offset_none := reg
878 def MemNoOffsetAsmOperand : AsmOperandClass { let Name = "MemNoOffset"; }
879 def addr_offset_none : Operand<i32>,
880 ComplexPattern<i32, 1, "SelectAddrOffsetNone", []> {
881 let PrintMethod = "printAddrMode7Operand";
882 let DecoderMethod = "DecodeAddrMode7Operand";
883 let ParserMatchClass = MemNoOffsetAsmOperand;
884 let MIOperandInfo = (ops GPR:$base);
887 def nohash_imm : Operand<i32> {
888 let PrintMethod = "printNoHashImmediate";
891 def CoprocNumAsmOperand : AsmOperandClass {
892 let Name = "CoprocNum";
893 let ParserMethod = "parseCoprocNumOperand";
895 def p_imm : Operand<i32> {
896 let PrintMethod = "printPImmediate";
897 let ParserMatchClass = CoprocNumAsmOperand;
898 let DecoderMethod = "DecodeCoprocessor";
901 def CoprocRegAsmOperand : AsmOperandClass {
902 let Name = "CoprocReg";
903 let ParserMethod = "parseCoprocRegOperand";
905 def c_imm : Operand<i32> {
906 let PrintMethod = "printCImmediate";
907 let ParserMatchClass = CoprocRegAsmOperand;
909 def CoprocOptionAsmOperand : AsmOperandClass {
910 let Name = "CoprocOption";
911 let ParserMethod = "parseCoprocOptionOperand";
913 def coproc_option_imm : Operand<i32> {
914 let PrintMethod = "printCoprocOptionImm";
915 let ParserMatchClass = CoprocOptionAsmOperand;
918 //===----------------------------------------------------------------------===//
920 include "ARMInstrFormats.td"
922 //===----------------------------------------------------------------------===//
923 // Multiclass helpers...
926 /// AsI1_bin_irs - Defines a set of (op r, {so_imm|r|so_reg}) patterns for a
927 /// binop that produces a value.
928 multiclass AsI1_bin_irs<bits<4> opcod, string opc,
929 InstrItinClass iii, InstrItinClass iir, InstrItinClass iis,
930 PatFrag opnode, string baseOpc, bit Commutable = 0> {
931 // The register-immediate version is re-materializable. This is useful
932 // in particular for taking the address of a local.
933 let isReMaterializable = 1 in {
934 def ri : AsI1<opcod, (outs GPR:$Rd), (ins GPR:$Rn, so_imm:$imm), DPFrm,
935 iii, opc, "\t$Rd, $Rn, $imm",
936 [(set GPR:$Rd, (opnode GPR:$Rn, so_imm:$imm))]> {
941 let Inst{19-16} = Rn;
942 let Inst{15-12} = Rd;
943 let Inst{11-0} = imm;
946 def rr : AsI1<opcod, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm), DPFrm,
947 iir, opc, "\t$Rd, $Rn, $Rm",
948 [(set GPR:$Rd, (opnode GPR:$Rn, GPR:$Rm))]> {
953 let isCommutable = Commutable;
954 let Inst{19-16} = Rn;
955 let Inst{15-12} = Rd;
956 let Inst{11-4} = 0b00000000;
960 def rsi : AsI1<opcod, (outs GPR:$Rd),
961 (ins GPR:$Rn, so_reg_imm:$shift), DPSoRegImmFrm,
962 iis, opc, "\t$Rd, $Rn, $shift",
963 [(set GPR:$Rd, (opnode GPR:$Rn, so_reg_imm:$shift))]> {
968 let Inst{19-16} = Rn;
969 let Inst{15-12} = Rd;
970 let Inst{11-5} = shift{11-5};
972 let Inst{3-0} = shift{3-0};
975 def rsr : AsI1<opcod, (outs GPR:$Rd),
976 (ins GPR:$Rn, so_reg_reg:$shift), DPSoRegRegFrm,
977 iis, opc, "\t$Rd, $Rn, $shift",
978 [(set GPR:$Rd, (opnode GPR:$Rn, so_reg_reg:$shift))]> {
983 let Inst{19-16} = Rn;
984 let Inst{15-12} = Rd;
985 let Inst{11-8} = shift{11-8};
987 let Inst{6-5} = shift{6-5};
989 let Inst{3-0} = shift{3-0};
992 // Assembly aliases for optional destination operand when it's the same
993 // as the source operand.
994 def : InstAlias<!strconcat(opc, "${s}${p} $Rdn, $imm"),
995 (!cast<Instruction>(!strconcat(baseOpc, "ri")) GPR:$Rdn, GPR:$Rdn,
996 so_imm:$imm, pred:$p,
999 def : InstAlias<!strconcat(opc, "${s}${p} $Rdn, $Rm"),
1000 (!cast<Instruction>(!strconcat(baseOpc, "rr")) GPR:$Rdn, GPR:$Rdn,
1004 def : InstAlias<!strconcat(opc, "${s}${p} $Rdn, $shift"),
1005 (!cast<Instruction>(!strconcat(baseOpc, "rsi")) GPR:$Rdn, GPR:$Rdn,
1006 so_reg_imm:$shift, pred:$p,
1009 def : InstAlias<!strconcat(opc, "${s}${p} $Rdn, $shift"),
1010 (!cast<Instruction>(!strconcat(baseOpc, "rsr")) GPR:$Rdn, GPR:$Rdn,
1011 so_reg_reg:$shift, pred:$p,
1017 /// AsI1_rbin_irs - Same as AsI1_bin_irs except the order of operands are
1018 /// reversed. The 'rr' form is only defined for the disassembler; for codegen
1019 /// it is equivalent to the AsI1_bin_irs counterpart.
1020 multiclass AsI1_rbin_irs<bits<4> opcod, string opc,
1021 InstrItinClass iii, InstrItinClass iir, InstrItinClass iis,
1022 PatFrag opnode, string baseOpc, bit Commutable = 0> {
1023 // The register-immediate version is re-materializable. This is useful
1024 // in particular for taking the address of a local.
1025 let isReMaterializable = 1 in {
1026 def ri : AsI1<opcod, (outs GPR:$Rd), (ins GPR:$Rn, so_imm:$imm), DPFrm,
1027 iii, opc, "\t$Rd, $Rn, $imm",
1028 [(set GPR:$Rd, (opnode so_imm:$imm, GPR:$Rn))]> {
1033 let Inst{19-16} = Rn;
1034 let Inst{15-12} = Rd;
1035 let Inst{11-0} = imm;
1038 def rr : AsI1<opcod, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm), DPFrm,
1039 iir, opc, "\t$Rd, $Rn, $Rm",
1040 [/* pattern left blank */]> {
1044 let Inst{11-4} = 0b00000000;
1047 let Inst{15-12} = Rd;
1048 let Inst{19-16} = Rn;
1051 def rsi : AsI1<opcod, (outs GPR:$Rd),
1052 (ins GPR:$Rn, so_reg_imm:$shift), DPSoRegImmFrm,
1053 iis, opc, "\t$Rd, $Rn, $shift",
1054 [(set GPR:$Rd, (opnode so_reg_imm:$shift, GPR:$Rn))]> {
1059 let Inst{19-16} = Rn;
1060 let Inst{15-12} = Rd;
1061 let Inst{11-5} = shift{11-5};
1063 let Inst{3-0} = shift{3-0};
1066 def rsr : AsI1<opcod, (outs GPR:$Rd),
1067 (ins GPR:$Rn, so_reg_reg:$shift), DPSoRegRegFrm,
1068 iis, opc, "\t$Rd, $Rn, $shift",
1069 [(set GPR:$Rd, (opnode so_reg_reg:$shift, GPR:$Rn))]> {
1074 let Inst{19-16} = Rn;
1075 let Inst{15-12} = Rd;
1076 let Inst{11-8} = shift{11-8};
1078 let Inst{6-5} = shift{6-5};
1080 let Inst{3-0} = shift{3-0};
1083 // Assembly aliases for optional destination operand when it's the same
1084 // as the source operand.
1085 def : InstAlias<!strconcat(opc, "${s}${p} $Rdn, $imm"),
1086 (!cast<Instruction>(!strconcat(baseOpc, "ri")) GPR:$Rdn, GPR:$Rdn,
1087 so_imm:$imm, pred:$p,
1090 def : InstAlias<!strconcat(opc, "${s}${p} $Rdn, $Rm"),
1091 (!cast<Instruction>(!strconcat(baseOpc, "rr")) GPR:$Rdn, GPR:$Rdn,
1095 def : InstAlias<!strconcat(opc, "${s}${p} $Rdn, $shift"),
1096 (!cast<Instruction>(!strconcat(baseOpc, "rsi")) GPR:$Rdn, GPR:$Rdn,
1097 so_reg_imm:$shift, pred:$p,
1100 def : InstAlias<!strconcat(opc, "${s}${p} $Rdn, $shift"),
1101 (!cast<Instruction>(!strconcat(baseOpc, "rsr")) GPR:$Rdn, GPR:$Rdn,
1102 so_reg_reg:$shift, pred:$p,
1108 /// AsI1_bin_s_irs - Same as AsI1_bin_irs except it sets the 's' bit by default.
1110 /// These opcodes will be converted to the real non-S opcodes by
1111 /// AdjustInstrPostInstrSelection after giving them an optional CPSR operand.
1112 let hasPostISelHook = 1, Defs = [CPSR] in {
1113 multiclass AsI1_bin_s_irs<InstrItinClass iii, InstrItinClass iir,
1114 InstrItinClass iis, PatFrag opnode,
1115 bit Commutable = 0> {
1116 def ri : ARMPseudoInst<(outs GPR:$Rd), (ins GPR:$Rn, so_imm:$imm, pred:$p),
1118 [(set GPR:$Rd, CPSR, (opnode GPR:$Rn, so_imm:$imm))]>;
1120 def rr : ARMPseudoInst<(outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm, pred:$p),
1122 [(set GPR:$Rd, CPSR, (opnode GPR:$Rn, GPR:$Rm))]> {
1123 let isCommutable = Commutable;
1125 def rsi : ARMPseudoInst<(outs GPR:$Rd),
1126 (ins GPR:$Rn, so_reg_imm:$shift, pred:$p),
1128 [(set GPR:$Rd, CPSR, (opnode GPR:$Rn,
1129 so_reg_imm:$shift))]>;
1131 def rsr : ARMPseudoInst<(outs GPR:$Rd),
1132 (ins GPR:$Rn, so_reg_reg:$shift, pred:$p),
1134 [(set GPR:$Rd, CPSR, (opnode GPR:$Rn,
1135 so_reg_reg:$shift))]>;
1139 /// AsI1_rbin_s_is - Same as AsI1_bin_s_irs, except selection DAG
1140 /// operands are reversed.
1141 let hasPostISelHook = 1, Defs = [CPSR] in {
1142 multiclass AsI1_rbin_s_is<InstrItinClass iii, InstrItinClass iir,
1143 InstrItinClass iis, PatFrag opnode,
1144 bit Commutable = 0> {
1145 def ri : ARMPseudoInst<(outs GPR:$Rd), (ins GPR:$Rn, so_imm:$imm, pred:$p),
1147 [(set GPR:$Rd, CPSR, (opnode so_imm:$imm, GPR:$Rn))]>;
1149 def rsi : ARMPseudoInst<(outs GPR:$Rd),
1150 (ins GPR:$Rn, so_reg_imm:$shift, pred:$p),
1152 [(set GPR:$Rd, CPSR, (opnode so_reg_imm:$shift,
1155 def rsr : ARMPseudoInst<(outs GPR:$Rd),
1156 (ins GPR:$Rn, so_reg_reg:$shift, pred:$p),
1158 [(set GPR:$Rd, CPSR, (opnode so_reg_reg:$shift,
1163 /// AI1_cmp_irs - Defines a set of (op r, {so_imm|r|so_reg}) cmp / test
1164 /// patterns. Similar to AsI1_bin_irs except the instruction does not produce
1165 /// a explicit result, only implicitly set CPSR.
1166 let isCompare = 1, Defs = [CPSR] in {
1167 multiclass AI1_cmp_irs<bits<4> opcod, string opc,
1168 InstrItinClass iii, InstrItinClass iir, InstrItinClass iis,
1169 PatFrag opnode, bit Commutable = 0> {
1170 def ri : AI1<opcod, (outs), (ins GPR:$Rn, so_imm:$imm), DPFrm, iii,
1172 [(opnode GPR:$Rn, so_imm:$imm)]> {
1177 let Inst{19-16} = Rn;
1178 let Inst{15-12} = 0b0000;
1179 let Inst{11-0} = imm;
1181 def rr : AI1<opcod, (outs), (ins GPR:$Rn, GPR:$Rm), DPFrm, iir,
1183 [(opnode GPR:$Rn, GPR:$Rm)]> {
1186 let isCommutable = Commutable;
1189 let Inst{19-16} = Rn;
1190 let Inst{15-12} = 0b0000;
1191 let Inst{11-4} = 0b00000000;
1194 def rsi : AI1<opcod, (outs),
1195 (ins GPR:$Rn, so_reg_imm:$shift), DPSoRegImmFrm, iis,
1196 opc, "\t$Rn, $shift",
1197 [(opnode GPR:$Rn, so_reg_imm:$shift)]> {
1202 let Inst{19-16} = Rn;
1203 let Inst{15-12} = 0b0000;
1204 let Inst{11-5} = shift{11-5};
1206 let Inst{3-0} = shift{3-0};
1208 def rsr : AI1<opcod, (outs),
1209 (ins GPR:$Rn, so_reg_reg:$shift), DPSoRegRegFrm, iis,
1210 opc, "\t$Rn, $shift",
1211 [(opnode GPR:$Rn, so_reg_reg:$shift)]> {
1216 let Inst{19-16} = Rn;
1217 let Inst{15-12} = 0b0000;
1218 let Inst{11-8} = shift{11-8};
1220 let Inst{6-5} = shift{6-5};
1222 let Inst{3-0} = shift{3-0};
1228 /// AI_ext_rrot - A unary operation with two forms: one whose operand is a
1229 /// register and one whose operand is a register rotated by 8/16/24.
1230 /// FIXME: Remove the 'r' variant. Its rot_imm is zero.
1231 class AI_ext_rrot<bits<8> opcod, string opc, PatFrag opnode>
1232 : AExtI<opcod, (outs GPRnopc:$Rd), (ins GPRnopc:$Rm, rot_imm:$rot),
1233 IIC_iEXTr, opc, "\t$Rd, $Rm$rot",
1234 [(set GPRnopc:$Rd, (opnode (rotr GPRnopc:$Rm, rot_imm:$rot)))]>,
1235 Requires<[IsARM, HasV6]> {
1239 let Inst{19-16} = 0b1111;
1240 let Inst{15-12} = Rd;
1241 let Inst{11-10} = rot;
1245 class AI_ext_rrot_np<bits<8> opcod, string opc>
1246 : AExtI<opcod, (outs GPRnopc:$Rd), (ins GPRnopc:$Rm, rot_imm:$rot),
1247 IIC_iEXTr, opc, "\t$Rd, $Rm$rot", []>,
1248 Requires<[IsARM, HasV6]> {
1250 let Inst{19-16} = 0b1111;
1251 let Inst{11-10} = rot;
1254 /// AI_exta_rrot - A binary operation with two forms: one whose operand is a
1255 /// register and one whose operand is a register rotated by 8/16/24.
1256 class AI_exta_rrot<bits<8> opcod, string opc, PatFrag opnode>
1257 : AExtI<opcod, (outs GPRnopc:$Rd), (ins GPR:$Rn, GPRnopc:$Rm, rot_imm:$rot),
1258 IIC_iEXTAr, opc, "\t$Rd, $Rn, $Rm$rot",
1259 [(set GPRnopc:$Rd, (opnode GPR:$Rn,
1260 (rotr GPRnopc:$Rm, rot_imm:$rot)))]>,
1261 Requires<[IsARM, HasV6]> {
1266 let Inst{19-16} = Rn;
1267 let Inst{15-12} = Rd;
1268 let Inst{11-10} = rot;
1269 let Inst{9-4} = 0b000111;
1273 class AI_exta_rrot_np<bits<8> opcod, string opc>
1274 : AExtI<opcod, (outs GPRnopc:$Rd), (ins GPR:$Rn, GPRnopc:$Rm, rot_imm:$rot),
1275 IIC_iEXTAr, opc, "\t$Rd, $Rn, $Rm$rot", []>,
1276 Requires<[IsARM, HasV6]> {
1279 let Inst{19-16} = Rn;
1280 let Inst{11-10} = rot;
1283 /// AI1_adde_sube_irs - Define instructions and patterns for adde and sube.
1284 multiclass AI1_adde_sube_irs<bits<4> opcod, string opc, PatFrag opnode,
1285 string baseOpc, bit Commutable = 0> {
1286 let hasPostISelHook = 1, Defs = [CPSR], Uses = [CPSR] in {
1287 def ri : AsI1<opcod, (outs GPR:$Rd), (ins GPR:$Rn, so_imm:$imm),
1288 DPFrm, IIC_iALUi, opc, "\t$Rd, $Rn, $imm",
1289 [(set GPR:$Rd, CPSR, (opnode GPR:$Rn, so_imm:$imm, CPSR))]>,
1295 let Inst{15-12} = Rd;
1296 let Inst{19-16} = Rn;
1297 let Inst{11-0} = imm;
1299 def rr : AsI1<opcod, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm),
1300 DPFrm, IIC_iALUr, opc, "\t$Rd, $Rn, $Rm",
1301 [(set GPR:$Rd, CPSR, (opnode GPR:$Rn, GPR:$Rm, CPSR))]>,
1306 let Inst{11-4} = 0b00000000;
1308 let isCommutable = Commutable;
1310 let Inst{15-12} = Rd;
1311 let Inst{19-16} = Rn;
1313 def rsi : AsI1<opcod, (outs GPR:$Rd),
1314 (ins GPR:$Rn, so_reg_imm:$shift),
1315 DPSoRegImmFrm, IIC_iALUsr, opc, "\t$Rd, $Rn, $shift",
1316 [(set GPR:$Rd, CPSR, (opnode GPR:$Rn, so_reg_imm:$shift, CPSR))]>,
1322 let Inst{19-16} = Rn;
1323 let Inst{15-12} = Rd;
1324 let Inst{11-5} = shift{11-5};
1326 let Inst{3-0} = shift{3-0};
1328 def rsr : AsI1<opcod, (outs GPR:$Rd),
1329 (ins GPR:$Rn, so_reg_reg:$shift),
1330 DPSoRegRegFrm, IIC_iALUsr, opc, "\t$Rd, $Rn, $shift",
1331 [(set GPR:$Rd, CPSR, (opnode GPR:$Rn, so_reg_reg:$shift, CPSR))]>,
1337 let Inst{19-16} = Rn;
1338 let Inst{15-12} = Rd;
1339 let Inst{11-8} = shift{11-8};
1341 let Inst{6-5} = shift{6-5};
1343 let Inst{3-0} = shift{3-0};
1347 // Assembly aliases for optional destination operand when it's the same
1348 // as the source operand.
1349 def : InstAlias<!strconcat(opc, "${s}${p} $Rdn, $imm"),
1350 (!cast<Instruction>(!strconcat(baseOpc, "ri")) GPR:$Rdn, GPR:$Rdn,
1351 so_imm:$imm, pred:$p,
1354 def : InstAlias<!strconcat(opc, "${s}${p} $Rdn, $Rm"),
1355 (!cast<Instruction>(!strconcat(baseOpc, "rr")) GPR:$Rdn, GPR:$Rdn,
1359 def : InstAlias<!strconcat(opc, "${s}${p} $Rdn, $shift"),
1360 (!cast<Instruction>(!strconcat(baseOpc, "rsi")) GPR:$Rdn, GPR:$Rdn,
1361 so_reg_imm:$shift, pred:$p,
1364 def : InstAlias<!strconcat(opc, "${s}${p} $Rdn, $shift"),
1365 (!cast<Instruction>(!strconcat(baseOpc, "rsr")) GPR:$Rdn, GPR:$Rdn,
1366 so_reg_reg:$shift, pred:$p,
1371 /// AI1_rsc_irs - Define instructions and patterns for rsc
1372 multiclass AI1_rsc_irs<bits<4> opcod, string opc, PatFrag opnode,
1374 let hasPostISelHook = 1, Defs = [CPSR], Uses = [CPSR] in {
1375 def ri : AsI1<opcod, (outs GPR:$Rd), (ins GPR:$Rn, so_imm:$imm),
1376 DPFrm, IIC_iALUi, opc, "\t$Rd, $Rn, $imm",
1377 [(set GPR:$Rd, CPSR, (opnode so_imm:$imm, GPR:$Rn, CPSR))]>,
1383 let Inst{15-12} = Rd;
1384 let Inst{19-16} = Rn;
1385 let Inst{11-0} = imm;
1387 def rr : AsI1<opcod, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm),
1388 DPFrm, IIC_iALUr, opc, "\t$Rd, $Rn, $Rm",
1389 [/* pattern left blank */]> {
1393 let Inst{11-4} = 0b00000000;
1396 let Inst{15-12} = Rd;
1397 let Inst{19-16} = Rn;
1399 def rsi : AsI1<opcod, (outs GPR:$Rd), (ins GPR:$Rn, so_reg_imm:$shift),
1400 DPSoRegImmFrm, IIC_iALUsr, opc, "\t$Rd, $Rn, $shift",
1401 [(set GPR:$Rd, CPSR, (opnode so_reg_imm:$shift, GPR:$Rn, CPSR))]>,
1407 let Inst{19-16} = Rn;
1408 let Inst{15-12} = Rd;
1409 let Inst{11-5} = shift{11-5};
1411 let Inst{3-0} = shift{3-0};
1413 def rsr : AsI1<opcod, (outs GPR:$Rd), (ins GPR:$Rn, so_reg_reg:$shift),
1414 DPSoRegRegFrm, IIC_iALUsr, opc, "\t$Rd, $Rn, $shift",
1415 [(set GPR:$Rd, CPSR, (opnode so_reg_reg:$shift, GPR:$Rn, CPSR))]>,
1421 let Inst{19-16} = Rn;
1422 let Inst{15-12} = Rd;
1423 let Inst{11-8} = shift{11-8};
1425 let Inst{6-5} = shift{6-5};
1427 let Inst{3-0} = shift{3-0};
1431 // Assembly aliases for optional destination operand when it's the same
1432 // as the source operand.
1433 def : InstAlias<!strconcat(opc, "${s}${p} $Rdn, $imm"),
1434 (!cast<Instruction>(!strconcat(baseOpc, "ri")) GPR:$Rdn, GPR:$Rdn,
1435 so_imm:$imm, pred:$p,
1438 def : InstAlias<!strconcat(opc, "${s}${p} $Rdn, $Rm"),
1439 (!cast<Instruction>(!strconcat(baseOpc, "rr")) GPR:$Rdn, GPR:$Rdn,
1443 def : InstAlias<!strconcat(opc, "${s}${p} $Rdn, $shift"),
1444 (!cast<Instruction>(!strconcat(baseOpc, "rsi")) GPR:$Rdn, GPR:$Rdn,
1445 so_reg_imm:$shift, pred:$p,
1448 def : InstAlias<!strconcat(opc, "${s}${p} $Rdn, $shift"),
1449 (!cast<Instruction>(!strconcat(baseOpc, "rsr")) GPR:$Rdn, GPR:$Rdn,
1450 so_reg_reg:$shift, pred:$p,
1455 let canFoldAsLoad = 1, isReMaterializable = 1 in {
1456 multiclass AI_ldr1<bit isByte, string opc, InstrItinClass iii,
1457 InstrItinClass iir, PatFrag opnode> {
1458 // Note: We use the complex addrmode_imm12 rather than just an input
1459 // GPR and a constrained immediate so that we can use this to match
1460 // frame index references and avoid matching constant pool references.
1461 def i12: AI2ldst<0b010, 1, isByte, (outs GPR:$Rt), (ins addrmode_imm12:$addr),
1462 AddrMode_i12, LdFrm, iii, opc, "\t$Rt, $addr",
1463 [(set GPR:$Rt, (opnode addrmode_imm12:$addr))]> {
1466 let Inst{23} = addr{12}; // U (add = ('U' == 1))
1467 let Inst{19-16} = addr{16-13}; // Rn
1468 let Inst{15-12} = Rt;
1469 let Inst{11-0} = addr{11-0}; // imm12
1471 def rs : AI2ldst<0b011, 1, isByte, (outs GPR:$Rt), (ins ldst_so_reg:$shift),
1472 AddrModeNone, LdFrm, iir, opc, "\t$Rt, $shift",
1473 [(set GPR:$Rt, (opnode ldst_so_reg:$shift))]> {
1476 let shift{4} = 0; // Inst{4} = 0
1477 let Inst{23} = shift{12}; // U (add = ('U' == 1))
1478 let Inst{19-16} = shift{16-13}; // Rn
1479 let Inst{15-12} = Rt;
1480 let Inst{11-0} = shift{11-0};
1485 let canFoldAsLoad = 1, isReMaterializable = 1 in {
1486 multiclass AI_ldr1nopc<bit isByte, string opc, InstrItinClass iii,
1487 InstrItinClass iir, PatFrag opnode> {
1488 // Note: We use the complex addrmode_imm12 rather than just an input
1489 // GPR and a constrained immediate so that we can use this to match
1490 // frame index references and avoid matching constant pool references.
1491 def i12: AI2ldst<0b010, 1, isByte, (outs GPRnopc:$Rt), (ins addrmode_imm12:$addr),
1492 AddrMode_i12, LdFrm, iii, opc, "\t$Rt, $addr",
1493 [(set GPRnopc:$Rt, (opnode addrmode_imm12:$addr))]> {
1496 let Inst{23} = addr{12}; // U (add = ('U' == 1))
1497 let Inst{19-16} = addr{16-13}; // Rn
1498 let Inst{15-12} = Rt;
1499 let Inst{11-0} = addr{11-0}; // imm12
1501 def rs : AI2ldst<0b011, 1, isByte, (outs GPRnopc:$Rt), (ins ldst_so_reg:$shift),
1502 AddrModeNone, LdFrm, iir, opc, "\t$Rt, $shift",
1503 [(set GPRnopc:$Rt, (opnode ldst_so_reg:$shift))]> {
1506 let shift{4} = 0; // Inst{4} = 0
1507 let Inst{23} = shift{12}; // U (add = ('U' == 1))
1508 let Inst{19-16} = shift{16-13}; // Rn
1509 let Inst{15-12} = Rt;
1510 let Inst{11-0} = shift{11-0};
1516 multiclass AI_str1<bit isByte, string opc, InstrItinClass iii,
1517 InstrItinClass iir, PatFrag opnode> {
1518 // Note: We use the complex addrmode_imm12 rather than just an input
1519 // GPR and a constrained immediate so that we can use this to match
1520 // frame index references and avoid matching constant pool references.
1521 def i12 : AI2ldst<0b010, 0, isByte, (outs),
1522 (ins GPR:$Rt, addrmode_imm12:$addr),
1523 AddrMode_i12, StFrm, iii, opc, "\t$Rt, $addr",
1524 [(opnode GPR:$Rt, addrmode_imm12:$addr)]> {
1527 let Inst{23} = addr{12}; // U (add = ('U' == 1))
1528 let Inst{19-16} = addr{16-13}; // Rn
1529 let Inst{15-12} = Rt;
1530 let Inst{11-0} = addr{11-0}; // imm12
1532 def rs : AI2ldst<0b011, 0, isByte, (outs), (ins GPR:$Rt, ldst_so_reg:$shift),
1533 AddrModeNone, StFrm, iir, opc, "\t$Rt, $shift",
1534 [(opnode GPR:$Rt, ldst_so_reg:$shift)]> {
1537 let shift{4} = 0; // Inst{4} = 0
1538 let Inst{23} = shift{12}; // U (add = ('U' == 1))
1539 let Inst{19-16} = shift{16-13}; // Rn
1540 let Inst{15-12} = Rt;
1541 let Inst{11-0} = shift{11-0};
1545 multiclass AI_str1nopc<bit isByte, string opc, InstrItinClass iii,
1546 InstrItinClass iir, PatFrag opnode> {
1547 // Note: We use the complex addrmode_imm12 rather than just an input
1548 // GPR and a constrained immediate so that we can use this to match
1549 // frame index references and avoid matching constant pool references.
1550 def i12 : AI2ldst<0b010, 0, isByte, (outs),
1551 (ins GPRnopc:$Rt, addrmode_imm12:$addr),
1552 AddrMode_i12, StFrm, iii, opc, "\t$Rt, $addr",
1553 [(opnode GPRnopc:$Rt, addrmode_imm12:$addr)]> {
1556 let Inst{23} = addr{12}; // U (add = ('U' == 1))
1557 let Inst{19-16} = addr{16-13}; // Rn
1558 let Inst{15-12} = Rt;
1559 let Inst{11-0} = addr{11-0}; // imm12
1561 def rs : AI2ldst<0b011, 0, isByte, (outs), (ins GPRnopc:$Rt, ldst_so_reg:$shift),
1562 AddrModeNone, StFrm, iir, opc, "\t$Rt, $shift",
1563 [(opnode GPRnopc:$Rt, ldst_so_reg:$shift)]> {
1566 let shift{4} = 0; // Inst{4} = 0
1567 let Inst{23} = shift{12}; // U (add = ('U' == 1))
1568 let Inst{19-16} = shift{16-13}; // Rn
1569 let Inst{15-12} = Rt;
1570 let Inst{11-0} = shift{11-0};
1575 //===----------------------------------------------------------------------===//
1577 //===----------------------------------------------------------------------===//
1579 //===----------------------------------------------------------------------===//
1580 // Miscellaneous Instructions.
1583 /// CONSTPOOL_ENTRY - This instruction represents a floating constant pool in
1584 /// the function. The first operand is the ID# for this instruction, the second
1585 /// is the index into the MachineConstantPool that this is, the third is the
1586 /// size in bytes of this constant pool entry.
1587 let neverHasSideEffects = 1, isNotDuplicable = 1 in
1588 def CONSTPOOL_ENTRY :
1589 PseudoInst<(outs), (ins cpinst_operand:$instid, cpinst_operand:$cpidx,
1590 i32imm:$size), NoItinerary, []>;
1592 // FIXME: Marking these as hasSideEffects is necessary to prevent machine DCE
1593 // from removing one half of the matched pairs. That breaks PEI, which assumes
1594 // these will always be in pairs, and asserts if it finds otherwise. Better way?
1595 let Defs = [SP], Uses = [SP], hasSideEffects = 1 in {
1596 def ADJCALLSTACKUP :
1597 PseudoInst<(outs), (ins i32imm:$amt1, i32imm:$amt2, pred:$p), NoItinerary,
1598 [(ARMcallseq_end timm:$amt1, timm:$amt2)]>;
1600 def ADJCALLSTACKDOWN :
1601 PseudoInst<(outs), (ins i32imm:$amt, pred:$p), NoItinerary,
1602 [(ARMcallseq_start timm:$amt)]>;
1605 // Atomic pseudo-insts which will be lowered to ldrexd/strexd loops.
1606 // (These pseudos use a hand-written selection code).
1607 let usesCustomInserter = 1, Defs = [CPSR], mayLoad = 1, mayStore = 1 in {
1608 def ATOMOR6432 : PseudoInst<(outs GPR:$dst1, GPR:$dst2),
1609 (ins GPR:$addr, GPR:$src1, GPR:$src2),
1611 def ATOMXOR6432 : PseudoInst<(outs GPR:$dst1, GPR:$dst2),
1612 (ins GPR:$addr, GPR:$src1, GPR:$src2),
1614 def ATOMADD6432 : PseudoInst<(outs GPR:$dst1, GPR:$dst2),
1615 (ins GPR:$addr, GPR:$src1, GPR:$src2),
1617 def ATOMSUB6432 : PseudoInst<(outs GPR:$dst1, GPR:$dst2),
1618 (ins GPR:$addr, GPR:$src1, GPR:$src2),
1620 def ATOMNAND6432 : PseudoInst<(outs GPR:$dst1, GPR:$dst2),
1621 (ins GPR:$addr, GPR:$src1, GPR:$src2),
1623 def ATOMAND6432 : PseudoInst<(outs GPR:$dst1, GPR:$dst2),
1624 (ins GPR:$addr, GPR:$src1, GPR:$src2),
1626 def ATOMSWAP6432 : PseudoInst<(outs GPR:$dst1, GPR:$dst2),
1627 (ins GPR:$addr, GPR:$src1, GPR:$src2),
1629 def ATOMCMPXCHG6432 : PseudoInst<(outs GPR:$dst1, GPR:$dst2),
1630 (ins GPR:$addr, GPR:$cmp1, GPR:$cmp2,
1631 GPR:$set1, GPR:$set2),
1635 def NOP : AI<(outs), (ins), MiscFrm, NoItinerary, "nop", "", []>,
1636 Requires<[IsARM, HasV6T2]> {
1637 let Inst{27-16} = 0b001100100000;
1638 let Inst{15-8} = 0b11110000;
1639 let Inst{7-0} = 0b00000000;
1642 def YIELD : AI<(outs), (ins), MiscFrm, NoItinerary, "yield", "", []>,
1643 Requires<[IsARM, HasV6T2]> {
1644 let Inst{27-16} = 0b001100100000;
1645 let Inst{15-8} = 0b11110000;
1646 let Inst{7-0} = 0b00000001;
1649 def WFE : AI<(outs), (ins), MiscFrm, NoItinerary, "wfe", "", []>,
1650 Requires<[IsARM, HasV6T2]> {
1651 let Inst{27-16} = 0b001100100000;
1652 let Inst{15-8} = 0b11110000;
1653 let Inst{7-0} = 0b00000010;
1656 def WFI : AI<(outs), (ins), MiscFrm, NoItinerary, "wfi", "", []>,
1657 Requires<[IsARM, HasV6T2]> {
1658 let Inst{27-16} = 0b001100100000;
1659 let Inst{15-8} = 0b11110000;
1660 let Inst{7-0} = 0b00000011;
1663 def SEL : AI<(outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm), DPFrm, NoItinerary, "sel",
1664 "\t$Rd, $Rn, $Rm", []>, Requires<[IsARM, HasV6]> {
1669 let Inst{15-12} = Rd;
1670 let Inst{19-16} = Rn;
1671 let Inst{27-20} = 0b01101000;
1672 let Inst{7-4} = 0b1011;
1673 let Inst{11-8} = 0b1111;
1676 def SEV : AI<(outs), (ins), MiscFrm, NoItinerary, "sev", "",
1677 []>, Requires<[IsARM, HasV6T2]> {
1678 let Inst{27-16} = 0b001100100000;
1679 let Inst{15-8} = 0b11110000;
1680 let Inst{7-0} = 0b00000100;
1683 // The i32imm operand $val can be used by a debugger to store more information
1684 // about the breakpoint.
1685 def BKPT : AI<(outs), (ins imm0_65535:$val), MiscFrm, NoItinerary,
1686 "bkpt", "\t$val", []>, Requires<[IsARM]> {
1688 let Inst{3-0} = val{3-0};
1689 let Inst{19-8} = val{15-4};
1690 let Inst{27-20} = 0b00010010;
1691 let Inst{7-4} = 0b0111;
1694 // Change Processor State
1695 // FIXME: We should use InstAlias to handle the optional operands.
1696 class CPS<dag iops, string asm_ops>
1697 : AXI<(outs), iops, MiscFrm, NoItinerary, !strconcat("cps", asm_ops),
1698 []>, Requires<[IsARM]> {
1704 let Inst{31-28} = 0b1111;
1705 let Inst{27-20} = 0b00010000;
1706 let Inst{19-18} = imod;
1707 let Inst{17} = M; // Enabled if mode is set;
1708 let Inst{16-9} = 0b00000000;
1709 let Inst{8-6} = iflags;
1711 let Inst{4-0} = mode;
1714 let DecoderMethod = "DecodeCPSInstruction" in {
1716 def CPS3p : CPS<(ins imod_op:$imod, iflags_op:$iflags, imm0_31:$mode),
1717 "$imod\t$iflags, $mode">;
1718 let mode = 0, M = 0 in
1719 def CPS2p : CPS<(ins imod_op:$imod, iflags_op:$iflags), "$imod\t$iflags">;
1721 let imod = 0, iflags = 0, M = 1 in
1722 def CPS1p : CPS<(ins imm0_31:$mode), "\t$mode">;
1725 // Preload signals the memory system of possible future data/instruction access.
1726 multiclass APreLoad<bits<1> read, bits<1> data, string opc> {
1728 def i12 : AXI<(outs), (ins addrmode_imm12:$addr), MiscFrm, IIC_Preload,
1729 !strconcat(opc, "\t$addr"),
1730 [(ARMPreload addrmode_imm12:$addr, (i32 read), (i32 data))]> {
1733 let Inst{31-26} = 0b111101;
1734 let Inst{25} = 0; // 0 for immediate form
1735 let Inst{24} = data;
1736 let Inst{23} = addr{12}; // U (add = ('U' == 1))
1737 let Inst{22} = read;
1738 let Inst{21-20} = 0b01;
1739 let Inst{19-16} = addr{16-13}; // Rn
1740 let Inst{15-12} = 0b1111;
1741 let Inst{11-0} = addr{11-0}; // imm12
1744 def rs : AXI<(outs), (ins ldst_so_reg:$shift), MiscFrm, IIC_Preload,
1745 !strconcat(opc, "\t$shift"),
1746 [(ARMPreload ldst_so_reg:$shift, (i32 read), (i32 data))]> {
1748 let Inst{31-26} = 0b111101;
1749 let Inst{25} = 1; // 1 for register form
1750 let Inst{24} = data;
1751 let Inst{23} = shift{12}; // U (add = ('U' == 1))
1752 let Inst{22} = read;
1753 let Inst{21-20} = 0b01;
1754 let Inst{19-16} = shift{16-13}; // Rn
1755 let Inst{15-12} = 0b1111;
1756 let Inst{11-0} = shift{11-0};
1761 defm PLD : APreLoad<1, 1, "pld">, Requires<[IsARM]>;
1762 defm PLDW : APreLoad<0, 1, "pldw">, Requires<[IsARM,HasV7,HasMP]>;
1763 defm PLI : APreLoad<1, 0, "pli">, Requires<[IsARM,HasV7]>;
1765 def SETEND : AXI<(outs), (ins setend_op:$end), MiscFrm, NoItinerary,
1766 "setend\t$end", []>, Requires<[IsARM]> {
1768 let Inst{31-10} = 0b1111000100000001000000;
1773 def DBG : AI<(outs), (ins imm0_15:$opt), MiscFrm, NoItinerary, "dbg", "\t$opt",
1774 []>, Requires<[IsARM, HasV7]> {
1776 let Inst{27-4} = 0b001100100000111100001111;
1777 let Inst{3-0} = opt;
1780 // A5.4 Permanently UNDEFINED instructions.
1781 let isBarrier = 1, isTerminator = 1 in
1782 def TRAP : AXI<(outs), (ins), MiscFrm, NoItinerary,
1785 let Inst = 0xe7ffdefe;
1788 // Address computation and loads and stores in PIC mode.
1789 let isNotDuplicable = 1 in {
1790 def PICADD : ARMPseudoInst<(outs GPR:$dst), (ins GPR:$a, pclabel:$cp, pred:$p),
1792 [(set GPR:$dst, (ARMpic_add GPR:$a, imm:$cp))]>;
1794 let AddedComplexity = 10 in {
1795 def PICLDR : ARMPseudoInst<(outs GPR:$dst), (ins addrmodepc:$addr, pred:$p),
1797 [(set GPR:$dst, (load addrmodepc:$addr))]>;
1799 def PICLDRH : ARMPseudoInst<(outs GPR:$Rt), (ins addrmodepc:$addr, pred:$p),
1801 [(set GPR:$Rt, (zextloadi16 addrmodepc:$addr))]>;
1803 def PICLDRB : ARMPseudoInst<(outs GPR:$Rt), (ins addrmodepc:$addr, pred:$p),
1805 [(set GPR:$Rt, (zextloadi8 addrmodepc:$addr))]>;
1807 def PICLDRSH : ARMPseudoInst<(outs GPR:$Rt), (ins addrmodepc:$addr, pred:$p),
1809 [(set GPR:$Rt, (sextloadi16 addrmodepc:$addr))]>;
1811 def PICLDRSB : ARMPseudoInst<(outs GPR:$Rt), (ins addrmodepc:$addr, pred:$p),
1813 [(set GPR:$Rt, (sextloadi8 addrmodepc:$addr))]>;
1815 let AddedComplexity = 10 in {
1816 def PICSTR : ARMPseudoInst<(outs), (ins GPR:$src, addrmodepc:$addr, pred:$p),
1817 4, IIC_iStore_r, [(store GPR:$src, addrmodepc:$addr)]>;
1819 def PICSTRH : ARMPseudoInst<(outs), (ins GPR:$src, addrmodepc:$addr, pred:$p),
1820 4, IIC_iStore_bh_r, [(truncstorei16 GPR:$src,
1821 addrmodepc:$addr)]>;
1823 def PICSTRB : ARMPseudoInst<(outs), (ins GPR:$src, addrmodepc:$addr, pred:$p),
1824 4, IIC_iStore_bh_r, [(truncstorei8 GPR:$src, addrmodepc:$addr)]>;
1826 } // isNotDuplicable = 1
1829 // LEApcrel - Load a pc-relative address into a register without offending the
1831 let neverHasSideEffects = 1, isReMaterializable = 1 in
1832 // The 'adr' mnemonic encodes differently if the label is before or after
1833 // the instruction. The {24-21} opcode bits are set by the fixup, as we don't
1834 // know until then which form of the instruction will be used.
1835 def ADR : AI1<{0,?,?,0}, (outs GPR:$Rd), (ins adrlabel:$label),
1836 MiscFrm, IIC_iALUi, "adr", "\t$Rd, $label", []> {
1839 let Inst{27-25} = 0b001;
1841 let Inst{23-22} = label{13-12};
1844 let Inst{19-16} = 0b1111;
1845 let Inst{15-12} = Rd;
1846 let Inst{11-0} = label{11-0};
1848 def LEApcrel : ARMPseudoInst<(outs GPR:$Rd), (ins i32imm:$label, pred:$p),
1851 def LEApcrelJT : ARMPseudoInst<(outs GPR:$Rd),
1852 (ins i32imm:$label, nohash_imm:$id, pred:$p),
1855 //===----------------------------------------------------------------------===//
1856 // Control Flow Instructions.
1859 let isReturn = 1, isTerminator = 1, isBarrier = 1 in {
1861 def BX_RET : AI<(outs), (ins), BrMiscFrm, IIC_Br,
1862 "bx", "\tlr", [(ARMretflag)]>,
1863 Requires<[IsARM, HasV4T]> {
1864 let Inst{27-0} = 0b0001001011111111111100011110;
1868 def MOVPCLR : AI<(outs), (ins), BrMiscFrm, IIC_Br,
1869 "mov", "\tpc, lr", [(ARMretflag)]>,
1870 Requires<[IsARM, NoV4T]> {
1871 let Inst{27-0} = 0b0001101000001111000000001110;
1875 // Indirect branches
1876 let isBranch = 1, isTerminator = 1, isBarrier = 1, isIndirectBranch = 1 in {
1878 def BX : AXI<(outs), (ins GPR:$dst), BrMiscFrm, IIC_Br, "bx\t$dst",
1879 [(brind GPR:$dst)]>,
1880 Requires<[IsARM, HasV4T]> {
1882 let Inst{31-4} = 0b1110000100101111111111110001;
1883 let Inst{3-0} = dst;
1886 def BX_pred : AI<(outs), (ins GPR:$dst), BrMiscFrm, IIC_Br,
1887 "bx", "\t$dst", [/* pattern left blank */]>,
1888 Requires<[IsARM, HasV4T]> {
1890 let Inst{27-4} = 0b000100101111111111110001;
1891 let Inst{3-0} = dst;
1895 // All calls clobber the non-callee saved registers. SP is marked as
1896 // a use to prevent stack-pointer assignments that appear immediately
1897 // before calls from potentially appearing dead.
1899 // On non-IOS platforms R9 is callee-saved.
1900 // FIXME: Do we really need a non-predicated version? If so, it should
1901 // at least be a pseudo instruction expanding to the predicated version
1902 // at MC lowering time.
1903 Defs = [R0, R1, R2, R3, R12, LR, QQQQ0, QQQQ2, QQQQ3, CPSR, FPSCR],
1905 def BL : ABXI<0b1011, (outs), (ins bl_target:$func, variable_ops),
1906 IIC_Br, "bl\t$func",
1907 [(ARMcall tglobaladdr:$func)]>,
1908 Requires<[IsARM, IsNotIOS]> {
1909 let Inst{31-28} = 0b1110;
1911 let Inst{23-0} = func;
1912 let DecoderMethod = "DecodeBranchImmInstruction";
1915 def BL_pred : ABI<0b1011, (outs), (ins bl_target:$func, variable_ops),
1916 IIC_Br, "bl", "\t$func",
1917 [(ARMcall_pred tglobaladdr:$func)]>,
1918 Requires<[IsARM, IsNotIOS]> {
1920 let Inst{23-0} = func;
1921 let DecoderMethod = "DecodeBranchImmInstruction";
1925 def BLX : AXI<(outs), (ins GPR:$func, variable_ops), BrMiscFrm,
1926 IIC_Br, "blx\t$func",
1927 [(ARMcall GPR:$func)]>,
1928 Requires<[IsARM, HasV5T, IsNotIOS]> {
1930 let Inst{31-4} = 0b1110000100101111111111110011;
1931 let Inst{3-0} = func;
1934 def BLX_pred : AI<(outs), (ins GPR:$func, variable_ops), BrMiscFrm,
1935 IIC_Br, "blx", "\t$func",
1936 [(ARMcall_pred GPR:$func)]>,
1937 Requires<[IsARM, HasV5T, IsNotIOS]> {
1939 let Inst{27-4} = 0b000100101111111111110011;
1940 let Inst{3-0} = func;
1944 // Note: Restrict $func to the tGPR regclass to prevent it being in LR.
1945 def BX_CALL : ARMPseudoInst<(outs), (ins tGPR:$func, variable_ops),
1946 8, IIC_Br, [(ARMcall_nolink tGPR:$func)]>,
1947 Requires<[IsARM, HasV4T, IsNotIOS]>;
1950 def BMOVPCRX_CALL : ARMPseudoInst<(outs), (ins tGPR:$func, variable_ops),
1951 8, IIC_Br, [(ARMcall_nolink tGPR:$func)]>,
1952 Requires<[IsARM, NoV4T, IsNotIOS]>;
1956 // On IOS R9 is call-clobbered.
1957 // R7 is marked as a use to prevent frame-pointer assignments from being
1958 // moved above / below calls.
1959 Defs = [R0, R1, R2, R3, R9, R12, LR, QQQQ0, QQQQ2, QQQQ3, CPSR, FPSCR],
1960 Uses = [R7, SP] in {
1961 def BLr9 : ARMPseudoExpand<(outs), (ins bl_target:$func, variable_ops),
1963 [(ARMcall tglobaladdr:$func)], (BL bl_target:$func)>,
1964 Requires<[IsARM, IsIOS]>;
1966 def BLr9_pred : ARMPseudoExpand<(outs),
1967 (ins bl_target:$func, pred:$p, variable_ops),
1969 [(ARMcall_pred tglobaladdr:$func)],
1970 (BL_pred bl_target:$func, pred:$p)>,
1971 Requires<[IsARM, IsIOS]>;
1974 def BLXr9 : ARMPseudoExpand<(outs), (ins GPR:$func, variable_ops),
1976 [(ARMcall GPR:$func)],
1978 Requires<[IsARM, HasV5T, IsIOS]>;
1980 def BLXr9_pred: ARMPseudoExpand<(outs), (ins GPR:$func, pred:$p,variable_ops),
1982 [(ARMcall_pred GPR:$func)],
1983 (BLX_pred GPR:$func, pred:$p)>,
1984 Requires<[IsARM, HasV5T, IsIOS]>;
1987 // Note: Restrict $func to the tGPR regclass to prevent it being in LR.
1988 def BXr9_CALL : ARMPseudoInst<(outs), (ins tGPR:$func, variable_ops),
1989 8, IIC_Br, [(ARMcall_nolink tGPR:$func)]>,
1990 Requires<[IsARM, HasV4T, IsIOS]>;
1993 def BMOVPCRXr9_CALL : ARMPseudoInst<(outs), (ins tGPR:$func, variable_ops),
1994 8, IIC_Br, [(ARMcall_nolink tGPR:$func)]>,
1995 Requires<[IsARM, NoV4T, IsIOS]>;
1998 let isBranch = 1, isTerminator = 1 in {
1999 // FIXME: should be able to write a pattern for ARMBrcond, but can't use
2000 // a two-value operand where a dag node expects two operands. :(
2001 def Bcc : ABI<0b1010, (outs), (ins br_target:$target),
2002 IIC_Br, "b", "\t$target",
2003 [/*(ARMbrcond bb:$target, imm:$cc, CCR:$ccr)*/]> {
2005 let Inst{23-0} = target;
2006 let DecoderMethod = "DecodeBranchImmInstruction";
2009 let isBarrier = 1 in {
2010 // B is "predicable" since it's just a Bcc with an 'always' condition.
2011 let isPredicable = 1 in
2012 // FIXME: We shouldn't need this pseudo at all. Just using Bcc directly
2013 // should be sufficient.
2014 // FIXME: Is B really a Barrier? That doesn't seem right.
2015 def B : ARMPseudoExpand<(outs), (ins br_target:$target), 4, IIC_Br,
2016 [(br bb:$target)], (Bcc br_target:$target, (ops 14, zero_reg))>;
2018 let isNotDuplicable = 1, isIndirectBranch = 1 in {
2019 def BR_JTr : ARMPseudoInst<(outs),
2020 (ins GPR:$target, i32imm:$jt, i32imm:$id),
2022 [(ARMbrjt GPR:$target, tjumptable:$jt, imm:$id)]>;
2023 // FIXME: This shouldn't use the generic "addrmode2," but rather be split
2024 // into i12 and rs suffixed versions.
2025 def BR_JTm : ARMPseudoInst<(outs),
2026 (ins addrmode2:$target, i32imm:$jt, i32imm:$id),
2028 [(ARMbrjt (i32 (load addrmode2:$target)), tjumptable:$jt,
2030 def BR_JTadd : ARMPseudoInst<(outs),
2031 (ins GPR:$target, GPR:$idx, i32imm:$jt, i32imm:$id),
2033 [(ARMbrjt (add GPR:$target, GPR:$idx), tjumptable:$jt,
2035 } // isNotDuplicable = 1, isIndirectBranch = 1
2041 def BLXi : AXI<(outs), (ins blx_target:$target), BrMiscFrm, NoItinerary,
2042 "blx\t$target", []>,
2043 Requires<[IsARM, HasV5T]> {
2044 let Inst{31-25} = 0b1111101;
2046 let Inst{23-0} = target{24-1};
2047 let Inst{24} = target{0};
2050 // Branch and Exchange Jazelle
2051 def BXJ : ABI<0b0001, (outs), (ins GPR:$func), NoItinerary, "bxj", "\t$func",
2052 [/* pattern left blank */]> {
2054 let Inst{23-20} = 0b0010;
2055 let Inst{19-8} = 0xfff;
2056 let Inst{7-4} = 0b0010;
2057 let Inst{3-0} = func;
2062 let isCall = 1, isTerminator = 1, isReturn = 1, isBarrier = 1 in {
2064 let Defs = [R0, R1, R2, R3, R9, R12, QQQQ0, QQQQ2, QQQQ3, PC],
2066 def TCRETURNdi : PseudoInst<(outs), (ins i32imm:$dst, variable_ops),
2067 IIC_Br, []>, Requires<[IsIOS]>;
2069 def TCRETURNri : PseudoInst<(outs), (ins tcGPR:$dst, variable_ops),
2070 IIC_Br, []>, Requires<[IsIOS]>;
2072 def TAILJMPd : ARMPseudoExpand<(outs), (ins br_target:$dst, variable_ops),
2074 (Bcc br_target:$dst, (ops 14, zero_reg))>,
2075 Requires<[IsARM, IsIOS]>;
2077 def TAILJMPr : ARMPseudoExpand<(outs), (ins tcGPR:$dst, variable_ops),
2080 Requires<[IsARM, IsIOS]>;
2084 // Non-IOS versions (the difference is R9).
2085 let Defs = [R0, R1, R2, R3, R12, QQQQ0, QQQQ2, QQQQ3, PC],
2087 def TCRETURNdiND : PseudoInst<(outs), (ins i32imm:$dst, variable_ops),
2088 IIC_Br, []>, Requires<[IsNotIOS]>;
2090 def TCRETURNriND : PseudoInst<(outs), (ins tcGPR:$dst, variable_ops),
2091 IIC_Br, []>, Requires<[IsNotIOS]>;
2093 def TAILJMPdND : ARMPseudoExpand<(outs), (ins brtarget:$dst, variable_ops),
2095 (Bcc br_target:$dst, (ops 14, zero_reg))>,
2096 Requires<[IsARM, IsNotIOS]>;
2098 def TAILJMPrND : ARMPseudoExpand<(outs), (ins tcGPR:$dst, variable_ops),
2101 Requires<[IsARM, IsNotIOS]>;
2105 // Secure Monitor Call is a system instruction.
2106 def SMC : ABI<0b0001, (outs), (ins imm0_15:$opt), NoItinerary, "smc", "\t$opt",
2109 let Inst{23-4} = 0b01100000000000000111;
2110 let Inst{3-0} = opt;
2113 // Supervisor Call (Software Interrupt)
2114 let isCall = 1, Uses = [SP] in {
2115 def SVC : ABI<0b1111, (outs), (ins imm24b:$svc), IIC_Br, "svc", "\t$svc", []> {
2117 let Inst{23-0} = svc;
2121 // Store Return State
2122 class SRSI<bit wb, string asm>
2123 : XI<(outs), (ins imm0_31:$mode), AddrModeNone, 4, IndexModeNone, BrFrm,
2124 NoItinerary, asm, "", []> {
2126 let Inst{31-28} = 0b1111;
2127 let Inst{27-25} = 0b100;
2131 let Inst{19-16} = 0b1101; // SP
2132 let Inst{15-5} = 0b00000101000;
2133 let Inst{4-0} = mode;
2136 def SRSDA : SRSI<0, "srsda\tsp, $mode"> {
2137 let Inst{24-23} = 0;
2139 def SRSDA_UPD : SRSI<1, "srsda\tsp!, $mode"> {
2140 let Inst{24-23} = 0;
2142 def SRSDB : SRSI<0, "srsdb\tsp, $mode"> {
2143 let Inst{24-23} = 0b10;
2145 def SRSDB_UPD : SRSI<1, "srsdb\tsp!, $mode"> {
2146 let Inst{24-23} = 0b10;
2148 def SRSIA : SRSI<0, "srsia\tsp, $mode"> {
2149 let Inst{24-23} = 0b01;
2151 def SRSIA_UPD : SRSI<1, "srsia\tsp!, $mode"> {
2152 let Inst{24-23} = 0b01;
2154 def SRSIB : SRSI<0, "srsib\tsp, $mode"> {
2155 let Inst{24-23} = 0b11;
2157 def SRSIB_UPD : SRSI<1, "srsib\tsp!, $mode"> {
2158 let Inst{24-23} = 0b11;
2161 // Return From Exception
2162 class RFEI<bit wb, string asm>
2163 : XI<(outs), (ins GPR:$Rn), AddrModeNone, 4, IndexModeNone, BrFrm,
2164 NoItinerary, asm, "", []> {
2166 let Inst{31-28} = 0b1111;
2167 let Inst{27-25} = 0b100;
2171 let Inst{19-16} = Rn;
2172 let Inst{15-0} = 0xa00;
2175 def RFEDA : RFEI<0, "rfeda\t$Rn"> {
2176 let Inst{24-23} = 0;
2178 def RFEDA_UPD : RFEI<1, "rfeda\t$Rn!"> {
2179 let Inst{24-23} = 0;
2181 def RFEDB : RFEI<0, "rfedb\t$Rn"> {
2182 let Inst{24-23} = 0b10;
2184 def RFEDB_UPD : RFEI<1, "rfedb\t$Rn!"> {
2185 let Inst{24-23} = 0b10;
2187 def RFEIA : RFEI<0, "rfeia\t$Rn"> {
2188 let Inst{24-23} = 0b01;
2190 def RFEIA_UPD : RFEI<1, "rfeia\t$Rn!"> {
2191 let Inst{24-23} = 0b01;
2193 def RFEIB : RFEI<0, "rfeib\t$Rn"> {
2194 let Inst{24-23} = 0b11;
2196 def RFEIB_UPD : RFEI<1, "rfeib\t$Rn!"> {
2197 let Inst{24-23} = 0b11;
2200 //===----------------------------------------------------------------------===//
2201 // Load / Store Instructions.
2207 defm LDR : AI_ldr1<0, "ldr", IIC_iLoad_r, IIC_iLoad_si,
2208 UnOpFrag<(load node:$Src)>>;
2209 defm LDRB : AI_ldr1nopc<1, "ldrb", IIC_iLoad_bh_r, IIC_iLoad_bh_si,
2210 UnOpFrag<(zextloadi8 node:$Src)>>;
2211 defm STR : AI_str1<0, "str", IIC_iStore_r, IIC_iStore_si,
2212 BinOpFrag<(store node:$LHS, node:$RHS)>>;
2213 defm STRB : AI_str1nopc<1, "strb", IIC_iStore_bh_r, IIC_iStore_bh_si,
2214 BinOpFrag<(truncstorei8 node:$LHS, node:$RHS)>>;
2216 // Special LDR for loads from non-pc-relative constpools.
2217 let canFoldAsLoad = 1, mayLoad = 1, neverHasSideEffects = 1,
2218 isReMaterializable = 1, isCodeGenOnly = 1 in
2219 def LDRcp : AI2ldst<0b010, 1, 0, (outs GPR:$Rt), (ins addrmode_imm12:$addr),
2220 AddrMode_i12, LdFrm, IIC_iLoad_r, "ldr", "\t$Rt, $addr",
2224 let Inst{23} = addr{12}; // U (add = ('U' == 1))
2225 let Inst{19-16} = 0b1111;
2226 let Inst{15-12} = Rt;
2227 let Inst{11-0} = addr{11-0}; // imm12
2230 // Loads with zero extension
2231 def LDRH : AI3ld<0b1011, 1, (outs GPR:$Rt), (ins addrmode3:$addr), LdMiscFrm,
2232 IIC_iLoad_bh_r, "ldrh", "\t$Rt, $addr",
2233 [(set GPR:$Rt, (zextloadi16 addrmode3:$addr))]>;
2235 // Loads with sign extension
2236 def LDRSH : AI3ld<0b1111, 1, (outs GPR:$Rt), (ins addrmode3:$addr), LdMiscFrm,
2237 IIC_iLoad_bh_r, "ldrsh", "\t$Rt, $addr",
2238 [(set GPR:$Rt, (sextloadi16 addrmode3:$addr))]>;
2240 def LDRSB : AI3ld<0b1101, 1, (outs GPR:$Rt), (ins addrmode3:$addr), LdMiscFrm,
2241 IIC_iLoad_bh_r, "ldrsb", "\t$Rt, $addr",
2242 [(set GPR:$Rt, (sextloadi8 addrmode3:$addr))]>;
2244 let mayLoad = 1, neverHasSideEffects = 1, hasExtraDefRegAllocReq = 1 in {
2246 def LDRD : AI3ld<0b1101, 0, (outs GPR:$Rd, GPR:$dst2),
2247 (ins addrmode3:$addr), LdMiscFrm,
2248 IIC_iLoad_d_r, "ldrd", "\t$Rd, $dst2, $addr",
2249 []>, Requires<[IsARM, HasV5TE]>;
2253 multiclass AI2_ldridx<bit isByte, string opc,
2254 InstrItinClass iii, InstrItinClass iir> {
2255 def _PRE_IMM : AI2ldstidx<1, isByte, 1, (outs GPR:$Rt, GPR:$Rn_wb),
2256 (ins addrmode_imm12:$addr), IndexModePre, LdFrm, iii,
2257 opc, "\t$Rt, $addr!", "$addr.base = $Rn_wb", []> {
2260 let Inst{23} = addr{12};
2261 let Inst{19-16} = addr{16-13};
2262 let Inst{11-0} = addr{11-0};
2263 let DecoderMethod = "DecodeLDRPreImm";
2264 let AsmMatchConverter = "cvtLdWriteBackRegAddrModeImm12";
2267 def _PRE_REG : AI2ldstidx<1, isByte, 1, (outs GPR:$Rt, GPR:$Rn_wb),
2268 (ins ldst_so_reg:$addr), IndexModePre, LdFrm, iir,
2269 opc, "\t$Rt, $addr!", "$addr.base = $Rn_wb", []> {
2272 let Inst{23} = addr{12};
2273 let Inst{19-16} = addr{16-13};
2274 let Inst{11-0} = addr{11-0};
2276 let DecoderMethod = "DecodeLDRPreReg";
2277 let AsmMatchConverter = "cvtLdWriteBackRegAddrMode2";
2280 def _POST_REG : AI2ldstidx<1, isByte, 0, (outs GPR:$Rt, GPR:$Rn_wb),
2281 (ins addr_offset_none:$addr, am2offset_reg:$offset),
2282 IndexModePost, LdFrm, iir,
2283 opc, "\t$Rt, $addr, $offset",
2284 "$addr.base = $Rn_wb", []> {
2290 let Inst{23} = offset{12};
2291 let Inst{19-16} = addr;
2292 let Inst{11-0} = offset{11-0};
2294 let DecoderMethod = "DecodeAddrMode2IdxInstruction";
2297 def _POST_IMM : AI2ldstidx<1, isByte, 0, (outs GPR:$Rt, GPR:$Rn_wb),
2298 (ins addr_offset_none:$addr, am2offset_imm:$offset),
2299 IndexModePost, LdFrm, iii,
2300 opc, "\t$Rt, $addr, $offset",
2301 "$addr.base = $Rn_wb", []> {
2307 let Inst{23} = offset{12};
2308 let Inst{19-16} = addr;
2309 let Inst{11-0} = offset{11-0};
2311 let DecoderMethod = "DecodeAddrMode2IdxInstruction";
2316 let mayLoad = 1, neverHasSideEffects = 1 in {
2317 // FIXME: for LDR_PRE_REG etc. the itineray should be either IIC_iLoad_ru or
2318 // IIC_iLoad_siu depending on whether it the offset register is shifted.
2319 defm LDR : AI2_ldridx<0, "ldr", IIC_iLoad_iu, IIC_iLoad_ru>;
2320 defm LDRB : AI2_ldridx<1, "ldrb", IIC_iLoad_bh_iu, IIC_iLoad_bh_ru>;
2323 multiclass AI3_ldridx<bits<4> op, string opc, InstrItinClass itin> {
2324 def _PRE : AI3ldstidx<op, 1, 1, (outs GPR:$Rt, GPR:$Rn_wb),
2325 (ins addrmode3:$addr), IndexModePre,
2327 opc, "\t$Rt, $addr!", "$addr.base = $Rn_wb", []> {
2329 let Inst{23} = addr{8}; // U bit
2330 let Inst{22} = addr{13}; // 1 == imm8, 0 == Rm
2331 let Inst{19-16} = addr{12-9}; // Rn
2332 let Inst{11-8} = addr{7-4}; // imm7_4/zero
2333 let Inst{3-0} = addr{3-0}; // imm3_0/Rm
2334 let AsmMatchConverter = "cvtLdWriteBackRegAddrMode3";
2335 let DecoderMethod = "DecodeAddrMode3Instruction";
2337 def _POST : AI3ldstidx<op, 1, 0, (outs GPR:$Rt, GPR:$Rn_wb),
2338 (ins addr_offset_none:$addr, am3offset:$offset),
2339 IndexModePost, LdMiscFrm, itin,
2340 opc, "\t$Rt, $addr, $offset", "$addr.base = $Rn_wb",
2344 let Inst{23} = offset{8}; // U bit
2345 let Inst{22} = offset{9}; // 1 == imm8, 0 == Rm
2346 let Inst{19-16} = addr;
2347 let Inst{11-8} = offset{7-4}; // imm7_4/zero
2348 let Inst{3-0} = offset{3-0}; // imm3_0/Rm
2349 let DecoderMethod = "DecodeAddrMode3Instruction";
2353 let mayLoad = 1, neverHasSideEffects = 1 in {
2354 defm LDRH : AI3_ldridx<0b1011, "ldrh", IIC_iLoad_bh_ru>;
2355 defm LDRSH : AI3_ldridx<0b1111, "ldrsh", IIC_iLoad_bh_ru>;
2356 defm LDRSB : AI3_ldridx<0b1101, "ldrsb", IIC_iLoad_bh_ru>;
2357 let hasExtraDefRegAllocReq = 1 in {
2358 def LDRD_PRE : AI3ldstidx<0b1101, 0, 1, (outs GPR:$Rt, GPR:$Rt2, GPR:$Rn_wb),
2359 (ins addrmode3:$addr), IndexModePre,
2360 LdMiscFrm, IIC_iLoad_d_ru,
2361 "ldrd", "\t$Rt, $Rt2, $addr!",
2362 "$addr.base = $Rn_wb", []> {
2364 let Inst{23} = addr{8}; // U bit
2365 let Inst{22} = addr{13}; // 1 == imm8, 0 == Rm
2366 let Inst{19-16} = addr{12-9}; // Rn
2367 let Inst{11-8} = addr{7-4}; // imm7_4/zero
2368 let Inst{3-0} = addr{3-0}; // imm3_0/Rm
2369 let DecoderMethod = "DecodeAddrMode3Instruction";
2370 let AsmMatchConverter = "cvtLdrdPre";
2372 def LDRD_POST: AI3ldstidx<0b1101, 0, 0, (outs GPR:$Rt, GPR:$Rt2, GPR:$Rn_wb),
2373 (ins addr_offset_none:$addr, am3offset:$offset),
2374 IndexModePost, LdMiscFrm, IIC_iLoad_d_ru,
2375 "ldrd", "\t$Rt, $Rt2, $addr, $offset",
2376 "$addr.base = $Rn_wb", []> {
2379 let Inst{23} = offset{8}; // U bit
2380 let Inst{22} = offset{9}; // 1 == imm8, 0 == Rm
2381 let Inst{19-16} = addr;
2382 let Inst{11-8} = offset{7-4}; // imm7_4/zero
2383 let Inst{3-0} = offset{3-0}; // imm3_0/Rm
2384 let DecoderMethod = "DecodeAddrMode3Instruction";
2386 } // hasExtraDefRegAllocReq = 1
2387 } // mayLoad = 1, neverHasSideEffects = 1
2389 // LDRT, LDRBT, LDRSBT, LDRHT, LDRSHT.
2390 let mayLoad = 1, neverHasSideEffects = 1 in {
2391 def LDRT_POST_REG : AI2ldstidx<1, 0, 0, (outs GPR:$Rt, GPR:$Rn_wb),
2392 (ins addr_offset_none:$addr, am2offset_reg:$offset),
2393 IndexModePost, LdFrm, IIC_iLoad_ru,
2394 "ldrt", "\t$Rt, $addr, $offset",
2395 "$addr.base = $Rn_wb", []> {
2401 let Inst{23} = offset{12};
2402 let Inst{21} = 1; // overwrite
2403 let Inst{19-16} = addr;
2404 let Inst{11-5} = offset{11-5};
2406 let Inst{3-0} = offset{3-0};
2407 let DecoderMethod = "DecodeAddrMode2IdxInstruction";
2410 def LDRT_POST_IMM : AI2ldstidx<1, 0, 0, (outs GPR:$Rt, GPR:$Rn_wb),
2411 (ins addr_offset_none:$addr, am2offset_imm:$offset),
2412 IndexModePost, LdFrm, IIC_iLoad_ru,
2413 "ldrt", "\t$Rt, $addr, $offset",
2414 "$addr.base = $Rn_wb", []> {
2420 let Inst{23} = offset{12};
2421 let Inst{21} = 1; // overwrite
2422 let Inst{19-16} = addr;
2423 let Inst{11-0} = offset{11-0};
2424 let DecoderMethod = "DecodeAddrMode2IdxInstruction";
2427 def LDRBT_POST_REG : AI2ldstidx<1, 1, 0, (outs GPR:$Rt, GPR:$Rn_wb),
2428 (ins addr_offset_none:$addr, am2offset_reg:$offset),
2429 IndexModePost, LdFrm, IIC_iLoad_bh_ru,
2430 "ldrbt", "\t$Rt, $addr, $offset",
2431 "$addr.base = $Rn_wb", []> {
2437 let Inst{23} = offset{12};
2438 let Inst{21} = 1; // overwrite
2439 let Inst{19-16} = addr;
2440 let Inst{11-5} = offset{11-5};
2442 let Inst{3-0} = offset{3-0};
2443 let DecoderMethod = "DecodeAddrMode2IdxInstruction";
2446 def LDRBT_POST_IMM : AI2ldstidx<1, 1, 0, (outs GPR:$Rt, GPR:$Rn_wb),
2447 (ins addr_offset_none:$addr, am2offset_imm:$offset),
2448 IndexModePost, LdFrm, IIC_iLoad_bh_ru,
2449 "ldrbt", "\t$Rt, $addr, $offset",
2450 "$addr.base = $Rn_wb", []> {
2456 let Inst{23} = offset{12};
2457 let Inst{21} = 1; // overwrite
2458 let Inst{19-16} = addr;
2459 let Inst{11-0} = offset{11-0};
2460 let DecoderMethod = "DecodeAddrMode2IdxInstruction";
2463 multiclass AI3ldrT<bits<4> op, string opc> {
2464 def i : AI3ldstidxT<op, 1, (outs GPR:$Rt, GPR:$base_wb),
2465 (ins addr_offset_none:$addr, postidx_imm8:$offset),
2466 IndexModePost, LdMiscFrm, IIC_iLoad_bh_ru, opc,
2467 "\t$Rt, $addr, $offset", "$addr.base = $base_wb", []> {
2469 let Inst{23} = offset{8};
2471 let Inst{11-8} = offset{7-4};
2472 let Inst{3-0} = offset{3-0};
2473 let AsmMatchConverter = "cvtLdExtTWriteBackImm";
2475 def r : AI3ldstidxT<op, 1, (outs GPR:$Rt, GPR:$base_wb),
2476 (ins addr_offset_none:$addr, postidx_reg:$Rm),
2477 IndexModePost, LdMiscFrm, IIC_iLoad_bh_ru, opc,
2478 "\t$Rt, $addr, $Rm", "$addr.base = $base_wb", []> {
2480 let Inst{23} = Rm{4};
2483 let Inst{3-0} = Rm{3-0};
2484 let AsmMatchConverter = "cvtLdExtTWriteBackReg";
2488 defm LDRSBT : AI3ldrT<0b1101, "ldrsbt">;
2489 defm LDRHT : AI3ldrT<0b1011, "ldrht">;
2490 defm LDRSHT : AI3ldrT<0b1111, "ldrsht">;
2495 // Stores with truncate
2496 def STRH : AI3str<0b1011, (outs), (ins GPR:$Rt, addrmode3:$addr), StMiscFrm,
2497 IIC_iStore_bh_r, "strh", "\t$Rt, $addr",
2498 [(truncstorei16 GPR:$Rt, addrmode3:$addr)]>;
2501 let mayStore = 1, neverHasSideEffects = 1, hasExtraSrcRegAllocReq = 1 in
2502 def STRD : AI3str<0b1111, (outs), (ins GPR:$Rt, GPR:$src2, addrmode3:$addr),
2503 StMiscFrm, IIC_iStore_d_r,
2504 "strd", "\t$Rt, $src2, $addr", []>,
2505 Requires<[IsARM, HasV5TE]> {
2510 multiclass AI2_stridx<bit isByte, string opc,
2511 InstrItinClass iii, InstrItinClass iir> {
2512 def _PRE_IMM : AI2ldstidx<0, isByte, 1, (outs GPR:$Rn_wb),
2513 (ins GPR:$Rt, addrmode_imm12:$addr), IndexModePre,
2515 opc, "\t$Rt, $addr!", "$addr.base = $Rn_wb", []> {
2518 let Inst{23} = addr{12}; // U (add = ('U' == 1))
2519 let Inst{19-16} = addr{16-13}; // Rn
2520 let Inst{11-0} = addr{11-0}; // imm12
2521 let AsmMatchConverter = "cvtStWriteBackRegAddrModeImm12";
2522 let DecoderMethod = "DecodeSTRPreImm";
2525 def _PRE_REG : AI2ldstidx<0, isByte, 1, (outs GPR:$Rn_wb),
2526 (ins GPR:$Rt, ldst_so_reg:$addr),
2527 IndexModePre, StFrm, iir,
2528 opc, "\t$Rt, $addr!", "$addr.base = $Rn_wb", []> {
2531 let Inst{23} = addr{12}; // U (add = ('U' == 1))
2532 let Inst{19-16} = addr{16-13}; // Rn
2533 let Inst{11-0} = addr{11-0};
2534 let Inst{4} = 0; // Inst{4} = 0
2535 let AsmMatchConverter = "cvtStWriteBackRegAddrMode2";
2536 let DecoderMethod = "DecodeSTRPreReg";
2538 def _POST_REG : AI2ldstidx<0, isByte, 0, (outs GPR:$Rn_wb),
2539 (ins GPR:$Rt, addr_offset_none:$addr, am2offset_reg:$offset),
2540 IndexModePost, StFrm, iir,
2541 opc, "\t$Rt, $addr, $offset",
2542 "$addr.base = $Rn_wb", []> {
2548 let Inst{23} = offset{12};
2549 let Inst{19-16} = addr;
2550 let Inst{11-0} = offset{11-0};
2552 let DecoderMethod = "DecodeAddrMode2IdxInstruction";
2555 def _POST_IMM : AI2ldstidx<0, isByte, 0, (outs GPR:$Rn_wb),
2556 (ins GPR:$Rt, addr_offset_none:$addr, am2offset_imm:$offset),
2557 IndexModePost, StFrm, iii,
2558 opc, "\t$Rt, $addr, $offset",
2559 "$addr.base = $Rn_wb", []> {
2565 let Inst{23} = offset{12};
2566 let Inst{19-16} = addr;
2567 let Inst{11-0} = offset{11-0};
2569 let DecoderMethod = "DecodeAddrMode2IdxInstruction";
2573 let mayStore = 1, neverHasSideEffects = 1 in {
2574 // FIXME: for STR_PRE_REG etc. the itineray should be either IIC_iStore_ru or
2575 // IIC_iStore_siu depending on whether it the offset register is shifted.
2576 defm STR : AI2_stridx<0, "str", IIC_iStore_iu, IIC_iStore_ru>;
2577 defm STRB : AI2_stridx<1, "strb", IIC_iStore_bh_iu, IIC_iStore_bh_ru>;
2580 def : ARMPat<(post_store GPR:$Rt, addr_offset_none:$addr,
2581 am2offset_reg:$offset),
2582 (STR_POST_REG GPR:$Rt, addr_offset_none:$addr,
2583 am2offset_reg:$offset)>;
2584 def : ARMPat<(post_store GPR:$Rt, addr_offset_none:$addr,
2585 am2offset_imm:$offset),
2586 (STR_POST_IMM GPR:$Rt, addr_offset_none:$addr,
2587 am2offset_imm:$offset)>;
2588 def : ARMPat<(post_truncsti8 GPR:$Rt, addr_offset_none:$addr,
2589 am2offset_reg:$offset),
2590 (STRB_POST_REG GPR:$Rt, addr_offset_none:$addr,
2591 am2offset_reg:$offset)>;
2592 def : ARMPat<(post_truncsti8 GPR:$Rt, addr_offset_none:$addr,
2593 am2offset_imm:$offset),
2594 (STRB_POST_IMM GPR:$Rt, addr_offset_none:$addr,
2595 am2offset_imm:$offset)>;
2597 // Pseudo-instructions for pattern matching the pre-indexed stores. We can't
2598 // put the patterns on the instruction definitions directly as ISel wants
2599 // the address base and offset to be separate operands, not a single
2600 // complex operand like we represent the instructions themselves. The
2601 // pseudos map between the two.
2602 let usesCustomInserter = 1,
2603 Constraints = "$Rn = $Rn_wb,@earlyclobber $Rn_wb" in {
2604 def STRi_preidx: ARMPseudoInst<(outs GPR:$Rn_wb),
2605 (ins GPR:$Rt, GPR:$Rn, am2offset_imm:$offset, pred:$p),
2608 (pre_store GPR:$Rt, GPR:$Rn, am2offset_imm:$offset))]>;
2609 def STRr_preidx: ARMPseudoInst<(outs GPR:$Rn_wb),
2610 (ins GPR:$Rt, GPR:$Rn, am2offset_reg:$offset, pred:$p),
2613 (pre_store GPR:$Rt, GPR:$Rn, am2offset_reg:$offset))]>;
2614 def STRBi_preidx: ARMPseudoInst<(outs GPR:$Rn_wb),
2615 (ins GPR:$Rt, GPR:$Rn, am2offset_imm:$offset, pred:$p),
2618 (pre_truncsti8 GPR:$Rt, GPR:$Rn, am2offset_imm:$offset))]>;
2619 def STRBr_preidx: ARMPseudoInst<(outs GPR:$Rn_wb),
2620 (ins GPR:$Rt, GPR:$Rn, am2offset_reg:$offset, pred:$p),
2623 (pre_truncsti8 GPR:$Rt, GPR:$Rn, am2offset_reg:$offset))]>;
2624 def STRH_preidx: ARMPseudoInst<(outs GPR:$Rn_wb),
2625 (ins GPR:$Rt, GPR:$Rn, am3offset:$offset, pred:$p),
2628 (pre_truncsti16 GPR:$Rt, GPR:$Rn, am3offset:$offset))]>;
2633 def STRH_PRE : AI3ldstidx<0b1011, 0, 1, (outs GPR:$Rn_wb),
2634 (ins GPR:$Rt, addrmode3:$addr), IndexModePre,
2635 StMiscFrm, IIC_iStore_bh_ru,
2636 "strh", "\t$Rt, $addr!", "$addr.base = $Rn_wb", []> {
2638 let Inst{23} = addr{8}; // U bit
2639 let Inst{22} = addr{13}; // 1 == imm8, 0 == Rm
2640 let Inst{19-16} = addr{12-9}; // Rn
2641 let Inst{11-8} = addr{7-4}; // imm7_4/zero
2642 let Inst{3-0} = addr{3-0}; // imm3_0/Rm
2643 let AsmMatchConverter = "cvtStWriteBackRegAddrMode3";
2644 let DecoderMethod = "DecodeAddrMode3Instruction";
2647 def STRH_POST : AI3ldstidx<0b1011, 0, 0, (outs GPR:$Rn_wb),
2648 (ins GPR:$Rt, addr_offset_none:$addr, am3offset:$offset),
2649 IndexModePost, StMiscFrm, IIC_iStore_bh_ru,
2650 "strh", "\t$Rt, $addr, $offset", "$addr.base = $Rn_wb",
2651 [(set GPR:$Rn_wb, (post_truncsti16 GPR:$Rt,
2652 addr_offset_none:$addr,
2653 am3offset:$offset))]> {
2656 let Inst{23} = offset{8}; // U bit
2657 let Inst{22} = offset{9}; // 1 == imm8, 0 == Rm
2658 let Inst{19-16} = addr;
2659 let Inst{11-8} = offset{7-4}; // imm7_4/zero
2660 let Inst{3-0} = offset{3-0}; // imm3_0/Rm
2661 let DecoderMethod = "DecodeAddrMode3Instruction";
2664 let mayStore = 1, neverHasSideEffects = 1, hasExtraSrcRegAllocReq = 1 in {
2665 def STRD_PRE : AI3ldstidx<0b1111, 0, 1, (outs GPR:$Rn_wb),
2666 (ins GPR:$Rt, GPR:$Rt2, addrmode3:$addr),
2667 IndexModePre, StMiscFrm, IIC_iStore_d_ru,
2668 "strd", "\t$Rt, $Rt2, $addr!",
2669 "$addr.base = $Rn_wb", []> {
2671 let Inst{23} = addr{8}; // U bit
2672 let Inst{22} = addr{13}; // 1 == imm8, 0 == Rm
2673 let Inst{19-16} = addr{12-9}; // Rn
2674 let Inst{11-8} = addr{7-4}; // imm7_4/zero
2675 let Inst{3-0} = addr{3-0}; // imm3_0/Rm
2676 let DecoderMethod = "DecodeAddrMode3Instruction";
2677 let AsmMatchConverter = "cvtStrdPre";
2680 def STRD_POST: AI3ldstidx<0b1111, 0, 0, (outs GPR:$Rn_wb),
2681 (ins GPR:$Rt, GPR:$Rt2, addr_offset_none:$addr,
2683 IndexModePost, StMiscFrm, IIC_iStore_d_ru,
2684 "strd", "\t$Rt, $Rt2, $addr, $offset",
2685 "$addr.base = $Rn_wb", []> {
2688 let Inst{23} = offset{8}; // U bit
2689 let Inst{22} = offset{9}; // 1 == imm8, 0 == Rm
2690 let Inst{19-16} = addr;
2691 let Inst{11-8} = offset{7-4}; // imm7_4/zero
2692 let Inst{3-0} = offset{3-0}; // imm3_0/Rm
2693 let DecoderMethod = "DecodeAddrMode3Instruction";
2695 } // mayStore = 1, neverHasSideEffects = 1, hasExtraSrcRegAllocReq = 1
2697 // STRT, STRBT, and STRHT
2699 def STRBT_POST_REG : AI2ldstidx<0, 1, 0, (outs GPR:$Rn_wb),
2700 (ins GPR:$Rt, addr_offset_none:$addr, am2offset_reg:$offset),
2701 IndexModePost, StFrm, IIC_iStore_bh_ru,
2702 "strbt", "\t$Rt, $addr, $offset",
2703 "$addr.base = $Rn_wb", []> {
2709 let Inst{23} = offset{12};
2710 let Inst{21} = 1; // overwrite
2711 let Inst{19-16} = addr;
2712 let Inst{11-5} = offset{11-5};
2714 let Inst{3-0} = offset{3-0};
2715 let DecoderMethod = "DecodeAddrMode2IdxInstruction";
2718 def STRBT_POST_IMM : AI2ldstidx<0, 1, 0, (outs GPR:$Rn_wb),
2719 (ins GPR:$Rt, addr_offset_none:$addr, am2offset_imm:$offset),
2720 IndexModePost, StFrm, IIC_iStore_bh_ru,
2721 "strbt", "\t$Rt, $addr, $offset",
2722 "$addr.base = $Rn_wb", []> {
2728 let Inst{23} = offset{12};
2729 let Inst{21} = 1; // overwrite
2730 let Inst{19-16} = addr;
2731 let Inst{11-0} = offset{11-0};
2732 let DecoderMethod = "DecodeAddrMode2IdxInstruction";
2735 let mayStore = 1, neverHasSideEffects = 1 in {
2736 def STRT_POST_REG : AI2ldstidx<0, 0, 0, (outs GPR:$Rn_wb),
2737 (ins GPR:$Rt, addr_offset_none:$addr, am2offset_reg:$offset),
2738 IndexModePost, StFrm, IIC_iStore_ru,
2739 "strt", "\t$Rt, $addr, $offset",
2740 "$addr.base = $Rn_wb", []> {
2746 let Inst{23} = offset{12};
2747 let Inst{21} = 1; // overwrite
2748 let Inst{19-16} = addr;
2749 let Inst{11-5} = offset{11-5};
2751 let Inst{3-0} = offset{3-0};
2752 let DecoderMethod = "DecodeAddrMode2IdxInstruction";
2755 def STRT_POST_IMM : AI2ldstidx<0, 0, 0, (outs GPR:$Rn_wb),
2756 (ins GPR:$Rt, addr_offset_none:$addr, am2offset_imm:$offset),
2757 IndexModePost, StFrm, IIC_iStore_ru,
2758 "strt", "\t$Rt, $addr, $offset",
2759 "$addr.base = $Rn_wb", []> {
2765 let Inst{23} = offset{12};
2766 let Inst{21} = 1; // overwrite
2767 let Inst{19-16} = addr;
2768 let Inst{11-0} = offset{11-0};
2769 let DecoderMethod = "DecodeAddrMode2IdxInstruction";
2774 multiclass AI3strT<bits<4> op, string opc> {
2775 def i : AI3ldstidxT<op, 0, (outs GPR:$base_wb),
2776 (ins GPR:$Rt, addr_offset_none:$addr, postidx_imm8:$offset),
2777 IndexModePost, StMiscFrm, IIC_iStore_bh_ru, opc,
2778 "\t$Rt, $addr, $offset", "$addr.base = $base_wb", []> {
2780 let Inst{23} = offset{8};
2782 let Inst{11-8} = offset{7-4};
2783 let Inst{3-0} = offset{3-0};
2784 let AsmMatchConverter = "cvtStExtTWriteBackImm";
2786 def r : AI3ldstidxT<op, 0, (outs GPR:$base_wb),
2787 (ins GPR:$Rt, addr_offset_none:$addr, postidx_reg:$Rm),
2788 IndexModePost, StMiscFrm, IIC_iStore_bh_ru, opc,
2789 "\t$Rt, $addr, $Rm", "$addr.base = $base_wb", []> {
2791 let Inst{23} = Rm{4};
2794 let Inst{3-0} = Rm{3-0};
2795 let AsmMatchConverter = "cvtStExtTWriteBackReg";
2800 defm STRHT : AI3strT<0b1011, "strht">;
2803 //===----------------------------------------------------------------------===//
2804 // Load / store multiple Instructions.
2807 multiclass arm_ldst_mult<string asm, string sfx, bit L_bit, bit P_bit, Format f,
2808 InstrItinClass itin, InstrItinClass itin_upd> {
2809 // IA is the default, so no need for an explicit suffix on the
2810 // mnemonic here. Without it is the cannonical spelling.
2812 AXI4<(outs), (ins GPR:$Rn, pred:$p, reglist:$regs, variable_ops),
2813 IndexModeNone, f, itin,
2814 !strconcat(asm, "${p}\t$Rn, $regs", sfx), "", []> {
2815 let Inst{24-23} = 0b01; // Increment After
2816 let Inst{22} = P_bit;
2817 let Inst{21} = 0; // No writeback
2818 let Inst{20} = L_bit;
2821 AXI4<(outs GPR:$wb), (ins GPR:$Rn, pred:$p, reglist:$regs, variable_ops),
2822 IndexModeUpd, f, itin_upd,
2823 !strconcat(asm, "${p}\t$Rn!, $regs", sfx), "$Rn = $wb", []> {
2824 let Inst{24-23} = 0b01; // Increment After
2825 let Inst{22} = P_bit;
2826 let Inst{21} = 1; // Writeback
2827 let Inst{20} = L_bit;
2829 let DecoderMethod = "DecodeMemMultipleWritebackInstruction";
2832 AXI4<(outs), (ins GPR:$Rn, pred:$p, reglist:$regs, variable_ops),
2833 IndexModeNone, f, itin,
2834 !strconcat(asm, "da${p}\t$Rn, $regs", sfx), "", []> {
2835 let Inst{24-23} = 0b00; // Decrement After
2836 let Inst{22} = P_bit;
2837 let Inst{21} = 0; // No writeback
2838 let Inst{20} = L_bit;
2841 AXI4<(outs GPR:$wb), (ins GPR:$Rn, pred:$p, reglist:$regs, variable_ops),
2842 IndexModeUpd, f, itin_upd,
2843 !strconcat(asm, "da${p}\t$Rn!, $regs", sfx), "$Rn = $wb", []> {
2844 let Inst{24-23} = 0b00; // Decrement After
2845 let Inst{22} = P_bit;
2846 let Inst{21} = 1; // Writeback
2847 let Inst{20} = L_bit;
2849 let DecoderMethod = "DecodeMemMultipleWritebackInstruction";
2852 AXI4<(outs), (ins GPR:$Rn, pred:$p, reglist:$regs, variable_ops),
2853 IndexModeNone, f, itin,
2854 !strconcat(asm, "db${p}\t$Rn, $regs", sfx), "", []> {
2855 let Inst{24-23} = 0b10; // Decrement Before
2856 let Inst{22} = P_bit;
2857 let Inst{21} = 0; // No writeback
2858 let Inst{20} = L_bit;
2861 AXI4<(outs GPR:$wb), (ins GPR:$Rn, pred:$p, reglist:$regs, variable_ops),
2862 IndexModeUpd, f, itin_upd,
2863 !strconcat(asm, "db${p}\t$Rn!, $regs", sfx), "$Rn = $wb", []> {
2864 let Inst{24-23} = 0b10; // Decrement Before
2865 let Inst{22} = P_bit;
2866 let Inst{21} = 1; // Writeback
2867 let Inst{20} = L_bit;
2869 let DecoderMethod = "DecodeMemMultipleWritebackInstruction";
2872 AXI4<(outs), (ins GPR:$Rn, pred:$p, reglist:$regs, variable_ops),
2873 IndexModeNone, f, itin,
2874 !strconcat(asm, "ib${p}\t$Rn, $regs", sfx), "", []> {
2875 let Inst{24-23} = 0b11; // Increment Before
2876 let Inst{22} = P_bit;
2877 let Inst{21} = 0; // No writeback
2878 let Inst{20} = L_bit;
2881 AXI4<(outs GPR:$wb), (ins GPR:$Rn, pred:$p, reglist:$regs, variable_ops),
2882 IndexModeUpd, f, itin_upd,
2883 !strconcat(asm, "ib${p}\t$Rn!, $regs", sfx), "$Rn = $wb", []> {
2884 let Inst{24-23} = 0b11; // Increment Before
2885 let Inst{22} = P_bit;
2886 let Inst{21} = 1; // Writeback
2887 let Inst{20} = L_bit;
2889 let DecoderMethod = "DecodeMemMultipleWritebackInstruction";
2893 let neverHasSideEffects = 1 in {
2895 let mayLoad = 1, hasExtraDefRegAllocReq = 1 in
2896 defm LDM : arm_ldst_mult<"ldm", "", 1, 0, LdStMulFrm, IIC_iLoad_m,
2899 let mayStore = 1, hasExtraSrcRegAllocReq = 1 in
2900 defm STM : arm_ldst_mult<"stm", "", 0, 0, LdStMulFrm, IIC_iStore_m,
2903 } // neverHasSideEffects
2905 // FIXME: remove when we have a way to marking a MI with these properties.
2906 // FIXME: Should pc be an implicit operand like PICADD, etc?
2907 let isReturn = 1, isTerminator = 1, isBarrier = 1, mayLoad = 1,
2908 hasExtraDefRegAllocReq = 1, isCodeGenOnly = 1 in
2909 def LDMIA_RET : ARMPseudoExpand<(outs GPR:$wb), (ins GPR:$Rn, pred:$p,
2910 reglist:$regs, variable_ops),
2911 4, IIC_iLoad_mBr, [],
2912 (LDMIA_UPD GPR:$wb, GPR:$Rn, pred:$p, reglist:$regs)>,
2913 RegConstraint<"$Rn = $wb">;
2915 let mayLoad = 1, hasExtraDefRegAllocReq = 1 in
2916 defm sysLDM : arm_ldst_mult<"ldm", " ^", 1, 1, LdStMulFrm, IIC_iLoad_m,
2919 let mayStore = 1, hasExtraSrcRegAllocReq = 1 in
2920 defm sysSTM : arm_ldst_mult<"stm", " ^", 0, 1, LdStMulFrm, IIC_iStore_m,
2925 //===----------------------------------------------------------------------===//
2926 // Move Instructions.
2929 let neverHasSideEffects = 1 in
2930 def MOVr : AsI1<0b1101, (outs GPR:$Rd), (ins GPR:$Rm), DPFrm, IIC_iMOVr,
2931 "mov", "\t$Rd, $Rm", []>, UnaryDP {
2935 let Inst{19-16} = 0b0000;
2936 let Inst{11-4} = 0b00000000;
2939 let Inst{15-12} = Rd;
2942 def : ARMInstAlias<"movs${p} $Rd, $Rm",
2943 (MOVr GPR:$Rd, GPR:$Rm, pred:$p, CPSR)>;
2945 // A version for the smaller set of tail call registers.
2946 let neverHasSideEffects = 1 in
2947 def MOVr_TC : AsI1<0b1101, (outs tcGPR:$Rd), (ins tcGPR:$Rm), DPFrm,
2948 IIC_iMOVr, "mov", "\t$Rd, $Rm", []>, UnaryDP {
2952 let Inst{11-4} = 0b00000000;
2955 let Inst{15-12} = Rd;
2958 def MOVsr : AsI1<0b1101, (outs GPRnopc:$Rd), (ins shift_so_reg_reg:$src),
2959 DPSoRegRegFrm, IIC_iMOVsr,
2960 "mov", "\t$Rd, $src",
2961 [(set GPRnopc:$Rd, shift_so_reg_reg:$src)]>, UnaryDP {
2964 let Inst{15-12} = Rd;
2965 let Inst{19-16} = 0b0000;
2966 let Inst{11-8} = src{11-8};
2968 let Inst{6-5} = src{6-5};
2970 let Inst{3-0} = src{3-0};
2974 def MOVsi : AsI1<0b1101, (outs GPR:$Rd), (ins shift_so_reg_imm:$src),
2975 DPSoRegImmFrm, IIC_iMOVsr,
2976 "mov", "\t$Rd, $src", [(set GPR:$Rd, shift_so_reg_imm:$src)]>,
2980 let Inst{15-12} = Rd;
2981 let Inst{19-16} = 0b0000;
2982 let Inst{11-5} = src{11-5};
2984 let Inst{3-0} = src{3-0};
2988 let isReMaterializable = 1, isAsCheapAsAMove = 1, isMoveImm = 1 in
2989 def MOVi : AsI1<0b1101, (outs GPR:$Rd), (ins so_imm:$imm), DPFrm, IIC_iMOVi,
2990 "mov", "\t$Rd, $imm", [(set GPR:$Rd, so_imm:$imm)]>, UnaryDP {
2994 let Inst{15-12} = Rd;
2995 let Inst{19-16} = 0b0000;
2996 let Inst{11-0} = imm;
2999 let isReMaterializable = 1, isAsCheapAsAMove = 1, isMoveImm = 1 in
3000 def MOVi16 : AI1<0b1000, (outs GPR:$Rd), (ins imm0_65535_expr:$imm),
3002 "movw", "\t$Rd, $imm",
3003 [(set GPR:$Rd, imm0_65535:$imm)]>,
3004 Requires<[IsARM, HasV6T2]>, UnaryDP {
3007 let Inst{15-12} = Rd;
3008 let Inst{11-0} = imm{11-0};
3009 let Inst{19-16} = imm{15-12};
3012 let DecoderMethod = "DecodeArmMOVTWInstruction";
3015 def : InstAlias<"mov${p} $Rd, $imm",
3016 (MOVi16 GPR:$Rd, imm0_65535_expr:$imm, pred:$p)>,
3019 def MOVi16_ga_pcrel : PseudoInst<(outs GPR:$Rd),
3020 (ins i32imm:$addr, pclabel:$id), IIC_iMOVi, []>;
3022 let Constraints = "$src = $Rd" in {
3023 def MOVTi16 : AI1<0b1010, (outs GPRnopc:$Rd),
3024 (ins GPR:$src, imm0_65535_expr:$imm),
3026 "movt", "\t$Rd, $imm",
3028 (or (and GPR:$src, 0xffff),
3029 lo16AllZero:$imm))]>, UnaryDP,
3030 Requires<[IsARM, HasV6T2]> {
3033 let Inst{15-12} = Rd;
3034 let Inst{11-0} = imm{11-0};
3035 let Inst{19-16} = imm{15-12};
3038 let DecoderMethod = "DecodeArmMOVTWInstruction";
3041 def MOVTi16_ga_pcrel : PseudoInst<(outs GPR:$Rd),
3042 (ins GPR:$src, i32imm:$addr, pclabel:$id), IIC_iMOVi, []>;
3046 def : ARMPat<(or GPR:$src, 0xffff0000), (MOVTi16 GPR:$src, 0xffff)>,
3047 Requires<[IsARM, HasV6T2]>;
3049 let Uses = [CPSR] in
3050 def RRX: PseudoInst<(outs GPR:$Rd), (ins GPR:$Rm), IIC_iMOVsi,
3051 [(set GPR:$Rd, (ARMrrx GPR:$Rm))]>, UnaryDP,
3054 // These aren't really mov instructions, but we have to define them this way
3055 // due to flag operands.
3057 let Defs = [CPSR] in {
3058 def MOVsrl_flag : PseudoInst<(outs GPR:$dst), (ins GPR:$src), IIC_iMOVsi,
3059 [(set GPR:$dst, (ARMsrl_flag GPR:$src))]>, UnaryDP,
3061 def MOVsra_flag : PseudoInst<(outs GPR:$dst), (ins GPR:$src), IIC_iMOVsi,
3062 [(set GPR:$dst, (ARMsra_flag GPR:$src))]>, UnaryDP,
3066 //===----------------------------------------------------------------------===//
3067 // Extend Instructions.
3072 def SXTB : AI_ext_rrot<0b01101010,
3073 "sxtb", UnOpFrag<(sext_inreg node:$Src, i8)>>;
3074 def SXTH : AI_ext_rrot<0b01101011,
3075 "sxth", UnOpFrag<(sext_inreg node:$Src, i16)>>;
3077 def SXTAB : AI_exta_rrot<0b01101010,
3078 "sxtab", BinOpFrag<(add node:$LHS, (sext_inreg node:$RHS, i8))>>;
3079 def SXTAH : AI_exta_rrot<0b01101011,
3080 "sxtah", BinOpFrag<(add node:$LHS, (sext_inreg node:$RHS,i16))>>;
3082 def SXTB16 : AI_ext_rrot_np<0b01101000, "sxtb16">;
3084 def SXTAB16 : AI_exta_rrot_np<0b01101000, "sxtab16">;
3088 let AddedComplexity = 16 in {
3089 def UXTB : AI_ext_rrot<0b01101110,
3090 "uxtb" , UnOpFrag<(and node:$Src, 0x000000FF)>>;
3091 def UXTH : AI_ext_rrot<0b01101111,
3092 "uxth" , UnOpFrag<(and node:$Src, 0x0000FFFF)>>;
3093 def UXTB16 : AI_ext_rrot<0b01101100,
3094 "uxtb16", UnOpFrag<(and node:$Src, 0x00FF00FF)>>;
3096 // FIXME: This pattern incorrectly assumes the shl operator is a rotate.
3097 // The transformation should probably be done as a combiner action
3098 // instead so we can include a check for masking back in the upper
3099 // eight bits of the source into the lower eight bits of the result.
3100 //def : ARMV6Pat<(and (shl GPR:$Src, (i32 8)), 0xFF00FF),
3101 // (UXTB16r_rot GPR:$Src, 3)>;
3102 def : ARMV6Pat<(and (srl GPR:$Src, (i32 8)), 0xFF00FF),
3103 (UXTB16 GPR:$Src, 1)>;
3105 def UXTAB : AI_exta_rrot<0b01101110, "uxtab",
3106 BinOpFrag<(add node:$LHS, (and node:$RHS, 0x00FF))>>;
3107 def UXTAH : AI_exta_rrot<0b01101111, "uxtah",
3108 BinOpFrag<(add node:$LHS, (and node:$RHS, 0xFFFF))>>;
3111 // This isn't safe in general, the add is two 16-bit units, not a 32-bit add.
3112 def UXTAB16 : AI_exta_rrot_np<0b01101100, "uxtab16">;
3115 def SBFX : I<(outs GPRnopc:$Rd),
3116 (ins GPRnopc:$Rn, imm0_31:$lsb, imm1_32:$width),
3117 AddrMode1, 4, IndexModeNone, DPFrm, IIC_iUNAsi,
3118 "sbfx", "\t$Rd, $Rn, $lsb, $width", "", []>,
3119 Requires<[IsARM, HasV6T2]> {
3124 let Inst{27-21} = 0b0111101;
3125 let Inst{6-4} = 0b101;
3126 let Inst{20-16} = width;
3127 let Inst{15-12} = Rd;
3128 let Inst{11-7} = lsb;
3132 def UBFX : I<(outs GPR:$Rd),
3133 (ins GPR:$Rn, imm0_31:$lsb, imm1_32:$width),
3134 AddrMode1, 4, IndexModeNone, DPFrm, IIC_iUNAsi,
3135 "ubfx", "\t$Rd, $Rn, $lsb, $width", "", []>,
3136 Requires<[IsARM, HasV6T2]> {
3141 let Inst{27-21} = 0b0111111;
3142 let Inst{6-4} = 0b101;
3143 let Inst{20-16} = width;
3144 let Inst{15-12} = Rd;
3145 let Inst{11-7} = lsb;
3149 //===----------------------------------------------------------------------===//
3150 // Arithmetic Instructions.
3153 defm ADD : AsI1_bin_irs<0b0100, "add",
3154 IIC_iALUi, IIC_iALUr, IIC_iALUsr,
3155 BinOpFrag<(add node:$LHS, node:$RHS)>, "ADD", 1>;
3156 defm SUB : AsI1_bin_irs<0b0010, "sub",
3157 IIC_iALUi, IIC_iALUr, IIC_iALUsr,
3158 BinOpFrag<(sub node:$LHS, node:$RHS)>, "SUB">;
3160 // ADD and SUB with 's' bit set.
3162 // Currently, ADDS/SUBS are pseudo opcodes that exist only in the
3163 // selection DAG. They are "lowered" to real ADD/SUB opcodes by
3164 // AdjustInstrPostInstrSelection where we determine whether or not to
3165 // set the "s" bit based on CPSR liveness.
3167 // FIXME: Eliminate ADDS/SUBS pseudo opcodes after adding tablegen
3168 // support for an optional CPSR definition that corresponds to the DAG
3169 // node's second value. We can then eliminate the implicit def of CPSR.
3170 defm ADDS : AsI1_bin_s_irs<IIC_iALUi, IIC_iALUr, IIC_iALUsr,
3171 BinOpFrag<(ARMaddc node:$LHS, node:$RHS)>, 1>;
3172 defm SUBS : AsI1_bin_s_irs<IIC_iALUi, IIC_iALUr, IIC_iALUsr,
3173 BinOpFrag<(ARMsubc node:$LHS, node:$RHS)>>;
3175 defm ADC : AI1_adde_sube_irs<0b0101, "adc",
3176 BinOpWithFlagFrag<(ARMadde node:$LHS, node:$RHS, node:$FLAG)>,
3178 defm SBC : AI1_adde_sube_irs<0b0110, "sbc",
3179 BinOpWithFlagFrag<(ARMsube node:$LHS, node:$RHS, node:$FLAG)>,
3182 defm RSB : AsI1_rbin_irs <0b0011, "rsb",
3183 IIC_iALUi, IIC_iALUr, IIC_iALUsr,
3184 BinOpFrag<(sub node:$LHS, node:$RHS)>, "RSB">;
3186 // FIXME: Eliminate them if we can write def : Pat patterns which defines
3187 // CPSR and the implicit def of CPSR is not needed.
3188 defm RSBS : AsI1_rbin_s_is<IIC_iALUi, IIC_iALUr, IIC_iALUsr,
3189 BinOpFrag<(ARMsubc node:$LHS, node:$RHS)>>;
3191 defm RSC : AI1_rsc_irs<0b0111, "rsc",
3192 BinOpWithFlagFrag<(ARMsube node:$LHS, node:$RHS, node:$FLAG)>,
3195 // (sub X, imm) gets canonicalized to (add X, -imm). Match this form.
3196 // The assume-no-carry-in form uses the negation of the input since add/sub
3197 // assume opposite meanings of the carry flag (i.e., carry == !borrow).
3198 // See the definition of AddWithCarry() in the ARM ARM A2.2.1 for the gory
3200 def : ARMPat<(add GPR:$src, so_imm_neg:$imm),
3201 (SUBri GPR:$src, so_imm_neg:$imm)>;
3202 def : ARMPat<(ARMaddc GPR:$src, so_imm_neg:$imm),
3203 (SUBSri GPR:$src, so_imm_neg:$imm)>;
3205 // The with-carry-in form matches bitwise not instead of the negation.
3206 // Effectively, the inverse interpretation of the carry flag already accounts
3207 // for part of the negation.
3208 def : ARMPat<(ARMadde GPR:$src, so_imm_not:$imm, CPSR),
3209 (SBCri GPR:$src, so_imm_not:$imm)>;
3211 // Note: These are implemented in C++ code, because they have to generate
3212 // ADD/SUBrs instructions, which use a complex pattern that a xform function
3214 // (mul X, 2^n+1) -> (add (X << n), X)
3215 // (mul X, 2^n-1) -> (rsb X, (X << n))
3217 // ARM Arithmetic Instruction
3218 // GPR:$dst = GPR:$a op GPR:$b
3219 class AAI<bits<8> op27_20, bits<8> op11_4, string opc,
3220 list<dag> pattern = [],
3221 dag iops = (ins GPRnopc:$Rn, GPRnopc:$Rm),
3222 string asm = "\t$Rd, $Rn, $Rm">
3223 : AI<(outs GPRnopc:$Rd), iops, DPFrm, IIC_iALUr, opc, asm, pattern> {
3227 let Inst{27-20} = op27_20;
3228 let Inst{11-4} = op11_4;
3229 let Inst{19-16} = Rn;
3230 let Inst{15-12} = Rd;
3234 // Saturating add/subtract
3236 def QADD : AAI<0b00010000, 0b00000101, "qadd",
3237 [(set GPRnopc:$Rd, (int_arm_qadd GPRnopc:$Rm, GPRnopc:$Rn))],
3238 (ins GPRnopc:$Rm, GPRnopc:$Rn), "\t$Rd, $Rm, $Rn">;
3239 def QSUB : AAI<0b00010010, 0b00000101, "qsub",
3240 [(set GPRnopc:$Rd, (int_arm_qsub GPRnopc:$Rm, GPRnopc:$Rn))],
3241 (ins GPRnopc:$Rm, GPRnopc:$Rn), "\t$Rd, $Rm, $Rn">;
3242 def QDADD : AAI<0b00010100, 0b00000101, "qdadd", [],
3243 (ins GPRnopc:$Rm, GPRnopc:$Rn),
3245 def QDSUB : AAI<0b00010110, 0b00000101, "qdsub", [],
3246 (ins GPRnopc:$Rm, GPRnopc:$Rn),
3249 def QADD16 : AAI<0b01100010, 0b11110001, "qadd16">;
3250 def QADD8 : AAI<0b01100010, 0b11111001, "qadd8">;
3251 def QASX : AAI<0b01100010, 0b11110011, "qasx">;
3252 def QSAX : AAI<0b01100010, 0b11110101, "qsax">;
3253 def QSUB16 : AAI<0b01100010, 0b11110111, "qsub16">;
3254 def QSUB8 : AAI<0b01100010, 0b11111111, "qsub8">;
3255 def UQADD16 : AAI<0b01100110, 0b11110001, "uqadd16">;
3256 def UQADD8 : AAI<0b01100110, 0b11111001, "uqadd8">;
3257 def UQASX : AAI<0b01100110, 0b11110011, "uqasx">;
3258 def UQSAX : AAI<0b01100110, 0b11110101, "uqsax">;
3259 def UQSUB16 : AAI<0b01100110, 0b11110111, "uqsub16">;
3260 def UQSUB8 : AAI<0b01100110, 0b11111111, "uqsub8">;
3262 // Signed/Unsigned add/subtract
3264 def SASX : AAI<0b01100001, 0b11110011, "sasx">;
3265 def SADD16 : AAI<0b01100001, 0b11110001, "sadd16">;
3266 def SADD8 : AAI<0b01100001, 0b11111001, "sadd8">;
3267 def SSAX : AAI<0b01100001, 0b11110101, "ssax">;
3268 def SSUB16 : AAI<0b01100001, 0b11110111, "ssub16">;
3269 def SSUB8 : AAI<0b01100001, 0b11111111, "ssub8">;
3270 def UASX : AAI<0b01100101, 0b11110011, "uasx">;
3271 def UADD16 : AAI<0b01100101, 0b11110001, "uadd16">;
3272 def UADD8 : AAI<0b01100101, 0b11111001, "uadd8">;
3273 def USAX : AAI<0b01100101, 0b11110101, "usax">;
3274 def USUB16 : AAI<0b01100101, 0b11110111, "usub16">;
3275 def USUB8 : AAI<0b01100101, 0b11111111, "usub8">;
3277 // Signed/Unsigned halving add/subtract
3279 def SHASX : AAI<0b01100011, 0b11110011, "shasx">;
3280 def SHADD16 : AAI<0b01100011, 0b11110001, "shadd16">;
3281 def SHADD8 : AAI<0b01100011, 0b11111001, "shadd8">;
3282 def SHSAX : AAI<0b01100011, 0b11110101, "shsax">;
3283 def SHSUB16 : AAI<0b01100011, 0b11110111, "shsub16">;
3284 def SHSUB8 : AAI<0b01100011, 0b11111111, "shsub8">;
3285 def UHASX : AAI<0b01100111, 0b11110011, "uhasx">;
3286 def UHADD16 : AAI<0b01100111, 0b11110001, "uhadd16">;
3287 def UHADD8 : AAI<0b01100111, 0b11111001, "uhadd8">;
3288 def UHSAX : AAI<0b01100111, 0b11110101, "uhsax">;
3289 def UHSUB16 : AAI<0b01100111, 0b11110111, "uhsub16">;
3290 def UHSUB8 : AAI<0b01100111, 0b11111111, "uhsub8">;
3292 // Unsigned Sum of Absolute Differences [and Accumulate].
3294 def USAD8 : AI<(outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm),
3295 MulFrm /* for convenience */, NoItinerary, "usad8",
3296 "\t$Rd, $Rn, $Rm", []>,
3297 Requires<[IsARM, HasV6]> {
3301 let Inst{27-20} = 0b01111000;
3302 let Inst{15-12} = 0b1111;
3303 let Inst{7-4} = 0b0001;
3304 let Inst{19-16} = Rd;
3305 let Inst{11-8} = Rm;
3308 def USADA8 : AI<(outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm, GPR:$Ra),
3309 MulFrm /* for convenience */, NoItinerary, "usada8",
3310 "\t$Rd, $Rn, $Rm, $Ra", []>,
3311 Requires<[IsARM, HasV6]> {
3316 let Inst{27-20} = 0b01111000;
3317 let Inst{7-4} = 0b0001;
3318 let Inst{19-16} = Rd;
3319 let Inst{15-12} = Ra;
3320 let Inst{11-8} = Rm;
3324 // Signed/Unsigned saturate
3326 def SSAT : AI<(outs GPRnopc:$Rd),
3327 (ins imm1_32:$sat_imm, GPRnopc:$Rn, shift_imm:$sh),
3328 SatFrm, NoItinerary, "ssat", "\t$Rd, $sat_imm, $Rn$sh", []> {
3333 let Inst{27-21} = 0b0110101;
3334 let Inst{5-4} = 0b01;
3335 let Inst{20-16} = sat_imm;
3336 let Inst{15-12} = Rd;
3337 let Inst{11-7} = sh{4-0};
3338 let Inst{6} = sh{5};
3342 def SSAT16 : AI<(outs GPRnopc:$Rd),
3343 (ins imm1_16:$sat_imm, GPRnopc:$Rn), SatFrm,
3344 NoItinerary, "ssat16", "\t$Rd, $sat_imm, $Rn", []> {
3348 let Inst{27-20} = 0b01101010;
3349 let Inst{11-4} = 0b11110011;
3350 let Inst{15-12} = Rd;
3351 let Inst{19-16} = sat_imm;
3355 def USAT : AI<(outs GPRnopc:$Rd),
3356 (ins imm0_31:$sat_imm, GPRnopc:$Rn, shift_imm:$sh),
3357 SatFrm, NoItinerary, "usat", "\t$Rd, $sat_imm, $Rn$sh", []> {
3362 let Inst{27-21} = 0b0110111;
3363 let Inst{5-4} = 0b01;
3364 let Inst{15-12} = Rd;
3365 let Inst{11-7} = sh{4-0};
3366 let Inst{6} = sh{5};
3367 let Inst{20-16} = sat_imm;
3371 def USAT16 : AI<(outs GPRnopc:$Rd),
3372 (ins imm0_15:$sat_imm, GPRnopc:$Rn), SatFrm,
3373 NoItinerary, "usat16", "\t$Rd, $sat_imm, $Rn", []> {
3377 let Inst{27-20} = 0b01101110;
3378 let Inst{11-4} = 0b11110011;
3379 let Inst{15-12} = Rd;
3380 let Inst{19-16} = sat_imm;
3384 def : ARMV6Pat<(int_arm_ssat GPRnopc:$a, imm:$pos),
3385 (SSAT imm:$pos, GPRnopc:$a, 0)>;
3386 def : ARMV6Pat<(int_arm_usat GPRnopc:$a, imm:$pos),
3387 (USAT imm:$pos, GPRnopc:$a, 0)>;
3389 //===----------------------------------------------------------------------===//
3390 // Bitwise Instructions.
3393 defm AND : AsI1_bin_irs<0b0000, "and",
3394 IIC_iBITi, IIC_iBITr, IIC_iBITsr,
3395 BinOpFrag<(and node:$LHS, node:$RHS)>, "AND", 1>;
3396 defm ORR : AsI1_bin_irs<0b1100, "orr",
3397 IIC_iBITi, IIC_iBITr, IIC_iBITsr,
3398 BinOpFrag<(or node:$LHS, node:$RHS)>, "ORR", 1>;
3399 defm EOR : AsI1_bin_irs<0b0001, "eor",
3400 IIC_iBITi, IIC_iBITr, IIC_iBITsr,
3401 BinOpFrag<(xor node:$LHS, node:$RHS)>, "EOR", 1>;
3402 defm BIC : AsI1_bin_irs<0b1110, "bic",
3403 IIC_iBITi, IIC_iBITr, IIC_iBITsr,
3404 BinOpFrag<(and node:$LHS, (not node:$RHS))>, "BIC">;
3406 // FIXME: bf_inv_mask_imm should be two operands, the lsb and the msb, just
3407 // like in the actual instruction encoding. The complexity of mapping the mask
3408 // to the lsb/msb pair should be handled by ISel, not encapsulated in the
3409 // instruction description.
3410 def BFC : I<(outs GPR:$Rd), (ins GPR:$src, bf_inv_mask_imm:$imm),
3411 AddrMode1, 4, IndexModeNone, DPFrm, IIC_iUNAsi,
3412 "bfc", "\t$Rd, $imm", "$src = $Rd",
3413 [(set GPR:$Rd, (and GPR:$src, bf_inv_mask_imm:$imm))]>,
3414 Requires<[IsARM, HasV6T2]> {
3417 let Inst{27-21} = 0b0111110;
3418 let Inst{6-0} = 0b0011111;
3419 let Inst{15-12} = Rd;
3420 let Inst{11-7} = imm{4-0}; // lsb
3421 let Inst{20-16} = imm{9-5}; // msb
3424 // A8.6.18 BFI - Bitfield insert (Encoding A1)
3425 def BFI:I<(outs GPRnopc:$Rd), (ins GPRnopc:$src, GPR:$Rn, bf_inv_mask_imm:$imm),
3426 AddrMode1, 4, IndexModeNone, DPFrm, IIC_iUNAsi,
3427 "bfi", "\t$Rd, $Rn, $imm", "$src = $Rd",
3428 [(set GPRnopc:$Rd, (ARMbfi GPRnopc:$src, GPR:$Rn,
3429 bf_inv_mask_imm:$imm))]>,
3430 Requires<[IsARM, HasV6T2]> {
3434 let Inst{27-21} = 0b0111110;
3435 let Inst{6-4} = 0b001; // Rn: Inst{3-0} != 15
3436 let Inst{15-12} = Rd;
3437 let Inst{11-7} = imm{4-0}; // lsb
3438 let Inst{20-16} = imm{9-5}; // width
3442 def MVNr : AsI1<0b1111, (outs GPR:$Rd), (ins GPR:$Rm), DPFrm, IIC_iMVNr,
3443 "mvn", "\t$Rd, $Rm",
3444 [(set GPR:$Rd, (not GPR:$Rm))]>, UnaryDP {
3448 let Inst{19-16} = 0b0000;
3449 let Inst{11-4} = 0b00000000;
3450 let Inst{15-12} = Rd;
3453 def MVNsi : AsI1<0b1111, (outs GPR:$Rd), (ins so_reg_imm:$shift),
3454 DPSoRegImmFrm, IIC_iMVNsr, "mvn", "\t$Rd, $shift",
3455 [(set GPR:$Rd, (not so_reg_imm:$shift))]>, UnaryDP {
3459 let Inst{19-16} = 0b0000;
3460 let Inst{15-12} = Rd;
3461 let Inst{11-5} = shift{11-5};
3463 let Inst{3-0} = shift{3-0};
3465 def MVNsr : AsI1<0b1111, (outs GPR:$Rd), (ins so_reg_reg:$shift),
3466 DPSoRegRegFrm, IIC_iMVNsr, "mvn", "\t$Rd, $shift",
3467 [(set GPR:$Rd, (not so_reg_reg:$shift))]>, UnaryDP {
3471 let Inst{19-16} = 0b0000;
3472 let Inst{15-12} = Rd;
3473 let Inst{11-8} = shift{11-8};
3475 let Inst{6-5} = shift{6-5};
3477 let Inst{3-0} = shift{3-0};
3479 let isReMaterializable = 1, isAsCheapAsAMove = 1, isMoveImm = 1 in
3480 def MVNi : AsI1<0b1111, (outs GPR:$Rd), (ins so_imm:$imm), DPFrm,
3481 IIC_iMVNi, "mvn", "\t$Rd, $imm",
3482 [(set GPR:$Rd, so_imm_not:$imm)]>,UnaryDP {
3486 let Inst{19-16} = 0b0000;
3487 let Inst{15-12} = Rd;
3488 let Inst{11-0} = imm;
3491 def : ARMPat<(and GPR:$src, so_imm_not:$imm),
3492 (BICri GPR:$src, so_imm_not:$imm)>;
3494 //===----------------------------------------------------------------------===//
3495 // Multiply Instructions.
3497 class AsMul1I32<bits<7> opcod, dag oops, dag iops, InstrItinClass itin,
3498 string opc, string asm, list<dag> pattern>
3499 : AsMul1I<opcod, oops, iops, itin, opc, asm, pattern> {
3503 let Inst{19-16} = Rd;
3504 let Inst{11-8} = Rm;
3507 class AsMul1I64<bits<7> opcod, dag oops, dag iops, InstrItinClass itin,
3508 string opc, string asm, list<dag> pattern>
3509 : AsMul1I<opcod, oops, iops, itin, opc, asm, pattern> {
3514 let Inst{19-16} = RdHi;
3515 let Inst{15-12} = RdLo;
3516 let Inst{11-8} = Rm;
3520 // FIXME: The v5 pseudos are only necessary for the additional Constraint
3521 // property. Remove them when it's possible to add those properties
3522 // on an individual MachineInstr, not just an instuction description.
3523 let isCommutable = 1 in {
3524 def MUL : AsMul1I32<0b0000000, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm),
3525 IIC_iMUL32, "mul", "\t$Rd, $Rn, $Rm",
3526 [(set GPR:$Rd, (mul GPR:$Rn, GPR:$Rm))]>,
3527 Requires<[IsARM, HasV6]> {
3528 let Inst{15-12} = 0b0000;
3531 let Constraints = "@earlyclobber $Rd" in
3532 def MULv5: ARMPseudoExpand<(outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm,
3533 pred:$p, cc_out:$s),
3535 [(set GPR:$Rd, (mul GPR:$Rn, GPR:$Rm))],
3536 (MUL GPR:$Rd, GPR:$Rn, GPR:$Rm, pred:$p, cc_out:$s)>,
3537 Requires<[IsARM, NoV6]>;
3540 def MLA : AsMul1I32<0b0000001, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm, GPR:$Ra),
3541 IIC_iMAC32, "mla", "\t$Rd, $Rn, $Rm, $Ra",
3542 [(set GPR:$Rd, (add (mul GPR:$Rn, GPR:$Rm), GPR:$Ra))]>,
3543 Requires<[IsARM, HasV6]> {
3545 let Inst{15-12} = Ra;
3548 let Constraints = "@earlyclobber $Rd" in
3549 def MLAv5: ARMPseudoExpand<(outs GPR:$Rd),
3550 (ins GPR:$Rn, GPR:$Rm, GPR:$Ra, pred:$p, cc_out:$s),
3552 [(set GPR:$Rd, (add (mul GPR:$Rn, GPR:$Rm), GPR:$Ra))],
3553 (MLA GPR:$Rd, GPR:$Rn, GPR:$Rm, GPR:$Ra, pred:$p, cc_out:$s)>,
3554 Requires<[IsARM, NoV6]>;
3556 def MLS : AMul1I<0b0000011, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm, GPR:$Ra),
3557 IIC_iMAC32, "mls", "\t$Rd, $Rn, $Rm, $Ra",
3558 [(set GPR:$Rd, (sub GPR:$Ra, (mul GPR:$Rn, GPR:$Rm)))]>,
3559 Requires<[IsARM, HasV6T2]> {
3564 let Inst{19-16} = Rd;
3565 let Inst{15-12} = Ra;
3566 let Inst{11-8} = Rm;
3570 // Extra precision multiplies with low / high results
3571 let neverHasSideEffects = 1 in {
3572 let isCommutable = 1 in {
3573 def SMULL : AsMul1I64<0b0000110, (outs GPR:$RdLo, GPR:$RdHi),
3574 (ins GPR:$Rn, GPR:$Rm), IIC_iMUL64,
3575 "smull", "\t$RdLo, $RdHi, $Rn, $Rm", []>,
3576 Requires<[IsARM, HasV6]>;
3578 def UMULL : AsMul1I64<0b0000100, (outs GPR:$RdLo, GPR:$RdHi),
3579 (ins GPR:$Rn, GPR:$Rm), IIC_iMUL64,
3580 "umull", "\t$RdLo, $RdHi, $Rn, $Rm", []>,
3581 Requires<[IsARM, HasV6]>;
3583 let Constraints = "@earlyclobber $RdLo,@earlyclobber $RdHi" in {
3584 def SMULLv5 : ARMPseudoExpand<(outs GPR:$RdLo, GPR:$RdHi),
3585 (ins GPR:$Rn, GPR:$Rm, pred:$p, cc_out:$s),
3587 (SMULL GPR:$RdLo, GPR:$RdHi, GPR:$Rn, GPR:$Rm, pred:$p, cc_out:$s)>,
3588 Requires<[IsARM, NoV6]>;
3590 def UMULLv5 : ARMPseudoExpand<(outs GPR:$RdLo, GPR:$RdHi),
3591 (ins GPR:$Rn, GPR:$Rm, pred:$p, cc_out:$s),
3593 (UMULL GPR:$RdLo, GPR:$RdHi, GPR:$Rn, GPR:$Rm, pred:$p, cc_out:$s)>,
3594 Requires<[IsARM, NoV6]>;
3598 // Multiply + accumulate
3599 def SMLAL : AsMul1I64<0b0000111, (outs GPR:$RdLo, GPR:$RdHi),
3600 (ins GPR:$Rn, GPR:$Rm), IIC_iMAC64,
3601 "smlal", "\t$RdLo, $RdHi, $Rn, $Rm", []>,
3602 Requires<[IsARM, HasV6]>;
3603 def UMLAL : AsMul1I64<0b0000101, (outs GPR:$RdLo, GPR:$RdHi),
3604 (ins GPR:$Rn, GPR:$Rm), IIC_iMAC64,
3605 "umlal", "\t$RdLo, $RdHi, $Rn, $Rm", []>,
3606 Requires<[IsARM, HasV6]>;
3608 def UMAAL : AMul1I <0b0000010, (outs GPR:$RdLo, GPR:$RdHi),
3609 (ins GPR:$Rn, GPR:$Rm), IIC_iMAC64,
3610 "umaal", "\t$RdLo, $RdHi, $Rn, $Rm", []>,
3611 Requires<[IsARM, HasV6]> {
3616 let Inst{19-16} = RdHi;
3617 let Inst{15-12} = RdLo;
3618 let Inst{11-8} = Rm;
3622 let Constraints = "@earlyclobber $RdLo,@earlyclobber $RdHi" in {
3623 def SMLALv5 : ARMPseudoExpand<(outs GPR:$RdLo, GPR:$RdHi),
3624 (ins GPR:$Rn, GPR:$Rm, pred:$p, cc_out:$s),
3626 (SMLAL GPR:$RdLo, GPR:$RdHi, GPR:$Rn, GPR:$Rm, pred:$p, cc_out:$s)>,
3627 Requires<[IsARM, NoV6]>;
3628 def UMLALv5 : ARMPseudoExpand<(outs GPR:$RdLo, GPR:$RdHi),
3629 (ins GPR:$Rn, GPR:$Rm, pred:$p, cc_out:$s),
3631 (UMLAL GPR:$RdLo, GPR:$RdHi, GPR:$Rn, GPR:$Rm, pred:$p, cc_out:$s)>,
3632 Requires<[IsARM, NoV6]>;
3633 def UMAALv5 : ARMPseudoExpand<(outs GPR:$RdLo, GPR:$RdHi),
3634 (ins GPR:$Rn, GPR:$Rm, pred:$p),
3636 (UMAAL GPR:$RdLo, GPR:$RdHi, GPR:$Rn, GPR:$Rm, pred:$p)>,
3637 Requires<[IsARM, NoV6]>;
3640 } // neverHasSideEffects
3642 // Most significant word multiply
3643 def SMMUL : AMul2I <0b0111010, 0b0001, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm),
3644 IIC_iMUL32, "smmul", "\t$Rd, $Rn, $Rm",
3645 [(set GPR:$Rd, (mulhs GPR:$Rn, GPR:$Rm))]>,
3646 Requires<[IsARM, HasV6]> {
3647 let Inst{15-12} = 0b1111;
3650 def SMMULR : AMul2I <0b0111010, 0b0011, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm),
3651 IIC_iMUL32, "smmulr", "\t$Rd, $Rn, $Rm", []>,
3652 Requires<[IsARM, HasV6]> {
3653 let Inst{15-12} = 0b1111;
3656 def SMMLA : AMul2Ia <0b0111010, 0b0001, (outs GPR:$Rd),
3657 (ins GPR:$Rn, GPR:$Rm, GPR:$Ra),
3658 IIC_iMAC32, "smmla", "\t$Rd, $Rn, $Rm, $Ra",
3659 [(set GPR:$Rd, (add (mulhs GPR:$Rn, GPR:$Rm), GPR:$Ra))]>,
3660 Requires<[IsARM, HasV6]>;
3662 def SMMLAR : AMul2Ia <0b0111010, 0b0011, (outs GPR:$Rd),
3663 (ins GPR:$Rn, GPR:$Rm, GPR:$Ra),
3664 IIC_iMAC32, "smmlar", "\t$Rd, $Rn, $Rm, $Ra", []>,
3665 Requires<[IsARM, HasV6]>;
3667 def SMMLS : AMul2Ia <0b0111010, 0b1101, (outs GPR:$Rd),
3668 (ins GPR:$Rn, GPR:$Rm, GPR:$Ra),
3669 IIC_iMAC32, "smmls", "\t$Rd, $Rn, $Rm, $Ra",
3670 [(set GPR:$Rd, (sub GPR:$Ra, (mulhs GPR:$Rn, GPR:$Rm)))]>,
3671 Requires<[IsARM, HasV6]>;
3673 def SMMLSR : AMul2Ia <0b0111010, 0b1111, (outs GPR:$Rd),
3674 (ins GPR:$Rn, GPR:$Rm, GPR:$Ra),
3675 IIC_iMAC32, "smmlsr", "\t$Rd, $Rn, $Rm, $Ra", []>,
3676 Requires<[IsARM, HasV6]>;
3678 multiclass AI_smul<string opc, PatFrag opnode> {
3679 def BB : AMulxyI<0b0001011, 0b00, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm),
3680 IIC_iMUL16, !strconcat(opc, "bb"), "\t$Rd, $Rn, $Rm",
3681 [(set GPR:$Rd, (opnode (sext_inreg GPR:$Rn, i16),
3682 (sext_inreg GPR:$Rm, i16)))]>,
3683 Requires<[IsARM, HasV5TE]>;
3685 def BT : AMulxyI<0b0001011, 0b10, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm),
3686 IIC_iMUL16, !strconcat(opc, "bt"), "\t$Rd, $Rn, $Rm",
3687 [(set GPR:$Rd, (opnode (sext_inreg GPR:$Rn, i16),
3688 (sra GPR:$Rm, (i32 16))))]>,
3689 Requires<[IsARM, HasV5TE]>;
3691 def TB : AMulxyI<0b0001011, 0b01, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm),
3692 IIC_iMUL16, !strconcat(opc, "tb"), "\t$Rd, $Rn, $Rm",
3693 [(set GPR:$Rd, (opnode (sra GPR:$Rn, (i32 16)),
3694 (sext_inreg GPR:$Rm, i16)))]>,
3695 Requires<[IsARM, HasV5TE]>;
3697 def TT : AMulxyI<0b0001011, 0b11, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm),
3698 IIC_iMUL16, !strconcat(opc, "tt"), "\t$Rd, $Rn, $Rm",
3699 [(set GPR:$Rd, (opnode (sra GPR:$Rn, (i32 16)),
3700 (sra GPR:$Rm, (i32 16))))]>,
3701 Requires<[IsARM, HasV5TE]>;
3703 def WB : AMulxyI<0b0001001, 0b01, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm),
3704 IIC_iMUL16, !strconcat(opc, "wb"), "\t$Rd, $Rn, $Rm",
3705 [(set GPR:$Rd, (sra (opnode GPR:$Rn,
3706 (sext_inreg GPR:$Rm, i16)), (i32 16)))]>,
3707 Requires<[IsARM, HasV5TE]>;
3709 def WT : AMulxyI<0b0001001, 0b11, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm),
3710 IIC_iMUL16, !strconcat(opc, "wt"), "\t$Rd, $Rn, $Rm",
3711 [(set GPR:$Rd, (sra (opnode GPR:$Rn,
3712 (sra GPR:$Rm, (i32 16))), (i32 16)))]>,
3713 Requires<[IsARM, HasV5TE]>;
3717 multiclass AI_smla<string opc, PatFrag opnode> {
3718 let DecoderMethod = "DecodeSMLAInstruction" in {
3719 def BB : AMulxyIa<0b0001000, 0b00, (outs GPRnopc:$Rd),
3720 (ins GPRnopc:$Rn, GPRnopc:$Rm, GPR:$Ra),
3721 IIC_iMAC16, !strconcat(opc, "bb"), "\t$Rd, $Rn, $Rm, $Ra",
3722 [(set GPRnopc:$Rd, (add GPR:$Ra,
3723 (opnode (sext_inreg GPRnopc:$Rn, i16),
3724 (sext_inreg GPRnopc:$Rm, i16))))]>,
3725 Requires<[IsARM, HasV5TE]>;
3727 def BT : AMulxyIa<0b0001000, 0b10, (outs GPRnopc:$Rd),
3728 (ins GPRnopc:$Rn, GPRnopc:$Rm, GPR:$Ra),
3729 IIC_iMAC16, !strconcat(opc, "bt"), "\t$Rd, $Rn, $Rm, $Ra",
3731 (add GPR:$Ra, (opnode (sext_inreg GPRnopc:$Rn, i16),
3732 (sra GPRnopc:$Rm, (i32 16)))))]>,
3733 Requires<[IsARM, HasV5TE]>;
3735 def TB : AMulxyIa<0b0001000, 0b01, (outs GPRnopc:$Rd),
3736 (ins GPRnopc:$Rn, GPRnopc:$Rm, GPR:$Ra),
3737 IIC_iMAC16, !strconcat(opc, "tb"), "\t$Rd, $Rn, $Rm, $Ra",
3739 (add GPR:$Ra, (opnode (sra GPRnopc:$Rn, (i32 16)),
3740 (sext_inreg GPRnopc:$Rm, i16))))]>,
3741 Requires<[IsARM, HasV5TE]>;
3743 def TT : AMulxyIa<0b0001000, 0b11, (outs GPRnopc:$Rd),
3744 (ins GPRnopc:$Rn, GPRnopc:$Rm, GPR:$Ra),
3745 IIC_iMAC16, !strconcat(opc, "tt"), "\t$Rd, $Rn, $Rm, $Ra",
3747 (add GPR:$Ra, (opnode (sra GPRnopc:$Rn, (i32 16)),
3748 (sra GPRnopc:$Rm, (i32 16)))))]>,
3749 Requires<[IsARM, HasV5TE]>;
3751 def WB : AMulxyIa<0b0001001, 0b00, (outs GPRnopc:$Rd),
3752 (ins GPRnopc:$Rn, GPRnopc:$Rm, GPR:$Ra),
3753 IIC_iMAC16, !strconcat(opc, "wb"), "\t$Rd, $Rn, $Rm, $Ra",
3755 (add GPR:$Ra, (sra (opnode GPRnopc:$Rn,
3756 (sext_inreg GPRnopc:$Rm, i16)), (i32 16))))]>,
3757 Requires<[IsARM, HasV5TE]>;
3759 def WT : AMulxyIa<0b0001001, 0b10, (outs GPRnopc:$Rd),
3760 (ins GPRnopc:$Rn, GPRnopc:$Rm, GPR:$Ra),
3761 IIC_iMAC16, !strconcat(opc, "wt"), "\t$Rd, $Rn, $Rm, $Ra",
3763 (add GPR:$Ra, (sra (opnode GPRnopc:$Rn,
3764 (sra GPRnopc:$Rm, (i32 16))), (i32 16))))]>,
3765 Requires<[IsARM, HasV5TE]>;
3769 defm SMUL : AI_smul<"smul", BinOpFrag<(mul node:$LHS, node:$RHS)>>;
3770 defm SMLA : AI_smla<"smla", BinOpFrag<(mul node:$LHS, node:$RHS)>>;
3772 // Halfword multiply accumulate long: SMLAL<x><y>.
3773 def SMLALBB : AMulxyI64<0b0001010, 0b00, (outs GPRnopc:$RdLo, GPRnopc:$RdHi),
3774 (ins GPRnopc:$Rn, GPRnopc:$Rm),
3775 IIC_iMAC64, "smlalbb", "\t$RdLo, $RdHi, $Rn, $Rm", []>,
3776 Requires<[IsARM, HasV5TE]>;
3778 def SMLALBT : AMulxyI64<0b0001010, 0b10, (outs GPRnopc:$RdLo, GPRnopc:$RdHi),
3779 (ins GPRnopc:$Rn, GPRnopc:$Rm),
3780 IIC_iMAC64, "smlalbt", "\t$RdLo, $RdHi, $Rn, $Rm", []>,
3781 Requires<[IsARM, HasV5TE]>;
3783 def SMLALTB : AMulxyI64<0b0001010, 0b01, (outs GPRnopc:$RdLo, GPRnopc:$RdHi),
3784 (ins GPRnopc:$Rn, GPRnopc:$Rm),
3785 IIC_iMAC64, "smlaltb", "\t$RdLo, $RdHi, $Rn, $Rm", []>,
3786 Requires<[IsARM, HasV5TE]>;
3788 def SMLALTT : AMulxyI64<0b0001010, 0b11, (outs GPRnopc:$RdLo, GPRnopc:$RdHi),
3789 (ins GPRnopc:$Rn, GPRnopc:$Rm),
3790 IIC_iMAC64, "smlaltt", "\t$RdLo, $RdHi, $Rn, $Rm", []>,
3791 Requires<[IsARM, HasV5TE]>;
3793 // Helper class for AI_smld.
3794 class AMulDualIbase<bit long, bit sub, bit swap, dag oops, dag iops,
3795 InstrItinClass itin, string opc, string asm>
3796 : AI<oops, iops, MulFrm, itin, opc, asm, []>, Requires<[IsARM, HasV6]> {
3799 let Inst{27-23} = 0b01110;
3800 let Inst{22} = long;
3801 let Inst{21-20} = 0b00;
3802 let Inst{11-8} = Rm;
3809 class AMulDualI<bit long, bit sub, bit swap, dag oops, dag iops,
3810 InstrItinClass itin, string opc, string asm>
3811 : AMulDualIbase<long, sub, swap, oops, iops, itin, opc, asm> {
3813 let Inst{15-12} = 0b1111;
3814 let Inst{19-16} = Rd;
3816 class AMulDualIa<bit long, bit sub, bit swap, dag oops, dag iops,
3817 InstrItinClass itin, string opc, string asm>
3818 : AMulDualIbase<long, sub, swap, oops, iops, itin, opc, asm> {
3821 let Inst{19-16} = Rd;
3822 let Inst{15-12} = Ra;
3824 class AMulDualI64<bit long, bit sub, bit swap, dag oops, dag iops,
3825 InstrItinClass itin, string opc, string asm>
3826 : AMulDualIbase<long, sub, swap, oops, iops, itin, opc, asm> {
3829 let Inst{19-16} = RdHi;
3830 let Inst{15-12} = RdLo;
3833 multiclass AI_smld<bit sub, string opc> {
3835 def D : AMulDualIa<0, sub, 0, (outs GPRnopc:$Rd),
3836 (ins GPRnopc:$Rn, GPRnopc:$Rm, GPR:$Ra),
3837 NoItinerary, !strconcat(opc, "d"), "\t$Rd, $Rn, $Rm, $Ra">;
3839 def DX: AMulDualIa<0, sub, 1, (outs GPRnopc:$Rd),
3840 (ins GPRnopc:$Rn, GPRnopc:$Rm, GPR:$Ra),
3841 NoItinerary, !strconcat(opc, "dx"), "\t$Rd, $Rn, $Rm, $Ra">;
3843 def LD: AMulDualI64<1, sub, 0, (outs GPRnopc:$RdLo, GPRnopc:$RdHi),
3844 (ins GPRnopc:$Rn, GPRnopc:$Rm), NoItinerary,
3845 !strconcat(opc, "ld"), "\t$RdLo, $RdHi, $Rn, $Rm">;
3847 def LDX : AMulDualI64<1, sub, 1, (outs GPRnopc:$RdLo, GPRnopc:$RdHi),
3848 (ins GPRnopc:$Rn, GPRnopc:$Rm), NoItinerary,
3849 !strconcat(opc, "ldx"),"\t$RdLo, $RdHi, $Rn, $Rm">;
3853 defm SMLA : AI_smld<0, "smla">;
3854 defm SMLS : AI_smld<1, "smls">;
3856 multiclass AI_sdml<bit sub, string opc> {
3858 def D:AMulDualI<0, sub, 0, (outs GPRnopc:$Rd), (ins GPRnopc:$Rn, GPRnopc:$Rm),
3859 NoItinerary, !strconcat(opc, "d"), "\t$Rd, $Rn, $Rm">;
3860 def DX:AMulDualI<0, sub, 1, (outs GPRnopc:$Rd),(ins GPRnopc:$Rn, GPRnopc:$Rm),
3861 NoItinerary, !strconcat(opc, "dx"), "\t$Rd, $Rn, $Rm">;
3864 defm SMUA : AI_sdml<0, "smua">;
3865 defm SMUS : AI_sdml<1, "smus">;
3867 //===----------------------------------------------------------------------===//
3868 // Misc. Arithmetic Instructions.
3871 def CLZ : AMiscA1I<0b000010110, 0b0001, (outs GPR:$Rd), (ins GPR:$Rm),
3872 IIC_iUNAr, "clz", "\t$Rd, $Rm",
3873 [(set GPR:$Rd, (ctlz GPR:$Rm))]>, Requires<[IsARM, HasV5T]>;
3875 def RBIT : AMiscA1I<0b01101111, 0b0011, (outs GPR:$Rd), (ins GPR:$Rm),
3876 IIC_iUNAr, "rbit", "\t$Rd, $Rm",
3877 [(set GPR:$Rd, (ARMrbit GPR:$Rm))]>,
3878 Requires<[IsARM, HasV6T2]>;
3880 def REV : AMiscA1I<0b01101011, 0b0011, (outs GPR:$Rd), (ins GPR:$Rm),
3881 IIC_iUNAr, "rev", "\t$Rd, $Rm",
3882 [(set GPR:$Rd, (bswap GPR:$Rm))]>, Requires<[IsARM, HasV6]>;
3884 let AddedComplexity = 5 in
3885 def REV16 : AMiscA1I<0b01101011, 0b1011, (outs GPR:$Rd), (ins GPR:$Rm),
3886 IIC_iUNAr, "rev16", "\t$Rd, $Rm",
3887 [(set GPR:$Rd, (rotr (bswap GPR:$Rm), (i32 16)))]>,
3888 Requires<[IsARM, HasV6]>;
3890 let AddedComplexity = 5 in
3891 def REVSH : AMiscA1I<0b01101111, 0b1011, (outs GPR:$Rd), (ins GPR:$Rm),
3892 IIC_iUNAr, "revsh", "\t$Rd, $Rm",
3893 [(set GPR:$Rd, (sra (bswap GPR:$Rm), (i32 16)))]>,
3894 Requires<[IsARM, HasV6]>;
3896 def : ARMV6Pat<(or (sra (shl GPR:$Rm, (i32 24)), (i32 16)),
3897 (and (srl GPR:$Rm, (i32 8)), 0xFF)),
3900 def PKHBT : APKHI<0b01101000, 0, (outs GPRnopc:$Rd),
3901 (ins GPRnopc:$Rn, GPRnopc:$Rm, pkh_lsl_amt:$sh),
3902 IIC_iALUsi, "pkhbt", "\t$Rd, $Rn, $Rm$sh",
3903 [(set GPRnopc:$Rd, (or (and GPRnopc:$Rn, 0xFFFF),
3904 (and (shl GPRnopc:$Rm, pkh_lsl_amt:$sh),
3906 Requires<[IsARM, HasV6]>;
3908 // Alternate cases for PKHBT where identities eliminate some nodes.
3909 def : ARMV6Pat<(or (and GPRnopc:$Rn, 0xFFFF), (and GPRnopc:$Rm, 0xFFFF0000)),
3910 (PKHBT GPRnopc:$Rn, GPRnopc:$Rm, 0)>;
3911 def : ARMV6Pat<(or (and GPRnopc:$Rn, 0xFFFF), (shl GPRnopc:$Rm, imm16_31:$sh)),
3912 (PKHBT GPRnopc:$Rn, GPRnopc:$Rm, imm16_31:$sh)>;
3914 // Note: Shifts of 1-15 bits will be transformed to srl instead of sra and
3915 // will match the pattern below.
3916 def PKHTB : APKHI<0b01101000, 1, (outs GPRnopc:$Rd),
3917 (ins GPRnopc:$Rn, GPRnopc:$Rm, pkh_asr_amt:$sh),
3918 IIC_iBITsi, "pkhtb", "\t$Rd, $Rn, $Rm$sh",
3919 [(set GPRnopc:$Rd, (or (and GPRnopc:$Rn, 0xFFFF0000),
3920 (and (sra GPRnopc:$Rm, pkh_asr_amt:$sh),
3922 Requires<[IsARM, HasV6]>;
3924 // Alternate cases for PKHTB where identities eliminate some nodes. Note that
3925 // a shift amount of 0 is *not legal* here, it is PKHBT instead.
3926 def : ARMV6Pat<(or (and GPRnopc:$src1, 0xFFFF0000),
3927 (srl GPRnopc:$src2, imm16_31:$sh)),
3928 (PKHTB GPRnopc:$src1, GPRnopc:$src2, imm16_31:$sh)>;
3929 def : ARMV6Pat<(or (and GPRnopc:$src1, 0xFFFF0000),
3930 (and (srl GPRnopc:$src2, imm1_15:$sh), 0xFFFF)),
3931 (PKHTB GPRnopc:$src1, GPRnopc:$src2, imm1_15:$sh)>;
3933 //===----------------------------------------------------------------------===//
3934 // Comparison Instructions...
3937 defm CMP : AI1_cmp_irs<0b1010, "cmp",
3938 IIC_iCMPi, IIC_iCMPr, IIC_iCMPsr,
3939 BinOpFrag<(ARMcmp node:$LHS, node:$RHS)>>;
3941 // ARMcmpZ can re-use the above instruction definitions.
3942 def : ARMPat<(ARMcmpZ GPR:$src, so_imm:$imm),
3943 (CMPri GPR:$src, so_imm:$imm)>;
3944 def : ARMPat<(ARMcmpZ GPR:$src, GPR:$rhs),
3945 (CMPrr GPR:$src, GPR:$rhs)>;
3946 def : ARMPat<(ARMcmpZ GPR:$src, so_reg_imm:$rhs),
3947 (CMPrsi GPR:$src, so_reg_imm:$rhs)>;
3948 def : ARMPat<(ARMcmpZ GPR:$src, so_reg_reg:$rhs),
3949 (CMPrsr GPR:$src, so_reg_reg:$rhs)>;
3951 // FIXME: We have to be careful when using the CMN instruction and comparison
3952 // with 0. One would expect these two pieces of code should give identical
3968 // However, the CMN gives the *opposite* result when r1 is 0. This is because
3969 // the carry flag is set in the CMP case but not in the CMN case. In short, the
3970 // CMP instruction doesn't perform a truncate of the (logical) NOT of 0 plus the
3971 // value of r0 and the carry bit (because the "carry bit" parameter to
3972 // AddWithCarry is defined as 1 in this case, the carry flag will always be set
3973 // when r0 >= 0). The CMN instruction doesn't perform a NOT of 0 so there is
3974 // never a "carry" when this AddWithCarry is performed (because the "carry bit"
3975 // parameter to AddWithCarry is defined as 0).
3977 // When x is 0 and unsigned:
3981 // ~x + 1 = 0x1 0000 0000
3982 // (-x = 0) != (0x1 0000 0000 = ~x + 1)
3984 // Therefore, we should disable CMN when comparing against zero, until we can
3985 // limit when the CMN instruction is used (when we know that the RHS is not 0 or
3986 // when it's a comparison which doesn't look at the 'carry' flag).
3988 // (See the ARM docs for the "AddWithCarry" pseudo-code.)
3990 // This is related to <rdar://problem/7569620>.
3992 //defm CMN : AI1_cmp_irs<0b1011, "cmn",
3993 // BinOpFrag<(ARMcmp node:$LHS,(ineg node:$RHS))>>;
3995 // Note that TST/TEQ don't set all the same flags that CMP does!
3996 defm TST : AI1_cmp_irs<0b1000, "tst",
3997 IIC_iTSTi, IIC_iTSTr, IIC_iTSTsr,
3998 BinOpFrag<(ARMcmpZ (and_su node:$LHS, node:$RHS), 0)>, 1>;
3999 defm TEQ : AI1_cmp_irs<0b1001, "teq",
4000 IIC_iTSTi, IIC_iTSTr, IIC_iTSTsr,
4001 BinOpFrag<(ARMcmpZ (xor_su node:$LHS, node:$RHS), 0)>, 1>;
4003 defm CMNz : AI1_cmp_irs<0b1011, "cmn",
4004 IIC_iCMPi, IIC_iCMPr, IIC_iCMPsr,
4005 BinOpFrag<(ARMcmpZ node:$LHS,(ineg node:$RHS))>>;
4007 //def : ARMPat<(ARMcmp GPR:$src, so_imm_neg:$imm),
4008 // (CMNri GPR:$src, so_imm_neg:$imm)>;
4010 def : ARMPat<(ARMcmpZ GPR:$src, so_imm_neg:$imm),
4011 (CMNzri GPR:$src, so_imm_neg:$imm)>;
4013 // Pseudo i64 compares for some floating point compares.
4014 let usesCustomInserter = 1, isBranch = 1, isTerminator = 1,
4016 def BCCi64 : PseudoInst<(outs),
4017 (ins i32imm:$cc, GPR:$lhs1, GPR:$lhs2, GPR:$rhs1, GPR:$rhs2, brtarget:$dst),
4019 [(ARMBcci64 imm:$cc, GPR:$lhs1, GPR:$lhs2, GPR:$rhs1, GPR:$rhs2, bb:$dst)]>;
4021 def BCCZi64 : PseudoInst<(outs),
4022 (ins i32imm:$cc, GPR:$lhs1, GPR:$lhs2, brtarget:$dst), IIC_Br,
4023 [(ARMBcci64 imm:$cc, GPR:$lhs1, GPR:$lhs2, 0, 0, bb:$dst)]>;
4024 } // usesCustomInserter
4027 // Conditional moves
4028 // FIXME: should be able to write a pattern for ARMcmov, but can't use
4029 // a two-value operand where a dag node expects two operands. :(
4030 let neverHasSideEffects = 1 in {
4031 def MOVCCr : ARMPseudoInst<(outs GPR:$Rd), (ins GPR:$false, GPR:$Rm, pred:$p),
4033 [/*(set GPR:$Rd, (ARMcmov GPR:$false, GPR:$Rm, imm:$cc, CCR:$ccr))*/]>,
4034 RegConstraint<"$false = $Rd">;
4035 def MOVCCsi : ARMPseudoInst<(outs GPR:$Rd),
4036 (ins GPR:$false, so_reg_imm:$shift, pred:$p),
4038 [/*(set GPR:$Rd, (ARMcmov GPR:$false, so_reg_imm:$shift,
4039 imm:$cc, CCR:$ccr))*/]>,
4040 RegConstraint<"$false = $Rd">;
4041 def MOVCCsr : ARMPseudoInst<(outs GPR:$Rd),
4042 (ins GPR:$false, so_reg_reg:$shift, pred:$p),
4044 [/*(set GPR:$Rd, (ARMcmov GPR:$false, so_reg_reg:$shift,
4045 imm:$cc, CCR:$ccr))*/]>,
4046 RegConstraint<"$false = $Rd">;
4049 let isMoveImm = 1 in
4050 def MOVCCi16 : ARMPseudoInst<(outs GPR:$Rd),
4051 (ins GPR:$false, imm0_65535_expr:$imm, pred:$p),
4054 RegConstraint<"$false = $Rd">, Requires<[IsARM, HasV6T2]>;
4056 let isMoveImm = 1 in
4057 def MOVCCi : ARMPseudoInst<(outs GPR:$Rd),
4058 (ins GPR:$false, so_imm:$imm, pred:$p),
4060 [/*(set GPR:$Rd, (ARMcmov GPR:$false, so_imm:$imm, imm:$cc, CCR:$ccr))*/]>,
4061 RegConstraint<"$false = $Rd">;
4063 // Two instruction predicate mov immediate.
4064 let isMoveImm = 1 in
4065 def MOVCCi32imm : ARMPseudoInst<(outs GPR:$Rd),
4066 (ins GPR:$false, i32imm:$src, pred:$p),
4067 8, IIC_iCMOVix2, []>, RegConstraint<"$false = $Rd">;
4069 let isMoveImm = 1 in
4070 def MVNCCi : ARMPseudoInst<(outs GPR:$Rd),
4071 (ins GPR:$false, so_imm:$imm, pred:$p),
4073 [/*(set GPR:$Rd, (ARMcmov GPR:$false, so_imm_not:$imm, imm:$cc, CCR:$ccr))*/]>,
4074 RegConstraint<"$false = $Rd">;
4075 } // neverHasSideEffects
4077 //===----------------------------------------------------------------------===//
4078 // Atomic operations intrinsics
4081 def MemBarrierOptOperand : AsmOperandClass {
4082 let Name = "MemBarrierOpt";
4083 let ParserMethod = "parseMemBarrierOptOperand";
4085 def memb_opt : Operand<i32> {
4086 let PrintMethod = "printMemBOption";
4087 let ParserMatchClass = MemBarrierOptOperand;
4088 let DecoderMethod = "DecodeMemBarrierOption";
4091 // memory barriers protect the atomic sequences
4092 let hasSideEffects = 1 in {
4093 def DMB : AInoP<(outs), (ins memb_opt:$opt), MiscFrm, NoItinerary,
4094 "dmb", "\t$opt", [(ARMMemBarrier (i32 imm:$opt))]>,
4095 Requires<[IsARM, HasDB]> {
4097 let Inst{31-4} = 0xf57ff05;
4098 let Inst{3-0} = opt;
4102 def DSB : AInoP<(outs), (ins memb_opt:$opt), MiscFrm, NoItinerary,
4103 "dsb", "\t$opt", []>,
4104 Requires<[IsARM, HasDB]> {
4106 let Inst{31-4} = 0xf57ff04;
4107 let Inst{3-0} = opt;
4110 // ISB has only full system option
4111 def ISB : AInoP<(outs), (ins memb_opt:$opt), MiscFrm, NoItinerary,
4112 "isb", "\t$opt", []>,
4113 Requires<[IsARM, HasDB]> {
4115 let Inst{31-4} = 0xf57ff06;
4116 let Inst{3-0} = opt;
4119 // Pseudo isntruction that combines movs + predicated rsbmi
4120 // to implement integer ABS
4121 let usesCustomInserter = 1, Defs = [CPSR] in {
4122 def ABS : ARMPseudoInst<
4123 (outs GPR:$dst), (ins GPR:$src),
4124 8, NoItinerary, []>;
4127 let usesCustomInserter = 1 in {
4128 let Defs = [CPSR] in {
4129 def ATOMIC_LOAD_ADD_I8 : PseudoInst<
4130 (outs GPR:$dst), (ins GPR:$ptr, GPR:$incr), NoItinerary,
4131 [(set GPR:$dst, (atomic_load_add_8 GPR:$ptr, GPR:$incr))]>;
4132 def ATOMIC_LOAD_SUB_I8 : PseudoInst<
4133 (outs GPR:$dst), (ins GPR:$ptr, GPR:$incr), NoItinerary,
4134 [(set GPR:$dst, (atomic_load_sub_8 GPR:$ptr, GPR:$incr))]>;
4135 def ATOMIC_LOAD_AND_I8 : PseudoInst<
4136 (outs GPR:$dst), (ins GPR:$ptr, GPR:$incr), NoItinerary,
4137 [(set GPR:$dst, (atomic_load_and_8 GPR:$ptr, GPR:$incr))]>;
4138 def ATOMIC_LOAD_OR_I8 : PseudoInst<
4139 (outs GPR:$dst), (ins GPR:$ptr, GPR:$incr), NoItinerary,
4140 [(set GPR:$dst, (atomic_load_or_8 GPR:$ptr, GPR:$incr))]>;
4141 def ATOMIC_LOAD_XOR_I8 : PseudoInst<
4142 (outs GPR:$dst), (ins GPR:$ptr, GPR:$incr), NoItinerary,
4143 [(set GPR:$dst, (atomic_load_xor_8 GPR:$ptr, GPR:$incr))]>;
4144 def ATOMIC_LOAD_NAND_I8 : PseudoInst<
4145 (outs GPR:$dst), (ins GPR:$ptr, GPR:$incr), NoItinerary,
4146 [(set GPR:$dst, (atomic_load_nand_8 GPR:$ptr, GPR:$incr))]>;
4147 def ATOMIC_LOAD_MIN_I8 : PseudoInst<
4148 (outs GPR:$dst), (ins GPR:$ptr, GPR:$val), NoItinerary,
4149 [(set GPR:$dst, (atomic_load_min_8 GPR:$ptr, GPR:$val))]>;
4150 def ATOMIC_LOAD_MAX_I8 : PseudoInst<
4151 (outs GPR:$dst), (ins GPR:$ptr, GPR:$val), NoItinerary,
4152 [(set GPR:$dst, (atomic_load_max_8 GPR:$ptr, GPR:$val))]>;
4153 def ATOMIC_LOAD_UMIN_I8 : PseudoInst<
4154 (outs GPR:$dst), (ins GPR:$ptr, GPR:$val), NoItinerary,
4155 [(set GPR:$dst, (atomic_load_umin_8 GPR:$ptr, GPR:$val))]>;
4156 def ATOMIC_LOAD_UMAX_I8 : PseudoInst<
4157 (outs GPR:$dst), (ins GPR:$ptr, GPR:$val), NoItinerary,
4158 [(set GPR:$dst, (atomic_load_umax_8 GPR:$ptr, GPR:$val))]>;
4159 def ATOMIC_LOAD_ADD_I16 : PseudoInst<
4160 (outs GPR:$dst), (ins GPR:$ptr, GPR:$incr), NoItinerary,
4161 [(set GPR:$dst, (atomic_load_add_16 GPR:$ptr, GPR:$incr))]>;
4162 def ATOMIC_LOAD_SUB_I16 : PseudoInst<
4163 (outs GPR:$dst), (ins GPR:$ptr, GPR:$incr), NoItinerary,
4164 [(set GPR:$dst, (atomic_load_sub_16 GPR:$ptr, GPR:$incr))]>;
4165 def ATOMIC_LOAD_AND_I16 : PseudoInst<
4166 (outs GPR:$dst), (ins GPR:$ptr, GPR:$incr), NoItinerary,
4167 [(set GPR:$dst, (atomic_load_and_16 GPR:$ptr, GPR:$incr))]>;
4168 def ATOMIC_LOAD_OR_I16 : PseudoInst<
4169 (outs GPR:$dst), (ins GPR:$ptr, GPR:$incr), NoItinerary,
4170 [(set GPR:$dst, (atomic_load_or_16 GPR:$ptr, GPR:$incr))]>;
4171 def ATOMIC_LOAD_XOR_I16 : PseudoInst<
4172 (outs GPR:$dst), (ins GPR:$ptr, GPR:$incr), NoItinerary,
4173 [(set GPR:$dst, (atomic_load_xor_16 GPR:$ptr, GPR:$incr))]>;
4174 def ATOMIC_LOAD_NAND_I16 : PseudoInst<
4175 (outs GPR:$dst), (ins GPR:$ptr, GPR:$incr), NoItinerary,
4176 [(set GPR:$dst, (atomic_load_nand_16 GPR:$ptr, GPR:$incr))]>;
4177 def ATOMIC_LOAD_MIN_I16 : PseudoInst<
4178 (outs GPR:$dst), (ins GPR:$ptr, GPR:$val), NoItinerary,
4179 [(set GPR:$dst, (atomic_load_min_16 GPR:$ptr, GPR:$val))]>;
4180 def ATOMIC_LOAD_MAX_I16 : PseudoInst<
4181 (outs GPR:$dst), (ins GPR:$ptr, GPR:$val), NoItinerary,
4182 [(set GPR:$dst, (atomic_load_max_16 GPR:$ptr, GPR:$val))]>;
4183 def ATOMIC_LOAD_UMIN_I16 : PseudoInst<
4184 (outs GPR:$dst), (ins GPR:$ptr, GPR:$val), NoItinerary,
4185 [(set GPR:$dst, (atomic_load_umin_16 GPR:$ptr, GPR:$val))]>;
4186 def ATOMIC_LOAD_UMAX_I16 : PseudoInst<
4187 (outs GPR:$dst), (ins GPR:$ptr, GPR:$val), NoItinerary,
4188 [(set GPR:$dst, (atomic_load_umax_16 GPR:$ptr, GPR:$val))]>;
4189 def ATOMIC_LOAD_ADD_I32 : PseudoInst<
4190 (outs GPR:$dst), (ins GPR:$ptr, GPR:$incr), NoItinerary,
4191 [(set GPR:$dst, (atomic_load_add_32 GPR:$ptr, GPR:$incr))]>;
4192 def ATOMIC_LOAD_SUB_I32 : PseudoInst<
4193 (outs GPR:$dst), (ins GPR:$ptr, GPR:$incr), NoItinerary,
4194 [(set GPR:$dst, (atomic_load_sub_32 GPR:$ptr, GPR:$incr))]>;
4195 def ATOMIC_LOAD_AND_I32 : PseudoInst<
4196 (outs GPR:$dst), (ins GPR:$ptr, GPR:$incr), NoItinerary,
4197 [(set GPR:$dst, (atomic_load_and_32 GPR:$ptr, GPR:$incr))]>;
4198 def ATOMIC_LOAD_OR_I32 : PseudoInst<
4199 (outs GPR:$dst), (ins GPR:$ptr, GPR:$incr), NoItinerary,
4200 [(set GPR:$dst, (atomic_load_or_32 GPR:$ptr, GPR:$incr))]>;
4201 def ATOMIC_LOAD_XOR_I32 : PseudoInst<
4202 (outs GPR:$dst), (ins GPR:$ptr, GPR:$incr), NoItinerary,
4203 [(set GPR:$dst, (atomic_load_xor_32 GPR:$ptr, GPR:$incr))]>;
4204 def ATOMIC_LOAD_NAND_I32 : PseudoInst<
4205 (outs GPR:$dst), (ins GPR:$ptr, GPR:$incr), NoItinerary,
4206 [(set GPR:$dst, (atomic_load_nand_32 GPR:$ptr, GPR:$incr))]>;
4207 def ATOMIC_LOAD_MIN_I32 : PseudoInst<
4208 (outs GPR:$dst), (ins GPR:$ptr, GPR:$val), NoItinerary,
4209 [(set GPR:$dst, (atomic_load_min_32 GPR:$ptr, GPR:$val))]>;
4210 def ATOMIC_LOAD_MAX_I32 : PseudoInst<
4211 (outs GPR:$dst), (ins GPR:$ptr, GPR:$val), NoItinerary,
4212 [(set GPR:$dst, (atomic_load_max_32 GPR:$ptr, GPR:$val))]>;
4213 def ATOMIC_LOAD_UMIN_I32 : PseudoInst<
4214 (outs GPR:$dst), (ins GPR:$ptr, GPR:$val), NoItinerary,
4215 [(set GPR:$dst, (atomic_load_umin_32 GPR:$ptr, GPR:$val))]>;
4216 def ATOMIC_LOAD_UMAX_I32 : PseudoInst<
4217 (outs GPR:$dst), (ins GPR:$ptr, GPR:$val), NoItinerary,
4218 [(set GPR:$dst, (atomic_load_umax_32 GPR:$ptr, GPR:$val))]>;
4220 def ATOMIC_SWAP_I8 : PseudoInst<
4221 (outs GPR:$dst), (ins GPR:$ptr, GPR:$new), NoItinerary,
4222 [(set GPR:$dst, (atomic_swap_8 GPR:$ptr, GPR:$new))]>;
4223 def ATOMIC_SWAP_I16 : PseudoInst<
4224 (outs GPR:$dst), (ins GPR:$ptr, GPR:$new), NoItinerary,
4225 [(set GPR:$dst, (atomic_swap_16 GPR:$ptr, GPR:$new))]>;
4226 def ATOMIC_SWAP_I32 : PseudoInst<
4227 (outs GPR:$dst), (ins GPR:$ptr, GPR:$new), NoItinerary,
4228 [(set GPR:$dst, (atomic_swap_32 GPR:$ptr, GPR:$new))]>;
4230 def ATOMIC_CMP_SWAP_I8 : PseudoInst<
4231 (outs GPR:$dst), (ins GPR:$ptr, GPR:$old, GPR:$new), NoItinerary,
4232 [(set GPR:$dst, (atomic_cmp_swap_8 GPR:$ptr, GPR:$old, GPR:$new))]>;
4233 def ATOMIC_CMP_SWAP_I16 : PseudoInst<
4234 (outs GPR:$dst), (ins GPR:$ptr, GPR:$old, GPR:$new), NoItinerary,
4235 [(set GPR:$dst, (atomic_cmp_swap_16 GPR:$ptr, GPR:$old, GPR:$new))]>;
4236 def ATOMIC_CMP_SWAP_I32 : PseudoInst<
4237 (outs GPR:$dst), (ins GPR:$ptr, GPR:$old, GPR:$new), NoItinerary,
4238 [(set GPR:$dst, (atomic_cmp_swap_32 GPR:$ptr, GPR:$old, GPR:$new))]>;
4242 let mayLoad = 1 in {
4243 def LDREXB : AIldrex<0b10, (outs GPR:$Rt), (ins addr_offset_none:$addr),
4245 "ldrexb", "\t$Rt, $addr", []>;
4246 def LDREXH : AIldrex<0b11, (outs GPR:$Rt), (ins addr_offset_none:$addr),
4247 NoItinerary, "ldrexh", "\t$Rt, $addr", []>;
4248 def LDREX : AIldrex<0b00, (outs GPR:$Rt), (ins addr_offset_none:$addr),
4249 NoItinerary, "ldrex", "\t$Rt, $addr", []>;
4250 let hasExtraDefRegAllocReq = 1 in
4251 def LDREXD: AIldrex<0b01, (outs GPR:$Rt, GPR:$Rt2),(ins addr_offset_none:$addr),
4252 NoItinerary, "ldrexd", "\t$Rt, $Rt2, $addr", []> {
4253 let DecoderMethod = "DecodeDoubleRegLoad";
4257 let mayStore = 1, Constraints = "@earlyclobber $Rd" in {
4258 def STREXB: AIstrex<0b10, (outs GPR:$Rd), (ins GPR:$Rt, addr_offset_none:$addr),
4259 NoItinerary, "strexb", "\t$Rd, $Rt, $addr", []>;
4260 def STREXH: AIstrex<0b11, (outs GPR:$Rd), (ins GPR:$Rt, addr_offset_none:$addr),
4261 NoItinerary, "strexh", "\t$Rd, $Rt, $addr", []>;
4262 def STREX : AIstrex<0b00, (outs GPR:$Rd), (ins GPR:$Rt, addr_offset_none:$addr),
4263 NoItinerary, "strex", "\t$Rd, $Rt, $addr", []>;
4266 let hasExtraSrcRegAllocReq = 1, Constraints = "@earlyclobber $Rd" in
4267 def STREXD : AIstrex<0b01, (outs GPR:$Rd),
4268 (ins GPR:$Rt, GPR:$Rt2, addr_offset_none:$addr),
4269 NoItinerary, "strexd", "\t$Rd, $Rt, $Rt2, $addr", []> {
4270 let DecoderMethod = "DecodeDoubleRegStore";
4273 def CLREX : AXI<(outs), (ins), MiscFrm, NoItinerary, "clrex", []>,
4274 Requires<[IsARM, HasV7]> {
4275 let Inst{31-0} = 0b11110101011111111111000000011111;
4278 // SWP/SWPB are deprecated in V6/V7.
4279 let mayLoad = 1, mayStore = 1 in {
4280 def SWP : AIswp<0, (outs GPR:$Rt), (ins GPR:$Rt2, addr_offset_none:$addr),
4282 def SWPB: AIswp<1, (outs GPR:$Rt), (ins GPR:$Rt2, addr_offset_none:$addr),
4286 //===----------------------------------------------------------------------===//
4287 // Coprocessor Instructions.
4290 def CDP : ABI<0b1110, (outs), (ins p_imm:$cop, imm0_15:$opc1,
4291 c_imm:$CRd, c_imm:$CRn, c_imm:$CRm, imm0_7:$opc2),
4292 NoItinerary, "cdp", "\t$cop, $opc1, $CRd, $CRn, $CRm, $opc2",
4293 [(int_arm_cdp imm:$cop, imm:$opc1, imm:$CRd, imm:$CRn,
4294 imm:$CRm, imm:$opc2)]> {
4302 let Inst{3-0} = CRm;
4304 let Inst{7-5} = opc2;
4305 let Inst{11-8} = cop;
4306 let Inst{15-12} = CRd;
4307 let Inst{19-16} = CRn;
4308 let Inst{23-20} = opc1;
4311 def CDP2 : ABXI<0b1110, (outs), (ins p_imm:$cop, imm0_15:$opc1,
4312 c_imm:$CRd, c_imm:$CRn, c_imm:$CRm, imm0_7:$opc2),
4313 NoItinerary, "cdp2\t$cop, $opc1, $CRd, $CRn, $CRm, $opc2",
4314 [(int_arm_cdp2 imm:$cop, imm:$opc1, imm:$CRd, imm:$CRn,
4315 imm:$CRm, imm:$opc2)]> {
4316 let Inst{31-28} = 0b1111;
4324 let Inst{3-0} = CRm;
4326 let Inst{7-5} = opc2;
4327 let Inst{11-8} = cop;
4328 let Inst{15-12} = CRd;
4329 let Inst{19-16} = CRn;
4330 let Inst{23-20} = opc1;
4333 class ACI<dag oops, dag iops, string opc, string asm,
4334 IndexMode im = IndexModeNone>
4335 : I<oops, iops, AddrModeNone, 4, im, BrFrm, NoItinerary,
4337 let Inst{27-25} = 0b110;
4339 class ACInoP<dag oops, dag iops, string opc, string asm,
4340 IndexMode im = IndexModeNone>
4341 : InoP<oops, iops, AddrModeNone, 4, im, BrFrm, NoItinerary,
4343 let Inst{31-28} = 0b1111;
4344 let Inst{27-25} = 0b110;
4346 multiclass LdStCop<bit load, bit Dbit, string asm> {
4347 def _OFFSET : ACI<(outs), (ins p_imm:$cop, c_imm:$CRd, addrmode5:$addr),
4348 asm, "\t$cop, $CRd, $addr"> {
4352 let Inst{24} = 1; // P = 1
4353 let Inst{23} = addr{8};
4354 let Inst{22} = Dbit;
4355 let Inst{21} = 0; // W = 0
4356 let Inst{20} = load;
4357 let Inst{19-16} = addr{12-9};
4358 let Inst{15-12} = CRd;
4359 let Inst{11-8} = cop;
4360 let Inst{7-0} = addr{7-0};
4361 let DecoderMethod = "DecodeCopMemInstruction";
4363 def _PRE : ACI<(outs), (ins p_imm:$cop, c_imm:$CRd, addrmode5:$addr),
4364 asm, "\t$cop, $CRd, $addr!", IndexModePre> {
4368 let Inst{24} = 1; // P = 1
4369 let Inst{23} = addr{8};
4370 let Inst{22} = Dbit;
4371 let Inst{21} = 1; // W = 1
4372 let Inst{20} = load;
4373 let Inst{19-16} = addr{12-9};
4374 let Inst{15-12} = CRd;
4375 let Inst{11-8} = cop;
4376 let Inst{7-0} = addr{7-0};
4377 let DecoderMethod = "DecodeCopMemInstruction";
4379 def _POST: ACI<(outs), (ins p_imm:$cop, c_imm:$CRd, addr_offset_none:$addr,
4380 postidx_imm8s4:$offset),
4381 asm, "\t$cop, $CRd, $addr, $offset", IndexModePost> {
4386 let Inst{24} = 0; // P = 0
4387 let Inst{23} = offset{8};
4388 let Inst{22} = Dbit;
4389 let Inst{21} = 1; // W = 1
4390 let Inst{20} = load;
4391 let Inst{19-16} = addr;
4392 let Inst{15-12} = CRd;
4393 let Inst{11-8} = cop;
4394 let Inst{7-0} = offset{7-0};
4395 let DecoderMethod = "DecodeCopMemInstruction";
4397 def _OPTION : ACI<(outs),
4398 (ins p_imm:$cop, c_imm:$CRd, addr_offset_none:$addr,
4399 coproc_option_imm:$option),
4400 asm, "\t$cop, $CRd, $addr, $option"> {
4405 let Inst{24} = 0; // P = 0
4406 let Inst{23} = 1; // U = 1
4407 let Inst{22} = Dbit;
4408 let Inst{21} = 0; // W = 0
4409 let Inst{20} = load;
4410 let Inst{19-16} = addr;
4411 let Inst{15-12} = CRd;
4412 let Inst{11-8} = cop;
4413 let Inst{7-0} = option;
4414 let DecoderMethod = "DecodeCopMemInstruction";
4417 multiclass LdSt2Cop<bit load, bit Dbit, string asm> {
4418 def _OFFSET : ACInoP<(outs), (ins p_imm:$cop, c_imm:$CRd, addrmode5:$addr),
4419 asm, "\t$cop, $CRd, $addr"> {
4423 let Inst{24} = 1; // P = 1
4424 let Inst{23} = addr{8};
4425 let Inst{22} = Dbit;
4426 let Inst{21} = 0; // W = 0
4427 let Inst{20} = load;
4428 let Inst{19-16} = addr{12-9};
4429 let Inst{15-12} = CRd;
4430 let Inst{11-8} = cop;
4431 let Inst{7-0} = addr{7-0};
4432 let DecoderMethod = "DecodeCopMemInstruction";
4434 def _PRE : ACInoP<(outs), (ins p_imm:$cop, c_imm:$CRd, addrmode5:$addr),
4435 asm, "\t$cop, $CRd, $addr!", IndexModePre> {
4439 let Inst{24} = 1; // P = 1
4440 let Inst{23} = addr{8};
4441 let Inst{22} = Dbit;
4442 let Inst{21} = 1; // W = 1
4443 let Inst{20} = load;
4444 let Inst{19-16} = addr{12-9};
4445 let Inst{15-12} = CRd;
4446 let Inst{11-8} = cop;
4447 let Inst{7-0} = addr{7-0};
4448 let DecoderMethod = "DecodeCopMemInstruction";
4450 def _POST: ACInoP<(outs), (ins p_imm:$cop, c_imm:$CRd, addr_offset_none:$addr,
4451 postidx_imm8s4:$offset),
4452 asm, "\t$cop, $CRd, $addr, $offset", IndexModePost> {
4457 let Inst{24} = 0; // P = 0
4458 let Inst{23} = offset{8};
4459 let Inst{22} = Dbit;
4460 let Inst{21} = 1; // W = 1
4461 let Inst{20} = load;
4462 let Inst{19-16} = addr;
4463 let Inst{15-12} = CRd;
4464 let Inst{11-8} = cop;
4465 let Inst{7-0} = offset{7-0};
4466 let DecoderMethod = "DecodeCopMemInstruction";
4468 def _OPTION : ACInoP<(outs),
4469 (ins p_imm:$cop, c_imm:$CRd, addr_offset_none:$addr,
4470 coproc_option_imm:$option),
4471 asm, "\t$cop, $CRd, $addr, $option"> {
4476 let Inst{24} = 0; // P = 0
4477 let Inst{23} = 1; // U = 1
4478 let Inst{22} = Dbit;
4479 let Inst{21} = 0; // W = 0
4480 let Inst{20} = load;
4481 let Inst{19-16} = addr;
4482 let Inst{15-12} = CRd;
4483 let Inst{11-8} = cop;
4484 let Inst{7-0} = option;
4485 let DecoderMethod = "DecodeCopMemInstruction";
4489 defm LDC : LdStCop <1, 0, "ldc">;
4490 defm LDCL : LdStCop <1, 1, "ldcl">;
4491 defm STC : LdStCop <0, 0, "stc">;
4492 defm STCL : LdStCop <0, 1, "stcl">;
4493 defm LDC2 : LdSt2Cop<1, 0, "ldc2">;
4494 defm LDC2L : LdSt2Cop<1, 1, "ldc2l">;
4495 defm STC2 : LdSt2Cop<0, 0, "stc2">;
4496 defm STC2L : LdSt2Cop<0, 1, "stc2l">;
4498 //===----------------------------------------------------------------------===//
4499 // Move between coprocessor and ARM core register.
4502 class MovRCopro<string opc, bit direction, dag oops, dag iops,
4504 : ABI<0b1110, oops, iops, NoItinerary, opc,
4505 "\t$cop, $opc1, $Rt, $CRn, $CRm, $opc2", pattern> {
4506 let Inst{20} = direction;
4516 let Inst{15-12} = Rt;
4517 let Inst{11-8} = cop;
4518 let Inst{23-21} = opc1;
4519 let Inst{7-5} = opc2;
4520 let Inst{3-0} = CRm;
4521 let Inst{19-16} = CRn;
4524 def MCR : MovRCopro<"mcr", 0 /* from ARM core register to coprocessor */,
4526 (ins p_imm:$cop, imm0_7:$opc1, GPR:$Rt, c_imm:$CRn,
4527 c_imm:$CRm, imm0_7:$opc2),
4528 [(int_arm_mcr imm:$cop, imm:$opc1, GPR:$Rt, imm:$CRn,
4529 imm:$CRm, imm:$opc2)]>;
4530 def MRC : MovRCopro<"mrc", 1 /* from coprocessor to ARM core register */,
4532 (ins p_imm:$cop, imm0_7:$opc1, c_imm:$CRn, c_imm:$CRm,
4535 def : ARMPat<(int_arm_mrc imm:$cop, imm:$opc1, imm:$CRn, imm:$CRm, imm:$opc2),
4536 (MRC imm:$cop, imm:$opc1, imm:$CRn, imm:$CRm, imm:$opc2)>;
4538 class MovRCopro2<string opc, bit direction, dag oops, dag iops,
4540 : ABXI<0b1110, oops, iops, NoItinerary,
4541 !strconcat(opc, "\t$cop, $opc1, $Rt, $CRn, $CRm, $opc2"), pattern> {
4542 let Inst{31-28} = 0b1111;
4543 let Inst{20} = direction;
4553 let Inst{15-12} = Rt;
4554 let Inst{11-8} = cop;
4555 let Inst{23-21} = opc1;
4556 let Inst{7-5} = opc2;
4557 let Inst{3-0} = CRm;
4558 let Inst{19-16} = CRn;
4561 def MCR2 : MovRCopro2<"mcr2", 0 /* from ARM core register to coprocessor */,
4563 (ins p_imm:$cop, imm0_7:$opc1, GPR:$Rt, c_imm:$CRn,
4564 c_imm:$CRm, imm0_7:$opc2),
4565 [(int_arm_mcr2 imm:$cop, imm:$opc1, GPR:$Rt, imm:$CRn,
4566 imm:$CRm, imm:$opc2)]>;
4567 def MRC2 : MovRCopro2<"mrc2", 1 /* from coprocessor to ARM core register */,
4569 (ins p_imm:$cop, imm0_7:$opc1, c_imm:$CRn, c_imm:$CRm,
4572 def : ARMV5TPat<(int_arm_mrc2 imm:$cop, imm:$opc1, imm:$CRn,
4573 imm:$CRm, imm:$opc2),
4574 (MRC2 imm:$cop, imm:$opc1, imm:$CRn, imm:$CRm, imm:$opc2)>;
4576 class MovRRCopro<string opc, bit direction, list<dag> pattern = []>
4577 : ABI<0b1100, (outs), (ins p_imm:$cop, imm0_15:$opc1,
4578 GPR:$Rt, GPR:$Rt2, c_imm:$CRm),
4579 NoItinerary, opc, "\t$cop, $opc1, $Rt, $Rt2, $CRm", pattern> {
4580 let Inst{23-21} = 0b010;
4581 let Inst{20} = direction;
4589 let Inst{15-12} = Rt;
4590 let Inst{19-16} = Rt2;
4591 let Inst{11-8} = cop;
4592 let Inst{7-4} = opc1;
4593 let Inst{3-0} = CRm;
4596 def MCRR : MovRRCopro<"mcrr", 0 /* from ARM core register to coprocessor */,
4597 [(int_arm_mcrr imm:$cop, imm:$opc1, GPR:$Rt, GPR:$Rt2,
4599 def MRRC : MovRRCopro<"mrrc", 1 /* from coprocessor to ARM core register */>;
4601 class MovRRCopro2<string opc, bit direction, list<dag> pattern = []>
4602 : ABXI<0b1100, (outs), (ins p_imm:$cop, imm0_15:$opc1,
4603 GPR:$Rt, GPR:$Rt2, c_imm:$CRm), NoItinerary,
4604 !strconcat(opc, "\t$cop, $opc1, $Rt, $Rt2, $CRm"), pattern> {
4605 let Inst{31-28} = 0b1111;
4606 let Inst{23-21} = 0b010;
4607 let Inst{20} = direction;
4615 let Inst{15-12} = Rt;
4616 let Inst{19-16} = Rt2;
4617 let Inst{11-8} = cop;
4618 let Inst{7-4} = opc1;
4619 let Inst{3-0} = CRm;
4622 def MCRR2 : MovRRCopro2<"mcrr2", 0 /* from ARM core register to coprocessor */,
4623 [(int_arm_mcrr2 imm:$cop, imm:$opc1, GPR:$Rt, GPR:$Rt2,
4625 def MRRC2 : MovRRCopro2<"mrrc2", 1 /* from coprocessor to ARM core register */>;
4627 //===----------------------------------------------------------------------===//
4628 // Move between special register and ARM core register
4631 // Move to ARM core register from Special Register
4632 def MRS : ABI<0b0001, (outs GPR:$Rd), (ins), NoItinerary,
4633 "mrs", "\t$Rd, apsr", []> {
4635 let Inst{23-16} = 0b00001111;
4636 let Inst{15-12} = Rd;
4637 let Inst{7-4} = 0b0000;
4640 def : InstAlias<"mrs${p} $Rd, cpsr", (MRS GPR:$Rd, pred:$p)>, Requires<[IsARM]>;
4642 def MRSsys : ABI<0b0001, (outs GPR:$Rd), (ins), NoItinerary,
4643 "mrs", "\t$Rd, spsr", []> {
4645 let Inst{23-16} = 0b01001111;
4646 let Inst{15-12} = Rd;
4647 let Inst{7-4} = 0b0000;
4650 // Move from ARM core register to Special Register
4652 // No need to have both system and application versions, the encodings are the
4653 // same and the assembly parser has no way to distinguish between them. The mask
4654 // operand contains the special register (R Bit) in bit 4 and bits 3-0 contains
4655 // the mask with the fields to be accessed in the special register.
4656 def MSR : ABI<0b0001, (outs), (ins msr_mask:$mask, GPR:$Rn), NoItinerary,
4657 "msr", "\t$mask, $Rn", []> {
4662 let Inst{22} = mask{4}; // R bit
4663 let Inst{21-20} = 0b10;
4664 let Inst{19-16} = mask{3-0};
4665 let Inst{15-12} = 0b1111;
4666 let Inst{11-4} = 0b00000000;
4670 def MSRi : ABI<0b0011, (outs), (ins msr_mask:$mask, so_imm:$a), NoItinerary,
4671 "msr", "\t$mask, $a", []> {
4676 let Inst{22} = mask{4}; // R bit
4677 let Inst{21-20} = 0b10;
4678 let Inst{19-16} = mask{3-0};
4679 let Inst{15-12} = 0b1111;
4683 //===----------------------------------------------------------------------===//
4687 // __aeabi_read_tp preserves the registers r1-r3.
4688 // This is a pseudo inst so that we can get the encoding right,
4689 // complete with fixup for the aeabi_read_tp function.
4691 Defs = [R0, R12, LR, CPSR], Uses = [SP] in {
4692 def TPsoft : PseudoInst<(outs), (ins), IIC_Br,
4693 [(set R0, ARMthread_pointer)]>;
4696 //===----------------------------------------------------------------------===//
4697 // SJLJ Exception handling intrinsics
4698 // eh_sjlj_setjmp() is an instruction sequence to store the return
4699 // address and save #0 in R0 for the non-longjmp case.
4700 // Since by its nature we may be coming from some other function to get
4701 // here, and we're using the stack frame for the containing function to
4702 // save/restore registers, we can't keep anything live in regs across
4703 // the eh_sjlj_setjmp(), else it will almost certainly have been tromped upon
4704 // when we get here from a longjmp(). We force everything out of registers
4705 // except for our own input by listing the relevant registers in Defs. By
4706 // doing so, we also cause the prologue/epilogue code to actively preserve
4707 // all of the callee-saved resgisters, which is exactly what we want.
4708 // A constant value is passed in $val, and we use the location as a scratch.
4710 // These are pseudo-instructions and are lowered to individual MC-insts, so
4711 // no encoding information is necessary.
4713 [ R0, R1, R2, R3, R4, R5, R6, R7, R8, R9, R10, R11, R12, LR, CPSR,
4714 QQQQ0, QQQQ1, QQQQ2, QQQQ3 ], hasSideEffects = 1, isBarrier = 1,
4715 usesCustomInserter = 1 in {
4716 def Int_eh_sjlj_setjmp : PseudoInst<(outs), (ins GPR:$src, GPR:$val),
4718 [(set R0, (ARMeh_sjlj_setjmp GPR:$src, GPR:$val))]>,
4719 Requires<[IsARM, HasVFP2]>;
4723 [ R0, R1, R2, R3, R4, R5, R6, R7, R8, R9, R10, R11, R12, LR, CPSR ],
4724 hasSideEffects = 1, isBarrier = 1, usesCustomInserter = 1 in {
4725 def Int_eh_sjlj_setjmp_nofp : PseudoInst<(outs), (ins GPR:$src, GPR:$val),
4727 [(set R0, (ARMeh_sjlj_setjmp GPR:$src, GPR:$val))]>,
4728 Requires<[IsARM, NoVFP]>;
4731 // FIXME: Non-IOS version(s)
4732 let isBarrier = 1, hasSideEffects = 1, isTerminator = 1,
4733 Defs = [ R7, LR, SP ] in {
4734 def Int_eh_sjlj_longjmp : PseudoInst<(outs), (ins GPR:$src, GPR:$scratch),
4736 [(ARMeh_sjlj_longjmp GPR:$src, GPR:$scratch)]>,
4737 Requires<[IsARM, IsIOS]>;
4740 // eh.sjlj.dispatchsetup pseudo-instructions.
4741 // These pseudos are used for both ARM and Thumb2. Any differences are
4742 // handled when the pseudo is expanded (which happens before any passes
4743 // that need the instruction size).
4745 [ R0, R1, R2, R3, R4, R5, R6, R7, R8, R9, R10, R11, R12, LR, CPSR,
4746 QQQQ0, QQQQ1, QQQQ2, QQQQ3 ], isBarrier = 1 in
4747 def Int_eh_sjlj_dispatchsetup : PseudoInst<(outs), (ins), NoItinerary, []>;
4750 [ R0, R1, R2, R3, R4, R5, R6, R7, R8, R9, R10, R11, R12, LR, CPSR ],
4752 def Int_eh_sjlj_dispatchsetup_nofp : PseudoInst<(outs), (ins), NoItinerary, []>;
4755 //===----------------------------------------------------------------------===//
4756 // Non-Instruction Patterns
4759 // ARMv4 indirect branch using (MOVr PC, dst)
4760 let isBranch = 1, isTerminator = 1, isBarrier = 1, isIndirectBranch = 1 in
4761 def MOVPCRX : ARMPseudoExpand<(outs), (ins GPR:$dst),
4762 4, IIC_Br, [(brind GPR:$dst)],
4763 (MOVr PC, GPR:$dst, (ops 14, zero_reg), zero_reg)>,
4764 Requires<[IsARM, NoV4T]>;
4766 // Large immediate handling.
4768 // 32-bit immediate using two piece so_imms or movw + movt.
4769 // This is a single pseudo instruction, the benefit is that it can be remat'd
4770 // as a single unit instead of having to handle reg inputs.
4771 // FIXME: Remove this when we can do generalized remat.
4772 let isReMaterializable = 1, isMoveImm = 1 in
4773 def MOVi32imm : PseudoInst<(outs GPR:$dst), (ins i32imm:$src), IIC_iMOVix2,
4774 [(set GPR:$dst, (arm_i32imm:$src))]>,
4777 // Pseudo instruction that combines movw + movt + add pc (if PIC).
4778 // It also makes it possible to rematerialize the instructions.
4779 // FIXME: Remove this when we can do generalized remat and when machine licm
4780 // can properly the instructions.
4781 let isReMaterializable = 1 in {
4782 def MOV_ga_pcrel : PseudoInst<(outs GPR:$dst), (ins i32imm:$addr),
4784 [(set GPR:$dst, (ARMWrapperPIC tglobaladdr:$addr))]>,
4785 Requires<[IsARM, UseMovt]>;
4787 def MOV_ga_dyn : PseudoInst<(outs GPR:$dst), (ins i32imm:$addr),
4789 [(set GPR:$dst, (ARMWrapperDYN tglobaladdr:$addr))]>,
4790 Requires<[IsARM, UseMovt]>;
4792 let AddedComplexity = 10 in
4793 def MOV_ga_pcrel_ldr : PseudoInst<(outs GPR:$dst), (ins i32imm:$addr),
4795 [(set GPR:$dst, (load (ARMWrapperPIC tglobaladdr:$addr)))]>,
4796 Requires<[IsARM, UseMovt]>;
4797 } // isReMaterializable
4799 // ConstantPool, GlobalAddress, and JumpTable
4800 def : ARMPat<(ARMWrapper tglobaladdr :$dst), (LEApcrel tglobaladdr :$dst)>,
4801 Requires<[IsARM, DontUseMovt]>;
4802 def : ARMPat<(ARMWrapper tconstpool :$dst), (LEApcrel tconstpool :$dst)>;
4803 def : ARMPat<(ARMWrapper tglobaladdr :$dst), (MOVi32imm tglobaladdr :$dst)>,
4804 Requires<[IsARM, UseMovt]>;
4805 def : ARMPat<(ARMWrapperJT tjumptable:$dst, imm:$id),
4806 (LEApcrelJT tjumptable:$dst, imm:$id)>;
4808 // TODO: add,sub,and, 3-instr forms?
4811 def : ARMPat<(ARMtcret tcGPR:$dst),
4812 (TCRETURNri tcGPR:$dst)>, Requires<[IsIOS]>;
4814 def : ARMPat<(ARMtcret (i32 tglobaladdr:$dst)),
4815 (TCRETURNdi texternalsym:$dst)>, Requires<[IsIOS]>;
4817 def : ARMPat<(ARMtcret (i32 texternalsym:$dst)),
4818 (TCRETURNdi texternalsym:$dst)>, Requires<[IsIOS]>;
4820 def : ARMPat<(ARMtcret tcGPR:$dst),
4821 (TCRETURNriND tcGPR:$dst)>, Requires<[IsNotIOS]>;
4823 def : ARMPat<(ARMtcret (i32 tglobaladdr:$dst)),
4824 (TCRETURNdiND texternalsym:$dst)>, Requires<[IsNotIOS]>;
4826 def : ARMPat<(ARMtcret (i32 texternalsym:$dst)),
4827 (TCRETURNdiND texternalsym:$dst)>, Requires<[IsNotIOS]>;
4830 def : ARMPat<(ARMcall texternalsym:$func), (BL texternalsym:$func)>,
4831 Requires<[IsARM, IsNotIOS]>;
4832 def : ARMPat<(ARMcall texternalsym:$func), (BLr9 texternalsym:$func)>,
4833 Requires<[IsARM, IsIOS]>;
4835 // zextload i1 -> zextload i8
4836 def : ARMPat<(zextloadi1 addrmode_imm12:$addr), (LDRBi12 addrmode_imm12:$addr)>;
4837 def : ARMPat<(zextloadi1 ldst_so_reg:$addr), (LDRBrs ldst_so_reg:$addr)>;
4839 // extload -> zextload
4840 def : ARMPat<(extloadi1 addrmode_imm12:$addr), (LDRBi12 addrmode_imm12:$addr)>;
4841 def : ARMPat<(extloadi1 ldst_so_reg:$addr), (LDRBrs ldst_so_reg:$addr)>;
4842 def : ARMPat<(extloadi8 addrmode_imm12:$addr), (LDRBi12 addrmode_imm12:$addr)>;
4843 def : ARMPat<(extloadi8 ldst_so_reg:$addr), (LDRBrs ldst_so_reg:$addr)>;
4845 def : ARMPat<(extloadi16 addrmode3:$addr), (LDRH addrmode3:$addr)>;
4847 def : ARMPat<(extloadi8 addrmodepc:$addr), (PICLDRB addrmodepc:$addr)>;
4848 def : ARMPat<(extloadi16 addrmodepc:$addr), (PICLDRH addrmodepc:$addr)>;
4851 def : ARMV5TEPat<(mul (sra (shl GPR:$a, (i32 16)), (i32 16)),
4852 (sra (shl GPR:$b, (i32 16)), (i32 16))),
4853 (SMULBB GPR:$a, GPR:$b)>;
4854 def : ARMV5TEPat<(mul sext_16_node:$a, sext_16_node:$b),
4855 (SMULBB GPR:$a, GPR:$b)>;
4856 def : ARMV5TEPat<(mul (sra (shl GPR:$a, (i32 16)), (i32 16)),
4857 (sra GPR:$b, (i32 16))),
4858 (SMULBT GPR:$a, GPR:$b)>;
4859 def : ARMV5TEPat<(mul sext_16_node:$a, (sra GPR:$b, (i32 16))),
4860 (SMULBT GPR:$a, GPR:$b)>;
4861 def : ARMV5TEPat<(mul (sra GPR:$a, (i32 16)),
4862 (sra (shl GPR:$b, (i32 16)), (i32 16))),
4863 (SMULTB GPR:$a, GPR:$b)>;
4864 def : ARMV5TEPat<(mul (sra GPR:$a, (i32 16)), sext_16_node:$b),
4865 (SMULTB GPR:$a, GPR:$b)>;
4866 def : ARMV5TEPat<(sra (mul GPR:$a, (sra (shl GPR:$b, (i32 16)), (i32 16))),
4868 (SMULWB GPR:$a, GPR:$b)>;
4869 def : ARMV5TEPat<(sra (mul GPR:$a, sext_16_node:$b), (i32 16)),
4870 (SMULWB GPR:$a, GPR:$b)>;
4872 def : ARMV5TEPat<(add GPR:$acc,
4873 (mul (sra (shl GPR:$a, (i32 16)), (i32 16)),
4874 (sra (shl GPR:$b, (i32 16)), (i32 16)))),
4875 (SMLABB GPR:$a, GPR:$b, GPR:$acc)>;
4876 def : ARMV5TEPat<(add GPR:$acc,
4877 (mul sext_16_node:$a, sext_16_node:$b)),
4878 (SMLABB GPR:$a, GPR:$b, GPR:$acc)>;
4879 def : ARMV5TEPat<(add GPR:$acc,
4880 (mul (sra (shl GPR:$a, (i32 16)), (i32 16)),
4881 (sra GPR:$b, (i32 16)))),
4882 (SMLABT GPR:$a, GPR:$b, GPR:$acc)>;
4883 def : ARMV5TEPat<(add GPR:$acc,
4884 (mul sext_16_node:$a, (sra GPR:$b, (i32 16)))),
4885 (SMLABT GPR:$a, GPR:$b, GPR:$acc)>;
4886 def : ARMV5TEPat<(add GPR:$acc,
4887 (mul (sra GPR:$a, (i32 16)),
4888 (sra (shl GPR:$b, (i32 16)), (i32 16)))),
4889 (SMLATB GPR:$a, GPR:$b, GPR:$acc)>;
4890 def : ARMV5TEPat<(add GPR:$acc,
4891 (mul (sra GPR:$a, (i32 16)), sext_16_node:$b)),
4892 (SMLATB GPR:$a, GPR:$b, GPR:$acc)>;
4893 def : ARMV5TEPat<(add GPR:$acc,
4894 (sra (mul GPR:$a, (sra (shl GPR:$b, (i32 16)), (i32 16))),
4896 (SMLAWB GPR:$a, GPR:$b, GPR:$acc)>;
4897 def : ARMV5TEPat<(add GPR:$acc,
4898 (sra (mul GPR:$a, sext_16_node:$b), (i32 16))),
4899 (SMLAWB GPR:$a, GPR:$b, GPR:$acc)>;
4902 // Pre-v7 uses MCR for synchronization barriers.
4903 def : ARMPat<(ARMMemBarrierMCR GPR:$zero), (MCR 15, 0, GPR:$zero, 7, 10, 5)>,
4904 Requires<[IsARM, HasV6]>;
4906 // SXT/UXT with no rotate
4907 let AddedComplexity = 16 in {
4908 def : ARMV6Pat<(and GPR:$Src, 0x000000FF), (UXTB GPR:$Src, 0)>;
4909 def : ARMV6Pat<(and GPR:$Src, 0x0000FFFF), (UXTH GPR:$Src, 0)>;
4910 def : ARMV6Pat<(and GPR:$Src, 0x00FF00FF), (UXTB16 GPR:$Src, 0)>;
4911 def : ARMV6Pat<(add GPR:$Rn, (and GPR:$Rm, 0x00FF)),
4912 (UXTAB GPR:$Rn, GPR:$Rm, 0)>;
4913 def : ARMV6Pat<(add GPR:$Rn, (and GPR:$Rm, 0xFFFF)),
4914 (UXTAH GPR:$Rn, GPR:$Rm, 0)>;
4917 def : ARMV6Pat<(sext_inreg GPR:$Src, i8), (SXTB GPR:$Src, 0)>;
4918 def : ARMV6Pat<(sext_inreg GPR:$Src, i16), (SXTH GPR:$Src, 0)>;
4920 def : ARMV6Pat<(add GPR:$Rn, (sext_inreg GPRnopc:$Rm, i8)),
4921 (SXTAB GPR:$Rn, GPRnopc:$Rm, 0)>;
4922 def : ARMV6Pat<(add GPR:$Rn, (sext_inreg GPRnopc:$Rm, i16)),
4923 (SXTAH GPR:$Rn, GPRnopc:$Rm, 0)>;
4925 // Atomic load/store patterns
4926 def : ARMPat<(atomic_load_8 ldst_so_reg:$src),
4927 (LDRBrs ldst_so_reg:$src)>;
4928 def : ARMPat<(atomic_load_8 addrmode_imm12:$src),
4929 (LDRBi12 addrmode_imm12:$src)>;
4930 def : ARMPat<(atomic_load_16 addrmode3:$src),
4931 (LDRH addrmode3:$src)>;
4932 def : ARMPat<(atomic_load_32 ldst_so_reg:$src),
4933 (LDRrs ldst_so_reg:$src)>;
4934 def : ARMPat<(atomic_load_32 addrmode_imm12:$src),
4935 (LDRi12 addrmode_imm12:$src)>;
4936 def : ARMPat<(atomic_store_8 ldst_so_reg:$ptr, GPR:$val),
4937 (STRBrs GPR:$val, ldst_so_reg:$ptr)>;
4938 def : ARMPat<(atomic_store_8 addrmode_imm12:$ptr, GPR:$val),
4939 (STRBi12 GPR:$val, addrmode_imm12:$ptr)>;
4940 def : ARMPat<(atomic_store_16 addrmode3:$ptr, GPR:$val),
4941 (STRH GPR:$val, addrmode3:$ptr)>;
4942 def : ARMPat<(atomic_store_32 ldst_so_reg:$ptr, GPR:$val),
4943 (STRrs GPR:$val, ldst_so_reg:$ptr)>;
4944 def : ARMPat<(atomic_store_32 addrmode_imm12:$ptr, GPR:$val),
4945 (STRi12 GPR:$val, addrmode_imm12:$ptr)>;
4948 //===----------------------------------------------------------------------===//
4952 include "ARMInstrThumb.td"
4954 //===----------------------------------------------------------------------===//
4958 include "ARMInstrThumb2.td"
4960 //===----------------------------------------------------------------------===//
4961 // Floating Point Support
4964 include "ARMInstrVFP.td"
4966 //===----------------------------------------------------------------------===//
4967 // Advanced SIMD (NEON) Support
4970 include "ARMInstrNEON.td"
4972 //===----------------------------------------------------------------------===//
4973 // Assembler aliases
4977 def : InstAlias<"dmb", (DMB 0xf)>, Requires<[IsARM, HasDB]>;
4978 def : InstAlias<"dsb", (DSB 0xf)>, Requires<[IsARM, HasDB]>;
4979 def : InstAlias<"isb", (ISB 0xf)>, Requires<[IsARM, HasDB]>;
4981 // System instructions
4982 def : MnemonicAlias<"swi", "svc">;
4984 // Load / Store Multiple
4985 def : MnemonicAlias<"ldmfd", "ldm">;
4986 def : MnemonicAlias<"ldmia", "ldm">;
4987 def : MnemonicAlias<"ldmea", "ldmdb">;
4988 def : MnemonicAlias<"stmfd", "stmdb">;
4989 def : MnemonicAlias<"stmia", "stm">;
4990 def : MnemonicAlias<"stmea", "stm">;
4992 // PKHBT/PKHTB with default shift amount. PKHTB is equivalent to PKHBT when the
4993 // shift amount is zero (i.e., unspecified).
4994 def : InstAlias<"pkhbt${p} $Rd, $Rn, $Rm",
4995 (PKHBT GPRnopc:$Rd, GPRnopc:$Rn, GPRnopc:$Rm, 0, pred:$p)>,
4996 Requires<[IsARM, HasV6]>;
4997 def : InstAlias<"pkhtb${p} $Rd, $Rn, $Rm",
4998 (PKHBT GPRnopc:$Rd, GPRnopc:$Rn, GPRnopc:$Rm, 0, pred:$p)>,
4999 Requires<[IsARM, HasV6]>;
5001 // PUSH/POP aliases for STM/LDM
5002 def : ARMInstAlias<"push${p} $regs", (STMDB_UPD SP, pred:$p, reglist:$regs)>;
5003 def : ARMInstAlias<"pop${p} $regs", (LDMIA_UPD SP, pred:$p, reglist:$regs)>;
5005 // SSAT/USAT optional shift operand.
5006 def : ARMInstAlias<"ssat${p} $Rd, $sat_imm, $Rn",
5007 (SSAT GPRnopc:$Rd, imm1_32:$sat_imm, GPRnopc:$Rn, 0, pred:$p)>;
5008 def : ARMInstAlias<"usat${p} $Rd, $sat_imm, $Rn",
5009 (USAT GPRnopc:$Rd, imm0_31:$sat_imm, GPRnopc:$Rn, 0, pred:$p)>;
5012 // Extend instruction optional rotate operand.
5013 def : ARMInstAlias<"sxtab${p} $Rd, $Rn, $Rm",
5014 (SXTAB GPRnopc:$Rd, GPR:$Rn, GPRnopc:$Rm, 0, pred:$p)>;
5015 def : ARMInstAlias<"sxtah${p} $Rd, $Rn, $Rm",
5016 (SXTAH GPRnopc:$Rd, GPR:$Rn, GPRnopc:$Rm, 0, pred:$p)>;
5017 def : ARMInstAlias<"sxtab16${p} $Rd, $Rn, $Rm",
5018 (SXTAB16 GPRnopc:$Rd, GPR:$Rn, GPRnopc:$Rm, 0, pred:$p)>;
5019 def : ARMInstAlias<"sxtb${p} $Rd, $Rm",
5020 (SXTB GPRnopc:$Rd, GPRnopc:$Rm, 0, pred:$p)>;
5021 def : ARMInstAlias<"sxtb16${p} $Rd, $Rm",
5022 (SXTB16 GPRnopc:$Rd, GPRnopc:$Rm, 0, pred:$p)>;
5023 def : ARMInstAlias<"sxth${p} $Rd, $Rm",
5024 (SXTH GPRnopc:$Rd, GPRnopc:$Rm, 0, pred:$p)>;
5026 def : ARMInstAlias<"uxtab${p} $Rd, $Rn, $Rm",
5027 (UXTAB GPRnopc:$Rd, GPR:$Rn, GPRnopc:$Rm, 0, pred:$p)>;
5028 def : ARMInstAlias<"uxtah${p} $Rd, $Rn, $Rm",
5029 (UXTAH GPRnopc:$Rd, GPR:$Rn, GPRnopc:$Rm, 0, pred:$p)>;
5030 def : ARMInstAlias<"uxtab16${p} $Rd, $Rn, $Rm",
5031 (UXTAB16 GPRnopc:$Rd, GPR:$Rn, GPRnopc:$Rm, 0, pred:$p)>;
5032 def : ARMInstAlias<"uxtb${p} $Rd, $Rm",
5033 (UXTB GPRnopc:$Rd, GPRnopc:$Rm, 0, pred:$p)>;
5034 def : ARMInstAlias<"uxtb16${p} $Rd, $Rm",
5035 (UXTB16 GPRnopc:$Rd, GPRnopc:$Rm, 0, pred:$p)>;
5036 def : ARMInstAlias<"uxth${p} $Rd, $Rm",
5037 (UXTH GPRnopc:$Rd, GPRnopc:$Rm, 0, pred:$p)>;
5041 def : MnemonicAlias<"rfefa", "rfeda">;
5042 def : MnemonicAlias<"rfeea", "rfedb">;
5043 def : MnemonicAlias<"rfefd", "rfeia">;
5044 def : MnemonicAlias<"rfeed", "rfeib">;
5045 def : MnemonicAlias<"rfe", "rfeia">;
5048 def : MnemonicAlias<"srsfa", "srsda">;
5049 def : MnemonicAlias<"srsea", "srsdb">;
5050 def : MnemonicAlias<"srsfd", "srsia">;
5051 def : MnemonicAlias<"srsed", "srsib">;
5052 def : MnemonicAlias<"srs", "srsia">;
5055 def : MnemonicAlias<"qsubaddx", "qsax">;
5057 def : MnemonicAlias<"saddsubx", "sasx">;
5058 // SHASX == SHADDSUBX
5059 def : MnemonicAlias<"shaddsubx", "shasx">;
5060 // SHSAX == SHSUBADDX
5061 def : MnemonicAlias<"shsubaddx", "shsax">;
5063 def : MnemonicAlias<"ssubaddx", "ssax">;
5065 def : MnemonicAlias<"uaddsubx", "uasx">;
5066 // UHASX == UHADDSUBX
5067 def : MnemonicAlias<"uhaddsubx", "uhasx">;
5068 // UHSAX == UHSUBADDX
5069 def : MnemonicAlias<"uhsubaddx", "uhsax">;
5070 // UQASX == UQADDSUBX
5071 def : MnemonicAlias<"uqaddsubx", "uqasx">;
5072 // UQSAX == UQSUBADDX
5073 def : MnemonicAlias<"uqsubaddx", "uqsax">;
5075 def : MnemonicAlias<"usubaddx", "usax">;
5077 // "mov Rd, so_imm_not" can be handled via "mvn" in assembly, just like
5079 def : ARMInstAlias<"mov${s}${p} $Rd, $imm",
5080 (MVNi rGPR:$Rd, so_imm_not:$imm, pred:$p, cc_out:$s)>;
5081 def : ARMInstAlias<"mvn${s}${p} $Rd, $imm",
5082 (MOVi rGPR:$Rd, so_imm_not:$imm, pred:$p, cc_out:$s)>;
5083 // Same for AND <--> BIC
5084 def : ARMInstAlias<"bic${s}${p} $Rd, $Rn, $imm",
5085 (ANDri rGPR:$Rd, rGPR:$Rn, so_imm_not:$imm,
5086 pred:$p, cc_out:$s)>;
5087 def : ARMInstAlias<"bic${s}${p} $Rdn, $imm",
5088 (ANDri rGPR:$Rdn, rGPR:$Rdn, so_imm_not:$imm,
5089 pred:$p, cc_out:$s)>;
5090 def : ARMInstAlias<"and${s}${p} $Rd, $Rn, $imm",
5091 (BICri rGPR:$Rd, rGPR:$Rn, so_imm_not:$imm,
5092 pred:$p, cc_out:$s)>;
5093 def : ARMInstAlias<"and${s}${p} $Rdn, $imm",
5094 (BICri rGPR:$Rdn, rGPR:$Rdn, so_imm_not:$imm,
5095 pred:$p, cc_out:$s)>;
5097 // Likewise, "add Rd, so_imm_neg" -> sub
5098 def : ARMInstAlias<"add${s}${p} $Rd, $Rn, $imm",
5099 (SUBri GPR:$Rd, GPR:$Rn, so_imm_neg:$imm, pred:$p, cc_out:$s)>;
5100 def : ARMInstAlias<"add${s}${p} $Rd, $imm",
5101 (SUBri GPR:$Rd, GPR:$Rd, so_imm_neg:$imm, pred:$p, cc_out:$s)>;
5102 // Same for CMP <--> CMN via so_imm_neg
5103 def : ARMInstAlias<"cmp${p} $Rd, $imm",
5104 (CMNzri rGPR:$Rd, so_imm_neg:$imm, pred:$p)>;
5105 def : ARMInstAlias<"cmn${p} $Rd, $imm",
5106 (CMPri rGPR:$Rd, so_imm_neg:$imm, pred:$p)>;
5108 // The shifter forms of the MOV instruction are aliased to the ASR, LSL,
5109 // LSR, ROR, and RRX instructions.
5110 // FIXME: We need C++ parser hooks to map the alias to the MOV
5111 // encoding. It seems we should be able to do that sort of thing
5112 // in tblgen, but it could get ugly.
5113 def ASRi : ARMAsmPseudo<"asr${s}${p} $Rd, $Rm, $imm",
5114 (ins GPR:$Rd, GPR:$Rm, imm0_32:$imm, pred:$p,
5116 def LSRi : ARMAsmPseudo<"lsr${s}${p} $Rd, $Rm, $imm",
5117 (ins GPR:$Rd, GPR:$Rm, imm0_32:$imm, pred:$p,
5119 def LSLi : ARMAsmPseudo<"lsl${s}${p} $Rd, $Rm, $imm",
5120 (ins GPR:$Rd, GPR:$Rm, imm0_31:$imm, pred:$p,
5122 def RORi : ARMAsmPseudo<"ror${s}${p} $Rd, $Rm, $imm",
5123 (ins GPR:$Rd, GPR:$Rm, imm0_31:$imm, pred:$p,
5125 def RRXi : ARMAsmPseudo<"rrx${s}${p} $Rd, $Rm",
5126 (ins GPRnopc:$Rd, GPRnopc:$Rm, pred:$p, cc_out:$s)>;
5127 def ASRr : ARMAsmPseudo<"asr${s}${p} $Rd, $Rn, $Rm",
5128 (ins GPRnopc:$Rd, GPRnopc:$Rn, GPRnopc:$Rm, pred:$p,
5130 def LSRr : ARMAsmPseudo<"lsr${s}${p} $Rd, $Rn, $Rm",
5131 (ins GPRnopc:$Rd, GPRnopc:$Rn, GPRnopc:$Rm, pred:$p,
5133 def LSLr : ARMAsmPseudo<"lsl${s}${p} $Rd, $Rn, $Rm",
5134 (ins GPRnopc:$Rd, GPRnopc:$Rn, GPRnopc:$Rm, pred:$p,
5136 def RORr : ARMAsmPseudo<"ror${s}${p} $Rd, $Rn, $Rm",
5137 (ins GPRnopc:$Rd, GPRnopc:$Rn, GPRnopc:$Rm, pred:$p,
5139 // shifter instructions also support a two-operand form.
5140 def : ARMInstAlias<"asr${s}${p} $Rm, $imm",
5141 (ASRi GPR:$Rm, GPR:$Rm, imm0_32:$imm, pred:$p, cc_out:$s)>;
5142 def : ARMInstAlias<"lsr${s}${p} $Rm, $imm",
5143 (LSRi GPR:$Rm, GPR:$Rm, imm0_32:$imm, pred:$p, cc_out:$s)>;
5144 def : ARMInstAlias<"lsl${s}${p} $Rm, $imm",
5145 (LSLi GPR:$Rm, GPR:$Rm, imm0_31:$imm, pred:$p, cc_out:$s)>;
5146 def : ARMInstAlias<"ror${s}${p} $Rm, $imm",
5147 (RORi GPR:$Rm, GPR:$Rm, imm0_31:$imm, pred:$p, cc_out:$s)>;
5148 def : ARMInstAlias<"asr${s}${p} $Rn, $Rm",
5149 (ASRr GPRnopc:$Rn, GPRnopc:$Rn, GPRnopc:$Rm, pred:$p,
5151 def : ARMInstAlias<"lsr${s}${p} $Rn, $Rm",
5152 (LSRr GPRnopc:$Rn, GPRnopc:$Rn, GPRnopc:$Rm, pred:$p,
5154 def : ARMInstAlias<"lsl${s}${p} $Rn, $Rm",
5155 (LSLr GPRnopc:$Rn, GPRnopc:$Rn, GPRnopc:$Rm, pred:$p,
5157 def : ARMInstAlias<"ror${s}${p} $Rn, $Rm",
5158 (RORr GPRnopc:$Rn, GPRnopc:$Rn, GPRnopc:$Rm, pred:$p,
5162 // 'mul' instruction can be specified with only two operands.
5163 def : ARMInstAlias<"mul${s}${p} $Rn, $Rm",
5164 (MUL rGPR:$Rn, rGPR:$Rm, rGPR:$Rn, pred:$p, cc_out:$s)>;
5166 // "neg" is and alias for "rsb rd, rn, #0"
5167 def : ARMInstAlias<"neg${s}${p} $Rd, $Rm",
5168 (RSBri GPR:$Rd, GPR:$Rm, 0, pred:$p, cc_out:$s)>;