1 //===- ARMInstrInfo.td - Target Description for ARM Target -*- tablegen -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file describes the ARM instructions in TableGen format.
12 //===----------------------------------------------------------------------===//
14 //===----------------------------------------------------------------------===//
15 // ARM specific DAG Nodes.
19 def SDT_ARMCallSeqStart : SDCallSeqStart<[ SDTCisVT<0, i32> ]>;
20 def SDT_ARMCallSeqEnd : SDCallSeqEnd<[ SDTCisVT<0, i32>, SDTCisVT<1, i32> ]>;
21 def SDT_ARMStructByVal : SDTypeProfile<0, 4,
22 [SDTCisVT<0, i32>, SDTCisVT<1, i32>,
23 SDTCisVT<2, i32>, SDTCisVT<3, i32>]>;
25 def SDT_ARMSaveCallPC : SDTypeProfile<0, 1, []>;
27 def SDT_ARMcall : SDTypeProfile<0, -1, [SDTCisPtrTy<0>]>;
29 def SDT_ARMCMov : SDTypeProfile<1, 3,
30 [SDTCisSameAs<0, 1>, SDTCisSameAs<0, 2>,
33 def SDT_ARMBrcond : SDTypeProfile<0, 2,
34 [SDTCisVT<0, OtherVT>, SDTCisVT<1, i32>]>;
36 def SDT_ARMBrJT : SDTypeProfile<0, 3,
37 [SDTCisPtrTy<0>, SDTCisVT<1, i32>,
40 def SDT_ARMBr2JT : SDTypeProfile<0, 4,
41 [SDTCisPtrTy<0>, SDTCisVT<1, i32>,
42 SDTCisVT<2, i32>, SDTCisVT<3, i32>]>;
44 def SDT_ARMBCC_i64 : SDTypeProfile<0, 6,
46 SDTCisVT<1, i32>, SDTCisVT<2, i32>,
47 SDTCisVT<3, i32>, SDTCisVT<4, i32>,
48 SDTCisVT<5, OtherVT>]>;
50 def SDT_ARMAnd : SDTypeProfile<1, 2,
51 [SDTCisVT<0, i32>, SDTCisVT<1, i32>,
54 def SDT_ARMCmp : SDTypeProfile<0, 2, [SDTCisSameAs<0, 1>]>;
56 def SDT_ARMPICAdd : SDTypeProfile<1, 2, [SDTCisSameAs<0, 1>,
57 SDTCisPtrTy<1>, SDTCisVT<2, i32>]>;
59 def SDT_ARMThreadPointer : SDTypeProfile<1, 0, [SDTCisPtrTy<0>]>;
60 def SDT_ARMEH_SJLJ_Setjmp : SDTypeProfile<1, 2, [SDTCisInt<0>, SDTCisPtrTy<1>,
62 def SDT_ARMEH_SJLJ_Longjmp: SDTypeProfile<0, 2, [SDTCisPtrTy<0>, SDTCisInt<1>]>;
64 def SDT_ARMMEMBARRIER : SDTypeProfile<0, 1, [SDTCisInt<0>]>;
66 def SDT_ARMPREFETCH : SDTypeProfile<0, 3, [SDTCisPtrTy<0>, SDTCisSameAs<1, 2>,
69 def SDT_ARMTCRET : SDTypeProfile<0, 1, [SDTCisPtrTy<0>]>;
71 def SDT_ARMBFI : SDTypeProfile<1, 3, [SDTCisVT<0, i32>, SDTCisVT<1, i32>,
72 SDTCisVT<2, i32>, SDTCisVT<3, i32>]>;
74 def SDTBinaryArithWithFlags : SDTypeProfile<2, 2,
77 SDTCisInt<0>, SDTCisVT<1, i32>]>;
79 // SDTBinaryArithWithFlagsInOut - RES1, CPSR = op LHS, RHS, CPSR
80 def SDTBinaryArithWithFlagsInOut : SDTypeProfile<2, 3,
87 def SDT_ARM64bitmlal : SDTypeProfile<2,4, [ SDTCisVT<0, i32>, SDTCisVT<1, i32>,
88 SDTCisVT<2, i32>, SDTCisVT<3, i32>,
89 SDTCisVT<4, i32>, SDTCisVT<5, i32> ] >;
90 def ARMUmlal : SDNode<"ARMISD::UMLAL", SDT_ARM64bitmlal>;
91 def ARMSmlal : SDNode<"ARMISD::SMLAL", SDT_ARM64bitmlal>;
94 def ARMWrapper : SDNode<"ARMISD::Wrapper", SDTIntUnaryOp>;
95 def ARMWrapperDYN : SDNode<"ARMISD::WrapperDYN", SDTIntUnaryOp>;
96 def ARMWrapperPIC : SDNode<"ARMISD::WrapperPIC", SDTIntUnaryOp>;
97 def ARMWrapperJT : SDNode<"ARMISD::WrapperJT", SDTIntBinOp>;
99 def ARMcallseq_start : SDNode<"ISD::CALLSEQ_START", SDT_ARMCallSeqStart,
100 [SDNPHasChain, SDNPSideEffect, SDNPOutGlue]>;
101 def ARMcallseq_end : SDNode<"ISD::CALLSEQ_END", SDT_ARMCallSeqEnd,
102 [SDNPHasChain, SDNPSideEffect,
103 SDNPOptInGlue, SDNPOutGlue]>;
104 def ARMcopystructbyval : SDNode<"ARMISD::COPY_STRUCT_BYVAL" ,
106 [SDNPHasChain, SDNPInGlue, SDNPOutGlue,
107 SDNPMayStore, SDNPMayLoad]>;
109 def ARMcall : SDNode<"ARMISD::CALL", SDT_ARMcall,
110 [SDNPHasChain, SDNPOptInGlue, SDNPOutGlue,
112 def ARMcall_pred : SDNode<"ARMISD::CALL_PRED", SDT_ARMcall,
113 [SDNPHasChain, SDNPOptInGlue, SDNPOutGlue,
115 def ARMcall_nolink : SDNode<"ARMISD::CALL_NOLINK", SDT_ARMcall,
116 [SDNPHasChain, SDNPOptInGlue, SDNPOutGlue,
119 def ARMretflag : SDNode<"ARMISD::RET_FLAG", SDTNone,
120 [SDNPHasChain, SDNPOptInGlue, SDNPVariadic]>;
122 def ARMcmov : SDNode<"ARMISD::CMOV", SDT_ARMCMov,
125 def ARMbrcond : SDNode<"ARMISD::BRCOND", SDT_ARMBrcond,
126 [SDNPHasChain, SDNPInGlue, SDNPOutGlue]>;
128 def ARMbrjt : SDNode<"ARMISD::BR_JT", SDT_ARMBrJT,
130 def ARMbr2jt : SDNode<"ARMISD::BR2_JT", SDT_ARMBr2JT,
133 def ARMBcci64 : SDNode<"ARMISD::BCC_i64", SDT_ARMBCC_i64,
136 def ARMcmp : SDNode<"ARMISD::CMP", SDT_ARMCmp,
139 def ARMcmn : SDNode<"ARMISD::CMN", SDT_ARMCmp,
142 def ARMcmpZ : SDNode<"ARMISD::CMPZ", SDT_ARMCmp,
143 [SDNPOutGlue, SDNPCommutative]>;
145 def ARMpic_add : SDNode<"ARMISD::PIC_ADD", SDT_ARMPICAdd>;
147 def ARMsrl_flag : SDNode<"ARMISD::SRL_FLAG", SDTIntUnaryOp, [SDNPOutGlue]>;
148 def ARMsra_flag : SDNode<"ARMISD::SRA_FLAG", SDTIntUnaryOp, [SDNPOutGlue]>;
149 def ARMrrx : SDNode<"ARMISD::RRX" , SDTIntUnaryOp, [SDNPInGlue ]>;
151 def ARMaddc : SDNode<"ARMISD::ADDC", SDTBinaryArithWithFlags,
153 def ARMsubc : SDNode<"ARMISD::SUBC", SDTBinaryArithWithFlags>;
154 def ARMadde : SDNode<"ARMISD::ADDE", SDTBinaryArithWithFlagsInOut>;
155 def ARMsube : SDNode<"ARMISD::SUBE", SDTBinaryArithWithFlagsInOut>;
157 def ARMthread_pointer: SDNode<"ARMISD::THREAD_POINTER", SDT_ARMThreadPointer>;
158 def ARMeh_sjlj_setjmp: SDNode<"ARMISD::EH_SJLJ_SETJMP",
159 SDT_ARMEH_SJLJ_Setjmp,
160 [SDNPHasChain, SDNPSideEffect]>;
161 def ARMeh_sjlj_longjmp: SDNode<"ARMISD::EH_SJLJ_LONGJMP",
162 SDT_ARMEH_SJLJ_Longjmp,
163 [SDNPHasChain, SDNPSideEffect]>;
165 def ARMMemBarrier : SDNode<"ARMISD::MEMBARRIER", SDT_ARMMEMBARRIER,
166 [SDNPHasChain, SDNPSideEffect]>;
167 def ARMMemBarrierMCR : SDNode<"ARMISD::MEMBARRIER_MCR", SDT_ARMMEMBARRIER,
168 [SDNPHasChain, SDNPSideEffect]>;
169 def ARMPreload : SDNode<"ARMISD::PRELOAD", SDT_ARMPREFETCH,
170 [SDNPHasChain, SDNPMayLoad, SDNPMayStore]>;
172 def ARMrbit : SDNode<"ARMISD::RBIT", SDTIntUnaryOp>;
174 def ARMtcret : SDNode<"ARMISD::TC_RETURN", SDT_ARMTCRET,
175 [SDNPHasChain, SDNPOptInGlue, SDNPVariadic]>;
178 def ARMbfi : SDNode<"ARMISD::BFI", SDT_ARMBFI>;
180 //===----------------------------------------------------------------------===//
181 // ARM Instruction Predicate Definitions.
183 def HasV4T : Predicate<"Subtarget->hasV4TOps()">,
184 AssemblerPredicate<"HasV4TOps", "armv4t">;
185 def NoV4T : Predicate<"!Subtarget->hasV4TOps()">;
186 def HasV5T : Predicate<"Subtarget->hasV5TOps()">;
187 def HasV5TE : Predicate<"Subtarget->hasV5TEOps()">,
188 AssemblerPredicate<"HasV5TEOps", "armv5te">;
189 def HasV6 : Predicate<"Subtarget->hasV6Ops()">,
190 AssemblerPredicate<"HasV6Ops", "armv6">;
191 def NoV6 : Predicate<"!Subtarget->hasV6Ops()">;
192 def HasV6T2 : Predicate<"Subtarget->hasV6T2Ops()">,
193 AssemblerPredicate<"HasV6T2Ops", "armv6t2">;
194 def NoV6T2 : Predicate<"!Subtarget->hasV6T2Ops()">;
195 def HasV7 : Predicate<"Subtarget->hasV7Ops()">,
196 AssemblerPredicate<"HasV7Ops", "armv7">;
197 def NoVFP : Predicate<"!Subtarget->hasVFP2()">;
198 def HasVFP2 : Predicate<"Subtarget->hasVFP2()">,
199 AssemblerPredicate<"FeatureVFP2", "VFP2">;
200 def HasVFP3 : Predicate<"Subtarget->hasVFP3()">,
201 AssemblerPredicate<"FeatureVFP3", "VFP3">;
202 def HasVFP4 : Predicate<"Subtarget->hasVFP4()">,
203 AssemblerPredicate<"FeatureVFP4", "VFP4">;
204 def HasNEON : Predicate<"Subtarget->hasNEON()">,
205 AssemblerPredicate<"FeatureNEON", "NEON">;
206 def HasFP16 : Predicate<"Subtarget->hasFP16()">,
207 AssemblerPredicate<"FeatureFP16","half-float">;
208 def HasDivide : Predicate<"Subtarget->hasDivide()">,
209 AssemblerPredicate<"FeatureHWDiv", "divide">;
210 def HasDivideInARM : Predicate<"Subtarget->hasDivideInARMMode()">,
211 AssemblerPredicate<"FeatureHWDivARM">;
212 def HasT2ExtractPack : Predicate<"Subtarget->hasT2ExtractPack()">,
213 AssemblerPredicate<"FeatureT2XtPk",
215 def HasThumb2DSP : Predicate<"Subtarget->hasThumb2DSP()">,
216 AssemblerPredicate<"FeatureDSPThumb2",
218 def HasDB : Predicate<"Subtarget->hasDataBarrier()">,
219 AssemblerPredicate<"FeatureDB",
221 def HasMP : Predicate<"Subtarget->hasMPExtension()">,
222 AssemblerPredicate<"FeatureMP",
224 def HasTrustZone : Predicate<"Subtarget->hasTrustZone()">,
225 AssemblerPredicate<"FeatureTrustZone",
227 def UseNEONForFP : Predicate<"Subtarget->useNEONForSinglePrecisionFP()">;
228 def DontUseNEONForFP : Predicate<"!Subtarget->useNEONForSinglePrecisionFP()">;
229 def IsThumb : Predicate<"Subtarget->isThumb()">,
230 AssemblerPredicate<"ModeThumb", "thumb">;
231 def IsThumb1Only : Predicate<"Subtarget->isThumb1Only()">;
232 def IsThumb2 : Predicate<"Subtarget->isThumb2()">,
233 AssemblerPredicate<"ModeThumb,FeatureThumb2",
235 def IsMClass : Predicate<"Subtarget->isMClass()">,
236 AssemblerPredicate<"FeatureMClass", "armv7m">;
237 def IsARClass : Predicate<"!Subtarget->isMClass()">,
238 AssemblerPredicate<"!FeatureMClass",
240 def IsARM : Predicate<"!Subtarget->isThumb()">,
241 AssemblerPredicate<"!ModeThumb", "arm-mode">;
242 def IsIOS : Predicate<"Subtarget->isTargetIOS()">;
243 def IsNotIOS : Predicate<"!Subtarget->isTargetIOS()">;
244 def IsNaCl : Predicate<"Subtarget->isTargetNaCl()">;
245 def UseNaClTrap : Predicate<"Subtarget->useNaClTrap()">,
246 AssemblerPredicate<"FeatureNaClTrap", "NaCl">;
247 def DontUseNaClTrap : Predicate<"!Subtarget->useNaClTrap()">;
249 // FIXME: Eventually this will be just "hasV6T2Ops".
250 def UseMovt : Predicate<"Subtarget->useMovt()">;
251 def DontUseMovt : Predicate<"!Subtarget->useMovt()">;
252 def UseFPVMLx : Predicate<"Subtarget->useFPVMLx()">;
253 def UseMulOps : Predicate<"Subtarget->useMulOps()">;
255 // Prefer fused MAC for fp mul + add over fp VMLA / VMLS if they are available.
256 // But only select them if more precision in FP computation is allowed.
257 // Do not use them for Darwin platforms.
258 def UseFusedMAC : Predicate<"(TM.Options.AllowFPOpFusion =="
259 " FPOpFusion::Fast) && "
260 "!Subtarget->isTargetDarwin()">;
261 def DontUseFusedMAC : Predicate<"!Subtarget->hasVFP4() || "
262 "Subtarget->isTargetDarwin()">;
264 // VGETLNi32 is microcoded on Swift - prefer VMOV.
265 def HasFastVGETLNi32 : Predicate<"!Subtarget->isSwift()">;
266 def HasSlowVGETLNi32 : Predicate<"Subtarget->isSwift()">;
268 // VDUP.32 is microcoded on Swift - prefer VMOV.
269 def HasFastVDUP32 : Predicate<"!Subtarget->isSwift()">;
270 def HasSlowVDUP32 : Predicate<"Subtarget->isSwift()">;
272 // Cortex-A9 prefers VMOVSR to VMOVDRR even when using NEON for scalar FP, as
273 // this allows more effective execution domain optimization. See
274 // setExecutionDomain().
275 def UseVMOVSR : Predicate<"Subtarget->isCortexA9() || !Subtarget->useNEONForSinglePrecisionFP()">;
276 def DontUseVMOVSR : Predicate<"!Subtarget->isCortexA9() && Subtarget->useNEONForSinglePrecisionFP()">;
278 def IsLE : Predicate<"getTargetLowering()->isLittleEndian()">;
279 def IsBE : Predicate<"getTargetLowering()->isBigEndian()">;
281 //===----------------------------------------------------------------------===//
282 // ARM Flag Definitions.
284 class RegConstraint<string C> {
285 string Constraints = C;
288 //===----------------------------------------------------------------------===//
289 // ARM specific transformation functions and pattern fragments.
292 // imm_neg_XFORM - Return the negation of an i32 immediate value.
293 def imm_neg_XFORM : SDNodeXForm<imm, [{
294 return CurDAG->getTargetConstant(-(int)N->getZExtValue(), MVT::i32);
297 // imm_not_XFORM - Return the complement of a i32 immediate value.
298 def imm_not_XFORM : SDNodeXForm<imm, [{
299 return CurDAG->getTargetConstant(~(int)N->getZExtValue(), MVT::i32);
302 /// imm16_31 predicate - True if the 32-bit immediate is in the range [16,31].
303 def imm16_31 : ImmLeaf<i32, [{
304 return (int32_t)Imm >= 16 && (int32_t)Imm < 32;
307 def so_imm_neg_asmoperand : AsmOperandClass { let Name = "ARMSOImmNeg"; }
308 def so_imm_neg : Operand<i32>, PatLeaf<(imm), [{
309 unsigned Value = -(unsigned)N->getZExtValue();
310 return Value && ARM_AM::getSOImmVal(Value) != -1;
312 let ParserMatchClass = so_imm_neg_asmoperand;
315 // Note: this pattern doesn't require an encoder method and such, as it's
316 // only used on aliases (Pat<> and InstAlias<>). The actual encoding
317 // is handled by the destination instructions, which use so_imm.
318 def so_imm_not_asmoperand : AsmOperandClass { let Name = "ARMSOImmNot"; }
319 def so_imm_not : Operand<i32>, PatLeaf<(imm), [{
320 return ARM_AM::getSOImmVal(~(uint32_t)N->getZExtValue()) != -1;
322 let ParserMatchClass = so_imm_not_asmoperand;
325 // sext_16_node predicate - True if the SDNode is sign-extended 16 or more bits.
326 def sext_16_node : PatLeaf<(i32 GPR:$a), [{
327 return CurDAG->ComputeNumSignBits(SDValue(N,0)) >= 17;
330 /// Split a 32-bit immediate into two 16 bit parts.
331 def hi16 : SDNodeXForm<imm, [{
332 return CurDAG->getTargetConstant((uint32_t)N->getZExtValue() >> 16, MVT::i32);
335 def lo16AllZero : PatLeaf<(i32 imm), [{
336 // Returns true if all low 16-bits are 0.
337 return (((uint32_t)N->getZExtValue()) & 0xFFFFUL) == 0;
340 class BinOpWithFlagFrag<dag res> :
341 PatFrag<(ops node:$LHS, node:$RHS, node:$FLAG), res>;
342 class BinOpFrag<dag res> : PatFrag<(ops node:$LHS, node:$RHS), res>;
343 class UnOpFrag <dag res> : PatFrag<(ops node:$Src), res>;
345 // An 'and' node with a single use.
346 def and_su : PatFrag<(ops node:$lhs, node:$rhs), (and node:$lhs, node:$rhs), [{
347 return N->hasOneUse();
350 // An 'xor' node with a single use.
351 def xor_su : PatFrag<(ops node:$lhs, node:$rhs), (xor node:$lhs, node:$rhs), [{
352 return N->hasOneUse();
355 // An 'fmul' node with a single use.
356 def fmul_su : PatFrag<(ops node:$lhs, node:$rhs), (fmul node:$lhs, node:$rhs),[{
357 return N->hasOneUse();
360 // An 'fadd' node which checks for single non-hazardous use.
361 def fadd_mlx : PatFrag<(ops node:$lhs, node:$rhs),(fadd node:$lhs, node:$rhs),[{
362 return hasNoVMLxHazardUse(N);
365 // An 'fsub' node which checks for single non-hazardous use.
366 def fsub_mlx : PatFrag<(ops node:$lhs, node:$rhs),(fsub node:$lhs, node:$rhs),[{
367 return hasNoVMLxHazardUse(N);
370 //===----------------------------------------------------------------------===//
371 // Operand Definitions.
374 // Immediate operands with a shared generic asm render method.
375 class ImmAsmOperand : AsmOperandClass { let RenderMethod = "addImmOperands"; }
378 // FIXME: rename brtarget to t2_brtarget
379 def brtarget : Operand<OtherVT> {
380 let EncoderMethod = "getBranchTargetOpValue";
381 let OperandType = "OPERAND_PCREL";
382 let DecoderMethod = "DecodeT2BROperand";
385 // FIXME: get rid of this one?
386 def uncondbrtarget : Operand<OtherVT> {
387 let EncoderMethod = "getUnconditionalBranchTargetOpValue";
388 let OperandType = "OPERAND_PCREL";
391 // Branch target for ARM. Handles conditional/unconditional
392 def br_target : Operand<OtherVT> {
393 let EncoderMethod = "getARMBranchTargetOpValue";
394 let OperandType = "OPERAND_PCREL";
398 // FIXME: rename bltarget to t2_bl_target?
399 def bltarget : Operand<i32> {
400 // Encoded the same as branch targets.
401 let EncoderMethod = "getBranchTargetOpValue";
402 let OperandType = "OPERAND_PCREL";
405 // Call target for ARM. Handles conditional/unconditional
406 // FIXME: rename bl_target to t2_bltarget?
407 def bl_target : Operand<i32> {
408 let EncoderMethod = "getARMBLTargetOpValue";
409 let OperandType = "OPERAND_PCREL";
412 def blx_target : Operand<i32> {
413 let EncoderMethod = "getARMBLXTargetOpValue";
414 let OperandType = "OPERAND_PCREL";
417 // A list of registers separated by comma. Used by load/store multiple.
418 def RegListAsmOperand : AsmOperandClass { let Name = "RegList"; }
419 def reglist : Operand<i32> {
420 let EncoderMethod = "getRegisterListOpValue";
421 let ParserMatchClass = RegListAsmOperand;
422 let PrintMethod = "printRegisterList";
423 let DecoderMethod = "DecodeRegListOperand";
426 def GPRPairOp : RegisterOperand<GPRPair, "printGPRPairOperand">;
428 def DPRRegListAsmOperand : AsmOperandClass { let Name = "DPRRegList"; }
429 def dpr_reglist : Operand<i32> {
430 let EncoderMethod = "getRegisterListOpValue";
431 let ParserMatchClass = DPRRegListAsmOperand;
432 let PrintMethod = "printRegisterList";
433 let DecoderMethod = "DecodeDPRRegListOperand";
436 def SPRRegListAsmOperand : AsmOperandClass { let Name = "SPRRegList"; }
437 def spr_reglist : Operand<i32> {
438 let EncoderMethod = "getRegisterListOpValue";
439 let ParserMatchClass = SPRRegListAsmOperand;
440 let PrintMethod = "printRegisterList";
441 let DecoderMethod = "DecodeSPRRegListOperand";
444 // An operand for the CONSTPOOL_ENTRY pseudo-instruction.
445 def cpinst_operand : Operand<i32> {
446 let PrintMethod = "printCPInstOperand";
450 def pclabel : Operand<i32> {
451 let PrintMethod = "printPCLabel";
454 // ADR instruction labels.
455 def AdrLabelAsmOperand : AsmOperandClass { let Name = "AdrLabel"; }
456 def adrlabel : Operand<i32> {
457 let EncoderMethod = "getAdrLabelOpValue";
458 let ParserMatchClass = AdrLabelAsmOperand;
459 let PrintMethod = "printAdrLabelOperand";
462 def neon_vcvt_imm32 : Operand<i32> {
463 let EncoderMethod = "getNEONVcvtImm32OpValue";
464 let DecoderMethod = "DecodeVCVTImmOperand";
467 // rot_imm: An integer that encodes a rotate amount. Must be 8, 16, or 24.
468 def rot_imm_XFORM: SDNodeXForm<imm, [{
469 switch (N->getZExtValue()){
471 case 0: return CurDAG->getTargetConstant(0, MVT::i32);
472 case 8: return CurDAG->getTargetConstant(1, MVT::i32);
473 case 16: return CurDAG->getTargetConstant(2, MVT::i32);
474 case 24: return CurDAG->getTargetConstant(3, MVT::i32);
477 def RotImmAsmOperand : AsmOperandClass {
479 let ParserMethod = "parseRotImm";
481 def rot_imm : Operand<i32>, PatLeaf<(i32 imm), [{
482 int32_t v = N->getZExtValue();
483 return v == 8 || v == 16 || v == 24; }],
485 let PrintMethod = "printRotImmOperand";
486 let ParserMatchClass = RotImmAsmOperand;
489 // shift_imm: An integer that encodes a shift amount and the type of shift
490 // (asr or lsl). The 6-bit immediate encodes as:
493 // {4-0} imm5 shift amount.
494 // asr #32 encoded as imm5 == 0.
495 def ShifterImmAsmOperand : AsmOperandClass {
496 let Name = "ShifterImm";
497 let ParserMethod = "parseShifterImm";
499 def shift_imm : Operand<i32> {
500 let PrintMethod = "printShiftImmOperand";
501 let ParserMatchClass = ShifterImmAsmOperand;
504 // shifter_operand operands: so_reg_reg, so_reg_imm, and so_imm.
505 def ShiftedRegAsmOperand : AsmOperandClass { let Name = "RegShiftedReg"; }
506 def so_reg_reg : Operand<i32>, // reg reg imm
507 ComplexPattern<i32, 3, "SelectRegShifterOperand",
508 [shl, srl, sra, rotr]> {
509 let EncoderMethod = "getSORegRegOpValue";
510 let PrintMethod = "printSORegRegOperand";
511 let DecoderMethod = "DecodeSORegRegOperand";
512 let ParserMatchClass = ShiftedRegAsmOperand;
513 let MIOperandInfo = (ops GPRnopc, GPRnopc, i32imm);
516 def ShiftedImmAsmOperand : AsmOperandClass { let Name = "RegShiftedImm"; }
517 def so_reg_imm : Operand<i32>, // reg imm
518 ComplexPattern<i32, 2, "SelectImmShifterOperand",
519 [shl, srl, sra, rotr]> {
520 let EncoderMethod = "getSORegImmOpValue";
521 let PrintMethod = "printSORegImmOperand";
522 let DecoderMethod = "DecodeSORegImmOperand";
523 let ParserMatchClass = ShiftedImmAsmOperand;
524 let MIOperandInfo = (ops GPR, i32imm);
527 // FIXME: Does this need to be distinct from so_reg?
528 def shift_so_reg_reg : Operand<i32>, // reg reg imm
529 ComplexPattern<i32, 3, "SelectShiftRegShifterOperand",
530 [shl,srl,sra,rotr]> {
531 let EncoderMethod = "getSORegRegOpValue";
532 let PrintMethod = "printSORegRegOperand";
533 let DecoderMethod = "DecodeSORegRegOperand";
534 let ParserMatchClass = ShiftedRegAsmOperand;
535 let MIOperandInfo = (ops GPR, GPR, i32imm);
538 // FIXME: Does this need to be distinct from so_reg?
539 def shift_so_reg_imm : Operand<i32>, // reg reg imm
540 ComplexPattern<i32, 2, "SelectShiftImmShifterOperand",
541 [shl,srl,sra,rotr]> {
542 let EncoderMethod = "getSORegImmOpValue";
543 let PrintMethod = "printSORegImmOperand";
544 let DecoderMethod = "DecodeSORegImmOperand";
545 let ParserMatchClass = ShiftedImmAsmOperand;
546 let MIOperandInfo = (ops GPR, i32imm);
550 // so_imm - Match a 32-bit shifter_operand immediate operand, which is an
551 // 8-bit immediate rotated by an arbitrary number of bits.
552 def SOImmAsmOperand: ImmAsmOperand { let Name = "ARMSOImm"; }
553 def so_imm : Operand<i32>, ImmLeaf<i32, [{
554 return ARM_AM::getSOImmVal(Imm) != -1;
556 let EncoderMethod = "getSOImmOpValue";
557 let ParserMatchClass = SOImmAsmOperand;
558 let DecoderMethod = "DecodeSOImmOperand";
561 // Break so_imm's up into two pieces. This handles immediates with up to 16
562 // bits set in them. This uses so_imm2part to match and so_imm2part_[12] to
563 // get the first/second pieces.
564 def so_imm2part : PatLeaf<(imm), [{
565 return ARM_AM::isSOImmTwoPartVal((unsigned)N->getZExtValue());
568 /// arm_i32imm - True for +V6T2, or true only if so_imm2part is true.
570 def arm_i32imm : PatLeaf<(imm), [{
571 if (Subtarget->hasV6T2Ops())
573 return ARM_AM::isSOImmTwoPartVal((unsigned)N->getZExtValue());
576 /// imm0_1 predicate - Immediate in the range [0,1].
577 def Imm0_1AsmOperand: ImmAsmOperand { let Name = "Imm0_1"; }
578 def imm0_1 : Operand<i32> { let ParserMatchClass = Imm0_1AsmOperand; }
580 /// imm0_3 predicate - Immediate in the range [0,3].
581 def Imm0_3AsmOperand: ImmAsmOperand { let Name = "Imm0_3"; }
582 def imm0_3 : Operand<i32> { let ParserMatchClass = Imm0_3AsmOperand; }
584 /// imm0_4 predicate - Immediate in the range [0,4].
585 def Imm0_4AsmOperand : ImmAsmOperand
588 let DiagnosticType = "ImmRange0_4";
590 def imm0_4 : Operand<i32>, ImmLeaf<i32, [{ return Imm >= 0 && Imm < 5; }]> {
591 let ParserMatchClass = Imm0_4AsmOperand;
592 let DecoderMethod = "DecodeImm0_4";
595 /// imm0_7 predicate - Immediate in the range [0,7].
596 def Imm0_7AsmOperand: ImmAsmOperand { let Name = "Imm0_7"; }
597 def imm0_7 : Operand<i32>, ImmLeaf<i32, [{
598 return Imm >= 0 && Imm < 8;
600 let ParserMatchClass = Imm0_7AsmOperand;
603 /// imm8 predicate - Immediate is exactly 8.
604 def Imm8AsmOperand: ImmAsmOperand { let Name = "Imm8"; }
605 def imm8 : Operand<i32>, ImmLeaf<i32, [{ return Imm == 8; }]> {
606 let ParserMatchClass = Imm8AsmOperand;
609 /// imm16 predicate - Immediate is exactly 16.
610 def Imm16AsmOperand: ImmAsmOperand { let Name = "Imm16"; }
611 def imm16 : Operand<i32>, ImmLeaf<i32, [{ return Imm == 16; }]> {
612 let ParserMatchClass = Imm16AsmOperand;
615 /// imm32 predicate - Immediate is exactly 32.
616 def Imm32AsmOperand: ImmAsmOperand { let Name = "Imm32"; }
617 def imm32 : Operand<i32>, ImmLeaf<i32, [{ return Imm == 32; }]> {
618 let ParserMatchClass = Imm32AsmOperand;
621 /// imm1_7 predicate - Immediate in the range [1,7].
622 def Imm1_7AsmOperand: ImmAsmOperand { let Name = "Imm1_7"; }
623 def imm1_7 : Operand<i32>, ImmLeaf<i32, [{ return Imm > 0 && Imm < 8; }]> {
624 let ParserMatchClass = Imm1_7AsmOperand;
627 /// imm1_15 predicate - Immediate in the range [1,15].
628 def Imm1_15AsmOperand: ImmAsmOperand { let Name = "Imm1_15"; }
629 def imm1_15 : Operand<i32>, ImmLeaf<i32, [{ return Imm > 0 && Imm < 16; }]> {
630 let ParserMatchClass = Imm1_15AsmOperand;
633 /// imm1_31 predicate - Immediate in the range [1,31].
634 def Imm1_31AsmOperand: ImmAsmOperand { let Name = "Imm1_31"; }
635 def imm1_31 : Operand<i32>, ImmLeaf<i32, [{ return Imm > 0 && Imm < 32; }]> {
636 let ParserMatchClass = Imm1_31AsmOperand;
639 /// imm0_15 predicate - Immediate in the range [0,15].
640 def Imm0_15AsmOperand: ImmAsmOperand {
641 let Name = "Imm0_15";
642 let DiagnosticType = "ImmRange0_15";
644 def imm0_15 : Operand<i32>, ImmLeaf<i32, [{
645 return Imm >= 0 && Imm < 16;
647 let ParserMatchClass = Imm0_15AsmOperand;
650 /// imm0_31 predicate - True if the 32-bit immediate is in the range [0,31].
651 def Imm0_31AsmOperand: ImmAsmOperand { let Name = "Imm0_31"; }
652 def imm0_31 : Operand<i32>, ImmLeaf<i32, [{
653 return Imm >= 0 && Imm < 32;
655 let ParserMatchClass = Imm0_31AsmOperand;
658 /// imm0_32 predicate - True if the 32-bit immediate is in the range [0,32].
659 def Imm0_32AsmOperand: ImmAsmOperand { let Name = "Imm0_32"; }
660 def imm0_32 : Operand<i32>, ImmLeaf<i32, [{
661 return Imm >= 0 && Imm < 32;
663 let ParserMatchClass = Imm0_32AsmOperand;
666 /// imm0_63 predicate - True if the 32-bit immediate is in the range [0,63].
667 def Imm0_63AsmOperand: ImmAsmOperand { let Name = "Imm0_63"; }
668 def imm0_63 : Operand<i32>, ImmLeaf<i32, [{
669 return Imm >= 0 && Imm < 64;
671 let ParserMatchClass = Imm0_63AsmOperand;
674 /// imm0_255 predicate - Immediate in the range [0,255].
675 def Imm0_255AsmOperand : ImmAsmOperand { let Name = "Imm0_255"; }
676 def imm0_255 : Operand<i32>, ImmLeaf<i32, [{ return Imm >= 0 && Imm < 256; }]> {
677 let ParserMatchClass = Imm0_255AsmOperand;
680 /// imm0_65535 - An immediate is in the range [0.65535].
681 def Imm0_65535AsmOperand: ImmAsmOperand { let Name = "Imm0_65535"; }
682 def imm0_65535 : Operand<i32>, ImmLeaf<i32, [{
683 return Imm >= 0 && Imm < 65536;
685 let ParserMatchClass = Imm0_65535AsmOperand;
688 // imm0_65535_neg - An immediate whose negative value is in the range [0.65535].
689 def imm0_65535_neg : Operand<i32>, ImmLeaf<i32, [{
690 return -Imm >= 0 && -Imm < 65536;
693 // imm0_65535_expr - For movt/movw - 16-bit immediate that can also reference
694 // a relocatable expression.
696 // FIXME: This really needs a Thumb version separate from the ARM version.
697 // While the range is the same, and can thus use the same match class,
698 // the encoding is different so it should have a different encoder method.
699 def Imm0_65535ExprAsmOperand: ImmAsmOperand { let Name = "Imm0_65535Expr"; }
700 def imm0_65535_expr : Operand<i32> {
701 let EncoderMethod = "getHiLo16ImmOpValue";
702 let ParserMatchClass = Imm0_65535ExprAsmOperand;
705 /// imm24b - True if the 32-bit immediate is encodable in 24 bits.
706 def Imm24bitAsmOperand: ImmAsmOperand { let Name = "Imm24bit"; }
707 def imm24b : Operand<i32>, ImmLeaf<i32, [{
708 return Imm >= 0 && Imm <= 0xffffff;
710 let ParserMatchClass = Imm24bitAsmOperand;
714 /// bf_inv_mask_imm predicate - An AND mask to clear an arbitrary width bitfield
716 def BitfieldAsmOperand : AsmOperandClass {
717 let Name = "Bitfield";
718 let ParserMethod = "parseBitfield";
721 def bf_inv_mask_imm : Operand<i32>,
723 return ARM::isBitFieldInvertedMask(N->getZExtValue());
725 let EncoderMethod = "getBitfieldInvertedMaskOpValue";
726 let PrintMethod = "printBitfieldInvMaskImmOperand";
727 let DecoderMethod = "DecodeBitfieldMaskOperand";
728 let ParserMatchClass = BitfieldAsmOperand;
731 def imm1_32_XFORM: SDNodeXForm<imm, [{
732 return CurDAG->getTargetConstant((int)N->getZExtValue() - 1, MVT::i32);
734 def Imm1_32AsmOperand: AsmOperandClass { let Name = "Imm1_32"; }
735 def imm1_32 : Operand<i32>, PatLeaf<(imm), [{
736 uint64_t Imm = N->getZExtValue();
737 return Imm > 0 && Imm <= 32;
740 let PrintMethod = "printImmPlusOneOperand";
741 let ParserMatchClass = Imm1_32AsmOperand;
744 def imm1_16_XFORM: SDNodeXForm<imm, [{
745 return CurDAG->getTargetConstant((int)N->getZExtValue() - 1, MVT::i32);
747 def Imm1_16AsmOperand: AsmOperandClass { let Name = "Imm1_16"; }
748 def imm1_16 : Operand<i32>, PatLeaf<(imm), [{ return Imm > 0 && Imm <= 16; }],
750 let PrintMethod = "printImmPlusOneOperand";
751 let ParserMatchClass = Imm1_16AsmOperand;
754 // Define ARM specific addressing modes.
755 // addrmode_imm12 := reg +/- imm12
757 def MemImm12OffsetAsmOperand : AsmOperandClass { let Name = "MemImm12Offset"; }
758 class AddrMode_Imm12 : Operand<i32>,
759 ComplexPattern<i32, 2, "SelectAddrModeImm12", []> {
760 // 12-bit immediate operand. Note that instructions using this encode
761 // #0 and #-0 differently. We flag #-0 as the magic value INT32_MIN. All other
762 // immediate values are as normal.
764 let EncoderMethod = "getAddrModeImm12OpValue";
765 let DecoderMethod = "DecodeAddrModeImm12Operand";
766 let ParserMatchClass = MemImm12OffsetAsmOperand;
767 let MIOperandInfo = (ops GPR:$base, i32imm:$offsimm);
770 def addrmode_imm12 : AddrMode_Imm12 {
771 let PrintMethod = "printAddrModeImm12Operand<false>";
774 def addrmode_imm12_pre : AddrMode_Imm12 {
775 let PrintMethod = "printAddrModeImm12Operand<true>";
778 // ldst_so_reg := reg +/- reg shop imm
780 def MemRegOffsetAsmOperand : AsmOperandClass { let Name = "MemRegOffset"; }
781 def ldst_so_reg : Operand<i32>,
782 ComplexPattern<i32, 3, "SelectLdStSOReg", []> {
783 let EncoderMethod = "getLdStSORegOpValue";
784 // FIXME: Simplify the printer
785 let PrintMethod = "printAddrMode2Operand";
786 let DecoderMethod = "DecodeSORegMemOperand";
787 let ParserMatchClass = MemRegOffsetAsmOperand;
788 let MIOperandInfo = (ops GPR:$base, GPRnopc:$offsreg, i32imm:$shift);
791 // postidx_imm8 := +/- [0,255]
794 // {8} 1 is imm8 is non-negative. 0 otherwise.
795 // {7-0} [0,255] imm8 value.
796 def PostIdxImm8AsmOperand : AsmOperandClass { let Name = "PostIdxImm8"; }
797 def postidx_imm8 : Operand<i32> {
798 let PrintMethod = "printPostIdxImm8Operand";
799 let ParserMatchClass = PostIdxImm8AsmOperand;
800 let MIOperandInfo = (ops i32imm);
803 // postidx_imm8s4 := +/- [0,1020]
806 // {8} 1 is imm8 is non-negative. 0 otherwise.
807 // {7-0} [0,255] imm8 value, scaled by 4.
808 def PostIdxImm8s4AsmOperand : AsmOperandClass { let Name = "PostIdxImm8s4"; }
809 def postidx_imm8s4 : Operand<i32> {
810 let PrintMethod = "printPostIdxImm8s4Operand";
811 let ParserMatchClass = PostIdxImm8s4AsmOperand;
812 let MIOperandInfo = (ops i32imm);
816 // postidx_reg := +/- reg
818 def PostIdxRegAsmOperand : AsmOperandClass {
819 let Name = "PostIdxReg";
820 let ParserMethod = "parsePostIdxReg";
822 def postidx_reg : Operand<i32> {
823 let EncoderMethod = "getPostIdxRegOpValue";
824 let DecoderMethod = "DecodePostIdxReg";
825 let PrintMethod = "printPostIdxRegOperand";
826 let ParserMatchClass = PostIdxRegAsmOperand;
827 let MIOperandInfo = (ops GPRnopc, i32imm);
831 // addrmode2 := reg +/- imm12
832 // := reg +/- reg shop imm
834 // FIXME: addrmode2 should be refactored the rest of the way to always
835 // use explicit imm vs. reg versions above (addrmode_imm12 and ldst_so_reg).
836 def AddrMode2AsmOperand : AsmOperandClass { let Name = "AddrMode2"; }
837 def addrmode2 : Operand<i32>,
838 ComplexPattern<i32, 3, "SelectAddrMode2", []> {
839 let EncoderMethod = "getAddrMode2OpValue";
840 let PrintMethod = "printAddrMode2Operand";
841 let ParserMatchClass = AddrMode2AsmOperand;
842 let MIOperandInfo = (ops GPR:$base, GPR:$offsreg, i32imm:$offsimm);
845 def PostIdxRegShiftedAsmOperand : AsmOperandClass {
846 let Name = "PostIdxRegShifted";
847 let ParserMethod = "parsePostIdxReg";
849 def am2offset_reg : Operand<i32>,
850 ComplexPattern<i32, 2, "SelectAddrMode2OffsetReg",
851 [], [SDNPWantRoot]> {
852 let EncoderMethod = "getAddrMode2OffsetOpValue";
853 let PrintMethod = "printAddrMode2OffsetOperand";
854 // When using this for assembly, it's always as a post-index offset.
855 let ParserMatchClass = PostIdxRegShiftedAsmOperand;
856 let MIOperandInfo = (ops GPRnopc, i32imm);
859 // FIXME: am2offset_imm should only need the immediate, not the GPR. Having
860 // the GPR is purely vestigal at this point.
861 def AM2OffsetImmAsmOperand : AsmOperandClass { let Name = "AM2OffsetImm"; }
862 def am2offset_imm : Operand<i32>,
863 ComplexPattern<i32, 2, "SelectAddrMode2OffsetImm",
864 [], [SDNPWantRoot]> {
865 let EncoderMethod = "getAddrMode2OffsetOpValue";
866 let PrintMethod = "printAddrMode2OffsetOperand";
867 let ParserMatchClass = AM2OffsetImmAsmOperand;
868 let MIOperandInfo = (ops GPRnopc, i32imm);
872 // addrmode3 := reg +/- reg
873 // addrmode3 := reg +/- imm8
875 // FIXME: split into imm vs. reg versions.
876 def AddrMode3AsmOperand : AsmOperandClass { let Name = "AddrMode3"; }
877 class AddrMode3 : Operand<i32>,
878 ComplexPattern<i32, 3, "SelectAddrMode3", []> {
879 let EncoderMethod = "getAddrMode3OpValue";
880 let ParserMatchClass = AddrMode3AsmOperand;
881 let MIOperandInfo = (ops GPR:$base, GPR:$offsreg, i32imm:$offsimm);
884 def addrmode3 : AddrMode3
886 let PrintMethod = "printAddrMode3Operand<false>";
889 def addrmode3_pre : AddrMode3
891 let PrintMethod = "printAddrMode3Operand<true>";
894 // FIXME: split into imm vs. reg versions.
895 // FIXME: parser method to handle +/- register.
896 def AM3OffsetAsmOperand : AsmOperandClass {
897 let Name = "AM3Offset";
898 let ParserMethod = "parseAM3Offset";
900 def am3offset : Operand<i32>,
901 ComplexPattern<i32, 2, "SelectAddrMode3Offset",
902 [], [SDNPWantRoot]> {
903 let EncoderMethod = "getAddrMode3OffsetOpValue";
904 let PrintMethod = "printAddrMode3OffsetOperand";
905 let ParserMatchClass = AM3OffsetAsmOperand;
906 let MIOperandInfo = (ops GPR, i32imm);
909 // ldstm_mode := {ia, ib, da, db}
911 def ldstm_mode : OptionalDefOperand<OtherVT, (ops i32), (ops (i32 1))> {
912 let EncoderMethod = "getLdStmModeOpValue";
913 let PrintMethod = "printLdStmModeOperand";
916 // addrmode5 := reg +/- imm8*4
918 def AddrMode5AsmOperand : AsmOperandClass { let Name = "AddrMode5"; }
919 class AddrMode5 : Operand<i32>,
920 ComplexPattern<i32, 2, "SelectAddrMode5", []> {
921 let EncoderMethod = "getAddrMode5OpValue";
922 let DecoderMethod = "DecodeAddrMode5Operand";
923 let ParserMatchClass = AddrMode5AsmOperand;
924 let MIOperandInfo = (ops GPR:$base, i32imm);
927 def addrmode5 : AddrMode5 {
928 let PrintMethod = "printAddrMode5Operand<false>";
931 def addrmode5_pre : AddrMode5 {
932 let PrintMethod = "printAddrMode5Operand<true>";
935 // addrmode6 := reg with optional alignment
937 def AddrMode6AsmOperand : AsmOperandClass { let Name = "AlignedMemory"; }
938 def addrmode6 : Operand<i32>,
939 ComplexPattern<i32, 2, "SelectAddrMode6", [], [SDNPWantParent]>{
940 let PrintMethod = "printAddrMode6Operand";
941 let MIOperandInfo = (ops GPR:$addr, i32imm:$align);
942 let EncoderMethod = "getAddrMode6AddressOpValue";
943 let DecoderMethod = "DecodeAddrMode6Operand";
944 let ParserMatchClass = AddrMode6AsmOperand;
947 def am6offset : Operand<i32>,
948 ComplexPattern<i32, 1, "SelectAddrMode6Offset",
949 [], [SDNPWantRoot]> {
950 let PrintMethod = "printAddrMode6OffsetOperand";
951 let MIOperandInfo = (ops GPR);
952 let EncoderMethod = "getAddrMode6OffsetOpValue";
953 let DecoderMethod = "DecodeGPRRegisterClass";
956 // Special version of addrmode6 to handle alignment encoding for VST1/VLD1
957 // (single element from one lane) for size 32.
958 def addrmode6oneL32 : Operand<i32>,
959 ComplexPattern<i32, 2, "SelectAddrMode6", [], [SDNPWantParent]>{
960 let PrintMethod = "printAddrMode6Operand";
961 let MIOperandInfo = (ops GPR:$addr, i32imm);
962 let EncoderMethod = "getAddrMode6OneLane32AddressOpValue";
965 // Special version of addrmode6 to handle alignment encoding for VLD-dup
966 // instructions, specifically VLD4-dup.
967 def addrmode6dup : Operand<i32>,
968 ComplexPattern<i32, 2, "SelectAddrMode6", [], [SDNPWantParent]>{
969 let PrintMethod = "printAddrMode6Operand";
970 let MIOperandInfo = (ops GPR:$addr, i32imm);
971 let EncoderMethod = "getAddrMode6DupAddressOpValue";
972 // FIXME: This is close, but not quite right. The alignment specifier is
974 let ParserMatchClass = AddrMode6AsmOperand;
977 // addrmodepc := pc + reg
979 def addrmodepc : Operand<i32>,
980 ComplexPattern<i32, 2, "SelectAddrModePC", []> {
981 let PrintMethod = "printAddrModePCOperand";
982 let MIOperandInfo = (ops GPR, i32imm);
985 // addr_offset_none := reg
987 def MemNoOffsetAsmOperand : AsmOperandClass { let Name = "MemNoOffset"; }
988 def addr_offset_none : Operand<i32>,
989 ComplexPattern<i32, 1, "SelectAddrOffsetNone", []> {
990 let PrintMethod = "printAddrMode7Operand";
991 let DecoderMethod = "DecodeAddrMode7Operand";
992 let ParserMatchClass = MemNoOffsetAsmOperand;
993 let MIOperandInfo = (ops GPR:$base);
996 def nohash_imm : Operand<i32> {
997 let PrintMethod = "printNoHashImmediate";
1000 def CoprocNumAsmOperand : AsmOperandClass {
1001 let Name = "CoprocNum";
1002 let ParserMethod = "parseCoprocNumOperand";
1004 def p_imm : Operand<i32> {
1005 let PrintMethod = "printPImmediate";
1006 let ParserMatchClass = CoprocNumAsmOperand;
1007 let DecoderMethod = "DecodeCoprocessor";
1010 def CoprocRegAsmOperand : AsmOperandClass {
1011 let Name = "CoprocReg";
1012 let ParserMethod = "parseCoprocRegOperand";
1014 def c_imm : Operand<i32> {
1015 let PrintMethod = "printCImmediate";
1016 let ParserMatchClass = CoprocRegAsmOperand;
1018 def CoprocOptionAsmOperand : AsmOperandClass {
1019 let Name = "CoprocOption";
1020 let ParserMethod = "parseCoprocOptionOperand";
1022 def coproc_option_imm : Operand<i32> {
1023 let PrintMethod = "printCoprocOptionImm";
1024 let ParserMatchClass = CoprocOptionAsmOperand;
1027 //===----------------------------------------------------------------------===//
1029 include "ARMInstrFormats.td"
1031 //===----------------------------------------------------------------------===//
1032 // Multiclass helpers...
1035 /// AsI1_bin_irs - Defines a set of (op r, {so_imm|r|so_reg}) patterns for a
1036 /// binop that produces a value.
1037 let TwoOperandAliasConstraint = "$Rn = $Rd" in
1038 multiclass AsI1_bin_irs<bits<4> opcod, string opc,
1039 InstrItinClass iii, InstrItinClass iir, InstrItinClass iis,
1040 PatFrag opnode, bit Commutable = 0> {
1041 // The register-immediate version is re-materializable. This is useful
1042 // in particular for taking the address of a local.
1043 let isReMaterializable = 1 in {
1044 def ri : AsI1<opcod, (outs GPR:$Rd), (ins GPR:$Rn, so_imm:$imm), DPFrm,
1045 iii, opc, "\t$Rd, $Rn, $imm",
1046 [(set GPR:$Rd, (opnode GPR:$Rn, so_imm:$imm))]>,
1047 Sched<[WriteALU, ReadALU]> {
1052 let Inst{19-16} = Rn;
1053 let Inst{15-12} = Rd;
1054 let Inst{11-0} = imm;
1057 def rr : AsI1<opcod, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm), DPFrm,
1058 iir, opc, "\t$Rd, $Rn, $Rm",
1059 [(set GPR:$Rd, (opnode GPR:$Rn, GPR:$Rm))]>,
1060 Sched<[WriteALU, ReadALU, ReadALU]> {
1065 let isCommutable = Commutable;
1066 let Inst{19-16} = Rn;
1067 let Inst{15-12} = Rd;
1068 let Inst{11-4} = 0b00000000;
1072 def rsi : AsI1<opcod, (outs GPR:$Rd),
1073 (ins GPR:$Rn, so_reg_imm:$shift), DPSoRegImmFrm,
1074 iis, opc, "\t$Rd, $Rn, $shift",
1075 [(set GPR:$Rd, (opnode GPR:$Rn, so_reg_imm:$shift))]>,
1076 Sched<[WriteALUsi, ReadALU]> {
1081 let Inst{19-16} = Rn;
1082 let Inst{15-12} = Rd;
1083 let Inst{11-5} = shift{11-5};
1085 let Inst{3-0} = shift{3-0};
1088 def rsr : AsI1<opcod, (outs GPR:$Rd),
1089 (ins GPR:$Rn, so_reg_reg:$shift), DPSoRegRegFrm,
1090 iis, opc, "\t$Rd, $Rn, $shift",
1091 [(set GPR:$Rd, (opnode GPR:$Rn, so_reg_reg:$shift))]>,
1092 Sched<[WriteALUsr, ReadALUsr]> {
1097 let Inst{19-16} = Rn;
1098 let Inst{15-12} = Rd;
1099 let Inst{11-8} = shift{11-8};
1101 let Inst{6-5} = shift{6-5};
1103 let Inst{3-0} = shift{3-0};
1107 /// AsI1_rbin_irs - Same as AsI1_bin_irs except the order of operands are
1108 /// reversed. The 'rr' form is only defined for the disassembler; for codegen
1109 /// it is equivalent to the AsI1_bin_irs counterpart.
1110 let TwoOperandAliasConstraint = "$Rn = $Rd" in
1111 multiclass AsI1_rbin_irs<bits<4> opcod, string opc,
1112 InstrItinClass iii, InstrItinClass iir, InstrItinClass iis,
1113 PatFrag opnode, bit Commutable = 0> {
1114 // The register-immediate version is re-materializable. This is useful
1115 // in particular for taking the address of a local.
1116 let isReMaterializable = 1 in {
1117 def ri : AsI1<opcod, (outs GPR:$Rd), (ins GPR:$Rn, so_imm:$imm), DPFrm,
1118 iii, opc, "\t$Rd, $Rn, $imm",
1119 [(set GPR:$Rd, (opnode so_imm:$imm, GPR:$Rn))]>,
1120 Sched<[WriteALU, ReadALU]> {
1125 let Inst{19-16} = Rn;
1126 let Inst{15-12} = Rd;
1127 let Inst{11-0} = imm;
1130 def rr : AsI1<opcod, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm), DPFrm,
1131 iir, opc, "\t$Rd, $Rn, $Rm",
1132 [/* pattern left blank */]>,
1133 Sched<[WriteALU, ReadALU, ReadALU]> {
1137 let Inst{11-4} = 0b00000000;
1140 let Inst{15-12} = Rd;
1141 let Inst{19-16} = Rn;
1144 def rsi : AsI1<opcod, (outs GPR:$Rd),
1145 (ins GPR:$Rn, so_reg_imm:$shift), DPSoRegImmFrm,
1146 iis, opc, "\t$Rd, $Rn, $shift",
1147 [(set GPR:$Rd, (opnode so_reg_imm:$shift, GPR:$Rn))]>,
1148 Sched<[WriteALUsi, ReadALU]> {
1153 let Inst{19-16} = Rn;
1154 let Inst{15-12} = Rd;
1155 let Inst{11-5} = shift{11-5};
1157 let Inst{3-0} = shift{3-0};
1160 def rsr : AsI1<opcod, (outs GPR:$Rd),
1161 (ins GPR:$Rn, so_reg_reg:$shift), DPSoRegRegFrm,
1162 iis, opc, "\t$Rd, $Rn, $shift",
1163 [(set GPR:$Rd, (opnode so_reg_reg:$shift, GPR:$Rn))]>,
1164 Sched<[WriteALUsr, ReadALUsr]> {
1169 let Inst{19-16} = Rn;
1170 let Inst{15-12} = Rd;
1171 let Inst{11-8} = shift{11-8};
1173 let Inst{6-5} = shift{6-5};
1175 let Inst{3-0} = shift{3-0};
1179 /// AsI1_bin_s_irs - Same as AsI1_bin_irs except it sets the 's' bit by default.
1181 /// These opcodes will be converted to the real non-S opcodes by
1182 /// AdjustInstrPostInstrSelection after giving them an optional CPSR operand.
1183 let hasPostISelHook = 1, Defs = [CPSR] in {
1184 multiclass AsI1_bin_s_irs<InstrItinClass iii, InstrItinClass iir,
1185 InstrItinClass iis, PatFrag opnode,
1186 bit Commutable = 0> {
1187 def ri : ARMPseudoInst<(outs GPR:$Rd), (ins GPR:$Rn, so_imm:$imm, pred:$p),
1189 [(set GPR:$Rd, CPSR, (opnode GPR:$Rn, so_imm:$imm))]>,
1190 Sched<[WriteALU, ReadALU]>;
1192 def rr : ARMPseudoInst<(outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm, pred:$p),
1194 [(set GPR:$Rd, CPSR, (opnode GPR:$Rn, GPR:$Rm))]>,
1195 Sched<[WriteALU, ReadALU, ReadALU]> {
1196 let isCommutable = Commutable;
1198 def rsi : ARMPseudoInst<(outs GPR:$Rd),
1199 (ins GPR:$Rn, so_reg_imm:$shift, pred:$p),
1201 [(set GPR:$Rd, CPSR, (opnode GPR:$Rn,
1202 so_reg_imm:$shift))]>,
1203 Sched<[WriteALUsi, ReadALU]>;
1205 def rsr : ARMPseudoInst<(outs GPR:$Rd),
1206 (ins GPR:$Rn, so_reg_reg:$shift, pred:$p),
1208 [(set GPR:$Rd, CPSR, (opnode GPR:$Rn,
1209 so_reg_reg:$shift))]>,
1210 Sched<[WriteALUSsr, ReadALUsr]>;
1214 /// AsI1_rbin_s_is - Same as AsI1_bin_s_irs, except selection DAG
1215 /// operands are reversed.
1216 let hasPostISelHook = 1, Defs = [CPSR] in {
1217 multiclass AsI1_rbin_s_is<InstrItinClass iii, InstrItinClass iir,
1218 InstrItinClass iis, PatFrag opnode,
1219 bit Commutable = 0> {
1220 def ri : ARMPseudoInst<(outs GPR:$Rd), (ins GPR:$Rn, so_imm:$imm, pred:$p),
1222 [(set GPR:$Rd, CPSR, (opnode so_imm:$imm, GPR:$Rn))]>,
1223 Sched<[WriteALU, ReadALU]>;
1225 def rsi : ARMPseudoInst<(outs GPR:$Rd),
1226 (ins GPR:$Rn, so_reg_imm:$shift, pred:$p),
1228 [(set GPR:$Rd, CPSR, (opnode so_reg_imm:$shift,
1230 Sched<[WriteALUsi, ReadALU]>;
1232 def rsr : ARMPseudoInst<(outs GPR:$Rd),
1233 (ins GPR:$Rn, so_reg_reg:$shift, pred:$p),
1235 [(set GPR:$Rd, CPSR, (opnode so_reg_reg:$shift,
1237 Sched<[WriteALUSsr, ReadALUsr]>;
1241 /// AI1_cmp_irs - Defines a set of (op r, {so_imm|r|so_reg}) cmp / test
1242 /// patterns. Similar to AsI1_bin_irs except the instruction does not produce
1243 /// a explicit result, only implicitly set CPSR.
1244 let isCompare = 1, Defs = [CPSR] in {
1245 multiclass AI1_cmp_irs<bits<4> opcod, string opc,
1246 InstrItinClass iii, InstrItinClass iir, InstrItinClass iis,
1247 PatFrag opnode, bit Commutable = 0> {
1248 def ri : AI1<opcod, (outs), (ins GPR:$Rn, so_imm:$imm), DPFrm, iii,
1250 [(opnode GPR:$Rn, so_imm:$imm)]>,
1251 Sched<[WriteCMP, ReadALU]> {
1256 let Inst{19-16} = Rn;
1257 let Inst{15-12} = 0b0000;
1258 let Inst{11-0} = imm;
1260 let Unpredictable{15-12} = 0b1111;
1262 def rr : AI1<opcod, (outs), (ins GPR:$Rn, GPR:$Rm), DPFrm, iir,
1264 [(opnode GPR:$Rn, GPR:$Rm)]>,
1265 Sched<[WriteCMP, ReadALU, ReadALU]> {
1268 let isCommutable = Commutable;
1271 let Inst{19-16} = Rn;
1272 let Inst{15-12} = 0b0000;
1273 let Inst{11-4} = 0b00000000;
1276 let Unpredictable{15-12} = 0b1111;
1278 def rsi : AI1<opcod, (outs),
1279 (ins GPR:$Rn, so_reg_imm:$shift), DPSoRegImmFrm, iis,
1280 opc, "\t$Rn, $shift",
1281 [(opnode GPR:$Rn, so_reg_imm:$shift)]>,
1282 Sched<[WriteCMPsi, ReadALU]> {
1287 let Inst{19-16} = Rn;
1288 let Inst{15-12} = 0b0000;
1289 let Inst{11-5} = shift{11-5};
1291 let Inst{3-0} = shift{3-0};
1293 let Unpredictable{15-12} = 0b1111;
1295 def rsr : AI1<opcod, (outs),
1296 (ins GPRnopc:$Rn, so_reg_reg:$shift), DPSoRegRegFrm, iis,
1297 opc, "\t$Rn, $shift",
1298 [(opnode GPRnopc:$Rn, so_reg_reg:$shift)]>,
1299 Sched<[WriteCMPsr, ReadALU]> {
1304 let Inst{19-16} = Rn;
1305 let Inst{15-12} = 0b0000;
1306 let Inst{11-8} = shift{11-8};
1308 let Inst{6-5} = shift{6-5};
1310 let Inst{3-0} = shift{3-0};
1312 let Unpredictable{15-12} = 0b1111;
1318 /// AI_ext_rrot - A unary operation with two forms: one whose operand is a
1319 /// register and one whose operand is a register rotated by 8/16/24.
1320 /// FIXME: Remove the 'r' variant. Its rot_imm is zero.
1321 class AI_ext_rrot<bits<8> opcod, string opc, PatFrag opnode>
1322 : AExtI<opcod, (outs GPRnopc:$Rd), (ins GPRnopc:$Rm, rot_imm:$rot),
1323 IIC_iEXTr, opc, "\t$Rd, $Rm$rot",
1324 [(set GPRnopc:$Rd, (opnode (rotr GPRnopc:$Rm, rot_imm:$rot)))]>,
1325 Requires<[IsARM, HasV6]>, Sched<[WriteALUsi]> {
1329 let Inst{19-16} = 0b1111;
1330 let Inst{15-12} = Rd;
1331 let Inst{11-10} = rot;
1335 class AI_ext_rrot_np<bits<8> opcod, string opc>
1336 : AExtI<opcod, (outs GPRnopc:$Rd), (ins GPRnopc:$Rm, rot_imm:$rot),
1337 IIC_iEXTr, opc, "\t$Rd, $Rm$rot", []>,
1338 Requires<[IsARM, HasV6]>, Sched<[WriteALUsi]> {
1340 let Inst{19-16} = 0b1111;
1341 let Inst{11-10} = rot;
1344 /// AI_exta_rrot - A binary operation with two forms: one whose operand is a
1345 /// register and one whose operand is a register rotated by 8/16/24.
1346 class AI_exta_rrot<bits<8> opcod, string opc, PatFrag opnode>
1347 : AExtI<opcod, (outs GPRnopc:$Rd), (ins GPR:$Rn, GPRnopc:$Rm, rot_imm:$rot),
1348 IIC_iEXTAr, opc, "\t$Rd, $Rn, $Rm$rot",
1349 [(set GPRnopc:$Rd, (opnode GPR:$Rn,
1350 (rotr GPRnopc:$Rm, rot_imm:$rot)))]>,
1351 Requires<[IsARM, HasV6]>, Sched<[WriteALUsr]> {
1356 let Inst{19-16} = Rn;
1357 let Inst{15-12} = Rd;
1358 let Inst{11-10} = rot;
1359 let Inst{9-4} = 0b000111;
1363 class AI_exta_rrot_np<bits<8> opcod, string opc>
1364 : AExtI<opcod, (outs GPRnopc:$Rd), (ins GPR:$Rn, GPRnopc:$Rm, rot_imm:$rot),
1365 IIC_iEXTAr, opc, "\t$Rd, $Rn, $Rm$rot", []>,
1366 Requires<[IsARM, HasV6]>, Sched<[WriteALUsr]> {
1369 let Inst{19-16} = Rn;
1370 let Inst{11-10} = rot;
1373 /// AI1_adde_sube_irs - Define instructions and patterns for adde and sube.
1374 let TwoOperandAliasConstraint = "$Rn = $Rd" in
1375 multiclass AI1_adde_sube_irs<bits<4> opcod, string opc, PatFrag opnode,
1376 bit Commutable = 0> {
1377 let hasPostISelHook = 1, Defs = [CPSR], Uses = [CPSR] in {
1378 def ri : AsI1<opcod, (outs GPR:$Rd), (ins GPR:$Rn, so_imm:$imm),
1379 DPFrm, IIC_iALUi, opc, "\t$Rd, $Rn, $imm",
1380 [(set GPR:$Rd, CPSR, (opnode GPR:$Rn, so_imm:$imm, CPSR))]>,
1382 Sched<[WriteALU, ReadALU]> {
1387 let Inst{15-12} = Rd;
1388 let Inst{19-16} = Rn;
1389 let Inst{11-0} = imm;
1391 def rr : AsI1<opcod, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm),
1392 DPFrm, IIC_iALUr, opc, "\t$Rd, $Rn, $Rm",
1393 [(set GPR:$Rd, CPSR, (opnode GPR:$Rn, GPR:$Rm, CPSR))]>,
1395 Sched<[WriteALU, ReadALU, ReadALU]> {
1399 let Inst{11-4} = 0b00000000;
1401 let isCommutable = Commutable;
1403 let Inst{15-12} = Rd;
1404 let Inst{19-16} = Rn;
1406 def rsi : AsI1<opcod, (outs GPR:$Rd),
1407 (ins GPR:$Rn, so_reg_imm:$shift),
1408 DPSoRegImmFrm, IIC_iALUsr, opc, "\t$Rd, $Rn, $shift",
1409 [(set GPR:$Rd, CPSR, (opnode GPR:$Rn, so_reg_imm:$shift, CPSR))]>,
1411 Sched<[WriteALUsi, ReadALU]> {
1416 let Inst{19-16} = Rn;
1417 let Inst{15-12} = Rd;
1418 let Inst{11-5} = shift{11-5};
1420 let Inst{3-0} = shift{3-0};
1422 def rsr : AsI1<opcod, (outs GPRnopc:$Rd),
1423 (ins GPRnopc:$Rn, so_reg_reg:$shift),
1424 DPSoRegRegFrm, IIC_iALUsr, opc, "\t$Rd, $Rn, $shift",
1425 [(set GPRnopc:$Rd, CPSR,
1426 (opnode GPRnopc:$Rn, so_reg_reg:$shift, CPSR))]>,
1428 Sched<[WriteALUsr, ReadALUsr]> {
1433 let Inst{19-16} = Rn;
1434 let Inst{15-12} = Rd;
1435 let Inst{11-8} = shift{11-8};
1437 let Inst{6-5} = shift{6-5};
1439 let Inst{3-0} = shift{3-0};
1444 /// AI1_rsc_irs - Define instructions and patterns for rsc
1445 let TwoOperandAliasConstraint = "$Rn = $Rd" in
1446 multiclass AI1_rsc_irs<bits<4> opcod, string opc, PatFrag opnode> {
1447 let hasPostISelHook = 1, Defs = [CPSR], Uses = [CPSR] in {
1448 def ri : AsI1<opcod, (outs GPR:$Rd), (ins GPR:$Rn, so_imm:$imm),
1449 DPFrm, IIC_iALUi, opc, "\t$Rd, $Rn, $imm",
1450 [(set GPR:$Rd, CPSR, (opnode so_imm:$imm, GPR:$Rn, CPSR))]>,
1452 Sched<[WriteALU, ReadALU]> {
1457 let Inst{15-12} = Rd;
1458 let Inst{19-16} = Rn;
1459 let Inst{11-0} = imm;
1461 def rr : AsI1<opcod, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm),
1462 DPFrm, IIC_iALUr, opc, "\t$Rd, $Rn, $Rm",
1463 [/* pattern left blank */]>,
1464 Sched<[WriteALU, ReadALU, ReadALU]> {
1468 let Inst{11-4} = 0b00000000;
1471 let Inst{15-12} = Rd;
1472 let Inst{19-16} = Rn;
1474 def rsi : AsI1<opcod, (outs GPR:$Rd), (ins GPR:$Rn, so_reg_imm:$shift),
1475 DPSoRegImmFrm, IIC_iALUsr, opc, "\t$Rd, $Rn, $shift",
1476 [(set GPR:$Rd, CPSR, (opnode so_reg_imm:$shift, GPR:$Rn, CPSR))]>,
1478 Sched<[WriteALUsi, ReadALU]> {
1483 let Inst{19-16} = Rn;
1484 let Inst{15-12} = Rd;
1485 let Inst{11-5} = shift{11-5};
1487 let Inst{3-0} = shift{3-0};
1489 def rsr : AsI1<opcod, (outs GPR:$Rd), (ins GPR:$Rn, so_reg_reg:$shift),
1490 DPSoRegRegFrm, IIC_iALUsr, opc, "\t$Rd, $Rn, $shift",
1491 [(set GPR:$Rd, CPSR, (opnode so_reg_reg:$shift, GPR:$Rn, CPSR))]>,
1493 Sched<[WriteALUsr, ReadALUsr]> {
1498 let Inst{19-16} = Rn;
1499 let Inst{15-12} = Rd;
1500 let Inst{11-8} = shift{11-8};
1502 let Inst{6-5} = shift{6-5};
1504 let Inst{3-0} = shift{3-0};
1509 let canFoldAsLoad = 1, isReMaterializable = 1 in {
1510 multiclass AI_ldr1<bit isByte, string opc, InstrItinClass iii,
1511 InstrItinClass iir, PatFrag opnode> {
1512 // Note: We use the complex addrmode_imm12 rather than just an input
1513 // GPR and a constrained immediate so that we can use this to match
1514 // frame index references and avoid matching constant pool references.
1515 def i12: AI2ldst<0b010, 1, isByte, (outs GPR:$Rt), (ins addrmode_imm12:$addr),
1516 AddrMode_i12, LdFrm, iii, opc, "\t$Rt, $addr",
1517 [(set GPR:$Rt, (opnode addrmode_imm12:$addr))]> {
1520 let Inst{23} = addr{12}; // U (add = ('U' == 1))
1521 let Inst{19-16} = addr{16-13}; // Rn
1522 let Inst{15-12} = Rt;
1523 let Inst{11-0} = addr{11-0}; // imm12
1525 def rs : AI2ldst<0b011, 1, isByte, (outs GPR:$Rt), (ins ldst_so_reg:$shift),
1526 AddrModeNone, LdFrm, iir, opc, "\t$Rt, $shift",
1527 [(set GPR:$Rt, (opnode ldst_so_reg:$shift))]> {
1530 let shift{4} = 0; // Inst{4} = 0
1531 let Inst{23} = shift{12}; // U (add = ('U' == 1))
1532 let Inst{19-16} = shift{16-13}; // Rn
1533 let Inst{15-12} = Rt;
1534 let Inst{11-0} = shift{11-0};
1539 let canFoldAsLoad = 1, isReMaterializable = 1 in {
1540 multiclass AI_ldr1nopc<bit isByte, string opc, InstrItinClass iii,
1541 InstrItinClass iir, PatFrag opnode> {
1542 // Note: We use the complex addrmode_imm12 rather than just an input
1543 // GPR and a constrained immediate so that we can use this to match
1544 // frame index references and avoid matching constant pool references.
1545 def i12: AI2ldst<0b010, 1, isByte, (outs GPRnopc:$Rt),
1546 (ins addrmode_imm12:$addr),
1547 AddrMode_i12, LdFrm, iii, opc, "\t$Rt, $addr",
1548 [(set GPRnopc:$Rt, (opnode addrmode_imm12:$addr))]> {
1551 let Inst{23} = addr{12}; // U (add = ('U' == 1))
1552 let Inst{19-16} = addr{16-13}; // Rn
1553 let Inst{15-12} = Rt;
1554 let Inst{11-0} = addr{11-0}; // imm12
1556 def rs : AI2ldst<0b011, 1, isByte, (outs GPRnopc:$Rt),
1557 (ins ldst_so_reg:$shift),
1558 AddrModeNone, LdFrm, iir, opc, "\t$Rt, $shift",
1559 [(set GPRnopc:$Rt, (opnode ldst_so_reg:$shift))]> {
1562 let shift{4} = 0; // Inst{4} = 0
1563 let Inst{23} = shift{12}; // U (add = ('U' == 1))
1564 let Inst{19-16} = shift{16-13}; // Rn
1565 let Inst{15-12} = Rt;
1566 let Inst{11-0} = shift{11-0};
1572 multiclass AI_str1<bit isByte, string opc, InstrItinClass iii,
1573 InstrItinClass iir, PatFrag opnode> {
1574 // Note: We use the complex addrmode_imm12 rather than just an input
1575 // GPR and a constrained immediate so that we can use this to match
1576 // frame index references and avoid matching constant pool references.
1577 def i12 : AI2ldst<0b010, 0, isByte, (outs),
1578 (ins GPR:$Rt, addrmode_imm12:$addr),
1579 AddrMode_i12, StFrm, iii, opc, "\t$Rt, $addr",
1580 [(opnode GPR:$Rt, addrmode_imm12:$addr)]> {
1583 let Inst{23} = addr{12}; // U (add = ('U' == 1))
1584 let Inst{19-16} = addr{16-13}; // Rn
1585 let Inst{15-12} = Rt;
1586 let Inst{11-0} = addr{11-0}; // imm12
1588 def rs : AI2ldst<0b011, 0, isByte, (outs), (ins GPR:$Rt, ldst_so_reg:$shift),
1589 AddrModeNone, StFrm, iir, opc, "\t$Rt, $shift",
1590 [(opnode GPR:$Rt, ldst_so_reg:$shift)]> {
1593 let shift{4} = 0; // Inst{4} = 0
1594 let Inst{23} = shift{12}; // U (add = ('U' == 1))
1595 let Inst{19-16} = shift{16-13}; // Rn
1596 let Inst{15-12} = Rt;
1597 let Inst{11-0} = shift{11-0};
1601 multiclass AI_str1nopc<bit isByte, string opc, InstrItinClass iii,
1602 InstrItinClass iir, PatFrag opnode> {
1603 // Note: We use the complex addrmode_imm12 rather than just an input
1604 // GPR and a constrained immediate so that we can use this to match
1605 // frame index references and avoid matching constant pool references.
1606 def i12 : AI2ldst<0b010, 0, isByte, (outs),
1607 (ins GPRnopc:$Rt, addrmode_imm12:$addr),
1608 AddrMode_i12, StFrm, iii, opc, "\t$Rt, $addr",
1609 [(opnode GPRnopc:$Rt, addrmode_imm12:$addr)]> {
1612 let Inst{23} = addr{12}; // U (add = ('U' == 1))
1613 let Inst{19-16} = addr{16-13}; // Rn
1614 let Inst{15-12} = Rt;
1615 let Inst{11-0} = addr{11-0}; // imm12
1617 def rs : AI2ldst<0b011, 0, isByte, (outs),
1618 (ins GPRnopc:$Rt, ldst_so_reg:$shift),
1619 AddrModeNone, StFrm, iir, opc, "\t$Rt, $shift",
1620 [(opnode GPRnopc:$Rt, ldst_so_reg:$shift)]> {
1623 let shift{4} = 0; // Inst{4} = 0
1624 let Inst{23} = shift{12}; // U (add = ('U' == 1))
1625 let Inst{19-16} = shift{16-13}; // Rn
1626 let Inst{15-12} = Rt;
1627 let Inst{11-0} = shift{11-0};
1632 //===----------------------------------------------------------------------===//
1634 //===----------------------------------------------------------------------===//
1636 //===----------------------------------------------------------------------===//
1637 // Miscellaneous Instructions.
1640 /// CONSTPOOL_ENTRY - This instruction represents a floating constant pool in
1641 /// the function. The first operand is the ID# for this instruction, the second
1642 /// is the index into the MachineConstantPool that this is, the third is the
1643 /// size in bytes of this constant pool entry.
1644 let neverHasSideEffects = 1, isNotDuplicable = 1 in
1645 def CONSTPOOL_ENTRY :
1646 PseudoInst<(outs), (ins cpinst_operand:$instid, cpinst_operand:$cpidx,
1647 i32imm:$size), NoItinerary, []>;
1649 // FIXME: Marking these as hasSideEffects is necessary to prevent machine DCE
1650 // from removing one half of the matched pairs. That breaks PEI, which assumes
1651 // these will always be in pairs, and asserts if it finds otherwise. Better way?
1652 let Defs = [SP], Uses = [SP], hasSideEffects = 1 in {
1653 def ADJCALLSTACKUP :
1654 PseudoInst<(outs), (ins i32imm:$amt1, i32imm:$amt2, pred:$p), NoItinerary,
1655 [(ARMcallseq_end timm:$amt1, timm:$amt2)]>;
1657 def ADJCALLSTACKDOWN :
1658 PseudoInst<(outs), (ins i32imm:$amt, pred:$p), NoItinerary,
1659 [(ARMcallseq_start timm:$amt)]>;
1662 // Atomic pseudo-insts which will be lowered to ldrexd/strexd loops.
1663 // (These pseudos use a hand-written selection code).
1664 let usesCustomInserter = 1, Defs = [CPSR], mayLoad = 1, mayStore = 1 in {
1665 def ATOMOR6432 : PseudoInst<(outs GPR:$dst1, GPR:$dst2),
1666 (ins GPR:$addr, GPR:$src1, GPR:$src2),
1668 def ATOMXOR6432 : PseudoInst<(outs GPR:$dst1, GPR:$dst2),
1669 (ins GPR:$addr, GPR:$src1, GPR:$src2),
1671 def ATOMADD6432 : PseudoInst<(outs GPR:$dst1, GPR:$dst2),
1672 (ins GPR:$addr, GPR:$src1, GPR:$src2),
1674 def ATOMSUB6432 : PseudoInst<(outs GPR:$dst1, GPR:$dst2),
1675 (ins GPR:$addr, GPR:$src1, GPR:$src2),
1677 def ATOMNAND6432 : PseudoInst<(outs GPR:$dst1, GPR:$dst2),
1678 (ins GPR:$addr, GPR:$src1, GPR:$src2),
1680 def ATOMAND6432 : PseudoInst<(outs GPR:$dst1, GPR:$dst2),
1681 (ins GPR:$addr, GPR:$src1, GPR:$src2),
1683 def ATOMSWAP6432 : PseudoInst<(outs GPR:$dst1, GPR:$dst2),
1684 (ins GPR:$addr, GPR:$src1, GPR:$src2),
1686 def ATOMCMPXCHG6432 : PseudoInst<(outs GPR:$dst1, GPR:$dst2),
1687 (ins GPR:$addr, GPR:$cmp1, GPR:$cmp2,
1688 GPR:$set1, GPR:$set2),
1690 def ATOMMIN6432 : PseudoInst<(outs GPR:$dst1, GPR:$dst2),
1691 (ins GPR:$addr, GPR:$src1, GPR:$src2),
1693 def ATOMUMIN6432 : PseudoInst<(outs GPR:$dst1, GPR:$dst2),
1694 (ins GPR:$addr, GPR:$src1, GPR:$src2),
1696 def ATOMMAX6432 : PseudoInst<(outs GPR:$dst1, GPR:$dst2),
1697 (ins GPR:$addr, GPR:$src1, GPR:$src2),
1699 def ATOMUMAX6432 : PseudoInst<(outs GPR:$dst1, GPR:$dst2),
1700 (ins GPR:$addr, GPR:$src1, GPR:$src2),
1704 def HINT : AI<(outs), (ins imm0_4:$imm), MiscFrm, NoItinerary,
1705 "hint", "\t$imm", []>, Requires<[IsARM, HasV6]> {
1707 let Inst{27-3} = 0b0011001000001111000000000;
1708 let Inst{2-0} = imm;
1711 def : InstAlias<"nop$p", (HINT 0, pred:$p)>, Requires<[IsARM, HasV6T2]>;
1712 def : InstAlias<"yield$p", (HINT 1, pred:$p)>, Requires<[IsARM, HasV6T2]>;
1713 def : InstAlias<"wfe$p", (HINT 2, pred:$p)>, Requires<[IsARM, HasV6T2]>;
1714 def : InstAlias<"wfi$p", (HINT 3, pred:$p)>, Requires<[IsARM, HasV6T2]>;
1715 def : InstAlias<"sev$p", (HINT 4, pred:$p)>, Requires<[IsARM, HasV6T2]>;
1717 def SEL : AI<(outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm), DPFrm, NoItinerary, "sel",
1718 "\t$Rd, $Rn, $Rm", []>, Requires<[IsARM, HasV6]> {
1723 let Inst{15-12} = Rd;
1724 let Inst{19-16} = Rn;
1725 let Inst{27-20} = 0b01101000;
1726 let Inst{7-4} = 0b1011;
1727 let Inst{11-8} = 0b1111;
1728 let Unpredictable{11-8} = 0b1111;
1731 // The 16-bit operand $val can be used by a debugger to store more information
1732 // about the breakpoint.
1733 def BKPT : AI<(outs), (ins imm0_65535:$val), MiscFrm, NoItinerary,
1734 "bkpt", "\t$val", []>, Requires<[IsARM]> {
1736 let Inst{3-0} = val{3-0};
1737 let Inst{19-8} = val{15-4};
1738 let Inst{27-20} = 0b00010010;
1739 let Inst{7-4} = 0b0111;
1742 // Change Processor State
1743 // FIXME: We should use InstAlias to handle the optional operands.
1744 class CPS<dag iops, string asm_ops>
1745 : AXI<(outs), iops, MiscFrm, NoItinerary, !strconcat("cps", asm_ops),
1746 []>, Requires<[IsARM]> {
1752 let Inst{31-28} = 0b1111;
1753 let Inst{27-20} = 0b00010000;
1754 let Inst{19-18} = imod;
1755 let Inst{17} = M; // Enabled if mode is set;
1756 let Inst{16-9} = 0b00000000;
1757 let Inst{8-6} = iflags;
1759 let Inst{4-0} = mode;
1762 let DecoderMethod = "DecodeCPSInstruction" in {
1764 def CPS3p : CPS<(ins imod_op:$imod, iflags_op:$iflags, imm0_31:$mode),
1765 "$imod\t$iflags, $mode">;
1766 let mode = 0, M = 0 in
1767 def CPS2p : CPS<(ins imod_op:$imod, iflags_op:$iflags), "$imod\t$iflags">;
1769 let imod = 0, iflags = 0, M = 1 in
1770 def CPS1p : CPS<(ins imm0_31:$mode), "\t$mode">;
1773 // Preload signals the memory system of possible future data/instruction access.
1774 multiclass APreLoad<bits<1> read, bits<1> data, string opc> {
1776 def i12 : AXI<(outs), (ins addrmode_imm12:$addr), MiscFrm, IIC_Preload,
1777 !strconcat(opc, "\t$addr"),
1778 [(ARMPreload addrmode_imm12:$addr, (i32 read), (i32 data))]>,
1779 Sched<[WritePreLd]> {
1782 let Inst{31-26} = 0b111101;
1783 let Inst{25} = 0; // 0 for immediate form
1784 let Inst{24} = data;
1785 let Inst{23} = addr{12}; // U (add = ('U' == 1))
1786 let Inst{22} = read;
1787 let Inst{21-20} = 0b01;
1788 let Inst{19-16} = addr{16-13}; // Rn
1789 let Inst{15-12} = 0b1111;
1790 let Inst{11-0} = addr{11-0}; // imm12
1793 def rs : AXI<(outs), (ins ldst_so_reg:$shift), MiscFrm, IIC_Preload,
1794 !strconcat(opc, "\t$shift"),
1795 [(ARMPreload ldst_so_reg:$shift, (i32 read), (i32 data))]>,
1796 Sched<[WritePreLd]> {
1798 let Inst{31-26} = 0b111101;
1799 let Inst{25} = 1; // 1 for register form
1800 let Inst{24} = data;
1801 let Inst{23} = shift{12}; // U (add = ('U' == 1))
1802 let Inst{22} = read;
1803 let Inst{21-20} = 0b01;
1804 let Inst{19-16} = shift{16-13}; // Rn
1805 let Inst{15-12} = 0b1111;
1806 let Inst{11-0} = shift{11-0};
1811 defm PLD : APreLoad<1, 1, "pld">, Requires<[IsARM]>;
1812 defm PLDW : APreLoad<0, 1, "pldw">, Requires<[IsARM,HasV7,HasMP]>;
1813 defm PLI : APreLoad<1, 0, "pli">, Requires<[IsARM,HasV7]>;
1815 def SETEND : AXI<(outs), (ins setend_op:$end), MiscFrm, NoItinerary,
1816 "setend\t$end", []>, Requires<[IsARM]> {
1818 let Inst{31-10} = 0b1111000100000001000000;
1823 def DBG : AI<(outs), (ins imm0_15:$opt), MiscFrm, NoItinerary, "dbg", "\t$opt",
1824 []>, Requires<[IsARM, HasV7]> {
1826 let Inst{27-4} = 0b001100100000111100001111;
1827 let Inst{3-0} = opt;
1831 * A5.4 Permanently UNDEFINED instructions.
1833 * For most targets use UDF #65006, for which the OS will generate SIGTRAP.
1834 * Other UDF encodings generate SIGILL.
1836 * NaCl's OS instead chooses an ARM UDF encoding that's also a UDF in Thumb.
1838 * 1110 0111 1111 iiii iiii iiii 1111 iiii
1840 * 1101 1110 iiii iiii
1841 * It uses the following encoding:
1842 * 1110 0111 1111 1110 1101 1110 1111 0000
1843 * - In ARM: UDF #60896;
1844 * - In Thumb: UDF #254 followed by a branch-to-self.
1846 let isBarrier = 1, isTerminator = 1 in
1847 def TRAPNaCl : AXI<(outs), (ins), MiscFrm, NoItinerary,
1849 Requires<[IsARM,UseNaClTrap]> {
1850 let Inst = 0xe7fedef0;
1852 let isBarrier = 1, isTerminator = 1 in
1853 def TRAP : AXI<(outs), (ins), MiscFrm, NoItinerary,
1855 Requires<[IsARM,DontUseNaClTrap]> {
1856 let Inst = 0xe7ffdefe;
1859 // Address computation and loads and stores in PIC mode.
1860 let isNotDuplicable = 1 in {
1861 def PICADD : ARMPseudoInst<(outs GPR:$dst), (ins GPR:$a, pclabel:$cp, pred:$p),
1863 [(set GPR:$dst, (ARMpic_add GPR:$a, imm:$cp))]>,
1864 Sched<[WriteALU, ReadALU]>;
1866 let AddedComplexity = 10 in {
1867 def PICLDR : ARMPseudoInst<(outs GPR:$dst), (ins addrmodepc:$addr, pred:$p),
1869 [(set GPR:$dst, (load addrmodepc:$addr))]>;
1871 def PICLDRH : ARMPseudoInst<(outs GPR:$Rt), (ins addrmodepc:$addr, pred:$p),
1873 [(set GPR:$Rt, (zextloadi16 addrmodepc:$addr))]>;
1875 def PICLDRB : ARMPseudoInst<(outs GPR:$Rt), (ins addrmodepc:$addr, pred:$p),
1877 [(set GPR:$Rt, (zextloadi8 addrmodepc:$addr))]>;
1879 def PICLDRSH : ARMPseudoInst<(outs GPR:$Rt), (ins addrmodepc:$addr, pred:$p),
1881 [(set GPR:$Rt, (sextloadi16 addrmodepc:$addr))]>;
1883 def PICLDRSB : ARMPseudoInst<(outs GPR:$Rt), (ins addrmodepc:$addr, pred:$p),
1885 [(set GPR:$Rt, (sextloadi8 addrmodepc:$addr))]>;
1887 let AddedComplexity = 10 in {
1888 def PICSTR : ARMPseudoInst<(outs), (ins GPR:$src, addrmodepc:$addr, pred:$p),
1889 4, IIC_iStore_r, [(store GPR:$src, addrmodepc:$addr)]>;
1891 def PICSTRH : ARMPseudoInst<(outs), (ins GPR:$src, addrmodepc:$addr, pred:$p),
1892 4, IIC_iStore_bh_r, [(truncstorei16 GPR:$src,
1893 addrmodepc:$addr)]>;
1895 def PICSTRB : ARMPseudoInst<(outs), (ins GPR:$src, addrmodepc:$addr, pred:$p),
1896 4, IIC_iStore_bh_r, [(truncstorei8 GPR:$src, addrmodepc:$addr)]>;
1898 } // isNotDuplicable = 1
1901 // LEApcrel - Load a pc-relative address into a register without offending the
1903 let neverHasSideEffects = 1, isReMaterializable = 1 in
1904 // The 'adr' mnemonic encodes differently if the label is before or after
1905 // the instruction. The {24-21} opcode bits are set by the fixup, as we don't
1906 // know until then which form of the instruction will be used.
1907 def ADR : AI1<{0,?,?,0}, (outs GPR:$Rd), (ins adrlabel:$label),
1908 MiscFrm, IIC_iALUi, "adr", "\t$Rd, $label", []>,
1909 Sched<[WriteALU, ReadALU]> {
1912 let Inst{27-25} = 0b001;
1914 let Inst{23-22} = label{13-12};
1917 let Inst{19-16} = 0b1111;
1918 let Inst{15-12} = Rd;
1919 let Inst{11-0} = label{11-0};
1922 let hasSideEffects = 1 in {
1923 def LEApcrel : ARMPseudoInst<(outs GPR:$Rd), (ins i32imm:$label, pred:$p),
1924 4, IIC_iALUi, []>, Sched<[WriteALU, ReadALU]>;
1926 def LEApcrelJT : ARMPseudoInst<(outs GPR:$Rd),
1927 (ins i32imm:$label, nohash_imm:$id, pred:$p),
1928 4, IIC_iALUi, []>, Sched<[WriteALU, ReadALU]>;
1931 //===----------------------------------------------------------------------===//
1932 // Control Flow Instructions.
1935 let isReturn = 1, isTerminator = 1, isBarrier = 1 in {
1937 def BX_RET : AI<(outs), (ins), BrMiscFrm, IIC_Br,
1938 "bx", "\tlr", [(ARMretflag)]>,
1939 Requires<[IsARM, HasV4T]>, Sched<[WriteBr]> {
1940 let Inst{27-0} = 0b0001001011111111111100011110;
1944 def MOVPCLR : AI<(outs), (ins), BrMiscFrm, IIC_Br,
1945 "mov", "\tpc, lr", [(ARMretflag)]>,
1946 Requires<[IsARM, NoV4T]>, Sched<[WriteBr]> {
1947 let Inst{27-0} = 0b0001101000001111000000001110;
1951 // Indirect branches
1952 let isBranch = 1, isTerminator = 1, isBarrier = 1, isIndirectBranch = 1 in {
1954 def BX : AXI<(outs), (ins GPR:$dst), BrMiscFrm, IIC_Br, "bx\t$dst",
1955 [(brind GPR:$dst)]>,
1956 Requires<[IsARM, HasV4T]>, Sched<[WriteBr]> {
1958 let Inst{31-4} = 0b1110000100101111111111110001;
1959 let Inst{3-0} = dst;
1962 def BX_pred : AI<(outs), (ins GPR:$dst), BrMiscFrm, IIC_Br,
1963 "bx", "\t$dst", [/* pattern left blank */]>,
1964 Requires<[IsARM, HasV4T]>, Sched<[WriteBr]> {
1966 let Inst{27-4} = 0b000100101111111111110001;
1967 let Inst{3-0} = dst;
1971 // SP is marked as a use to prevent stack-pointer assignments that appear
1972 // immediately before calls from potentially appearing dead.
1974 // FIXME: Do we really need a non-predicated version? If so, it should
1975 // at least be a pseudo instruction expanding to the predicated version
1976 // at MC lowering time.
1977 Defs = [LR], Uses = [SP] in {
1978 def BL : ABXI<0b1011, (outs), (ins bl_target:$func),
1979 IIC_Br, "bl\t$func",
1980 [(ARMcall tglobaladdr:$func)]>,
1981 Requires<[IsARM]>, Sched<[WriteBrL]> {
1982 let Inst{31-28} = 0b1110;
1984 let Inst{23-0} = func;
1985 let DecoderMethod = "DecodeBranchImmInstruction";
1988 def BL_pred : ABI<0b1011, (outs), (ins bl_target:$func),
1989 IIC_Br, "bl", "\t$func",
1990 [(ARMcall_pred tglobaladdr:$func)]>,
1991 Requires<[IsARM]>, Sched<[WriteBrL]> {
1993 let Inst{23-0} = func;
1994 let DecoderMethod = "DecodeBranchImmInstruction";
1998 def BLX : AXI<(outs), (ins GPR:$func), BrMiscFrm,
1999 IIC_Br, "blx\t$func",
2000 [(ARMcall GPR:$func)]>,
2001 Requires<[IsARM, HasV5T]>, Sched<[WriteBrL]> {
2003 let Inst{31-4} = 0b1110000100101111111111110011;
2004 let Inst{3-0} = func;
2007 def BLX_pred : AI<(outs), (ins GPR:$func), BrMiscFrm,
2008 IIC_Br, "blx", "\t$func",
2009 [(ARMcall_pred GPR:$func)]>,
2010 Requires<[IsARM, HasV5T]>, Sched<[WriteBrL]> {
2012 let Inst{27-4} = 0b000100101111111111110011;
2013 let Inst{3-0} = func;
2017 // Note: Restrict $func to the tGPR regclass to prevent it being in LR.
2018 def BX_CALL : ARMPseudoInst<(outs), (ins tGPR:$func),
2019 8, IIC_Br, [(ARMcall_nolink tGPR:$func)]>,
2020 Requires<[IsARM, HasV4T]>, Sched<[WriteBr]>;
2023 def BMOVPCRX_CALL : ARMPseudoInst<(outs), (ins tGPR:$func),
2024 8, IIC_Br, [(ARMcall_nolink tGPR:$func)]>,
2025 Requires<[IsARM, NoV4T]>, Sched<[WriteBr]>;
2027 // mov lr, pc; b if callee is marked noreturn to avoid confusing the
2028 // return stack predictor.
2029 def BMOVPCB_CALL : ARMPseudoInst<(outs), (ins bl_target:$func),
2030 8, IIC_Br, [(ARMcall_nolink tglobaladdr:$func)]>,
2031 Requires<[IsARM]>, Sched<[WriteBr]>;
2034 let isBranch = 1, isTerminator = 1 in {
2035 // FIXME: should be able to write a pattern for ARMBrcond, but can't use
2036 // a two-value operand where a dag node expects two operands. :(
2037 def Bcc : ABI<0b1010, (outs), (ins br_target:$target),
2038 IIC_Br, "b", "\t$target",
2039 [/*(ARMbrcond bb:$target, imm:$cc, CCR:$ccr)*/]>,
2042 let Inst{23-0} = target;
2043 let DecoderMethod = "DecodeBranchImmInstruction";
2046 let isBarrier = 1 in {
2047 // B is "predicable" since it's just a Bcc with an 'always' condition.
2048 let isPredicable = 1 in
2049 // FIXME: We shouldn't need this pseudo at all. Just using Bcc directly
2050 // should be sufficient.
2051 // FIXME: Is B really a Barrier? That doesn't seem right.
2052 def B : ARMPseudoExpand<(outs), (ins br_target:$target), 4, IIC_Br,
2053 [(br bb:$target)], (Bcc br_target:$target, (ops 14, zero_reg))>,
2056 let isNotDuplicable = 1, isIndirectBranch = 1 in {
2057 def BR_JTr : ARMPseudoInst<(outs),
2058 (ins GPR:$target, i32imm:$jt, i32imm:$id),
2060 [(ARMbrjt GPR:$target, tjumptable:$jt, imm:$id)]>,
2062 // FIXME: This shouldn't use the generic "addrmode2," but rather be split
2063 // into i12 and rs suffixed versions.
2064 def BR_JTm : ARMPseudoInst<(outs),
2065 (ins addrmode2:$target, i32imm:$jt, i32imm:$id),
2067 [(ARMbrjt (i32 (load addrmode2:$target)), tjumptable:$jt,
2068 imm:$id)]>, Sched<[WriteBrTbl]>;
2069 def BR_JTadd : ARMPseudoInst<(outs),
2070 (ins GPR:$target, GPR:$idx, i32imm:$jt, i32imm:$id),
2072 [(ARMbrjt (add GPR:$target, GPR:$idx), tjumptable:$jt,
2073 imm:$id)]>, Sched<[WriteBrTbl]>;
2074 } // isNotDuplicable = 1, isIndirectBranch = 1
2080 def BLXi : AXI<(outs), (ins blx_target:$target), BrMiscFrm, NoItinerary,
2081 "blx\t$target", []>,
2082 Requires<[IsARM, HasV5T]>, Sched<[WriteBrL]> {
2083 let Inst{31-25} = 0b1111101;
2085 let Inst{23-0} = target{24-1};
2086 let Inst{24} = target{0};
2089 // Branch and Exchange Jazelle
2090 def BXJ : ABI<0b0001, (outs), (ins GPR:$func), NoItinerary, "bxj", "\t$func",
2091 [/* pattern left blank */]>, Sched<[WriteBr]> {
2093 let Inst{23-20} = 0b0010;
2094 let Inst{19-8} = 0xfff;
2095 let Inst{7-4} = 0b0010;
2096 let Inst{3-0} = func;
2101 let isCall = 1, isTerminator = 1, isReturn = 1, isBarrier = 1, Uses = [SP] in {
2102 def TCRETURNdi : PseudoInst<(outs), (ins i32imm:$dst), IIC_Br, []>,
2105 def TCRETURNri : PseudoInst<(outs), (ins tcGPR:$dst), IIC_Br, []>,
2108 def TAILJMPd : ARMPseudoExpand<(outs), (ins br_target:$dst),
2110 (Bcc br_target:$dst, (ops 14, zero_reg))>,
2111 Requires<[IsARM]>, Sched<[WriteBr]>;
2113 def TAILJMPr : ARMPseudoExpand<(outs), (ins tcGPR:$dst),
2115 (BX GPR:$dst)>, Sched<[WriteBr]>,
2119 // Secure Monitor Call is a system instruction.
2120 def SMC : ABI<0b0001, (outs), (ins imm0_15:$opt), NoItinerary, "smc", "\t$opt",
2121 []>, Requires<[IsARM, HasTrustZone]> {
2123 let Inst{23-4} = 0b01100000000000000111;
2124 let Inst{3-0} = opt;
2127 // Supervisor Call (Software Interrupt)
2128 let isCall = 1, Uses = [SP] in {
2129 def SVC : ABI<0b1111, (outs), (ins imm24b:$svc), IIC_Br, "svc", "\t$svc", []>,
2132 let Inst{23-0} = svc;
2136 // Store Return State
2137 class SRSI<bit wb, string asm>
2138 : XI<(outs), (ins imm0_31:$mode), AddrModeNone, 4, IndexModeNone, BrFrm,
2139 NoItinerary, asm, "", []> {
2141 let Inst{31-28} = 0b1111;
2142 let Inst{27-25} = 0b100;
2146 let Inst{19-16} = 0b1101; // SP
2147 let Inst{15-5} = 0b00000101000;
2148 let Inst{4-0} = mode;
2151 def SRSDA : SRSI<0, "srsda\tsp, $mode"> {
2152 let Inst{24-23} = 0;
2154 def SRSDA_UPD : SRSI<1, "srsda\tsp!, $mode"> {
2155 let Inst{24-23} = 0;
2157 def SRSDB : SRSI<0, "srsdb\tsp, $mode"> {
2158 let Inst{24-23} = 0b10;
2160 def SRSDB_UPD : SRSI<1, "srsdb\tsp!, $mode"> {
2161 let Inst{24-23} = 0b10;
2163 def SRSIA : SRSI<0, "srsia\tsp, $mode"> {
2164 let Inst{24-23} = 0b01;
2166 def SRSIA_UPD : SRSI<1, "srsia\tsp!, $mode"> {
2167 let Inst{24-23} = 0b01;
2169 def SRSIB : SRSI<0, "srsib\tsp, $mode"> {
2170 let Inst{24-23} = 0b11;
2172 def SRSIB_UPD : SRSI<1, "srsib\tsp!, $mode"> {
2173 let Inst{24-23} = 0b11;
2176 def : ARMInstAlias<"srsda $mode", (SRSDA imm0_31:$mode)>;
2177 def : ARMInstAlias<"srsda $mode!", (SRSDA_UPD imm0_31:$mode)>;
2179 def : ARMInstAlias<"srsdb $mode", (SRSDB imm0_31:$mode)>;
2180 def : ARMInstAlias<"srsdb $mode!", (SRSDB_UPD imm0_31:$mode)>;
2182 def : ARMInstAlias<"srsia $mode", (SRSIA imm0_31:$mode)>;
2183 def : ARMInstAlias<"srsia $mode!", (SRSIA_UPD imm0_31:$mode)>;
2185 def : ARMInstAlias<"srsib $mode", (SRSIB imm0_31:$mode)>;
2186 def : ARMInstAlias<"srsib $mode!", (SRSIB_UPD imm0_31:$mode)>;
2188 // Return From Exception
2189 class RFEI<bit wb, string asm>
2190 : XI<(outs), (ins GPR:$Rn), AddrModeNone, 4, IndexModeNone, BrFrm,
2191 NoItinerary, asm, "", []> {
2193 let Inst{31-28} = 0b1111;
2194 let Inst{27-25} = 0b100;
2198 let Inst{19-16} = Rn;
2199 let Inst{15-0} = 0xa00;
2202 def RFEDA : RFEI<0, "rfeda\t$Rn"> {
2203 let Inst{24-23} = 0;
2205 def RFEDA_UPD : RFEI<1, "rfeda\t$Rn!"> {
2206 let Inst{24-23} = 0;
2208 def RFEDB : RFEI<0, "rfedb\t$Rn"> {
2209 let Inst{24-23} = 0b10;
2211 def RFEDB_UPD : RFEI<1, "rfedb\t$Rn!"> {
2212 let Inst{24-23} = 0b10;
2214 def RFEIA : RFEI<0, "rfeia\t$Rn"> {
2215 let Inst{24-23} = 0b01;
2217 def RFEIA_UPD : RFEI<1, "rfeia\t$Rn!"> {
2218 let Inst{24-23} = 0b01;
2220 def RFEIB : RFEI<0, "rfeib\t$Rn"> {
2221 let Inst{24-23} = 0b11;
2223 def RFEIB_UPD : RFEI<1, "rfeib\t$Rn!"> {
2224 let Inst{24-23} = 0b11;
2227 //===----------------------------------------------------------------------===//
2228 // Load / Store Instructions.
2234 defm LDR : AI_ldr1<0, "ldr", IIC_iLoad_r, IIC_iLoad_si,
2235 UnOpFrag<(load node:$Src)>>;
2236 defm LDRB : AI_ldr1nopc<1, "ldrb", IIC_iLoad_bh_r, IIC_iLoad_bh_si,
2237 UnOpFrag<(zextloadi8 node:$Src)>>;
2238 defm STR : AI_str1<0, "str", IIC_iStore_r, IIC_iStore_si,
2239 BinOpFrag<(store node:$LHS, node:$RHS)>>;
2240 defm STRB : AI_str1nopc<1, "strb", IIC_iStore_bh_r, IIC_iStore_bh_si,
2241 BinOpFrag<(truncstorei8 node:$LHS, node:$RHS)>>;
2243 // Special LDR for loads from non-pc-relative constpools.
2244 let canFoldAsLoad = 1, mayLoad = 1, neverHasSideEffects = 1,
2245 isReMaterializable = 1, isCodeGenOnly = 1 in
2246 def LDRcp : AI2ldst<0b010, 1, 0, (outs GPR:$Rt), (ins addrmode_imm12:$addr),
2247 AddrMode_i12, LdFrm, IIC_iLoad_r, "ldr", "\t$Rt, $addr",
2251 let Inst{23} = addr{12}; // U (add = ('U' == 1))
2252 let Inst{19-16} = 0b1111;
2253 let Inst{15-12} = Rt;
2254 let Inst{11-0} = addr{11-0}; // imm12
2257 // Loads with zero extension
2258 def LDRH : AI3ld<0b1011, 1, (outs GPR:$Rt), (ins addrmode3:$addr), LdMiscFrm,
2259 IIC_iLoad_bh_r, "ldrh", "\t$Rt, $addr",
2260 [(set GPR:$Rt, (zextloadi16 addrmode3:$addr))]>;
2262 // Loads with sign extension
2263 def LDRSH : AI3ld<0b1111, 1, (outs GPR:$Rt), (ins addrmode3:$addr), LdMiscFrm,
2264 IIC_iLoad_bh_r, "ldrsh", "\t$Rt, $addr",
2265 [(set GPR:$Rt, (sextloadi16 addrmode3:$addr))]>;
2267 def LDRSB : AI3ld<0b1101, 1, (outs GPR:$Rt), (ins addrmode3:$addr), LdMiscFrm,
2268 IIC_iLoad_bh_r, "ldrsb", "\t$Rt, $addr",
2269 [(set GPR:$Rt, (sextloadi8 addrmode3:$addr))]>;
2271 let mayLoad = 1, neverHasSideEffects = 1, hasExtraDefRegAllocReq = 1 in {
2273 def LDRD : AI3ld<0b1101, 0, (outs GPR:$Rd, GPR:$dst2),
2274 (ins addrmode3:$addr), LdMiscFrm,
2275 IIC_iLoad_d_r, "ldrd", "\t$Rd, $dst2, $addr",
2276 []>, Requires<[IsARM, HasV5TE]>;
2280 multiclass AI2_ldridx<bit isByte, string opc,
2281 InstrItinClass iii, InstrItinClass iir> {
2282 def _PRE_IMM : AI2ldstidx<1, isByte, 1, (outs GPR:$Rt, GPR:$Rn_wb),
2283 (ins addrmode_imm12_pre:$addr), IndexModePre, LdFrm, iii,
2284 opc, "\t$Rt, $addr!", "$addr.base = $Rn_wb", []> {
2287 let Inst{23} = addr{12};
2288 let Inst{19-16} = addr{16-13};
2289 let Inst{11-0} = addr{11-0};
2290 let DecoderMethod = "DecodeLDRPreImm";
2291 let AsmMatchConverter = "cvtLdWriteBackRegAddrModeImm12";
2294 def _PRE_REG : AI2ldstidx<1, isByte, 1, (outs GPR:$Rt, GPR:$Rn_wb),
2295 (ins ldst_so_reg:$addr), IndexModePre, LdFrm, iir,
2296 opc, "\t$Rt, $addr!", "$addr.base = $Rn_wb", []> {
2299 let Inst{23} = addr{12};
2300 let Inst{19-16} = addr{16-13};
2301 let Inst{11-0} = addr{11-0};
2303 let DecoderMethod = "DecodeLDRPreReg";
2304 let AsmMatchConverter = "cvtLdWriteBackRegAddrMode2";
2307 def _POST_REG : AI2ldstidx<1, isByte, 0, (outs GPR:$Rt, GPR:$Rn_wb),
2308 (ins addr_offset_none:$addr, am2offset_reg:$offset),
2309 IndexModePost, LdFrm, iir,
2310 opc, "\t$Rt, $addr, $offset",
2311 "$addr.base = $Rn_wb", []> {
2317 let Inst{23} = offset{12};
2318 let Inst{19-16} = addr;
2319 let Inst{11-0} = offset{11-0};
2322 let DecoderMethod = "DecodeAddrMode2IdxInstruction";
2325 def _POST_IMM : AI2ldstidx<1, isByte, 0, (outs GPR:$Rt, GPR:$Rn_wb),
2326 (ins addr_offset_none:$addr, am2offset_imm:$offset),
2327 IndexModePost, LdFrm, iii,
2328 opc, "\t$Rt, $addr, $offset",
2329 "$addr.base = $Rn_wb", []> {
2335 let Inst{23} = offset{12};
2336 let Inst{19-16} = addr;
2337 let Inst{11-0} = offset{11-0};
2339 let DecoderMethod = "DecodeAddrMode2IdxInstruction";
2344 let mayLoad = 1, neverHasSideEffects = 1 in {
2345 // FIXME: for LDR_PRE_REG etc. the itineray should be either IIC_iLoad_ru or
2346 // IIC_iLoad_siu depending on whether it the offset register is shifted.
2347 defm LDR : AI2_ldridx<0, "ldr", IIC_iLoad_iu, IIC_iLoad_ru>;
2348 defm LDRB : AI2_ldridx<1, "ldrb", IIC_iLoad_bh_iu, IIC_iLoad_bh_ru>;
2351 multiclass AI3_ldridx<bits<4> op, string opc, InstrItinClass itin> {
2352 def _PRE : AI3ldstidx<op, 1, 1, (outs GPR:$Rt, GPR:$Rn_wb),
2353 (ins addrmode3_pre:$addr), IndexModePre,
2355 opc, "\t$Rt, $addr!", "$addr.base = $Rn_wb", []> {
2357 let Inst{23} = addr{8}; // U bit
2358 let Inst{22} = addr{13}; // 1 == imm8, 0 == Rm
2359 let Inst{19-16} = addr{12-9}; // Rn
2360 let Inst{11-8} = addr{7-4}; // imm7_4/zero
2361 let Inst{3-0} = addr{3-0}; // imm3_0/Rm
2362 let AsmMatchConverter = "cvtLdWriteBackRegAddrMode3";
2363 let DecoderMethod = "DecodeAddrMode3Instruction";
2365 def _POST : AI3ldstidx<op, 1, 0, (outs GPR:$Rt, GPR:$Rn_wb),
2366 (ins addr_offset_none:$addr, am3offset:$offset),
2367 IndexModePost, LdMiscFrm, itin,
2368 opc, "\t$Rt, $addr, $offset", "$addr.base = $Rn_wb",
2372 let Inst{23} = offset{8}; // U bit
2373 let Inst{22} = offset{9}; // 1 == imm8, 0 == Rm
2374 let Inst{19-16} = addr;
2375 let Inst{11-8} = offset{7-4}; // imm7_4/zero
2376 let Inst{3-0} = offset{3-0}; // imm3_0/Rm
2377 let DecoderMethod = "DecodeAddrMode3Instruction";
2381 let mayLoad = 1, neverHasSideEffects = 1 in {
2382 defm LDRH : AI3_ldridx<0b1011, "ldrh", IIC_iLoad_bh_ru>;
2383 defm LDRSH : AI3_ldridx<0b1111, "ldrsh", IIC_iLoad_bh_ru>;
2384 defm LDRSB : AI3_ldridx<0b1101, "ldrsb", IIC_iLoad_bh_ru>;
2385 let hasExtraDefRegAllocReq = 1 in {
2386 def LDRD_PRE : AI3ldstidx<0b1101, 0, 1, (outs GPR:$Rt, GPR:$Rt2, GPR:$Rn_wb),
2387 (ins addrmode3_pre:$addr), IndexModePre,
2388 LdMiscFrm, IIC_iLoad_d_ru,
2389 "ldrd", "\t$Rt, $Rt2, $addr!",
2390 "$addr.base = $Rn_wb", []> {
2392 let Inst{23} = addr{8}; // U bit
2393 let Inst{22} = addr{13}; // 1 == imm8, 0 == Rm
2394 let Inst{19-16} = addr{12-9}; // Rn
2395 let Inst{11-8} = addr{7-4}; // imm7_4/zero
2396 let Inst{3-0} = addr{3-0}; // imm3_0/Rm
2397 let DecoderMethod = "DecodeAddrMode3Instruction";
2398 let AsmMatchConverter = "cvtLdrdPre";
2400 def LDRD_POST: AI3ldstidx<0b1101, 0, 0, (outs GPR:$Rt, GPR:$Rt2, GPR:$Rn_wb),
2401 (ins addr_offset_none:$addr, am3offset:$offset),
2402 IndexModePost, LdMiscFrm, IIC_iLoad_d_ru,
2403 "ldrd", "\t$Rt, $Rt2, $addr, $offset",
2404 "$addr.base = $Rn_wb", []> {
2407 let Inst{23} = offset{8}; // U bit
2408 let Inst{22} = offset{9}; // 1 == imm8, 0 == Rm
2409 let Inst{19-16} = addr;
2410 let Inst{11-8} = offset{7-4}; // imm7_4/zero
2411 let Inst{3-0} = offset{3-0}; // imm3_0/Rm
2412 let DecoderMethod = "DecodeAddrMode3Instruction";
2414 } // hasExtraDefRegAllocReq = 1
2415 } // mayLoad = 1, neverHasSideEffects = 1
2417 // LDRT, LDRBT, LDRSBT, LDRHT, LDRSHT.
2418 let mayLoad = 1, neverHasSideEffects = 1 in {
2419 def LDRT_POST_REG : AI2ldstidx<1, 0, 0, (outs GPR:$Rt, GPR:$Rn_wb),
2420 (ins addr_offset_none:$addr, am2offset_reg:$offset),
2421 IndexModePost, LdFrm, IIC_iLoad_ru,
2422 "ldrt", "\t$Rt, $addr, $offset",
2423 "$addr.base = $Rn_wb", []> {
2429 let Inst{23} = offset{12};
2430 let Inst{21} = 1; // overwrite
2431 let Inst{19-16} = addr;
2432 let Inst{11-5} = offset{11-5};
2434 let Inst{3-0} = offset{3-0};
2435 let DecoderMethod = "DecodeAddrMode2IdxInstruction";
2438 def LDRT_POST_IMM : AI2ldstidx<1, 0, 0, (outs GPR:$Rt, GPR:$Rn_wb),
2439 (ins addr_offset_none:$addr, am2offset_imm:$offset),
2440 IndexModePost, LdFrm, IIC_iLoad_ru,
2441 "ldrt", "\t$Rt, $addr, $offset",
2442 "$addr.base = $Rn_wb", []> {
2448 let Inst{23} = offset{12};
2449 let Inst{21} = 1; // overwrite
2450 let Inst{19-16} = addr;
2451 let Inst{11-0} = offset{11-0};
2452 let DecoderMethod = "DecodeAddrMode2IdxInstruction";
2455 def LDRBT_POST_REG : AI2ldstidx<1, 1, 0, (outs GPR:$Rt, GPR:$Rn_wb),
2456 (ins addr_offset_none:$addr, am2offset_reg:$offset),
2457 IndexModePost, LdFrm, IIC_iLoad_bh_ru,
2458 "ldrbt", "\t$Rt, $addr, $offset",
2459 "$addr.base = $Rn_wb", []> {
2465 let Inst{23} = offset{12};
2466 let Inst{21} = 1; // overwrite
2467 let Inst{19-16} = addr;
2468 let Inst{11-5} = offset{11-5};
2470 let Inst{3-0} = offset{3-0};
2471 let DecoderMethod = "DecodeAddrMode2IdxInstruction";
2474 def LDRBT_POST_IMM : AI2ldstidx<1, 1, 0, (outs GPR:$Rt, GPR:$Rn_wb),
2475 (ins addr_offset_none:$addr, am2offset_imm:$offset),
2476 IndexModePost, LdFrm, IIC_iLoad_bh_ru,
2477 "ldrbt", "\t$Rt, $addr, $offset",
2478 "$addr.base = $Rn_wb", []> {
2484 let Inst{23} = offset{12};
2485 let Inst{21} = 1; // overwrite
2486 let Inst{19-16} = addr;
2487 let Inst{11-0} = offset{11-0};
2488 let DecoderMethod = "DecodeAddrMode2IdxInstruction";
2491 multiclass AI3ldrT<bits<4> op, string opc> {
2492 def i : AI3ldstidxT<op, 1, (outs GPR:$Rt, GPR:$base_wb),
2493 (ins addr_offset_none:$addr, postidx_imm8:$offset),
2494 IndexModePost, LdMiscFrm, IIC_iLoad_bh_ru, opc,
2495 "\t$Rt, $addr, $offset", "$addr.base = $base_wb", []> {
2497 let Inst{23} = offset{8};
2499 let Inst{11-8} = offset{7-4};
2500 let Inst{3-0} = offset{3-0};
2501 let AsmMatchConverter = "cvtLdExtTWriteBackImm";
2503 def r : AI3ldstidxT<op, 1, (outs GPRnopc:$Rt, GPRnopc:$base_wb),
2504 (ins addr_offset_none:$addr, postidx_reg:$Rm),
2505 IndexModePost, LdMiscFrm, IIC_iLoad_bh_ru, opc,
2506 "\t$Rt, $addr, $Rm", "$addr.base = $base_wb", []> {
2508 let Inst{23} = Rm{4};
2511 let Unpredictable{11-8} = 0b1111;
2512 let Inst{3-0} = Rm{3-0};
2513 let AsmMatchConverter = "cvtLdExtTWriteBackReg";
2514 let DecoderMethod = "DecodeLDR";
2518 defm LDRSBT : AI3ldrT<0b1101, "ldrsbt">;
2519 defm LDRHT : AI3ldrT<0b1011, "ldrht">;
2520 defm LDRSHT : AI3ldrT<0b1111, "ldrsht">;
2525 // Stores with truncate
2526 def STRH : AI3str<0b1011, (outs), (ins GPR:$Rt, addrmode3:$addr), StMiscFrm,
2527 IIC_iStore_bh_r, "strh", "\t$Rt, $addr",
2528 [(truncstorei16 GPR:$Rt, addrmode3:$addr)]>;
2531 let mayStore = 1, neverHasSideEffects = 1, hasExtraSrcRegAllocReq = 1 in
2532 def STRD : AI3str<0b1111, (outs), (ins GPR:$Rt, GPR:$src2, addrmode3:$addr),
2533 StMiscFrm, IIC_iStore_d_r,
2534 "strd", "\t$Rt, $src2, $addr", []>,
2535 Requires<[IsARM, HasV5TE]> {
2540 multiclass AI2_stridx<bit isByte, string opc,
2541 InstrItinClass iii, InstrItinClass iir> {
2542 def _PRE_IMM : AI2ldstidx<0, isByte, 1, (outs GPR:$Rn_wb),
2543 (ins GPR:$Rt, addrmode_imm12_pre:$addr), IndexModePre,
2545 opc, "\t$Rt, $addr!", "$addr.base = $Rn_wb", []> {
2548 let Inst{23} = addr{12}; // U (add = ('U' == 1))
2549 let Inst{19-16} = addr{16-13}; // Rn
2550 let Inst{11-0} = addr{11-0}; // imm12
2551 let AsmMatchConverter = "cvtStWriteBackRegAddrModeImm12";
2552 let DecoderMethod = "DecodeSTRPreImm";
2555 def _PRE_REG : AI2ldstidx<0, isByte, 1, (outs GPR:$Rn_wb),
2556 (ins GPR:$Rt, ldst_so_reg:$addr),
2557 IndexModePre, StFrm, iir,
2558 opc, "\t$Rt, $addr!", "$addr.base = $Rn_wb", []> {
2561 let Inst{23} = addr{12}; // U (add = ('U' == 1))
2562 let Inst{19-16} = addr{16-13}; // Rn
2563 let Inst{11-0} = addr{11-0};
2564 let Inst{4} = 0; // Inst{4} = 0
2565 let AsmMatchConverter = "cvtStWriteBackRegAddrMode2";
2566 let DecoderMethod = "DecodeSTRPreReg";
2568 def _POST_REG : AI2ldstidx<0, isByte, 0, (outs GPR:$Rn_wb),
2569 (ins GPR:$Rt, addr_offset_none:$addr, am2offset_reg:$offset),
2570 IndexModePost, StFrm, iir,
2571 opc, "\t$Rt, $addr, $offset",
2572 "$addr.base = $Rn_wb", []> {
2578 let Inst{23} = offset{12};
2579 let Inst{19-16} = addr;
2580 let Inst{11-0} = offset{11-0};
2583 let DecoderMethod = "DecodeAddrMode2IdxInstruction";
2586 def _POST_IMM : AI2ldstidx<0, isByte, 0, (outs GPR:$Rn_wb),
2587 (ins GPR:$Rt, addr_offset_none:$addr, am2offset_imm:$offset),
2588 IndexModePost, StFrm, iii,
2589 opc, "\t$Rt, $addr, $offset",
2590 "$addr.base = $Rn_wb", []> {
2596 let Inst{23} = offset{12};
2597 let Inst{19-16} = addr;
2598 let Inst{11-0} = offset{11-0};
2600 let DecoderMethod = "DecodeAddrMode2IdxInstruction";
2604 let mayStore = 1, neverHasSideEffects = 1 in {
2605 // FIXME: for STR_PRE_REG etc. the itineray should be either IIC_iStore_ru or
2606 // IIC_iStore_siu depending on whether it the offset register is shifted.
2607 defm STR : AI2_stridx<0, "str", IIC_iStore_iu, IIC_iStore_ru>;
2608 defm STRB : AI2_stridx<1, "strb", IIC_iStore_bh_iu, IIC_iStore_bh_ru>;
2611 def : ARMPat<(post_store GPR:$Rt, addr_offset_none:$addr,
2612 am2offset_reg:$offset),
2613 (STR_POST_REG GPR:$Rt, addr_offset_none:$addr,
2614 am2offset_reg:$offset)>;
2615 def : ARMPat<(post_store GPR:$Rt, addr_offset_none:$addr,
2616 am2offset_imm:$offset),
2617 (STR_POST_IMM GPR:$Rt, addr_offset_none:$addr,
2618 am2offset_imm:$offset)>;
2619 def : ARMPat<(post_truncsti8 GPR:$Rt, addr_offset_none:$addr,
2620 am2offset_reg:$offset),
2621 (STRB_POST_REG GPR:$Rt, addr_offset_none:$addr,
2622 am2offset_reg:$offset)>;
2623 def : ARMPat<(post_truncsti8 GPR:$Rt, addr_offset_none:$addr,
2624 am2offset_imm:$offset),
2625 (STRB_POST_IMM GPR:$Rt, addr_offset_none:$addr,
2626 am2offset_imm:$offset)>;
2628 // Pseudo-instructions for pattern matching the pre-indexed stores. We can't
2629 // put the patterns on the instruction definitions directly as ISel wants
2630 // the address base and offset to be separate operands, not a single
2631 // complex operand like we represent the instructions themselves. The
2632 // pseudos map between the two.
2633 let usesCustomInserter = 1,
2634 Constraints = "$Rn = $Rn_wb,@earlyclobber $Rn_wb" in {
2635 def STRi_preidx: ARMPseudoInst<(outs GPR:$Rn_wb),
2636 (ins GPR:$Rt, GPR:$Rn, am2offset_imm:$offset, pred:$p),
2639 (pre_store GPR:$Rt, GPR:$Rn, am2offset_imm:$offset))]>;
2640 def STRr_preidx: ARMPseudoInst<(outs GPR:$Rn_wb),
2641 (ins GPR:$Rt, GPR:$Rn, am2offset_reg:$offset, pred:$p),
2644 (pre_store GPR:$Rt, GPR:$Rn, am2offset_reg:$offset))]>;
2645 def STRBi_preidx: ARMPseudoInst<(outs GPR:$Rn_wb),
2646 (ins GPR:$Rt, GPR:$Rn, am2offset_imm:$offset, pred:$p),
2649 (pre_truncsti8 GPR:$Rt, GPR:$Rn, am2offset_imm:$offset))]>;
2650 def STRBr_preidx: ARMPseudoInst<(outs GPR:$Rn_wb),
2651 (ins GPR:$Rt, GPR:$Rn, am2offset_reg:$offset, pred:$p),
2654 (pre_truncsti8 GPR:$Rt, GPR:$Rn, am2offset_reg:$offset))]>;
2655 def STRH_preidx: ARMPseudoInst<(outs GPR:$Rn_wb),
2656 (ins GPR:$Rt, GPR:$Rn, am3offset:$offset, pred:$p),
2659 (pre_truncsti16 GPR:$Rt, GPR:$Rn, am3offset:$offset))]>;
2664 def STRH_PRE : AI3ldstidx<0b1011, 0, 1, (outs GPR:$Rn_wb),
2665 (ins GPR:$Rt, addrmode3_pre:$addr), IndexModePre,
2666 StMiscFrm, IIC_iStore_bh_ru,
2667 "strh", "\t$Rt, $addr!", "$addr.base = $Rn_wb", []> {
2669 let Inst{23} = addr{8}; // U bit
2670 let Inst{22} = addr{13}; // 1 == imm8, 0 == Rm
2671 let Inst{19-16} = addr{12-9}; // Rn
2672 let Inst{11-8} = addr{7-4}; // imm7_4/zero
2673 let Inst{3-0} = addr{3-0}; // imm3_0/Rm
2674 let AsmMatchConverter = "cvtStWriteBackRegAddrMode3";
2675 let DecoderMethod = "DecodeAddrMode3Instruction";
2678 def STRH_POST : AI3ldstidx<0b1011, 0, 0, (outs GPR:$Rn_wb),
2679 (ins GPR:$Rt, addr_offset_none:$addr, am3offset:$offset),
2680 IndexModePost, StMiscFrm, IIC_iStore_bh_ru,
2681 "strh", "\t$Rt, $addr, $offset", "$addr.base = $Rn_wb",
2682 [(set GPR:$Rn_wb, (post_truncsti16 GPR:$Rt,
2683 addr_offset_none:$addr,
2684 am3offset:$offset))]> {
2687 let Inst{23} = offset{8}; // U bit
2688 let Inst{22} = offset{9}; // 1 == imm8, 0 == Rm
2689 let Inst{19-16} = addr;
2690 let Inst{11-8} = offset{7-4}; // imm7_4/zero
2691 let Inst{3-0} = offset{3-0}; // imm3_0/Rm
2692 let DecoderMethod = "DecodeAddrMode3Instruction";
2695 let mayStore = 1, neverHasSideEffects = 1, hasExtraSrcRegAllocReq = 1 in {
2696 def STRD_PRE : AI3ldstidx<0b1111, 0, 1, (outs GPR:$Rn_wb),
2697 (ins GPR:$Rt, GPR:$Rt2, addrmode3_pre:$addr),
2698 IndexModePre, StMiscFrm, IIC_iStore_d_ru,
2699 "strd", "\t$Rt, $Rt2, $addr!",
2700 "$addr.base = $Rn_wb", []> {
2702 let Inst{23} = addr{8}; // U bit
2703 let Inst{22} = addr{13}; // 1 == imm8, 0 == Rm
2704 let Inst{19-16} = addr{12-9}; // Rn
2705 let Inst{11-8} = addr{7-4}; // imm7_4/zero
2706 let Inst{3-0} = addr{3-0}; // imm3_0/Rm
2707 let DecoderMethod = "DecodeAddrMode3Instruction";
2708 let AsmMatchConverter = "cvtStrdPre";
2711 def STRD_POST: AI3ldstidx<0b1111, 0, 0, (outs GPR:$Rn_wb),
2712 (ins GPR:$Rt, GPR:$Rt2, addr_offset_none:$addr,
2714 IndexModePost, StMiscFrm, IIC_iStore_d_ru,
2715 "strd", "\t$Rt, $Rt2, $addr, $offset",
2716 "$addr.base = $Rn_wb", []> {
2719 let Inst{23} = offset{8}; // U bit
2720 let Inst{22} = offset{9}; // 1 == imm8, 0 == Rm
2721 let Inst{19-16} = addr;
2722 let Inst{11-8} = offset{7-4}; // imm7_4/zero
2723 let Inst{3-0} = offset{3-0}; // imm3_0/Rm
2724 let DecoderMethod = "DecodeAddrMode3Instruction";
2726 } // mayStore = 1, neverHasSideEffects = 1, hasExtraSrcRegAllocReq = 1
2728 // STRT, STRBT, and STRHT
2730 def STRBT_POST_REG : AI2ldstidx<0, 1, 0, (outs GPR:$Rn_wb),
2731 (ins GPR:$Rt, addr_offset_none:$addr, am2offset_reg:$offset),
2732 IndexModePost, StFrm, IIC_iStore_bh_ru,
2733 "strbt", "\t$Rt, $addr, $offset",
2734 "$addr.base = $Rn_wb", []> {
2740 let Inst{23} = offset{12};
2741 let Inst{21} = 1; // overwrite
2742 let Inst{19-16} = addr;
2743 let Inst{11-5} = offset{11-5};
2745 let Inst{3-0} = offset{3-0};
2746 let DecoderMethod = "DecodeAddrMode2IdxInstruction";
2749 def STRBT_POST_IMM : AI2ldstidx<0, 1, 0, (outs GPR:$Rn_wb),
2750 (ins GPR:$Rt, addr_offset_none:$addr, am2offset_imm:$offset),
2751 IndexModePost, StFrm, IIC_iStore_bh_ru,
2752 "strbt", "\t$Rt, $addr, $offset",
2753 "$addr.base = $Rn_wb", []> {
2759 let Inst{23} = offset{12};
2760 let Inst{21} = 1; // overwrite
2761 let Inst{19-16} = addr;
2762 let Inst{11-0} = offset{11-0};
2763 let DecoderMethod = "DecodeAddrMode2IdxInstruction";
2766 let mayStore = 1, neverHasSideEffects = 1 in {
2767 def STRT_POST_REG : AI2ldstidx<0, 0, 0, (outs GPR:$Rn_wb),
2768 (ins GPR:$Rt, addr_offset_none:$addr, am2offset_reg:$offset),
2769 IndexModePost, StFrm, IIC_iStore_ru,
2770 "strt", "\t$Rt, $addr, $offset",
2771 "$addr.base = $Rn_wb", []> {
2777 let Inst{23} = offset{12};
2778 let Inst{21} = 1; // overwrite
2779 let Inst{19-16} = addr;
2780 let Inst{11-5} = offset{11-5};
2782 let Inst{3-0} = offset{3-0};
2783 let DecoderMethod = "DecodeAddrMode2IdxInstruction";
2786 def STRT_POST_IMM : AI2ldstidx<0, 0, 0, (outs GPR:$Rn_wb),
2787 (ins GPR:$Rt, addr_offset_none:$addr, am2offset_imm:$offset),
2788 IndexModePost, StFrm, IIC_iStore_ru,
2789 "strt", "\t$Rt, $addr, $offset",
2790 "$addr.base = $Rn_wb", []> {
2796 let Inst{23} = offset{12};
2797 let Inst{21} = 1; // overwrite
2798 let Inst{19-16} = addr;
2799 let Inst{11-0} = offset{11-0};
2800 let DecoderMethod = "DecodeAddrMode2IdxInstruction";
2805 multiclass AI3strT<bits<4> op, string opc> {
2806 def i : AI3ldstidxT<op, 0, (outs GPR:$base_wb),
2807 (ins GPR:$Rt, addr_offset_none:$addr, postidx_imm8:$offset),
2808 IndexModePost, StMiscFrm, IIC_iStore_bh_ru, opc,
2809 "\t$Rt, $addr, $offset", "$addr.base = $base_wb", []> {
2811 let Inst{23} = offset{8};
2813 let Inst{11-8} = offset{7-4};
2814 let Inst{3-0} = offset{3-0};
2815 let AsmMatchConverter = "cvtStExtTWriteBackImm";
2817 def r : AI3ldstidxT<op, 0, (outs GPR:$base_wb),
2818 (ins GPR:$Rt, addr_offset_none:$addr, postidx_reg:$Rm),
2819 IndexModePost, StMiscFrm, IIC_iStore_bh_ru, opc,
2820 "\t$Rt, $addr, $Rm", "$addr.base = $base_wb", []> {
2822 let Inst{23} = Rm{4};
2825 let Inst{3-0} = Rm{3-0};
2826 let AsmMatchConverter = "cvtStExtTWriteBackReg";
2831 defm STRHT : AI3strT<0b1011, "strht">;
2834 //===----------------------------------------------------------------------===//
2835 // Load / store multiple Instructions.
2838 multiclass arm_ldst_mult<string asm, string sfx, bit L_bit, bit P_bit, Format f,
2839 InstrItinClass itin, InstrItinClass itin_upd> {
2840 // IA is the default, so no need for an explicit suffix on the
2841 // mnemonic here. Without it is the canonical spelling.
2843 AXI4<(outs), (ins GPR:$Rn, pred:$p, reglist:$regs, variable_ops),
2844 IndexModeNone, f, itin,
2845 !strconcat(asm, "${p}\t$Rn, $regs", sfx), "", []> {
2846 let Inst{24-23} = 0b01; // Increment After
2847 let Inst{22} = P_bit;
2848 let Inst{21} = 0; // No writeback
2849 let Inst{20} = L_bit;
2852 AXI4<(outs GPR:$wb), (ins GPR:$Rn, pred:$p, reglist:$regs, variable_ops),
2853 IndexModeUpd, f, itin_upd,
2854 !strconcat(asm, "${p}\t$Rn!, $regs", sfx), "$Rn = $wb", []> {
2855 let Inst{24-23} = 0b01; // Increment After
2856 let Inst{22} = P_bit;
2857 let Inst{21} = 1; // Writeback
2858 let Inst{20} = L_bit;
2860 let DecoderMethod = "DecodeMemMultipleWritebackInstruction";
2863 AXI4<(outs), (ins GPR:$Rn, pred:$p, reglist:$regs, variable_ops),
2864 IndexModeNone, f, itin,
2865 !strconcat(asm, "da${p}\t$Rn, $regs", sfx), "", []> {
2866 let Inst{24-23} = 0b00; // Decrement After
2867 let Inst{22} = P_bit;
2868 let Inst{21} = 0; // No writeback
2869 let Inst{20} = L_bit;
2872 AXI4<(outs GPR:$wb), (ins GPR:$Rn, pred:$p, reglist:$regs, variable_ops),
2873 IndexModeUpd, f, itin_upd,
2874 !strconcat(asm, "da${p}\t$Rn!, $regs", sfx), "$Rn = $wb", []> {
2875 let Inst{24-23} = 0b00; // Decrement After
2876 let Inst{22} = P_bit;
2877 let Inst{21} = 1; // Writeback
2878 let Inst{20} = L_bit;
2880 let DecoderMethod = "DecodeMemMultipleWritebackInstruction";
2883 AXI4<(outs), (ins GPR:$Rn, pred:$p, reglist:$regs, variable_ops),
2884 IndexModeNone, f, itin,
2885 !strconcat(asm, "db${p}\t$Rn, $regs", sfx), "", []> {
2886 let Inst{24-23} = 0b10; // Decrement Before
2887 let Inst{22} = P_bit;
2888 let Inst{21} = 0; // No writeback
2889 let Inst{20} = L_bit;
2892 AXI4<(outs GPR:$wb), (ins GPR:$Rn, pred:$p, reglist:$regs, variable_ops),
2893 IndexModeUpd, f, itin_upd,
2894 !strconcat(asm, "db${p}\t$Rn!, $regs", sfx), "$Rn = $wb", []> {
2895 let Inst{24-23} = 0b10; // Decrement Before
2896 let Inst{22} = P_bit;
2897 let Inst{21} = 1; // Writeback
2898 let Inst{20} = L_bit;
2900 let DecoderMethod = "DecodeMemMultipleWritebackInstruction";
2903 AXI4<(outs), (ins GPR:$Rn, pred:$p, reglist:$regs, variable_ops),
2904 IndexModeNone, f, itin,
2905 !strconcat(asm, "ib${p}\t$Rn, $regs", sfx), "", []> {
2906 let Inst{24-23} = 0b11; // Increment Before
2907 let Inst{22} = P_bit;
2908 let Inst{21} = 0; // No writeback
2909 let Inst{20} = L_bit;
2912 AXI4<(outs GPR:$wb), (ins GPR:$Rn, pred:$p, reglist:$regs, variable_ops),
2913 IndexModeUpd, f, itin_upd,
2914 !strconcat(asm, "ib${p}\t$Rn!, $regs", sfx), "$Rn = $wb", []> {
2915 let Inst{24-23} = 0b11; // Increment Before
2916 let Inst{22} = P_bit;
2917 let Inst{21} = 1; // Writeback
2918 let Inst{20} = L_bit;
2920 let DecoderMethod = "DecodeMemMultipleWritebackInstruction";
2924 let neverHasSideEffects = 1 in {
2926 let mayLoad = 1, hasExtraDefRegAllocReq = 1 in
2927 defm LDM : arm_ldst_mult<"ldm", "", 1, 0, LdStMulFrm, IIC_iLoad_m,
2930 let mayStore = 1, hasExtraSrcRegAllocReq = 1 in
2931 defm STM : arm_ldst_mult<"stm", "", 0, 0, LdStMulFrm, IIC_iStore_m,
2934 } // neverHasSideEffects
2936 // FIXME: remove when we have a way to marking a MI with these properties.
2937 // FIXME: Should pc be an implicit operand like PICADD, etc?
2938 let isReturn = 1, isTerminator = 1, isBarrier = 1, mayLoad = 1,
2939 hasExtraDefRegAllocReq = 1, isCodeGenOnly = 1 in
2940 def LDMIA_RET : ARMPseudoExpand<(outs GPR:$wb), (ins GPR:$Rn, pred:$p,
2941 reglist:$regs, variable_ops),
2942 4, IIC_iLoad_mBr, [],
2943 (LDMIA_UPD GPR:$wb, GPR:$Rn, pred:$p, reglist:$regs)>,
2944 RegConstraint<"$Rn = $wb">;
2946 let mayLoad = 1, hasExtraDefRegAllocReq = 1 in
2947 defm sysLDM : arm_ldst_mult<"ldm", " ^", 1, 1, LdStMulFrm, IIC_iLoad_m,
2950 let mayStore = 1, hasExtraSrcRegAllocReq = 1 in
2951 defm sysSTM : arm_ldst_mult<"stm", " ^", 0, 1, LdStMulFrm, IIC_iStore_m,
2956 //===----------------------------------------------------------------------===//
2957 // Move Instructions.
2960 let neverHasSideEffects = 1 in
2961 def MOVr : AsI1<0b1101, (outs GPR:$Rd), (ins GPR:$Rm), DPFrm, IIC_iMOVr,
2962 "mov", "\t$Rd, $Rm", []>, UnaryDP, Sched<[WriteALU]> {
2966 let Inst{19-16} = 0b0000;
2967 let Inst{11-4} = 0b00000000;
2970 let Inst{15-12} = Rd;
2973 // A version for the smaller set of tail call registers.
2974 let neverHasSideEffects = 1 in
2975 def MOVr_TC : AsI1<0b1101, (outs tcGPR:$Rd), (ins tcGPR:$Rm), DPFrm,
2976 IIC_iMOVr, "mov", "\t$Rd, $Rm", []>, UnaryDP, Sched<[WriteALU]> {
2980 let Inst{11-4} = 0b00000000;
2983 let Inst{15-12} = Rd;
2986 def MOVsr : AsI1<0b1101, (outs GPRnopc:$Rd), (ins shift_so_reg_reg:$src),
2987 DPSoRegRegFrm, IIC_iMOVsr,
2988 "mov", "\t$Rd, $src",
2989 [(set GPRnopc:$Rd, shift_so_reg_reg:$src)]>, UnaryDP,
2993 let Inst{15-12} = Rd;
2994 let Inst{19-16} = 0b0000;
2995 let Inst{11-8} = src{11-8};
2997 let Inst{6-5} = src{6-5};
2999 let Inst{3-0} = src{3-0};
3003 def MOVsi : AsI1<0b1101, (outs GPR:$Rd), (ins shift_so_reg_imm:$src),
3004 DPSoRegImmFrm, IIC_iMOVsr,
3005 "mov", "\t$Rd, $src", [(set GPR:$Rd, shift_so_reg_imm:$src)]>,
3006 UnaryDP, Sched<[WriteALU]> {
3009 let Inst{15-12} = Rd;
3010 let Inst{19-16} = 0b0000;
3011 let Inst{11-5} = src{11-5};
3013 let Inst{3-0} = src{3-0};
3017 let isReMaterializable = 1, isAsCheapAsAMove = 1, isMoveImm = 1 in
3018 def MOVi : AsI1<0b1101, (outs GPR:$Rd), (ins so_imm:$imm), DPFrm, IIC_iMOVi,
3019 "mov", "\t$Rd, $imm", [(set GPR:$Rd, so_imm:$imm)]>, UnaryDP,
3024 let Inst{15-12} = Rd;
3025 let Inst{19-16} = 0b0000;
3026 let Inst{11-0} = imm;
3029 let isReMaterializable = 1, isAsCheapAsAMove = 1, isMoveImm = 1 in
3030 def MOVi16 : AI1<0b1000, (outs GPR:$Rd), (ins imm0_65535_expr:$imm),
3032 "movw", "\t$Rd, $imm",
3033 [(set GPR:$Rd, imm0_65535:$imm)]>,
3034 Requires<[IsARM, HasV6T2]>, UnaryDP, Sched<[WriteALU]> {
3037 let Inst{15-12} = Rd;
3038 let Inst{11-0} = imm{11-0};
3039 let Inst{19-16} = imm{15-12};
3042 let DecoderMethod = "DecodeArmMOVTWInstruction";
3045 def : InstAlias<"mov${p} $Rd, $imm",
3046 (MOVi16 GPR:$Rd, imm0_65535_expr:$imm, pred:$p)>,
3049 def MOVi16_ga_pcrel : PseudoInst<(outs GPR:$Rd),
3050 (ins i32imm:$addr, pclabel:$id), IIC_iMOVi, []>,
3053 let Constraints = "$src = $Rd" in {
3054 def MOVTi16 : AI1<0b1010, (outs GPRnopc:$Rd),
3055 (ins GPR:$src, imm0_65535_expr:$imm),
3057 "movt", "\t$Rd, $imm",
3059 (or (and GPR:$src, 0xffff),
3060 lo16AllZero:$imm))]>, UnaryDP,
3061 Requires<[IsARM, HasV6T2]>, Sched<[WriteALU]> {
3064 let Inst{15-12} = Rd;
3065 let Inst{11-0} = imm{11-0};
3066 let Inst{19-16} = imm{15-12};
3069 let DecoderMethod = "DecodeArmMOVTWInstruction";
3072 def MOVTi16_ga_pcrel : PseudoInst<(outs GPR:$Rd),
3073 (ins GPR:$src, i32imm:$addr, pclabel:$id), IIC_iMOVi, []>,
3078 def : ARMPat<(or GPR:$src, 0xffff0000), (MOVTi16 GPR:$src, 0xffff)>,
3079 Requires<[IsARM, HasV6T2]>;
3081 let Uses = [CPSR] in
3082 def RRX: PseudoInst<(outs GPR:$Rd), (ins GPR:$Rm), IIC_iMOVsi,
3083 [(set GPR:$Rd, (ARMrrx GPR:$Rm))]>, UnaryDP,
3084 Requires<[IsARM]>, Sched<[WriteALU]>;
3086 // These aren't really mov instructions, but we have to define them this way
3087 // due to flag operands.
3089 let Defs = [CPSR] in {
3090 def MOVsrl_flag : PseudoInst<(outs GPR:$dst), (ins GPR:$src), IIC_iMOVsi,
3091 [(set GPR:$dst, (ARMsrl_flag GPR:$src))]>, UnaryDP,
3092 Sched<[WriteALU]>, Requires<[IsARM]>;
3093 def MOVsra_flag : PseudoInst<(outs GPR:$dst), (ins GPR:$src), IIC_iMOVsi,
3094 [(set GPR:$dst, (ARMsra_flag GPR:$src))]>, UnaryDP,
3095 Sched<[WriteALU]>, Requires<[IsARM]>;
3098 //===----------------------------------------------------------------------===//
3099 // Extend Instructions.
3104 def SXTB : AI_ext_rrot<0b01101010,
3105 "sxtb", UnOpFrag<(sext_inreg node:$Src, i8)>>;
3106 def SXTH : AI_ext_rrot<0b01101011,
3107 "sxth", UnOpFrag<(sext_inreg node:$Src, i16)>>;
3109 def SXTAB : AI_exta_rrot<0b01101010,
3110 "sxtab", BinOpFrag<(add node:$LHS, (sext_inreg node:$RHS, i8))>>;
3111 def SXTAH : AI_exta_rrot<0b01101011,
3112 "sxtah", BinOpFrag<(add node:$LHS, (sext_inreg node:$RHS,i16))>>;
3114 def SXTB16 : AI_ext_rrot_np<0b01101000, "sxtb16">;
3116 def SXTAB16 : AI_exta_rrot_np<0b01101000, "sxtab16">;
3120 let AddedComplexity = 16 in {
3121 def UXTB : AI_ext_rrot<0b01101110,
3122 "uxtb" , UnOpFrag<(and node:$Src, 0x000000FF)>>;
3123 def UXTH : AI_ext_rrot<0b01101111,
3124 "uxth" , UnOpFrag<(and node:$Src, 0x0000FFFF)>>;
3125 def UXTB16 : AI_ext_rrot<0b01101100,
3126 "uxtb16", UnOpFrag<(and node:$Src, 0x00FF00FF)>>;
3128 // FIXME: This pattern incorrectly assumes the shl operator is a rotate.
3129 // The transformation should probably be done as a combiner action
3130 // instead so we can include a check for masking back in the upper
3131 // eight bits of the source into the lower eight bits of the result.
3132 //def : ARMV6Pat<(and (shl GPR:$Src, (i32 8)), 0xFF00FF),
3133 // (UXTB16r_rot GPR:$Src, 3)>;
3134 def : ARMV6Pat<(and (srl GPR:$Src, (i32 8)), 0xFF00FF),
3135 (UXTB16 GPR:$Src, 1)>;
3137 def UXTAB : AI_exta_rrot<0b01101110, "uxtab",
3138 BinOpFrag<(add node:$LHS, (and node:$RHS, 0x00FF))>>;
3139 def UXTAH : AI_exta_rrot<0b01101111, "uxtah",
3140 BinOpFrag<(add node:$LHS, (and node:$RHS, 0xFFFF))>>;
3143 // This isn't safe in general, the add is two 16-bit units, not a 32-bit add.
3144 def UXTAB16 : AI_exta_rrot_np<0b01101100, "uxtab16">;
3147 def SBFX : I<(outs GPRnopc:$Rd),
3148 (ins GPRnopc:$Rn, imm0_31:$lsb, imm1_32:$width),
3149 AddrMode1, 4, IndexModeNone, DPFrm, IIC_iUNAsi,
3150 "sbfx", "\t$Rd, $Rn, $lsb, $width", "", []>,
3151 Requires<[IsARM, HasV6T2]> {
3156 let Inst{27-21} = 0b0111101;
3157 let Inst{6-4} = 0b101;
3158 let Inst{20-16} = width;
3159 let Inst{15-12} = Rd;
3160 let Inst{11-7} = lsb;
3164 def UBFX : I<(outs GPR:$Rd),
3165 (ins GPR:$Rn, imm0_31:$lsb, imm1_32:$width),
3166 AddrMode1, 4, IndexModeNone, DPFrm, IIC_iUNAsi,
3167 "ubfx", "\t$Rd, $Rn, $lsb, $width", "", []>,
3168 Requires<[IsARM, HasV6T2]> {
3173 let Inst{27-21} = 0b0111111;
3174 let Inst{6-4} = 0b101;
3175 let Inst{20-16} = width;
3176 let Inst{15-12} = Rd;
3177 let Inst{11-7} = lsb;
3181 //===----------------------------------------------------------------------===//
3182 // Arithmetic Instructions.
3185 defm ADD : AsI1_bin_irs<0b0100, "add",
3186 IIC_iALUi, IIC_iALUr, IIC_iALUsr,
3187 BinOpFrag<(add node:$LHS, node:$RHS)>, 1>;
3188 defm SUB : AsI1_bin_irs<0b0010, "sub",
3189 IIC_iALUi, IIC_iALUr, IIC_iALUsr,
3190 BinOpFrag<(sub node:$LHS, node:$RHS)>>;
3192 // ADD and SUB with 's' bit set.
3194 // Currently, ADDS/SUBS are pseudo opcodes that exist only in the
3195 // selection DAG. They are "lowered" to real ADD/SUB opcodes by
3196 // AdjustInstrPostInstrSelection where we determine whether or not to
3197 // set the "s" bit based on CPSR liveness.
3199 // FIXME: Eliminate ADDS/SUBS pseudo opcodes after adding tablegen
3200 // support for an optional CPSR definition that corresponds to the DAG
3201 // node's second value. We can then eliminate the implicit def of CPSR.
3202 defm ADDS : AsI1_bin_s_irs<IIC_iALUi, IIC_iALUr, IIC_iALUsr,
3203 BinOpFrag<(ARMaddc node:$LHS, node:$RHS)>, 1>;
3204 defm SUBS : AsI1_bin_s_irs<IIC_iALUi, IIC_iALUr, IIC_iALUsr,
3205 BinOpFrag<(ARMsubc node:$LHS, node:$RHS)>>;
3207 defm ADC : AI1_adde_sube_irs<0b0101, "adc",
3208 BinOpWithFlagFrag<(ARMadde node:$LHS, node:$RHS, node:$FLAG)>, 1>;
3209 defm SBC : AI1_adde_sube_irs<0b0110, "sbc",
3210 BinOpWithFlagFrag<(ARMsube node:$LHS, node:$RHS, node:$FLAG)>>;
3212 defm RSB : AsI1_rbin_irs<0b0011, "rsb",
3213 IIC_iALUi, IIC_iALUr, IIC_iALUsr,
3214 BinOpFrag<(sub node:$LHS, node:$RHS)>>;
3216 // FIXME: Eliminate them if we can write def : Pat patterns which defines
3217 // CPSR and the implicit def of CPSR is not needed.
3218 defm RSBS : AsI1_rbin_s_is<IIC_iALUi, IIC_iALUr, IIC_iALUsr,
3219 BinOpFrag<(ARMsubc node:$LHS, node:$RHS)>>;
3221 defm RSC : AI1_rsc_irs<0b0111, "rsc",
3222 BinOpWithFlagFrag<(ARMsube node:$LHS, node:$RHS, node:$FLAG)>>;
3224 // (sub X, imm) gets canonicalized to (add X, -imm). Match this form.
3225 // The assume-no-carry-in form uses the negation of the input since add/sub
3226 // assume opposite meanings of the carry flag (i.e., carry == !borrow).
3227 // See the definition of AddWithCarry() in the ARM ARM A2.2.1 for the gory
3229 def : ARMPat<(add GPR:$src, so_imm_neg:$imm),
3230 (SUBri GPR:$src, so_imm_neg:$imm)>;
3231 def : ARMPat<(ARMaddc GPR:$src, so_imm_neg:$imm),
3232 (SUBSri GPR:$src, so_imm_neg:$imm)>;
3234 def : ARMPat<(add GPR:$src, imm0_65535_neg:$imm),
3235 (SUBrr GPR:$src, (MOVi16 (imm_neg_XFORM imm:$imm)))>,
3236 Requires<[IsARM, HasV6T2]>;
3237 def : ARMPat<(ARMaddc GPR:$src, imm0_65535_neg:$imm),
3238 (SUBSrr GPR:$src, (MOVi16 (imm_neg_XFORM imm:$imm)))>,
3239 Requires<[IsARM, HasV6T2]>;
3241 // The with-carry-in form matches bitwise not instead of the negation.
3242 // Effectively, the inverse interpretation of the carry flag already accounts
3243 // for part of the negation.
3244 def : ARMPat<(ARMadde GPR:$src, so_imm_not:$imm, CPSR),
3245 (SBCri GPR:$src, so_imm_not:$imm)>;
3246 def : ARMPat<(ARMadde GPR:$src, imm0_65535_neg:$imm, CPSR),
3247 (SBCrr GPR:$src, (MOVi16 (imm_not_XFORM imm:$imm)))>;
3249 // Note: These are implemented in C++ code, because they have to generate
3250 // ADD/SUBrs instructions, which use a complex pattern that a xform function
3252 // (mul X, 2^n+1) -> (add (X << n), X)
3253 // (mul X, 2^n-1) -> (rsb X, (X << n))
3255 // ARM Arithmetic Instruction
3256 // GPR:$dst = GPR:$a op GPR:$b
3257 class AAI<bits<8> op27_20, bits<8> op11_4, string opc,
3258 list<dag> pattern = [],
3259 dag iops = (ins GPRnopc:$Rn, GPRnopc:$Rm),
3260 string asm = "\t$Rd, $Rn, $Rm">
3261 : AI<(outs GPRnopc:$Rd), iops, DPFrm, IIC_iALUr, opc, asm, pattern>,
3262 Sched<[WriteALU, ReadALU, ReadALU]> {
3266 let Inst{27-20} = op27_20;
3267 let Inst{11-4} = op11_4;
3268 let Inst{19-16} = Rn;
3269 let Inst{15-12} = Rd;
3272 let Unpredictable{11-8} = 0b1111;
3275 // Saturating add/subtract
3277 let DecoderMethod = "DecodeQADDInstruction" in
3278 def QADD : AAI<0b00010000, 0b00000101, "qadd",
3279 [(set GPRnopc:$Rd, (int_arm_qadd GPRnopc:$Rm, GPRnopc:$Rn))],
3280 (ins GPRnopc:$Rm, GPRnopc:$Rn), "\t$Rd, $Rm, $Rn">;
3282 def QSUB : AAI<0b00010010, 0b00000101, "qsub",
3283 [(set GPRnopc:$Rd, (int_arm_qsub GPRnopc:$Rm, GPRnopc:$Rn))],
3284 (ins GPRnopc:$Rm, GPRnopc:$Rn), "\t$Rd, $Rm, $Rn">;
3285 def QDADD : AAI<0b00010100, 0b00000101, "qdadd", [],
3286 (ins GPRnopc:$Rm, GPRnopc:$Rn),
3288 def QDSUB : AAI<0b00010110, 0b00000101, "qdsub", [],
3289 (ins GPRnopc:$Rm, GPRnopc:$Rn),
3292 def QADD16 : AAI<0b01100010, 0b11110001, "qadd16">;
3293 def QADD8 : AAI<0b01100010, 0b11111001, "qadd8">;
3294 def QASX : AAI<0b01100010, 0b11110011, "qasx">;
3295 def QSAX : AAI<0b01100010, 0b11110101, "qsax">;
3296 def QSUB16 : AAI<0b01100010, 0b11110111, "qsub16">;
3297 def QSUB8 : AAI<0b01100010, 0b11111111, "qsub8">;
3298 def UQADD16 : AAI<0b01100110, 0b11110001, "uqadd16">;
3299 def UQADD8 : AAI<0b01100110, 0b11111001, "uqadd8">;
3300 def UQASX : AAI<0b01100110, 0b11110011, "uqasx">;
3301 def UQSAX : AAI<0b01100110, 0b11110101, "uqsax">;
3302 def UQSUB16 : AAI<0b01100110, 0b11110111, "uqsub16">;
3303 def UQSUB8 : AAI<0b01100110, 0b11111111, "uqsub8">;
3305 // Signed/Unsigned add/subtract
3307 def SASX : AAI<0b01100001, 0b11110011, "sasx">;
3308 def SADD16 : AAI<0b01100001, 0b11110001, "sadd16">;
3309 def SADD8 : AAI<0b01100001, 0b11111001, "sadd8">;
3310 def SSAX : AAI<0b01100001, 0b11110101, "ssax">;
3311 def SSUB16 : AAI<0b01100001, 0b11110111, "ssub16">;
3312 def SSUB8 : AAI<0b01100001, 0b11111111, "ssub8">;
3313 def UASX : AAI<0b01100101, 0b11110011, "uasx">;
3314 def UADD16 : AAI<0b01100101, 0b11110001, "uadd16">;
3315 def UADD8 : AAI<0b01100101, 0b11111001, "uadd8">;
3316 def USAX : AAI<0b01100101, 0b11110101, "usax">;
3317 def USUB16 : AAI<0b01100101, 0b11110111, "usub16">;
3318 def USUB8 : AAI<0b01100101, 0b11111111, "usub8">;
3320 // Signed/Unsigned halving add/subtract
3322 def SHASX : AAI<0b01100011, 0b11110011, "shasx">;
3323 def SHADD16 : AAI<0b01100011, 0b11110001, "shadd16">;
3324 def SHADD8 : AAI<0b01100011, 0b11111001, "shadd8">;
3325 def SHSAX : AAI<0b01100011, 0b11110101, "shsax">;
3326 def SHSUB16 : AAI<0b01100011, 0b11110111, "shsub16">;
3327 def SHSUB8 : AAI<0b01100011, 0b11111111, "shsub8">;
3328 def UHASX : AAI<0b01100111, 0b11110011, "uhasx">;
3329 def UHADD16 : AAI<0b01100111, 0b11110001, "uhadd16">;
3330 def UHADD8 : AAI<0b01100111, 0b11111001, "uhadd8">;
3331 def UHSAX : AAI<0b01100111, 0b11110101, "uhsax">;
3332 def UHSUB16 : AAI<0b01100111, 0b11110111, "uhsub16">;
3333 def UHSUB8 : AAI<0b01100111, 0b11111111, "uhsub8">;
3335 // Unsigned Sum of Absolute Differences [and Accumulate].
3337 def USAD8 : AI<(outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm),
3338 MulFrm /* for convenience */, NoItinerary, "usad8",
3339 "\t$Rd, $Rn, $Rm", []>,
3340 Requires<[IsARM, HasV6]>, Sched<[WriteALU, ReadALU, ReadALU]> {
3344 let Inst{27-20} = 0b01111000;
3345 let Inst{15-12} = 0b1111;
3346 let Inst{7-4} = 0b0001;
3347 let Inst{19-16} = Rd;
3348 let Inst{11-8} = Rm;
3351 def USADA8 : AI<(outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm, GPR:$Ra),
3352 MulFrm /* for convenience */, NoItinerary, "usada8",
3353 "\t$Rd, $Rn, $Rm, $Ra", []>,
3354 Requires<[IsARM, HasV6]>, Sched<[WriteALU, ReadALU, ReadALU]>{
3359 let Inst{27-20} = 0b01111000;
3360 let Inst{7-4} = 0b0001;
3361 let Inst{19-16} = Rd;
3362 let Inst{15-12} = Ra;
3363 let Inst{11-8} = Rm;
3367 // Signed/Unsigned saturate
3369 def SSAT : AI<(outs GPRnopc:$Rd),
3370 (ins imm1_32:$sat_imm, GPRnopc:$Rn, shift_imm:$sh),
3371 SatFrm, NoItinerary, "ssat", "\t$Rd, $sat_imm, $Rn$sh", []> {
3376 let Inst{27-21} = 0b0110101;
3377 let Inst{5-4} = 0b01;
3378 let Inst{20-16} = sat_imm;
3379 let Inst{15-12} = Rd;
3380 let Inst{11-7} = sh{4-0};
3381 let Inst{6} = sh{5};
3385 def SSAT16 : AI<(outs GPRnopc:$Rd),
3386 (ins imm1_16:$sat_imm, GPRnopc:$Rn), SatFrm,
3387 NoItinerary, "ssat16", "\t$Rd, $sat_imm, $Rn", []> {
3391 let Inst{27-20} = 0b01101010;
3392 let Inst{11-4} = 0b11110011;
3393 let Inst{15-12} = Rd;
3394 let Inst{19-16} = sat_imm;
3398 def USAT : AI<(outs GPRnopc:$Rd),
3399 (ins imm0_31:$sat_imm, GPRnopc:$Rn, shift_imm:$sh),
3400 SatFrm, NoItinerary, "usat", "\t$Rd, $sat_imm, $Rn$sh", []> {
3405 let Inst{27-21} = 0b0110111;
3406 let Inst{5-4} = 0b01;
3407 let Inst{15-12} = Rd;
3408 let Inst{11-7} = sh{4-0};
3409 let Inst{6} = sh{5};
3410 let Inst{20-16} = sat_imm;
3414 def USAT16 : AI<(outs GPRnopc:$Rd),
3415 (ins imm0_15:$sat_imm, GPRnopc:$Rn), SatFrm,
3416 NoItinerary, "usat16", "\t$Rd, $sat_imm, $Rn", []> {
3420 let Inst{27-20} = 0b01101110;
3421 let Inst{11-4} = 0b11110011;
3422 let Inst{15-12} = Rd;
3423 let Inst{19-16} = sat_imm;
3427 def : ARMV6Pat<(int_arm_ssat GPRnopc:$a, imm:$pos),
3428 (SSAT imm:$pos, GPRnopc:$a, 0)>;
3429 def : ARMV6Pat<(int_arm_usat GPRnopc:$a, imm:$pos),
3430 (USAT imm:$pos, GPRnopc:$a, 0)>;
3432 //===----------------------------------------------------------------------===//
3433 // Bitwise Instructions.
3436 defm AND : AsI1_bin_irs<0b0000, "and",
3437 IIC_iBITi, IIC_iBITr, IIC_iBITsr,
3438 BinOpFrag<(and node:$LHS, node:$RHS)>, 1>;
3439 defm ORR : AsI1_bin_irs<0b1100, "orr",
3440 IIC_iBITi, IIC_iBITr, IIC_iBITsr,
3441 BinOpFrag<(or node:$LHS, node:$RHS)>, 1>;
3442 defm EOR : AsI1_bin_irs<0b0001, "eor",
3443 IIC_iBITi, IIC_iBITr, IIC_iBITsr,
3444 BinOpFrag<(xor node:$LHS, node:$RHS)>, 1>;
3445 defm BIC : AsI1_bin_irs<0b1110, "bic",
3446 IIC_iBITi, IIC_iBITr, IIC_iBITsr,
3447 BinOpFrag<(and node:$LHS, (not node:$RHS))>>;
3449 // FIXME: bf_inv_mask_imm should be two operands, the lsb and the msb, just
3450 // like in the actual instruction encoding. The complexity of mapping the mask
3451 // to the lsb/msb pair should be handled by ISel, not encapsulated in the
3452 // instruction description.
3453 def BFC : I<(outs GPR:$Rd), (ins GPR:$src, bf_inv_mask_imm:$imm),
3454 AddrMode1, 4, IndexModeNone, DPFrm, IIC_iUNAsi,
3455 "bfc", "\t$Rd, $imm", "$src = $Rd",
3456 [(set GPR:$Rd, (and GPR:$src, bf_inv_mask_imm:$imm))]>,
3457 Requires<[IsARM, HasV6T2]> {
3460 let Inst{27-21} = 0b0111110;
3461 let Inst{6-0} = 0b0011111;
3462 let Inst{15-12} = Rd;
3463 let Inst{11-7} = imm{4-0}; // lsb
3464 let Inst{20-16} = imm{9-5}; // msb
3467 // A8.6.18 BFI - Bitfield insert (Encoding A1)
3468 def BFI:I<(outs GPRnopc:$Rd), (ins GPRnopc:$src, GPR:$Rn, bf_inv_mask_imm:$imm),
3469 AddrMode1, 4, IndexModeNone, DPFrm, IIC_iUNAsi,
3470 "bfi", "\t$Rd, $Rn, $imm", "$src = $Rd",
3471 [(set GPRnopc:$Rd, (ARMbfi GPRnopc:$src, GPR:$Rn,
3472 bf_inv_mask_imm:$imm))]>,
3473 Requires<[IsARM, HasV6T2]> {
3477 let Inst{27-21} = 0b0111110;
3478 let Inst{6-4} = 0b001; // Rn: Inst{3-0} != 15
3479 let Inst{15-12} = Rd;
3480 let Inst{11-7} = imm{4-0}; // lsb
3481 let Inst{20-16} = imm{9-5}; // width
3485 def MVNr : AsI1<0b1111, (outs GPR:$Rd), (ins GPR:$Rm), DPFrm, IIC_iMVNr,
3486 "mvn", "\t$Rd, $Rm",
3487 [(set GPR:$Rd, (not GPR:$Rm))]>, UnaryDP, Sched<[WriteALU]> {
3491 let Inst{19-16} = 0b0000;
3492 let Inst{11-4} = 0b00000000;
3493 let Inst{15-12} = Rd;
3496 def MVNsi : AsI1<0b1111, (outs GPR:$Rd), (ins so_reg_imm:$shift),
3497 DPSoRegImmFrm, IIC_iMVNsr, "mvn", "\t$Rd, $shift",
3498 [(set GPR:$Rd, (not so_reg_imm:$shift))]>, UnaryDP,
3503 let Inst{19-16} = 0b0000;
3504 let Inst{15-12} = Rd;
3505 let Inst{11-5} = shift{11-5};
3507 let Inst{3-0} = shift{3-0};
3509 def MVNsr : AsI1<0b1111, (outs GPR:$Rd), (ins so_reg_reg:$shift),
3510 DPSoRegRegFrm, IIC_iMVNsr, "mvn", "\t$Rd, $shift",
3511 [(set GPR:$Rd, (not so_reg_reg:$shift))]>, UnaryDP,
3516 let Inst{19-16} = 0b0000;
3517 let Inst{15-12} = Rd;
3518 let Inst{11-8} = shift{11-8};
3520 let Inst{6-5} = shift{6-5};
3522 let Inst{3-0} = shift{3-0};
3524 let isReMaterializable = 1, isAsCheapAsAMove = 1, isMoveImm = 1 in
3525 def MVNi : AsI1<0b1111, (outs GPR:$Rd), (ins so_imm:$imm), DPFrm,
3526 IIC_iMVNi, "mvn", "\t$Rd, $imm",
3527 [(set GPR:$Rd, so_imm_not:$imm)]>,UnaryDP, Sched<[WriteALU]> {
3531 let Inst{19-16} = 0b0000;
3532 let Inst{15-12} = Rd;
3533 let Inst{11-0} = imm;
3536 def : ARMPat<(and GPR:$src, so_imm_not:$imm),
3537 (BICri GPR:$src, so_imm_not:$imm)>;
3539 //===----------------------------------------------------------------------===//
3540 // Multiply Instructions.
3542 class AsMul1I32<bits<7> opcod, dag oops, dag iops, InstrItinClass itin,
3543 string opc, string asm, list<dag> pattern>
3544 : AsMul1I<opcod, oops, iops, itin, opc, asm, pattern> {
3548 let Inst{19-16} = Rd;
3549 let Inst{11-8} = Rm;
3552 class AsMul1I64<bits<7> opcod, dag oops, dag iops, InstrItinClass itin,
3553 string opc, string asm, list<dag> pattern>
3554 : AsMul1I<opcod, oops, iops, itin, opc, asm, pattern> {
3559 let Inst{19-16} = RdHi;
3560 let Inst{15-12} = RdLo;
3561 let Inst{11-8} = Rm;
3564 class AsMla1I64<bits<7> opcod, dag oops, dag iops, InstrItinClass itin,
3565 string opc, string asm, list<dag> pattern>
3566 : AsMul1I<opcod, oops, iops, itin, opc, asm, pattern> {
3571 let Inst{19-16} = RdHi;
3572 let Inst{15-12} = RdLo;
3573 let Inst{11-8} = Rm;
3577 // FIXME: The v5 pseudos are only necessary for the additional Constraint
3578 // property. Remove them when it's possible to add those properties
3579 // on an individual MachineInstr, not just an instruction description.
3580 let isCommutable = 1, TwoOperandAliasConstraint = "$Rn = $Rd" in {
3581 def MUL : AsMul1I32<0b0000000, (outs GPRnopc:$Rd),
3582 (ins GPRnopc:$Rn, GPRnopc:$Rm),
3583 IIC_iMUL32, "mul", "\t$Rd, $Rn, $Rm",
3584 [(set GPRnopc:$Rd, (mul GPRnopc:$Rn, GPRnopc:$Rm))]>,
3585 Requires<[IsARM, HasV6]> {
3586 let Inst{15-12} = 0b0000;
3587 let Unpredictable{15-12} = 0b1111;
3590 let Constraints = "@earlyclobber $Rd" in
3591 def MULv5: ARMPseudoExpand<(outs GPRnopc:$Rd), (ins GPRnopc:$Rn, GPRnopc:$Rm,
3592 pred:$p, cc_out:$s),
3594 [(set GPRnopc:$Rd, (mul GPRnopc:$Rn, GPRnopc:$Rm))],
3595 (MUL GPRnopc:$Rd, GPRnopc:$Rn, GPRnopc:$Rm, pred:$p, cc_out:$s)>,
3596 Requires<[IsARM, NoV6, UseMulOps]>;
3599 def MLA : AsMul1I32<0b0000001, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm, GPR:$Ra),
3600 IIC_iMAC32, "mla", "\t$Rd, $Rn, $Rm, $Ra",
3601 [(set GPR:$Rd, (add (mul GPR:$Rn, GPR:$Rm), GPR:$Ra))]>,
3602 Requires<[IsARM, HasV6, UseMulOps]> {
3604 let Inst{15-12} = Ra;
3607 let Constraints = "@earlyclobber $Rd" in
3608 def MLAv5: ARMPseudoExpand<(outs GPR:$Rd),
3609 (ins GPR:$Rn, GPR:$Rm, GPR:$Ra, pred:$p, cc_out:$s),
3611 [(set GPR:$Rd, (add (mul GPR:$Rn, GPR:$Rm), GPR:$Ra))],
3612 (MLA GPR:$Rd, GPR:$Rn, GPR:$Rm, GPR:$Ra, pred:$p, cc_out:$s)>,
3613 Requires<[IsARM, NoV6]>;
3615 def MLS : AMul1I<0b0000011, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm, GPR:$Ra),
3616 IIC_iMAC32, "mls", "\t$Rd, $Rn, $Rm, $Ra",
3617 [(set GPR:$Rd, (sub GPR:$Ra, (mul GPR:$Rn, GPR:$Rm)))]>,
3618 Requires<[IsARM, HasV6T2, UseMulOps]> {
3623 let Inst{19-16} = Rd;
3624 let Inst{15-12} = Ra;
3625 let Inst{11-8} = Rm;
3629 // Extra precision multiplies with low / high results
3630 let neverHasSideEffects = 1 in {
3631 let isCommutable = 1 in {
3632 def SMULL : AsMul1I64<0b0000110, (outs GPR:$RdLo, GPR:$RdHi),
3633 (ins GPR:$Rn, GPR:$Rm), IIC_iMUL64,
3634 "smull", "\t$RdLo, $RdHi, $Rn, $Rm", []>,
3635 Requires<[IsARM, HasV6]>;
3637 def UMULL : AsMul1I64<0b0000100, (outs GPR:$RdLo, GPR:$RdHi),
3638 (ins GPR:$Rn, GPR:$Rm), IIC_iMUL64,
3639 "umull", "\t$RdLo, $RdHi, $Rn, $Rm", []>,
3640 Requires<[IsARM, HasV6]>;
3642 let Constraints = "@earlyclobber $RdLo,@earlyclobber $RdHi" in {
3643 def SMULLv5 : ARMPseudoExpand<(outs GPR:$RdLo, GPR:$RdHi),
3644 (ins GPR:$Rn, GPR:$Rm, pred:$p, cc_out:$s),
3646 (SMULL GPR:$RdLo, GPR:$RdHi, GPR:$Rn, GPR:$Rm, pred:$p, cc_out:$s)>,
3647 Requires<[IsARM, NoV6]>;
3649 def UMULLv5 : ARMPseudoExpand<(outs GPR:$RdLo, GPR:$RdHi),
3650 (ins GPR:$Rn, GPR:$Rm, pred:$p, cc_out:$s),
3652 (UMULL GPR:$RdLo, GPR:$RdHi, GPR:$Rn, GPR:$Rm, pred:$p, cc_out:$s)>,
3653 Requires<[IsARM, NoV6]>;
3657 // Multiply + accumulate
3658 def SMLAL : AsMla1I64<0b0000111, (outs GPR:$RdLo, GPR:$RdHi),
3659 (ins GPR:$Rn, GPR:$Rm, GPR:$RLo, GPR:$RHi), IIC_iMAC64,
3660 "smlal", "\t$RdLo, $RdHi, $Rn, $Rm", []>,
3661 RegConstraint<"$RLo = $RdLo, $RHi = $RdHi">, Requires<[IsARM, HasV6]>;
3662 def UMLAL : AsMla1I64<0b0000101, (outs GPR:$RdLo, GPR:$RdHi),
3663 (ins GPR:$Rn, GPR:$Rm, GPR:$RLo, GPR:$RHi), IIC_iMAC64,
3664 "umlal", "\t$RdLo, $RdHi, $Rn, $Rm", []>,
3665 RegConstraint<"$RLo = $RdLo, $RHi = $RdHi">, Requires<[IsARM, HasV6]>;
3667 def UMAAL : AMul1I <0b0000010, (outs GPR:$RdLo, GPR:$RdHi),
3668 (ins GPR:$Rn, GPR:$Rm), IIC_iMAC64,
3669 "umaal", "\t$RdLo, $RdHi, $Rn, $Rm", []>,
3670 Requires<[IsARM, HasV6]> {
3675 let Inst{19-16} = RdHi;
3676 let Inst{15-12} = RdLo;
3677 let Inst{11-8} = Rm;
3681 let Constraints = "$RLo = $RdLo,$RHi = $RdHi" in {
3682 def SMLALv5 : ARMPseudoExpand<(outs GPR:$RdLo, GPR:$RdHi),
3683 (ins GPR:$Rn, GPR:$Rm, GPR:$RLo, GPR:$RHi, pred:$p, cc_out:$s),
3685 (SMLAL GPR:$RdLo, GPR:$RdHi, GPR:$Rn, GPR:$Rm, GPR:$RLo, GPR:$RHi,
3686 pred:$p, cc_out:$s)>,
3687 Requires<[IsARM, NoV6]>;
3688 def UMLALv5 : ARMPseudoExpand<(outs GPR:$RdLo, GPR:$RdHi),
3689 (ins GPR:$Rn, GPR:$Rm, GPR:$RLo, GPR:$RHi, pred:$p, cc_out:$s),
3691 (UMLAL GPR:$RdLo, GPR:$RdHi, GPR:$Rn, GPR:$Rm, GPR:$RLo, GPR:$RHi,
3692 pred:$p, cc_out:$s)>,
3693 Requires<[IsARM, NoV6]>;
3696 let Constraints = "@earlyclobber $RdLo,@earlyclobber $RdHi" in {
3697 def UMAALv5 : ARMPseudoExpand<(outs GPR:$RdLo, GPR:$RdHi),
3698 (ins GPR:$Rn, GPR:$Rm, pred:$p),
3700 (UMAAL GPR:$RdLo, GPR:$RdHi, GPR:$Rn, GPR:$Rm, pred:$p)>,
3701 Requires<[IsARM, NoV6]>;
3704 } // neverHasSideEffects
3706 // Most significant word multiply
3707 def SMMUL : AMul2I <0b0111010, 0b0001, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm),
3708 IIC_iMUL32, "smmul", "\t$Rd, $Rn, $Rm",
3709 [(set GPR:$Rd, (mulhs GPR:$Rn, GPR:$Rm))]>,
3710 Requires<[IsARM, HasV6]> {
3711 let Inst{15-12} = 0b1111;
3714 def SMMULR : AMul2I <0b0111010, 0b0011, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm),
3715 IIC_iMUL32, "smmulr", "\t$Rd, $Rn, $Rm", []>,
3716 Requires<[IsARM, HasV6]> {
3717 let Inst{15-12} = 0b1111;
3720 def SMMLA : AMul2Ia <0b0111010, 0b0001, (outs GPR:$Rd),
3721 (ins GPR:$Rn, GPR:$Rm, GPR:$Ra),
3722 IIC_iMAC32, "smmla", "\t$Rd, $Rn, $Rm, $Ra",
3723 [(set GPR:$Rd, (add (mulhs GPR:$Rn, GPR:$Rm), GPR:$Ra))]>,
3724 Requires<[IsARM, HasV6, UseMulOps]>;
3726 def SMMLAR : AMul2Ia <0b0111010, 0b0011, (outs GPR:$Rd),
3727 (ins GPR:$Rn, GPR:$Rm, GPR:$Ra),
3728 IIC_iMAC32, "smmlar", "\t$Rd, $Rn, $Rm, $Ra", []>,
3729 Requires<[IsARM, HasV6]>;
3731 def SMMLS : AMul2Ia <0b0111010, 0b1101, (outs GPR:$Rd),
3732 (ins GPR:$Rn, GPR:$Rm, GPR:$Ra),
3733 IIC_iMAC32, "smmls", "\t$Rd, $Rn, $Rm, $Ra", []>,
3734 Requires<[IsARM, HasV6, UseMulOps]>;
3736 def SMMLSR : AMul2Ia <0b0111010, 0b1111, (outs GPR:$Rd),
3737 (ins GPR:$Rn, GPR:$Rm, GPR:$Ra),
3738 IIC_iMAC32, "smmlsr", "\t$Rd, $Rn, $Rm, $Ra", []>,
3739 Requires<[IsARM, HasV6]>;
3741 multiclass AI_smul<string opc, PatFrag opnode> {
3742 def BB : AMulxyI<0b0001011, 0b00, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm),
3743 IIC_iMUL16, !strconcat(opc, "bb"), "\t$Rd, $Rn, $Rm",
3744 [(set GPR:$Rd, (opnode (sext_inreg GPR:$Rn, i16),
3745 (sext_inreg GPR:$Rm, i16)))]>,
3746 Requires<[IsARM, HasV5TE]>;
3748 def BT : AMulxyI<0b0001011, 0b10, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm),
3749 IIC_iMUL16, !strconcat(opc, "bt"), "\t$Rd, $Rn, $Rm",
3750 [(set GPR:$Rd, (opnode (sext_inreg GPR:$Rn, i16),
3751 (sra GPR:$Rm, (i32 16))))]>,
3752 Requires<[IsARM, HasV5TE]>;
3754 def TB : AMulxyI<0b0001011, 0b01, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm),
3755 IIC_iMUL16, !strconcat(opc, "tb"), "\t$Rd, $Rn, $Rm",
3756 [(set GPR:$Rd, (opnode (sra GPR:$Rn, (i32 16)),
3757 (sext_inreg GPR:$Rm, i16)))]>,
3758 Requires<[IsARM, HasV5TE]>;
3760 def TT : AMulxyI<0b0001011, 0b11, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm),
3761 IIC_iMUL16, !strconcat(opc, "tt"), "\t$Rd, $Rn, $Rm",
3762 [(set GPR:$Rd, (opnode (sra GPR:$Rn, (i32 16)),
3763 (sra GPR:$Rm, (i32 16))))]>,
3764 Requires<[IsARM, HasV5TE]>;
3766 def WB : AMulxyI<0b0001001, 0b01, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm),
3767 IIC_iMUL16, !strconcat(opc, "wb"), "\t$Rd, $Rn, $Rm",
3768 [(set GPR:$Rd, (sra (opnode GPR:$Rn,
3769 (sext_inreg GPR:$Rm, i16)), (i32 16)))]>,
3770 Requires<[IsARM, HasV5TE]>;
3772 def WT : AMulxyI<0b0001001, 0b11, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm),
3773 IIC_iMUL16, !strconcat(opc, "wt"), "\t$Rd, $Rn, $Rm",
3774 [(set GPR:$Rd, (sra (opnode GPR:$Rn,
3775 (sra GPR:$Rm, (i32 16))), (i32 16)))]>,
3776 Requires<[IsARM, HasV5TE]>;
3780 multiclass AI_smla<string opc, PatFrag opnode> {
3781 let DecoderMethod = "DecodeSMLAInstruction" in {
3782 def BB : AMulxyIa<0b0001000, 0b00, (outs GPRnopc:$Rd),
3783 (ins GPRnopc:$Rn, GPRnopc:$Rm, GPR:$Ra),
3784 IIC_iMAC16, !strconcat(opc, "bb"), "\t$Rd, $Rn, $Rm, $Ra",
3785 [(set GPRnopc:$Rd, (add GPR:$Ra,
3786 (opnode (sext_inreg GPRnopc:$Rn, i16),
3787 (sext_inreg GPRnopc:$Rm, i16))))]>,
3788 Requires<[IsARM, HasV5TE, UseMulOps]>;
3790 def BT : AMulxyIa<0b0001000, 0b10, (outs GPRnopc:$Rd),
3791 (ins GPRnopc:$Rn, GPRnopc:$Rm, GPR:$Ra),
3792 IIC_iMAC16, !strconcat(opc, "bt"), "\t$Rd, $Rn, $Rm, $Ra",
3794 (add GPR:$Ra, (opnode (sext_inreg GPRnopc:$Rn, i16),
3795 (sra GPRnopc:$Rm, (i32 16)))))]>,
3796 Requires<[IsARM, HasV5TE, UseMulOps]>;
3798 def TB : AMulxyIa<0b0001000, 0b01, (outs GPRnopc:$Rd),
3799 (ins GPRnopc:$Rn, GPRnopc:$Rm, GPR:$Ra),
3800 IIC_iMAC16, !strconcat(opc, "tb"), "\t$Rd, $Rn, $Rm, $Ra",
3802 (add GPR:$Ra, (opnode (sra GPRnopc:$Rn, (i32 16)),
3803 (sext_inreg GPRnopc:$Rm, i16))))]>,
3804 Requires<[IsARM, HasV5TE, UseMulOps]>;
3806 def TT : AMulxyIa<0b0001000, 0b11, (outs GPRnopc:$Rd),
3807 (ins GPRnopc:$Rn, GPRnopc:$Rm, GPR:$Ra),
3808 IIC_iMAC16, !strconcat(opc, "tt"), "\t$Rd, $Rn, $Rm, $Ra",
3810 (add GPR:$Ra, (opnode (sra GPRnopc:$Rn, (i32 16)),
3811 (sra GPRnopc:$Rm, (i32 16)))))]>,
3812 Requires<[IsARM, HasV5TE, UseMulOps]>;
3814 def WB : AMulxyIa<0b0001001, 0b00, (outs GPRnopc:$Rd),
3815 (ins GPRnopc:$Rn, GPRnopc:$Rm, GPR:$Ra),
3816 IIC_iMAC16, !strconcat(opc, "wb"), "\t$Rd, $Rn, $Rm, $Ra",
3818 (add GPR:$Ra, (sra (opnode GPRnopc:$Rn,
3819 (sext_inreg GPRnopc:$Rm, i16)), (i32 16))))]>,
3820 Requires<[IsARM, HasV5TE, UseMulOps]>;
3822 def WT : AMulxyIa<0b0001001, 0b10, (outs GPRnopc:$Rd),
3823 (ins GPRnopc:$Rn, GPRnopc:$Rm, GPR:$Ra),
3824 IIC_iMAC16, !strconcat(opc, "wt"), "\t$Rd, $Rn, $Rm, $Ra",
3826 (add GPR:$Ra, (sra (opnode GPRnopc:$Rn,
3827 (sra GPRnopc:$Rm, (i32 16))), (i32 16))))]>,
3828 Requires<[IsARM, HasV5TE, UseMulOps]>;
3832 defm SMUL : AI_smul<"smul", BinOpFrag<(mul node:$LHS, node:$RHS)>>;
3833 defm SMLA : AI_smla<"smla", BinOpFrag<(mul node:$LHS, node:$RHS)>>;
3835 // Halfword multiply accumulate long: SMLAL<x><y>.
3836 def SMLALBB : AMulxyI64<0b0001010, 0b00, (outs GPRnopc:$RdLo, GPRnopc:$RdHi),
3837 (ins GPRnopc:$Rn, GPRnopc:$Rm),
3838 IIC_iMAC64, "smlalbb", "\t$RdLo, $RdHi, $Rn, $Rm", []>,
3839 Requires<[IsARM, HasV5TE]>;
3841 def SMLALBT : AMulxyI64<0b0001010, 0b10, (outs GPRnopc:$RdLo, GPRnopc:$RdHi),
3842 (ins GPRnopc:$Rn, GPRnopc:$Rm),
3843 IIC_iMAC64, "smlalbt", "\t$RdLo, $RdHi, $Rn, $Rm", []>,
3844 Requires<[IsARM, HasV5TE]>;
3846 def SMLALTB : AMulxyI64<0b0001010, 0b01, (outs GPRnopc:$RdLo, GPRnopc:$RdHi),
3847 (ins GPRnopc:$Rn, GPRnopc:$Rm),
3848 IIC_iMAC64, "smlaltb", "\t$RdLo, $RdHi, $Rn, $Rm", []>,
3849 Requires<[IsARM, HasV5TE]>;
3851 def SMLALTT : AMulxyI64<0b0001010, 0b11, (outs GPRnopc:$RdLo, GPRnopc:$RdHi),
3852 (ins GPRnopc:$Rn, GPRnopc:$Rm),
3853 IIC_iMAC64, "smlaltt", "\t$RdLo, $RdHi, $Rn, $Rm", []>,
3854 Requires<[IsARM, HasV5TE]>;
3856 // Helper class for AI_smld.
3857 class AMulDualIbase<bit long, bit sub, bit swap, dag oops, dag iops,
3858 InstrItinClass itin, string opc, string asm>
3859 : AI<oops, iops, MulFrm, itin, opc, asm, []>, Requires<[IsARM, HasV6]> {
3862 let Inst{27-23} = 0b01110;
3863 let Inst{22} = long;
3864 let Inst{21-20} = 0b00;
3865 let Inst{11-8} = Rm;
3872 class AMulDualI<bit long, bit sub, bit swap, dag oops, dag iops,
3873 InstrItinClass itin, string opc, string asm>
3874 : AMulDualIbase<long, sub, swap, oops, iops, itin, opc, asm> {
3876 let Inst{15-12} = 0b1111;
3877 let Inst{19-16} = Rd;
3879 class AMulDualIa<bit long, bit sub, bit swap, dag oops, dag iops,
3880 InstrItinClass itin, string opc, string asm>
3881 : AMulDualIbase<long, sub, swap, oops, iops, itin, opc, asm> {
3884 let Inst{19-16} = Rd;
3885 let Inst{15-12} = Ra;
3887 class AMulDualI64<bit long, bit sub, bit swap, dag oops, dag iops,
3888 InstrItinClass itin, string opc, string asm>
3889 : AMulDualIbase<long, sub, swap, oops, iops, itin, opc, asm> {
3892 let Inst{19-16} = RdHi;
3893 let Inst{15-12} = RdLo;
3896 multiclass AI_smld<bit sub, string opc> {
3898 def D : AMulDualIa<0, sub, 0, (outs GPRnopc:$Rd),
3899 (ins GPRnopc:$Rn, GPRnopc:$Rm, GPR:$Ra),
3900 NoItinerary, !strconcat(opc, "d"), "\t$Rd, $Rn, $Rm, $Ra">;
3902 def DX: AMulDualIa<0, sub, 1, (outs GPRnopc:$Rd),
3903 (ins GPRnopc:$Rn, GPRnopc:$Rm, GPR:$Ra),
3904 NoItinerary, !strconcat(opc, "dx"), "\t$Rd, $Rn, $Rm, $Ra">;
3906 def LD: AMulDualI64<1, sub, 0, (outs GPRnopc:$RdLo, GPRnopc:$RdHi),
3907 (ins GPRnopc:$Rn, GPRnopc:$Rm), NoItinerary,
3908 !strconcat(opc, "ld"), "\t$RdLo, $RdHi, $Rn, $Rm">;
3910 def LDX : AMulDualI64<1, sub, 1, (outs GPRnopc:$RdLo, GPRnopc:$RdHi),
3911 (ins GPRnopc:$Rn, GPRnopc:$Rm), NoItinerary,
3912 !strconcat(opc, "ldx"),"\t$RdLo, $RdHi, $Rn, $Rm">;
3916 defm SMLA : AI_smld<0, "smla">;
3917 defm SMLS : AI_smld<1, "smls">;
3919 multiclass AI_sdml<bit sub, string opc> {
3921 def D:AMulDualI<0, sub, 0, (outs GPRnopc:$Rd), (ins GPRnopc:$Rn, GPRnopc:$Rm),
3922 NoItinerary, !strconcat(opc, "d"), "\t$Rd, $Rn, $Rm">;
3923 def DX:AMulDualI<0, sub, 1, (outs GPRnopc:$Rd),(ins GPRnopc:$Rn, GPRnopc:$Rm),
3924 NoItinerary, !strconcat(opc, "dx"), "\t$Rd, $Rn, $Rm">;
3927 defm SMUA : AI_sdml<0, "smua">;
3928 defm SMUS : AI_sdml<1, "smus">;
3930 //===----------------------------------------------------------------------===//
3931 // Division Instructions (ARMv7-A with virtualization extension)
3933 def SDIV : ADivA1I<0b001, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm), IIC_iDIV,
3934 "sdiv", "\t$Rd, $Rn, $Rm",
3935 [(set GPR:$Rd, (sdiv GPR:$Rn, GPR:$Rm))]>,
3936 Requires<[IsARM, HasDivideInARM]>;
3938 def UDIV : ADivA1I<0b011, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm), IIC_iDIV,
3939 "udiv", "\t$Rd, $Rn, $Rm",
3940 [(set GPR:$Rd, (udiv GPR:$Rn, GPR:$Rm))]>,
3941 Requires<[IsARM, HasDivideInARM]>;
3943 //===----------------------------------------------------------------------===//
3944 // Misc. Arithmetic Instructions.
3947 def CLZ : AMiscA1I<0b000010110, 0b0001, (outs GPR:$Rd), (ins GPR:$Rm),
3948 IIC_iUNAr, "clz", "\t$Rd, $Rm",
3949 [(set GPR:$Rd, (ctlz GPR:$Rm))]>, Requires<[IsARM, HasV5T]>,
3952 def RBIT : AMiscA1I<0b01101111, 0b0011, (outs GPR:$Rd), (ins GPR:$Rm),
3953 IIC_iUNAr, "rbit", "\t$Rd, $Rm",
3954 [(set GPR:$Rd, (ARMrbit GPR:$Rm))]>,
3955 Requires<[IsARM, HasV6T2]>,
3958 def REV : AMiscA1I<0b01101011, 0b0011, (outs GPR:$Rd), (ins GPR:$Rm),
3959 IIC_iUNAr, "rev", "\t$Rd, $Rm",
3960 [(set GPR:$Rd, (bswap GPR:$Rm))]>, Requires<[IsARM, HasV6]>,
3963 let AddedComplexity = 5 in
3964 def REV16 : AMiscA1I<0b01101011, 0b1011, (outs GPR:$Rd), (ins GPR:$Rm),
3965 IIC_iUNAr, "rev16", "\t$Rd, $Rm",
3966 [(set GPR:$Rd, (rotr (bswap GPR:$Rm), (i32 16)))]>,
3967 Requires<[IsARM, HasV6]>,
3970 let AddedComplexity = 5 in
3971 def REVSH : AMiscA1I<0b01101111, 0b1011, (outs GPR:$Rd), (ins GPR:$Rm),
3972 IIC_iUNAr, "revsh", "\t$Rd, $Rm",
3973 [(set GPR:$Rd, (sra (bswap GPR:$Rm), (i32 16)))]>,
3974 Requires<[IsARM, HasV6]>,
3977 def : ARMV6Pat<(or (sra (shl GPR:$Rm, (i32 24)), (i32 16)),
3978 (and (srl GPR:$Rm, (i32 8)), 0xFF)),
3981 def PKHBT : APKHI<0b01101000, 0, (outs GPRnopc:$Rd),
3982 (ins GPRnopc:$Rn, GPRnopc:$Rm, pkh_lsl_amt:$sh),
3983 IIC_iALUsi, "pkhbt", "\t$Rd, $Rn, $Rm$sh",
3984 [(set GPRnopc:$Rd, (or (and GPRnopc:$Rn, 0xFFFF),
3985 (and (shl GPRnopc:$Rm, pkh_lsl_amt:$sh),
3987 Requires<[IsARM, HasV6]>,
3988 Sched<[WriteALUsi, ReadALU]>;
3990 // Alternate cases for PKHBT where identities eliminate some nodes.
3991 def : ARMV6Pat<(or (and GPRnopc:$Rn, 0xFFFF), (and GPRnopc:$Rm, 0xFFFF0000)),
3992 (PKHBT GPRnopc:$Rn, GPRnopc:$Rm, 0)>;
3993 def : ARMV6Pat<(or (and GPRnopc:$Rn, 0xFFFF), (shl GPRnopc:$Rm, imm16_31:$sh)),
3994 (PKHBT GPRnopc:$Rn, GPRnopc:$Rm, imm16_31:$sh)>;
3996 // Note: Shifts of 1-15 bits will be transformed to srl instead of sra and
3997 // will match the pattern below.
3998 def PKHTB : APKHI<0b01101000, 1, (outs GPRnopc:$Rd),
3999 (ins GPRnopc:$Rn, GPRnopc:$Rm, pkh_asr_amt:$sh),
4000 IIC_iBITsi, "pkhtb", "\t$Rd, $Rn, $Rm$sh",
4001 [(set GPRnopc:$Rd, (or (and GPRnopc:$Rn, 0xFFFF0000),
4002 (and (sra GPRnopc:$Rm, pkh_asr_amt:$sh),
4004 Requires<[IsARM, HasV6]>,
4005 Sched<[WriteALUsi, ReadALU]>;
4007 // Alternate cases for PKHTB where identities eliminate some nodes. Note that
4008 // a shift amount of 0 is *not legal* here, it is PKHBT instead.
4009 def : ARMV6Pat<(or (and GPRnopc:$src1, 0xFFFF0000),
4010 (srl GPRnopc:$src2, imm16_31:$sh)),
4011 (PKHTB GPRnopc:$src1, GPRnopc:$src2, imm16_31:$sh)>;
4012 def : ARMV6Pat<(or (and GPRnopc:$src1, 0xFFFF0000),
4013 (and (srl GPRnopc:$src2, imm1_15:$sh), 0xFFFF)),
4014 (PKHTB GPRnopc:$src1, GPRnopc:$src2, imm1_15:$sh)>;
4016 //===----------------------------------------------------------------------===//
4017 // Comparison Instructions...
4020 defm CMP : AI1_cmp_irs<0b1010, "cmp",
4021 IIC_iCMPi, IIC_iCMPr, IIC_iCMPsr,
4022 BinOpFrag<(ARMcmp node:$LHS, node:$RHS)>>;
4024 // ARMcmpZ can re-use the above instruction definitions.
4025 def : ARMPat<(ARMcmpZ GPR:$src, so_imm:$imm),
4026 (CMPri GPR:$src, so_imm:$imm)>;
4027 def : ARMPat<(ARMcmpZ GPR:$src, GPR:$rhs),
4028 (CMPrr GPR:$src, GPR:$rhs)>;
4029 def : ARMPat<(ARMcmpZ GPR:$src, so_reg_imm:$rhs),
4030 (CMPrsi GPR:$src, so_reg_imm:$rhs)>;
4031 def : ARMPat<(ARMcmpZ GPR:$src, so_reg_reg:$rhs),
4032 (CMPrsr GPR:$src, so_reg_reg:$rhs)>;
4034 // CMN register-integer
4035 let isCompare = 1, Defs = [CPSR] in {
4036 def CMNri : AI1<0b1011, (outs), (ins GPR:$Rn, so_imm:$imm), DPFrm, IIC_iCMPi,
4037 "cmn", "\t$Rn, $imm",
4038 [(ARMcmn GPR:$Rn, so_imm:$imm)]>,
4039 Sched<[WriteCMP, ReadALU]> {
4044 let Inst{19-16} = Rn;
4045 let Inst{15-12} = 0b0000;
4046 let Inst{11-0} = imm;
4048 let Unpredictable{15-12} = 0b1111;
4051 // CMN register-register/shift
4052 def CMNzrr : AI1<0b1011, (outs), (ins GPR:$Rn, GPR:$Rm), DPFrm, IIC_iCMPr,
4053 "cmn", "\t$Rn, $Rm",
4054 [(BinOpFrag<(ARMcmpZ node:$LHS,(ineg node:$RHS))>
4055 GPR:$Rn, GPR:$Rm)]>, Sched<[WriteCMP, ReadALU, ReadALU]> {
4058 let isCommutable = 1;
4061 let Inst{19-16} = Rn;
4062 let Inst{15-12} = 0b0000;
4063 let Inst{11-4} = 0b00000000;
4066 let Unpredictable{15-12} = 0b1111;
4069 def CMNzrsi : AI1<0b1011, (outs),
4070 (ins GPR:$Rn, so_reg_imm:$shift), DPSoRegImmFrm, IIC_iCMPsr,
4071 "cmn", "\t$Rn, $shift",
4072 [(BinOpFrag<(ARMcmpZ node:$LHS,(ineg node:$RHS))>
4073 GPR:$Rn, so_reg_imm:$shift)]>,
4074 Sched<[WriteCMPsi, ReadALU]> {
4079 let Inst{19-16} = Rn;
4080 let Inst{15-12} = 0b0000;
4081 let Inst{11-5} = shift{11-5};
4083 let Inst{3-0} = shift{3-0};
4085 let Unpredictable{15-12} = 0b1111;
4088 def CMNzrsr : AI1<0b1011, (outs),
4089 (ins GPRnopc:$Rn, so_reg_reg:$shift), DPSoRegRegFrm, IIC_iCMPsr,
4090 "cmn", "\t$Rn, $shift",
4091 [(BinOpFrag<(ARMcmpZ node:$LHS,(ineg node:$RHS))>
4092 GPRnopc:$Rn, so_reg_reg:$shift)]>,
4093 Sched<[WriteCMPsr, ReadALU]> {
4098 let Inst{19-16} = Rn;
4099 let Inst{15-12} = 0b0000;
4100 let Inst{11-8} = shift{11-8};
4102 let Inst{6-5} = shift{6-5};
4104 let Inst{3-0} = shift{3-0};
4106 let Unpredictable{15-12} = 0b1111;
4111 def : ARMPat<(ARMcmp GPR:$src, so_imm_neg:$imm),
4112 (CMNri GPR:$src, so_imm_neg:$imm)>;
4114 def : ARMPat<(ARMcmpZ GPR:$src, so_imm_neg:$imm),
4115 (CMNri GPR:$src, so_imm_neg:$imm)>;
4117 // Note that TST/TEQ don't set all the same flags that CMP does!
4118 defm TST : AI1_cmp_irs<0b1000, "tst",
4119 IIC_iTSTi, IIC_iTSTr, IIC_iTSTsr,
4120 BinOpFrag<(ARMcmpZ (and_su node:$LHS, node:$RHS), 0)>, 1>;
4121 defm TEQ : AI1_cmp_irs<0b1001, "teq",
4122 IIC_iTSTi, IIC_iTSTr, IIC_iTSTsr,
4123 BinOpFrag<(ARMcmpZ (xor_su node:$LHS, node:$RHS), 0)>, 1>;
4125 // Pseudo i64 compares for some floating point compares.
4126 let usesCustomInserter = 1, isBranch = 1, isTerminator = 1,
4128 def BCCi64 : PseudoInst<(outs),
4129 (ins i32imm:$cc, GPR:$lhs1, GPR:$lhs2, GPR:$rhs1, GPR:$rhs2, brtarget:$dst),
4131 [(ARMBcci64 imm:$cc, GPR:$lhs1, GPR:$lhs2, GPR:$rhs1, GPR:$rhs2, bb:$dst)]>,
4134 def BCCZi64 : PseudoInst<(outs),
4135 (ins i32imm:$cc, GPR:$lhs1, GPR:$lhs2, brtarget:$dst), IIC_Br,
4136 [(ARMBcci64 imm:$cc, GPR:$lhs1, GPR:$lhs2, 0, 0, bb:$dst)]>,
4138 } // usesCustomInserter
4141 // Conditional moves
4142 // FIXME: should be able to write a pattern for ARMcmov, but can't use
4143 // a two-value operand where a dag node expects two operands. :(
4144 let neverHasSideEffects = 1 in {
4146 let isCommutable = 1, isSelect = 1 in
4147 def MOVCCr : ARMPseudoInst<(outs GPR:$Rd), (ins GPR:$false, GPR:$Rm, pred:$p),
4149 [/*(set GPR:$Rd, (ARMcmov GPR:$false, GPR:$Rm, imm:$cc, CCR:$ccr))*/]>,
4150 RegConstraint<"$false = $Rd">, Sched<[WriteALU]>;
4152 def MOVCCsi : ARMPseudoInst<(outs GPR:$Rd),
4153 (ins GPR:$false, so_reg_imm:$shift, pred:$p),
4155 [/*(set GPR:$Rd, (ARMcmov GPR:$false, so_reg_imm:$shift,
4156 imm:$cc, CCR:$ccr))*/]>,
4157 RegConstraint<"$false = $Rd">, Sched<[WriteALU]>;
4158 def MOVCCsr : ARMPseudoInst<(outs GPR:$Rd),
4159 (ins GPR:$false, so_reg_reg:$shift, pred:$p),
4161 [/*(set GPR:$Rd, (ARMcmov GPR:$false, so_reg_reg:$shift,
4162 imm:$cc, CCR:$ccr))*/]>,
4163 RegConstraint<"$false = $Rd">, Sched<[WriteALU]>;
4166 let isMoveImm = 1 in
4167 def MOVCCi16 : ARMPseudoInst<(outs GPR:$Rd),
4168 (ins GPR:$false, imm0_65535_expr:$imm, pred:$p),
4171 RegConstraint<"$false = $Rd">, Requires<[IsARM, HasV6T2]>,
4174 let isMoveImm = 1 in
4175 def MOVCCi : ARMPseudoInst<(outs GPR:$Rd),
4176 (ins GPR:$false, so_imm:$imm, pred:$p),
4178 [/*(set GPR:$Rd, (ARMcmov GPR:$false, so_imm:$imm, imm:$cc, CCR:$ccr))*/]>,
4179 RegConstraint<"$false = $Rd">, Sched<[WriteALU]>;
4181 // Two instruction predicate mov immediate.
4182 let isMoveImm = 1 in
4183 def MOVCCi32imm : ARMPseudoInst<(outs GPR:$Rd),
4184 (ins GPR:$false, i32imm:$src, pred:$p),
4185 8, IIC_iCMOVix2, []>, RegConstraint<"$false = $Rd">;
4187 let isMoveImm = 1 in
4188 def MVNCCi : ARMPseudoInst<(outs GPR:$Rd),
4189 (ins GPR:$false, so_imm:$imm, pred:$p),
4191 [/*(set GPR:$Rd, (ARMcmov GPR:$false, so_imm_not:$imm, imm:$cc, CCR:$ccr))*/]>,
4192 RegConstraint<"$false = $Rd">, Sched<[WriteALU]>;
4194 } // neverHasSideEffects
4197 //===----------------------------------------------------------------------===//
4198 // Atomic operations intrinsics
4201 def MemBarrierOptOperand : AsmOperandClass {
4202 let Name = "MemBarrierOpt";
4203 let ParserMethod = "parseMemBarrierOptOperand";
4205 def memb_opt : Operand<i32> {
4206 let PrintMethod = "printMemBOption";
4207 let ParserMatchClass = MemBarrierOptOperand;
4208 let DecoderMethod = "DecodeMemBarrierOption";
4211 def InstSyncBarrierOptOperand : AsmOperandClass {
4212 let Name = "InstSyncBarrierOpt";
4213 let ParserMethod = "parseInstSyncBarrierOptOperand";
4215 def instsyncb_opt : Operand<i32> {
4216 let PrintMethod = "printInstSyncBOption";
4217 let ParserMatchClass = InstSyncBarrierOptOperand;
4218 let DecoderMethod = "DecodeInstSyncBarrierOption";
4221 // memory barriers protect the atomic sequences
4222 let hasSideEffects = 1 in {
4223 def DMB : AInoP<(outs), (ins memb_opt:$opt), MiscFrm, NoItinerary,
4224 "dmb", "\t$opt", [(ARMMemBarrier (i32 imm:$opt))]>,
4225 Requires<[IsARM, HasDB]> {
4227 let Inst{31-4} = 0xf57ff05;
4228 let Inst{3-0} = opt;
4232 def DSB : AInoP<(outs), (ins memb_opt:$opt), MiscFrm, NoItinerary,
4233 "dsb", "\t$opt", []>,
4234 Requires<[IsARM, HasDB]> {
4236 let Inst{31-4} = 0xf57ff04;
4237 let Inst{3-0} = opt;
4240 // ISB has only full system option
4241 def ISB : AInoP<(outs), (ins instsyncb_opt:$opt), MiscFrm, NoItinerary,
4242 "isb", "\t$opt", []>,
4243 Requires<[IsARM, HasDB]> {
4245 let Inst{31-4} = 0xf57ff06;
4246 let Inst{3-0} = opt;
4249 // Pseudo instruction that combines movs + predicated rsbmi
4250 // to implement integer ABS
4251 let usesCustomInserter = 1, Defs = [CPSR] in
4252 def ABS : ARMPseudoInst<(outs GPR:$dst), (ins GPR:$src), 8, NoItinerary, []>;
4254 let usesCustomInserter = 1 in {
4255 let Defs = [CPSR] in {
4256 def ATOMIC_LOAD_ADD_I8 : PseudoInst<
4257 (outs GPR:$dst), (ins GPR:$ptr, GPR:$incr), NoItinerary,
4258 [(set GPR:$dst, (atomic_load_add_8 GPR:$ptr, GPR:$incr))]>;
4259 def ATOMIC_LOAD_SUB_I8 : PseudoInst<
4260 (outs GPR:$dst), (ins GPR:$ptr, GPR:$incr), NoItinerary,
4261 [(set GPR:$dst, (atomic_load_sub_8 GPR:$ptr, GPR:$incr))]>;
4262 def ATOMIC_LOAD_AND_I8 : PseudoInst<
4263 (outs GPR:$dst), (ins GPR:$ptr, GPR:$incr), NoItinerary,
4264 [(set GPR:$dst, (atomic_load_and_8 GPR:$ptr, GPR:$incr))]>;
4265 def ATOMIC_LOAD_OR_I8 : PseudoInst<
4266 (outs GPR:$dst), (ins GPR:$ptr, GPR:$incr), NoItinerary,
4267 [(set GPR:$dst, (atomic_load_or_8 GPR:$ptr, GPR:$incr))]>;
4268 def ATOMIC_LOAD_XOR_I8 : PseudoInst<
4269 (outs GPR:$dst), (ins GPR:$ptr, GPR:$incr), NoItinerary,
4270 [(set GPR:$dst, (atomic_load_xor_8 GPR:$ptr, GPR:$incr))]>;
4271 def ATOMIC_LOAD_NAND_I8 : PseudoInst<
4272 (outs GPR:$dst), (ins GPR:$ptr, GPR:$incr), NoItinerary,
4273 [(set GPR:$dst, (atomic_load_nand_8 GPR:$ptr, GPR:$incr))]>;
4274 def ATOMIC_LOAD_MIN_I8 : PseudoInst<
4275 (outs GPR:$dst), (ins GPR:$ptr, GPR:$val), NoItinerary,
4276 [(set GPR:$dst, (atomic_load_min_8 GPR:$ptr, GPR:$val))]>;
4277 def ATOMIC_LOAD_MAX_I8 : PseudoInst<
4278 (outs GPR:$dst), (ins GPR:$ptr, GPR:$val), NoItinerary,
4279 [(set GPR:$dst, (atomic_load_max_8 GPR:$ptr, GPR:$val))]>;
4280 def ATOMIC_LOAD_UMIN_I8 : PseudoInst<
4281 (outs GPR:$dst), (ins GPR:$ptr, GPR:$val), NoItinerary,
4282 [(set GPR:$dst, (atomic_load_umin_8 GPR:$ptr, GPR:$val))]>;
4283 def ATOMIC_LOAD_UMAX_I8 : PseudoInst<
4284 (outs GPR:$dst), (ins GPR:$ptr, GPR:$val), NoItinerary,
4285 [(set GPR:$dst, (atomic_load_umax_8 GPR:$ptr, GPR:$val))]>;
4286 def ATOMIC_LOAD_ADD_I16 : PseudoInst<
4287 (outs GPR:$dst), (ins GPR:$ptr, GPR:$incr), NoItinerary,
4288 [(set GPR:$dst, (atomic_load_add_16 GPR:$ptr, GPR:$incr))]>;
4289 def ATOMIC_LOAD_SUB_I16 : PseudoInst<
4290 (outs GPR:$dst), (ins GPR:$ptr, GPR:$incr), NoItinerary,
4291 [(set GPR:$dst, (atomic_load_sub_16 GPR:$ptr, GPR:$incr))]>;
4292 def ATOMIC_LOAD_AND_I16 : PseudoInst<
4293 (outs GPR:$dst), (ins GPR:$ptr, GPR:$incr), NoItinerary,
4294 [(set GPR:$dst, (atomic_load_and_16 GPR:$ptr, GPR:$incr))]>;
4295 def ATOMIC_LOAD_OR_I16 : PseudoInst<
4296 (outs GPR:$dst), (ins GPR:$ptr, GPR:$incr), NoItinerary,
4297 [(set GPR:$dst, (atomic_load_or_16 GPR:$ptr, GPR:$incr))]>;
4298 def ATOMIC_LOAD_XOR_I16 : PseudoInst<
4299 (outs GPR:$dst), (ins GPR:$ptr, GPR:$incr), NoItinerary,
4300 [(set GPR:$dst, (atomic_load_xor_16 GPR:$ptr, GPR:$incr))]>;
4301 def ATOMIC_LOAD_NAND_I16 : PseudoInst<
4302 (outs GPR:$dst), (ins GPR:$ptr, GPR:$incr), NoItinerary,
4303 [(set GPR:$dst, (atomic_load_nand_16 GPR:$ptr, GPR:$incr))]>;
4304 def ATOMIC_LOAD_MIN_I16 : PseudoInst<
4305 (outs GPR:$dst), (ins GPR:$ptr, GPR:$val), NoItinerary,
4306 [(set GPR:$dst, (atomic_load_min_16 GPR:$ptr, GPR:$val))]>;
4307 def ATOMIC_LOAD_MAX_I16 : PseudoInst<
4308 (outs GPR:$dst), (ins GPR:$ptr, GPR:$val), NoItinerary,
4309 [(set GPR:$dst, (atomic_load_max_16 GPR:$ptr, GPR:$val))]>;
4310 def ATOMIC_LOAD_UMIN_I16 : PseudoInst<
4311 (outs GPR:$dst), (ins GPR:$ptr, GPR:$val), NoItinerary,
4312 [(set GPR:$dst, (atomic_load_umin_16 GPR:$ptr, GPR:$val))]>;
4313 def ATOMIC_LOAD_UMAX_I16 : PseudoInst<
4314 (outs GPR:$dst), (ins GPR:$ptr, GPR:$val), NoItinerary,
4315 [(set GPR:$dst, (atomic_load_umax_16 GPR:$ptr, GPR:$val))]>;
4316 def ATOMIC_LOAD_ADD_I32 : PseudoInst<
4317 (outs GPR:$dst), (ins GPR:$ptr, GPR:$incr), NoItinerary,
4318 [(set GPR:$dst, (atomic_load_add_32 GPR:$ptr, GPR:$incr))]>;
4319 def ATOMIC_LOAD_SUB_I32 : PseudoInst<
4320 (outs GPR:$dst), (ins GPR:$ptr, GPR:$incr), NoItinerary,
4321 [(set GPR:$dst, (atomic_load_sub_32 GPR:$ptr, GPR:$incr))]>;
4322 def ATOMIC_LOAD_AND_I32 : PseudoInst<
4323 (outs GPR:$dst), (ins GPR:$ptr, GPR:$incr), NoItinerary,
4324 [(set GPR:$dst, (atomic_load_and_32 GPR:$ptr, GPR:$incr))]>;
4325 def ATOMIC_LOAD_OR_I32 : PseudoInst<
4326 (outs GPR:$dst), (ins GPR:$ptr, GPR:$incr), NoItinerary,
4327 [(set GPR:$dst, (atomic_load_or_32 GPR:$ptr, GPR:$incr))]>;
4328 def ATOMIC_LOAD_XOR_I32 : PseudoInst<
4329 (outs GPR:$dst), (ins GPR:$ptr, GPR:$incr), NoItinerary,
4330 [(set GPR:$dst, (atomic_load_xor_32 GPR:$ptr, GPR:$incr))]>;
4331 def ATOMIC_LOAD_NAND_I32 : PseudoInst<
4332 (outs GPR:$dst), (ins GPR:$ptr, GPR:$incr), NoItinerary,
4333 [(set GPR:$dst, (atomic_load_nand_32 GPR:$ptr, GPR:$incr))]>;
4334 def ATOMIC_LOAD_MIN_I32 : PseudoInst<
4335 (outs GPR:$dst), (ins GPR:$ptr, GPR:$val), NoItinerary,
4336 [(set GPR:$dst, (atomic_load_min_32 GPR:$ptr, GPR:$val))]>;
4337 def ATOMIC_LOAD_MAX_I32 : PseudoInst<
4338 (outs GPR:$dst), (ins GPR:$ptr, GPR:$val), NoItinerary,
4339 [(set GPR:$dst, (atomic_load_max_32 GPR:$ptr, GPR:$val))]>;
4340 def ATOMIC_LOAD_UMIN_I32 : PseudoInst<
4341 (outs GPR:$dst), (ins GPR:$ptr, GPR:$val), NoItinerary,
4342 [(set GPR:$dst, (atomic_load_umin_32 GPR:$ptr, GPR:$val))]>;
4343 def ATOMIC_LOAD_UMAX_I32 : PseudoInst<
4344 (outs GPR:$dst), (ins GPR:$ptr, GPR:$val), NoItinerary,
4345 [(set GPR:$dst, (atomic_load_umax_32 GPR:$ptr, GPR:$val))]>;
4347 def ATOMIC_SWAP_I8 : PseudoInst<
4348 (outs GPR:$dst), (ins GPR:$ptr, GPR:$new), NoItinerary,
4349 [(set GPR:$dst, (atomic_swap_8 GPR:$ptr, GPR:$new))]>;
4350 def ATOMIC_SWAP_I16 : PseudoInst<
4351 (outs GPR:$dst), (ins GPR:$ptr, GPR:$new), NoItinerary,
4352 [(set GPR:$dst, (atomic_swap_16 GPR:$ptr, GPR:$new))]>;
4353 def ATOMIC_SWAP_I32 : PseudoInst<
4354 (outs GPR:$dst), (ins GPR:$ptr, GPR:$new), NoItinerary,
4355 [(set GPR:$dst, (atomic_swap_32 GPR:$ptr, GPR:$new))]>;
4357 def ATOMIC_CMP_SWAP_I8 : PseudoInst<
4358 (outs GPR:$dst), (ins GPR:$ptr, GPR:$old, GPR:$new), NoItinerary,
4359 [(set GPR:$dst, (atomic_cmp_swap_8 GPR:$ptr, GPR:$old, GPR:$new))]>;
4360 def ATOMIC_CMP_SWAP_I16 : PseudoInst<
4361 (outs GPR:$dst), (ins GPR:$ptr, GPR:$old, GPR:$new), NoItinerary,
4362 [(set GPR:$dst, (atomic_cmp_swap_16 GPR:$ptr, GPR:$old, GPR:$new))]>;
4363 def ATOMIC_CMP_SWAP_I32 : PseudoInst<
4364 (outs GPR:$dst), (ins GPR:$ptr, GPR:$old, GPR:$new), NoItinerary,
4365 [(set GPR:$dst, (atomic_cmp_swap_32 GPR:$ptr, GPR:$old, GPR:$new))]>;
4369 let usesCustomInserter = 1 in {
4370 def COPY_STRUCT_BYVAL_I32 : PseudoInst<
4371 (outs), (ins GPR:$dst, GPR:$src, i32imm:$size, i32imm:$alignment),
4373 [(ARMcopystructbyval GPR:$dst, GPR:$src, imm:$size, imm:$alignment)]>;
4376 let mayLoad = 1 in {
4377 def LDREXB : AIldrex<0b10, (outs GPR:$Rt), (ins addr_offset_none:$addr),
4379 "ldrexb", "\t$Rt, $addr", []>;
4380 def LDREXH : AIldrex<0b11, (outs GPR:$Rt), (ins addr_offset_none:$addr),
4381 NoItinerary, "ldrexh", "\t$Rt, $addr", []>;
4382 def LDREX : AIldrex<0b00, (outs GPR:$Rt), (ins addr_offset_none:$addr),
4383 NoItinerary, "ldrex", "\t$Rt, $addr", []>;
4384 let hasExtraDefRegAllocReq = 1 in
4385 def LDREXD: AIldrex<0b01, (outs GPRPairOp:$Rt),(ins addr_offset_none:$addr),
4386 NoItinerary, "ldrexd", "\t$Rt, $addr", []> {
4387 let DecoderMethod = "DecodeDoubleRegLoad";
4391 let mayStore = 1, Constraints = "@earlyclobber $Rd" in {
4392 def STREXB: AIstrex<0b10, (outs GPR:$Rd), (ins GPR:$Rt, addr_offset_none:$addr),
4393 NoItinerary, "strexb", "\t$Rd, $Rt, $addr", []>;
4394 def STREXH: AIstrex<0b11, (outs GPR:$Rd), (ins GPR:$Rt, addr_offset_none:$addr),
4395 NoItinerary, "strexh", "\t$Rd, $Rt, $addr", []>;
4396 def STREX : AIstrex<0b00, (outs GPR:$Rd), (ins GPR:$Rt, addr_offset_none:$addr),
4397 NoItinerary, "strex", "\t$Rd, $Rt, $addr", []>;
4398 let hasExtraSrcRegAllocReq = 1 in
4399 def STREXD : AIstrex<0b01, (outs GPR:$Rd),
4400 (ins GPRPairOp:$Rt, addr_offset_none:$addr),
4401 NoItinerary, "strexd", "\t$Rd, $Rt, $addr", []> {
4402 let DecoderMethod = "DecodeDoubleRegStore";
4407 def CLREX : AXI<(outs), (ins), MiscFrm, NoItinerary, "clrex", []>,
4408 Requires<[IsARM, HasV7]> {
4409 let Inst{31-0} = 0b11110101011111111111000000011111;
4412 // SWP/SWPB are deprecated in V6/V7.
4413 let mayLoad = 1, mayStore = 1 in {
4414 def SWP : AIswp<0, (outs GPRnopc:$Rt),
4415 (ins GPRnopc:$Rt2, addr_offset_none:$addr), "swp", []>;
4416 def SWPB: AIswp<1, (outs GPRnopc:$Rt),
4417 (ins GPRnopc:$Rt2, addr_offset_none:$addr), "swpb", []>;
4420 //===----------------------------------------------------------------------===//
4421 // Coprocessor Instructions.
4424 def CDP : ABI<0b1110, (outs), (ins p_imm:$cop, imm0_15:$opc1,
4425 c_imm:$CRd, c_imm:$CRn, c_imm:$CRm, imm0_7:$opc2),
4426 NoItinerary, "cdp", "\t$cop, $opc1, $CRd, $CRn, $CRm, $opc2",
4427 [(int_arm_cdp imm:$cop, imm:$opc1, imm:$CRd, imm:$CRn,
4428 imm:$CRm, imm:$opc2)]> {
4436 let Inst{3-0} = CRm;
4438 let Inst{7-5} = opc2;
4439 let Inst{11-8} = cop;
4440 let Inst{15-12} = CRd;
4441 let Inst{19-16} = CRn;
4442 let Inst{23-20} = opc1;
4445 def CDP2 : ABXI<0b1110, (outs), (ins p_imm:$cop, imm0_15:$opc1,
4446 c_imm:$CRd, c_imm:$CRn, c_imm:$CRm, imm0_7:$opc2),
4447 NoItinerary, "cdp2\t$cop, $opc1, $CRd, $CRn, $CRm, $opc2",
4448 [(int_arm_cdp2 imm:$cop, imm:$opc1, imm:$CRd, imm:$CRn,
4449 imm:$CRm, imm:$opc2)]> {
4450 let Inst{31-28} = 0b1111;
4458 let Inst{3-0} = CRm;
4460 let Inst{7-5} = opc2;
4461 let Inst{11-8} = cop;
4462 let Inst{15-12} = CRd;
4463 let Inst{19-16} = CRn;
4464 let Inst{23-20} = opc1;
4467 class ACI<dag oops, dag iops, string opc, string asm,
4468 IndexMode im = IndexModeNone>
4469 : I<oops, iops, AddrModeNone, 4, im, BrFrm, NoItinerary,
4471 let Inst{27-25} = 0b110;
4473 class ACInoP<dag oops, dag iops, string opc, string asm,
4474 IndexMode im = IndexModeNone>
4475 : InoP<oops, iops, AddrModeNone, 4, im, BrFrm, NoItinerary,
4477 let Inst{31-28} = 0b1111;
4478 let Inst{27-25} = 0b110;
4480 multiclass LdStCop<bit load, bit Dbit, string asm> {
4481 def _OFFSET : ACI<(outs), (ins p_imm:$cop, c_imm:$CRd, addrmode5:$addr),
4482 asm, "\t$cop, $CRd, $addr"> {
4486 let Inst{24} = 1; // P = 1
4487 let Inst{23} = addr{8};
4488 let Inst{22} = Dbit;
4489 let Inst{21} = 0; // W = 0
4490 let Inst{20} = load;
4491 let Inst{19-16} = addr{12-9};
4492 let Inst{15-12} = CRd;
4493 let Inst{11-8} = cop;
4494 let Inst{7-0} = addr{7-0};
4495 let DecoderMethod = "DecodeCopMemInstruction";
4497 def _PRE : ACI<(outs), (ins p_imm:$cop, c_imm:$CRd, addrmode5_pre:$addr),
4498 asm, "\t$cop, $CRd, $addr!", IndexModePre> {
4502 let Inst{24} = 1; // P = 1
4503 let Inst{23} = addr{8};
4504 let Inst{22} = Dbit;
4505 let Inst{21} = 1; // W = 1
4506 let Inst{20} = load;
4507 let Inst{19-16} = addr{12-9};
4508 let Inst{15-12} = CRd;
4509 let Inst{11-8} = cop;
4510 let Inst{7-0} = addr{7-0};
4511 let DecoderMethod = "DecodeCopMemInstruction";
4513 def _POST: ACI<(outs), (ins p_imm:$cop, c_imm:$CRd, addr_offset_none:$addr,
4514 postidx_imm8s4:$offset),
4515 asm, "\t$cop, $CRd, $addr, $offset", IndexModePost> {
4520 let Inst{24} = 0; // P = 0
4521 let Inst{23} = offset{8};
4522 let Inst{22} = Dbit;
4523 let Inst{21} = 1; // W = 1
4524 let Inst{20} = load;
4525 let Inst{19-16} = addr;
4526 let Inst{15-12} = CRd;
4527 let Inst{11-8} = cop;
4528 let Inst{7-0} = offset{7-0};
4529 let DecoderMethod = "DecodeCopMemInstruction";
4531 def _OPTION : ACI<(outs),
4532 (ins p_imm:$cop, c_imm:$CRd, addr_offset_none:$addr,
4533 coproc_option_imm:$option),
4534 asm, "\t$cop, $CRd, $addr, $option"> {
4539 let Inst{24} = 0; // P = 0
4540 let Inst{23} = 1; // U = 1
4541 let Inst{22} = Dbit;
4542 let Inst{21} = 0; // W = 0
4543 let Inst{20} = load;
4544 let Inst{19-16} = addr;
4545 let Inst{15-12} = CRd;
4546 let Inst{11-8} = cop;
4547 let Inst{7-0} = option;
4548 let DecoderMethod = "DecodeCopMemInstruction";
4551 multiclass LdSt2Cop<bit load, bit Dbit, string asm> {
4552 def _OFFSET : ACInoP<(outs), (ins p_imm:$cop, c_imm:$CRd, addrmode5:$addr),
4553 asm, "\t$cop, $CRd, $addr"> {
4557 let Inst{24} = 1; // P = 1
4558 let Inst{23} = addr{8};
4559 let Inst{22} = Dbit;
4560 let Inst{21} = 0; // W = 0
4561 let Inst{20} = load;
4562 let Inst{19-16} = addr{12-9};
4563 let Inst{15-12} = CRd;
4564 let Inst{11-8} = cop;
4565 let Inst{7-0} = addr{7-0};
4566 let DecoderMethod = "DecodeCopMemInstruction";
4568 def _PRE : ACInoP<(outs), (ins p_imm:$cop, c_imm:$CRd, addrmode5_pre:$addr),
4569 asm, "\t$cop, $CRd, $addr!", IndexModePre> {
4573 let Inst{24} = 1; // P = 1
4574 let Inst{23} = addr{8};
4575 let Inst{22} = Dbit;
4576 let Inst{21} = 1; // W = 1
4577 let Inst{20} = load;
4578 let Inst{19-16} = addr{12-9};
4579 let Inst{15-12} = CRd;
4580 let Inst{11-8} = cop;
4581 let Inst{7-0} = addr{7-0};
4582 let DecoderMethod = "DecodeCopMemInstruction";
4584 def _POST: ACInoP<(outs), (ins p_imm:$cop, c_imm:$CRd, addr_offset_none:$addr,
4585 postidx_imm8s4:$offset),
4586 asm, "\t$cop, $CRd, $addr, $offset", IndexModePost> {
4591 let Inst{24} = 0; // P = 0
4592 let Inst{23} = offset{8};
4593 let Inst{22} = Dbit;
4594 let Inst{21} = 1; // W = 1
4595 let Inst{20} = load;
4596 let Inst{19-16} = addr;
4597 let Inst{15-12} = CRd;
4598 let Inst{11-8} = cop;
4599 let Inst{7-0} = offset{7-0};
4600 let DecoderMethod = "DecodeCopMemInstruction";
4602 def _OPTION : ACInoP<(outs),
4603 (ins p_imm:$cop, c_imm:$CRd, addr_offset_none:$addr,
4604 coproc_option_imm:$option),
4605 asm, "\t$cop, $CRd, $addr, $option"> {
4610 let Inst{24} = 0; // P = 0
4611 let Inst{23} = 1; // U = 1
4612 let Inst{22} = Dbit;
4613 let Inst{21} = 0; // W = 0
4614 let Inst{20} = load;
4615 let Inst{19-16} = addr;
4616 let Inst{15-12} = CRd;
4617 let Inst{11-8} = cop;
4618 let Inst{7-0} = option;
4619 let DecoderMethod = "DecodeCopMemInstruction";
4623 defm LDC : LdStCop <1, 0, "ldc">;
4624 defm LDCL : LdStCop <1, 1, "ldcl">;
4625 defm STC : LdStCop <0, 0, "stc">;
4626 defm STCL : LdStCop <0, 1, "stcl">;
4627 defm LDC2 : LdSt2Cop<1, 0, "ldc2">;
4628 defm LDC2L : LdSt2Cop<1, 1, "ldc2l">;
4629 defm STC2 : LdSt2Cop<0, 0, "stc2">;
4630 defm STC2L : LdSt2Cop<0, 1, "stc2l">;
4632 //===----------------------------------------------------------------------===//
4633 // Move between coprocessor and ARM core register.
4636 class MovRCopro<string opc, bit direction, dag oops, dag iops,
4638 : ABI<0b1110, oops, iops, NoItinerary, opc,
4639 "\t$cop, $opc1, $Rt, $CRn, $CRm, $opc2", pattern> {
4640 let Inst{20} = direction;
4650 let Inst{15-12} = Rt;
4651 let Inst{11-8} = cop;
4652 let Inst{23-21} = opc1;
4653 let Inst{7-5} = opc2;
4654 let Inst{3-0} = CRm;
4655 let Inst{19-16} = CRn;
4658 def MCR : MovRCopro<"mcr", 0 /* from ARM core register to coprocessor */,
4660 (ins p_imm:$cop, imm0_7:$opc1, GPR:$Rt, c_imm:$CRn,
4661 c_imm:$CRm, imm0_7:$opc2),
4662 [(int_arm_mcr imm:$cop, imm:$opc1, GPR:$Rt, imm:$CRn,
4663 imm:$CRm, imm:$opc2)]>;
4664 def : ARMInstAlias<"mcr${p} $cop, $opc1, $Rt, $CRn, $CRm",
4665 (MCR p_imm:$cop, imm0_7:$opc1, GPR:$Rt, c_imm:$CRn,
4666 c_imm:$CRm, 0, pred:$p)>;
4667 def MRC : MovRCopro<"mrc", 1 /* from coprocessor to ARM core register */,
4668 (outs GPRwithAPSR:$Rt),
4669 (ins p_imm:$cop, imm0_7:$opc1, c_imm:$CRn, c_imm:$CRm,
4671 def : ARMInstAlias<"mrc${p} $cop, $opc1, $Rt, $CRn, $CRm",
4672 (MRC GPRwithAPSR:$Rt, p_imm:$cop, imm0_7:$opc1, c_imm:$CRn,
4673 c_imm:$CRm, 0, pred:$p)>;
4675 def : ARMPat<(int_arm_mrc imm:$cop, imm:$opc1, imm:$CRn, imm:$CRm, imm:$opc2),
4676 (MRC imm:$cop, imm:$opc1, imm:$CRn, imm:$CRm, imm:$opc2)>;
4678 class MovRCopro2<string opc, bit direction, dag oops, dag iops,
4680 : ABXI<0b1110, oops, iops, NoItinerary,
4681 !strconcat(opc, "\t$cop, $opc1, $Rt, $CRn, $CRm, $opc2"), pattern> {
4682 let Inst{31-24} = 0b11111110;
4683 let Inst{20} = direction;
4693 let Inst{15-12} = Rt;
4694 let Inst{11-8} = cop;
4695 let Inst{23-21} = opc1;
4696 let Inst{7-5} = opc2;
4697 let Inst{3-0} = CRm;
4698 let Inst{19-16} = CRn;
4701 def MCR2 : MovRCopro2<"mcr2", 0 /* from ARM core register to coprocessor */,
4703 (ins p_imm:$cop, imm0_7:$opc1, GPR:$Rt, c_imm:$CRn,
4704 c_imm:$CRm, imm0_7:$opc2),
4705 [(int_arm_mcr2 imm:$cop, imm:$opc1, GPR:$Rt, imm:$CRn,
4706 imm:$CRm, imm:$opc2)]>;
4707 def : ARMInstAlias<"mcr2$ $cop, $opc1, $Rt, $CRn, $CRm",
4708 (MCR2 p_imm:$cop, imm0_7:$opc1, GPR:$Rt, c_imm:$CRn,
4710 def MRC2 : MovRCopro2<"mrc2", 1 /* from coprocessor to ARM core register */,
4711 (outs GPRwithAPSR:$Rt),
4712 (ins p_imm:$cop, imm0_7:$opc1, c_imm:$CRn, c_imm:$CRm,
4714 def : ARMInstAlias<"mrc2$ $cop, $opc1, $Rt, $CRn, $CRm",
4715 (MRC2 GPRwithAPSR:$Rt, p_imm:$cop, imm0_7:$opc1, c_imm:$CRn,
4718 def : ARMV5TPat<(int_arm_mrc2 imm:$cop, imm:$opc1, imm:$CRn,
4719 imm:$CRm, imm:$opc2),
4720 (MRC2 imm:$cop, imm:$opc1, imm:$CRn, imm:$CRm, imm:$opc2)>;
4722 class MovRRCopro<string opc, bit direction, list<dag> pattern = []>
4723 : ABI<0b1100, (outs), (ins p_imm:$cop, imm0_15:$opc1,
4724 GPRnopc:$Rt, GPRnopc:$Rt2, c_imm:$CRm),
4725 NoItinerary, opc, "\t$cop, $opc1, $Rt, $Rt2, $CRm", pattern> {
4726 let Inst{23-21} = 0b010;
4727 let Inst{20} = direction;
4735 let Inst{15-12} = Rt;
4736 let Inst{19-16} = Rt2;
4737 let Inst{11-8} = cop;
4738 let Inst{7-4} = opc1;
4739 let Inst{3-0} = CRm;
4742 def MCRR : MovRRCopro<"mcrr", 0 /* from ARM core register to coprocessor */,
4743 [(int_arm_mcrr imm:$cop, imm:$opc1, GPRnopc:$Rt,
4744 GPRnopc:$Rt2, imm:$CRm)]>;
4745 def MRRC : MovRRCopro<"mrrc", 1 /* from coprocessor to ARM core register */>;
4747 class MovRRCopro2<string opc, bit direction, list<dag> pattern = []>
4748 : ABXI<0b1100, (outs), (ins p_imm:$cop, imm0_15:$opc1,
4749 GPRnopc:$Rt, GPRnopc:$Rt2, c_imm:$CRm), NoItinerary,
4750 !strconcat(opc, "\t$cop, $opc1, $Rt, $Rt2, $CRm"), pattern> {
4751 let Inst{31-28} = 0b1111;
4752 let Inst{23-21} = 0b010;
4753 let Inst{20} = direction;
4761 let Inst{15-12} = Rt;
4762 let Inst{19-16} = Rt2;
4763 let Inst{11-8} = cop;
4764 let Inst{7-4} = opc1;
4765 let Inst{3-0} = CRm;
4767 let DecoderMethod = "DecodeMRRC2";
4770 def MCRR2 : MovRRCopro2<"mcrr2", 0 /* from ARM core register to coprocessor */,
4771 [(int_arm_mcrr2 imm:$cop, imm:$opc1, GPRnopc:$Rt,
4772 GPRnopc:$Rt2, imm:$CRm)]>;
4773 def MRRC2 : MovRRCopro2<"mrrc2", 1 /* from coprocessor to ARM core register */>;
4775 //===----------------------------------------------------------------------===//
4776 // Move between special register and ARM core register
4779 // Move to ARM core register from Special Register
4780 def MRS : ABI<0b0001, (outs GPRnopc:$Rd), (ins), NoItinerary,
4781 "mrs", "\t$Rd, apsr", []> {
4783 let Inst{23-16} = 0b00001111;
4784 let Unpredictable{19-17} = 0b111;
4786 let Inst{15-12} = Rd;
4788 let Inst{11-0} = 0b000000000000;
4789 let Unpredictable{11-0} = 0b110100001111;
4792 def : InstAlias<"mrs${p} $Rd, cpsr", (MRS GPRnopc:$Rd, pred:$p)>,
4795 // The MRSsys instruction is the MRS instruction from the ARM ARM,
4796 // section B9.3.9, with the R bit set to 1.
4797 def MRSsys : ABI<0b0001, (outs GPRnopc:$Rd), (ins), NoItinerary,
4798 "mrs", "\t$Rd, spsr", []> {
4800 let Inst{23-16} = 0b01001111;
4801 let Unpredictable{19-16} = 0b1111;
4803 let Inst{15-12} = Rd;
4805 let Inst{11-0} = 0b000000000000;
4806 let Unpredictable{11-0} = 0b110100001111;
4809 // Move from ARM core register to Special Register
4811 // No need to have both system and application versions, the encodings are the
4812 // same and the assembly parser has no way to distinguish between them. The mask
4813 // operand contains the special register (R Bit) in bit 4 and bits 3-0 contains
4814 // the mask with the fields to be accessed in the special register.
4815 def MSR : ABI<0b0001, (outs), (ins msr_mask:$mask, GPR:$Rn), NoItinerary,
4816 "msr", "\t$mask, $Rn", []> {
4821 let Inst{22} = mask{4}; // R bit
4822 let Inst{21-20} = 0b10;
4823 let Inst{19-16} = mask{3-0};
4824 let Inst{15-12} = 0b1111;
4825 let Inst{11-4} = 0b00000000;
4829 def MSRi : ABI<0b0011, (outs), (ins msr_mask:$mask, so_imm:$a), NoItinerary,
4830 "msr", "\t$mask, $a", []> {
4835 let Inst{22} = mask{4}; // R bit
4836 let Inst{21-20} = 0b10;
4837 let Inst{19-16} = mask{3-0};
4838 let Inst{15-12} = 0b1111;
4842 //===----------------------------------------------------------------------===//
4846 // __aeabi_read_tp preserves the registers r1-r3.
4847 // This is a pseudo inst so that we can get the encoding right,
4848 // complete with fixup for the aeabi_read_tp function.
4850 Defs = [R0, R12, LR, CPSR], Uses = [SP] in {
4851 def TPsoft : PseudoInst<(outs), (ins), IIC_Br,
4852 [(set R0, ARMthread_pointer)]>, Sched<[WriteBr]>;
4855 //===----------------------------------------------------------------------===//
4856 // SJLJ Exception handling intrinsics
4857 // eh_sjlj_setjmp() is an instruction sequence to store the return
4858 // address and save #0 in R0 for the non-longjmp case.
4859 // Since by its nature we may be coming from some other function to get
4860 // here, and we're using the stack frame for the containing function to
4861 // save/restore registers, we can't keep anything live in regs across
4862 // the eh_sjlj_setjmp(), else it will almost certainly have been tromped upon
4863 // when we get here from a longjmp(). We force everything out of registers
4864 // except for our own input by listing the relevant registers in Defs. By
4865 // doing so, we also cause the prologue/epilogue code to actively preserve
4866 // all of the callee-saved resgisters, which is exactly what we want.
4867 // A constant value is passed in $val, and we use the location as a scratch.
4869 // These are pseudo-instructions and are lowered to individual MC-insts, so
4870 // no encoding information is necessary.
4872 [ R0, R1, R2, R3, R4, R5, R6, R7, R8, R9, R10, R11, R12, LR, CPSR,
4873 Q0, Q1, Q2, Q3, Q4, Q5, Q6, Q7, Q8, Q9, Q10, Q11, Q12, Q13, Q14, Q15 ],
4874 hasSideEffects = 1, isBarrier = 1, usesCustomInserter = 1 in {
4875 def Int_eh_sjlj_setjmp : PseudoInst<(outs), (ins GPR:$src, GPR:$val),
4877 [(set R0, (ARMeh_sjlj_setjmp GPR:$src, GPR:$val))]>,
4878 Requires<[IsARM, HasVFP2]>;
4882 [ R0, R1, R2, R3, R4, R5, R6, R7, R8, R9, R10, R11, R12, LR, CPSR ],
4883 hasSideEffects = 1, isBarrier = 1, usesCustomInserter = 1 in {
4884 def Int_eh_sjlj_setjmp_nofp : PseudoInst<(outs), (ins GPR:$src, GPR:$val),
4886 [(set R0, (ARMeh_sjlj_setjmp GPR:$src, GPR:$val))]>,
4887 Requires<[IsARM, NoVFP]>;
4890 // FIXME: Non-IOS version(s)
4891 let isBarrier = 1, hasSideEffects = 1, isTerminator = 1,
4892 Defs = [ R7, LR, SP ] in {
4893 def Int_eh_sjlj_longjmp : PseudoInst<(outs), (ins GPR:$src, GPR:$scratch),
4895 [(ARMeh_sjlj_longjmp GPR:$src, GPR:$scratch)]>,
4896 Requires<[IsARM, IsIOS]>;
4899 // eh.sjlj.dispatchsetup pseudo-instruction.
4900 // This pseudo is used for both ARM and Thumb. Any differences are handled when
4901 // the pseudo is expanded (which happens before any passes that need the
4902 // instruction size).
4903 let isBarrier = 1 in
4904 def Int_eh_sjlj_dispatchsetup : PseudoInst<(outs), (ins), NoItinerary, []>;
4907 //===----------------------------------------------------------------------===//
4908 // Non-Instruction Patterns
4911 // ARMv4 indirect branch using (MOVr PC, dst)
4912 let isBranch = 1, isTerminator = 1, isBarrier = 1, isIndirectBranch = 1 in
4913 def MOVPCRX : ARMPseudoExpand<(outs), (ins GPR:$dst),
4914 4, IIC_Br, [(brind GPR:$dst)],
4915 (MOVr PC, GPR:$dst, (ops 14, zero_reg), zero_reg)>,
4916 Requires<[IsARM, NoV4T]>, Sched<[WriteBr]>;
4918 // Large immediate handling.
4920 // 32-bit immediate using two piece so_imms or movw + movt.
4921 // This is a single pseudo instruction, the benefit is that it can be remat'd
4922 // as a single unit instead of having to handle reg inputs.
4923 // FIXME: Remove this when we can do generalized remat.
4924 let isReMaterializable = 1, isMoveImm = 1 in
4925 def MOVi32imm : PseudoInst<(outs GPR:$dst), (ins i32imm:$src), IIC_iMOVix2,
4926 [(set GPR:$dst, (arm_i32imm:$src))]>,
4929 // Pseudo instruction that combines movw + movt + add pc (if PIC).
4930 // It also makes it possible to rematerialize the instructions.
4931 // FIXME: Remove this when we can do generalized remat and when machine licm
4932 // can properly the instructions.
4933 let isReMaterializable = 1 in {
4934 def MOV_ga_pcrel : PseudoInst<(outs GPR:$dst), (ins i32imm:$addr),
4936 [(set GPR:$dst, (ARMWrapperPIC tglobaladdr:$addr))]>,
4937 Requires<[IsARM, UseMovt]>;
4939 def MOV_ga_dyn : PseudoInst<(outs GPR:$dst), (ins i32imm:$addr),
4941 [(set GPR:$dst, (ARMWrapperDYN tglobaladdr:$addr))]>,
4942 Requires<[IsARM, UseMovt]>;
4944 let AddedComplexity = 10 in
4945 def MOV_ga_pcrel_ldr : PseudoInst<(outs GPR:$dst), (ins i32imm:$addr),
4947 [(set GPR:$dst, (load (ARMWrapperPIC tglobaladdr:$addr)))]>,
4948 Requires<[IsARM, UseMovt]>;
4949 } // isReMaterializable
4951 // ConstantPool, GlobalAddress, and JumpTable
4952 def : ARMPat<(ARMWrapper tglobaladdr :$dst), (LEApcrel tglobaladdr :$dst)>,
4953 Requires<[IsARM, DontUseMovt]>;
4954 def : ARMPat<(ARMWrapper tconstpool :$dst), (LEApcrel tconstpool :$dst)>;
4955 def : ARMPat<(ARMWrapper tglobaladdr :$dst), (MOVi32imm tglobaladdr :$dst)>,
4956 Requires<[IsARM, UseMovt]>;
4957 def : ARMPat<(ARMWrapperJT tjumptable:$dst, imm:$id),
4958 (LEApcrelJT tjumptable:$dst, imm:$id)>;
4960 // TODO: add,sub,and, 3-instr forms?
4962 // Tail calls. These patterns also apply to Thumb mode.
4963 def : Pat<(ARMtcret tcGPR:$dst), (TCRETURNri tcGPR:$dst)>;
4964 def : Pat<(ARMtcret (i32 tglobaladdr:$dst)), (TCRETURNdi texternalsym:$dst)>;
4965 def : Pat<(ARMtcret (i32 texternalsym:$dst)), (TCRETURNdi texternalsym:$dst)>;
4968 def : ARMPat<(ARMcall texternalsym:$func), (BL texternalsym:$func)>;
4969 def : ARMPat<(ARMcall_nolink texternalsym:$func),
4970 (BMOVPCB_CALL texternalsym:$func)>;
4972 // zextload i1 -> zextload i8
4973 def : ARMPat<(zextloadi1 addrmode_imm12:$addr), (LDRBi12 addrmode_imm12:$addr)>;
4974 def : ARMPat<(zextloadi1 ldst_so_reg:$addr), (LDRBrs ldst_so_reg:$addr)>;
4976 // extload -> zextload
4977 def : ARMPat<(extloadi1 addrmode_imm12:$addr), (LDRBi12 addrmode_imm12:$addr)>;
4978 def : ARMPat<(extloadi1 ldst_so_reg:$addr), (LDRBrs ldst_so_reg:$addr)>;
4979 def : ARMPat<(extloadi8 addrmode_imm12:$addr), (LDRBi12 addrmode_imm12:$addr)>;
4980 def : ARMPat<(extloadi8 ldst_so_reg:$addr), (LDRBrs ldst_so_reg:$addr)>;
4982 def : ARMPat<(extloadi16 addrmode3:$addr), (LDRH addrmode3:$addr)>;
4984 def : ARMPat<(extloadi8 addrmodepc:$addr), (PICLDRB addrmodepc:$addr)>;
4985 def : ARMPat<(extloadi16 addrmodepc:$addr), (PICLDRH addrmodepc:$addr)>;
4988 def : ARMV5TEPat<(mul (sra (shl GPR:$a, (i32 16)), (i32 16)),
4989 (sra (shl GPR:$b, (i32 16)), (i32 16))),
4990 (SMULBB GPR:$a, GPR:$b)>;
4991 def : ARMV5TEPat<(mul sext_16_node:$a, sext_16_node:$b),
4992 (SMULBB GPR:$a, GPR:$b)>;
4993 def : ARMV5TEPat<(mul (sra (shl GPR:$a, (i32 16)), (i32 16)),
4994 (sra GPR:$b, (i32 16))),
4995 (SMULBT GPR:$a, GPR:$b)>;
4996 def : ARMV5TEPat<(mul sext_16_node:$a, (sra GPR:$b, (i32 16))),
4997 (SMULBT GPR:$a, GPR:$b)>;
4998 def : ARMV5TEPat<(mul (sra GPR:$a, (i32 16)),
4999 (sra (shl GPR:$b, (i32 16)), (i32 16))),
5000 (SMULTB GPR:$a, GPR:$b)>;
5001 def : ARMV5TEPat<(mul (sra GPR:$a, (i32 16)), sext_16_node:$b),
5002 (SMULTB GPR:$a, GPR:$b)>;
5003 def : ARMV5TEPat<(sra (mul GPR:$a, (sra (shl GPR:$b, (i32 16)), (i32 16))),
5005 (SMULWB GPR:$a, GPR:$b)>;
5006 def : ARMV5TEPat<(sra (mul GPR:$a, sext_16_node:$b), (i32 16)),
5007 (SMULWB GPR:$a, GPR:$b)>;
5009 def : ARMV5MOPat<(add GPR:$acc,
5010 (mul (sra (shl GPR:$a, (i32 16)), (i32 16)),
5011 (sra (shl GPR:$b, (i32 16)), (i32 16)))),
5012 (SMLABB GPR:$a, GPR:$b, GPR:$acc)>;
5013 def : ARMV5MOPat<(add GPR:$acc,
5014 (mul sext_16_node:$a, sext_16_node:$b)),
5015 (SMLABB GPR:$a, GPR:$b, GPR:$acc)>;
5016 def : ARMV5MOPat<(add GPR:$acc,
5017 (mul (sra (shl GPR:$a, (i32 16)), (i32 16)),
5018 (sra GPR:$b, (i32 16)))),
5019 (SMLABT GPR:$a, GPR:$b, GPR:$acc)>;
5020 def : ARMV5MOPat<(add GPR:$acc,
5021 (mul sext_16_node:$a, (sra GPR:$b, (i32 16)))),
5022 (SMLABT GPR:$a, GPR:$b, GPR:$acc)>;
5023 def : ARMV5MOPat<(add GPR:$acc,
5024 (mul (sra GPR:$a, (i32 16)),
5025 (sra (shl GPR:$b, (i32 16)), (i32 16)))),
5026 (SMLATB GPR:$a, GPR:$b, GPR:$acc)>;
5027 def : ARMV5MOPat<(add GPR:$acc,
5028 (mul (sra GPR:$a, (i32 16)), sext_16_node:$b)),
5029 (SMLATB GPR:$a, GPR:$b, GPR:$acc)>;
5030 def : ARMV5MOPat<(add GPR:$acc,
5031 (sra (mul GPR:$a, (sra (shl GPR:$b, (i32 16)), (i32 16))),
5033 (SMLAWB GPR:$a, GPR:$b, GPR:$acc)>;
5034 def : ARMV5MOPat<(add GPR:$acc,
5035 (sra (mul GPR:$a, sext_16_node:$b), (i32 16))),
5036 (SMLAWB GPR:$a, GPR:$b, GPR:$acc)>;
5039 // Pre-v7 uses MCR for synchronization barriers.
5040 def : ARMPat<(ARMMemBarrierMCR GPR:$zero), (MCR 15, 0, GPR:$zero, 7, 10, 5)>,
5041 Requires<[IsARM, HasV6]>;
5043 // SXT/UXT with no rotate
5044 let AddedComplexity = 16 in {
5045 def : ARMV6Pat<(and GPR:$Src, 0x000000FF), (UXTB GPR:$Src, 0)>;
5046 def : ARMV6Pat<(and GPR:$Src, 0x0000FFFF), (UXTH GPR:$Src, 0)>;
5047 def : ARMV6Pat<(and GPR:$Src, 0x00FF00FF), (UXTB16 GPR:$Src, 0)>;
5048 def : ARMV6Pat<(add GPR:$Rn, (and GPR:$Rm, 0x00FF)),
5049 (UXTAB GPR:$Rn, GPR:$Rm, 0)>;
5050 def : ARMV6Pat<(add GPR:$Rn, (and GPR:$Rm, 0xFFFF)),
5051 (UXTAH GPR:$Rn, GPR:$Rm, 0)>;
5054 def : ARMV6Pat<(sext_inreg GPR:$Src, i8), (SXTB GPR:$Src, 0)>;
5055 def : ARMV6Pat<(sext_inreg GPR:$Src, i16), (SXTH GPR:$Src, 0)>;
5057 def : ARMV6Pat<(add GPR:$Rn, (sext_inreg GPRnopc:$Rm, i8)),
5058 (SXTAB GPR:$Rn, GPRnopc:$Rm, 0)>;
5059 def : ARMV6Pat<(add GPR:$Rn, (sext_inreg GPRnopc:$Rm, i16)),
5060 (SXTAH GPR:$Rn, GPRnopc:$Rm, 0)>;
5062 // Atomic load/store patterns
5063 def : ARMPat<(atomic_load_8 ldst_so_reg:$src),
5064 (LDRBrs ldst_so_reg:$src)>;
5065 def : ARMPat<(atomic_load_8 addrmode_imm12:$src),
5066 (LDRBi12 addrmode_imm12:$src)>;
5067 def : ARMPat<(atomic_load_16 addrmode3:$src),
5068 (LDRH addrmode3:$src)>;
5069 def : ARMPat<(atomic_load_32 ldst_so_reg:$src),
5070 (LDRrs ldst_so_reg:$src)>;
5071 def : ARMPat<(atomic_load_32 addrmode_imm12:$src),
5072 (LDRi12 addrmode_imm12:$src)>;
5073 def : ARMPat<(atomic_store_8 ldst_so_reg:$ptr, GPR:$val),
5074 (STRBrs GPR:$val, ldst_so_reg:$ptr)>;
5075 def : ARMPat<(atomic_store_8 addrmode_imm12:$ptr, GPR:$val),
5076 (STRBi12 GPR:$val, addrmode_imm12:$ptr)>;
5077 def : ARMPat<(atomic_store_16 addrmode3:$ptr, GPR:$val),
5078 (STRH GPR:$val, addrmode3:$ptr)>;
5079 def : ARMPat<(atomic_store_32 ldst_so_reg:$ptr, GPR:$val),
5080 (STRrs GPR:$val, ldst_so_reg:$ptr)>;
5081 def : ARMPat<(atomic_store_32 addrmode_imm12:$ptr, GPR:$val),
5082 (STRi12 GPR:$val, addrmode_imm12:$ptr)>;
5085 //===----------------------------------------------------------------------===//
5089 include "ARMInstrThumb.td"
5091 //===----------------------------------------------------------------------===//
5095 include "ARMInstrThumb2.td"
5097 //===----------------------------------------------------------------------===//
5098 // Floating Point Support
5101 include "ARMInstrVFP.td"
5103 //===----------------------------------------------------------------------===//
5104 // Advanced SIMD (NEON) Support
5107 include "ARMInstrNEON.td"
5109 //===----------------------------------------------------------------------===//
5110 // Assembler aliases
5114 def : InstAlias<"dmb", (DMB 0xf)>, Requires<[IsARM, HasDB]>;
5115 def : InstAlias<"dsb", (DSB 0xf)>, Requires<[IsARM, HasDB]>;
5116 def : InstAlias<"isb", (ISB 0xf)>, Requires<[IsARM, HasDB]>;
5118 // System instructions
5119 def : MnemonicAlias<"swi", "svc">;
5121 // Load / Store Multiple
5122 def : MnemonicAlias<"ldmfd", "ldm">;
5123 def : MnemonicAlias<"ldmia", "ldm">;
5124 def : MnemonicAlias<"ldmea", "ldmdb">;
5125 def : MnemonicAlias<"stmfd", "stmdb">;
5126 def : MnemonicAlias<"stmia", "stm">;
5127 def : MnemonicAlias<"stmea", "stm">;
5129 // PKHBT/PKHTB with default shift amount. PKHTB is equivalent to PKHBT when the
5130 // shift amount is zero (i.e., unspecified).
5131 def : InstAlias<"pkhbt${p} $Rd, $Rn, $Rm",
5132 (PKHBT GPRnopc:$Rd, GPRnopc:$Rn, GPRnopc:$Rm, 0, pred:$p)>,
5133 Requires<[IsARM, HasV6]>;
5134 def : InstAlias<"pkhtb${p} $Rd, $Rn, $Rm",
5135 (PKHBT GPRnopc:$Rd, GPRnopc:$Rn, GPRnopc:$Rm, 0, pred:$p)>,
5136 Requires<[IsARM, HasV6]>;
5138 // PUSH/POP aliases for STM/LDM
5139 def : ARMInstAlias<"push${p} $regs", (STMDB_UPD SP, pred:$p, reglist:$regs)>;
5140 def : ARMInstAlias<"pop${p} $regs", (LDMIA_UPD SP, pred:$p, reglist:$regs)>;
5142 // SSAT/USAT optional shift operand.
5143 def : ARMInstAlias<"ssat${p} $Rd, $sat_imm, $Rn",
5144 (SSAT GPRnopc:$Rd, imm1_32:$sat_imm, GPRnopc:$Rn, 0, pred:$p)>;
5145 def : ARMInstAlias<"usat${p} $Rd, $sat_imm, $Rn",
5146 (USAT GPRnopc:$Rd, imm0_31:$sat_imm, GPRnopc:$Rn, 0, pred:$p)>;
5149 // Extend instruction optional rotate operand.
5150 def : ARMInstAlias<"sxtab${p} $Rd, $Rn, $Rm",
5151 (SXTAB GPRnopc:$Rd, GPR:$Rn, GPRnopc:$Rm, 0, pred:$p)>;
5152 def : ARMInstAlias<"sxtah${p} $Rd, $Rn, $Rm",
5153 (SXTAH GPRnopc:$Rd, GPR:$Rn, GPRnopc:$Rm, 0, pred:$p)>;
5154 def : ARMInstAlias<"sxtab16${p} $Rd, $Rn, $Rm",
5155 (SXTAB16 GPRnopc:$Rd, GPR:$Rn, GPRnopc:$Rm, 0, pred:$p)>;
5156 def : ARMInstAlias<"sxtb${p} $Rd, $Rm",
5157 (SXTB GPRnopc:$Rd, GPRnopc:$Rm, 0, pred:$p)>;
5158 def : ARMInstAlias<"sxtb16${p} $Rd, $Rm",
5159 (SXTB16 GPRnopc:$Rd, GPRnopc:$Rm, 0, pred:$p)>;
5160 def : ARMInstAlias<"sxth${p} $Rd, $Rm",
5161 (SXTH GPRnopc:$Rd, GPRnopc:$Rm, 0, pred:$p)>;
5163 def : ARMInstAlias<"uxtab${p} $Rd, $Rn, $Rm",
5164 (UXTAB GPRnopc:$Rd, GPR:$Rn, GPRnopc:$Rm, 0, pred:$p)>;
5165 def : ARMInstAlias<"uxtah${p} $Rd, $Rn, $Rm",
5166 (UXTAH GPRnopc:$Rd, GPR:$Rn, GPRnopc:$Rm, 0, pred:$p)>;
5167 def : ARMInstAlias<"uxtab16${p} $Rd, $Rn, $Rm",
5168 (UXTAB16 GPRnopc:$Rd, GPR:$Rn, GPRnopc:$Rm, 0, pred:$p)>;
5169 def : ARMInstAlias<"uxtb${p} $Rd, $Rm",
5170 (UXTB GPRnopc:$Rd, GPRnopc:$Rm, 0, pred:$p)>;
5171 def : ARMInstAlias<"uxtb16${p} $Rd, $Rm",
5172 (UXTB16 GPRnopc:$Rd, GPRnopc:$Rm, 0, pred:$p)>;
5173 def : ARMInstAlias<"uxth${p} $Rd, $Rm",
5174 (UXTH GPRnopc:$Rd, GPRnopc:$Rm, 0, pred:$p)>;
5178 def : MnemonicAlias<"rfefa", "rfeda">;
5179 def : MnemonicAlias<"rfeea", "rfedb">;
5180 def : MnemonicAlias<"rfefd", "rfeia">;
5181 def : MnemonicAlias<"rfeed", "rfeib">;
5182 def : MnemonicAlias<"rfe", "rfeia">;
5185 def : MnemonicAlias<"srsfa", "srsda">;
5186 def : MnemonicAlias<"srsea", "srsdb">;
5187 def : MnemonicAlias<"srsfd", "srsia">;
5188 def : MnemonicAlias<"srsed", "srsib">;
5189 def : MnemonicAlias<"srs", "srsia">;
5192 def : MnemonicAlias<"qsubaddx", "qsax">;
5194 def : MnemonicAlias<"saddsubx", "sasx">;
5195 // SHASX == SHADDSUBX
5196 def : MnemonicAlias<"shaddsubx", "shasx">;
5197 // SHSAX == SHSUBADDX
5198 def : MnemonicAlias<"shsubaddx", "shsax">;
5200 def : MnemonicAlias<"ssubaddx", "ssax">;
5202 def : MnemonicAlias<"uaddsubx", "uasx">;
5203 // UHASX == UHADDSUBX
5204 def : MnemonicAlias<"uhaddsubx", "uhasx">;
5205 // UHSAX == UHSUBADDX
5206 def : MnemonicAlias<"uhsubaddx", "uhsax">;
5207 // UQASX == UQADDSUBX
5208 def : MnemonicAlias<"uqaddsubx", "uqasx">;
5209 // UQSAX == UQSUBADDX
5210 def : MnemonicAlias<"uqsubaddx", "uqsax">;
5212 def : MnemonicAlias<"usubaddx", "usax">;
5214 // "mov Rd, so_imm_not" can be handled via "mvn" in assembly, just like
5216 def : ARMInstAlias<"mov${s}${p} $Rd, $imm",
5217 (MVNi rGPR:$Rd, so_imm_not:$imm, pred:$p, cc_out:$s)>;
5218 def : ARMInstAlias<"mvn${s}${p} $Rd, $imm",
5219 (MOVi rGPR:$Rd, so_imm_not:$imm, pred:$p, cc_out:$s)>;
5220 // Same for AND <--> BIC
5221 def : ARMInstAlias<"bic${s}${p} $Rd, $Rn, $imm",
5222 (ANDri rGPR:$Rd, rGPR:$Rn, so_imm_not:$imm,
5223 pred:$p, cc_out:$s)>;
5224 def : ARMInstAlias<"bic${s}${p} $Rdn, $imm",
5225 (ANDri rGPR:$Rdn, rGPR:$Rdn, so_imm_not:$imm,
5226 pred:$p, cc_out:$s)>;
5227 def : ARMInstAlias<"and${s}${p} $Rd, $Rn, $imm",
5228 (BICri rGPR:$Rd, rGPR:$Rn, so_imm_not:$imm,
5229 pred:$p, cc_out:$s)>;
5230 def : ARMInstAlias<"and${s}${p} $Rdn, $imm",
5231 (BICri rGPR:$Rdn, rGPR:$Rdn, so_imm_not:$imm,
5232 pred:$p, cc_out:$s)>;
5234 // Likewise, "add Rd, so_imm_neg" -> sub
5235 def : ARMInstAlias<"add${s}${p} $Rd, $Rn, $imm",
5236 (SUBri GPR:$Rd, GPR:$Rn, so_imm_neg:$imm, pred:$p, cc_out:$s)>;
5237 def : ARMInstAlias<"add${s}${p} $Rd, $imm",
5238 (SUBri GPR:$Rd, GPR:$Rd, so_imm_neg:$imm, pred:$p, cc_out:$s)>;
5239 // Same for CMP <--> CMN via so_imm_neg
5240 def : ARMInstAlias<"cmp${p} $Rd, $imm",
5241 (CMNri rGPR:$Rd, so_imm_neg:$imm, pred:$p)>;
5242 def : ARMInstAlias<"cmn${p} $Rd, $imm",
5243 (CMPri rGPR:$Rd, so_imm_neg:$imm, pred:$p)>;
5245 // The shifter forms of the MOV instruction are aliased to the ASR, LSL,
5246 // LSR, ROR, and RRX instructions.
5247 // FIXME: We need C++ parser hooks to map the alias to the MOV
5248 // encoding. It seems we should be able to do that sort of thing
5249 // in tblgen, but it could get ugly.
5250 let TwoOperandAliasConstraint = "$Rm = $Rd" in {
5251 def ASRi : ARMAsmPseudo<"asr${s}${p} $Rd, $Rm, $imm",
5252 (ins GPR:$Rd, GPR:$Rm, imm0_32:$imm, pred:$p,
5254 def LSRi : ARMAsmPseudo<"lsr${s}${p} $Rd, $Rm, $imm",
5255 (ins GPR:$Rd, GPR:$Rm, imm0_32:$imm, pred:$p,
5257 def LSLi : ARMAsmPseudo<"lsl${s}${p} $Rd, $Rm, $imm",
5258 (ins GPR:$Rd, GPR:$Rm, imm0_31:$imm, pred:$p,
5260 def RORi : ARMAsmPseudo<"ror${s}${p} $Rd, $Rm, $imm",
5261 (ins GPR:$Rd, GPR:$Rm, imm0_31:$imm, pred:$p,
5264 def RRXi : ARMAsmPseudo<"rrx${s}${p} $Rd, $Rm",
5265 (ins GPR:$Rd, GPR:$Rm, pred:$p, cc_out:$s)>;
5266 let TwoOperandAliasConstraint = "$Rn = $Rd" in {
5267 def ASRr : ARMAsmPseudo<"asr${s}${p} $Rd, $Rn, $Rm",
5268 (ins GPRnopc:$Rd, GPRnopc:$Rn, GPRnopc:$Rm, pred:$p,
5270 def LSRr : ARMAsmPseudo<"lsr${s}${p} $Rd, $Rn, $Rm",
5271 (ins GPRnopc:$Rd, GPRnopc:$Rn, GPRnopc:$Rm, pred:$p,
5273 def LSLr : ARMAsmPseudo<"lsl${s}${p} $Rd, $Rn, $Rm",
5274 (ins GPRnopc:$Rd, GPRnopc:$Rn, GPRnopc:$Rm, pred:$p,
5276 def RORr : ARMAsmPseudo<"ror${s}${p} $Rd, $Rn, $Rm",
5277 (ins GPRnopc:$Rd, GPRnopc:$Rn, GPRnopc:$Rm, pred:$p,
5281 // "neg" is and alias for "rsb rd, rn, #0"
5282 def : ARMInstAlias<"neg${s}${p} $Rd, $Rm",
5283 (RSBri GPR:$Rd, GPR:$Rm, 0, pred:$p, cc_out:$s)>;
5285 // Pre-v6, 'mov r0, r0' was used as a NOP encoding.
5286 def : InstAlias<"nop${p}", (MOVr R0, R0, pred:$p, zero_reg)>,
5287 Requires<[IsARM, NoV6]>;
5289 // UMULL/SMULL are available on all arches, but the instruction definitions
5290 // need difference constraints pre-v6. Use these aliases for the assembly
5291 // parsing on pre-v6.
5292 def : InstAlias<"smull${s}${p} $RdLo, $RdHi, $Rn, $Rm",
5293 (SMULL GPR:$RdLo, GPR:$RdHi, GPR:$Rn, GPR:$Rm, pred:$p, cc_out:$s)>,
5294 Requires<[IsARM, NoV6]>;
5295 def : InstAlias<"umull${s}${p} $RdLo, $RdHi, $Rn, $Rm",
5296 (UMULL GPR:$RdLo, GPR:$RdHi, GPR:$Rn, GPR:$Rm, pred:$p, cc_out:$s)>,
5297 Requires<[IsARM, NoV6]>;
5299 // 'it' blocks in ARM mode just validate the predicates. The IT itself
5301 def ITasm : ARMAsmPseudo<"it$mask $cc", (ins it_pred:$cc, it_mask:$mask)>;