1 //===- ARMInstrInfo.td - Target Description for ARM Target -*- tablegen -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file describes the ARM instructions in TableGen format.
12 //===----------------------------------------------------------------------===//
14 //===----------------------------------------------------------------------===//
15 // ARM specific DAG Nodes.
19 def SDT_ARMCallSeqStart : SDCallSeqStart<[ SDTCisVT<0, i32> ]>;
20 def SDT_ARMCallSeqEnd : SDCallSeqEnd<[ SDTCisVT<0, i32>, SDTCisVT<1, i32> ]>;
22 def SDT_ARMSaveCallPC : SDTypeProfile<0, 1, []>;
24 def SDT_ARMcall : SDTypeProfile<0, -1, [SDTCisInt<0>]>;
26 def SDT_ARMCMov : SDTypeProfile<1, 3,
27 [SDTCisSameAs<0, 1>, SDTCisSameAs<0, 2>,
30 def SDT_ARMBrcond : SDTypeProfile<0, 2,
31 [SDTCisVT<0, OtherVT>, SDTCisVT<1, i32>]>;
33 def SDT_ARMBrJT : SDTypeProfile<0, 3,
34 [SDTCisPtrTy<0>, SDTCisVT<1, i32>,
37 def SDT_ARMBr2JT : SDTypeProfile<0, 4,
38 [SDTCisPtrTy<0>, SDTCisVT<1, i32>,
39 SDTCisVT<2, i32>, SDTCisVT<3, i32>]>;
41 def SDT_ARMCmp : SDTypeProfile<0, 2, [SDTCisSameAs<0, 1>]>;
43 def SDT_ARMPICAdd : SDTypeProfile<1, 2, [SDTCisSameAs<0, 1>,
44 SDTCisPtrTy<1>, SDTCisVT<2, i32>]>;
46 def SDT_ARMThreadPointer : SDTypeProfile<1, 0, [SDTCisPtrTy<0>]>;
47 def SDT_ARMEH_SJLJ_Setjmp : SDTypeProfile<1, 2, [SDTCisInt<0>, SDTCisPtrTy<1>,
50 def SDT_ARMMEMBARRIERV7 : SDTypeProfile<0, 0, []>;
51 def SDT_ARMSYNCBARRIERV7 : SDTypeProfile<0, 0, []>;
52 def SDT_ARMMEMBARRIERV6 : SDTypeProfile<0, 1, [SDTCisInt<0>]>;
53 def SDT_ARMSYNCBARRIERV6 : SDTypeProfile<0, 1, [SDTCisInt<0>]>;
56 def ARMWrapper : SDNode<"ARMISD::Wrapper", SDTIntUnaryOp>;
57 def ARMWrapperJT : SDNode<"ARMISD::WrapperJT", SDTIntBinOp>;
59 def ARMcallseq_start : SDNode<"ISD::CALLSEQ_START", SDT_ARMCallSeqStart,
60 [SDNPHasChain, SDNPOutFlag]>;
61 def ARMcallseq_end : SDNode<"ISD::CALLSEQ_END", SDT_ARMCallSeqEnd,
62 [SDNPHasChain, SDNPOptInFlag, SDNPOutFlag]>;
64 def ARMcall : SDNode<"ARMISD::CALL", SDT_ARMcall,
65 [SDNPHasChain, SDNPOptInFlag, SDNPOutFlag]>;
66 def ARMcall_pred : SDNode<"ARMISD::CALL_PRED", SDT_ARMcall,
67 [SDNPHasChain, SDNPOptInFlag, SDNPOutFlag]>;
68 def ARMcall_nolink : SDNode<"ARMISD::CALL_NOLINK", SDT_ARMcall,
69 [SDNPHasChain, SDNPOptInFlag, SDNPOutFlag]>;
71 def ARMretflag : SDNode<"ARMISD::RET_FLAG", SDTNone,
72 [SDNPHasChain, SDNPOptInFlag]>;
74 def ARMcmov : SDNode<"ARMISD::CMOV", SDT_ARMCMov,
76 def ARMcneg : SDNode<"ARMISD::CNEG", SDT_ARMCMov,
79 def ARMbrcond : SDNode<"ARMISD::BRCOND", SDT_ARMBrcond,
80 [SDNPHasChain, SDNPInFlag, SDNPOutFlag]>;
82 def ARMbrjt : SDNode<"ARMISD::BR_JT", SDT_ARMBrJT,
84 def ARMbr2jt : SDNode<"ARMISD::BR2_JT", SDT_ARMBr2JT,
87 def ARMcmp : SDNode<"ARMISD::CMP", SDT_ARMCmp,
90 def ARMcmpZ : SDNode<"ARMISD::CMPZ", SDT_ARMCmp,
91 [SDNPOutFlag,SDNPCommutative]>;
93 def ARMpic_add : SDNode<"ARMISD::PIC_ADD", SDT_ARMPICAdd>;
95 def ARMsrl_flag : SDNode<"ARMISD::SRL_FLAG", SDTIntUnaryOp, [SDNPOutFlag]>;
96 def ARMsra_flag : SDNode<"ARMISD::SRA_FLAG", SDTIntUnaryOp, [SDNPOutFlag]>;
97 def ARMrrx : SDNode<"ARMISD::RRX" , SDTIntUnaryOp, [SDNPInFlag ]>;
99 def ARMthread_pointer: SDNode<"ARMISD::THREAD_POINTER", SDT_ARMThreadPointer>;
100 def ARMeh_sjlj_setjmp: SDNode<"ARMISD::EH_SJLJ_SETJMP", SDT_ARMEH_SJLJ_Setjmp>;
102 def ARMMemBarrierV7 : SDNode<"ARMISD::MEMBARRIER", SDT_ARMMEMBARRIERV7,
104 def ARMSyncBarrierV7 : SDNode<"ARMISD::SYNCBARRIER", SDT_ARMMEMBARRIERV7,
106 def ARMMemBarrierV6 : SDNode<"ARMISD::MEMBARRIER", SDT_ARMMEMBARRIERV6,
108 def ARMSyncBarrierV6 : SDNode<"ARMISD::SYNCBARRIER", SDT_ARMMEMBARRIERV6,
111 def ARMrbit : SDNode<"ARMISD::RBIT", SDTIntUnaryOp>;
113 //===----------------------------------------------------------------------===//
114 // ARM Instruction Predicate Definitions.
116 def HasV5T : Predicate<"Subtarget->hasV5TOps()">;
117 def HasV5TE : Predicate<"Subtarget->hasV5TEOps()">;
118 def HasV6 : Predicate<"Subtarget->hasV6Ops()">;
119 def HasV6T2 : Predicate<"Subtarget->hasV6T2Ops()">;
120 def NoV6T2 : Predicate<"!Subtarget->hasV6T2Ops()">;
121 def HasV7 : Predicate<"Subtarget->hasV7Ops()">;
122 def HasVFP2 : Predicate<"Subtarget->hasVFP2()">;
123 def HasVFP3 : Predicate<"Subtarget->hasVFP3()">;
124 def HasNEON : Predicate<"Subtarget->hasNEON()">;
125 def UseNEONForFP : Predicate<"Subtarget->useNEONForSinglePrecisionFP()">;
126 def DontUseNEONForFP : Predicate<"!Subtarget->useNEONForSinglePrecisionFP()">;
127 def IsThumb : Predicate<"Subtarget->isThumb()">;
128 def IsThumb1Only : Predicate<"Subtarget->isThumb1Only()">;
129 def IsThumb2 : Predicate<"Subtarget->isThumb2()">;
130 def IsARM : Predicate<"!Subtarget->isThumb()">;
131 def IsDarwin : Predicate<"Subtarget->isTargetDarwin()">;
132 def IsNotDarwin : Predicate<"!Subtarget->isTargetDarwin()">;
133 def CarryDefIsUnused : Predicate<"!N->hasAnyUseOfValue(1)">;
134 def CarryDefIsUsed : Predicate<"N->hasAnyUseOfValue(1)">;
136 // FIXME: Eventually this will be just "hasV6T2Ops".
137 def UseMovt : Predicate<"Subtarget->useMovt()">;
138 def DontUseMovt : Predicate<"!Subtarget->useMovt()">;
140 //===----------------------------------------------------------------------===//
141 // ARM Flag Definitions.
143 class RegConstraint<string C> {
144 string Constraints = C;
147 //===----------------------------------------------------------------------===//
148 // ARM specific transformation functions and pattern fragments.
151 // so_imm_neg_XFORM - Return a so_imm value packed into the format described for
152 // so_imm_neg def below.
153 def so_imm_neg_XFORM : SDNodeXForm<imm, [{
154 return CurDAG->getTargetConstant(-(int)N->getZExtValue(), MVT::i32);
157 // so_imm_not_XFORM - Return a so_imm value packed into the format described for
158 // so_imm_not def below.
159 def so_imm_not_XFORM : SDNodeXForm<imm, [{
160 return CurDAG->getTargetConstant(~(int)N->getZExtValue(), MVT::i32);
163 // rot_imm predicate - True if the 32-bit immediate is equal to 8, 16, or 24.
164 def rot_imm : PatLeaf<(i32 imm), [{
165 int32_t v = (int32_t)N->getZExtValue();
166 return v == 8 || v == 16 || v == 24;
169 /// imm1_15 predicate - True if the 32-bit immediate is in the range [1,15].
170 def imm1_15 : PatLeaf<(i32 imm), [{
171 return (int32_t)N->getZExtValue() >= 1 && (int32_t)N->getZExtValue() < 16;
174 /// imm16_31 predicate - True if the 32-bit immediate is in the range [16,31].
175 def imm16_31 : PatLeaf<(i32 imm), [{
176 return (int32_t)N->getZExtValue() >= 16 && (int32_t)N->getZExtValue() < 32;
181 return ARM_AM::getSOImmVal(-(int)N->getZExtValue()) != -1;
182 }], so_imm_neg_XFORM>;
186 return ARM_AM::getSOImmVal(~(int)N->getZExtValue()) != -1;
187 }], so_imm_not_XFORM>;
189 // sext_16_node predicate - True if the SDNode is sign-extended 16 or more bits.
190 def sext_16_node : PatLeaf<(i32 GPR:$a), [{
191 return CurDAG->ComputeNumSignBits(SDValue(N,0)) >= 17;
194 /// bf_inv_mask_imm predicate - An AND mask to clear an arbitrary width bitfield
196 def bf_inv_mask_imm : Operand<i32>,
198 uint32_t v = (uint32_t)N->getZExtValue();
201 // there can be 1's on either or both "outsides", all the "inside"
203 unsigned int lsb = 0, msb = 31;
204 while (v & (1 << msb)) --msb;
205 while (v & (1 << lsb)) ++lsb;
206 for (unsigned int i = lsb; i <= msb; ++i) {
212 let PrintMethod = "printBitfieldInvMaskImmOperand";
215 /// Split a 32-bit immediate into two 16 bit parts.
216 def lo16 : SDNodeXForm<imm, [{
217 return CurDAG->getTargetConstant((uint32_t)N->getZExtValue() & 0xffff,
221 def hi16 : SDNodeXForm<imm, [{
222 return CurDAG->getTargetConstant((uint32_t)N->getZExtValue() >> 16, MVT::i32);
225 def lo16AllZero : PatLeaf<(i32 imm), [{
226 // Returns true if all low 16-bits are 0.
227 return (((uint32_t)N->getZExtValue()) & 0xFFFFUL) == 0;
230 /// imm0_65535 predicate - True if the 32-bit immediate is in the range
232 def imm0_65535 : PatLeaf<(i32 imm), [{
233 return (uint32_t)N->getZExtValue() < 65536;
236 class BinOpFrag<dag res> : PatFrag<(ops node:$LHS, node:$RHS), res>;
237 class UnOpFrag <dag res> : PatFrag<(ops node:$Src), res>;
239 //===----------------------------------------------------------------------===//
240 // Operand Definitions.
244 def brtarget : Operand<OtherVT>;
246 // A list of registers separated by comma. Used by load/store multiple.
247 def reglist : Operand<i32> {
248 let PrintMethod = "printRegisterList";
251 // An operand for the CONSTPOOL_ENTRY pseudo-instruction.
252 def cpinst_operand : Operand<i32> {
253 let PrintMethod = "printCPInstOperand";
256 def jtblock_operand : Operand<i32> {
257 let PrintMethod = "printJTBlockOperand";
259 def jt2block_operand : Operand<i32> {
260 let PrintMethod = "printJT2BlockOperand";
264 def pclabel : Operand<i32> {
265 let PrintMethod = "printPCLabel";
268 // shifter_operand operands: so_reg and so_imm.
269 def so_reg : Operand<i32>, // reg reg imm
270 ComplexPattern<i32, 3, "SelectShifterOperandReg",
271 [shl,srl,sra,rotr]> {
272 let PrintMethod = "printSORegOperand";
273 let MIOperandInfo = (ops GPR, GPR, i32imm);
276 // so_imm - Match a 32-bit shifter_operand immediate operand, which is an
277 // 8-bit immediate rotated by an arbitrary number of bits. so_imm values are
278 // represented in the imm field in the same 12-bit form that they are encoded
279 // into so_imm instructions: the 8-bit immediate is the least significant bits
280 // [bits 0-7], the 4-bit shift amount is the next 4 bits [bits 8-11].
281 def so_imm : Operand<i32>,
283 return ARM_AM::getSOImmVal(N->getZExtValue()) != -1;
285 let PrintMethod = "printSOImmOperand";
288 // Break so_imm's up into two pieces. This handles immediates with up to 16
289 // bits set in them. This uses so_imm2part to match and so_imm2part_[12] to
290 // get the first/second pieces.
291 def so_imm2part : Operand<i32>,
293 return ARM_AM::isSOImmTwoPartVal((unsigned)N->getZExtValue());
295 let PrintMethod = "printSOImm2PartOperand";
298 def so_imm2part_1 : SDNodeXForm<imm, [{
299 unsigned V = ARM_AM::getSOImmTwoPartFirst((unsigned)N->getZExtValue());
300 return CurDAG->getTargetConstant(V, MVT::i32);
303 def so_imm2part_2 : SDNodeXForm<imm, [{
304 unsigned V = ARM_AM::getSOImmTwoPartSecond((unsigned)N->getZExtValue());
305 return CurDAG->getTargetConstant(V, MVT::i32);
308 def so_neg_imm2part : Operand<i32>, PatLeaf<(imm), [{
309 return ARM_AM::isSOImmTwoPartVal(-(int)N->getZExtValue());
311 let PrintMethod = "printSOImm2PartOperand";
314 def so_neg_imm2part_1 : SDNodeXForm<imm, [{
315 unsigned V = ARM_AM::getSOImmTwoPartFirst(-(int)N->getZExtValue());
316 return CurDAG->getTargetConstant(V, MVT::i32);
319 def so_neg_imm2part_2 : SDNodeXForm<imm, [{
320 unsigned V = ARM_AM::getSOImmTwoPartSecond(-(int)N->getZExtValue());
321 return CurDAG->getTargetConstant(V, MVT::i32);
324 /// imm0_31 predicate - True if the 32-bit immediate is in the range [0,31].
325 def imm0_31 : Operand<i32>, PatLeaf<(imm), [{
326 return (int32_t)N->getZExtValue() < 32;
329 // Define ARM specific addressing modes.
331 // addrmode2 := reg +/- reg shop imm
332 // addrmode2 := reg +/- imm12
334 def addrmode2 : Operand<i32>,
335 ComplexPattern<i32, 3, "SelectAddrMode2", []> {
336 let PrintMethod = "printAddrMode2Operand";
337 let MIOperandInfo = (ops GPR:$base, GPR:$offsreg, i32imm:$offsimm);
340 def am2offset : Operand<i32>,
341 ComplexPattern<i32, 2, "SelectAddrMode2Offset", []> {
342 let PrintMethod = "printAddrMode2OffsetOperand";
343 let MIOperandInfo = (ops GPR, i32imm);
346 // addrmode3 := reg +/- reg
347 // addrmode3 := reg +/- imm8
349 def addrmode3 : Operand<i32>,
350 ComplexPattern<i32, 3, "SelectAddrMode3", []> {
351 let PrintMethod = "printAddrMode3Operand";
352 let MIOperandInfo = (ops GPR:$base, GPR:$offsreg, i32imm:$offsimm);
355 def am3offset : Operand<i32>,
356 ComplexPattern<i32, 2, "SelectAddrMode3Offset", []> {
357 let PrintMethod = "printAddrMode3OffsetOperand";
358 let MIOperandInfo = (ops GPR, i32imm);
361 // addrmode4 := reg, <mode|W>
363 def addrmode4 : Operand<i32>,
364 ComplexPattern<i32, 2, "SelectAddrMode4", []> {
365 let PrintMethod = "printAddrMode4Operand";
366 let MIOperandInfo = (ops GPR, i32imm);
369 // addrmode5 := reg +/- imm8*4
371 def addrmode5 : Operand<i32>,
372 ComplexPattern<i32, 2, "SelectAddrMode5", []> {
373 let PrintMethod = "printAddrMode5Operand";
374 let MIOperandInfo = (ops GPR, i32imm);
377 // addrmode6 := reg with optional writeback
379 def addrmode6 : Operand<i32>,
380 ComplexPattern<i32, 4, "SelectAddrMode6", []> {
381 let PrintMethod = "printAddrMode6Operand";
382 let MIOperandInfo = (ops GPR:$addr, GPR:$upd, i32imm, i32imm);
385 // addrmodepc := pc + reg
387 def addrmodepc : Operand<i32>,
388 ComplexPattern<i32, 2, "SelectAddrModePC", []> {
389 let PrintMethod = "printAddrModePCOperand";
390 let MIOperandInfo = (ops GPR, i32imm);
393 def nohash_imm : Operand<i32> {
394 let PrintMethod = "printNoHashImmediate";
397 //===----------------------------------------------------------------------===//
399 include "ARMInstrFormats.td"
401 //===----------------------------------------------------------------------===//
402 // Multiclass helpers...
405 /// AsI1_bin_irs - Defines a set of (op r, {so_imm|r|so_reg}) patterns for a
406 /// binop that produces a value.
407 multiclass AsI1_bin_irs<bits<4> opcod, string opc, PatFrag opnode,
408 bit Commutable = 0> {
409 def ri : AsI1<opcod, (outs GPR:$dst), (ins GPR:$a, so_imm:$b), DPFrm,
410 IIC_iALUi, opc, "\t$dst, $a, $b",
411 [(set GPR:$dst, (opnode GPR:$a, so_imm:$b))]> {
414 def rr : AsI1<opcod, (outs GPR:$dst), (ins GPR:$a, GPR:$b), DPFrm,
415 IIC_iALUr, opc, "\t$dst, $a, $b",
416 [(set GPR:$dst, (opnode GPR:$a, GPR:$b))]> {
417 let Inst{11-4} = 0b00000000;
419 let isCommutable = Commutable;
421 def rs : AsI1<opcod, (outs GPR:$dst), (ins GPR:$a, so_reg:$b), DPSoRegFrm,
422 IIC_iALUsr, opc, "\t$dst, $a, $b",
423 [(set GPR:$dst, (opnode GPR:$a, so_reg:$b))]> {
428 /// AI1_bin_s_irs - Similar to AsI1_bin_irs except it sets the 's' bit so the
429 /// instruction modifies the CPSR register.
430 let Defs = [CPSR] in {
431 multiclass AI1_bin_s_irs<bits<4> opcod, string opc, PatFrag opnode,
432 bit Commutable = 0> {
433 def ri : AI1<opcod, (outs GPR:$dst), (ins GPR:$a, so_imm:$b), DPFrm,
434 IIC_iALUi, opc, "\t$dst, $a, $b",
435 [(set GPR:$dst, (opnode GPR:$a, so_imm:$b))]> {
439 def rr : AI1<opcod, (outs GPR:$dst), (ins GPR:$a, GPR:$b), DPFrm,
440 IIC_iALUr, opc, "\t$dst, $a, $b",
441 [(set GPR:$dst, (opnode GPR:$a, GPR:$b))]> {
442 let isCommutable = Commutable;
443 let Inst{11-4} = 0b00000000;
447 def rs : AI1<opcod, (outs GPR:$dst), (ins GPR:$a, so_reg:$b), DPSoRegFrm,
448 IIC_iALUsr, opc, "\t$dst, $a, $b",
449 [(set GPR:$dst, (opnode GPR:$a, so_reg:$b))]> {
456 /// AI1_cmp_irs - Defines a set of (op r, {so_imm|r|so_reg}) cmp / test
457 /// patterns. Similar to AsI1_bin_irs except the instruction does not produce
458 /// a explicit result, only implicitly set CPSR.
459 let Defs = [CPSR] in {
460 multiclass AI1_cmp_irs<bits<4> opcod, string opc, PatFrag opnode,
461 bit Commutable = 0> {
462 def ri : AI1<opcod, (outs), (ins GPR:$a, so_imm:$b), DPFrm, IIC_iCMPi,
464 [(opnode GPR:$a, so_imm:$b)]> {
468 def rr : AI1<opcod, (outs), (ins GPR:$a, GPR:$b), DPFrm, IIC_iCMPr,
470 [(opnode GPR:$a, GPR:$b)]> {
471 let Inst{11-4} = 0b00000000;
474 let isCommutable = Commutable;
476 def rs : AI1<opcod, (outs), (ins GPR:$a, so_reg:$b), DPSoRegFrm, IIC_iCMPsr,
478 [(opnode GPR:$a, so_reg:$b)]> {
485 /// AI_unary_rrot - A unary operation with two forms: one whose operand is a
486 /// register and one whose operand is a register rotated by 8/16/24.
487 /// FIXME: Remove the 'r' variant. Its rot_imm is zero.
488 multiclass AI_unary_rrot<bits<8> opcod, string opc, PatFrag opnode> {
489 def r : AExtI<opcod, (outs GPR:$dst), (ins GPR:$src),
490 IIC_iUNAr, opc, "\t$dst, $src",
491 [(set GPR:$dst, (opnode GPR:$src))]>,
492 Requires<[IsARM, HasV6]> {
493 let Inst{11-10} = 0b00;
494 let Inst{19-16} = 0b1111;
496 def r_rot : AExtI<opcod, (outs GPR:$dst), (ins GPR:$src, i32imm:$rot),
497 IIC_iUNAsi, opc, "\t$dst, $src, ror $rot",
498 [(set GPR:$dst, (opnode (rotr GPR:$src, rot_imm:$rot)))]>,
499 Requires<[IsARM, HasV6]> {
500 let Inst{19-16} = 0b1111;
504 /// AI_bin_rrot - A binary operation with two forms: one whose operand is a
505 /// register and one whose operand is a register rotated by 8/16/24.
506 multiclass AI_bin_rrot<bits<8> opcod, string opc, PatFrag opnode> {
507 def rr : AExtI<opcod, (outs GPR:$dst), (ins GPR:$LHS, GPR:$RHS),
508 IIC_iALUr, opc, "\t$dst, $LHS, $RHS",
509 [(set GPR:$dst, (opnode GPR:$LHS, GPR:$RHS))]>,
510 Requires<[IsARM, HasV6]> {
511 let Inst{11-10} = 0b00;
513 def rr_rot : AExtI<opcod, (outs GPR:$dst), (ins GPR:$LHS, GPR:$RHS, i32imm:$rot),
514 IIC_iALUsi, opc, "\t$dst, $LHS, $RHS, ror $rot",
515 [(set GPR:$dst, (opnode GPR:$LHS,
516 (rotr GPR:$RHS, rot_imm:$rot)))]>,
517 Requires<[IsARM, HasV6]>;
520 /// AI1_adde_sube_irs - Define instructions and patterns for adde and sube.
521 let Uses = [CPSR] in {
522 multiclass AI1_adde_sube_irs<bits<4> opcod, string opc, PatFrag opnode,
523 bit Commutable = 0> {
524 def ri : AsI1<opcod, (outs GPR:$dst), (ins GPR:$a, so_imm:$b),
525 DPFrm, IIC_iALUi, opc, "\t$dst, $a, $b",
526 [(set GPR:$dst, (opnode GPR:$a, so_imm:$b))]>,
527 Requires<[IsARM, CarryDefIsUnused]> {
530 def rr : AsI1<opcod, (outs GPR:$dst), (ins GPR:$a, GPR:$b),
531 DPFrm, IIC_iALUr, opc, "\t$dst, $a, $b",
532 [(set GPR:$dst, (opnode GPR:$a, GPR:$b))]>,
533 Requires<[IsARM, CarryDefIsUnused]> {
534 let isCommutable = Commutable;
535 let Inst{11-4} = 0b00000000;
538 def rs : AsI1<opcod, (outs GPR:$dst), (ins GPR:$a, so_reg:$b),
539 DPSoRegFrm, IIC_iALUsr, opc, "\t$dst, $a, $b",
540 [(set GPR:$dst, (opnode GPR:$a, so_reg:$b))]>,
541 Requires<[IsARM, CarryDefIsUnused]> {
545 // Carry setting variants
546 let Defs = [CPSR] in {
547 multiclass AI1_adde_sube_s_irs<bits<4> opcod, string opc, PatFrag opnode,
548 bit Commutable = 0> {
549 def Sri : AXI1<opcod, (outs GPR:$dst), (ins GPR:$a, so_imm:$b),
550 DPFrm, IIC_iALUi, !strconcat(opc, "\t$dst, $a, $b"),
551 [(set GPR:$dst, (opnode GPR:$a, so_imm:$b))]>,
552 Requires<[IsARM, CarryDefIsUsed]> {
557 def Srr : AXI1<opcod, (outs GPR:$dst), (ins GPR:$a, GPR:$b),
558 DPFrm, IIC_iALUr, !strconcat(opc, "\t$dst, $a, $b"),
559 [(set GPR:$dst, (opnode GPR:$a, GPR:$b))]>,
560 Requires<[IsARM, CarryDefIsUsed]> {
562 let Inst{11-4} = 0b00000000;
566 def Srs : AXI1<opcod, (outs GPR:$dst), (ins GPR:$a, so_reg:$b),
567 DPSoRegFrm, IIC_iALUsr, !strconcat(opc, "\t$dst, $a, $b"),
568 [(set GPR:$dst, (opnode GPR:$a, so_reg:$b))]>,
569 Requires<[IsARM, CarryDefIsUsed]> {
578 //===----------------------------------------------------------------------===//
580 //===----------------------------------------------------------------------===//
582 //===----------------------------------------------------------------------===//
583 // Miscellaneous Instructions.
586 /// CONSTPOOL_ENTRY - This instruction represents a floating constant pool in
587 /// the function. The first operand is the ID# for this instruction, the second
588 /// is the index into the MachineConstantPool that this is, the third is the
589 /// size in bytes of this constant pool entry.
590 let neverHasSideEffects = 1, isNotDuplicable = 1 in
591 def CONSTPOOL_ENTRY :
592 PseudoInst<(outs), (ins cpinst_operand:$instid, cpinst_operand:$cpidx,
593 i32imm:$size), NoItinerary,
594 "${instid:label} ${cpidx:cpentry}", []>;
596 let Defs = [SP], Uses = [SP] in {
598 PseudoInst<(outs), (ins i32imm:$amt1, i32imm:$amt2, pred:$p), NoItinerary,
599 "@ ADJCALLSTACKUP $amt1",
600 [(ARMcallseq_end timm:$amt1, timm:$amt2)]>;
602 def ADJCALLSTACKDOWN :
603 PseudoInst<(outs), (ins i32imm:$amt, pred:$p), NoItinerary,
604 "@ ADJCALLSTACKDOWN $amt",
605 [(ARMcallseq_start timm:$amt)]>;
608 // Address computation and loads and stores in PIC mode.
609 let isNotDuplicable = 1 in {
610 def PICADD : AXI1<0b0100, (outs GPR:$dst), (ins GPR:$a, pclabel:$cp, pred:$p),
611 Pseudo, IIC_iALUr, "\n$cp:\n\tadd$p\t$dst, pc, $a",
612 [(set GPR:$dst, (ARMpic_add GPR:$a, imm:$cp))]>;
614 let AddedComplexity = 10 in {
615 def PICLDR : AXI2ldw<(outs GPR:$dst), (ins addrmodepc:$addr, pred:$p),
616 Pseudo, IIC_iLoadr, "\n${addr:label}:\n\tldr$p\t$dst, $addr",
617 [(set GPR:$dst, (load addrmodepc:$addr))]>;
619 def PICLDRH : AXI3ldh<(outs GPR:$dst), (ins addrmodepc:$addr, pred:$p),
620 Pseudo, IIC_iLoadr, "\n${addr:label}:\n\tldrh${p}\t$dst, $addr",
621 [(set GPR:$dst, (zextloadi16 addrmodepc:$addr))]>;
623 def PICLDRB : AXI2ldb<(outs GPR:$dst), (ins addrmodepc:$addr, pred:$p),
624 Pseudo, IIC_iLoadr, "\n${addr:label}:\n\tldrb${p}\t$dst, $addr",
625 [(set GPR:$dst, (zextloadi8 addrmodepc:$addr))]>;
627 def PICLDRSH : AXI3ldsh<(outs GPR:$dst), (ins addrmodepc:$addr, pred:$p),
628 Pseudo, IIC_iLoadr, "\n${addr:label}:\n\tldrsh${p}\t$dst, $addr",
629 [(set GPR:$dst, (sextloadi16 addrmodepc:$addr))]>;
631 def PICLDRSB : AXI3ldsb<(outs GPR:$dst), (ins addrmodepc:$addr, pred:$p),
632 Pseudo, IIC_iLoadr, "\n${addr:label}:\n\tldrsb${p}\t$dst, $addr",
633 [(set GPR:$dst, (sextloadi8 addrmodepc:$addr))]>;
635 let AddedComplexity = 10 in {
636 def PICSTR : AXI2stw<(outs), (ins GPR:$src, addrmodepc:$addr, pred:$p),
637 Pseudo, IIC_iStorer, "\n${addr:label}:\n\tstr$p\t$src, $addr",
638 [(store GPR:$src, addrmodepc:$addr)]>;
640 def PICSTRH : AXI3sth<(outs), (ins GPR:$src, addrmodepc:$addr, pred:$p),
641 Pseudo, IIC_iStorer, "\n${addr:label}:\n\tstrh${p}\t$src, $addr",
642 [(truncstorei16 GPR:$src, addrmodepc:$addr)]>;
644 def PICSTRB : AXI2stb<(outs), (ins GPR:$src, addrmodepc:$addr, pred:$p),
645 Pseudo, IIC_iStorer, "\n${addr:label}:\n\tstrb${p}\t$src, $addr",
646 [(truncstorei8 GPR:$src, addrmodepc:$addr)]>;
648 } // isNotDuplicable = 1
651 // LEApcrel - Load a pc-relative address into a register without offending the
653 def LEApcrel : AXI1<0x0, (outs GPR:$dst), (ins i32imm:$label, pred:$p),
655 !strconcat(!strconcat(".set ${:private}PCRELV${:uid}, ($label-(",
656 "${:private}PCRELL${:uid}+8))\n"),
657 !strconcat("${:private}PCRELL${:uid}:\n\t",
658 "add$p\t$dst, pc, #${:private}PCRELV${:uid}")),
661 def LEApcrelJT : AXI1<0x0, (outs GPR:$dst),
662 (ins i32imm:$label, nohash_imm:$id, pred:$p),
664 !strconcat(!strconcat(".set ${:private}PCRELV${:uid}, "
666 "${:private}PCRELL${:uid}+8))\n"),
667 !strconcat("${:private}PCRELL${:uid}:\n\t",
668 "add$p\t$dst, pc, #${:private}PCRELV${:uid}")),
673 //===----------------------------------------------------------------------===//
674 // Control Flow Instructions.
677 let isReturn = 1, isTerminator = 1, isBarrier = 1 in
678 def BX_RET : AI<(outs), (ins), BrMiscFrm, IIC_Br,
679 "bx", "\tlr", [(ARMretflag)]> {
680 let Inst{3-0} = 0b1110;
681 let Inst{7-4} = 0b0001;
682 let Inst{19-8} = 0b111111111111;
683 let Inst{27-20} = 0b00010010;
687 let isBranch = 1, isTerminator = 1, isBarrier = 1, isIndirectBranch = 1 in {
688 def BRIND : AXI<(outs), (ins GPR:$dst), BrMiscFrm, IIC_Br, "bx\t$dst",
689 [(brind GPR:$dst)]> {
690 let Inst{7-4} = 0b0001;
691 let Inst{19-8} = 0b111111111111;
692 let Inst{27-20} = 0b00010010;
693 let Inst{31-28} = 0b1110;
697 // FIXME: remove when we have a way to marking a MI with these properties.
698 // FIXME: Should pc be an implicit operand like PICADD, etc?
699 let isReturn = 1, isTerminator = 1, isBarrier = 1, mayLoad = 1,
700 hasExtraDefRegAllocReq = 1 in
701 def LDM_RET : AXI4ld<(outs),
702 (ins addrmode4:$addr, pred:$p, reglist:$wb, variable_ops),
703 LdStMulFrm, IIC_Br, "ldm${addr:submode}${p}\t$addr, $wb",
706 // On non-Darwin platforms R9 is callee-saved.
708 Defs = [R0, R1, R2, R3, R12, LR,
709 D0, D1, D2, D3, D4, D5, D6, D7,
710 D16, D17, D18, D19, D20, D21, D22, D23,
711 D24, D25, D26, D27, D28, D29, D30, D31, CPSR, FPSCR] in {
712 def BL : ABXI<0b1011, (outs), (ins i32imm:$func, variable_ops),
713 IIC_Br, "bl\t${func:call}",
714 [(ARMcall tglobaladdr:$func)]>,
715 Requires<[IsARM, IsNotDarwin]> {
716 let Inst{31-28} = 0b1110;
719 def BL_pred : ABI<0b1011, (outs), (ins i32imm:$func, variable_ops),
720 IIC_Br, "bl", "\t${func:call}",
721 [(ARMcall_pred tglobaladdr:$func)]>,
722 Requires<[IsARM, IsNotDarwin]>;
725 def BLX : AXI<(outs), (ins GPR:$func, variable_ops), BrMiscFrm,
726 IIC_Br, "blx\t$func",
727 [(ARMcall GPR:$func)]>,
728 Requires<[IsARM, HasV5T, IsNotDarwin]> {
729 let Inst{7-4} = 0b0011;
730 let Inst{19-8} = 0b111111111111;
731 let Inst{27-20} = 0b00010010;
735 def BX : ABXIx2<(outs), (ins GPR:$func, variable_ops),
736 IIC_Br, "mov\tlr, pc\n\tbx\t$func",
737 [(ARMcall_nolink GPR:$func)]>,
738 Requires<[IsARM, IsNotDarwin]> {
739 let Inst{7-4} = 0b0001;
740 let Inst{19-8} = 0b111111111111;
741 let Inst{27-20} = 0b00010010;
745 // On Darwin R9 is call-clobbered.
747 Defs = [R0, R1, R2, R3, R9, R12, LR,
748 D0, D1, D2, D3, D4, D5, D6, D7,
749 D16, D17, D18, D19, D20, D21, D22, D23,
750 D24, D25, D26, D27, D28, D29, D30, D31, CPSR, FPSCR] in {
751 def BLr9 : ABXI<0b1011, (outs), (ins i32imm:$func, variable_ops),
752 IIC_Br, "bl\t${func:call}",
753 [(ARMcall tglobaladdr:$func)]>, Requires<[IsARM, IsDarwin]> {
754 let Inst{31-28} = 0b1110;
757 def BLr9_pred : ABI<0b1011, (outs), (ins i32imm:$func, variable_ops),
758 IIC_Br, "bl", "\t${func:call}",
759 [(ARMcall_pred tglobaladdr:$func)]>,
760 Requires<[IsARM, IsDarwin]>;
763 def BLXr9 : AXI<(outs), (ins GPR:$func, variable_ops), BrMiscFrm,
764 IIC_Br, "blx\t$func",
765 [(ARMcall GPR:$func)]>, Requires<[IsARM, HasV5T, IsDarwin]> {
766 let Inst{7-4} = 0b0011;
767 let Inst{19-8} = 0b111111111111;
768 let Inst{27-20} = 0b00010010;
772 def BXr9 : ABXIx2<(outs), (ins GPR:$func, variable_ops),
773 IIC_Br, "mov\tlr, pc\n\tbx\t$func",
774 [(ARMcall_nolink GPR:$func)]>, Requires<[IsARM, IsDarwin]> {
775 let Inst{7-4} = 0b0001;
776 let Inst{19-8} = 0b111111111111;
777 let Inst{27-20} = 0b00010010;
781 let isBranch = 1, isTerminator = 1 in {
782 // B is "predicable" since it can be xformed into a Bcc.
783 let isBarrier = 1 in {
784 let isPredicable = 1 in
785 def B : ABXI<0b1010, (outs), (ins brtarget:$target), IIC_Br,
786 "b\t$target", [(br bb:$target)]>;
788 let isNotDuplicable = 1, isIndirectBranch = 1 in {
789 def BR_JTr : JTI<(outs), (ins GPR:$target, jtblock_operand:$jt, i32imm:$id),
790 IIC_Br, "mov\tpc, $target \n$jt",
791 [(ARMbrjt GPR:$target, tjumptable:$jt, imm:$id)]> {
792 let Inst{11-4} = 0b00000000;
793 let Inst{15-12} = 0b1111;
794 let Inst{20} = 0; // S Bit
795 let Inst{24-21} = 0b1101;
796 let Inst{27-25} = 0b000;
798 def BR_JTm : JTI<(outs),
799 (ins addrmode2:$target, jtblock_operand:$jt, i32imm:$id),
800 IIC_Br, "ldr\tpc, $target \n$jt",
801 [(ARMbrjt (i32 (load addrmode2:$target)), tjumptable:$jt,
803 let Inst{15-12} = 0b1111;
804 let Inst{20} = 1; // L bit
805 let Inst{21} = 0; // W bit
806 let Inst{22} = 0; // B bit
807 let Inst{24} = 1; // P bit
808 let Inst{27-25} = 0b011;
810 def BR_JTadd : JTI<(outs),
811 (ins GPR:$target, GPR:$idx, jtblock_operand:$jt, i32imm:$id),
812 IIC_Br, "add\tpc, $target, $idx \n$jt",
813 [(ARMbrjt (add GPR:$target, GPR:$idx), tjumptable:$jt,
815 let Inst{15-12} = 0b1111;
816 let Inst{20} = 0; // S bit
817 let Inst{24-21} = 0b0100;
818 let Inst{27-25} = 0b000;
820 } // isNotDuplicable = 1, isIndirectBranch = 1
823 // FIXME: should be able to write a pattern for ARMBrcond, but can't use
824 // a two-value operand where a dag node expects two operands. :(
825 def Bcc : ABI<0b1010, (outs), (ins brtarget:$target),
826 IIC_Br, "b", "\t$target",
827 [/*(ARMbrcond bb:$target, imm:$cc, CCR:$ccr)*/]>;
830 //===----------------------------------------------------------------------===//
831 // Load / store Instructions.
835 let canFoldAsLoad = 1, isReMaterializable = 1, mayHaveSideEffects = 1 in
836 def LDR : AI2ldw<(outs GPR:$dst), (ins addrmode2:$addr), LdFrm, IIC_iLoadr,
837 "ldr", "\t$dst, $addr",
838 [(set GPR:$dst, (load addrmode2:$addr))]>;
840 // Special LDR for loads from non-pc-relative constpools.
841 let canFoldAsLoad = 1, mayLoad = 1, isReMaterializable = 1,
842 mayHaveSideEffects = 1 in
843 def LDRcp : AI2ldw<(outs GPR:$dst), (ins addrmode2:$addr), LdFrm, IIC_iLoadr,
844 "ldr", "\t$dst, $addr", []>;
846 // Loads with zero extension
847 def LDRH : AI3ldh<(outs GPR:$dst), (ins addrmode3:$addr), LdMiscFrm,
848 IIC_iLoadr, "ldrh", "\t$dst, $addr",
849 [(set GPR:$dst, (zextloadi16 addrmode3:$addr))]>;
851 def LDRB : AI2ldb<(outs GPR:$dst), (ins addrmode2:$addr), LdFrm,
852 IIC_iLoadr, "ldrb", "\t$dst, $addr",
853 [(set GPR:$dst, (zextloadi8 addrmode2:$addr))]>;
855 // Loads with sign extension
856 def LDRSH : AI3ldsh<(outs GPR:$dst), (ins addrmode3:$addr), LdMiscFrm,
857 IIC_iLoadr, "ldrsh", "\t$dst, $addr",
858 [(set GPR:$dst, (sextloadi16 addrmode3:$addr))]>;
860 def LDRSB : AI3ldsb<(outs GPR:$dst), (ins addrmode3:$addr), LdMiscFrm,
861 IIC_iLoadr, "ldrsb", "\t$dst, $addr",
862 [(set GPR:$dst, (sextloadi8 addrmode3:$addr))]>;
864 let mayLoad = 1, hasExtraDefRegAllocReq = 1 in {
866 def LDRD : AI3ldd<(outs GPR:$dst1, GPR:$dst2), (ins addrmode3:$addr), LdMiscFrm,
867 IIC_iLoadr, "ldrd", "\t$dst1, $addr",
868 []>, Requires<[IsARM, HasV5TE]>;
871 def LDR_PRE : AI2ldwpr<(outs GPR:$dst, GPR:$base_wb),
872 (ins addrmode2:$addr), LdFrm, IIC_iLoadru,
873 "ldr", "\t$dst, $addr!", "$addr.base = $base_wb", []>;
875 def LDR_POST : AI2ldwpo<(outs GPR:$dst, GPR:$base_wb),
876 (ins GPR:$base, am2offset:$offset), LdFrm, IIC_iLoadru,
877 "ldr", "\t$dst, [$base], $offset", "$base = $base_wb", []>;
879 def LDRH_PRE : AI3ldhpr<(outs GPR:$dst, GPR:$base_wb),
880 (ins addrmode3:$addr), LdMiscFrm, IIC_iLoadru,
881 "ldrh", "\t$dst, $addr!", "$addr.base = $base_wb", []>;
883 def LDRH_POST : AI3ldhpo<(outs GPR:$dst, GPR:$base_wb),
884 (ins GPR:$base,am3offset:$offset), LdMiscFrm, IIC_iLoadru,
885 "ldrh", "\t$dst, [$base], $offset", "$base = $base_wb", []>;
887 def LDRB_PRE : AI2ldbpr<(outs GPR:$dst, GPR:$base_wb),
888 (ins addrmode2:$addr), LdFrm, IIC_iLoadru,
889 "ldrb", "\t$dst, $addr!", "$addr.base = $base_wb", []>;
891 def LDRB_POST : AI2ldbpo<(outs GPR:$dst, GPR:$base_wb),
892 (ins GPR:$base,am2offset:$offset), LdFrm, IIC_iLoadru,
893 "ldrb", "\t$dst, [$base], $offset", "$base = $base_wb", []>;
895 def LDRSH_PRE : AI3ldshpr<(outs GPR:$dst, GPR:$base_wb),
896 (ins addrmode3:$addr), LdMiscFrm, IIC_iLoadru,
897 "ldrsh", "\t$dst, $addr!", "$addr.base = $base_wb", []>;
899 def LDRSH_POST: AI3ldshpo<(outs GPR:$dst, GPR:$base_wb),
900 (ins GPR:$base,am3offset:$offset), LdMiscFrm, IIC_iLoadru,
901 "ldrsh", "\t$dst, [$base], $offset", "$base = $base_wb", []>;
903 def LDRSB_PRE : AI3ldsbpr<(outs GPR:$dst, GPR:$base_wb),
904 (ins addrmode3:$addr), LdMiscFrm, IIC_iLoadru,
905 "ldrsb", "\t$dst, $addr!", "$addr.base = $base_wb", []>;
907 def LDRSB_POST: AI3ldsbpo<(outs GPR:$dst, GPR:$base_wb),
908 (ins GPR:$base,am3offset:$offset), LdMiscFrm, IIC_iLoadru,
909 "ldrsb", "\t$dst, [$base], $offset", "$base = $base_wb", []>;
913 def STR : AI2stw<(outs), (ins GPR:$src, addrmode2:$addr), StFrm, IIC_iStorer,
914 "str", "\t$src, $addr",
915 [(store GPR:$src, addrmode2:$addr)]>;
917 // Stores with truncate
918 def STRH : AI3sth<(outs), (ins GPR:$src, addrmode3:$addr), StMiscFrm, IIC_iStorer,
919 "strh", "\t$src, $addr",
920 [(truncstorei16 GPR:$src, addrmode3:$addr)]>;
922 def STRB : AI2stb<(outs), (ins GPR:$src, addrmode2:$addr), StFrm, IIC_iStorer,
923 "strb", "\t$src, $addr",
924 [(truncstorei8 GPR:$src, addrmode2:$addr)]>;
927 let mayStore = 1, hasExtraSrcRegAllocReq = 1 in
928 def STRD : AI3std<(outs), (ins GPR:$src1, GPR:$src2, addrmode3:$addr),
929 StMiscFrm, IIC_iStorer,
930 "strd", "\t$src1, $addr", []>, Requires<[IsARM, HasV5TE]>;
933 def STR_PRE : AI2stwpr<(outs GPR:$base_wb),
934 (ins GPR:$src, GPR:$base, am2offset:$offset),
936 "str", "\t$src, [$base, $offset]!", "$base = $base_wb",
938 (pre_store GPR:$src, GPR:$base, am2offset:$offset))]>;
940 def STR_POST : AI2stwpo<(outs GPR:$base_wb),
941 (ins GPR:$src, GPR:$base,am2offset:$offset),
943 "str", "\t$src, [$base], $offset", "$base = $base_wb",
945 (post_store GPR:$src, GPR:$base, am2offset:$offset))]>;
947 def STRH_PRE : AI3sthpr<(outs GPR:$base_wb),
948 (ins GPR:$src, GPR:$base,am3offset:$offset),
949 StMiscFrm, IIC_iStoreru,
950 "strh", "\t$src, [$base, $offset]!", "$base = $base_wb",
952 (pre_truncsti16 GPR:$src, GPR:$base,am3offset:$offset))]>;
954 def STRH_POST: AI3sthpo<(outs GPR:$base_wb),
955 (ins GPR:$src, GPR:$base,am3offset:$offset),
956 StMiscFrm, IIC_iStoreru,
957 "strh", "\t$src, [$base], $offset", "$base = $base_wb",
958 [(set GPR:$base_wb, (post_truncsti16 GPR:$src,
959 GPR:$base, am3offset:$offset))]>;
961 def STRB_PRE : AI2stbpr<(outs GPR:$base_wb),
962 (ins GPR:$src, GPR:$base,am2offset:$offset),
964 "strb", "\t$src, [$base, $offset]!", "$base = $base_wb",
965 [(set GPR:$base_wb, (pre_truncsti8 GPR:$src,
966 GPR:$base, am2offset:$offset))]>;
968 def STRB_POST: AI2stbpo<(outs GPR:$base_wb),
969 (ins GPR:$src, GPR:$base,am2offset:$offset),
971 "strb", "\t$src, [$base], $offset", "$base = $base_wb",
972 [(set GPR:$base_wb, (post_truncsti8 GPR:$src,
973 GPR:$base, am2offset:$offset))]>;
975 //===----------------------------------------------------------------------===//
976 // Load / store multiple Instructions.
979 let mayLoad = 1, hasExtraDefRegAllocReq = 1 in
980 def LDM : AXI4ld<(outs),
981 (ins addrmode4:$addr, pred:$p, reglist:$wb, variable_ops),
982 LdStMulFrm, IIC_iLoadm, "ldm${addr:submode}${p}\t$addr, $wb",
985 let mayStore = 1, hasExtraSrcRegAllocReq = 1 in
986 def STM : AXI4st<(outs),
987 (ins addrmode4:$addr, pred:$p, reglist:$wb, variable_ops),
988 LdStMulFrm, IIC_iStorem, "stm${addr:submode}${p}\t$addr, $wb",
991 //===----------------------------------------------------------------------===//
992 // Move Instructions.
995 let neverHasSideEffects = 1 in
996 def MOVr : AsI1<0b1101, (outs GPR:$dst), (ins GPR:$src), DPFrm, IIC_iMOVr,
997 "mov", "\t$dst, $src", []>, UnaryDP {
998 let Inst{11-4} = 0b00000000;
1002 def MOVs : AsI1<0b1101, (outs GPR:$dst), (ins so_reg:$src),
1003 DPSoRegFrm, IIC_iMOVsr,
1004 "mov", "\t$dst, $src", [(set GPR:$dst, so_reg:$src)]>, UnaryDP {
1008 let isReMaterializable = 1, isAsCheapAsAMove = 1 in
1009 def MOVi : AsI1<0b1101, (outs GPR:$dst), (ins so_imm:$src), DPFrm, IIC_iMOVi,
1010 "mov", "\t$dst, $src", [(set GPR:$dst, so_imm:$src)]>, UnaryDP {
1014 let isReMaterializable = 1, isAsCheapAsAMove = 1 in
1015 def MOVi16 : AI1<0b1000, (outs GPR:$dst), (ins i32imm:$src),
1017 "movw", "\t$dst, $src",
1018 [(set GPR:$dst, imm0_65535:$src)]>,
1019 Requires<[IsARM, HasV6T2]>, UnaryDP {
1024 let Constraints = "$src = $dst" in
1025 def MOVTi16 : AI1<0b1010, (outs GPR:$dst), (ins GPR:$src, i32imm:$imm),
1027 "movt", "\t$dst, $imm",
1029 (or (and GPR:$src, 0xffff),
1030 lo16AllZero:$imm))]>, UnaryDP,
1031 Requires<[IsARM, HasV6T2]> {
1036 def : ARMPat<(or GPR:$src, 0xffff0000), (MOVTi16 GPR:$src, 0xffff)>,
1037 Requires<[IsARM, HasV6T2]>;
1039 let Uses = [CPSR] in
1040 def MOVrx : AsI1<0b1101, (outs GPR:$dst), (ins GPR:$src), Pseudo, IIC_iMOVsi,
1041 "mov", "\t$dst, $src, rrx",
1042 [(set GPR:$dst, (ARMrrx GPR:$src))]>, UnaryDP;
1044 // These aren't really mov instructions, but we have to define them this way
1045 // due to flag operands.
1047 let Defs = [CPSR] in {
1048 def MOVsrl_flag : AI1<0b1101, (outs GPR:$dst), (ins GPR:$src), Pseudo,
1049 IIC_iMOVsi, "movs", "\t$dst, $src, lsr #1",
1050 [(set GPR:$dst, (ARMsrl_flag GPR:$src))]>, UnaryDP;
1051 def MOVsra_flag : AI1<0b1101, (outs GPR:$dst), (ins GPR:$src), Pseudo,
1052 IIC_iMOVsi, "movs", "\t$dst, $src, asr #1",
1053 [(set GPR:$dst, (ARMsra_flag GPR:$src))]>, UnaryDP;
1056 //===----------------------------------------------------------------------===//
1057 // Extend Instructions.
1062 defm SXTB : AI_unary_rrot<0b01101010,
1063 "sxtb", UnOpFrag<(sext_inreg node:$Src, i8)>>;
1064 defm SXTH : AI_unary_rrot<0b01101011,
1065 "sxth", UnOpFrag<(sext_inreg node:$Src, i16)>>;
1067 defm SXTAB : AI_bin_rrot<0b01101010,
1068 "sxtab", BinOpFrag<(add node:$LHS, (sext_inreg node:$RHS, i8))>>;
1069 defm SXTAH : AI_bin_rrot<0b01101011,
1070 "sxtah", BinOpFrag<(add node:$LHS, (sext_inreg node:$RHS,i16))>>;
1072 // TODO: SXT(A){B|H}16
1076 let AddedComplexity = 16 in {
1077 defm UXTB : AI_unary_rrot<0b01101110,
1078 "uxtb" , UnOpFrag<(and node:$Src, 0x000000FF)>>;
1079 defm UXTH : AI_unary_rrot<0b01101111,
1080 "uxth" , UnOpFrag<(and node:$Src, 0x0000FFFF)>>;
1081 defm UXTB16 : AI_unary_rrot<0b01101100,
1082 "uxtb16", UnOpFrag<(and node:$Src, 0x00FF00FF)>>;
1084 def : ARMV6Pat<(and (shl GPR:$Src, (i32 8)), 0xFF00FF),
1085 (UXTB16r_rot GPR:$Src, 24)>;
1086 def : ARMV6Pat<(and (srl GPR:$Src, (i32 8)), 0xFF00FF),
1087 (UXTB16r_rot GPR:$Src, 8)>;
1089 defm UXTAB : AI_bin_rrot<0b01101110, "uxtab",
1090 BinOpFrag<(add node:$LHS, (and node:$RHS, 0x00FF))>>;
1091 defm UXTAH : AI_bin_rrot<0b01101111, "uxtah",
1092 BinOpFrag<(add node:$LHS, (and node:$RHS, 0xFFFF))>>;
1095 // This isn't safe in general, the add is two 16-bit units, not a 32-bit add.
1096 //defm UXTAB16 : xxx<"uxtab16", 0xff00ff>;
1098 // TODO: UXT(A){B|H}16
1100 def SBFX : I<(outs GPR:$dst),
1101 (ins GPR:$src, imm0_31:$lsb, imm0_31:$width),
1102 AddrMode1, Size4Bytes, IndexModeNone, DPFrm, IIC_iALUi,
1103 "sbfx", "\t$dst, $src, $lsb, $width", "", []>,
1104 Requires<[IsARM, HasV6T2]> {
1105 let Inst{27-21} = 0b0111101;
1106 let Inst{6-4} = 0b101;
1109 def UBFX : I<(outs GPR:$dst),
1110 (ins GPR:$src, imm0_31:$lsb, imm0_31:$width),
1111 AddrMode1, Size4Bytes, IndexModeNone, DPFrm, IIC_iALUi,
1112 "ubfx", "\t$dst, $src, $lsb, $width", "", []>,
1113 Requires<[IsARM, HasV6T2]> {
1114 let Inst{27-21} = 0b0111111;
1115 let Inst{6-4} = 0b101;
1118 //===----------------------------------------------------------------------===//
1119 // Arithmetic Instructions.
1122 defm ADD : AsI1_bin_irs<0b0100, "add",
1123 BinOpFrag<(add node:$LHS, node:$RHS)>, 1>;
1124 defm SUB : AsI1_bin_irs<0b0010, "sub",
1125 BinOpFrag<(sub node:$LHS, node:$RHS)>>;
1127 // ADD and SUB with 's' bit set.
1128 defm ADDS : AI1_bin_s_irs<0b0100, "adds",
1129 BinOpFrag<(addc node:$LHS, node:$RHS)>, 1>;
1130 defm SUBS : AI1_bin_s_irs<0b0010, "subs",
1131 BinOpFrag<(subc node:$LHS, node:$RHS)>>;
1133 defm ADC : AI1_adde_sube_irs<0b0101, "adc",
1134 BinOpFrag<(adde node:$LHS, node:$RHS)>, 1>;
1135 defm SBC : AI1_adde_sube_irs<0b0110, "sbc",
1136 BinOpFrag<(sube node:$LHS, node:$RHS)>>;
1137 defm ADCS : AI1_adde_sube_s_irs<0b0101, "adcs",
1138 BinOpFrag<(adde node:$LHS, node:$RHS)>, 1>;
1139 defm SBCS : AI1_adde_sube_s_irs<0b0110, "sbcs",
1140 BinOpFrag<(sube node:$LHS, node:$RHS)>>;
1142 // These don't define reg/reg forms, because they are handled above.
1143 def RSBri : AsI1<0b0011, (outs GPR:$dst), (ins GPR:$a, so_imm:$b), DPFrm,
1144 IIC_iALUi, "rsb", "\t$dst, $a, $b",
1145 [(set GPR:$dst, (sub so_imm:$b, GPR:$a))]> {
1149 def RSBrs : AsI1<0b0011, (outs GPR:$dst), (ins GPR:$a, so_reg:$b), DPSoRegFrm,
1150 IIC_iALUsr, "rsb", "\t$dst, $a, $b",
1151 [(set GPR:$dst, (sub so_reg:$b, GPR:$a))]> {
1155 // RSB with 's' bit set.
1156 let Defs = [CPSR] in {
1157 def RSBSri : AI1<0b0011, (outs GPR:$dst), (ins GPR:$a, so_imm:$b), DPFrm,
1158 IIC_iALUi, "rsbs", "\t$dst, $a, $b",
1159 [(set GPR:$dst, (subc so_imm:$b, GPR:$a))]> {
1163 def RSBSrs : AI1<0b0011, (outs GPR:$dst), (ins GPR:$a, so_reg:$b), DPSoRegFrm,
1164 IIC_iALUsr, "rsbs", "\t$dst, $a, $b",
1165 [(set GPR:$dst, (subc so_reg:$b, GPR:$a))]> {
1171 let Uses = [CPSR] in {
1172 def RSCri : AsI1<0b0111, (outs GPR:$dst), (ins GPR:$a, so_imm:$b),
1173 DPFrm, IIC_iALUi, "rsc", "\t$dst, $a, $b",
1174 [(set GPR:$dst, (sube so_imm:$b, GPR:$a))]>,
1175 Requires<[IsARM, CarryDefIsUnused]> {
1178 def RSCrs : AsI1<0b0111, (outs GPR:$dst), (ins GPR:$a, so_reg:$b),
1179 DPSoRegFrm, IIC_iALUsr, "rsc", "\t$dst, $a, $b",
1180 [(set GPR:$dst, (sube so_reg:$b, GPR:$a))]>,
1181 Requires<[IsARM, CarryDefIsUnused]> {
1186 // FIXME: Allow these to be predicated.
1187 let Defs = [CPSR], Uses = [CPSR] in {
1188 def RSCSri : AXI1<0b0111, (outs GPR:$dst), (ins GPR:$a, so_imm:$b),
1189 DPFrm, IIC_iALUi, "rscs\t$dst, $a, $b",
1190 [(set GPR:$dst, (sube so_imm:$b, GPR:$a))]>,
1191 Requires<[IsARM, CarryDefIsUnused]> {
1195 def RSCSrs : AXI1<0b0111, (outs GPR:$dst), (ins GPR:$a, so_reg:$b),
1196 DPSoRegFrm, IIC_iALUsr, "rscs\t$dst, $a, $b",
1197 [(set GPR:$dst, (sube so_reg:$b, GPR:$a))]>,
1198 Requires<[IsARM, CarryDefIsUnused]> {
1204 // (sub X, imm) gets canonicalized to (add X, -imm). Match this form.
1205 def : ARMPat<(add GPR:$src, so_imm_neg:$imm),
1206 (SUBri GPR:$src, so_imm_neg:$imm)>;
1208 //def : ARMPat<(addc GPR:$src, so_imm_neg:$imm),
1209 // (SUBSri GPR:$src, so_imm_neg:$imm)>;
1210 //def : ARMPat<(adde GPR:$src, so_imm_neg:$imm),
1211 // (SBCri GPR:$src, so_imm_neg:$imm)>;
1213 // Note: These are implemented in C++ code, because they have to generate
1214 // ADD/SUBrs instructions, which use a complex pattern that a xform function
1216 // (mul X, 2^n+1) -> (add (X << n), X)
1217 // (mul X, 2^n-1) -> (rsb X, (X << n))
1220 //===----------------------------------------------------------------------===//
1221 // Bitwise Instructions.
1224 defm AND : AsI1_bin_irs<0b0000, "and",
1225 BinOpFrag<(and node:$LHS, node:$RHS)>, 1>;
1226 defm ORR : AsI1_bin_irs<0b1100, "orr",
1227 BinOpFrag<(or node:$LHS, node:$RHS)>, 1>;
1228 defm EOR : AsI1_bin_irs<0b0001, "eor",
1229 BinOpFrag<(xor node:$LHS, node:$RHS)>, 1>;
1230 defm BIC : AsI1_bin_irs<0b1110, "bic",
1231 BinOpFrag<(and node:$LHS, (not node:$RHS))>>;
1233 def BFC : I<(outs GPR:$dst), (ins GPR:$src, bf_inv_mask_imm:$imm),
1234 AddrMode1, Size4Bytes, IndexModeNone, DPFrm, IIC_iUNAsi,
1235 "bfc", "\t$dst, $imm", "$src = $dst",
1236 [(set GPR:$dst, (and GPR:$src, bf_inv_mask_imm:$imm))]>,
1237 Requires<[IsARM, HasV6T2]> {
1238 let Inst{27-21} = 0b0111110;
1239 let Inst{6-0} = 0b0011111;
1242 def MVNr : AsI1<0b1111, (outs GPR:$dst), (ins GPR:$src), DPFrm, IIC_iMOVr,
1243 "mvn", "\t$dst, $src",
1244 [(set GPR:$dst, (not GPR:$src))]>, UnaryDP {
1246 let Inst{11-4} = 0b00000000;
1248 def MVNs : AsI1<0b1111, (outs GPR:$dst), (ins so_reg:$src), DPSoRegFrm,
1249 IIC_iMOVsr, "mvn", "\t$dst, $src",
1250 [(set GPR:$dst, (not so_reg:$src))]>, UnaryDP {
1253 let isReMaterializable = 1, isAsCheapAsAMove = 1 in
1254 def MVNi : AsI1<0b1111, (outs GPR:$dst), (ins so_imm:$imm), DPFrm,
1255 IIC_iMOVi, "mvn", "\t$dst, $imm",
1256 [(set GPR:$dst, so_imm_not:$imm)]>,UnaryDP {
1260 def : ARMPat<(and GPR:$src, so_imm_not:$imm),
1261 (BICri GPR:$src, so_imm_not:$imm)>;
1263 //===----------------------------------------------------------------------===//
1264 // Multiply Instructions.
1267 let isCommutable = 1 in
1268 def MUL : AsMul1I<0b0000000, (outs GPR:$dst), (ins GPR:$a, GPR:$b),
1269 IIC_iMUL32, "mul", "\t$dst, $a, $b",
1270 [(set GPR:$dst, (mul GPR:$a, GPR:$b))]>;
1272 def MLA : AsMul1I<0b0000001, (outs GPR:$dst), (ins GPR:$a, GPR:$b, GPR:$c),
1273 IIC_iMAC32, "mla", "\t$dst, $a, $b, $c",
1274 [(set GPR:$dst, (add (mul GPR:$a, GPR:$b), GPR:$c))]>;
1276 def MLS : AMul1I<0b0000011, (outs GPR:$dst), (ins GPR:$a, GPR:$b, GPR:$c),
1277 IIC_iMAC32, "mls", "\t$dst, $a, $b, $c",
1278 [(set GPR:$dst, (sub GPR:$c, (mul GPR:$a, GPR:$b)))]>,
1279 Requires<[IsARM, HasV6T2]>;
1281 // Extra precision multiplies with low / high results
1282 let neverHasSideEffects = 1 in {
1283 let isCommutable = 1 in {
1284 def SMULL : AsMul1I<0b0000110, (outs GPR:$ldst, GPR:$hdst),
1285 (ins GPR:$a, GPR:$b), IIC_iMUL64,
1286 "smull", "\t$ldst, $hdst, $a, $b", []>;
1288 def UMULL : AsMul1I<0b0000100, (outs GPR:$ldst, GPR:$hdst),
1289 (ins GPR:$a, GPR:$b), IIC_iMUL64,
1290 "umull", "\t$ldst, $hdst, $a, $b", []>;
1293 // Multiply + accumulate
1294 def SMLAL : AsMul1I<0b0000111, (outs GPR:$ldst, GPR:$hdst),
1295 (ins GPR:$a, GPR:$b), IIC_iMAC64,
1296 "smlal", "\t$ldst, $hdst, $a, $b", []>;
1298 def UMLAL : AsMul1I<0b0000101, (outs GPR:$ldst, GPR:$hdst),
1299 (ins GPR:$a, GPR:$b), IIC_iMAC64,
1300 "umlal", "\t$ldst, $hdst, $a, $b", []>;
1302 def UMAAL : AMul1I <0b0000010, (outs GPR:$ldst, GPR:$hdst),
1303 (ins GPR:$a, GPR:$b), IIC_iMAC64,
1304 "umaal", "\t$ldst, $hdst, $a, $b", []>,
1305 Requires<[IsARM, HasV6]>;
1306 } // neverHasSideEffects
1308 // Most significant word multiply
1309 def SMMUL : AMul2I <0b0111010, (outs GPR:$dst), (ins GPR:$a, GPR:$b),
1310 IIC_iMUL32, "smmul", "\t$dst, $a, $b",
1311 [(set GPR:$dst, (mulhs GPR:$a, GPR:$b))]>,
1312 Requires<[IsARM, HasV6]> {
1313 let Inst{7-4} = 0b0001;
1314 let Inst{15-12} = 0b1111;
1317 def SMMLA : AMul2I <0b0111010, (outs GPR:$dst), (ins GPR:$a, GPR:$b, GPR:$c),
1318 IIC_iMAC32, "smmla", "\t$dst, $a, $b, $c",
1319 [(set GPR:$dst, (add (mulhs GPR:$a, GPR:$b), GPR:$c))]>,
1320 Requires<[IsARM, HasV6]> {
1321 let Inst{7-4} = 0b0001;
1325 def SMMLS : AMul2I <0b0111010, (outs GPR:$dst), (ins GPR:$a, GPR:$b, GPR:$c),
1326 IIC_iMAC32, "smmls", "\t$dst, $a, $b, $c",
1327 [(set GPR:$dst, (sub GPR:$c, (mulhs GPR:$a, GPR:$b)))]>,
1328 Requires<[IsARM, HasV6]> {
1329 let Inst{7-4} = 0b1101;
1332 multiclass AI_smul<string opc, PatFrag opnode> {
1333 def BB : AMulxyI<0b0001011, (outs GPR:$dst), (ins GPR:$a, GPR:$b),
1334 IIC_iMUL32, !strconcat(opc, "bb"), "\t$dst, $a, $b",
1335 [(set GPR:$dst, (opnode (sext_inreg GPR:$a, i16),
1336 (sext_inreg GPR:$b, i16)))]>,
1337 Requires<[IsARM, HasV5TE]> {
1342 def BT : AMulxyI<0b0001011, (outs GPR:$dst), (ins GPR:$a, GPR:$b),
1343 IIC_iMUL32, !strconcat(opc, "bt"), "\t$dst, $a, $b",
1344 [(set GPR:$dst, (opnode (sext_inreg GPR:$a, i16),
1345 (sra GPR:$b, (i32 16))))]>,
1346 Requires<[IsARM, HasV5TE]> {
1351 def TB : AMulxyI<0b0001011, (outs GPR:$dst), (ins GPR:$a, GPR:$b),
1352 IIC_iMUL32, !strconcat(opc, "tb"), "\t$dst, $a, $b",
1353 [(set GPR:$dst, (opnode (sra GPR:$a, (i32 16)),
1354 (sext_inreg GPR:$b, i16)))]>,
1355 Requires<[IsARM, HasV5TE]> {
1360 def TT : AMulxyI<0b0001011, (outs GPR:$dst), (ins GPR:$a, GPR:$b),
1361 IIC_iMUL32, !strconcat(opc, "tt"), "\t$dst, $a, $b",
1362 [(set GPR:$dst, (opnode (sra GPR:$a, (i32 16)),
1363 (sra GPR:$b, (i32 16))))]>,
1364 Requires<[IsARM, HasV5TE]> {
1369 def WB : AMulxyI<0b0001001, (outs GPR:$dst), (ins GPR:$a, GPR:$b),
1370 IIC_iMUL16, !strconcat(opc, "wb"), "\t$dst, $a, $b",
1371 [(set GPR:$dst, (sra (opnode GPR:$a,
1372 (sext_inreg GPR:$b, i16)), (i32 16)))]>,
1373 Requires<[IsARM, HasV5TE]> {
1378 def WT : AMulxyI<0b0001001, (outs GPR:$dst), (ins GPR:$a, GPR:$b),
1379 IIC_iMUL16, !strconcat(opc, "wt"), "\t$dst, $a, $b",
1380 [(set GPR:$dst, (sra (opnode GPR:$a,
1381 (sra GPR:$b, (i32 16))), (i32 16)))]>,
1382 Requires<[IsARM, HasV5TE]> {
1389 multiclass AI_smla<string opc, PatFrag opnode> {
1390 def BB : AMulxyI<0b0001000, (outs GPR:$dst), (ins GPR:$a, GPR:$b, GPR:$acc),
1391 IIC_iMAC16, !strconcat(opc, "bb"), "\t$dst, $a, $b, $acc",
1392 [(set GPR:$dst, (add GPR:$acc,
1393 (opnode (sext_inreg GPR:$a, i16),
1394 (sext_inreg GPR:$b, i16))))]>,
1395 Requires<[IsARM, HasV5TE]> {
1400 def BT : AMulxyI<0b0001000, (outs GPR:$dst), (ins GPR:$a, GPR:$b, GPR:$acc),
1401 IIC_iMAC16, !strconcat(opc, "bt"), "\t$dst, $a, $b, $acc",
1402 [(set GPR:$dst, (add GPR:$acc, (opnode (sext_inreg GPR:$a, i16),
1403 (sra GPR:$b, (i32 16)))))]>,
1404 Requires<[IsARM, HasV5TE]> {
1409 def TB : AMulxyI<0b0001000, (outs GPR:$dst), (ins GPR:$a, GPR:$b, GPR:$acc),
1410 IIC_iMAC16, !strconcat(opc, "tb"), "\t$dst, $a, $b, $acc",
1411 [(set GPR:$dst, (add GPR:$acc, (opnode (sra GPR:$a, (i32 16)),
1412 (sext_inreg GPR:$b, i16))))]>,
1413 Requires<[IsARM, HasV5TE]> {
1418 def TT : AMulxyI<0b0001000, (outs GPR:$dst), (ins GPR:$a, GPR:$b, GPR:$acc),
1419 IIC_iMAC16, !strconcat(opc, "tt"), "\t$dst, $a, $b, $acc",
1420 [(set GPR:$dst, (add GPR:$acc, (opnode (sra GPR:$a, (i32 16)),
1421 (sra GPR:$b, (i32 16)))))]>,
1422 Requires<[IsARM, HasV5TE]> {
1427 def WB : AMulxyI<0b0001001, (outs GPR:$dst), (ins GPR:$a, GPR:$b, GPR:$acc),
1428 IIC_iMAC16, !strconcat(opc, "wb"), "\t$dst, $a, $b, $acc",
1429 [(set GPR:$dst, (add GPR:$acc, (sra (opnode GPR:$a,
1430 (sext_inreg GPR:$b, i16)), (i32 16))))]>,
1431 Requires<[IsARM, HasV5TE]> {
1436 def WT : AMulxyI<0b0001001, (outs GPR:$dst), (ins GPR:$a, GPR:$b, GPR:$acc),
1437 IIC_iMAC16, !strconcat(opc, "wt"), "\t$dst, $a, $b, $acc",
1438 [(set GPR:$dst, (add GPR:$acc, (sra (opnode GPR:$a,
1439 (sra GPR:$b, (i32 16))), (i32 16))))]>,
1440 Requires<[IsARM, HasV5TE]> {
1446 defm SMUL : AI_smul<"smul", BinOpFrag<(mul node:$LHS, node:$RHS)>>;
1447 defm SMLA : AI_smla<"smla", BinOpFrag<(mul node:$LHS, node:$RHS)>>;
1449 // TODO: Halfword multiple accumulate long: SMLAL<x><y>
1450 // TODO: Dual halfword multiple: SMUAD, SMUSD, SMLAD, SMLSD, SMLALD, SMLSLD
1452 //===----------------------------------------------------------------------===//
1453 // Misc. Arithmetic Instructions.
1456 def CLZ : AMiscA1I<0b000010110, (outs GPR:$dst), (ins GPR:$src), IIC_iUNAr,
1457 "clz", "\t$dst, $src",
1458 [(set GPR:$dst, (ctlz GPR:$src))]>, Requires<[IsARM, HasV5T]> {
1459 let Inst{7-4} = 0b0001;
1460 let Inst{11-8} = 0b1111;
1461 let Inst{19-16} = 0b1111;
1464 def RBIT : AMiscA1I<0b01101111, (outs GPR:$dst), (ins GPR:$src), IIC_iUNAr,
1465 "rbit", "\t$dst, $src",
1466 [(set GPR:$dst, (ARMrbit GPR:$src))]>,
1467 Requires<[IsARM, HasV6T2]> {
1468 let Inst{7-4} = 0b0011;
1469 let Inst{11-8} = 0b1111;
1470 let Inst{19-16} = 0b1111;
1473 def REV : AMiscA1I<0b01101011, (outs GPR:$dst), (ins GPR:$src), IIC_iUNAr,
1474 "rev", "\t$dst, $src",
1475 [(set GPR:$dst, (bswap GPR:$src))]>, Requires<[IsARM, HasV6]> {
1476 let Inst{7-4} = 0b0011;
1477 let Inst{11-8} = 0b1111;
1478 let Inst{19-16} = 0b1111;
1481 def REV16 : AMiscA1I<0b01101011, (outs GPR:$dst), (ins GPR:$src), IIC_iUNAr,
1482 "rev16", "\t$dst, $src",
1484 (or (and (srl GPR:$src, (i32 8)), 0xFF),
1485 (or (and (shl GPR:$src, (i32 8)), 0xFF00),
1486 (or (and (srl GPR:$src, (i32 8)), 0xFF0000),
1487 (and (shl GPR:$src, (i32 8)), 0xFF000000)))))]>,
1488 Requires<[IsARM, HasV6]> {
1489 let Inst{7-4} = 0b1011;
1490 let Inst{11-8} = 0b1111;
1491 let Inst{19-16} = 0b1111;
1494 def REVSH : AMiscA1I<0b01101111, (outs GPR:$dst), (ins GPR:$src), IIC_iUNAr,
1495 "revsh", "\t$dst, $src",
1498 (or (srl (and GPR:$src, 0xFF00), (i32 8)),
1499 (shl GPR:$src, (i32 8))), i16))]>,
1500 Requires<[IsARM, HasV6]> {
1501 let Inst{7-4} = 0b1011;
1502 let Inst{11-8} = 0b1111;
1503 let Inst{19-16} = 0b1111;
1506 def PKHBT : AMiscA1I<0b01101000, (outs GPR:$dst),
1507 (ins GPR:$src1, GPR:$src2, i32imm:$shamt),
1508 IIC_iALUsi, "pkhbt", "\t$dst, $src1, $src2, LSL $shamt",
1509 [(set GPR:$dst, (or (and GPR:$src1, 0xFFFF),
1510 (and (shl GPR:$src2, (i32 imm:$shamt)),
1512 Requires<[IsARM, HasV6]> {
1513 let Inst{6-4} = 0b001;
1516 // Alternate cases for PKHBT where identities eliminate some nodes.
1517 def : ARMV6Pat<(or (and GPR:$src1, 0xFFFF), (and GPR:$src2, 0xFFFF0000)),
1518 (PKHBT GPR:$src1, GPR:$src2, 0)>;
1519 def : ARMV6Pat<(or (and GPR:$src1, 0xFFFF), (shl GPR:$src2, imm16_31:$shamt)),
1520 (PKHBT GPR:$src1, GPR:$src2, imm16_31:$shamt)>;
1523 def PKHTB : AMiscA1I<0b01101000, (outs GPR:$dst),
1524 (ins GPR:$src1, GPR:$src2, i32imm:$shamt),
1525 IIC_iALUsi, "pkhtb", "\t$dst, $src1, $src2, ASR $shamt",
1526 [(set GPR:$dst, (or (and GPR:$src1, 0xFFFF0000),
1527 (and (sra GPR:$src2, imm16_31:$shamt),
1528 0xFFFF)))]>, Requires<[IsARM, HasV6]> {
1529 let Inst{6-4} = 0b101;
1532 // Alternate cases for PKHTB where identities eliminate some nodes. Note that
1533 // a shift amount of 0 is *not legal* here, it is PKHBT instead.
1534 def : ARMV6Pat<(or (and GPR:$src1, 0xFFFF0000), (srl GPR:$src2, (i32 16))),
1535 (PKHTB GPR:$src1, GPR:$src2, 16)>;
1536 def : ARMV6Pat<(or (and GPR:$src1, 0xFFFF0000),
1537 (and (srl GPR:$src2, imm1_15:$shamt), 0xFFFF)),
1538 (PKHTB GPR:$src1, GPR:$src2, imm1_15:$shamt)>;
1540 //===----------------------------------------------------------------------===//
1541 // Comparison Instructions...
1544 defm CMP : AI1_cmp_irs<0b1010, "cmp",
1545 BinOpFrag<(ARMcmp node:$LHS, node:$RHS)>>;
1546 //FIXME: Disable CMN, as CCodes are backwards from compare expectations
1547 // Compare-to-zero still works out, just not the relationals
1548 //defm CMN : AI1_cmp_irs<0b1011, "cmn",
1549 // BinOpFrag<(ARMcmp node:$LHS,(ineg node:$RHS))>>;
1551 // Note that TST/TEQ don't set all the same flags that CMP does!
1552 defm TST : AI1_cmp_irs<0b1000, "tst",
1553 BinOpFrag<(ARMcmpZ (and node:$LHS, node:$RHS), 0)>, 1>;
1554 defm TEQ : AI1_cmp_irs<0b1001, "teq",
1555 BinOpFrag<(ARMcmpZ (xor node:$LHS, node:$RHS), 0)>, 1>;
1557 defm CMPz : AI1_cmp_irs<0b1010, "cmp",
1558 BinOpFrag<(ARMcmpZ node:$LHS, node:$RHS)>>;
1559 defm CMNz : AI1_cmp_irs<0b1011, "cmn",
1560 BinOpFrag<(ARMcmpZ node:$LHS,(ineg node:$RHS))>>;
1562 //def : ARMPat<(ARMcmp GPR:$src, so_imm_neg:$imm),
1563 // (CMNri GPR:$src, so_imm_neg:$imm)>;
1565 def : ARMPat<(ARMcmpZ GPR:$src, so_imm_neg:$imm),
1566 (CMNzri GPR:$src, so_imm_neg:$imm)>;
1569 // Conditional moves
1570 // FIXME: should be able to write a pattern for ARMcmov, but can't use
1571 // a two-value operand where a dag node expects two operands. :(
1572 def MOVCCr : AI1<0b1101, (outs GPR:$dst), (ins GPR:$false, GPR:$true), DPFrm,
1573 IIC_iCMOVr, "mov", "\t$dst, $true",
1574 [/*(set GPR:$dst, (ARMcmov GPR:$false, GPR:$true, imm:$cc, CCR:$ccr))*/]>,
1575 RegConstraint<"$false = $dst">, UnaryDP {
1576 let Inst{11-4} = 0b00000000;
1580 def MOVCCs : AI1<0b1101, (outs GPR:$dst),
1581 (ins GPR:$false, so_reg:$true), DPSoRegFrm, IIC_iCMOVsr,
1582 "mov", "\t$dst, $true",
1583 [/*(set GPR:$dst, (ARMcmov GPR:$false, so_reg:$true, imm:$cc, CCR:$ccr))*/]>,
1584 RegConstraint<"$false = $dst">, UnaryDP {
1588 def MOVCCi : AI1<0b1101, (outs GPR:$dst),
1589 (ins GPR:$false, so_imm:$true), DPFrm, IIC_iCMOVi,
1590 "mov", "\t$dst, $true",
1591 [/*(set GPR:$dst, (ARMcmov GPR:$false, so_imm:$true, imm:$cc, CCR:$ccr))*/]>,
1592 RegConstraint<"$false = $dst">, UnaryDP {
1596 //===----------------------------------------------------------------------===//
1597 // Atomic operations intrinsics
1600 // memory barriers protect the atomic sequences
1601 let hasSideEffects = 1 in {
1602 def Int_MemBarrierV7 : AInoP<(outs), (ins),
1603 Pseudo, NoItinerary,
1605 [(ARMMemBarrierV7)]>,
1606 Requires<[IsARM, HasV7]> {
1607 let Inst{31-4} = 0xf57ff05;
1608 // FIXME: add support for options other than a full system DMB
1609 let Inst{3-0} = 0b1111;
1612 def Int_SyncBarrierV7 : AInoP<(outs), (ins),
1613 Pseudo, NoItinerary,
1615 [(ARMSyncBarrierV7)]>,
1616 Requires<[IsARM, HasV7]> {
1617 let Inst{31-4} = 0xf57ff04;
1618 // FIXME: add support for options other than a full system DSB
1619 let Inst{3-0} = 0b1111;
1622 def Int_MemBarrierV6 : AInoP<(outs), (ins GPR:$zero),
1623 Pseudo, NoItinerary,
1624 "mcr", "\tp15, 0, $zero, c7, c10, 5",
1625 [(ARMMemBarrierV6 GPR:$zero)]>,
1626 Requires<[IsARM, HasV6]> {
1627 // FIXME: add support for options other than a full system DMB
1628 // FIXME: add encoding
1631 def Int_SyncBarrierV6 : AInoP<(outs), (ins GPR:$zero),
1632 Pseudo, NoItinerary,
1633 "mcr", "\tp15, 0, $zero, c7, c10, 4",
1634 [(ARMSyncBarrierV6 GPR:$zero)]>,
1635 Requires<[IsARM, HasV6]> {
1636 // FIXME: add support for options other than a full system DSB
1637 // FIXME: add encoding
1641 let usesCustomInserter = 1 in {
1642 let Uses = [CPSR] in {
1643 def ATOMIC_LOAD_ADD_I8 : PseudoInst<
1644 (outs GPR:$dst), (ins GPR:$ptr, GPR:$incr), NoItinerary,
1645 "${:comment} ATOMIC_LOAD_ADD_I8 PSEUDO!",
1646 [(set GPR:$dst, (atomic_load_add_8 GPR:$ptr, GPR:$incr))]>;
1647 def ATOMIC_LOAD_SUB_I8 : PseudoInst<
1648 (outs GPR:$dst), (ins GPR:$ptr, GPR:$incr), NoItinerary,
1649 "${:comment} ATOMIC_LOAD_SUB_I8 PSEUDO!",
1650 [(set GPR:$dst, (atomic_load_sub_8 GPR:$ptr, GPR:$incr))]>;
1651 def ATOMIC_LOAD_AND_I8 : PseudoInst<
1652 (outs GPR:$dst), (ins GPR:$ptr, GPR:$incr), NoItinerary,
1653 "${:comment} ATOMIC_LOAD_AND_I8 PSEUDO!",
1654 [(set GPR:$dst, (atomic_load_and_8 GPR:$ptr, GPR:$incr))]>;
1655 def ATOMIC_LOAD_OR_I8 : PseudoInst<
1656 (outs GPR:$dst), (ins GPR:$ptr, GPR:$incr), NoItinerary,
1657 "${:comment} ATOMIC_LOAD_OR_I8 PSEUDO!",
1658 [(set GPR:$dst, (atomic_load_or_8 GPR:$ptr, GPR:$incr))]>;
1659 def ATOMIC_LOAD_XOR_I8 : PseudoInst<
1660 (outs GPR:$dst), (ins GPR:$ptr, GPR:$incr), NoItinerary,
1661 "${:comment} ATOMIC_LOAD_XOR_I8 PSEUDO!",
1662 [(set GPR:$dst, (atomic_load_xor_8 GPR:$ptr, GPR:$incr))]>;
1663 def ATOMIC_LOAD_NAND_I8 : PseudoInst<
1664 (outs GPR:$dst), (ins GPR:$ptr, GPR:$incr), NoItinerary,
1665 "${:comment} ATOMIC_LOAD_NAND_I8 PSEUDO!",
1666 [(set GPR:$dst, (atomic_load_nand_8 GPR:$ptr, GPR:$incr))]>;
1667 def ATOMIC_LOAD_ADD_I16 : PseudoInst<
1668 (outs GPR:$dst), (ins GPR:$ptr, GPR:$incr), NoItinerary,
1669 "${:comment} ATOMIC_LOAD_ADD_I16 PSEUDO!",
1670 [(set GPR:$dst, (atomic_load_add_16 GPR:$ptr, GPR:$incr))]>;
1671 def ATOMIC_LOAD_SUB_I16 : PseudoInst<
1672 (outs GPR:$dst), (ins GPR:$ptr, GPR:$incr), NoItinerary,
1673 "${:comment} ATOMIC_LOAD_SUB_I16 PSEUDO!",
1674 [(set GPR:$dst, (atomic_load_sub_16 GPR:$ptr, GPR:$incr))]>;
1675 def ATOMIC_LOAD_AND_I16 : PseudoInst<
1676 (outs GPR:$dst), (ins GPR:$ptr, GPR:$incr), NoItinerary,
1677 "${:comment} ATOMIC_LOAD_AND_I16 PSEUDO!",
1678 [(set GPR:$dst, (atomic_load_and_16 GPR:$ptr, GPR:$incr))]>;
1679 def ATOMIC_LOAD_OR_I16 : PseudoInst<
1680 (outs GPR:$dst), (ins GPR:$ptr, GPR:$incr), NoItinerary,
1681 "${:comment} ATOMIC_LOAD_OR_I16 PSEUDO!",
1682 [(set GPR:$dst, (atomic_load_or_16 GPR:$ptr, GPR:$incr))]>;
1683 def ATOMIC_LOAD_XOR_I16 : PseudoInst<
1684 (outs GPR:$dst), (ins GPR:$ptr, GPR:$incr), NoItinerary,
1685 "${:comment} ATOMIC_LOAD_XOR_I16 PSEUDO!",
1686 [(set GPR:$dst, (atomic_load_xor_16 GPR:$ptr, GPR:$incr))]>;
1687 def ATOMIC_LOAD_NAND_I16 : PseudoInst<
1688 (outs GPR:$dst), (ins GPR:$ptr, GPR:$incr), NoItinerary,
1689 "${:comment} ATOMIC_LOAD_NAND_I16 PSEUDO!",
1690 [(set GPR:$dst, (atomic_load_nand_16 GPR:$ptr, GPR:$incr))]>;
1691 def ATOMIC_LOAD_ADD_I32 : PseudoInst<
1692 (outs GPR:$dst), (ins GPR:$ptr, GPR:$incr), NoItinerary,
1693 "${:comment} ATOMIC_LOAD_ADD_I32 PSEUDO!",
1694 [(set GPR:$dst, (atomic_load_add_32 GPR:$ptr, GPR:$incr))]>;
1695 def ATOMIC_LOAD_SUB_I32 : PseudoInst<
1696 (outs GPR:$dst), (ins GPR:$ptr, GPR:$incr), NoItinerary,
1697 "${:comment} ATOMIC_LOAD_SUB_I32 PSEUDO!",
1698 [(set GPR:$dst, (atomic_load_sub_32 GPR:$ptr, GPR:$incr))]>;
1699 def ATOMIC_LOAD_AND_I32 : PseudoInst<
1700 (outs GPR:$dst), (ins GPR:$ptr, GPR:$incr), NoItinerary,
1701 "${:comment} ATOMIC_LOAD_AND_I32 PSEUDO!",
1702 [(set GPR:$dst, (atomic_load_and_32 GPR:$ptr, GPR:$incr))]>;
1703 def ATOMIC_LOAD_OR_I32 : PseudoInst<
1704 (outs GPR:$dst), (ins GPR:$ptr, GPR:$incr), NoItinerary,
1705 "${:comment} ATOMIC_LOAD_OR_I32 PSEUDO!",
1706 [(set GPR:$dst, (atomic_load_or_32 GPR:$ptr, GPR:$incr))]>;
1707 def ATOMIC_LOAD_XOR_I32 : PseudoInst<
1708 (outs GPR:$dst), (ins GPR:$ptr, GPR:$incr), NoItinerary,
1709 "${:comment} ATOMIC_LOAD_XOR_I32 PSEUDO!",
1710 [(set GPR:$dst, (atomic_load_xor_32 GPR:$ptr, GPR:$incr))]>;
1711 def ATOMIC_LOAD_NAND_I32 : PseudoInst<
1712 (outs GPR:$dst), (ins GPR:$ptr, GPR:$incr), NoItinerary,
1713 "${:comment} ATOMIC_LOAD_NAND_I32 PSEUDO!",
1714 [(set GPR:$dst, (atomic_load_nand_32 GPR:$ptr, GPR:$incr))]>;
1716 def ATOMIC_SWAP_I8 : PseudoInst<
1717 (outs GPR:$dst), (ins GPR:$ptr, GPR:$new), NoItinerary,
1718 "${:comment} ATOMIC_SWAP_I8 PSEUDO!",
1719 [(set GPR:$dst, (atomic_swap_8 GPR:$ptr, GPR:$new))]>;
1720 def ATOMIC_SWAP_I16 : PseudoInst<
1721 (outs GPR:$dst), (ins GPR:$ptr, GPR:$new), NoItinerary,
1722 "${:comment} ATOMIC_SWAP_I16 PSEUDO!",
1723 [(set GPR:$dst, (atomic_swap_16 GPR:$ptr, GPR:$new))]>;
1724 def ATOMIC_SWAP_I32 : PseudoInst<
1725 (outs GPR:$dst), (ins GPR:$ptr, GPR:$new), NoItinerary,
1726 "${:comment} ATOMIC_SWAP_I32 PSEUDO!",
1727 [(set GPR:$dst, (atomic_swap_32 GPR:$ptr, GPR:$new))]>;
1729 def ATOMIC_CMP_SWAP_I8 : PseudoInst<
1730 (outs GPR:$dst), (ins GPR:$ptr, GPR:$old, GPR:$new), NoItinerary,
1731 "${:comment} ATOMIC_CMP_SWAP_I8 PSEUDO!",
1732 [(set GPR:$dst, (atomic_cmp_swap_8 GPR:$ptr, GPR:$old, GPR:$new))]>;
1733 def ATOMIC_CMP_SWAP_I16 : PseudoInst<
1734 (outs GPR:$dst), (ins GPR:$ptr, GPR:$old, GPR:$new), NoItinerary,
1735 "${:comment} ATOMIC_CMP_SWAP_I16 PSEUDO!",
1736 [(set GPR:$dst, (atomic_cmp_swap_16 GPR:$ptr, GPR:$old, GPR:$new))]>;
1737 def ATOMIC_CMP_SWAP_I32 : PseudoInst<
1738 (outs GPR:$dst), (ins GPR:$ptr, GPR:$old, GPR:$new), NoItinerary,
1739 "${:comment} ATOMIC_CMP_SWAP_I32 PSEUDO!",
1740 [(set GPR:$dst, (atomic_cmp_swap_32 GPR:$ptr, GPR:$old, GPR:$new))]>;
1744 let mayLoad = 1 in {
1745 def LDREXB : AIldrex<0b10, (outs GPR:$dest), (ins GPR:$ptr), NoItinerary,
1746 "ldrexb", "\t$dest, [$ptr]",
1748 def LDREXH : AIldrex<0b11, (outs GPR:$dest), (ins GPR:$ptr), NoItinerary,
1749 "ldrexh", "\t$dest, [$ptr]",
1751 def LDREX : AIldrex<0b00, (outs GPR:$dest), (ins GPR:$ptr), NoItinerary,
1752 "ldrex", "\t$dest, [$ptr]",
1754 def LDREXD : AIldrex<0b01, (outs GPR:$dest, GPR:$dest2), (ins GPR:$ptr),
1756 "ldrexd", "\t$dest, $dest2, [$ptr]",
1760 let mayStore = 1, Constraints = "@earlyclobber $success" in {
1761 def STREXB : AIstrex<0b10, (outs GPR:$success), (ins GPR:$src, GPR:$ptr),
1763 "strexb", "\t$success, $src, [$ptr]",
1765 def STREXH : AIstrex<0b11, (outs GPR:$success), (ins GPR:$src, GPR:$ptr),
1767 "strexh", "\t$success, $src, [$ptr]",
1769 def STREX : AIstrex<0b00, (outs GPR:$success), (ins GPR:$src, GPR:$ptr),
1771 "strex", "\t$success, $src, [$ptr]",
1773 def STREXD : AIstrex<0b01, (outs GPR:$success),
1774 (ins GPR:$src, GPR:$src2, GPR:$ptr),
1776 "strexd", "\t$success, $src, $src2, [$ptr]",
1780 //===----------------------------------------------------------------------===//
1784 // __aeabi_read_tp preserves the registers r1-r3.
1786 Defs = [R0, R12, LR, CPSR] in {
1787 def TPsoft : ABXI<0b1011, (outs), (ins), IIC_Br,
1788 "bl\t__aeabi_read_tp",
1789 [(set R0, ARMthread_pointer)]>;
1792 //===----------------------------------------------------------------------===//
1793 // SJLJ Exception handling intrinsics
1794 // eh_sjlj_setjmp() is an instruction sequence to store the return
1795 // address and save #0 in R0 for the non-longjmp case.
1796 // Since by its nature we may be coming from some other function to get
1797 // here, and we're using the stack frame for the containing function to
1798 // save/restore registers, we can't keep anything live in regs across
1799 // the eh_sjlj_setjmp(), else it will almost certainly have been tromped upon
1800 // when we get here from a longjmp(). We force everthing out of registers
1801 // except for our own input by listing the relevant registers in Defs. By
1802 // doing so, we also cause the prologue/epilogue code to actively preserve
1803 // all of the callee-saved resgisters, which is exactly what we want.
1804 // A constant value is passed in $val, and we use the location as a scratch.
1806 [ R0, R1, R2, R3, R4, R5, R6, R7, R8, R9, R10, R11, R12, LR, D0,
1807 D1, D2, D3, D4, D5, D6, D7, D8, D9, D10, D11, D12, D13, D14, D15,
1808 D16, D17, D18, D19, D20, D21, D22, D23, D24, D25, D26, D27, D28, D29, D30,
1810 def Int_eh_sjlj_setjmp : XI<(outs), (ins GPR:$src, GPR:$val),
1811 AddrModeNone, SizeSpecial, IndexModeNone,
1812 Pseudo, NoItinerary,
1813 "str\tsp, [$src, #+8] @ eh_setjmp begin\n\t"
1814 "add\t$val, pc, #8\n\t"
1815 "str\t$val, [$src, #+4]\n\t"
1817 "add\tpc, pc, #0\n\t"
1818 "mov\tr0, #1 @ eh_setjmp end", "",
1819 [(set R0, (ARMeh_sjlj_setjmp GPR:$src, GPR:$val))]>;
1822 //===----------------------------------------------------------------------===//
1823 // Non-Instruction Patterns
1826 // Large immediate handling.
1828 // Two piece so_imms.
1829 let isReMaterializable = 1 in
1830 def MOVi2pieces : AI1x2<(outs GPR:$dst), (ins so_imm2part:$src),
1832 "mov", "\t$dst, $src",
1833 [(set GPR:$dst, so_imm2part:$src)]>,
1834 Requires<[IsARM, NoV6T2]>;
1836 def : ARMPat<(or GPR:$LHS, so_imm2part:$RHS),
1837 (ORRri (ORRri GPR:$LHS, (so_imm2part_1 imm:$RHS)),
1838 (so_imm2part_2 imm:$RHS))>;
1839 def : ARMPat<(xor GPR:$LHS, so_imm2part:$RHS),
1840 (EORri (EORri GPR:$LHS, (so_imm2part_1 imm:$RHS)),
1841 (so_imm2part_2 imm:$RHS))>;
1842 def : ARMPat<(add GPR:$LHS, so_imm2part:$RHS),
1843 (ADDri (ADDri GPR:$LHS, (so_imm2part_1 imm:$RHS)),
1844 (so_imm2part_2 imm:$RHS))>;
1845 def : ARMPat<(add GPR:$LHS, so_neg_imm2part:$RHS),
1846 (SUBri (SUBri GPR:$LHS, (so_neg_imm2part_1 imm:$RHS)),
1847 (so_neg_imm2part_2 imm:$RHS))>;
1849 // 32-bit immediate using movw + movt.
1850 // This is a single pseudo instruction, the benefit is that it can be remat'd
1851 // as a single unit instead of having to handle reg inputs.
1852 // FIXME: Remove this when we can do generalized remat.
1853 let isReMaterializable = 1 in
1854 def MOVi32imm : AI1x2<(outs GPR:$dst), (ins i32imm:$src), Pseudo, IIC_iMOVi,
1855 "movw", "\t$dst, ${src:lo16}\n\tmovt${p}\t$dst, ${src:hi16}",
1856 [(set GPR:$dst, (i32 imm:$src))]>,
1857 Requires<[IsARM, HasV6T2]>;
1859 // ConstantPool, GlobalAddress, and JumpTable
1860 def : ARMPat<(ARMWrapper tglobaladdr :$dst), (LEApcrel tglobaladdr :$dst)>,
1861 Requires<[IsARM, DontUseMovt]>;
1862 def : ARMPat<(ARMWrapper tconstpool :$dst), (LEApcrel tconstpool :$dst)>;
1863 def : ARMPat<(ARMWrapper tglobaladdr :$dst), (MOVi32imm tglobaladdr :$dst)>,
1864 Requires<[IsARM, UseMovt]>;
1865 def : ARMPat<(ARMWrapperJT tjumptable:$dst, imm:$id),
1866 (LEApcrelJT tjumptable:$dst, imm:$id)>;
1868 // TODO: add,sub,and, 3-instr forms?
1872 def : ARMPat<(ARMcall texternalsym:$func), (BL texternalsym:$func)>,
1873 Requires<[IsARM, IsNotDarwin]>;
1874 def : ARMPat<(ARMcall texternalsym:$func), (BLr9 texternalsym:$func)>,
1875 Requires<[IsARM, IsDarwin]>;
1877 // zextload i1 -> zextload i8
1878 def : ARMPat<(zextloadi1 addrmode2:$addr), (LDRB addrmode2:$addr)>;
1880 // extload -> zextload
1881 def : ARMPat<(extloadi1 addrmode2:$addr), (LDRB addrmode2:$addr)>;
1882 def : ARMPat<(extloadi8 addrmode2:$addr), (LDRB addrmode2:$addr)>;
1883 def : ARMPat<(extloadi16 addrmode3:$addr), (LDRH addrmode3:$addr)>;
1885 def : ARMPat<(extloadi8 addrmodepc:$addr), (PICLDRB addrmodepc:$addr)>;
1886 def : ARMPat<(extloadi16 addrmodepc:$addr), (PICLDRH addrmodepc:$addr)>;
1889 def : ARMV5TEPat<(mul (sra (shl GPR:$a, (i32 16)), (i32 16)),
1890 (sra (shl GPR:$b, (i32 16)), (i32 16))),
1891 (SMULBB GPR:$a, GPR:$b)>;
1892 def : ARMV5TEPat<(mul sext_16_node:$a, sext_16_node:$b),
1893 (SMULBB GPR:$a, GPR:$b)>;
1894 def : ARMV5TEPat<(mul (sra (shl GPR:$a, (i32 16)), (i32 16)),
1895 (sra GPR:$b, (i32 16))),
1896 (SMULBT GPR:$a, GPR:$b)>;
1897 def : ARMV5TEPat<(mul sext_16_node:$a, (sra GPR:$b, (i32 16))),
1898 (SMULBT GPR:$a, GPR:$b)>;
1899 def : ARMV5TEPat<(mul (sra GPR:$a, (i32 16)),
1900 (sra (shl GPR:$b, (i32 16)), (i32 16))),
1901 (SMULTB GPR:$a, GPR:$b)>;
1902 def : ARMV5TEPat<(mul (sra GPR:$a, (i32 16)), sext_16_node:$b),
1903 (SMULTB GPR:$a, GPR:$b)>;
1904 def : ARMV5TEPat<(sra (mul GPR:$a, (sra (shl GPR:$b, (i32 16)), (i32 16))),
1906 (SMULWB GPR:$a, GPR:$b)>;
1907 def : ARMV5TEPat<(sra (mul GPR:$a, sext_16_node:$b), (i32 16)),
1908 (SMULWB GPR:$a, GPR:$b)>;
1910 def : ARMV5TEPat<(add GPR:$acc,
1911 (mul (sra (shl GPR:$a, (i32 16)), (i32 16)),
1912 (sra (shl GPR:$b, (i32 16)), (i32 16)))),
1913 (SMLABB GPR:$a, GPR:$b, GPR:$acc)>;
1914 def : ARMV5TEPat<(add GPR:$acc,
1915 (mul sext_16_node:$a, sext_16_node:$b)),
1916 (SMLABB GPR:$a, GPR:$b, GPR:$acc)>;
1917 def : ARMV5TEPat<(add GPR:$acc,
1918 (mul (sra (shl GPR:$a, (i32 16)), (i32 16)),
1919 (sra GPR:$b, (i32 16)))),
1920 (SMLABT GPR:$a, GPR:$b, GPR:$acc)>;
1921 def : ARMV5TEPat<(add GPR:$acc,
1922 (mul sext_16_node:$a, (sra GPR:$b, (i32 16)))),
1923 (SMLABT GPR:$a, GPR:$b, GPR:$acc)>;
1924 def : ARMV5TEPat<(add GPR:$acc,
1925 (mul (sra GPR:$a, (i32 16)),
1926 (sra (shl GPR:$b, (i32 16)), (i32 16)))),
1927 (SMLATB GPR:$a, GPR:$b, GPR:$acc)>;
1928 def : ARMV5TEPat<(add GPR:$acc,
1929 (mul (sra GPR:$a, (i32 16)), sext_16_node:$b)),
1930 (SMLATB GPR:$a, GPR:$b, GPR:$acc)>;
1931 def : ARMV5TEPat<(add GPR:$acc,
1932 (sra (mul GPR:$a, (sra (shl GPR:$b, (i32 16)), (i32 16))),
1934 (SMLAWB GPR:$a, GPR:$b, GPR:$acc)>;
1935 def : ARMV5TEPat<(add GPR:$acc,
1936 (sra (mul GPR:$a, sext_16_node:$b), (i32 16))),
1937 (SMLAWB GPR:$a, GPR:$b, GPR:$acc)>;
1939 //===----------------------------------------------------------------------===//
1943 include "ARMInstrThumb.td"
1945 //===----------------------------------------------------------------------===//
1949 include "ARMInstrThumb2.td"
1951 //===----------------------------------------------------------------------===//
1952 // Floating Point Support
1955 include "ARMInstrVFP.td"
1957 //===----------------------------------------------------------------------===//
1958 // Advanced SIMD (NEON) Support
1961 include "ARMInstrNEON.td"