1 //===- ARMInstrInfo.td - Target Description for ARM Target -*- tablegen -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file describes the ARM instructions in TableGen format.
12 //===----------------------------------------------------------------------===//
14 //===----------------------------------------------------------------------===//
15 // ARM specific DAG Nodes.
19 def SDT_ARMCallSeqStart : SDCallSeqStart<[ SDTCisVT<0, i32> ]>;
20 def SDT_ARMCallSeqEnd : SDCallSeqEnd<[ SDTCisVT<0, i32>, SDTCisVT<1, i32> ]>;
22 def SDT_ARMSaveCallPC : SDTypeProfile<0, 1, []>;
24 def SDT_ARMcall : SDTypeProfile<0, -1, [SDTCisInt<0>]>;
26 def SDT_ARMCMov : SDTypeProfile<1, 3,
27 [SDTCisSameAs<0, 1>, SDTCisSameAs<0, 2>,
30 def SDT_ARMBrcond : SDTypeProfile<0, 2,
31 [SDTCisVT<0, OtherVT>, SDTCisVT<1, i32>]>;
33 def SDT_ARMBrJT : SDTypeProfile<0, 3,
34 [SDTCisPtrTy<0>, SDTCisVT<1, i32>,
37 def SDT_ARMBr2JT : SDTypeProfile<0, 4,
38 [SDTCisPtrTy<0>, SDTCisVT<1, i32>,
39 SDTCisVT<2, i32>, SDTCisVT<3, i32>]>;
41 def SDT_ARMCmp : SDTypeProfile<0, 2, [SDTCisSameAs<0, 1>]>;
43 def SDT_ARMPICAdd : SDTypeProfile<1, 2, [SDTCisSameAs<0, 1>,
44 SDTCisPtrTy<1>, SDTCisVT<2, i32>]>;
46 def SDT_ARMThreadPointer : SDTypeProfile<1, 0, [SDTCisPtrTy<0>]>;
47 def SDT_ARMEH_SJLJ_Setjmp : SDTypeProfile<1, 1, [SDTCisInt<0>, SDTCisPtrTy<1>]>;
50 def ARMWrapper : SDNode<"ARMISD::Wrapper", SDTIntUnaryOp>;
51 def ARMWrapperJT : SDNode<"ARMISD::WrapperJT", SDTIntBinOp>;
53 def ARMcallseq_start : SDNode<"ISD::CALLSEQ_START", SDT_ARMCallSeqStart,
54 [SDNPHasChain, SDNPOutFlag]>;
55 def ARMcallseq_end : SDNode<"ISD::CALLSEQ_END", SDT_ARMCallSeqEnd,
56 [SDNPHasChain, SDNPOptInFlag, SDNPOutFlag]>;
58 def ARMcall : SDNode<"ARMISD::CALL", SDT_ARMcall,
59 [SDNPHasChain, SDNPOptInFlag, SDNPOutFlag]>;
60 def ARMcall_pred : SDNode<"ARMISD::CALL_PRED", SDT_ARMcall,
61 [SDNPHasChain, SDNPOptInFlag, SDNPOutFlag]>;
62 def ARMcall_nolink : SDNode<"ARMISD::CALL_NOLINK", SDT_ARMcall,
63 [SDNPHasChain, SDNPOptInFlag, SDNPOutFlag]>;
65 def ARMretflag : SDNode<"ARMISD::RET_FLAG", SDTNone,
66 [SDNPHasChain, SDNPOptInFlag]>;
68 def ARMcmov : SDNode<"ARMISD::CMOV", SDT_ARMCMov,
70 def ARMcneg : SDNode<"ARMISD::CNEG", SDT_ARMCMov,
73 def ARMbrcond : SDNode<"ARMISD::BRCOND", SDT_ARMBrcond,
74 [SDNPHasChain, SDNPInFlag, SDNPOutFlag]>;
76 def ARMbrjt : SDNode<"ARMISD::BR_JT", SDT_ARMBrJT,
78 def ARMbr2jt : SDNode<"ARMISD::BR2_JT", SDT_ARMBr2JT,
81 def ARMcmp : SDNode<"ARMISD::CMP", SDT_ARMCmp,
84 def ARMcmpZ : SDNode<"ARMISD::CMPZ", SDT_ARMCmp,
85 [SDNPOutFlag,SDNPCommutative]>;
87 def ARMpic_add : SDNode<"ARMISD::PIC_ADD", SDT_ARMPICAdd>;
89 def ARMsrl_flag : SDNode<"ARMISD::SRL_FLAG", SDTIntUnaryOp, [SDNPOutFlag]>;
90 def ARMsra_flag : SDNode<"ARMISD::SRA_FLAG", SDTIntUnaryOp, [SDNPOutFlag]>;
91 def ARMrrx : SDNode<"ARMISD::RRX" , SDTIntUnaryOp, [SDNPInFlag ]>;
93 def ARMthread_pointer: SDNode<"ARMISD::THREAD_POINTER", SDT_ARMThreadPointer>;
94 def ARMeh_sjlj_setjmp: SDNode<"ARMISD::EH_SJLJ_SETJMP", SDT_ARMEH_SJLJ_Setjmp>;
96 //===----------------------------------------------------------------------===//
97 // ARM Instruction Predicate Definitions.
99 def HasV5T : Predicate<"Subtarget->hasV5TOps()">;
100 def HasV5TE : Predicate<"Subtarget->hasV5TEOps()">;
101 def HasV6 : Predicate<"Subtarget->hasV6Ops()">;
102 def HasV6T2 : Predicate<"Subtarget->hasV6T2Ops()">;
103 def NoV6T2 : Predicate<"!Subtarget->hasV6T2Ops()">;
104 def HasV7 : Predicate<"Subtarget->hasV7Ops()">;
105 def HasVFP2 : Predicate<"Subtarget->hasVFP2()">;
106 def HasVFP3 : Predicate<"Subtarget->hasVFP3()">;
107 def HasNEON : Predicate<"Subtarget->hasNEON()">;
108 def UseNEONForFP : Predicate<"Subtarget->useNEONForSinglePrecisionFP()">;
109 def DontUseNEONForFP : Predicate<"!Subtarget->useNEONForSinglePrecisionFP()">;
110 def IsThumb : Predicate<"Subtarget->isThumb()">;
111 def IsThumb1Only : Predicate<"Subtarget->isThumb1Only()">;
112 def IsThumb2 : Predicate<"Subtarget->isThumb2()">;
113 def IsARM : Predicate<"!Subtarget->isThumb()">;
114 def IsDarwin : Predicate<"Subtarget->isTargetDarwin()">;
115 def IsNotDarwin : Predicate<"!Subtarget->isTargetDarwin()">;
116 def CarryDefIsUnused : Predicate<"!N.getNode()->hasAnyUseOfValue(1)">;
117 def CarryDefIsUsed : Predicate<"N.getNode()->hasAnyUseOfValue(1)">;
119 //===----------------------------------------------------------------------===//
120 // ARM Flag Definitions.
122 class RegConstraint<string C> {
123 string Constraints = C;
126 //===----------------------------------------------------------------------===//
127 // ARM specific transformation functions and pattern fragments.
130 // so_imm_neg_XFORM - Return a so_imm value packed into the format described for
131 // so_imm_neg def below.
132 def so_imm_neg_XFORM : SDNodeXForm<imm, [{
133 return CurDAG->getTargetConstant(-(int)N->getZExtValue(), MVT::i32);
136 // so_imm_not_XFORM - Return a so_imm value packed into the format described for
137 // so_imm_not def below.
138 def so_imm_not_XFORM : SDNodeXForm<imm, [{
139 return CurDAG->getTargetConstant(~(int)N->getZExtValue(), MVT::i32);
142 // rot_imm predicate - True if the 32-bit immediate is equal to 8, 16, or 24.
143 def rot_imm : PatLeaf<(i32 imm), [{
144 int32_t v = (int32_t)N->getZExtValue();
145 return v == 8 || v == 16 || v == 24;
148 /// imm1_15 predicate - True if the 32-bit immediate is in the range [1,15].
149 def imm1_15 : PatLeaf<(i32 imm), [{
150 return (int32_t)N->getZExtValue() >= 1 && (int32_t)N->getZExtValue() < 16;
153 /// imm16_31 predicate - True if the 32-bit immediate is in the range [16,31].
154 def imm16_31 : PatLeaf<(i32 imm), [{
155 return (int32_t)N->getZExtValue() >= 16 && (int32_t)N->getZExtValue() < 32;
160 return ARM_AM::getSOImmVal(-(int)N->getZExtValue()) != -1;
161 }], so_imm_neg_XFORM>;
165 return ARM_AM::getSOImmVal(~(int)N->getZExtValue()) != -1;
166 }], so_imm_not_XFORM>;
168 // sext_16_node predicate - True if the SDNode is sign-extended 16 or more bits.
169 def sext_16_node : PatLeaf<(i32 GPR:$a), [{
170 return CurDAG->ComputeNumSignBits(SDValue(N,0)) >= 17;
173 /// bf_inv_mask_imm predicate - An AND mask to clear an arbitrary width bitfield
175 def bf_inv_mask_imm : Operand<i32>,
177 uint32_t v = (uint32_t)N->getZExtValue();
180 // there can be 1's on either or both "outsides", all the "inside"
182 unsigned int lsb = 0, msb = 31;
183 while (v & (1 << msb)) --msb;
184 while (v & (1 << lsb)) ++lsb;
185 for (unsigned int i = lsb; i <= msb; ++i) {
191 let PrintMethod = "printBitfieldInvMaskImmOperand";
194 /// Split a 32-bit immediate into two 16 bit parts.
195 def lo16 : SDNodeXForm<imm, [{
196 return CurDAG->getTargetConstant((uint32_t)N->getZExtValue() & 0xffff,
200 def hi16 : SDNodeXForm<imm, [{
201 return CurDAG->getTargetConstant((uint32_t)N->getZExtValue() >> 16, MVT::i32);
204 def lo16AllZero : PatLeaf<(i32 imm), [{
205 // Returns true if all low 16-bits are 0.
206 return (((uint32_t)N->getZExtValue()) & 0xFFFFUL) == 0;
209 /// imm0_65535 predicate - True if the 32-bit immediate is in the range
211 def imm0_65535 : PatLeaf<(i32 imm), [{
212 return (uint32_t)N->getZExtValue() < 65536;
215 class BinOpFrag<dag res> : PatFrag<(ops node:$LHS, node:$RHS), res>;
216 class UnOpFrag <dag res> : PatFrag<(ops node:$Src), res>;
218 //===----------------------------------------------------------------------===//
219 // Operand Definitions.
223 def brtarget : Operand<OtherVT>;
225 // A list of registers separated by comma. Used by load/store multiple.
226 def reglist : Operand<i32> {
227 let PrintMethod = "printRegisterList";
230 // An operand for the CONSTPOOL_ENTRY pseudo-instruction.
231 def cpinst_operand : Operand<i32> {
232 let PrintMethod = "printCPInstOperand";
235 def jtblock_operand : Operand<i32> {
236 let PrintMethod = "printJTBlockOperand";
238 def jt2block_operand : Operand<i32> {
239 let PrintMethod = "printJT2BlockOperand";
243 def pclabel : Operand<i32> {
244 let PrintMethod = "printPCLabel";
247 // shifter_operand operands: so_reg and so_imm.
248 def so_reg : Operand<i32>, // reg reg imm
249 ComplexPattern<i32, 3, "SelectShifterOperandReg",
250 [shl,srl,sra,rotr]> {
251 let PrintMethod = "printSORegOperand";
252 let MIOperandInfo = (ops GPR, GPR, i32imm);
255 // so_imm - Match a 32-bit shifter_operand immediate operand, which is an
256 // 8-bit immediate rotated by an arbitrary number of bits. so_imm values are
257 // represented in the imm field in the same 12-bit form that they are encoded
258 // into so_imm instructions: the 8-bit immediate is the least significant bits
259 // [bits 0-7], the 4-bit shift amount is the next 4 bits [bits 8-11].
260 def so_imm : Operand<i32>,
262 return ARM_AM::getSOImmVal(N->getZExtValue()) != -1;
264 let PrintMethod = "printSOImmOperand";
267 // Break so_imm's up into two pieces. This handles immediates with up to 16
268 // bits set in them. This uses so_imm2part to match and so_imm2part_[12] to
269 // get the first/second pieces.
270 def so_imm2part : Operand<i32>,
272 return ARM_AM::isSOImmTwoPartVal((unsigned)N->getZExtValue());
274 let PrintMethod = "printSOImm2PartOperand";
277 def so_imm2part_1 : SDNodeXForm<imm, [{
278 unsigned V = ARM_AM::getSOImmTwoPartFirst((unsigned)N->getZExtValue());
279 return CurDAG->getTargetConstant(V, MVT::i32);
282 def so_imm2part_2 : SDNodeXForm<imm, [{
283 unsigned V = ARM_AM::getSOImmTwoPartSecond((unsigned)N->getZExtValue());
284 return CurDAG->getTargetConstant(V, MVT::i32);
287 /// imm0_31 predicate - True if the 32-bit immediate is in the range [0,31].
288 def imm0_31 : Operand<i32>, PatLeaf<(imm), [{
289 return (int32_t)N->getZExtValue() < 32;
292 // Define ARM specific addressing modes.
294 // addrmode2 := reg +/- reg shop imm
295 // addrmode2 := reg +/- imm12
297 def addrmode2 : Operand<i32>,
298 ComplexPattern<i32, 3, "SelectAddrMode2", []> {
299 let PrintMethod = "printAddrMode2Operand";
300 let MIOperandInfo = (ops GPR:$base, GPR:$offsreg, i32imm:$offsimm);
303 def am2offset : Operand<i32>,
304 ComplexPattern<i32, 2, "SelectAddrMode2Offset", []> {
305 let PrintMethod = "printAddrMode2OffsetOperand";
306 let MIOperandInfo = (ops GPR, i32imm);
309 // addrmode3 := reg +/- reg
310 // addrmode3 := reg +/- imm8
312 def addrmode3 : Operand<i32>,
313 ComplexPattern<i32, 3, "SelectAddrMode3", []> {
314 let PrintMethod = "printAddrMode3Operand";
315 let MIOperandInfo = (ops GPR:$base, GPR:$offsreg, i32imm:$offsimm);
318 def am3offset : Operand<i32>,
319 ComplexPattern<i32, 2, "SelectAddrMode3Offset", []> {
320 let PrintMethod = "printAddrMode3OffsetOperand";
321 let MIOperandInfo = (ops GPR, i32imm);
324 // addrmode4 := reg, <mode|W>
326 def addrmode4 : Operand<i32>,
327 ComplexPattern<i32, 2, "SelectAddrMode4", []> {
328 let PrintMethod = "printAddrMode4Operand";
329 let MIOperandInfo = (ops GPR, i32imm);
332 // addrmode5 := reg +/- imm8*4
334 def addrmode5 : Operand<i32>,
335 ComplexPattern<i32, 2, "SelectAddrMode5", []> {
336 let PrintMethod = "printAddrMode5Operand";
337 let MIOperandInfo = (ops GPR, i32imm);
340 // addrmode6 := reg with optional writeback
342 def addrmode6 : Operand<i32>,
343 ComplexPattern<i32, 4, "SelectAddrMode6", []> {
344 let PrintMethod = "printAddrMode6Operand";
345 let MIOperandInfo = (ops GPR:$addr, GPR:$upd, i32imm, i32imm);
348 // addrmodepc := pc + reg
350 def addrmodepc : Operand<i32>,
351 ComplexPattern<i32, 2, "SelectAddrModePC", []> {
352 let PrintMethod = "printAddrModePCOperand";
353 let MIOperandInfo = (ops GPR, i32imm);
356 def nohash_imm : Operand<i32> {
357 let PrintMethod = "printNoHashImmediate";
360 //===----------------------------------------------------------------------===//
362 include "ARMInstrFormats.td"
364 //===----------------------------------------------------------------------===//
365 // Multiclass helpers...
368 /// AsI1_bin_irs - Defines a set of (op r, {so_imm|r|so_reg}) patterns for a
369 /// binop that produces a value.
370 multiclass AsI1_bin_irs<bits<4> opcod, string opc, PatFrag opnode,
371 bit Commutable = 0> {
372 def ri : AsI1<opcod, (outs GPR:$dst), (ins GPR:$a, so_imm:$b), DPFrm,
373 IIC_iALUi, opc, "\t$dst, $a, $b",
374 [(set GPR:$dst, (opnode GPR:$a, so_imm:$b))]> {
377 def rr : AsI1<opcod, (outs GPR:$dst), (ins GPR:$a, GPR:$b), DPFrm,
378 IIC_iALUr, opc, "\t$dst, $a, $b",
379 [(set GPR:$dst, (opnode GPR:$a, GPR:$b))]> {
380 let Inst{11-4} = 0b00000000;
382 let isCommutable = Commutable;
384 def rs : AsI1<opcod, (outs GPR:$dst), (ins GPR:$a, so_reg:$b), DPSoRegFrm,
385 IIC_iALUsr, opc, "\t$dst, $a, $b",
386 [(set GPR:$dst, (opnode GPR:$a, so_reg:$b))]> {
391 /// AI1_bin_s_irs - Similar to AsI1_bin_irs except it sets the 's' bit so the
392 /// instruction modifies the CPSR register.
393 let Defs = [CPSR] in {
394 multiclass AI1_bin_s_irs<bits<4> opcod, string opc, PatFrag opnode,
395 bit Commutable = 0> {
396 def ri : AI1<opcod, (outs GPR:$dst), (ins GPR:$a, so_imm:$b), DPFrm,
397 IIC_iALUi, opc, "\t$dst, $a, $b",
398 [(set GPR:$dst, (opnode GPR:$a, so_imm:$b))]> {
402 def rr : AI1<opcod, (outs GPR:$dst), (ins GPR:$a, GPR:$b), DPFrm,
403 IIC_iALUr, opc, "\t$dst, $a, $b",
404 [(set GPR:$dst, (opnode GPR:$a, GPR:$b))]> {
405 let isCommutable = Commutable;
406 let Inst{11-4} = 0b00000000;
410 def rs : AI1<opcod, (outs GPR:$dst), (ins GPR:$a, so_reg:$b), DPSoRegFrm,
411 IIC_iALUsr, opc, "\t$dst, $a, $b",
412 [(set GPR:$dst, (opnode GPR:$a, so_reg:$b))]> {
419 /// AI1_cmp_irs - Defines a set of (op r, {so_imm|r|so_reg}) cmp / test
420 /// patterns. Similar to AsI1_bin_irs except the instruction does not produce
421 /// a explicit result, only implicitly set CPSR.
422 let Defs = [CPSR] in {
423 multiclass AI1_cmp_irs<bits<4> opcod, string opc, PatFrag opnode,
424 bit Commutable = 0> {
425 def ri : AI1<opcod, (outs), (ins GPR:$a, so_imm:$b), DPFrm, IIC_iCMPi,
427 [(opnode GPR:$a, so_imm:$b)]> {
431 def rr : AI1<opcod, (outs), (ins GPR:$a, GPR:$b), DPFrm, IIC_iCMPr,
433 [(opnode GPR:$a, GPR:$b)]> {
434 let Inst{11-4} = 0b00000000;
437 let isCommutable = Commutable;
439 def rs : AI1<opcod, (outs), (ins GPR:$a, so_reg:$b), DPSoRegFrm, IIC_iCMPsr,
441 [(opnode GPR:$a, so_reg:$b)]> {
448 /// AI_unary_rrot - A unary operation with two forms: one whose operand is a
449 /// register and one whose operand is a register rotated by 8/16/24.
450 /// FIXME: Remove the 'r' variant. Its rot_imm is zero.
451 multiclass AI_unary_rrot<bits<8> opcod, string opc, PatFrag opnode> {
452 def r : AExtI<opcod, (outs GPR:$dst), (ins GPR:$src),
453 IIC_iUNAr, opc, "\t$dst, $src",
454 [(set GPR:$dst, (opnode GPR:$src))]>,
455 Requires<[IsARM, HasV6]> {
456 let Inst{11-10} = 0b00;
457 let Inst{19-16} = 0b1111;
459 def r_rot : AExtI<opcod, (outs GPR:$dst), (ins GPR:$src, i32imm:$rot),
460 IIC_iUNAsi, opc, "\t$dst, $src, ror $rot",
461 [(set GPR:$dst, (opnode (rotr GPR:$src, rot_imm:$rot)))]>,
462 Requires<[IsARM, HasV6]> {
463 let Inst{19-16} = 0b1111;
467 /// AI_bin_rrot - A binary operation with two forms: one whose operand is a
468 /// register and one whose operand is a register rotated by 8/16/24.
469 multiclass AI_bin_rrot<bits<8> opcod, string opc, PatFrag opnode> {
470 def rr : AExtI<opcod, (outs GPR:$dst), (ins GPR:$LHS, GPR:$RHS),
471 IIC_iALUr, opc, "\t$dst, $LHS, $RHS",
472 [(set GPR:$dst, (opnode GPR:$LHS, GPR:$RHS))]>,
473 Requires<[IsARM, HasV6]> {
474 let Inst{11-10} = 0b00;
476 def rr_rot : AExtI<opcod, (outs GPR:$dst), (ins GPR:$LHS, GPR:$RHS, i32imm:$rot),
477 IIC_iALUsi, opc, "\t$dst, $LHS, $RHS, ror $rot",
478 [(set GPR:$dst, (opnode GPR:$LHS,
479 (rotr GPR:$RHS, rot_imm:$rot)))]>,
480 Requires<[IsARM, HasV6]>;
483 /// AI1_adde_sube_irs - Define instructions and patterns for adde and sube.
484 let Uses = [CPSR] in {
485 multiclass AI1_adde_sube_irs<bits<4> opcod, string opc, PatFrag opnode,
486 bit Commutable = 0> {
487 def ri : AsI1<opcod, (outs GPR:$dst), (ins GPR:$a, so_imm:$b),
488 DPFrm, IIC_iALUi, opc, "\t$dst, $a, $b",
489 [(set GPR:$dst, (opnode GPR:$a, so_imm:$b))]>,
490 Requires<[IsARM, CarryDefIsUnused]> {
493 def rr : AsI1<opcod, (outs GPR:$dst), (ins GPR:$a, GPR:$b),
494 DPFrm, IIC_iALUr, opc, "\t$dst, $a, $b",
495 [(set GPR:$dst, (opnode GPR:$a, GPR:$b))]>,
496 Requires<[IsARM, CarryDefIsUnused]> {
497 let isCommutable = Commutable;
498 let Inst{11-4} = 0b00000000;
501 def rs : AsI1<opcod, (outs GPR:$dst), (ins GPR:$a, so_reg:$b),
502 DPSoRegFrm, IIC_iALUsr, opc, "\t$dst, $a, $b",
503 [(set GPR:$dst, (opnode GPR:$a, so_reg:$b))]>,
504 Requires<[IsARM, CarryDefIsUnused]> {
508 // Carry setting variants
509 let Defs = [CPSR] in {
510 multiclass AI1_adde_sube_s_irs<bits<4> opcod, string opc, PatFrag opnode,
511 bit Commutable = 0> {
512 def Sri : AXI1<opcod, (outs GPR:$dst), (ins GPR:$a, so_imm:$b),
513 DPFrm, IIC_iALUi, !strconcat(opc, "\t$dst, $a, $b"),
514 [(set GPR:$dst, (opnode GPR:$a, so_imm:$b))]>,
515 Requires<[IsARM, CarryDefIsUsed]> {
520 def Srr : AXI1<opcod, (outs GPR:$dst), (ins GPR:$a, GPR:$b),
521 DPFrm, IIC_iALUr, !strconcat(opc, "\t$dst, $a, $b"),
522 [(set GPR:$dst, (opnode GPR:$a, GPR:$b))]>,
523 Requires<[IsARM, CarryDefIsUsed]> {
525 let Inst{11-4} = 0b00000000;
529 def Srs : AXI1<opcod, (outs GPR:$dst), (ins GPR:$a, so_reg:$b),
530 DPSoRegFrm, IIC_iALUsr, !strconcat(opc, "\t$dst, $a, $b"),
531 [(set GPR:$dst, (opnode GPR:$a, so_reg:$b))]>,
532 Requires<[IsARM, CarryDefIsUsed]> {
541 //===----------------------------------------------------------------------===//
543 //===----------------------------------------------------------------------===//
545 //===----------------------------------------------------------------------===//
546 // Miscellaneous Instructions.
549 /// CONSTPOOL_ENTRY - This instruction represents a floating constant pool in
550 /// the function. The first operand is the ID# for this instruction, the second
551 /// is the index into the MachineConstantPool that this is, the third is the
552 /// size in bytes of this constant pool entry.
553 let neverHasSideEffects = 1, isNotDuplicable = 1 in
554 def CONSTPOOL_ENTRY :
555 PseudoInst<(outs), (ins cpinst_operand:$instid, cpinst_operand:$cpidx,
556 i32imm:$size), NoItinerary,
557 "${instid:label} ${cpidx:cpentry}", []>;
559 let Defs = [SP], Uses = [SP] in {
561 PseudoInst<(outs), (ins i32imm:$amt1, i32imm:$amt2, pred:$p), NoItinerary,
562 "@ ADJCALLSTACKUP $amt1",
563 [(ARMcallseq_end timm:$amt1, timm:$amt2)]>;
565 def ADJCALLSTACKDOWN :
566 PseudoInst<(outs), (ins i32imm:$amt, pred:$p), NoItinerary,
567 "@ ADJCALLSTACKDOWN $amt",
568 [(ARMcallseq_start timm:$amt)]>;
572 PseudoInst<(outs), (ins i32imm:$line, i32imm:$col, i32imm:$file), NoItinerary,
573 ".loc $file, $line, $col",
574 [(dwarf_loc (i32 imm:$line), (i32 imm:$col), (i32 imm:$file))]>;
577 // Address computation and loads and stores in PIC mode.
578 let isNotDuplicable = 1 in {
579 def PICADD : AXI1<0b0100, (outs GPR:$dst), (ins GPR:$a, pclabel:$cp, pred:$p),
580 Pseudo, IIC_iALUr, "\n$cp:\n\tadd$p\t$dst, pc, $a",
581 [(set GPR:$dst, (ARMpic_add GPR:$a, imm:$cp))]>;
583 let AddedComplexity = 10 in {
584 let canFoldAsLoad = 1 in
585 def PICLDR : AXI2ldw<(outs GPR:$dst), (ins addrmodepc:$addr, pred:$p),
586 Pseudo, IIC_iLoadr, "\n${addr:label}:\n\tldr$p\t$dst, $addr",
587 [(set GPR:$dst, (load addrmodepc:$addr))]>;
589 def PICLDRH : AXI3ldh<(outs GPR:$dst), (ins addrmodepc:$addr, pred:$p),
590 Pseudo, IIC_iLoadr, "\n${addr:label}:\n\tldr${p}h\t$dst, $addr",
591 [(set GPR:$dst, (zextloadi16 addrmodepc:$addr))]>;
593 def PICLDRB : AXI2ldb<(outs GPR:$dst), (ins addrmodepc:$addr, pred:$p),
594 Pseudo, IIC_iLoadr, "\n${addr:label}:\n\tldr${p}b\t$dst, $addr",
595 [(set GPR:$dst, (zextloadi8 addrmodepc:$addr))]>;
597 def PICLDRSH : AXI3ldsh<(outs GPR:$dst), (ins addrmodepc:$addr, pred:$p),
598 Pseudo, IIC_iLoadr, "\n${addr:label}:\n\tldr${p}sh\t$dst, $addr",
599 [(set GPR:$dst, (sextloadi16 addrmodepc:$addr))]>;
601 def PICLDRSB : AXI3ldsb<(outs GPR:$dst), (ins addrmodepc:$addr, pred:$p),
602 Pseudo, IIC_iLoadr, "\n${addr:label}:\n\tldr${p}sb\t$dst, $addr",
603 [(set GPR:$dst, (sextloadi8 addrmodepc:$addr))]>;
605 let AddedComplexity = 10 in {
606 def PICSTR : AXI2stw<(outs), (ins GPR:$src, addrmodepc:$addr, pred:$p),
607 Pseudo, IIC_iStorer, "\n${addr:label}:\n\tstr$p\t$src, $addr",
608 [(store GPR:$src, addrmodepc:$addr)]>;
610 def PICSTRH : AXI3sth<(outs), (ins GPR:$src, addrmodepc:$addr, pred:$p),
611 Pseudo, IIC_iStorer, "\n${addr:label}:\n\tstr${p}h\t$src, $addr",
612 [(truncstorei16 GPR:$src, addrmodepc:$addr)]>;
614 def PICSTRB : AXI2stb<(outs), (ins GPR:$src, addrmodepc:$addr, pred:$p),
615 Pseudo, IIC_iStorer, "\n${addr:label}:\n\tstr${p}b\t$src, $addr",
616 [(truncstorei8 GPR:$src, addrmodepc:$addr)]>;
618 } // isNotDuplicable = 1
621 // LEApcrel - Load a pc-relative address into a register without offending the
623 def LEApcrel : AXI1<0x0, (outs GPR:$dst), (ins i32imm:$label, pred:$p),
625 !strconcat(!strconcat(".set ${:private}PCRELV${:uid}, ($label-(",
626 "${:private}PCRELL${:uid}+8))\n"),
627 !strconcat("${:private}PCRELL${:uid}:\n\t",
628 "add$p\t$dst, pc, #${:private}PCRELV${:uid}")),
631 def LEApcrelJT : AXI1<0x0, (outs GPR:$dst),
632 (ins i32imm:$label, nohash_imm:$id, pred:$p),
634 !strconcat(!strconcat(".set ${:private}PCRELV${:uid}, "
636 "${:private}PCRELL${:uid}+8))\n"),
637 !strconcat("${:private}PCRELL${:uid}:\n\t",
638 "add$p\t$dst, pc, #${:private}PCRELV${:uid}")),
643 //===----------------------------------------------------------------------===//
644 // Control Flow Instructions.
647 let isReturn = 1, isTerminator = 1, isBarrier = 1 in
648 def BX_RET : AI<(outs), (ins), BrMiscFrm, IIC_Br,
649 "bx", "\tlr", [(ARMretflag)]> {
650 let Inst{7-4} = 0b0001;
651 let Inst{19-8} = 0b111111111111;
652 let Inst{27-20} = 0b00010010;
656 let isBranch = 1, isTerminator = 1, isBarrier = 1, isIndirectBranch = 1 in {
657 def BRIND : AXI<(outs), (ins GPR:$dst), BrMiscFrm, IIC_Br, "bx\t$dst",
658 [(brind GPR:$dst)]> {
659 let Inst{7-4} = 0b0001;
660 let Inst{19-8} = 0b111111111111;
661 let Inst{27-20} = 0b00010010;
665 // FIXME: remove when we have a way to marking a MI with these properties.
666 // FIXME: Should pc be an implicit operand like PICADD, etc?
667 let isReturn = 1, isTerminator = 1, isBarrier = 1, mayLoad = 1,
668 hasExtraDefRegAllocReq = 1 in
669 def LDM_RET : AXI4ld<(outs),
670 (ins addrmode4:$addr, pred:$p, reglist:$wb, variable_ops),
671 LdStMulFrm, IIC_Br, "ldm${addr:submode}${p}\t$addr, $wb",
674 // On non-Darwin platforms R9 is callee-saved.
676 Defs = [R0, R1, R2, R3, R12, LR,
677 D0, D1, D2, D3, D4, D5, D6, D7,
678 D16, D17, D18, D19, D20, D21, D22, D23,
679 D24, D25, D26, D27, D28, D29, D30, D31, CPSR, FPSCR] in {
680 def BL : ABXI<0b1011, (outs), (ins i32imm:$func, variable_ops),
681 IIC_Br, "bl\t${func:call}",
682 [(ARMcall tglobaladdr:$func)]>,
683 Requires<[IsARM, IsNotDarwin]> {
684 let Inst{31-28} = 0b1110;
687 def BL_pred : ABI<0b1011, (outs), (ins i32imm:$func, variable_ops),
688 IIC_Br, "bl", "\t${func:call}",
689 [(ARMcall_pred tglobaladdr:$func)]>,
690 Requires<[IsARM, IsNotDarwin]>;
693 def BLX : AXI<(outs), (ins GPR:$func, variable_ops), BrMiscFrm,
694 IIC_Br, "blx\t$func",
695 [(ARMcall GPR:$func)]>,
696 Requires<[IsARM, HasV5T, IsNotDarwin]> {
697 let Inst{7-4} = 0b0011;
698 let Inst{19-8} = 0b111111111111;
699 let Inst{27-20} = 0b00010010;
703 def BX : ABXIx2<(outs), (ins GPR:$func, variable_ops),
704 IIC_Br, "mov\tlr, pc\n\tbx\t$func",
705 [(ARMcall_nolink GPR:$func)]>,
706 Requires<[IsARM, IsNotDarwin]> {
707 let Inst{7-4} = 0b0001;
708 let Inst{19-8} = 0b111111111111;
709 let Inst{27-20} = 0b00010010;
713 // On Darwin R9 is call-clobbered.
715 Defs = [R0, R1, R2, R3, R9, R12, LR,
716 D0, D1, D2, D3, D4, D5, D6, D7,
717 D16, D17, D18, D19, D20, D21, D22, D23,
718 D24, D25, D26, D27, D28, D29, D30, D31, CPSR, FPSCR] in {
719 def BLr9 : ABXI<0b1011, (outs), (ins i32imm:$func, variable_ops),
720 IIC_Br, "bl\t${func:call}",
721 [(ARMcall tglobaladdr:$func)]>, Requires<[IsARM, IsDarwin]> {
722 let Inst{31-28} = 0b1110;
725 def BLr9_pred : ABI<0b1011, (outs), (ins i32imm:$func, variable_ops),
726 IIC_Br, "bl", "\t${func:call}",
727 [(ARMcall_pred tglobaladdr:$func)]>,
728 Requires<[IsARM, IsDarwin]>;
731 def BLXr9 : AXI<(outs), (ins GPR:$func, variable_ops), BrMiscFrm,
732 IIC_Br, "blx\t$func",
733 [(ARMcall GPR:$func)]>, Requires<[IsARM, HasV5T, IsDarwin]> {
734 let Inst{7-4} = 0b0011;
735 let Inst{19-8} = 0b111111111111;
736 let Inst{27-20} = 0b00010010;
740 def BXr9 : ABXIx2<(outs), (ins GPR:$func, variable_ops),
741 IIC_Br, "mov\tlr, pc\n\tbx\t$func",
742 [(ARMcall_nolink GPR:$func)]>, Requires<[IsARM, IsDarwin]> {
743 let Inst{7-4} = 0b0001;
744 let Inst{19-8} = 0b111111111111;
745 let Inst{27-20} = 0b00010010;
749 let isBranch = 1, isTerminator = 1 in {
750 // B is "predicable" since it can be xformed into a Bcc.
751 let isBarrier = 1 in {
752 let isPredicable = 1 in
753 def B : ABXI<0b1010, (outs), (ins brtarget:$target), IIC_Br,
754 "b\t$target", [(br bb:$target)]>;
756 let isNotDuplicable = 1, isIndirectBranch = 1 in {
757 def BR_JTr : JTI<(outs), (ins GPR:$target, jtblock_operand:$jt, i32imm:$id),
758 IIC_Br, "mov\tpc, $target \n$jt",
759 [(ARMbrjt GPR:$target, tjumptable:$jt, imm:$id)]> {
760 let Inst{20} = 0; // S Bit
761 let Inst{24-21} = 0b1101;
762 let Inst{27-25} = 0b000;
764 def BR_JTm : JTI<(outs),
765 (ins addrmode2:$target, jtblock_operand:$jt, i32imm:$id),
766 IIC_Br, "ldr\tpc, $target \n$jt",
767 [(ARMbrjt (i32 (load addrmode2:$target)), tjumptable:$jt,
769 let Inst{20} = 1; // L bit
770 let Inst{21} = 0; // W bit
771 let Inst{22} = 0; // B bit
772 let Inst{24} = 1; // P bit
773 let Inst{27-25} = 0b011;
775 def BR_JTadd : JTI<(outs),
776 (ins GPR:$target, GPR:$idx, jtblock_operand:$jt, i32imm:$id),
777 IIC_Br, "add\tpc, $target, $idx \n$jt",
778 [(ARMbrjt (add GPR:$target, GPR:$idx), tjumptable:$jt,
780 let Inst{20} = 0; // S bit
781 let Inst{24-21} = 0b0100;
782 let Inst{27-25} = 0b000;
784 } // isNotDuplicable = 1, isIndirectBranch = 1
787 // FIXME: should be able to write a pattern for ARMBrcond, but can't use
788 // a two-value operand where a dag node expects two operands. :(
789 def Bcc : ABI<0b1010, (outs), (ins brtarget:$target),
790 IIC_Br, "b", "\t$target",
791 [/*(ARMbrcond bb:$target, imm:$cc, CCR:$ccr)*/]>;
794 //===----------------------------------------------------------------------===//
795 // Load / store Instructions.
799 let canFoldAsLoad = 1, isReMaterializable = 1 in
800 def LDR : AI2ldw<(outs GPR:$dst), (ins addrmode2:$addr), LdFrm, IIC_iLoadr,
801 "ldr", "\t$dst, $addr",
802 [(set GPR:$dst, (load addrmode2:$addr))]>;
804 // Special LDR for loads from non-pc-relative constpools.
805 let canFoldAsLoad = 1, mayLoad = 1, isReMaterializable = 1 in
806 def LDRcp : AI2ldw<(outs GPR:$dst), (ins addrmode2:$addr), LdFrm, IIC_iLoadr,
807 "ldr", "\t$dst, $addr", []>;
809 // Loads with zero extension
810 def LDRH : AI3ldh<(outs GPR:$dst), (ins addrmode3:$addr), LdMiscFrm,
811 IIC_iLoadr, "ldrh", "\t$dst, $addr",
812 [(set GPR:$dst, (zextloadi16 addrmode3:$addr))]>;
814 def LDRB : AI2ldb<(outs GPR:$dst), (ins addrmode2:$addr), LdFrm,
815 IIC_iLoadr, "ldrb", "\t$dst, $addr",
816 [(set GPR:$dst, (zextloadi8 addrmode2:$addr))]>;
818 // Loads with sign extension
819 def LDRSH : AI3ldsh<(outs GPR:$dst), (ins addrmode3:$addr), LdMiscFrm,
820 IIC_iLoadr, "ldrsh", "\t$dst, $addr",
821 [(set GPR:$dst, (sextloadi16 addrmode3:$addr))]>;
823 def LDRSB : AI3ldsb<(outs GPR:$dst), (ins addrmode3:$addr), LdMiscFrm,
824 IIC_iLoadr, "ldrsb", "\t$dst, $addr",
825 [(set GPR:$dst, (sextloadi8 addrmode3:$addr))]>;
827 let mayLoad = 1, hasExtraDefRegAllocReq = 1 in {
829 def LDRD : AI3ldd<(outs GPR:$dst1, GPR:$dst2), (ins addrmode3:$addr), LdMiscFrm,
830 IIC_iLoadr, "ldrd", "\t$dst1, $addr",
831 []>, Requires<[IsARM, HasV5TE]>;
834 def LDR_PRE : AI2ldwpr<(outs GPR:$dst, GPR:$base_wb),
835 (ins addrmode2:$addr), LdFrm, IIC_iLoadru,
836 "ldr", "\t$dst, $addr!", "$addr.base = $base_wb", []>;
838 def LDR_POST : AI2ldwpo<(outs GPR:$dst, GPR:$base_wb),
839 (ins GPR:$base, am2offset:$offset), LdFrm, IIC_iLoadru,
840 "ldr", "\t$dst, [$base], $offset", "$base = $base_wb", []>;
842 def LDRH_PRE : AI3ldhpr<(outs GPR:$dst, GPR:$base_wb),
843 (ins addrmode3:$addr), LdMiscFrm, IIC_iLoadru,
844 "ldrh", "\t$dst, $addr!", "$addr.base = $base_wb", []>;
846 def LDRH_POST : AI3ldhpo<(outs GPR:$dst, GPR:$base_wb),
847 (ins GPR:$base,am3offset:$offset), LdMiscFrm, IIC_iLoadru,
848 "ldrh", "\t$dst, [$base], $offset", "$base = $base_wb", []>;
850 def LDRB_PRE : AI2ldbpr<(outs GPR:$dst, GPR:$base_wb),
851 (ins addrmode2:$addr), LdFrm, IIC_iLoadru,
852 "ldrb", "\t$dst, $addr!", "$addr.base = $base_wb", []>;
854 def LDRB_POST : AI2ldbpo<(outs GPR:$dst, GPR:$base_wb),
855 (ins GPR:$base,am2offset:$offset), LdFrm, IIC_iLoadru,
856 "ldrb", "\t$dst, [$base], $offset", "$base = $base_wb", []>;
858 def LDRSH_PRE : AI3ldshpr<(outs GPR:$dst, GPR:$base_wb),
859 (ins addrmode3:$addr), LdMiscFrm, IIC_iLoadru,
860 "ldrsh", "\t$dst, $addr!", "$addr.base = $base_wb", []>;
862 def LDRSH_POST: AI3ldshpo<(outs GPR:$dst, GPR:$base_wb),
863 (ins GPR:$base,am3offset:$offset), LdMiscFrm, IIC_iLoadru,
864 "ldrsh", "\t$dst, [$base], $offset", "$base = $base_wb", []>;
866 def LDRSB_PRE : AI3ldsbpr<(outs GPR:$dst, GPR:$base_wb),
867 (ins addrmode3:$addr), LdMiscFrm, IIC_iLoadru,
868 "ldrsb", "\t$dst, $addr!", "$addr.base = $base_wb", []>;
870 def LDRSB_POST: AI3ldsbpo<(outs GPR:$dst, GPR:$base_wb),
871 (ins GPR:$base,am3offset:$offset), LdMiscFrm, IIC_iLoadru,
872 "ldrsb", "\t$dst, [$base], $offset", "$base = $base_wb", []>;
876 def STR : AI2stw<(outs), (ins GPR:$src, addrmode2:$addr), StFrm, IIC_iStorer,
877 "str", "\t$src, $addr",
878 [(store GPR:$src, addrmode2:$addr)]>;
880 // Stores with truncate
881 def STRH : AI3sth<(outs), (ins GPR:$src, addrmode3:$addr), StMiscFrm, IIC_iStorer,
882 "strh", "\t$src, $addr",
883 [(truncstorei16 GPR:$src, addrmode3:$addr)]>;
885 def STRB : AI2stb<(outs), (ins GPR:$src, addrmode2:$addr), StFrm, IIC_iStorer,
886 "strb", "\t$src, $addr",
887 [(truncstorei8 GPR:$src, addrmode2:$addr)]>;
890 let mayStore = 1, hasExtraSrcRegAllocReq = 1 in
891 def STRD : AI3std<(outs), (ins GPR:$src1, GPR:$src2, addrmode3:$addr),
892 StMiscFrm, IIC_iStorer,
893 "strd", "\t$src1, $addr", []>, Requires<[IsARM, HasV5TE]>;
896 def STR_PRE : AI2stwpr<(outs GPR:$base_wb),
897 (ins GPR:$src, GPR:$base, am2offset:$offset),
899 "str", "\t$src, [$base, $offset]!", "$base = $base_wb",
901 (pre_store GPR:$src, GPR:$base, am2offset:$offset))]>;
903 def STR_POST : AI2stwpo<(outs GPR:$base_wb),
904 (ins GPR:$src, GPR:$base,am2offset:$offset),
906 "str", "\t$src, [$base], $offset", "$base = $base_wb",
908 (post_store GPR:$src, GPR:$base, am2offset:$offset))]>;
910 def STRH_PRE : AI3sthpr<(outs GPR:$base_wb),
911 (ins GPR:$src, GPR:$base,am3offset:$offset),
912 StMiscFrm, IIC_iStoreru,
913 "strh", "\t$src, [$base, $offset]!", "$base = $base_wb",
915 (pre_truncsti16 GPR:$src, GPR:$base,am3offset:$offset))]>;
917 def STRH_POST: AI3sthpo<(outs GPR:$base_wb),
918 (ins GPR:$src, GPR:$base,am3offset:$offset),
919 StMiscFrm, IIC_iStoreru,
920 "strh", "\t$src, [$base], $offset", "$base = $base_wb",
921 [(set GPR:$base_wb, (post_truncsti16 GPR:$src,
922 GPR:$base, am3offset:$offset))]>;
924 def STRB_PRE : AI2stbpr<(outs GPR:$base_wb),
925 (ins GPR:$src, GPR:$base,am2offset:$offset),
927 "strb", "\t$src, [$base, $offset]!", "$base = $base_wb",
928 [(set GPR:$base_wb, (pre_truncsti8 GPR:$src,
929 GPR:$base, am2offset:$offset))]>;
931 def STRB_POST: AI2stbpo<(outs GPR:$base_wb),
932 (ins GPR:$src, GPR:$base,am2offset:$offset),
934 "strb", "\t$src, [$base], $offset", "$base = $base_wb",
935 [(set GPR:$base_wb, (post_truncsti8 GPR:$src,
936 GPR:$base, am2offset:$offset))]>;
938 //===----------------------------------------------------------------------===//
939 // Load / store multiple Instructions.
942 let mayLoad = 1, hasExtraDefRegAllocReq = 1 in
943 def LDM : AXI4ld<(outs),
944 (ins addrmode4:$addr, pred:$p, reglist:$wb, variable_ops),
945 LdStMulFrm, IIC_iLoadm, "ldm${addr:submode}${p}\t$addr, $wb",
948 let mayStore = 1, hasExtraSrcRegAllocReq = 1 in
949 def STM : AXI4st<(outs),
950 (ins addrmode4:$addr, pred:$p, reglist:$wb, variable_ops),
951 LdStMulFrm, IIC_iStorem, "stm${addr:submode}${p}\t$addr, $wb",
954 //===----------------------------------------------------------------------===//
955 // Move Instructions.
958 let neverHasSideEffects = 1 in
959 def MOVr : AsI1<0b1101, (outs GPR:$dst), (ins GPR:$src), DPFrm, IIC_iMOVr,
960 "mov", "\t$dst, $src", []>, UnaryDP {
961 let Inst{11-4} = 0b00000000;
965 def MOVs : AsI1<0b1101, (outs GPR:$dst), (ins so_reg:$src),
966 DPSoRegFrm, IIC_iMOVsr,
967 "mov", "\t$dst, $src", [(set GPR:$dst, so_reg:$src)]>, UnaryDP {
971 let isReMaterializable = 1, isAsCheapAsAMove = 1 in
972 def MOVi : AsI1<0b1101, (outs GPR:$dst), (ins so_imm:$src), DPFrm, IIC_iMOVi,
973 "mov", "\t$dst, $src", [(set GPR:$dst, so_imm:$src)]>, UnaryDP {
977 let isReMaterializable = 1, isAsCheapAsAMove = 1 in
978 def MOVi16 : AI1<0b1000, (outs GPR:$dst), (ins i32imm:$src),
980 "movw", "\t$dst, $src",
981 [(set GPR:$dst, imm0_65535:$src)]>,
982 Requires<[IsARM, HasV6T2]> {
987 let Constraints = "$src = $dst" in
988 def MOVTi16 : AI1<0b1010, (outs GPR:$dst), (ins GPR:$src, i32imm:$imm),
990 "movt", "\t$dst, $imm",
992 (or (and GPR:$src, 0xffff),
993 lo16AllZero:$imm))]>, UnaryDP,
994 Requires<[IsARM, HasV6T2]> {
999 def : ARMPat<(or GPR:$src, 0xffff0000), (MOVTi16 GPR:$src, 0xffff)>,
1000 Requires<[IsARM, HasV6T2]>;
1002 let Uses = [CPSR] in
1003 def MOVrx : AsI1<0b1101, (outs GPR:$dst), (ins GPR:$src), Pseudo, IIC_iMOVsi,
1004 "mov", "\t$dst, $src, rrx",
1005 [(set GPR:$dst, (ARMrrx GPR:$src))]>, UnaryDP;
1007 // These aren't really mov instructions, but we have to define them this way
1008 // due to flag operands.
1010 let Defs = [CPSR] in {
1011 def MOVsrl_flag : AI1<0b1101, (outs GPR:$dst), (ins GPR:$src), Pseudo,
1012 IIC_iMOVsi, "movs", "\t$dst, $src, lsr #1",
1013 [(set GPR:$dst, (ARMsrl_flag GPR:$src))]>, UnaryDP;
1014 def MOVsra_flag : AI1<0b1101, (outs GPR:$dst), (ins GPR:$src), Pseudo,
1015 IIC_iMOVsi, "movs", "\t$dst, $src, asr #1",
1016 [(set GPR:$dst, (ARMsra_flag GPR:$src))]>, UnaryDP;
1019 //===----------------------------------------------------------------------===//
1020 // Extend Instructions.
1025 defm SXTB : AI_unary_rrot<0b01101010,
1026 "sxtb", UnOpFrag<(sext_inreg node:$Src, i8)>>;
1027 defm SXTH : AI_unary_rrot<0b01101011,
1028 "sxth", UnOpFrag<(sext_inreg node:$Src, i16)>>;
1030 defm SXTAB : AI_bin_rrot<0b01101010,
1031 "sxtab", BinOpFrag<(add node:$LHS, (sext_inreg node:$RHS, i8))>>;
1032 defm SXTAH : AI_bin_rrot<0b01101011,
1033 "sxtah", BinOpFrag<(add node:$LHS, (sext_inreg node:$RHS,i16))>>;
1035 // TODO: SXT(A){B|H}16
1039 let AddedComplexity = 16 in {
1040 defm UXTB : AI_unary_rrot<0b01101110,
1041 "uxtb" , UnOpFrag<(and node:$Src, 0x000000FF)>>;
1042 defm UXTH : AI_unary_rrot<0b01101111,
1043 "uxth" , UnOpFrag<(and node:$Src, 0x0000FFFF)>>;
1044 defm UXTB16 : AI_unary_rrot<0b01101100,
1045 "uxtb16", UnOpFrag<(and node:$Src, 0x00FF00FF)>>;
1047 def : ARMV6Pat<(and (shl GPR:$Src, (i32 8)), 0xFF00FF),
1048 (UXTB16r_rot GPR:$Src, 24)>;
1049 def : ARMV6Pat<(and (srl GPR:$Src, (i32 8)), 0xFF00FF),
1050 (UXTB16r_rot GPR:$Src, 8)>;
1052 defm UXTAB : AI_bin_rrot<0b01101110, "uxtab",
1053 BinOpFrag<(add node:$LHS, (and node:$RHS, 0x00FF))>>;
1054 defm UXTAH : AI_bin_rrot<0b01101111, "uxtah",
1055 BinOpFrag<(add node:$LHS, (and node:$RHS, 0xFFFF))>>;
1058 // This isn't safe in general, the add is two 16-bit units, not a 32-bit add.
1059 //defm UXTAB16 : xxx<"uxtab16", 0xff00ff>;
1061 // TODO: UXT(A){B|H}16
1063 def SBFX : I<(outs GPR:$dst),
1064 (ins GPR:$src, imm0_31:$lsb, imm0_31:$width),
1065 AddrMode1, Size4Bytes, IndexModeNone, DPFrm, IIC_iALUi,
1066 "sbfx", "\t$dst, $src, $lsb, $width", "", []>,
1067 Requires<[IsARM, HasV6T2]> {
1068 let Inst{27-21} = 0b0111101;
1069 let Inst{6-4} = 0b101;
1072 def UBFX : I<(outs GPR:$dst),
1073 (ins GPR:$src, imm0_31:$lsb, imm0_31:$width),
1074 AddrMode1, Size4Bytes, IndexModeNone, DPFrm, IIC_iALUi,
1075 "ubfx", "\t$dst, $src, $lsb, $width", "", []>,
1076 Requires<[IsARM, HasV6T2]> {
1077 let Inst{27-21} = 0b0111111;
1078 let Inst{6-4} = 0b101;
1081 //===----------------------------------------------------------------------===//
1082 // Arithmetic Instructions.
1085 defm ADD : AsI1_bin_irs<0b0100, "add",
1086 BinOpFrag<(add node:$LHS, node:$RHS)>, 1>;
1087 defm SUB : AsI1_bin_irs<0b0010, "sub",
1088 BinOpFrag<(sub node:$LHS, node:$RHS)>>;
1090 // ADD and SUB with 's' bit set.
1091 defm ADDS : AI1_bin_s_irs<0b0100, "adds",
1092 BinOpFrag<(addc node:$LHS, node:$RHS)>, 1>;
1093 defm SUBS : AI1_bin_s_irs<0b0010, "subs",
1094 BinOpFrag<(subc node:$LHS, node:$RHS)>>;
1096 defm ADC : AI1_adde_sube_irs<0b0101, "adc",
1097 BinOpFrag<(adde node:$LHS, node:$RHS)>, 1>;
1098 defm SBC : AI1_adde_sube_irs<0b0110, "sbc",
1099 BinOpFrag<(sube node:$LHS, node:$RHS)>>;
1100 defm ADCS : AI1_adde_sube_s_irs<0b0101, "adcs",
1101 BinOpFrag<(adde node:$LHS, node:$RHS)>, 1>;
1102 defm SBCS : AI1_adde_sube_s_irs<0b0110, "sbcs",
1103 BinOpFrag<(sube node:$LHS, node:$RHS)>>;
1105 // These don't define reg/reg forms, because they are handled above.
1106 def RSBri : AsI1<0b0011, (outs GPR:$dst), (ins GPR:$a, so_imm:$b), DPFrm,
1107 IIC_iALUi, "rsb", "\t$dst, $a, $b",
1108 [(set GPR:$dst, (sub so_imm:$b, GPR:$a))]> {
1112 def RSBrs : AsI1<0b0011, (outs GPR:$dst), (ins GPR:$a, so_reg:$b), DPSoRegFrm,
1113 IIC_iALUsr, "rsb", "\t$dst, $a, $b",
1114 [(set GPR:$dst, (sub so_reg:$b, GPR:$a))]> {
1118 // RSB with 's' bit set.
1119 let Defs = [CPSR] in {
1120 def RSBSri : AI1<0b0011, (outs GPR:$dst), (ins GPR:$a, so_imm:$b), DPFrm,
1121 IIC_iALUi, "rsbs", "\t$dst, $a, $b",
1122 [(set GPR:$dst, (subc so_imm:$b, GPR:$a))]> {
1126 def RSBSrs : AI1<0b0011, (outs GPR:$dst), (ins GPR:$a, so_reg:$b), DPSoRegFrm,
1127 IIC_iALUsr, "rsbs", "\t$dst, $a, $b",
1128 [(set GPR:$dst, (subc so_reg:$b, GPR:$a))]> {
1134 let Uses = [CPSR] in {
1135 def RSCri : AsI1<0b0111, (outs GPR:$dst), (ins GPR:$a, so_imm:$b),
1136 DPFrm, IIC_iALUi, "rsc", "\t$dst, $a, $b",
1137 [(set GPR:$dst, (sube so_imm:$b, GPR:$a))]>,
1138 Requires<[IsARM, CarryDefIsUnused]> {
1141 def RSCrs : AsI1<0b0111, (outs GPR:$dst), (ins GPR:$a, so_reg:$b),
1142 DPSoRegFrm, IIC_iALUsr, "rsc", "\t$dst, $a, $b",
1143 [(set GPR:$dst, (sube so_reg:$b, GPR:$a))]>,
1144 Requires<[IsARM, CarryDefIsUnused]> {
1149 // FIXME: Allow these to be predicated.
1150 let Defs = [CPSR], Uses = [CPSR] in {
1151 def RSCSri : AXI1<0b0111, (outs GPR:$dst), (ins GPR:$a, so_imm:$b),
1152 DPFrm, IIC_iALUi, "rscs\t$dst, $a, $b",
1153 [(set GPR:$dst, (sube so_imm:$b, GPR:$a))]>,
1154 Requires<[IsARM, CarryDefIsUnused]> {
1158 def RSCSrs : AXI1<0b0111, (outs GPR:$dst), (ins GPR:$a, so_reg:$b),
1159 DPSoRegFrm, IIC_iALUsr, "rscs\t$dst, $a, $b",
1160 [(set GPR:$dst, (sube so_reg:$b, GPR:$a))]>,
1161 Requires<[IsARM, CarryDefIsUnused]> {
1167 // (sub X, imm) gets canonicalized to (add X, -imm). Match this form.
1168 def : ARMPat<(add GPR:$src, so_imm_neg:$imm),
1169 (SUBri GPR:$src, so_imm_neg:$imm)>;
1171 //def : ARMPat<(addc GPR:$src, so_imm_neg:$imm),
1172 // (SUBSri GPR:$src, so_imm_neg:$imm)>;
1173 //def : ARMPat<(adde GPR:$src, so_imm_neg:$imm),
1174 // (SBCri GPR:$src, so_imm_neg:$imm)>;
1176 // Note: These are implemented in C++ code, because they have to generate
1177 // ADD/SUBrs instructions, which use a complex pattern that a xform function
1179 // (mul X, 2^n+1) -> (add (X << n), X)
1180 // (mul X, 2^n-1) -> (rsb X, (X << n))
1183 //===----------------------------------------------------------------------===//
1184 // Bitwise Instructions.
1187 defm AND : AsI1_bin_irs<0b0000, "and",
1188 BinOpFrag<(and node:$LHS, node:$RHS)>, 1>;
1189 defm ORR : AsI1_bin_irs<0b1100, "orr",
1190 BinOpFrag<(or node:$LHS, node:$RHS)>, 1>;
1191 defm EOR : AsI1_bin_irs<0b0001, "eor",
1192 BinOpFrag<(xor node:$LHS, node:$RHS)>, 1>;
1193 defm BIC : AsI1_bin_irs<0b1110, "bic",
1194 BinOpFrag<(and node:$LHS, (not node:$RHS))>>;
1196 def BFC : I<(outs GPR:$dst), (ins GPR:$src, bf_inv_mask_imm:$imm),
1197 AddrMode1, Size4Bytes, IndexModeNone, DPFrm, IIC_iUNAsi,
1198 "bfc", "\t$dst, $imm", "$src = $dst",
1199 [(set GPR:$dst, (and GPR:$src, bf_inv_mask_imm:$imm))]>,
1200 Requires<[IsARM, HasV6T2]> {
1201 let Inst{27-21} = 0b0111110;
1202 let Inst{6-0} = 0b0011111;
1205 def MVNr : AsI1<0b1111, (outs GPR:$dst), (ins GPR:$src), DPFrm, IIC_iMOVr,
1206 "mvn", "\t$dst, $src",
1207 [(set GPR:$dst, (not GPR:$src))]>, UnaryDP {
1208 let Inst{11-4} = 0b00000000;
1210 def MVNs : AsI1<0b1111, (outs GPR:$dst), (ins so_reg:$src), DPSoRegFrm,
1211 IIC_iMOVsr, "mvn", "\t$dst, $src",
1212 [(set GPR:$dst, (not so_reg:$src))]>, UnaryDP;
1213 let isReMaterializable = 1, isAsCheapAsAMove = 1 in
1214 def MVNi : AsI1<0b1111, (outs GPR:$dst), (ins so_imm:$imm), DPFrm,
1215 IIC_iMOVi, "mvn", "\t$dst, $imm",
1216 [(set GPR:$dst, so_imm_not:$imm)]>,UnaryDP {
1220 def : ARMPat<(and GPR:$src, so_imm_not:$imm),
1221 (BICri GPR:$src, so_imm_not:$imm)>;
1223 //===----------------------------------------------------------------------===//
1224 // Multiply Instructions.
1227 let isCommutable = 1 in
1228 def MUL : AsMul1I<0b0000000, (outs GPR:$dst), (ins GPR:$a, GPR:$b),
1229 IIC_iMUL32, "mul", "\t$dst, $a, $b",
1230 [(set GPR:$dst, (mul GPR:$a, GPR:$b))]>;
1232 def MLA : AsMul1I<0b0000001, (outs GPR:$dst), (ins GPR:$a, GPR:$b, GPR:$c),
1233 IIC_iMAC32, "mla", "\t$dst, $a, $b, $c",
1234 [(set GPR:$dst, (add (mul GPR:$a, GPR:$b), GPR:$c))]>;
1236 def MLS : AMul1I<0b0000011, (outs GPR:$dst), (ins GPR:$a, GPR:$b, GPR:$c),
1237 IIC_iMAC32, "mls", "\t$dst, $a, $b, $c",
1238 [(set GPR:$dst, (sub GPR:$c, (mul GPR:$a, GPR:$b)))]>,
1239 Requires<[IsARM, HasV6T2]>;
1241 // Extra precision multiplies with low / high results
1242 let neverHasSideEffects = 1 in {
1243 let isCommutable = 1 in {
1244 def SMULL : AsMul1I<0b0000110, (outs GPR:$ldst, GPR:$hdst),
1245 (ins GPR:$a, GPR:$b), IIC_iMUL64,
1246 "smull", "\t$ldst, $hdst, $a, $b", []>;
1248 def UMULL : AsMul1I<0b0000100, (outs GPR:$ldst, GPR:$hdst),
1249 (ins GPR:$a, GPR:$b), IIC_iMUL64,
1250 "umull", "\t$ldst, $hdst, $a, $b", []>;
1253 // Multiply + accumulate
1254 def SMLAL : AsMul1I<0b0000111, (outs GPR:$ldst, GPR:$hdst),
1255 (ins GPR:$a, GPR:$b), IIC_iMAC64,
1256 "smlal", "\t$ldst, $hdst, $a, $b", []>;
1258 def UMLAL : AsMul1I<0b0000101, (outs GPR:$ldst, GPR:$hdst),
1259 (ins GPR:$a, GPR:$b), IIC_iMAC64,
1260 "umlal", "\t$ldst, $hdst, $a, $b", []>;
1262 def UMAAL : AMul1I <0b0000010, (outs GPR:$ldst, GPR:$hdst),
1263 (ins GPR:$a, GPR:$b), IIC_iMAC64,
1264 "umaal", "\t$ldst, $hdst, $a, $b", []>,
1265 Requires<[IsARM, HasV6]>;
1266 } // neverHasSideEffects
1268 // Most significant word multiply
1269 def SMMUL : AMul2I <0b0111010, (outs GPR:$dst), (ins GPR:$a, GPR:$b),
1270 IIC_iMUL32, "smmul", "\t$dst, $a, $b",
1271 [(set GPR:$dst, (mulhs GPR:$a, GPR:$b))]>,
1272 Requires<[IsARM, HasV6]> {
1273 let Inst{7-4} = 0b0001;
1274 let Inst{15-12} = 0b1111;
1277 def SMMLA : AMul2I <0b0111010, (outs GPR:$dst), (ins GPR:$a, GPR:$b, GPR:$c),
1278 IIC_iMAC32, "smmla", "\t$dst, $a, $b, $c",
1279 [(set GPR:$dst, (add (mulhs GPR:$a, GPR:$b), GPR:$c))]>,
1280 Requires<[IsARM, HasV6]> {
1281 let Inst{7-4} = 0b0001;
1285 def SMMLS : AMul2I <0b0111010, (outs GPR:$dst), (ins GPR:$a, GPR:$b, GPR:$c),
1286 IIC_iMAC32, "smmls", "\t$dst, $a, $b, $c",
1287 [(set GPR:$dst, (sub GPR:$c, (mulhs GPR:$a, GPR:$b)))]>,
1288 Requires<[IsARM, HasV6]> {
1289 let Inst{7-4} = 0b1101;
1292 multiclass AI_smul<string opc, PatFrag opnode> {
1293 def BB : AMulxyI<0b0001011, (outs GPR:$dst), (ins GPR:$a, GPR:$b),
1294 IIC_iMUL32, !strconcat(opc, "bb"), "\t$dst, $a, $b",
1295 [(set GPR:$dst, (opnode (sext_inreg GPR:$a, i16),
1296 (sext_inreg GPR:$b, i16)))]>,
1297 Requires<[IsARM, HasV5TE]> {
1302 def BT : AMulxyI<0b0001011, (outs GPR:$dst), (ins GPR:$a, GPR:$b),
1303 IIC_iMUL32, !strconcat(opc, "bt"), "\t$dst, $a, $b",
1304 [(set GPR:$dst, (opnode (sext_inreg GPR:$a, i16),
1305 (sra GPR:$b, (i32 16))))]>,
1306 Requires<[IsARM, HasV5TE]> {
1311 def TB : AMulxyI<0b0001011, (outs GPR:$dst), (ins GPR:$a, GPR:$b),
1312 IIC_iMUL32, !strconcat(opc, "tb"), "\t$dst, $a, $b",
1313 [(set GPR:$dst, (opnode (sra GPR:$a, (i32 16)),
1314 (sext_inreg GPR:$b, i16)))]>,
1315 Requires<[IsARM, HasV5TE]> {
1320 def TT : AMulxyI<0b0001011, (outs GPR:$dst), (ins GPR:$a, GPR:$b),
1321 IIC_iMUL32, !strconcat(opc, "tt"), "\t$dst, $a, $b",
1322 [(set GPR:$dst, (opnode (sra GPR:$a, (i32 16)),
1323 (sra GPR:$b, (i32 16))))]>,
1324 Requires<[IsARM, HasV5TE]> {
1329 def WB : AMulxyI<0b0001001, (outs GPR:$dst), (ins GPR:$a, GPR:$b),
1330 IIC_iMUL16, !strconcat(opc, "wb"), "\t$dst, $a, $b",
1331 [(set GPR:$dst, (sra (opnode GPR:$a,
1332 (sext_inreg GPR:$b, i16)), (i32 16)))]>,
1333 Requires<[IsARM, HasV5TE]> {
1338 def WT : AMulxyI<0b0001001, (outs GPR:$dst), (ins GPR:$a, GPR:$b),
1339 IIC_iMUL16, !strconcat(opc, "wt"), "\t$dst, $a, $b",
1340 [(set GPR:$dst, (sra (opnode GPR:$a,
1341 (sra GPR:$b, (i32 16))), (i32 16)))]>,
1342 Requires<[IsARM, HasV5TE]> {
1349 multiclass AI_smla<string opc, PatFrag opnode> {
1350 def BB : AMulxyI<0b0001000, (outs GPR:$dst), (ins GPR:$a, GPR:$b, GPR:$acc),
1351 IIC_iMAC16, !strconcat(opc, "bb"), "\t$dst, $a, $b, $acc",
1352 [(set GPR:$dst, (add GPR:$acc,
1353 (opnode (sext_inreg GPR:$a, i16),
1354 (sext_inreg GPR:$b, i16))))]>,
1355 Requires<[IsARM, HasV5TE]> {
1360 def BT : AMulxyI<0b0001000, (outs GPR:$dst), (ins GPR:$a, GPR:$b, GPR:$acc),
1361 IIC_iMAC16, !strconcat(opc, "bt"), "\t$dst, $a, $b, $acc",
1362 [(set GPR:$dst, (add GPR:$acc, (opnode (sext_inreg GPR:$a, i16),
1363 (sra GPR:$b, (i32 16)))))]>,
1364 Requires<[IsARM, HasV5TE]> {
1369 def TB : AMulxyI<0b0001000, (outs GPR:$dst), (ins GPR:$a, GPR:$b, GPR:$acc),
1370 IIC_iMAC16, !strconcat(opc, "tb"), "\t$dst, $a, $b, $acc",
1371 [(set GPR:$dst, (add GPR:$acc, (opnode (sra GPR:$a, (i32 16)),
1372 (sext_inreg GPR:$b, i16))))]>,
1373 Requires<[IsARM, HasV5TE]> {
1378 def TT : AMulxyI<0b0001000, (outs GPR:$dst), (ins GPR:$a, GPR:$b, GPR:$acc),
1379 IIC_iMAC16, !strconcat(opc, "tt"), "\t$dst, $a, $b, $acc",
1380 [(set GPR:$dst, (add GPR:$acc, (opnode (sra GPR:$a, (i32 16)),
1381 (sra GPR:$b, (i32 16)))))]>,
1382 Requires<[IsARM, HasV5TE]> {
1387 def WB : AMulxyI<0b0001001, (outs GPR:$dst), (ins GPR:$a, GPR:$b, GPR:$acc),
1388 IIC_iMAC16, !strconcat(opc, "wb"), "\t$dst, $a, $b, $acc",
1389 [(set GPR:$dst, (add GPR:$acc, (sra (opnode GPR:$a,
1390 (sext_inreg GPR:$b, i16)), (i32 16))))]>,
1391 Requires<[IsARM, HasV5TE]> {
1396 def WT : AMulxyI<0b0001001, (outs GPR:$dst), (ins GPR:$a, GPR:$b, GPR:$acc),
1397 IIC_iMAC16, !strconcat(opc, "wt"), "\t$dst, $a, $b, $acc",
1398 [(set GPR:$dst, (add GPR:$acc, (sra (opnode GPR:$a,
1399 (sra GPR:$b, (i32 16))), (i32 16))))]>,
1400 Requires<[IsARM, HasV5TE]> {
1406 defm SMUL : AI_smul<"smul", BinOpFrag<(mul node:$LHS, node:$RHS)>>;
1407 defm SMLA : AI_smla<"smla", BinOpFrag<(mul node:$LHS, node:$RHS)>>;
1409 // TODO: Halfword multiple accumulate long: SMLAL<x><y>
1410 // TODO: Dual halfword multiple: SMUAD, SMUSD, SMLAD, SMLSD, SMLALD, SMLSLD
1412 //===----------------------------------------------------------------------===//
1413 // Misc. Arithmetic Instructions.
1416 def CLZ : AMiscA1I<0b000010110, (outs GPR:$dst), (ins GPR:$src), IIC_iUNAr,
1417 "clz", "\t$dst, $src",
1418 [(set GPR:$dst, (ctlz GPR:$src))]>, Requires<[IsARM, HasV5T]> {
1419 let Inst{7-4} = 0b0001;
1420 let Inst{11-8} = 0b1111;
1421 let Inst{19-16} = 0b1111;
1424 def REV : AMiscA1I<0b01101011, (outs GPR:$dst), (ins GPR:$src), IIC_iUNAr,
1425 "rev", "\t$dst, $src",
1426 [(set GPR:$dst, (bswap GPR:$src))]>, Requires<[IsARM, HasV6]> {
1427 let Inst{7-4} = 0b0011;
1428 let Inst{11-8} = 0b1111;
1429 let Inst{19-16} = 0b1111;
1432 def REV16 : AMiscA1I<0b01101011, (outs GPR:$dst), (ins GPR:$src), IIC_iUNAr,
1433 "rev16", "\t$dst, $src",
1435 (or (and (srl GPR:$src, (i32 8)), 0xFF),
1436 (or (and (shl GPR:$src, (i32 8)), 0xFF00),
1437 (or (and (srl GPR:$src, (i32 8)), 0xFF0000),
1438 (and (shl GPR:$src, (i32 8)), 0xFF000000)))))]>,
1439 Requires<[IsARM, HasV6]> {
1440 let Inst{7-4} = 0b1011;
1441 let Inst{11-8} = 0b1111;
1442 let Inst{19-16} = 0b1111;
1445 def REVSH : AMiscA1I<0b01101111, (outs GPR:$dst), (ins GPR:$src), IIC_iUNAr,
1446 "revsh", "\t$dst, $src",
1449 (or (srl (and GPR:$src, 0xFF00), (i32 8)),
1450 (shl GPR:$src, (i32 8))), i16))]>,
1451 Requires<[IsARM, HasV6]> {
1452 let Inst{7-4} = 0b1011;
1453 let Inst{11-8} = 0b1111;
1454 let Inst{19-16} = 0b1111;
1457 def PKHBT : AMiscA1I<0b01101000, (outs GPR:$dst),
1458 (ins GPR:$src1, GPR:$src2, i32imm:$shamt),
1459 IIC_iALUsi, "pkhbt", "\t$dst, $src1, $src2, LSL $shamt",
1460 [(set GPR:$dst, (or (and GPR:$src1, 0xFFFF),
1461 (and (shl GPR:$src2, (i32 imm:$shamt)),
1463 Requires<[IsARM, HasV6]> {
1464 let Inst{6-4} = 0b001;
1467 // Alternate cases for PKHBT where identities eliminate some nodes.
1468 def : ARMV6Pat<(or (and GPR:$src1, 0xFFFF), (and GPR:$src2, 0xFFFF0000)),
1469 (PKHBT GPR:$src1, GPR:$src2, 0)>;
1470 def : ARMV6Pat<(or (and GPR:$src1, 0xFFFF), (shl GPR:$src2, imm16_31:$shamt)),
1471 (PKHBT GPR:$src1, GPR:$src2, imm16_31:$shamt)>;
1474 def PKHTB : AMiscA1I<0b01101000, (outs GPR:$dst),
1475 (ins GPR:$src1, GPR:$src2, i32imm:$shamt),
1476 IIC_iALUsi, "pkhtb", "\t$dst, $src1, $src2, ASR $shamt",
1477 [(set GPR:$dst, (or (and GPR:$src1, 0xFFFF0000),
1478 (and (sra GPR:$src2, imm16_31:$shamt),
1479 0xFFFF)))]>, Requires<[IsARM, HasV6]> {
1480 let Inst{6-4} = 0b101;
1483 // Alternate cases for PKHTB where identities eliminate some nodes. Note that
1484 // a shift amount of 0 is *not legal* here, it is PKHBT instead.
1485 def : ARMV6Pat<(or (and GPR:$src1, 0xFFFF0000), (srl GPR:$src2, (i32 16))),
1486 (PKHTB GPR:$src1, GPR:$src2, 16)>;
1487 def : ARMV6Pat<(or (and GPR:$src1, 0xFFFF0000),
1488 (and (srl GPR:$src2, imm1_15:$shamt), 0xFFFF)),
1489 (PKHTB GPR:$src1, GPR:$src2, imm1_15:$shamt)>;
1491 //===----------------------------------------------------------------------===//
1492 // Comparison Instructions...
1495 defm CMP : AI1_cmp_irs<0b1010, "cmp",
1496 BinOpFrag<(ARMcmp node:$LHS, node:$RHS)>>;
1497 defm CMN : AI1_cmp_irs<0b1011, "cmn",
1498 BinOpFrag<(ARMcmp node:$LHS,(ineg node:$RHS))>>;
1500 // Note that TST/TEQ don't set all the same flags that CMP does!
1501 defm TST : AI1_cmp_irs<0b1000, "tst",
1502 BinOpFrag<(ARMcmpZ (and node:$LHS, node:$RHS), 0)>, 1>;
1503 defm TEQ : AI1_cmp_irs<0b1001, "teq",
1504 BinOpFrag<(ARMcmpZ (xor node:$LHS, node:$RHS), 0)>, 1>;
1506 defm CMPz : AI1_cmp_irs<0b1010, "cmp",
1507 BinOpFrag<(ARMcmpZ node:$LHS, node:$RHS)>>;
1508 defm CMNz : AI1_cmp_irs<0b1011, "cmn",
1509 BinOpFrag<(ARMcmpZ node:$LHS,(ineg node:$RHS))>>;
1511 def : ARMPat<(ARMcmp GPR:$src, so_imm_neg:$imm),
1512 (CMNri GPR:$src, so_imm_neg:$imm)>;
1514 def : ARMPat<(ARMcmpZ GPR:$src, so_imm_neg:$imm),
1515 (CMNri GPR:$src, so_imm_neg:$imm)>;
1518 // Conditional moves
1519 // FIXME: should be able to write a pattern for ARMcmov, but can't use
1520 // a two-value operand where a dag node expects two operands. :(
1521 def MOVCCr : AI1<0b1101, (outs GPR:$dst), (ins GPR:$false, GPR:$true), DPFrm,
1522 IIC_iCMOVr, "mov", "\t$dst, $true",
1523 [/*(set GPR:$dst, (ARMcmov GPR:$false, GPR:$true, imm:$cc, CCR:$ccr))*/]>,
1524 RegConstraint<"$false = $dst">, UnaryDP {
1525 let Inst{11-4} = 0b00000000;
1529 def MOVCCs : AI1<0b1101, (outs GPR:$dst),
1530 (ins GPR:$false, so_reg:$true), DPSoRegFrm, IIC_iCMOVsr,
1531 "mov", "\t$dst, $true",
1532 [/*(set GPR:$dst, (ARMcmov GPR:$false, so_reg:$true, imm:$cc, CCR:$ccr))*/]>,
1533 RegConstraint<"$false = $dst">, UnaryDP {
1537 def MOVCCi : AI1<0b1101, (outs GPR:$dst),
1538 (ins GPR:$false, so_imm:$true), DPFrm, IIC_iCMOVi,
1539 "mov", "\t$dst, $true",
1540 [/*(set GPR:$dst, (ARMcmov GPR:$false, so_imm:$true, imm:$cc, CCR:$ccr))*/]>,
1541 RegConstraint<"$false = $dst">, UnaryDP {
1546 //===----------------------------------------------------------------------===//
1550 // __aeabi_read_tp preserves the registers r1-r3.
1552 Defs = [R0, R12, LR, CPSR] in {
1553 def TPsoft : ABXI<0b1011, (outs), (ins), IIC_Br,
1554 "bl\t__aeabi_read_tp",
1555 [(set R0, ARMthread_pointer)]>;
1558 //===----------------------------------------------------------------------===//
1559 // SJLJ Exception handling intrinsics
1560 // eh_sjlj_setjmp() is an instruction sequence to store the return
1561 // address and save #0 in R0 for the non-longjmp case.
1562 // Since by its nature we may be coming from some other function to get
1563 // here, and we're using the stack frame for the containing function to
1564 // save/restore registers, we can't keep anything live in regs across
1565 // the eh_sjlj_setjmp(), else it will almost certainly have been tromped upon
1566 // when we get here from a longjmp(). We force everthing out of registers
1567 // except for our own input by listing the relevant registers in Defs. By
1568 // doing so, we also cause the prologue/epilogue code to actively preserve
1569 // all of the callee-saved resgisters, which is exactly what we want.
1571 [ R0, R1, R2, R3, R4, R5, R6, R7, R8, R9, R10, R11, R12, LR, D0,
1572 D1, D2, D3, D4, D5, D6, D7, D8, D9, D10, D11, D12, D13, D14, D15,
1573 D16, D17, D18, D19, D20, D21, D22, D23, D24, D25, D26, D27, D28, D29, D30,
1575 def Int_eh_sjlj_setjmp : XI<(outs), (ins GPR:$src),
1576 AddrModeNone, SizeSpecial, IndexModeNone,
1577 Pseudo, NoItinerary,
1578 "str\tsp, [$src, #+8] @ eh_setjmp begin\n\t"
1579 "add\tr12, pc, #8\n\t"
1580 "str\tr12, [$src, #+4]\n\t"
1582 "add\tpc, pc, #0\n\t"
1583 "mov\tr0, #1 @ eh_setjmp end", "",
1584 [(set R0, (ARMeh_sjlj_setjmp GPR:$src))]>;
1587 //===----------------------------------------------------------------------===//
1588 // Non-Instruction Patterns
1591 // ConstantPool, GlobalAddress, and JumpTable
1592 def : ARMPat<(ARMWrapper tglobaladdr :$dst), (LEApcrel tglobaladdr :$dst)>;
1593 def : ARMPat<(ARMWrapper tconstpool :$dst), (LEApcrel tconstpool :$dst)>;
1594 def : ARMPat<(ARMWrapperJT tjumptable:$dst, imm:$id),
1595 (LEApcrelJT tjumptable:$dst, imm:$id)>;
1597 // Large immediate handling.
1599 // Two piece so_imms.
1600 let isReMaterializable = 1 in
1601 def MOVi2pieces : AI1x2<(outs GPR:$dst), (ins so_imm2part:$src),
1603 "mov", "\t$dst, $src",
1604 [(set GPR:$dst, so_imm2part:$src)]>,
1605 Requires<[IsARM, NoV6T2]>;
1607 def : ARMPat<(or GPR:$LHS, so_imm2part:$RHS),
1608 (ORRri (ORRri GPR:$LHS, (so_imm2part_1 imm:$RHS)),
1609 (so_imm2part_2 imm:$RHS))>;
1610 def : ARMPat<(xor GPR:$LHS, so_imm2part:$RHS),
1611 (EORri (EORri GPR:$LHS, (so_imm2part_1 imm:$RHS)),
1612 (so_imm2part_2 imm:$RHS))>;
1613 def : ARMPat<(add GPR:$LHS, so_imm2part:$RHS),
1614 (ADDri (ADDri GPR:$LHS, (so_imm2part_1 imm:$RHS)),
1615 (so_imm2part_2 imm:$RHS))>;
1616 def : ARMPat<(sub GPR:$LHS, so_imm2part:$RHS),
1617 (SUBri (SUBri GPR:$LHS, (so_imm2part_1 imm:$RHS)),
1618 (so_imm2part_2 imm:$RHS))>;
1620 // 32-bit immediate using movw + movt.
1621 // This is a single pseudo instruction, the benefit is that it can be remat'd
1622 // as a single unit instead of having to handle reg inputs.
1623 // FIXME: Remove this when we can do generalized remat.
1624 let isReMaterializable = 1 in
1625 def MOVi32imm : AI1x2<(outs GPR:$dst), (ins i32imm:$src), Pseudo, IIC_iMOVi,
1626 "movw", "\t$dst, ${src:lo16}\n\tmovt${p} $dst, ${src:hi16}",
1627 [(set GPR:$dst, (i32 imm:$src))]>,
1628 Requires<[IsARM, HasV6T2]>;
1630 // TODO: add,sub,and, 3-instr forms?
1634 def : ARMPat<(ARMcall texternalsym:$func), (BL texternalsym:$func)>,
1635 Requires<[IsARM, IsNotDarwin]>;
1636 def : ARMPat<(ARMcall texternalsym:$func), (BLr9 texternalsym:$func)>,
1637 Requires<[IsARM, IsDarwin]>;
1639 // zextload i1 -> zextload i8
1640 def : ARMPat<(zextloadi1 addrmode2:$addr), (LDRB addrmode2:$addr)>;
1642 // extload -> zextload
1643 def : ARMPat<(extloadi1 addrmode2:$addr), (LDRB addrmode2:$addr)>;
1644 def : ARMPat<(extloadi8 addrmode2:$addr), (LDRB addrmode2:$addr)>;
1645 def : ARMPat<(extloadi16 addrmode3:$addr), (LDRH addrmode3:$addr)>;
1647 def : ARMPat<(extloadi8 addrmodepc:$addr), (PICLDRB addrmodepc:$addr)>;
1648 def : ARMPat<(extloadi16 addrmodepc:$addr), (PICLDRH addrmodepc:$addr)>;
1651 def : ARMV5TEPat<(mul (sra (shl GPR:$a, (i32 16)), (i32 16)),
1652 (sra (shl GPR:$b, (i32 16)), (i32 16))),
1653 (SMULBB GPR:$a, GPR:$b)>;
1654 def : ARMV5TEPat<(mul sext_16_node:$a, sext_16_node:$b),
1655 (SMULBB GPR:$a, GPR:$b)>;
1656 def : ARMV5TEPat<(mul (sra (shl GPR:$a, (i32 16)), (i32 16)),
1657 (sra GPR:$b, (i32 16))),
1658 (SMULBT GPR:$a, GPR:$b)>;
1659 def : ARMV5TEPat<(mul sext_16_node:$a, (sra GPR:$b, (i32 16))),
1660 (SMULBT GPR:$a, GPR:$b)>;
1661 def : ARMV5TEPat<(mul (sra GPR:$a, (i32 16)),
1662 (sra (shl GPR:$b, (i32 16)), (i32 16))),
1663 (SMULTB GPR:$a, GPR:$b)>;
1664 def : ARMV5TEPat<(mul (sra GPR:$a, (i32 16)), sext_16_node:$b),
1665 (SMULTB GPR:$a, GPR:$b)>;
1666 def : ARMV5TEPat<(sra (mul GPR:$a, (sra (shl GPR:$b, (i32 16)), (i32 16))),
1668 (SMULWB GPR:$a, GPR:$b)>;
1669 def : ARMV5TEPat<(sra (mul GPR:$a, sext_16_node:$b), (i32 16)),
1670 (SMULWB GPR:$a, GPR:$b)>;
1672 def : ARMV5TEPat<(add GPR:$acc,
1673 (mul (sra (shl GPR:$a, (i32 16)), (i32 16)),
1674 (sra (shl GPR:$b, (i32 16)), (i32 16)))),
1675 (SMLABB GPR:$a, GPR:$b, GPR:$acc)>;
1676 def : ARMV5TEPat<(add GPR:$acc,
1677 (mul sext_16_node:$a, sext_16_node:$b)),
1678 (SMLABB GPR:$a, GPR:$b, GPR:$acc)>;
1679 def : ARMV5TEPat<(add GPR:$acc,
1680 (mul (sra (shl GPR:$a, (i32 16)), (i32 16)),
1681 (sra GPR:$b, (i32 16)))),
1682 (SMLABT GPR:$a, GPR:$b, GPR:$acc)>;
1683 def : ARMV5TEPat<(add GPR:$acc,
1684 (mul sext_16_node:$a, (sra GPR:$b, (i32 16)))),
1685 (SMLABT GPR:$a, GPR:$b, GPR:$acc)>;
1686 def : ARMV5TEPat<(add GPR:$acc,
1687 (mul (sra GPR:$a, (i32 16)),
1688 (sra (shl GPR:$b, (i32 16)), (i32 16)))),
1689 (SMLATB GPR:$a, GPR:$b, GPR:$acc)>;
1690 def : ARMV5TEPat<(add GPR:$acc,
1691 (mul (sra GPR:$a, (i32 16)), sext_16_node:$b)),
1692 (SMLATB GPR:$a, GPR:$b, GPR:$acc)>;
1693 def : ARMV5TEPat<(add GPR:$acc,
1694 (sra (mul GPR:$a, (sra (shl GPR:$b, (i32 16)), (i32 16))),
1696 (SMLAWB GPR:$a, GPR:$b, GPR:$acc)>;
1697 def : ARMV5TEPat<(add GPR:$acc,
1698 (sra (mul GPR:$a, sext_16_node:$b), (i32 16))),
1699 (SMLAWB GPR:$a, GPR:$b, GPR:$acc)>;
1701 //===----------------------------------------------------------------------===//
1705 include "ARMInstrThumb.td"
1707 //===----------------------------------------------------------------------===//
1711 include "ARMInstrThumb2.td"
1713 //===----------------------------------------------------------------------===//
1714 // Floating Point Support
1717 include "ARMInstrVFP.td"
1719 //===----------------------------------------------------------------------===//
1720 // Advanced SIMD (NEON) Support
1723 include "ARMInstrNEON.td"