1 //===- ARMInstrInfo.td - Target Description for ARM Target -*- tablegen -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file describes the ARM instructions in TableGen format.
12 //===----------------------------------------------------------------------===//
14 //===----------------------------------------------------------------------===//
15 // ARM specific DAG Nodes.
19 def SDT_ARMCallSeqStart : SDCallSeqStart<[ SDTCisVT<0, i32> ]>;
20 def SDT_ARMCallSeqEnd : SDCallSeqEnd<[ SDTCisVT<0, i32>, SDTCisVT<1, i32> ]>;
22 def SDT_ARMSaveCallPC : SDTypeProfile<0, 1, []>;
24 def SDT_ARMcall : SDTypeProfile<0, -1, [SDTCisInt<0>]>;
26 def SDT_ARMCMov : SDTypeProfile<1, 3,
27 [SDTCisSameAs<0, 1>, SDTCisSameAs<0, 2>,
30 def SDT_ARMBrcond : SDTypeProfile<0, 2,
31 [SDTCisVT<0, OtherVT>, SDTCisVT<1, i32>]>;
33 def SDT_ARMBrJT : SDTypeProfile<0, 3,
34 [SDTCisPtrTy<0>, SDTCisVT<1, i32>,
37 def SDT_ARMBr2JT : SDTypeProfile<0, 4,
38 [SDTCisPtrTy<0>, SDTCisVT<1, i32>,
39 SDTCisVT<2, i32>, SDTCisVT<3, i32>]>;
41 def SDT_ARMCmp : SDTypeProfile<0, 2, [SDTCisSameAs<0, 1>]>;
43 def SDT_ARMPICAdd : SDTypeProfile<1, 2, [SDTCisSameAs<0, 1>,
44 SDTCisPtrTy<1>, SDTCisVT<2, i32>]>;
46 def SDT_ARMThreadPointer : SDTypeProfile<1, 0, [SDTCisPtrTy<0>]>;
47 def SDT_ARMEH_SJLJ_Setjmp : SDTypeProfile<1, 1, [SDTCisInt<0>, SDTCisPtrTy<1>]>;
50 def ARMWrapper : SDNode<"ARMISD::Wrapper", SDTIntUnaryOp>;
51 def ARMWrapperJT : SDNode<"ARMISD::WrapperJT", SDTIntBinOp>;
53 def ARMcallseq_start : SDNode<"ISD::CALLSEQ_START", SDT_ARMCallSeqStart,
54 [SDNPHasChain, SDNPOutFlag]>;
55 def ARMcallseq_end : SDNode<"ISD::CALLSEQ_END", SDT_ARMCallSeqEnd,
56 [SDNPHasChain, SDNPOptInFlag, SDNPOutFlag]>;
58 def ARMcall : SDNode<"ARMISD::CALL", SDT_ARMcall,
59 [SDNPHasChain, SDNPOptInFlag, SDNPOutFlag]>;
60 def ARMcall_pred : SDNode<"ARMISD::CALL_PRED", SDT_ARMcall,
61 [SDNPHasChain, SDNPOptInFlag, SDNPOutFlag]>;
62 def ARMcall_nolink : SDNode<"ARMISD::CALL_NOLINK", SDT_ARMcall,
63 [SDNPHasChain, SDNPOptInFlag, SDNPOutFlag]>;
65 def ARMretflag : SDNode<"ARMISD::RET_FLAG", SDTNone,
66 [SDNPHasChain, SDNPOptInFlag]>;
68 def ARMcmov : SDNode<"ARMISD::CMOV", SDT_ARMCMov,
70 def ARMcneg : SDNode<"ARMISD::CNEG", SDT_ARMCMov,
73 def ARMbrcond : SDNode<"ARMISD::BRCOND", SDT_ARMBrcond,
74 [SDNPHasChain, SDNPInFlag, SDNPOutFlag]>;
76 def ARMbrjt : SDNode<"ARMISD::BR_JT", SDT_ARMBrJT,
78 def ARMbr2jt : SDNode<"ARMISD::BR2_JT", SDT_ARMBr2JT,
81 def ARMcmp : SDNode<"ARMISD::CMP", SDT_ARMCmp,
84 def ARMcmpZ : SDNode<"ARMISD::CMPZ", SDT_ARMCmp,
85 [SDNPOutFlag,SDNPCommutative]>;
87 def ARMpic_add : SDNode<"ARMISD::PIC_ADD", SDT_ARMPICAdd>;
89 def ARMsrl_flag : SDNode<"ARMISD::SRL_FLAG", SDTIntUnaryOp, [SDNPOutFlag]>;
90 def ARMsra_flag : SDNode<"ARMISD::SRA_FLAG", SDTIntUnaryOp, [SDNPOutFlag]>;
91 def ARMrrx : SDNode<"ARMISD::RRX" , SDTIntUnaryOp, [SDNPInFlag ]>;
93 def ARMthread_pointer: SDNode<"ARMISD::THREAD_POINTER", SDT_ARMThreadPointer>;
94 def ARMeh_sjlj_setjmp: SDNode<"ARMISD::EH_SJLJ_SETJMP", SDT_ARMEH_SJLJ_Setjmp>;
96 //===----------------------------------------------------------------------===//
97 // ARM Instruction Predicate Definitions.
99 def HasV5T : Predicate<"Subtarget->hasV5TOps()">;
100 def HasV5TE : Predicate<"Subtarget->hasV5TEOps()">;
101 def HasV6 : Predicate<"Subtarget->hasV6Ops()">;
102 def HasV6T2 : Predicate<"Subtarget->hasV6T2Ops()">;
103 def NoV6T2 : Predicate<"!Subtarget->hasV6T2Ops()">;
104 def HasV7 : Predicate<"Subtarget->hasV7Ops()">;
105 def HasVFP2 : Predicate<"Subtarget->hasVFP2()">;
106 def HasVFP3 : Predicate<"Subtarget->hasVFP3()">;
107 def HasNEON : Predicate<"Subtarget->hasNEON()">;
108 def UseNEONForFP : Predicate<"Subtarget->useNEONForSinglePrecisionFP()">;
109 def DontUseNEONForFP : Predicate<"!Subtarget->useNEONForSinglePrecisionFP()">;
110 def IsThumb : Predicate<"Subtarget->isThumb()">;
111 def IsThumb1Only : Predicate<"Subtarget->isThumb1Only()">;
112 def IsThumb2 : Predicate<"Subtarget->isThumb2()">;
113 def IsARM : Predicate<"!Subtarget->isThumb()">;
114 def IsDarwin : Predicate<"Subtarget->isTargetDarwin()">;
115 def IsNotDarwin : Predicate<"!Subtarget->isTargetDarwin()">;
116 def CarryDefIsUnused : Predicate<"!N.getNode()->hasAnyUseOfValue(1)">;
117 def CarryDefIsUsed : Predicate<"N.getNode()->hasAnyUseOfValue(1)">;
119 //===----------------------------------------------------------------------===//
120 // ARM Flag Definitions.
122 class RegConstraint<string C> {
123 string Constraints = C;
126 //===----------------------------------------------------------------------===//
127 // ARM specific transformation functions and pattern fragments.
130 // so_imm_neg_XFORM - Return a so_imm value packed into the format described for
131 // so_imm_neg def below.
132 def so_imm_neg_XFORM : SDNodeXForm<imm, [{
133 return CurDAG->getTargetConstant(-(int)N->getZExtValue(), MVT::i32);
136 // so_imm_not_XFORM - Return a so_imm value packed into the format described for
137 // so_imm_not def below.
138 def so_imm_not_XFORM : SDNodeXForm<imm, [{
139 return CurDAG->getTargetConstant(~(int)N->getZExtValue(), MVT::i32);
142 // rot_imm predicate - True if the 32-bit immediate is equal to 8, 16, or 24.
143 def rot_imm : PatLeaf<(i32 imm), [{
144 int32_t v = (int32_t)N->getZExtValue();
145 return v == 8 || v == 16 || v == 24;
148 /// imm1_15 predicate - True if the 32-bit immediate is in the range [1,15].
149 def imm1_15 : PatLeaf<(i32 imm), [{
150 return (int32_t)N->getZExtValue() >= 1 && (int32_t)N->getZExtValue() < 16;
153 /// imm16_31 predicate - True if the 32-bit immediate is in the range [16,31].
154 def imm16_31 : PatLeaf<(i32 imm), [{
155 return (int32_t)N->getZExtValue() >= 16 && (int32_t)N->getZExtValue() < 32;
160 return ARM_AM::getSOImmVal(-(int)N->getZExtValue()) != -1;
161 }], so_imm_neg_XFORM>;
165 return ARM_AM::getSOImmVal(~(int)N->getZExtValue()) != -1;
166 }], so_imm_not_XFORM>;
168 // sext_16_node predicate - True if the SDNode is sign-extended 16 or more bits.
169 def sext_16_node : PatLeaf<(i32 GPR:$a), [{
170 return CurDAG->ComputeNumSignBits(SDValue(N,0)) >= 17;
173 /// bf_inv_mask_imm predicate - An AND mask to clear an arbitrary width bitfield
175 def bf_inv_mask_imm : Operand<i32>,
177 uint32_t v = (uint32_t)N->getZExtValue();
180 // there can be 1's on either or both "outsides", all the "inside"
182 unsigned int lsb = 0, msb = 31;
183 while (v & (1 << msb)) --msb;
184 while (v & (1 << lsb)) ++lsb;
185 for (unsigned int i = lsb; i <= msb; ++i) {
191 let PrintMethod = "printBitfieldInvMaskImmOperand";
194 /// Split a 32-bit immediate into two 16 bit parts.
195 def lo16 : SDNodeXForm<imm, [{
196 return CurDAG->getTargetConstant((uint32_t)N->getZExtValue() & 0xffff,
200 def hi16 : SDNodeXForm<imm, [{
201 return CurDAG->getTargetConstant((uint32_t)N->getZExtValue() >> 16, MVT::i32);
204 def lo16AllZero : PatLeaf<(i32 imm), [{
205 // Returns true if all low 16-bits are 0.
206 return (((uint32_t)N->getZExtValue()) & 0xFFFFUL) == 0;
209 /// imm0_65535 predicate - True if the 32-bit immediate is in the range
211 def imm0_65535 : PatLeaf<(i32 imm), [{
212 return (uint32_t)N->getZExtValue() < 65536;
215 class BinOpFrag<dag res> : PatFrag<(ops node:$LHS, node:$RHS), res>;
216 class UnOpFrag <dag res> : PatFrag<(ops node:$Src), res>;
218 //===----------------------------------------------------------------------===//
219 // Operand Definitions.
223 def brtarget : Operand<OtherVT>;
225 // A list of registers separated by comma. Used by load/store multiple.
226 def reglist : Operand<i32> {
227 let PrintMethod = "printRegisterList";
230 // An operand for the CONSTPOOL_ENTRY pseudo-instruction.
231 def cpinst_operand : Operand<i32> {
232 let PrintMethod = "printCPInstOperand";
235 def jtblock_operand : Operand<i32> {
236 let PrintMethod = "printJTBlockOperand";
238 def jt2block_operand : Operand<i32> {
239 let PrintMethod = "printJT2BlockOperand";
243 def pclabel : Operand<i32> {
244 let PrintMethod = "printPCLabel";
247 // shifter_operand operands: so_reg and so_imm.
248 def so_reg : Operand<i32>, // reg reg imm
249 ComplexPattern<i32, 3, "SelectShifterOperandReg",
250 [shl,srl,sra,rotr]> {
251 let PrintMethod = "printSORegOperand";
252 let MIOperandInfo = (ops GPR, GPR, i32imm);
255 // so_imm - Match a 32-bit shifter_operand immediate operand, which is an
256 // 8-bit immediate rotated by an arbitrary number of bits. so_imm values are
257 // represented in the imm field in the same 12-bit form that they are encoded
258 // into so_imm instructions: the 8-bit immediate is the least significant bits
259 // [bits 0-7], the 4-bit shift amount is the next 4 bits [bits 8-11].
260 def so_imm : Operand<i32>,
262 return ARM_AM::getSOImmVal(N->getZExtValue()) != -1;
264 let PrintMethod = "printSOImmOperand";
267 // Break so_imm's up into two pieces. This handles immediates with up to 16
268 // bits set in them. This uses so_imm2part to match and so_imm2part_[12] to
269 // get the first/second pieces.
270 def so_imm2part : Operand<i32>,
272 return ARM_AM::isSOImmTwoPartVal((unsigned)N->getZExtValue());
274 let PrintMethod = "printSOImm2PartOperand";
277 def so_imm2part_1 : SDNodeXForm<imm, [{
278 unsigned V = ARM_AM::getSOImmTwoPartFirst((unsigned)N->getZExtValue());
279 return CurDAG->getTargetConstant(V, MVT::i32);
282 def so_imm2part_2 : SDNodeXForm<imm, [{
283 unsigned V = ARM_AM::getSOImmTwoPartSecond((unsigned)N->getZExtValue());
284 return CurDAG->getTargetConstant(V, MVT::i32);
287 def so_neg_imm2part : Operand<i32>, PatLeaf<(imm), [{
288 return ARM_AM::isSOImmTwoPartVal(-(int)N->getZExtValue());
290 let PrintMethod = "printSOImm2PartOperand";
293 def so_neg_imm2part_1 : SDNodeXForm<imm, [{
294 unsigned V = ARM_AM::getSOImmTwoPartFirst(-(int)N->getZExtValue());
295 return CurDAG->getTargetConstant(V, MVT::i32);
298 def so_neg_imm2part_2 : SDNodeXForm<imm, [{
299 unsigned V = ARM_AM::getSOImmTwoPartSecond(-(int)N->getZExtValue());
300 return CurDAG->getTargetConstant(V, MVT::i32);
303 /// imm0_31 predicate - True if the 32-bit immediate is in the range [0,31].
304 def imm0_31 : Operand<i32>, PatLeaf<(imm), [{
305 return (int32_t)N->getZExtValue() < 32;
308 // Define ARM specific addressing modes.
310 // addrmode2 := reg +/- reg shop imm
311 // addrmode2 := reg +/- imm12
313 def addrmode2 : Operand<i32>,
314 ComplexPattern<i32, 3, "SelectAddrMode2", []> {
315 let PrintMethod = "printAddrMode2Operand";
316 let MIOperandInfo = (ops GPR:$base, GPR:$offsreg, i32imm:$offsimm);
319 def am2offset : Operand<i32>,
320 ComplexPattern<i32, 2, "SelectAddrMode2Offset", []> {
321 let PrintMethod = "printAddrMode2OffsetOperand";
322 let MIOperandInfo = (ops GPR, i32imm);
325 // addrmode3 := reg +/- reg
326 // addrmode3 := reg +/- imm8
328 def addrmode3 : Operand<i32>,
329 ComplexPattern<i32, 3, "SelectAddrMode3", []> {
330 let PrintMethod = "printAddrMode3Operand";
331 let MIOperandInfo = (ops GPR:$base, GPR:$offsreg, i32imm:$offsimm);
334 def am3offset : Operand<i32>,
335 ComplexPattern<i32, 2, "SelectAddrMode3Offset", []> {
336 let PrintMethod = "printAddrMode3OffsetOperand";
337 let MIOperandInfo = (ops GPR, i32imm);
340 // addrmode4 := reg, <mode|W>
342 def addrmode4 : Operand<i32>,
343 ComplexPattern<i32, 2, "SelectAddrMode4", []> {
344 let PrintMethod = "printAddrMode4Operand";
345 let MIOperandInfo = (ops GPR, i32imm);
348 // addrmode5 := reg +/- imm8*4
350 def addrmode5 : Operand<i32>,
351 ComplexPattern<i32, 2, "SelectAddrMode5", []> {
352 let PrintMethod = "printAddrMode5Operand";
353 let MIOperandInfo = (ops GPR, i32imm);
356 // addrmode6 := reg with optional writeback
358 def addrmode6 : Operand<i32>,
359 ComplexPattern<i32, 4, "SelectAddrMode6", []> {
360 let PrintMethod = "printAddrMode6Operand";
361 let MIOperandInfo = (ops GPR:$addr, GPR:$upd, i32imm, i32imm);
364 // addrmodepc := pc + reg
366 def addrmodepc : Operand<i32>,
367 ComplexPattern<i32, 2, "SelectAddrModePC", []> {
368 let PrintMethod = "printAddrModePCOperand";
369 let MIOperandInfo = (ops GPR, i32imm);
372 def nohash_imm : Operand<i32> {
373 let PrintMethod = "printNoHashImmediate";
376 //===----------------------------------------------------------------------===//
378 include "ARMInstrFormats.td"
380 //===----------------------------------------------------------------------===//
381 // Multiclass helpers...
384 /// AsI1_bin_irs - Defines a set of (op r, {so_imm|r|so_reg}) patterns for a
385 /// binop that produces a value.
386 multiclass AsI1_bin_irs<bits<4> opcod, string opc, PatFrag opnode,
387 bit Commutable = 0> {
388 def ri : AsI1<opcod, (outs GPR:$dst), (ins GPR:$a, so_imm:$b), DPFrm,
389 IIC_iALUi, opc, "\t$dst, $a, $b",
390 [(set GPR:$dst, (opnode GPR:$a, so_imm:$b))]> {
393 def rr : AsI1<opcod, (outs GPR:$dst), (ins GPR:$a, GPR:$b), DPFrm,
394 IIC_iALUr, opc, "\t$dst, $a, $b",
395 [(set GPR:$dst, (opnode GPR:$a, GPR:$b))]> {
396 let Inst{11-4} = 0b00000000;
398 let isCommutable = Commutable;
400 def rs : AsI1<opcod, (outs GPR:$dst), (ins GPR:$a, so_reg:$b), DPSoRegFrm,
401 IIC_iALUsr, opc, "\t$dst, $a, $b",
402 [(set GPR:$dst, (opnode GPR:$a, so_reg:$b))]> {
407 /// AI1_bin_s_irs - Similar to AsI1_bin_irs except it sets the 's' bit so the
408 /// instruction modifies the CPSR register.
409 let Defs = [CPSR] in {
410 multiclass AI1_bin_s_irs<bits<4> opcod, string opc, PatFrag opnode,
411 bit Commutable = 0> {
412 def ri : AI1<opcod, (outs GPR:$dst), (ins GPR:$a, so_imm:$b), DPFrm,
413 IIC_iALUi, opc, "\t$dst, $a, $b",
414 [(set GPR:$dst, (opnode GPR:$a, so_imm:$b))]> {
418 def rr : AI1<opcod, (outs GPR:$dst), (ins GPR:$a, GPR:$b), DPFrm,
419 IIC_iALUr, opc, "\t$dst, $a, $b",
420 [(set GPR:$dst, (opnode GPR:$a, GPR:$b))]> {
421 let isCommutable = Commutable;
422 let Inst{11-4} = 0b00000000;
426 def rs : AI1<opcod, (outs GPR:$dst), (ins GPR:$a, so_reg:$b), DPSoRegFrm,
427 IIC_iALUsr, opc, "\t$dst, $a, $b",
428 [(set GPR:$dst, (opnode GPR:$a, so_reg:$b))]> {
435 /// AI1_cmp_irs - Defines a set of (op r, {so_imm|r|so_reg}) cmp / test
436 /// patterns. Similar to AsI1_bin_irs except the instruction does not produce
437 /// a explicit result, only implicitly set CPSR.
438 let Defs = [CPSR] in {
439 multiclass AI1_cmp_irs<bits<4> opcod, string opc, PatFrag opnode,
440 bit Commutable = 0> {
441 def ri : AI1<opcod, (outs), (ins GPR:$a, so_imm:$b), DPFrm, IIC_iCMPi,
443 [(opnode GPR:$a, so_imm:$b)]> {
447 def rr : AI1<opcod, (outs), (ins GPR:$a, GPR:$b), DPFrm, IIC_iCMPr,
449 [(opnode GPR:$a, GPR:$b)]> {
450 let Inst{11-4} = 0b00000000;
453 let isCommutable = Commutable;
455 def rs : AI1<opcod, (outs), (ins GPR:$a, so_reg:$b), DPSoRegFrm, IIC_iCMPsr,
457 [(opnode GPR:$a, so_reg:$b)]> {
464 /// AI_unary_rrot - A unary operation with two forms: one whose operand is a
465 /// register and one whose operand is a register rotated by 8/16/24.
466 /// FIXME: Remove the 'r' variant. Its rot_imm is zero.
467 multiclass AI_unary_rrot<bits<8> opcod, string opc, PatFrag opnode> {
468 def r : AExtI<opcod, (outs GPR:$dst), (ins GPR:$src),
469 IIC_iUNAr, opc, "\t$dst, $src",
470 [(set GPR:$dst, (opnode GPR:$src))]>,
471 Requires<[IsARM, HasV6]> {
472 let Inst{11-10} = 0b00;
473 let Inst{19-16} = 0b1111;
475 def r_rot : AExtI<opcod, (outs GPR:$dst), (ins GPR:$src, i32imm:$rot),
476 IIC_iUNAsi, opc, "\t$dst, $src, ror $rot",
477 [(set GPR:$dst, (opnode (rotr GPR:$src, rot_imm:$rot)))]>,
478 Requires<[IsARM, HasV6]> {
479 let Inst{19-16} = 0b1111;
483 /// AI_bin_rrot - A binary operation with two forms: one whose operand is a
484 /// register and one whose operand is a register rotated by 8/16/24.
485 multiclass AI_bin_rrot<bits<8> opcod, string opc, PatFrag opnode> {
486 def rr : AExtI<opcod, (outs GPR:$dst), (ins GPR:$LHS, GPR:$RHS),
487 IIC_iALUr, opc, "\t$dst, $LHS, $RHS",
488 [(set GPR:$dst, (opnode GPR:$LHS, GPR:$RHS))]>,
489 Requires<[IsARM, HasV6]> {
490 let Inst{11-10} = 0b00;
492 def rr_rot : AExtI<opcod, (outs GPR:$dst), (ins GPR:$LHS, GPR:$RHS, i32imm:$rot),
493 IIC_iALUsi, opc, "\t$dst, $LHS, $RHS, ror $rot",
494 [(set GPR:$dst, (opnode GPR:$LHS,
495 (rotr GPR:$RHS, rot_imm:$rot)))]>,
496 Requires<[IsARM, HasV6]>;
499 /// AI1_adde_sube_irs - Define instructions and patterns for adde and sube.
500 let Uses = [CPSR] in {
501 multiclass AI1_adde_sube_irs<bits<4> opcod, string opc, PatFrag opnode,
502 bit Commutable = 0> {
503 def ri : AsI1<opcod, (outs GPR:$dst), (ins GPR:$a, so_imm:$b),
504 DPFrm, IIC_iALUi, opc, "\t$dst, $a, $b",
505 [(set GPR:$dst, (opnode GPR:$a, so_imm:$b))]>,
506 Requires<[IsARM, CarryDefIsUnused]> {
509 def rr : AsI1<opcod, (outs GPR:$dst), (ins GPR:$a, GPR:$b),
510 DPFrm, IIC_iALUr, opc, "\t$dst, $a, $b",
511 [(set GPR:$dst, (opnode GPR:$a, GPR:$b))]>,
512 Requires<[IsARM, CarryDefIsUnused]> {
513 let isCommutable = Commutable;
514 let Inst{11-4} = 0b00000000;
517 def rs : AsI1<opcod, (outs GPR:$dst), (ins GPR:$a, so_reg:$b),
518 DPSoRegFrm, IIC_iALUsr, opc, "\t$dst, $a, $b",
519 [(set GPR:$dst, (opnode GPR:$a, so_reg:$b))]>,
520 Requires<[IsARM, CarryDefIsUnused]> {
524 // Carry setting variants
525 let Defs = [CPSR] in {
526 multiclass AI1_adde_sube_s_irs<bits<4> opcod, string opc, PatFrag opnode,
527 bit Commutable = 0> {
528 def Sri : AXI1<opcod, (outs GPR:$dst), (ins GPR:$a, so_imm:$b),
529 DPFrm, IIC_iALUi, !strconcat(opc, "\t$dst, $a, $b"),
530 [(set GPR:$dst, (opnode GPR:$a, so_imm:$b))]>,
531 Requires<[IsARM, CarryDefIsUsed]> {
536 def Srr : AXI1<opcod, (outs GPR:$dst), (ins GPR:$a, GPR:$b),
537 DPFrm, IIC_iALUr, !strconcat(opc, "\t$dst, $a, $b"),
538 [(set GPR:$dst, (opnode GPR:$a, GPR:$b))]>,
539 Requires<[IsARM, CarryDefIsUsed]> {
541 let Inst{11-4} = 0b00000000;
545 def Srs : AXI1<opcod, (outs GPR:$dst), (ins GPR:$a, so_reg:$b),
546 DPSoRegFrm, IIC_iALUsr, !strconcat(opc, "\t$dst, $a, $b"),
547 [(set GPR:$dst, (opnode GPR:$a, so_reg:$b))]>,
548 Requires<[IsARM, CarryDefIsUsed]> {
557 //===----------------------------------------------------------------------===//
559 //===----------------------------------------------------------------------===//
561 //===----------------------------------------------------------------------===//
562 // Miscellaneous Instructions.
565 /// CONSTPOOL_ENTRY - This instruction represents a floating constant pool in
566 /// the function. The first operand is the ID# for this instruction, the second
567 /// is the index into the MachineConstantPool that this is, the third is the
568 /// size in bytes of this constant pool entry.
569 let neverHasSideEffects = 1, isNotDuplicable = 1 in
570 def CONSTPOOL_ENTRY :
571 PseudoInst<(outs), (ins cpinst_operand:$instid, cpinst_operand:$cpidx,
572 i32imm:$size), NoItinerary,
573 "${instid:label} ${cpidx:cpentry}", []>;
575 let Defs = [SP], Uses = [SP] in {
577 PseudoInst<(outs), (ins i32imm:$amt1, i32imm:$amt2, pred:$p), NoItinerary,
578 "@ ADJCALLSTACKUP $amt1",
579 [(ARMcallseq_end timm:$amt1, timm:$amt2)]>;
581 def ADJCALLSTACKDOWN :
582 PseudoInst<(outs), (ins i32imm:$amt, pred:$p), NoItinerary,
583 "@ ADJCALLSTACKDOWN $amt",
584 [(ARMcallseq_start timm:$amt)]>;
587 // Address computation and loads and stores in PIC mode.
588 let isNotDuplicable = 1 in {
589 def PICADD : AXI1<0b0100, (outs GPR:$dst), (ins GPR:$a, pclabel:$cp, pred:$p),
590 Pseudo, IIC_iALUr, "\n$cp:\n\tadd$p\t$dst, pc, $a",
591 [(set GPR:$dst, (ARMpic_add GPR:$a, imm:$cp))]>;
593 let AddedComplexity = 10 in {
594 def PICLDR : AXI2ldw<(outs GPR:$dst), (ins addrmodepc:$addr, pred:$p),
595 Pseudo, IIC_iLoadr, "\n${addr:label}:\n\tldr$p\t$dst, $addr",
596 [(set GPR:$dst, (load addrmodepc:$addr))]>;
598 def PICLDRH : AXI3ldh<(outs GPR:$dst), (ins addrmodepc:$addr, pred:$p),
599 Pseudo, IIC_iLoadr, "\n${addr:label}:\n\tldr${p}h\t$dst, $addr",
600 [(set GPR:$dst, (zextloadi16 addrmodepc:$addr))]>;
602 def PICLDRB : AXI2ldb<(outs GPR:$dst), (ins addrmodepc:$addr, pred:$p),
603 Pseudo, IIC_iLoadr, "\n${addr:label}:\n\tldr${p}b\t$dst, $addr",
604 [(set GPR:$dst, (zextloadi8 addrmodepc:$addr))]>;
606 def PICLDRSH : AXI3ldsh<(outs GPR:$dst), (ins addrmodepc:$addr, pred:$p),
607 Pseudo, IIC_iLoadr, "\n${addr:label}:\n\tldr${p}sh\t$dst, $addr",
608 [(set GPR:$dst, (sextloadi16 addrmodepc:$addr))]>;
610 def PICLDRSB : AXI3ldsb<(outs GPR:$dst), (ins addrmodepc:$addr, pred:$p),
611 Pseudo, IIC_iLoadr, "\n${addr:label}:\n\tldr${p}sb\t$dst, $addr",
612 [(set GPR:$dst, (sextloadi8 addrmodepc:$addr))]>;
614 let AddedComplexity = 10 in {
615 def PICSTR : AXI2stw<(outs), (ins GPR:$src, addrmodepc:$addr, pred:$p),
616 Pseudo, IIC_iStorer, "\n${addr:label}:\n\tstr$p\t$src, $addr",
617 [(store GPR:$src, addrmodepc:$addr)]>;
619 def PICSTRH : AXI3sth<(outs), (ins GPR:$src, addrmodepc:$addr, pred:$p),
620 Pseudo, IIC_iStorer, "\n${addr:label}:\n\tstrh${p}\t$src, $addr",
621 [(truncstorei16 GPR:$src, addrmodepc:$addr)]>;
623 def PICSTRB : AXI2stb<(outs), (ins GPR:$src, addrmodepc:$addr, pred:$p),
624 Pseudo, IIC_iStorer, "\n${addr:label}:\n\tstrb${p}\t$src, $addr",
625 [(truncstorei8 GPR:$src, addrmodepc:$addr)]>;
627 } // isNotDuplicable = 1
630 // LEApcrel - Load a pc-relative address into a register without offending the
632 def LEApcrel : AXI1<0x0, (outs GPR:$dst), (ins i32imm:$label, pred:$p),
634 !strconcat(!strconcat(".set ${:private}PCRELV${:uid}, ($label-(",
635 "${:private}PCRELL${:uid}+8))\n"),
636 !strconcat("${:private}PCRELL${:uid}:\n\t",
637 "add$p\t$dst, pc, #${:private}PCRELV${:uid}")),
640 def LEApcrelJT : AXI1<0x0, (outs GPR:$dst),
641 (ins i32imm:$label, nohash_imm:$id, pred:$p),
643 !strconcat(!strconcat(".set ${:private}PCRELV${:uid}, "
645 "${:private}PCRELL${:uid}+8))\n"),
646 !strconcat("${:private}PCRELL${:uid}:\n\t",
647 "add$p\t$dst, pc, #${:private}PCRELV${:uid}")),
652 //===----------------------------------------------------------------------===//
653 // Control Flow Instructions.
656 let isReturn = 1, isTerminator = 1, isBarrier = 1 in
657 def BX_RET : AI<(outs), (ins), BrMiscFrm, IIC_Br,
658 "bx", "\tlr", [(ARMretflag)]> {
659 let Inst{3-0} = 0b1110;
660 let Inst{7-4} = 0b0001;
661 let Inst{19-8} = 0b111111111111;
662 let Inst{27-20} = 0b00010010;
666 let isBranch = 1, isTerminator = 1, isBarrier = 1, isIndirectBranch = 1 in {
667 def BRIND : AXI<(outs), (ins GPR:$dst), BrMiscFrm, IIC_Br, "bx\t$dst",
668 [(brind GPR:$dst)]> {
669 let Inst{7-4} = 0b0001;
670 let Inst{19-8} = 0b111111111111;
671 let Inst{27-20} = 0b00010010;
672 let Inst{31-28} = 0b1110;
676 // FIXME: remove when we have a way to marking a MI with these properties.
677 // FIXME: Should pc be an implicit operand like PICADD, etc?
678 let isReturn = 1, isTerminator = 1, isBarrier = 1, mayLoad = 1,
679 hasExtraDefRegAllocReq = 1 in
680 def LDM_RET : AXI4ld<(outs),
681 (ins addrmode4:$addr, pred:$p, reglist:$wb, variable_ops),
682 LdStMulFrm, IIC_Br, "ldm${addr:submode}${p}\t$addr, $wb",
685 // On non-Darwin platforms R9 is callee-saved.
687 Defs = [R0, R1, R2, R3, R12, LR,
688 D0, D1, D2, D3, D4, D5, D6, D7,
689 D16, D17, D18, D19, D20, D21, D22, D23,
690 D24, D25, D26, D27, D28, D29, D30, D31, CPSR, FPSCR] in {
691 def BL : ABXI<0b1011, (outs), (ins i32imm:$func, variable_ops),
692 IIC_Br, "bl\t${func:call}",
693 [(ARMcall tglobaladdr:$func)]>,
694 Requires<[IsARM, IsNotDarwin]> {
695 let Inst{31-28} = 0b1110;
698 def BL_pred : ABI<0b1011, (outs), (ins i32imm:$func, variable_ops),
699 IIC_Br, "bl", "\t${func:call}",
700 [(ARMcall_pred tglobaladdr:$func)]>,
701 Requires<[IsARM, IsNotDarwin]>;
704 def BLX : AXI<(outs), (ins GPR:$func, variable_ops), BrMiscFrm,
705 IIC_Br, "blx\t$func",
706 [(ARMcall GPR:$func)]>,
707 Requires<[IsARM, HasV5T, IsNotDarwin]> {
708 let Inst{7-4} = 0b0011;
709 let Inst{19-8} = 0b111111111111;
710 let Inst{27-20} = 0b00010010;
714 def BX : ABXIx2<(outs), (ins GPR:$func, variable_ops),
715 IIC_Br, "mov\tlr, pc\n\tbx\t$func",
716 [(ARMcall_nolink GPR:$func)]>,
717 Requires<[IsARM, IsNotDarwin]> {
718 let Inst{7-4} = 0b0001;
719 let Inst{19-8} = 0b111111111111;
720 let Inst{27-20} = 0b00010010;
724 // On Darwin R9 is call-clobbered.
726 Defs = [R0, R1, R2, R3, R9, R12, LR,
727 D0, D1, D2, D3, D4, D5, D6, D7,
728 D16, D17, D18, D19, D20, D21, D22, D23,
729 D24, D25, D26, D27, D28, D29, D30, D31, CPSR, FPSCR] in {
730 def BLr9 : ABXI<0b1011, (outs), (ins i32imm:$func, variable_ops),
731 IIC_Br, "bl\t${func:call}",
732 [(ARMcall tglobaladdr:$func)]>, Requires<[IsARM, IsDarwin]> {
733 let Inst{31-28} = 0b1110;
736 def BLr9_pred : ABI<0b1011, (outs), (ins i32imm:$func, variable_ops),
737 IIC_Br, "bl", "\t${func:call}",
738 [(ARMcall_pred tglobaladdr:$func)]>,
739 Requires<[IsARM, IsDarwin]>;
742 def BLXr9 : AXI<(outs), (ins GPR:$func, variable_ops), BrMiscFrm,
743 IIC_Br, "blx\t$func",
744 [(ARMcall GPR:$func)]>, Requires<[IsARM, HasV5T, IsDarwin]> {
745 let Inst{7-4} = 0b0011;
746 let Inst{19-8} = 0b111111111111;
747 let Inst{27-20} = 0b00010010;
751 def BXr9 : ABXIx2<(outs), (ins GPR:$func, variable_ops),
752 IIC_Br, "mov\tlr, pc\n\tbx\t$func",
753 [(ARMcall_nolink GPR:$func)]>, Requires<[IsARM, IsDarwin]> {
754 let Inst{7-4} = 0b0001;
755 let Inst{19-8} = 0b111111111111;
756 let Inst{27-20} = 0b00010010;
760 let isBranch = 1, isTerminator = 1 in {
761 // B is "predicable" since it can be xformed into a Bcc.
762 let isBarrier = 1 in {
763 let isPredicable = 1 in
764 def B : ABXI<0b1010, (outs), (ins brtarget:$target), IIC_Br,
765 "b\t$target", [(br bb:$target)]>;
767 let isNotDuplicable = 1, isIndirectBranch = 1 in {
768 def BR_JTr : JTI<(outs), (ins GPR:$target, jtblock_operand:$jt, i32imm:$id),
769 IIC_Br, "mov\tpc, $target \n$jt",
770 [(ARMbrjt GPR:$target, tjumptable:$jt, imm:$id)]> {
771 let Inst{15-12} = 0b1111;
772 let Inst{20} = 0; // S Bit
773 let Inst{24-21} = 0b1101;
774 let Inst{27-25} = 0b000;
776 def BR_JTm : JTI<(outs),
777 (ins addrmode2:$target, jtblock_operand:$jt, i32imm:$id),
778 IIC_Br, "ldr\tpc, $target \n$jt",
779 [(ARMbrjt (i32 (load addrmode2:$target)), tjumptable:$jt,
781 let Inst{15-12} = 0b1111;
782 let Inst{20} = 1; // L bit
783 let Inst{21} = 0; // W bit
784 let Inst{22} = 0; // B bit
785 let Inst{24} = 1; // P bit
786 let Inst{27-25} = 0b011;
788 def BR_JTadd : JTI<(outs),
789 (ins GPR:$target, GPR:$idx, jtblock_operand:$jt, i32imm:$id),
790 IIC_Br, "add\tpc, $target, $idx \n$jt",
791 [(ARMbrjt (add GPR:$target, GPR:$idx), tjumptable:$jt,
793 let Inst{15-12} = 0b1111;
794 let Inst{20} = 0; // S bit
795 let Inst{24-21} = 0b0100;
796 let Inst{27-25} = 0b000;
798 } // isNotDuplicable = 1, isIndirectBranch = 1
801 // FIXME: should be able to write a pattern for ARMBrcond, but can't use
802 // a two-value operand where a dag node expects two operands. :(
803 def Bcc : ABI<0b1010, (outs), (ins brtarget:$target),
804 IIC_Br, "b", "\t$target",
805 [/*(ARMbrcond bb:$target, imm:$cc, CCR:$ccr)*/]>;
808 //===----------------------------------------------------------------------===//
809 // Load / store Instructions.
813 let canFoldAsLoad = 1, isReMaterializable = 1, mayHaveSideEffects = 1 in
814 def LDR : AI2ldw<(outs GPR:$dst), (ins addrmode2:$addr), LdFrm, IIC_iLoadr,
815 "ldr", "\t$dst, $addr",
816 [(set GPR:$dst, (load addrmode2:$addr))]>;
818 // Special LDR for loads from non-pc-relative constpools.
819 let canFoldAsLoad = 1, mayLoad = 1, isReMaterializable = 1,
820 mayHaveSideEffects = 1 in
821 def LDRcp : AI2ldw<(outs GPR:$dst), (ins addrmode2:$addr), LdFrm, IIC_iLoadr,
822 "ldr", "\t$dst, $addr", []>;
824 // Loads with zero extension
825 def LDRH : AI3ldh<(outs GPR:$dst), (ins addrmode3:$addr), LdMiscFrm,
826 IIC_iLoadr, "ldrh", "\t$dst, $addr",
827 [(set GPR:$dst, (zextloadi16 addrmode3:$addr))]>;
829 def LDRB : AI2ldb<(outs GPR:$dst), (ins addrmode2:$addr), LdFrm,
830 IIC_iLoadr, "ldrb", "\t$dst, $addr",
831 [(set GPR:$dst, (zextloadi8 addrmode2:$addr))]>;
833 // Loads with sign extension
834 def LDRSH : AI3ldsh<(outs GPR:$dst), (ins addrmode3:$addr), LdMiscFrm,
835 IIC_iLoadr, "ldrsh", "\t$dst, $addr",
836 [(set GPR:$dst, (sextloadi16 addrmode3:$addr))]>;
838 def LDRSB : AI3ldsb<(outs GPR:$dst), (ins addrmode3:$addr), LdMiscFrm,
839 IIC_iLoadr, "ldrsb", "\t$dst, $addr",
840 [(set GPR:$dst, (sextloadi8 addrmode3:$addr))]>;
842 let mayLoad = 1, hasExtraDefRegAllocReq = 1 in {
844 def LDRD : AI3ldd<(outs GPR:$dst1, GPR:$dst2), (ins addrmode3:$addr), LdMiscFrm,
845 IIC_iLoadr, "ldrd", "\t$dst1, $addr",
846 []>, Requires<[IsARM, HasV5TE]>;
849 def LDR_PRE : AI2ldwpr<(outs GPR:$dst, GPR:$base_wb),
850 (ins addrmode2:$addr), LdFrm, IIC_iLoadru,
851 "ldr", "\t$dst, $addr!", "$addr.base = $base_wb", []>;
853 def LDR_POST : AI2ldwpo<(outs GPR:$dst, GPR:$base_wb),
854 (ins GPR:$base, am2offset:$offset), LdFrm, IIC_iLoadru,
855 "ldr", "\t$dst, [$base], $offset", "$base = $base_wb", []>;
857 def LDRH_PRE : AI3ldhpr<(outs GPR:$dst, GPR:$base_wb),
858 (ins addrmode3:$addr), LdMiscFrm, IIC_iLoadru,
859 "ldrh", "\t$dst, $addr!", "$addr.base = $base_wb", []>;
861 def LDRH_POST : AI3ldhpo<(outs GPR:$dst, GPR:$base_wb),
862 (ins GPR:$base,am3offset:$offset), LdMiscFrm, IIC_iLoadru,
863 "ldrh", "\t$dst, [$base], $offset", "$base = $base_wb", []>;
865 def LDRB_PRE : AI2ldbpr<(outs GPR:$dst, GPR:$base_wb),
866 (ins addrmode2:$addr), LdFrm, IIC_iLoadru,
867 "ldrb", "\t$dst, $addr!", "$addr.base = $base_wb", []>;
869 def LDRB_POST : AI2ldbpo<(outs GPR:$dst, GPR:$base_wb),
870 (ins GPR:$base,am2offset:$offset), LdFrm, IIC_iLoadru,
871 "ldrb", "\t$dst, [$base], $offset", "$base = $base_wb", []>;
873 def LDRSH_PRE : AI3ldshpr<(outs GPR:$dst, GPR:$base_wb),
874 (ins addrmode3:$addr), LdMiscFrm, IIC_iLoadru,
875 "ldrsh", "\t$dst, $addr!", "$addr.base = $base_wb", []>;
877 def LDRSH_POST: AI3ldshpo<(outs GPR:$dst, GPR:$base_wb),
878 (ins GPR:$base,am3offset:$offset), LdMiscFrm, IIC_iLoadru,
879 "ldrsh", "\t$dst, [$base], $offset", "$base = $base_wb", []>;
881 def LDRSB_PRE : AI3ldsbpr<(outs GPR:$dst, GPR:$base_wb),
882 (ins addrmode3:$addr), LdMiscFrm, IIC_iLoadru,
883 "ldrsb", "\t$dst, $addr!", "$addr.base = $base_wb", []>;
885 def LDRSB_POST: AI3ldsbpo<(outs GPR:$dst, GPR:$base_wb),
886 (ins GPR:$base,am3offset:$offset), LdMiscFrm, IIC_iLoadru,
887 "ldrsb", "\t$dst, [$base], $offset", "$base = $base_wb", []>;
891 def STR : AI2stw<(outs), (ins GPR:$src, addrmode2:$addr), StFrm, IIC_iStorer,
892 "str", "\t$src, $addr",
893 [(store GPR:$src, addrmode2:$addr)]>;
895 // Stores with truncate
896 def STRH : AI3sth<(outs), (ins GPR:$src, addrmode3:$addr), StMiscFrm, IIC_iStorer,
897 "strh", "\t$src, $addr",
898 [(truncstorei16 GPR:$src, addrmode3:$addr)]>;
900 def STRB : AI2stb<(outs), (ins GPR:$src, addrmode2:$addr), StFrm, IIC_iStorer,
901 "strb", "\t$src, $addr",
902 [(truncstorei8 GPR:$src, addrmode2:$addr)]>;
905 let mayStore = 1, hasExtraSrcRegAllocReq = 1 in
906 def STRD : AI3std<(outs), (ins GPR:$src1, GPR:$src2, addrmode3:$addr),
907 StMiscFrm, IIC_iStorer,
908 "strd", "\t$src1, $addr", []>, Requires<[IsARM, HasV5TE]>;
911 def STR_PRE : AI2stwpr<(outs GPR:$base_wb),
912 (ins GPR:$src, GPR:$base, am2offset:$offset),
914 "str", "\t$src, [$base, $offset]!", "$base = $base_wb",
916 (pre_store GPR:$src, GPR:$base, am2offset:$offset))]>;
918 def STR_POST : AI2stwpo<(outs GPR:$base_wb),
919 (ins GPR:$src, GPR:$base,am2offset:$offset),
921 "str", "\t$src, [$base], $offset", "$base = $base_wb",
923 (post_store GPR:$src, GPR:$base, am2offset:$offset))]>;
925 def STRH_PRE : AI3sthpr<(outs GPR:$base_wb),
926 (ins GPR:$src, GPR:$base,am3offset:$offset),
927 StMiscFrm, IIC_iStoreru,
928 "strh", "\t$src, [$base, $offset]!", "$base = $base_wb",
930 (pre_truncsti16 GPR:$src, GPR:$base,am3offset:$offset))]>;
932 def STRH_POST: AI3sthpo<(outs GPR:$base_wb),
933 (ins GPR:$src, GPR:$base,am3offset:$offset),
934 StMiscFrm, IIC_iStoreru,
935 "strh", "\t$src, [$base], $offset", "$base = $base_wb",
936 [(set GPR:$base_wb, (post_truncsti16 GPR:$src,
937 GPR:$base, am3offset:$offset))]>;
939 def STRB_PRE : AI2stbpr<(outs GPR:$base_wb),
940 (ins GPR:$src, GPR:$base,am2offset:$offset),
942 "strb", "\t$src, [$base, $offset]!", "$base = $base_wb",
943 [(set GPR:$base_wb, (pre_truncsti8 GPR:$src,
944 GPR:$base, am2offset:$offset))]>;
946 def STRB_POST: AI2stbpo<(outs GPR:$base_wb),
947 (ins GPR:$src, GPR:$base,am2offset:$offset),
949 "strb", "\t$src, [$base], $offset", "$base = $base_wb",
950 [(set GPR:$base_wb, (post_truncsti8 GPR:$src,
951 GPR:$base, am2offset:$offset))]>;
953 //===----------------------------------------------------------------------===//
954 // Load / store multiple Instructions.
957 let mayLoad = 1, hasExtraDefRegAllocReq = 1 in
958 def LDM : AXI4ld<(outs),
959 (ins addrmode4:$addr, pred:$p, reglist:$wb, variable_ops),
960 LdStMulFrm, IIC_iLoadm, "ldm${addr:submode}${p}\t$addr, $wb",
963 let mayStore = 1, hasExtraSrcRegAllocReq = 1 in
964 def STM : AXI4st<(outs),
965 (ins addrmode4:$addr, pred:$p, reglist:$wb, variable_ops),
966 LdStMulFrm, IIC_iStorem, "stm${addr:submode}${p}\t$addr, $wb",
969 //===----------------------------------------------------------------------===//
970 // Move Instructions.
973 let neverHasSideEffects = 1 in
974 def MOVr : AsI1<0b1101, (outs GPR:$dst), (ins GPR:$src), DPFrm, IIC_iMOVr,
975 "mov", "\t$dst, $src", []>, UnaryDP {
976 let Inst{11-4} = 0b00000000;
980 def MOVs : AsI1<0b1101, (outs GPR:$dst), (ins so_reg:$src),
981 DPSoRegFrm, IIC_iMOVsr,
982 "mov", "\t$dst, $src", [(set GPR:$dst, so_reg:$src)]>, UnaryDP {
986 let isReMaterializable = 1, isAsCheapAsAMove = 1 in
987 def MOVi : AsI1<0b1101, (outs GPR:$dst), (ins so_imm:$src), DPFrm, IIC_iMOVi,
988 "mov", "\t$dst, $src", [(set GPR:$dst, so_imm:$src)]>, UnaryDP {
992 let isReMaterializable = 1, isAsCheapAsAMove = 1 in
993 def MOVi16 : AI1<0b1000, (outs GPR:$dst), (ins i32imm:$src),
995 "movw", "\t$dst, $src",
996 [(set GPR:$dst, imm0_65535:$src)]>,
997 Requires<[IsARM, HasV6T2]> {
1002 let Constraints = "$src = $dst" in
1003 def MOVTi16 : AI1<0b1010, (outs GPR:$dst), (ins GPR:$src, i32imm:$imm),
1005 "movt", "\t$dst, $imm",
1007 (or (and GPR:$src, 0xffff),
1008 lo16AllZero:$imm))]>, UnaryDP,
1009 Requires<[IsARM, HasV6T2]> {
1014 def : ARMPat<(or GPR:$src, 0xffff0000), (MOVTi16 GPR:$src, 0xffff)>,
1015 Requires<[IsARM, HasV6T2]>;
1017 let Uses = [CPSR] in
1018 def MOVrx : AsI1<0b1101, (outs GPR:$dst), (ins GPR:$src), Pseudo, IIC_iMOVsi,
1019 "mov", "\t$dst, $src, rrx",
1020 [(set GPR:$dst, (ARMrrx GPR:$src))]>, UnaryDP;
1022 // These aren't really mov instructions, but we have to define them this way
1023 // due to flag operands.
1025 let Defs = [CPSR] in {
1026 def MOVsrl_flag : AI1<0b1101, (outs GPR:$dst), (ins GPR:$src), Pseudo,
1027 IIC_iMOVsi, "movs", "\t$dst, $src, lsr #1",
1028 [(set GPR:$dst, (ARMsrl_flag GPR:$src))]>, UnaryDP;
1029 def MOVsra_flag : AI1<0b1101, (outs GPR:$dst), (ins GPR:$src), Pseudo,
1030 IIC_iMOVsi, "movs", "\t$dst, $src, asr #1",
1031 [(set GPR:$dst, (ARMsra_flag GPR:$src))]>, UnaryDP;
1034 //===----------------------------------------------------------------------===//
1035 // Extend Instructions.
1040 defm SXTB : AI_unary_rrot<0b01101010,
1041 "sxtb", UnOpFrag<(sext_inreg node:$Src, i8)>>;
1042 defm SXTH : AI_unary_rrot<0b01101011,
1043 "sxth", UnOpFrag<(sext_inreg node:$Src, i16)>>;
1045 defm SXTAB : AI_bin_rrot<0b01101010,
1046 "sxtab", BinOpFrag<(add node:$LHS, (sext_inreg node:$RHS, i8))>>;
1047 defm SXTAH : AI_bin_rrot<0b01101011,
1048 "sxtah", BinOpFrag<(add node:$LHS, (sext_inreg node:$RHS,i16))>>;
1050 // TODO: SXT(A){B|H}16
1054 let AddedComplexity = 16 in {
1055 defm UXTB : AI_unary_rrot<0b01101110,
1056 "uxtb" , UnOpFrag<(and node:$Src, 0x000000FF)>>;
1057 defm UXTH : AI_unary_rrot<0b01101111,
1058 "uxth" , UnOpFrag<(and node:$Src, 0x0000FFFF)>>;
1059 defm UXTB16 : AI_unary_rrot<0b01101100,
1060 "uxtb16", UnOpFrag<(and node:$Src, 0x00FF00FF)>>;
1062 def : ARMV6Pat<(and (shl GPR:$Src, (i32 8)), 0xFF00FF),
1063 (UXTB16r_rot GPR:$Src, 24)>;
1064 def : ARMV6Pat<(and (srl GPR:$Src, (i32 8)), 0xFF00FF),
1065 (UXTB16r_rot GPR:$Src, 8)>;
1067 defm UXTAB : AI_bin_rrot<0b01101110, "uxtab",
1068 BinOpFrag<(add node:$LHS, (and node:$RHS, 0x00FF))>>;
1069 defm UXTAH : AI_bin_rrot<0b01101111, "uxtah",
1070 BinOpFrag<(add node:$LHS, (and node:$RHS, 0xFFFF))>>;
1073 // This isn't safe in general, the add is two 16-bit units, not a 32-bit add.
1074 //defm UXTAB16 : xxx<"uxtab16", 0xff00ff>;
1076 // TODO: UXT(A){B|H}16
1078 def SBFX : I<(outs GPR:$dst),
1079 (ins GPR:$src, imm0_31:$lsb, imm0_31:$width),
1080 AddrMode1, Size4Bytes, IndexModeNone, DPFrm, IIC_iALUi,
1081 "sbfx", "\t$dst, $src, $lsb, $width", "", []>,
1082 Requires<[IsARM, HasV6T2]> {
1083 let Inst{27-21} = 0b0111101;
1084 let Inst{6-4} = 0b101;
1087 def UBFX : I<(outs GPR:$dst),
1088 (ins GPR:$src, imm0_31:$lsb, imm0_31:$width),
1089 AddrMode1, Size4Bytes, IndexModeNone, DPFrm, IIC_iALUi,
1090 "ubfx", "\t$dst, $src, $lsb, $width", "", []>,
1091 Requires<[IsARM, HasV6T2]> {
1092 let Inst{27-21} = 0b0111111;
1093 let Inst{6-4} = 0b101;
1096 //===----------------------------------------------------------------------===//
1097 // Arithmetic Instructions.
1100 defm ADD : AsI1_bin_irs<0b0100, "add",
1101 BinOpFrag<(add node:$LHS, node:$RHS)>, 1>;
1102 defm SUB : AsI1_bin_irs<0b0010, "sub",
1103 BinOpFrag<(sub node:$LHS, node:$RHS)>>;
1105 // ADD and SUB with 's' bit set.
1106 defm ADDS : AI1_bin_s_irs<0b0100, "adds",
1107 BinOpFrag<(addc node:$LHS, node:$RHS)>, 1>;
1108 defm SUBS : AI1_bin_s_irs<0b0010, "subs",
1109 BinOpFrag<(subc node:$LHS, node:$RHS)>>;
1111 defm ADC : AI1_adde_sube_irs<0b0101, "adc",
1112 BinOpFrag<(adde node:$LHS, node:$RHS)>, 1>;
1113 defm SBC : AI1_adde_sube_irs<0b0110, "sbc",
1114 BinOpFrag<(sube node:$LHS, node:$RHS)>>;
1115 defm ADCS : AI1_adde_sube_s_irs<0b0101, "adcs",
1116 BinOpFrag<(adde node:$LHS, node:$RHS)>, 1>;
1117 defm SBCS : AI1_adde_sube_s_irs<0b0110, "sbcs",
1118 BinOpFrag<(sube node:$LHS, node:$RHS)>>;
1120 // These don't define reg/reg forms, because they are handled above.
1121 def RSBri : AsI1<0b0011, (outs GPR:$dst), (ins GPR:$a, so_imm:$b), DPFrm,
1122 IIC_iALUi, "rsb", "\t$dst, $a, $b",
1123 [(set GPR:$dst, (sub so_imm:$b, GPR:$a))]> {
1127 def RSBrs : AsI1<0b0011, (outs GPR:$dst), (ins GPR:$a, so_reg:$b), DPSoRegFrm,
1128 IIC_iALUsr, "rsb", "\t$dst, $a, $b",
1129 [(set GPR:$dst, (sub so_reg:$b, GPR:$a))]> {
1133 // RSB with 's' bit set.
1134 let Defs = [CPSR] in {
1135 def RSBSri : AI1<0b0011, (outs GPR:$dst), (ins GPR:$a, so_imm:$b), DPFrm,
1136 IIC_iALUi, "rsbs", "\t$dst, $a, $b",
1137 [(set GPR:$dst, (subc so_imm:$b, GPR:$a))]> {
1141 def RSBSrs : AI1<0b0011, (outs GPR:$dst), (ins GPR:$a, so_reg:$b), DPSoRegFrm,
1142 IIC_iALUsr, "rsbs", "\t$dst, $a, $b",
1143 [(set GPR:$dst, (subc so_reg:$b, GPR:$a))]> {
1149 let Uses = [CPSR] in {
1150 def RSCri : AsI1<0b0111, (outs GPR:$dst), (ins GPR:$a, so_imm:$b),
1151 DPFrm, IIC_iALUi, "rsc", "\t$dst, $a, $b",
1152 [(set GPR:$dst, (sube so_imm:$b, GPR:$a))]>,
1153 Requires<[IsARM, CarryDefIsUnused]> {
1156 def RSCrs : AsI1<0b0111, (outs GPR:$dst), (ins GPR:$a, so_reg:$b),
1157 DPSoRegFrm, IIC_iALUsr, "rsc", "\t$dst, $a, $b",
1158 [(set GPR:$dst, (sube so_reg:$b, GPR:$a))]>,
1159 Requires<[IsARM, CarryDefIsUnused]> {
1164 // FIXME: Allow these to be predicated.
1165 let Defs = [CPSR], Uses = [CPSR] in {
1166 def RSCSri : AXI1<0b0111, (outs GPR:$dst), (ins GPR:$a, so_imm:$b),
1167 DPFrm, IIC_iALUi, "rscs\t$dst, $a, $b",
1168 [(set GPR:$dst, (sube so_imm:$b, GPR:$a))]>,
1169 Requires<[IsARM, CarryDefIsUnused]> {
1173 def RSCSrs : AXI1<0b0111, (outs GPR:$dst), (ins GPR:$a, so_reg:$b),
1174 DPSoRegFrm, IIC_iALUsr, "rscs\t$dst, $a, $b",
1175 [(set GPR:$dst, (sube so_reg:$b, GPR:$a))]>,
1176 Requires<[IsARM, CarryDefIsUnused]> {
1182 // (sub X, imm) gets canonicalized to (add X, -imm). Match this form.
1183 def : ARMPat<(add GPR:$src, so_imm_neg:$imm),
1184 (SUBri GPR:$src, so_imm_neg:$imm)>;
1186 //def : ARMPat<(addc GPR:$src, so_imm_neg:$imm),
1187 // (SUBSri GPR:$src, so_imm_neg:$imm)>;
1188 //def : ARMPat<(adde GPR:$src, so_imm_neg:$imm),
1189 // (SBCri GPR:$src, so_imm_neg:$imm)>;
1191 // Note: These are implemented in C++ code, because they have to generate
1192 // ADD/SUBrs instructions, which use a complex pattern that a xform function
1194 // (mul X, 2^n+1) -> (add (X << n), X)
1195 // (mul X, 2^n-1) -> (rsb X, (X << n))
1198 //===----------------------------------------------------------------------===//
1199 // Bitwise Instructions.
1202 defm AND : AsI1_bin_irs<0b0000, "and",
1203 BinOpFrag<(and node:$LHS, node:$RHS)>, 1>;
1204 defm ORR : AsI1_bin_irs<0b1100, "orr",
1205 BinOpFrag<(or node:$LHS, node:$RHS)>, 1>;
1206 defm EOR : AsI1_bin_irs<0b0001, "eor",
1207 BinOpFrag<(xor node:$LHS, node:$RHS)>, 1>;
1208 defm BIC : AsI1_bin_irs<0b1110, "bic",
1209 BinOpFrag<(and node:$LHS, (not node:$RHS))>>;
1211 def BFC : I<(outs GPR:$dst), (ins GPR:$src, bf_inv_mask_imm:$imm),
1212 AddrMode1, Size4Bytes, IndexModeNone, DPFrm, IIC_iUNAsi,
1213 "bfc", "\t$dst, $imm", "$src = $dst",
1214 [(set GPR:$dst, (and GPR:$src, bf_inv_mask_imm:$imm))]>,
1215 Requires<[IsARM, HasV6T2]> {
1216 let Inst{27-21} = 0b0111110;
1217 let Inst{6-0} = 0b0011111;
1220 def MVNr : AsI1<0b1111, (outs GPR:$dst), (ins GPR:$src), DPFrm, IIC_iMOVr,
1221 "mvn", "\t$dst, $src",
1222 [(set GPR:$dst, (not GPR:$src))]>, UnaryDP {
1223 let Inst{11-4} = 0b00000000;
1225 def MVNs : AsI1<0b1111, (outs GPR:$dst), (ins so_reg:$src), DPSoRegFrm,
1226 IIC_iMOVsr, "mvn", "\t$dst, $src",
1227 [(set GPR:$dst, (not so_reg:$src))]>, UnaryDP;
1228 let isReMaterializable = 1, isAsCheapAsAMove = 1 in
1229 def MVNi : AsI1<0b1111, (outs GPR:$dst), (ins so_imm:$imm), DPFrm,
1230 IIC_iMOVi, "mvn", "\t$dst, $imm",
1231 [(set GPR:$dst, so_imm_not:$imm)]>,UnaryDP {
1235 def : ARMPat<(and GPR:$src, so_imm_not:$imm),
1236 (BICri GPR:$src, so_imm_not:$imm)>;
1238 //===----------------------------------------------------------------------===//
1239 // Multiply Instructions.
1242 let isCommutable = 1 in
1243 def MUL : AsMul1I<0b0000000, (outs GPR:$dst), (ins GPR:$a, GPR:$b),
1244 IIC_iMUL32, "mul", "\t$dst, $a, $b",
1245 [(set GPR:$dst, (mul GPR:$a, GPR:$b))]>;
1247 def MLA : AsMul1I<0b0000001, (outs GPR:$dst), (ins GPR:$a, GPR:$b, GPR:$c),
1248 IIC_iMAC32, "mla", "\t$dst, $a, $b, $c",
1249 [(set GPR:$dst, (add (mul GPR:$a, GPR:$b), GPR:$c))]>;
1251 def MLS : AMul1I<0b0000011, (outs GPR:$dst), (ins GPR:$a, GPR:$b, GPR:$c),
1252 IIC_iMAC32, "mls", "\t$dst, $a, $b, $c",
1253 [(set GPR:$dst, (sub GPR:$c, (mul GPR:$a, GPR:$b)))]>,
1254 Requires<[IsARM, HasV6T2]>;
1256 // Extra precision multiplies with low / high results
1257 let neverHasSideEffects = 1 in {
1258 let isCommutable = 1 in {
1259 def SMULL : AsMul1I<0b0000110, (outs GPR:$ldst, GPR:$hdst),
1260 (ins GPR:$a, GPR:$b), IIC_iMUL64,
1261 "smull", "\t$ldst, $hdst, $a, $b", []>;
1263 def UMULL : AsMul1I<0b0000100, (outs GPR:$ldst, GPR:$hdst),
1264 (ins GPR:$a, GPR:$b), IIC_iMUL64,
1265 "umull", "\t$ldst, $hdst, $a, $b", []>;
1268 // Multiply + accumulate
1269 def SMLAL : AsMul1I<0b0000111, (outs GPR:$ldst, GPR:$hdst),
1270 (ins GPR:$a, GPR:$b), IIC_iMAC64,
1271 "smlal", "\t$ldst, $hdst, $a, $b", []>;
1273 def UMLAL : AsMul1I<0b0000101, (outs GPR:$ldst, GPR:$hdst),
1274 (ins GPR:$a, GPR:$b), IIC_iMAC64,
1275 "umlal", "\t$ldst, $hdst, $a, $b", []>;
1277 def UMAAL : AMul1I <0b0000010, (outs GPR:$ldst, GPR:$hdst),
1278 (ins GPR:$a, GPR:$b), IIC_iMAC64,
1279 "umaal", "\t$ldst, $hdst, $a, $b", []>,
1280 Requires<[IsARM, HasV6]>;
1281 } // neverHasSideEffects
1283 // Most significant word multiply
1284 def SMMUL : AMul2I <0b0111010, (outs GPR:$dst), (ins GPR:$a, GPR:$b),
1285 IIC_iMUL32, "smmul", "\t$dst, $a, $b",
1286 [(set GPR:$dst, (mulhs GPR:$a, GPR:$b))]>,
1287 Requires<[IsARM, HasV6]> {
1288 let Inst{7-4} = 0b0001;
1289 let Inst{15-12} = 0b1111;
1292 def SMMLA : AMul2I <0b0111010, (outs GPR:$dst), (ins GPR:$a, GPR:$b, GPR:$c),
1293 IIC_iMAC32, "smmla", "\t$dst, $a, $b, $c",
1294 [(set GPR:$dst, (add (mulhs GPR:$a, GPR:$b), GPR:$c))]>,
1295 Requires<[IsARM, HasV6]> {
1296 let Inst{7-4} = 0b0001;
1300 def SMMLS : AMul2I <0b0111010, (outs GPR:$dst), (ins GPR:$a, GPR:$b, GPR:$c),
1301 IIC_iMAC32, "smmls", "\t$dst, $a, $b, $c",
1302 [(set GPR:$dst, (sub GPR:$c, (mulhs GPR:$a, GPR:$b)))]>,
1303 Requires<[IsARM, HasV6]> {
1304 let Inst{7-4} = 0b1101;
1307 multiclass AI_smul<string opc, PatFrag opnode> {
1308 def BB : AMulxyI<0b0001011, (outs GPR:$dst), (ins GPR:$a, GPR:$b),
1309 IIC_iMUL32, !strconcat(opc, "bb"), "\t$dst, $a, $b",
1310 [(set GPR:$dst, (opnode (sext_inreg GPR:$a, i16),
1311 (sext_inreg GPR:$b, i16)))]>,
1312 Requires<[IsARM, HasV5TE]> {
1317 def BT : AMulxyI<0b0001011, (outs GPR:$dst), (ins GPR:$a, GPR:$b),
1318 IIC_iMUL32, !strconcat(opc, "bt"), "\t$dst, $a, $b",
1319 [(set GPR:$dst, (opnode (sext_inreg GPR:$a, i16),
1320 (sra GPR:$b, (i32 16))))]>,
1321 Requires<[IsARM, HasV5TE]> {
1326 def TB : AMulxyI<0b0001011, (outs GPR:$dst), (ins GPR:$a, GPR:$b),
1327 IIC_iMUL32, !strconcat(opc, "tb"), "\t$dst, $a, $b",
1328 [(set GPR:$dst, (opnode (sra GPR:$a, (i32 16)),
1329 (sext_inreg GPR:$b, i16)))]>,
1330 Requires<[IsARM, HasV5TE]> {
1335 def TT : AMulxyI<0b0001011, (outs GPR:$dst), (ins GPR:$a, GPR:$b),
1336 IIC_iMUL32, !strconcat(opc, "tt"), "\t$dst, $a, $b",
1337 [(set GPR:$dst, (opnode (sra GPR:$a, (i32 16)),
1338 (sra GPR:$b, (i32 16))))]>,
1339 Requires<[IsARM, HasV5TE]> {
1344 def WB : AMulxyI<0b0001001, (outs GPR:$dst), (ins GPR:$a, GPR:$b),
1345 IIC_iMUL16, !strconcat(opc, "wb"), "\t$dst, $a, $b",
1346 [(set GPR:$dst, (sra (opnode GPR:$a,
1347 (sext_inreg GPR:$b, i16)), (i32 16)))]>,
1348 Requires<[IsARM, HasV5TE]> {
1353 def WT : AMulxyI<0b0001001, (outs GPR:$dst), (ins GPR:$a, GPR:$b),
1354 IIC_iMUL16, !strconcat(opc, "wt"), "\t$dst, $a, $b",
1355 [(set GPR:$dst, (sra (opnode GPR:$a,
1356 (sra GPR:$b, (i32 16))), (i32 16)))]>,
1357 Requires<[IsARM, HasV5TE]> {
1364 multiclass AI_smla<string opc, PatFrag opnode> {
1365 def BB : AMulxyI<0b0001000, (outs GPR:$dst), (ins GPR:$a, GPR:$b, GPR:$acc),
1366 IIC_iMAC16, !strconcat(opc, "bb"), "\t$dst, $a, $b, $acc",
1367 [(set GPR:$dst, (add GPR:$acc,
1368 (opnode (sext_inreg GPR:$a, i16),
1369 (sext_inreg GPR:$b, i16))))]>,
1370 Requires<[IsARM, HasV5TE]> {
1375 def BT : AMulxyI<0b0001000, (outs GPR:$dst), (ins GPR:$a, GPR:$b, GPR:$acc),
1376 IIC_iMAC16, !strconcat(opc, "bt"), "\t$dst, $a, $b, $acc",
1377 [(set GPR:$dst, (add GPR:$acc, (opnode (sext_inreg GPR:$a, i16),
1378 (sra GPR:$b, (i32 16)))))]>,
1379 Requires<[IsARM, HasV5TE]> {
1384 def TB : AMulxyI<0b0001000, (outs GPR:$dst), (ins GPR:$a, GPR:$b, GPR:$acc),
1385 IIC_iMAC16, !strconcat(opc, "tb"), "\t$dst, $a, $b, $acc",
1386 [(set GPR:$dst, (add GPR:$acc, (opnode (sra GPR:$a, (i32 16)),
1387 (sext_inreg GPR:$b, i16))))]>,
1388 Requires<[IsARM, HasV5TE]> {
1393 def TT : AMulxyI<0b0001000, (outs GPR:$dst), (ins GPR:$a, GPR:$b, GPR:$acc),
1394 IIC_iMAC16, !strconcat(opc, "tt"), "\t$dst, $a, $b, $acc",
1395 [(set GPR:$dst, (add GPR:$acc, (opnode (sra GPR:$a, (i32 16)),
1396 (sra GPR:$b, (i32 16)))))]>,
1397 Requires<[IsARM, HasV5TE]> {
1402 def WB : AMulxyI<0b0001001, (outs GPR:$dst), (ins GPR:$a, GPR:$b, GPR:$acc),
1403 IIC_iMAC16, !strconcat(opc, "wb"), "\t$dst, $a, $b, $acc",
1404 [(set GPR:$dst, (add GPR:$acc, (sra (opnode GPR:$a,
1405 (sext_inreg GPR:$b, i16)), (i32 16))))]>,
1406 Requires<[IsARM, HasV5TE]> {
1411 def WT : AMulxyI<0b0001001, (outs GPR:$dst), (ins GPR:$a, GPR:$b, GPR:$acc),
1412 IIC_iMAC16, !strconcat(opc, "wt"), "\t$dst, $a, $b, $acc",
1413 [(set GPR:$dst, (add GPR:$acc, (sra (opnode GPR:$a,
1414 (sra GPR:$b, (i32 16))), (i32 16))))]>,
1415 Requires<[IsARM, HasV5TE]> {
1421 defm SMUL : AI_smul<"smul", BinOpFrag<(mul node:$LHS, node:$RHS)>>;
1422 defm SMLA : AI_smla<"smla", BinOpFrag<(mul node:$LHS, node:$RHS)>>;
1424 // TODO: Halfword multiple accumulate long: SMLAL<x><y>
1425 // TODO: Dual halfword multiple: SMUAD, SMUSD, SMLAD, SMLSD, SMLALD, SMLSLD
1427 //===----------------------------------------------------------------------===//
1428 // Misc. Arithmetic Instructions.
1431 def CLZ : AMiscA1I<0b000010110, (outs GPR:$dst), (ins GPR:$src), IIC_iUNAr,
1432 "clz", "\t$dst, $src",
1433 [(set GPR:$dst, (ctlz GPR:$src))]>, Requires<[IsARM, HasV5T]> {
1434 let Inst{7-4} = 0b0001;
1435 let Inst{11-8} = 0b1111;
1436 let Inst{19-16} = 0b1111;
1439 def REV : AMiscA1I<0b01101011, (outs GPR:$dst), (ins GPR:$src), IIC_iUNAr,
1440 "rev", "\t$dst, $src",
1441 [(set GPR:$dst, (bswap GPR:$src))]>, Requires<[IsARM, HasV6]> {
1442 let Inst{7-4} = 0b0011;
1443 let Inst{11-8} = 0b1111;
1444 let Inst{19-16} = 0b1111;
1447 def REV16 : AMiscA1I<0b01101011, (outs GPR:$dst), (ins GPR:$src), IIC_iUNAr,
1448 "rev16", "\t$dst, $src",
1450 (or (and (srl GPR:$src, (i32 8)), 0xFF),
1451 (or (and (shl GPR:$src, (i32 8)), 0xFF00),
1452 (or (and (srl GPR:$src, (i32 8)), 0xFF0000),
1453 (and (shl GPR:$src, (i32 8)), 0xFF000000)))))]>,
1454 Requires<[IsARM, HasV6]> {
1455 let Inst{7-4} = 0b1011;
1456 let Inst{11-8} = 0b1111;
1457 let Inst{19-16} = 0b1111;
1460 def REVSH : AMiscA1I<0b01101111, (outs GPR:$dst), (ins GPR:$src), IIC_iUNAr,
1461 "revsh", "\t$dst, $src",
1464 (or (srl (and GPR:$src, 0xFF00), (i32 8)),
1465 (shl GPR:$src, (i32 8))), i16))]>,
1466 Requires<[IsARM, HasV6]> {
1467 let Inst{7-4} = 0b1011;
1468 let Inst{11-8} = 0b1111;
1469 let Inst{19-16} = 0b1111;
1472 def PKHBT : AMiscA1I<0b01101000, (outs GPR:$dst),
1473 (ins GPR:$src1, GPR:$src2, i32imm:$shamt),
1474 IIC_iALUsi, "pkhbt", "\t$dst, $src1, $src2, LSL $shamt",
1475 [(set GPR:$dst, (or (and GPR:$src1, 0xFFFF),
1476 (and (shl GPR:$src2, (i32 imm:$shamt)),
1478 Requires<[IsARM, HasV6]> {
1479 let Inst{6-4} = 0b001;
1482 // Alternate cases for PKHBT where identities eliminate some nodes.
1483 def : ARMV6Pat<(or (and GPR:$src1, 0xFFFF), (and GPR:$src2, 0xFFFF0000)),
1484 (PKHBT GPR:$src1, GPR:$src2, 0)>;
1485 def : ARMV6Pat<(or (and GPR:$src1, 0xFFFF), (shl GPR:$src2, imm16_31:$shamt)),
1486 (PKHBT GPR:$src1, GPR:$src2, imm16_31:$shamt)>;
1489 def PKHTB : AMiscA1I<0b01101000, (outs GPR:$dst),
1490 (ins GPR:$src1, GPR:$src2, i32imm:$shamt),
1491 IIC_iALUsi, "pkhtb", "\t$dst, $src1, $src2, ASR $shamt",
1492 [(set GPR:$dst, (or (and GPR:$src1, 0xFFFF0000),
1493 (and (sra GPR:$src2, imm16_31:$shamt),
1494 0xFFFF)))]>, Requires<[IsARM, HasV6]> {
1495 let Inst{6-4} = 0b101;
1498 // Alternate cases for PKHTB where identities eliminate some nodes. Note that
1499 // a shift amount of 0 is *not legal* here, it is PKHBT instead.
1500 def : ARMV6Pat<(or (and GPR:$src1, 0xFFFF0000), (srl GPR:$src2, (i32 16))),
1501 (PKHTB GPR:$src1, GPR:$src2, 16)>;
1502 def : ARMV6Pat<(or (and GPR:$src1, 0xFFFF0000),
1503 (and (srl GPR:$src2, imm1_15:$shamt), 0xFFFF)),
1504 (PKHTB GPR:$src1, GPR:$src2, imm1_15:$shamt)>;
1506 //===----------------------------------------------------------------------===//
1507 // Comparison Instructions...
1510 defm CMP : AI1_cmp_irs<0b1010, "cmp",
1511 BinOpFrag<(ARMcmp node:$LHS, node:$RHS)>>;
1512 defm CMN : AI1_cmp_irs<0b1011, "cmn",
1513 BinOpFrag<(ARMcmp node:$LHS,(ineg node:$RHS))>>;
1515 // Note that TST/TEQ don't set all the same flags that CMP does!
1516 defm TST : AI1_cmp_irs<0b1000, "tst",
1517 BinOpFrag<(ARMcmpZ (and node:$LHS, node:$RHS), 0)>, 1>;
1518 defm TEQ : AI1_cmp_irs<0b1001, "teq",
1519 BinOpFrag<(ARMcmpZ (xor node:$LHS, node:$RHS), 0)>, 1>;
1521 defm CMPz : AI1_cmp_irs<0b1010, "cmp",
1522 BinOpFrag<(ARMcmpZ node:$LHS, node:$RHS)>>;
1523 defm CMNz : AI1_cmp_irs<0b1011, "cmn",
1524 BinOpFrag<(ARMcmpZ node:$LHS,(ineg node:$RHS))>>;
1526 def : ARMPat<(ARMcmp GPR:$src, so_imm_neg:$imm),
1527 (CMNri GPR:$src, so_imm_neg:$imm)>;
1529 def : ARMPat<(ARMcmpZ GPR:$src, so_imm_neg:$imm),
1530 (CMNri GPR:$src, so_imm_neg:$imm)>;
1533 // Conditional moves
1534 // FIXME: should be able to write a pattern for ARMcmov, but can't use
1535 // a two-value operand where a dag node expects two operands. :(
1536 def MOVCCr : AI1<0b1101, (outs GPR:$dst), (ins GPR:$false, GPR:$true), DPFrm,
1537 IIC_iCMOVr, "mov", "\t$dst, $true",
1538 [/*(set GPR:$dst, (ARMcmov GPR:$false, GPR:$true, imm:$cc, CCR:$ccr))*/]>,
1539 RegConstraint<"$false = $dst">, UnaryDP {
1540 let Inst{11-4} = 0b00000000;
1544 def MOVCCs : AI1<0b1101, (outs GPR:$dst),
1545 (ins GPR:$false, so_reg:$true), DPSoRegFrm, IIC_iCMOVsr,
1546 "mov", "\t$dst, $true",
1547 [/*(set GPR:$dst, (ARMcmov GPR:$false, so_reg:$true, imm:$cc, CCR:$ccr))*/]>,
1548 RegConstraint<"$false = $dst">, UnaryDP {
1552 def MOVCCi : AI1<0b1101, (outs GPR:$dst),
1553 (ins GPR:$false, so_imm:$true), DPFrm, IIC_iCMOVi,
1554 "mov", "\t$dst, $true",
1555 [/*(set GPR:$dst, (ARMcmov GPR:$false, so_imm:$true, imm:$cc, CCR:$ccr))*/]>,
1556 RegConstraint<"$false = $dst">, UnaryDP {
1561 //===----------------------------------------------------------------------===//
1565 // __aeabi_read_tp preserves the registers r1-r3.
1567 Defs = [R0, R12, LR, CPSR] in {
1568 def TPsoft : ABXI<0b1011, (outs), (ins), IIC_Br,
1569 "bl\t__aeabi_read_tp",
1570 [(set R0, ARMthread_pointer)]>;
1573 //===----------------------------------------------------------------------===//
1574 // SJLJ Exception handling intrinsics
1575 // eh_sjlj_setjmp() is an instruction sequence to store the return
1576 // address and save #0 in R0 for the non-longjmp case.
1577 // Since by its nature we may be coming from some other function to get
1578 // here, and we're using the stack frame for the containing function to
1579 // save/restore registers, we can't keep anything live in regs across
1580 // the eh_sjlj_setjmp(), else it will almost certainly have been tromped upon
1581 // when we get here from a longjmp(). We force everthing out of registers
1582 // except for our own input by listing the relevant registers in Defs. By
1583 // doing so, we also cause the prologue/epilogue code to actively preserve
1584 // all of the callee-saved resgisters, which is exactly what we want.
1586 [ R0, R1, R2, R3, R4, R5, R6, R7, R8, R9, R10, R11, R12, LR, D0,
1587 D1, D2, D3, D4, D5, D6, D7, D8, D9, D10, D11, D12, D13, D14, D15,
1588 D16, D17, D18, D19, D20, D21, D22, D23, D24, D25, D26, D27, D28, D29, D30,
1590 def Int_eh_sjlj_setjmp : XI<(outs), (ins GPR:$src),
1591 AddrModeNone, SizeSpecial, IndexModeNone,
1592 Pseudo, NoItinerary,
1593 "str\tsp, [$src, #+8] @ eh_setjmp begin\n\t"
1594 "add\tr12, pc, #8\n\t"
1595 "str\tr12, [$src, #+4]\n\t"
1597 "add\tpc, pc, #0\n\t"
1598 "mov\tr0, #1 @ eh_setjmp end", "",
1599 [(set R0, (ARMeh_sjlj_setjmp GPR:$src))]>;
1602 //===----------------------------------------------------------------------===//
1603 // Non-Instruction Patterns
1606 // ConstantPool, GlobalAddress, and JumpTable
1607 def : ARMPat<(ARMWrapper tglobaladdr :$dst), (LEApcrel tglobaladdr :$dst)>;
1608 def : ARMPat<(ARMWrapper tconstpool :$dst), (LEApcrel tconstpool :$dst)>;
1609 def : ARMPat<(ARMWrapperJT tjumptable:$dst, imm:$id),
1610 (LEApcrelJT tjumptable:$dst, imm:$id)>;
1612 // Large immediate handling.
1614 // Two piece so_imms.
1615 let isReMaterializable = 1 in
1616 def MOVi2pieces : AI1x2<(outs GPR:$dst), (ins so_imm2part:$src),
1618 "mov", "\t$dst, $src",
1619 [(set GPR:$dst, so_imm2part:$src)]>,
1620 Requires<[IsARM, NoV6T2]>;
1622 def : ARMPat<(or GPR:$LHS, so_imm2part:$RHS),
1623 (ORRri (ORRri GPR:$LHS, (so_imm2part_1 imm:$RHS)),
1624 (so_imm2part_2 imm:$RHS))>;
1625 def : ARMPat<(xor GPR:$LHS, so_imm2part:$RHS),
1626 (EORri (EORri GPR:$LHS, (so_imm2part_1 imm:$RHS)),
1627 (so_imm2part_2 imm:$RHS))>;
1628 def : ARMPat<(add GPR:$LHS, so_imm2part:$RHS),
1629 (ADDri (ADDri GPR:$LHS, (so_imm2part_1 imm:$RHS)),
1630 (so_imm2part_2 imm:$RHS))>;
1631 def : ARMPat<(add GPR:$LHS, so_neg_imm2part:$RHS),
1632 (SUBri (SUBri GPR:$LHS, (so_neg_imm2part_1 imm:$RHS)),
1633 (so_neg_imm2part_2 imm:$RHS))>;
1635 // 32-bit immediate using movw + movt.
1636 // This is a single pseudo instruction, the benefit is that it can be remat'd
1637 // as a single unit instead of having to handle reg inputs.
1638 // FIXME: Remove this when we can do generalized remat.
1639 let isReMaterializable = 1 in
1640 def MOVi32imm : AI1x2<(outs GPR:$dst), (ins i32imm:$src), Pseudo, IIC_iMOVi,
1641 "movw", "\t$dst, ${src:lo16}\n\tmovt${p} $dst, ${src:hi16}",
1642 [(set GPR:$dst, (i32 imm:$src))]>,
1643 Requires<[IsARM, HasV6T2]>;
1645 // TODO: add,sub,and, 3-instr forms?
1649 def : ARMPat<(ARMcall texternalsym:$func), (BL texternalsym:$func)>,
1650 Requires<[IsARM, IsNotDarwin]>;
1651 def : ARMPat<(ARMcall texternalsym:$func), (BLr9 texternalsym:$func)>,
1652 Requires<[IsARM, IsDarwin]>;
1654 // zextload i1 -> zextload i8
1655 def : ARMPat<(zextloadi1 addrmode2:$addr), (LDRB addrmode2:$addr)>;
1657 // extload -> zextload
1658 def : ARMPat<(extloadi1 addrmode2:$addr), (LDRB addrmode2:$addr)>;
1659 def : ARMPat<(extloadi8 addrmode2:$addr), (LDRB addrmode2:$addr)>;
1660 def : ARMPat<(extloadi16 addrmode3:$addr), (LDRH addrmode3:$addr)>;
1662 def : ARMPat<(extloadi8 addrmodepc:$addr), (PICLDRB addrmodepc:$addr)>;
1663 def : ARMPat<(extloadi16 addrmodepc:$addr), (PICLDRH addrmodepc:$addr)>;
1666 def : ARMV5TEPat<(mul (sra (shl GPR:$a, (i32 16)), (i32 16)),
1667 (sra (shl GPR:$b, (i32 16)), (i32 16))),
1668 (SMULBB GPR:$a, GPR:$b)>;
1669 def : ARMV5TEPat<(mul sext_16_node:$a, sext_16_node:$b),
1670 (SMULBB GPR:$a, GPR:$b)>;
1671 def : ARMV5TEPat<(mul (sra (shl GPR:$a, (i32 16)), (i32 16)),
1672 (sra GPR:$b, (i32 16))),
1673 (SMULBT GPR:$a, GPR:$b)>;
1674 def : ARMV5TEPat<(mul sext_16_node:$a, (sra GPR:$b, (i32 16))),
1675 (SMULBT GPR:$a, GPR:$b)>;
1676 def : ARMV5TEPat<(mul (sra GPR:$a, (i32 16)),
1677 (sra (shl GPR:$b, (i32 16)), (i32 16))),
1678 (SMULTB GPR:$a, GPR:$b)>;
1679 def : ARMV5TEPat<(mul (sra GPR:$a, (i32 16)), sext_16_node:$b),
1680 (SMULTB GPR:$a, GPR:$b)>;
1681 def : ARMV5TEPat<(sra (mul GPR:$a, (sra (shl GPR:$b, (i32 16)), (i32 16))),
1683 (SMULWB GPR:$a, GPR:$b)>;
1684 def : ARMV5TEPat<(sra (mul GPR:$a, sext_16_node:$b), (i32 16)),
1685 (SMULWB GPR:$a, GPR:$b)>;
1687 def : ARMV5TEPat<(add GPR:$acc,
1688 (mul (sra (shl GPR:$a, (i32 16)), (i32 16)),
1689 (sra (shl GPR:$b, (i32 16)), (i32 16)))),
1690 (SMLABB GPR:$a, GPR:$b, GPR:$acc)>;
1691 def : ARMV5TEPat<(add GPR:$acc,
1692 (mul sext_16_node:$a, sext_16_node:$b)),
1693 (SMLABB GPR:$a, GPR:$b, GPR:$acc)>;
1694 def : ARMV5TEPat<(add GPR:$acc,
1695 (mul (sra (shl GPR:$a, (i32 16)), (i32 16)),
1696 (sra GPR:$b, (i32 16)))),
1697 (SMLABT GPR:$a, GPR:$b, GPR:$acc)>;
1698 def : ARMV5TEPat<(add GPR:$acc,
1699 (mul sext_16_node:$a, (sra GPR:$b, (i32 16)))),
1700 (SMLABT GPR:$a, GPR:$b, GPR:$acc)>;
1701 def : ARMV5TEPat<(add GPR:$acc,
1702 (mul (sra GPR:$a, (i32 16)),
1703 (sra (shl GPR:$b, (i32 16)), (i32 16)))),
1704 (SMLATB GPR:$a, GPR:$b, GPR:$acc)>;
1705 def : ARMV5TEPat<(add GPR:$acc,
1706 (mul (sra GPR:$a, (i32 16)), sext_16_node:$b)),
1707 (SMLATB GPR:$a, GPR:$b, GPR:$acc)>;
1708 def : ARMV5TEPat<(add GPR:$acc,
1709 (sra (mul GPR:$a, (sra (shl GPR:$b, (i32 16)), (i32 16))),
1711 (SMLAWB GPR:$a, GPR:$b, GPR:$acc)>;
1712 def : ARMV5TEPat<(add GPR:$acc,
1713 (sra (mul GPR:$a, sext_16_node:$b), (i32 16))),
1714 (SMLAWB GPR:$a, GPR:$b, GPR:$acc)>;
1716 //===----------------------------------------------------------------------===//
1720 include "ARMInstrThumb.td"
1722 //===----------------------------------------------------------------------===//
1726 include "ARMInstrThumb2.td"
1728 //===----------------------------------------------------------------------===//
1729 // Floating Point Support
1732 include "ARMInstrVFP.td"
1734 //===----------------------------------------------------------------------===//
1735 // Advanced SIMD (NEON) Support
1738 include "ARMInstrNEON.td"