1 //===- ARMInstrInfo.td - Target Description for ARM Target -*- tablegen -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file describes the ARM instructions in TableGen format.
12 //===----------------------------------------------------------------------===//
14 //===----------------------------------------------------------------------===//
15 // ARM specific DAG Nodes.
19 def SDT_ARMCallSeqStart : SDCallSeqStart<[ SDTCisVT<0, i32> ]>;
20 def SDT_ARMCallSeqEnd : SDCallSeqEnd<[ SDTCisVT<0, i32>, SDTCisVT<1, i32> ]>;
21 def SDT_ARMStructByVal : SDTypeProfile<0, 4,
22 [SDTCisVT<0, i32>, SDTCisVT<1, i32>,
23 SDTCisVT<2, i32>, SDTCisVT<3, i32>]>;
25 def SDT_ARMSaveCallPC : SDTypeProfile<0, 1, []>;
27 def SDT_ARMcall : SDTypeProfile<0, -1, [SDTCisPtrTy<0>]>;
29 def SDT_ARMCMov : SDTypeProfile<1, 3,
30 [SDTCisSameAs<0, 1>, SDTCisSameAs<0, 2>,
33 def SDT_ARMBrcond : SDTypeProfile<0, 2,
34 [SDTCisVT<0, OtherVT>, SDTCisVT<1, i32>]>;
36 def SDT_ARMBrJT : SDTypeProfile<0, 3,
37 [SDTCisPtrTy<0>, SDTCisVT<1, i32>,
40 def SDT_ARMBr2JT : SDTypeProfile<0, 4,
41 [SDTCisPtrTy<0>, SDTCisVT<1, i32>,
42 SDTCisVT<2, i32>, SDTCisVT<3, i32>]>;
44 def SDT_ARMBCC_i64 : SDTypeProfile<0, 6,
46 SDTCisVT<1, i32>, SDTCisVT<2, i32>,
47 SDTCisVT<3, i32>, SDTCisVT<4, i32>,
48 SDTCisVT<5, OtherVT>]>;
50 def SDT_ARMAnd : SDTypeProfile<1, 2,
51 [SDTCisVT<0, i32>, SDTCisVT<1, i32>,
54 def SDT_ARMCmp : SDTypeProfile<0, 2, [SDTCisSameAs<0, 1>]>;
56 def SDT_ARMPICAdd : SDTypeProfile<1, 2, [SDTCisSameAs<0, 1>,
57 SDTCisPtrTy<1>, SDTCisVT<2, i32>]>;
59 def SDT_ARMThreadPointer : SDTypeProfile<1, 0, [SDTCisPtrTy<0>]>;
60 def SDT_ARMEH_SJLJ_Setjmp : SDTypeProfile<1, 2, [SDTCisInt<0>, SDTCisPtrTy<1>,
62 def SDT_ARMEH_SJLJ_Longjmp: SDTypeProfile<0, 2, [SDTCisPtrTy<0>, SDTCisInt<1>]>;
64 def SDT_ARMMEMBARRIER : SDTypeProfile<0, 1, [SDTCisInt<0>]>;
66 def SDT_ARMPREFETCH : SDTypeProfile<0, 3, [SDTCisPtrTy<0>, SDTCisSameAs<1, 2>,
69 def SDT_ARMTCRET : SDTypeProfile<0, 1, [SDTCisPtrTy<0>]>;
71 def SDT_ARMBFI : SDTypeProfile<1, 3, [SDTCisVT<0, i32>, SDTCisVT<1, i32>,
72 SDTCisVT<2, i32>, SDTCisVT<3, i32>]>;
74 def SDTBinaryArithWithFlags : SDTypeProfile<2, 2,
77 SDTCisInt<0>, SDTCisVT<1, i32>]>;
79 // SDTBinaryArithWithFlagsInOut - RES1, CPSR = op LHS, RHS, CPSR
80 def SDTBinaryArithWithFlagsInOut : SDTypeProfile<2, 3,
87 def SDT_ARM64bitmlal : SDTypeProfile<2,4, [ SDTCisVT<0, i32>, SDTCisVT<1, i32>,
88 SDTCisVT<2, i32>, SDTCisVT<3, i32>,
89 SDTCisVT<4, i32>, SDTCisVT<5, i32> ] >;
90 def ARMUmlal : SDNode<"ARMISD::UMLAL", SDT_ARM64bitmlal>;
91 def ARMSmlal : SDNode<"ARMISD::SMLAL", SDT_ARM64bitmlal>;
94 def ARMWrapper : SDNode<"ARMISD::Wrapper", SDTIntUnaryOp>;
95 def ARMWrapperDYN : SDNode<"ARMISD::WrapperDYN", SDTIntUnaryOp>;
96 def ARMWrapperPIC : SDNode<"ARMISD::WrapperPIC", SDTIntUnaryOp>;
97 def ARMWrapperJT : SDNode<"ARMISD::WrapperJT", SDTIntBinOp>;
99 def ARMcallseq_start : SDNode<"ISD::CALLSEQ_START", SDT_ARMCallSeqStart,
100 [SDNPHasChain, SDNPSideEffect, SDNPOutGlue]>;
101 def ARMcallseq_end : SDNode<"ISD::CALLSEQ_END", SDT_ARMCallSeqEnd,
102 [SDNPHasChain, SDNPSideEffect,
103 SDNPOptInGlue, SDNPOutGlue]>;
104 def ARMcopystructbyval : SDNode<"ARMISD::COPY_STRUCT_BYVAL" ,
106 [SDNPHasChain, SDNPInGlue, SDNPOutGlue,
107 SDNPMayStore, SDNPMayLoad]>;
109 def ARMcall : SDNode<"ARMISD::CALL", SDT_ARMcall,
110 [SDNPHasChain, SDNPOptInGlue, SDNPOutGlue,
112 def ARMcall_pred : SDNode<"ARMISD::CALL_PRED", SDT_ARMcall,
113 [SDNPHasChain, SDNPOptInGlue, SDNPOutGlue,
115 def ARMcall_nolink : SDNode<"ARMISD::CALL_NOLINK", SDT_ARMcall,
116 [SDNPHasChain, SDNPOptInGlue, SDNPOutGlue,
119 def ARMretflag : SDNode<"ARMISD::RET_FLAG", SDTNone,
120 [SDNPHasChain, SDNPOptInGlue, SDNPVariadic]>;
122 def ARMcmov : SDNode<"ARMISD::CMOV", SDT_ARMCMov,
125 def ARMbrcond : SDNode<"ARMISD::BRCOND", SDT_ARMBrcond,
126 [SDNPHasChain, SDNPInGlue, SDNPOutGlue]>;
128 def ARMbrjt : SDNode<"ARMISD::BR_JT", SDT_ARMBrJT,
130 def ARMbr2jt : SDNode<"ARMISD::BR2_JT", SDT_ARMBr2JT,
133 def ARMBcci64 : SDNode<"ARMISD::BCC_i64", SDT_ARMBCC_i64,
136 def ARMcmp : SDNode<"ARMISD::CMP", SDT_ARMCmp,
139 def ARMcmn : SDNode<"ARMISD::CMN", SDT_ARMCmp,
142 def ARMcmpZ : SDNode<"ARMISD::CMPZ", SDT_ARMCmp,
143 [SDNPOutGlue, SDNPCommutative]>;
145 def ARMpic_add : SDNode<"ARMISD::PIC_ADD", SDT_ARMPICAdd>;
147 def ARMsrl_flag : SDNode<"ARMISD::SRL_FLAG", SDTIntUnaryOp, [SDNPOutGlue]>;
148 def ARMsra_flag : SDNode<"ARMISD::SRA_FLAG", SDTIntUnaryOp, [SDNPOutGlue]>;
149 def ARMrrx : SDNode<"ARMISD::RRX" , SDTIntUnaryOp, [SDNPInGlue ]>;
151 def ARMaddc : SDNode<"ARMISD::ADDC", SDTBinaryArithWithFlags,
153 def ARMsubc : SDNode<"ARMISD::SUBC", SDTBinaryArithWithFlags>;
154 def ARMadde : SDNode<"ARMISD::ADDE", SDTBinaryArithWithFlagsInOut>;
155 def ARMsube : SDNode<"ARMISD::SUBE", SDTBinaryArithWithFlagsInOut>;
157 def ARMthread_pointer: SDNode<"ARMISD::THREAD_POINTER", SDT_ARMThreadPointer>;
158 def ARMeh_sjlj_setjmp: SDNode<"ARMISD::EH_SJLJ_SETJMP",
159 SDT_ARMEH_SJLJ_Setjmp,
160 [SDNPHasChain, SDNPSideEffect]>;
161 def ARMeh_sjlj_longjmp: SDNode<"ARMISD::EH_SJLJ_LONGJMP",
162 SDT_ARMEH_SJLJ_Longjmp,
163 [SDNPHasChain, SDNPSideEffect]>;
165 def ARMMemBarrier : SDNode<"ARMISD::MEMBARRIER", SDT_ARMMEMBARRIER,
166 [SDNPHasChain, SDNPSideEffect]>;
167 def ARMMemBarrierMCR : SDNode<"ARMISD::MEMBARRIER_MCR", SDT_ARMMEMBARRIER,
168 [SDNPHasChain, SDNPSideEffect]>;
169 def ARMPreload : SDNode<"ARMISD::PRELOAD", SDT_ARMPREFETCH,
170 [SDNPHasChain, SDNPMayLoad, SDNPMayStore]>;
172 def ARMrbit : SDNode<"ARMISD::RBIT", SDTIntUnaryOp>;
174 def ARMtcret : SDNode<"ARMISD::TC_RETURN", SDT_ARMTCRET,
175 [SDNPHasChain, SDNPOptInGlue, SDNPVariadic]>;
178 def ARMbfi : SDNode<"ARMISD::BFI", SDT_ARMBFI>;
180 //===----------------------------------------------------------------------===//
181 // ARM Instruction Predicate Definitions.
183 def HasV4T : Predicate<"Subtarget->hasV4TOps()">,
184 AssemblerPredicate<"HasV4TOps", "armv4t">;
185 def NoV4T : Predicate<"!Subtarget->hasV4TOps()">;
186 def HasV5T : Predicate<"Subtarget->hasV5TOps()">;
187 def HasV5TE : Predicate<"Subtarget->hasV5TEOps()">,
188 AssemblerPredicate<"HasV5TEOps", "armv5te">;
189 def HasV6 : Predicate<"Subtarget->hasV6Ops()">,
190 AssemblerPredicate<"HasV6Ops", "armv6">;
191 def NoV6 : Predicate<"!Subtarget->hasV6Ops()">;
192 def HasV6T2 : Predicate<"Subtarget->hasV6T2Ops()">,
193 AssemblerPredicate<"HasV6T2Ops", "armv6t2">;
194 def NoV6T2 : Predicate<"!Subtarget->hasV6T2Ops()">;
195 def HasV7 : Predicate<"Subtarget->hasV7Ops()">,
196 AssemblerPredicate<"HasV7Ops", "armv7">;
197 def NoVFP : Predicate<"!Subtarget->hasVFP2()">;
198 def HasVFP2 : Predicate<"Subtarget->hasVFP2()">,
199 AssemblerPredicate<"FeatureVFP2", "VFP2">;
200 def HasVFP3 : Predicate<"Subtarget->hasVFP3()">,
201 AssemblerPredicate<"FeatureVFP3", "VFP3">;
202 def HasVFP4 : Predicate<"Subtarget->hasVFP4()">,
203 AssemblerPredicate<"FeatureVFP4", "VFP4">;
204 def HasNEON : Predicate<"Subtarget->hasNEON()">,
205 AssemblerPredicate<"FeatureNEON", "NEON">;
206 def HasFP16 : Predicate<"Subtarget->hasFP16()">,
207 AssemblerPredicate<"FeatureFP16","half-float">;
208 def HasDivide : Predicate<"Subtarget->hasDivide()">,
209 AssemblerPredicate<"FeatureHWDiv", "divide">;
210 def HasDivideInARM : Predicate<"Subtarget->hasDivideInARMMode()">,
211 AssemblerPredicate<"FeatureHWDivARM">;
212 def HasT2ExtractPack : Predicate<"Subtarget->hasT2ExtractPack()">,
213 AssemblerPredicate<"FeatureT2XtPk",
215 def HasThumb2DSP : Predicate<"Subtarget->hasThumb2DSP()">,
216 AssemblerPredicate<"FeatureDSPThumb2",
218 def HasDB : Predicate<"Subtarget->hasDataBarrier()">,
219 AssemblerPredicate<"FeatureDB",
221 def HasMP : Predicate<"Subtarget->hasMPExtension()">,
222 AssemblerPredicate<"FeatureMP",
224 def UseNEONForFP : Predicate<"Subtarget->useNEONForSinglePrecisionFP()">;
225 def DontUseNEONForFP : Predicate<"!Subtarget->useNEONForSinglePrecisionFP()">;
226 def IsThumb : Predicate<"Subtarget->isThumb()">,
227 AssemblerPredicate<"ModeThumb", "thumb">;
228 def IsThumb1Only : Predicate<"Subtarget->isThumb1Only()">;
229 def IsThumb2 : Predicate<"Subtarget->isThumb2()">,
230 AssemblerPredicate<"ModeThumb,FeatureThumb2",
232 def IsMClass : Predicate<"Subtarget->isMClass()">,
233 AssemblerPredicate<"FeatureMClass", "armv7m">;
234 def IsARClass : Predicate<"!Subtarget->isMClass()">,
235 AssemblerPredicate<"!FeatureMClass",
237 def IsARM : Predicate<"!Subtarget->isThumb()">,
238 AssemblerPredicate<"!ModeThumb", "arm-mode">;
239 def IsIOS : Predicate<"Subtarget->isTargetIOS()">;
240 def IsNotIOS : Predicate<"!Subtarget->isTargetIOS()">;
241 def IsNaCl : Predicate<"Subtarget->isTargetNaCl()">;
242 def UseNaClTrap : Predicate<"Subtarget->useNaClTrap()">,
243 AssemblerPredicate<"FeatureNaClTrap", "NaCl">;
244 def DontUseNaClTrap : Predicate<"!Subtarget->useNaClTrap()">;
246 // FIXME: Eventually this will be just "hasV6T2Ops".
247 def UseMovt : Predicate<"Subtarget->useMovt()">;
248 def DontUseMovt : Predicate<"!Subtarget->useMovt()">;
249 def UseFPVMLx : Predicate<"Subtarget->useFPVMLx()">;
250 def UseMulOps : Predicate<"Subtarget->useMulOps()">;
252 // Prefer fused MAC for fp mul + add over fp VMLA / VMLS if they are available.
253 // But only select them if more precision in FP computation is allowed.
254 // Do not use them for Darwin platforms.
255 def UseFusedMAC : Predicate<"(TM.Options.AllowFPOpFusion =="
256 " FPOpFusion::Fast) && "
257 "!Subtarget->isTargetDarwin()">;
258 def DontUseFusedMAC : Predicate<"!Subtarget->hasVFP4() || "
259 "Subtarget->isTargetDarwin()">;
261 // VGETLNi32 is microcoded on Swift - prefer VMOV.
262 def HasFastVGETLNi32 : Predicate<"!Subtarget->isSwift()">;
263 def HasSlowVGETLNi32 : Predicate<"Subtarget->isSwift()">;
265 // VDUP.32 is microcoded on Swift - prefer VMOV.
266 def HasFastVDUP32 : Predicate<"!Subtarget->isSwift()">;
267 def HasSlowVDUP32 : Predicate<"Subtarget->isSwift()">;
269 // Cortex-A9 prefers VMOVSR to VMOVDRR even when using NEON for scalar FP, as
270 // this allows more effective execution domain optimization. See
271 // setExecutionDomain().
272 def UseVMOVSR : Predicate<"Subtarget->isCortexA9() || !Subtarget->useNEONForSinglePrecisionFP()">;
273 def DontUseVMOVSR : Predicate<"!Subtarget->isCortexA9() && Subtarget->useNEONForSinglePrecisionFP()">;
275 def IsLE : Predicate<"TLI.isLittleEndian()">;
276 def IsBE : Predicate<"TLI.isBigEndian()">;
278 //===----------------------------------------------------------------------===//
279 // ARM Flag Definitions.
281 class RegConstraint<string C> {
282 string Constraints = C;
285 //===----------------------------------------------------------------------===//
286 // ARM specific transformation functions and pattern fragments.
289 // imm_neg_XFORM - Return the negation of an i32 immediate value.
290 def imm_neg_XFORM : SDNodeXForm<imm, [{
291 return CurDAG->getTargetConstant(-(int)N->getZExtValue(), MVT::i32);
294 // imm_not_XFORM - Return the complement of a i32 immediate value.
295 def imm_not_XFORM : SDNodeXForm<imm, [{
296 return CurDAG->getTargetConstant(~(int)N->getZExtValue(), MVT::i32);
299 /// imm16_31 predicate - True if the 32-bit immediate is in the range [16,31].
300 def imm16_31 : ImmLeaf<i32, [{
301 return (int32_t)Imm >= 16 && (int32_t)Imm < 32;
304 def so_imm_neg_asmoperand : AsmOperandClass { let Name = "ARMSOImmNeg"; }
305 def so_imm_neg : Operand<i32>, PatLeaf<(imm), [{
306 unsigned Value = -(unsigned)N->getZExtValue();
307 return Value && ARM_AM::getSOImmVal(Value) != -1;
309 let ParserMatchClass = so_imm_neg_asmoperand;
312 // Note: this pattern doesn't require an encoder method and such, as it's
313 // only used on aliases (Pat<> and InstAlias<>). The actual encoding
314 // is handled by the destination instructions, which use so_imm.
315 def so_imm_not_asmoperand : AsmOperandClass { let Name = "ARMSOImmNot"; }
316 def so_imm_not : Operand<i32>, PatLeaf<(imm), [{
317 return ARM_AM::getSOImmVal(~(uint32_t)N->getZExtValue()) != -1;
319 let ParserMatchClass = so_imm_not_asmoperand;
322 // sext_16_node predicate - True if the SDNode is sign-extended 16 or more bits.
323 def sext_16_node : PatLeaf<(i32 GPR:$a), [{
324 return CurDAG->ComputeNumSignBits(SDValue(N,0)) >= 17;
327 /// Split a 32-bit immediate into two 16 bit parts.
328 def hi16 : SDNodeXForm<imm, [{
329 return CurDAG->getTargetConstant((uint32_t)N->getZExtValue() >> 16, MVT::i32);
332 def lo16AllZero : PatLeaf<(i32 imm), [{
333 // Returns true if all low 16-bits are 0.
334 return (((uint32_t)N->getZExtValue()) & 0xFFFFUL) == 0;
337 class BinOpWithFlagFrag<dag res> :
338 PatFrag<(ops node:$LHS, node:$RHS, node:$FLAG), res>;
339 class BinOpFrag<dag res> : PatFrag<(ops node:$LHS, node:$RHS), res>;
340 class UnOpFrag <dag res> : PatFrag<(ops node:$Src), res>;
342 // An 'and' node with a single use.
343 def and_su : PatFrag<(ops node:$lhs, node:$rhs), (and node:$lhs, node:$rhs), [{
344 return N->hasOneUse();
347 // An 'xor' node with a single use.
348 def xor_su : PatFrag<(ops node:$lhs, node:$rhs), (xor node:$lhs, node:$rhs), [{
349 return N->hasOneUse();
352 // An 'fmul' node with a single use.
353 def fmul_su : PatFrag<(ops node:$lhs, node:$rhs), (fmul node:$lhs, node:$rhs),[{
354 return N->hasOneUse();
357 // An 'fadd' node which checks for single non-hazardous use.
358 def fadd_mlx : PatFrag<(ops node:$lhs, node:$rhs),(fadd node:$lhs, node:$rhs),[{
359 return hasNoVMLxHazardUse(N);
362 // An 'fsub' node which checks for single non-hazardous use.
363 def fsub_mlx : PatFrag<(ops node:$lhs, node:$rhs),(fsub node:$lhs, node:$rhs),[{
364 return hasNoVMLxHazardUse(N);
367 //===----------------------------------------------------------------------===//
368 // Operand Definitions.
371 // Immediate operands with a shared generic asm render method.
372 class ImmAsmOperand : AsmOperandClass { let RenderMethod = "addImmOperands"; }
375 // FIXME: rename brtarget to t2_brtarget
376 def brtarget : Operand<OtherVT> {
377 let EncoderMethod = "getBranchTargetOpValue";
378 let OperandType = "OPERAND_PCREL";
379 let DecoderMethod = "DecodeT2BROperand";
382 // FIXME: get rid of this one?
383 def uncondbrtarget : Operand<OtherVT> {
384 let EncoderMethod = "getUnconditionalBranchTargetOpValue";
385 let OperandType = "OPERAND_PCREL";
388 // Branch target for ARM. Handles conditional/unconditional
389 def br_target : Operand<OtherVT> {
390 let EncoderMethod = "getARMBranchTargetOpValue";
391 let OperandType = "OPERAND_PCREL";
395 // FIXME: rename bltarget to t2_bl_target?
396 def bltarget : Operand<i32> {
397 // Encoded the same as branch targets.
398 let EncoderMethod = "getBranchTargetOpValue";
399 let OperandType = "OPERAND_PCREL";
402 // Call target for ARM. Handles conditional/unconditional
403 // FIXME: rename bl_target to t2_bltarget?
404 def bl_target : Operand<i32> {
405 let EncoderMethod = "getARMBLTargetOpValue";
406 let OperandType = "OPERAND_PCREL";
409 def blx_target : Operand<i32> {
410 let EncoderMethod = "getARMBLXTargetOpValue";
411 let OperandType = "OPERAND_PCREL";
414 // A list of registers separated by comma. Used by load/store multiple.
415 def RegListAsmOperand : AsmOperandClass { let Name = "RegList"; }
416 def reglist : Operand<i32> {
417 let EncoderMethod = "getRegisterListOpValue";
418 let ParserMatchClass = RegListAsmOperand;
419 let PrintMethod = "printRegisterList";
420 let DecoderMethod = "DecodeRegListOperand";
423 def GPRPairOp : RegisterOperand<GPRPair, "printGPRPairOperand">;
425 def DPRRegListAsmOperand : AsmOperandClass { let Name = "DPRRegList"; }
426 def dpr_reglist : Operand<i32> {
427 let EncoderMethod = "getRegisterListOpValue";
428 let ParserMatchClass = DPRRegListAsmOperand;
429 let PrintMethod = "printRegisterList";
430 let DecoderMethod = "DecodeDPRRegListOperand";
433 def SPRRegListAsmOperand : AsmOperandClass { let Name = "SPRRegList"; }
434 def spr_reglist : Operand<i32> {
435 let EncoderMethod = "getRegisterListOpValue";
436 let ParserMatchClass = SPRRegListAsmOperand;
437 let PrintMethod = "printRegisterList";
438 let DecoderMethod = "DecodeSPRRegListOperand";
441 // An operand for the CONSTPOOL_ENTRY pseudo-instruction.
442 def cpinst_operand : Operand<i32> {
443 let PrintMethod = "printCPInstOperand";
447 def pclabel : Operand<i32> {
448 let PrintMethod = "printPCLabel";
451 // ADR instruction labels.
452 def AdrLabelAsmOperand : AsmOperandClass { let Name = "AdrLabel"; }
453 def adrlabel : Operand<i32> {
454 let EncoderMethod = "getAdrLabelOpValue";
455 let ParserMatchClass = AdrLabelAsmOperand;
456 let PrintMethod = "printAdrLabelOperand";
459 def neon_vcvt_imm32 : Operand<i32> {
460 let EncoderMethod = "getNEONVcvtImm32OpValue";
461 let DecoderMethod = "DecodeVCVTImmOperand";
464 // rot_imm: An integer that encodes a rotate amount. Must be 8, 16, or 24.
465 def rot_imm_XFORM: SDNodeXForm<imm, [{
466 switch (N->getZExtValue()){
468 case 0: return CurDAG->getTargetConstant(0, MVT::i32);
469 case 8: return CurDAG->getTargetConstant(1, MVT::i32);
470 case 16: return CurDAG->getTargetConstant(2, MVT::i32);
471 case 24: return CurDAG->getTargetConstant(3, MVT::i32);
474 def RotImmAsmOperand : AsmOperandClass {
476 let ParserMethod = "parseRotImm";
478 def rot_imm : Operand<i32>, PatLeaf<(i32 imm), [{
479 int32_t v = N->getZExtValue();
480 return v == 8 || v == 16 || v == 24; }],
482 let PrintMethod = "printRotImmOperand";
483 let ParserMatchClass = RotImmAsmOperand;
486 // shift_imm: An integer that encodes a shift amount and the type of shift
487 // (asr or lsl). The 6-bit immediate encodes as:
490 // {4-0} imm5 shift amount.
491 // asr #32 encoded as imm5 == 0.
492 def ShifterImmAsmOperand : AsmOperandClass {
493 let Name = "ShifterImm";
494 let ParserMethod = "parseShifterImm";
496 def shift_imm : Operand<i32> {
497 let PrintMethod = "printShiftImmOperand";
498 let ParserMatchClass = ShifterImmAsmOperand;
501 // shifter_operand operands: so_reg_reg, so_reg_imm, and so_imm.
502 def ShiftedRegAsmOperand : AsmOperandClass { let Name = "RegShiftedReg"; }
503 def so_reg_reg : Operand<i32>, // reg reg imm
504 ComplexPattern<i32, 3, "SelectRegShifterOperand",
505 [shl, srl, sra, rotr]> {
506 let EncoderMethod = "getSORegRegOpValue";
507 let PrintMethod = "printSORegRegOperand";
508 let DecoderMethod = "DecodeSORegRegOperand";
509 let ParserMatchClass = ShiftedRegAsmOperand;
510 let MIOperandInfo = (ops GPRnopc, GPRnopc, i32imm);
513 def ShiftedImmAsmOperand : AsmOperandClass { let Name = "RegShiftedImm"; }
514 def so_reg_imm : Operand<i32>, // reg imm
515 ComplexPattern<i32, 2, "SelectImmShifterOperand",
516 [shl, srl, sra, rotr]> {
517 let EncoderMethod = "getSORegImmOpValue";
518 let PrintMethod = "printSORegImmOperand";
519 let DecoderMethod = "DecodeSORegImmOperand";
520 let ParserMatchClass = ShiftedImmAsmOperand;
521 let MIOperandInfo = (ops GPR, i32imm);
524 // FIXME: Does this need to be distinct from so_reg?
525 def shift_so_reg_reg : Operand<i32>, // reg reg imm
526 ComplexPattern<i32, 3, "SelectShiftRegShifterOperand",
527 [shl,srl,sra,rotr]> {
528 let EncoderMethod = "getSORegRegOpValue";
529 let PrintMethod = "printSORegRegOperand";
530 let DecoderMethod = "DecodeSORegRegOperand";
531 let ParserMatchClass = ShiftedRegAsmOperand;
532 let MIOperandInfo = (ops GPR, GPR, i32imm);
535 // FIXME: Does this need to be distinct from so_reg?
536 def shift_so_reg_imm : Operand<i32>, // reg reg imm
537 ComplexPattern<i32, 2, "SelectShiftImmShifterOperand",
538 [shl,srl,sra,rotr]> {
539 let EncoderMethod = "getSORegImmOpValue";
540 let PrintMethod = "printSORegImmOperand";
541 let DecoderMethod = "DecodeSORegImmOperand";
542 let ParserMatchClass = ShiftedImmAsmOperand;
543 let MIOperandInfo = (ops GPR, i32imm);
547 // so_imm - Match a 32-bit shifter_operand immediate operand, which is an
548 // 8-bit immediate rotated by an arbitrary number of bits.
549 def SOImmAsmOperand: ImmAsmOperand { let Name = "ARMSOImm"; }
550 def so_imm : Operand<i32>, ImmLeaf<i32, [{
551 return ARM_AM::getSOImmVal(Imm) != -1;
553 let EncoderMethod = "getSOImmOpValue";
554 let ParserMatchClass = SOImmAsmOperand;
555 let DecoderMethod = "DecodeSOImmOperand";
558 // Break so_imm's up into two pieces. This handles immediates with up to 16
559 // bits set in them. This uses so_imm2part to match and so_imm2part_[12] to
560 // get the first/second pieces.
561 def so_imm2part : PatLeaf<(imm), [{
562 return ARM_AM::isSOImmTwoPartVal((unsigned)N->getZExtValue());
565 /// arm_i32imm - True for +V6T2, or true only if so_imm2part is true.
567 def arm_i32imm : PatLeaf<(imm), [{
568 if (Subtarget->hasV6T2Ops())
570 return ARM_AM::isSOImmTwoPartVal((unsigned)N->getZExtValue());
573 /// imm0_1 predicate - Immediate in the range [0,1].
574 def Imm0_1AsmOperand: ImmAsmOperand { let Name = "Imm0_1"; }
575 def imm0_1 : Operand<i32> { let ParserMatchClass = Imm0_1AsmOperand; }
577 /// imm0_3 predicate - Immediate in the range [0,3].
578 def Imm0_3AsmOperand: ImmAsmOperand { let Name = "Imm0_3"; }
579 def imm0_3 : Operand<i32> { let ParserMatchClass = Imm0_3AsmOperand; }
581 /// imm0_7 predicate - Immediate in the range [0,7].
582 def Imm0_7AsmOperand: ImmAsmOperand { let Name = "Imm0_7"; }
583 def imm0_7 : Operand<i32>, ImmLeaf<i32, [{
584 return Imm >= 0 && Imm < 8;
586 let ParserMatchClass = Imm0_7AsmOperand;
589 /// imm8 predicate - Immediate is exactly 8.
590 def Imm8AsmOperand: ImmAsmOperand { let Name = "Imm8"; }
591 def imm8 : Operand<i32>, ImmLeaf<i32, [{ return Imm == 8; }]> {
592 let ParserMatchClass = Imm8AsmOperand;
595 /// imm16 predicate - Immediate is exactly 16.
596 def Imm16AsmOperand: ImmAsmOperand { let Name = "Imm16"; }
597 def imm16 : Operand<i32>, ImmLeaf<i32, [{ return Imm == 16; }]> {
598 let ParserMatchClass = Imm16AsmOperand;
601 /// imm32 predicate - Immediate is exactly 32.
602 def Imm32AsmOperand: ImmAsmOperand { let Name = "Imm32"; }
603 def imm32 : Operand<i32>, ImmLeaf<i32, [{ return Imm == 32; }]> {
604 let ParserMatchClass = Imm32AsmOperand;
607 /// imm1_7 predicate - Immediate in the range [1,7].
608 def Imm1_7AsmOperand: ImmAsmOperand { let Name = "Imm1_7"; }
609 def imm1_7 : Operand<i32>, ImmLeaf<i32, [{ return Imm > 0 && Imm < 8; }]> {
610 let ParserMatchClass = Imm1_7AsmOperand;
613 /// imm1_15 predicate - Immediate in the range [1,15].
614 def Imm1_15AsmOperand: ImmAsmOperand { let Name = "Imm1_15"; }
615 def imm1_15 : Operand<i32>, ImmLeaf<i32, [{ return Imm > 0 && Imm < 16; }]> {
616 let ParserMatchClass = Imm1_15AsmOperand;
619 /// imm1_31 predicate - Immediate in the range [1,31].
620 def Imm1_31AsmOperand: ImmAsmOperand { let Name = "Imm1_31"; }
621 def imm1_31 : Operand<i32>, ImmLeaf<i32, [{ return Imm > 0 && Imm < 32; }]> {
622 let ParserMatchClass = Imm1_31AsmOperand;
625 /// imm0_15 predicate - Immediate in the range [0,15].
626 def Imm0_15AsmOperand: ImmAsmOperand {
627 let Name = "Imm0_15";
628 let DiagnosticType = "ImmRange0_15";
630 def imm0_15 : Operand<i32>, ImmLeaf<i32, [{
631 return Imm >= 0 && Imm < 16;
633 let ParserMatchClass = Imm0_15AsmOperand;
636 /// imm0_31 predicate - True if the 32-bit immediate is in the range [0,31].
637 def Imm0_31AsmOperand: ImmAsmOperand { let Name = "Imm0_31"; }
638 def imm0_31 : Operand<i32>, ImmLeaf<i32, [{
639 return Imm >= 0 && Imm < 32;
641 let ParserMatchClass = Imm0_31AsmOperand;
644 /// imm0_32 predicate - True if the 32-bit immediate is in the range [0,32].
645 def Imm0_32AsmOperand: ImmAsmOperand { let Name = "Imm0_32"; }
646 def imm0_32 : Operand<i32>, ImmLeaf<i32, [{
647 return Imm >= 0 && Imm < 32;
649 let ParserMatchClass = Imm0_32AsmOperand;
652 /// imm0_63 predicate - True if the 32-bit immediate is in the range [0,63].
653 def Imm0_63AsmOperand: ImmAsmOperand { let Name = "Imm0_63"; }
654 def imm0_63 : Operand<i32>, ImmLeaf<i32, [{
655 return Imm >= 0 && Imm < 64;
657 let ParserMatchClass = Imm0_63AsmOperand;
660 /// imm0_255 predicate - Immediate in the range [0,255].
661 def Imm0_255AsmOperand : ImmAsmOperand { let Name = "Imm0_255"; }
662 def imm0_255 : Operand<i32>, ImmLeaf<i32, [{ return Imm >= 0 && Imm < 256; }]> {
663 let ParserMatchClass = Imm0_255AsmOperand;
666 /// imm0_65535 - An immediate is in the range [0.65535].
667 def Imm0_65535AsmOperand: ImmAsmOperand { let Name = "Imm0_65535"; }
668 def imm0_65535 : Operand<i32>, ImmLeaf<i32, [{
669 return Imm >= 0 && Imm < 65536;
671 let ParserMatchClass = Imm0_65535AsmOperand;
674 // imm0_65535_neg - An immediate whose negative value is in the range [0.65535].
675 def imm0_65535_neg : Operand<i32>, ImmLeaf<i32, [{
676 return -Imm >= 0 && -Imm < 65536;
679 // imm0_65535_expr - For movt/movw - 16-bit immediate that can also reference
680 // a relocatable expression.
682 // FIXME: This really needs a Thumb version separate from the ARM version.
683 // While the range is the same, and can thus use the same match class,
684 // the encoding is different so it should have a different encoder method.
685 def Imm0_65535ExprAsmOperand: ImmAsmOperand { let Name = "Imm0_65535Expr"; }
686 def imm0_65535_expr : Operand<i32> {
687 let EncoderMethod = "getHiLo16ImmOpValue";
688 let ParserMatchClass = Imm0_65535ExprAsmOperand;
691 /// imm24b - True if the 32-bit immediate is encodable in 24 bits.
692 def Imm24bitAsmOperand: ImmAsmOperand { let Name = "Imm24bit"; }
693 def imm24b : Operand<i32>, ImmLeaf<i32, [{
694 return Imm >= 0 && Imm <= 0xffffff;
696 let ParserMatchClass = Imm24bitAsmOperand;
700 /// bf_inv_mask_imm predicate - An AND mask to clear an arbitrary width bitfield
702 def BitfieldAsmOperand : AsmOperandClass {
703 let Name = "Bitfield";
704 let ParserMethod = "parseBitfield";
707 def bf_inv_mask_imm : Operand<i32>,
709 return ARM::isBitFieldInvertedMask(N->getZExtValue());
711 let EncoderMethod = "getBitfieldInvertedMaskOpValue";
712 let PrintMethod = "printBitfieldInvMaskImmOperand";
713 let DecoderMethod = "DecodeBitfieldMaskOperand";
714 let ParserMatchClass = BitfieldAsmOperand;
717 def imm1_32_XFORM: SDNodeXForm<imm, [{
718 return CurDAG->getTargetConstant((int)N->getZExtValue() - 1, MVT::i32);
720 def Imm1_32AsmOperand: AsmOperandClass { let Name = "Imm1_32"; }
721 def imm1_32 : Operand<i32>, PatLeaf<(imm), [{
722 uint64_t Imm = N->getZExtValue();
723 return Imm > 0 && Imm <= 32;
726 let PrintMethod = "printImmPlusOneOperand";
727 let ParserMatchClass = Imm1_32AsmOperand;
730 def imm1_16_XFORM: SDNodeXForm<imm, [{
731 return CurDAG->getTargetConstant((int)N->getZExtValue() - 1, MVT::i32);
733 def Imm1_16AsmOperand: AsmOperandClass { let Name = "Imm1_16"; }
734 def imm1_16 : Operand<i32>, PatLeaf<(imm), [{ return Imm > 0 && Imm <= 16; }],
736 let PrintMethod = "printImmPlusOneOperand";
737 let ParserMatchClass = Imm1_16AsmOperand;
740 // Define ARM specific addressing modes.
741 // addrmode_imm12 := reg +/- imm12
743 def MemImm12OffsetAsmOperand : AsmOperandClass { let Name = "MemImm12Offset"; }
744 def addrmode_imm12 : Operand<i32>,
745 ComplexPattern<i32, 2, "SelectAddrModeImm12", []> {
746 // 12-bit immediate operand. Note that instructions using this encode
747 // #0 and #-0 differently. We flag #-0 as the magic value INT32_MIN. All other
748 // immediate values are as normal.
750 let EncoderMethod = "getAddrModeImm12OpValue";
751 let PrintMethod = "printAddrModeImm12Operand";
752 let DecoderMethod = "DecodeAddrModeImm12Operand";
753 let ParserMatchClass = MemImm12OffsetAsmOperand;
754 let MIOperandInfo = (ops GPR:$base, i32imm:$offsimm);
756 // ldst_so_reg := reg +/- reg shop imm
758 def MemRegOffsetAsmOperand : AsmOperandClass { let Name = "MemRegOffset"; }
759 def ldst_so_reg : Operand<i32>,
760 ComplexPattern<i32, 3, "SelectLdStSOReg", []> {
761 let EncoderMethod = "getLdStSORegOpValue";
762 // FIXME: Simplify the printer
763 let PrintMethod = "printAddrMode2Operand";
764 let DecoderMethod = "DecodeSORegMemOperand";
765 let ParserMatchClass = MemRegOffsetAsmOperand;
766 let MIOperandInfo = (ops GPR:$base, GPRnopc:$offsreg, i32imm:$shift);
769 // postidx_imm8 := +/- [0,255]
772 // {8} 1 is imm8 is non-negative. 0 otherwise.
773 // {7-0} [0,255] imm8 value.
774 def PostIdxImm8AsmOperand : AsmOperandClass { let Name = "PostIdxImm8"; }
775 def postidx_imm8 : Operand<i32> {
776 let PrintMethod = "printPostIdxImm8Operand";
777 let ParserMatchClass = PostIdxImm8AsmOperand;
778 let MIOperandInfo = (ops i32imm);
781 // postidx_imm8s4 := +/- [0,1020]
784 // {8} 1 is imm8 is non-negative. 0 otherwise.
785 // {7-0} [0,255] imm8 value, scaled by 4.
786 def PostIdxImm8s4AsmOperand : AsmOperandClass { let Name = "PostIdxImm8s4"; }
787 def postidx_imm8s4 : Operand<i32> {
788 let PrintMethod = "printPostIdxImm8s4Operand";
789 let ParserMatchClass = PostIdxImm8s4AsmOperand;
790 let MIOperandInfo = (ops i32imm);
794 // postidx_reg := +/- reg
796 def PostIdxRegAsmOperand : AsmOperandClass {
797 let Name = "PostIdxReg";
798 let ParserMethod = "parsePostIdxReg";
800 def postidx_reg : Operand<i32> {
801 let EncoderMethod = "getPostIdxRegOpValue";
802 let DecoderMethod = "DecodePostIdxReg";
803 let PrintMethod = "printPostIdxRegOperand";
804 let ParserMatchClass = PostIdxRegAsmOperand;
805 let MIOperandInfo = (ops GPRnopc, i32imm);
809 // addrmode2 := reg +/- imm12
810 // := reg +/- reg shop imm
812 // FIXME: addrmode2 should be refactored the rest of the way to always
813 // use explicit imm vs. reg versions above (addrmode_imm12 and ldst_so_reg).
814 def AddrMode2AsmOperand : AsmOperandClass { let Name = "AddrMode2"; }
815 def addrmode2 : Operand<i32>,
816 ComplexPattern<i32, 3, "SelectAddrMode2", []> {
817 let EncoderMethod = "getAddrMode2OpValue";
818 let PrintMethod = "printAddrMode2Operand";
819 let ParserMatchClass = AddrMode2AsmOperand;
820 let MIOperandInfo = (ops GPR:$base, GPR:$offsreg, i32imm:$offsimm);
823 def PostIdxRegShiftedAsmOperand : AsmOperandClass {
824 let Name = "PostIdxRegShifted";
825 let ParserMethod = "parsePostIdxReg";
827 def am2offset_reg : Operand<i32>,
828 ComplexPattern<i32, 2, "SelectAddrMode2OffsetReg",
829 [], [SDNPWantRoot]> {
830 let EncoderMethod = "getAddrMode2OffsetOpValue";
831 let PrintMethod = "printAddrMode2OffsetOperand";
832 // When using this for assembly, it's always as a post-index offset.
833 let ParserMatchClass = PostIdxRegShiftedAsmOperand;
834 let MIOperandInfo = (ops GPRnopc, i32imm);
837 // FIXME: am2offset_imm should only need the immediate, not the GPR. Having
838 // the GPR is purely vestigal at this point.
839 def AM2OffsetImmAsmOperand : AsmOperandClass { let Name = "AM2OffsetImm"; }
840 def am2offset_imm : Operand<i32>,
841 ComplexPattern<i32, 2, "SelectAddrMode2OffsetImm",
842 [], [SDNPWantRoot]> {
843 let EncoderMethod = "getAddrMode2OffsetOpValue";
844 let PrintMethod = "printAddrMode2OffsetOperand";
845 let ParserMatchClass = AM2OffsetImmAsmOperand;
846 let MIOperandInfo = (ops GPRnopc, i32imm);
850 // addrmode3 := reg +/- reg
851 // addrmode3 := reg +/- imm8
853 // FIXME: split into imm vs. reg versions.
854 def AddrMode3AsmOperand : AsmOperandClass { let Name = "AddrMode3"; }
855 def addrmode3 : Operand<i32>,
856 ComplexPattern<i32, 3, "SelectAddrMode3", []> {
857 let EncoderMethod = "getAddrMode3OpValue";
858 let PrintMethod = "printAddrMode3Operand";
859 let ParserMatchClass = AddrMode3AsmOperand;
860 let MIOperandInfo = (ops GPR:$base, GPR:$offsreg, i32imm:$offsimm);
863 // FIXME: split into imm vs. reg versions.
864 // FIXME: parser method to handle +/- register.
865 def AM3OffsetAsmOperand : AsmOperandClass {
866 let Name = "AM3Offset";
867 let ParserMethod = "parseAM3Offset";
869 def am3offset : Operand<i32>,
870 ComplexPattern<i32, 2, "SelectAddrMode3Offset",
871 [], [SDNPWantRoot]> {
872 let EncoderMethod = "getAddrMode3OffsetOpValue";
873 let PrintMethod = "printAddrMode3OffsetOperand";
874 let ParserMatchClass = AM3OffsetAsmOperand;
875 let MIOperandInfo = (ops GPR, i32imm);
878 // ldstm_mode := {ia, ib, da, db}
880 def ldstm_mode : OptionalDefOperand<OtherVT, (ops i32), (ops (i32 1))> {
881 let EncoderMethod = "getLdStmModeOpValue";
882 let PrintMethod = "printLdStmModeOperand";
885 // addrmode5 := reg +/- imm8*4
887 def AddrMode5AsmOperand : AsmOperandClass { let Name = "AddrMode5"; }
888 def addrmode5 : Operand<i32>,
889 ComplexPattern<i32, 2, "SelectAddrMode5", []> {
890 let PrintMethod = "printAddrMode5Operand";
891 let EncoderMethod = "getAddrMode5OpValue";
892 let DecoderMethod = "DecodeAddrMode5Operand";
893 let ParserMatchClass = AddrMode5AsmOperand;
894 let MIOperandInfo = (ops GPR:$base, i32imm);
897 // addrmode6 := reg with optional alignment
899 def AddrMode6AsmOperand : AsmOperandClass { let Name = "AlignedMemory"; }
900 def addrmode6 : Operand<i32>,
901 ComplexPattern<i32, 2, "SelectAddrMode6", [], [SDNPWantParent]>{
902 let PrintMethod = "printAddrMode6Operand";
903 let MIOperandInfo = (ops GPR:$addr, i32imm:$align);
904 let EncoderMethod = "getAddrMode6AddressOpValue";
905 let DecoderMethod = "DecodeAddrMode6Operand";
906 let ParserMatchClass = AddrMode6AsmOperand;
909 def am6offset : Operand<i32>,
910 ComplexPattern<i32, 1, "SelectAddrMode6Offset",
911 [], [SDNPWantRoot]> {
912 let PrintMethod = "printAddrMode6OffsetOperand";
913 let MIOperandInfo = (ops GPR);
914 let EncoderMethod = "getAddrMode6OffsetOpValue";
915 let DecoderMethod = "DecodeGPRRegisterClass";
918 // Special version of addrmode6 to handle alignment encoding for VST1/VLD1
919 // (single element from one lane) for size 32.
920 def addrmode6oneL32 : Operand<i32>,
921 ComplexPattern<i32, 2, "SelectAddrMode6", [], [SDNPWantParent]>{
922 let PrintMethod = "printAddrMode6Operand";
923 let MIOperandInfo = (ops GPR:$addr, i32imm);
924 let EncoderMethod = "getAddrMode6OneLane32AddressOpValue";
927 // Special version of addrmode6 to handle alignment encoding for VLD-dup
928 // instructions, specifically VLD4-dup.
929 def addrmode6dup : Operand<i32>,
930 ComplexPattern<i32, 2, "SelectAddrMode6", [], [SDNPWantParent]>{
931 let PrintMethod = "printAddrMode6Operand";
932 let MIOperandInfo = (ops GPR:$addr, i32imm);
933 let EncoderMethod = "getAddrMode6DupAddressOpValue";
934 // FIXME: This is close, but not quite right. The alignment specifier is
936 let ParserMatchClass = AddrMode6AsmOperand;
939 // addrmodepc := pc + reg
941 def addrmodepc : Operand<i32>,
942 ComplexPattern<i32, 2, "SelectAddrModePC", []> {
943 let PrintMethod = "printAddrModePCOperand";
944 let MIOperandInfo = (ops GPR, i32imm);
947 // addr_offset_none := reg
949 def MemNoOffsetAsmOperand : AsmOperandClass { let Name = "MemNoOffset"; }
950 def addr_offset_none : Operand<i32>,
951 ComplexPattern<i32, 1, "SelectAddrOffsetNone", []> {
952 let PrintMethod = "printAddrMode7Operand";
953 let DecoderMethod = "DecodeAddrMode7Operand";
954 let ParserMatchClass = MemNoOffsetAsmOperand;
955 let MIOperandInfo = (ops GPR:$base);
958 def nohash_imm : Operand<i32> {
959 let PrintMethod = "printNoHashImmediate";
962 def CoprocNumAsmOperand : AsmOperandClass {
963 let Name = "CoprocNum";
964 let ParserMethod = "parseCoprocNumOperand";
966 def p_imm : Operand<i32> {
967 let PrintMethod = "printPImmediate";
968 let ParserMatchClass = CoprocNumAsmOperand;
969 let DecoderMethod = "DecodeCoprocessor";
972 def pf_imm : Operand<i32> {
973 let PrintMethod = "printPImmediate";
974 let ParserMatchClass = CoprocNumAsmOperand;
977 def CoprocRegAsmOperand : AsmOperandClass {
978 let Name = "CoprocReg";
979 let ParserMethod = "parseCoprocRegOperand";
981 def c_imm : Operand<i32> {
982 let PrintMethod = "printCImmediate";
983 let ParserMatchClass = CoprocRegAsmOperand;
985 def CoprocOptionAsmOperand : AsmOperandClass {
986 let Name = "CoprocOption";
987 let ParserMethod = "parseCoprocOptionOperand";
989 def coproc_option_imm : Operand<i32> {
990 let PrintMethod = "printCoprocOptionImm";
991 let ParserMatchClass = CoprocOptionAsmOperand;
994 //===----------------------------------------------------------------------===//
996 include "ARMInstrFormats.td"
998 //===----------------------------------------------------------------------===//
999 // Multiclass helpers...
1002 /// AsI1_bin_irs - Defines a set of (op r, {so_imm|r|so_reg}) patterns for a
1003 /// binop that produces a value.
1004 let TwoOperandAliasConstraint = "$Rn = $Rd" in
1005 multiclass AsI1_bin_irs<bits<4> opcod, string opc,
1006 InstrItinClass iii, InstrItinClass iir, InstrItinClass iis,
1007 PatFrag opnode, bit Commutable = 0> {
1008 // The register-immediate version is re-materializable. This is useful
1009 // in particular for taking the address of a local.
1010 let isReMaterializable = 1 in {
1011 def ri : AsI1<opcod, (outs GPR:$Rd), (ins GPR:$Rn, so_imm:$imm), DPFrm,
1012 iii, opc, "\t$Rd, $Rn, $imm",
1013 [(set GPR:$Rd, (opnode GPR:$Rn, so_imm:$imm))]> {
1018 let Inst{19-16} = Rn;
1019 let Inst{15-12} = Rd;
1020 let Inst{11-0} = imm;
1023 def rr : AsI1<opcod, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm), DPFrm,
1024 iir, opc, "\t$Rd, $Rn, $Rm",
1025 [(set GPR:$Rd, (opnode GPR:$Rn, GPR:$Rm))]> {
1030 let isCommutable = Commutable;
1031 let Inst{19-16} = Rn;
1032 let Inst{15-12} = Rd;
1033 let Inst{11-4} = 0b00000000;
1037 def rsi : AsI1<opcod, (outs GPR:$Rd),
1038 (ins GPR:$Rn, so_reg_imm:$shift), DPSoRegImmFrm,
1039 iis, opc, "\t$Rd, $Rn, $shift",
1040 [(set GPR:$Rd, (opnode GPR:$Rn, so_reg_imm:$shift))]> {
1045 let Inst{19-16} = Rn;
1046 let Inst{15-12} = Rd;
1047 let Inst{11-5} = shift{11-5};
1049 let Inst{3-0} = shift{3-0};
1052 def rsr : AsI1<opcod, (outs GPR:$Rd),
1053 (ins GPR:$Rn, so_reg_reg:$shift), DPSoRegRegFrm,
1054 iis, opc, "\t$Rd, $Rn, $shift",
1055 [(set GPR:$Rd, (opnode GPR:$Rn, so_reg_reg:$shift))]> {
1060 let Inst{19-16} = Rn;
1061 let Inst{15-12} = Rd;
1062 let Inst{11-8} = shift{11-8};
1064 let Inst{6-5} = shift{6-5};
1066 let Inst{3-0} = shift{3-0};
1070 /// AsI1_rbin_irs - Same as AsI1_bin_irs except the order of operands are
1071 /// reversed. The 'rr' form is only defined for the disassembler; for codegen
1072 /// it is equivalent to the AsI1_bin_irs counterpart.
1073 let TwoOperandAliasConstraint = "$Rn = $Rd" in
1074 multiclass AsI1_rbin_irs<bits<4> opcod, string opc,
1075 InstrItinClass iii, InstrItinClass iir, InstrItinClass iis,
1076 PatFrag opnode, bit Commutable = 0> {
1077 // The register-immediate version is re-materializable. This is useful
1078 // in particular for taking the address of a local.
1079 let isReMaterializable = 1 in {
1080 def ri : AsI1<opcod, (outs GPR:$Rd), (ins GPR:$Rn, so_imm:$imm), DPFrm,
1081 iii, opc, "\t$Rd, $Rn, $imm",
1082 [(set GPR:$Rd, (opnode so_imm:$imm, GPR:$Rn))]> {
1087 let Inst{19-16} = Rn;
1088 let Inst{15-12} = Rd;
1089 let Inst{11-0} = imm;
1092 def rr : AsI1<opcod, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm), DPFrm,
1093 iir, opc, "\t$Rd, $Rn, $Rm",
1094 [/* pattern left blank */]> {
1098 let Inst{11-4} = 0b00000000;
1101 let Inst{15-12} = Rd;
1102 let Inst{19-16} = Rn;
1105 def rsi : AsI1<opcod, (outs GPR:$Rd),
1106 (ins GPR:$Rn, so_reg_imm:$shift), DPSoRegImmFrm,
1107 iis, opc, "\t$Rd, $Rn, $shift",
1108 [(set GPR:$Rd, (opnode so_reg_imm:$shift, GPR:$Rn))]> {
1113 let Inst{19-16} = Rn;
1114 let Inst{15-12} = Rd;
1115 let Inst{11-5} = shift{11-5};
1117 let Inst{3-0} = shift{3-0};
1120 def rsr : AsI1<opcod, (outs GPR:$Rd),
1121 (ins GPR:$Rn, so_reg_reg:$shift), DPSoRegRegFrm,
1122 iis, opc, "\t$Rd, $Rn, $shift",
1123 [(set GPR:$Rd, (opnode so_reg_reg:$shift, GPR:$Rn))]> {
1128 let Inst{19-16} = Rn;
1129 let Inst{15-12} = Rd;
1130 let Inst{11-8} = shift{11-8};
1132 let Inst{6-5} = shift{6-5};
1134 let Inst{3-0} = shift{3-0};
1138 /// AsI1_bin_s_irs - Same as AsI1_bin_irs except it sets the 's' bit by default.
1140 /// These opcodes will be converted to the real non-S opcodes by
1141 /// AdjustInstrPostInstrSelection after giving them an optional CPSR operand.
1142 let hasPostISelHook = 1, Defs = [CPSR] in {
1143 multiclass AsI1_bin_s_irs<InstrItinClass iii, InstrItinClass iir,
1144 InstrItinClass iis, PatFrag opnode,
1145 bit Commutable = 0> {
1146 def ri : ARMPseudoInst<(outs GPR:$Rd), (ins GPR:$Rn, so_imm:$imm, pred:$p),
1148 [(set GPR:$Rd, CPSR, (opnode GPR:$Rn, so_imm:$imm))]>;
1150 def rr : ARMPseudoInst<(outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm, pred:$p),
1152 [(set GPR:$Rd, CPSR, (opnode GPR:$Rn, GPR:$Rm))]> {
1153 let isCommutable = Commutable;
1155 def rsi : ARMPseudoInst<(outs GPR:$Rd),
1156 (ins GPR:$Rn, so_reg_imm:$shift, pred:$p),
1158 [(set GPR:$Rd, CPSR, (opnode GPR:$Rn,
1159 so_reg_imm:$shift))]>;
1161 def rsr : ARMPseudoInst<(outs GPR:$Rd),
1162 (ins GPR:$Rn, so_reg_reg:$shift, pred:$p),
1164 [(set GPR:$Rd, CPSR, (opnode GPR:$Rn,
1165 so_reg_reg:$shift))]>;
1169 /// AsI1_rbin_s_is - Same as AsI1_bin_s_irs, except selection DAG
1170 /// operands are reversed.
1171 let hasPostISelHook = 1, Defs = [CPSR] in {
1172 multiclass AsI1_rbin_s_is<InstrItinClass iii, InstrItinClass iir,
1173 InstrItinClass iis, PatFrag opnode,
1174 bit Commutable = 0> {
1175 def ri : ARMPseudoInst<(outs GPR:$Rd), (ins GPR:$Rn, so_imm:$imm, pred:$p),
1177 [(set GPR:$Rd, CPSR, (opnode so_imm:$imm, GPR:$Rn))]>;
1179 def rsi : ARMPseudoInst<(outs GPR:$Rd),
1180 (ins GPR:$Rn, so_reg_imm:$shift, pred:$p),
1182 [(set GPR:$Rd, CPSR, (opnode so_reg_imm:$shift,
1185 def rsr : ARMPseudoInst<(outs GPR:$Rd),
1186 (ins GPR:$Rn, so_reg_reg:$shift, pred:$p),
1188 [(set GPR:$Rd, CPSR, (opnode so_reg_reg:$shift,
1193 /// AI1_cmp_irs - Defines a set of (op r, {so_imm|r|so_reg}) cmp / test
1194 /// patterns. Similar to AsI1_bin_irs except the instruction does not produce
1195 /// a explicit result, only implicitly set CPSR.
1196 let isCompare = 1, Defs = [CPSR] in {
1197 multiclass AI1_cmp_irs<bits<4> opcod, string opc,
1198 InstrItinClass iii, InstrItinClass iir, InstrItinClass iis,
1199 PatFrag opnode, bit Commutable = 0> {
1200 def ri : AI1<opcod, (outs), (ins GPR:$Rn, so_imm:$imm), DPFrm, iii,
1202 [(opnode GPR:$Rn, so_imm:$imm)]> {
1207 let Inst{19-16} = Rn;
1208 let Inst{15-12} = 0b0000;
1209 let Inst{11-0} = imm;
1211 let Unpredictable{15-12} = 0b1111;
1213 def rr : AI1<opcod, (outs), (ins GPR:$Rn, GPR:$Rm), DPFrm, iir,
1215 [(opnode GPR:$Rn, GPR:$Rm)]> {
1218 let isCommutable = Commutable;
1221 let Inst{19-16} = Rn;
1222 let Inst{15-12} = 0b0000;
1223 let Inst{11-4} = 0b00000000;
1226 let Unpredictable{15-12} = 0b1111;
1228 def rsi : AI1<opcod, (outs),
1229 (ins GPR:$Rn, so_reg_imm:$shift), DPSoRegImmFrm, iis,
1230 opc, "\t$Rn, $shift",
1231 [(opnode GPR:$Rn, so_reg_imm:$shift)]> {
1236 let Inst{19-16} = Rn;
1237 let Inst{15-12} = 0b0000;
1238 let Inst{11-5} = shift{11-5};
1240 let Inst{3-0} = shift{3-0};
1242 let Unpredictable{15-12} = 0b1111;
1244 def rsr : AI1<opcod, (outs),
1245 (ins GPRnopc:$Rn, so_reg_reg:$shift), DPSoRegRegFrm, iis,
1246 opc, "\t$Rn, $shift",
1247 [(opnode GPRnopc:$Rn, so_reg_reg:$shift)]> {
1252 let Inst{19-16} = Rn;
1253 let Inst{15-12} = 0b0000;
1254 let Inst{11-8} = shift{11-8};
1256 let Inst{6-5} = shift{6-5};
1258 let Inst{3-0} = shift{3-0};
1260 let Unpredictable{15-12} = 0b1111;
1266 /// AI_ext_rrot - A unary operation with two forms: one whose operand is a
1267 /// register and one whose operand is a register rotated by 8/16/24.
1268 /// FIXME: Remove the 'r' variant. Its rot_imm is zero.
1269 class AI_ext_rrot<bits<8> opcod, string opc, PatFrag opnode>
1270 : AExtI<opcod, (outs GPRnopc:$Rd), (ins GPRnopc:$Rm, rot_imm:$rot),
1271 IIC_iEXTr, opc, "\t$Rd, $Rm$rot",
1272 [(set GPRnopc:$Rd, (opnode (rotr GPRnopc:$Rm, rot_imm:$rot)))]>,
1273 Requires<[IsARM, HasV6]> {
1277 let Inst{19-16} = 0b1111;
1278 let Inst{15-12} = Rd;
1279 let Inst{11-10} = rot;
1283 class AI_ext_rrot_np<bits<8> opcod, string opc>
1284 : AExtI<opcod, (outs GPRnopc:$Rd), (ins GPRnopc:$Rm, rot_imm:$rot),
1285 IIC_iEXTr, opc, "\t$Rd, $Rm$rot", []>,
1286 Requires<[IsARM, HasV6]> {
1288 let Inst{19-16} = 0b1111;
1289 let Inst{11-10} = rot;
1292 /// AI_exta_rrot - A binary operation with two forms: one whose operand is a
1293 /// register and one whose operand is a register rotated by 8/16/24.
1294 class AI_exta_rrot<bits<8> opcod, string opc, PatFrag opnode>
1295 : AExtI<opcod, (outs GPRnopc:$Rd), (ins GPR:$Rn, GPRnopc:$Rm, rot_imm:$rot),
1296 IIC_iEXTAr, opc, "\t$Rd, $Rn, $Rm$rot",
1297 [(set GPRnopc:$Rd, (opnode GPR:$Rn,
1298 (rotr GPRnopc:$Rm, rot_imm:$rot)))]>,
1299 Requires<[IsARM, HasV6]> {
1304 let Inst{19-16} = Rn;
1305 let Inst{15-12} = Rd;
1306 let Inst{11-10} = rot;
1307 let Inst{9-4} = 0b000111;
1311 class AI_exta_rrot_np<bits<8> opcod, string opc>
1312 : AExtI<opcod, (outs GPRnopc:$Rd), (ins GPR:$Rn, GPRnopc:$Rm, rot_imm:$rot),
1313 IIC_iEXTAr, opc, "\t$Rd, $Rn, $Rm$rot", []>,
1314 Requires<[IsARM, HasV6]> {
1317 let Inst{19-16} = Rn;
1318 let Inst{11-10} = rot;
1321 /// AI1_adde_sube_irs - Define instructions and patterns for adde and sube.
1322 let TwoOperandAliasConstraint = "$Rn = $Rd" in
1323 multiclass AI1_adde_sube_irs<bits<4> opcod, string opc, PatFrag opnode,
1324 bit Commutable = 0> {
1325 let hasPostISelHook = 1, Defs = [CPSR], Uses = [CPSR] in {
1326 def ri : AsI1<opcod, (outs GPR:$Rd), (ins GPR:$Rn, so_imm:$imm),
1327 DPFrm, IIC_iALUi, opc, "\t$Rd, $Rn, $imm",
1328 [(set GPR:$Rd, CPSR, (opnode GPR:$Rn, so_imm:$imm, CPSR))]>,
1334 let Inst{15-12} = Rd;
1335 let Inst{19-16} = Rn;
1336 let Inst{11-0} = imm;
1338 def rr : AsI1<opcod, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm),
1339 DPFrm, IIC_iALUr, opc, "\t$Rd, $Rn, $Rm",
1340 [(set GPR:$Rd, CPSR, (opnode GPR:$Rn, GPR:$Rm, CPSR))]>,
1345 let Inst{11-4} = 0b00000000;
1347 let isCommutable = Commutable;
1349 let Inst{15-12} = Rd;
1350 let Inst{19-16} = Rn;
1352 def rsi : AsI1<opcod, (outs GPR:$Rd),
1353 (ins GPR:$Rn, so_reg_imm:$shift),
1354 DPSoRegImmFrm, IIC_iALUsr, opc, "\t$Rd, $Rn, $shift",
1355 [(set GPR:$Rd, CPSR, (opnode GPR:$Rn, so_reg_imm:$shift, CPSR))]>,
1361 let Inst{19-16} = Rn;
1362 let Inst{15-12} = Rd;
1363 let Inst{11-5} = shift{11-5};
1365 let Inst{3-0} = shift{3-0};
1367 def rsr : AsI1<opcod, (outs GPRnopc:$Rd),
1368 (ins GPRnopc:$Rn, so_reg_reg:$shift),
1369 DPSoRegRegFrm, IIC_iALUsr, opc, "\t$Rd, $Rn, $shift",
1370 [(set GPRnopc:$Rd, CPSR,
1371 (opnode GPRnopc:$Rn, so_reg_reg:$shift, CPSR))]>,
1377 let Inst{19-16} = Rn;
1378 let Inst{15-12} = Rd;
1379 let Inst{11-8} = shift{11-8};
1381 let Inst{6-5} = shift{6-5};
1383 let Inst{3-0} = shift{3-0};
1388 /// AI1_rsc_irs - Define instructions and patterns for rsc
1389 let TwoOperandAliasConstraint = "$Rn = $Rd" in
1390 multiclass AI1_rsc_irs<bits<4> opcod, string opc, PatFrag opnode> {
1391 let hasPostISelHook = 1, Defs = [CPSR], Uses = [CPSR] in {
1392 def ri : AsI1<opcod, (outs GPR:$Rd), (ins GPR:$Rn, so_imm:$imm),
1393 DPFrm, IIC_iALUi, opc, "\t$Rd, $Rn, $imm",
1394 [(set GPR:$Rd, CPSR, (opnode so_imm:$imm, GPR:$Rn, CPSR))]>,
1400 let Inst{15-12} = Rd;
1401 let Inst{19-16} = Rn;
1402 let Inst{11-0} = imm;
1404 def rr : AsI1<opcod, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm),
1405 DPFrm, IIC_iALUr, opc, "\t$Rd, $Rn, $Rm",
1406 [/* pattern left blank */]> {
1410 let Inst{11-4} = 0b00000000;
1413 let Inst{15-12} = Rd;
1414 let Inst{19-16} = Rn;
1416 def rsi : AsI1<opcod, (outs GPR:$Rd), (ins GPR:$Rn, so_reg_imm:$shift),
1417 DPSoRegImmFrm, IIC_iALUsr, opc, "\t$Rd, $Rn, $shift",
1418 [(set GPR:$Rd, CPSR, (opnode so_reg_imm:$shift, GPR:$Rn, CPSR))]>,
1424 let Inst{19-16} = Rn;
1425 let Inst{15-12} = Rd;
1426 let Inst{11-5} = shift{11-5};
1428 let Inst{3-0} = shift{3-0};
1430 def rsr : AsI1<opcod, (outs GPR:$Rd), (ins GPR:$Rn, so_reg_reg:$shift),
1431 DPSoRegRegFrm, IIC_iALUsr, opc, "\t$Rd, $Rn, $shift",
1432 [(set GPR:$Rd, CPSR, (opnode so_reg_reg:$shift, GPR:$Rn, CPSR))]>,
1438 let Inst{19-16} = Rn;
1439 let Inst{15-12} = Rd;
1440 let Inst{11-8} = shift{11-8};
1442 let Inst{6-5} = shift{6-5};
1444 let Inst{3-0} = shift{3-0};
1449 let canFoldAsLoad = 1, isReMaterializable = 1 in {
1450 multiclass AI_ldr1<bit isByte, string opc, InstrItinClass iii,
1451 InstrItinClass iir, PatFrag opnode> {
1452 // Note: We use the complex addrmode_imm12 rather than just an input
1453 // GPR and a constrained immediate so that we can use this to match
1454 // frame index references and avoid matching constant pool references.
1455 def i12: AI2ldst<0b010, 1, isByte, (outs GPR:$Rt), (ins addrmode_imm12:$addr),
1456 AddrMode_i12, LdFrm, iii, opc, "\t$Rt, $addr",
1457 [(set GPR:$Rt, (opnode addrmode_imm12:$addr))]> {
1460 let Inst{23} = addr{12}; // U (add = ('U' == 1))
1461 let Inst{19-16} = addr{16-13}; // Rn
1462 let Inst{15-12} = Rt;
1463 let Inst{11-0} = addr{11-0}; // imm12
1465 def rs : AI2ldst<0b011, 1, isByte, (outs GPR:$Rt), (ins ldst_so_reg:$shift),
1466 AddrModeNone, LdFrm, iir, opc, "\t$Rt, $shift",
1467 [(set GPR:$Rt, (opnode ldst_so_reg:$shift))]> {
1470 let shift{4} = 0; // Inst{4} = 0
1471 let Inst{23} = shift{12}; // U (add = ('U' == 1))
1472 let Inst{19-16} = shift{16-13}; // Rn
1473 let Inst{15-12} = Rt;
1474 let Inst{11-0} = shift{11-0};
1479 let canFoldAsLoad = 1, isReMaterializable = 1 in {
1480 multiclass AI_ldr1nopc<bit isByte, string opc, InstrItinClass iii,
1481 InstrItinClass iir, PatFrag opnode> {
1482 // Note: We use the complex addrmode_imm12 rather than just an input
1483 // GPR and a constrained immediate so that we can use this to match
1484 // frame index references and avoid matching constant pool references.
1485 def i12: AI2ldst<0b010, 1, isByte, (outs GPRnopc:$Rt),
1486 (ins addrmode_imm12:$addr),
1487 AddrMode_i12, LdFrm, iii, opc, "\t$Rt, $addr",
1488 [(set GPRnopc:$Rt, (opnode addrmode_imm12:$addr))]> {
1491 let Inst{23} = addr{12}; // U (add = ('U' == 1))
1492 let Inst{19-16} = addr{16-13}; // Rn
1493 let Inst{15-12} = Rt;
1494 let Inst{11-0} = addr{11-0}; // imm12
1496 def rs : AI2ldst<0b011, 1, isByte, (outs GPRnopc:$Rt),
1497 (ins ldst_so_reg:$shift),
1498 AddrModeNone, LdFrm, iir, opc, "\t$Rt, $shift",
1499 [(set GPRnopc:$Rt, (opnode ldst_so_reg:$shift))]> {
1502 let shift{4} = 0; // Inst{4} = 0
1503 let Inst{23} = shift{12}; // U (add = ('U' == 1))
1504 let Inst{19-16} = shift{16-13}; // Rn
1505 let Inst{15-12} = Rt;
1506 let Inst{11-0} = shift{11-0};
1512 multiclass AI_str1<bit isByte, string opc, InstrItinClass iii,
1513 InstrItinClass iir, PatFrag opnode> {
1514 // Note: We use the complex addrmode_imm12 rather than just an input
1515 // GPR and a constrained immediate so that we can use this to match
1516 // frame index references and avoid matching constant pool references.
1517 def i12 : AI2ldst<0b010, 0, isByte, (outs),
1518 (ins GPR:$Rt, addrmode_imm12:$addr),
1519 AddrMode_i12, StFrm, iii, opc, "\t$Rt, $addr",
1520 [(opnode GPR:$Rt, addrmode_imm12:$addr)]> {
1523 let Inst{23} = addr{12}; // U (add = ('U' == 1))
1524 let Inst{19-16} = addr{16-13}; // Rn
1525 let Inst{15-12} = Rt;
1526 let Inst{11-0} = addr{11-0}; // imm12
1528 def rs : AI2ldst<0b011, 0, isByte, (outs), (ins GPR:$Rt, ldst_so_reg:$shift),
1529 AddrModeNone, StFrm, iir, opc, "\t$Rt, $shift",
1530 [(opnode GPR:$Rt, ldst_so_reg:$shift)]> {
1533 let shift{4} = 0; // Inst{4} = 0
1534 let Inst{23} = shift{12}; // U (add = ('U' == 1))
1535 let Inst{19-16} = shift{16-13}; // Rn
1536 let Inst{15-12} = Rt;
1537 let Inst{11-0} = shift{11-0};
1541 multiclass AI_str1nopc<bit isByte, string opc, InstrItinClass iii,
1542 InstrItinClass iir, PatFrag opnode> {
1543 // Note: We use the complex addrmode_imm12 rather than just an input
1544 // GPR and a constrained immediate so that we can use this to match
1545 // frame index references and avoid matching constant pool references.
1546 def i12 : AI2ldst<0b010, 0, isByte, (outs),
1547 (ins GPRnopc:$Rt, addrmode_imm12:$addr),
1548 AddrMode_i12, StFrm, iii, opc, "\t$Rt, $addr",
1549 [(opnode GPRnopc:$Rt, addrmode_imm12:$addr)]> {
1552 let Inst{23} = addr{12}; // U (add = ('U' == 1))
1553 let Inst{19-16} = addr{16-13}; // Rn
1554 let Inst{15-12} = Rt;
1555 let Inst{11-0} = addr{11-0}; // imm12
1557 def rs : AI2ldst<0b011, 0, isByte, (outs),
1558 (ins GPRnopc:$Rt, ldst_so_reg:$shift),
1559 AddrModeNone, StFrm, iir, opc, "\t$Rt, $shift",
1560 [(opnode GPRnopc:$Rt, ldst_so_reg:$shift)]> {
1563 let shift{4} = 0; // Inst{4} = 0
1564 let Inst{23} = shift{12}; // U (add = ('U' == 1))
1565 let Inst{19-16} = shift{16-13}; // Rn
1566 let Inst{15-12} = Rt;
1567 let Inst{11-0} = shift{11-0};
1572 //===----------------------------------------------------------------------===//
1574 //===----------------------------------------------------------------------===//
1576 //===----------------------------------------------------------------------===//
1577 // Miscellaneous Instructions.
1580 /// CONSTPOOL_ENTRY - This instruction represents a floating constant pool in
1581 /// the function. The first operand is the ID# for this instruction, the second
1582 /// is the index into the MachineConstantPool that this is, the third is the
1583 /// size in bytes of this constant pool entry.
1584 let neverHasSideEffects = 1, isNotDuplicable = 1 in
1585 def CONSTPOOL_ENTRY :
1586 PseudoInst<(outs), (ins cpinst_operand:$instid, cpinst_operand:$cpidx,
1587 i32imm:$size), NoItinerary, []>;
1589 // FIXME: Marking these as hasSideEffects is necessary to prevent machine DCE
1590 // from removing one half of the matched pairs. That breaks PEI, which assumes
1591 // these will always be in pairs, and asserts if it finds otherwise. Better way?
1592 let Defs = [SP], Uses = [SP], hasSideEffects = 1 in {
1593 def ADJCALLSTACKUP :
1594 PseudoInst<(outs), (ins i32imm:$amt1, i32imm:$amt2, pred:$p), NoItinerary,
1595 [(ARMcallseq_end timm:$amt1, timm:$amt2)]>;
1597 def ADJCALLSTACKDOWN :
1598 PseudoInst<(outs), (ins i32imm:$amt, pred:$p), NoItinerary,
1599 [(ARMcallseq_start timm:$amt)]>;
1602 // Atomic pseudo-insts which will be lowered to ldrexd/strexd loops.
1603 // (These pseudos use a hand-written selection code).
1604 let usesCustomInserter = 1, Defs = [CPSR], mayLoad = 1, mayStore = 1 in {
1605 def ATOMOR6432 : PseudoInst<(outs GPR:$dst1, GPR:$dst2),
1606 (ins GPR:$addr, GPR:$src1, GPR:$src2),
1608 def ATOMXOR6432 : PseudoInst<(outs GPR:$dst1, GPR:$dst2),
1609 (ins GPR:$addr, GPR:$src1, GPR:$src2),
1611 def ATOMADD6432 : PseudoInst<(outs GPR:$dst1, GPR:$dst2),
1612 (ins GPR:$addr, GPR:$src1, GPR:$src2),
1614 def ATOMSUB6432 : PseudoInst<(outs GPR:$dst1, GPR:$dst2),
1615 (ins GPR:$addr, GPR:$src1, GPR:$src2),
1617 def ATOMNAND6432 : PseudoInst<(outs GPR:$dst1, GPR:$dst2),
1618 (ins GPR:$addr, GPR:$src1, GPR:$src2),
1620 def ATOMAND6432 : PseudoInst<(outs GPR:$dst1, GPR:$dst2),
1621 (ins GPR:$addr, GPR:$src1, GPR:$src2),
1623 def ATOMSWAP6432 : PseudoInst<(outs GPR:$dst1, GPR:$dst2),
1624 (ins GPR:$addr, GPR:$src1, GPR:$src2),
1626 def ATOMCMPXCHG6432 : PseudoInst<(outs GPR:$dst1, GPR:$dst2),
1627 (ins GPR:$addr, GPR:$cmp1, GPR:$cmp2,
1628 GPR:$set1, GPR:$set2),
1630 def ATOMMIN6432 : PseudoInst<(outs GPR:$dst1, GPR:$dst2),
1631 (ins GPR:$addr, GPR:$src1, GPR:$src2),
1633 def ATOMUMIN6432 : PseudoInst<(outs GPR:$dst1, GPR:$dst2),
1634 (ins GPR:$addr, GPR:$src1, GPR:$src2),
1636 def ATOMMAX6432 : PseudoInst<(outs GPR:$dst1, GPR:$dst2),
1637 (ins GPR:$addr, GPR:$src1, GPR:$src2),
1639 def ATOMUMAX6432 : PseudoInst<(outs GPR:$dst1, GPR:$dst2),
1640 (ins GPR:$addr, GPR:$src1, GPR:$src2),
1644 def HINT : AI<(outs), (ins imm0_255:$imm), MiscFrm, NoItinerary,
1645 "hint", "\t$imm", []>, Requires<[IsARM, HasV6]> {
1647 let Inst{27-8} = 0b00110010000011110000;
1648 let Inst{7-0} = imm;
1651 def : InstAlias<"nop$p", (HINT 0, pred:$p)>, Requires<[IsARM, HasV6T2]>;
1652 def : InstAlias<"yield$p", (HINT 1, pred:$p)>, Requires<[IsARM, HasV6T2]>;
1653 def : InstAlias<"wfe$p", (HINT 2, pred:$p)>, Requires<[IsARM, HasV6T2]>;
1654 def : InstAlias<"wfi$p", (HINT 3, pred:$p)>, Requires<[IsARM, HasV6T2]>;
1655 def : InstAlias<"sev$p", (HINT 4, pred:$p)>, Requires<[IsARM, HasV6T2]>;
1657 def SEL : AI<(outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm), DPFrm, NoItinerary, "sel",
1658 "\t$Rd, $Rn, $Rm", []>, Requires<[IsARM, HasV6]> {
1663 let Inst{15-12} = Rd;
1664 let Inst{19-16} = Rn;
1665 let Inst{27-20} = 0b01101000;
1666 let Inst{7-4} = 0b1011;
1667 let Inst{11-8} = 0b1111;
1668 let Unpredictable{11-8} = 0b1111;
1671 // The 16-bit operand $val can be used by a debugger to store more information
1672 // about the breakpoint.
1673 def BKPT : AI<(outs), (ins imm0_65535:$val), MiscFrm, NoItinerary,
1674 "bkpt", "\t$val", []>, Requires<[IsARM]> {
1676 let Inst{3-0} = val{3-0};
1677 let Inst{19-8} = val{15-4};
1678 let Inst{27-20} = 0b00010010;
1679 let Inst{7-4} = 0b0111;
1682 // Change Processor State
1683 // FIXME: We should use InstAlias to handle the optional operands.
1684 class CPS<dag iops, string asm_ops>
1685 : AXI<(outs), iops, MiscFrm, NoItinerary, !strconcat("cps", asm_ops),
1686 []>, Requires<[IsARM]> {
1692 let Inst{31-28} = 0b1111;
1693 let Inst{27-20} = 0b00010000;
1694 let Inst{19-18} = imod;
1695 let Inst{17} = M; // Enabled if mode is set;
1696 let Inst{16-9} = 0b00000000;
1697 let Inst{8-6} = iflags;
1699 let Inst{4-0} = mode;
1702 let DecoderMethod = "DecodeCPSInstruction" in {
1704 def CPS3p : CPS<(ins imod_op:$imod, iflags_op:$iflags, imm0_31:$mode),
1705 "$imod\t$iflags, $mode">;
1706 let mode = 0, M = 0 in
1707 def CPS2p : CPS<(ins imod_op:$imod, iflags_op:$iflags), "$imod\t$iflags">;
1709 let imod = 0, iflags = 0, M = 1 in
1710 def CPS1p : CPS<(ins imm0_31:$mode), "\t$mode">;
1713 // Preload signals the memory system of possible future data/instruction access.
1714 multiclass APreLoad<bits<1> read, bits<1> data, string opc> {
1716 def i12 : AXI<(outs), (ins addrmode_imm12:$addr), MiscFrm, IIC_Preload,
1717 !strconcat(opc, "\t$addr"),
1718 [(ARMPreload addrmode_imm12:$addr, (i32 read), (i32 data))]> {
1721 let Inst{31-26} = 0b111101;
1722 let Inst{25} = 0; // 0 for immediate form
1723 let Inst{24} = data;
1724 let Inst{23} = addr{12}; // U (add = ('U' == 1))
1725 let Inst{22} = read;
1726 let Inst{21-20} = 0b01;
1727 let Inst{19-16} = addr{16-13}; // Rn
1728 let Inst{15-12} = 0b1111;
1729 let Inst{11-0} = addr{11-0}; // imm12
1732 def rs : AXI<(outs), (ins ldst_so_reg:$shift), MiscFrm, IIC_Preload,
1733 !strconcat(opc, "\t$shift"),
1734 [(ARMPreload ldst_so_reg:$shift, (i32 read), (i32 data))]> {
1736 let Inst{31-26} = 0b111101;
1737 let Inst{25} = 1; // 1 for register form
1738 let Inst{24} = data;
1739 let Inst{23} = shift{12}; // U (add = ('U' == 1))
1740 let Inst{22} = read;
1741 let Inst{21-20} = 0b01;
1742 let Inst{19-16} = shift{16-13}; // Rn
1743 let Inst{15-12} = 0b1111;
1744 let Inst{11-0} = shift{11-0};
1749 defm PLD : APreLoad<1, 1, "pld">, Requires<[IsARM]>;
1750 defm PLDW : APreLoad<0, 1, "pldw">, Requires<[IsARM,HasV7,HasMP]>;
1751 defm PLI : APreLoad<1, 0, "pli">, Requires<[IsARM,HasV7]>;
1753 def SETEND : AXI<(outs), (ins setend_op:$end), MiscFrm, NoItinerary,
1754 "setend\t$end", []>, Requires<[IsARM]> {
1756 let Inst{31-10} = 0b1111000100000001000000;
1761 def DBG : AI<(outs), (ins imm0_15:$opt), MiscFrm, NoItinerary, "dbg", "\t$opt",
1762 []>, Requires<[IsARM, HasV7]> {
1764 let Inst{27-4} = 0b001100100000111100001111;
1765 let Inst{3-0} = opt;
1769 * A5.4 Permanently UNDEFINED instructions.
1771 * For most targets use UDF #65006, for which the OS will generate SIGTRAP.
1772 * Other UDF encodings generate SIGILL.
1774 * NaCl's OS instead chooses an ARM UDF encoding that's also a UDF in Thumb.
1776 * 1110 0111 1111 iiii iiii iiii 1111 iiii
1778 * 1101 1110 iiii iiii
1779 * It uses the following encoding:
1780 * 1110 0111 1111 1110 1101 1110 1111 0000
1781 * - In ARM: UDF #60896;
1782 * - In Thumb: UDF #254 followed by a branch-to-self.
1784 let isBarrier = 1, isTerminator = 1 in
1785 def TRAPNaCl : AXI<(outs), (ins), MiscFrm, NoItinerary,
1787 Requires<[IsARM,UseNaClTrap]> {
1788 let Inst = 0xe7fedef0;
1790 let isBarrier = 1, isTerminator = 1 in
1791 def TRAP : AXI<(outs), (ins), MiscFrm, NoItinerary,
1793 Requires<[IsARM,DontUseNaClTrap]> {
1794 let Inst = 0xe7ffdefe;
1797 // Address computation and loads and stores in PIC mode.
1798 let isNotDuplicable = 1 in {
1799 def PICADD : ARMPseudoInst<(outs GPR:$dst), (ins GPR:$a, pclabel:$cp, pred:$p),
1801 [(set GPR:$dst, (ARMpic_add GPR:$a, imm:$cp))]>;
1803 let AddedComplexity = 10 in {
1804 def PICLDR : ARMPseudoInst<(outs GPR:$dst), (ins addrmodepc:$addr, pred:$p),
1806 [(set GPR:$dst, (load addrmodepc:$addr))]>;
1808 def PICLDRH : ARMPseudoInst<(outs GPR:$Rt), (ins addrmodepc:$addr, pred:$p),
1810 [(set GPR:$Rt, (zextloadi16 addrmodepc:$addr))]>;
1812 def PICLDRB : ARMPseudoInst<(outs GPR:$Rt), (ins addrmodepc:$addr, pred:$p),
1814 [(set GPR:$Rt, (zextloadi8 addrmodepc:$addr))]>;
1816 def PICLDRSH : ARMPseudoInst<(outs GPR:$Rt), (ins addrmodepc:$addr, pred:$p),
1818 [(set GPR:$Rt, (sextloadi16 addrmodepc:$addr))]>;
1820 def PICLDRSB : ARMPseudoInst<(outs GPR:$Rt), (ins addrmodepc:$addr, pred:$p),
1822 [(set GPR:$Rt, (sextloadi8 addrmodepc:$addr))]>;
1824 let AddedComplexity = 10 in {
1825 def PICSTR : ARMPseudoInst<(outs), (ins GPR:$src, addrmodepc:$addr, pred:$p),
1826 4, IIC_iStore_r, [(store GPR:$src, addrmodepc:$addr)]>;
1828 def PICSTRH : ARMPseudoInst<(outs), (ins GPR:$src, addrmodepc:$addr, pred:$p),
1829 4, IIC_iStore_bh_r, [(truncstorei16 GPR:$src,
1830 addrmodepc:$addr)]>;
1832 def PICSTRB : ARMPseudoInst<(outs), (ins GPR:$src, addrmodepc:$addr, pred:$p),
1833 4, IIC_iStore_bh_r, [(truncstorei8 GPR:$src, addrmodepc:$addr)]>;
1835 } // isNotDuplicable = 1
1838 // LEApcrel - Load a pc-relative address into a register without offending the
1840 let neverHasSideEffects = 1, isReMaterializable = 1 in
1841 // The 'adr' mnemonic encodes differently if the label is before or after
1842 // the instruction. The {24-21} opcode bits are set by the fixup, as we don't
1843 // know until then which form of the instruction will be used.
1844 def ADR : AI1<{0,?,?,0}, (outs GPR:$Rd), (ins adrlabel:$label),
1845 MiscFrm, IIC_iALUi, "adr", "\t$Rd, $label", []> {
1848 let Inst{27-25} = 0b001;
1850 let Inst{23-22} = label{13-12};
1853 let Inst{19-16} = 0b1111;
1854 let Inst{15-12} = Rd;
1855 let Inst{11-0} = label{11-0};
1858 let hasSideEffects = 1 in {
1859 def LEApcrel : ARMPseudoInst<(outs GPR:$Rd), (ins i32imm:$label, pred:$p),
1862 def LEApcrelJT : ARMPseudoInst<(outs GPR:$Rd),
1863 (ins i32imm:$label, nohash_imm:$id, pred:$p),
1867 //===----------------------------------------------------------------------===//
1868 // Control Flow Instructions.
1871 let isReturn = 1, isTerminator = 1, isBarrier = 1 in {
1873 def BX_RET : AI<(outs), (ins), BrMiscFrm, IIC_Br,
1874 "bx", "\tlr", [(ARMretflag)]>,
1875 Requires<[IsARM, HasV4T]> {
1876 let Inst{27-0} = 0b0001001011111111111100011110;
1880 def MOVPCLR : AI<(outs), (ins), BrMiscFrm, IIC_Br,
1881 "mov", "\tpc, lr", [(ARMretflag)]>,
1882 Requires<[IsARM, NoV4T]> {
1883 let Inst{27-0} = 0b0001101000001111000000001110;
1887 // Indirect branches
1888 let isBranch = 1, isTerminator = 1, isBarrier = 1, isIndirectBranch = 1 in {
1890 def BX : AXI<(outs), (ins GPR:$dst), BrMiscFrm, IIC_Br, "bx\t$dst",
1891 [(brind GPR:$dst)]>,
1892 Requires<[IsARM, HasV4T]> {
1894 let Inst{31-4} = 0b1110000100101111111111110001;
1895 let Inst{3-0} = dst;
1898 def BX_pred : AI<(outs), (ins GPR:$dst), BrMiscFrm, IIC_Br,
1899 "bx", "\t$dst", [/* pattern left blank */]>,
1900 Requires<[IsARM, HasV4T]> {
1902 let Inst{27-4} = 0b000100101111111111110001;
1903 let Inst{3-0} = dst;
1907 // SP is marked as a use to prevent stack-pointer assignments that appear
1908 // immediately before calls from potentially appearing dead.
1910 // FIXME: Do we really need a non-predicated version? If so, it should
1911 // at least be a pseudo instruction expanding to the predicated version
1912 // at MC lowering time.
1913 Defs = [LR], Uses = [SP] in {
1914 def BL : ABXI<0b1011, (outs), (ins bl_target:$func),
1915 IIC_Br, "bl\t$func",
1916 [(ARMcall tglobaladdr:$func)]>,
1918 let Inst{31-28} = 0b1110;
1920 let Inst{23-0} = func;
1921 let DecoderMethod = "DecodeBranchImmInstruction";
1924 def BL_pred : ABI<0b1011, (outs), (ins bl_target:$func),
1925 IIC_Br, "bl", "\t$func",
1926 [(ARMcall_pred tglobaladdr:$func)]>,
1929 let Inst{23-0} = func;
1930 let DecoderMethod = "DecodeBranchImmInstruction";
1934 def BLX : AXI<(outs), (ins GPR:$func), BrMiscFrm,
1935 IIC_Br, "blx\t$func",
1936 [(ARMcall GPR:$func)]>,
1937 Requires<[IsARM, HasV5T]> {
1939 let Inst{31-4} = 0b1110000100101111111111110011;
1940 let Inst{3-0} = func;
1943 def BLX_pred : AI<(outs), (ins GPR:$func), BrMiscFrm,
1944 IIC_Br, "blx", "\t$func",
1945 [(ARMcall_pred GPR:$func)]>,
1946 Requires<[IsARM, HasV5T]> {
1948 let Inst{27-4} = 0b000100101111111111110011;
1949 let Inst{3-0} = func;
1953 // Note: Restrict $func to the tGPR regclass to prevent it being in LR.
1954 def BX_CALL : ARMPseudoInst<(outs), (ins tGPR:$func),
1955 8, IIC_Br, [(ARMcall_nolink tGPR:$func)]>,
1956 Requires<[IsARM, HasV4T]>;
1959 def BMOVPCRX_CALL : ARMPseudoInst<(outs), (ins tGPR:$func),
1960 8, IIC_Br, [(ARMcall_nolink tGPR:$func)]>,
1961 Requires<[IsARM, NoV4T]>;
1963 // mov lr, pc; b if callee is marked noreturn to avoid confusing the
1964 // return stack predictor.
1965 def BMOVPCB_CALL : ARMPseudoInst<(outs), (ins bl_target:$func),
1966 8, IIC_Br, [(ARMcall_nolink tglobaladdr:$func)]>,
1970 let isBranch = 1, isTerminator = 1 in {
1971 // FIXME: should be able to write a pattern for ARMBrcond, but can't use
1972 // a two-value operand where a dag node expects two operands. :(
1973 def Bcc : ABI<0b1010, (outs), (ins br_target:$target),
1974 IIC_Br, "b", "\t$target",
1975 [/*(ARMbrcond bb:$target, imm:$cc, CCR:$ccr)*/]> {
1977 let Inst{23-0} = target;
1978 let DecoderMethod = "DecodeBranchImmInstruction";
1981 let isBarrier = 1 in {
1982 // B is "predicable" since it's just a Bcc with an 'always' condition.
1983 let isPredicable = 1 in
1984 // FIXME: We shouldn't need this pseudo at all. Just using Bcc directly
1985 // should be sufficient.
1986 // FIXME: Is B really a Barrier? That doesn't seem right.
1987 def B : ARMPseudoExpand<(outs), (ins br_target:$target), 4, IIC_Br,
1988 [(br bb:$target)], (Bcc br_target:$target, (ops 14, zero_reg))>;
1990 let isNotDuplicable = 1, isIndirectBranch = 1 in {
1991 def BR_JTr : ARMPseudoInst<(outs),
1992 (ins GPR:$target, i32imm:$jt, i32imm:$id),
1994 [(ARMbrjt GPR:$target, tjumptable:$jt, imm:$id)]>;
1995 // FIXME: This shouldn't use the generic "addrmode2," but rather be split
1996 // into i12 and rs suffixed versions.
1997 def BR_JTm : ARMPseudoInst<(outs),
1998 (ins addrmode2:$target, i32imm:$jt, i32imm:$id),
2000 [(ARMbrjt (i32 (load addrmode2:$target)), tjumptable:$jt,
2002 def BR_JTadd : ARMPseudoInst<(outs),
2003 (ins GPR:$target, GPR:$idx, i32imm:$jt, i32imm:$id),
2005 [(ARMbrjt (add GPR:$target, GPR:$idx), tjumptable:$jt,
2007 } // isNotDuplicable = 1, isIndirectBranch = 1
2013 def BLXi : AXI<(outs), (ins blx_target:$target), BrMiscFrm, NoItinerary,
2014 "blx\t$target", []>,
2015 Requires<[IsARM, HasV5T]> {
2016 let Inst{31-25} = 0b1111101;
2018 let Inst{23-0} = target{24-1};
2019 let Inst{24} = target{0};
2022 // Branch and Exchange Jazelle
2023 def BXJ : ABI<0b0001, (outs), (ins GPR:$func), NoItinerary, "bxj", "\t$func",
2024 [/* pattern left blank */]> {
2026 let Inst{23-20} = 0b0010;
2027 let Inst{19-8} = 0xfff;
2028 let Inst{7-4} = 0b0010;
2029 let Inst{3-0} = func;
2034 let isCall = 1, isTerminator = 1, isReturn = 1, isBarrier = 1, Uses = [SP] in {
2035 def TCRETURNdi : PseudoInst<(outs), (ins i32imm:$dst), IIC_Br, []>;
2037 def TCRETURNri : PseudoInst<(outs), (ins tcGPR:$dst), IIC_Br, []>;
2039 def TAILJMPd : ARMPseudoExpand<(outs), (ins br_target:$dst),
2041 (Bcc br_target:$dst, (ops 14, zero_reg))>,
2044 def TAILJMPr : ARMPseudoExpand<(outs), (ins tcGPR:$dst),
2050 // Secure Monitor Call is a system instruction.
2051 def SMC : ABI<0b0001, (outs), (ins imm0_15:$opt), NoItinerary, "smc", "\t$opt",
2054 let Inst{23-4} = 0b01100000000000000111;
2055 let Inst{3-0} = opt;
2058 // Supervisor Call (Software Interrupt)
2059 let isCall = 1, Uses = [SP] in {
2060 def SVC : ABI<0b1111, (outs), (ins imm24b:$svc), IIC_Br, "svc", "\t$svc", []> {
2062 let Inst{23-0} = svc;
2066 // Store Return State
2067 class SRSI<bit wb, string asm>
2068 : XI<(outs), (ins imm0_31:$mode), AddrModeNone, 4, IndexModeNone, BrFrm,
2069 NoItinerary, asm, "", []> {
2071 let Inst{31-28} = 0b1111;
2072 let Inst{27-25} = 0b100;
2076 let Inst{19-16} = 0b1101; // SP
2077 let Inst{15-5} = 0b00000101000;
2078 let Inst{4-0} = mode;
2081 def SRSDA : SRSI<0, "srsda\tsp, $mode"> {
2082 let Inst{24-23} = 0;
2084 def SRSDA_UPD : SRSI<1, "srsda\tsp!, $mode"> {
2085 let Inst{24-23} = 0;
2087 def SRSDB : SRSI<0, "srsdb\tsp, $mode"> {
2088 let Inst{24-23} = 0b10;
2090 def SRSDB_UPD : SRSI<1, "srsdb\tsp!, $mode"> {
2091 let Inst{24-23} = 0b10;
2093 def SRSIA : SRSI<0, "srsia\tsp, $mode"> {
2094 let Inst{24-23} = 0b01;
2096 def SRSIA_UPD : SRSI<1, "srsia\tsp!, $mode"> {
2097 let Inst{24-23} = 0b01;
2099 def SRSIB : SRSI<0, "srsib\tsp, $mode"> {
2100 let Inst{24-23} = 0b11;
2102 def SRSIB_UPD : SRSI<1, "srsib\tsp!, $mode"> {
2103 let Inst{24-23} = 0b11;
2106 def : ARMInstAlias<"srsda $mode", (SRSDA imm0_31:$mode)>;
2107 def : ARMInstAlias<"srsda $mode!", (SRSDA_UPD imm0_31:$mode)>;
2109 def : ARMInstAlias<"srsdb $mode", (SRSDB imm0_31:$mode)>;
2110 def : ARMInstAlias<"srsdb $mode!", (SRSDB_UPD imm0_31:$mode)>;
2112 def : ARMInstAlias<"srsia $mode", (SRSIA imm0_31:$mode)>;
2113 def : ARMInstAlias<"srsia $mode!", (SRSIA_UPD imm0_31:$mode)>;
2115 def : ARMInstAlias<"srsib $mode", (SRSIB imm0_31:$mode)>;
2116 def : ARMInstAlias<"srsib $mode!", (SRSIB_UPD imm0_31:$mode)>;
2118 // Return From Exception
2119 class RFEI<bit wb, string asm>
2120 : XI<(outs), (ins GPR:$Rn), AddrModeNone, 4, IndexModeNone, BrFrm,
2121 NoItinerary, asm, "", []> {
2123 let Inst{31-28} = 0b1111;
2124 let Inst{27-25} = 0b100;
2128 let Inst{19-16} = Rn;
2129 let Inst{15-0} = 0xa00;
2132 def RFEDA : RFEI<0, "rfeda\t$Rn"> {
2133 let Inst{24-23} = 0;
2135 def RFEDA_UPD : RFEI<1, "rfeda\t$Rn!"> {
2136 let Inst{24-23} = 0;
2138 def RFEDB : RFEI<0, "rfedb\t$Rn"> {
2139 let Inst{24-23} = 0b10;
2141 def RFEDB_UPD : RFEI<1, "rfedb\t$Rn!"> {
2142 let Inst{24-23} = 0b10;
2144 def RFEIA : RFEI<0, "rfeia\t$Rn"> {
2145 let Inst{24-23} = 0b01;
2147 def RFEIA_UPD : RFEI<1, "rfeia\t$Rn!"> {
2148 let Inst{24-23} = 0b01;
2150 def RFEIB : RFEI<0, "rfeib\t$Rn"> {
2151 let Inst{24-23} = 0b11;
2153 def RFEIB_UPD : RFEI<1, "rfeib\t$Rn!"> {
2154 let Inst{24-23} = 0b11;
2157 //===----------------------------------------------------------------------===//
2158 // Load / Store Instructions.
2164 defm LDR : AI_ldr1<0, "ldr", IIC_iLoad_r, IIC_iLoad_si,
2165 UnOpFrag<(load node:$Src)>>;
2166 defm LDRB : AI_ldr1nopc<1, "ldrb", IIC_iLoad_bh_r, IIC_iLoad_bh_si,
2167 UnOpFrag<(zextloadi8 node:$Src)>>;
2168 defm STR : AI_str1<0, "str", IIC_iStore_r, IIC_iStore_si,
2169 BinOpFrag<(store node:$LHS, node:$RHS)>>;
2170 defm STRB : AI_str1nopc<1, "strb", IIC_iStore_bh_r, IIC_iStore_bh_si,
2171 BinOpFrag<(truncstorei8 node:$LHS, node:$RHS)>>;
2173 // Special LDR for loads from non-pc-relative constpools.
2174 let canFoldAsLoad = 1, mayLoad = 1, neverHasSideEffects = 1,
2175 isReMaterializable = 1, isCodeGenOnly = 1 in
2176 def LDRcp : AI2ldst<0b010, 1, 0, (outs GPR:$Rt), (ins addrmode_imm12:$addr),
2177 AddrMode_i12, LdFrm, IIC_iLoad_r, "ldr", "\t$Rt, $addr",
2181 let Inst{23} = addr{12}; // U (add = ('U' == 1))
2182 let Inst{19-16} = 0b1111;
2183 let Inst{15-12} = Rt;
2184 let Inst{11-0} = addr{11-0}; // imm12
2187 // Loads with zero extension
2188 def LDRH : AI3ld<0b1011, 1, (outs GPR:$Rt), (ins addrmode3:$addr), LdMiscFrm,
2189 IIC_iLoad_bh_r, "ldrh", "\t$Rt, $addr",
2190 [(set GPR:$Rt, (zextloadi16 addrmode3:$addr))]>;
2192 // Loads with sign extension
2193 def LDRSH : AI3ld<0b1111, 1, (outs GPR:$Rt), (ins addrmode3:$addr), LdMiscFrm,
2194 IIC_iLoad_bh_r, "ldrsh", "\t$Rt, $addr",
2195 [(set GPR:$Rt, (sextloadi16 addrmode3:$addr))]>;
2197 def LDRSB : AI3ld<0b1101, 1, (outs GPR:$Rt), (ins addrmode3:$addr), LdMiscFrm,
2198 IIC_iLoad_bh_r, "ldrsb", "\t$Rt, $addr",
2199 [(set GPR:$Rt, (sextloadi8 addrmode3:$addr))]>;
2201 let mayLoad = 1, neverHasSideEffects = 1, hasExtraDefRegAllocReq = 1 in {
2203 def LDRD : AI3ld<0b1101, 0, (outs GPR:$Rd, GPR:$dst2),
2204 (ins addrmode3:$addr), LdMiscFrm,
2205 IIC_iLoad_d_r, "ldrd", "\t$Rd, $dst2, $addr",
2206 []>, Requires<[IsARM, HasV5TE]>;
2210 multiclass AI2_ldridx<bit isByte, string opc,
2211 InstrItinClass iii, InstrItinClass iir> {
2212 def _PRE_IMM : AI2ldstidx<1, isByte, 1, (outs GPR:$Rt, GPR:$Rn_wb),
2213 (ins addrmode_imm12:$addr), IndexModePre, LdFrm, iii,
2214 opc, "\t$Rt, $addr!", "$addr.base = $Rn_wb", []> {
2217 let Inst{23} = addr{12};
2218 let Inst{19-16} = addr{16-13};
2219 let Inst{11-0} = addr{11-0};
2220 let DecoderMethod = "DecodeLDRPreImm";
2221 let AsmMatchConverter = "cvtLdWriteBackRegAddrModeImm12";
2224 def _PRE_REG : AI2ldstidx<1, isByte, 1, (outs GPR:$Rt, GPR:$Rn_wb),
2225 (ins ldst_so_reg:$addr), IndexModePre, LdFrm, iir,
2226 opc, "\t$Rt, $addr!", "$addr.base = $Rn_wb", []> {
2229 let Inst{23} = addr{12};
2230 let Inst{19-16} = addr{16-13};
2231 let Inst{11-0} = addr{11-0};
2233 let DecoderMethod = "DecodeLDRPreReg";
2234 let AsmMatchConverter = "cvtLdWriteBackRegAddrMode2";
2237 def _POST_REG : AI2ldstidx<1, isByte, 0, (outs GPR:$Rt, GPR:$Rn_wb),
2238 (ins addr_offset_none:$addr, am2offset_reg:$offset),
2239 IndexModePost, LdFrm, iir,
2240 opc, "\t$Rt, $addr, $offset",
2241 "$addr.base = $Rn_wb", []> {
2247 let Inst{23} = offset{12};
2248 let Inst{19-16} = addr;
2249 let Inst{11-0} = offset{11-0};
2251 let DecoderMethod = "DecodeAddrMode2IdxInstruction";
2254 def _POST_IMM : AI2ldstidx<1, isByte, 0, (outs GPR:$Rt, GPR:$Rn_wb),
2255 (ins addr_offset_none:$addr, am2offset_imm:$offset),
2256 IndexModePost, LdFrm, iii,
2257 opc, "\t$Rt, $addr, $offset",
2258 "$addr.base = $Rn_wb", []> {
2264 let Inst{23} = offset{12};
2265 let Inst{19-16} = addr;
2266 let Inst{11-0} = offset{11-0};
2268 let DecoderMethod = "DecodeAddrMode2IdxInstruction";
2273 let mayLoad = 1, neverHasSideEffects = 1 in {
2274 // FIXME: for LDR_PRE_REG etc. the itineray should be either IIC_iLoad_ru or
2275 // IIC_iLoad_siu depending on whether it the offset register is shifted.
2276 defm LDR : AI2_ldridx<0, "ldr", IIC_iLoad_iu, IIC_iLoad_ru>;
2277 defm LDRB : AI2_ldridx<1, "ldrb", IIC_iLoad_bh_iu, IIC_iLoad_bh_ru>;
2280 multiclass AI3_ldridx<bits<4> op, string opc, InstrItinClass itin> {
2281 def _PRE : AI3ldstidx<op, 1, 1, (outs GPR:$Rt, GPR:$Rn_wb),
2282 (ins addrmode3:$addr), IndexModePre,
2284 opc, "\t$Rt, $addr!", "$addr.base = $Rn_wb", []> {
2286 let Inst{23} = addr{8}; // U bit
2287 let Inst{22} = addr{13}; // 1 == imm8, 0 == Rm
2288 let Inst{19-16} = addr{12-9}; // Rn
2289 let Inst{11-8} = addr{7-4}; // imm7_4/zero
2290 let Inst{3-0} = addr{3-0}; // imm3_0/Rm
2291 let AsmMatchConverter = "cvtLdWriteBackRegAddrMode3";
2292 let DecoderMethod = "DecodeAddrMode3Instruction";
2294 def _POST : AI3ldstidx<op, 1, 0, (outs GPR:$Rt, GPR:$Rn_wb),
2295 (ins addr_offset_none:$addr, am3offset:$offset),
2296 IndexModePost, LdMiscFrm, itin,
2297 opc, "\t$Rt, $addr, $offset", "$addr.base = $Rn_wb",
2301 let Inst{23} = offset{8}; // U bit
2302 let Inst{22} = offset{9}; // 1 == imm8, 0 == Rm
2303 let Inst{19-16} = addr;
2304 let Inst{11-8} = offset{7-4}; // imm7_4/zero
2305 let Inst{3-0} = offset{3-0}; // imm3_0/Rm
2306 let DecoderMethod = "DecodeAddrMode3Instruction";
2310 let mayLoad = 1, neverHasSideEffects = 1 in {
2311 defm LDRH : AI3_ldridx<0b1011, "ldrh", IIC_iLoad_bh_ru>;
2312 defm LDRSH : AI3_ldridx<0b1111, "ldrsh", IIC_iLoad_bh_ru>;
2313 defm LDRSB : AI3_ldridx<0b1101, "ldrsb", IIC_iLoad_bh_ru>;
2314 let hasExtraDefRegAllocReq = 1 in {
2315 def LDRD_PRE : AI3ldstidx<0b1101, 0, 1, (outs GPR:$Rt, GPR:$Rt2, GPR:$Rn_wb),
2316 (ins addrmode3:$addr), IndexModePre,
2317 LdMiscFrm, IIC_iLoad_d_ru,
2318 "ldrd", "\t$Rt, $Rt2, $addr!",
2319 "$addr.base = $Rn_wb", []> {
2321 let Inst{23} = addr{8}; // U bit
2322 let Inst{22} = addr{13}; // 1 == imm8, 0 == Rm
2323 let Inst{19-16} = addr{12-9}; // Rn
2324 let Inst{11-8} = addr{7-4}; // imm7_4/zero
2325 let Inst{3-0} = addr{3-0}; // imm3_0/Rm
2326 let DecoderMethod = "DecodeAddrMode3Instruction";
2327 let AsmMatchConverter = "cvtLdrdPre";
2329 def LDRD_POST: AI3ldstidx<0b1101, 0, 0, (outs GPR:$Rt, GPR:$Rt2, GPR:$Rn_wb),
2330 (ins addr_offset_none:$addr, am3offset:$offset),
2331 IndexModePost, LdMiscFrm, IIC_iLoad_d_ru,
2332 "ldrd", "\t$Rt, $Rt2, $addr, $offset",
2333 "$addr.base = $Rn_wb", []> {
2336 let Inst{23} = offset{8}; // U bit
2337 let Inst{22} = offset{9}; // 1 == imm8, 0 == Rm
2338 let Inst{19-16} = addr;
2339 let Inst{11-8} = offset{7-4}; // imm7_4/zero
2340 let Inst{3-0} = offset{3-0}; // imm3_0/Rm
2341 let DecoderMethod = "DecodeAddrMode3Instruction";
2343 } // hasExtraDefRegAllocReq = 1
2344 } // mayLoad = 1, neverHasSideEffects = 1
2346 // LDRT, LDRBT, LDRSBT, LDRHT, LDRSHT.
2347 let mayLoad = 1, neverHasSideEffects = 1 in {
2348 def LDRT_POST_REG : AI2ldstidx<1, 0, 0, (outs GPR:$Rt, GPR:$Rn_wb),
2349 (ins addr_offset_none:$addr, am2offset_reg:$offset),
2350 IndexModePost, LdFrm, IIC_iLoad_ru,
2351 "ldrt", "\t$Rt, $addr, $offset",
2352 "$addr.base = $Rn_wb", []> {
2358 let Inst{23} = offset{12};
2359 let Inst{21} = 1; // overwrite
2360 let Inst{19-16} = addr;
2361 let Inst{11-5} = offset{11-5};
2363 let Inst{3-0} = offset{3-0};
2364 let DecoderMethod = "DecodeAddrMode2IdxInstruction";
2367 def LDRT_POST_IMM : AI2ldstidx<1, 0, 0, (outs GPR:$Rt, GPR:$Rn_wb),
2368 (ins addr_offset_none:$addr, am2offset_imm:$offset),
2369 IndexModePost, LdFrm, IIC_iLoad_ru,
2370 "ldrt", "\t$Rt, $addr, $offset",
2371 "$addr.base = $Rn_wb", []> {
2377 let Inst{23} = offset{12};
2378 let Inst{21} = 1; // overwrite
2379 let Inst{19-16} = addr;
2380 let Inst{11-0} = offset{11-0};
2381 let DecoderMethod = "DecodeAddrMode2IdxInstruction";
2384 def LDRBT_POST_REG : AI2ldstidx<1, 1, 0, (outs GPR:$Rt, GPR:$Rn_wb),
2385 (ins addr_offset_none:$addr, am2offset_reg:$offset),
2386 IndexModePost, LdFrm, IIC_iLoad_bh_ru,
2387 "ldrbt", "\t$Rt, $addr, $offset",
2388 "$addr.base = $Rn_wb", []> {
2394 let Inst{23} = offset{12};
2395 let Inst{21} = 1; // overwrite
2396 let Inst{19-16} = addr;
2397 let Inst{11-5} = offset{11-5};
2399 let Inst{3-0} = offset{3-0};
2400 let DecoderMethod = "DecodeAddrMode2IdxInstruction";
2403 def LDRBT_POST_IMM : AI2ldstidx<1, 1, 0, (outs GPR:$Rt, GPR:$Rn_wb),
2404 (ins addr_offset_none:$addr, am2offset_imm:$offset),
2405 IndexModePost, LdFrm, IIC_iLoad_bh_ru,
2406 "ldrbt", "\t$Rt, $addr, $offset",
2407 "$addr.base = $Rn_wb", []> {
2413 let Inst{23} = offset{12};
2414 let Inst{21} = 1; // overwrite
2415 let Inst{19-16} = addr;
2416 let Inst{11-0} = offset{11-0};
2417 let DecoderMethod = "DecodeAddrMode2IdxInstruction";
2420 multiclass AI3ldrT<bits<4> op, string opc> {
2421 def i : AI3ldstidxT<op, 1, (outs GPR:$Rt, GPR:$base_wb),
2422 (ins addr_offset_none:$addr, postidx_imm8:$offset),
2423 IndexModePost, LdMiscFrm, IIC_iLoad_bh_ru, opc,
2424 "\t$Rt, $addr, $offset", "$addr.base = $base_wb", []> {
2426 let Inst{23} = offset{8};
2428 let Inst{11-8} = offset{7-4};
2429 let Inst{3-0} = offset{3-0};
2430 let AsmMatchConverter = "cvtLdExtTWriteBackImm";
2432 def r : AI3ldstidxT<op, 1, (outs GPRnopc:$Rt, GPRnopc:$base_wb),
2433 (ins addr_offset_none:$addr, postidx_reg:$Rm),
2434 IndexModePost, LdMiscFrm, IIC_iLoad_bh_ru, opc,
2435 "\t$Rt, $addr, $Rm", "$addr.base = $base_wb", []> {
2437 let Inst{23} = Rm{4};
2440 let Unpredictable{11-8} = 0b1111;
2441 let Inst{3-0} = Rm{3-0};
2442 let AsmMatchConverter = "cvtLdExtTWriteBackReg";
2443 let DecoderMethod = "DecodeLDR";
2447 defm LDRSBT : AI3ldrT<0b1101, "ldrsbt">;
2448 defm LDRHT : AI3ldrT<0b1011, "ldrht">;
2449 defm LDRSHT : AI3ldrT<0b1111, "ldrsht">;
2454 // Stores with truncate
2455 def STRH : AI3str<0b1011, (outs), (ins GPR:$Rt, addrmode3:$addr), StMiscFrm,
2456 IIC_iStore_bh_r, "strh", "\t$Rt, $addr",
2457 [(truncstorei16 GPR:$Rt, addrmode3:$addr)]>;
2460 let mayStore = 1, neverHasSideEffects = 1, hasExtraSrcRegAllocReq = 1 in
2461 def STRD : AI3str<0b1111, (outs), (ins GPR:$Rt, GPR:$src2, addrmode3:$addr),
2462 StMiscFrm, IIC_iStore_d_r,
2463 "strd", "\t$Rt, $src2, $addr", []>,
2464 Requires<[IsARM, HasV5TE]> {
2469 multiclass AI2_stridx<bit isByte, string opc,
2470 InstrItinClass iii, InstrItinClass iir> {
2471 def _PRE_IMM : AI2ldstidx<0, isByte, 1, (outs GPR:$Rn_wb),
2472 (ins GPR:$Rt, addrmode_imm12:$addr), IndexModePre,
2474 opc, "\t$Rt, $addr!", "$addr.base = $Rn_wb", []> {
2477 let Inst{23} = addr{12}; // U (add = ('U' == 1))
2478 let Inst{19-16} = addr{16-13}; // Rn
2479 let Inst{11-0} = addr{11-0}; // imm12
2480 let AsmMatchConverter = "cvtStWriteBackRegAddrModeImm12";
2481 let DecoderMethod = "DecodeSTRPreImm";
2484 def _PRE_REG : AI2ldstidx<0, isByte, 1, (outs GPR:$Rn_wb),
2485 (ins GPR:$Rt, ldst_so_reg:$addr),
2486 IndexModePre, StFrm, iir,
2487 opc, "\t$Rt, $addr!", "$addr.base = $Rn_wb", []> {
2490 let Inst{23} = addr{12}; // U (add = ('U' == 1))
2491 let Inst{19-16} = addr{16-13}; // Rn
2492 let Inst{11-0} = addr{11-0};
2493 let Inst{4} = 0; // Inst{4} = 0
2494 let AsmMatchConverter = "cvtStWriteBackRegAddrMode2";
2495 let DecoderMethod = "DecodeSTRPreReg";
2497 def _POST_REG : AI2ldstidx<0, isByte, 0, (outs GPR:$Rn_wb),
2498 (ins GPR:$Rt, addr_offset_none:$addr, am2offset_reg:$offset),
2499 IndexModePost, StFrm, iir,
2500 opc, "\t$Rt, $addr, $offset",
2501 "$addr.base = $Rn_wb", []> {
2507 let Inst{23} = offset{12};
2508 let Inst{19-16} = addr;
2509 let Inst{11-0} = offset{11-0};
2512 let DecoderMethod = "DecodeAddrMode2IdxInstruction";
2515 def _POST_IMM : AI2ldstidx<0, isByte, 0, (outs GPR:$Rn_wb),
2516 (ins GPR:$Rt, addr_offset_none:$addr, am2offset_imm:$offset),
2517 IndexModePost, StFrm, iii,
2518 opc, "\t$Rt, $addr, $offset",
2519 "$addr.base = $Rn_wb", []> {
2525 let Inst{23} = offset{12};
2526 let Inst{19-16} = addr;
2527 let Inst{11-0} = offset{11-0};
2529 let DecoderMethod = "DecodeAddrMode2IdxInstruction";
2533 let mayStore = 1, neverHasSideEffects = 1 in {
2534 // FIXME: for STR_PRE_REG etc. the itineray should be either IIC_iStore_ru or
2535 // IIC_iStore_siu depending on whether it the offset register is shifted.
2536 defm STR : AI2_stridx<0, "str", IIC_iStore_iu, IIC_iStore_ru>;
2537 defm STRB : AI2_stridx<1, "strb", IIC_iStore_bh_iu, IIC_iStore_bh_ru>;
2540 def : ARMPat<(post_store GPR:$Rt, addr_offset_none:$addr,
2541 am2offset_reg:$offset),
2542 (STR_POST_REG GPR:$Rt, addr_offset_none:$addr,
2543 am2offset_reg:$offset)>;
2544 def : ARMPat<(post_store GPR:$Rt, addr_offset_none:$addr,
2545 am2offset_imm:$offset),
2546 (STR_POST_IMM GPR:$Rt, addr_offset_none:$addr,
2547 am2offset_imm:$offset)>;
2548 def : ARMPat<(post_truncsti8 GPR:$Rt, addr_offset_none:$addr,
2549 am2offset_reg:$offset),
2550 (STRB_POST_REG GPR:$Rt, addr_offset_none:$addr,
2551 am2offset_reg:$offset)>;
2552 def : ARMPat<(post_truncsti8 GPR:$Rt, addr_offset_none:$addr,
2553 am2offset_imm:$offset),
2554 (STRB_POST_IMM GPR:$Rt, addr_offset_none:$addr,
2555 am2offset_imm:$offset)>;
2557 // Pseudo-instructions for pattern matching the pre-indexed stores. We can't
2558 // put the patterns on the instruction definitions directly as ISel wants
2559 // the address base and offset to be separate operands, not a single
2560 // complex operand like we represent the instructions themselves. The
2561 // pseudos map between the two.
2562 let usesCustomInserter = 1,
2563 Constraints = "$Rn = $Rn_wb,@earlyclobber $Rn_wb" in {
2564 def STRi_preidx: ARMPseudoInst<(outs GPR:$Rn_wb),
2565 (ins GPR:$Rt, GPR:$Rn, am2offset_imm:$offset, pred:$p),
2568 (pre_store GPR:$Rt, GPR:$Rn, am2offset_imm:$offset))]>;
2569 def STRr_preidx: ARMPseudoInst<(outs GPR:$Rn_wb),
2570 (ins GPR:$Rt, GPR:$Rn, am2offset_reg:$offset, pred:$p),
2573 (pre_store GPR:$Rt, GPR:$Rn, am2offset_reg:$offset))]>;
2574 def STRBi_preidx: ARMPseudoInst<(outs GPR:$Rn_wb),
2575 (ins GPR:$Rt, GPR:$Rn, am2offset_imm:$offset, pred:$p),
2578 (pre_truncsti8 GPR:$Rt, GPR:$Rn, am2offset_imm:$offset))]>;
2579 def STRBr_preidx: ARMPseudoInst<(outs GPR:$Rn_wb),
2580 (ins GPR:$Rt, GPR:$Rn, am2offset_reg:$offset, pred:$p),
2583 (pre_truncsti8 GPR:$Rt, GPR:$Rn, am2offset_reg:$offset))]>;
2584 def STRH_preidx: ARMPseudoInst<(outs GPR:$Rn_wb),
2585 (ins GPR:$Rt, GPR:$Rn, am3offset:$offset, pred:$p),
2588 (pre_truncsti16 GPR:$Rt, GPR:$Rn, am3offset:$offset))]>;
2593 def STRH_PRE : AI3ldstidx<0b1011, 0, 1, (outs GPR:$Rn_wb),
2594 (ins GPR:$Rt, addrmode3:$addr), IndexModePre,
2595 StMiscFrm, IIC_iStore_bh_ru,
2596 "strh", "\t$Rt, $addr!", "$addr.base = $Rn_wb", []> {
2598 let Inst{23} = addr{8}; // U bit
2599 let Inst{22} = addr{13}; // 1 == imm8, 0 == Rm
2600 let Inst{19-16} = addr{12-9}; // Rn
2601 let Inst{11-8} = addr{7-4}; // imm7_4/zero
2602 let Inst{3-0} = addr{3-0}; // imm3_0/Rm
2603 let AsmMatchConverter = "cvtStWriteBackRegAddrMode3";
2604 let DecoderMethod = "DecodeAddrMode3Instruction";
2607 def STRH_POST : AI3ldstidx<0b1011, 0, 0, (outs GPR:$Rn_wb),
2608 (ins GPR:$Rt, addr_offset_none:$addr, am3offset:$offset),
2609 IndexModePost, StMiscFrm, IIC_iStore_bh_ru,
2610 "strh", "\t$Rt, $addr, $offset", "$addr.base = $Rn_wb",
2611 [(set GPR:$Rn_wb, (post_truncsti16 GPR:$Rt,
2612 addr_offset_none:$addr,
2613 am3offset:$offset))]> {
2616 let Inst{23} = offset{8}; // U bit
2617 let Inst{22} = offset{9}; // 1 == imm8, 0 == Rm
2618 let Inst{19-16} = addr;
2619 let Inst{11-8} = offset{7-4}; // imm7_4/zero
2620 let Inst{3-0} = offset{3-0}; // imm3_0/Rm
2621 let DecoderMethod = "DecodeAddrMode3Instruction";
2624 let mayStore = 1, neverHasSideEffects = 1, hasExtraSrcRegAllocReq = 1 in {
2625 def STRD_PRE : AI3ldstidx<0b1111, 0, 1, (outs GPR:$Rn_wb),
2626 (ins GPR:$Rt, GPR:$Rt2, addrmode3:$addr),
2627 IndexModePre, StMiscFrm, IIC_iStore_d_ru,
2628 "strd", "\t$Rt, $Rt2, $addr!",
2629 "$addr.base = $Rn_wb", []> {
2631 let Inst{23} = addr{8}; // U bit
2632 let Inst{22} = addr{13}; // 1 == imm8, 0 == Rm
2633 let Inst{19-16} = addr{12-9}; // Rn
2634 let Inst{11-8} = addr{7-4}; // imm7_4/zero
2635 let Inst{3-0} = addr{3-0}; // imm3_0/Rm
2636 let DecoderMethod = "DecodeAddrMode3Instruction";
2637 let AsmMatchConverter = "cvtStrdPre";
2640 def STRD_POST: AI3ldstidx<0b1111, 0, 0, (outs GPR:$Rn_wb),
2641 (ins GPR:$Rt, GPR:$Rt2, addr_offset_none:$addr,
2643 IndexModePost, StMiscFrm, IIC_iStore_d_ru,
2644 "strd", "\t$Rt, $Rt2, $addr, $offset",
2645 "$addr.base = $Rn_wb", []> {
2648 let Inst{23} = offset{8}; // U bit
2649 let Inst{22} = offset{9}; // 1 == imm8, 0 == Rm
2650 let Inst{19-16} = addr;
2651 let Inst{11-8} = offset{7-4}; // imm7_4/zero
2652 let Inst{3-0} = offset{3-0}; // imm3_0/Rm
2653 let DecoderMethod = "DecodeAddrMode3Instruction";
2655 } // mayStore = 1, neverHasSideEffects = 1, hasExtraSrcRegAllocReq = 1
2657 // STRT, STRBT, and STRHT
2659 def STRBT_POST_REG : AI2ldstidx<0, 1, 0, (outs GPR:$Rn_wb),
2660 (ins GPR:$Rt, addr_offset_none:$addr, am2offset_reg:$offset),
2661 IndexModePost, StFrm, IIC_iStore_bh_ru,
2662 "strbt", "\t$Rt, $addr, $offset",
2663 "$addr.base = $Rn_wb", []> {
2669 let Inst{23} = offset{12};
2670 let Inst{21} = 1; // overwrite
2671 let Inst{19-16} = addr;
2672 let Inst{11-5} = offset{11-5};
2674 let Inst{3-0} = offset{3-0};
2675 let DecoderMethod = "DecodeAddrMode2IdxInstruction";
2678 def STRBT_POST_IMM : AI2ldstidx<0, 1, 0, (outs GPR:$Rn_wb),
2679 (ins GPR:$Rt, addr_offset_none:$addr, am2offset_imm:$offset),
2680 IndexModePost, StFrm, IIC_iStore_bh_ru,
2681 "strbt", "\t$Rt, $addr, $offset",
2682 "$addr.base = $Rn_wb", []> {
2688 let Inst{23} = offset{12};
2689 let Inst{21} = 1; // overwrite
2690 let Inst{19-16} = addr;
2691 let Inst{11-0} = offset{11-0};
2692 let DecoderMethod = "DecodeAddrMode2IdxInstruction";
2695 let mayStore = 1, neverHasSideEffects = 1 in {
2696 def STRT_POST_REG : AI2ldstidx<0, 0, 0, (outs GPR:$Rn_wb),
2697 (ins GPR:$Rt, addr_offset_none:$addr, am2offset_reg:$offset),
2698 IndexModePost, StFrm, IIC_iStore_ru,
2699 "strt", "\t$Rt, $addr, $offset",
2700 "$addr.base = $Rn_wb", []> {
2706 let Inst{23} = offset{12};
2707 let Inst{21} = 1; // overwrite
2708 let Inst{19-16} = addr;
2709 let Inst{11-5} = offset{11-5};
2711 let Inst{3-0} = offset{3-0};
2712 let DecoderMethod = "DecodeAddrMode2IdxInstruction";
2715 def STRT_POST_IMM : AI2ldstidx<0, 0, 0, (outs GPR:$Rn_wb),
2716 (ins GPR:$Rt, addr_offset_none:$addr, am2offset_imm:$offset),
2717 IndexModePost, StFrm, IIC_iStore_ru,
2718 "strt", "\t$Rt, $addr, $offset",
2719 "$addr.base = $Rn_wb", []> {
2725 let Inst{23} = offset{12};
2726 let Inst{21} = 1; // overwrite
2727 let Inst{19-16} = addr;
2728 let Inst{11-0} = offset{11-0};
2729 let DecoderMethod = "DecodeAddrMode2IdxInstruction";
2734 multiclass AI3strT<bits<4> op, string opc> {
2735 def i : AI3ldstidxT<op, 0, (outs GPR:$base_wb),
2736 (ins GPR:$Rt, addr_offset_none:$addr, postidx_imm8:$offset),
2737 IndexModePost, StMiscFrm, IIC_iStore_bh_ru, opc,
2738 "\t$Rt, $addr, $offset", "$addr.base = $base_wb", []> {
2740 let Inst{23} = offset{8};
2742 let Inst{11-8} = offset{7-4};
2743 let Inst{3-0} = offset{3-0};
2744 let AsmMatchConverter = "cvtStExtTWriteBackImm";
2746 def r : AI3ldstidxT<op, 0, (outs GPR:$base_wb),
2747 (ins GPR:$Rt, addr_offset_none:$addr, postidx_reg:$Rm),
2748 IndexModePost, StMiscFrm, IIC_iStore_bh_ru, opc,
2749 "\t$Rt, $addr, $Rm", "$addr.base = $base_wb", []> {
2751 let Inst{23} = Rm{4};
2754 let Inst{3-0} = Rm{3-0};
2755 let AsmMatchConverter = "cvtStExtTWriteBackReg";
2760 defm STRHT : AI3strT<0b1011, "strht">;
2763 //===----------------------------------------------------------------------===//
2764 // Load / store multiple Instructions.
2767 multiclass arm_ldst_mult<string asm, string sfx, bit L_bit, bit P_bit, Format f,
2768 InstrItinClass itin, InstrItinClass itin_upd> {
2769 // IA is the default, so no need for an explicit suffix on the
2770 // mnemonic here. Without it is the canonical spelling.
2772 AXI4<(outs), (ins GPR:$Rn, pred:$p, reglist:$regs, variable_ops),
2773 IndexModeNone, f, itin,
2774 !strconcat(asm, "${p}\t$Rn, $regs", sfx), "", []> {
2775 let Inst{24-23} = 0b01; // Increment After
2776 let Inst{22} = P_bit;
2777 let Inst{21} = 0; // No writeback
2778 let Inst{20} = L_bit;
2781 AXI4<(outs GPR:$wb), (ins GPR:$Rn, pred:$p, reglist:$regs, variable_ops),
2782 IndexModeUpd, f, itin_upd,
2783 !strconcat(asm, "${p}\t$Rn!, $regs", sfx), "$Rn = $wb", []> {
2784 let Inst{24-23} = 0b01; // Increment After
2785 let Inst{22} = P_bit;
2786 let Inst{21} = 1; // Writeback
2787 let Inst{20} = L_bit;
2789 let DecoderMethod = "DecodeMemMultipleWritebackInstruction";
2792 AXI4<(outs), (ins GPR:$Rn, pred:$p, reglist:$regs, variable_ops),
2793 IndexModeNone, f, itin,
2794 !strconcat(asm, "da${p}\t$Rn, $regs", sfx), "", []> {
2795 let Inst{24-23} = 0b00; // Decrement After
2796 let Inst{22} = P_bit;
2797 let Inst{21} = 0; // No writeback
2798 let Inst{20} = L_bit;
2801 AXI4<(outs GPR:$wb), (ins GPR:$Rn, pred:$p, reglist:$regs, variable_ops),
2802 IndexModeUpd, f, itin_upd,
2803 !strconcat(asm, "da${p}\t$Rn!, $regs", sfx), "$Rn = $wb", []> {
2804 let Inst{24-23} = 0b00; // Decrement After
2805 let Inst{22} = P_bit;
2806 let Inst{21} = 1; // Writeback
2807 let Inst{20} = L_bit;
2809 let DecoderMethod = "DecodeMemMultipleWritebackInstruction";
2812 AXI4<(outs), (ins GPR:$Rn, pred:$p, reglist:$regs, variable_ops),
2813 IndexModeNone, f, itin,
2814 !strconcat(asm, "db${p}\t$Rn, $regs", sfx), "", []> {
2815 let Inst{24-23} = 0b10; // Decrement Before
2816 let Inst{22} = P_bit;
2817 let Inst{21} = 0; // No writeback
2818 let Inst{20} = L_bit;
2821 AXI4<(outs GPR:$wb), (ins GPR:$Rn, pred:$p, reglist:$regs, variable_ops),
2822 IndexModeUpd, f, itin_upd,
2823 !strconcat(asm, "db${p}\t$Rn!, $regs", sfx), "$Rn = $wb", []> {
2824 let Inst{24-23} = 0b10; // Decrement Before
2825 let Inst{22} = P_bit;
2826 let Inst{21} = 1; // Writeback
2827 let Inst{20} = L_bit;
2829 let DecoderMethod = "DecodeMemMultipleWritebackInstruction";
2832 AXI4<(outs), (ins GPR:$Rn, pred:$p, reglist:$regs, variable_ops),
2833 IndexModeNone, f, itin,
2834 !strconcat(asm, "ib${p}\t$Rn, $regs", sfx), "", []> {
2835 let Inst{24-23} = 0b11; // Increment Before
2836 let Inst{22} = P_bit;
2837 let Inst{21} = 0; // No writeback
2838 let Inst{20} = L_bit;
2841 AXI4<(outs GPR:$wb), (ins GPR:$Rn, pred:$p, reglist:$regs, variable_ops),
2842 IndexModeUpd, f, itin_upd,
2843 !strconcat(asm, "ib${p}\t$Rn!, $regs", sfx), "$Rn = $wb", []> {
2844 let Inst{24-23} = 0b11; // Increment Before
2845 let Inst{22} = P_bit;
2846 let Inst{21} = 1; // Writeback
2847 let Inst{20} = L_bit;
2849 let DecoderMethod = "DecodeMemMultipleWritebackInstruction";
2853 let neverHasSideEffects = 1 in {
2855 let mayLoad = 1, hasExtraDefRegAllocReq = 1 in
2856 defm LDM : arm_ldst_mult<"ldm", "", 1, 0, LdStMulFrm, IIC_iLoad_m,
2859 let mayStore = 1, hasExtraSrcRegAllocReq = 1 in
2860 defm STM : arm_ldst_mult<"stm", "", 0, 0, LdStMulFrm, IIC_iStore_m,
2863 } // neverHasSideEffects
2865 // FIXME: remove when we have a way to marking a MI with these properties.
2866 // FIXME: Should pc be an implicit operand like PICADD, etc?
2867 let isReturn = 1, isTerminator = 1, isBarrier = 1, mayLoad = 1,
2868 hasExtraDefRegAllocReq = 1, isCodeGenOnly = 1 in
2869 def LDMIA_RET : ARMPseudoExpand<(outs GPR:$wb), (ins GPR:$Rn, pred:$p,
2870 reglist:$regs, variable_ops),
2871 4, IIC_iLoad_mBr, [],
2872 (LDMIA_UPD GPR:$wb, GPR:$Rn, pred:$p, reglist:$regs)>,
2873 RegConstraint<"$Rn = $wb">;
2875 let mayLoad = 1, hasExtraDefRegAllocReq = 1 in
2876 defm sysLDM : arm_ldst_mult<"ldm", " ^", 1, 1, LdStMulFrm, IIC_iLoad_m,
2879 let mayStore = 1, hasExtraSrcRegAllocReq = 1 in
2880 defm sysSTM : arm_ldst_mult<"stm", " ^", 0, 1, LdStMulFrm, IIC_iStore_m,
2885 //===----------------------------------------------------------------------===//
2886 // Move Instructions.
2889 let neverHasSideEffects = 1 in
2890 def MOVr : AsI1<0b1101, (outs GPR:$Rd), (ins GPR:$Rm), DPFrm, IIC_iMOVr,
2891 "mov", "\t$Rd, $Rm", []>, UnaryDP {
2895 let Inst{19-16} = 0b0000;
2896 let Inst{11-4} = 0b00000000;
2899 let Inst{15-12} = Rd;
2902 // A version for the smaller set of tail call registers.
2903 let neverHasSideEffects = 1 in
2904 def MOVr_TC : AsI1<0b1101, (outs tcGPR:$Rd), (ins tcGPR:$Rm), DPFrm,
2905 IIC_iMOVr, "mov", "\t$Rd, $Rm", []>, UnaryDP {
2909 let Inst{11-4} = 0b00000000;
2912 let Inst{15-12} = Rd;
2915 def MOVsr : AsI1<0b1101, (outs GPRnopc:$Rd), (ins shift_so_reg_reg:$src),
2916 DPSoRegRegFrm, IIC_iMOVsr,
2917 "mov", "\t$Rd, $src",
2918 [(set GPRnopc:$Rd, shift_so_reg_reg:$src)]>, UnaryDP {
2921 let Inst{15-12} = Rd;
2922 let Inst{19-16} = 0b0000;
2923 let Inst{11-8} = src{11-8};
2925 let Inst{6-5} = src{6-5};
2927 let Inst{3-0} = src{3-0};
2931 def MOVsi : AsI1<0b1101, (outs GPR:$Rd), (ins shift_so_reg_imm:$src),
2932 DPSoRegImmFrm, IIC_iMOVsr,
2933 "mov", "\t$Rd, $src", [(set GPR:$Rd, shift_so_reg_imm:$src)]>,
2937 let Inst{15-12} = Rd;
2938 let Inst{19-16} = 0b0000;
2939 let Inst{11-5} = src{11-5};
2941 let Inst{3-0} = src{3-0};
2945 let isReMaterializable = 1, isAsCheapAsAMove = 1, isMoveImm = 1 in
2946 def MOVi : AsI1<0b1101, (outs GPR:$Rd), (ins so_imm:$imm), DPFrm, IIC_iMOVi,
2947 "mov", "\t$Rd, $imm", [(set GPR:$Rd, so_imm:$imm)]>, UnaryDP {
2951 let Inst{15-12} = Rd;
2952 let Inst{19-16} = 0b0000;
2953 let Inst{11-0} = imm;
2956 let isReMaterializable = 1, isAsCheapAsAMove = 1, isMoveImm = 1 in
2957 def MOVi16 : AI1<0b1000, (outs GPR:$Rd), (ins imm0_65535_expr:$imm),
2959 "movw", "\t$Rd, $imm",
2960 [(set GPR:$Rd, imm0_65535:$imm)]>,
2961 Requires<[IsARM, HasV6T2]>, UnaryDP {
2964 let Inst{15-12} = Rd;
2965 let Inst{11-0} = imm{11-0};
2966 let Inst{19-16} = imm{15-12};
2969 let DecoderMethod = "DecodeArmMOVTWInstruction";
2972 def : InstAlias<"mov${p} $Rd, $imm",
2973 (MOVi16 GPR:$Rd, imm0_65535_expr:$imm, pred:$p)>,
2976 def MOVi16_ga_pcrel : PseudoInst<(outs GPR:$Rd),
2977 (ins i32imm:$addr, pclabel:$id), IIC_iMOVi, []>;
2979 let Constraints = "$src = $Rd" in {
2980 def MOVTi16 : AI1<0b1010, (outs GPRnopc:$Rd),
2981 (ins GPR:$src, imm0_65535_expr:$imm),
2983 "movt", "\t$Rd, $imm",
2985 (or (and GPR:$src, 0xffff),
2986 lo16AllZero:$imm))]>, UnaryDP,
2987 Requires<[IsARM, HasV6T2]> {
2990 let Inst{15-12} = Rd;
2991 let Inst{11-0} = imm{11-0};
2992 let Inst{19-16} = imm{15-12};
2995 let DecoderMethod = "DecodeArmMOVTWInstruction";
2998 def MOVTi16_ga_pcrel : PseudoInst<(outs GPR:$Rd),
2999 (ins GPR:$src, i32imm:$addr, pclabel:$id), IIC_iMOVi, []>;
3003 def : ARMPat<(or GPR:$src, 0xffff0000), (MOVTi16 GPR:$src, 0xffff)>,
3004 Requires<[IsARM, HasV6T2]>;
3006 let Uses = [CPSR] in
3007 def RRX: PseudoInst<(outs GPR:$Rd), (ins GPR:$Rm), IIC_iMOVsi,
3008 [(set GPR:$Rd, (ARMrrx GPR:$Rm))]>, UnaryDP,
3011 // These aren't really mov instructions, but we have to define them this way
3012 // due to flag operands.
3014 let Defs = [CPSR] in {
3015 def MOVsrl_flag : PseudoInst<(outs GPR:$dst), (ins GPR:$src), IIC_iMOVsi,
3016 [(set GPR:$dst, (ARMsrl_flag GPR:$src))]>, UnaryDP,
3018 def MOVsra_flag : PseudoInst<(outs GPR:$dst), (ins GPR:$src), IIC_iMOVsi,
3019 [(set GPR:$dst, (ARMsra_flag GPR:$src))]>, UnaryDP,
3023 //===----------------------------------------------------------------------===//
3024 // Extend Instructions.
3029 def SXTB : AI_ext_rrot<0b01101010,
3030 "sxtb", UnOpFrag<(sext_inreg node:$Src, i8)>>;
3031 def SXTH : AI_ext_rrot<0b01101011,
3032 "sxth", UnOpFrag<(sext_inreg node:$Src, i16)>>;
3034 def SXTAB : AI_exta_rrot<0b01101010,
3035 "sxtab", BinOpFrag<(add node:$LHS, (sext_inreg node:$RHS, i8))>>;
3036 def SXTAH : AI_exta_rrot<0b01101011,
3037 "sxtah", BinOpFrag<(add node:$LHS, (sext_inreg node:$RHS,i16))>>;
3039 def SXTB16 : AI_ext_rrot_np<0b01101000, "sxtb16">;
3041 def SXTAB16 : AI_exta_rrot_np<0b01101000, "sxtab16">;
3045 let AddedComplexity = 16 in {
3046 def UXTB : AI_ext_rrot<0b01101110,
3047 "uxtb" , UnOpFrag<(and node:$Src, 0x000000FF)>>;
3048 def UXTH : AI_ext_rrot<0b01101111,
3049 "uxth" , UnOpFrag<(and node:$Src, 0x0000FFFF)>>;
3050 def UXTB16 : AI_ext_rrot<0b01101100,
3051 "uxtb16", UnOpFrag<(and node:$Src, 0x00FF00FF)>>;
3053 // FIXME: This pattern incorrectly assumes the shl operator is a rotate.
3054 // The transformation should probably be done as a combiner action
3055 // instead so we can include a check for masking back in the upper
3056 // eight bits of the source into the lower eight bits of the result.
3057 //def : ARMV6Pat<(and (shl GPR:$Src, (i32 8)), 0xFF00FF),
3058 // (UXTB16r_rot GPR:$Src, 3)>;
3059 def : ARMV6Pat<(and (srl GPR:$Src, (i32 8)), 0xFF00FF),
3060 (UXTB16 GPR:$Src, 1)>;
3062 def UXTAB : AI_exta_rrot<0b01101110, "uxtab",
3063 BinOpFrag<(add node:$LHS, (and node:$RHS, 0x00FF))>>;
3064 def UXTAH : AI_exta_rrot<0b01101111, "uxtah",
3065 BinOpFrag<(add node:$LHS, (and node:$RHS, 0xFFFF))>>;
3068 // This isn't safe in general, the add is two 16-bit units, not a 32-bit add.
3069 def UXTAB16 : AI_exta_rrot_np<0b01101100, "uxtab16">;
3072 def SBFX : I<(outs GPRnopc:$Rd),
3073 (ins GPRnopc:$Rn, imm0_31:$lsb, imm1_32:$width),
3074 AddrMode1, 4, IndexModeNone, DPFrm, IIC_iUNAsi,
3075 "sbfx", "\t$Rd, $Rn, $lsb, $width", "", []>,
3076 Requires<[IsARM, HasV6T2]> {
3081 let Inst{27-21} = 0b0111101;
3082 let Inst{6-4} = 0b101;
3083 let Inst{20-16} = width;
3084 let Inst{15-12} = Rd;
3085 let Inst{11-7} = lsb;
3089 def UBFX : I<(outs GPR:$Rd),
3090 (ins GPR:$Rn, imm0_31:$lsb, imm1_32:$width),
3091 AddrMode1, 4, IndexModeNone, DPFrm, IIC_iUNAsi,
3092 "ubfx", "\t$Rd, $Rn, $lsb, $width", "", []>,
3093 Requires<[IsARM, HasV6T2]> {
3098 let Inst{27-21} = 0b0111111;
3099 let Inst{6-4} = 0b101;
3100 let Inst{20-16} = width;
3101 let Inst{15-12} = Rd;
3102 let Inst{11-7} = lsb;
3106 //===----------------------------------------------------------------------===//
3107 // Arithmetic Instructions.
3110 defm ADD : AsI1_bin_irs<0b0100, "add",
3111 IIC_iALUi, IIC_iALUr, IIC_iALUsr,
3112 BinOpFrag<(add node:$LHS, node:$RHS)>, 1>;
3113 defm SUB : AsI1_bin_irs<0b0010, "sub",
3114 IIC_iALUi, IIC_iALUr, IIC_iALUsr,
3115 BinOpFrag<(sub node:$LHS, node:$RHS)>>;
3117 // ADD and SUB with 's' bit set.
3119 // Currently, ADDS/SUBS are pseudo opcodes that exist only in the
3120 // selection DAG. They are "lowered" to real ADD/SUB opcodes by
3121 // AdjustInstrPostInstrSelection where we determine whether or not to
3122 // set the "s" bit based on CPSR liveness.
3124 // FIXME: Eliminate ADDS/SUBS pseudo opcodes after adding tablegen
3125 // support for an optional CPSR definition that corresponds to the DAG
3126 // node's second value. We can then eliminate the implicit def of CPSR.
3127 defm ADDS : AsI1_bin_s_irs<IIC_iALUi, IIC_iALUr, IIC_iALUsr,
3128 BinOpFrag<(ARMaddc node:$LHS, node:$RHS)>, 1>;
3129 defm SUBS : AsI1_bin_s_irs<IIC_iALUi, IIC_iALUr, IIC_iALUsr,
3130 BinOpFrag<(ARMsubc node:$LHS, node:$RHS)>>;
3132 defm ADC : AI1_adde_sube_irs<0b0101, "adc",
3133 BinOpWithFlagFrag<(ARMadde node:$LHS, node:$RHS, node:$FLAG)>, 1>;
3134 defm SBC : AI1_adde_sube_irs<0b0110, "sbc",
3135 BinOpWithFlagFrag<(ARMsube node:$LHS, node:$RHS, node:$FLAG)>>;
3137 defm RSB : AsI1_rbin_irs<0b0011, "rsb",
3138 IIC_iALUi, IIC_iALUr, IIC_iALUsr,
3139 BinOpFrag<(sub node:$LHS, node:$RHS)>>;
3141 // FIXME: Eliminate them if we can write def : Pat patterns which defines
3142 // CPSR and the implicit def of CPSR is not needed.
3143 defm RSBS : AsI1_rbin_s_is<IIC_iALUi, IIC_iALUr, IIC_iALUsr,
3144 BinOpFrag<(ARMsubc node:$LHS, node:$RHS)>>;
3146 defm RSC : AI1_rsc_irs<0b0111, "rsc",
3147 BinOpWithFlagFrag<(ARMsube node:$LHS, node:$RHS, node:$FLAG)>>;
3149 // (sub X, imm) gets canonicalized to (add X, -imm). Match this form.
3150 // The assume-no-carry-in form uses the negation of the input since add/sub
3151 // assume opposite meanings of the carry flag (i.e., carry == !borrow).
3152 // See the definition of AddWithCarry() in the ARM ARM A2.2.1 for the gory
3154 def : ARMPat<(add GPR:$src, so_imm_neg:$imm),
3155 (SUBri GPR:$src, so_imm_neg:$imm)>;
3156 def : ARMPat<(ARMaddc GPR:$src, so_imm_neg:$imm),
3157 (SUBSri GPR:$src, so_imm_neg:$imm)>;
3159 def : ARMPat<(add GPR:$src, imm0_65535_neg:$imm),
3160 (SUBrr GPR:$src, (MOVi16 (imm_neg_XFORM imm:$imm)))>,
3161 Requires<[IsARM, HasV6T2]>;
3162 def : ARMPat<(ARMaddc GPR:$src, imm0_65535_neg:$imm),
3163 (SUBSrr GPR:$src, (MOVi16 (imm_neg_XFORM imm:$imm)))>,
3164 Requires<[IsARM, HasV6T2]>;
3166 // The with-carry-in form matches bitwise not instead of the negation.
3167 // Effectively, the inverse interpretation of the carry flag already accounts
3168 // for part of the negation.
3169 def : ARMPat<(ARMadde GPR:$src, so_imm_not:$imm, CPSR),
3170 (SBCri GPR:$src, so_imm_not:$imm)>;
3171 def : ARMPat<(ARMadde GPR:$src, imm0_65535_neg:$imm, CPSR),
3172 (SBCrr GPR:$src, (MOVi16 (imm_not_XFORM imm:$imm)))>;
3174 // Note: These are implemented in C++ code, because they have to generate
3175 // ADD/SUBrs instructions, which use a complex pattern that a xform function
3177 // (mul X, 2^n+1) -> (add (X << n), X)
3178 // (mul X, 2^n-1) -> (rsb X, (X << n))
3180 // ARM Arithmetic Instruction
3181 // GPR:$dst = GPR:$a op GPR:$b
3182 class AAI<bits<8> op27_20, bits<8> op11_4, string opc,
3183 list<dag> pattern = [],
3184 dag iops = (ins GPRnopc:$Rn, GPRnopc:$Rm),
3185 string asm = "\t$Rd, $Rn, $Rm">
3186 : AI<(outs GPRnopc:$Rd), iops, DPFrm, IIC_iALUr, opc, asm, pattern> {
3190 let Inst{27-20} = op27_20;
3191 let Inst{11-4} = op11_4;
3192 let Inst{19-16} = Rn;
3193 let Inst{15-12} = Rd;
3196 let Unpredictable{11-8} = 0b1111;
3199 // Saturating add/subtract
3201 def QADD : AAI<0b00010000, 0b00000101, "qadd",
3202 [(set GPRnopc:$Rd, (int_arm_qadd GPRnopc:$Rm, GPRnopc:$Rn))],
3203 (ins GPRnopc:$Rm, GPRnopc:$Rn), "\t$Rd, $Rm, $Rn">;
3204 def QSUB : AAI<0b00010010, 0b00000101, "qsub",
3205 [(set GPRnopc:$Rd, (int_arm_qsub GPRnopc:$Rm, GPRnopc:$Rn))],
3206 (ins GPRnopc:$Rm, GPRnopc:$Rn), "\t$Rd, $Rm, $Rn">;
3207 def QDADD : AAI<0b00010100, 0b00000101, "qdadd", [],
3208 (ins GPRnopc:$Rm, GPRnopc:$Rn),
3210 def QDSUB : AAI<0b00010110, 0b00000101, "qdsub", [],
3211 (ins GPRnopc:$Rm, GPRnopc:$Rn),
3214 def QADD16 : AAI<0b01100010, 0b11110001, "qadd16">;
3215 def QADD8 : AAI<0b01100010, 0b11111001, "qadd8">;
3216 def QASX : AAI<0b01100010, 0b11110011, "qasx">;
3217 def QSAX : AAI<0b01100010, 0b11110101, "qsax">;
3218 def QSUB16 : AAI<0b01100010, 0b11110111, "qsub16">;
3219 def QSUB8 : AAI<0b01100010, 0b11111111, "qsub8">;
3220 def UQADD16 : AAI<0b01100110, 0b11110001, "uqadd16">;
3221 def UQADD8 : AAI<0b01100110, 0b11111001, "uqadd8">;
3222 def UQASX : AAI<0b01100110, 0b11110011, "uqasx">;
3223 def UQSAX : AAI<0b01100110, 0b11110101, "uqsax">;
3224 def UQSUB16 : AAI<0b01100110, 0b11110111, "uqsub16">;
3225 def UQSUB8 : AAI<0b01100110, 0b11111111, "uqsub8">;
3227 // Signed/Unsigned add/subtract
3229 def SASX : AAI<0b01100001, 0b11110011, "sasx">;
3230 def SADD16 : AAI<0b01100001, 0b11110001, "sadd16">;
3231 def SADD8 : AAI<0b01100001, 0b11111001, "sadd8">;
3232 def SSAX : AAI<0b01100001, 0b11110101, "ssax">;
3233 def SSUB16 : AAI<0b01100001, 0b11110111, "ssub16">;
3234 def SSUB8 : AAI<0b01100001, 0b11111111, "ssub8">;
3235 def UASX : AAI<0b01100101, 0b11110011, "uasx">;
3236 def UADD16 : AAI<0b01100101, 0b11110001, "uadd16">;
3237 def UADD8 : AAI<0b01100101, 0b11111001, "uadd8">;
3238 def USAX : AAI<0b01100101, 0b11110101, "usax">;
3239 def USUB16 : AAI<0b01100101, 0b11110111, "usub16">;
3240 def USUB8 : AAI<0b01100101, 0b11111111, "usub8">;
3242 // Signed/Unsigned halving add/subtract
3244 def SHASX : AAI<0b01100011, 0b11110011, "shasx">;
3245 def SHADD16 : AAI<0b01100011, 0b11110001, "shadd16">;
3246 def SHADD8 : AAI<0b01100011, 0b11111001, "shadd8">;
3247 def SHSAX : AAI<0b01100011, 0b11110101, "shsax">;
3248 def SHSUB16 : AAI<0b01100011, 0b11110111, "shsub16">;
3249 def SHSUB8 : AAI<0b01100011, 0b11111111, "shsub8">;
3250 def UHASX : AAI<0b01100111, 0b11110011, "uhasx">;
3251 def UHADD16 : AAI<0b01100111, 0b11110001, "uhadd16">;
3252 def UHADD8 : AAI<0b01100111, 0b11111001, "uhadd8">;
3253 def UHSAX : AAI<0b01100111, 0b11110101, "uhsax">;
3254 def UHSUB16 : AAI<0b01100111, 0b11110111, "uhsub16">;
3255 def UHSUB8 : AAI<0b01100111, 0b11111111, "uhsub8">;
3257 // Unsigned Sum of Absolute Differences [and Accumulate].
3259 def USAD8 : AI<(outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm),
3260 MulFrm /* for convenience */, NoItinerary, "usad8",
3261 "\t$Rd, $Rn, $Rm", []>,
3262 Requires<[IsARM, HasV6]> {
3266 let Inst{27-20} = 0b01111000;
3267 let Inst{15-12} = 0b1111;
3268 let Inst{7-4} = 0b0001;
3269 let Inst{19-16} = Rd;
3270 let Inst{11-8} = Rm;
3273 def USADA8 : AI<(outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm, GPR:$Ra),
3274 MulFrm /* for convenience */, NoItinerary, "usada8",
3275 "\t$Rd, $Rn, $Rm, $Ra", []>,
3276 Requires<[IsARM, HasV6]> {
3281 let Inst{27-20} = 0b01111000;
3282 let Inst{7-4} = 0b0001;
3283 let Inst{19-16} = Rd;
3284 let Inst{15-12} = Ra;
3285 let Inst{11-8} = Rm;
3289 // Signed/Unsigned saturate
3291 def SSAT : AI<(outs GPRnopc:$Rd),
3292 (ins imm1_32:$sat_imm, GPRnopc:$Rn, shift_imm:$sh),
3293 SatFrm, NoItinerary, "ssat", "\t$Rd, $sat_imm, $Rn$sh", []> {
3298 let Inst{27-21} = 0b0110101;
3299 let Inst{5-4} = 0b01;
3300 let Inst{20-16} = sat_imm;
3301 let Inst{15-12} = Rd;
3302 let Inst{11-7} = sh{4-0};
3303 let Inst{6} = sh{5};
3307 def SSAT16 : AI<(outs GPRnopc:$Rd),
3308 (ins imm1_16:$sat_imm, GPRnopc:$Rn), SatFrm,
3309 NoItinerary, "ssat16", "\t$Rd, $sat_imm, $Rn", []> {
3313 let Inst{27-20} = 0b01101010;
3314 let Inst{11-4} = 0b11110011;
3315 let Inst{15-12} = Rd;
3316 let Inst{19-16} = sat_imm;
3320 def USAT : AI<(outs GPRnopc:$Rd),
3321 (ins imm0_31:$sat_imm, GPRnopc:$Rn, shift_imm:$sh),
3322 SatFrm, NoItinerary, "usat", "\t$Rd, $sat_imm, $Rn$sh", []> {
3327 let Inst{27-21} = 0b0110111;
3328 let Inst{5-4} = 0b01;
3329 let Inst{15-12} = Rd;
3330 let Inst{11-7} = sh{4-0};
3331 let Inst{6} = sh{5};
3332 let Inst{20-16} = sat_imm;
3336 def USAT16 : AI<(outs GPRnopc:$Rd),
3337 (ins imm0_15:$sat_imm, GPRnopc:$Rn), SatFrm,
3338 NoItinerary, "usat16", "\t$Rd, $sat_imm, $Rn", []> {
3342 let Inst{27-20} = 0b01101110;
3343 let Inst{11-4} = 0b11110011;
3344 let Inst{15-12} = Rd;
3345 let Inst{19-16} = sat_imm;
3349 def : ARMV6Pat<(int_arm_ssat GPRnopc:$a, imm:$pos),
3350 (SSAT imm:$pos, GPRnopc:$a, 0)>;
3351 def : ARMV6Pat<(int_arm_usat GPRnopc:$a, imm:$pos),
3352 (USAT imm:$pos, GPRnopc:$a, 0)>;
3354 //===----------------------------------------------------------------------===//
3355 // Bitwise Instructions.
3358 defm AND : AsI1_bin_irs<0b0000, "and",
3359 IIC_iBITi, IIC_iBITr, IIC_iBITsr,
3360 BinOpFrag<(and node:$LHS, node:$RHS)>, 1>;
3361 defm ORR : AsI1_bin_irs<0b1100, "orr",
3362 IIC_iBITi, IIC_iBITr, IIC_iBITsr,
3363 BinOpFrag<(or node:$LHS, node:$RHS)>, 1>;
3364 defm EOR : AsI1_bin_irs<0b0001, "eor",
3365 IIC_iBITi, IIC_iBITr, IIC_iBITsr,
3366 BinOpFrag<(xor node:$LHS, node:$RHS)>, 1>;
3367 defm BIC : AsI1_bin_irs<0b1110, "bic",
3368 IIC_iBITi, IIC_iBITr, IIC_iBITsr,
3369 BinOpFrag<(and node:$LHS, (not node:$RHS))>>;
3371 // FIXME: bf_inv_mask_imm should be two operands, the lsb and the msb, just
3372 // like in the actual instruction encoding. The complexity of mapping the mask
3373 // to the lsb/msb pair should be handled by ISel, not encapsulated in the
3374 // instruction description.
3375 def BFC : I<(outs GPR:$Rd), (ins GPR:$src, bf_inv_mask_imm:$imm),
3376 AddrMode1, 4, IndexModeNone, DPFrm, IIC_iUNAsi,
3377 "bfc", "\t$Rd, $imm", "$src = $Rd",
3378 [(set GPR:$Rd, (and GPR:$src, bf_inv_mask_imm:$imm))]>,
3379 Requires<[IsARM, HasV6T2]> {
3382 let Inst{27-21} = 0b0111110;
3383 let Inst{6-0} = 0b0011111;
3384 let Inst{15-12} = Rd;
3385 let Inst{11-7} = imm{4-0}; // lsb
3386 let Inst{20-16} = imm{9-5}; // msb
3389 // A8.6.18 BFI - Bitfield insert (Encoding A1)
3390 def BFI:I<(outs GPRnopc:$Rd), (ins GPRnopc:$src, GPR:$Rn, bf_inv_mask_imm:$imm),
3391 AddrMode1, 4, IndexModeNone, DPFrm, IIC_iUNAsi,
3392 "bfi", "\t$Rd, $Rn, $imm", "$src = $Rd",
3393 [(set GPRnopc:$Rd, (ARMbfi GPRnopc:$src, GPR:$Rn,
3394 bf_inv_mask_imm:$imm))]>,
3395 Requires<[IsARM, HasV6T2]> {
3399 let Inst{27-21} = 0b0111110;
3400 let Inst{6-4} = 0b001; // Rn: Inst{3-0} != 15
3401 let Inst{15-12} = Rd;
3402 let Inst{11-7} = imm{4-0}; // lsb
3403 let Inst{20-16} = imm{9-5}; // width
3407 def MVNr : AsI1<0b1111, (outs GPR:$Rd), (ins GPR:$Rm), DPFrm, IIC_iMVNr,
3408 "mvn", "\t$Rd, $Rm",
3409 [(set GPR:$Rd, (not GPR:$Rm))]>, UnaryDP {
3413 let Inst{19-16} = 0b0000;
3414 let Inst{11-4} = 0b00000000;
3415 let Inst{15-12} = Rd;
3418 def MVNsi : AsI1<0b1111, (outs GPR:$Rd), (ins so_reg_imm:$shift),
3419 DPSoRegImmFrm, IIC_iMVNsr, "mvn", "\t$Rd, $shift",
3420 [(set GPR:$Rd, (not so_reg_imm:$shift))]>, UnaryDP {
3424 let Inst{19-16} = 0b0000;
3425 let Inst{15-12} = Rd;
3426 let Inst{11-5} = shift{11-5};
3428 let Inst{3-0} = shift{3-0};
3430 def MVNsr : AsI1<0b1111, (outs GPR:$Rd), (ins so_reg_reg:$shift),
3431 DPSoRegRegFrm, IIC_iMVNsr, "mvn", "\t$Rd, $shift",
3432 [(set GPR:$Rd, (not so_reg_reg:$shift))]>, UnaryDP {
3436 let Inst{19-16} = 0b0000;
3437 let Inst{15-12} = Rd;
3438 let Inst{11-8} = shift{11-8};
3440 let Inst{6-5} = shift{6-5};
3442 let Inst{3-0} = shift{3-0};
3444 let isReMaterializable = 1, isAsCheapAsAMove = 1, isMoveImm = 1 in
3445 def MVNi : AsI1<0b1111, (outs GPR:$Rd), (ins so_imm:$imm), DPFrm,
3446 IIC_iMVNi, "mvn", "\t$Rd, $imm",
3447 [(set GPR:$Rd, so_imm_not:$imm)]>,UnaryDP {
3451 let Inst{19-16} = 0b0000;
3452 let Inst{15-12} = Rd;
3453 let Inst{11-0} = imm;
3456 def : ARMPat<(and GPR:$src, so_imm_not:$imm),
3457 (BICri GPR:$src, so_imm_not:$imm)>;
3459 //===----------------------------------------------------------------------===//
3460 // Multiply Instructions.
3462 class AsMul1I32<bits<7> opcod, dag oops, dag iops, InstrItinClass itin,
3463 string opc, string asm, list<dag> pattern>
3464 : AsMul1I<opcod, oops, iops, itin, opc, asm, pattern> {
3468 let Inst{19-16} = Rd;
3469 let Inst{11-8} = Rm;
3472 class AsMul1I64<bits<7> opcod, dag oops, dag iops, InstrItinClass itin,
3473 string opc, string asm, list<dag> pattern>
3474 : AsMul1I<opcod, oops, iops, itin, opc, asm, pattern> {
3479 let Inst{19-16} = RdHi;
3480 let Inst{15-12} = RdLo;
3481 let Inst{11-8} = Rm;
3484 class AsMla1I64<bits<7> opcod, dag oops, dag iops, InstrItinClass itin,
3485 string opc, string asm, list<dag> pattern>
3486 : AsMul1I<opcod, oops, iops, itin, opc, asm, pattern> {
3491 let Inst{19-16} = RdHi;
3492 let Inst{15-12} = RdLo;
3493 let Inst{11-8} = Rm;
3497 // FIXME: The v5 pseudos are only necessary for the additional Constraint
3498 // property. Remove them when it's possible to add those properties
3499 // on an individual MachineInstr, not just an instruction description.
3500 let isCommutable = 1, TwoOperandAliasConstraint = "$Rn = $Rd" in {
3501 def MUL : AsMul1I32<0b0000000, (outs GPRnopc:$Rd),
3502 (ins GPRnopc:$Rn, GPRnopc:$Rm),
3503 IIC_iMUL32, "mul", "\t$Rd, $Rn, $Rm",
3504 [(set GPRnopc:$Rd, (mul GPRnopc:$Rn, GPRnopc:$Rm))]>,
3505 Requires<[IsARM, HasV6]> {
3506 let Inst{15-12} = 0b0000;
3507 let Unpredictable{15-12} = 0b1111;
3510 let Constraints = "@earlyclobber $Rd" in
3511 def MULv5: ARMPseudoExpand<(outs GPRnopc:$Rd), (ins GPRnopc:$Rn, GPRnopc:$Rm,
3512 pred:$p, cc_out:$s),
3514 [(set GPRnopc:$Rd, (mul GPRnopc:$Rn, GPRnopc:$Rm))],
3515 (MUL GPRnopc:$Rd, GPRnopc:$Rn, GPRnopc:$Rm, pred:$p, cc_out:$s)>,
3516 Requires<[IsARM, NoV6, UseMulOps]>;
3519 def MLA : AsMul1I32<0b0000001, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm, GPR:$Ra),
3520 IIC_iMAC32, "mla", "\t$Rd, $Rn, $Rm, $Ra",
3521 [(set GPR:$Rd, (add (mul GPR:$Rn, GPR:$Rm), GPR:$Ra))]>,
3522 Requires<[IsARM, HasV6, UseMulOps]> {
3524 let Inst{15-12} = Ra;
3527 let Constraints = "@earlyclobber $Rd" in
3528 def MLAv5: ARMPseudoExpand<(outs GPR:$Rd),
3529 (ins GPR:$Rn, GPR:$Rm, GPR:$Ra, pred:$p, cc_out:$s),
3531 [(set GPR:$Rd, (add (mul GPR:$Rn, GPR:$Rm), GPR:$Ra))],
3532 (MLA GPR:$Rd, GPR:$Rn, GPR:$Rm, GPR:$Ra, pred:$p, cc_out:$s)>,
3533 Requires<[IsARM, NoV6]>;
3535 def MLS : AMul1I<0b0000011, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm, GPR:$Ra),
3536 IIC_iMAC32, "mls", "\t$Rd, $Rn, $Rm, $Ra",
3537 [(set GPR:$Rd, (sub GPR:$Ra, (mul GPR:$Rn, GPR:$Rm)))]>,
3538 Requires<[IsARM, HasV6T2, UseMulOps]> {
3543 let Inst{19-16} = Rd;
3544 let Inst{15-12} = Ra;
3545 let Inst{11-8} = Rm;
3549 // Extra precision multiplies with low / high results
3550 let neverHasSideEffects = 1 in {
3551 let isCommutable = 1 in {
3552 def SMULL : AsMul1I64<0b0000110, (outs GPR:$RdLo, GPR:$RdHi),
3553 (ins GPR:$Rn, GPR:$Rm), IIC_iMUL64,
3554 "smull", "\t$RdLo, $RdHi, $Rn, $Rm", []>,
3555 Requires<[IsARM, HasV6]>;
3557 def UMULL : AsMul1I64<0b0000100, (outs GPR:$RdLo, GPR:$RdHi),
3558 (ins GPR:$Rn, GPR:$Rm), IIC_iMUL64,
3559 "umull", "\t$RdLo, $RdHi, $Rn, $Rm", []>,
3560 Requires<[IsARM, HasV6]>;
3562 let Constraints = "@earlyclobber $RdLo,@earlyclobber $RdHi" in {
3563 def SMULLv5 : ARMPseudoExpand<(outs GPR:$RdLo, GPR:$RdHi),
3564 (ins GPR:$Rn, GPR:$Rm, pred:$p, cc_out:$s),
3566 (SMULL GPR:$RdLo, GPR:$RdHi, GPR:$Rn, GPR:$Rm, pred:$p, cc_out:$s)>,
3567 Requires<[IsARM, NoV6]>;
3569 def UMULLv5 : ARMPseudoExpand<(outs GPR:$RdLo, GPR:$RdHi),
3570 (ins GPR:$Rn, GPR:$Rm, pred:$p, cc_out:$s),
3572 (UMULL GPR:$RdLo, GPR:$RdHi, GPR:$Rn, GPR:$Rm, pred:$p, cc_out:$s)>,
3573 Requires<[IsARM, NoV6]>;
3577 // Multiply + accumulate
3578 def SMLAL : AsMla1I64<0b0000111, (outs GPR:$RdLo, GPR:$RdHi),
3579 (ins GPR:$Rn, GPR:$Rm, GPR:$RLo, GPR:$RHi), IIC_iMAC64,
3580 "smlal", "\t$RdLo, $RdHi, $Rn, $Rm", []>,
3581 RegConstraint<"$RLo = $RdLo, $RHi = $RdHi">, Requires<[IsARM, HasV6]>;
3582 def UMLAL : AsMla1I64<0b0000101, (outs GPR:$RdLo, GPR:$RdHi),
3583 (ins GPR:$Rn, GPR:$Rm, GPR:$RLo, GPR:$RHi), IIC_iMAC64,
3584 "umlal", "\t$RdLo, $RdHi, $Rn, $Rm", []>,
3585 RegConstraint<"$RLo = $RdLo, $RHi = $RdHi">, Requires<[IsARM, HasV6]>;
3587 def UMAAL : AMul1I <0b0000010, (outs GPR:$RdLo, GPR:$RdHi),
3588 (ins GPR:$Rn, GPR:$Rm), IIC_iMAC64,
3589 "umaal", "\t$RdLo, $RdHi, $Rn, $Rm", []>,
3590 Requires<[IsARM, HasV6]> {
3595 let Inst{19-16} = RdHi;
3596 let Inst{15-12} = RdLo;
3597 let Inst{11-8} = Rm;
3601 let Constraints = "$RLo = $RdLo,$RHi = $RdHi" in {
3602 def SMLALv5 : ARMPseudoExpand<(outs GPR:$RdLo, GPR:$RdHi),
3603 (ins GPR:$Rn, GPR:$Rm, GPR:$RLo, GPR:$RHi, pred:$p, cc_out:$s),
3605 (SMLAL GPR:$RdLo, GPR:$RdHi, GPR:$Rn, GPR:$Rm, GPR:$RLo, GPR:$RHi,
3606 pred:$p, cc_out:$s)>,
3607 Requires<[IsARM, NoV6]>;
3608 def UMLALv5 : ARMPseudoExpand<(outs GPR:$RdLo, GPR:$RdHi),
3609 (ins GPR:$Rn, GPR:$Rm, GPR:$RLo, GPR:$RHi, pred:$p, cc_out:$s),
3611 (UMLAL GPR:$RdLo, GPR:$RdHi, GPR:$Rn, GPR:$Rm, GPR:$RLo, GPR:$RHi,
3612 pred:$p, cc_out:$s)>,
3613 Requires<[IsARM, NoV6]>;
3616 let Constraints = "@earlyclobber $RdLo,@earlyclobber $RdHi" in {
3617 def UMAALv5 : ARMPseudoExpand<(outs GPR:$RdLo, GPR:$RdHi),
3618 (ins GPR:$Rn, GPR:$Rm, pred:$p),
3620 (UMAAL GPR:$RdLo, GPR:$RdHi, GPR:$Rn, GPR:$Rm, pred:$p)>,
3621 Requires<[IsARM, NoV6]>;
3624 } // neverHasSideEffects
3626 // Most significant word multiply
3627 def SMMUL : AMul2I <0b0111010, 0b0001, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm),
3628 IIC_iMUL32, "smmul", "\t$Rd, $Rn, $Rm",
3629 [(set GPR:$Rd, (mulhs GPR:$Rn, GPR:$Rm))]>,
3630 Requires<[IsARM, HasV6]> {
3631 let Inst{15-12} = 0b1111;
3634 def SMMULR : AMul2I <0b0111010, 0b0011, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm),
3635 IIC_iMUL32, "smmulr", "\t$Rd, $Rn, $Rm", []>,
3636 Requires<[IsARM, HasV6]> {
3637 let Inst{15-12} = 0b1111;
3640 def SMMLA : AMul2Ia <0b0111010, 0b0001, (outs GPR:$Rd),
3641 (ins GPR:$Rn, GPR:$Rm, GPR:$Ra),
3642 IIC_iMAC32, "smmla", "\t$Rd, $Rn, $Rm, $Ra",
3643 [(set GPR:$Rd, (add (mulhs GPR:$Rn, GPR:$Rm), GPR:$Ra))]>,
3644 Requires<[IsARM, HasV6, UseMulOps]>;
3646 def SMMLAR : AMul2Ia <0b0111010, 0b0011, (outs GPR:$Rd),
3647 (ins GPR:$Rn, GPR:$Rm, GPR:$Ra),
3648 IIC_iMAC32, "smmlar", "\t$Rd, $Rn, $Rm, $Ra", []>,
3649 Requires<[IsARM, HasV6]>;
3651 def SMMLS : AMul2Ia <0b0111010, 0b1101, (outs GPR:$Rd),
3652 (ins GPR:$Rn, GPR:$Rm, GPR:$Ra),
3653 IIC_iMAC32, "smmls", "\t$Rd, $Rn, $Rm, $Ra", []>,
3654 Requires<[IsARM, HasV6, UseMulOps]>;
3656 def SMMLSR : AMul2Ia <0b0111010, 0b1111, (outs GPR:$Rd),
3657 (ins GPR:$Rn, GPR:$Rm, GPR:$Ra),
3658 IIC_iMAC32, "smmlsr", "\t$Rd, $Rn, $Rm, $Ra", []>,
3659 Requires<[IsARM, HasV6]>;
3661 multiclass AI_smul<string opc, PatFrag opnode> {
3662 def BB : AMulxyI<0b0001011, 0b00, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm),
3663 IIC_iMUL16, !strconcat(opc, "bb"), "\t$Rd, $Rn, $Rm",
3664 [(set GPR:$Rd, (opnode (sext_inreg GPR:$Rn, i16),
3665 (sext_inreg GPR:$Rm, i16)))]>,
3666 Requires<[IsARM, HasV5TE]>;
3668 def BT : AMulxyI<0b0001011, 0b10, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm),
3669 IIC_iMUL16, !strconcat(opc, "bt"), "\t$Rd, $Rn, $Rm",
3670 [(set GPR:$Rd, (opnode (sext_inreg GPR:$Rn, i16),
3671 (sra GPR:$Rm, (i32 16))))]>,
3672 Requires<[IsARM, HasV5TE]>;
3674 def TB : AMulxyI<0b0001011, 0b01, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm),
3675 IIC_iMUL16, !strconcat(opc, "tb"), "\t$Rd, $Rn, $Rm",
3676 [(set GPR:$Rd, (opnode (sra GPR:$Rn, (i32 16)),
3677 (sext_inreg GPR:$Rm, i16)))]>,
3678 Requires<[IsARM, HasV5TE]>;
3680 def TT : AMulxyI<0b0001011, 0b11, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm),
3681 IIC_iMUL16, !strconcat(opc, "tt"), "\t$Rd, $Rn, $Rm",
3682 [(set GPR:$Rd, (opnode (sra GPR:$Rn, (i32 16)),
3683 (sra GPR:$Rm, (i32 16))))]>,
3684 Requires<[IsARM, HasV5TE]>;
3686 def WB : AMulxyI<0b0001001, 0b01, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm),
3687 IIC_iMUL16, !strconcat(opc, "wb"), "\t$Rd, $Rn, $Rm",
3688 [(set GPR:$Rd, (sra (opnode GPR:$Rn,
3689 (sext_inreg GPR:$Rm, i16)), (i32 16)))]>,
3690 Requires<[IsARM, HasV5TE]>;
3692 def WT : AMulxyI<0b0001001, 0b11, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm),
3693 IIC_iMUL16, !strconcat(opc, "wt"), "\t$Rd, $Rn, $Rm",
3694 [(set GPR:$Rd, (sra (opnode GPR:$Rn,
3695 (sra GPR:$Rm, (i32 16))), (i32 16)))]>,
3696 Requires<[IsARM, HasV5TE]>;
3700 multiclass AI_smla<string opc, PatFrag opnode> {
3701 let DecoderMethod = "DecodeSMLAInstruction" in {
3702 def BB : AMulxyIa<0b0001000, 0b00, (outs GPRnopc:$Rd),
3703 (ins GPRnopc:$Rn, GPRnopc:$Rm, GPR:$Ra),
3704 IIC_iMAC16, !strconcat(opc, "bb"), "\t$Rd, $Rn, $Rm, $Ra",
3705 [(set GPRnopc:$Rd, (add GPR:$Ra,
3706 (opnode (sext_inreg GPRnopc:$Rn, i16),
3707 (sext_inreg GPRnopc:$Rm, i16))))]>,
3708 Requires<[IsARM, HasV5TE, UseMulOps]>;
3710 def BT : AMulxyIa<0b0001000, 0b10, (outs GPRnopc:$Rd),
3711 (ins GPRnopc:$Rn, GPRnopc:$Rm, GPR:$Ra),
3712 IIC_iMAC16, !strconcat(opc, "bt"), "\t$Rd, $Rn, $Rm, $Ra",
3714 (add GPR:$Ra, (opnode (sext_inreg GPRnopc:$Rn, i16),
3715 (sra GPRnopc:$Rm, (i32 16)))))]>,
3716 Requires<[IsARM, HasV5TE, UseMulOps]>;
3718 def TB : AMulxyIa<0b0001000, 0b01, (outs GPRnopc:$Rd),
3719 (ins GPRnopc:$Rn, GPRnopc:$Rm, GPR:$Ra),
3720 IIC_iMAC16, !strconcat(opc, "tb"), "\t$Rd, $Rn, $Rm, $Ra",
3722 (add GPR:$Ra, (opnode (sra GPRnopc:$Rn, (i32 16)),
3723 (sext_inreg GPRnopc:$Rm, i16))))]>,
3724 Requires<[IsARM, HasV5TE, UseMulOps]>;
3726 def TT : AMulxyIa<0b0001000, 0b11, (outs GPRnopc:$Rd),
3727 (ins GPRnopc:$Rn, GPRnopc:$Rm, GPR:$Ra),
3728 IIC_iMAC16, !strconcat(opc, "tt"), "\t$Rd, $Rn, $Rm, $Ra",
3730 (add GPR:$Ra, (opnode (sra GPRnopc:$Rn, (i32 16)),
3731 (sra GPRnopc:$Rm, (i32 16)))))]>,
3732 Requires<[IsARM, HasV5TE, UseMulOps]>;
3734 def WB : AMulxyIa<0b0001001, 0b00, (outs GPRnopc:$Rd),
3735 (ins GPRnopc:$Rn, GPRnopc:$Rm, GPR:$Ra),
3736 IIC_iMAC16, !strconcat(opc, "wb"), "\t$Rd, $Rn, $Rm, $Ra",
3738 (add GPR:$Ra, (sra (opnode GPRnopc:$Rn,
3739 (sext_inreg GPRnopc:$Rm, i16)), (i32 16))))]>,
3740 Requires<[IsARM, HasV5TE, UseMulOps]>;
3742 def WT : AMulxyIa<0b0001001, 0b10, (outs GPRnopc:$Rd),
3743 (ins GPRnopc:$Rn, GPRnopc:$Rm, GPR:$Ra),
3744 IIC_iMAC16, !strconcat(opc, "wt"), "\t$Rd, $Rn, $Rm, $Ra",
3746 (add GPR:$Ra, (sra (opnode GPRnopc:$Rn,
3747 (sra GPRnopc:$Rm, (i32 16))), (i32 16))))]>,
3748 Requires<[IsARM, HasV5TE, UseMulOps]>;
3752 defm SMUL : AI_smul<"smul", BinOpFrag<(mul node:$LHS, node:$RHS)>>;
3753 defm SMLA : AI_smla<"smla", BinOpFrag<(mul node:$LHS, node:$RHS)>>;
3755 // Halfword multiply accumulate long: SMLAL<x><y>.
3756 def SMLALBB : AMulxyI64<0b0001010, 0b00, (outs GPRnopc:$RdLo, GPRnopc:$RdHi),
3757 (ins GPRnopc:$Rn, GPRnopc:$Rm),
3758 IIC_iMAC64, "smlalbb", "\t$RdLo, $RdHi, $Rn, $Rm", []>,
3759 Requires<[IsARM, HasV5TE]>;
3761 def SMLALBT : AMulxyI64<0b0001010, 0b10, (outs GPRnopc:$RdLo, GPRnopc:$RdHi),
3762 (ins GPRnopc:$Rn, GPRnopc:$Rm),
3763 IIC_iMAC64, "smlalbt", "\t$RdLo, $RdHi, $Rn, $Rm", []>,
3764 Requires<[IsARM, HasV5TE]>;
3766 def SMLALTB : AMulxyI64<0b0001010, 0b01, (outs GPRnopc:$RdLo, GPRnopc:$RdHi),
3767 (ins GPRnopc:$Rn, GPRnopc:$Rm),
3768 IIC_iMAC64, "smlaltb", "\t$RdLo, $RdHi, $Rn, $Rm", []>,
3769 Requires<[IsARM, HasV5TE]>;
3771 def SMLALTT : AMulxyI64<0b0001010, 0b11, (outs GPRnopc:$RdLo, GPRnopc:$RdHi),
3772 (ins GPRnopc:$Rn, GPRnopc:$Rm),
3773 IIC_iMAC64, "smlaltt", "\t$RdLo, $RdHi, $Rn, $Rm", []>,
3774 Requires<[IsARM, HasV5TE]>;
3776 // Helper class for AI_smld.
3777 class AMulDualIbase<bit long, bit sub, bit swap, dag oops, dag iops,
3778 InstrItinClass itin, string opc, string asm>
3779 : AI<oops, iops, MulFrm, itin, opc, asm, []>, Requires<[IsARM, HasV6]> {
3782 let Inst{27-23} = 0b01110;
3783 let Inst{22} = long;
3784 let Inst{21-20} = 0b00;
3785 let Inst{11-8} = Rm;
3792 class AMulDualI<bit long, bit sub, bit swap, dag oops, dag iops,
3793 InstrItinClass itin, string opc, string asm>
3794 : AMulDualIbase<long, sub, swap, oops, iops, itin, opc, asm> {
3796 let Inst{15-12} = 0b1111;
3797 let Inst{19-16} = Rd;
3799 class AMulDualIa<bit long, bit sub, bit swap, dag oops, dag iops,
3800 InstrItinClass itin, string opc, string asm>
3801 : AMulDualIbase<long, sub, swap, oops, iops, itin, opc, asm> {
3804 let Inst{19-16} = Rd;
3805 let Inst{15-12} = Ra;
3807 class AMulDualI64<bit long, bit sub, bit swap, dag oops, dag iops,
3808 InstrItinClass itin, string opc, string asm>
3809 : AMulDualIbase<long, sub, swap, oops, iops, itin, opc, asm> {
3812 let Inst{19-16} = RdHi;
3813 let Inst{15-12} = RdLo;
3816 multiclass AI_smld<bit sub, string opc> {
3818 def D : AMulDualIa<0, sub, 0, (outs GPRnopc:$Rd),
3819 (ins GPRnopc:$Rn, GPRnopc:$Rm, GPR:$Ra),
3820 NoItinerary, !strconcat(opc, "d"), "\t$Rd, $Rn, $Rm, $Ra">;
3822 def DX: AMulDualIa<0, sub, 1, (outs GPRnopc:$Rd),
3823 (ins GPRnopc:$Rn, GPRnopc:$Rm, GPR:$Ra),
3824 NoItinerary, !strconcat(opc, "dx"), "\t$Rd, $Rn, $Rm, $Ra">;
3826 def LD: AMulDualI64<1, sub, 0, (outs GPRnopc:$RdLo, GPRnopc:$RdHi),
3827 (ins GPRnopc:$Rn, GPRnopc:$Rm), NoItinerary,
3828 !strconcat(opc, "ld"), "\t$RdLo, $RdHi, $Rn, $Rm">;
3830 def LDX : AMulDualI64<1, sub, 1, (outs GPRnopc:$RdLo, GPRnopc:$RdHi),
3831 (ins GPRnopc:$Rn, GPRnopc:$Rm), NoItinerary,
3832 !strconcat(opc, "ldx"),"\t$RdLo, $RdHi, $Rn, $Rm">;
3836 defm SMLA : AI_smld<0, "smla">;
3837 defm SMLS : AI_smld<1, "smls">;
3839 multiclass AI_sdml<bit sub, string opc> {
3841 def D:AMulDualI<0, sub, 0, (outs GPRnopc:$Rd), (ins GPRnopc:$Rn, GPRnopc:$Rm),
3842 NoItinerary, !strconcat(opc, "d"), "\t$Rd, $Rn, $Rm">;
3843 def DX:AMulDualI<0, sub, 1, (outs GPRnopc:$Rd),(ins GPRnopc:$Rn, GPRnopc:$Rm),
3844 NoItinerary, !strconcat(opc, "dx"), "\t$Rd, $Rn, $Rm">;
3847 defm SMUA : AI_sdml<0, "smua">;
3848 defm SMUS : AI_sdml<1, "smus">;
3850 //===----------------------------------------------------------------------===//
3851 // Division Instructions (ARMv7-A with virtualization extension)
3853 def SDIV : ADivA1I<0b001, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm), IIC_iDIV,
3854 "sdiv", "\t$Rd, $Rn, $Rm",
3855 [(set GPR:$Rd, (sdiv GPR:$Rn, GPR:$Rm))]>,
3856 Requires<[IsARM, HasDivideInARM]>;
3858 def UDIV : ADivA1I<0b011, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm), IIC_iDIV,
3859 "udiv", "\t$Rd, $Rn, $Rm",
3860 [(set GPR:$Rd, (udiv GPR:$Rn, GPR:$Rm))]>,
3861 Requires<[IsARM, HasDivideInARM]>;
3863 //===----------------------------------------------------------------------===//
3864 // Misc. Arithmetic Instructions.
3867 def CLZ : AMiscA1I<0b000010110, 0b0001, (outs GPR:$Rd), (ins GPR:$Rm),
3868 IIC_iUNAr, "clz", "\t$Rd, $Rm",
3869 [(set GPR:$Rd, (ctlz GPR:$Rm))]>, Requires<[IsARM, HasV5T]>;
3871 def RBIT : AMiscA1I<0b01101111, 0b0011, (outs GPR:$Rd), (ins GPR:$Rm),
3872 IIC_iUNAr, "rbit", "\t$Rd, $Rm",
3873 [(set GPR:$Rd, (ARMrbit GPR:$Rm))]>,
3874 Requires<[IsARM, HasV6T2]>;
3876 def REV : AMiscA1I<0b01101011, 0b0011, (outs GPR:$Rd), (ins GPR:$Rm),
3877 IIC_iUNAr, "rev", "\t$Rd, $Rm",
3878 [(set GPR:$Rd, (bswap GPR:$Rm))]>, Requires<[IsARM, HasV6]>;
3880 let AddedComplexity = 5 in
3881 def REV16 : AMiscA1I<0b01101011, 0b1011, (outs GPR:$Rd), (ins GPR:$Rm),
3882 IIC_iUNAr, "rev16", "\t$Rd, $Rm",
3883 [(set GPR:$Rd, (rotr (bswap GPR:$Rm), (i32 16)))]>,
3884 Requires<[IsARM, HasV6]>;
3886 let AddedComplexity = 5 in
3887 def REVSH : AMiscA1I<0b01101111, 0b1011, (outs GPR:$Rd), (ins GPR:$Rm),
3888 IIC_iUNAr, "revsh", "\t$Rd, $Rm",
3889 [(set GPR:$Rd, (sra (bswap GPR:$Rm), (i32 16)))]>,
3890 Requires<[IsARM, HasV6]>;
3892 def : ARMV6Pat<(or (sra (shl GPR:$Rm, (i32 24)), (i32 16)),
3893 (and (srl GPR:$Rm, (i32 8)), 0xFF)),
3896 def PKHBT : APKHI<0b01101000, 0, (outs GPRnopc:$Rd),
3897 (ins GPRnopc:$Rn, GPRnopc:$Rm, pkh_lsl_amt:$sh),
3898 IIC_iALUsi, "pkhbt", "\t$Rd, $Rn, $Rm$sh",
3899 [(set GPRnopc:$Rd, (or (and GPRnopc:$Rn, 0xFFFF),
3900 (and (shl GPRnopc:$Rm, pkh_lsl_amt:$sh),
3902 Requires<[IsARM, HasV6]>;
3904 // Alternate cases for PKHBT where identities eliminate some nodes.
3905 def : ARMV6Pat<(or (and GPRnopc:$Rn, 0xFFFF), (and GPRnopc:$Rm, 0xFFFF0000)),
3906 (PKHBT GPRnopc:$Rn, GPRnopc:$Rm, 0)>;
3907 def : ARMV6Pat<(or (and GPRnopc:$Rn, 0xFFFF), (shl GPRnopc:$Rm, imm16_31:$sh)),
3908 (PKHBT GPRnopc:$Rn, GPRnopc:$Rm, imm16_31:$sh)>;
3910 // Note: Shifts of 1-15 bits will be transformed to srl instead of sra and
3911 // will match the pattern below.
3912 def PKHTB : APKHI<0b01101000, 1, (outs GPRnopc:$Rd),
3913 (ins GPRnopc:$Rn, GPRnopc:$Rm, pkh_asr_amt:$sh),
3914 IIC_iBITsi, "pkhtb", "\t$Rd, $Rn, $Rm$sh",
3915 [(set GPRnopc:$Rd, (or (and GPRnopc:$Rn, 0xFFFF0000),
3916 (and (sra GPRnopc:$Rm, pkh_asr_amt:$sh),
3918 Requires<[IsARM, HasV6]>;
3920 // Alternate cases for PKHTB where identities eliminate some nodes. Note that
3921 // a shift amount of 0 is *not legal* here, it is PKHBT instead.
3922 def : ARMV6Pat<(or (and GPRnopc:$src1, 0xFFFF0000),
3923 (srl GPRnopc:$src2, imm16_31:$sh)),
3924 (PKHTB GPRnopc:$src1, GPRnopc:$src2, imm16_31:$sh)>;
3925 def : ARMV6Pat<(or (and GPRnopc:$src1, 0xFFFF0000),
3926 (and (srl GPRnopc:$src2, imm1_15:$sh), 0xFFFF)),
3927 (PKHTB GPRnopc:$src1, GPRnopc:$src2, imm1_15:$sh)>;
3929 //===----------------------------------------------------------------------===//
3930 // Comparison Instructions...
3933 defm CMP : AI1_cmp_irs<0b1010, "cmp",
3934 IIC_iCMPi, IIC_iCMPr, IIC_iCMPsr,
3935 BinOpFrag<(ARMcmp node:$LHS, node:$RHS)>>;
3937 // ARMcmpZ can re-use the above instruction definitions.
3938 def : ARMPat<(ARMcmpZ GPR:$src, so_imm:$imm),
3939 (CMPri GPR:$src, so_imm:$imm)>;
3940 def : ARMPat<(ARMcmpZ GPR:$src, GPR:$rhs),
3941 (CMPrr GPR:$src, GPR:$rhs)>;
3942 def : ARMPat<(ARMcmpZ GPR:$src, so_reg_imm:$rhs),
3943 (CMPrsi GPR:$src, so_reg_imm:$rhs)>;
3944 def : ARMPat<(ARMcmpZ GPR:$src, so_reg_reg:$rhs),
3945 (CMPrsr GPR:$src, so_reg_reg:$rhs)>;
3947 // CMN register-integer
3948 let isCompare = 1, Defs = [CPSR] in {
3949 def CMNri : AI1<0b1011, (outs), (ins GPR:$Rn, so_imm:$imm), DPFrm, IIC_iCMPi,
3950 "cmn", "\t$Rn, $imm",
3951 [(ARMcmn GPR:$Rn, so_imm:$imm)]> {
3956 let Inst{19-16} = Rn;
3957 let Inst{15-12} = 0b0000;
3958 let Inst{11-0} = imm;
3960 let Unpredictable{15-12} = 0b1111;
3963 // CMN register-register/shift
3964 def CMNzrr : AI1<0b1011, (outs), (ins GPR:$Rn, GPR:$Rm), DPFrm, IIC_iCMPr,
3965 "cmn", "\t$Rn, $Rm",
3966 [(BinOpFrag<(ARMcmpZ node:$LHS,(ineg node:$RHS))>
3967 GPR:$Rn, GPR:$Rm)]> {
3970 let isCommutable = 1;
3973 let Inst{19-16} = Rn;
3974 let Inst{15-12} = 0b0000;
3975 let Inst{11-4} = 0b00000000;
3978 let Unpredictable{15-12} = 0b1111;
3981 def CMNzrsi : AI1<0b1011, (outs),
3982 (ins GPR:$Rn, so_reg_imm:$shift), DPSoRegImmFrm, IIC_iCMPsr,
3983 "cmn", "\t$Rn, $shift",
3984 [(BinOpFrag<(ARMcmpZ node:$LHS,(ineg node:$RHS))>
3985 GPR:$Rn, so_reg_imm:$shift)]> {
3990 let Inst{19-16} = Rn;
3991 let Inst{15-12} = 0b0000;
3992 let Inst{11-5} = shift{11-5};
3994 let Inst{3-0} = shift{3-0};
3996 let Unpredictable{15-12} = 0b1111;
3999 def CMNzrsr : AI1<0b1011, (outs),
4000 (ins GPRnopc:$Rn, so_reg_reg:$shift), DPSoRegRegFrm, IIC_iCMPsr,
4001 "cmn", "\t$Rn, $shift",
4002 [(BinOpFrag<(ARMcmpZ node:$LHS,(ineg node:$RHS))>
4003 GPRnopc:$Rn, so_reg_reg:$shift)]> {
4008 let Inst{19-16} = Rn;
4009 let Inst{15-12} = 0b0000;
4010 let Inst{11-8} = shift{11-8};
4012 let Inst{6-5} = shift{6-5};
4014 let Inst{3-0} = shift{3-0};
4016 let Unpredictable{15-12} = 0b1111;
4021 def : ARMPat<(ARMcmp GPR:$src, so_imm_neg:$imm),
4022 (CMNri GPR:$src, so_imm_neg:$imm)>;
4024 def : ARMPat<(ARMcmpZ GPR:$src, so_imm_neg:$imm),
4025 (CMNri GPR:$src, so_imm_neg:$imm)>;
4027 // Note that TST/TEQ don't set all the same flags that CMP does!
4028 defm TST : AI1_cmp_irs<0b1000, "tst",
4029 IIC_iTSTi, IIC_iTSTr, IIC_iTSTsr,
4030 BinOpFrag<(ARMcmpZ (and_su node:$LHS, node:$RHS), 0)>, 1>;
4031 defm TEQ : AI1_cmp_irs<0b1001, "teq",
4032 IIC_iTSTi, IIC_iTSTr, IIC_iTSTsr,
4033 BinOpFrag<(ARMcmpZ (xor_su node:$LHS, node:$RHS), 0)>, 1>;
4035 // Pseudo i64 compares for some floating point compares.
4036 let usesCustomInserter = 1, isBranch = 1, isTerminator = 1,
4038 def BCCi64 : PseudoInst<(outs),
4039 (ins i32imm:$cc, GPR:$lhs1, GPR:$lhs2, GPR:$rhs1, GPR:$rhs2, brtarget:$dst),
4041 [(ARMBcci64 imm:$cc, GPR:$lhs1, GPR:$lhs2, GPR:$rhs1, GPR:$rhs2, bb:$dst)]>;
4043 def BCCZi64 : PseudoInst<(outs),
4044 (ins i32imm:$cc, GPR:$lhs1, GPR:$lhs2, brtarget:$dst), IIC_Br,
4045 [(ARMBcci64 imm:$cc, GPR:$lhs1, GPR:$lhs2, 0, 0, bb:$dst)]>;
4046 } // usesCustomInserter
4049 // Conditional moves
4050 // FIXME: should be able to write a pattern for ARMcmov, but can't use
4051 // a two-value operand where a dag node expects two operands. :(
4052 let neverHasSideEffects = 1 in {
4054 let isCommutable = 1, isSelect = 1 in
4055 def MOVCCr : ARMPseudoInst<(outs GPR:$Rd), (ins GPR:$false, GPR:$Rm, pred:$p),
4057 [/*(set GPR:$Rd, (ARMcmov GPR:$false, GPR:$Rm, imm:$cc, CCR:$ccr))*/]>,
4058 RegConstraint<"$false = $Rd">;
4060 def MOVCCsi : ARMPseudoInst<(outs GPR:$Rd),
4061 (ins GPR:$false, so_reg_imm:$shift, pred:$p),
4063 [/*(set GPR:$Rd, (ARMcmov GPR:$false, so_reg_imm:$shift,
4064 imm:$cc, CCR:$ccr))*/]>,
4065 RegConstraint<"$false = $Rd">;
4066 def MOVCCsr : ARMPseudoInst<(outs GPR:$Rd),
4067 (ins GPR:$false, so_reg_reg:$shift, pred:$p),
4069 [/*(set GPR:$Rd, (ARMcmov GPR:$false, so_reg_reg:$shift,
4070 imm:$cc, CCR:$ccr))*/]>,
4071 RegConstraint<"$false = $Rd">;
4074 let isMoveImm = 1 in
4075 def MOVCCi16 : ARMPseudoInst<(outs GPR:$Rd),
4076 (ins GPR:$false, imm0_65535_expr:$imm, pred:$p),
4079 RegConstraint<"$false = $Rd">, Requires<[IsARM, HasV6T2]>;
4081 let isMoveImm = 1 in
4082 def MOVCCi : ARMPseudoInst<(outs GPR:$Rd),
4083 (ins GPR:$false, so_imm:$imm, pred:$p),
4085 [/*(set GPR:$Rd, (ARMcmov GPR:$false, so_imm:$imm, imm:$cc, CCR:$ccr))*/]>,
4086 RegConstraint<"$false = $Rd">;
4088 // Two instruction predicate mov immediate.
4089 let isMoveImm = 1 in
4090 def MOVCCi32imm : ARMPseudoInst<(outs GPR:$Rd),
4091 (ins GPR:$false, i32imm:$src, pred:$p),
4092 8, IIC_iCMOVix2, []>, RegConstraint<"$false = $Rd">;
4094 let isMoveImm = 1 in
4095 def MVNCCi : ARMPseudoInst<(outs GPR:$Rd),
4096 (ins GPR:$false, so_imm:$imm, pred:$p),
4098 [/*(set GPR:$Rd, (ARMcmov GPR:$false, so_imm_not:$imm, imm:$cc, CCR:$ccr))*/]>,
4099 RegConstraint<"$false = $Rd">;
4101 } // neverHasSideEffects
4104 //===----------------------------------------------------------------------===//
4105 // Atomic operations intrinsics
4108 def MemBarrierOptOperand : AsmOperandClass {
4109 let Name = "MemBarrierOpt";
4110 let ParserMethod = "parseMemBarrierOptOperand";
4112 def memb_opt : Operand<i32> {
4113 let PrintMethod = "printMemBOption";
4114 let ParserMatchClass = MemBarrierOptOperand;
4115 let DecoderMethod = "DecodeMemBarrierOption";
4118 // memory barriers protect the atomic sequences
4119 let hasSideEffects = 1 in {
4120 def DMB : AInoP<(outs), (ins memb_opt:$opt), MiscFrm, NoItinerary,
4121 "dmb", "\t$opt", [(ARMMemBarrier (i32 imm:$opt))]>,
4122 Requires<[IsARM, HasDB]> {
4124 let Inst{31-4} = 0xf57ff05;
4125 let Inst{3-0} = opt;
4129 def DSB : AInoP<(outs), (ins memb_opt:$opt), MiscFrm, NoItinerary,
4130 "dsb", "\t$opt", []>,
4131 Requires<[IsARM, HasDB]> {
4133 let Inst{31-4} = 0xf57ff04;
4134 let Inst{3-0} = opt;
4137 // ISB has only full system option
4138 def ISB : AInoP<(outs), (ins memb_opt:$opt), MiscFrm, NoItinerary,
4139 "isb", "\t$opt", []>,
4140 Requires<[IsARM, HasDB]> {
4142 let Inst{31-4} = 0xf57ff06;
4143 let Inst{3-0} = opt;
4146 // Pseudo instruction that combines movs + predicated rsbmi
4147 // to implement integer ABS
4148 let usesCustomInserter = 1, Defs = [CPSR] in
4149 def ABS : ARMPseudoInst<(outs GPR:$dst), (ins GPR:$src), 8, NoItinerary, []>;
4151 let usesCustomInserter = 1 in {
4152 let Defs = [CPSR] in {
4153 def ATOMIC_LOAD_ADD_I8 : PseudoInst<
4154 (outs GPR:$dst), (ins GPR:$ptr, GPR:$incr), NoItinerary,
4155 [(set GPR:$dst, (atomic_load_add_8 GPR:$ptr, GPR:$incr))]>;
4156 def ATOMIC_LOAD_SUB_I8 : PseudoInst<
4157 (outs GPR:$dst), (ins GPR:$ptr, GPR:$incr), NoItinerary,
4158 [(set GPR:$dst, (atomic_load_sub_8 GPR:$ptr, GPR:$incr))]>;
4159 def ATOMIC_LOAD_AND_I8 : PseudoInst<
4160 (outs GPR:$dst), (ins GPR:$ptr, GPR:$incr), NoItinerary,
4161 [(set GPR:$dst, (atomic_load_and_8 GPR:$ptr, GPR:$incr))]>;
4162 def ATOMIC_LOAD_OR_I8 : PseudoInst<
4163 (outs GPR:$dst), (ins GPR:$ptr, GPR:$incr), NoItinerary,
4164 [(set GPR:$dst, (atomic_load_or_8 GPR:$ptr, GPR:$incr))]>;
4165 def ATOMIC_LOAD_XOR_I8 : PseudoInst<
4166 (outs GPR:$dst), (ins GPR:$ptr, GPR:$incr), NoItinerary,
4167 [(set GPR:$dst, (atomic_load_xor_8 GPR:$ptr, GPR:$incr))]>;
4168 def ATOMIC_LOAD_NAND_I8 : PseudoInst<
4169 (outs GPR:$dst), (ins GPR:$ptr, GPR:$incr), NoItinerary,
4170 [(set GPR:$dst, (atomic_load_nand_8 GPR:$ptr, GPR:$incr))]>;
4171 def ATOMIC_LOAD_MIN_I8 : PseudoInst<
4172 (outs GPR:$dst), (ins GPR:$ptr, GPR:$val), NoItinerary,
4173 [(set GPR:$dst, (atomic_load_min_8 GPR:$ptr, GPR:$val))]>;
4174 def ATOMIC_LOAD_MAX_I8 : PseudoInst<
4175 (outs GPR:$dst), (ins GPR:$ptr, GPR:$val), NoItinerary,
4176 [(set GPR:$dst, (atomic_load_max_8 GPR:$ptr, GPR:$val))]>;
4177 def ATOMIC_LOAD_UMIN_I8 : PseudoInst<
4178 (outs GPR:$dst), (ins GPR:$ptr, GPR:$val), NoItinerary,
4179 [(set GPR:$dst, (atomic_load_umin_8 GPR:$ptr, GPR:$val))]>;
4180 def ATOMIC_LOAD_UMAX_I8 : PseudoInst<
4181 (outs GPR:$dst), (ins GPR:$ptr, GPR:$val), NoItinerary,
4182 [(set GPR:$dst, (atomic_load_umax_8 GPR:$ptr, GPR:$val))]>;
4183 def ATOMIC_LOAD_ADD_I16 : PseudoInst<
4184 (outs GPR:$dst), (ins GPR:$ptr, GPR:$incr), NoItinerary,
4185 [(set GPR:$dst, (atomic_load_add_16 GPR:$ptr, GPR:$incr))]>;
4186 def ATOMIC_LOAD_SUB_I16 : PseudoInst<
4187 (outs GPR:$dst), (ins GPR:$ptr, GPR:$incr), NoItinerary,
4188 [(set GPR:$dst, (atomic_load_sub_16 GPR:$ptr, GPR:$incr))]>;
4189 def ATOMIC_LOAD_AND_I16 : PseudoInst<
4190 (outs GPR:$dst), (ins GPR:$ptr, GPR:$incr), NoItinerary,
4191 [(set GPR:$dst, (atomic_load_and_16 GPR:$ptr, GPR:$incr))]>;
4192 def ATOMIC_LOAD_OR_I16 : PseudoInst<
4193 (outs GPR:$dst), (ins GPR:$ptr, GPR:$incr), NoItinerary,
4194 [(set GPR:$dst, (atomic_load_or_16 GPR:$ptr, GPR:$incr))]>;
4195 def ATOMIC_LOAD_XOR_I16 : PseudoInst<
4196 (outs GPR:$dst), (ins GPR:$ptr, GPR:$incr), NoItinerary,
4197 [(set GPR:$dst, (atomic_load_xor_16 GPR:$ptr, GPR:$incr))]>;
4198 def ATOMIC_LOAD_NAND_I16 : PseudoInst<
4199 (outs GPR:$dst), (ins GPR:$ptr, GPR:$incr), NoItinerary,
4200 [(set GPR:$dst, (atomic_load_nand_16 GPR:$ptr, GPR:$incr))]>;
4201 def ATOMIC_LOAD_MIN_I16 : PseudoInst<
4202 (outs GPR:$dst), (ins GPR:$ptr, GPR:$val), NoItinerary,
4203 [(set GPR:$dst, (atomic_load_min_16 GPR:$ptr, GPR:$val))]>;
4204 def ATOMIC_LOAD_MAX_I16 : PseudoInst<
4205 (outs GPR:$dst), (ins GPR:$ptr, GPR:$val), NoItinerary,
4206 [(set GPR:$dst, (atomic_load_max_16 GPR:$ptr, GPR:$val))]>;
4207 def ATOMIC_LOAD_UMIN_I16 : PseudoInst<
4208 (outs GPR:$dst), (ins GPR:$ptr, GPR:$val), NoItinerary,
4209 [(set GPR:$dst, (atomic_load_umin_16 GPR:$ptr, GPR:$val))]>;
4210 def ATOMIC_LOAD_UMAX_I16 : PseudoInst<
4211 (outs GPR:$dst), (ins GPR:$ptr, GPR:$val), NoItinerary,
4212 [(set GPR:$dst, (atomic_load_umax_16 GPR:$ptr, GPR:$val))]>;
4213 def ATOMIC_LOAD_ADD_I32 : PseudoInst<
4214 (outs GPR:$dst), (ins GPR:$ptr, GPR:$incr), NoItinerary,
4215 [(set GPR:$dst, (atomic_load_add_32 GPR:$ptr, GPR:$incr))]>;
4216 def ATOMIC_LOAD_SUB_I32 : PseudoInst<
4217 (outs GPR:$dst), (ins GPR:$ptr, GPR:$incr), NoItinerary,
4218 [(set GPR:$dst, (atomic_load_sub_32 GPR:$ptr, GPR:$incr))]>;
4219 def ATOMIC_LOAD_AND_I32 : PseudoInst<
4220 (outs GPR:$dst), (ins GPR:$ptr, GPR:$incr), NoItinerary,
4221 [(set GPR:$dst, (atomic_load_and_32 GPR:$ptr, GPR:$incr))]>;
4222 def ATOMIC_LOAD_OR_I32 : PseudoInst<
4223 (outs GPR:$dst), (ins GPR:$ptr, GPR:$incr), NoItinerary,
4224 [(set GPR:$dst, (atomic_load_or_32 GPR:$ptr, GPR:$incr))]>;
4225 def ATOMIC_LOAD_XOR_I32 : PseudoInst<
4226 (outs GPR:$dst), (ins GPR:$ptr, GPR:$incr), NoItinerary,
4227 [(set GPR:$dst, (atomic_load_xor_32 GPR:$ptr, GPR:$incr))]>;
4228 def ATOMIC_LOAD_NAND_I32 : PseudoInst<
4229 (outs GPR:$dst), (ins GPR:$ptr, GPR:$incr), NoItinerary,
4230 [(set GPR:$dst, (atomic_load_nand_32 GPR:$ptr, GPR:$incr))]>;
4231 def ATOMIC_LOAD_MIN_I32 : PseudoInst<
4232 (outs GPR:$dst), (ins GPR:$ptr, GPR:$val), NoItinerary,
4233 [(set GPR:$dst, (atomic_load_min_32 GPR:$ptr, GPR:$val))]>;
4234 def ATOMIC_LOAD_MAX_I32 : PseudoInst<
4235 (outs GPR:$dst), (ins GPR:$ptr, GPR:$val), NoItinerary,
4236 [(set GPR:$dst, (atomic_load_max_32 GPR:$ptr, GPR:$val))]>;
4237 def ATOMIC_LOAD_UMIN_I32 : PseudoInst<
4238 (outs GPR:$dst), (ins GPR:$ptr, GPR:$val), NoItinerary,
4239 [(set GPR:$dst, (atomic_load_umin_32 GPR:$ptr, GPR:$val))]>;
4240 def ATOMIC_LOAD_UMAX_I32 : PseudoInst<
4241 (outs GPR:$dst), (ins GPR:$ptr, GPR:$val), NoItinerary,
4242 [(set GPR:$dst, (atomic_load_umax_32 GPR:$ptr, GPR:$val))]>;
4244 def ATOMIC_SWAP_I8 : PseudoInst<
4245 (outs GPR:$dst), (ins GPR:$ptr, GPR:$new), NoItinerary,
4246 [(set GPR:$dst, (atomic_swap_8 GPR:$ptr, GPR:$new))]>;
4247 def ATOMIC_SWAP_I16 : PseudoInst<
4248 (outs GPR:$dst), (ins GPR:$ptr, GPR:$new), NoItinerary,
4249 [(set GPR:$dst, (atomic_swap_16 GPR:$ptr, GPR:$new))]>;
4250 def ATOMIC_SWAP_I32 : PseudoInst<
4251 (outs GPR:$dst), (ins GPR:$ptr, GPR:$new), NoItinerary,
4252 [(set GPR:$dst, (atomic_swap_32 GPR:$ptr, GPR:$new))]>;
4254 def ATOMIC_CMP_SWAP_I8 : PseudoInst<
4255 (outs GPR:$dst), (ins GPR:$ptr, GPR:$old, GPR:$new), NoItinerary,
4256 [(set GPR:$dst, (atomic_cmp_swap_8 GPR:$ptr, GPR:$old, GPR:$new))]>;
4257 def ATOMIC_CMP_SWAP_I16 : PseudoInst<
4258 (outs GPR:$dst), (ins GPR:$ptr, GPR:$old, GPR:$new), NoItinerary,
4259 [(set GPR:$dst, (atomic_cmp_swap_16 GPR:$ptr, GPR:$old, GPR:$new))]>;
4260 def ATOMIC_CMP_SWAP_I32 : PseudoInst<
4261 (outs GPR:$dst), (ins GPR:$ptr, GPR:$old, GPR:$new), NoItinerary,
4262 [(set GPR:$dst, (atomic_cmp_swap_32 GPR:$ptr, GPR:$old, GPR:$new))]>;
4266 let usesCustomInserter = 1 in {
4267 def COPY_STRUCT_BYVAL_I32 : PseudoInst<
4268 (outs), (ins GPR:$dst, GPR:$src, i32imm:$size, i32imm:$alignment),
4270 [(ARMcopystructbyval GPR:$dst, GPR:$src, imm:$size, imm:$alignment)]>;
4273 let mayLoad = 1 in {
4274 def LDREXB : AIldrex<0b10, (outs GPR:$Rt), (ins addr_offset_none:$addr),
4276 "ldrexb", "\t$Rt, $addr", []>;
4277 def LDREXH : AIldrex<0b11, (outs GPR:$Rt), (ins addr_offset_none:$addr),
4278 NoItinerary, "ldrexh", "\t$Rt, $addr", []>;
4279 def LDREX : AIldrex<0b00, (outs GPR:$Rt), (ins addr_offset_none:$addr),
4280 NoItinerary, "ldrex", "\t$Rt, $addr", []>;
4281 let hasExtraDefRegAllocReq = 1 in
4282 def LDREXD: AIldrex<0b01, (outs GPRPairOp:$Rt),(ins addr_offset_none:$addr),
4283 NoItinerary, "ldrexd", "\t$Rt, $addr", []> {
4284 let DecoderMethod = "DecodeDoubleRegLoad";
4288 let mayStore = 1, Constraints = "@earlyclobber $Rd" in {
4289 def STREXB: AIstrex<0b10, (outs GPR:$Rd), (ins GPR:$Rt, addr_offset_none:$addr),
4290 NoItinerary, "strexb", "\t$Rd, $Rt, $addr", []>;
4291 def STREXH: AIstrex<0b11, (outs GPR:$Rd), (ins GPR:$Rt, addr_offset_none:$addr),
4292 NoItinerary, "strexh", "\t$Rd, $Rt, $addr", []>;
4293 def STREX : AIstrex<0b00, (outs GPR:$Rd), (ins GPR:$Rt, addr_offset_none:$addr),
4294 NoItinerary, "strex", "\t$Rd, $Rt, $addr", []>;
4295 let hasExtraSrcRegAllocReq = 1 in
4296 def STREXD : AIstrex<0b01, (outs GPR:$Rd),
4297 (ins GPRPairOp:$Rt, addr_offset_none:$addr),
4298 NoItinerary, "strexd", "\t$Rd, $Rt, $addr", []> {
4299 let DecoderMethod = "DecodeDoubleRegStore";
4304 def CLREX : AXI<(outs), (ins), MiscFrm, NoItinerary, "clrex", []>,
4305 Requires<[IsARM, HasV7]> {
4306 let Inst{31-0} = 0b11110101011111111111000000011111;
4309 // SWP/SWPB are deprecated in V6/V7.
4310 let mayLoad = 1, mayStore = 1 in {
4311 def SWP : AIswp<0, (outs GPRnopc:$Rt),
4312 (ins GPRnopc:$Rt2, addr_offset_none:$addr), "swp", []>;
4313 def SWPB: AIswp<1, (outs GPRnopc:$Rt),
4314 (ins GPRnopc:$Rt2, addr_offset_none:$addr), "swpb", []>;
4317 //===----------------------------------------------------------------------===//
4318 // Coprocessor Instructions.
4321 def CDP : ABI<0b1110, (outs), (ins p_imm:$cop, imm0_15:$opc1,
4322 c_imm:$CRd, c_imm:$CRn, c_imm:$CRm, imm0_7:$opc2),
4323 NoItinerary, "cdp", "\t$cop, $opc1, $CRd, $CRn, $CRm, $opc2",
4324 [(int_arm_cdp imm:$cop, imm:$opc1, imm:$CRd, imm:$CRn,
4325 imm:$CRm, imm:$opc2)]> {
4333 let Inst{3-0} = CRm;
4335 let Inst{7-5} = opc2;
4336 let Inst{11-8} = cop;
4337 let Inst{15-12} = CRd;
4338 let Inst{19-16} = CRn;
4339 let Inst{23-20} = opc1;
4342 def CDP2 : ABXI<0b1110, (outs), (ins pf_imm:$cop, imm0_15:$opc1,
4343 c_imm:$CRd, c_imm:$CRn, c_imm:$CRm, imm0_7:$opc2),
4344 NoItinerary, "cdp2\t$cop, $opc1, $CRd, $CRn, $CRm, $opc2",
4345 [(int_arm_cdp2 imm:$cop, imm:$opc1, imm:$CRd, imm:$CRn,
4346 imm:$CRm, imm:$opc2)]> {
4347 let Inst{31-28} = 0b1111;
4355 let Inst{3-0} = CRm;
4357 let Inst{7-5} = opc2;
4358 let Inst{11-8} = cop;
4359 let Inst{15-12} = CRd;
4360 let Inst{19-16} = CRn;
4361 let Inst{23-20} = opc1;
4364 class ACI<dag oops, dag iops, string opc, string asm,
4365 IndexMode im = IndexModeNone>
4366 : I<oops, iops, AddrModeNone, 4, im, BrFrm, NoItinerary,
4368 let Inst{27-25} = 0b110;
4370 class ACInoP<dag oops, dag iops, string opc, string asm,
4371 IndexMode im = IndexModeNone>
4372 : InoP<oops, iops, AddrModeNone, 4, im, BrFrm, NoItinerary,
4374 let Inst{31-28} = 0b1111;
4375 let Inst{27-25} = 0b110;
4377 multiclass LdStCop<bit load, bit Dbit, string asm> {
4378 def _OFFSET : ACI<(outs), (ins p_imm:$cop, c_imm:$CRd, addrmode5:$addr),
4379 asm, "\t$cop, $CRd, $addr"> {
4383 let Inst{24} = 1; // P = 1
4384 let Inst{23} = addr{8};
4385 let Inst{22} = Dbit;
4386 let Inst{21} = 0; // W = 0
4387 let Inst{20} = load;
4388 let Inst{19-16} = addr{12-9};
4389 let Inst{15-12} = CRd;
4390 let Inst{11-8} = cop;
4391 let Inst{7-0} = addr{7-0};
4392 let DecoderMethod = "DecodeCopMemInstruction";
4394 def _PRE : ACI<(outs), (ins p_imm:$cop, c_imm:$CRd, addrmode5:$addr),
4395 asm, "\t$cop, $CRd, $addr!", IndexModePre> {
4399 let Inst{24} = 1; // P = 1
4400 let Inst{23} = addr{8};
4401 let Inst{22} = Dbit;
4402 let Inst{21} = 1; // W = 1
4403 let Inst{20} = load;
4404 let Inst{19-16} = addr{12-9};
4405 let Inst{15-12} = CRd;
4406 let Inst{11-8} = cop;
4407 let Inst{7-0} = addr{7-0};
4408 let DecoderMethod = "DecodeCopMemInstruction";
4410 def _POST: ACI<(outs), (ins p_imm:$cop, c_imm:$CRd, addr_offset_none:$addr,
4411 postidx_imm8s4:$offset),
4412 asm, "\t$cop, $CRd, $addr, $offset", IndexModePost> {
4417 let Inst{24} = 0; // P = 0
4418 let Inst{23} = offset{8};
4419 let Inst{22} = Dbit;
4420 let Inst{21} = 1; // W = 1
4421 let Inst{20} = load;
4422 let Inst{19-16} = addr;
4423 let Inst{15-12} = CRd;
4424 let Inst{11-8} = cop;
4425 let Inst{7-0} = offset{7-0};
4426 let DecoderMethod = "DecodeCopMemInstruction";
4428 def _OPTION : ACI<(outs),
4429 (ins p_imm:$cop, c_imm:$CRd, addr_offset_none:$addr,
4430 coproc_option_imm:$option),
4431 asm, "\t$cop, $CRd, $addr, $option"> {
4436 let Inst{24} = 0; // P = 0
4437 let Inst{23} = 1; // U = 1
4438 let Inst{22} = Dbit;
4439 let Inst{21} = 0; // W = 0
4440 let Inst{20} = load;
4441 let Inst{19-16} = addr;
4442 let Inst{15-12} = CRd;
4443 let Inst{11-8} = cop;
4444 let Inst{7-0} = option;
4445 let DecoderMethod = "DecodeCopMemInstruction";
4448 multiclass LdSt2Cop<bit load, bit Dbit, string asm> {
4449 def _OFFSET : ACInoP<(outs), (ins p_imm:$cop, c_imm:$CRd, addrmode5:$addr),
4450 asm, "\t$cop, $CRd, $addr"> {
4454 let Inst{24} = 1; // P = 1
4455 let Inst{23} = addr{8};
4456 let Inst{22} = Dbit;
4457 let Inst{21} = 0; // W = 0
4458 let Inst{20} = load;
4459 let Inst{19-16} = addr{12-9};
4460 let Inst{15-12} = CRd;
4461 let Inst{11-8} = cop;
4462 let Inst{7-0} = addr{7-0};
4463 let DecoderMethod = "DecodeCopMemInstruction";
4465 def _PRE : ACInoP<(outs), (ins p_imm:$cop, c_imm:$CRd, addrmode5:$addr),
4466 asm, "\t$cop, $CRd, $addr!", IndexModePre> {
4470 let Inst{24} = 1; // P = 1
4471 let Inst{23} = addr{8};
4472 let Inst{22} = Dbit;
4473 let Inst{21} = 1; // W = 1
4474 let Inst{20} = load;
4475 let Inst{19-16} = addr{12-9};
4476 let Inst{15-12} = CRd;
4477 let Inst{11-8} = cop;
4478 let Inst{7-0} = addr{7-0};
4479 let DecoderMethod = "DecodeCopMemInstruction";
4481 def _POST: ACInoP<(outs), (ins p_imm:$cop, c_imm:$CRd, addr_offset_none:$addr,
4482 postidx_imm8s4:$offset),
4483 asm, "\t$cop, $CRd, $addr, $offset", IndexModePost> {
4488 let Inst{24} = 0; // P = 0
4489 let Inst{23} = offset{8};
4490 let Inst{22} = Dbit;
4491 let Inst{21} = 1; // W = 1
4492 let Inst{20} = load;
4493 let Inst{19-16} = addr;
4494 let Inst{15-12} = CRd;
4495 let Inst{11-8} = cop;
4496 let Inst{7-0} = offset{7-0};
4497 let DecoderMethod = "DecodeCopMemInstruction";
4499 def _OPTION : ACInoP<(outs),
4500 (ins p_imm:$cop, c_imm:$CRd, addr_offset_none:$addr,
4501 coproc_option_imm:$option),
4502 asm, "\t$cop, $CRd, $addr, $option"> {
4507 let Inst{24} = 0; // P = 0
4508 let Inst{23} = 1; // U = 1
4509 let Inst{22} = Dbit;
4510 let Inst{21} = 0; // W = 0
4511 let Inst{20} = load;
4512 let Inst{19-16} = addr;
4513 let Inst{15-12} = CRd;
4514 let Inst{11-8} = cop;
4515 let Inst{7-0} = option;
4516 let DecoderMethod = "DecodeCopMemInstruction";
4520 defm LDC : LdStCop <1, 0, "ldc">;
4521 defm LDCL : LdStCop <1, 1, "ldcl">;
4522 defm STC : LdStCop <0, 0, "stc">;
4523 defm STCL : LdStCop <0, 1, "stcl">;
4524 defm LDC2 : LdSt2Cop<1, 0, "ldc2">;
4525 defm LDC2L : LdSt2Cop<1, 1, "ldc2l">;
4526 defm STC2 : LdSt2Cop<0, 0, "stc2">;
4527 defm STC2L : LdSt2Cop<0, 1, "stc2l">;
4529 //===----------------------------------------------------------------------===//
4530 // Move between coprocessor and ARM core register.
4533 class MovRCopro<string opc, bit direction, dag oops, dag iops,
4535 : ABI<0b1110, oops, iops, NoItinerary, opc,
4536 "\t$cop, $opc1, $Rt, $CRn, $CRm, $opc2", pattern> {
4537 let Inst{20} = direction;
4547 let Inst{15-12} = Rt;
4548 let Inst{11-8} = cop;
4549 let Inst{23-21} = opc1;
4550 let Inst{7-5} = opc2;
4551 let Inst{3-0} = CRm;
4552 let Inst{19-16} = CRn;
4555 def MCR : MovRCopro<"mcr", 0 /* from ARM core register to coprocessor */,
4557 (ins p_imm:$cop, imm0_7:$opc1, GPR:$Rt, c_imm:$CRn,
4558 c_imm:$CRm, imm0_7:$opc2),
4559 [(int_arm_mcr imm:$cop, imm:$opc1, GPR:$Rt, imm:$CRn,
4560 imm:$CRm, imm:$opc2)]>;
4561 def : ARMInstAlias<"mcr${p} $cop, $opc1, $Rt, $CRn, $CRm",
4562 (MCR p_imm:$cop, imm0_7:$opc1, GPR:$Rt, c_imm:$CRn,
4563 c_imm:$CRm, 0, pred:$p)>;
4564 def MRC : MovRCopro<"mrc", 1 /* from coprocessor to ARM core register */,
4566 (ins p_imm:$cop, imm0_7:$opc1, c_imm:$CRn, c_imm:$CRm,
4568 def : ARMInstAlias<"mrc${p} $cop, $opc1, $Rt, $CRn, $CRm",
4569 (MRC GPR:$Rt, p_imm:$cop, imm0_7:$opc1, c_imm:$CRn,
4570 c_imm:$CRm, 0, pred:$p)>;
4572 def : ARMPat<(int_arm_mrc imm:$cop, imm:$opc1, imm:$CRn, imm:$CRm, imm:$opc2),
4573 (MRC imm:$cop, imm:$opc1, imm:$CRn, imm:$CRm, imm:$opc2)>;
4575 class MovRCopro2<string opc, bit direction, dag oops, dag iops,
4577 : ABXI<0b1110, oops, iops, NoItinerary,
4578 !strconcat(opc, "\t$cop, $opc1, $Rt, $CRn, $CRm, $opc2"), pattern> {
4579 let Inst{31-28} = 0b1111;
4580 let Inst{20} = direction;
4590 let Inst{15-12} = Rt;
4591 let Inst{11-8} = cop;
4592 let Inst{23-21} = opc1;
4593 let Inst{7-5} = opc2;
4594 let Inst{3-0} = CRm;
4595 let Inst{19-16} = CRn;
4598 def MCR2 : MovRCopro2<"mcr2", 0 /* from ARM core register to coprocessor */,
4600 (ins p_imm:$cop, imm0_7:$opc1, GPR:$Rt, c_imm:$CRn,
4601 c_imm:$CRm, imm0_7:$opc2),
4602 [(int_arm_mcr2 imm:$cop, imm:$opc1, GPR:$Rt, imm:$CRn,
4603 imm:$CRm, imm:$opc2)]>;
4604 def : ARMInstAlias<"mcr2$ $cop, $opc1, $Rt, $CRn, $CRm",
4605 (MCR2 p_imm:$cop, imm0_7:$opc1, GPR:$Rt, c_imm:$CRn,
4607 def MRC2 : MovRCopro2<"mrc2", 1 /* from coprocessor to ARM core register */,
4609 (ins p_imm:$cop, imm0_7:$opc1, c_imm:$CRn, c_imm:$CRm,
4611 def : ARMInstAlias<"mrc2$ $cop, $opc1, $Rt, $CRn, $CRm",
4612 (MRC2 GPR:$Rt, p_imm:$cop, imm0_7:$opc1, c_imm:$CRn,
4615 def : ARMV5TPat<(int_arm_mrc2 imm:$cop, imm:$opc1, imm:$CRn,
4616 imm:$CRm, imm:$opc2),
4617 (MRC2 imm:$cop, imm:$opc1, imm:$CRn, imm:$CRm, imm:$opc2)>;
4619 class MovRRCopro<string opc, bit direction, list<dag> pattern = []>
4620 : ABI<0b1100, (outs), (ins p_imm:$cop, imm0_15:$opc1,
4621 GPRnopc:$Rt, GPRnopc:$Rt2, c_imm:$CRm),
4622 NoItinerary, opc, "\t$cop, $opc1, $Rt, $Rt2, $CRm", pattern> {
4623 let Inst{23-21} = 0b010;
4624 let Inst{20} = direction;
4632 let Inst{15-12} = Rt;
4633 let Inst{19-16} = Rt2;
4634 let Inst{11-8} = cop;
4635 let Inst{7-4} = opc1;
4636 let Inst{3-0} = CRm;
4639 def MCRR : MovRRCopro<"mcrr", 0 /* from ARM core register to coprocessor */,
4640 [(int_arm_mcrr imm:$cop, imm:$opc1, GPRnopc:$Rt,
4641 GPRnopc:$Rt2, imm:$CRm)]>;
4642 def MRRC : MovRRCopro<"mrrc", 1 /* from coprocessor to ARM core register */>;
4644 class MovRRCopro2<string opc, bit direction, list<dag> pattern = []>
4645 : ABXI<0b1100, (outs), (ins p_imm:$cop, imm0_15:$opc1,
4646 GPRnopc:$Rt, GPRnopc:$Rt2, c_imm:$CRm), NoItinerary,
4647 !strconcat(opc, "\t$cop, $opc1, $Rt, $Rt2, $CRm"), pattern> {
4648 let Inst{31-28} = 0b1111;
4649 let Inst{23-21} = 0b010;
4650 let Inst{20} = direction;
4658 let Inst{15-12} = Rt;
4659 let Inst{19-16} = Rt2;
4660 let Inst{11-8} = cop;
4661 let Inst{7-4} = opc1;
4662 let Inst{3-0} = CRm;
4664 let DecoderMethod = "DecodeMRRC2";
4667 def MCRR2 : MovRRCopro2<"mcrr2", 0 /* from ARM core register to coprocessor */,
4668 [(int_arm_mcrr2 imm:$cop, imm:$opc1, GPRnopc:$Rt,
4669 GPRnopc:$Rt2, imm:$CRm)]>;
4670 def MRRC2 : MovRRCopro2<"mrrc2", 1 /* from coprocessor to ARM core register */>;
4672 //===----------------------------------------------------------------------===//
4673 // Move between special register and ARM core register
4676 // Move to ARM core register from Special Register
4677 def MRS : ABI<0b0001, (outs GPRnopc:$Rd), (ins), NoItinerary,
4678 "mrs", "\t$Rd, apsr", []> {
4680 let Inst{23-16} = 0b00001111;
4681 let Unpredictable{19-17} = 0b111;
4683 let Inst{15-12} = Rd;
4685 let Inst{11-0} = 0b000000000000;
4686 let Unpredictable{11-0} = 0b110100001111;
4689 def : InstAlias<"mrs${p} $Rd, cpsr", (MRS GPRnopc:$Rd, pred:$p)>,
4692 // The MRSsys instruction is the MRS instruction from the ARM ARM,
4693 // section B9.3.9, with the R bit set to 1.
4694 def MRSsys : ABI<0b0001, (outs GPRnopc:$Rd), (ins), NoItinerary,
4695 "mrs", "\t$Rd, spsr", []> {
4697 let Inst{23-16} = 0b01001111;
4698 let Unpredictable{19-16} = 0b1111;
4700 let Inst{15-12} = Rd;
4702 let Inst{11-0} = 0b000000000000;
4703 let Unpredictable{11-0} = 0b110100001111;
4706 // Move from ARM core register to Special Register
4708 // No need to have both system and application versions, the encodings are the
4709 // same and the assembly parser has no way to distinguish between them. The mask
4710 // operand contains the special register (R Bit) in bit 4 and bits 3-0 contains
4711 // the mask with the fields to be accessed in the special register.
4712 def MSR : ABI<0b0001, (outs), (ins msr_mask:$mask, GPR:$Rn), NoItinerary,
4713 "msr", "\t$mask, $Rn", []> {
4718 let Inst{22} = mask{4}; // R bit
4719 let Inst{21-20} = 0b10;
4720 let Inst{19-16} = mask{3-0};
4721 let Inst{15-12} = 0b1111;
4722 let Inst{11-4} = 0b00000000;
4726 def MSRi : ABI<0b0011, (outs), (ins msr_mask:$mask, so_imm:$a), NoItinerary,
4727 "msr", "\t$mask, $a", []> {
4732 let Inst{22} = mask{4}; // R bit
4733 let Inst{21-20} = 0b10;
4734 let Inst{19-16} = mask{3-0};
4735 let Inst{15-12} = 0b1111;
4739 //===----------------------------------------------------------------------===//
4743 // __aeabi_read_tp preserves the registers r1-r3.
4744 // This is a pseudo inst so that we can get the encoding right,
4745 // complete with fixup for the aeabi_read_tp function.
4747 Defs = [R0, R12, LR, CPSR], Uses = [SP] in {
4748 def TPsoft : PseudoInst<(outs), (ins), IIC_Br,
4749 [(set R0, ARMthread_pointer)]>;
4752 //===----------------------------------------------------------------------===//
4753 // SJLJ Exception handling intrinsics
4754 // eh_sjlj_setjmp() is an instruction sequence to store the return
4755 // address and save #0 in R0 for the non-longjmp case.
4756 // Since by its nature we may be coming from some other function to get
4757 // here, and we're using the stack frame for the containing function to
4758 // save/restore registers, we can't keep anything live in regs across
4759 // the eh_sjlj_setjmp(), else it will almost certainly have been tromped upon
4760 // when we get here from a longjmp(). We force everything out of registers
4761 // except for our own input by listing the relevant registers in Defs. By
4762 // doing so, we also cause the prologue/epilogue code to actively preserve
4763 // all of the callee-saved resgisters, which is exactly what we want.
4764 // A constant value is passed in $val, and we use the location as a scratch.
4766 // These are pseudo-instructions and are lowered to individual MC-insts, so
4767 // no encoding information is necessary.
4769 [ R0, R1, R2, R3, R4, R5, R6, R7, R8, R9, R10, R11, R12, LR, CPSR,
4770 Q0, Q1, Q2, Q3, Q4, Q5, Q6, Q7, Q8, Q9, Q10, Q11, Q12, Q13, Q14, Q15 ],
4771 hasSideEffects = 1, isBarrier = 1, usesCustomInserter = 1 in {
4772 def Int_eh_sjlj_setjmp : PseudoInst<(outs), (ins GPR:$src, GPR:$val),
4774 [(set R0, (ARMeh_sjlj_setjmp GPR:$src, GPR:$val))]>,
4775 Requires<[IsARM, HasVFP2]>;
4779 [ R0, R1, R2, R3, R4, R5, R6, R7, R8, R9, R10, R11, R12, LR, CPSR ],
4780 hasSideEffects = 1, isBarrier = 1, usesCustomInserter = 1 in {
4781 def Int_eh_sjlj_setjmp_nofp : PseudoInst<(outs), (ins GPR:$src, GPR:$val),
4783 [(set R0, (ARMeh_sjlj_setjmp GPR:$src, GPR:$val))]>,
4784 Requires<[IsARM, NoVFP]>;
4787 // FIXME: Non-IOS version(s)
4788 let isBarrier = 1, hasSideEffects = 1, isTerminator = 1,
4789 Defs = [ R7, LR, SP ] in {
4790 def Int_eh_sjlj_longjmp : PseudoInst<(outs), (ins GPR:$src, GPR:$scratch),
4792 [(ARMeh_sjlj_longjmp GPR:$src, GPR:$scratch)]>,
4793 Requires<[IsARM, IsIOS]>;
4796 // eh.sjlj.dispatchsetup pseudo-instruction.
4797 // This pseudo is used for both ARM and Thumb. Any differences are handled when
4798 // the pseudo is expanded (which happens before any passes that need the
4799 // instruction size).
4800 let isBarrier = 1 in
4801 def Int_eh_sjlj_dispatchsetup : PseudoInst<(outs), (ins), NoItinerary, []>;
4804 //===----------------------------------------------------------------------===//
4805 // Non-Instruction Patterns
4808 // ARMv4 indirect branch using (MOVr PC, dst)
4809 let isBranch = 1, isTerminator = 1, isBarrier = 1, isIndirectBranch = 1 in
4810 def MOVPCRX : ARMPseudoExpand<(outs), (ins GPR:$dst),
4811 4, IIC_Br, [(brind GPR:$dst)],
4812 (MOVr PC, GPR:$dst, (ops 14, zero_reg), zero_reg)>,
4813 Requires<[IsARM, NoV4T]>;
4815 // Large immediate handling.
4817 // 32-bit immediate using two piece so_imms or movw + movt.
4818 // This is a single pseudo instruction, the benefit is that it can be remat'd
4819 // as a single unit instead of having to handle reg inputs.
4820 // FIXME: Remove this when we can do generalized remat.
4821 let isReMaterializable = 1, isMoveImm = 1 in
4822 def MOVi32imm : PseudoInst<(outs GPR:$dst), (ins i32imm:$src), IIC_iMOVix2,
4823 [(set GPR:$dst, (arm_i32imm:$src))]>,
4826 // Pseudo instruction that combines movw + movt + add pc (if PIC).
4827 // It also makes it possible to rematerialize the instructions.
4828 // FIXME: Remove this when we can do generalized remat and when machine licm
4829 // can properly the instructions.
4830 let isReMaterializable = 1 in {
4831 def MOV_ga_pcrel : PseudoInst<(outs GPR:$dst), (ins i32imm:$addr),
4833 [(set GPR:$dst, (ARMWrapperPIC tglobaladdr:$addr))]>,
4834 Requires<[IsARM, UseMovt]>;
4836 def MOV_ga_dyn : PseudoInst<(outs GPR:$dst), (ins i32imm:$addr),
4838 [(set GPR:$dst, (ARMWrapperDYN tglobaladdr:$addr))]>,
4839 Requires<[IsARM, UseMovt]>;
4841 let AddedComplexity = 10 in
4842 def MOV_ga_pcrel_ldr : PseudoInst<(outs GPR:$dst), (ins i32imm:$addr),
4844 [(set GPR:$dst, (load (ARMWrapperPIC tglobaladdr:$addr)))]>,
4845 Requires<[IsARM, UseMovt]>;
4846 } // isReMaterializable
4848 // ConstantPool, GlobalAddress, and JumpTable
4849 def : ARMPat<(ARMWrapper tglobaladdr :$dst), (LEApcrel tglobaladdr :$dst)>,
4850 Requires<[IsARM, DontUseMovt]>;
4851 def : ARMPat<(ARMWrapper tconstpool :$dst), (LEApcrel tconstpool :$dst)>;
4852 def : ARMPat<(ARMWrapper tglobaladdr :$dst), (MOVi32imm tglobaladdr :$dst)>,
4853 Requires<[IsARM, UseMovt]>;
4854 def : ARMPat<(ARMWrapperJT tjumptable:$dst, imm:$id),
4855 (LEApcrelJT tjumptable:$dst, imm:$id)>;
4857 // TODO: add,sub,and, 3-instr forms?
4859 // Tail calls. These patterns also apply to Thumb mode.
4860 def : Pat<(ARMtcret tcGPR:$dst), (TCRETURNri tcGPR:$dst)>;
4861 def : Pat<(ARMtcret (i32 tglobaladdr:$dst)), (TCRETURNdi texternalsym:$dst)>;
4862 def : Pat<(ARMtcret (i32 texternalsym:$dst)), (TCRETURNdi texternalsym:$dst)>;
4865 def : ARMPat<(ARMcall texternalsym:$func), (BL texternalsym:$func)>;
4866 def : ARMPat<(ARMcall_nolink texternalsym:$func),
4867 (BMOVPCB_CALL texternalsym:$func)>;
4869 // zextload i1 -> zextload i8
4870 def : ARMPat<(zextloadi1 addrmode_imm12:$addr), (LDRBi12 addrmode_imm12:$addr)>;
4871 def : ARMPat<(zextloadi1 ldst_so_reg:$addr), (LDRBrs ldst_so_reg:$addr)>;
4873 // extload -> zextload
4874 def : ARMPat<(extloadi1 addrmode_imm12:$addr), (LDRBi12 addrmode_imm12:$addr)>;
4875 def : ARMPat<(extloadi1 ldst_so_reg:$addr), (LDRBrs ldst_so_reg:$addr)>;
4876 def : ARMPat<(extloadi8 addrmode_imm12:$addr), (LDRBi12 addrmode_imm12:$addr)>;
4877 def : ARMPat<(extloadi8 ldst_so_reg:$addr), (LDRBrs ldst_so_reg:$addr)>;
4879 def : ARMPat<(extloadi16 addrmode3:$addr), (LDRH addrmode3:$addr)>;
4881 def : ARMPat<(extloadi8 addrmodepc:$addr), (PICLDRB addrmodepc:$addr)>;
4882 def : ARMPat<(extloadi16 addrmodepc:$addr), (PICLDRH addrmodepc:$addr)>;
4885 def : ARMV5TEPat<(mul (sra (shl GPR:$a, (i32 16)), (i32 16)),
4886 (sra (shl GPR:$b, (i32 16)), (i32 16))),
4887 (SMULBB GPR:$a, GPR:$b)>;
4888 def : ARMV5TEPat<(mul sext_16_node:$a, sext_16_node:$b),
4889 (SMULBB GPR:$a, GPR:$b)>;
4890 def : ARMV5TEPat<(mul (sra (shl GPR:$a, (i32 16)), (i32 16)),
4891 (sra GPR:$b, (i32 16))),
4892 (SMULBT GPR:$a, GPR:$b)>;
4893 def : ARMV5TEPat<(mul sext_16_node:$a, (sra GPR:$b, (i32 16))),
4894 (SMULBT GPR:$a, GPR:$b)>;
4895 def : ARMV5TEPat<(mul (sra GPR:$a, (i32 16)),
4896 (sra (shl GPR:$b, (i32 16)), (i32 16))),
4897 (SMULTB GPR:$a, GPR:$b)>;
4898 def : ARMV5TEPat<(mul (sra GPR:$a, (i32 16)), sext_16_node:$b),
4899 (SMULTB GPR:$a, GPR:$b)>;
4900 def : ARMV5TEPat<(sra (mul GPR:$a, (sra (shl GPR:$b, (i32 16)), (i32 16))),
4902 (SMULWB GPR:$a, GPR:$b)>;
4903 def : ARMV5TEPat<(sra (mul GPR:$a, sext_16_node:$b), (i32 16)),
4904 (SMULWB GPR:$a, GPR:$b)>;
4906 def : ARMV5MOPat<(add GPR:$acc,
4907 (mul (sra (shl GPR:$a, (i32 16)), (i32 16)),
4908 (sra (shl GPR:$b, (i32 16)), (i32 16)))),
4909 (SMLABB GPR:$a, GPR:$b, GPR:$acc)>;
4910 def : ARMV5MOPat<(add GPR:$acc,
4911 (mul sext_16_node:$a, sext_16_node:$b)),
4912 (SMLABB GPR:$a, GPR:$b, GPR:$acc)>;
4913 def : ARMV5MOPat<(add GPR:$acc,
4914 (mul (sra (shl GPR:$a, (i32 16)), (i32 16)),
4915 (sra GPR:$b, (i32 16)))),
4916 (SMLABT GPR:$a, GPR:$b, GPR:$acc)>;
4917 def : ARMV5MOPat<(add GPR:$acc,
4918 (mul sext_16_node:$a, (sra GPR:$b, (i32 16)))),
4919 (SMLABT GPR:$a, GPR:$b, GPR:$acc)>;
4920 def : ARMV5MOPat<(add GPR:$acc,
4921 (mul (sra GPR:$a, (i32 16)),
4922 (sra (shl GPR:$b, (i32 16)), (i32 16)))),
4923 (SMLATB GPR:$a, GPR:$b, GPR:$acc)>;
4924 def : ARMV5MOPat<(add GPR:$acc,
4925 (mul (sra GPR:$a, (i32 16)), sext_16_node:$b)),
4926 (SMLATB GPR:$a, GPR:$b, GPR:$acc)>;
4927 def : ARMV5MOPat<(add GPR:$acc,
4928 (sra (mul GPR:$a, (sra (shl GPR:$b, (i32 16)), (i32 16))),
4930 (SMLAWB GPR:$a, GPR:$b, GPR:$acc)>;
4931 def : ARMV5MOPat<(add GPR:$acc,
4932 (sra (mul GPR:$a, sext_16_node:$b), (i32 16))),
4933 (SMLAWB GPR:$a, GPR:$b, GPR:$acc)>;
4936 // Pre-v7 uses MCR for synchronization barriers.
4937 def : ARMPat<(ARMMemBarrierMCR GPR:$zero), (MCR 15, 0, GPR:$zero, 7, 10, 5)>,
4938 Requires<[IsARM, HasV6]>;
4940 // SXT/UXT with no rotate
4941 let AddedComplexity = 16 in {
4942 def : ARMV6Pat<(and GPR:$Src, 0x000000FF), (UXTB GPR:$Src, 0)>;
4943 def : ARMV6Pat<(and GPR:$Src, 0x0000FFFF), (UXTH GPR:$Src, 0)>;
4944 def : ARMV6Pat<(and GPR:$Src, 0x00FF00FF), (UXTB16 GPR:$Src, 0)>;
4945 def : ARMV6Pat<(add GPR:$Rn, (and GPR:$Rm, 0x00FF)),
4946 (UXTAB GPR:$Rn, GPR:$Rm, 0)>;
4947 def : ARMV6Pat<(add GPR:$Rn, (and GPR:$Rm, 0xFFFF)),
4948 (UXTAH GPR:$Rn, GPR:$Rm, 0)>;
4951 def : ARMV6Pat<(sext_inreg GPR:$Src, i8), (SXTB GPR:$Src, 0)>;
4952 def : ARMV6Pat<(sext_inreg GPR:$Src, i16), (SXTH GPR:$Src, 0)>;
4954 def : ARMV6Pat<(add GPR:$Rn, (sext_inreg GPRnopc:$Rm, i8)),
4955 (SXTAB GPR:$Rn, GPRnopc:$Rm, 0)>;
4956 def : ARMV6Pat<(add GPR:$Rn, (sext_inreg GPRnopc:$Rm, i16)),
4957 (SXTAH GPR:$Rn, GPRnopc:$Rm, 0)>;
4959 // Atomic load/store patterns
4960 def : ARMPat<(atomic_load_8 ldst_so_reg:$src),
4961 (LDRBrs ldst_so_reg:$src)>;
4962 def : ARMPat<(atomic_load_8 addrmode_imm12:$src),
4963 (LDRBi12 addrmode_imm12:$src)>;
4964 def : ARMPat<(atomic_load_16 addrmode3:$src),
4965 (LDRH addrmode3:$src)>;
4966 def : ARMPat<(atomic_load_32 ldst_so_reg:$src),
4967 (LDRrs ldst_so_reg:$src)>;
4968 def : ARMPat<(atomic_load_32 addrmode_imm12:$src),
4969 (LDRi12 addrmode_imm12:$src)>;
4970 def : ARMPat<(atomic_store_8 ldst_so_reg:$ptr, GPR:$val),
4971 (STRBrs GPR:$val, ldst_so_reg:$ptr)>;
4972 def : ARMPat<(atomic_store_8 addrmode_imm12:$ptr, GPR:$val),
4973 (STRBi12 GPR:$val, addrmode_imm12:$ptr)>;
4974 def : ARMPat<(atomic_store_16 addrmode3:$ptr, GPR:$val),
4975 (STRH GPR:$val, addrmode3:$ptr)>;
4976 def : ARMPat<(atomic_store_32 ldst_so_reg:$ptr, GPR:$val),
4977 (STRrs GPR:$val, ldst_so_reg:$ptr)>;
4978 def : ARMPat<(atomic_store_32 addrmode_imm12:$ptr, GPR:$val),
4979 (STRi12 GPR:$val, addrmode_imm12:$ptr)>;
4982 //===----------------------------------------------------------------------===//
4986 include "ARMInstrThumb.td"
4988 //===----------------------------------------------------------------------===//
4992 include "ARMInstrThumb2.td"
4994 //===----------------------------------------------------------------------===//
4995 // Floating Point Support
4998 include "ARMInstrVFP.td"
5000 //===----------------------------------------------------------------------===//
5001 // Advanced SIMD (NEON) Support
5004 include "ARMInstrNEON.td"
5006 //===----------------------------------------------------------------------===//
5007 // Assembler aliases
5011 def : InstAlias<"dmb", (DMB 0xf)>, Requires<[IsARM, HasDB]>;
5012 def : InstAlias<"dsb", (DSB 0xf)>, Requires<[IsARM, HasDB]>;
5013 def : InstAlias<"isb", (ISB 0xf)>, Requires<[IsARM, HasDB]>;
5015 // System instructions
5016 def : MnemonicAlias<"swi", "svc">;
5018 // Load / Store Multiple
5019 def : MnemonicAlias<"ldmfd", "ldm">;
5020 def : MnemonicAlias<"ldmia", "ldm">;
5021 def : MnemonicAlias<"ldmea", "ldmdb">;
5022 def : MnemonicAlias<"stmfd", "stmdb">;
5023 def : MnemonicAlias<"stmia", "stm">;
5024 def : MnemonicAlias<"stmea", "stm">;
5026 // PKHBT/PKHTB with default shift amount. PKHTB is equivalent to PKHBT when the
5027 // shift amount is zero (i.e., unspecified).
5028 def : InstAlias<"pkhbt${p} $Rd, $Rn, $Rm",
5029 (PKHBT GPRnopc:$Rd, GPRnopc:$Rn, GPRnopc:$Rm, 0, pred:$p)>,
5030 Requires<[IsARM, HasV6]>;
5031 def : InstAlias<"pkhtb${p} $Rd, $Rn, $Rm",
5032 (PKHBT GPRnopc:$Rd, GPRnopc:$Rn, GPRnopc:$Rm, 0, pred:$p)>,
5033 Requires<[IsARM, HasV6]>;
5035 // PUSH/POP aliases for STM/LDM
5036 def : ARMInstAlias<"push${p} $regs", (STMDB_UPD SP, pred:$p, reglist:$regs)>;
5037 def : ARMInstAlias<"pop${p} $regs", (LDMIA_UPD SP, pred:$p, reglist:$regs)>;
5039 // SSAT/USAT optional shift operand.
5040 def : ARMInstAlias<"ssat${p} $Rd, $sat_imm, $Rn",
5041 (SSAT GPRnopc:$Rd, imm1_32:$sat_imm, GPRnopc:$Rn, 0, pred:$p)>;
5042 def : ARMInstAlias<"usat${p} $Rd, $sat_imm, $Rn",
5043 (USAT GPRnopc:$Rd, imm0_31:$sat_imm, GPRnopc:$Rn, 0, pred:$p)>;
5046 // Extend instruction optional rotate operand.
5047 def : ARMInstAlias<"sxtab${p} $Rd, $Rn, $Rm",
5048 (SXTAB GPRnopc:$Rd, GPR:$Rn, GPRnopc:$Rm, 0, pred:$p)>;
5049 def : ARMInstAlias<"sxtah${p} $Rd, $Rn, $Rm",
5050 (SXTAH GPRnopc:$Rd, GPR:$Rn, GPRnopc:$Rm, 0, pred:$p)>;
5051 def : ARMInstAlias<"sxtab16${p} $Rd, $Rn, $Rm",
5052 (SXTAB16 GPRnopc:$Rd, GPR:$Rn, GPRnopc:$Rm, 0, pred:$p)>;
5053 def : ARMInstAlias<"sxtb${p} $Rd, $Rm",
5054 (SXTB GPRnopc:$Rd, GPRnopc:$Rm, 0, pred:$p)>;
5055 def : ARMInstAlias<"sxtb16${p} $Rd, $Rm",
5056 (SXTB16 GPRnopc:$Rd, GPRnopc:$Rm, 0, pred:$p)>;
5057 def : ARMInstAlias<"sxth${p} $Rd, $Rm",
5058 (SXTH GPRnopc:$Rd, GPRnopc:$Rm, 0, pred:$p)>;
5060 def : ARMInstAlias<"uxtab${p} $Rd, $Rn, $Rm",
5061 (UXTAB GPRnopc:$Rd, GPR:$Rn, GPRnopc:$Rm, 0, pred:$p)>;
5062 def : ARMInstAlias<"uxtah${p} $Rd, $Rn, $Rm",
5063 (UXTAH GPRnopc:$Rd, GPR:$Rn, GPRnopc:$Rm, 0, pred:$p)>;
5064 def : ARMInstAlias<"uxtab16${p} $Rd, $Rn, $Rm",
5065 (UXTAB16 GPRnopc:$Rd, GPR:$Rn, GPRnopc:$Rm, 0, pred:$p)>;
5066 def : ARMInstAlias<"uxtb${p} $Rd, $Rm",
5067 (UXTB GPRnopc:$Rd, GPRnopc:$Rm, 0, pred:$p)>;
5068 def : ARMInstAlias<"uxtb16${p} $Rd, $Rm",
5069 (UXTB16 GPRnopc:$Rd, GPRnopc:$Rm, 0, pred:$p)>;
5070 def : ARMInstAlias<"uxth${p} $Rd, $Rm",
5071 (UXTH GPRnopc:$Rd, GPRnopc:$Rm, 0, pred:$p)>;
5075 def : MnemonicAlias<"rfefa", "rfeda">;
5076 def : MnemonicAlias<"rfeea", "rfedb">;
5077 def : MnemonicAlias<"rfefd", "rfeia">;
5078 def : MnemonicAlias<"rfeed", "rfeib">;
5079 def : MnemonicAlias<"rfe", "rfeia">;
5082 def : MnemonicAlias<"srsfa", "srsda">;
5083 def : MnemonicAlias<"srsea", "srsdb">;
5084 def : MnemonicAlias<"srsfd", "srsia">;
5085 def : MnemonicAlias<"srsed", "srsib">;
5086 def : MnemonicAlias<"srs", "srsia">;
5089 def : MnemonicAlias<"qsubaddx", "qsax">;
5091 def : MnemonicAlias<"saddsubx", "sasx">;
5092 // SHASX == SHADDSUBX
5093 def : MnemonicAlias<"shaddsubx", "shasx">;
5094 // SHSAX == SHSUBADDX
5095 def : MnemonicAlias<"shsubaddx", "shsax">;
5097 def : MnemonicAlias<"ssubaddx", "ssax">;
5099 def : MnemonicAlias<"uaddsubx", "uasx">;
5100 // UHASX == UHADDSUBX
5101 def : MnemonicAlias<"uhaddsubx", "uhasx">;
5102 // UHSAX == UHSUBADDX
5103 def : MnemonicAlias<"uhsubaddx", "uhsax">;
5104 // UQASX == UQADDSUBX
5105 def : MnemonicAlias<"uqaddsubx", "uqasx">;
5106 // UQSAX == UQSUBADDX
5107 def : MnemonicAlias<"uqsubaddx", "uqsax">;
5109 def : MnemonicAlias<"usubaddx", "usax">;
5111 // "mov Rd, so_imm_not" can be handled via "mvn" in assembly, just like
5113 def : ARMInstAlias<"mov${s}${p} $Rd, $imm",
5114 (MVNi rGPR:$Rd, so_imm_not:$imm, pred:$p, cc_out:$s)>;
5115 def : ARMInstAlias<"mvn${s}${p} $Rd, $imm",
5116 (MOVi rGPR:$Rd, so_imm_not:$imm, pred:$p, cc_out:$s)>;
5117 // Same for AND <--> BIC
5118 def : ARMInstAlias<"bic${s}${p} $Rd, $Rn, $imm",
5119 (ANDri rGPR:$Rd, rGPR:$Rn, so_imm_not:$imm,
5120 pred:$p, cc_out:$s)>;
5121 def : ARMInstAlias<"bic${s}${p} $Rdn, $imm",
5122 (ANDri rGPR:$Rdn, rGPR:$Rdn, so_imm_not:$imm,
5123 pred:$p, cc_out:$s)>;
5124 def : ARMInstAlias<"and${s}${p} $Rd, $Rn, $imm",
5125 (BICri rGPR:$Rd, rGPR:$Rn, so_imm_not:$imm,
5126 pred:$p, cc_out:$s)>;
5127 def : ARMInstAlias<"and${s}${p} $Rdn, $imm",
5128 (BICri rGPR:$Rdn, rGPR:$Rdn, so_imm_not:$imm,
5129 pred:$p, cc_out:$s)>;
5131 // Likewise, "add Rd, so_imm_neg" -> sub
5132 def : ARMInstAlias<"add${s}${p} $Rd, $Rn, $imm",
5133 (SUBri GPR:$Rd, GPR:$Rn, so_imm_neg:$imm, pred:$p, cc_out:$s)>;
5134 def : ARMInstAlias<"add${s}${p} $Rd, $imm",
5135 (SUBri GPR:$Rd, GPR:$Rd, so_imm_neg:$imm, pred:$p, cc_out:$s)>;
5136 // Same for CMP <--> CMN via so_imm_neg
5137 def : ARMInstAlias<"cmp${p} $Rd, $imm",
5138 (CMNri rGPR:$Rd, so_imm_neg:$imm, pred:$p)>;
5139 def : ARMInstAlias<"cmn${p} $Rd, $imm",
5140 (CMPri rGPR:$Rd, so_imm_neg:$imm, pred:$p)>;
5142 // The shifter forms of the MOV instruction are aliased to the ASR, LSL,
5143 // LSR, ROR, and RRX instructions.
5144 // FIXME: We need C++ parser hooks to map the alias to the MOV
5145 // encoding. It seems we should be able to do that sort of thing
5146 // in tblgen, but it could get ugly.
5147 let TwoOperandAliasConstraint = "$Rm = $Rd" in {
5148 def ASRi : ARMAsmPseudo<"asr${s}${p} $Rd, $Rm, $imm",
5149 (ins GPR:$Rd, GPR:$Rm, imm0_32:$imm, pred:$p,
5151 def LSRi : ARMAsmPseudo<"lsr${s}${p} $Rd, $Rm, $imm",
5152 (ins GPR:$Rd, GPR:$Rm, imm0_32:$imm, pred:$p,
5154 def LSLi : ARMAsmPseudo<"lsl${s}${p} $Rd, $Rm, $imm",
5155 (ins GPR:$Rd, GPR:$Rm, imm0_31:$imm, pred:$p,
5157 def RORi : ARMAsmPseudo<"ror${s}${p} $Rd, $Rm, $imm",
5158 (ins GPR:$Rd, GPR:$Rm, imm0_31:$imm, pred:$p,
5161 def RRXi : ARMAsmPseudo<"rrx${s}${p} $Rd, $Rm",
5162 (ins GPRnopc:$Rd, GPRnopc:$Rm, pred:$p, cc_out:$s)>;
5163 let TwoOperandAliasConstraint = "$Rn = $Rd" in {
5164 def ASRr : ARMAsmPseudo<"asr${s}${p} $Rd, $Rn, $Rm",
5165 (ins GPRnopc:$Rd, GPRnopc:$Rn, GPRnopc:$Rm, pred:$p,
5167 def LSRr : ARMAsmPseudo<"lsr${s}${p} $Rd, $Rn, $Rm",
5168 (ins GPRnopc:$Rd, GPRnopc:$Rn, GPRnopc:$Rm, pred:$p,
5170 def LSLr : ARMAsmPseudo<"lsl${s}${p} $Rd, $Rn, $Rm",
5171 (ins GPRnopc:$Rd, GPRnopc:$Rn, GPRnopc:$Rm, pred:$p,
5173 def RORr : ARMAsmPseudo<"ror${s}${p} $Rd, $Rn, $Rm",
5174 (ins GPRnopc:$Rd, GPRnopc:$Rn, GPRnopc:$Rm, pred:$p,
5178 // "neg" is and alias for "rsb rd, rn, #0"
5179 def : ARMInstAlias<"neg${s}${p} $Rd, $Rm",
5180 (RSBri GPR:$Rd, GPR:$Rm, 0, pred:$p, cc_out:$s)>;
5182 // Pre-v6, 'mov r0, r0' was used as a NOP encoding.
5183 def : InstAlias<"nop${p}", (MOVr R0, R0, pred:$p, zero_reg)>,
5184 Requires<[IsARM, NoV6]>;
5186 // UMULL/SMULL are available on all arches, but the instruction definitions
5187 // need difference constraints pre-v6. Use these aliases for the assembly
5188 // parsing on pre-v6.
5189 def : InstAlias<"smull${s}${p} $RdLo, $RdHi, $Rn, $Rm",
5190 (SMULL GPR:$RdLo, GPR:$RdHi, GPR:$Rn, GPR:$Rm, pred:$p, cc_out:$s)>,
5191 Requires<[IsARM, NoV6]>;
5192 def : InstAlias<"umull${s}${p} $RdLo, $RdHi, $Rn, $Rm",
5193 (UMULL GPR:$RdLo, GPR:$RdHi, GPR:$Rn, GPR:$Rm, pred:$p, cc_out:$s)>,
5194 Requires<[IsARM, NoV6]>;
5196 // 'it' blocks in ARM mode just validate the predicates. The IT itself
5198 def ITasm : ARMAsmPseudo<"it$mask $cc", (ins it_pred:$cc, it_mask:$mask)>;