1 //===- ARMInstrInfo.td - Target Description for ARM Target -*- tablegen -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file describes the ARM instructions in TableGen format.
12 //===----------------------------------------------------------------------===//
14 //===----------------------------------------------------------------------===//
15 // ARM specific DAG Nodes.
19 def SDT_ARMCallSeqStart : SDCallSeqStart<[ SDTCisVT<0, i32> ]>;
20 def SDT_ARMCallSeqEnd : SDCallSeqEnd<[ SDTCisVT<0, i32>, SDTCisVT<1, i32> ]>;
22 def SDT_ARMSaveCallPC : SDTypeProfile<0, 1, []>;
24 def SDT_ARMcall : SDTypeProfile<0, -1, [SDTCisInt<0>]>;
26 def SDT_ARMCMov : SDTypeProfile<1, 3,
27 [SDTCisSameAs<0, 1>, SDTCisSameAs<0, 2>,
30 def SDT_ARMBrcond : SDTypeProfile<0, 2,
31 [SDTCisVT<0, OtherVT>, SDTCisVT<1, i32>]>;
33 def SDT_ARMBrJT : SDTypeProfile<0, 3,
34 [SDTCisPtrTy<0>, SDTCisVT<1, i32>,
37 def SDT_ARMBr2JT : SDTypeProfile<0, 4,
38 [SDTCisPtrTy<0>, SDTCisVT<1, i32>,
39 SDTCisVT<2, i32>, SDTCisVT<3, i32>]>;
41 def SDT_ARMCmp : SDTypeProfile<0, 2, [SDTCisSameAs<0, 1>]>;
43 def SDT_ARMPICAdd : SDTypeProfile<1, 2, [SDTCisSameAs<0, 1>,
44 SDTCisPtrTy<1>, SDTCisVT<2, i32>]>;
46 def SDT_ARMThreadPointer : SDTypeProfile<1, 0, [SDTCisPtrTy<0>]>;
47 def SDT_ARMEH_SJLJ_Setjmp : SDTypeProfile<1, 1, [SDTCisInt<0>, SDTCisPtrTy<1>]>;
50 def ARMWrapper : SDNode<"ARMISD::Wrapper", SDTIntUnaryOp>;
51 def ARMWrapperJT : SDNode<"ARMISD::WrapperJT", SDTIntBinOp>;
53 def ARMcallseq_start : SDNode<"ISD::CALLSEQ_START", SDT_ARMCallSeqStart,
54 [SDNPHasChain, SDNPOutFlag]>;
55 def ARMcallseq_end : SDNode<"ISD::CALLSEQ_END", SDT_ARMCallSeqEnd,
56 [SDNPHasChain, SDNPOptInFlag, SDNPOutFlag]>;
58 def ARMcall : SDNode<"ARMISD::CALL", SDT_ARMcall,
59 [SDNPHasChain, SDNPOptInFlag, SDNPOutFlag]>;
60 def ARMcall_pred : SDNode<"ARMISD::CALL_PRED", SDT_ARMcall,
61 [SDNPHasChain, SDNPOptInFlag, SDNPOutFlag]>;
62 def ARMcall_nolink : SDNode<"ARMISD::CALL_NOLINK", SDT_ARMcall,
63 [SDNPHasChain, SDNPOptInFlag, SDNPOutFlag]>;
65 def ARMretflag : SDNode<"ARMISD::RET_FLAG", SDTNone,
66 [SDNPHasChain, SDNPOptInFlag]>;
68 def ARMcmov : SDNode<"ARMISD::CMOV", SDT_ARMCMov,
70 def ARMcneg : SDNode<"ARMISD::CNEG", SDT_ARMCMov,
73 def ARMbrcond : SDNode<"ARMISD::BRCOND", SDT_ARMBrcond,
74 [SDNPHasChain, SDNPInFlag, SDNPOutFlag]>;
76 def ARMbrjt : SDNode<"ARMISD::BR_JT", SDT_ARMBrJT,
78 def ARMbr2jt : SDNode<"ARMISD::BR2_JT", SDT_ARMBr2JT,
81 def ARMcmp : SDNode<"ARMISD::CMP", SDT_ARMCmp,
84 def ARMcmpZ : SDNode<"ARMISD::CMPZ", SDT_ARMCmp,
85 [SDNPOutFlag,SDNPCommutative]>;
87 def ARMpic_add : SDNode<"ARMISD::PIC_ADD", SDT_ARMPICAdd>;
89 def ARMsrl_flag : SDNode<"ARMISD::SRL_FLAG", SDTIntUnaryOp, [SDNPOutFlag]>;
90 def ARMsra_flag : SDNode<"ARMISD::SRA_FLAG", SDTIntUnaryOp, [SDNPOutFlag]>;
91 def ARMrrx : SDNode<"ARMISD::RRX" , SDTIntUnaryOp, [SDNPInFlag ]>;
93 def ARMthread_pointer: SDNode<"ARMISD::THREAD_POINTER", SDT_ARMThreadPointer>;
94 def ARMeh_sjlj_setjmp: SDNode<"ARMISD::EH_SJLJ_SETJMP", SDT_ARMEH_SJLJ_Setjmp>;
96 //===----------------------------------------------------------------------===//
97 // ARM Instruction Predicate Definitions.
99 def HasV5T : Predicate<"Subtarget->hasV5TOps()">;
100 def HasV5TE : Predicate<"Subtarget->hasV5TEOps()">;
101 def HasV6 : Predicate<"Subtarget->hasV6Ops()">;
102 def HasV6T2 : Predicate<"Subtarget->hasV6T2Ops()">;
103 def HasV7 : Predicate<"Subtarget->hasV7Ops()">;
104 def HasVFP2 : Predicate<"Subtarget->hasVFP2()">;
105 def HasVFP3 : Predicate<"Subtarget->hasVFP3()">;
106 def HasNEON : Predicate<"Subtarget->hasNEON()">;
107 def UseNEONForFP : Predicate<"Subtarget->useNEONForSinglePrecisionFP()">;
108 def DontUseNEONForFP : Predicate<"!Subtarget->useNEONForSinglePrecisionFP()">;
109 def IsThumb : Predicate<"Subtarget->isThumb()">;
110 def IsThumb1Only : Predicate<"Subtarget->isThumb1Only()">;
111 def IsThumb2 : Predicate<"Subtarget->isThumb2()">;
112 def IsARM : Predicate<"!Subtarget->isThumb()">;
113 def IsDarwin : Predicate<"Subtarget->isTargetDarwin()">;
114 def IsNotDarwin : Predicate<"!Subtarget->isTargetDarwin()">;
115 def CarryDefIsUnused : Predicate<"!N.getNode()->hasAnyUseOfValue(1)">;
116 def CarryDefIsUsed : Predicate<"N.getNode()->hasAnyUseOfValue(1)">;
118 //===----------------------------------------------------------------------===//
119 // ARM Flag Definitions.
121 class RegConstraint<string C> {
122 string Constraints = C;
125 //===----------------------------------------------------------------------===//
126 // ARM specific transformation functions and pattern fragments.
129 // so_imm_neg_XFORM - Return a so_imm value packed into the format described for
130 // so_imm_neg def below.
131 def so_imm_neg_XFORM : SDNodeXForm<imm, [{
132 return CurDAG->getTargetConstant(-(int)N->getZExtValue(), MVT::i32);
135 // so_imm_not_XFORM - Return a so_imm value packed into the format described for
136 // so_imm_not def below.
137 def so_imm_not_XFORM : SDNodeXForm<imm, [{
138 return CurDAG->getTargetConstant(~(int)N->getZExtValue(), MVT::i32);
141 // rot_imm predicate - True if the 32-bit immediate is equal to 8, 16, or 24.
142 def rot_imm : PatLeaf<(i32 imm), [{
143 int32_t v = (int32_t)N->getZExtValue();
144 return v == 8 || v == 16 || v == 24;
147 /// imm1_15 predicate - True if the 32-bit immediate is in the range [1,15].
148 def imm1_15 : PatLeaf<(i32 imm), [{
149 return (int32_t)N->getZExtValue() >= 1 && (int32_t)N->getZExtValue() < 16;
152 /// imm16_31 predicate - True if the 32-bit immediate is in the range [16,31].
153 def imm16_31 : PatLeaf<(i32 imm), [{
154 return (int32_t)N->getZExtValue() >= 16 && (int32_t)N->getZExtValue() < 32;
159 return ARM_AM::getSOImmVal(-(int)N->getZExtValue()) != -1;
160 }], so_imm_neg_XFORM>;
164 return ARM_AM::getSOImmVal(~(int)N->getZExtValue()) != -1;
165 }], so_imm_not_XFORM>;
167 // sext_16_node predicate - True if the SDNode is sign-extended 16 or more bits.
168 def sext_16_node : PatLeaf<(i32 GPR:$a), [{
169 return CurDAG->ComputeNumSignBits(SDValue(N,0)) >= 17;
172 /// bf_inv_mask_imm predicate - An AND mask to clear an arbitrary width bitfield
174 def bf_inv_mask_imm : Operand<i32>,
176 uint32_t v = (uint32_t)N->getZExtValue();
179 // there can be 1's on either or both "outsides", all the "inside"
181 unsigned int lsb = 0, msb = 31;
182 while (v & (1 << msb)) --msb;
183 while (v & (1 << lsb)) ++lsb;
184 for (unsigned int i = lsb; i <= msb; ++i) {
190 let PrintMethod = "printBitfieldInvMaskImmOperand";
193 class BinOpFrag<dag res> : PatFrag<(ops node:$LHS, node:$RHS), res>;
194 class UnOpFrag <dag res> : PatFrag<(ops node:$Src), res>;
196 //===----------------------------------------------------------------------===//
197 // Operand Definitions.
201 def brtarget : Operand<OtherVT>;
203 // A list of registers separated by comma. Used by load/store multiple.
204 def reglist : Operand<i32> {
205 let PrintMethod = "printRegisterList";
208 // An operand for the CONSTPOOL_ENTRY pseudo-instruction.
209 def cpinst_operand : Operand<i32> {
210 let PrintMethod = "printCPInstOperand";
213 def jtblock_operand : Operand<i32> {
214 let PrintMethod = "printJTBlockOperand";
216 def jt2block_operand : Operand<i32> {
217 let PrintMethod = "printJT2BlockOperand";
221 def pclabel : Operand<i32> {
222 let PrintMethod = "printPCLabel";
225 // shifter_operand operands: so_reg and so_imm.
226 def so_reg : Operand<i32>, // reg reg imm
227 ComplexPattern<i32, 3, "SelectShifterOperandReg",
228 [shl,srl,sra,rotr]> {
229 let PrintMethod = "printSORegOperand";
230 let MIOperandInfo = (ops GPR, GPR, i32imm);
233 // so_imm - Match a 32-bit shifter_operand immediate operand, which is an
234 // 8-bit immediate rotated by an arbitrary number of bits. so_imm values are
235 // represented in the imm field in the same 12-bit form that they are encoded
236 // into so_imm instructions: the 8-bit immediate is the least significant bits
237 // [bits 0-7], the 4-bit shift amount is the next 4 bits [bits 8-11].
238 def so_imm : Operand<i32>,
240 return ARM_AM::getSOImmVal(N->getZExtValue()) != -1;
242 let PrintMethod = "printSOImmOperand";
245 // Break so_imm's up into two pieces. This handles immediates with up to 16
246 // bits set in them. This uses so_imm2part to match and so_imm2part_[12] to
247 // get the first/second pieces.
248 def so_imm2part : Operand<i32>,
250 return ARM_AM::isSOImmTwoPartVal((unsigned)N->getZExtValue());
252 let PrintMethod = "printSOImm2PartOperand";
255 def so_imm2part_1 : SDNodeXForm<imm, [{
256 unsigned V = ARM_AM::getSOImmTwoPartFirst((unsigned)N->getZExtValue());
257 return CurDAG->getTargetConstant(V, MVT::i32);
260 def so_imm2part_2 : SDNodeXForm<imm, [{
261 unsigned V = ARM_AM::getSOImmTwoPartSecond((unsigned)N->getZExtValue());
262 return CurDAG->getTargetConstant(V, MVT::i32);
266 // Define ARM specific addressing modes.
268 // addrmode2 := reg +/- reg shop imm
269 // addrmode2 := reg +/- imm12
271 def addrmode2 : Operand<i32>,
272 ComplexPattern<i32, 3, "SelectAddrMode2", []> {
273 let PrintMethod = "printAddrMode2Operand";
274 let MIOperandInfo = (ops GPR:$base, GPR:$offsreg, i32imm:$offsimm);
277 def am2offset : Operand<i32>,
278 ComplexPattern<i32, 2, "SelectAddrMode2Offset", []> {
279 let PrintMethod = "printAddrMode2OffsetOperand";
280 let MIOperandInfo = (ops GPR, i32imm);
283 // addrmode3 := reg +/- reg
284 // addrmode3 := reg +/- imm8
286 def addrmode3 : Operand<i32>,
287 ComplexPattern<i32, 3, "SelectAddrMode3", []> {
288 let PrintMethod = "printAddrMode3Operand";
289 let MIOperandInfo = (ops GPR:$base, GPR:$offsreg, i32imm:$offsimm);
292 def am3offset : Operand<i32>,
293 ComplexPattern<i32, 2, "SelectAddrMode3Offset", []> {
294 let PrintMethod = "printAddrMode3OffsetOperand";
295 let MIOperandInfo = (ops GPR, i32imm);
298 // addrmode4 := reg, <mode|W>
300 def addrmode4 : Operand<i32>,
301 ComplexPattern<i32, 2, "SelectAddrMode4", []> {
302 let PrintMethod = "printAddrMode4Operand";
303 let MIOperandInfo = (ops GPR, i32imm);
306 // addrmode5 := reg +/- imm8*4
308 def addrmode5 : Operand<i32>,
309 ComplexPattern<i32, 2, "SelectAddrMode5", []> {
310 let PrintMethod = "printAddrMode5Operand";
311 let MIOperandInfo = (ops GPR, i32imm);
314 // addrmode6 := reg with optional writeback
316 def addrmode6 : Operand<i32>,
317 ComplexPattern<i32, 3, "SelectAddrMode6", []> {
318 let PrintMethod = "printAddrMode6Operand";
319 let MIOperandInfo = (ops GPR:$addr, GPR:$upd, i32imm);
322 // addrmodepc := pc + reg
324 def addrmodepc : Operand<i32>,
325 ComplexPattern<i32, 2, "SelectAddrModePC", []> {
326 let PrintMethod = "printAddrModePCOperand";
327 let MIOperandInfo = (ops GPR, i32imm);
330 def lane_cst : Operand<i32> {
331 let PrintMethod = "printLaneOperand";
334 //===----------------------------------------------------------------------===//
336 include "ARMInstrFormats.td"
338 //===----------------------------------------------------------------------===//
339 // Multiclass helpers...
342 /// AsI1_bin_irs - Defines a set of (op r, {so_imm|r|so_reg}) patterns for a
343 /// binop that produces a value.
344 multiclass AsI1_bin_irs<bits<4> opcod, string opc, PatFrag opnode,
345 bit Commutable = 0> {
346 def ri : AsI1<opcod, (outs GPR:$dst), (ins GPR:$a, so_imm:$b), DPFrm,
347 IIC_iALU, opc, " $dst, $a, $b",
348 [(set GPR:$dst, (opnode GPR:$a, so_imm:$b))]> {
351 def rr : AsI1<opcod, (outs GPR:$dst), (ins GPR:$a, GPR:$b), DPFrm,
352 IIC_iALU, opc, " $dst, $a, $b",
353 [(set GPR:$dst, (opnode GPR:$a, GPR:$b))]> {
355 let isCommutable = Commutable;
357 def rs : AsI1<opcod, (outs GPR:$dst), (ins GPR:$a, so_reg:$b), DPSoRegFrm,
358 IIC_iALU, opc, " $dst, $a, $b",
359 [(set GPR:$dst, (opnode GPR:$a, so_reg:$b))]> {
364 /// AI1_bin_s_irs - Similar to AsI1_bin_irs except it sets the 's' bit so the
365 /// instruction modifies the CSPR register.
366 let Defs = [CPSR] in {
367 multiclass AI1_bin_s_irs<bits<4> opcod, string opc, PatFrag opnode,
368 bit Commutable = 0> {
369 def ri : AI1<opcod, (outs GPR:$dst), (ins GPR:$a, so_imm:$b), DPFrm,
370 IIC_iALU, opc, "s $dst, $a, $b",
371 [(set GPR:$dst, (opnode GPR:$a, so_imm:$b))]> {
374 def rr : AI1<opcod, (outs GPR:$dst), (ins GPR:$a, GPR:$b), DPFrm,
375 IIC_iALU, opc, "s $dst, $a, $b",
376 [(set GPR:$dst, (opnode GPR:$a, GPR:$b))]> {
377 let isCommutable = Commutable;
380 def rs : AI1<opcod, (outs GPR:$dst), (ins GPR:$a, so_reg:$b), DPSoRegFrm,
381 IIC_iALU, opc, "s $dst, $a, $b",
382 [(set GPR:$dst, (opnode GPR:$a, so_reg:$b))]> {
388 /// AI1_cmp_irs - Defines a set of (op r, {so_imm|r|so_reg}) cmp / test
389 /// patterns. Similar to AsI1_bin_irs except the instruction does not produce
390 /// a explicit result, only implicitly set CPSR.
391 let Defs = [CPSR] in {
392 multiclass AI1_cmp_irs<bits<4> opcod, string opc, PatFrag opnode,
393 bit Commutable = 0> {
394 def ri : AI1<opcod, (outs), (ins GPR:$a, so_imm:$b), DPFrm, IIC_iALU,
396 [(opnode GPR:$a, so_imm:$b)]> {
399 def rr : AI1<opcod, (outs), (ins GPR:$a, GPR:$b), DPFrm, IIC_iALU,
401 [(opnode GPR:$a, GPR:$b)]> {
403 let isCommutable = Commutable;
405 def rs : AI1<opcod, (outs), (ins GPR:$a, so_reg:$b), DPSoRegFrm, IIC_iALU,
407 [(opnode GPR:$a, so_reg:$b)]> {
413 /// AI_unary_rrot - A unary operation with two forms: one whose operand is a
414 /// register and one whose operand is a register rotated by 8/16/24.
415 /// FIXME: Remove the 'r' variant. Its rot_imm is zero.
416 multiclass AI_unary_rrot<bits<8> opcod, string opc, PatFrag opnode> {
417 def r : AExtI<opcod, (outs GPR:$dst), (ins GPR:$Src),
418 IIC_iALU, opc, " $dst, $Src",
419 [(set GPR:$dst, (opnode GPR:$Src))]>,
420 Requires<[IsARM, HasV6]> {
421 let Inst{19-16} = 0b1111;
423 def r_rot : AExtI<opcod, (outs GPR:$dst), (ins GPR:$Src, i32imm:$rot),
424 IIC_iALU, opc, " $dst, $Src, ror $rot",
425 [(set GPR:$dst, (opnode (rotr GPR:$Src, rot_imm:$rot)))]>,
426 Requires<[IsARM, HasV6]> {
427 let Inst{19-16} = 0b1111;
431 /// AI_bin_rrot - A binary operation with two forms: one whose operand is a
432 /// register and one whose operand is a register rotated by 8/16/24.
433 multiclass AI_bin_rrot<bits<8> opcod, string opc, PatFrag opnode> {
434 def rr : AExtI<opcod, (outs GPR:$dst), (ins GPR:$LHS, GPR:$RHS),
435 IIC_iALU, opc, " $dst, $LHS, $RHS",
436 [(set GPR:$dst, (opnode GPR:$LHS, GPR:$RHS))]>,
437 Requires<[IsARM, HasV6]>;
438 def rr_rot : AExtI<opcod, (outs GPR:$dst), (ins GPR:$LHS, GPR:$RHS, i32imm:$rot),
439 IIC_iALU, opc, " $dst, $LHS, $RHS, ror $rot",
440 [(set GPR:$dst, (opnode GPR:$LHS,
441 (rotr GPR:$RHS, rot_imm:$rot)))]>,
442 Requires<[IsARM, HasV6]>;
445 /// AI1_adde_sube_irs - Define instructions and patterns for adde and sube.
446 let Uses = [CPSR] in {
447 multiclass AI1_adde_sube_irs<bits<4> opcod, string opc, PatFrag opnode,
448 bit Commutable = 0> {
449 def ri : AsI1<opcod, (outs GPR:$dst), (ins GPR:$a, so_imm:$b),
450 DPFrm, IIC_iALU, opc, " $dst, $a, $b",
451 [(set GPR:$dst, (opnode GPR:$a, so_imm:$b))]>,
452 Requires<[IsARM, CarryDefIsUnused]> {
455 def rr : AsI1<opcod, (outs GPR:$dst), (ins GPR:$a, GPR:$b),
456 DPFrm, IIC_iALU, opc, " $dst, $a, $b",
457 [(set GPR:$dst, (opnode GPR:$a, GPR:$b))]>,
458 Requires<[IsARM, CarryDefIsUnused]> {
459 let isCommutable = Commutable;
462 def rs : AsI1<opcod, (outs GPR:$dst), (ins GPR:$a, so_reg:$b),
463 DPSoRegFrm, IIC_iALU, opc, " $dst, $a, $b",
464 [(set GPR:$dst, (opnode GPR:$a, so_reg:$b))]>,
465 Requires<[IsARM, CarryDefIsUnused]> {
468 // Carry setting variants
469 def Sri : AXI1<opcod, (outs GPR:$dst), (ins GPR:$a, so_imm:$b),
470 DPFrm, IIC_iALU, !strconcat(opc, "s $dst, $a, $b"),
471 [(set GPR:$dst, (opnode GPR:$a, so_imm:$b))]>,
472 Requires<[IsARM, CarryDefIsUsed]> {
476 def Srr : AXI1<opcod, (outs GPR:$dst), (ins GPR:$a, GPR:$b),
477 DPFrm, IIC_iALU, !strconcat(opc, "s $dst, $a, $b"),
478 [(set GPR:$dst, (opnode GPR:$a, GPR:$b))]>,
479 Requires<[IsARM, CarryDefIsUsed]> {
483 def Srs : AXI1<opcod, (outs GPR:$dst), (ins GPR:$a, so_reg:$b),
484 DPSoRegFrm, IIC_iALU, !strconcat(opc, "s $dst, $a, $b"),
485 [(set GPR:$dst, (opnode GPR:$a, so_reg:$b))]>,
486 Requires<[IsARM, CarryDefIsUsed]> {
493 //===----------------------------------------------------------------------===//
495 //===----------------------------------------------------------------------===//
497 //===----------------------------------------------------------------------===//
498 // Miscellaneous Instructions.
501 /// CONSTPOOL_ENTRY - This instruction represents a floating constant pool in
502 /// the function. The first operand is the ID# for this instruction, the second
503 /// is the index into the MachineConstantPool that this is, the third is the
504 /// size in bytes of this constant pool entry.
505 let neverHasSideEffects = 1, isNotDuplicable = 1 in
506 def CONSTPOOL_ENTRY :
507 PseudoInst<(outs), (ins cpinst_operand:$instid, cpinst_operand:$cpidx,
508 i32imm:$size), NoItinerary,
509 "${instid:label} ${cpidx:cpentry}", []>;
511 let Defs = [SP], Uses = [SP] in {
513 PseudoInst<(outs), (ins i32imm:$amt1, i32imm:$amt2, pred:$p), NoItinerary,
514 "@ ADJCALLSTACKUP $amt1",
515 [(ARMcallseq_end timm:$amt1, timm:$amt2)]>;
517 def ADJCALLSTACKDOWN :
518 PseudoInst<(outs), (ins i32imm:$amt, pred:$p), NoItinerary,
519 "@ ADJCALLSTACKDOWN $amt",
520 [(ARMcallseq_start timm:$amt)]>;
524 PseudoInst<(outs), (ins i32imm:$line, i32imm:$col, i32imm:$file), NoItinerary,
525 ".loc $file, $line, $col",
526 [(dwarf_loc (i32 imm:$line), (i32 imm:$col), (i32 imm:$file))]>;
529 // Address computation and loads and stores in PIC mode.
530 let isNotDuplicable = 1 in {
531 def PICADD : AXI1<0b0100, (outs GPR:$dst), (ins GPR:$a, pclabel:$cp, pred:$p),
532 Pseudo, IIC_iALU, "$cp:\n\tadd$p $dst, pc, $a",
533 [(set GPR:$dst, (ARMpic_add GPR:$a, imm:$cp))]>;
535 let AddedComplexity = 10 in {
536 let canFoldAsLoad = 1 in
537 def PICLDR : AXI2ldw<(outs GPR:$dst), (ins addrmodepc:$addr, pred:$p),
538 Pseudo, IIC_iLoad, "${addr:label}:\n\tldr$p $dst, $addr",
539 [(set GPR:$dst, (load addrmodepc:$addr))]>;
541 def PICLDRH : AXI3ldh<(outs GPR:$dst), (ins addrmodepc:$addr, pred:$p),
542 Pseudo, IIC_iLoad, "${addr:label}:\n\tldr${p}h $dst, $addr",
543 [(set GPR:$dst, (zextloadi16 addrmodepc:$addr))]>;
545 def PICLDRB : AXI2ldb<(outs GPR:$dst), (ins addrmodepc:$addr, pred:$p),
546 Pseudo, IIC_iLoad, "${addr:label}:\n\tldr${p}b $dst, $addr",
547 [(set GPR:$dst, (zextloadi8 addrmodepc:$addr))]>;
549 def PICLDRSH : AXI3ldsh<(outs GPR:$dst), (ins addrmodepc:$addr, pred:$p),
550 Pseudo, IIC_iLoad, "${addr:label}:\n\tldr${p}sh $dst, $addr",
551 [(set GPR:$dst, (sextloadi16 addrmodepc:$addr))]>;
553 def PICLDRSB : AXI3ldsb<(outs GPR:$dst), (ins addrmodepc:$addr, pred:$p),
554 Pseudo, IIC_iLoad, "${addr:label}:\n\tldr${p}sb $dst, $addr",
555 [(set GPR:$dst, (sextloadi8 addrmodepc:$addr))]>;
557 let AddedComplexity = 10 in {
558 def PICSTR : AXI2stw<(outs), (ins GPR:$src, addrmodepc:$addr, pred:$p),
559 Pseudo, IIC_iStore, "${addr:label}:\n\tstr$p $src, $addr",
560 [(store GPR:$src, addrmodepc:$addr)]>;
562 def PICSTRH : AXI3sth<(outs), (ins GPR:$src, addrmodepc:$addr, pred:$p),
563 Pseudo, IIC_iStore, "${addr:label}:\n\tstr${p}h $src, $addr",
564 [(truncstorei16 GPR:$src, addrmodepc:$addr)]>;
566 def PICSTRB : AXI2stb<(outs), (ins GPR:$src, addrmodepc:$addr, pred:$p),
567 Pseudo, IIC_iStore, "${addr:label}:\n\tstr${p}b $src, $addr",
568 [(truncstorei8 GPR:$src, addrmodepc:$addr)]>;
570 } // isNotDuplicable = 1
573 // LEApcrel - Load a pc-relative address into a register without offending the
575 def LEApcrel : AXI1<0x0, (outs GPR:$dst), (ins i32imm:$label, pred:$p),
577 !strconcat(!strconcat(".set ${:private}PCRELV${:uid}, ($label-(",
578 "${:private}PCRELL${:uid}+8))\n"),
579 !strconcat("${:private}PCRELL${:uid}:\n\t",
580 "add$p $dst, pc, #${:private}PCRELV${:uid}")),
583 def LEApcrelJT : AXI1<0x0, (outs GPR:$dst),
584 (ins i32imm:$label, lane_cst:$id, pred:$p),
586 !strconcat(!strconcat(".set ${:private}PCRELV${:uid}, "
588 "${:private}PCRELL${:uid}+8))\n"),
589 !strconcat("${:private}PCRELL${:uid}:\n\t",
590 "add$p $dst, pc, #${:private}PCRELV${:uid}")),
595 //===----------------------------------------------------------------------===//
596 // Control Flow Instructions.
599 let isReturn = 1, isTerminator = 1 in
600 def BX_RET : AI<(outs), (ins), BrMiscFrm, IIC_Br,
601 "bx", " lr", [(ARMretflag)]> {
602 let Inst{7-4} = 0b0001;
603 let Inst{19-8} = 0b111111111111;
604 let Inst{27-20} = 0b00010010;
607 // FIXME: remove when we have a way to marking a MI with these properties.
608 // FIXME: $dst1 should be a def. But the extra ops must be in the end of the
610 // FIXME: Should pc be an implicit operand like PICADD, etc?
611 let isReturn = 1, isTerminator = 1, mayLoad = 1 in
612 def LDM_RET : AXI4ld<(outs),
613 (ins addrmode4:$addr, pred:$p, reglist:$dst1, variable_ops),
614 LdStMulFrm, IIC_Br, "ldm${p}${addr:submode} $addr, $dst1",
617 // On non-Darwin platforms R9 is callee-saved.
618 let isCall = 1, Itinerary = IIC_Br,
619 Defs = [R0, R1, R2, R3, R12, LR,
620 D0, D1, D2, D3, D4, D5, D6, D7,
621 D16, D17, D18, D19, D20, D21, D22, D23,
622 D24, D25, D26, D27, D28, D29, D30, D31, CPSR] in {
623 def BL : ABXI<0b1011, (outs), (ins i32imm:$func, variable_ops),
624 IIC_Br, "bl ${func:call}",
625 [(ARMcall tglobaladdr:$func)]>,
626 Requires<[IsARM, IsNotDarwin]>;
628 def BL_pred : ABI<0b1011, (outs), (ins i32imm:$func, variable_ops),
629 IIC_Br, "bl", " ${func:call}",
630 [(ARMcall_pred tglobaladdr:$func)]>,
631 Requires<[IsARM, IsNotDarwin]>;
634 def BLX : AXI<(outs), (ins GPR:$func, variable_ops), BrMiscFrm,
636 [(ARMcall GPR:$func)]>,
637 Requires<[IsARM, HasV5T, IsNotDarwin]> {
638 let Inst{7-4} = 0b0011;
639 let Inst{19-8} = 0b111111111111;
640 let Inst{27-20} = 0b00010010;
644 def BX : ABXIx2<(outs), (ins GPR:$func, variable_ops),
645 IIC_Br, "mov lr, pc\n\tbx $func",
646 [(ARMcall_nolink GPR:$func)]>,
647 Requires<[IsARM, IsNotDarwin]> {
648 let Inst{7-4} = 0b0001;
649 let Inst{19-8} = 0b111111111111;
650 let Inst{27-20} = 0b00010010;
654 // On Darwin R9 is call-clobbered.
655 let isCall = 1, Itinerary = IIC_Br,
656 Defs = [R0, R1, R2, R3, R9, R12, LR,
657 D0, D1, D2, D3, D4, D5, D6, D7,
658 D16, D17, D18, D19, D20, D21, D22, D23,
659 D24, D25, D26, D27, D28, D29, D30, D31, CPSR] in {
660 def BLr9 : ABXI<0b1011, (outs), (ins i32imm:$func, variable_ops),
661 IIC_Br, "bl ${func:call}",
662 [(ARMcall tglobaladdr:$func)]>, Requires<[IsARM, IsDarwin]>;
664 def BLr9_pred : ABI<0b1011, (outs), (ins i32imm:$func, variable_ops),
665 IIC_Br, "bl", " ${func:call}",
666 [(ARMcall_pred tglobaladdr:$func)]>,
667 Requires<[IsARM, IsDarwin]>;
670 def BLXr9 : AXI<(outs), (ins GPR:$func, variable_ops), BrMiscFrm,
672 [(ARMcall GPR:$func)]>, Requires<[IsARM, HasV5T, IsDarwin]> {
673 let Inst{7-4} = 0b0011;
674 let Inst{19-8} = 0b111111111111;
675 let Inst{27-20} = 0b00010010;
679 def BXr9 : ABXIx2<(outs), (ins GPR:$func, variable_ops),
680 IIC_Br, "mov lr, pc\n\tbx $func",
681 [(ARMcall_nolink GPR:$func)]>, Requires<[IsARM, IsDarwin]> {
682 let Inst{7-4} = 0b0001;
683 let Inst{19-8} = 0b111111111111;
684 let Inst{27-20} = 0b00010010;
688 let isBranch = 1, isTerminator = 1, Itinerary = IIC_Br in {
689 // B is "predicable" since it can be xformed into a Bcc.
690 let isBarrier = 1 in {
691 let isPredicable = 1 in
692 def B : ABXI<0b1010, (outs), (ins brtarget:$target), IIC_Br,
693 "b $target", [(br bb:$target)]>;
695 let isNotDuplicable = 1, isIndirectBranch = 1 in {
696 def BR_JTr : JTI<(outs), (ins GPR:$target, jtblock_operand:$jt, i32imm:$id),
697 IIC_Br, "mov pc, $target \n$jt",
698 [(ARMbrjt GPR:$target, tjumptable:$jt, imm:$id)]> {
699 let Inst{20} = 0; // S Bit
700 let Inst{24-21} = 0b1101;
701 let Inst{27-25} = 0b000;
703 def BR_JTm : JTI<(outs),
704 (ins addrmode2:$target, jtblock_operand:$jt, i32imm:$id),
705 IIC_Br, "ldr pc, $target \n$jt",
706 [(ARMbrjt (i32 (load addrmode2:$target)), tjumptable:$jt,
708 let Inst{20} = 1; // L bit
709 let Inst{21} = 0; // W bit
710 let Inst{22} = 0; // B bit
711 let Inst{24} = 1; // P bit
712 let Inst{27-25} = 0b011;
714 def BR_JTadd : JTI<(outs),
715 (ins GPR:$target, GPR:$idx, jtblock_operand:$jt, i32imm:$id),
716 IIC_Br, "add pc, $target, $idx \n$jt",
717 [(ARMbrjt (add GPR:$target, GPR:$idx), tjumptable:$jt,
719 let Inst{20} = 0; // S bit
720 let Inst{24-21} = 0b0100;
721 let Inst{27-25} = 0b000;
723 } // isNotDuplicable = 1, isIndirectBranch = 1
726 // FIXME: should be able to write a pattern for ARMBrcond, but can't use
727 // a two-value operand where a dag node expects two operands. :(
728 def Bcc : ABI<0b1010, (outs), (ins brtarget:$target),
729 IIC_Br, "b", " $target",
730 [/*(ARMbrcond bb:$target, imm:$cc, CCR:$ccr)*/]>;
733 //===----------------------------------------------------------------------===//
734 // Load / store Instructions.
738 let canFoldAsLoad = 1 in
739 def LDR : AI2ldw<(outs GPR:$dst), (ins addrmode2:$addr), LdFrm, IIC_iLoad,
740 "ldr", " $dst, $addr",
741 [(set GPR:$dst, (load addrmode2:$addr))]>;
743 // Special LDR for loads from non-pc-relative constpools.
744 let canFoldAsLoad = 1, mayLoad = 1, isReMaterializable = 1 in
745 def LDRcp : AI2ldw<(outs GPR:$dst), (ins addrmode2:$addr), LdFrm, IIC_iLoad,
746 "ldr", " $dst, $addr", []>;
748 // Loads with zero extension
749 def LDRH : AI3ldh<(outs GPR:$dst), (ins addrmode3:$addr), LdMiscFrm, IIC_iLoad,
750 "ldr", "h $dst, $addr",
751 [(set GPR:$dst, (zextloadi16 addrmode3:$addr))]>;
753 def LDRB : AI2ldb<(outs GPR:$dst), (ins addrmode2:$addr), LdFrm, IIC_iLoad,
754 "ldr", "b $dst, $addr",
755 [(set GPR:$dst, (zextloadi8 addrmode2:$addr))]>;
757 // Loads with sign extension
758 def LDRSH : AI3ldsh<(outs GPR:$dst), (ins addrmode3:$addr), LdMiscFrm, IIC_iLoad,
759 "ldr", "sh $dst, $addr",
760 [(set GPR:$dst, (sextloadi16 addrmode3:$addr))]>;
762 def LDRSB : AI3ldsb<(outs GPR:$dst), (ins addrmode3:$addr), LdMiscFrm, IIC_iLoad,
763 "ldr", "sb $dst, $addr",
764 [(set GPR:$dst, (sextloadi8 addrmode3:$addr))]>;
768 def LDRD : AI3ldd<(outs GPR:$dst1, GPR:$dst2), (ins addrmode3:$addr), LdMiscFrm,
769 IIC_iLoad, "ldr", "d $dst1, $addr", []>, Requires<[IsARM, HasV5T]>;
772 def LDR_PRE : AI2ldwpr<(outs GPR:$dst, GPR:$base_wb),
773 (ins addrmode2:$addr), LdFrm, IIC_iLoad,
774 "ldr", " $dst, $addr!", "$addr.base = $base_wb", []>;
776 def LDR_POST : AI2ldwpo<(outs GPR:$dst, GPR:$base_wb),
777 (ins GPR:$base, am2offset:$offset), LdFrm, IIC_iLoad,
778 "ldr", " $dst, [$base], $offset", "$base = $base_wb", []>;
780 def LDRH_PRE : AI3ldhpr<(outs GPR:$dst, GPR:$base_wb),
781 (ins addrmode3:$addr), LdMiscFrm, IIC_iLoad,
782 "ldr", "h $dst, $addr!", "$addr.base = $base_wb", []>;
784 def LDRH_POST : AI3ldhpo<(outs GPR:$dst, GPR:$base_wb),
785 (ins GPR:$base,am3offset:$offset), LdMiscFrm, IIC_iLoad,
786 "ldr", "h $dst, [$base], $offset", "$base = $base_wb", []>;
788 def LDRB_PRE : AI2ldbpr<(outs GPR:$dst, GPR:$base_wb),
789 (ins addrmode2:$addr), LdFrm, IIC_iLoad,
790 "ldr", "b $dst, $addr!", "$addr.base = $base_wb", []>;
792 def LDRB_POST : AI2ldbpo<(outs GPR:$dst, GPR:$base_wb),
793 (ins GPR:$base,am2offset:$offset), LdFrm, IIC_iLoad,
794 "ldr", "b $dst, [$base], $offset", "$base = $base_wb", []>;
796 def LDRSH_PRE : AI3ldshpr<(outs GPR:$dst, GPR:$base_wb),
797 (ins addrmode3:$addr), LdMiscFrm, IIC_iLoad,
798 "ldr", "sh $dst, $addr!", "$addr.base = $base_wb", []>;
800 def LDRSH_POST: AI3ldshpo<(outs GPR:$dst, GPR:$base_wb),
801 (ins GPR:$base,am3offset:$offset), LdMiscFrm, IIC_iLoad,
802 "ldr", "sh $dst, [$base], $offset", "$base = $base_wb", []>;
804 def LDRSB_PRE : AI3ldsbpr<(outs GPR:$dst, GPR:$base_wb),
805 (ins addrmode3:$addr), LdMiscFrm, IIC_iLoad,
806 "ldr", "sb $dst, $addr!", "$addr.base = $base_wb", []>;
808 def LDRSB_POST: AI3ldsbpo<(outs GPR:$dst, GPR:$base_wb),
809 (ins GPR:$base,am3offset:$offset), LdMiscFrm, IIC_iLoad,
810 "ldr", "sb $dst, [$base], $offset", "$base = $base_wb", []>;
814 def STR : AI2stw<(outs), (ins GPR:$src, addrmode2:$addr), StFrm, IIC_iStore,
815 "str", " $src, $addr",
816 [(store GPR:$src, addrmode2:$addr)]>;
818 // Stores with truncate
819 def STRH : AI3sth<(outs), (ins GPR:$src, addrmode3:$addr), StMiscFrm, IIC_iStore,
820 "str", "h $src, $addr",
821 [(truncstorei16 GPR:$src, addrmode3:$addr)]>;
823 def STRB : AI2stb<(outs), (ins GPR:$src, addrmode2:$addr), StFrm, IIC_iStore,
824 "str", "b $src, $addr",
825 [(truncstorei8 GPR:$src, addrmode2:$addr)]>;
829 def STRD : AI3std<(outs), (ins GPR:$src1, GPR:$src2, addrmode3:$addr),
830 StMiscFrm, IIC_iStore,
831 "str", "d $src1, $addr", []>, Requires<[IsARM, HasV5T]>;
834 def STR_PRE : AI2stwpr<(outs GPR:$base_wb),
835 (ins GPR:$src, GPR:$base, am2offset:$offset),
837 "str", " $src, [$base, $offset]!", "$base = $base_wb",
839 (pre_store GPR:$src, GPR:$base, am2offset:$offset))]>;
841 def STR_POST : AI2stwpo<(outs GPR:$base_wb),
842 (ins GPR:$src, GPR:$base,am2offset:$offset),
844 "str", " $src, [$base], $offset", "$base = $base_wb",
846 (post_store GPR:$src, GPR:$base, am2offset:$offset))]>;
848 def STRH_PRE : AI3sthpr<(outs GPR:$base_wb),
849 (ins GPR:$src, GPR:$base,am3offset:$offset),
850 StMiscFrm, IIC_iStore,
851 "str", "h $src, [$base, $offset]!", "$base = $base_wb",
853 (pre_truncsti16 GPR:$src, GPR:$base,am3offset:$offset))]>;
855 def STRH_POST: AI3sthpo<(outs GPR:$base_wb),
856 (ins GPR:$src, GPR:$base,am3offset:$offset),
857 StMiscFrm, IIC_iStore,
858 "str", "h $src, [$base], $offset", "$base = $base_wb",
859 [(set GPR:$base_wb, (post_truncsti16 GPR:$src,
860 GPR:$base, am3offset:$offset))]>;
862 def STRB_PRE : AI2stbpr<(outs GPR:$base_wb),
863 (ins GPR:$src, GPR:$base,am2offset:$offset),
865 "str", "b $src, [$base, $offset]!", "$base = $base_wb",
866 [(set GPR:$base_wb, (pre_truncsti8 GPR:$src,
867 GPR:$base, am2offset:$offset))]>;
869 def STRB_POST: AI2stbpo<(outs GPR:$base_wb),
870 (ins GPR:$src, GPR:$base,am2offset:$offset),
872 "str", "b $src, [$base], $offset", "$base = $base_wb",
873 [(set GPR:$base_wb, (post_truncsti8 GPR:$src,
874 GPR:$base, am2offset:$offset))]>;
876 //===----------------------------------------------------------------------===//
877 // Load / store multiple Instructions.
880 // FIXME: $dst1 should be a def.
882 def LDM : AXI4ld<(outs),
883 (ins addrmode4:$addr, pred:$p, reglist:$dst1, variable_ops),
884 LdStMulFrm, IIC_iLoad, "ldm${p}${addr:submode} $addr, $dst1",
888 def STM : AXI4st<(outs),
889 (ins addrmode4:$addr, pred:$p, reglist:$src1, variable_ops),
890 LdStMulFrm, IIC_iStore, "stm${p}${addr:submode} $addr, $src1",
893 //===----------------------------------------------------------------------===//
894 // Move Instructions.
897 let neverHasSideEffects = 1 in
898 def MOVr : AsI1<0b1101, (outs GPR:$dst), (ins GPR:$src), DPFrm, IIC_iALU,
899 "mov", " $dst, $src", []>, UnaryDP;
900 def MOVs : AsI1<0b1101, (outs GPR:$dst), (ins so_reg:$src),
901 DPSoRegFrm, IIC_iALU,
902 "mov", " $dst, $src", [(set GPR:$dst, so_reg:$src)]>, UnaryDP;
904 let isReMaterializable = 1, isAsCheapAsAMove = 1 in
905 def MOVi : AsI1<0b1101, (outs GPR:$dst), (ins so_imm:$src), DPFrm, IIC_iALU,
906 "mov", " $dst, $src", [(set GPR:$dst, so_imm:$src)]>, UnaryDP;
908 def MOVrx : AsI1<0b1101, (outs GPR:$dst), (ins GPR:$src), Pseudo, IIC_iALU,
909 "mov", " $dst, $src, rrx",
910 [(set GPR:$dst, (ARMrrx GPR:$src))]>, UnaryDP;
912 // These aren't really mov instructions, but we have to define them this way
913 // due to flag operands.
915 let Defs = [CPSR] in {
916 def MOVsrl_flag : AI1<0b1101, (outs GPR:$dst), (ins GPR:$src), Pseudo,
917 IIC_iALU, "mov", "s $dst, $src, lsr #1",
918 [(set GPR:$dst, (ARMsrl_flag GPR:$src))]>, UnaryDP;
919 def MOVsra_flag : AI1<0b1101, (outs GPR:$dst), (ins GPR:$src), Pseudo,
920 IIC_iALU, "mov", "s $dst, $src, asr #1",
921 [(set GPR:$dst, (ARMsra_flag GPR:$src))]>, UnaryDP;
924 //===----------------------------------------------------------------------===//
925 // Extend Instructions.
930 defm SXTB : AI_unary_rrot<0b01101010,
931 "sxtb", UnOpFrag<(sext_inreg node:$Src, i8)>>;
932 defm SXTH : AI_unary_rrot<0b01101011,
933 "sxth", UnOpFrag<(sext_inreg node:$Src, i16)>>;
935 defm SXTAB : AI_bin_rrot<0b01101010,
936 "sxtab", BinOpFrag<(add node:$LHS, (sext_inreg node:$RHS, i8))>>;
937 defm SXTAH : AI_bin_rrot<0b01101011,
938 "sxtah", BinOpFrag<(add node:$LHS, (sext_inreg node:$RHS,i16))>>;
940 // TODO: SXT(A){B|H}16
944 let AddedComplexity = 16 in {
945 defm UXTB : AI_unary_rrot<0b01101110,
946 "uxtb" , UnOpFrag<(and node:$Src, 0x000000FF)>>;
947 defm UXTH : AI_unary_rrot<0b01101111,
948 "uxth" , UnOpFrag<(and node:$Src, 0x0000FFFF)>>;
949 defm UXTB16 : AI_unary_rrot<0b01101100,
950 "uxtb16", UnOpFrag<(and node:$Src, 0x00FF00FF)>>;
952 def : ARMV6Pat<(and (shl GPR:$Src, (i32 8)), 0xFF00FF),
953 (UXTB16r_rot GPR:$Src, 24)>;
954 def : ARMV6Pat<(and (srl GPR:$Src, (i32 8)), 0xFF00FF),
955 (UXTB16r_rot GPR:$Src, 8)>;
957 defm UXTAB : AI_bin_rrot<0b01101110, "uxtab",
958 BinOpFrag<(add node:$LHS, (and node:$RHS, 0x00FF))>>;
959 defm UXTAH : AI_bin_rrot<0b01101111, "uxtah",
960 BinOpFrag<(add node:$LHS, (and node:$RHS, 0xFFFF))>>;
963 // This isn't safe in general, the add is two 16-bit units, not a 32-bit add.
964 //defm UXTAB16 : xxx<"uxtab16", 0xff00ff>;
966 // TODO: UXT(A){B|H}16
968 //===----------------------------------------------------------------------===//
969 // Arithmetic Instructions.
972 defm ADD : AsI1_bin_irs<0b0100, "add",
973 BinOpFrag<(add node:$LHS, node:$RHS)>, 1>;
974 defm SUB : AsI1_bin_irs<0b0010, "sub",
975 BinOpFrag<(sub node:$LHS, node:$RHS)>>;
977 // ADD and SUB with 's' bit set.
978 defm ADDS : AI1_bin_s_irs<0b0100, "add",
979 BinOpFrag<(addc node:$LHS, node:$RHS)>>;
980 defm SUBS : AI1_bin_s_irs<0b0010, "sub",
981 BinOpFrag<(subc node:$LHS, node:$RHS)>>;
983 defm ADC : AI1_adde_sube_irs<0b0101, "adc",
984 BinOpFrag<(adde node:$LHS, node:$RHS)>, 1>;
985 defm SBC : AI1_adde_sube_irs<0b0110, "sbc",
986 BinOpFrag<(sube node:$LHS, node:$RHS)>>;
988 // These don't define reg/reg forms, because they are handled above.
989 def RSBri : AsI1<0b0011, (outs GPR:$dst), (ins GPR:$a, so_imm:$b), DPFrm,
990 IIC_iALU, "rsb", " $dst, $a, $b",
991 [(set GPR:$dst, (sub so_imm:$b, GPR:$a))]>;
993 def RSBrs : AsI1<0b0011, (outs GPR:$dst), (ins GPR:$a, so_reg:$b), DPSoRegFrm,
994 IIC_iALU, "rsb", " $dst, $a, $b",
995 [(set GPR:$dst, (sub so_reg:$b, GPR:$a))]>;
997 // RSB with 's' bit set.
998 let Defs = [CPSR] in {
999 def RSBSri : AI1<0b0011, (outs GPR:$dst), (ins GPR:$a, so_imm:$b), DPFrm,
1000 IIC_iALU, "rsb", "s $dst, $a, $b",
1001 [(set GPR:$dst, (subc so_imm:$b, GPR:$a))]>;
1002 def RSBSrs : AI1<0b0011, (outs GPR:$dst), (ins GPR:$a, so_reg:$b), DPSoRegFrm,
1003 IIC_iALU, "rsb", "s $dst, $a, $b",
1004 [(set GPR:$dst, (subc so_reg:$b, GPR:$a))]>;
1007 let Uses = [CPSR] in {
1008 def RSCri : AsI1<0b0111, (outs GPR:$dst), (ins GPR:$a, so_imm:$b),
1009 DPFrm, IIC_iALU, "rsc", " $dst, $a, $b",
1010 [(set GPR:$dst, (sube so_imm:$b, GPR:$a))]>,
1011 Requires<[IsARM, CarryDefIsUnused]>;
1012 def RSCrs : AsI1<0b0111, (outs GPR:$dst), (ins GPR:$a, so_reg:$b),
1013 DPSoRegFrm, IIC_iALU, "rsc", " $dst, $a, $b",
1014 [(set GPR:$dst, (sube so_reg:$b, GPR:$a))]>,
1015 Requires<[IsARM, CarryDefIsUnused]>;
1018 // FIXME: Allow these to be predicated.
1019 let Defs = [CPSR], Uses = [CPSR] in {
1020 def RSCSri : AXI1<0b0111, (outs GPR:$dst), (ins GPR:$a, so_imm:$b),
1021 DPFrm, IIC_iALU, "rscs $dst, $a, $b",
1022 [(set GPR:$dst, (sube so_imm:$b, GPR:$a))]>,
1023 Requires<[IsARM, CarryDefIsUnused]>;
1024 def RSCSrs : AXI1<0b0111, (outs GPR:$dst), (ins GPR:$a, so_reg:$b),
1025 DPSoRegFrm, IIC_iALU, "rscs $dst, $a, $b",
1026 [(set GPR:$dst, (sube so_reg:$b, GPR:$a))]>,
1027 Requires<[IsARM, CarryDefIsUnused]>;
1030 // (sub X, imm) gets canonicalized to (add X, -imm). Match this form.
1031 def : ARMPat<(add GPR:$src, so_imm_neg:$imm),
1032 (SUBri GPR:$src, so_imm_neg:$imm)>;
1034 //def : ARMPat<(addc GPR:$src, so_imm_neg:$imm),
1035 // (SUBSri GPR:$src, so_imm_neg:$imm)>;
1036 //def : ARMPat<(adde GPR:$src, so_imm_neg:$imm),
1037 // (SBCri GPR:$src, so_imm_neg:$imm)>;
1039 // Note: These are implemented in C++ code, because they have to generate
1040 // ADD/SUBrs instructions, which use a complex pattern that a xform function
1042 // (mul X, 2^n+1) -> (add (X << n), X)
1043 // (mul X, 2^n-1) -> (rsb X, (X << n))
1046 //===----------------------------------------------------------------------===//
1047 // Bitwise Instructions.
1050 defm AND : AsI1_bin_irs<0b0000, "and",
1051 BinOpFrag<(and node:$LHS, node:$RHS)>, 1>;
1052 defm ORR : AsI1_bin_irs<0b1100, "orr",
1053 BinOpFrag<(or node:$LHS, node:$RHS)>, 1>;
1054 defm EOR : AsI1_bin_irs<0b0001, "eor",
1055 BinOpFrag<(xor node:$LHS, node:$RHS)>, 1>;
1056 defm BIC : AsI1_bin_irs<0b1110, "bic",
1057 BinOpFrag<(and node:$LHS, (not node:$RHS))>>;
1059 def BFC : I<(outs GPR:$dst), (ins GPR:$src, bf_inv_mask_imm:$imm),
1060 AddrMode1, Size4Bytes, IndexModeNone, DPFrm, NoItinerary,
1061 "bfc", " $dst, $imm", "$src = $dst",
1062 [(set GPR:$dst, (and GPR:$src, bf_inv_mask_imm:$imm))]>,
1063 Requires<[IsARM, HasV6T2]> {
1064 let Inst{27-21} = 0b0111110;
1065 let Inst{6-0} = 0b0011111;
1068 def MVNr : AsI1<0b1111, (outs GPR:$dst), (ins GPR:$src), DPFrm, IIC_iALU,
1069 "mvn", " $dst, $src",
1070 [(set GPR:$dst, (not GPR:$src))]>, UnaryDP;
1071 def MVNs : AsI1<0b1111, (outs GPR:$dst), (ins so_reg:$src), DPSoRegFrm,
1072 IIC_iALU, "mvn", " $dst, $src",
1073 [(set GPR:$dst, (not so_reg:$src))]>, UnaryDP;
1074 let isReMaterializable = 1, isAsCheapAsAMove = 1 in
1075 def MVNi : AsI1<0b1111, (outs GPR:$dst), (ins so_imm:$imm), DPFrm, IIC_iALU,
1076 "mvn", " $dst, $imm",
1077 [(set GPR:$dst, so_imm_not:$imm)]>,UnaryDP;
1079 def : ARMPat<(and GPR:$src, so_imm_not:$imm),
1080 (BICri GPR:$src, so_imm_not:$imm)>;
1082 //===----------------------------------------------------------------------===//
1083 // Multiply Instructions.
1086 let isCommutable = 1 in
1087 def MUL : AsMul1I<0b0000000, (outs GPR:$dst), (ins GPR:$a, GPR:$b), IIC_iALU,
1088 "mul", " $dst, $a, $b",
1089 [(set GPR:$dst, (mul GPR:$a, GPR:$b))]>;
1091 def MLA : AsMul1I<0b0000001, (outs GPR:$dst), (ins GPR:$a, GPR:$b, GPR:$c),
1092 IIC_iALU, "mla", " $dst, $a, $b, $c",
1093 [(set GPR:$dst, (add (mul GPR:$a, GPR:$b), GPR:$c))]>;
1095 def MLS : AMul1I<0b0000011, (outs GPR:$dst), (ins GPR:$a, GPR:$b, GPR:$c),
1096 IIC_iALU, "mls", " $dst, $a, $b, $c",
1097 [(set GPR:$dst, (sub GPR:$c, (mul GPR:$a, GPR:$b)))]>,
1098 Requires<[IsARM, HasV6T2]>;
1100 // Extra precision multiplies with low / high results
1101 let neverHasSideEffects = 1 in {
1102 let isCommutable = 1 in {
1103 def SMULL : AsMul1I<0b0000110, (outs GPR:$ldst, GPR:$hdst),
1104 (ins GPR:$a, GPR:$b), IIC_iALU,
1105 "smull", " $ldst, $hdst, $a, $b", []>;
1107 def UMULL : AsMul1I<0b0000100, (outs GPR:$ldst, GPR:$hdst),
1108 (ins GPR:$a, GPR:$b), IIC_iALU,
1109 "umull", " $ldst, $hdst, $a, $b", []>;
1112 // Multiply + accumulate
1113 def SMLAL : AsMul1I<0b0000111, (outs GPR:$ldst, GPR:$hdst),
1114 (ins GPR:$a, GPR:$b), IIC_iALU,
1115 "smlal", " $ldst, $hdst, $a, $b", []>;
1117 def UMLAL : AsMul1I<0b0000101, (outs GPR:$ldst, GPR:$hdst),
1118 (ins GPR:$a, GPR:$b), IIC_iALU,
1119 "umlal", " $ldst, $hdst, $a, $b", []>;
1121 def UMAAL : AMul1I <0b0000010, (outs GPR:$ldst, GPR:$hdst),
1122 (ins GPR:$a, GPR:$b), IIC_iALU,
1123 "umaal", " $ldst, $hdst, $a, $b", []>,
1124 Requires<[IsARM, HasV6]>;
1125 } // neverHasSideEffects
1127 // Most significant word multiply
1128 def SMMUL : AMul2I <0b0111010, (outs GPR:$dst), (ins GPR:$a, GPR:$b),
1129 IIC_iALU, "smmul", " $dst, $a, $b",
1130 [(set GPR:$dst, (mulhs GPR:$a, GPR:$b))]>,
1131 Requires<[IsARM, HasV6]> {
1132 let Inst{7-4} = 0b0001;
1133 let Inst{15-12} = 0b1111;
1136 def SMMLA : AMul2I <0b0111010, (outs GPR:$dst), (ins GPR:$a, GPR:$b, GPR:$c),
1137 IIC_iALU, "smmla", " $dst, $a, $b, $c",
1138 [(set GPR:$dst, (add (mulhs GPR:$a, GPR:$b), GPR:$c))]>,
1139 Requires<[IsARM, HasV6]> {
1140 let Inst{7-4} = 0b0001;
1144 def SMMLS : AMul2I <0b0111010, (outs GPR:$dst), (ins GPR:$a, GPR:$b, GPR:$c),
1145 IIC_iALU, "smmls", " $dst, $a, $b, $c",
1146 [(set GPR:$dst, (sub GPR:$c, (mulhs GPR:$a, GPR:$b)))]>,
1147 Requires<[IsARM, HasV6]> {
1148 let Inst{7-4} = 0b1101;
1151 multiclass AI_smul<string opc, PatFrag opnode> {
1152 def BB : AMulxyI<0b0001011, (outs GPR:$dst), (ins GPR:$a, GPR:$b),
1153 IIC_iALU, !strconcat(opc, "bb"), " $dst, $a, $b",
1154 [(set GPR:$dst, (opnode (sext_inreg GPR:$a, i16),
1155 (sext_inreg GPR:$b, i16)))]>,
1156 Requires<[IsARM, HasV5TE]> {
1161 def BT : AMulxyI<0b0001011, (outs GPR:$dst), (ins GPR:$a, GPR:$b),
1162 IIC_iALU, !strconcat(opc, "bt"), " $dst, $a, $b",
1163 [(set GPR:$dst, (opnode (sext_inreg GPR:$a, i16),
1164 (sra GPR:$b, (i32 16))))]>,
1165 Requires<[IsARM, HasV5TE]> {
1170 def TB : AMulxyI<0b0001011, (outs GPR:$dst), (ins GPR:$a, GPR:$b),
1171 IIC_iALU, !strconcat(opc, "tb"), " $dst, $a, $b",
1172 [(set GPR:$dst, (opnode (sra GPR:$a, (i32 16)),
1173 (sext_inreg GPR:$b, i16)))]>,
1174 Requires<[IsARM, HasV5TE]> {
1179 def TT : AMulxyI<0b0001011, (outs GPR:$dst), (ins GPR:$a, GPR:$b),
1180 IIC_iALU, !strconcat(opc, "tt"), " $dst, $a, $b",
1181 [(set GPR:$dst, (opnode (sra GPR:$a, (i32 16)),
1182 (sra GPR:$b, (i32 16))))]>,
1183 Requires<[IsARM, HasV5TE]> {
1188 def WB : AMulxyI<0b0001001, (outs GPR:$dst), (ins GPR:$a, GPR:$b),
1189 IIC_iALU, !strconcat(opc, "wb"), " $dst, $a, $b",
1190 [(set GPR:$dst, (sra (opnode GPR:$a,
1191 (sext_inreg GPR:$b, i16)), (i32 16)))]>,
1192 Requires<[IsARM, HasV5TE]> {
1197 def WT : AMulxyI<0b0001001, (outs GPR:$dst), (ins GPR:$a, GPR:$b),
1198 IIC_iALU, !strconcat(opc, "wt"), " $dst, $a, $b",
1199 [(set GPR:$dst, (sra (opnode GPR:$a,
1200 (sra GPR:$b, (i32 16))), (i32 16)))]>,
1201 Requires<[IsARM, HasV5TE]> {
1208 multiclass AI_smla<string opc, PatFrag opnode> {
1209 def BB : AMulxyI<0b0001000, (outs GPR:$dst), (ins GPR:$a, GPR:$b, GPR:$acc),
1210 IIC_iALU, !strconcat(opc, "bb"), " $dst, $a, $b, $acc",
1211 [(set GPR:$dst, (add GPR:$acc,
1212 (opnode (sext_inreg GPR:$a, i16),
1213 (sext_inreg GPR:$b, i16))))]>,
1214 Requires<[IsARM, HasV5TE]> {
1219 def BT : AMulxyI<0b0001000, (outs GPR:$dst), (ins GPR:$a, GPR:$b, GPR:$acc),
1220 IIC_iALU, !strconcat(opc, "bt"), " $dst, $a, $b, $acc",
1221 [(set GPR:$dst, (add GPR:$acc, (opnode (sext_inreg GPR:$a, i16),
1222 (sra GPR:$b, (i32 16)))))]>,
1223 Requires<[IsARM, HasV5TE]> {
1228 def TB : AMulxyI<0b0001000, (outs GPR:$dst), (ins GPR:$a, GPR:$b, GPR:$acc),
1229 IIC_iALU, !strconcat(opc, "tb"), " $dst, $a, $b, $acc",
1230 [(set GPR:$dst, (add GPR:$acc, (opnode (sra GPR:$a, (i32 16)),
1231 (sext_inreg GPR:$b, i16))))]>,
1232 Requires<[IsARM, HasV5TE]> {
1237 def TT : AMulxyI<0b0001000, (outs GPR:$dst), (ins GPR:$a, GPR:$b, GPR:$acc),
1238 IIC_iALU, !strconcat(opc, "tt"), " $dst, $a, $b, $acc",
1239 [(set GPR:$dst, (add GPR:$acc, (opnode (sra GPR:$a, (i32 16)),
1240 (sra GPR:$b, (i32 16)))))]>,
1241 Requires<[IsARM, HasV5TE]> {
1246 def WB : AMulxyI<0b0001001, (outs GPR:$dst), (ins GPR:$a, GPR:$b, GPR:$acc),
1247 IIC_iALU, !strconcat(opc, "wb"), " $dst, $a, $b, $acc",
1248 [(set GPR:$dst, (add GPR:$acc, (sra (opnode GPR:$a,
1249 (sext_inreg GPR:$b, i16)), (i32 16))))]>,
1250 Requires<[IsARM, HasV5TE]> {
1255 def WT : AMulxyI<0b0001001, (outs GPR:$dst), (ins GPR:$a, GPR:$b, GPR:$acc),
1256 IIC_iALU, !strconcat(opc, "wt"), " $dst, $a, $b, $acc",
1257 [(set GPR:$dst, (add GPR:$acc, (sra (opnode GPR:$a,
1258 (sra GPR:$b, (i32 16))), (i32 16))))]>,
1259 Requires<[IsARM, HasV5TE]> {
1265 defm SMUL : AI_smul<"smul", BinOpFrag<(mul node:$LHS, node:$RHS)>>;
1266 defm SMLA : AI_smla<"smla", BinOpFrag<(mul node:$LHS, node:$RHS)>>;
1268 // TODO: Halfword multiple accumulate long: SMLAL<x><y>
1269 // TODO: Dual halfword multiple: SMUAD, SMUSD, SMLAD, SMLSD, SMLALD, SMLSLD
1271 //===----------------------------------------------------------------------===//
1272 // Misc. Arithmetic Instructions.
1275 def CLZ : AMiscA1I<0b000010110, (outs GPR:$dst), (ins GPR:$src), IIC_iALU,
1276 "clz", " $dst, $src",
1277 [(set GPR:$dst, (ctlz GPR:$src))]>, Requires<[IsARM, HasV5T]> {
1278 let Inst{7-4} = 0b0001;
1279 let Inst{11-8} = 0b1111;
1280 let Inst{19-16} = 0b1111;
1283 def REV : AMiscA1I<0b01101011, (outs GPR:$dst), (ins GPR:$src), IIC_iALU,
1284 "rev", " $dst, $src",
1285 [(set GPR:$dst, (bswap GPR:$src))]>, Requires<[IsARM, HasV6]> {
1286 let Inst{7-4} = 0b0011;
1287 let Inst{11-8} = 0b1111;
1288 let Inst{19-16} = 0b1111;
1291 def REV16 : AMiscA1I<0b01101011, (outs GPR:$dst), (ins GPR:$src), IIC_iALU,
1292 "rev16", " $dst, $src",
1294 (or (and (srl GPR:$src, (i32 8)), 0xFF),
1295 (or (and (shl GPR:$src, (i32 8)), 0xFF00),
1296 (or (and (srl GPR:$src, (i32 8)), 0xFF0000),
1297 (and (shl GPR:$src, (i32 8)), 0xFF000000)))))]>,
1298 Requires<[IsARM, HasV6]> {
1299 let Inst{7-4} = 0b1011;
1300 let Inst{11-8} = 0b1111;
1301 let Inst{19-16} = 0b1111;
1304 def REVSH : AMiscA1I<0b01101111, (outs GPR:$dst), (ins GPR:$src), IIC_iALU,
1305 "revsh", " $dst, $src",
1308 (or (srl (and GPR:$src, 0xFF00), (i32 8)),
1309 (shl GPR:$src, (i32 8))), i16))]>,
1310 Requires<[IsARM, HasV6]> {
1311 let Inst{7-4} = 0b1011;
1312 let Inst{11-8} = 0b1111;
1313 let Inst{19-16} = 0b1111;
1316 def PKHBT : AMiscA1I<0b01101000, (outs GPR:$dst),
1317 (ins GPR:$src1, GPR:$src2, i32imm:$shamt),
1318 IIC_iALU, "pkhbt", " $dst, $src1, $src2, LSL $shamt",
1319 [(set GPR:$dst, (or (and GPR:$src1, 0xFFFF),
1320 (and (shl GPR:$src2, (i32 imm:$shamt)),
1322 Requires<[IsARM, HasV6]> {
1323 let Inst{6-4} = 0b001;
1326 // Alternate cases for PKHBT where identities eliminate some nodes.
1327 def : ARMV6Pat<(or (and GPR:$src1, 0xFFFF), (and GPR:$src2, 0xFFFF0000)),
1328 (PKHBT GPR:$src1, GPR:$src2, 0)>;
1329 def : ARMV6Pat<(or (and GPR:$src1, 0xFFFF), (shl GPR:$src2, imm16_31:$shamt)),
1330 (PKHBT GPR:$src1, GPR:$src2, imm16_31:$shamt)>;
1333 def PKHTB : AMiscA1I<0b01101000, (outs GPR:$dst),
1334 (ins GPR:$src1, GPR:$src2, i32imm:$shamt),
1335 IIC_iALU, "pkhtb", " $dst, $src1, $src2, ASR $shamt",
1336 [(set GPR:$dst, (or (and GPR:$src1, 0xFFFF0000),
1337 (and (sra GPR:$src2, imm16_31:$shamt),
1338 0xFFFF)))]>, Requires<[IsARM, HasV6]> {
1339 let Inst{6-4} = 0b101;
1342 // Alternate cases for PKHTB where identities eliminate some nodes. Note that
1343 // a shift amount of 0 is *not legal* here, it is PKHBT instead.
1344 def : ARMV6Pat<(or (and GPR:$src1, 0xFFFF0000), (srl GPR:$src2, (i32 16))),
1345 (PKHTB GPR:$src1, GPR:$src2, 16)>;
1346 def : ARMV6Pat<(or (and GPR:$src1, 0xFFFF0000),
1347 (and (srl GPR:$src2, imm1_15:$shamt), 0xFFFF)),
1348 (PKHTB GPR:$src1, GPR:$src2, imm1_15:$shamt)>;
1350 //===----------------------------------------------------------------------===//
1351 // Comparison Instructions...
1354 defm CMP : AI1_cmp_irs<0b1010, "cmp",
1355 BinOpFrag<(ARMcmp node:$LHS, node:$RHS)>>;
1356 defm CMN : AI1_cmp_irs<0b1011, "cmn",
1357 BinOpFrag<(ARMcmp node:$LHS,(ineg node:$RHS))>>;
1359 // Note that TST/TEQ don't set all the same flags that CMP does!
1360 defm TST : AI1_cmp_irs<0b1000, "tst",
1361 BinOpFrag<(ARMcmpZ (and node:$LHS, node:$RHS), 0)>, 1>;
1362 defm TEQ : AI1_cmp_irs<0b1001, "teq",
1363 BinOpFrag<(ARMcmpZ (xor node:$LHS, node:$RHS), 0)>, 1>;
1365 defm CMPz : AI1_cmp_irs<0b1010, "cmp",
1366 BinOpFrag<(ARMcmpZ node:$LHS, node:$RHS)>>;
1367 defm CMNz : AI1_cmp_irs<0b1011, "cmn",
1368 BinOpFrag<(ARMcmpZ node:$LHS,(ineg node:$RHS))>>;
1370 def : ARMPat<(ARMcmp GPR:$src, so_imm_neg:$imm),
1371 (CMNri GPR:$src, so_imm_neg:$imm)>;
1373 def : ARMPat<(ARMcmpZ GPR:$src, so_imm_neg:$imm),
1374 (CMNri GPR:$src, so_imm_neg:$imm)>;
1377 // Conditional moves
1378 // FIXME: should be able to write a pattern for ARMcmov, but can't use
1379 // a two-value operand where a dag node expects two operands. :(
1380 def MOVCCr : AI1<0b1101, (outs GPR:$dst), (ins GPR:$false, GPR:$true), DPFrm,
1381 IIC_iALU, "mov", " $dst, $true",
1382 [/*(set GPR:$dst, (ARMcmov GPR:$false, GPR:$true, imm:$cc, CCR:$ccr))*/]>,
1383 RegConstraint<"$false = $dst">, UnaryDP;
1385 def MOVCCs : AI1<0b1101, (outs GPR:$dst),
1386 (ins GPR:$false, so_reg:$true), DPSoRegFrm, IIC_iALU,
1387 "mov", " $dst, $true",
1388 [/*(set GPR:$dst, (ARMcmov GPR:$false, so_reg:$true, imm:$cc, CCR:$ccr))*/]>,
1389 RegConstraint<"$false = $dst">, UnaryDP;
1391 def MOVCCi : AI1<0b1101, (outs GPR:$dst),
1392 (ins GPR:$false, so_imm:$true), DPFrm, IIC_iALU,
1393 "mov", " $dst, $true",
1394 [/*(set GPR:$dst, (ARMcmov GPR:$false, so_imm:$true, imm:$cc, CCR:$ccr))*/]>,
1395 RegConstraint<"$false = $dst">, UnaryDP;
1398 //===----------------------------------------------------------------------===//
1402 // __aeabi_read_tp preserves the registers r1-r3.
1404 Defs = [R0, R12, LR, CPSR] in {
1405 def TPsoft : ABXI<0b1011, (outs), (ins), IIC_Br,
1406 "bl __aeabi_read_tp",
1407 [(set R0, ARMthread_pointer)]>;
1410 //===----------------------------------------------------------------------===//
1411 // SJLJ Exception handling intrinsics
1412 // eh_sjlj_setjmp() is a three instruction sequence to store the return
1413 // address and save #0 in R0 for the non-longjmp case.
1414 // Since by its nature we may be coming from some other function to get
1415 // here, and we're using the stack frame for the containing function to
1416 // save/restore registers, we can't keep anything live in regs across
1417 // the eh_sjlj_setjmp(), else it will almost certainly have been tromped upon
1418 // when we get here from a longjmp(). We force everthing out of registers
1419 // except for our own input by listing the relevant registers in Defs. By
1420 // doing so, we also cause the prologue/epilogue code to actively preserve
1421 // all of the callee-saved resgisters, which is exactly what we want.
1423 [ R0, R1, R3, R4, R5, R6, R7, R8, R9, R10, R11, R12, LR,
1424 D0, D2, D3, D4, D5, D6, D7, D8, D9, D10, D11, D12, D13, D14, D15,
1425 D16, D17, D18, D19, D20, D21, D22, D23, D24, D25, D26, D27, D28, D29, D30,
1427 def Int_eh_sjlj_setjmp : XI<(outs), (ins GPR:$src),
1428 AddrModeNone, SizeSpecial, IndexModeNone,
1429 Pseudo, NoItinerary,
1430 "add r0, pc, #4\n\t"
1431 "str r0, [$src, #+4]\n\t"
1432 "mov r0, #0 @ eh_setjmp", "",
1433 [(set R0, (ARMeh_sjlj_setjmp GPR:$src))]>;
1436 //===----------------------------------------------------------------------===//
1437 // Non-Instruction Patterns
1440 // ConstantPool, GlobalAddress, and JumpTable
1441 def : ARMPat<(ARMWrapper tglobaladdr :$dst), (LEApcrel tglobaladdr :$dst)>;
1442 def : ARMPat<(ARMWrapper tconstpool :$dst), (LEApcrel tconstpool :$dst)>;
1443 def : ARMPat<(ARMWrapperJT tjumptable:$dst, imm:$id),
1444 (LEApcrelJT tjumptable:$dst, imm:$id)>;
1446 // Large immediate handling.
1448 // Two piece so_imms.
1449 let isReMaterializable = 1 in
1450 def MOVi2pieces : AI1x2<(outs GPR:$dst), (ins so_imm2part:$src),
1452 "mov", " $dst, $src",
1453 [(set GPR:$dst, so_imm2part:$src)]>;
1455 def : ARMPat<(or GPR:$LHS, so_imm2part:$RHS),
1456 (ORRri (ORRri GPR:$LHS, (so_imm2part_1 imm:$RHS)),
1457 (so_imm2part_2 imm:$RHS))>;
1458 def : ARMPat<(xor GPR:$LHS, so_imm2part:$RHS),
1459 (EORri (EORri GPR:$LHS, (so_imm2part_1 imm:$RHS)),
1460 (so_imm2part_2 imm:$RHS))>;
1462 // TODO: add,sub,and, 3-instr forms?
1466 def : ARMPat<(ARMcall texternalsym:$func), (BL texternalsym:$func)>,
1467 Requires<[IsARM, IsNotDarwin]>;
1468 def : ARMPat<(ARMcall texternalsym:$func), (BLr9 texternalsym:$func)>,
1469 Requires<[IsARM, IsDarwin]>;
1471 // zextload i1 -> zextload i8
1472 def : ARMPat<(zextloadi1 addrmode2:$addr), (LDRB addrmode2:$addr)>;
1474 // extload -> zextload
1475 def : ARMPat<(extloadi1 addrmode2:$addr), (LDRB addrmode2:$addr)>;
1476 def : ARMPat<(extloadi8 addrmode2:$addr), (LDRB addrmode2:$addr)>;
1477 def : ARMPat<(extloadi16 addrmode3:$addr), (LDRH addrmode3:$addr)>;
1479 def : ARMPat<(extloadi8 addrmodepc:$addr), (PICLDRB addrmodepc:$addr)>;
1480 def : ARMPat<(extloadi16 addrmodepc:$addr), (PICLDRH addrmodepc:$addr)>;
1483 def : ARMV5TEPat<(mul (sra (shl GPR:$a, (i32 16)), (i32 16)),
1484 (sra (shl GPR:$b, (i32 16)), (i32 16))),
1485 (SMULBB GPR:$a, GPR:$b)>;
1486 def : ARMV5TEPat<(mul sext_16_node:$a, sext_16_node:$b),
1487 (SMULBB GPR:$a, GPR:$b)>;
1488 def : ARMV5TEPat<(mul (sra (shl GPR:$a, (i32 16)), (i32 16)),
1489 (sra GPR:$b, (i32 16))),
1490 (SMULBT GPR:$a, GPR:$b)>;
1491 def : ARMV5TEPat<(mul sext_16_node:$a, (sra GPR:$b, (i32 16))),
1492 (SMULBT GPR:$a, GPR:$b)>;
1493 def : ARMV5TEPat<(mul (sra GPR:$a, (i32 16)),
1494 (sra (shl GPR:$b, (i32 16)), (i32 16))),
1495 (SMULTB GPR:$a, GPR:$b)>;
1496 def : ARMV5TEPat<(mul (sra GPR:$a, (i32 16)), sext_16_node:$b),
1497 (SMULTB GPR:$a, GPR:$b)>;
1498 def : ARMV5TEPat<(sra (mul GPR:$a, (sra (shl GPR:$b, (i32 16)), (i32 16))),
1500 (SMULWB GPR:$a, GPR:$b)>;
1501 def : ARMV5TEPat<(sra (mul GPR:$a, sext_16_node:$b), (i32 16)),
1502 (SMULWB GPR:$a, GPR:$b)>;
1504 def : ARMV5TEPat<(add GPR:$acc,
1505 (mul (sra (shl GPR:$a, (i32 16)), (i32 16)),
1506 (sra (shl GPR:$b, (i32 16)), (i32 16)))),
1507 (SMLABB GPR:$a, GPR:$b, GPR:$acc)>;
1508 def : ARMV5TEPat<(add GPR:$acc,
1509 (mul sext_16_node:$a, sext_16_node:$b)),
1510 (SMLABB GPR:$a, GPR:$b, GPR:$acc)>;
1511 def : ARMV5TEPat<(add GPR:$acc,
1512 (mul (sra (shl GPR:$a, (i32 16)), (i32 16)),
1513 (sra GPR:$b, (i32 16)))),
1514 (SMLABT GPR:$a, GPR:$b, GPR:$acc)>;
1515 def : ARMV5TEPat<(add GPR:$acc,
1516 (mul sext_16_node:$a, (sra GPR:$b, (i32 16)))),
1517 (SMLABT GPR:$a, GPR:$b, GPR:$acc)>;
1518 def : ARMV5TEPat<(add GPR:$acc,
1519 (mul (sra GPR:$a, (i32 16)),
1520 (sra (shl GPR:$b, (i32 16)), (i32 16)))),
1521 (SMLATB GPR:$a, GPR:$b, GPR:$acc)>;
1522 def : ARMV5TEPat<(add GPR:$acc,
1523 (mul (sra GPR:$a, (i32 16)), sext_16_node:$b)),
1524 (SMLATB GPR:$a, GPR:$b, GPR:$acc)>;
1525 def : ARMV5TEPat<(add GPR:$acc,
1526 (sra (mul GPR:$a, (sra (shl GPR:$b, (i32 16)), (i32 16))),
1528 (SMLAWB GPR:$a, GPR:$b, GPR:$acc)>;
1529 def : ARMV5TEPat<(add GPR:$acc,
1530 (sra (mul GPR:$a, sext_16_node:$b), (i32 16))),
1531 (SMLAWB GPR:$a, GPR:$b, GPR:$acc)>;
1533 //===----------------------------------------------------------------------===//
1537 include "ARMInstrThumb.td"
1539 //===----------------------------------------------------------------------===//
1543 include "ARMInstrThumb2.td"
1545 //===----------------------------------------------------------------------===//
1546 // Floating Point Support
1549 include "ARMInstrVFP.td"
1551 //===----------------------------------------------------------------------===//
1552 // Advanced SIMD (NEON) Support
1555 include "ARMInstrNEON.td"