1 //===- ARMInstrInfo.td - Target Description for ARM Target -*- tablegen -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file describes the ARM instructions in TableGen format.
12 //===----------------------------------------------------------------------===//
14 //===----------------------------------------------------------------------===//
15 // ARM specific DAG Nodes.
19 def SDT_ARMCallSeqStart : SDCallSeqStart<[ SDTCisVT<0, i32> ]>;
20 def SDT_ARMCallSeqEnd : SDCallSeqEnd<[ SDTCisVT<0, i32>, SDTCisVT<1, i32> ]>;
21 def SDT_ARMStructByVal : SDTypeProfile<0, 4,
22 [SDTCisVT<0, i32>, SDTCisVT<1, i32>,
23 SDTCisVT<2, i32>, SDTCisVT<3, i32>]>;
25 def SDT_ARMSaveCallPC : SDTypeProfile<0, 1, []>;
27 def SDT_ARMcall : SDTypeProfile<0, -1, [SDTCisPtrTy<0>]>;
29 def SDT_ARMCMov : SDTypeProfile<1, 3,
30 [SDTCisSameAs<0, 1>, SDTCisSameAs<0, 2>,
33 def SDT_ARMBrcond : SDTypeProfile<0, 2,
34 [SDTCisVT<0, OtherVT>, SDTCisVT<1, i32>]>;
36 def SDT_ARMBrJT : SDTypeProfile<0, 3,
37 [SDTCisPtrTy<0>, SDTCisVT<1, i32>,
40 def SDT_ARMBr2JT : SDTypeProfile<0, 4,
41 [SDTCisPtrTy<0>, SDTCisVT<1, i32>,
42 SDTCisVT<2, i32>, SDTCisVT<3, i32>]>;
44 def SDT_ARMBCC_i64 : SDTypeProfile<0, 6,
46 SDTCisVT<1, i32>, SDTCisVT<2, i32>,
47 SDTCisVT<3, i32>, SDTCisVT<4, i32>,
48 SDTCisVT<5, OtherVT>]>;
50 def SDT_ARMAnd : SDTypeProfile<1, 2,
51 [SDTCisVT<0, i32>, SDTCisVT<1, i32>,
54 def SDT_ARMCmp : SDTypeProfile<0, 2, [SDTCisSameAs<0, 1>]>;
56 def SDT_ARMPICAdd : SDTypeProfile<1, 2, [SDTCisSameAs<0, 1>,
57 SDTCisPtrTy<1>, SDTCisVT<2, i32>]>;
59 def SDT_ARMThreadPointer : SDTypeProfile<1, 0, [SDTCisPtrTy<0>]>;
60 def SDT_ARMEH_SJLJ_Setjmp : SDTypeProfile<1, 2, [SDTCisInt<0>, SDTCisPtrTy<1>,
62 def SDT_ARMEH_SJLJ_Longjmp: SDTypeProfile<0, 2, [SDTCisPtrTy<0>, SDTCisInt<1>]>;
64 def SDT_ARMMEMBARRIER : SDTypeProfile<0, 1, [SDTCisInt<0>]>;
66 def SDT_ARMPREFETCH : SDTypeProfile<0, 3, [SDTCisPtrTy<0>, SDTCisSameAs<1, 2>,
69 def SDT_ARMTCRET : SDTypeProfile<0, 1, [SDTCisPtrTy<0>]>;
71 def SDT_ARMBFI : SDTypeProfile<1, 3, [SDTCisVT<0, i32>, SDTCisVT<1, i32>,
72 SDTCisVT<2, i32>, SDTCisVT<3, i32>]>;
74 def SDTBinaryArithWithFlags : SDTypeProfile<2, 2,
77 SDTCisInt<0>, SDTCisVT<1, i32>]>;
79 // SDTBinaryArithWithFlagsInOut - RES1, CPSR = op LHS, RHS, CPSR
80 def SDTBinaryArithWithFlagsInOut : SDTypeProfile<2, 3,
87 def SDT_ARM64bitmlal : SDTypeProfile<2,4, [ SDTCisVT<0, i32>, SDTCisVT<1, i32>,
88 SDTCisVT<2, i32>, SDTCisVT<3, i32>,
89 SDTCisVT<4, i32>, SDTCisVT<5, i32> ] >;
90 def ARMUmlal : SDNode<"ARMISD::UMLAL", SDT_ARM64bitmlal>;
91 def ARMSmlal : SDNode<"ARMISD::SMLAL", SDT_ARM64bitmlal>;
94 def ARMWrapper : SDNode<"ARMISD::Wrapper", SDTIntUnaryOp>;
95 def ARMWrapperDYN : SDNode<"ARMISD::WrapperDYN", SDTIntUnaryOp>;
96 def ARMWrapperPIC : SDNode<"ARMISD::WrapperPIC", SDTIntUnaryOp>;
97 def ARMWrapperJT : SDNode<"ARMISD::WrapperJT", SDTIntBinOp>;
99 def ARMcallseq_start : SDNode<"ISD::CALLSEQ_START", SDT_ARMCallSeqStart,
100 [SDNPHasChain, SDNPSideEffect, SDNPOutGlue]>;
101 def ARMcallseq_end : SDNode<"ISD::CALLSEQ_END", SDT_ARMCallSeqEnd,
102 [SDNPHasChain, SDNPSideEffect,
103 SDNPOptInGlue, SDNPOutGlue]>;
104 def ARMcopystructbyval : SDNode<"ARMISD::COPY_STRUCT_BYVAL" ,
106 [SDNPHasChain, SDNPInGlue, SDNPOutGlue,
107 SDNPMayStore, SDNPMayLoad]>;
109 def ARMcall : SDNode<"ARMISD::CALL", SDT_ARMcall,
110 [SDNPHasChain, SDNPOptInGlue, SDNPOutGlue,
112 def ARMcall_pred : SDNode<"ARMISD::CALL_PRED", SDT_ARMcall,
113 [SDNPHasChain, SDNPOptInGlue, SDNPOutGlue,
115 def ARMcall_nolink : SDNode<"ARMISD::CALL_NOLINK", SDT_ARMcall,
116 [SDNPHasChain, SDNPOptInGlue, SDNPOutGlue,
119 def ARMretflag : SDNode<"ARMISD::RET_FLAG", SDTNone,
120 [SDNPHasChain, SDNPOptInGlue, SDNPVariadic]>;
122 def ARMcmov : SDNode<"ARMISD::CMOV", SDT_ARMCMov,
125 def ARMbrcond : SDNode<"ARMISD::BRCOND", SDT_ARMBrcond,
126 [SDNPHasChain, SDNPInGlue, SDNPOutGlue]>;
128 def ARMbrjt : SDNode<"ARMISD::BR_JT", SDT_ARMBrJT,
130 def ARMbr2jt : SDNode<"ARMISD::BR2_JT", SDT_ARMBr2JT,
133 def ARMBcci64 : SDNode<"ARMISD::BCC_i64", SDT_ARMBCC_i64,
136 def ARMcmp : SDNode<"ARMISD::CMP", SDT_ARMCmp,
139 def ARMcmn : SDNode<"ARMISD::CMN", SDT_ARMCmp,
142 def ARMcmpZ : SDNode<"ARMISD::CMPZ", SDT_ARMCmp,
143 [SDNPOutGlue, SDNPCommutative]>;
145 def ARMpic_add : SDNode<"ARMISD::PIC_ADD", SDT_ARMPICAdd>;
147 def ARMsrl_flag : SDNode<"ARMISD::SRL_FLAG", SDTIntUnaryOp, [SDNPOutGlue]>;
148 def ARMsra_flag : SDNode<"ARMISD::SRA_FLAG", SDTIntUnaryOp, [SDNPOutGlue]>;
149 def ARMrrx : SDNode<"ARMISD::RRX" , SDTIntUnaryOp, [SDNPInGlue ]>;
151 def ARMaddc : SDNode<"ARMISD::ADDC", SDTBinaryArithWithFlags,
153 def ARMsubc : SDNode<"ARMISD::SUBC", SDTBinaryArithWithFlags>;
154 def ARMadde : SDNode<"ARMISD::ADDE", SDTBinaryArithWithFlagsInOut>;
155 def ARMsube : SDNode<"ARMISD::SUBE", SDTBinaryArithWithFlagsInOut>;
157 def ARMthread_pointer: SDNode<"ARMISD::THREAD_POINTER", SDT_ARMThreadPointer>;
158 def ARMeh_sjlj_setjmp: SDNode<"ARMISD::EH_SJLJ_SETJMP",
159 SDT_ARMEH_SJLJ_Setjmp,
160 [SDNPHasChain, SDNPSideEffect]>;
161 def ARMeh_sjlj_longjmp: SDNode<"ARMISD::EH_SJLJ_LONGJMP",
162 SDT_ARMEH_SJLJ_Longjmp,
163 [SDNPHasChain, SDNPSideEffect]>;
165 def ARMMemBarrier : SDNode<"ARMISD::MEMBARRIER", SDT_ARMMEMBARRIER,
166 [SDNPHasChain, SDNPSideEffect]>;
167 def ARMMemBarrierMCR : SDNode<"ARMISD::MEMBARRIER_MCR", SDT_ARMMEMBARRIER,
168 [SDNPHasChain, SDNPSideEffect]>;
169 def ARMPreload : SDNode<"ARMISD::PRELOAD", SDT_ARMPREFETCH,
170 [SDNPHasChain, SDNPMayLoad, SDNPMayStore]>;
172 def ARMrbit : SDNode<"ARMISD::RBIT", SDTIntUnaryOp>;
174 def ARMtcret : SDNode<"ARMISD::TC_RETURN", SDT_ARMTCRET,
175 [SDNPHasChain, SDNPOptInGlue, SDNPVariadic]>;
178 def ARMbfi : SDNode<"ARMISD::BFI", SDT_ARMBFI>;
180 //===----------------------------------------------------------------------===//
181 // ARM Instruction Predicate Definitions.
183 def HasV4T : Predicate<"Subtarget->hasV4TOps()">,
184 AssemblerPredicate<"HasV4TOps", "armv4t">;
185 def NoV4T : Predicate<"!Subtarget->hasV4TOps()">;
186 def HasV5T : Predicate<"Subtarget->hasV5TOps()">;
187 def HasV5TE : Predicate<"Subtarget->hasV5TEOps()">,
188 AssemblerPredicate<"HasV5TEOps", "armv5te">;
189 def HasV6 : Predicate<"Subtarget->hasV6Ops()">,
190 AssemblerPredicate<"HasV6Ops", "armv6">;
191 def NoV6 : Predicate<"!Subtarget->hasV6Ops()">;
192 def HasV6T2 : Predicate<"Subtarget->hasV6T2Ops()">,
193 AssemblerPredicate<"HasV6T2Ops", "armv6t2">;
194 def NoV6T2 : Predicate<"!Subtarget->hasV6T2Ops()">;
195 def HasV7 : Predicate<"Subtarget->hasV7Ops()">,
196 AssemblerPredicate<"HasV7Ops", "armv7">;
197 def HasV8 : Predicate<"Subtarget->hasV8Ops()">,
198 AssemblerPredicate<"HasV8Ops", "armv8">;
199 def NoVFP : Predicate<"!Subtarget->hasVFP2()">;
200 def HasVFP2 : Predicate<"Subtarget->hasVFP2()">,
201 AssemblerPredicate<"FeatureVFP2", "VFP2">;
202 def HasVFP3 : Predicate<"Subtarget->hasVFP3()">,
203 AssemblerPredicate<"FeatureVFP3", "VFP3">;
204 def HasVFP4 : Predicate<"Subtarget->hasVFP4()">,
205 AssemblerPredicate<"FeatureVFP4", "VFP4">;
206 def HasV8FP : Predicate<"Subtarget->hasV8FP()">,
207 AssemblerPredicate<"FeatureV8FP", "V8FP">;
208 def HasNEON : Predicate<"Subtarget->hasNEON()">,
209 AssemblerPredicate<"FeatureNEON", "NEON">;
210 def HasFP16 : Predicate<"Subtarget->hasFP16()">,
211 AssemblerPredicate<"FeatureFP16","half-float">;
212 def HasDivide : Predicate<"Subtarget->hasDivide()">,
213 AssemblerPredicate<"FeatureHWDiv", "divide">;
214 def HasDivideInARM : Predicate<"Subtarget->hasDivideInARMMode()">,
215 AssemblerPredicate<"FeatureHWDivARM">;
216 def HasT2ExtractPack : Predicate<"Subtarget->hasT2ExtractPack()">,
217 AssemblerPredicate<"FeatureT2XtPk",
219 def HasThumb2DSP : Predicate<"Subtarget->hasThumb2DSP()">,
220 AssemblerPredicate<"FeatureDSPThumb2",
222 def HasDB : Predicate<"Subtarget->hasDataBarrier()">,
223 AssemblerPredicate<"FeatureDB",
225 def HasMP : Predicate<"Subtarget->hasMPExtension()">,
226 AssemblerPredicate<"FeatureMP",
228 def HasTrustZone : Predicate<"Subtarget->hasTrustZone()">,
229 AssemblerPredicate<"FeatureTrustZone",
231 def UseNEONForFP : Predicate<"Subtarget->useNEONForSinglePrecisionFP()">;
232 def DontUseNEONForFP : Predicate<"!Subtarget->useNEONForSinglePrecisionFP()">;
233 def IsThumb : Predicate<"Subtarget->isThumb()">,
234 AssemblerPredicate<"ModeThumb", "thumb">;
235 def IsThumb1Only : Predicate<"Subtarget->isThumb1Only()">;
236 def IsThumb2 : Predicate<"Subtarget->isThumb2()">,
237 AssemblerPredicate<"ModeThumb,FeatureThumb2",
239 def IsMClass : Predicate<"Subtarget->isMClass()">,
240 AssemblerPredicate<"FeatureMClass", "armv7m">;
241 def IsARClass : Predicate<"!Subtarget->isMClass()">,
242 AssemblerPredicate<"!FeatureMClass",
244 def IsARM : Predicate<"!Subtarget->isThumb()">,
245 AssemblerPredicate<"!ModeThumb", "arm-mode">;
246 def IsIOS : Predicate<"Subtarget->isTargetIOS()">;
247 def IsNotIOS : Predicate<"!Subtarget->isTargetIOS()">;
248 def IsNaCl : Predicate<"Subtarget->isTargetNaCl()">;
249 def UseNaClTrap : Predicate<"Subtarget->useNaClTrap()">,
250 AssemblerPredicate<"FeatureNaClTrap", "NaCl">;
251 def DontUseNaClTrap : Predicate<"!Subtarget->useNaClTrap()">;
253 // FIXME: Eventually this will be just "hasV6T2Ops".
254 def UseMovt : Predicate<"Subtarget->useMovt()">;
255 def DontUseMovt : Predicate<"!Subtarget->useMovt()">;
256 def UseFPVMLx : Predicate<"Subtarget->useFPVMLx()">;
257 def UseMulOps : Predicate<"Subtarget->useMulOps()">;
259 // Prefer fused MAC for fp mul + add over fp VMLA / VMLS if they are available.
260 // But only select them if more precision in FP computation is allowed.
261 // Do not use them for Darwin platforms.
262 def UseFusedMAC : Predicate<"(TM.Options.AllowFPOpFusion =="
263 " FPOpFusion::Fast) && "
264 "!Subtarget->isTargetDarwin()">;
265 def DontUseFusedMAC : Predicate<"!Subtarget->hasVFP4() || "
266 "Subtarget->isTargetDarwin()">;
268 // VGETLNi32 is microcoded on Swift - prefer VMOV.
269 def HasFastVGETLNi32 : Predicate<"!Subtarget->isSwift()">;
270 def HasSlowVGETLNi32 : Predicate<"Subtarget->isSwift()">;
272 // VDUP.32 is microcoded on Swift - prefer VMOV.
273 def HasFastVDUP32 : Predicate<"!Subtarget->isSwift()">;
274 def HasSlowVDUP32 : Predicate<"Subtarget->isSwift()">;
276 // Cortex-A9 prefers VMOVSR to VMOVDRR even when using NEON for scalar FP, as
277 // this allows more effective execution domain optimization. See
278 // setExecutionDomain().
279 def UseVMOVSR : Predicate<"Subtarget->isCortexA9() || !Subtarget->useNEONForSinglePrecisionFP()">;
280 def DontUseVMOVSR : Predicate<"!Subtarget->isCortexA9() && Subtarget->useNEONForSinglePrecisionFP()">;
282 def IsLE : Predicate<"getTargetLowering()->isLittleEndian()">;
283 def IsBE : Predicate<"getTargetLowering()->isBigEndian()">;
285 //===----------------------------------------------------------------------===//
286 // ARM Flag Definitions.
288 class RegConstraint<string C> {
289 string Constraints = C;
292 //===----------------------------------------------------------------------===//
293 // ARM specific transformation functions and pattern fragments.
296 // imm_neg_XFORM - Return the negation of an i32 immediate value.
297 def imm_neg_XFORM : SDNodeXForm<imm, [{
298 return CurDAG->getTargetConstant(-(int)N->getZExtValue(), MVT::i32);
301 // imm_not_XFORM - Return the complement of a i32 immediate value.
302 def imm_not_XFORM : SDNodeXForm<imm, [{
303 return CurDAG->getTargetConstant(~(int)N->getZExtValue(), MVT::i32);
306 /// imm16_31 predicate - True if the 32-bit immediate is in the range [16,31].
307 def imm16_31 : ImmLeaf<i32, [{
308 return (int32_t)Imm >= 16 && (int32_t)Imm < 32;
311 def so_imm_neg_asmoperand : AsmOperandClass { let Name = "ARMSOImmNeg"; }
312 def so_imm_neg : Operand<i32>, PatLeaf<(imm), [{
313 unsigned Value = -(unsigned)N->getZExtValue();
314 return Value && ARM_AM::getSOImmVal(Value) != -1;
316 let ParserMatchClass = so_imm_neg_asmoperand;
319 // Note: this pattern doesn't require an encoder method and such, as it's
320 // only used on aliases (Pat<> and InstAlias<>). The actual encoding
321 // is handled by the destination instructions, which use so_imm.
322 def so_imm_not_asmoperand : AsmOperandClass { let Name = "ARMSOImmNot"; }
323 def so_imm_not : Operand<i32>, PatLeaf<(imm), [{
324 return ARM_AM::getSOImmVal(~(uint32_t)N->getZExtValue()) != -1;
326 let ParserMatchClass = so_imm_not_asmoperand;
329 // sext_16_node predicate - True if the SDNode is sign-extended 16 or more bits.
330 def sext_16_node : PatLeaf<(i32 GPR:$a), [{
331 return CurDAG->ComputeNumSignBits(SDValue(N,0)) >= 17;
334 /// Split a 32-bit immediate into two 16 bit parts.
335 def hi16 : SDNodeXForm<imm, [{
336 return CurDAG->getTargetConstant((uint32_t)N->getZExtValue() >> 16, MVT::i32);
339 def lo16AllZero : PatLeaf<(i32 imm), [{
340 // Returns true if all low 16-bits are 0.
341 return (((uint32_t)N->getZExtValue()) & 0xFFFFUL) == 0;
344 class BinOpWithFlagFrag<dag res> :
345 PatFrag<(ops node:$LHS, node:$RHS, node:$FLAG), res>;
346 class BinOpFrag<dag res> : PatFrag<(ops node:$LHS, node:$RHS), res>;
347 class UnOpFrag <dag res> : PatFrag<(ops node:$Src), res>;
349 // An 'and' node with a single use.
350 def and_su : PatFrag<(ops node:$lhs, node:$rhs), (and node:$lhs, node:$rhs), [{
351 return N->hasOneUse();
354 // An 'xor' node with a single use.
355 def xor_su : PatFrag<(ops node:$lhs, node:$rhs), (xor node:$lhs, node:$rhs), [{
356 return N->hasOneUse();
359 // An 'fmul' node with a single use.
360 def fmul_su : PatFrag<(ops node:$lhs, node:$rhs), (fmul node:$lhs, node:$rhs),[{
361 return N->hasOneUse();
364 // An 'fadd' node which checks for single non-hazardous use.
365 def fadd_mlx : PatFrag<(ops node:$lhs, node:$rhs),(fadd node:$lhs, node:$rhs),[{
366 return hasNoVMLxHazardUse(N);
369 // An 'fsub' node which checks for single non-hazardous use.
370 def fsub_mlx : PatFrag<(ops node:$lhs, node:$rhs),(fsub node:$lhs, node:$rhs),[{
371 return hasNoVMLxHazardUse(N);
374 //===----------------------------------------------------------------------===//
375 // Operand Definitions.
378 // Immediate operands with a shared generic asm render method.
379 class ImmAsmOperand : AsmOperandClass { let RenderMethod = "addImmOperands"; }
382 // FIXME: rename brtarget to t2_brtarget
383 def brtarget : Operand<OtherVT> {
384 let EncoderMethod = "getBranchTargetOpValue";
385 let OperandType = "OPERAND_PCREL";
386 let DecoderMethod = "DecodeT2BROperand";
389 // FIXME: get rid of this one?
390 def uncondbrtarget : Operand<OtherVT> {
391 let EncoderMethod = "getUnconditionalBranchTargetOpValue";
392 let OperandType = "OPERAND_PCREL";
395 // Branch target for ARM. Handles conditional/unconditional
396 def br_target : Operand<OtherVT> {
397 let EncoderMethod = "getARMBranchTargetOpValue";
398 let OperandType = "OPERAND_PCREL";
402 // FIXME: rename bltarget to t2_bl_target?
403 def bltarget : Operand<i32> {
404 // Encoded the same as branch targets.
405 let EncoderMethod = "getBranchTargetOpValue";
406 let OperandType = "OPERAND_PCREL";
409 // Call target for ARM. Handles conditional/unconditional
410 // FIXME: rename bl_target to t2_bltarget?
411 def bl_target : Operand<i32> {
412 let EncoderMethod = "getARMBLTargetOpValue";
413 let OperandType = "OPERAND_PCREL";
416 def blx_target : Operand<i32> {
417 let EncoderMethod = "getARMBLXTargetOpValue";
418 let OperandType = "OPERAND_PCREL";
421 // A list of registers separated by comma. Used by load/store multiple.
422 def RegListAsmOperand : AsmOperandClass { let Name = "RegList"; }
423 def reglist : Operand<i32> {
424 let EncoderMethod = "getRegisterListOpValue";
425 let ParserMatchClass = RegListAsmOperand;
426 let PrintMethod = "printRegisterList";
427 let DecoderMethod = "DecodeRegListOperand";
430 def GPRPairOp : RegisterOperand<GPRPair, "printGPRPairOperand">;
432 def DPRRegListAsmOperand : AsmOperandClass { let Name = "DPRRegList"; }
433 def dpr_reglist : Operand<i32> {
434 let EncoderMethod = "getRegisterListOpValue";
435 let ParserMatchClass = DPRRegListAsmOperand;
436 let PrintMethod = "printRegisterList";
437 let DecoderMethod = "DecodeDPRRegListOperand";
440 def SPRRegListAsmOperand : AsmOperandClass { let Name = "SPRRegList"; }
441 def spr_reglist : Operand<i32> {
442 let EncoderMethod = "getRegisterListOpValue";
443 let ParserMatchClass = SPRRegListAsmOperand;
444 let PrintMethod = "printRegisterList";
445 let DecoderMethod = "DecodeSPRRegListOperand";
448 // An operand for the CONSTPOOL_ENTRY pseudo-instruction.
449 def cpinst_operand : Operand<i32> {
450 let PrintMethod = "printCPInstOperand";
454 def pclabel : Operand<i32> {
455 let PrintMethod = "printPCLabel";
458 // ADR instruction labels.
459 def AdrLabelAsmOperand : AsmOperandClass { let Name = "AdrLabel"; }
460 def adrlabel : Operand<i32> {
461 let EncoderMethod = "getAdrLabelOpValue";
462 let ParserMatchClass = AdrLabelAsmOperand;
463 let PrintMethod = "printAdrLabelOperand<0>";
466 def neon_vcvt_imm32 : Operand<i32> {
467 let EncoderMethod = "getNEONVcvtImm32OpValue";
468 let DecoderMethod = "DecodeVCVTImmOperand";
471 // rot_imm: An integer that encodes a rotate amount. Must be 8, 16, or 24.
472 def rot_imm_XFORM: SDNodeXForm<imm, [{
473 switch (N->getZExtValue()){
475 case 0: return CurDAG->getTargetConstant(0, MVT::i32);
476 case 8: return CurDAG->getTargetConstant(1, MVT::i32);
477 case 16: return CurDAG->getTargetConstant(2, MVT::i32);
478 case 24: return CurDAG->getTargetConstant(3, MVT::i32);
481 def RotImmAsmOperand : AsmOperandClass {
483 let ParserMethod = "parseRotImm";
485 def rot_imm : Operand<i32>, PatLeaf<(i32 imm), [{
486 int32_t v = N->getZExtValue();
487 return v == 8 || v == 16 || v == 24; }],
489 let PrintMethod = "printRotImmOperand";
490 let ParserMatchClass = RotImmAsmOperand;
493 // shift_imm: An integer that encodes a shift amount and the type of shift
494 // (asr or lsl). The 6-bit immediate encodes as:
497 // {4-0} imm5 shift amount.
498 // asr #32 encoded as imm5 == 0.
499 def ShifterImmAsmOperand : AsmOperandClass {
500 let Name = "ShifterImm";
501 let ParserMethod = "parseShifterImm";
503 def shift_imm : Operand<i32> {
504 let PrintMethod = "printShiftImmOperand";
505 let ParserMatchClass = ShifterImmAsmOperand;
508 // shifter_operand operands: so_reg_reg, so_reg_imm, and so_imm.
509 def ShiftedRegAsmOperand : AsmOperandClass { let Name = "RegShiftedReg"; }
510 def so_reg_reg : Operand<i32>, // reg reg imm
511 ComplexPattern<i32, 3, "SelectRegShifterOperand",
512 [shl, srl, sra, rotr]> {
513 let EncoderMethod = "getSORegRegOpValue";
514 let PrintMethod = "printSORegRegOperand";
515 let DecoderMethod = "DecodeSORegRegOperand";
516 let ParserMatchClass = ShiftedRegAsmOperand;
517 let MIOperandInfo = (ops GPRnopc, GPRnopc, i32imm);
520 def ShiftedImmAsmOperand : AsmOperandClass { let Name = "RegShiftedImm"; }
521 def so_reg_imm : Operand<i32>, // reg imm
522 ComplexPattern<i32, 2, "SelectImmShifterOperand",
523 [shl, srl, sra, rotr]> {
524 let EncoderMethod = "getSORegImmOpValue";
525 let PrintMethod = "printSORegImmOperand";
526 let DecoderMethod = "DecodeSORegImmOperand";
527 let ParserMatchClass = ShiftedImmAsmOperand;
528 let MIOperandInfo = (ops GPR, i32imm);
531 // FIXME: Does this need to be distinct from so_reg?
532 def shift_so_reg_reg : Operand<i32>, // reg reg imm
533 ComplexPattern<i32, 3, "SelectShiftRegShifterOperand",
534 [shl,srl,sra,rotr]> {
535 let EncoderMethod = "getSORegRegOpValue";
536 let PrintMethod = "printSORegRegOperand";
537 let DecoderMethod = "DecodeSORegRegOperand";
538 let ParserMatchClass = ShiftedRegAsmOperand;
539 let MIOperandInfo = (ops GPR, GPR, i32imm);
542 // FIXME: Does this need to be distinct from so_reg?
543 def shift_so_reg_imm : Operand<i32>, // reg reg imm
544 ComplexPattern<i32, 2, "SelectShiftImmShifterOperand",
545 [shl,srl,sra,rotr]> {
546 let EncoderMethod = "getSORegImmOpValue";
547 let PrintMethod = "printSORegImmOperand";
548 let DecoderMethod = "DecodeSORegImmOperand";
549 let ParserMatchClass = ShiftedImmAsmOperand;
550 let MIOperandInfo = (ops GPR, i32imm);
554 // so_imm - Match a 32-bit shifter_operand immediate operand, which is an
555 // 8-bit immediate rotated by an arbitrary number of bits.
556 def SOImmAsmOperand: ImmAsmOperand { let Name = "ARMSOImm"; }
557 def so_imm : Operand<i32>, ImmLeaf<i32, [{
558 return ARM_AM::getSOImmVal(Imm) != -1;
560 let EncoderMethod = "getSOImmOpValue";
561 let ParserMatchClass = SOImmAsmOperand;
562 let DecoderMethod = "DecodeSOImmOperand";
565 // Break so_imm's up into two pieces. This handles immediates with up to 16
566 // bits set in them. This uses so_imm2part to match and so_imm2part_[12] to
567 // get the first/second pieces.
568 def so_imm2part : PatLeaf<(imm), [{
569 return ARM_AM::isSOImmTwoPartVal((unsigned)N->getZExtValue());
572 /// arm_i32imm - True for +V6T2, or true only if so_imm2part is true.
574 def arm_i32imm : PatLeaf<(imm), [{
575 if (Subtarget->hasV6T2Ops())
577 return ARM_AM::isSOImmTwoPartVal((unsigned)N->getZExtValue());
580 /// imm0_1 predicate - Immediate in the range [0,1].
581 def Imm0_1AsmOperand: ImmAsmOperand { let Name = "Imm0_1"; }
582 def imm0_1 : Operand<i32> { let ParserMatchClass = Imm0_1AsmOperand; }
584 /// imm0_3 predicate - Immediate in the range [0,3].
585 def Imm0_3AsmOperand: ImmAsmOperand { let Name = "Imm0_3"; }
586 def imm0_3 : Operand<i32> { let ParserMatchClass = Imm0_3AsmOperand; }
588 /// imm0_4 predicate - Immediate in the range [0,4].
589 def Imm0_4AsmOperand : ImmAsmOperand
592 let DiagnosticType = "ImmRange0_4";
594 def imm0_4 : Operand<i32>, ImmLeaf<i32, [{ return Imm >= 0 && Imm < 5; }]> {
595 let ParserMatchClass = Imm0_4AsmOperand;
596 let DecoderMethod = "DecodeImm0_4";
599 /// imm0_7 predicate - Immediate in the range [0,7].
600 def Imm0_7AsmOperand: ImmAsmOperand { let Name = "Imm0_7"; }
601 def imm0_7 : Operand<i32>, ImmLeaf<i32, [{
602 return Imm >= 0 && Imm < 8;
604 let ParserMatchClass = Imm0_7AsmOperand;
607 /// imm8 predicate - Immediate is exactly 8.
608 def Imm8AsmOperand: ImmAsmOperand { let Name = "Imm8"; }
609 def imm8 : Operand<i32>, ImmLeaf<i32, [{ return Imm == 8; }]> {
610 let ParserMatchClass = Imm8AsmOperand;
613 /// imm16 predicate - Immediate is exactly 16.
614 def Imm16AsmOperand: ImmAsmOperand { let Name = "Imm16"; }
615 def imm16 : Operand<i32>, ImmLeaf<i32, [{ return Imm == 16; }]> {
616 let ParserMatchClass = Imm16AsmOperand;
619 /// imm32 predicate - Immediate is exactly 32.
620 def Imm32AsmOperand: ImmAsmOperand { let Name = "Imm32"; }
621 def imm32 : Operand<i32>, ImmLeaf<i32, [{ return Imm == 32; }]> {
622 let ParserMatchClass = Imm32AsmOperand;
625 /// imm1_7 predicate - Immediate in the range [1,7].
626 def Imm1_7AsmOperand: ImmAsmOperand { let Name = "Imm1_7"; }
627 def imm1_7 : Operand<i32>, ImmLeaf<i32, [{ return Imm > 0 && Imm < 8; }]> {
628 let ParserMatchClass = Imm1_7AsmOperand;
631 /// imm1_15 predicate - Immediate in the range [1,15].
632 def Imm1_15AsmOperand: ImmAsmOperand { let Name = "Imm1_15"; }
633 def imm1_15 : Operand<i32>, ImmLeaf<i32, [{ return Imm > 0 && Imm < 16; }]> {
634 let ParserMatchClass = Imm1_15AsmOperand;
637 /// imm1_31 predicate - Immediate in the range [1,31].
638 def Imm1_31AsmOperand: ImmAsmOperand { let Name = "Imm1_31"; }
639 def imm1_31 : Operand<i32>, ImmLeaf<i32, [{ return Imm > 0 && Imm < 32; }]> {
640 let ParserMatchClass = Imm1_31AsmOperand;
643 /// imm0_15 predicate - Immediate in the range [0,15].
644 def Imm0_15AsmOperand: ImmAsmOperand {
645 let Name = "Imm0_15";
646 let DiagnosticType = "ImmRange0_15";
648 def imm0_15 : Operand<i32>, ImmLeaf<i32, [{
649 return Imm >= 0 && Imm < 16;
651 let ParserMatchClass = Imm0_15AsmOperand;
654 /// imm0_31 predicate - True if the 32-bit immediate is in the range [0,31].
655 def Imm0_31AsmOperand: ImmAsmOperand { let Name = "Imm0_31"; }
656 def imm0_31 : Operand<i32>, ImmLeaf<i32, [{
657 return Imm >= 0 && Imm < 32;
659 let ParserMatchClass = Imm0_31AsmOperand;
662 /// imm0_32 predicate - True if the 32-bit immediate is in the range [0,32].
663 def Imm0_32AsmOperand: ImmAsmOperand { let Name = "Imm0_32"; }
664 def imm0_32 : Operand<i32>, ImmLeaf<i32, [{
665 return Imm >= 0 && Imm < 32;
667 let ParserMatchClass = Imm0_32AsmOperand;
670 /// imm0_63 predicate - True if the 32-bit immediate is in the range [0,63].
671 def Imm0_63AsmOperand: ImmAsmOperand { let Name = "Imm0_63"; }
672 def imm0_63 : Operand<i32>, ImmLeaf<i32, [{
673 return Imm >= 0 && Imm < 64;
675 let ParserMatchClass = Imm0_63AsmOperand;
678 /// imm0_255 predicate - Immediate in the range [0,255].
679 def Imm0_255AsmOperand : ImmAsmOperand { let Name = "Imm0_255"; }
680 def imm0_255 : Operand<i32>, ImmLeaf<i32, [{ return Imm >= 0 && Imm < 256; }]> {
681 let ParserMatchClass = Imm0_255AsmOperand;
684 /// imm0_65535 - An immediate is in the range [0.65535].
685 def Imm0_65535AsmOperand: ImmAsmOperand { let Name = "Imm0_65535"; }
686 def imm0_65535 : Operand<i32>, ImmLeaf<i32, [{
687 return Imm >= 0 && Imm < 65536;
689 let ParserMatchClass = Imm0_65535AsmOperand;
692 // imm0_65535_neg - An immediate whose negative value is in the range [0.65535].
693 def imm0_65535_neg : Operand<i32>, ImmLeaf<i32, [{
694 return -Imm >= 0 && -Imm < 65536;
697 // imm0_65535_expr - For movt/movw - 16-bit immediate that can also reference
698 // a relocatable expression.
700 // FIXME: This really needs a Thumb version separate from the ARM version.
701 // While the range is the same, and can thus use the same match class,
702 // the encoding is different so it should have a different encoder method.
703 def Imm0_65535ExprAsmOperand: ImmAsmOperand { let Name = "Imm0_65535Expr"; }
704 def imm0_65535_expr : Operand<i32> {
705 let EncoderMethod = "getHiLo16ImmOpValue";
706 let ParserMatchClass = Imm0_65535ExprAsmOperand;
709 /// imm24b - True if the 32-bit immediate is encodable in 24 bits.
710 def Imm24bitAsmOperand: ImmAsmOperand { let Name = "Imm24bit"; }
711 def imm24b : Operand<i32>, ImmLeaf<i32, [{
712 return Imm >= 0 && Imm <= 0xffffff;
714 let ParserMatchClass = Imm24bitAsmOperand;
718 /// bf_inv_mask_imm predicate - An AND mask to clear an arbitrary width bitfield
720 def BitfieldAsmOperand : AsmOperandClass {
721 let Name = "Bitfield";
722 let ParserMethod = "parseBitfield";
725 def bf_inv_mask_imm : Operand<i32>,
727 return ARM::isBitFieldInvertedMask(N->getZExtValue());
729 let EncoderMethod = "getBitfieldInvertedMaskOpValue";
730 let PrintMethod = "printBitfieldInvMaskImmOperand";
731 let DecoderMethod = "DecodeBitfieldMaskOperand";
732 let ParserMatchClass = BitfieldAsmOperand;
735 def imm1_32_XFORM: SDNodeXForm<imm, [{
736 return CurDAG->getTargetConstant((int)N->getZExtValue() - 1, MVT::i32);
738 def Imm1_32AsmOperand: AsmOperandClass { let Name = "Imm1_32"; }
739 def imm1_32 : Operand<i32>, PatLeaf<(imm), [{
740 uint64_t Imm = N->getZExtValue();
741 return Imm > 0 && Imm <= 32;
744 let PrintMethod = "printImmPlusOneOperand";
745 let ParserMatchClass = Imm1_32AsmOperand;
748 def imm1_16_XFORM: SDNodeXForm<imm, [{
749 return CurDAG->getTargetConstant((int)N->getZExtValue() - 1, MVT::i32);
751 def Imm1_16AsmOperand: AsmOperandClass { let Name = "Imm1_16"; }
752 def imm1_16 : Operand<i32>, PatLeaf<(imm), [{ return Imm > 0 && Imm <= 16; }],
754 let PrintMethod = "printImmPlusOneOperand";
755 let ParserMatchClass = Imm1_16AsmOperand;
758 // Define ARM specific addressing modes.
759 // addrmode_imm12 := reg +/- imm12
761 def MemImm12OffsetAsmOperand : AsmOperandClass { let Name = "MemImm12Offset"; }
762 class AddrMode_Imm12 : Operand<i32>,
763 ComplexPattern<i32, 2, "SelectAddrModeImm12", []> {
764 // 12-bit immediate operand. Note that instructions using this encode
765 // #0 and #-0 differently. We flag #-0 as the magic value INT32_MIN. All other
766 // immediate values are as normal.
768 let EncoderMethod = "getAddrModeImm12OpValue";
769 let DecoderMethod = "DecodeAddrModeImm12Operand";
770 let ParserMatchClass = MemImm12OffsetAsmOperand;
771 let MIOperandInfo = (ops GPR:$base, i32imm:$offsimm);
774 def addrmode_imm12 : AddrMode_Imm12 {
775 let PrintMethod = "printAddrModeImm12Operand<false>";
778 def addrmode_imm12_pre : AddrMode_Imm12 {
779 let PrintMethod = "printAddrModeImm12Operand<true>";
782 // ldst_so_reg := reg +/- reg shop imm
784 def MemRegOffsetAsmOperand : AsmOperandClass { let Name = "MemRegOffset"; }
785 def ldst_so_reg : Operand<i32>,
786 ComplexPattern<i32, 3, "SelectLdStSOReg", []> {
787 let EncoderMethod = "getLdStSORegOpValue";
788 // FIXME: Simplify the printer
789 let PrintMethod = "printAddrMode2Operand";
790 let DecoderMethod = "DecodeSORegMemOperand";
791 let ParserMatchClass = MemRegOffsetAsmOperand;
792 let MIOperandInfo = (ops GPR:$base, GPRnopc:$offsreg, i32imm:$shift);
795 // postidx_imm8 := +/- [0,255]
798 // {8} 1 is imm8 is non-negative. 0 otherwise.
799 // {7-0} [0,255] imm8 value.
800 def PostIdxImm8AsmOperand : AsmOperandClass { let Name = "PostIdxImm8"; }
801 def postidx_imm8 : Operand<i32> {
802 let PrintMethod = "printPostIdxImm8Operand";
803 let ParserMatchClass = PostIdxImm8AsmOperand;
804 let MIOperandInfo = (ops i32imm);
807 // postidx_imm8s4 := +/- [0,1020]
810 // {8} 1 is imm8 is non-negative. 0 otherwise.
811 // {7-0} [0,255] imm8 value, scaled by 4.
812 def PostIdxImm8s4AsmOperand : AsmOperandClass { let Name = "PostIdxImm8s4"; }
813 def postidx_imm8s4 : Operand<i32> {
814 let PrintMethod = "printPostIdxImm8s4Operand";
815 let ParserMatchClass = PostIdxImm8s4AsmOperand;
816 let MIOperandInfo = (ops i32imm);
820 // postidx_reg := +/- reg
822 def PostIdxRegAsmOperand : AsmOperandClass {
823 let Name = "PostIdxReg";
824 let ParserMethod = "parsePostIdxReg";
826 def postidx_reg : Operand<i32> {
827 let EncoderMethod = "getPostIdxRegOpValue";
828 let DecoderMethod = "DecodePostIdxReg";
829 let PrintMethod = "printPostIdxRegOperand";
830 let ParserMatchClass = PostIdxRegAsmOperand;
831 let MIOperandInfo = (ops GPRnopc, i32imm);
835 // addrmode2 := reg +/- imm12
836 // := reg +/- reg shop imm
838 // FIXME: addrmode2 should be refactored the rest of the way to always
839 // use explicit imm vs. reg versions above (addrmode_imm12 and ldst_so_reg).
840 def AddrMode2AsmOperand : AsmOperandClass { let Name = "AddrMode2"; }
841 def addrmode2 : Operand<i32>,
842 ComplexPattern<i32, 3, "SelectAddrMode2", []> {
843 let EncoderMethod = "getAddrMode2OpValue";
844 let PrintMethod = "printAddrMode2Operand";
845 let ParserMatchClass = AddrMode2AsmOperand;
846 let MIOperandInfo = (ops GPR:$base, GPR:$offsreg, i32imm:$offsimm);
849 def PostIdxRegShiftedAsmOperand : AsmOperandClass {
850 let Name = "PostIdxRegShifted";
851 let ParserMethod = "parsePostIdxReg";
853 def am2offset_reg : Operand<i32>,
854 ComplexPattern<i32, 2, "SelectAddrMode2OffsetReg",
855 [], [SDNPWantRoot]> {
856 let EncoderMethod = "getAddrMode2OffsetOpValue";
857 let PrintMethod = "printAddrMode2OffsetOperand";
858 // When using this for assembly, it's always as a post-index offset.
859 let ParserMatchClass = PostIdxRegShiftedAsmOperand;
860 let MIOperandInfo = (ops GPRnopc, i32imm);
863 // FIXME: am2offset_imm should only need the immediate, not the GPR. Having
864 // the GPR is purely vestigal at this point.
865 def AM2OffsetImmAsmOperand : AsmOperandClass { let Name = "AM2OffsetImm"; }
866 def am2offset_imm : Operand<i32>,
867 ComplexPattern<i32, 2, "SelectAddrMode2OffsetImm",
868 [], [SDNPWantRoot]> {
869 let EncoderMethod = "getAddrMode2OffsetOpValue";
870 let PrintMethod = "printAddrMode2OffsetOperand";
871 let ParserMatchClass = AM2OffsetImmAsmOperand;
872 let MIOperandInfo = (ops GPRnopc, i32imm);
876 // addrmode3 := reg +/- reg
877 // addrmode3 := reg +/- imm8
879 // FIXME: split into imm vs. reg versions.
880 def AddrMode3AsmOperand : AsmOperandClass { let Name = "AddrMode3"; }
881 class AddrMode3 : Operand<i32>,
882 ComplexPattern<i32, 3, "SelectAddrMode3", []> {
883 let EncoderMethod = "getAddrMode3OpValue";
884 let ParserMatchClass = AddrMode3AsmOperand;
885 let MIOperandInfo = (ops GPR:$base, GPR:$offsreg, i32imm:$offsimm);
888 def addrmode3 : AddrMode3
890 let PrintMethod = "printAddrMode3Operand<false>";
893 def addrmode3_pre : AddrMode3
895 let PrintMethod = "printAddrMode3Operand<true>";
898 // FIXME: split into imm vs. reg versions.
899 // FIXME: parser method to handle +/- register.
900 def AM3OffsetAsmOperand : AsmOperandClass {
901 let Name = "AM3Offset";
902 let ParserMethod = "parseAM3Offset";
904 def am3offset : Operand<i32>,
905 ComplexPattern<i32, 2, "SelectAddrMode3Offset",
906 [], [SDNPWantRoot]> {
907 let EncoderMethod = "getAddrMode3OffsetOpValue";
908 let PrintMethod = "printAddrMode3OffsetOperand";
909 let ParserMatchClass = AM3OffsetAsmOperand;
910 let MIOperandInfo = (ops GPR, i32imm);
913 // ldstm_mode := {ia, ib, da, db}
915 def ldstm_mode : OptionalDefOperand<OtherVT, (ops i32), (ops (i32 1))> {
916 let EncoderMethod = "getLdStmModeOpValue";
917 let PrintMethod = "printLdStmModeOperand";
920 // addrmode5 := reg +/- imm8*4
922 def AddrMode5AsmOperand : AsmOperandClass { let Name = "AddrMode5"; }
923 class AddrMode5 : Operand<i32>,
924 ComplexPattern<i32, 2, "SelectAddrMode5", []> {
925 let EncoderMethod = "getAddrMode5OpValue";
926 let DecoderMethod = "DecodeAddrMode5Operand";
927 let ParserMatchClass = AddrMode5AsmOperand;
928 let MIOperandInfo = (ops GPR:$base, i32imm);
931 def addrmode5 : AddrMode5 {
932 let PrintMethod = "printAddrMode5Operand<false>";
935 def addrmode5_pre : AddrMode5 {
936 let PrintMethod = "printAddrMode5Operand<true>";
939 // addrmode6 := reg with optional alignment
941 def AddrMode6AsmOperand : AsmOperandClass { let Name = "AlignedMemory"; }
942 def addrmode6 : Operand<i32>,
943 ComplexPattern<i32, 2, "SelectAddrMode6", [], [SDNPWantParent]>{
944 let PrintMethod = "printAddrMode6Operand";
945 let MIOperandInfo = (ops GPR:$addr, i32imm:$align);
946 let EncoderMethod = "getAddrMode6AddressOpValue";
947 let DecoderMethod = "DecodeAddrMode6Operand";
948 let ParserMatchClass = AddrMode6AsmOperand;
951 def am6offset : Operand<i32>,
952 ComplexPattern<i32, 1, "SelectAddrMode6Offset",
953 [], [SDNPWantRoot]> {
954 let PrintMethod = "printAddrMode6OffsetOperand";
955 let MIOperandInfo = (ops GPR);
956 let EncoderMethod = "getAddrMode6OffsetOpValue";
957 let DecoderMethod = "DecodeGPRRegisterClass";
960 // Special version of addrmode6 to handle alignment encoding for VST1/VLD1
961 // (single element from one lane) for size 32.
962 def addrmode6oneL32 : Operand<i32>,
963 ComplexPattern<i32, 2, "SelectAddrMode6", [], [SDNPWantParent]>{
964 let PrintMethod = "printAddrMode6Operand";
965 let MIOperandInfo = (ops GPR:$addr, i32imm);
966 let EncoderMethod = "getAddrMode6OneLane32AddressOpValue";
969 // Special version of addrmode6 to handle alignment encoding for VLD-dup
970 // instructions, specifically VLD4-dup.
971 def addrmode6dup : Operand<i32>,
972 ComplexPattern<i32, 2, "SelectAddrMode6", [], [SDNPWantParent]>{
973 let PrintMethod = "printAddrMode6Operand";
974 let MIOperandInfo = (ops GPR:$addr, i32imm);
975 let EncoderMethod = "getAddrMode6DupAddressOpValue";
976 // FIXME: This is close, but not quite right. The alignment specifier is
978 let ParserMatchClass = AddrMode6AsmOperand;
981 // addrmodepc := pc + reg
983 def addrmodepc : Operand<i32>,
984 ComplexPattern<i32, 2, "SelectAddrModePC", []> {
985 let PrintMethod = "printAddrModePCOperand";
986 let MIOperandInfo = (ops GPR, i32imm);
989 // addr_offset_none := reg
991 def MemNoOffsetAsmOperand : AsmOperandClass { let Name = "MemNoOffset"; }
992 def addr_offset_none : Operand<i32>,
993 ComplexPattern<i32, 1, "SelectAddrOffsetNone", []> {
994 let PrintMethod = "printAddrMode7Operand";
995 let DecoderMethod = "DecodeAddrMode7Operand";
996 let ParserMatchClass = MemNoOffsetAsmOperand;
997 let MIOperandInfo = (ops GPR:$base);
1000 def nohash_imm : Operand<i32> {
1001 let PrintMethod = "printNoHashImmediate";
1004 def CoprocNumAsmOperand : AsmOperandClass {
1005 let Name = "CoprocNum";
1006 let ParserMethod = "parseCoprocNumOperand";
1008 def p_imm : Operand<i32> {
1009 let PrintMethod = "printPImmediate";
1010 let ParserMatchClass = CoprocNumAsmOperand;
1011 let DecoderMethod = "DecodeCoprocessor";
1014 def CoprocRegAsmOperand : AsmOperandClass {
1015 let Name = "CoprocReg";
1016 let ParserMethod = "parseCoprocRegOperand";
1018 def c_imm : Operand<i32> {
1019 let PrintMethod = "printCImmediate";
1020 let ParserMatchClass = CoprocRegAsmOperand;
1022 def CoprocOptionAsmOperand : AsmOperandClass {
1023 let Name = "CoprocOption";
1024 let ParserMethod = "parseCoprocOptionOperand";
1026 def coproc_option_imm : Operand<i32> {
1027 let PrintMethod = "printCoprocOptionImm";
1028 let ParserMatchClass = CoprocOptionAsmOperand;
1031 //===----------------------------------------------------------------------===//
1033 include "ARMInstrFormats.td"
1035 //===----------------------------------------------------------------------===//
1036 // Multiclass helpers...
1039 /// AsI1_bin_irs - Defines a set of (op r, {so_imm|r|so_reg}) patterns for a
1040 /// binop that produces a value.
1041 let TwoOperandAliasConstraint = "$Rn = $Rd" in
1042 multiclass AsI1_bin_irs<bits<4> opcod, string opc,
1043 InstrItinClass iii, InstrItinClass iir, InstrItinClass iis,
1044 PatFrag opnode, bit Commutable = 0> {
1045 // The register-immediate version is re-materializable. This is useful
1046 // in particular for taking the address of a local.
1047 let isReMaterializable = 1 in {
1048 def ri : AsI1<opcod, (outs GPR:$Rd), (ins GPR:$Rn, so_imm:$imm), DPFrm,
1049 iii, opc, "\t$Rd, $Rn, $imm",
1050 [(set GPR:$Rd, (opnode GPR:$Rn, so_imm:$imm))]>,
1051 Sched<[WriteALU, ReadALU]> {
1056 let Inst{19-16} = Rn;
1057 let Inst{15-12} = Rd;
1058 let Inst{11-0} = imm;
1061 def rr : AsI1<opcod, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm), DPFrm,
1062 iir, opc, "\t$Rd, $Rn, $Rm",
1063 [(set GPR:$Rd, (opnode GPR:$Rn, GPR:$Rm))]>,
1064 Sched<[WriteALU, ReadALU, ReadALU]> {
1069 let isCommutable = Commutable;
1070 let Inst{19-16} = Rn;
1071 let Inst{15-12} = Rd;
1072 let Inst{11-4} = 0b00000000;
1076 def rsi : AsI1<opcod, (outs GPR:$Rd),
1077 (ins GPR:$Rn, so_reg_imm:$shift), DPSoRegImmFrm,
1078 iis, opc, "\t$Rd, $Rn, $shift",
1079 [(set GPR:$Rd, (opnode GPR:$Rn, so_reg_imm:$shift))]>,
1080 Sched<[WriteALUsi, ReadALU]> {
1085 let Inst{19-16} = Rn;
1086 let Inst{15-12} = Rd;
1087 let Inst{11-5} = shift{11-5};
1089 let Inst{3-0} = shift{3-0};
1092 def rsr : AsI1<opcod, (outs GPR:$Rd),
1093 (ins GPR:$Rn, so_reg_reg:$shift), DPSoRegRegFrm,
1094 iis, opc, "\t$Rd, $Rn, $shift",
1095 [(set GPR:$Rd, (opnode GPR:$Rn, so_reg_reg:$shift))]>,
1096 Sched<[WriteALUsr, ReadALUsr]> {
1101 let Inst{19-16} = Rn;
1102 let Inst{15-12} = Rd;
1103 let Inst{11-8} = shift{11-8};
1105 let Inst{6-5} = shift{6-5};
1107 let Inst{3-0} = shift{3-0};
1111 /// AsI1_rbin_irs - Same as AsI1_bin_irs except the order of operands are
1112 /// reversed. The 'rr' form is only defined for the disassembler; for codegen
1113 /// it is equivalent to the AsI1_bin_irs counterpart.
1114 let TwoOperandAliasConstraint = "$Rn = $Rd" in
1115 multiclass AsI1_rbin_irs<bits<4> opcod, string opc,
1116 InstrItinClass iii, InstrItinClass iir, InstrItinClass iis,
1117 PatFrag opnode, bit Commutable = 0> {
1118 // The register-immediate version is re-materializable. This is useful
1119 // in particular for taking the address of a local.
1120 let isReMaterializable = 1 in {
1121 def ri : AsI1<opcod, (outs GPR:$Rd), (ins GPR:$Rn, so_imm:$imm), DPFrm,
1122 iii, opc, "\t$Rd, $Rn, $imm",
1123 [(set GPR:$Rd, (opnode so_imm:$imm, GPR:$Rn))]>,
1124 Sched<[WriteALU, ReadALU]> {
1129 let Inst{19-16} = Rn;
1130 let Inst{15-12} = Rd;
1131 let Inst{11-0} = imm;
1134 def rr : AsI1<opcod, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm), DPFrm,
1135 iir, opc, "\t$Rd, $Rn, $Rm",
1136 [/* pattern left blank */]>,
1137 Sched<[WriteALU, ReadALU, ReadALU]> {
1141 let Inst{11-4} = 0b00000000;
1144 let Inst{15-12} = Rd;
1145 let Inst{19-16} = Rn;
1148 def rsi : AsI1<opcod, (outs GPR:$Rd),
1149 (ins GPR:$Rn, so_reg_imm:$shift), DPSoRegImmFrm,
1150 iis, opc, "\t$Rd, $Rn, $shift",
1151 [(set GPR:$Rd, (opnode so_reg_imm:$shift, GPR:$Rn))]>,
1152 Sched<[WriteALUsi, ReadALU]> {
1157 let Inst{19-16} = Rn;
1158 let Inst{15-12} = Rd;
1159 let Inst{11-5} = shift{11-5};
1161 let Inst{3-0} = shift{3-0};
1164 def rsr : AsI1<opcod, (outs GPR:$Rd),
1165 (ins GPR:$Rn, so_reg_reg:$shift), DPSoRegRegFrm,
1166 iis, opc, "\t$Rd, $Rn, $shift",
1167 [(set GPR:$Rd, (opnode so_reg_reg:$shift, GPR:$Rn))]>,
1168 Sched<[WriteALUsr, ReadALUsr]> {
1173 let Inst{19-16} = Rn;
1174 let Inst{15-12} = Rd;
1175 let Inst{11-8} = shift{11-8};
1177 let Inst{6-5} = shift{6-5};
1179 let Inst{3-0} = shift{3-0};
1183 /// AsI1_bin_s_irs - Same as AsI1_bin_irs except it sets the 's' bit by default.
1185 /// These opcodes will be converted to the real non-S opcodes by
1186 /// AdjustInstrPostInstrSelection after giving them an optional CPSR operand.
1187 let hasPostISelHook = 1, Defs = [CPSR] in {
1188 multiclass AsI1_bin_s_irs<InstrItinClass iii, InstrItinClass iir,
1189 InstrItinClass iis, PatFrag opnode,
1190 bit Commutable = 0> {
1191 def ri : ARMPseudoInst<(outs GPR:$Rd), (ins GPR:$Rn, so_imm:$imm, pred:$p),
1193 [(set GPR:$Rd, CPSR, (opnode GPR:$Rn, so_imm:$imm))]>,
1194 Sched<[WriteALU, ReadALU]>;
1196 def rr : ARMPseudoInst<(outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm, pred:$p),
1198 [(set GPR:$Rd, CPSR, (opnode GPR:$Rn, GPR:$Rm))]>,
1199 Sched<[WriteALU, ReadALU, ReadALU]> {
1200 let isCommutable = Commutable;
1202 def rsi : ARMPseudoInst<(outs GPR:$Rd),
1203 (ins GPR:$Rn, so_reg_imm:$shift, pred:$p),
1205 [(set GPR:$Rd, CPSR, (opnode GPR:$Rn,
1206 so_reg_imm:$shift))]>,
1207 Sched<[WriteALUsi, ReadALU]>;
1209 def rsr : ARMPseudoInst<(outs GPR:$Rd),
1210 (ins GPR:$Rn, so_reg_reg:$shift, pred:$p),
1212 [(set GPR:$Rd, CPSR, (opnode GPR:$Rn,
1213 so_reg_reg:$shift))]>,
1214 Sched<[WriteALUSsr, ReadALUsr]>;
1218 /// AsI1_rbin_s_is - Same as AsI1_bin_s_irs, except selection DAG
1219 /// operands are reversed.
1220 let hasPostISelHook = 1, Defs = [CPSR] in {
1221 multiclass AsI1_rbin_s_is<InstrItinClass iii, InstrItinClass iir,
1222 InstrItinClass iis, PatFrag opnode,
1223 bit Commutable = 0> {
1224 def ri : ARMPseudoInst<(outs GPR:$Rd), (ins GPR:$Rn, so_imm:$imm, pred:$p),
1226 [(set GPR:$Rd, CPSR, (opnode so_imm:$imm, GPR:$Rn))]>,
1227 Sched<[WriteALU, ReadALU]>;
1229 def rsi : ARMPseudoInst<(outs GPR:$Rd),
1230 (ins GPR:$Rn, so_reg_imm:$shift, pred:$p),
1232 [(set GPR:$Rd, CPSR, (opnode so_reg_imm:$shift,
1234 Sched<[WriteALUsi, ReadALU]>;
1236 def rsr : ARMPseudoInst<(outs GPR:$Rd),
1237 (ins GPR:$Rn, so_reg_reg:$shift, pred:$p),
1239 [(set GPR:$Rd, CPSR, (opnode so_reg_reg:$shift,
1241 Sched<[WriteALUSsr, ReadALUsr]>;
1245 /// AI1_cmp_irs - Defines a set of (op r, {so_imm|r|so_reg}) cmp / test
1246 /// patterns. Similar to AsI1_bin_irs except the instruction does not produce
1247 /// a explicit result, only implicitly set CPSR.
1248 let isCompare = 1, Defs = [CPSR] in {
1249 multiclass AI1_cmp_irs<bits<4> opcod, string opc,
1250 InstrItinClass iii, InstrItinClass iir, InstrItinClass iis,
1251 PatFrag opnode, bit Commutable = 0> {
1252 def ri : AI1<opcod, (outs), (ins GPR:$Rn, so_imm:$imm), DPFrm, iii,
1254 [(opnode GPR:$Rn, so_imm:$imm)]>,
1255 Sched<[WriteCMP, ReadALU]> {
1260 let Inst{19-16} = Rn;
1261 let Inst{15-12} = 0b0000;
1262 let Inst{11-0} = imm;
1264 let Unpredictable{15-12} = 0b1111;
1266 def rr : AI1<opcod, (outs), (ins GPR:$Rn, GPR:$Rm), DPFrm, iir,
1268 [(opnode GPR:$Rn, GPR:$Rm)]>,
1269 Sched<[WriteCMP, ReadALU, ReadALU]> {
1272 let isCommutable = Commutable;
1275 let Inst{19-16} = Rn;
1276 let Inst{15-12} = 0b0000;
1277 let Inst{11-4} = 0b00000000;
1280 let Unpredictable{15-12} = 0b1111;
1282 def rsi : AI1<opcod, (outs),
1283 (ins GPR:$Rn, so_reg_imm:$shift), DPSoRegImmFrm, iis,
1284 opc, "\t$Rn, $shift",
1285 [(opnode GPR:$Rn, so_reg_imm:$shift)]>,
1286 Sched<[WriteCMPsi, ReadALU]> {
1291 let Inst{19-16} = Rn;
1292 let Inst{15-12} = 0b0000;
1293 let Inst{11-5} = shift{11-5};
1295 let Inst{3-0} = shift{3-0};
1297 let Unpredictable{15-12} = 0b1111;
1299 def rsr : AI1<opcod, (outs),
1300 (ins GPRnopc:$Rn, so_reg_reg:$shift), DPSoRegRegFrm, iis,
1301 opc, "\t$Rn, $shift",
1302 [(opnode GPRnopc:$Rn, so_reg_reg:$shift)]>,
1303 Sched<[WriteCMPsr, ReadALU]> {
1308 let Inst{19-16} = Rn;
1309 let Inst{15-12} = 0b0000;
1310 let Inst{11-8} = shift{11-8};
1312 let Inst{6-5} = shift{6-5};
1314 let Inst{3-0} = shift{3-0};
1316 let Unpredictable{15-12} = 0b1111;
1322 /// AI_ext_rrot - A unary operation with two forms: one whose operand is a
1323 /// register and one whose operand is a register rotated by 8/16/24.
1324 /// FIXME: Remove the 'r' variant. Its rot_imm is zero.
1325 class AI_ext_rrot<bits<8> opcod, string opc, PatFrag opnode>
1326 : AExtI<opcod, (outs GPRnopc:$Rd), (ins GPRnopc:$Rm, rot_imm:$rot),
1327 IIC_iEXTr, opc, "\t$Rd, $Rm$rot",
1328 [(set GPRnopc:$Rd, (opnode (rotr GPRnopc:$Rm, rot_imm:$rot)))]>,
1329 Requires<[IsARM, HasV6]>, Sched<[WriteALUsi]> {
1333 let Inst{19-16} = 0b1111;
1334 let Inst{15-12} = Rd;
1335 let Inst{11-10} = rot;
1339 class AI_ext_rrot_np<bits<8> opcod, string opc>
1340 : AExtI<opcod, (outs GPRnopc:$Rd), (ins GPRnopc:$Rm, rot_imm:$rot),
1341 IIC_iEXTr, opc, "\t$Rd, $Rm$rot", []>,
1342 Requires<[IsARM, HasV6]>, Sched<[WriteALUsi]> {
1344 let Inst{19-16} = 0b1111;
1345 let Inst{11-10} = rot;
1348 /// AI_exta_rrot - A binary operation with two forms: one whose operand is a
1349 /// register and one whose operand is a register rotated by 8/16/24.
1350 class AI_exta_rrot<bits<8> opcod, string opc, PatFrag opnode>
1351 : AExtI<opcod, (outs GPRnopc:$Rd), (ins GPR:$Rn, GPRnopc:$Rm, rot_imm:$rot),
1352 IIC_iEXTAr, opc, "\t$Rd, $Rn, $Rm$rot",
1353 [(set GPRnopc:$Rd, (opnode GPR:$Rn,
1354 (rotr GPRnopc:$Rm, rot_imm:$rot)))]>,
1355 Requires<[IsARM, HasV6]>, Sched<[WriteALUsr]> {
1360 let Inst{19-16} = Rn;
1361 let Inst{15-12} = Rd;
1362 let Inst{11-10} = rot;
1363 let Inst{9-4} = 0b000111;
1367 class AI_exta_rrot_np<bits<8> opcod, string opc>
1368 : AExtI<opcod, (outs GPRnopc:$Rd), (ins GPR:$Rn, GPRnopc:$Rm, rot_imm:$rot),
1369 IIC_iEXTAr, opc, "\t$Rd, $Rn, $Rm$rot", []>,
1370 Requires<[IsARM, HasV6]>, Sched<[WriteALUsr]> {
1373 let Inst{19-16} = Rn;
1374 let Inst{11-10} = rot;
1377 /// AI1_adde_sube_irs - Define instructions and patterns for adde and sube.
1378 let TwoOperandAliasConstraint = "$Rn = $Rd" in
1379 multiclass AI1_adde_sube_irs<bits<4> opcod, string opc, PatFrag opnode,
1380 bit Commutable = 0> {
1381 let hasPostISelHook = 1, Defs = [CPSR], Uses = [CPSR] in {
1382 def ri : AsI1<opcod, (outs GPR:$Rd), (ins GPR:$Rn, so_imm:$imm),
1383 DPFrm, IIC_iALUi, opc, "\t$Rd, $Rn, $imm",
1384 [(set GPR:$Rd, CPSR, (opnode GPR:$Rn, so_imm:$imm, CPSR))]>,
1386 Sched<[WriteALU, ReadALU]> {
1391 let Inst{15-12} = Rd;
1392 let Inst{19-16} = Rn;
1393 let Inst{11-0} = imm;
1395 def rr : AsI1<opcod, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm),
1396 DPFrm, IIC_iALUr, opc, "\t$Rd, $Rn, $Rm",
1397 [(set GPR:$Rd, CPSR, (opnode GPR:$Rn, GPR:$Rm, CPSR))]>,
1399 Sched<[WriteALU, ReadALU, ReadALU]> {
1403 let Inst{11-4} = 0b00000000;
1405 let isCommutable = Commutable;
1407 let Inst{15-12} = Rd;
1408 let Inst{19-16} = Rn;
1410 def rsi : AsI1<opcod, (outs GPR:$Rd),
1411 (ins GPR:$Rn, so_reg_imm:$shift),
1412 DPSoRegImmFrm, IIC_iALUsr, opc, "\t$Rd, $Rn, $shift",
1413 [(set GPR:$Rd, CPSR, (opnode GPR:$Rn, so_reg_imm:$shift, CPSR))]>,
1415 Sched<[WriteALUsi, ReadALU]> {
1420 let Inst{19-16} = Rn;
1421 let Inst{15-12} = Rd;
1422 let Inst{11-5} = shift{11-5};
1424 let Inst{3-0} = shift{3-0};
1426 def rsr : AsI1<opcod, (outs GPRnopc:$Rd),
1427 (ins GPRnopc:$Rn, so_reg_reg:$shift),
1428 DPSoRegRegFrm, IIC_iALUsr, opc, "\t$Rd, $Rn, $shift",
1429 [(set GPRnopc:$Rd, CPSR,
1430 (opnode GPRnopc:$Rn, so_reg_reg:$shift, CPSR))]>,
1432 Sched<[WriteALUsr, ReadALUsr]> {
1437 let Inst{19-16} = Rn;
1438 let Inst{15-12} = Rd;
1439 let Inst{11-8} = shift{11-8};
1441 let Inst{6-5} = shift{6-5};
1443 let Inst{3-0} = shift{3-0};
1448 /// AI1_rsc_irs - Define instructions and patterns for rsc
1449 let TwoOperandAliasConstraint = "$Rn = $Rd" in
1450 multiclass AI1_rsc_irs<bits<4> opcod, string opc, PatFrag opnode> {
1451 let hasPostISelHook = 1, Defs = [CPSR], Uses = [CPSR] in {
1452 def ri : AsI1<opcod, (outs GPR:$Rd), (ins GPR:$Rn, so_imm:$imm),
1453 DPFrm, IIC_iALUi, opc, "\t$Rd, $Rn, $imm",
1454 [(set GPR:$Rd, CPSR, (opnode so_imm:$imm, GPR:$Rn, CPSR))]>,
1456 Sched<[WriteALU, ReadALU]> {
1461 let Inst{15-12} = Rd;
1462 let Inst{19-16} = Rn;
1463 let Inst{11-0} = imm;
1465 def rr : AsI1<opcod, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm),
1466 DPFrm, IIC_iALUr, opc, "\t$Rd, $Rn, $Rm",
1467 [/* pattern left blank */]>,
1468 Sched<[WriteALU, ReadALU, ReadALU]> {
1472 let Inst{11-4} = 0b00000000;
1475 let Inst{15-12} = Rd;
1476 let Inst{19-16} = Rn;
1478 def rsi : AsI1<opcod, (outs GPR:$Rd), (ins GPR:$Rn, so_reg_imm:$shift),
1479 DPSoRegImmFrm, IIC_iALUsr, opc, "\t$Rd, $Rn, $shift",
1480 [(set GPR:$Rd, CPSR, (opnode so_reg_imm:$shift, GPR:$Rn, CPSR))]>,
1482 Sched<[WriteALUsi, ReadALU]> {
1487 let Inst{19-16} = Rn;
1488 let Inst{15-12} = Rd;
1489 let Inst{11-5} = shift{11-5};
1491 let Inst{3-0} = shift{3-0};
1493 def rsr : AsI1<opcod, (outs GPR:$Rd), (ins GPR:$Rn, so_reg_reg:$shift),
1494 DPSoRegRegFrm, IIC_iALUsr, opc, "\t$Rd, $Rn, $shift",
1495 [(set GPR:$Rd, CPSR, (opnode so_reg_reg:$shift, GPR:$Rn, CPSR))]>,
1497 Sched<[WriteALUsr, ReadALUsr]> {
1502 let Inst{19-16} = Rn;
1503 let Inst{15-12} = Rd;
1504 let Inst{11-8} = shift{11-8};
1506 let Inst{6-5} = shift{6-5};
1508 let Inst{3-0} = shift{3-0};
1513 let canFoldAsLoad = 1, isReMaterializable = 1 in {
1514 multiclass AI_ldr1<bit isByte, string opc, InstrItinClass iii,
1515 InstrItinClass iir, PatFrag opnode> {
1516 // Note: We use the complex addrmode_imm12 rather than just an input
1517 // GPR and a constrained immediate so that we can use this to match
1518 // frame index references and avoid matching constant pool references.
1519 def i12: AI2ldst<0b010, 1, isByte, (outs GPR:$Rt), (ins addrmode_imm12:$addr),
1520 AddrMode_i12, LdFrm, iii, opc, "\t$Rt, $addr",
1521 [(set GPR:$Rt, (opnode addrmode_imm12:$addr))]> {
1524 let Inst{23} = addr{12}; // U (add = ('U' == 1))
1525 let Inst{19-16} = addr{16-13}; // Rn
1526 let Inst{15-12} = Rt;
1527 let Inst{11-0} = addr{11-0}; // imm12
1529 def rs : AI2ldst<0b011, 1, isByte, (outs GPR:$Rt), (ins ldst_so_reg:$shift),
1530 AddrModeNone, LdFrm, iir, opc, "\t$Rt, $shift",
1531 [(set GPR:$Rt, (opnode ldst_so_reg:$shift))]> {
1534 let shift{4} = 0; // Inst{4} = 0
1535 let Inst{23} = shift{12}; // U (add = ('U' == 1))
1536 let Inst{19-16} = shift{16-13}; // Rn
1537 let Inst{15-12} = Rt;
1538 let Inst{11-0} = shift{11-0};
1543 let canFoldAsLoad = 1, isReMaterializable = 1 in {
1544 multiclass AI_ldr1nopc<bit isByte, string opc, InstrItinClass iii,
1545 InstrItinClass iir, PatFrag opnode> {
1546 // Note: We use the complex addrmode_imm12 rather than just an input
1547 // GPR and a constrained immediate so that we can use this to match
1548 // frame index references and avoid matching constant pool references.
1549 def i12: AI2ldst<0b010, 1, isByte, (outs GPRnopc:$Rt),
1550 (ins addrmode_imm12:$addr),
1551 AddrMode_i12, LdFrm, iii, opc, "\t$Rt, $addr",
1552 [(set GPRnopc:$Rt, (opnode addrmode_imm12:$addr))]> {
1555 let Inst{23} = addr{12}; // U (add = ('U' == 1))
1556 let Inst{19-16} = addr{16-13}; // Rn
1557 let Inst{15-12} = Rt;
1558 let Inst{11-0} = addr{11-0}; // imm12
1560 def rs : AI2ldst<0b011, 1, isByte, (outs GPRnopc:$Rt),
1561 (ins ldst_so_reg:$shift),
1562 AddrModeNone, LdFrm, iir, opc, "\t$Rt, $shift",
1563 [(set GPRnopc:$Rt, (opnode ldst_so_reg:$shift))]> {
1566 let shift{4} = 0; // Inst{4} = 0
1567 let Inst{23} = shift{12}; // U (add = ('U' == 1))
1568 let Inst{19-16} = shift{16-13}; // Rn
1569 let Inst{15-12} = Rt;
1570 let Inst{11-0} = shift{11-0};
1576 multiclass AI_str1<bit isByte, string opc, InstrItinClass iii,
1577 InstrItinClass iir, PatFrag opnode> {
1578 // Note: We use the complex addrmode_imm12 rather than just an input
1579 // GPR and a constrained immediate so that we can use this to match
1580 // frame index references and avoid matching constant pool references.
1581 def i12 : AI2ldst<0b010, 0, isByte, (outs),
1582 (ins GPR:$Rt, addrmode_imm12:$addr),
1583 AddrMode_i12, StFrm, iii, opc, "\t$Rt, $addr",
1584 [(opnode GPR:$Rt, addrmode_imm12:$addr)]> {
1587 let Inst{23} = addr{12}; // U (add = ('U' == 1))
1588 let Inst{19-16} = addr{16-13}; // Rn
1589 let Inst{15-12} = Rt;
1590 let Inst{11-0} = addr{11-0}; // imm12
1592 def rs : AI2ldst<0b011, 0, isByte, (outs), (ins GPR:$Rt, ldst_so_reg:$shift),
1593 AddrModeNone, StFrm, iir, opc, "\t$Rt, $shift",
1594 [(opnode GPR:$Rt, ldst_so_reg:$shift)]> {
1597 let shift{4} = 0; // Inst{4} = 0
1598 let Inst{23} = shift{12}; // U (add = ('U' == 1))
1599 let Inst{19-16} = shift{16-13}; // Rn
1600 let Inst{15-12} = Rt;
1601 let Inst{11-0} = shift{11-0};
1605 multiclass AI_str1nopc<bit isByte, string opc, InstrItinClass iii,
1606 InstrItinClass iir, PatFrag opnode> {
1607 // Note: We use the complex addrmode_imm12 rather than just an input
1608 // GPR and a constrained immediate so that we can use this to match
1609 // frame index references and avoid matching constant pool references.
1610 def i12 : AI2ldst<0b010, 0, isByte, (outs),
1611 (ins GPRnopc:$Rt, addrmode_imm12:$addr),
1612 AddrMode_i12, StFrm, iii, opc, "\t$Rt, $addr",
1613 [(opnode GPRnopc:$Rt, addrmode_imm12:$addr)]> {
1616 let Inst{23} = addr{12}; // U (add = ('U' == 1))
1617 let Inst{19-16} = addr{16-13}; // Rn
1618 let Inst{15-12} = Rt;
1619 let Inst{11-0} = addr{11-0}; // imm12
1621 def rs : AI2ldst<0b011, 0, isByte, (outs),
1622 (ins GPRnopc:$Rt, ldst_so_reg:$shift),
1623 AddrModeNone, StFrm, iir, opc, "\t$Rt, $shift",
1624 [(opnode GPRnopc:$Rt, ldst_so_reg:$shift)]> {
1627 let shift{4} = 0; // Inst{4} = 0
1628 let Inst{23} = shift{12}; // U (add = ('U' == 1))
1629 let Inst{19-16} = shift{16-13}; // Rn
1630 let Inst{15-12} = Rt;
1631 let Inst{11-0} = shift{11-0};
1636 //===----------------------------------------------------------------------===//
1638 //===----------------------------------------------------------------------===//
1640 //===----------------------------------------------------------------------===//
1641 // Miscellaneous Instructions.
1644 /// CONSTPOOL_ENTRY - This instruction represents a floating constant pool in
1645 /// the function. The first operand is the ID# for this instruction, the second
1646 /// is the index into the MachineConstantPool that this is, the third is the
1647 /// size in bytes of this constant pool entry.
1648 let neverHasSideEffects = 1, isNotDuplicable = 1 in
1649 def CONSTPOOL_ENTRY :
1650 PseudoInst<(outs), (ins cpinst_operand:$instid, cpinst_operand:$cpidx,
1651 i32imm:$size), NoItinerary, []>;
1653 // FIXME: Marking these as hasSideEffects is necessary to prevent machine DCE
1654 // from removing one half of the matched pairs. That breaks PEI, which assumes
1655 // these will always be in pairs, and asserts if it finds otherwise. Better way?
1656 let Defs = [SP], Uses = [SP], hasSideEffects = 1 in {
1657 def ADJCALLSTACKUP :
1658 PseudoInst<(outs), (ins i32imm:$amt1, i32imm:$amt2, pred:$p), NoItinerary,
1659 [(ARMcallseq_end timm:$amt1, timm:$amt2)]>;
1661 def ADJCALLSTACKDOWN :
1662 PseudoInst<(outs), (ins i32imm:$amt, pred:$p), NoItinerary,
1663 [(ARMcallseq_start timm:$amt)]>;
1666 // Atomic pseudo-insts which will be lowered to ldrexd/strexd loops.
1667 // (These pseudos use a hand-written selection code).
1668 let usesCustomInserter = 1, Defs = [CPSR], mayLoad = 1, mayStore = 1 in {
1669 def ATOMOR6432 : PseudoInst<(outs GPR:$dst1, GPR:$dst2),
1670 (ins GPR:$addr, GPR:$src1, GPR:$src2),
1672 def ATOMXOR6432 : PseudoInst<(outs GPR:$dst1, GPR:$dst2),
1673 (ins GPR:$addr, GPR:$src1, GPR:$src2),
1675 def ATOMADD6432 : PseudoInst<(outs GPR:$dst1, GPR:$dst2),
1676 (ins GPR:$addr, GPR:$src1, GPR:$src2),
1678 def ATOMSUB6432 : PseudoInst<(outs GPR:$dst1, GPR:$dst2),
1679 (ins GPR:$addr, GPR:$src1, GPR:$src2),
1681 def ATOMNAND6432 : PseudoInst<(outs GPR:$dst1, GPR:$dst2),
1682 (ins GPR:$addr, GPR:$src1, GPR:$src2),
1684 def ATOMAND6432 : PseudoInst<(outs GPR:$dst1, GPR:$dst2),
1685 (ins GPR:$addr, GPR:$src1, GPR:$src2),
1687 def ATOMSWAP6432 : PseudoInst<(outs GPR:$dst1, GPR:$dst2),
1688 (ins GPR:$addr, GPR:$src1, GPR:$src2),
1690 def ATOMCMPXCHG6432 : PseudoInst<(outs GPR:$dst1, GPR:$dst2),
1691 (ins GPR:$addr, GPR:$cmp1, GPR:$cmp2,
1692 GPR:$set1, GPR:$set2),
1694 def ATOMMIN6432 : PseudoInst<(outs GPR:$dst1, GPR:$dst2),
1695 (ins GPR:$addr, GPR:$src1, GPR:$src2),
1697 def ATOMUMIN6432 : PseudoInst<(outs GPR:$dst1, GPR:$dst2),
1698 (ins GPR:$addr, GPR:$src1, GPR:$src2),
1700 def ATOMMAX6432 : PseudoInst<(outs GPR:$dst1, GPR:$dst2),
1701 (ins GPR:$addr, GPR:$src1, GPR:$src2),
1703 def ATOMUMAX6432 : PseudoInst<(outs GPR:$dst1, GPR:$dst2),
1704 (ins GPR:$addr, GPR:$src1, GPR:$src2),
1708 def HINT : AI<(outs), (ins imm0_4:$imm), MiscFrm, NoItinerary,
1709 "hint", "\t$imm", []>, Requires<[IsARM, HasV6]> {
1711 let Inst{27-3} = 0b0011001000001111000000000;
1712 let Inst{2-0} = imm;
1715 def : InstAlias<"nop$p", (HINT 0, pred:$p)>, Requires<[IsARM, HasV6T2]>;
1716 def : InstAlias<"yield$p", (HINT 1, pred:$p)>, Requires<[IsARM, HasV6T2]>;
1717 def : InstAlias<"wfe$p", (HINT 2, pred:$p)>, Requires<[IsARM, HasV6T2]>;
1718 def : InstAlias<"wfi$p", (HINT 3, pred:$p)>, Requires<[IsARM, HasV6T2]>;
1719 def : InstAlias<"sev$p", (HINT 4, pred:$p)>, Requires<[IsARM, HasV6T2]>;
1721 def SEL : AI<(outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm), DPFrm, NoItinerary, "sel",
1722 "\t$Rd, $Rn, $Rm", []>, Requires<[IsARM, HasV6]> {
1727 let Inst{15-12} = Rd;
1728 let Inst{19-16} = Rn;
1729 let Inst{27-20} = 0b01101000;
1730 let Inst{7-4} = 0b1011;
1731 let Inst{11-8} = 0b1111;
1732 let Unpredictable{11-8} = 0b1111;
1735 // The 16-bit operand $val can be used by a debugger to store more information
1736 // about the breakpoint.
1737 def BKPT : AInoP<(outs), (ins imm0_65535:$val), MiscFrm, NoItinerary,
1738 "bkpt", "\t$val", []>, Requires<[IsARM]> {
1740 let Inst{3-0} = val{3-0};
1741 let Inst{19-8} = val{15-4};
1742 let Inst{27-20} = 0b00010010;
1743 let Inst{31-28} = 0xe; // AL
1744 let Inst{7-4} = 0b0111;
1747 // Change Processor State
1748 // FIXME: We should use InstAlias to handle the optional operands.
1749 class CPS<dag iops, string asm_ops>
1750 : AXI<(outs), iops, MiscFrm, NoItinerary, !strconcat("cps", asm_ops),
1751 []>, Requires<[IsARM]> {
1757 let Inst{31-28} = 0b1111;
1758 let Inst{27-20} = 0b00010000;
1759 let Inst{19-18} = imod;
1760 let Inst{17} = M; // Enabled if mode is set;
1761 let Inst{16-9} = 0b00000000;
1762 let Inst{8-6} = iflags;
1764 let Inst{4-0} = mode;
1767 let DecoderMethod = "DecodeCPSInstruction" in {
1769 def CPS3p : CPS<(ins imod_op:$imod, iflags_op:$iflags, imm0_31:$mode),
1770 "$imod\t$iflags, $mode">;
1771 let mode = 0, M = 0 in
1772 def CPS2p : CPS<(ins imod_op:$imod, iflags_op:$iflags), "$imod\t$iflags">;
1774 let imod = 0, iflags = 0, M = 1 in
1775 def CPS1p : CPS<(ins imm0_31:$mode), "\t$mode">;
1778 // Preload signals the memory system of possible future data/instruction access.
1779 multiclass APreLoad<bits<1> read, bits<1> data, string opc> {
1781 def i12 : AXI<(outs), (ins addrmode_imm12:$addr), MiscFrm, IIC_Preload,
1782 !strconcat(opc, "\t$addr"),
1783 [(ARMPreload addrmode_imm12:$addr, (i32 read), (i32 data))]>,
1784 Sched<[WritePreLd]> {
1787 let Inst{31-26} = 0b111101;
1788 let Inst{25} = 0; // 0 for immediate form
1789 let Inst{24} = data;
1790 let Inst{23} = addr{12}; // U (add = ('U' == 1))
1791 let Inst{22} = read;
1792 let Inst{21-20} = 0b01;
1793 let Inst{19-16} = addr{16-13}; // Rn
1794 let Inst{15-12} = 0b1111;
1795 let Inst{11-0} = addr{11-0}; // imm12
1798 def rs : AXI<(outs), (ins ldst_so_reg:$shift), MiscFrm, IIC_Preload,
1799 !strconcat(opc, "\t$shift"),
1800 [(ARMPreload ldst_so_reg:$shift, (i32 read), (i32 data))]>,
1801 Sched<[WritePreLd]> {
1803 let Inst{31-26} = 0b111101;
1804 let Inst{25} = 1; // 1 for register form
1805 let Inst{24} = data;
1806 let Inst{23} = shift{12}; // U (add = ('U' == 1))
1807 let Inst{22} = read;
1808 let Inst{21-20} = 0b01;
1809 let Inst{19-16} = shift{16-13}; // Rn
1810 let Inst{15-12} = 0b1111;
1811 let Inst{11-0} = shift{11-0};
1816 defm PLD : APreLoad<1, 1, "pld">, Requires<[IsARM]>;
1817 defm PLDW : APreLoad<0, 1, "pldw">, Requires<[IsARM,HasV7,HasMP]>;
1818 defm PLI : APreLoad<1, 0, "pli">, Requires<[IsARM,HasV7]>;
1820 def SETEND : AXI<(outs), (ins setend_op:$end), MiscFrm, NoItinerary,
1821 "setend\t$end", []>, Requires<[IsARM]> {
1823 let Inst{31-10} = 0b1111000100000001000000;
1828 def DBG : AI<(outs), (ins imm0_15:$opt), MiscFrm, NoItinerary, "dbg", "\t$opt",
1829 []>, Requires<[IsARM, HasV7]> {
1831 let Inst{27-4} = 0b001100100000111100001111;
1832 let Inst{3-0} = opt;
1836 * A5.4 Permanently UNDEFINED instructions.
1838 * For most targets use UDF #65006, for which the OS will generate SIGTRAP.
1839 * Other UDF encodings generate SIGILL.
1841 * NaCl's OS instead chooses an ARM UDF encoding that's also a UDF in Thumb.
1843 * 1110 0111 1111 iiii iiii iiii 1111 iiii
1845 * 1101 1110 iiii iiii
1846 * It uses the following encoding:
1847 * 1110 0111 1111 1110 1101 1110 1111 0000
1848 * - In ARM: UDF #60896;
1849 * - In Thumb: UDF #254 followed by a branch-to-self.
1851 let isBarrier = 1, isTerminator = 1 in
1852 def TRAPNaCl : AXI<(outs), (ins), MiscFrm, NoItinerary,
1854 Requires<[IsARM,UseNaClTrap]> {
1855 let Inst = 0xe7fedef0;
1857 let isBarrier = 1, isTerminator = 1 in
1858 def TRAP : AXI<(outs), (ins), MiscFrm, NoItinerary,
1860 Requires<[IsARM,DontUseNaClTrap]> {
1861 let Inst = 0xe7ffdefe;
1864 // Address computation and loads and stores in PIC mode.
1865 let isNotDuplicable = 1 in {
1866 def PICADD : ARMPseudoInst<(outs GPR:$dst), (ins GPR:$a, pclabel:$cp, pred:$p),
1868 [(set GPR:$dst, (ARMpic_add GPR:$a, imm:$cp))]>,
1869 Sched<[WriteALU, ReadALU]>;
1871 let AddedComplexity = 10 in {
1872 def PICLDR : ARMPseudoInst<(outs GPR:$dst), (ins addrmodepc:$addr, pred:$p),
1874 [(set GPR:$dst, (load addrmodepc:$addr))]>;
1876 def PICLDRH : ARMPseudoInst<(outs GPR:$Rt), (ins addrmodepc:$addr, pred:$p),
1878 [(set GPR:$Rt, (zextloadi16 addrmodepc:$addr))]>;
1880 def PICLDRB : ARMPseudoInst<(outs GPR:$Rt), (ins addrmodepc:$addr, pred:$p),
1882 [(set GPR:$Rt, (zextloadi8 addrmodepc:$addr))]>;
1884 def PICLDRSH : ARMPseudoInst<(outs GPR:$Rt), (ins addrmodepc:$addr, pred:$p),
1886 [(set GPR:$Rt, (sextloadi16 addrmodepc:$addr))]>;
1888 def PICLDRSB : ARMPseudoInst<(outs GPR:$Rt), (ins addrmodepc:$addr, pred:$p),
1890 [(set GPR:$Rt, (sextloadi8 addrmodepc:$addr))]>;
1892 let AddedComplexity = 10 in {
1893 def PICSTR : ARMPseudoInst<(outs), (ins GPR:$src, addrmodepc:$addr, pred:$p),
1894 4, IIC_iStore_r, [(store GPR:$src, addrmodepc:$addr)]>;
1896 def PICSTRH : ARMPseudoInst<(outs), (ins GPR:$src, addrmodepc:$addr, pred:$p),
1897 4, IIC_iStore_bh_r, [(truncstorei16 GPR:$src,
1898 addrmodepc:$addr)]>;
1900 def PICSTRB : ARMPseudoInst<(outs), (ins GPR:$src, addrmodepc:$addr, pred:$p),
1901 4, IIC_iStore_bh_r, [(truncstorei8 GPR:$src, addrmodepc:$addr)]>;
1903 } // isNotDuplicable = 1
1906 // LEApcrel - Load a pc-relative address into a register without offending the
1908 let neverHasSideEffects = 1, isReMaterializable = 1 in
1909 // The 'adr' mnemonic encodes differently if the label is before or after
1910 // the instruction. The {24-21} opcode bits are set by the fixup, as we don't
1911 // know until then which form of the instruction will be used.
1912 def ADR : AI1<{0,?,?,0}, (outs GPR:$Rd), (ins adrlabel:$label),
1913 MiscFrm, IIC_iALUi, "adr", "\t$Rd, $label", []>,
1914 Sched<[WriteALU, ReadALU]> {
1917 let Inst{27-25} = 0b001;
1919 let Inst{23-22} = label{13-12};
1922 let Inst{19-16} = 0b1111;
1923 let Inst{15-12} = Rd;
1924 let Inst{11-0} = label{11-0};
1927 let hasSideEffects = 1 in {
1928 def LEApcrel : ARMPseudoInst<(outs GPR:$Rd), (ins i32imm:$label, pred:$p),
1929 4, IIC_iALUi, []>, Sched<[WriteALU, ReadALU]>;
1931 def LEApcrelJT : ARMPseudoInst<(outs GPR:$Rd),
1932 (ins i32imm:$label, nohash_imm:$id, pred:$p),
1933 4, IIC_iALUi, []>, Sched<[WriteALU, ReadALU]>;
1936 //===----------------------------------------------------------------------===//
1937 // Control Flow Instructions.
1940 let isReturn = 1, isTerminator = 1, isBarrier = 1 in {
1942 def BX_RET : AI<(outs), (ins), BrMiscFrm, IIC_Br,
1943 "bx", "\tlr", [(ARMretflag)]>,
1944 Requires<[IsARM, HasV4T]>, Sched<[WriteBr]> {
1945 let Inst{27-0} = 0b0001001011111111111100011110;
1949 def MOVPCLR : AI<(outs), (ins), BrMiscFrm, IIC_Br,
1950 "mov", "\tpc, lr", [(ARMretflag)]>,
1951 Requires<[IsARM, NoV4T]>, Sched<[WriteBr]> {
1952 let Inst{27-0} = 0b0001101000001111000000001110;
1956 // Indirect branches
1957 let isBranch = 1, isTerminator = 1, isBarrier = 1, isIndirectBranch = 1 in {
1959 def BX : AXI<(outs), (ins GPR:$dst), BrMiscFrm, IIC_Br, "bx\t$dst",
1960 [(brind GPR:$dst)]>,
1961 Requires<[IsARM, HasV4T]>, Sched<[WriteBr]> {
1963 let Inst{31-4} = 0b1110000100101111111111110001;
1964 let Inst{3-0} = dst;
1967 def BX_pred : AI<(outs), (ins GPR:$dst), BrMiscFrm, IIC_Br,
1968 "bx", "\t$dst", [/* pattern left blank */]>,
1969 Requires<[IsARM, HasV4T]>, Sched<[WriteBr]> {
1971 let Inst{27-4} = 0b000100101111111111110001;
1972 let Inst{3-0} = dst;
1976 // SP is marked as a use to prevent stack-pointer assignments that appear
1977 // immediately before calls from potentially appearing dead.
1979 // FIXME: Do we really need a non-predicated version? If so, it should
1980 // at least be a pseudo instruction expanding to the predicated version
1981 // at MC lowering time.
1982 Defs = [LR], Uses = [SP] in {
1983 def BL : ABXI<0b1011, (outs), (ins bl_target:$func),
1984 IIC_Br, "bl\t$func",
1985 [(ARMcall tglobaladdr:$func)]>,
1986 Requires<[IsARM]>, Sched<[WriteBrL]> {
1987 let Inst{31-28} = 0b1110;
1989 let Inst{23-0} = func;
1990 let DecoderMethod = "DecodeBranchImmInstruction";
1993 def BL_pred : ABI<0b1011, (outs), (ins bl_target:$func),
1994 IIC_Br, "bl", "\t$func",
1995 [(ARMcall_pred tglobaladdr:$func)]>,
1996 Requires<[IsARM]>, Sched<[WriteBrL]> {
1998 let Inst{23-0} = func;
1999 let DecoderMethod = "DecodeBranchImmInstruction";
2003 def BLX : AXI<(outs), (ins GPR:$func), BrMiscFrm,
2004 IIC_Br, "blx\t$func",
2005 [(ARMcall GPR:$func)]>,
2006 Requires<[IsARM, HasV5T]>, Sched<[WriteBrL]> {
2008 let Inst{31-4} = 0b1110000100101111111111110011;
2009 let Inst{3-0} = func;
2012 def BLX_pred : AI<(outs), (ins GPR:$func), BrMiscFrm,
2013 IIC_Br, "blx", "\t$func",
2014 [(ARMcall_pred GPR:$func)]>,
2015 Requires<[IsARM, HasV5T]>, Sched<[WriteBrL]> {
2017 let Inst{27-4} = 0b000100101111111111110011;
2018 let Inst{3-0} = func;
2022 // Note: Restrict $func to the tGPR regclass to prevent it being in LR.
2023 def BX_CALL : ARMPseudoInst<(outs), (ins tGPR:$func),
2024 8, IIC_Br, [(ARMcall_nolink tGPR:$func)]>,
2025 Requires<[IsARM, HasV4T]>, Sched<[WriteBr]>;
2028 def BMOVPCRX_CALL : ARMPseudoInst<(outs), (ins tGPR:$func),
2029 8, IIC_Br, [(ARMcall_nolink tGPR:$func)]>,
2030 Requires<[IsARM, NoV4T]>, Sched<[WriteBr]>;
2032 // mov lr, pc; b if callee is marked noreturn to avoid confusing the
2033 // return stack predictor.
2034 def BMOVPCB_CALL : ARMPseudoInst<(outs), (ins bl_target:$func),
2035 8, IIC_Br, [(ARMcall_nolink tglobaladdr:$func)]>,
2036 Requires<[IsARM]>, Sched<[WriteBr]>;
2039 let isBranch = 1, isTerminator = 1 in {
2040 // FIXME: should be able to write a pattern for ARMBrcond, but can't use
2041 // a two-value operand where a dag node expects two operands. :(
2042 def Bcc : ABI<0b1010, (outs), (ins br_target:$target),
2043 IIC_Br, "b", "\t$target",
2044 [/*(ARMbrcond bb:$target, imm:$cc, CCR:$ccr)*/]>,
2047 let Inst{23-0} = target;
2048 let DecoderMethod = "DecodeBranchImmInstruction";
2051 let isBarrier = 1 in {
2052 // B is "predicable" since it's just a Bcc with an 'always' condition.
2053 let isPredicable = 1 in
2054 // FIXME: We shouldn't need this pseudo at all. Just using Bcc directly
2055 // should be sufficient.
2056 // FIXME: Is B really a Barrier? That doesn't seem right.
2057 def B : ARMPseudoExpand<(outs), (ins br_target:$target), 4, IIC_Br,
2058 [(br bb:$target)], (Bcc br_target:$target, (ops 14, zero_reg))>,
2061 let isNotDuplicable = 1, isIndirectBranch = 1 in {
2062 def BR_JTr : ARMPseudoInst<(outs),
2063 (ins GPR:$target, i32imm:$jt, i32imm:$id),
2065 [(ARMbrjt GPR:$target, tjumptable:$jt, imm:$id)]>,
2067 // FIXME: This shouldn't use the generic "addrmode2," but rather be split
2068 // into i12 and rs suffixed versions.
2069 def BR_JTm : ARMPseudoInst<(outs),
2070 (ins addrmode2:$target, i32imm:$jt, i32imm:$id),
2072 [(ARMbrjt (i32 (load addrmode2:$target)), tjumptable:$jt,
2073 imm:$id)]>, Sched<[WriteBrTbl]>;
2074 def BR_JTadd : ARMPseudoInst<(outs),
2075 (ins GPR:$target, GPR:$idx, i32imm:$jt, i32imm:$id),
2077 [(ARMbrjt (add GPR:$target, GPR:$idx), tjumptable:$jt,
2078 imm:$id)]>, Sched<[WriteBrTbl]>;
2079 } // isNotDuplicable = 1, isIndirectBranch = 1
2085 def BLXi : AXI<(outs), (ins blx_target:$target), BrMiscFrm, NoItinerary,
2086 "blx\t$target", []>,
2087 Requires<[IsARM, HasV5T]>, Sched<[WriteBrL]> {
2088 let Inst{31-25} = 0b1111101;
2090 let Inst{23-0} = target{24-1};
2091 let Inst{24} = target{0};
2094 // Branch and Exchange Jazelle
2095 def BXJ : ABI<0b0001, (outs), (ins GPR:$func), NoItinerary, "bxj", "\t$func",
2096 [/* pattern left blank */]>, Sched<[WriteBr]> {
2098 let Inst{23-20} = 0b0010;
2099 let Inst{19-8} = 0xfff;
2100 let Inst{7-4} = 0b0010;
2101 let Inst{3-0} = func;
2106 let isCall = 1, isTerminator = 1, isReturn = 1, isBarrier = 1, Uses = [SP] in {
2107 def TCRETURNdi : PseudoInst<(outs), (ins i32imm:$dst), IIC_Br, []>,
2110 def TCRETURNri : PseudoInst<(outs), (ins tcGPR:$dst), IIC_Br, []>,
2113 def TAILJMPd : ARMPseudoExpand<(outs), (ins br_target:$dst),
2115 (Bcc br_target:$dst, (ops 14, zero_reg))>,
2116 Requires<[IsARM]>, Sched<[WriteBr]>;
2118 def TAILJMPr : ARMPseudoExpand<(outs), (ins tcGPR:$dst),
2120 (BX GPR:$dst)>, Sched<[WriteBr]>,
2124 // Secure Monitor Call is a system instruction.
2125 def SMC : ABI<0b0001, (outs), (ins imm0_15:$opt), NoItinerary, "smc", "\t$opt",
2126 []>, Requires<[IsARM, HasTrustZone]> {
2128 let Inst{23-4} = 0b01100000000000000111;
2129 let Inst{3-0} = opt;
2132 // Supervisor Call (Software Interrupt)
2133 let isCall = 1, Uses = [SP] in {
2134 def SVC : ABI<0b1111, (outs), (ins imm24b:$svc), IIC_Br, "svc", "\t$svc", []>,
2137 let Inst{23-0} = svc;
2141 // Store Return State
2142 class SRSI<bit wb, string asm>
2143 : XI<(outs), (ins imm0_31:$mode), AddrModeNone, 4, IndexModeNone, BrFrm,
2144 NoItinerary, asm, "", []> {
2146 let Inst{31-28} = 0b1111;
2147 let Inst{27-25} = 0b100;
2151 let Inst{19-16} = 0b1101; // SP
2152 let Inst{15-5} = 0b00000101000;
2153 let Inst{4-0} = mode;
2156 def SRSDA : SRSI<0, "srsda\tsp, $mode"> {
2157 let Inst{24-23} = 0;
2159 def SRSDA_UPD : SRSI<1, "srsda\tsp!, $mode"> {
2160 let Inst{24-23} = 0;
2162 def SRSDB : SRSI<0, "srsdb\tsp, $mode"> {
2163 let Inst{24-23} = 0b10;
2165 def SRSDB_UPD : SRSI<1, "srsdb\tsp!, $mode"> {
2166 let Inst{24-23} = 0b10;
2168 def SRSIA : SRSI<0, "srsia\tsp, $mode"> {
2169 let Inst{24-23} = 0b01;
2171 def SRSIA_UPD : SRSI<1, "srsia\tsp!, $mode"> {
2172 let Inst{24-23} = 0b01;
2174 def SRSIB : SRSI<0, "srsib\tsp, $mode"> {
2175 let Inst{24-23} = 0b11;
2177 def SRSIB_UPD : SRSI<1, "srsib\tsp!, $mode"> {
2178 let Inst{24-23} = 0b11;
2181 def : ARMInstAlias<"srsda $mode", (SRSDA imm0_31:$mode)>;
2182 def : ARMInstAlias<"srsda $mode!", (SRSDA_UPD imm0_31:$mode)>;
2184 def : ARMInstAlias<"srsdb $mode", (SRSDB imm0_31:$mode)>;
2185 def : ARMInstAlias<"srsdb $mode!", (SRSDB_UPD imm0_31:$mode)>;
2187 def : ARMInstAlias<"srsia $mode", (SRSIA imm0_31:$mode)>;
2188 def : ARMInstAlias<"srsia $mode!", (SRSIA_UPD imm0_31:$mode)>;
2190 def : ARMInstAlias<"srsib $mode", (SRSIB imm0_31:$mode)>;
2191 def : ARMInstAlias<"srsib $mode!", (SRSIB_UPD imm0_31:$mode)>;
2193 // Return From Exception
2194 class RFEI<bit wb, string asm>
2195 : XI<(outs), (ins GPR:$Rn), AddrModeNone, 4, IndexModeNone, BrFrm,
2196 NoItinerary, asm, "", []> {
2198 let Inst{31-28} = 0b1111;
2199 let Inst{27-25} = 0b100;
2203 let Inst{19-16} = Rn;
2204 let Inst{15-0} = 0xa00;
2207 def RFEDA : RFEI<0, "rfeda\t$Rn"> {
2208 let Inst{24-23} = 0;
2210 def RFEDA_UPD : RFEI<1, "rfeda\t$Rn!"> {
2211 let Inst{24-23} = 0;
2213 def RFEDB : RFEI<0, "rfedb\t$Rn"> {
2214 let Inst{24-23} = 0b10;
2216 def RFEDB_UPD : RFEI<1, "rfedb\t$Rn!"> {
2217 let Inst{24-23} = 0b10;
2219 def RFEIA : RFEI<0, "rfeia\t$Rn"> {
2220 let Inst{24-23} = 0b01;
2222 def RFEIA_UPD : RFEI<1, "rfeia\t$Rn!"> {
2223 let Inst{24-23} = 0b01;
2225 def RFEIB : RFEI<0, "rfeib\t$Rn"> {
2226 let Inst{24-23} = 0b11;
2228 def RFEIB_UPD : RFEI<1, "rfeib\t$Rn!"> {
2229 let Inst{24-23} = 0b11;
2232 //===----------------------------------------------------------------------===//
2233 // Load / Store Instructions.
2239 defm LDR : AI_ldr1<0, "ldr", IIC_iLoad_r, IIC_iLoad_si,
2240 UnOpFrag<(load node:$Src)>>;
2241 defm LDRB : AI_ldr1nopc<1, "ldrb", IIC_iLoad_bh_r, IIC_iLoad_bh_si,
2242 UnOpFrag<(zextloadi8 node:$Src)>>;
2243 defm STR : AI_str1<0, "str", IIC_iStore_r, IIC_iStore_si,
2244 BinOpFrag<(store node:$LHS, node:$RHS)>>;
2245 defm STRB : AI_str1nopc<1, "strb", IIC_iStore_bh_r, IIC_iStore_bh_si,
2246 BinOpFrag<(truncstorei8 node:$LHS, node:$RHS)>>;
2248 // Special LDR for loads from non-pc-relative constpools.
2249 let canFoldAsLoad = 1, mayLoad = 1, neverHasSideEffects = 1,
2250 isReMaterializable = 1, isCodeGenOnly = 1 in
2251 def LDRcp : AI2ldst<0b010, 1, 0, (outs GPR:$Rt), (ins addrmode_imm12:$addr),
2252 AddrMode_i12, LdFrm, IIC_iLoad_r, "ldr", "\t$Rt, $addr",
2256 let Inst{23} = addr{12}; // U (add = ('U' == 1))
2257 let Inst{19-16} = 0b1111;
2258 let Inst{15-12} = Rt;
2259 let Inst{11-0} = addr{11-0}; // imm12
2262 // Loads with zero extension
2263 def LDRH : AI3ld<0b1011, 1, (outs GPR:$Rt), (ins addrmode3:$addr), LdMiscFrm,
2264 IIC_iLoad_bh_r, "ldrh", "\t$Rt, $addr",
2265 [(set GPR:$Rt, (zextloadi16 addrmode3:$addr))]>;
2267 // Loads with sign extension
2268 def LDRSH : AI3ld<0b1111, 1, (outs GPR:$Rt), (ins addrmode3:$addr), LdMiscFrm,
2269 IIC_iLoad_bh_r, "ldrsh", "\t$Rt, $addr",
2270 [(set GPR:$Rt, (sextloadi16 addrmode3:$addr))]>;
2272 def LDRSB : AI3ld<0b1101, 1, (outs GPR:$Rt), (ins addrmode3:$addr), LdMiscFrm,
2273 IIC_iLoad_bh_r, "ldrsb", "\t$Rt, $addr",
2274 [(set GPR:$Rt, (sextloadi8 addrmode3:$addr))]>;
2276 let mayLoad = 1, neverHasSideEffects = 1, hasExtraDefRegAllocReq = 1 in {
2278 def LDRD : AI3ld<0b1101, 0, (outs GPR:$Rd, GPR:$dst2),
2279 (ins addrmode3:$addr), LdMiscFrm,
2280 IIC_iLoad_d_r, "ldrd", "\t$Rd, $dst2, $addr",
2281 []>, Requires<[IsARM, HasV5TE]>;
2285 multiclass AI2_ldridx<bit isByte, string opc,
2286 InstrItinClass iii, InstrItinClass iir> {
2287 def _PRE_IMM : AI2ldstidx<1, isByte, 1, (outs GPR:$Rt, GPR:$Rn_wb),
2288 (ins addrmode_imm12_pre:$addr), IndexModePre, LdFrm, iii,
2289 opc, "\t$Rt, $addr!", "$addr.base = $Rn_wb", []> {
2292 let Inst{23} = addr{12};
2293 let Inst{19-16} = addr{16-13};
2294 let Inst{11-0} = addr{11-0};
2295 let DecoderMethod = "DecodeLDRPreImm";
2296 let AsmMatchConverter = "cvtLdWriteBackRegAddrModeImm12";
2299 def _PRE_REG : AI2ldstidx<1, isByte, 1, (outs GPR:$Rt, GPR:$Rn_wb),
2300 (ins ldst_so_reg:$addr), IndexModePre, LdFrm, iir,
2301 opc, "\t$Rt, $addr!", "$addr.base = $Rn_wb", []> {
2304 let Inst{23} = addr{12};
2305 let Inst{19-16} = addr{16-13};
2306 let Inst{11-0} = addr{11-0};
2308 let DecoderMethod = "DecodeLDRPreReg";
2309 let AsmMatchConverter = "cvtLdWriteBackRegAddrMode2";
2312 def _POST_REG : AI2ldstidx<1, isByte, 0, (outs GPR:$Rt, GPR:$Rn_wb),
2313 (ins addr_offset_none:$addr, am2offset_reg:$offset),
2314 IndexModePost, LdFrm, iir,
2315 opc, "\t$Rt, $addr, $offset",
2316 "$addr.base = $Rn_wb", []> {
2322 let Inst{23} = offset{12};
2323 let Inst{19-16} = addr;
2324 let Inst{11-0} = offset{11-0};
2327 let DecoderMethod = "DecodeAddrMode2IdxInstruction";
2330 def _POST_IMM : AI2ldstidx<1, isByte, 0, (outs GPR:$Rt, GPR:$Rn_wb),
2331 (ins addr_offset_none:$addr, am2offset_imm:$offset),
2332 IndexModePost, LdFrm, iii,
2333 opc, "\t$Rt, $addr, $offset",
2334 "$addr.base = $Rn_wb", []> {
2340 let Inst{23} = offset{12};
2341 let Inst{19-16} = addr;
2342 let Inst{11-0} = offset{11-0};
2344 let DecoderMethod = "DecodeAddrMode2IdxInstruction";
2349 let mayLoad = 1, neverHasSideEffects = 1 in {
2350 // FIXME: for LDR_PRE_REG etc. the itineray should be either IIC_iLoad_ru or
2351 // IIC_iLoad_siu depending on whether it the offset register is shifted.
2352 defm LDR : AI2_ldridx<0, "ldr", IIC_iLoad_iu, IIC_iLoad_ru>;
2353 defm LDRB : AI2_ldridx<1, "ldrb", IIC_iLoad_bh_iu, IIC_iLoad_bh_ru>;
2356 multiclass AI3_ldridx<bits<4> op, string opc, InstrItinClass itin> {
2357 def _PRE : AI3ldstidx<op, 1, 1, (outs GPR:$Rt, GPR:$Rn_wb),
2358 (ins addrmode3_pre:$addr), IndexModePre,
2360 opc, "\t$Rt, $addr!", "$addr.base = $Rn_wb", []> {
2362 let Inst{23} = addr{8}; // U bit
2363 let Inst{22} = addr{13}; // 1 == imm8, 0 == Rm
2364 let Inst{19-16} = addr{12-9}; // Rn
2365 let Inst{11-8} = addr{7-4}; // imm7_4/zero
2366 let Inst{3-0} = addr{3-0}; // imm3_0/Rm
2367 let AsmMatchConverter = "cvtLdWriteBackRegAddrMode3";
2368 let DecoderMethod = "DecodeAddrMode3Instruction";
2370 def _POST : AI3ldstidx<op, 1, 0, (outs GPR:$Rt, GPR:$Rn_wb),
2371 (ins addr_offset_none:$addr, am3offset:$offset),
2372 IndexModePost, LdMiscFrm, itin,
2373 opc, "\t$Rt, $addr, $offset", "$addr.base = $Rn_wb",
2377 let Inst{23} = offset{8}; // U bit
2378 let Inst{22} = offset{9}; // 1 == imm8, 0 == Rm
2379 let Inst{19-16} = addr;
2380 let Inst{11-8} = offset{7-4}; // imm7_4/zero
2381 let Inst{3-0} = offset{3-0}; // imm3_0/Rm
2382 let DecoderMethod = "DecodeAddrMode3Instruction";
2386 let mayLoad = 1, neverHasSideEffects = 1 in {
2387 defm LDRH : AI3_ldridx<0b1011, "ldrh", IIC_iLoad_bh_ru>;
2388 defm LDRSH : AI3_ldridx<0b1111, "ldrsh", IIC_iLoad_bh_ru>;
2389 defm LDRSB : AI3_ldridx<0b1101, "ldrsb", IIC_iLoad_bh_ru>;
2390 let hasExtraDefRegAllocReq = 1 in {
2391 def LDRD_PRE : AI3ldstidx<0b1101, 0, 1, (outs GPR:$Rt, GPR:$Rt2, GPR:$Rn_wb),
2392 (ins addrmode3_pre:$addr), IndexModePre,
2393 LdMiscFrm, IIC_iLoad_d_ru,
2394 "ldrd", "\t$Rt, $Rt2, $addr!",
2395 "$addr.base = $Rn_wb", []> {
2397 let Inst{23} = addr{8}; // U bit
2398 let Inst{22} = addr{13}; // 1 == imm8, 0 == Rm
2399 let Inst{19-16} = addr{12-9}; // Rn
2400 let Inst{11-8} = addr{7-4}; // imm7_4/zero
2401 let Inst{3-0} = addr{3-0}; // imm3_0/Rm
2402 let DecoderMethod = "DecodeAddrMode3Instruction";
2403 let AsmMatchConverter = "cvtLdrdPre";
2405 def LDRD_POST: AI3ldstidx<0b1101, 0, 0, (outs GPR:$Rt, GPR:$Rt2, GPR:$Rn_wb),
2406 (ins addr_offset_none:$addr, am3offset:$offset),
2407 IndexModePost, LdMiscFrm, IIC_iLoad_d_ru,
2408 "ldrd", "\t$Rt, $Rt2, $addr, $offset",
2409 "$addr.base = $Rn_wb", []> {
2412 let Inst{23} = offset{8}; // U bit
2413 let Inst{22} = offset{9}; // 1 == imm8, 0 == Rm
2414 let Inst{19-16} = addr;
2415 let Inst{11-8} = offset{7-4}; // imm7_4/zero
2416 let Inst{3-0} = offset{3-0}; // imm3_0/Rm
2417 let DecoderMethod = "DecodeAddrMode3Instruction";
2419 } // hasExtraDefRegAllocReq = 1
2420 } // mayLoad = 1, neverHasSideEffects = 1
2422 // LDRT, LDRBT, LDRSBT, LDRHT, LDRSHT.
2423 let mayLoad = 1, neverHasSideEffects = 1 in {
2424 def LDRT_POST_REG : AI2ldstidx<1, 0, 0, (outs GPR:$Rt, GPR:$Rn_wb),
2425 (ins addr_offset_none:$addr, am2offset_reg:$offset),
2426 IndexModePost, LdFrm, IIC_iLoad_ru,
2427 "ldrt", "\t$Rt, $addr, $offset",
2428 "$addr.base = $Rn_wb", []> {
2434 let Inst{23} = offset{12};
2435 let Inst{21} = 1; // overwrite
2436 let Inst{19-16} = addr;
2437 let Inst{11-5} = offset{11-5};
2439 let Inst{3-0} = offset{3-0};
2440 let DecoderMethod = "DecodeAddrMode2IdxInstruction";
2443 def LDRT_POST_IMM : AI2ldstidx<1, 0, 0, (outs GPR:$Rt, GPR:$Rn_wb),
2444 (ins addr_offset_none:$addr, am2offset_imm:$offset),
2445 IndexModePost, LdFrm, IIC_iLoad_ru,
2446 "ldrt", "\t$Rt, $addr, $offset",
2447 "$addr.base = $Rn_wb", []> {
2453 let Inst{23} = offset{12};
2454 let Inst{21} = 1; // overwrite
2455 let Inst{19-16} = addr;
2456 let Inst{11-0} = offset{11-0};
2457 let DecoderMethod = "DecodeAddrMode2IdxInstruction";
2460 def LDRBT_POST_REG : AI2ldstidx<1, 1, 0, (outs GPR:$Rt, GPR:$Rn_wb),
2461 (ins addr_offset_none:$addr, am2offset_reg:$offset),
2462 IndexModePost, LdFrm, IIC_iLoad_bh_ru,
2463 "ldrbt", "\t$Rt, $addr, $offset",
2464 "$addr.base = $Rn_wb", []> {
2470 let Inst{23} = offset{12};
2471 let Inst{21} = 1; // overwrite
2472 let Inst{19-16} = addr;
2473 let Inst{11-5} = offset{11-5};
2475 let Inst{3-0} = offset{3-0};
2476 let DecoderMethod = "DecodeAddrMode2IdxInstruction";
2479 def LDRBT_POST_IMM : AI2ldstidx<1, 1, 0, (outs GPR:$Rt, GPR:$Rn_wb),
2480 (ins addr_offset_none:$addr, am2offset_imm:$offset),
2481 IndexModePost, LdFrm, IIC_iLoad_bh_ru,
2482 "ldrbt", "\t$Rt, $addr, $offset",
2483 "$addr.base = $Rn_wb", []> {
2489 let Inst{23} = offset{12};
2490 let Inst{21} = 1; // overwrite
2491 let Inst{19-16} = addr;
2492 let Inst{11-0} = offset{11-0};
2493 let DecoderMethod = "DecodeAddrMode2IdxInstruction";
2496 multiclass AI3ldrT<bits<4> op, string opc> {
2497 def i : AI3ldstidxT<op, 1, (outs GPR:$Rt, GPR:$base_wb),
2498 (ins addr_offset_none:$addr, postidx_imm8:$offset),
2499 IndexModePost, LdMiscFrm, IIC_iLoad_bh_ru, opc,
2500 "\t$Rt, $addr, $offset", "$addr.base = $base_wb", []> {
2502 let Inst{23} = offset{8};
2504 let Inst{11-8} = offset{7-4};
2505 let Inst{3-0} = offset{3-0};
2506 let AsmMatchConverter = "cvtLdExtTWriteBackImm";
2508 def r : AI3ldstidxT<op, 1, (outs GPRnopc:$Rt, GPRnopc:$base_wb),
2509 (ins addr_offset_none:$addr, postidx_reg:$Rm),
2510 IndexModePost, LdMiscFrm, IIC_iLoad_bh_ru, opc,
2511 "\t$Rt, $addr, $Rm", "$addr.base = $base_wb", []> {
2513 let Inst{23} = Rm{4};
2516 let Unpredictable{11-8} = 0b1111;
2517 let Inst{3-0} = Rm{3-0};
2518 let AsmMatchConverter = "cvtLdExtTWriteBackReg";
2519 let DecoderMethod = "DecodeLDR";
2523 defm LDRSBT : AI3ldrT<0b1101, "ldrsbt">;
2524 defm LDRHT : AI3ldrT<0b1011, "ldrht">;
2525 defm LDRSHT : AI3ldrT<0b1111, "ldrsht">;
2530 // Stores with truncate
2531 def STRH : AI3str<0b1011, (outs), (ins GPR:$Rt, addrmode3:$addr), StMiscFrm,
2532 IIC_iStore_bh_r, "strh", "\t$Rt, $addr",
2533 [(truncstorei16 GPR:$Rt, addrmode3:$addr)]>;
2536 let mayStore = 1, neverHasSideEffects = 1, hasExtraSrcRegAllocReq = 1 in
2537 def STRD : AI3str<0b1111, (outs), (ins GPR:$Rt, GPR:$src2, addrmode3:$addr),
2538 StMiscFrm, IIC_iStore_d_r,
2539 "strd", "\t$Rt, $src2, $addr", []>,
2540 Requires<[IsARM, HasV5TE]> {
2545 multiclass AI2_stridx<bit isByte, string opc,
2546 InstrItinClass iii, InstrItinClass iir> {
2547 def _PRE_IMM : AI2ldstidx<0, isByte, 1, (outs GPR:$Rn_wb),
2548 (ins GPR:$Rt, addrmode_imm12_pre:$addr), IndexModePre,
2550 opc, "\t$Rt, $addr!", "$addr.base = $Rn_wb", []> {
2553 let Inst{23} = addr{12}; // U (add = ('U' == 1))
2554 let Inst{19-16} = addr{16-13}; // Rn
2555 let Inst{11-0} = addr{11-0}; // imm12
2556 let AsmMatchConverter = "cvtStWriteBackRegAddrModeImm12";
2557 let DecoderMethod = "DecodeSTRPreImm";
2560 def _PRE_REG : AI2ldstidx<0, isByte, 1, (outs GPR:$Rn_wb),
2561 (ins GPR:$Rt, ldst_so_reg:$addr),
2562 IndexModePre, StFrm, iir,
2563 opc, "\t$Rt, $addr!", "$addr.base = $Rn_wb", []> {
2566 let Inst{23} = addr{12}; // U (add = ('U' == 1))
2567 let Inst{19-16} = addr{16-13}; // Rn
2568 let Inst{11-0} = addr{11-0};
2569 let Inst{4} = 0; // Inst{4} = 0
2570 let AsmMatchConverter = "cvtStWriteBackRegAddrMode2";
2571 let DecoderMethod = "DecodeSTRPreReg";
2573 def _POST_REG : AI2ldstidx<0, isByte, 0, (outs GPR:$Rn_wb),
2574 (ins GPR:$Rt, addr_offset_none:$addr, am2offset_reg:$offset),
2575 IndexModePost, StFrm, iir,
2576 opc, "\t$Rt, $addr, $offset",
2577 "$addr.base = $Rn_wb", []> {
2583 let Inst{23} = offset{12};
2584 let Inst{19-16} = addr;
2585 let Inst{11-0} = offset{11-0};
2588 let DecoderMethod = "DecodeAddrMode2IdxInstruction";
2591 def _POST_IMM : AI2ldstidx<0, isByte, 0, (outs GPR:$Rn_wb),
2592 (ins GPR:$Rt, addr_offset_none:$addr, am2offset_imm:$offset),
2593 IndexModePost, StFrm, iii,
2594 opc, "\t$Rt, $addr, $offset",
2595 "$addr.base = $Rn_wb", []> {
2601 let Inst{23} = offset{12};
2602 let Inst{19-16} = addr;
2603 let Inst{11-0} = offset{11-0};
2605 let DecoderMethod = "DecodeAddrMode2IdxInstruction";
2609 let mayStore = 1, neverHasSideEffects = 1 in {
2610 // FIXME: for STR_PRE_REG etc. the itineray should be either IIC_iStore_ru or
2611 // IIC_iStore_siu depending on whether it the offset register is shifted.
2612 defm STR : AI2_stridx<0, "str", IIC_iStore_iu, IIC_iStore_ru>;
2613 defm STRB : AI2_stridx<1, "strb", IIC_iStore_bh_iu, IIC_iStore_bh_ru>;
2616 def : ARMPat<(post_store GPR:$Rt, addr_offset_none:$addr,
2617 am2offset_reg:$offset),
2618 (STR_POST_REG GPR:$Rt, addr_offset_none:$addr,
2619 am2offset_reg:$offset)>;
2620 def : ARMPat<(post_store GPR:$Rt, addr_offset_none:$addr,
2621 am2offset_imm:$offset),
2622 (STR_POST_IMM GPR:$Rt, addr_offset_none:$addr,
2623 am2offset_imm:$offset)>;
2624 def : ARMPat<(post_truncsti8 GPR:$Rt, addr_offset_none:$addr,
2625 am2offset_reg:$offset),
2626 (STRB_POST_REG GPR:$Rt, addr_offset_none:$addr,
2627 am2offset_reg:$offset)>;
2628 def : ARMPat<(post_truncsti8 GPR:$Rt, addr_offset_none:$addr,
2629 am2offset_imm:$offset),
2630 (STRB_POST_IMM GPR:$Rt, addr_offset_none:$addr,
2631 am2offset_imm:$offset)>;
2633 // Pseudo-instructions for pattern matching the pre-indexed stores. We can't
2634 // put the patterns on the instruction definitions directly as ISel wants
2635 // the address base and offset to be separate operands, not a single
2636 // complex operand like we represent the instructions themselves. The
2637 // pseudos map between the two.
2638 let usesCustomInserter = 1,
2639 Constraints = "$Rn = $Rn_wb,@earlyclobber $Rn_wb" in {
2640 def STRi_preidx: ARMPseudoInst<(outs GPR:$Rn_wb),
2641 (ins GPR:$Rt, GPR:$Rn, am2offset_imm:$offset, pred:$p),
2644 (pre_store GPR:$Rt, GPR:$Rn, am2offset_imm:$offset))]>;
2645 def STRr_preidx: ARMPseudoInst<(outs GPR:$Rn_wb),
2646 (ins GPR:$Rt, GPR:$Rn, am2offset_reg:$offset, pred:$p),
2649 (pre_store GPR:$Rt, GPR:$Rn, am2offset_reg:$offset))]>;
2650 def STRBi_preidx: ARMPseudoInst<(outs GPR:$Rn_wb),
2651 (ins GPR:$Rt, GPR:$Rn, am2offset_imm:$offset, pred:$p),
2654 (pre_truncsti8 GPR:$Rt, GPR:$Rn, am2offset_imm:$offset))]>;
2655 def STRBr_preidx: ARMPseudoInst<(outs GPR:$Rn_wb),
2656 (ins GPR:$Rt, GPR:$Rn, am2offset_reg:$offset, pred:$p),
2659 (pre_truncsti8 GPR:$Rt, GPR:$Rn, am2offset_reg:$offset))]>;
2660 def STRH_preidx: ARMPseudoInst<(outs GPR:$Rn_wb),
2661 (ins GPR:$Rt, GPR:$Rn, am3offset:$offset, pred:$p),
2664 (pre_truncsti16 GPR:$Rt, GPR:$Rn, am3offset:$offset))]>;
2669 def STRH_PRE : AI3ldstidx<0b1011, 0, 1, (outs GPR:$Rn_wb),
2670 (ins GPR:$Rt, addrmode3_pre:$addr), IndexModePre,
2671 StMiscFrm, IIC_iStore_bh_ru,
2672 "strh", "\t$Rt, $addr!", "$addr.base = $Rn_wb", []> {
2674 let Inst{23} = addr{8}; // U bit
2675 let Inst{22} = addr{13}; // 1 == imm8, 0 == Rm
2676 let Inst{19-16} = addr{12-9}; // Rn
2677 let Inst{11-8} = addr{7-4}; // imm7_4/zero
2678 let Inst{3-0} = addr{3-0}; // imm3_0/Rm
2679 let AsmMatchConverter = "cvtStWriteBackRegAddrMode3";
2680 let DecoderMethod = "DecodeAddrMode3Instruction";
2683 def STRH_POST : AI3ldstidx<0b1011, 0, 0, (outs GPR:$Rn_wb),
2684 (ins GPR:$Rt, addr_offset_none:$addr, am3offset:$offset),
2685 IndexModePost, StMiscFrm, IIC_iStore_bh_ru,
2686 "strh", "\t$Rt, $addr, $offset", "$addr.base = $Rn_wb",
2687 [(set GPR:$Rn_wb, (post_truncsti16 GPR:$Rt,
2688 addr_offset_none:$addr,
2689 am3offset:$offset))]> {
2692 let Inst{23} = offset{8}; // U bit
2693 let Inst{22} = offset{9}; // 1 == imm8, 0 == Rm
2694 let Inst{19-16} = addr;
2695 let Inst{11-8} = offset{7-4}; // imm7_4/zero
2696 let Inst{3-0} = offset{3-0}; // imm3_0/Rm
2697 let DecoderMethod = "DecodeAddrMode3Instruction";
2700 let mayStore = 1, neverHasSideEffects = 1, hasExtraSrcRegAllocReq = 1 in {
2701 def STRD_PRE : AI3ldstidx<0b1111, 0, 1, (outs GPR:$Rn_wb),
2702 (ins GPR:$Rt, GPR:$Rt2, addrmode3_pre:$addr),
2703 IndexModePre, StMiscFrm, IIC_iStore_d_ru,
2704 "strd", "\t$Rt, $Rt2, $addr!",
2705 "$addr.base = $Rn_wb", []> {
2707 let Inst{23} = addr{8}; // U bit
2708 let Inst{22} = addr{13}; // 1 == imm8, 0 == Rm
2709 let Inst{19-16} = addr{12-9}; // Rn
2710 let Inst{11-8} = addr{7-4}; // imm7_4/zero
2711 let Inst{3-0} = addr{3-0}; // imm3_0/Rm
2712 let DecoderMethod = "DecodeAddrMode3Instruction";
2713 let AsmMatchConverter = "cvtStrdPre";
2716 def STRD_POST: AI3ldstidx<0b1111, 0, 0, (outs GPR:$Rn_wb),
2717 (ins GPR:$Rt, GPR:$Rt2, addr_offset_none:$addr,
2719 IndexModePost, StMiscFrm, IIC_iStore_d_ru,
2720 "strd", "\t$Rt, $Rt2, $addr, $offset",
2721 "$addr.base = $Rn_wb", []> {
2724 let Inst{23} = offset{8}; // U bit
2725 let Inst{22} = offset{9}; // 1 == imm8, 0 == Rm
2726 let Inst{19-16} = addr;
2727 let Inst{11-8} = offset{7-4}; // imm7_4/zero
2728 let Inst{3-0} = offset{3-0}; // imm3_0/Rm
2729 let DecoderMethod = "DecodeAddrMode3Instruction";
2731 } // mayStore = 1, neverHasSideEffects = 1, hasExtraSrcRegAllocReq = 1
2733 // STRT, STRBT, and STRHT
2735 def STRBT_POST_REG : AI2ldstidx<0, 1, 0, (outs GPR:$Rn_wb),
2736 (ins GPR:$Rt, addr_offset_none:$addr, am2offset_reg:$offset),
2737 IndexModePost, StFrm, IIC_iStore_bh_ru,
2738 "strbt", "\t$Rt, $addr, $offset",
2739 "$addr.base = $Rn_wb", []> {
2745 let Inst{23} = offset{12};
2746 let Inst{21} = 1; // overwrite
2747 let Inst{19-16} = addr;
2748 let Inst{11-5} = offset{11-5};
2750 let Inst{3-0} = offset{3-0};
2751 let DecoderMethod = "DecodeAddrMode2IdxInstruction";
2754 def STRBT_POST_IMM : AI2ldstidx<0, 1, 0, (outs GPR:$Rn_wb),
2755 (ins GPR:$Rt, addr_offset_none:$addr, am2offset_imm:$offset),
2756 IndexModePost, StFrm, IIC_iStore_bh_ru,
2757 "strbt", "\t$Rt, $addr, $offset",
2758 "$addr.base = $Rn_wb", []> {
2764 let Inst{23} = offset{12};
2765 let Inst{21} = 1; // overwrite
2766 let Inst{19-16} = addr;
2767 let Inst{11-0} = offset{11-0};
2768 let DecoderMethod = "DecodeAddrMode2IdxInstruction";
2771 let mayStore = 1, neverHasSideEffects = 1 in {
2772 def STRT_POST_REG : AI2ldstidx<0, 0, 0, (outs GPR:$Rn_wb),
2773 (ins GPR:$Rt, addr_offset_none:$addr, am2offset_reg:$offset),
2774 IndexModePost, StFrm, IIC_iStore_ru,
2775 "strt", "\t$Rt, $addr, $offset",
2776 "$addr.base = $Rn_wb", []> {
2782 let Inst{23} = offset{12};
2783 let Inst{21} = 1; // overwrite
2784 let Inst{19-16} = addr;
2785 let Inst{11-5} = offset{11-5};
2787 let Inst{3-0} = offset{3-0};
2788 let DecoderMethod = "DecodeAddrMode2IdxInstruction";
2791 def STRT_POST_IMM : AI2ldstidx<0, 0, 0, (outs GPR:$Rn_wb),
2792 (ins GPR:$Rt, addr_offset_none:$addr, am2offset_imm:$offset),
2793 IndexModePost, StFrm, IIC_iStore_ru,
2794 "strt", "\t$Rt, $addr, $offset",
2795 "$addr.base = $Rn_wb", []> {
2801 let Inst{23} = offset{12};
2802 let Inst{21} = 1; // overwrite
2803 let Inst{19-16} = addr;
2804 let Inst{11-0} = offset{11-0};
2805 let DecoderMethod = "DecodeAddrMode2IdxInstruction";
2810 multiclass AI3strT<bits<4> op, string opc> {
2811 def i : AI3ldstidxT<op, 0, (outs GPR:$base_wb),
2812 (ins GPR:$Rt, addr_offset_none:$addr, postidx_imm8:$offset),
2813 IndexModePost, StMiscFrm, IIC_iStore_bh_ru, opc,
2814 "\t$Rt, $addr, $offset", "$addr.base = $base_wb", []> {
2816 let Inst{23} = offset{8};
2818 let Inst{11-8} = offset{7-4};
2819 let Inst{3-0} = offset{3-0};
2820 let AsmMatchConverter = "cvtStExtTWriteBackImm";
2822 def r : AI3ldstidxT<op, 0, (outs GPR:$base_wb),
2823 (ins GPR:$Rt, addr_offset_none:$addr, postidx_reg:$Rm),
2824 IndexModePost, StMiscFrm, IIC_iStore_bh_ru, opc,
2825 "\t$Rt, $addr, $Rm", "$addr.base = $base_wb", []> {
2827 let Inst{23} = Rm{4};
2830 let Inst{3-0} = Rm{3-0};
2831 let AsmMatchConverter = "cvtStExtTWriteBackReg";
2836 defm STRHT : AI3strT<0b1011, "strht">;
2839 //===----------------------------------------------------------------------===//
2840 // Load / store multiple Instructions.
2843 multiclass arm_ldst_mult<string asm, string sfx, bit L_bit, bit P_bit, Format f,
2844 InstrItinClass itin, InstrItinClass itin_upd> {
2845 // IA is the default, so no need for an explicit suffix on the
2846 // mnemonic here. Without it is the canonical spelling.
2848 AXI4<(outs), (ins GPR:$Rn, pred:$p, reglist:$regs, variable_ops),
2849 IndexModeNone, f, itin,
2850 !strconcat(asm, "${p}\t$Rn, $regs", sfx), "", []> {
2851 let Inst{24-23} = 0b01; // Increment After
2852 let Inst{22} = P_bit;
2853 let Inst{21} = 0; // No writeback
2854 let Inst{20} = L_bit;
2857 AXI4<(outs GPR:$wb), (ins GPR:$Rn, pred:$p, reglist:$regs, variable_ops),
2858 IndexModeUpd, f, itin_upd,
2859 !strconcat(asm, "${p}\t$Rn!, $regs", sfx), "$Rn = $wb", []> {
2860 let Inst{24-23} = 0b01; // Increment After
2861 let Inst{22} = P_bit;
2862 let Inst{21} = 1; // Writeback
2863 let Inst{20} = L_bit;
2865 let DecoderMethod = "DecodeMemMultipleWritebackInstruction";
2868 AXI4<(outs), (ins GPR:$Rn, pred:$p, reglist:$regs, variable_ops),
2869 IndexModeNone, f, itin,
2870 !strconcat(asm, "da${p}\t$Rn, $regs", sfx), "", []> {
2871 let Inst{24-23} = 0b00; // Decrement After
2872 let Inst{22} = P_bit;
2873 let Inst{21} = 0; // No writeback
2874 let Inst{20} = L_bit;
2877 AXI4<(outs GPR:$wb), (ins GPR:$Rn, pred:$p, reglist:$regs, variable_ops),
2878 IndexModeUpd, f, itin_upd,
2879 !strconcat(asm, "da${p}\t$Rn!, $regs", sfx), "$Rn = $wb", []> {
2880 let Inst{24-23} = 0b00; // Decrement After
2881 let Inst{22} = P_bit;
2882 let Inst{21} = 1; // Writeback
2883 let Inst{20} = L_bit;
2885 let DecoderMethod = "DecodeMemMultipleWritebackInstruction";
2888 AXI4<(outs), (ins GPR:$Rn, pred:$p, reglist:$regs, variable_ops),
2889 IndexModeNone, f, itin,
2890 !strconcat(asm, "db${p}\t$Rn, $regs", sfx), "", []> {
2891 let Inst{24-23} = 0b10; // Decrement Before
2892 let Inst{22} = P_bit;
2893 let Inst{21} = 0; // No writeback
2894 let Inst{20} = L_bit;
2897 AXI4<(outs GPR:$wb), (ins GPR:$Rn, pred:$p, reglist:$regs, variable_ops),
2898 IndexModeUpd, f, itin_upd,
2899 !strconcat(asm, "db${p}\t$Rn!, $regs", sfx), "$Rn = $wb", []> {
2900 let Inst{24-23} = 0b10; // Decrement Before
2901 let Inst{22} = P_bit;
2902 let Inst{21} = 1; // Writeback
2903 let Inst{20} = L_bit;
2905 let DecoderMethod = "DecodeMemMultipleWritebackInstruction";
2908 AXI4<(outs), (ins GPR:$Rn, pred:$p, reglist:$regs, variable_ops),
2909 IndexModeNone, f, itin,
2910 !strconcat(asm, "ib${p}\t$Rn, $regs", sfx), "", []> {
2911 let Inst{24-23} = 0b11; // Increment Before
2912 let Inst{22} = P_bit;
2913 let Inst{21} = 0; // No writeback
2914 let Inst{20} = L_bit;
2917 AXI4<(outs GPR:$wb), (ins GPR:$Rn, pred:$p, reglist:$regs, variable_ops),
2918 IndexModeUpd, f, itin_upd,
2919 !strconcat(asm, "ib${p}\t$Rn!, $regs", sfx), "$Rn = $wb", []> {
2920 let Inst{24-23} = 0b11; // Increment Before
2921 let Inst{22} = P_bit;
2922 let Inst{21} = 1; // Writeback
2923 let Inst{20} = L_bit;
2925 let DecoderMethod = "DecodeMemMultipleWritebackInstruction";
2929 let neverHasSideEffects = 1 in {
2931 let mayLoad = 1, hasExtraDefRegAllocReq = 1 in
2932 defm LDM : arm_ldst_mult<"ldm", "", 1, 0, LdStMulFrm, IIC_iLoad_m,
2935 let mayStore = 1, hasExtraSrcRegAllocReq = 1 in
2936 defm STM : arm_ldst_mult<"stm", "", 0, 0, LdStMulFrm, IIC_iStore_m,
2939 } // neverHasSideEffects
2941 // FIXME: remove when we have a way to marking a MI with these properties.
2942 // FIXME: Should pc be an implicit operand like PICADD, etc?
2943 let isReturn = 1, isTerminator = 1, isBarrier = 1, mayLoad = 1,
2944 hasExtraDefRegAllocReq = 1, isCodeGenOnly = 1 in
2945 def LDMIA_RET : ARMPseudoExpand<(outs GPR:$wb), (ins GPR:$Rn, pred:$p,
2946 reglist:$regs, variable_ops),
2947 4, IIC_iLoad_mBr, [],
2948 (LDMIA_UPD GPR:$wb, GPR:$Rn, pred:$p, reglist:$regs)>,
2949 RegConstraint<"$Rn = $wb">;
2951 let mayLoad = 1, hasExtraDefRegAllocReq = 1 in
2952 defm sysLDM : arm_ldst_mult<"ldm", " ^", 1, 1, LdStMulFrm, IIC_iLoad_m,
2955 let mayStore = 1, hasExtraSrcRegAllocReq = 1 in
2956 defm sysSTM : arm_ldst_mult<"stm", " ^", 0, 1, LdStMulFrm, IIC_iStore_m,
2961 //===----------------------------------------------------------------------===//
2962 // Move Instructions.
2965 let neverHasSideEffects = 1 in
2966 def MOVr : AsI1<0b1101, (outs GPR:$Rd), (ins GPR:$Rm), DPFrm, IIC_iMOVr,
2967 "mov", "\t$Rd, $Rm", []>, UnaryDP, Sched<[WriteALU]> {
2971 let Inst{19-16} = 0b0000;
2972 let Inst{11-4} = 0b00000000;
2975 let Inst{15-12} = Rd;
2978 // A version for the smaller set of tail call registers.
2979 let neverHasSideEffects = 1 in
2980 def MOVr_TC : AsI1<0b1101, (outs tcGPR:$Rd), (ins tcGPR:$Rm), DPFrm,
2981 IIC_iMOVr, "mov", "\t$Rd, $Rm", []>, UnaryDP, Sched<[WriteALU]> {
2985 let Inst{11-4} = 0b00000000;
2988 let Inst{15-12} = Rd;
2991 def MOVsr : AsI1<0b1101, (outs GPRnopc:$Rd), (ins shift_so_reg_reg:$src),
2992 DPSoRegRegFrm, IIC_iMOVsr,
2993 "mov", "\t$Rd, $src",
2994 [(set GPRnopc:$Rd, shift_so_reg_reg:$src)]>, UnaryDP,
2998 let Inst{15-12} = Rd;
2999 let Inst{19-16} = 0b0000;
3000 let Inst{11-8} = src{11-8};
3002 let Inst{6-5} = src{6-5};
3004 let Inst{3-0} = src{3-0};
3008 def MOVsi : AsI1<0b1101, (outs GPR:$Rd), (ins shift_so_reg_imm:$src),
3009 DPSoRegImmFrm, IIC_iMOVsr,
3010 "mov", "\t$Rd, $src", [(set GPR:$Rd, shift_so_reg_imm:$src)]>,
3011 UnaryDP, Sched<[WriteALU]> {
3014 let Inst{15-12} = Rd;
3015 let Inst{19-16} = 0b0000;
3016 let Inst{11-5} = src{11-5};
3018 let Inst{3-0} = src{3-0};
3022 let isReMaterializable = 1, isAsCheapAsAMove = 1, isMoveImm = 1 in
3023 def MOVi : AsI1<0b1101, (outs GPR:$Rd), (ins so_imm:$imm), DPFrm, IIC_iMOVi,
3024 "mov", "\t$Rd, $imm", [(set GPR:$Rd, so_imm:$imm)]>, UnaryDP,
3029 let Inst{15-12} = Rd;
3030 let Inst{19-16} = 0b0000;
3031 let Inst{11-0} = imm;
3034 let isReMaterializable = 1, isAsCheapAsAMove = 1, isMoveImm = 1 in
3035 def MOVi16 : AI1<0b1000, (outs GPR:$Rd), (ins imm0_65535_expr:$imm),
3037 "movw", "\t$Rd, $imm",
3038 [(set GPR:$Rd, imm0_65535:$imm)]>,
3039 Requires<[IsARM, HasV6T2]>, UnaryDP, Sched<[WriteALU]> {
3042 let Inst{15-12} = Rd;
3043 let Inst{11-0} = imm{11-0};
3044 let Inst{19-16} = imm{15-12};
3047 let DecoderMethod = "DecodeArmMOVTWInstruction";
3050 def : InstAlias<"mov${p} $Rd, $imm",
3051 (MOVi16 GPR:$Rd, imm0_65535_expr:$imm, pred:$p)>,
3054 def MOVi16_ga_pcrel : PseudoInst<(outs GPR:$Rd),
3055 (ins i32imm:$addr, pclabel:$id), IIC_iMOVi, []>,
3058 let Constraints = "$src = $Rd" in {
3059 def MOVTi16 : AI1<0b1010, (outs GPRnopc:$Rd),
3060 (ins GPR:$src, imm0_65535_expr:$imm),
3062 "movt", "\t$Rd, $imm",
3064 (or (and GPR:$src, 0xffff),
3065 lo16AllZero:$imm))]>, UnaryDP,
3066 Requires<[IsARM, HasV6T2]>, Sched<[WriteALU]> {
3069 let Inst{15-12} = Rd;
3070 let Inst{11-0} = imm{11-0};
3071 let Inst{19-16} = imm{15-12};
3074 let DecoderMethod = "DecodeArmMOVTWInstruction";
3077 def MOVTi16_ga_pcrel : PseudoInst<(outs GPR:$Rd),
3078 (ins GPR:$src, i32imm:$addr, pclabel:$id), IIC_iMOVi, []>,
3083 def : ARMPat<(or GPR:$src, 0xffff0000), (MOVTi16 GPR:$src, 0xffff)>,
3084 Requires<[IsARM, HasV6T2]>;
3086 let Uses = [CPSR] in
3087 def RRX: PseudoInst<(outs GPR:$Rd), (ins GPR:$Rm), IIC_iMOVsi,
3088 [(set GPR:$Rd, (ARMrrx GPR:$Rm))]>, UnaryDP,
3089 Requires<[IsARM]>, Sched<[WriteALU]>;
3091 // These aren't really mov instructions, but we have to define them this way
3092 // due to flag operands.
3094 let Defs = [CPSR] in {
3095 def MOVsrl_flag : PseudoInst<(outs GPR:$dst), (ins GPR:$src), IIC_iMOVsi,
3096 [(set GPR:$dst, (ARMsrl_flag GPR:$src))]>, UnaryDP,
3097 Sched<[WriteALU]>, Requires<[IsARM]>;
3098 def MOVsra_flag : PseudoInst<(outs GPR:$dst), (ins GPR:$src), IIC_iMOVsi,
3099 [(set GPR:$dst, (ARMsra_flag GPR:$src))]>, UnaryDP,
3100 Sched<[WriteALU]>, Requires<[IsARM]>;
3103 //===----------------------------------------------------------------------===//
3104 // Extend Instructions.
3109 def SXTB : AI_ext_rrot<0b01101010,
3110 "sxtb", UnOpFrag<(sext_inreg node:$Src, i8)>>;
3111 def SXTH : AI_ext_rrot<0b01101011,
3112 "sxth", UnOpFrag<(sext_inreg node:$Src, i16)>>;
3114 def SXTAB : AI_exta_rrot<0b01101010,
3115 "sxtab", BinOpFrag<(add node:$LHS, (sext_inreg node:$RHS, i8))>>;
3116 def SXTAH : AI_exta_rrot<0b01101011,
3117 "sxtah", BinOpFrag<(add node:$LHS, (sext_inreg node:$RHS,i16))>>;
3119 def SXTB16 : AI_ext_rrot_np<0b01101000, "sxtb16">;
3121 def SXTAB16 : AI_exta_rrot_np<0b01101000, "sxtab16">;
3125 let AddedComplexity = 16 in {
3126 def UXTB : AI_ext_rrot<0b01101110,
3127 "uxtb" , UnOpFrag<(and node:$Src, 0x000000FF)>>;
3128 def UXTH : AI_ext_rrot<0b01101111,
3129 "uxth" , UnOpFrag<(and node:$Src, 0x0000FFFF)>>;
3130 def UXTB16 : AI_ext_rrot<0b01101100,
3131 "uxtb16", UnOpFrag<(and node:$Src, 0x00FF00FF)>>;
3133 // FIXME: This pattern incorrectly assumes the shl operator is a rotate.
3134 // The transformation should probably be done as a combiner action
3135 // instead so we can include a check for masking back in the upper
3136 // eight bits of the source into the lower eight bits of the result.
3137 //def : ARMV6Pat<(and (shl GPR:$Src, (i32 8)), 0xFF00FF),
3138 // (UXTB16r_rot GPR:$Src, 3)>;
3139 def : ARMV6Pat<(and (srl GPR:$Src, (i32 8)), 0xFF00FF),
3140 (UXTB16 GPR:$Src, 1)>;
3142 def UXTAB : AI_exta_rrot<0b01101110, "uxtab",
3143 BinOpFrag<(add node:$LHS, (and node:$RHS, 0x00FF))>>;
3144 def UXTAH : AI_exta_rrot<0b01101111, "uxtah",
3145 BinOpFrag<(add node:$LHS, (and node:$RHS, 0xFFFF))>>;
3148 // This isn't safe in general, the add is two 16-bit units, not a 32-bit add.
3149 def UXTAB16 : AI_exta_rrot_np<0b01101100, "uxtab16">;
3152 def SBFX : I<(outs GPRnopc:$Rd),
3153 (ins GPRnopc:$Rn, imm0_31:$lsb, imm1_32:$width),
3154 AddrMode1, 4, IndexModeNone, DPFrm, IIC_iUNAsi,
3155 "sbfx", "\t$Rd, $Rn, $lsb, $width", "", []>,
3156 Requires<[IsARM, HasV6T2]> {
3161 let Inst{27-21} = 0b0111101;
3162 let Inst{6-4} = 0b101;
3163 let Inst{20-16} = width;
3164 let Inst{15-12} = Rd;
3165 let Inst{11-7} = lsb;
3169 def UBFX : I<(outs GPR:$Rd),
3170 (ins GPR:$Rn, imm0_31:$lsb, imm1_32:$width),
3171 AddrMode1, 4, IndexModeNone, DPFrm, IIC_iUNAsi,
3172 "ubfx", "\t$Rd, $Rn, $lsb, $width", "", []>,
3173 Requires<[IsARM, HasV6T2]> {
3178 let Inst{27-21} = 0b0111111;
3179 let Inst{6-4} = 0b101;
3180 let Inst{20-16} = width;
3181 let Inst{15-12} = Rd;
3182 let Inst{11-7} = lsb;
3186 //===----------------------------------------------------------------------===//
3187 // Arithmetic Instructions.
3190 defm ADD : AsI1_bin_irs<0b0100, "add",
3191 IIC_iALUi, IIC_iALUr, IIC_iALUsr,
3192 BinOpFrag<(add node:$LHS, node:$RHS)>, 1>;
3193 defm SUB : AsI1_bin_irs<0b0010, "sub",
3194 IIC_iALUi, IIC_iALUr, IIC_iALUsr,
3195 BinOpFrag<(sub node:$LHS, node:$RHS)>>;
3197 // ADD and SUB with 's' bit set.
3199 // Currently, ADDS/SUBS are pseudo opcodes that exist only in the
3200 // selection DAG. They are "lowered" to real ADD/SUB opcodes by
3201 // AdjustInstrPostInstrSelection where we determine whether or not to
3202 // set the "s" bit based on CPSR liveness.
3204 // FIXME: Eliminate ADDS/SUBS pseudo opcodes after adding tablegen
3205 // support for an optional CPSR definition that corresponds to the DAG
3206 // node's second value. We can then eliminate the implicit def of CPSR.
3207 defm ADDS : AsI1_bin_s_irs<IIC_iALUi, IIC_iALUr, IIC_iALUsr,
3208 BinOpFrag<(ARMaddc node:$LHS, node:$RHS)>, 1>;
3209 defm SUBS : AsI1_bin_s_irs<IIC_iALUi, IIC_iALUr, IIC_iALUsr,
3210 BinOpFrag<(ARMsubc node:$LHS, node:$RHS)>>;
3212 defm ADC : AI1_adde_sube_irs<0b0101, "adc",
3213 BinOpWithFlagFrag<(ARMadde node:$LHS, node:$RHS, node:$FLAG)>, 1>;
3214 defm SBC : AI1_adde_sube_irs<0b0110, "sbc",
3215 BinOpWithFlagFrag<(ARMsube node:$LHS, node:$RHS, node:$FLAG)>>;
3217 defm RSB : AsI1_rbin_irs<0b0011, "rsb",
3218 IIC_iALUi, IIC_iALUr, IIC_iALUsr,
3219 BinOpFrag<(sub node:$LHS, node:$RHS)>>;
3221 // FIXME: Eliminate them if we can write def : Pat patterns which defines
3222 // CPSR and the implicit def of CPSR is not needed.
3223 defm RSBS : AsI1_rbin_s_is<IIC_iALUi, IIC_iALUr, IIC_iALUsr,
3224 BinOpFrag<(ARMsubc node:$LHS, node:$RHS)>>;
3226 defm RSC : AI1_rsc_irs<0b0111, "rsc",
3227 BinOpWithFlagFrag<(ARMsube node:$LHS, node:$RHS, node:$FLAG)>>;
3229 // (sub X, imm) gets canonicalized to (add X, -imm). Match this form.
3230 // The assume-no-carry-in form uses the negation of the input since add/sub
3231 // assume opposite meanings of the carry flag (i.e., carry == !borrow).
3232 // See the definition of AddWithCarry() in the ARM ARM A2.2.1 for the gory
3234 def : ARMPat<(add GPR:$src, so_imm_neg:$imm),
3235 (SUBri GPR:$src, so_imm_neg:$imm)>;
3236 def : ARMPat<(ARMaddc GPR:$src, so_imm_neg:$imm),
3237 (SUBSri GPR:$src, so_imm_neg:$imm)>;
3239 def : ARMPat<(add GPR:$src, imm0_65535_neg:$imm),
3240 (SUBrr GPR:$src, (MOVi16 (imm_neg_XFORM imm:$imm)))>,
3241 Requires<[IsARM, HasV6T2]>;
3242 def : ARMPat<(ARMaddc GPR:$src, imm0_65535_neg:$imm),
3243 (SUBSrr GPR:$src, (MOVi16 (imm_neg_XFORM imm:$imm)))>,
3244 Requires<[IsARM, HasV6T2]>;
3246 // The with-carry-in form matches bitwise not instead of the negation.
3247 // Effectively, the inverse interpretation of the carry flag already accounts
3248 // for part of the negation.
3249 def : ARMPat<(ARMadde GPR:$src, so_imm_not:$imm, CPSR),
3250 (SBCri GPR:$src, so_imm_not:$imm)>;
3251 def : ARMPat<(ARMadde GPR:$src, imm0_65535_neg:$imm, CPSR),
3252 (SBCrr GPR:$src, (MOVi16 (imm_not_XFORM imm:$imm)))>;
3254 // Note: These are implemented in C++ code, because they have to generate
3255 // ADD/SUBrs instructions, which use a complex pattern that a xform function
3257 // (mul X, 2^n+1) -> (add (X << n), X)
3258 // (mul X, 2^n-1) -> (rsb X, (X << n))
3260 // ARM Arithmetic Instruction
3261 // GPR:$dst = GPR:$a op GPR:$b
3262 class AAI<bits<8> op27_20, bits<8> op11_4, string opc,
3263 list<dag> pattern = [],
3264 dag iops = (ins GPRnopc:$Rn, GPRnopc:$Rm),
3265 string asm = "\t$Rd, $Rn, $Rm">
3266 : AI<(outs GPRnopc:$Rd), iops, DPFrm, IIC_iALUr, opc, asm, pattern>,
3267 Sched<[WriteALU, ReadALU, ReadALU]> {
3271 let Inst{27-20} = op27_20;
3272 let Inst{11-4} = op11_4;
3273 let Inst{19-16} = Rn;
3274 let Inst{15-12} = Rd;
3277 let Unpredictable{11-8} = 0b1111;
3280 // Saturating add/subtract
3282 let DecoderMethod = "DecodeQADDInstruction" in
3283 def QADD : AAI<0b00010000, 0b00000101, "qadd",
3284 [(set GPRnopc:$Rd, (int_arm_qadd GPRnopc:$Rm, GPRnopc:$Rn))],
3285 (ins GPRnopc:$Rm, GPRnopc:$Rn), "\t$Rd, $Rm, $Rn">;
3287 def QSUB : AAI<0b00010010, 0b00000101, "qsub",
3288 [(set GPRnopc:$Rd, (int_arm_qsub GPRnopc:$Rm, GPRnopc:$Rn))],
3289 (ins GPRnopc:$Rm, GPRnopc:$Rn), "\t$Rd, $Rm, $Rn">;
3290 def QDADD : AAI<0b00010100, 0b00000101, "qdadd", [],
3291 (ins GPRnopc:$Rm, GPRnopc:$Rn),
3293 def QDSUB : AAI<0b00010110, 0b00000101, "qdsub", [],
3294 (ins GPRnopc:$Rm, GPRnopc:$Rn),
3297 def QADD16 : AAI<0b01100010, 0b11110001, "qadd16">;
3298 def QADD8 : AAI<0b01100010, 0b11111001, "qadd8">;
3299 def QASX : AAI<0b01100010, 0b11110011, "qasx">;
3300 def QSAX : AAI<0b01100010, 0b11110101, "qsax">;
3301 def QSUB16 : AAI<0b01100010, 0b11110111, "qsub16">;
3302 def QSUB8 : AAI<0b01100010, 0b11111111, "qsub8">;
3303 def UQADD16 : AAI<0b01100110, 0b11110001, "uqadd16">;
3304 def UQADD8 : AAI<0b01100110, 0b11111001, "uqadd8">;
3305 def UQASX : AAI<0b01100110, 0b11110011, "uqasx">;
3306 def UQSAX : AAI<0b01100110, 0b11110101, "uqsax">;
3307 def UQSUB16 : AAI<0b01100110, 0b11110111, "uqsub16">;
3308 def UQSUB8 : AAI<0b01100110, 0b11111111, "uqsub8">;
3310 // Signed/Unsigned add/subtract
3312 def SASX : AAI<0b01100001, 0b11110011, "sasx">;
3313 def SADD16 : AAI<0b01100001, 0b11110001, "sadd16">;
3314 def SADD8 : AAI<0b01100001, 0b11111001, "sadd8">;
3315 def SSAX : AAI<0b01100001, 0b11110101, "ssax">;
3316 def SSUB16 : AAI<0b01100001, 0b11110111, "ssub16">;
3317 def SSUB8 : AAI<0b01100001, 0b11111111, "ssub8">;
3318 def UASX : AAI<0b01100101, 0b11110011, "uasx">;
3319 def UADD16 : AAI<0b01100101, 0b11110001, "uadd16">;
3320 def UADD8 : AAI<0b01100101, 0b11111001, "uadd8">;
3321 def USAX : AAI<0b01100101, 0b11110101, "usax">;
3322 def USUB16 : AAI<0b01100101, 0b11110111, "usub16">;
3323 def USUB8 : AAI<0b01100101, 0b11111111, "usub8">;
3325 // Signed/Unsigned halving add/subtract
3327 def SHASX : AAI<0b01100011, 0b11110011, "shasx">;
3328 def SHADD16 : AAI<0b01100011, 0b11110001, "shadd16">;
3329 def SHADD8 : AAI<0b01100011, 0b11111001, "shadd8">;
3330 def SHSAX : AAI<0b01100011, 0b11110101, "shsax">;
3331 def SHSUB16 : AAI<0b01100011, 0b11110111, "shsub16">;
3332 def SHSUB8 : AAI<0b01100011, 0b11111111, "shsub8">;
3333 def UHASX : AAI<0b01100111, 0b11110011, "uhasx">;
3334 def UHADD16 : AAI<0b01100111, 0b11110001, "uhadd16">;
3335 def UHADD8 : AAI<0b01100111, 0b11111001, "uhadd8">;
3336 def UHSAX : AAI<0b01100111, 0b11110101, "uhsax">;
3337 def UHSUB16 : AAI<0b01100111, 0b11110111, "uhsub16">;
3338 def UHSUB8 : AAI<0b01100111, 0b11111111, "uhsub8">;
3340 // Unsigned Sum of Absolute Differences [and Accumulate].
3342 def USAD8 : AI<(outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm),
3343 MulFrm /* for convenience */, NoItinerary, "usad8",
3344 "\t$Rd, $Rn, $Rm", []>,
3345 Requires<[IsARM, HasV6]>, Sched<[WriteALU, ReadALU, ReadALU]> {
3349 let Inst{27-20} = 0b01111000;
3350 let Inst{15-12} = 0b1111;
3351 let Inst{7-4} = 0b0001;
3352 let Inst{19-16} = Rd;
3353 let Inst{11-8} = Rm;
3356 def USADA8 : AI<(outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm, GPR:$Ra),
3357 MulFrm /* for convenience */, NoItinerary, "usada8",
3358 "\t$Rd, $Rn, $Rm, $Ra", []>,
3359 Requires<[IsARM, HasV6]>, Sched<[WriteALU, ReadALU, ReadALU]>{
3364 let Inst{27-20} = 0b01111000;
3365 let Inst{7-4} = 0b0001;
3366 let Inst{19-16} = Rd;
3367 let Inst{15-12} = Ra;
3368 let Inst{11-8} = Rm;
3372 // Signed/Unsigned saturate
3374 def SSAT : AI<(outs GPRnopc:$Rd),
3375 (ins imm1_32:$sat_imm, GPRnopc:$Rn, shift_imm:$sh),
3376 SatFrm, NoItinerary, "ssat", "\t$Rd, $sat_imm, $Rn$sh", []> {
3381 let Inst{27-21} = 0b0110101;
3382 let Inst{5-4} = 0b01;
3383 let Inst{20-16} = sat_imm;
3384 let Inst{15-12} = Rd;
3385 let Inst{11-7} = sh{4-0};
3386 let Inst{6} = sh{5};
3390 def SSAT16 : AI<(outs GPRnopc:$Rd),
3391 (ins imm1_16:$sat_imm, GPRnopc:$Rn), SatFrm,
3392 NoItinerary, "ssat16", "\t$Rd, $sat_imm, $Rn", []> {
3396 let Inst{27-20} = 0b01101010;
3397 let Inst{11-4} = 0b11110011;
3398 let Inst{15-12} = Rd;
3399 let Inst{19-16} = sat_imm;
3403 def USAT : AI<(outs GPRnopc:$Rd),
3404 (ins imm0_31:$sat_imm, GPRnopc:$Rn, shift_imm:$sh),
3405 SatFrm, NoItinerary, "usat", "\t$Rd, $sat_imm, $Rn$sh", []> {
3410 let Inst{27-21} = 0b0110111;
3411 let Inst{5-4} = 0b01;
3412 let Inst{15-12} = Rd;
3413 let Inst{11-7} = sh{4-0};
3414 let Inst{6} = sh{5};
3415 let Inst{20-16} = sat_imm;
3419 def USAT16 : AI<(outs GPRnopc:$Rd),
3420 (ins imm0_15:$sat_imm, GPRnopc:$Rn), SatFrm,
3421 NoItinerary, "usat16", "\t$Rd, $sat_imm, $Rn", []> {
3425 let Inst{27-20} = 0b01101110;
3426 let Inst{11-4} = 0b11110011;
3427 let Inst{15-12} = Rd;
3428 let Inst{19-16} = sat_imm;
3432 def : ARMV6Pat<(int_arm_ssat GPRnopc:$a, imm:$pos),
3433 (SSAT imm:$pos, GPRnopc:$a, 0)>;
3434 def : ARMV6Pat<(int_arm_usat GPRnopc:$a, imm:$pos),
3435 (USAT imm:$pos, GPRnopc:$a, 0)>;
3437 //===----------------------------------------------------------------------===//
3438 // Bitwise Instructions.
3441 defm AND : AsI1_bin_irs<0b0000, "and",
3442 IIC_iBITi, IIC_iBITr, IIC_iBITsr,
3443 BinOpFrag<(and node:$LHS, node:$RHS)>, 1>;
3444 defm ORR : AsI1_bin_irs<0b1100, "orr",
3445 IIC_iBITi, IIC_iBITr, IIC_iBITsr,
3446 BinOpFrag<(or node:$LHS, node:$RHS)>, 1>;
3447 defm EOR : AsI1_bin_irs<0b0001, "eor",
3448 IIC_iBITi, IIC_iBITr, IIC_iBITsr,
3449 BinOpFrag<(xor node:$LHS, node:$RHS)>, 1>;
3450 defm BIC : AsI1_bin_irs<0b1110, "bic",
3451 IIC_iBITi, IIC_iBITr, IIC_iBITsr,
3452 BinOpFrag<(and node:$LHS, (not node:$RHS))>>;
3454 // FIXME: bf_inv_mask_imm should be two operands, the lsb and the msb, just
3455 // like in the actual instruction encoding. The complexity of mapping the mask
3456 // to the lsb/msb pair should be handled by ISel, not encapsulated in the
3457 // instruction description.
3458 def BFC : I<(outs GPR:$Rd), (ins GPR:$src, bf_inv_mask_imm:$imm),
3459 AddrMode1, 4, IndexModeNone, DPFrm, IIC_iUNAsi,
3460 "bfc", "\t$Rd, $imm", "$src = $Rd",
3461 [(set GPR:$Rd, (and GPR:$src, bf_inv_mask_imm:$imm))]>,
3462 Requires<[IsARM, HasV6T2]> {
3465 let Inst{27-21} = 0b0111110;
3466 let Inst{6-0} = 0b0011111;
3467 let Inst{15-12} = Rd;
3468 let Inst{11-7} = imm{4-0}; // lsb
3469 let Inst{20-16} = imm{9-5}; // msb
3472 // A8.6.18 BFI - Bitfield insert (Encoding A1)
3473 def BFI:I<(outs GPRnopc:$Rd), (ins GPRnopc:$src, GPR:$Rn, bf_inv_mask_imm:$imm),
3474 AddrMode1, 4, IndexModeNone, DPFrm, IIC_iUNAsi,
3475 "bfi", "\t$Rd, $Rn, $imm", "$src = $Rd",
3476 [(set GPRnopc:$Rd, (ARMbfi GPRnopc:$src, GPR:$Rn,
3477 bf_inv_mask_imm:$imm))]>,
3478 Requires<[IsARM, HasV6T2]> {
3482 let Inst{27-21} = 0b0111110;
3483 let Inst{6-4} = 0b001; // Rn: Inst{3-0} != 15
3484 let Inst{15-12} = Rd;
3485 let Inst{11-7} = imm{4-0}; // lsb
3486 let Inst{20-16} = imm{9-5}; // width
3490 def MVNr : AsI1<0b1111, (outs GPR:$Rd), (ins GPR:$Rm), DPFrm, IIC_iMVNr,
3491 "mvn", "\t$Rd, $Rm",
3492 [(set GPR:$Rd, (not GPR:$Rm))]>, UnaryDP, Sched<[WriteALU]> {
3496 let Inst{19-16} = 0b0000;
3497 let Inst{11-4} = 0b00000000;
3498 let Inst{15-12} = Rd;
3501 def MVNsi : AsI1<0b1111, (outs GPR:$Rd), (ins so_reg_imm:$shift),
3502 DPSoRegImmFrm, IIC_iMVNsr, "mvn", "\t$Rd, $shift",
3503 [(set GPR:$Rd, (not so_reg_imm:$shift))]>, UnaryDP,
3508 let Inst{19-16} = 0b0000;
3509 let Inst{15-12} = Rd;
3510 let Inst{11-5} = shift{11-5};
3512 let Inst{3-0} = shift{3-0};
3514 def MVNsr : AsI1<0b1111, (outs GPR:$Rd), (ins so_reg_reg:$shift),
3515 DPSoRegRegFrm, IIC_iMVNsr, "mvn", "\t$Rd, $shift",
3516 [(set GPR:$Rd, (not so_reg_reg:$shift))]>, UnaryDP,
3521 let Inst{19-16} = 0b0000;
3522 let Inst{15-12} = Rd;
3523 let Inst{11-8} = shift{11-8};
3525 let Inst{6-5} = shift{6-5};
3527 let Inst{3-0} = shift{3-0};
3529 let isReMaterializable = 1, isAsCheapAsAMove = 1, isMoveImm = 1 in
3530 def MVNi : AsI1<0b1111, (outs GPR:$Rd), (ins so_imm:$imm), DPFrm,
3531 IIC_iMVNi, "mvn", "\t$Rd, $imm",
3532 [(set GPR:$Rd, so_imm_not:$imm)]>,UnaryDP, Sched<[WriteALU]> {
3536 let Inst{19-16} = 0b0000;
3537 let Inst{15-12} = Rd;
3538 let Inst{11-0} = imm;
3541 def : ARMPat<(and GPR:$src, so_imm_not:$imm),
3542 (BICri GPR:$src, so_imm_not:$imm)>;
3544 //===----------------------------------------------------------------------===//
3545 // Multiply Instructions.
3547 class AsMul1I32<bits<7> opcod, dag oops, dag iops, InstrItinClass itin,
3548 string opc, string asm, list<dag> pattern>
3549 : AsMul1I<opcod, oops, iops, itin, opc, asm, pattern> {
3553 let Inst{19-16} = Rd;
3554 let Inst{11-8} = Rm;
3557 class AsMul1I64<bits<7> opcod, dag oops, dag iops, InstrItinClass itin,
3558 string opc, string asm, list<dag> pattern>
3559 : AsMul1I<opcod, oops, iops, itin, opc, asm, pattern> {
3564 let Inst{19-16} = RdHi;
3565 let Inst{15-12} = RdLo;
3566 let Inst{11-8} = Rm;
3569 class AsMla1I64<bits<7> opcod, dag oops, dag iops, InstrItinClass itin,
3570 string opc, string asm, list<dag> pattern>
3571 : AsMul1I<opcod, oops, iops, itin, opc, asm, pattern> {
3576 let Inst{19-16} = RdHi;
3577 let Inst{15-12} = RdLo;
3578 let Inst{11-8} = Rm;
3582 // FIXME: The v5 pseudos are only necessary for the additional Constraint
3583 // property. Remove them when it's possible to add those properties
3584 // on an individual MachineInstr, not just an instruction description.
3585 let isCommutable = 1, TwoOperandAliasConstraint = "$Rn = $Rd" in {
3586 def MUL : AsMul1I32<0b0000000, (outs GPRnopc:$Rd),
3587 (ins GPRnopc:$Rn, GPRnopc:$Rm),
3588 IIC_iMUL32, "mul", "\t$Rd, $Rn, $Rm",
3589 [(set GPRnopc:$Rd, (mul GPRnopc:$Rn, GPRnopc:$Rm))]>,
3590 Requires<[IsARM, HasV6]> {
3591 let Inst{15-12} = 0b0000;
3592 let Unpredictable{15-12} = 0b1111;
3595 let Constraints = "@earlyclobber $Rd" in
3596 def MULv5: ARMPseudoExpand<(outs GPRnopc:$Rd), (ins GPRnopc:$Rn, GPRnopc:$Rm,
3597 pred:$p, cc_out:$s),
3599 [(set GPRnopc:$Rd, (mul GPRnopc:$Rn, GPRnopc:$Rm))],
3600 (MUL GPRnopc:$Rd, GPRnopc:$Rn, GPRnopc:$Rm, pred:$p, cc_out:$s)>,
3601 Requires<[IsARM, NoV6, UseMulOps]>;
3604 def MLA : AsMul1I32<0b0000001, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm, GPR:$Ra),
3605 IIC_iMAC32, "mla", "\t$Rd, $Rn, $Rm, $Ra",
3606 [(set GPR:$Rd, (add (mul GPR:$Rn, GPR:$Rm), GPR:$Ra))]>,
3607 Requires<[IsARM, HasV6, UseMulOps]> {
3609 let Inst{15-12} = Ra;
3612 let Constraints = "@earlyclobber $Rd" in
3613 def MLAv5: ARMPseudoExpand<(outs GPR:$Rd),
3614 (ins GPR:$Rn, GPR:$Rm, GPR:$Ra, pred:$p, cc_out:$s),
3616 [(set GPR:$Rd, (add (mul GPR:$Rn, GPR:$Rm), GPR:$Ra))],
3617 (MLA GPR:$Rd, GPR:$Rn, GPR:$Rm, GPR:$Ra, pred:$p, cc_out:$s)>,
3618 Requires<[IsARM, NoV6]>;
3620 def MLS : AMul1I<0b0000011, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm, GPR:$Ra),
3621 IIC_iMAC32, "mls", "\t$Rd, $Rn, $Rm, $Ra",
3622 [(set GPR:$Rd, (sub GPR:$Ra, (mul GPR:$Rn, GPR:$Rm)))]>,
3623 Requires<[IsARM, HasV6T2, UseMulOps]> {
3628 let Inst{19-16} = Rd;
3629 let Inst{15-12} = Ra;
3630 let Inst{11-8} = Rm;
3634 // Extra precision multiplies with low / high results
3635 let neverHasSideEffects = 1 in {
3636 let isCommutable = 1 in {
3637 def SMULL : AsMul1I64<0b0000110, (outs GPR:$RdLo, GPR:$RdHi),
3638 (ins GPR:$Rn, GPR:$Rm), IIC_iMUL64,
3639 "smull", "\t$RdLo, $RdHi, $Rn, $Rm", []>,
3640 Requires<[IsARM, HasV6]>;
3642 def UMULL : AsMul1I64<0b0000100, (outs GPR:$RdLo, GPR:$RdHi),
3643 (ins GPR:$Rn, GPR:$Rm), IIC_iMUL64,
3644 "umull", "\t$RdLo, $RdHi, $Rn, $Rm", []>,
3645 Requires<[IsARM, HasV6]>;
3647 let Constraints = "@earlyclobber $RdLo,@earlyclobber $RdHi" in {
3648 def SMULLv5 : ARMPseudoExpand<(outs GPR:$RdLo, GPR:$RdHi),
3649 (ins GPR:$Rn, GPR:$Rm, pred:$p, cc_out:$s),
3651 (SMULL GPR:$RdLo, GPR:$RdHi, GPR:$Rn, GPR:$Rm, pred:$p, cc_out:$s)>,
3652 Requires<[IsARM, NoV6]>;
3654 def UMULLv5 : ARMPseudoExpand<(outs GPR:$RdLo, GPR:$RdHi),
3655 (ins GPR:$Rn, GPR:$Rm, pred:$p, cc_out:$s),
3657 (UMULL GPR:$RdLo, GPR:$RdHi, GPR:$Rn, GPR:$Rm, pred:$p, cc_out:$s)>,
3658 Requires<[IsARM, NoV6]>;
3662 // Multiply + accumulate
3663 def SMLAL : AsMla1I64<0b0000111, (outs GPR:$RdLo, GPR:$RdHi),
3664 (ins GPR:$Rn, GPR:$Rm, GPR:$RLo, GPR:$RHi), IIC_iMAC64,
3665 "smlal", "\t$RdLo, $RdHi, $Rn, $Rm", []>,
3666 RegConstraint<"$RLo = $RdLo, $RHi = $RdHi">, Requires<[IsARM, HasV6]>;
3667 def UMLAL : AsMla1I64<0b0000101, (outs GPR:$RdLo, GPR:$RdHi),
3668 (ins GPR:$Rn, GPR:$Rm, GPR:$RLo, GPR:$RHi), IIC_iMAC64,
3669 "umlal", "\t$RdLo, $RdHi, $Rn, $Rm", []>,
3670 RegConstraint<"$RLo = $RdLo, $RHi = $RdHi">, Requires<[IsARM, HasV6]>;
3672 def UMAAL : AMul1I <0b0000010, (outs GPR:$RdLo, GPR:$RdHi),
3673 (ins GPR:$Rn, GPR:$Rm), IIC_iMAC64,
3674 "umaal", "\t$RdLo, $RdHi, $Rn, $Rm", []>,
3675 Requires<[IsARM, HasV6]> {
3680 let Inst{19-16} = RdHi;
3681 let Inst{15-12} = RdLo;
3682 let Inst{11-8} = Rm;
3686 let Constraints = "$RLo = $RdLo,$RHi = $RdHi" in {
3687 def SMLALv5 : ARMPseudoExpand<(outs GPR:$RdLo, GPR:$RdHi),
3688 (ins GPR:$Rn, GPR:$Rm, GPR:$RLo, GPR:$RHi, pred:$p, cc_out:$s),
3690 (SMLAL GPR:$RdLo, GPR:$RdHi, GPR:$Rn, GPR:$Rm, GPR:$RLo, GPR:$RHi,
3691 pred:$p, cc_out:$s)>,
3692 Requires<[IsARM, NoV6]>;
3693 def UMLALv5 : ARMPseudoExpand<(outs GPR:$RdLo, GPR:$RdHi),
3694 (ins GPR:$Rn, GPR:$Rm, GPR:$RLo, GPR:$RHi, pred:$p, cc_out:$s),
3696 (UMLAL GPR:$RdLo, GPR:$RdHi, GPR:$Rn, GPR:$Rm, GPR:$RLo, GPR:$RHi,
3697 pred:$p, cc_out:$s)>,
3698 Requires<[IsARM, NoV6]>;
3701 let Constraints = "@earlyclobber $RdLo,@earlyclobber $RdHi" in {
3702 def UMAALv5 : ARMPseudoExpand<(outs GPR:$RdLo, GPR:$RdHi),
3703 (ins GPR:$Rn, GPR:$Rm, pred:$p),
3705 (UMAAL GPR:$RdLo, GPR:$RdHi, GPR:$Rn, GPR:$Rm, pred:$p)>,
3706 Requires<[IsARM, NoV6]>;
3709 } // neverHasSideEffects
3711 // Most significant word multiply
3712 def SMMUL : AMul2I <0b0111010, 0b0001, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm),
3713 IIC_iMUL32, "smmul", "\t$Rd, $Rn, $Rm",
3714 [(set GPR:$Rd, (mulhs GPR:$Rn, GPR:$Rm))]>,
3715 Requires<[IsARM, HasV6]> {
3716 let Inst{15-12} = 0b1111;
3719 def SMMULR : AMul2I <0b0111010, 0b0011, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm),
3720 IIC_iMUL32, "smmulr", "\t$Rd, $Rn, $Rm", []>,
3721 Requires<[IsARM, HasV6]> {
3722 let Inst{15-12} = 0b1111;
3725 def SMMLA : AMul2Ia <0b0111010, 0b0001, (outs GPR:$Rd),
3726 (ins GPR:$Rn, GPR:$Rm, GPR:$Ra),
3727 IIC_iMAC32, "smmla", "\t$Rd, $Rn, $Rm, $Ra",
3728 [(set GPR:$Rd, (add (mulhs GPR:$Rn, GPR:$Rm), GPR:$Ra))]>,
3729 Requires<[IsARM, HasV6, UseMulOps]>;
3731 def SMMLAR : AMul2Ia <0b0111010, 0b0011, (outs GPR:$Rd),
3732 (ins GPR:$Rn, GPR:$Rm, GPR:$Ra),
3733 IIC_iMAC32, "smmlar", "\t$Rd, $Rn, $Rm, $Ra", []>,
3734 Requires<[IsARM, HasV6]>;
3736 def SMMLS : AMul2Ia <0b0111010, 0b1101, (outs GPR:$Rd),
3737 (ins GPR:$Rn, GPR:$Rm, GPR:$Ra),
3738 IIC_iMAC32, "smmls", "\t$Rd, $Rn, $Rm, $Ra", []>,
3739 Requires<[IsARM, HasV6, UseMulOps]>;
3741 def SMMLSR : AMul2Ia <0b0111010, 0b1111, (outs GPR:$Rd),
3742 (ins GPR:$Rn, GPR:$Rm, GPR:$Ra),
3743 IIC_iMAC32, "smmlsr", "\t$Rd, $Rn, $Rm, $Ra", []>,
3744 Requires<[IsARM, HasV6]>;
3746 multiclass AI_smul<string opc, PatFrag opnode> {
3747 def BB : AMulxyI<0b0001011, 0b00, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm),
3748 IIC_iMUL16, !strconcat(opc, "bb"), "\t$Rd, $Rn, $Rm",
3749 [(set GPR:$Rd, (opnode (sext_inreg GPR:$Rn, i16),
3750 (sext_inreg GPR:$Rm, i16)))]>,
3751 Requires<[IsARM, HasV5TE]>;
3753 def BT : AMulxyI<0b0001011, 0b10, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm),
3754 IIC_iMUL16, !strconcat(opc, "bt"), "\t$Rd, $Rn, $Rm",
3755 [(set GPR:$Rd, (opnode (sext_inreg GPR:$Rn, i16),
3756 (sra GPR:$Rm, (i32 16))))]>,
3757 Requires<[IsARM, HasV5TE]>;
3759 def TB : AMulxyI<0b0001011, 0b01, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm),
3760 IIC_iMUL16, !strconcat(opc, "tb"), "\t$Rd, $Rn, $Rm",
3761 [(set GPR:$Rd, (opnode (sra GPR:$Rn, (i32 16)),
3762 (sext_inreg GPR:$Rm, i16)))]>,
3763 Requires<[IsARM, HasV5TE]>;
3765 def TT : AMulxyI<0b0001011, 0b11, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm),
3766 IIC_iMUL16, !strconcat(opc, "tt"), "\t$Rd, $Rn, $Rm",
3767 [(set GPR:$Rd, (opnode (sra GPR:$Rn, (i32 16)),
3768 (sra GPR:$Rm, (i32 16))))]>,
3769 Requires<[IsARM, HasV5TE]>;
3771 def WB : AMulxyI<0b0001001, 0b01, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm),
3772 IIC_iMUL16, !strconcat(opc, "wb"), "\t$Rd, $Rn, $Rm",
3773 [(set GPR:$Rd, (sra (opnode GPR:$Rn,
3774 (sext_inreg GPR:$Rm, i16)), (i32 16)))]>,
3775 Requires<[IsARM, HasV5TE]>;
3777 def WT : AMulxyI<0b0001001, 0b11, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm),
3778 IIC_iMUL16, !strconcat(opc, "wt"), "\t$Rd, $Rn, $Rm",
3779 [(set GPR:$Rd, (sra (opnode GPR:$Rn,
3780 (sra GPR:$Rm, (i32 16))), (i32 16)))]>,
3781 Requires<[IsARM, HasV5TE]>;
3785 multiclass AI_smla<string opc, PatFrag opnode> {
3786 let DecoderMethod = "DecodeSMLAInstruction" in {
3787 def BB : AMulxyIa<0b0001000, 0b00, (outs GPRnopc:$Rd),
3788 (ins GPRnopc:$Rn, GPRnopc:$Rm, GPR:$Ra),
3789 IIC_iMAC16, !strconcat(opc, "bb"), "\t$Rd, $Rn, $Rm, $Ra",
3790 [(set GPRnopc:$Rd, (add GPR:$Ra,
3791 (opnode (sext_inreg GPRnopc:$Rn, i16),
3792 (sext_inreg GPRnopc:$Rm, i16))))]>,
3793 Requires<[IsARM, HasV5TE, UseMulOps]>;
3795 def BT : AMulxyIa<0b0001000, 0b10, (outs GPRnopc:$Rd),
3796 (ins GPRnopc:$Rn, GPRnopc:$Rm, GPR:$Ra),
3797 IIC_iMAC16, !strconcat(opc, "bt"), "\t$Rd, $Rn, $Rm, $Ra",
3799 (add GPR:$Ra, (opnode (sext_inreg GPRnopc:$Rn, i16),
3800 (sra GPRnopc:$Rm, (i32 16)))))]>,
3801 Requires<[IsARM, HasV5TE, UseMulOps]>;
3803 def TB : AMulxyIa<0b0001000, 0b01, (outs GPRnopc:$Rd),
3804 (ins GPRnopc:$Rn, GPRnopc:$Rm, GPR:$Ra),
3805 IIC_iMAC16, !strconcat(opc, "tb"), "\t$Rd, $Rn, $Rm, $Ra",
3807 (add GPR:$Ra, (opnode (sra GPRnopc:$Rn, (i32 16)),
3808 (sext_inreg GPRnopc:$Rm, i16))))]>,
3809 Requires<[IsARM, HasV5TE, UseMulOps]>;
3811 def TT : AMulxyIa<0b0001000, 0b11, (outs GPRnopc:$Rd),
3812 (ins GPRnopc:$Rn, GPRnopc:$Rm, GPR:$Ra),
3813 IIC_iMAC16, !strconcat(opc, "tt"), "\t$Rd, $Rn, $Rm, $Ra",
3815 (add GPR:$Ra, (opnode (sra GPRnopc:$Rn, (i32 16)),
3816 (sra GPRnopc:$Rm, (i32 16)))))]>,
3817 Requires<[IsARM, HasV5TE, UseMulOps]>;
3819 def WB : AMulxyIa<0b0001001, 0b00, (outs GPRnopc:$Rd),
3820 (ins GPRnopc:$Rn, GPRnopc:$Rm, GPR:$Ra),
3821 IIC_iMAC16, !strconcat(opc, "wb"), "\t$Rd, $Rn, $Rm, $Ra",
3823 (add GPR:$Ra, (sra (opnode GPRnopc:$Rn,
3824 (sext_inreg GPRnopc:$Rm, i16)), (i32 16))))]>,
3825 Requires<[IsARM, HasV5TE, UseMulOps]>;
3827 def WT : AMulxyIa<0b0001001, 0b10, (outs GPRnopc:$Rd),
3828 (ins GPRnopc:$Rn, GPRnopc:$Rm, GPR:$Ra),
3829 IIC_iMAC16, !strconcat(opc, "wt"), "\t$Rd, $Rn, $Rm, $Ra",
3831 (add GPR:$Ra, (sra (opnode GPRnopc:$Rn,
3832 (sra GPRnopc:$Rm, (i32 16))), (i32 16))))]>,
3833 Requires<[IsARM, HasV5TE, UseMulOps]>;
3837 defm SMUL : AI_smul<"smul", BinOpFrag<(mul node:$LHS, node:$RHS)>>;
3838 defm SMLA : AI_smla<"smla", BinOpFrag<(mul node:$LHS, node:$RHS)>>;
3840 // Halfword multiply accumulate long: SMLAL<x><y>.
3841 def SMLALBB : AMulxyI64<0b0001010, 0b00, (outs GPRnopc:$RdLo, GPRnopc:$RdHi),
3842 (ins GPRnopc:$Rn, GPRnopc:$Rm),
3843 IIC_iMAC64, "smlalbb", "\t$RdLo, $RdHi, $Rn, $Rm", []>,
3844 Requires<[IsARM, HasV5TE]>;
3846 def SMLALBT : AMulxyI64<0b0001010, 0b10, (outs GPRnopc:$RdLo, GPRnopc:$RdHi),
3847 (ins GPRnopc:$Rn, GPRnopc:$Rm),
3848 IIC_iMAC64, "smlalbt", "\t$RdLo, $RdHi, $Rn, $Rm", []>,
3849 Requires<[IsARM, HasV5TE]>;
3851 def SMLALTB : AMulxyI64<0b0001010, 0b01, (outs GPRnopc:$RdLo, GPRnopc:$RdHi),
3852 (ins GPRnopc:$Rn, GPRnopc:$Rm),
3853 IIC_iMAC64, "smlaltb", "\t$RdLo, $RdHi, $Rn, $Rm", []>,
3854 Requires<[IsARM, HasV5TE]>;
3856 def SMLALTT : AMulxyI64<0b0001010, 0b11, (outs GPRnopc:$RdLo, GPRnopc:$RdHi),
3857 (ins GPRnopc:$Rn, GPRnopc:$Rm),
3858 IIC_iMAC64, "smlaltt", "\t$RdLo, $RdHi, $Rn, $Rm", []>,
3859 Requires<[IsARM, HasV5TE]>;
3861 // Helper class for AI_smld.
3862 class AMulDualIbase<bit long, bit sub, bit swap, dag oops, dag iops,
3863 InstrItinClass itin, string opc, string asm>
3864 : AI<oops, iops, MulFrm, itin, opc, asm, []>, Requires<[IsARM, HasV6]> {
3867 let Inst{27-23} = 0b01110;
3868 let Inst{22} = long;
3869 let Inst{21-20} = 0b00;
3870 let Inst{11-8} = Rm;
3877 class AMulDualI<bit long, bit sub, bit swap, dag oops, dag iops,
3878 InstrItinClass itin, string opc, string asm>
3879 : AMulDualIbase<long, sub, swap, oops, iops, itin, opc, asm> {
3881 let Inst{15-12} = 0b1111;
3882 let Inst{19-16} = Rd;
3884 class AMulDualIa<bit long, bit sub, bit swap, dag oops, dag iops,
3885 InstrItinClass itin, string opc, string asm>
3886 : AMulDualIbase<long, sub, swap, oops, iops, itin, opc, asm> {
3889 let Inst{19-16} = Rd;
3890 let Inst{15-12} = Ra;
3892 class AMulDualI64<bit long, bit sub, bit swap, dag oops, dag iops,
3893 InstrItinClass itin, string opc, string asm>
3894 : AMulDualIbase<long, sub, swap, oops, iops, itin, opc, asm> {
3897 let Inst{19-16} = RdHi;
3898 let Inst{15-12} = RdLo;
3901 multiclass AI_smld<bit sub, string opc> {
3903 def D : AMulDualIa<0, sub, 0, (outs GPRnopc:$Rd),
3904 (ins GPRnopc:$Rn, GPRnopc:$Rm, GPR:$Ra),
3905 NoItinerary, !strconcat(opc, "d"), "\t$Rd, $Rn, $Rm, $Ra">;
3907 def DX: AMulDualIa<0, sub, 1, (outs GPRnopc:$Rd),
3908 (ins GPRnopc:$Rn, GPRnopc:$Rm, GPR:$Ra),
3909 NoItinerary, !strconcat(opc, "dx"), "\t$Rd, $Rn, $Rm, $Ra">;
3911 def LD: AMulDualI64<1, sub, 0, (outs GPRnopc:$RdLo, GPRnopc:$RdHi),
3912 (ins GPRnopc:$Rn, GPRnopc:$Rm), NoItinerary,
3913 !strconcat(opc, "ld"), "\t$RdLo, $RdHi, $Rn, $Rm">;
3915 def LDX : AMulDualI64<1, sub, 1, (outs GPRnopc:$RdLo, GPRnopc:$RdHi),
3916 (ins GPRnopc:$Rn, GPRnopc:$Rm), NoItinerary,
3917 !strconcat(opc, "ldx"),"\t$RdLo, $RdHi, $Rn, $Rm">;
3921 defm SMLA : AI_smld<0, "smla">;
3922 defm SMLS : AI_smld<1, "smls">;
3924 multiclass AI_sdml<bit sub, string opc> {
3926 def D:AMulDualI<0, sub, 0, (outs GPRnopc:$Rd), (ins GPRnopc:$Rn, GPRnopc:$Rm),
3927 NoItinerary, !strconcat(opc, "d"), "\t$Rd, $Rn, $Rm">;
3928 def DX:AMulDualI<0, sub, 1, (outs GPRnopc:$Rd),(ins GPRnopc:$Rn, GPRnopc:$Rm),
3929 NoItinerary, !strconcat(opc, "dx"), "\t$Rd, $Rn, $Rm">;
3932 defm SMUA : AI_sdml<0, "smua">;
3933 defm SMUS : AI_sdml<1, "smus">;
3935 //===----------------------------------------------------------------------===//
3936 // Division Instructions (ARMv7-A with virtualization extension)
3938 def SDIV : ADivA1I<0b001, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm), IIC_iDIV,
3939 "sdiv", "\t$Rd, $Rn, $Rm",
3940 [(set GPR:$Rd, (sdiv GPR:$Rn, GPR:$Rm))]>,
3941 Requires<[IsARM, HasDivideInARM]>;
3943 def UDIV : ADivA1I<0b011, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm), IIC_iDIV,
3944 "udiv", "\t$Rd, $Rn, $Rm",
3945 [(set GPR:$Rd, (udiv GPR:$Rn, GPR:$Rm))]>,
3946 Requires<[IsARM, HasDivideInARM]>;
3948 //===----------------------------------------------------------------------===//
3949 // Misc. Arithmetic Instructions.
3952 def CLZ : AMiscA1I<0b000010110, 0b0001, (outs GPR:$Rd), (ins GPR:$Rm),
3953 IIC_iUNAr, "clz", "\t$Rd, $Rm",
3954 [(set GPR:$Rd, (ctlz GPR:$Rm))]>, Requires<[IsARM, HasV5T]>,
3957 def RBIT : AMiscA1I<0b01101111, 0b0011, (outs GPR:$Rd), (ins GPR:$Rm),
3958 IIC_iUNAr, "rbit", "\t$Rd, $Rm",
3959 [(set GPR:$Rd, (ARMrbit GPR:$Rm))]>,
3960 Requires<[IsARM, HasV6T2]>,
3963 def REV : AMiscA1I<0b01101011, 0b0011, (outs GPR:$Rd), (ins GPR:$Rm),
3964 IIC_iUNAr, "rev", "\t$Rd, $Rm",
3965 [(set GPR:$Rd, (bswap GPR:$Rm))]>, Requires<[IsARM, HasV6]>,
3968 let AddedComplexity = 5 in
3969 def REV16 : AMiscA1I<0b01101011, 0b1011, (outs GPR:$Rd), (ins GPR:$Rm),
3970 IIC_iUNAr, "rev16", "\t$Rd, $Rm",
3971 [(set GPR:$Rd, (rotr (bswap GPR:$Rm), (i32 16)))]>,
3972 Requires<[IsARM, HasV6]>,
3975 let AddedComplexity = 5 in
3976 def REVSH : AMiscA1I<0b01101111, 0b1011, (outs GPR:$Rd), (ins GPR:$Rm),
3977 IIC_iUNAr, "revsh", "\t$Rd, $Rm",
3978 [(set GPR:$Rd, (sra (bswap GPR:$Rm), (i32 16)))]>,
3979 Requires<[IsARM, HasV6]>,
3982 def : ARMV6Pat<(or (sra (shl GPR:$Rm, (i32 24)), (i32 16)),
3983 (and (srl GPR:$Rm, (i32 8)), 0xFF)),
3986 def PKHBT : APKHI<0b01101000, 0, (outs GPRnopc:$Rd),
3987 (ins GPRnopc:$Rn, GPRnopc:$Rm, pkh_lsl_amt:$sh),
3988 IIC_iALUsi, "pkhbt", "\t$Rd, $Rn, $Rm$sh",
3989 [(set GPRnopc:$Rd, (or (and GPRnopc:$Rn, 0xFFFF),
3990 (and (shl GPRnopc:$Rm, pkh_lsl_amt:$sh),
3992 Requires<[IsARM, HasV6]>,
3993 Sched<[WriteALUsi, ReadALU]>;
3995 // Alternate cases for PKHBT where identities eliminate some nodes.
3996 def : ARMV6Pat<(or (and GPRnopc:$Rn, 0xFFFF), (and GPRnopc:$Rm, 0xFFFF0000)),
3997 (PKHBT GPRnopc:$Rn, GPRnopc:$Rm, 0)>;
3998 def : ARMV6Pat<(or (and GPRnopc:$Rn, 0xFFFF), (shl GPRnopc:$Rm, imm16_31:$sh)),
3999 (PKHBT GPRnopc:$Rn, GPRnopc:$Rm, imm16_31:$sh)>;
4001 // Note: Shifts of 1-15 bits will be transformed to srl instead of sra and
4002 // will match the pattern below.
4003 def PKHTB : APKHI<0b01101000, 1, (outs GPRnopc:$Rd),
4004 (ins GPRnopc:$Rn, GPRnopc:$Rm, pkh_asr_amt:$sh),
4005 IIC_iBITsi, "pkhtb", "\t$Rd, $Rn, $Rm$sh",
4006 [(set GPRnopc:$Rd, (or (and GPRnopc:$Rn, 0xFFFF0000),
4007 (and (sra GPRnopc:$Rm, pkh_asr_amt:$sh),
4009 Requires<[IsARM, HasV6]>,
4010 Sched<[WriteALUsi, ReadALU]>;
4012 // Alternate cases for PKHTB where identities eliminate some nodes. Note that
4013 // a shift amount of 0 is *not legal* here, it is PKHBT instead.
4014 // We also can not replace a srl (17..31) by an arithmetic shift we would use in
4015 // pkhtb src1, src2, asr (17..31).
4016 def : ARMV6Pat<(or (and GPRnopc:$src1, 0xFFFF0000),
4017 (srl GPRnopc:$src2, imm16:$sh)),
4018 (PKHTB GPRnopc:$src1, GPRnopc:$src2, imm16:$sh)>;
4019 def : ARMV6Pat<(or (and GPRnopc:$src1, 0xFFFF0000),
4020 (sra GPRnopc:$src2, imm16_31:$sh)),
4021 (PKHTB GPRnopc:$src1, GPRnopc:$src2, imm16_31:$sh)>;
4022 def : ARMV6Pat<(or (and GPRnopc:$src1, 0xFFFF0000),
4023 (and (srl GPRnopc:$src2, imm1_15:$sh), 0xFFFF)),
4024 (PKHTB GPRnopc:$src1, GPRnopc:$src2, imm1_15:$sh)>;
4026 //===----------------------------------------------------------------------===//
4027 // Comparison Instructions...
4030 defm CMP : AI1_cmp_irs<0b1010, "cmp",
4031 IIC_iCMPi, IIC_iCMPr, IIC_iCMPsr,
4032 BinOpFrag<(ARMcmp node:$LHS, node:$RHS)>>;
4034 // ARMcmpZ can re-use the above instruction definitions.
4035 def : ARMPat<(ARMcmpZ GPR:$src, so_imm:$imm),
4036 (CMPri GPR:$src, so_imm:$imm)>;
4037 def : ARMPat<(ARMcmpZ GPR:$src, GPR:$rhs),
4038 (CMPrr GPR:$src, GPR:$rhs)>;
4039 def : ARMPat<(ARMcmpZ GPR:$src, so_reg_imm:$rhs),
4040 (CMPrsi GPR:$src, so_reg_imm:$rhs)>;
4041 def : ARMPat<(ARMcmpZ GPR:$src, so_reg_reg:$rhs),
4042 (CMPrsr GPR:$src, so_reg_reg:$rhs)>;
4044 // CMN register-integer
4045 let isCompare = 1, Defs = [CPSR] in {
4046 def CMNri : AI1<0b1011, (outs), (ins GPR:$Rn, so_imm:$imm), DPFrm, IIC_iCMPi,
4047 "cmn", "\t$Rn, $imm",
4048 [(ARMcmn GPR:$Rn, so_imm:$imm)]>,
4049 Sched<[WriteCMP, ReadALU]> {
4054 let Inst{19-16} = Rn;
4055 let Inst{15-12} = 0b0000;
4056 let Inst{11-0} = imm;
4058 let Unpredictable{15-12} = 0b1111;
4061 // CMN register-register/shift
4062 def CMNzrr : AI1<0b1011, (outs), (ins GPR:$Rn, GPR:$Rm), DPFrm, IIC_iCMPr,
4063 "cmn", "\t$Rn, $Rm",
4064 [(BinOpFrag<(ARMcmpZ node:$LHS,(ineg node:$RHS))>
4065 GPR:$Rn, GPR:$Rm)]>, Sched<[WriteCMP, ReadALU, ReadALU]> {
4068 let isCommutable = 1;
4071 let Inst{19-16} = Rn;
4072 let Inst{15-12} = 0b0000;
4073 let Inst{11-4} = 0b00000000;
4076 let Unpredictable{15-12} = 0b1111;
4079 def CMNzrsi : AI1<0b1011, (outs),
4080 (ins GPR:$Rn, so_reg_imm:$shift), DPSoRegImmFrm, IIC_iCMPsr,
4081 "cmn", "\t$Rn, $shift",
4082 [(BinOpFrag<(ARMcmpZ node:$LHS,(ineg node:$RHS))>
4083 GPR:$Rn, so_reg_imm:$shift)]>,
4084 Sched<[WriteCMPsi, ReadALU]> {
4089 let Inst{19-16} = Rn;
4090 let Inst{15-12} = 0b0000;
4091 let Inst{11-5} = shift{11-5};
4093 let Inst{3-0} = shift{3-0};
4095 let Unpredictable{15-12} = 0b1111;
4098 def CMNzrsr : AI1<0b1011, (outs),
4099 (ins GPRnopc:$Rn, so_reg_reg:$shift), DPSoRegRegFrm, IIC_iCMPsr,
4100 "cmn", "\t$Rn, $shift",
4101 [(BinOpFrag<(ARMcmpZ node:$LHS,(ineg node:$RHS))>
4102 GPRnopc:$Rn, so_reg_reg:$shift)]>,
4103 Sched<[WriteCMPsr, ReadALU]> {
4108 let Inst{19-16} = Rn;
4109 let Inst{15-12} = 0b0000;
4110 let Inst{11-8} = shift{11-8};
4112 let Inst{6-5} = shift{6-5};
4114 let Inst{3-0} = shift{3-0};
4116 let Unpredictable{15-12} = 0b1111;
4121 def : ARMPat<(ARMcmp GPR:$src, so_imm_neg:$imm),
4122 (CMNri GPR:$src, so_imm_neg:$imm)>;
4124 def : ARMPat<(ARMcmpZ GPR:$src, so_imm_neg:$imm),
4125 (CMNri GPR:$src, so_imm_neg:$imm)>;
4127 // Note that TST/TEQ don't set all the same flags that CMP does!
4128 defm TST : AI1_cmp_irs<0b1000, "tst",
4129 IIC_iTSTi, IIC_iTSTr, IIC_iTSTsr,
4130 BinOpFrag<(ARMcmpZ (and_su node:$LHS, node:$RHS), 0)>, 1>;
4131 defm TEQ : AI1_cmp_irs<0b1001, "teq",
4132 IIC_iTSTi, IIC_iTSTr, IIC_iTSTsr,
4133 BinOpFrag<(ARMcmpZ (xor_su node:$LHS, node:$RHS), 0)>, 1>;
4135 // Pseudo i64 compares for some floating point compares.
4136 let usesCustomInserter = 1, isBranch = 1, isTerminator = 1,
4138 def BCCi64 : PseudoInst<(outs),
4139 (ins i32imm:$cc, GPR:$lhs1, GPR:$lhs2, GPR:$rhs1, GPR:$rhs2, brtarget:$dst),
4141 [(ARMBcci64 imm:$cc, GPR:$lhs1, GPR:$lhs2, GPR:$rhs1, GPR:$rhs2, bb:$dst)]>,
4144 def BCCZi64 : PseudoInst<(outs),
4145 (ins i32imm:$cc, GPR:$lhs1, GPR:$lhs2, brtarget:$dst), IIC_Br,
4146 [(ARMBcci64 imm:$cc, GPR:$lhs1, GPR:$lhs2, 0, 0, bb:$dst)]>,
4148 } // usesCustomInserter
4151 // Conditional moves
4152 // FIXME: should be able to write a pattern for ARMcmov, but can't use
4153 // a two-value operand where a dag node expects two operands. :(
4154 let neverHasSideEffects = 1 in {
4156 let isCommutable = 1, isSelect = 1 in
4157 def MOVCCr : ARMPseudoInst<(outs GPR:$Rd), (ins GPR:$false, GPR:$Rm, pred:$p),
4159 [/*(set GPR:$Rd, (ARMcmov GPR:$false, GPR:$Rm, imm:$cc, CCR:$ccr))*/]>,
4160 RegConstraint<"$false = $Rd">, Sched<[WriteALU]>;
4162 def MOVCCsi : ARMPseudoInst<(outs GPR:$Rd),
4163 (ins GPR:$false, so_reg_imm:$shift, pred:$p),
4165 [/*(set GPR:$Rd, (ARMcmov GPR:$false, so_reg_imm:$shift,
4166 imm:$cc, CCR:$ccr))*/]>,
4167 RegConstraint<"$false = $Rd">, Sched<[WriteALU]>;
4168 def MOVCCsr : ARMPseudoInst<(outs GPR:$Rd),
4169 (ins GPR:$false, so_reg_reg:$shift, pred:$p),
4171 [/*(set GPR:$Rd, (ARMcmov GPR:$false, so_reg_reg:$shift,
4172 imm:$cc, CCR:$ccr))*/]>,
4173 RegConstraint<"$false = $Rd">, Sched<[WriteALU]>;
4176 let isMoveImm = 1 in
4177 def MOVCCi16 : ARMPseudoInst<(outs GPR:$Rd),
4178 (ins GPR:$false, imm0_65535_expr:$imm, pred:$p),
4181 RegConstraint<"$false = $Rd">, Requires<[IsARM, HasV6T2]>,
4184 let isMoveImm = 1 in
4185 def MOVCCi : ARMPseudoInst<(outs GPR:$Rd),
4186 (ins GPR:$false, so_imm:$imm, pred:$p),
4188 [/*(set GPR:$Rd, (ARMcmov GPR:$false, so_imm:$imm, imm:$cc, CCR:$ccr))*/]>,
4189 RegConstraint<"$false = $Rd">, Sched<[WriteALU]>;
4191 // Two instruction predicate mov immediate.
4192 let isMoveImm = 1 in
4193 def MOVCCi32imm : ARMPseudoInst<(outs GPR:$Rd),
4194 (ins GPR:$false, i32imm:$src, pred:$p),
4195 8, IIC_iCMOVix2, []>, RegConstraint<"$false = $Rd">;
4197 let isMoveImm = 1 in
4198 def MVNCCi : ARMPseudoInst<(outs GPR:$Rd),
4199 (ins GPR:$false, so_imm:$imm, pred:$p),
4201 [/*(set GPR:$Rd, (ARMcmov GPR:$false, so_imm_not:$imm, imm:$cc, CCR:$ccr))*/]>,
4202 RegConstraint<"$false = $Rd">, Sched<[WriteALU]>;
4204 } // neverHasSideEffects
4207 //===----------------------------------------------------------------------===//
4208 // Atomic operations intrinsics
4211 def MemBarrierOptOperand : AsmOperandClass {
4212 let Name = "MemBarrierOpt";
4213 let ParserMethod = "parseMemBarrierOptOperand";
4215 def memb_opt : Operand<i32> {
4216 let PrintMethod = "printMemBOption";
4217 let ParserMatchClass = MemBarrierOptOperand;
4218 let DecoderMethod = "DecodeMemBarrierOption";
4221 def InstSyncBarrierOptOperand : AsmOperandClass {
4222 let Name = "InstSyncBarrierOpt";
4223 let ParserMethod = "parseInstSyncBarrierOptOperand";
4225 def instsyncb_opt : Operand<i32> {
4226 let PrintMethod = "printInstSyncBOption";
4227 let ParserMatchClass = InstSyncBarrierOptOperand;
4228 let DecoderMethod = "DecodeInstSyncBarrierOption";
4231 // memory barriers protect the atomic sequences
4232 let hasSideEffects = 1 in {
4233 def DMB : AInoP<(outs), (ins memb_opt:$opt), MiscFrm, NoItinerary,
4234 "dmb", "\t$opt", [(ARMMemBarrier (i32 imm:$opt))]>,
4235 Requires<[IsARM, HasDB]> {
4237 let Inst{31-4} = 0xf57ff05;
4238 let Inst{3-0} = opt;
4242 def DSB : AInoP<(outs), (ins memb_opt:$opt), MiscFrm, NoItinerary,
4243 "dsb", "\t$opt", []>,
4244 Requires<[IsARM, HasDB]> {
4246 let Inst{31-4} = 0xf57ff04;
4247 let Inst{3-0} = opt;
4250 // ISB has only full system option
4251 def ISB : AInoP<(outs), (ins instsyncb_opt:$opt), MiscFrm, NoItinerary,
4252 "isb", "\t$opt", []>,
4253 Requires<[IsARM, HasDB]> {
4255 let Inst{31-4} = 0xf57ff06;
4256 let Inst{3-0} = opt;
4259 // Pseudo instruction that combines movs + predicated rsbmi
4260 // to implement integer ABS
4261 let usesCustomInserter = 1, Defs = [CPSR] in
4262 def ABS : ARMPseudoInst<(outs GPR:$dst), (ins GPR:$src), 8, NoItinerary, []>;
4264 let usesCustomInserter = 1 in {
4265 let Defs = [CPSR] in {
4266 def ATOMIC_LOAD_ADD_I8 : PseudoInst<
4267 (outs GPR:$dst), (ins GPR:$ptr, GPR:$incr), NoItinerary,
4268 [(set GPR:$dst, (atomic_load_add_8 GPR:$ptr, GPR:$incr))]>;
4269 def ATOMIC_LOAD_SUB_I8 : PseudoInst<
4270 (outs GPR:$dst), (ins GPR:$ptr, GPR:$incr), NoItinerary,
4271 [(set GPR:$dst, (atomic_load_sub_8 GPR:$ptr, GPR:$incr))]>;
4272 def ATOMIC_LOAD_AND_I8 : PseudoInst<
4273 (outs GPR:$dst), (ins GPR:$ptr, GPR:$incr), NoItinerary,
4274 [(set GPR:$dst, (atomic_load_and_8 GPR:$ptr, GPR:$incr))]>;
4275 def ATOMIC_LOAD_OR_I8 : PseudoInst<
4276 (outs GPR:$dst), (ins GPR:$ptr, GPR:$incr), NoItinerary,
4277 [(set GPR:$dst, (atomic_load_or_8 GPR:$ptr, GPR:$incr))]>;
4278 def ATOMIC_LOAD_XOR_I8 : PseudoInst<
4279 (outs GPR:$dst), (ins GPR:$ptr, GPR:$incr), NoItinerary,
4280 [(set GPR:$dst, (atomic_load_xor_8 GPR:$ptr, GPR:$incr))]>;
4281 def ATOMIC_LOAD_NAND_I8 : PseudoInst<
4282 (outs GPR:$dst), (ins GPR:$ptr, GPR:$incr), NoItinerary,
4283 [(set GPR:$dst, (atomic_load_nand_8 GPR:$ptr, GPR:$incr))]>;
4284 def ATOMIC_LOAD_MIN_I8 : PseudoInst<
4285 (outs GPR:$dst), (ins GPR:$ptr, GPR:$val), NoItinerary,
4286 [(set GPR:$dst, (atomic_load_min_8 GPR:$ptr, GPR:$val))]>;
4287 def ATOMIC_LOAD_MAX_I8 : PseudoInst<
4288 (outs GPR:$dst), (ins GPR:$ptr, GPR:$val), NoItinerary,
4289 [(set GPR:$dst, (atomic_load_max_8 GPR:$ptr, GPR:$val))]>;
4290 def ATOMIC_LOAD_UMIN_I8 : PseudoInst<
4291 (outs GPR:$dst), (ins GPR:$ptr, GPR:$val), NoItinerary,
4292 [(set GPR:$dst, (atomic_load_umin_8 GPR:$ptr, GPR:$val))]>;
4293 def ATOMIC_LOAD_UMAX_I8 : PseudoInst<
4294 (outs GPR:$dst), (ins GPR:$ptr, GPR:$val), NoItinerary,
4295 [(set GPR:$dst, (atomic_load_umax_8 GPR:$ptr, GPR:$val))]>;
4296 def ATOMIC_LOAD_ADD_I16 : PseudoInst<
4297 (outs GPR:$dst), (ins GPR:$ptr, GPR:$incr), NoItinerary,
4298 [(set GPR:$dst, (atomic_load_add_16 GPR:$ptr, GPR:$incr))]>;
4299 def ATOMIC_LOAD_SUB_I16 : PseudoInst<
4300 (outs GPR:$dst), (ins GPR:$ptr, GPR:$incr), NoItinerary,
4301 [(set GPR:$dst, (atomic_load_sub_16 GPR:$ptr, GPR:$incr))]>;
4302 def ATOMIC_LOAD_AND_I16 : PseudoInst<
4303 (outs GPR:$dst), (ins GPR:$ptr, GPR:$incr), NoItinerary,
4304 [(set GPR:$dst, (atomic_load_and_16 GPR:$ptr, GPR:$incr))]>;
4305 def ATOMIC_LOAD_OR_I16 : PseudoInst<
4306 (outs GPR:$dst), (ins GPR:$ptr, GPR:$incr), NoItinerary,
4307 [(set GPR:$dst, (atomic_load_or_16 GPR:$ptr, GPR:$incr))]>;
4308 def ATOMIC_LOAD_XOR_I16 : PseudoInst<
4309 (outs GPR:$dst), (ins GPR:$ptr, GPR:$incr), NoItinerary,
4310 [(set GPR:$dst, (atomic_load_xor_16 GPR:$ptr, GPR:$incr))]>;
4311 def ATOMIC_LOAD_NAND_I16 : PseudoInst<
4312 (outs GPR:$dst), (ins GPR:$ptr, GPR:$incr), NoItinerary,
4313 [(set GPR:$dst, (atomic_load_nand_16 GPR:$ptr, GPR:$incr))]>;
4314 def ATOMIC_LOAD_MIN_I16 : PseudoInst<
4315 (outs GPR:$dst), (ins GPR:$ptr, GPR:$val), NoItinerary,
4316 [(set GPR:$dst, (atomic_load_min_16 GPR:$ptr, GPR:$val))]>;
4317 def ATOMIC_LOAD_MAX_I16 : PseudoInst<
4318 (outs GPR:$dst), (ins GPR:$ptr, GPR:$val), NoItinerary,
4319 [(set GPR:$dst, (atomic_load_max_16 GPR:$ptr, GPR:$val))]>;
4320 def ATOMIC_LOAD_UMIN_I16 : PseudoInst<
4321 (outs GPR:$dst), (ins GPR:$ptr, GPR:$val), NoItinerary,
4322 [(set GPR:$dst, (atomic_load_umin_16 GPR:$ptr, GPR:$val))]>;
4323 def ATOMIC_LOAD_UMAX_I16 : PseudoInst<
4324 (outs GPR:$dst), (ins GPR:$ptr, GPR:$val), NoItinerary,
4325 [(set GPR:$dst, (atomic_load_umax_16 GPR:$ptr, GPR:$val))]>;
4326 def ATOMIC_LOAD_ADD_I32 : PseudoInst<
4327 (outs GPR:$dst), (ins GPR:$ptr, GPR:$incr), NoItinerary,
4328 [(set GPR:$dst, (atomic_load_add_32 GPR:$ptr, GPR:$incr))]>;
4329 def ATOMIC_LOAD_SUB_I32 : PseudoInst<
4330 (outs GPR:$dst), (ins GPR:$ptr, GPR:$incr), NoItinerary,
4331 [(set GPR:$dst, (atomic_load_sub_32 GPR:$ptr, GPR:$incr))]>;
4332 def ATOMIC_LOAD_AND_I32 : PseudoInst<
4333 (outs GPR:$dst), (ins GPR:$ptr, GPR:$incr), NoItinerary,
4334 [(set GPR:$dst, (atomic_load_and_32 GPR:$ptr, GPR:$incr))]>;
4335 def ATOMIC_LOAD_OR_I32 : PseudoInst<
4336 (outs GPR:$dst), (ins GPR:$ptr, GPR:$incr), NoItinerary,
4337 [(set GPR:$dst, (atomic_load_or_32 GPR:$ptr, GPR:$incr))]>;
4338 def ATOMIC_LOAD_XOR_I32 : PseudoInst<
4339 (outs GPR:$dst), (ins GPR:$ptr, GPR:$incr), NoItinerary,
4340 [(set GPR:$dst, (atomic_load_xor_32 GPR:$ptr, GPR:$incr))]>;
4341 def ATOMIC_LOAD_NAND_I32 : PseudoInst<
4342 (outs GPR:$dst), (ins GPR:$ptr, GPR:$incr), NoItinerary,
4343 [(set GPR:$dst, (atomic_load_nand_32 GPR:$ptr, GPR:$incr))]>;
4344 def ATOMIC_LOAD_MIN_I32 : PseudoInst<
4345 (outs GPR:$dst), (ins GPR:$ptr, GPR:$val), NoItinerary,
4346 [(set GPR:$dst, (atomic_load_min_32 GPR:$ptr, GPR:$val))]>;
4347 def ATOMIC_LOAD_MAX_I32 : PseudoInst<
4348 (outs GPR:$dst), (ins GPR:$ptr, GPR:$val), NoItinerary,
4349 [(set GPR:$dst, (atomic_load_max_32 GPR:$ptr, GPR:$val))]>;
4350 def ATOMIC_LOAD_UMIN_I32 : PseudoInst<
4351 (outs GPR:$dst), (ins GPR:$ptr, GPR:$val), NoItinerary,
4352 [(set GPR:$dst, (atomic_load_umin_32 GPR:$ptr, GPR:$val))]>;
4353 def ATOMIC_LOAD_UMAX_I32 : PseudoInst<
4354 (outs GPR:$dst), (ins GPR:$ptr, GPR:$val), NoItinerary,
4355 [(set GPR:$dst, (atomic_load_umax_32 GPR:$ptr, GPR:$val))]>;
4357 def ATOMIC_SWAP_I8 : PseudoInst<
4358 (outs GPR:$dst), (ins GPR:$ptr, GPR:$new), NoItinerary,
4359 [(set GPR:$dst, (atomic_swap_8 GPR:$ptr, GPR:$new))]>;
4360 def ATOMIC_SWAP_I16 : PseudoInst<
4361 (outs GPR:$dst), (ins GPR:$ptr, GPR:$new), NoItinerary,
4362 [(set GPR:$dst, (atomic_swap_16 GPR:$ptr, GPR:$new))]>;
4363 def ATOMIC_SWAP_I32 : PseudoInst<
4364 (outs GPR:$dst), (ins GPR:$ptr, GPR:$new), NoItinerary,
4365 [(set GPR:$dst, (atomic_swap_32 GPR:$ptr, GPR:$new))]>;
4367 def ATOMIC_CMP_SWAP_I8 : PseudoInst<
4368 (outs GPR:$dst), (ins GPR:$ptr, GPR:$old, GPR:$new), NoItinerary,
4369 [(set GPR:$dst, (atomic_cmp_swap_8 GPR:$ptr, GPR:$old, GPR:$new))]>;
4370 def ATOMIC_CMP_SWAP_I16 : PseudoInst<
4371 (outs GPR:$dst), (ins GPR:$ptr, GPR:$old, GPR:$new), NoItinerary,
4372 [(set GPR:$dst, (atomic_cmp_swap_16 GPR:$ptr, GPR:$old, GPR:$new))]>;
4373 def ATOMIC_CMP_SWAP_I32 : PseudoInst<
4374 (outs GPR:$dst), (ins GPR:$ptr, GPR:$old, GPR:$new), NoItinerary,
4375 [(set GPR:$dst, (atomic_cmp_swap_32 GPR:$ptr, GPR:$old, GPR:$new))]>;
4379 let usesCustomInserter = 1 in {
4380 def COPY_STRUCT_BYVAL_I32 : PseudoInst<
4381 (outs), (ins GPR:$dst, GPR:$src, i32imm:$size, i32imm:$alignment),
4383 [(ARMcopystructbyval GPR:$dst, GPR:$src, imm:$size, imm:$alignment)]>;
4386 let mayLoad = 1 in {
4387 def LDREXB : AIldrex<0b10, (outs GPR:$Rt), (ins addr_offset_none:$addr),
4389 "ldrexb", "\t$Rt, $addr", []>;
4390 def LDREXH : AIldrex<0b11, (outs GPR:$Rt), (ins addr_offset_none:$addr),
4391 NoItinerary, "ldrexh", "\t$Rt, $addr", []>;
4392 def LDREX : AIldrex<0b00, (outs GPR:$Rt), (ins addr_offset_none:$addr),
4393 NoItinerary, "ldrex", "\t$Rt, $addr", []>;
4394 let hasExtraDefRegAllocReq = 1 in
4395 def LDREXD: AIldrex<0b01, (outs GPRPairOp:$Rt),(ins addr_offset_none:$addr),
4396 NoItinerary, "ldrexd", "\t$Rt, $addr", []> {
4397 let DecoderMethod = "DecodeDoubleRegLoad";
4401 let mayStore = 1, Constraints = "@earlyclobber $Rd" in {
4402 def STREXB: AIstrex<0b10, (outs GPR:$Rd), (ins GPR:$Rt, addr_offset_none:$addr),
4403 NoItinerary, "strexb", "\t$Rd, $Rt, $addr", []>;
4404 def STREXH: AIstrex<0b11, (outs GPR:$Rd), (ins GPR:$Rt, addr_offset_none:$addr),
4405 NoItinerary, "strexh", "\t$Rd, $Rt, $addr", []>;
4406 def STREX : AIstrex<0b00, (outs GPR:$Rd), (ins GPR:$Rt, addr_offset_none:$addr),
4407 NoItinerary, "strex", "\t$Rd, $Rt, $addr", []>;
4408 let hasExtraSrcRegAllocReq = 1 in
4409 def STREXD : AIstrex<0b01, (outs GPR:$Rd),
4410 (ins GPRPairOp:$Rt, addr_offset_none:$addr),
4411 NoItinerary, "strexd", "\t$Rd, $Rt, $addr", []> {
4412 let DecoderMethod = "DecodeDoubleRegStore";
4417 def CLREX : AXI<(outs), (ins), MiscFrm, NoItinerary, "clrex", []>,
4418 Requires<[IsARM, HasV7]> {
4419 let Inst{31-0} = 0b11110101011111111111000000011111;
4422 // SWP/SWPB are deprecated in V6/V7.
4423 let mayLoad = 1, mayStore = 1 in {
4424 def SWP : AIswp<0, (outs GPRnopc:$Rt),
4425 (ins GPRnopc:$Rt2, addr_offset_none:$addr), "swp", []>;
4426 def SWPB: AIswp<1, (outs GPRnopc:$Rt),
4427 (ins GPRnopc:$Rt2, addr_offset_none:$addr), "swpb", []>;
4430 //===----------------------------------------------------------------------===//
4431 // Coprocessor Instructions.
4434 def CDP : ABI<0b1110, (outs), (ins p_imm:$cop, imm0_15:$opc1,
4435 c_imm:$CRd, c_imm:$CRn, c_imm:$CRm, imm0_7:$opc2),
4436 NoItinerary, "cdp", "\t$cop, $opc1, $CRd, $CRn, $CRm, $opc2",
4437 [(int_arm_cdp imm:$cop, imm:$opc1, imm:$CRd, imm:$CRn,
4438 imm:$CRm, imm:$opc2)]> {
4446 let Inst{3-0} = CRm;
4448 let Inst{7-5} = opc2;
4449 let Inst{11-8} = cop;
4450 let Inst{15-12} = CRd;
4451 let Inst{19-16} = CRn;
4452 let Inst{23-20} = opc1;
4455 def CDP2 : ABXI<0b1110, (outs), (ins p_imm:$cop, imm0_15:$opc1,
4456 c_imm:$CRd, c_imm:$CRn, c_imm:$CRm, imm0_7:$opc2),
4457 NoItinerary, "cdp2\t$cop, $opc1, $CRd, $CRn, $CRm, $opc2",
4458 [(int_arm_cdp2 imm:$cop, imm:$opc1, imm:$CRd, imm:$CRn,
4459 imm:$CRm, imm:$opc2)]> {
4460 let Inst{31-28} = 0b1111;
4468 let Inst{3-0} = CRm;
4470 let Inst{7-5} = opc2;
4471 let Inst{11-8} = cop;
4472 let Inst{15-12} = CRd;
4473 let Inst{19-16} = CRn;
4474 let Inst{23-20} = opc1;
4477 class ACI<dag oops, dag iops, string opc, string asm,
4478 IndexMode im = IndexModeNone>
4479 : I<oops, iops, AddrModeNone, 4, im, BrFrm, NoItinerary,
4481 let Inst{27-25} = 0b110;
4483 class ACInoP<dag oops, dag iops, string opc, string asm,
4484 IndexMode im = IndexModeNone>
4485 : InoP<oops, iops, AddrModeNone, 4, im, BrFrm, NoItinerary,
4487 let Inst{31-28} = 0b1111;
4488 let Inst{27-25} = 0b110;
4490 multiclass LdStCop<bit load, bit Dbit, string asm> {
4491 def _OFFSET : ACI<(outs), (ins p_imm:$cop, c_imm:$CRd, addrmode5:$addr),
4492 asm, "\t$cop, $CRd, $addr"> {
4496 let Inst{24} = 1; // P = 1
4497 let Inst{23} = addr{8};
4498 let Inst{22} = Dbit;
4499 let Inst{21} = 0; // W = 0
4500 let Inst{20} = load;
4501 let Inst{19-16} = addr{12-9};
4502 let Inst{15-12} = CRd;
4503 let Inst{11-8} = cop;
4504 let Inst{7-0} = addr{7-0};
4505 let DecoderMethod = "DecodeCopMemInstruction";
4507 def _PRE : ACI<(outs), (ins p_imm:$cop, c_imm:$CRd, addrmode5_pre:$addr),
4508 asm, "\t$cop, $CRd, $addr!", IndexModePre> {
4512 let Inst{24} = 1; // P = 1
4513 let Inst{23} = addr{8};
4514 let Inst{22} = Dbit;
4515 let Inst{21} = 1; // W = 1
4516 let Inst{20} = load;
4517 let Inst{19-16} = addr{12-9};
4518 let Inst{15-12} = CRd;
4519 let Inst{11-8} = cop;
4520 let Inst{7-0} = addr{7-0};
4521 let DecoderMethod = "DecodeCopMemInstruction";
4523 def _POST: ACI<(outs), (ins p_imm:$cop, c_imm:$CRd, addr_offset_none:$addr,
4524 postidx_imm8s4:$offset),
4525 asm, "\t$cop, $CRd, $addr, $offset", IndexModePost> {
4530 let Inst{24} = 0; // P = 0
4531 let Inst{23} = offset{8};
4532 let Inst{22} = Dbit;
4533 let Inst{21} = 1; // W = 1
4534 let Inst{20} = load;
4535 let Inst{19-16} = addr;
4536 let Inst{15-12} = CRd;
4537 let Inst{11-8} = cop;
4538 let Inst{7-0} = offset{7-0};
4539 let DecoderMethod = "DecodeCopMemInstruction";
4541 def _OPTION : ACI<(outs),
4542 (ins p_imm:$cop, c_imm:$CRd, addr_offset_none:$addr,
4543 coproc_option_imm:$option),
4544 asm, "\t$cop, $CRd, $addr, $option"> {
4549 let Inst{24} = 0; // P = 0
4550 let Inst{23} = 1; // U = 1
4551 let Inst{22} = Dbit;
4552 let Inst{21} = 0; // W = 0
4553 let Inst{20} = load;
4554 let Inst{19-16} = addr;
4555 let Inst{15-12} = CRd;
4556 let Inst{11-8} = cop;
4557 let Inst{7-0} = option;
4558 let DecoderMethod = "DecodeCopMemInstruction";
4561 multiclass LdSt2Cop<bit load, bit Dbit, string asm> {
4562 def _OFFSET : ACInoP<(outs), (ins p_imm:$cop, c_imm:$CRd, addrmode5:$addr),
4563 asm, "\t$cop, $CRd, $addr"> {
4567 let Inst{24} = 1; // P = 1
4568 let Inst{23} = addr{8};
4569 let Inst{22} = Dbit;
4570 let Inst{21} = 0; // W = 0
4571 let Inst{20} = load;
4572 let Inst{19-16} = addr{12-9};
4573 let Inst{15-12} = CRd;
4574 let Inst{11-8} = cop;
4575 let Inst{7-0} = addr{7-0};
4576 let DecoderMethod = "DecodeCopMemInstruction";
4578 def _PRE : ACInoP<(outs), (ins p_imm:$cop, c_imm:$CRd, addrmode5_pre:$addr),
4579 asm, "\t$cop, $CRd, $addr!", IndexModePre> {
4583 let Inst{24} = 1; // P = 1
4584 let Inst{23} = addr{8};
4585 let Inst{22} = Dbit;
4586 let Inst{21} = 1; // W = 1
4587 let Inst{20} = load;
4588 let Inst{19-16} = addr{12-9};
4589 let Inst{15-12} = CRd;
4590 let Inst{11-8} = cop;
4591 let Inst{7-0} = addr{7-0};
4592 let DecoderMethod = "DecodeCopMemInstruction";
4594 def _POST: ACInoP<(outs), (ins p_imm:$cop, c_imm:$CRd, addr_offset_none:$addr,
4595 postidx_imm8s4:$offset),
4596 asm, "\t$cop, $CRd, $addr, $offset", IndexModePost> {
4601 let Inst{24} = 0; // P = 0
4602 let Inst{23} = offset{8};
4603 let Inst{22} = Dbit;
4604 let Inst{21} = 1; // W = 1
4605 let Inst{20} = load;
4606 let Inst{19-16} = addr;
4607 let Inst{15-12} = CRd;
4608 let Inst{11-8} = cop;
4609 let Inst{7-0} = offset{7-0};
4610 let DecoderMethod = "DecodeCopMemInstruction";
4612 def _OPTION : ACInoP<(outs),
4613 (ins p_imm:$cop, c_imm:$CRd, addr_offset_none:$addr,
4614 coproc_option_imm:$option),
4615 asm, "\t$cop, $CRd, $addr, $option"> {
4620 let Inst{24} = 0; // P = 0
4621 let Inst{23} = 1; // U = 1
4622 let Inst{22} = Dbit;
4623 let Inst{21} = 0; // W = 0
4624 let Inst{20} = load;
4625 let Inst{19-16} = addr;
4626 let Inst{15-12} = CRd;
4627 let Inst{11-8} = cop;
4628 let Inst{7-0} = option;
4629 let DecoderMethod = "DecodeCopMemInstruction";
4633 defm LDC : LdStCop <1, 0, "ldc">;
4634 defm LDCL : LdStCop <1, 1, "ldcl">;
4635 defm STC : LdStCop <0, 0, "stc">;
4636 defm STCL : LdStCop <0, 1, "stcl">;
4637 defm LDC2 : LdSt2Cop<1, 0, "ldc2">;
4638 defm LDC2L : LdSt2Cop<1, 1, "ldc2l">;
4639 defm STC2 : LdSt2Cop<0, 0, "stc2">;
4640 defm STC2L : LdSt2Cop<0, 1, "stc2l">;
4642 //===----------------------------------------------------------------------===//
4643 // Move between coprocessor and ARM core register.
4646 class MovRCopro<string opc, bit direction, dag oops, dag iops,
4648 : ABI<0b1110, oops, iops, NoItinerary, opc,
4649 "\t$cop, $opc1, $Rt, $CRn, $CRm, $opc2", pattern> {
4650 let Inst{20} = direction;
4660 let Inst{15-12} = Rt;
4661 let Inst{11-8} = cop;
4662 let Inst{23-21} = opc1;
4663 let Inst{7-5} = opc2;
4664 let Inst{3-0} = CRm;
4665 let Inst{19-16} = CRn;
4668 def MCR : MovRCopro<"mcr", 0 /* from ARM core register to coprocessor */,
4670 (ins p_imm:$cop, imm0_7:$opc1, GPR:$Rt, c_imm:$CRn,
4671 c_imm:$CRm, imm0_7:$opc2),
4672 [(int_arm_mcr imm:$cop, imm:$opc1, GPR:$Rt, imm:$CRn,
4673 imm:$CRm, imm:$opc2)]>;
4674 def : ARMInstAlias<"mcr${p} $cop, $opc1, $Rt, $CRn, $CRm",
4675 (MCR p_imm:$cop, imm0_7:$opc1, GPR:$Rt, c_imm:$CRn,
4676 c_imm:$CRm, 0, pred:$p)>;
4677 def MRC : MovRCopro<"mrc", 1 /* from coprocessor to ARM core register */,
4678 (outs GPRwithAPSR:$Rt),
4679 (ins p_imm:$cop, imm0_7:$opc1, c_imm:$CRn, c_imm:$CRm,
4681 def : ARMInstAlias<"mrc${p} $cop, $opc1, $Rt, $CRn, $CRm",
4682 (MRC GPRwithAPSR:$Rt, p_imm:$cop, imm0_7:$opc1, c_imm:$CRn,
4683 c_imm:$CRm, 0, pred:$p)>;
4685 def : ARMPat<(int_arm_mrc imm:$cop, imm:$opc1, imm:$CRn, imm:$CRm, imm:$opc2),
4686 (MRC imm:$cop, imm:$opc1, imm:$CRn, imm:$CRm, imm:$opc2)>;
4688 class MovRCopro2<string opc, bit direction, dag oops, dag iops,
4690 : ABXI<0b1110, oops, iops, NoItinerary,
4691 !strconcat(opc, "\t$cop, $opc1, $Rt, $CRn, $CRm, $opc2"), pattern> {
4692 let Inst{31-24} = 0b11111110;
4693 let Inst{20} = direction;
4703 let Inst{15-12} = Rt;
4704 let Inst{11-8} = cop;
4705 let Inst{23-21} = opc1;
4706 let Inst{7-5} = opc2;
4707 let Inst{3-0} = CRm;
4708 let Inst{19-16} = CRn;
4711 def MCR2 : MovRCopro2<"mcr2", 0 /* from ARM core register to coprocessor */,
4713 (ins p_imm:$cop, imm0_7:$opc1, GPR:$Rt, c_imm:$CRn,
4714 c_imm:$CRm, imm0_7:$opc2),
4715 [(int_arm_mcr2 imm:$cop, imm:$opc1, GPR:$Rt, imm:$CRn,
4716 imm:$CRm, imm:$opc2)]>;
4717 def : ARMInstAlias<"mcr2$ $cop, $opc1, $Rt, $CRn, $CRm",
4718 (MCR2 p_imm:$cop, imm0_7:$opc1, GPR:$Rt, c_imm:$CRn,
4720 def MRC2 : MovRCopro2<"mrc2", 1 /* from coprocessor to ARM core register */,
4721 (outs GPRwithAPSR:$Rt),
4722 (ins p_imm:$cop, imm0_7:$opc1, c_imm:$CRn, c_imm:$CRm,
4724 def : ARMInstAlias<"mrc2$ $cop, $opc1, $Rt, $CRn, $CRm",
4725 (MRC2 GPRwithAPSR:$Rt, p_imm:$cop, imm0_7:$opc1, c_imm:$CRn,
4728 def : ARMV5TPat<(int_arm_mrc2 imm:$cop, imm:$opc1, imm:$CRn,
4729 imm:$CRm, imm:$opc2),
4730 (MRC2 imm:$cop, imm:$opc1, imm:$CRn, imm:$CRm, imm:$opc2)>;
4732 class MovRRCopro<string opc, bit direction, list<dag> pattern = []>
4733 : ABI<0b1100, (outs), (ins p_imm:$cop, imm0_15:$opc1,
4734 GPRnopc:$Rt, GPRnopc:$Rt2, c_imm:$CRm),
4735 NoItinerary, opc, "\t$cop, $opc1, $Rt, $Rt2, $CRm", pattern> {
4736 let Inst{23-21} = 0b010;
4737 let Inst{20} = direction;
4745 let Inst{15-12} = Rt;
4746 let Inst{19-16} = Rt2;
4747 let Inst{11-8} = cop;
4748 let Inst{7-4} = opc1;
4749 let Inst{3-0} = CRm;
4752 def MCRR : MovRRCopro<"mcrr", 0 /* from ARM core register to coprocessor */,
4753 [(int_arm_mcrr imm:$cop, imm:$opc1, GPRnopc:$Rt,
4754 GPRnopc:$Rt2, imm:$CRm)]>;
4755 def MRRC : MovRRCopro<"mrrc", 1 /* from coprocessor to ARM core register */>;
4757 class MovRRCopro2<string opc, bit direction, list<dag> pattern = []>
4758 : ABXI<0b1100, (outs), (ins p_imm:$cop, imm0_15:$opc1,
4759 GPRnopc:$Rt, GPRnopc:$Rt2, c_imm:$CRm), NoItinerary,
4760 !strconcat(opc, "\t$cop, $opc1, $Rt, $Rt2, $CRm"), pattern> {
4761 let Inst{31-28} = 0b1111;
4762 let Inst{23-21} = 0b010;
4763 let Inst{20} = direction;
4771 let Inst{15-12} = Rt;
4772 let Inst{19-16} = Rt2;
4773 let Inst{11-8} = cop;
4774 let Inst{7-4} = opc1;
4775 let Inst{3-0} = CRm;
4777 let DecoderMethod = "DecodeMRRC2";
4780 def MCRR2 : MovRRCopro2<"mcrr2", 0 /* from ARM core register to coprocessor */,
4781 [(int_arm_mcrr2 imm:$cop, imm:$opc1, GPRnopc:$Rt,
4782 GPRnopc:$Rt2, imm:$CRm)]>;
4783 def MRRC2 : MovRRCopro2<"mrrc2", 1 /* from coprocessor to ARM core register */>;
4785 //===----------------------------------------------------------------------===//
4786 // Move between special register and ARM core register
4789 // Move to ARM core register from Special Register
4790 def MRS : ABI<0b0001, (outs GPRnopc:$Rd), (ins), NoItinerary,
4791 "mrs", "\t$Rd, apsr", []> {
4793 let Inst{23-16} = 0b00001111;
4794 let Unpredictable{19-17} = 0b111;
4796 let Inst{15-12} = Rd;
4798 let Inst{11-0} = 0b000000000000;
4799 let Unpredictable{11-0} = 0b110100001111;
4802 def : InstAlias<"mrs${p} $Rd, cpsr", (MRS GPRnopc:$Rd, pred:$p)>,
4805 // The MRSsys instruction is the MRS instruction from the ARM ARM,
4806 // section B9.3.9, with the R bit set to 1.
4807 def MRSsys : ABI<0b0001, (outs GPRnopc:$Rd), (ins), NoItinerary,
4808 "mrs", "\t$Rd, spsr", []> {
4810 let Inst{23-16} = 0b01001111;
4811 let Unpredictable{19-16} = 0b1111;
4813 let Inst{15-12} = Rd;
4815 let Inst{11-0} = 0b000000000000;
4816 let Unpredictable{11-0} = 0b110100001111;
4819 // Move from ARM core register to Special Register
4821 // No need to have both system and application versions, the encodings are the
4822 // same and the assembly parser has no way to distinguish between them. The mask
4823 // operand contains the special register (R Bit) in bit 4 and bits 3-0 contains
4824 // the mask with the fields to be accessed in the special register.
4825 def MSR : ABI<0b0001, (outs), (ins msr_mask:$mask, GPR:$Rn), NoItinerary,
4826 "msr", "\t$mask, $Rn", []> {
4831 let Inst{22} = mask{4}; // R bit
4832 let Inst{21-20} = 0b10;
4833 let Inst{19-16} = mask{3-0};
4834 let Inst{15-12} = 0b1111;
4835 let Inst{11-4} = 0b00000000;
4839 def MSRi : ABI<0b0011, (outs), (ins msr_mask:$mask, so_imm:$a), NoItinerary,
4840 "msr", "\t$mask, $a", []> {
4845 let Inst{22} = mask{4}; // R bit
4846 let Inst{21-20} = 0b10;
4847 let Inst{19-16} = mask{3-0};
4848 let Inst{15-12} = 0b1111;
4852 //===----------------------------------------------------------------------===//
4856 // __aeabi_read_tp preserves the registers r1-r3.
4857 // This is a pseudo inst so that we can get the encoding right,
4858 // complete with fixup for the aeabi_read_tp function.
4860 Defs = [R0, R12, LR, CPSR], Uses = [SP] in {
4861 def TPsoft : PseudoInst<(outs), (ins), IIC_Br,
4862 [(set R0, ARMthread_pointer)]>, Sched<[WriteBr]>;
4865 //===----------------------------------------------------------------------===//
4866 // SJLJ Exception handling intrinsics
4867 // eh_sjlj_setjmp() is an instruction sequence to store the return
4868 // address and save #0 in R0 for the non-longjmp case.
4869 // Since by its nature we may be coming from some other function to get
4870 // here, and we're using the stack frame for the containing function to
4871 // save/restore registers, we can't keep anything live in regs across
4872 // the eh_sjlj_setjmp(), else it will almost certainly have been tromped upon
4873 // when we get here from a longjmp(). We force everything out of registers
4874 // except for our own input by listing the relevant registers in Defs. By
4875 // doing so, we also cause the prologue/epilogue code to actively preserve
4876 // all of the callee-saved resgisters, which is exactly what we want.
4877 // A constant value is passed in $val, and we use the location as a scratch.
4879 // These are pseudo-instructions and are lowered to individual MC-insts, so
4880 // no encoding information is necessary.
4882 [ R0, R1, R2, R3, R4, R5, R6, R7, R8, R9, R10, R11, R12, LR, CPSR,
4883 Q0, Q1, Q2, Q3, Q4, Q5, Q6, Q7, Q8, Q9, Q10, Q11, Q12, Q13, Q14, Q15 ],
4884 hasSideEffects = 1, isBarrier = 1, usesCustomInserter = 1 in {
4885 def Int_eh_sjlj_setjmp : PseudoInst<(outs), (ins GPR:$src, GPR:$val),
4887 [(set R0, (ARMeh_sjlj_setjmp GPR:$src, GPR:$val))]>,
4888 Requires<[IsARM, HasVFP2]>;
4892 [ R0, R1, R2, R3, R4, R5, R6, R7, R8, R9, R10, R11, R12, LR, CPSR ],
4893 hasSideEffects = 1, isBarrier = 1, usesCustomInserter = 1 in {
4894 def Int_eh_sjlj_setjmp_nofp : PseudoInst<(outs), (ins GPR:$src, GPR:$val),
4896 [(set R0, (ARMeh_sjlj_setjmp GPR:$src, GPR:$val))]>,
4897 Requires<[IsARM, NoVFP]>;
4900 // FIXME: Non-IOS version(s)
4901 let isBarrier = 1, hasSideEffects = 1, isTerminator = 1,
4902 Defs = [ R7, LR, SP ] in {
4903 def Int_eh_sjlj_longjmp : PseudoInst<(outs), (ins GPR:$src, GPR:$scratch),
4905 [(ARMeh_sjlj_longjmp GPR:$src, GPR:$scratch)]>,
4906 Requires<[IsARM, IsIOS]>;
4909 // eh.sjlj.dispatchsetup pseudo-instruction.
4910 // This pseudo is used for both ARM and Thumb. Any differences are handled when
4911 // the pseudo is expanded (which happens before any passes that need the
4912 // instruction size).
4913 let isBarrier = 1 in
4914 def Int_eh_sjlj_dispatchsetup : PseudoInst<(outs), (ins), NoItinerary, []>;
4917 //===----------------------------------------------------------------------===//
4918 // Non-Instruction Patterns
4921 // ARMv4 indirect branch using (MOVr PC, dst)
4922 let isBranch = 1, isTerminator = 1, isBarrier = 1, isIndirectBranch = 1 in
4923 def MOVPCRX : ARMPseudoExpand<(outs), (ins GPR:$dst),
4924 4, IIC_Br, [(brind GPR:$dst)],
4925 (MOVr PC, GPR:$dst, (ops 14, zero_reg), zero_reg)>,
4926 Requires<[IsARM, NoV4T]>, Sched<[WriteBr]>;
4928 // Large immediate handling.
4930 // 32-bit immediate using two piece so_imms or movw + movt.
4931 // This is a single pseudo instruction, the benefit is that it can be remat'd
4932 // as a single unit instead of having to handle reg inputs.
4933 // FIXME: Remove this when we can do generalized remat.
4934 let isReMaterializable = 1, isMoveImm = 1 in
4935 def MOVi32imm : PseudoInst<(outs GPR:$dst), (ins i32imm:$src), IIC_iMOVix2,
4936 [(set GPR:$dst, (arm_i32imm:$src))]>,
4939 // Pseudo instruction that combines movw + movt + add pc (if PIC).
4940 // It also makes it possible to rematerialize the instructions.
4941 // FIXME: Remove this when we can do generalized remat and when machine licm
4942 // can properly the instructions.
4943 let isReMaterializable = 1 in {
4944 def MOV_ga_pcrel : PseudoInst<(outs GPR:$dst), (ins i32imm:$addr),
4946 [(set GPR:$dst, (ARMWrapperPIC tglobaladdr:$addr))]>,
4947 Requires<[IsARM, UseMovt]>;
4949 def MOV_ga_dyn : PseudoInst<(outs GPR:$dst), (ins i32imm:$addr),
4951 [(set GPR:$dst, (ARMWrapperDYN tglobaladdr:$addr))]>,
4952 Requires<[IsARM, UseMovt]>;
4954 let AddedComplexity = 10 in
4955 def MOV_ga_pcrel_ldr : PseudoInst<(outs GPR:$dst), (ins i32imm:$addr),
4957 [(set GPR:$dst, (load (ARMWrapperPIC tglobaladdr:$addr)))]>,
4958 Requires<[IsARM, UseMovt]>;
4959 } // isReMaterializable
4961 // ConstantPool, GlobalAddress, and JumpTable
4962 def : ARMPat<(ARMWrapper tglobaladdr :$dst), (LEApcrel tglobaladdr :$dst)>,
4963 Requires<[IsARM, DontUseMovt]>;
4964 def : ARMPat<(ARMWrapper tconstpool :$dst), (LEApcrel tconstpool :$dst)>;
4965 def : ARMPat<(ARMWrapper tglobaladdr :$dst), (MOVi32imm tglobaladdr :$dst)>,
4966 Requires<[IsARM, UseMovt]>;
4967 def : ARMPat<(ARMWrapperJT tjumptable:$dst, imm:$id),
4968 (LEApcrelJT tjumptable:$dst, imm:$id)>;
4970 // TODO: add,sub,and, 3-instr forms?
4972 // Tail calls. These patterns also apply to Thumb mode.
4973 def : Pat<(ARMtcret tcGPR:$dst), (TCRETURNri tcGPR:$dst)>;
4974 def : Pat<(ARMtcret (i32 tglobaladdr:$dst)), (TCRETURNdi texternalsym:$dst)>;
4975 def : Pat<(ARMtcret (i32 texternalsym:$dst)), (TCRETURNdi texternalsym:$dst)>;
4978 def : ARMPat<(ARMcall texternalsym:$func), (BL texternalsym:$func)>;
4979 def : ARMPat<(ARMcall_nolink texternalsym:$func),
4980 (BMOVPCB_CALL texternalsym:$func)>;
4982 // zextload i1 -> zextload i8
4983 def : ARMPat<(zextloadi1 addrmode_imm12:$addr), (LDRBi12 addrmode_imm12:$addr)>;
4984 def : ARMPat<(zextloadi1 ldst_so_reg:$addr), (LDRBrs ldst_so_reg:$addr)>;
4986 // extload -> zextload
4987 def : ARMPat<(extloadi1 addrmode_imm12:$addr), (LDRBi12 addrmode_imm12:$addr)>;
4988 def : ARMPat<(extloadi1 ldst_so_reg:$addr), (LDRBrs ldst_so_reg:$addr)>;
4989 def : ARMPat<(extloadi8 addrmode_imm12:$addr), (LDRBi12 addrmode_imm12:$addr)>;
4990 def : ARMPat<(extloadi8 ldst_so_reg:$addr), (LDRBrs ldst_so_reg:$addr)>;
4992 def : ARMPat<(extloadi16 addrmode3:$addr), (LDRH addrmode3:$addr)>;
4994 def : ARMPat<(extloadi8 addrmodepc:$addr), (PICLDRB addrmodepc:$addr)>;
4995 def : ARMPat<(extloadi16 addrmodepc:$addr), (PICLDRH addrmodepc:$addr)>;
4998 def : ARMV5TEPat<(mul (sra (shl GPR:$a, (i32 16)), (i32 16)),
4999 (sra (shl GPR:$b, (i32 16)), (i32 16))),
5000 (SMULBB GPR:$a, GPR:$b)>;
5001 def : ARMV5TEPat<(mul sext_16_node:$a, sext_16_node:$b),
5002 (SMULBB GPR:$a, GPR:$b)>;
5003 def : ARMV5TEPat<(mul (sra (shl GPR:$a, (i32 16)), (i32 16)),
5004 (sra GPR:$b, (i32 16))),
5005 (SMULBT GPR:$a, GPR:$b)>;
5006 def : ARMV5TEPat<(mul sext_16_node:$a, (sra GPR:$b, (i32 16))),
5007 (SMULBT GPR:$a, GPR:$b)>;
5008 def : ARMV5TEPat<(mul (sra GPR:$a, (i32 16)),
5009 (sra (shl GPR:$b, (i32 16)), (i32 16))),
5010 (SMULTB GPR:$a, GPR:$b)>;
5011 def : ARMV5TEPat<(mul (sra GPR:$a, (i32 16)), sext_16_node:$b),
5012 (SMULTB GPR:$a, GPR:$b)>;
5013 def : ARMV5TEPat<(sra (mul GPR:$a, (sra (shl GPR:$b, (i32 16)), (i32 16))),
5015 (SMULWB GPR:$a, GPR:$b)>;
5016 def : ARMV5TEPat<(sra (mul GPR:$a, sext_16_node:$b), (i32 16)),
5017 (SMULWB GPR:$a, GPR:$b)>;
5019 def : ARMV5MOPat<(add GPR:$acc,
5020 (mul (sra (shl GPR:$a, (i32 16)), (i32 16)),
5021 (sra (shl GPR:$b, (i32 16)), (i32 16)))),
5022 (SMLABB GPR:$a, GPR:$b, GPR:$acc)>;
5023 def : ARMV5MOPat<(add GPR:$acc,
5024 (mul sext_16_node:$a, sext_16_node:$b)),
5025 (SMLABB GPR:$a, GPR:$b, GPR:$acc)>;
5026 def : ARMV5MOPat<(add GPR:$acc,
5027 (mul (sra (shl GPR:$a, (i32 16)), (i32 16)),
5028 (sra GPR:$b, (i32 16)))),
5029 (SMLABT GPR:$a, GPR:$b, GPR:$acc)>;
5030 def : ARMV5MOPat<(add GPR:$acc,
5031 (mul sext_16_node:$a, (sra GPR:$b, (i32 16)))),
5032 (SMLABT GPR:$a, GPR:$b, GPR:$acc)>;
5033 def : ARMV5MOPat<(add GPR:$acc,
5034 (mul (sra GPR:$a, (i32 16)),
5035 (sra (shl GPR:$b, (i32 16)), (i32 16)))),
5036 (SMLATB GPR:$a, GPR:$b, GPR:$acc)>;
5037 def : ARMV5MOPat<(add GPR:$acc,
5038 (mul (sra GPR:$a, (i32 16)), sext_16_node:$b)),
5039 (SMLATB GPR:$a, GPR:$b, GPR:$acc)>;
5040 def : ARMV5MOPat<(add GPR:$acc,
5041 (sra (mul GPR:$a, (sra (shl GPR:$b, (i32 16)), (i32 16))),
5043 (SMLAWB GPR:$a, GPR:$b, GPR:$acc)>;
5044 def : ARMV5MOPat<(add GPR:$acc,
5045 (sra (mul GPR:$a, sext_16_node:$b), (i32 16))),
5046 (SMLAWB GPR:$a, GPR:$b, GPR:$acc)>;
5049 // Pre-v7 uses MCR for synchronization barriers.
5050 def : ARMPat<(ARMMemBarrierMCR GPR:$zero), (MCR 15, 0, GPR:$zero, 7, 10, 5)>,
5051 Requires<[IsARM, HasV6]>;
5053 // SXT/UXT with no rotate
5054 let AddedComplexity = 16 in {
5055 def : ARMV6Pat<(and GPR:$Src, 0x000000FF), (UXTB GPR:$Src, 0)>;
5056 def : ARMV6Pat<(and GPR:$Src, 0x0000FFFF), (UXTH GPR:$Src, 0)>;
5057 def : ARMV6Pat<(and GPR:$Src, 0x00FF00FF), (UXTB16 GPR:$Src, 0)>;
5058 def : ARMV6Pat<(add GPR:$Rn, (and GPR:$Rm, 0x00FF)),
5059 (UXTAB GPR:$Rn, GPR:$Rm, 0)>;
5060 def : ARMV6Pat<(add GPR:$Rn, (and GPR:$Rm, 0xFFFF)),
5061 (UXTAH GPR:$Rn, GPR:$Rm, 0)>;
5064 def : ARMV6Pat<(sext_inreg GPR:$Src, i8), (SXTB GPR:$Src, 0)>;
5065 def : ARMV6Pat<(sext_inreg GPR:$Src, i16), (SXTH GPR:$Src, 0)>;
5067 def : ARMV6Pat<(add GPR:$Rn, (sext_inreg GPRnopc:$Rm, i8)),
5068 (SXTAB GPR:$Rn, GPRnopc:$Rm, 0)>;
5069 def : ARMV6Pat<(add GPR:$Rn, (sext_inreg GPRnopc:$Rm, i16)),
5070 (SXTAH GPR:$Rn, GPRnopc:$Rm, 0)>;
5072 // Atomic load/store patterns
5073 def : ARMPat<(atomic_load_8 ldst_so_reg:$src),
5074 (LDRBrs ldst_so_reg:$src)>;
5075 def : ARMPat<(atomic_load_8 addrmode_imm12:$src),
5076 (LDRBi12 addrmode_imm12:$src)>;
5077 def : ARMPat<(atomic_load_16 addrmode3:$src),
5078 (LDRH addrmode3:$src)>;
5079 def : ARMPat<(atomic_load_32 ldst_so_reg:$src),
5080 (LDRrs ldst_so_reg:$src)>;
5081 def : ARMPat<(atomic_load_32 addrmode_imm12:$src),
5082 (LDRi12 addrmode_imm12:$src)>;
5083 def : ARMPat<(atomic_store_8 ldst_so_reg:$ptr, GPR:$val),
5084 (STRBrs GPR:$val, ldst_so_reg:$ptr)>;
5085 def : ARMPat<(atomic_store_8 addrmode_imm12:$ptr, GPR:$val),
5086 (STRBi12 GPR:$val, addrmode_imm12:$ptr)>;
5087 def : ARMPat<(atomic_store_16 addrmode3:$ptr, GPR:$val),
5088 (STRH GPR:$val, addrmode3:$ptr)>;
5089 def : ARMPat<(atomic_store_32 ldst_so_reg:$ptr, GPR:$val),
5090 (STRrs GPR:$val, ldst_so_reg:$ptr)>;
5091 def : ARMPat<(atomic_store_32 addrmode_imm12:$ptr, GPR:$val),
5092 (STRi12 GPR:$val, addrmode_imm12:$ptr)>;
5095 //===----------------------------------------------------------------------===//
5099 include "ARMInstrThumb.td"
5101 //===----------------------------------------------------------------------===//
5105 include "ARMInstrThumb2.td"
5107 //===----------------------------------------------------------------------===//
5108 // Floating Point Support
5111 include "ARMInstrVFP.td"
5113 //===----------------------------------------------------------------------===//
5114 // Advanced SIMD (NEON) Support
5117 include "ARMInstrNEON.td"
5119 //===----------------------------------------------------------------------===//
5120 // Assembler aliases
5124 def : InstAlias<"dmb", (DMB 0xf)>, Requires<[IsARM, HasDB]>;
5125 def : InstAlias<"dsb", (DSB 0xf)>, Requires<[IsARM, HasDB]>;
5126 def : InstAlias<"isb", (ISB 0xf)>, Requires<[IsARM, HasDB]>;
5128 // System instructions
5129 def : MnemonicAlias<"swi", "svc">;
5131 // Load / Store Multiple
5132 def : MnemonicAlias<"ldmfd", "ldm">;
5133 def : MnemonicAlias<"ldmia", "ldm">;
5134 def : MnemonicAlias<"ldmea", "ldmdb">;
5135 def : MnemonicAlias<"stmfd", "stmdb">;
5136 def : MnemonicAlias<"stmia", "stm">;
5137 def : MnemonicAlias<"stmea", "stm">;
5139 // PKHBT/PKHTB with default shift amount. PKHTB is equivalent to PKHBT when the
5140 // shift amount is zero (i.e., unspecified).
5141 def : InstAlias<"pkhbt${p} $Rd, $Rn, $Rm",
5142 (PKHBT GPRnopc:$Rd, GPRnopc:$Rn, GPRnopc:$Rm, 0, pred:$p)>,
5143 Requires<[IsARM, HasV6]>;
5144 def : InstAlias<"pkhtb${p} $Rd, $Rn, $Rm",
5145 (PKHBT GPRnopc:$Rd, GPRnopc:$Rn, GPRnopc:$Rm, 0, pred:$p)>,
5146 Requires<[IsARM, HasV6]>;
5148 // PUSH/POP aliases for STM/LDM
5149 def : ARMInstAlias<"push${p} $regs", (STMDB_UPD SP, pred:$p, reglist:$regs)>;
5150 def : ARMInstAlias<"pop${p} $regs", (LDMIA_UPD SP, pred:$p, reglist:$regs)>;
5152 // SSAT/USAT optional shift operand.
5153 def : ARMInstAlias<"ssat${p} $Rd, $sat_imm, $Rn",
5154 (SSAT GPRnopc:$Rd, imm1_32:$sat_imm, GPRnopc:$Rn, 0, pred:$p)>;
5155 def : ARMInstAlias<"usat${p} $Rd, $sat_imm, $Rn",
5156 (USAT GPRnopc:$Rd, imm0_31:$sat_imm, GPRnopc:$Rn, 0, pred:$p)>;
5159 // Extend instruction optional rotate operand.
5160 def : ARMInstAlias<"sxtab${p} $Rd, $Rn, $Rm",
5161 (SXTAB GPRnopc:$Rd, GPR:$Rn, GPRnopc:$Rm, 0, pred:$p)>;
5162 def : ARMInstAlias<"sxtah${p} $Rd, $Rn, $Rm",
5163 (SXTAH GPRnopc:$Rd, GPR:$Rn, GPRnopc:$Rm, 0, pred:$p)>;
5164 def : ARMInstAlias<"sxtab16${p} $Rd, $Rn, $Rm",
5165 (SXTAB16 GPRnopc:$Rd, GPR:$Rn, GPRnopc:$Rm, 0, pred:$p)>;
5166 def : ARMInstAlias<"sxtb${p} $Rd, $Rm",
5167 (SXTB GPRnopc:$Rd, GPRnopc:$Rm, 0, pred:$p)>;
5168 def : ARMInstAlias<"sxtb16${p} $Rd, $Rm",
5169 (SXTB16 GPRnopc:$Rd, GPRnopc:$Rm, 0, pred:$p)>;
5170 def : ARMInstAlias<"sxth${p} $Rd, $Rm",
5171 (SXTH GPRnopc:$Rd, GPRnopc:$Rm, 0, pred:$p)>;
5173 def : ARMInstAlias<"uxtab${p} $Rd, $Rn, $Rm",
5174 (UXTAB GPRnopc:$Rd, GPR:$Rn, GPRnopc:$Rm, 0, pred:$p)>;
5175 def : ARMInstAlias<"uxtah${p} $Rd, $Rn, $Rm",
5176 (UXTAH GPRnopc:$Rd, GPR:$Rn, GPRnopc:$Rm, 0, pred:$p)>;
5177 def : ARMInstAlias<"uxtab16${p} $Rd, $Rn, $Rm",
5178 (UXTAB16 GPRnopc:$Rd, GPR:$Rn, GPRnopc:$Rm, 0, pred:$p)>;
5179 def : ARMInstAlias<"uxtb${p} $Rd, $Rm",
5180 (UXTB GPRnopc:$Rd, GPRnopc:$Rm, 0, pred:$p)>;
5181 def : ARMInstAlias<"uxtb16${p} $Rd, $Rm",
5182 (UXTB16 GPRnopc:$Rd, GPRnopc:$Rm, 0, pred:$p)>;
5183 def : ARMInstAlias<"uxth${p} $Rd, $Rm",
5184 (UXTH GPRnopc:$Rd, GPRnopc:$Rm, 0, pred:$p)>;
5188 def : MnemonicAlias<"rfefa", "rfeda">;
5189 def : MnemonicAlias<"rfeea", "rfedb">;
5190 def : MnemonicAlias<"rfefd", "rfeia">;
5191 def : MnemonicAlias<"rfeed", "rfeib">;
5192 def : MnemonicAlias<"rfe", "rfeia">;
5195 def : MnemonicAlias<"srsfa", "srsib">;
5196 def : MnemonicAlias<"srsea", "srsia">;
5197 def : MnemonicAlias<"srsfd", "srsdb">;
5198 def : MnemonicAlias<"srsed", "srsda">;
5199 def : MnemonicAlias<"srs", "srsia">;
5202 def : MnemonicAlias<"qsubaddx", "qsax">;
5204 def : MnemonicAlias<"saddsubx", "sasx">;
5205 // SHASX == SHADDSUBX
5206 def : MnemonicAlias<"shaddsubx", "shasx">;
5207 // SHSAX == SHSUBADDX
5208 def : MnemonicAlias<"shsubaddx", "shsax">;
5210 def : MnemonicAlias<"ssubaddx", "ssax">;
5212 def : MnemonicAlias<"uaddsubx", "uasx">;
5213 // UHASX == UHADDSUBX
5214 def : MnemonicAlias<"uhaddsubx", "uhasx">;
5215 // UHSAX == UHSUBADDX
5216 def : MnemonicAlias<"uhsubaddx", "uhsax">;
5217 // UQASX == UQADDSUBX
5218 def : MnemonicAlias<"uqaddsubx", "uqasx">;
5219 // UQSAX == UQSUBADDX
5220 def : MnemonicAlias<"uqsubaddx", "uqsax">;
5222 def : MnemonicAlias<"usubaddx", "usax">;
5224 // "mov Rd, so_imm_not" can be handled via "mvn" in assembly, just like
5226 def : ARMInstAlias<"mov${s}${p} $Rd, $imm",
5227 (MVNi rGPR:$Rd, so_imm_not:$imm, pred:$p, cc_out:$s)>;
5228 def : ARMInstAlias<"mvn${s}${p} $Rd, $imm",
5229 (MOVi rGPR:$Rd, so_imm_not:$imm, pred:$p, cc_out:$s)>;
5230 // Same for AND <--> BIC
5231 def : ARMInstAlias<"bic${s}${p} $Rd, $Rn, $imm",
5232 (ANDri rGPR:$Rd, rGPR:$Rn, so_imm_not:$imm,
5233 pred:$p, cc_out:$s)>;
5234 def : ARMInstAlias<"bic${s}${p} $Rdn, $imm",
5235 (ANDri rGPR:$Rdn, rGPR:$Rdn, so_imm_not:$imm,
5236 pred:$p, cc_out:$s)>;
5237 def : ARMInstAlias<"and${s}${p} $Rd, $Rn, $imm",
5238 (BICri rGPR:$Rd, rGPR:$Rn, so_imm_not:$imm,
5239 pred:$p, cc_out:$s)>;
5240 def : ARMInstAlias<"and${s}${p} $Rdn, $imm",
5241 (BICri rGPR:$Rdn, rGPR:$Rdn, so_imm_not:$imm,
5242 pred:$p, cc_out:$s)>;
5244 // Likewise, "add Rd, so_imm_neg" -> sub
5245 def : ARMInstAlias<"add${s}${p} $Rd, $Rn, $imm",
5246 (SUBri GPR:$Rd, GPR:$Rn, so_imm_neg:$imm, pred:$p, cc_out:$s)>;
5247 def : ARMInstAlias<"add${s}${p} $Rd, $imm",
5248 (SUBri GPR:$Rd, GPR:$Rd, so_imm_neg:$imm, pred:$p, cc_out:$s)>;
5249 // Same for CMP <--> CMN via so_imm_neg
5250 def : ARMInstAlias<"cmp${p} $Rd, $imm",
5251 (CMNri rGPR:$Rd, so_imm_neg:$imm, pred:$p)>;
5252 def : ARMInstAlias<"cmn${p} $Rd, $imm",
5253 (CMPri rGPR:$Rd, so_imm_neg:$imm, pred:$p)>;
5255 // The shifter forms of the MOV instruction are aliased to the ASR, LSL,
5256 // LSR, ROR, and RRX instructions.
5257 // FIXME: We need C++ parser hooks to map the alias to the MOV
5258 // encoding. It seems we should be able to do that sort of thing
5259 // in tblgen, but it could get ugly.
5260 let TwoOperandAliasConstraint = "$Rm = $Rd" in {
5261 def ASRi : ARMAsmPseudo<"asr${s}${p} $Rd, $Rm, $imm",
5262 (ins GPR:$Rd, GPR:$Rm, imm0_32:$imm, pred:$p,
5264 def LSRi : ARMAsmPseudo<"lsr${s}${p} $Rd, $Rm, $imm",
5265 (ins GPR:$Rd, GPR:$Rm, imm0_32:$imm, pred:$p,
5267 def LSLi : ARMAsmPseudo<"lsl${s}${p} $Rd, $Rm, $imm",
5268 (ins GPR:$Rd, GPR:$Rm, imm0_31:$imm, pred:$p,
5270 def RORi : ARMAsmPseudo<"ror${s}${p} $Rd, $Rm, $imm",
5271 (ins GPR:$Rd, GPR:$Rm, imm0_31:$imm, pred:$p,
5274 def RRXi : ARMAsmPseudo<"rrx${s}${p} $Rd, $Rm",
5275 (ins GPR:$Rd, GPR:$Rm, pred:$p, cc_out:$s)>;
5276 let TwoOperandAliasConstraint = "$Rn = $Rd" in {
5277 def ASRr : ARMAsmPseudo<"asr${s}${p} $Rd, $Rn, $Rm",
5278 (ins GPRnopc:$Rd, GPRnopc:$Rn, GPRnopc:$Rm, pred:$p,
5280 def LSRr : ARMAsmPseudo<"lsr${s}${p} $Rd, $Rn, $Rm",
5281 (ins GPRnopc:$Rd, GPRnopc:$Rn, GPRnopc:$Rm, pred:$p,
5283 def LSLr : ARMAsmPseudo<"lsl${s}${p} $Rd, $Rn, $Rm",
5284 (ins GPRnopc:$Rd, GPRnopc:$Rn, GPRnopc:$Rm, pred:$p,
5286 def RORr : ARMAsmPseudo<"ror${s}${p} $Rd, $Rn, $Rm",
5287 (ins GPRnopc:$Rd, GPRnopc:$Rn, GPRnopc:$Rm, pred:$p,
5291 // "neg" is and alias for "rsb rd, rn, #0"
5292 def : ARMInstAlias<"neg${s}${p} $Rd, $Rm",
5293 (RSBri GPR:$Rd, GPR:$Rm, 0, pred:$p, cc_out:$s)>;
5295 // Pre-v6, 'mov r0, r0' was used as a NOP encoding.
5296 def : InstAlias<"nop${p}", (MOVr R0, R0, pred:$p, zero_reg)>,
5297 Requires<[IsARM, NoV6]>;
5299 // UMULL/SMULL are available on all arches, but the instruction definitions
5300 // need difference constraints pre-v6. Use these aliases for the assembly
5301 // parsing on pre-v6.
5302 def : InstAlias<"smull${s}${p} $RdLo, $RdHi, $Rn, $Rm",
5303 (SMULL GPR:$RdLo, GPR:$RdHi, GPR:$Rn, GPR:$Rm, pred:$p, cc_out:$s)>,
5304 Requires<[IsARM, NoV6]>;
5305 def : InstAlias<"umull${s}${p} $RdLo, $RdHi, $Rn, $Rm",
5306 (UMULL GPR:$RdLo, GPR:$RdHi, GPR:$Rn, GPR:$Rm, pred:$p, cc_out:$s)>,
5307 Requires<[IsARM, NoV6]>;
5309 // 'it' blocks in ARM mode just validate the predicates. The IT itself
5311 def ITasm : ARMAsmPseudo<"it$mask $cc", (ins it_pred:$cc, it_mask:$mask)>;