1 //===- ARMInstrInfo.td - Target Description for ARM Target -*- tablegen -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file describes the ARM instructions in TableGen format.
12 //===----------------------------------------------------------------------===//
14 //===----------------------------------------------------------------------===//
15 // ARM specific DAG Nodes.
19 def SDT_ARMCallSeqStart : SDCallSeqStart<[ SDTCisVT<0, i32> ]>;
20 def SDT_ARMCallSeqEnd : SDCallSeqEnd<[ SDTCisVT<0, i32>, SDTCisVT<1, i32> ]>;
21 def SDT_ARMStructByVal : SDTypeProfile<0, 4,
22 [SDTCisVT<0, i32>, SDTCisVT<1, i32>,
23 SDTCisVT<2, i32>, SDTCisVT<3, i32>]>;
25 def SDT_ARMSaveCallPC : SDTypeProfile<0, 1, []>;
27 def SDT_ARMcall : SDTypeProfile<0, -1, [SDTCisPtrTy<0>]>;
29 def SDT_ARMCMov : SDTypeProfile<1, 3,
30 [SDTCisSameAs<0, 1>, SDTCisSameAs<0, 2>,
33 def SDT_ARMBrcond : SDTypeProfile<0, 2,
34 [SDTCisVT<0, OtherVT>, SDTCisVT<1, i32>]>;
36 def SDT_ARMBrJT : SDTypeProfile<0, 3,
37 [SDTCisPtrTy<0>, SDTCisVT<1, i32>,
40 def SDT_ARMBr2JT : SDTypeProfile<0, 4,
41 [SDTCisPtrTy<0>, SDTCisVT<1, i32>,
42 SDTCisVT<2, i32>, SDTCisVT<3, i32>]>;
44 def SDT_ARMBCC_i64 : SDTypeProfile<0, 6,
46 SDTCisVT<1, i32>, SDTCisVT<2, i32>,
47 SDTCisVT<3, i32>, SDTCisVT<4, i32>,
48 SDTCisVT<5, OtherVT>]>;
50 def SDT_ARMAnd : SDTypeProfile<1, 2,
51 [SDTCisVT<0, i32>, SDTCisVT<1, i32>,
54 def SDT_ARMCmp : SDTypeProfile<0, 2, [SDTCisSameAs<0, 1>]>;
56 def SDT_ARMPICAdd : SDTypeProfile<1, 2, [SDTCisSameAs<0, 1>,
57 SDTCisPtrTy<1>, SDTCisVT<2, i32>]>;
59 def SDT_ARMThreadPointer : SDTypeProfile<1, 0, [SDTCisPtrTy<0>]>;
60 def SDT_ARMEH_SJLJ_Setjmp : SDTypeProfile<1, 2, [SDTCisInt<0>, SDTCisPtrTy<1>,
62 def SDT_ARMEH_SJLJ_Longjmp: SDTypeProfile<0, 2, [SDTCisPtrTy<0>, SDTCisInt<1>]>;
64 def SDT_ARMMEMBARRIER : SDTypeProfile<0, 1, [SDTCisInt<0>]>;
66 def SDT_ARMPREFETCH : SDTypeProfile<0, 3, [SDTCisPtrTy<0>, SDTCisSameAs<1, 2>,
69 def SDT_ARMTCRET : SDTypeProfile<0, 1, [SDTCisPtrTy<0>]>;
71 def SDT_ARMBFI : SDTypeProfile<1, 3, [SDTCisVT<0, i32>, SDTCisVT<1, i32>,
72 SDTCisVT<2, i32>, SDTCisVT<3, i32>]>;
74 def SDTBinaryArithWithFlags : SDTypeProfile<2, 2,
77 SDTCisInt<0>, SDTCisVT<1, i32>]>;
79 // SDTBinaryArithWithFlagsInOut - RES1, CPSR = op LHS, RHS, CPSR
80 def SDTBinaryArithWithFlagsInOut : SDTypeProfile<2, 3,
87 def SDT_ARM64bitmlal : SDTypeProfile<2,4, [ SDTCisVT<0, i32>, SDTCisVT<1, i32>,
88 SDTCisVT<2, i32>, SDTCisVT<3, i32>,
89 SDTCisVT<4, i32>, SDTCisVT<5, i32> ] >;
90 def ARMUmlal : SDNode<"ARMISD::UMLAL", SDT_ARM64bitmlal>;
91 def ARMSmlal : SDNode<"ARMISD::SMLAL", SDT_ARM64bitmlal>;
94 def ARMWrapper : SDNode<"ARMISD::Wrapper", SDTIntUnaryOp>;
95 def ARMWrapperDYN : SDNode<"ARMISD::WrapperDYN", SDTIntUnaryOp>;
96 def ARMWrapperPIC : SDNode<"ARMISD::WrapperPIC", SDTIntUnaryOp>;
97 def ARMWrapperJT : SDNode<"ARMISD::WrapperJT", SDTIntBinOp>;
99 def ARMcallseq_start : SDNode<"ISD::CALLSEQ_START", SDT_ARMCallSeqStart,
100 [SDNPHasChain, SDNPSideEffect, SDNPOutGlue]>;
101 def ARMcallseq_end : SDNode<"ISD::CALLSEQ_END", SDT_ARMCallSeqEnd,
102 [SDNPHasChain, SDNPSideEffect,
103 SDNPOptInGlue, SDNPOutGlue]>;
104 def ARMcopystructbyval : SDNode<"ARMISD::COPY_STRUCT_BYVAL" ,
106 [SDNPHasChain, SDNPInGlue, SDNPOutGlue,
107 SDNPMayStore, SDNPMayLoad]>;
109 def ARMcall : SDNode<"ARMISD::CALL", SDT_ARMcall,
110 [SDNPHasChain, SDNPOptInGlue, SDNPOutGlue,
112 def ARMcall_pred : SDNode<"ARMISD::CALL_PRED", SDT_ARMcall,
113 [SDNPHasChain, SDNPOptInGlue, SDNPOutGlue,
115 def ARMcall_nolink : SDNode<"ARMISD::CALL_NOLINK", SDT_ARMcall,
116 [SDNPHasChain, SDNPOptInGlue, SDNPOutGlue,
119 def ARMretflag : SDNode<"ARMISD::RET_FLAG", SDTNone,
120 [SDNPHasChain, SDNPOptInGlue]>;
122 def ARMcmov : SDNode<"ARMISD::CMOV", SDT_ARMCMov,
125 def ARMbrcond : SDNode<"ARMISD::BRCOND", SDT_ARMBrcond,
126 [SDNPHasChain, SDNPInGlue, SDNPOutGlue]>;
128 def ARMbrjt : SDNode<"ARMISD::BR_JT", SDT_ARMBrJT,
130 def ARMbr2jt : SDNode<"ARMISD::BR2_JT", SDT_ARMBr2JT,
133 def ARMBcci64 : SDNode<"ARMISD::BCC_i64", SDT_ARMBCC_i64,
136 def ARMcmp : SDNode<"ARMISD::CMP", SDT_ARMCmp,
139 def ARMcmn : SDNode<"ARMISD::CMN", SDT_ARMCmp,
142 def ARMcmpZ : SDNode<"ARMISD::CMPZ", SDT_ARMCmp,
143 [SDNPOutGlue, SDNPCommutative]>;
145 def ARMpic_add : SDNode<"ARMISD::PIC_ADD", SDT_ARMPICAdd>;
147 def ARMsrl_flag : SDNode<"ARMISD::SRL_FLAG", SDTIntUnaryOp, [SDNPOutGlue]>;
148 def ARMsra_flag : SDNode<"ARMISD::SRA_FLAG", SDTIntUnaryOp, [SDNPOutGlue]>;
149 def ARMrrx : SDNode<"ARMISD::RRX" , SDTIntUnaryOp, [SDNPInGlue ]>;
151 def ARMaddc : SDNode<"ARMISD::ADDC", SDTBinaryArithWithFlags,
153 def ARMsubc : SDNode<"ARMISD::SUBC", SDTBinaryArithWithFlags>;
154 def ARMadde : SDNode<"ARMISD::ADDE", SDTBinaryArithWithFlagsInOut>;
155 def ARMsube : SDNode<"ARMISD::SUBE", SDTBinaryArithWithFlagsInOut>;
157 def ARMthread_pointer: SDNode<"ARMISD::THREAD_POINTER", SDT_ARMThreadPointer>;
158 def ARMeh_sjlj_setjmp: SDNode<"ARMISD::EH_SJLJ_SETJMP",
159 SDT_ARMEH_SJLJ_Setjmp,
160 [SDNPHasChain, SDNPSideEffect]>;
161 def ARMeh_sjlj_longjmp: SDNode<"ARMISD::EH_SJLJ_LONGJMP",
162 SDT_ARMEH_SJLJ_Longjmp,
163 [SDNPHasChain, SDNPSideEffect]>;
165 def ARMMemBarrier : SDNode<"ARMISD::MEMBARRIER", SDT_ARMMEMBARRIER,
166 [SDNPHasChain, SDNPSideEffect]>;
167 def ARMMemBarrierMCR : SDNode<"ARMISD::MEMBARRIER_MCR", SDT_ARMMEMBARRIER,
168 [SDNPHasChain, SDNPSideEffect]>;
169 def ARMPreload : SDNode<"ARMISD::PRELOAD", SDT_ARMPREFETCH,
170 [SDNPHasChain, SDNPMayLoad, SDNPMayStore]>;
172 def ARMrbit : SDNode<"ARMISD::RBIT", SDTIntUnaryOp>;
174 def ARMtcret : SDNode<"ARMISD::TC_RETURN", SDT_ARMTCRET,
175 [SDNPHasChain, SDNPOptInGlue, SDNPVariadic]>;
178 def ARMbfi : SDNode<"ARMISD::BFI", SDT_ARMBFI>;
180 //===----------------------------------------------------------------------===//
181 // ARM Instruction Predicate Definitions.
183 def HasV4T : Predicate<"Subtarget->hasV4TOps()">,
184 AssemblerPredicate<"HasV4TOps", "armv4t">;
185 def NoV4T : Predicate<"!Subtarget->hasV4TOps()">;
186 def HasV5T : Predicate<"Subtarget->hasV5TOps()">;
187 def HasV5TE : Predicate<"Subtarget->hasV5TEOps()">,
188 AssemblerPredicate<"HasV5TEOps", "armv5te">;
189 def HasV6 : Predicate<"Subtarget->hasV6Ops()">,
190 AssemblerPredicate<"HasV6Ops", "armv6">;
191 def NoV6 : Predicate<"!Subtarget->hasV6Ops()">;
192 def HasV6T2 : Predicate<"Subtarget->hasV6T2Ops()">,
193 AssemblerPredicate<"HasV6T2Ops", "armv6t2">;
194 def NoV6T2 : Predicate<"!Subtarget->hasV6T2Ops()">;
195 def HasV7 : Predicate<"Subtarget->hasV7Ops()">,
196 AssemblerPredicate<"HasV7Ops", "armv7">;
197 def NoVFP : Predicate<"!Subtarget->hasVFP2()">;
198 def HasVFP2 : Predicate<"Subtarget->hasVFP2()">,
199 AssemblerPredicate<"FeatureVFP2", "VFP2">;
200 def HasVFP3 : Predicate<"Subtarget->hasVFP3()">,
201 AssemblerPredicate<"FeatureVFP3", "VFP3">;
202 def HasVFP4 : Predicate<"Subtarget->hasVFP4()">,
203 AssemblerPredicate<"FeatureVFP4", "VFP4">;
204 def HasNEON : Predicate<"Subtarget->hasNEON()">,
205 AssemblerPredicate<"FeatureNEON", "NEON">;
206 def HasFP16 : Predicate<"Subtarget->hasFP16()">,
207 AssemblerPredicate<"FeatureFP16","half-float">;
208 def HasDivide : Predicate<"Subtarget->hasDivide()">,
209 AssemblerPredicate<"FeatureHWDiv", "divide">;
210 def HasDivideInARM : Predicate<"Subtarget->hasDivideInARMMode()">,
211 AssemblerPredicate<"FeatureHWDivARM">;
212 def HasT2ExtractPack : Predicate<"Subtarget->hasT2ExtractPack()">,
213 AssemblerPredicate<"FeatureT2XtPk",
215 def HasThumb2DSP : Predicate<"Subtarget->hasThumb2DSP()">,
216 AssemblerPredicate<"FeatureDSPThumb2",
218 def HasDB : Predicate<"Subtarget->hasDataBarrier()">,
219 AssemblerPredicate<"FeatureDB",
221 def HasMP : Predicate<"Subtarget->hasMPExtension()">,
222 AssemblerPredicate<"FeatureMP",
224 def UseNEONForFP : Predicate<"Subtarget->useNEONForSinglePrecisionFP()">;
225 def DontUseNEONForFP : Predicate<"!Subtarget->useNEONForSinglePrecisionFP()">;
226 def IsThumb : Predicate<"Subtarget->isThumb()">,
227 AssemblerPredicate<"ModeThumb", "thumb">;
228 def IsThumb1Only : Predicate<"Subtarget->isThumb1Only()">;
229 def IsThumb2 : Predicate<"Subtarget->isThumb2()">,
230 AssemblerPredicate<"ModeThumb,FeatureThumb2",
232 def IsMClass : Predicate<"Subtarget->isMClass()">,
233 AssemblerPredicate<"FeatureMClass", "armv7m">;
234 def IsARClass : Predicate<"!Subtarget->isMClass()">,
235 AssemblerPredicate<"!FeatureMClass",
237 def IsARM : Predicate<"!Subtarget->isThumb()">,
238 AssemblerPredicate<"!ModeThumb", "arm-mode">;
239 def IsIOS : Predicate<"Subtarget->isTargetIOS()">;
240 def IsNotIOS : Predicate<"!Subtarget->isTargetIOS()">;
241 def IsNaCl : Predicate<"Subtarget->isTargetNaCl()">;
243 // FIXME: Eventually this will be just "hasV6T2Ops".
244 def UseMovt : Predicate<"Subtarget->useMovt()">;
245 def DontUseMovt : Predicate<"!Subtarget->useMovt()">;
246 def UseFPVMLx : Predicate<"Subtarget->useFPVMLx()">;
247 def UseMulOps : Predicate<"Subtarget->useMulOps()">;
249 // Prefer fused MAC for fp mul + add over fp VMLA / VMLS if they are available.
250 // But only select them if more precision in FP computation is allowed.
251 // Do not use them for Darwin platforms.
252 def UseFusedMAC : Predicate<"(TM.Options.AllowFPOpFusion =="
253 " FPOpFusion::Fast) && "
254 "!Subtarget->isTargetDarwin()">;
255 def DontUseFusedMAC : Predicate<"!Subtarget->hasVFP4() || "
256 "Subtarget->isTargetDarwin()">;
258 // VGETLNi32 is microcoded on Swift - prefer VMOV.
259 def HasFastVGETLNi32 : Predicate<"!Subtarget->isSwift()">;
260 def HasSlowVGETLNi32 : Predicate<"Subtarget->isSwift()">;
262 // VDUP.32 is microcoded on Swift - prefer VMOV.
263 def HasFastVDUP32 : Predicate<"!Subtarget->isSwift()">;
264 def HasSlowVDUP32 : Predicate<"Subtarget->isSwift()">;
266 // Cortex-A9 prefers VMOVSR to VMOVDRR even when using NEON for scalar FP, as
267 // this allows more effective execution domain optimization. See
268 // setExecutionDomain().
269 def UseVMOVSR : Predicate<"Subtarget->isCortexA9() || !Subtarget->useNEONForSinglePrecisionFP()">;
270 def DontUseVMOVSR : Predicate<"!Subtarget->isCortexA9() && Subtarget->useNEONForSinglePrecisionFP()">;
272 def IsLE : Predicate<"TLI.isLittleEndian()">;
273 def IsBE : Predicate<"TLI.isBigEndian()">;
275 //===----------------------------------------------------------------------===//
276 // ARM Flag Definitions.
278 class RegConstraint<string C> {
279 string Constraints = C;
282 //===----------------------------------------------------------------------===//
283 // ARM specific transformation functions and pattern fragments.
286 // imm_neg_XFORM - Return a imm value packed into the format described for
287 // imm_neg defs below.
288 def imm_neg_XFORM : SDNodeXForm<imm, [{
289 return CurDAG->getTargetConstant(-(int)N->getZExtValue(), MVT::i32);
292 // so_imm_not_XFORM - Return a so_imm value packed into the format described for
293 // so_imm_not def below.
294 def so_imm_not_XFORM : SDNodeXForm<imm, [{
295 return CurDAG->getTargetConstant(~(int)N->getZExtValue(), MVT::i32);
298 /// imm16_31 predicate - True if the 32-bit immediate is in the range [16,31].
299 def imm16_31 : ImmLeaf<i32, [{
300 return (int32_t)Imm >= 16 && (int32_t)Imm < 32;
303 def so_imm_neg_asmoperand : AsmOperandClass { let Name = "ARMSOImmNeg"; }
304 def so_imm_neg : Operand<i32>, PatLeaf<(imm), [{
305 unsigned Value = -(unsigned)N->getZExtValue();
306 return Value && ARM_AM::getSOImmVal(Value) != -1;
308 let ParserMatchClass = so_imm_neg_asmoperand;
311 // Note: this pattern doesn't require an encoder method and such, as it's
312 // only used on aliases (Pat<> and InstAlias<>). The actual encoding
313 // is handled by the destination instructions, which use so_imm.
314 def so_imm_not_asmoperand : AsmOperandClass { let Name = "ARMSOImmNot"; }
315 def so_imm_not : Operand<i32>, PatLeaf<(imm), [{
316 return ARM_AM::getSOImmVal(~(uint32_t)N->getZExtValue()) != -1;
317 }], so_imm_not_XFORM> {
318 let ParserMatchClass = so_imm_not_asmoperand;
321 // sext_16_node predicate - True if the SDNode is sign-extended 16 or more bits.
322 def sext_16_node : PatLeaf<(i32 GPR:$a), [{
323 return CurDAG->ComputeNumSignBits(SDValue(N,0)) >= 17;
326 /// Split a 32-bit immediate into two 16 bit parts.
327 def hi16 : SDNodeXForm<imm, [{
328 return CurDAG->getTargetConstant((uint32_t)N->getZExtValue() >> 16, MVT::i32);
331 def lo16AllZero : PatLeaf<(i32 imm), [{
332 // Returns true if all low 16-bits are 0.
333 return (((uint32_t)N->getZExtValue()) & 0xFFFFUL) == 0;
336 class BinOpWithFlagFrag<dag res> :
337 PatFrag<(ops node:$LHS, node:$RHS, node:$FLAG), res>;
338 class BinOpFrag<dag res> : PatFrag<(ops node:$LHS, node:$RHS), res>;
339 class UnOpFrag <dag res> : PatFrag<(ops node:$Src), res>;
341 // An 'and' node with a single use.
342 def and_su : PatFrag<(ops node:$lhs, node:$rhs), (and node:$lhs, node:$rhs), [{
343 return N->hasOneUse();
346 // An 'xor' node with a single use.
347 def xor_su : PatFrag<(ops node:$lhs, node:$rhs), (xor node:$lhs, node:$rhs), [{
348 return N->hasOneUse();
351 // An 'fmul' node with a single use.
352 def fmul_su : PatFrag<(ops node:$lhs, node:$rhs), (fmul node:$lhs, node:$rhs),[{
353 return N->hasOneUse();
356 // An 'fadd' node which checks for single non-hazardous use.
357 def fadd_mlx : PatFrag<(ops node:$lhs, node:$rhs),(fadd node:$lhs, node:$rhs),[{
358 return hasNoVMLxHazardUse(N);
361 // An 'fsub' node which checks for single non-hazardous use.
362 def fsub_mlx : PatFrag<(ops node:$lhs, node:$rhs),(fsub node:$lhs, node:$rhs),[{
363 return hasNoVMLxHazardUse(N);
366 //===----------------------------------------------------------------------===//
367 // Operand Definitions.
370 // Immediate operands with a shared generic asm render method.
371 class ImmAsmOperand : AsmOperandClass { let RenderMethod = "addImmOperands"; }
374 // FIXME: rename brtarget to t2_brtarget
375 def brtarget : Operand<OtherVT> {
376 let EncoderMethod = "getBranchTargetOpValue";
377 let OperandType = "OPERAND_PCREL";
378 let DecoderMethod = "DecodeT2BROperand";
381 // FIXME: get rid of this one?
382 def uncondbrtarget : Operand<OtherVT> {
383 let EncoderMethod = "getUnconditionalBranchTargetOpValue";
384 let OperandType = "OPERAND_PCREL";
387 // Branch target for ARM. Handles conditional/unconditional
388 def br_target : Operand<OtherVT> {
389 let EncoderMethod = "getARMBranchTargetOpValue";
390 let OperandType = "OPERAND_PCREL";
394 // FIXME: rename bltarget to t2_bl_target?
395 def bltarget : Operand<i32> {
396 // Encoded the same as branch targets.
397 let EncoderMethod = "getBranchTargetOpValue";
398 let OperandType = "OPERAND_PCREL";
401 // Call target for ARM. Handles conditional/unconditional
402 // FIXME: rename bl_target to t2_bltarget?
403 def bl_target : Operand<i32> {
404 let EncoderMethod = "getARMBLTargetOpValue";
405 let OperandType = "OPERAND_PCREL";
408 def blx_target : Operand<i32> {
409 let EncoderMethod = "getARMBLXTargetOpValue";
410 let OperandType = "OPERAND_PCREL";
413 // A list of registers separated by comma. Used by load/store multiple.
414 def RegListAsmOperand : AsmOperandClass { let Name = "RegList"; }
415 def reglist : Operand<i32> {
416 let EncoderMethod = "getRegisterListOpValue";
417 let ParserMatchClass = RegListAsmOperand;
418 let PrintMethod = "printRegisterList";
419 let DecoderMethod = "DecodeRegListOperand";
422 def DPRRegListAsmOperand : AsmOperandClass { let Name = "DPRRegList"; }
423 def dpr_reglist : Operand<i32> {
424 let EncoderMethod = "getRegisterListOpValue";
425 let ParserMatchClass = DPRRegListAsmOperand;
426 let PrintMethod = "printRegisterList";
427 let DecoderMethod = "DecodeDPRRegListOperand";
430 def SPRRegListAsmOperand : AsmOperandClass { let Name = "SPRRegList"; }
431 def spr_reglist : Operand<i32> {
432 let EncoderMethod = "getRegisterListOpValue";
433 let ParserMatchClass = SPRRegListAsmOperand;
434 let PrintMethod = "printRegisterList";
435 let DecoderMethod = "DecodeSPRRegListOperand";
438 // An operand for the CONSTPOOL_ENTRY pseudo-instruction.
439 def cpinst_operand : Operand<i32> {
440 let PrintMethod = "printCPInstOperand";
444 def pclabel : Operand<i32> {
445 let PrintMethod = "printPCLabel";
448 // ADR instruction labels.
449 def AdrLabelAsmOperand : AsmOperandClass { let Name = "AdrLabel"; }
450 def adrlabel : Operand<i32> {
451 let EncoderMethod = "getAdrLabelOpValue";
452 let ParserMatchClass = AdrLabelAsmOperand;
453 let PrintMethod = "printAdrLabelOperand";
456 def neon_vcvt_imm32 : Operand<i32> {
457 let EncoderMethod = "getNEONVcvtImm32OpValue";
458 let DecoderMethod = "DecodeVCVTImmOperand";
461 // rot_imm: An integer that encodes a rotate amount. Must be 8, 16, or 24.
462 def rot_imm_XFORM: SDNodeXForm<imm, [{
463 switch (N->getZExtValue()){
465 case 0: return CurDAG->getTargetConstant(0, MVT::i32);
466 case 8: return CurDAG->getTargetConstant(1, MVT::i32);
467 case 16: return CurDAG->getTargetConstant(2, MVT::i32);
468 case 24: return CurDAG->getTargetConstant(3, MVT::i32);
471 def RotImmAsmOperand : AsmOperandClass {
473 let ParserMethod = "parseRotImm";
475 def rot_imm : Operand<i32>, PatLeaf<(i32 imm), [{
476 int32_t v = N->getZExtValue();
477 return v == 8 || v == 16 || v == 24; }],
479 let PrintMethod = "printRotImmOperand";
480 let ParserMatchClass = RotImmAsmOperand;
483 // shift_imm: An integer that encodes a shift amount and the type of shift
484 // (asr or lsl). The 6-bit immediate encodes as:
487 // {4-0} imm5 shift amount.
488 // asr #32 encoded as imm5 == 0.
489 def ShifterImmAsmOperand : AsmOperandClass {
490 let Name = "ShifterImm";
491 let ParserMethod = "parseShifterImm";
493 def shift_imm : Operand<i32> {
494 let PrintMethod = "printShiftImmOperand";
495 let ParserMatchClass = ShifterImmAsmOperand;
498 // shifter_operand operands: so_reg_reg, so_reg_imm, and so_imm.
499 def ShiftedRegAsmOperand : AsmOperandClass { let Name = "RegShiftedReg"; }
500 def so_reg_reg : Operand<i32>, // reg reg imm
501 ComplexPattern<i32, 3, "SelectRegShifterOperand",
502 [shl, srl, sra, rotr]> {
503 let EncoderMethod = "getSORegRegOpValue";
504 let PrintMethod = "printSORegRegOperand";
505 let DecoderMethod = "DecodeSORegRegOperand";
506 let ParserMatchClass = ShiftedRegAsmOperand;
507 let MIOperandInfo = (ops GPRnopc, GPRnopc, i32imm);
510 def ShiftedImmAsmOperand : AsmOperandClass { let Name = "RegShiftedImm"; }
511 def so_reg_imm : Operand<i32>, // reg imm
512 ComplexPattern<i32, 2, "SelectImmShifterOperand",
513 [shl, srl, sra, rotr]> {
514 let EncoderMethod = "getSORegImmOpValue";
515 let PrintMethod = "printSORegImmOperand";
516 let DecoderMethod = "DecodeSORegImmOperand";
517 let ParserMatchClass = ShiftedImmAsmOperand;
518 let MIOperandInfo = (ops GPR, i32imm);
521 // FIXME: Does this need to be distinct from so_reg?
522 def shift_so_reg_reg : Operand<i32>, // reg reg imm
523 ComplexPattern<i32, 3, "SelectShiftRegShifterOperand",
524 [shl,srl,sra,rotr]> {
525 let EncoderMethod = "getSORegRegOpValue";
526 let PrintMethod = "printSORegRegOperand";
527 let DecoderMethod = "DecodeSORegRegOperand";
528 let ParserMatchClass = ShiftedRegAsmOperand;
529 let MIOperandInfo = (ops GPR, GPR, i32imm);
532 // FIXME: Does this need to be distinct from so_reg?
533 def shift_so_reg_imm : Operand<i32>, // reg reg imm
534 ComplexPattern<i32, 2, "SelectShiftImmShifterOperand",
535 [shl,srl,sra,rotr]> {
536 let EncoderMethod = "getSORegImmOpValue";
537 let PrintMethod = "printSORegImmOperand";
538 let DecoderMethod = "DecodeSORegImmOperand";
539 let ParserMatchClass = ShiftedImmAsmOperand;
540 let MIOperandInfo = (ops GPR, i32imm);
544 // so_imm - Match a 32-bit shifter_operand immediate operand, which is an
545 // 8-bit immediate rotated by an arbitrary number of bits.
546 def SOImmAsmOperand: ImmAsmOperand { let Name = "ARMSOImm"; }
547 def so_imm : Operand<i32>, ImmLeaf<i32, [{
548 return ARM_AM::getSOImmVal(Imm) != -1;
550 let EncoderMethod = "getSOImmOpValue";
551 let ParserMatchClass = SOImmAsmOperand;
552 let DecoderMethod = "DecodeSOImmOperand";
555 // Break so_imm's up into two pieces. This handles immediates with up to 16
556 // bits set in them. This uses so_imm2part to match and so_imm2part_[12] to
557 // get the first/second pieces.
558 def so_imm2part : PatLeaf<(imm), [{
559 return ARM_AM::isSOImmTwoPartVal((unsigned)N->getZExtValue());
562 /// arm_i32imm - True for +V6T2, or true only if so_imm2part is true.
564 def arm_i32imm : PatLeaf<(imm), [{
565 if (Subtarget->hasV6T2Ops())
567 return ARM_AM::isSOImmTwoPartVal((unsigned)N->getZExtValue());
570 /// imm0_1 predicate - Immediate in the range [0,1].
571 def Imm0_1AsmOperand: ImmAsmOperand { let Name = "Imm0_1"; }
572 def imm0_1 : Operand<i32> { let ParserMatchClass = Imm0_1AsmOperand; }
574 /// imm0_3 predicate - Immediate in the range [0,3].
575 def Imm0_3AsmOperand: ImmAsmOperand { let Name = "Imm0_3"; }
576 def imm0_3 : Operand<i32> { let ParserMatchClass = Imm0_3AsmOperand; }
578 /// imm0_7 predicate - Immediate in the range [0,7].
579 def Imm0_7AsmOperand: ImmAsmOperand { let Name = "Imm0_7"; }
580 def imm0_7 : Operand<i32>, ImmLeaf<i32, [{
581 return Imm >= 0 && Imm < 8;
583 let ParserMatchClass = Imm0_7AsmOperand;
586 /// imm8 predicate - Immediate is exactly 8.
587 def Imm8AsmOperand: ImmAsmOperand { let Name = "Imm8"; }
588 def imm8 : Operand<i32>, ImmLeaf<i32, [{ return Imm == 8; }]> {
589 let ParserMatchClass = Imm8AsmOperand;
592 /// imm16 predicate - Immediate is exactly 16.
593 def Imm16AsmOperand: ImmAsmOperand { let Name = "Imm16"; }
594 def imm16 : Operand<i32>, ImmLeaf<i32, [{ return Imm == 16; }]> {
595 let ParserMatchClass = Imm16AsmOperand;
598 /// imm32 predicate - Immediate is exactly 32.
599 def Imm32AsmOperand: ImmAsmOperand { let Name = "Imm32"; }
600 def imm32 : Operand<i32>, ImmLeaf<i32, [{ return Imm == 32; }]> {
601 let ParserMatchClass = Imm32AsmOperand;
604 /// imm1_7 predicate - Immediate in the range [1,7].
605 def Imm1_7AsmOperand: ImmAsmOperand { let Name = "Imm1_7"; }
606 def imm1_7 : Operand<i32>, ImmLeaf<i32, [{ return Imm > 0 && Imm < 8; }]> {
607 let ParserMatchClass = Imm1_7AsmOperand;
610 /// imm1_15 predicate - Immediate in the range [1,15].
611 def Imm1_15AsmOperand: ImmAsmOperand { let Name = "Imm1_15"; }
612 def imm1_15 : Operand<i32>, ImmLeaf<i32, [{ return Imm > 0 && Imm < 16; }]> {
613 let ParserMatchClass = Imm1_15AsmOperand;
616 /// imm1_31 predicate - Immediate in the range [1,31].
617 def Imm1_31AsmOperand: ImmAsmOperand { let Name = "Imm1_31"; }
618 def imm1_31 : Operand<i32>, ImmLeaf<i32, [{ return Imm > 0 && Imm < 32; }]> {
619 let ParserMatchClass = Imm1_31AsmOperand;
622 /// imm0_15 predicate - Immediate in the range [0,15].
623 def Imm0_15AsmOperand: ImmAsmOperand {
624 let Name = "Imm0_15";
625 let DiagnosticType = "ImmRange0_15";
627 def imm0_15 : Operand<i32>, ImmLeaf<i32, [{
628 return Imm >= 0 && Imm < 16;
630 let ParserMatchClass = Imm0_15AsmOperand;
633 /// imm0_31 predicate - True if the 32-bit immediate is in the range [0,31].
634 def Imm0_31AsmOperand: ImmAsmOperand { let Name = "Imm0_31"; }
635 def imm0_31 : Operand<i32>, ImmLeaf<i32, [{
636 return Imm >= 0 && Imm < 32;
638 let ParserMatchClass = Imm0_31AsmOperand;
641 /// imm0_32 predicate - True if the 32-bit immediate is in the range [0,32].
642 def Imm0_32AsmOperand: ImmAsmOperand { let Name = "Imm0_32"; }
643 def imm0_32 : Operand<i32>, ImmLeaf<i32, [{
644 return Imm >= 0 && Imm < 32;
646 let ParserMatchClass = Imm0_32AsmOperand;
649 /// imm0_63 predicate - True if the 32-bit immediate is in the range [0,63].
650 def Imm0_63AsmOperand: ImmAsmOperand { let Name = "Imm0_63"; }
651 def imm0_63 : Operand<i32>, ImmLeaf<i32, [{
652 return Imm >= 0 && Imm < 64;
654 let ParserMatchClass = Imm0_63AsmOperand;
657 /// imm0_255 predicate - Immediate in the range [0,255].
658 def Imm0_255AsmOperand : ImmAsmOperand { let Name = "Imm0_255"; }
659 def imm0_255 : Operand<i32>, ImmLeaf<i32, [{ return Imm >= 0 && Imm < 256; }]> {
660 let ParserMatchClass = Imm0_255AsmOperand;
663 /// imm0_65535 - An immediate is in the range [0.65535].
664 def Imm0_65535AsmOperand: ImmAsmOperand { let Name = "Imm0_65535"; }
665 def imm0_65535 : Operand<i32>, ImmLeaf<i32, [{
666 return Imm >= 0 && Imm < 65536;
668 let ParserMatchClass = Imm0_65535AsmOperand;
671 // imm0_65535_neg - An immediate whose negative value is in the range [0.65535].
672 def imm0_65535_neg : Operand<i32>, ImmLeaf<i32, [{
673 return -Imm >= 0 && -Imm < 65536;
676 // imm0_65535_expr - For movt/movw - 16-bit immediate that can also reference
677 // a relocatable expression.
679 // FIXME: This really needs a Thumb version separate from the ARM version.
680 // While the range is the same, and can thus use the same match class,
681 // the encoding is different so it should have a different encoder method.
682 def Imm0_65535ExprAsmOperand: ImmAsmOperand { let Name = "Imm0_65535Expr"; }
683 def imm0_65535_expr : Operand<i32> {
684 let EncoderMethod = "getHiLo16ImmOpValue";
685 let ParserMatchClass = Imm0_65535ExprAsmOperand;
688 /// imm24b - True if the 32-bit immediate is encodable in 24 bits.
689 def Imm24bitAsmOperand: ImmAsmOperand { let Name = "Imm24bit"; }
690 def imm24b : Operand<i32>, ImmLeaf<i32, [{
691 return Imm >= 0 && Imm <= 0xffffff;
693 let ParserMatchClass = Imm24bitAsmOperand;
697 /// bf_inv_mask_imm predicate - An AND mask to clear an arbitrary width bitfield
699 def BitfieldAsmOperand : AsmOperandClass {
700 let Name = "Bitfield";
701 let ParserMethod = "parseBitfield";
704 def bf_inv_mask_imm : Operand<i32>,
706 return ARM::isBitFieldInvertedMask(N->getZExtValue());
708 let EncoderMethod = "getBitfieldInvertedMaskOpValue";
709 let PrintMethod = "printBitfieldInvMaskImmOperand";
710 let DecoderMethod = "DecodeBitfieldMaskOperand";
711 let ParserMatchClass = BitfieldAsmOperand;
714 def imm1_32_XFORM: SDNodeXForm<imm, [{
715 return CurDAG->getTargetConstant((int)N->getZExtValue() - 1, MVT::i32);
717 def Imm1_32AsmOperand: AsmOperandClass { let Name = "Imm1_32"; }
718 def imm1_32 : Operand<i32>, PatLeaf<(imm), [{
719 uint64_t Imm = N->getZExtValue();
720 return Imm > 0 && Imm <= 32;
723 let PrintMethod = "printImmPlusOneOperand";
724 let ParserMatchClass = Imm1_32AsmOperand;
727 def imm1_16_XFORM: SDNodeXForm<imm, [{
728 return CurDAG->getTargetConstant((int)N->getZExtValue() - 1, MVT::i32);
730 def Imm1_16AsmOperand: AsmOperandClass { let Name = "Imm1_16"; }
731 def imm1_16 : Operand<i32>, PatLeaf<(imm), [{ return Imm > 0 && Imm <= 16; }],
733 let PrintMethod = "printImmPlusOneOperand";
734 let ParserMatchClass = Imm1_16AsmOperand;
737 // Define ARM specific addressing modes.
738 // addrmode_imm12 := reg +/- imm12
740 def MemImm12OffsetAsmOperand : AsmOperandClass { let Name = "MemImm12Offset"; }
741 def addrmode_imm12 : Operand<i32>,
742 ComplexPattern<i32, 2, "SelectAddrModeImm12", []> {
743 // 12-bit immediate operand. Note that instructions using this encode
744 // #0 and #-0 differently. We flag #-0 as the magic value INT32_MIN. All other
745 // immediate values are as normal.
747 let EncoderMethod = "getAddrModeImm12OpValue";
748 let PrintMethod = "printAddrModeImm12Operand";
749 let DecoderMethod = "DecodeAddrModeImm12Operand";
750 let ParserMatchClass = MemImm12OffsetAsmOperand;
751 let MIOperandInfo = (ops GPR:$base, i32imm:$offsimm);
753 // ldst_so_reg := reg +/- reg shop imm
755 def MemRegOffsetAsmOperand : AsmOperandClass { let Name = "MemRegOffset"; }
756 def ldst_so_reg : Operand<i32>,
757 ComplexPattern<i32, 3, "SelectLdStSOReg", []> {
758 let EncoderMethod = "getLdStSORegOpValue";
759 // FIXME: Simplify the printer
760 let PrintMethod = "printAddrMode2Operand";
761 let DecoderMethod = "DecodeSORegMemOperand";
762 let ParserMatchClass = MemRegOffsetAsmOperand;
763 let MIOperandInfo = (ops GPR:$base, GPRnopc:$offsreg, i32imm:$shift);
766 // postidx_imm8 := +/- [0,255]
769 // {8} 1 is imm8 is non-negative. 0 otherwise.
770 // {7-0} [0,255] imm8 value.
771 def PostIdxImm8AsmOperand : AsmOperandClass { let Name = "PostIdxImm8"; }
772 def postidx_imm8 : Operand<i32> {
773 let PrintMethod = "printPostIdxImm8Operand";
774 let ParserMatchClass = PostIdxImm8AsmOperand;
775 let MIOperandInfo = (ops i32imm);
778 // postidx_imm8s4 := +/- [0,1020]
781 // {8} 1 is imm8 is non-negative. 0 otherwise.
782 // {7-0} [0,255] imm8 value, scaled by 4.
783 def PostIdxImm8s4AsmOperand : AsmOperandClass { let Name = "PostIdxImm8s4"; }
784 def postidx_imm8s4 : Operand<i32> {
785 let PrintMethod = "printPostIdxImm8s4Operand";
786 let ParserMatchClass = PostIdxImm8s4AsmOperand;
787 let MIOperandInfo = (ops i32imm);
791 // postidx_reg := +/- reg
793 def PostIdxRegAsmOperand : AsmOperandClass {
794 let Name = "PostIdxReg";
795 let ParserMethod = "parsePostIdxReg";
797 def postidx_reg : Operand<i32> {
798 let EncoderMethod = "getPostIdxRegOpValue";
799 let DecoderMethod = "DecodePostIdxReg";
800 let PrintMethod = "printPostIdxRegOperand";
801 let ParserMatchClass = PostIdxRegAsmOperand;
802 let MIOperandInfo = (ops GPRnopc, i32imm);
806 // addrmode2 := reg +/- imm12
807 // := reg +/- reg shop imm
809 // FIXME: addrmode2 should be refactored the rest of the way to always
810 // use explicit imm vs. reg versions above (addrmode_imm12 and ldst_so_reg).
811 def AddrMode2AsmOperand : AsmOperandClass { let Name = "AddrMode2"; }
812 def addrmode2 : Operand<i32>,
813 ComplexPattern<i32, 3, "SelectAddrMode2", []> {
814 let EncoderMethod = "getAddrMode2OpValue";
815 let PrintMethod = "printAddrMode2Operand";
816 let ParserMatchClass = AddrMode2AsmOperand;
817 let MIOperandInfo = (ops GPR:$base, GPR:$offsreg, i32imm:$offsimm);
820 def PostIdxRegShiftedAsmOperand : AsmOperandClass {
821 let Name = "PostIdxRegShifted";
822 let ParserMethod = "parsePostIdxReg";
824 def am2offset_reg : Operand<i32>,
825 ComplexPattern<i32, 2, "SelectAddrMode2OffsetReg",
826 [], [SDNPWantRoot]> {
827 let EncoderMethod = "getAddrMode2OffsetOpValue";
828 let PrintMethod = "printAddrMode2OffsetOperand";
829 // When using this for assembly, it's always as a post-index offset.
830 let ParserMatchClass = PostIdxRegShiftedAsmOperand;
831 let MIOperandInfo = (ops GPRnopc, i32imm);
834 // FIXME: am2offset_imm should only need the immediate, not the GPR. Having
835 // the GPR is purely vestigal at this point.
836 def AM2OffsetImmAsmOperand : AsmOperandClass { let Name = "AM2OffsetImm"; }
837 def am2offset_imm : Operand<i32>,
838 ComplexPattern<i32, 2, "SelectAddrMode2OffsetImm",
839 [], [SDNPWantRoot]> {
840 let EncoderMethod = "getAddrMode2OffsetOpValue";
841 let PrintMethod = "printAddrMode2OffsetOperand";
842 let ParserMatchClass = AM2OffsetImmAsmOperand;
843 let MIOperandInfo = (ops GPRnopc, i32imm);
847 // addrmode3 := reg +/- reg
848 // addrmode3 := reg +/- imm8
850 // FIXME: split into imm vs. reg versions.
851 def AddrMode3AsmOperand : AsmOperandClass { let Name = "AddrMode3"; }
852 def addrmode3 : Operand<i32>,
853 ComplexPattern<i32, 3, "SelectAddrMode3", []> {
854 let EncoderMethod = "getAddrMode3OpValue";
855 let PrintMethod = "printAddrMode3Operand";
856 let ParserMatchClass = AddrMode3AsmOperand;
857 let MIOperandInfo = (ops GPR:$base, GPR:$offsreg, i32imm:$offsimm);
860 // FIXME: split into imm vs. reg versions.
861 // FIXME: parser method to handle +/- register.
862 def AM3OffsetAsmOperand : AsmOperandClass {
863 let Name = "AM3Offset";
864 let ParserMethod = "parseAM3Offset";
866 def am3offset : Operand<i32>,
867 ComplexPattern<i32, 2, "SelectAddrMode3Offset",
868 [], [SDNPWantRoot]> {
869 let EncoderMethod = "getAddrMode3OffsetOpValue";
870 let PrintMethod = "printAddrMode3OffsetOperand";
871 let ParserMatchClass = AM3OffsetAsmOperand;
872 let MIOperandInfo = (ops GPR, i32imm);
875 // ldstm_mode := {ia, ib, da, db}
877 def ldstm_mode : OptionalDefOperand<OtherVT, (ops i32), (ops (i32 1))> {
878 let EncoderMethod = "getLdStmModeOpValue";
879 let PrintMethod = "printLdStmModeOperand";
882 // addrmode5 := reg +/- imm8*4
884 def AddrMode5AsmOperand : AsmOperandClass { let Name = "AddrMode5"; }
885 def addrmode5 : Operand<i32>,
886 ComplexPattern<i32, 2, "SelectAddrMode5", []> {
887 let PrintMethod = "printAddrMode5Operand";
888 let EncoderMethod = "getAddrMode5OpValue";
889 let DecoderMethod = "DecodeAddrMode5Operand";
890 let ParserMatchClass = AddrMode5AsmOperand;
891 let MIOperandInfo = (ops GPR:$base, i32imm);
894 // addrmode6 := reg with optional alignment
896 def AddrMode6AsmOperand : AsmOperandClass { let Name = "AlignedMemory"; }
897 def addrmode6 : Operand<i32>,
898 ComplexPattern<i32, 2, "SelectAddrMode6", [], [SDNPWantParent]>{
899 let PrintMethod = "printAddrMode6Operand";
900 let MIOperandInfo = (ops GPR:$addr, i32imm:$align);
901 let EncoderMethod = "getAddrMode6AddressOpValue";
902 let DecoderMethod = "DecodeAddrMode6Operand";
903 let ParserMatchClass = AddrMode6AsmOperand;
906 def am6offset : Operand<i32>,
907 ComplexPattern<i32, 1, "SelectAddrMode6Offset",
908 [], [SDNPWantRoot]> {
909 let PrintMethod = "printAddrMode6OffsetOperand";
910 let MIOperandInfo = (ops GPR);
911 let EncoderMethod = "getAddrMode6OffsetOpValue";
912 let DecoderMethod = "DecodeGPRRegisterClass";
915 // Special version of addrmode6 to handle alignment encoding for VST1/VLD1
916 // (single element from one lane) for size 32.
917 def addrmode6oneL32 : Operand<i32>,
918 ComplexPattern<i32, 2, "SelectAddrMode6", [], [SDNPWantParent]>{
919 let PrintMethod = "printAddrMode6Operand";
920 let MIOperandInfo = (ops GPR:$addr, i32imm);
921 let EncoderMethod = "getAddrMode6OneLane32AddressOpValue";
924 // Special version of addrmode6 to handle alignment encoding for VLD-dup
925 // instructions, specifically VLD4-dup.
926 def addrmode6dup : Operand<i32>,
927 ComplexPattern<i32, 2, "SelectAddrMode6", [], [SDNPWantParent]>{
928 let PrintMethod = "printAddrMode6Operand";
929 let MIOperandInfo = (ops GPR:$addr, i32imm);
930 let EncoderMethod = "getAddrMode6DupAddressOpValue";
931 // FIXME: This is close, but not quite right. The alignment specifier is
933 let ParserMatchClass = AddrMode6AsmOperand;
936 // addrmodepc := pc + reg
938 def addrmodepc : Operand<i32>,
939 ComplexPattern<i32, 2, "SelectAddrModePC", []> {
940 let PrintMethod = "printAddrModePCOperand";
941 let MIOperandInfo = (ops GPR, i32imm);
944 // addr_offset_none := reg
946 def MemNoOffsetAsmOperand : AsmOperandClass { let Name = "MemNoOffset"; }
947 def addr_offset_none : Operand<i32>,
948 ComplexPattern<i32, 1, "SelectAddrOffsetNone", []> {
949 let PrintMethod = "printAddrMode7Operand";
950 let DecoderMethod = "DecodeAddrMode7Operand";
951 let ParserMatchClass = MemNoOffsetAsmOperand;
952 let MIOperandInfo = (ops GPR:$base);
955 def nohash_imm : Operand<i32> {
956 let PrintMethod = "printNoHashImmediate";
959 def CoprocNumAsmOperand : AsmOperandClass {
960 let Name = "CoprocNum";
961 let ParserMethod = "parseCoprocNumOperand";
963 def p_imm : Operand<i32> {
964 let PrintMethod = "printPImmediate";
965 let ParserMatchClass = CoprocNumAsmOperand;
966 let DecoderMethod = "DecodeCoprocessor";
969 def pf_imm : Operand<i32> {
970 let PrintMethod = "printPImmediate";
971 let ParserMatchClass = CoprocNumAsmOperand;
974 def CoprocRegAsmOperand : AsmOperandClass {
975 let Name = "CoprocReg";
976 let ParserMethod = "parseCoprocRegOperand";
978 def c_imm : Operand<i32> {
979 let PrintMethod = "printCImmediate";
980 let ParserMatchClass = CoprocRegAsmOperand;
982 def CoprocOptionAsmOperand : AsmOperandClass {
983 let Name = "CoprocOption";
984 let ParserMethod = "parseCoprocOptionOperand";
986 def coproc_option_imm : Operand<i32> {
987 let PrintMethod = "printCoprocOptionImm";
988 let ParserMatchClass = CoprocOptionAsmOperand;
991 //===----------------------------------------------------------------------===//
993 include "ARMInstrFormats.td"
995 //===----------------------------------------------------------------------===//
996 // Multiclass helpers...
999 /// AsI1_bin_irs - Defines a set of (op r, {so_imm|r|so_reg}) patterns for a
1000 /// binop that produces a value.
1001 let TwoOperandAliasConstraint = "$Rn = $Rd" in
1002 multiclass AsI1_bin_irs<bits<4> opcod, string opc,
1003 InstrItinClass iii, InstrItinClass iir, InstrItinClass iis,
1004 PatFrag opnode, bit Commutable = 0> {
1005 // The register-immediate version is re-materializable. This is useful
1006 // in particular for taking the address of a local.
1007 let isReMaterializable = 1 in {
1008 def ri : AsI1<opcod, (outs GPR:$Rd), (ins GPR:$Rn, so_imm:$imm), DPFrm,
1009 iii, opc, "\t$Rd, $Rn, $imm",
1010 [(set GPR:$Rd, (opnode GPR:$Rn, so_imm:$imm))]> {
1015 let Inst{19-16} = Rn;
1016 let Inst{15-12} = Rd;
1017 let Inst{11-0} = imm;
1020 def rr : AsI1<opcod, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm), DPFrm,
1021 iir, opc, "\t$Rd, $Rn, $Rm",
1022 [(set GPR:$Rd, (opnode GPR:$Rn, GPR:$Rm))]> {
1027 let isCommutable = Commutable;
1028 let Inst{19-16} = Rn;
1029 let Inst{15-12} = Rd;
1030 let Inst{11-4} = 0b00000000;
1034 def rsi : AsI1<opcod, (outs GPR:$Rd),
1035 (ins GPR:$Rn, so_reg_imm:$shift), DPSoRegImmFrm,
1036 iis, opc, "\t$Rd, $Rn, $shift",
1037 [(set GPR:$Rd, (opnode GPR:$Rn, so_reg_imm:$shift))]> {
1042 let Inst{19-16} = Rn;
1043 let Inst{15-12} = Rd;
1044 let Inst{11-5} = shift{11-5};
1046 let Inst{3-0} = shift{3-0};
1049 def rsr : AsI1<opcod, (outs GPR:$Rd),
1050 (ins GPR:$Rn, so_reg_reg:$shift), DPSoRegRegFrm,
1051 iis, opc, "\t$Rd, $Rn, $shift",
1052 [(set GPR:$Rd, (opnode GPR:$Rn, so_reg_reg:$shift))]> {
1057 let Inst{19-16} = Rn;
1058 let Inst{15-12} = Rd;
1059 let Inst{11-8} = shift{11-8};
1061 let Inst{6-5} = shift{6-5};
1063 let Inst{3-0} = shift{3-0};
1067 /// AsI1_rbin_irs - Same as AsI1_bin_irs except the order of operands are
1068 /// reversed. The 'rr' form is only defined for the disassembler; for codegen
1069 /// it is equivalent to the AsI1_bin_irs counterpart.
1070 let TwoOperandAliasConstraint = "$Rn = $Rd" in
1071 multiclass AsI1_rbin_irs<bits<4> opcod, string opc,
1072 InstrItinClass iii, InstrItinClass iir, InstrItinClass iis,
1073 PatFrag opnode, bit Commutable = 0> {
1074 // The register-immediate version is re-materializable. This is useful
1075 // in particular for taking the address of a local.
1076 let isReMaterializable = 1 in {
1077 def ri : AsI1<opcod, (outs GPR:$Rd), (ins GPR:$Rn, so_imm:$imm), DPFrm,
1078 iii, opc, "\t$Rd, $Rn, $imm",
1079 [(set GPR:$Rd, (opnode so_imm:$imm, GPR:$Rn))]> {
1084 let Inst{19-16} = Rn;
1085 let Inst{15-12} = Rd;
1086 let Inst{11-0} = imm;
1089 def rr : AsI1<opcod, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm), DPFrm,
1090 iir, opc, "\t$Rd, $Rn, $Rm",
1091 [/* pattern left blank */]> {
1095 let Inst{11-4} = 0b00000000;
1098 let Inst{15-12} = Rd;
1099 let Inst{19-16} = Rn;
1102 def rsi : AsI1<opcod, (outs GPR:$Rd),
1103 (ins GPR:$Rn, so_reg_imm:$shift), DPSoRegImmFrm,
1104 iis, opc, "\t$Rd, $Rn, $shift",
1105 [(set GPR:$Rd, (opnode so_reg_imm:$shift, GPR:$Rn))]> {
1110 let Inst{19-16} = Rn;
1111 let Inst{15-12} = Rd;
1112 let Inst{11-5} = shift{11-5};
1114 let Inst{3-0} = shift{3-0};
1117 def rsr : AsI1<opcod, (outs GPR:$Rd),
1118 (ins GPR:$Rn, so_reg_reg:$shift), DPSoRegRegFrm,
1119 iis, opc, "\t$Rd, $Rn, $shift",
1120 [(set GPR:$Rd, (opnode so_reg_reg:$shift, GPR:$Rn))]> {
1125 let Inst{19-16} = Rn;
1126 let Inst{15-12} = Rd;
1127 let Inst{11-8} = shift{11-8};
1129 let Inst{6-5} = shift{6-5};
1131 let Inst{3-0} = shift{3-0};
1135 /// AsI1_bin_s_irs - Same as AsI1_bin_irs except it sets the 's' bit by default.
1137 /// These opcodes will be converted to the real non-S opcodes by
1138 /// AdjustInstrPostInstrSelection after giving them an optional CPSR operand.
1139 let hasPostISelHook = 1, Defs = [CPSR] in {
1140 multiclass AsI1_bin_s_irs<InstrItinClass iii, InstrItinClass iir,
1141 InstrItinClass iis, PatFrag opnode,
1142 bit Commutable = 0> {
1143 def ri : ARMPseudoInst<(outs GPR:$Rd), (ins GPR:$Rn, so_imm:$imm, pred:$p),
1145 [(set GPR:$Rd, CPSR, (opnode GPR:$Rn, so_imm:$imm))]>;
1147 def rr : ARMPseudoInst<(outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm, pred:$p),
1149 [(set GPR:$Rd, CPSR, (opnode GPR:$Rn, GPR:$Rm))]> {
1150 let isCommutable = Commutable;
1152 def rsi : ARMPseudoInst<(outs GPR:$Rd),
1153 (ins GPR:$Rn, so_reg_imm:$shift, pred:$p),
1155 [(set GPR:$Rd, CPSR, (opnode GPR:$Rn,
1156 so_reg_imm:$shift))]>;
1158 def rsr : ARMPseudoInst<(outs GPR:$Rd),
1159 (ins GPR:$Rn, so_reg_reg:$shift, pred:$p),
1161 [(set GPR:$Rd, CPSR, (opnode GPR:$Rn,
1162 so_reg_reg:$shift))]>;
1166 /// AsI1_rbin_s_is - Same as AsI1_bin_s_irs, except selection DAG
1167 /// operands are reversed.
1168 let hasPostISelHook = 1, Defs = [CPSR] in {
1169 multiclass AsI1_rbin_s_is<InstrItinClass iii, InstrItinClass iir,
1170 InstrItinClass iis, PatFrag opnode,
1171 bit Commutable = 0> {
1172 def ri : ARMPseudoInst<(outs GPR:$Rd), (ins GPR:$Rn, so_imm:$imm, pred:$p),
1174 [(set GPR:$Rd, CPSR, (opnode so_imm:$imm, GPR:$Rn))]>;
1176 def rsi : ARMPseudoInst<(outs GPR:$Rd),
1177 (ins GPR:$Rn, so_reg_imm:$shift, pred:$p),
1179 [(set GPR:$Rd, CPSR, (opnode so_reg_imm:$shift,
1182 def rsr : ARMPseudoInst<(outs GPR:$Rd),
1183 (ins GPR:$Rn, so_reg_reg:$shift, pred:$p),
1185 [(set GPR:$Rd, CPSR, (opnode so_reg_reg:$shift,
1190 /// AI1_cmp_irs - Defines a set of (op r, {so_imm|r|so_reg}) cmp / test
1191 /// patterns. Similar to AsI1_bin_irs except the instruction does not produce
1192 /// a explicit result, only implicitly set CPSR.
1193 let isCompare = 1, Defs = [CPSR] in {
1194 multiclass AI1_cmp_irs<bits<4> opcod, string opc,
1195 InstrItinClass iii, InstrItinClass iir, InstrItinClass iis,
1196 PatFrag opnode, bit Commutable = 0> {
1197 def ri : AI1<opcod, (outs), (ins GPR:$Rn, so_imm:$imm), DPFrm, iii,
1199 [(opnode GPR:$Rn, so_imm:$imm)]> {
1204 let Inst{19-16} = Rn;
1205 let Inst{15-12} = 0b0000;
1206 let Inst{11-0} = imm;
1208 let Unpredictable{15-12} = 0b1111;
1210 def rr : AI1<opcod, (outs), (ins GPR:$Rn, GPR:$Rm), DPFrm, iir,
1212 [(opnode GPR:$Rn, GPR:$Rm)]> {
1215 let isCommutable = Commutable;
1218 let Inst{19-16} = Rn;
1219 let Inst{15-12} = 0b0000;
1220 let Inst{11-4} = 0b00000000;
1223 let Unpredictable{15-12} = 0b1111;
1225 def rsi : AI1<opcod, (outs),
1226 (ins GPR:$Rn, so_reg_imm:$shift), DPSoRegImmFrm, iis,
1227 opc, "\t$Rn, $shift",
1228 [(opnode GPR:$Rn, so_reg_imm:$shift)]> {
1233 let Inst{19-16} = Rn;
1234 let Inst{15-12} = 0b0000;
1235 let Inst{11-5} = shift{11-5};
1237 let Inst{3-0} = shift{3-0};
1239 let Unpredictable{15-12} = 0b1111;
1241 def rsr : AI1<opcod, (outs),
1242 (ins GPRnopc:$Rn, so_reg_reg:$shift), DPSoRegRegFrm, iis,
1243 opc, "\t$Rn, $shift",
1244 [(opnode GPRnopc:$Rn, so_reg_reg:$shift)]> {
1249 let Inst{19-16} = Rn;
1250 let Inst{15-12} = 0b0000;
1251 let Inst{11-8} = shift{11-8};
1253 let Inst{6-5} = shift{6-5};
1255 let Inst{3-0} = shift{3-0};
1257 let Unpredictable{15-12} = 0b1111;
1263 /// AI_ext_rrot - A unary operation with two forms: one whose operand is a
1264 /// register and one whose operand is a register rotated by 8/16/24.
1265 /// FIXME: Remove the 'r' variant. Its rot_imm is zero.
1266 class AI_ext_rrot<bits<8> opcod, string opc, PatFrag opnode>
1267 : AExtI<opcod, (outs GPRnopc:$Rd), (ins GPRnopc:$Rm, rot_imm:$rot),
1268 IIC_iEXTr, opc, "\t$Rd, $Rm$rot",
1269 [(set GPRnopc:$Rd, (opnode (rotr GPRnopc:$Rm, rot_imm:$rot)))]>,
1270 Requires<[IsARM, HasV6]> {
1274 let Inst{19-16} = 0b1111;
1275 let Inst{15-12} = Rd;
1276 let Inst{11-10} = rot;
1280 class AI_ext_rrot_np<bits<8> opcod, string opc>
1281 : AExtI<opcod, (outs GPRnopc:$Rd), (ins GPRnopc:$Rm, rot_imm:$rot),
1282 IIC_iEXTr, opc, "\t$Rd, $Rm$rot", []>,
1283 Requires<[IsARM, HasV6]> {
1285 let Inst{19-16} = 0b1111;
1286 let Inst{11-10} = rot;
1289 /// AI_exta_rrot - A binary operation with two forms: one whose operand is a
1290 /// register and one whose operand is a register rotated by 8/16/24.
1291 class AI_exta_rrot<bits<8> opcod, string opc, PatFrag opnode>
1292 : AExtI<opcod, (outs GPRnopc:$Rd), (ins GPR:$Rn, GPRnopc:$Rm, rot_imm:$rot),
1293 IIC_iEXTAr, opc, "\t$Rd, $Rn, $Rm$rot",
1294 [(set GPRnopc:$Rd, (opnode GPR:$Rn,
1295 (rotr GPRnopc:$Rm, rot_imm:$rot)))]>,
1296 Requires<[IsARM, HasV6]> {
1301 let Inst{19-16} = Rn;
1302 let Inst{15-12} = Rd;
1303 let Inst{11-10} = rot;
1304 let Inst{9-4} = 0b000111;
1308 class AI_exta_rrot_np<bits<8> opcod, string opc>
1309 : AExtI<opcod, (outs GPRnopc:$Rd), (ins GPR:$Rn, GPRnopc:$Rm, rot_imm:$rot),
1310 IIC_iEXTAr, opc, "\t$Rd, $Rn, $Rm$rot", []>,
1311 Requires<[IsARM, HasV6]> {
1314 let Inst{19-16} = Rn;
1315 let Inst{11-10} = rot;
1318 /// AI1_adde_sube_irs - Define instructions and patterns for adde and sube.
1319 let TwoOperandAliasConstraint = "$Rn = $Rd" in
1320 multiclass AI1_adde_sube_irs<bits<4> opcod, string opc, PatFrag opnode,
1321 bit Commutable = 0> {
1322 let hasPostISelHook = 1, Defs = [CPSR], Uses = [CPSR] in {
1323 def ri : AsI1<opcod, (outs GPR:$Rd), (ins GPR:$Rn, so_imm:$imm),
1324 DPFrm, IIC_iALUi, opc, "\t$Rd, $Rn, $imm",
1325 [(set GPR:$Rd, CPSR, (opnode GPR:$Rn, so_imm:$imm, CPSR))]>,
1331 let Inst{15-12} = Rd;
1332 let Inst{19-16} = Rn;
1333 let Inst{11-0} = imm;
1335 def rr : AsI1<opcod, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm),
1336 DPFrm, IIC_iALUr, opc, "\t$Rd, $Rn, $Rm",
1337 [(set GPR:$Rd, CPSR, (opnode GPR:$Rn, GPR:$Rm, CPSR))]>,
1342 let Inst{11-4} = 0b00000000;
1344 let isCommutable = Commutable;
1346 let Inst{15-12} = Rd;
1347 let Inst{19-16} = Rn;
1349 def rsi : AsI1<opcod, (outs GPR:$Rd),
1350 (ins GPR:$Rn, so_reg_imm:$shift),
1351 DPSoRegImmFrm, IIC_iALUsr, opc, "\t$Rd, $Rn, $shift",
1352 [(set GPR:$Rd, CPSR, (opnode GPR:$Rn, so_reg_imm:$shift, CPSR))]>,
1358 let Inst{19-16} = Rn;
1359 let Inst{15-12} = Rd;
1360 let Inst{11-5} = shift{11-5};
1362 let Inst{3-0} = shift{3-0};
1364 def rsr : AsI1<opcod, (outs GPRnopc:$Rd),
1365 (ins GPRnopc:$Rn, so_reg_reg:$shift),
1366 DPSoRegRegFrm, IIC_iALUsr, opc, "\t$Rd, $Rn, $shift",
1367 [(set GPRnopc:$Rd, CPSR,
1368 (opnode GPRnopc:$Rn, so_reg_reg:$shift, CPSR))]>,
1374 let Inst{19-16} = Rn;
1375 let Inst{15-12} = Rd;
1376 let Inst{11-8} = shift{11-8};
1378 let Inst{6-5} = shift{6-5};
1380 let Inst{3-0} = shift{3-0};
1385 /// AI1_rsc_irs - Define instructions and patterns for rsc
1386 let TwoOperandAliasConstraint = "$Rn = $Rd" in
1387 multiclass AI1_rsc_irs<bits<4> opcod, string opc, PatFrag opnode> {
1388 let hasPostISelHook = 1, Defs = [CPSR], Uses = [CPSR] in {
1389 def ri : AsI1<opcod, (outs GPR:$Rd), (ins GPR:$Rn, so_imm:$imm),
1390 DPFrm, IIC_iALUi, opc, "\t$Rd, $Rn, $imm",
1391 [(set GPR:$Rd, CPSR, (opnode so_imm:$imm, GPR:$Rn, CPSR))]>,
1397 let Inst{15-12} = Rd;
1398 let Inst{19-16} = Rn;
1399 let Inst{11-0} = imm;
1401 def rr : AsI1<opcod, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm),
1402 DPFrm, IIC_iALUr, opc, "\t$Rd, $Rn, $Rm",
1403 [/* pattern left blank */]> {
1407 let Inst{11-4} = 0b00000000;
1410 let Inst{15-12} = Rd;
1411 let Inst{19-16} = Rn;
1413 def rsi : AsI1<opcod, (outs GPR:$Rd), (ins GPR:$Rn, so_reg_imm:$shift),
1414 DPSoRegImmFrm, IIC_iALUsr, opc, "\t$Rd, $Rn, $shift",
1415 [(set GPR:$Rd, CPSR, (opnode so_reg_imm:$shift, GPR:$Rn, CPSR))]>,
1421 let Inst{19-16} = Rn;
1422 let Inst{15-12} = Rd;
1423 let Inst{11-5} = shift{11-5};
1425 let Inst{3-0} = shift{3-0};
1427 def rsr : AsI1<opcod, (outs GPR:$Rd), (ins GPR:$Rn, so_reg_reg:$shift),
1428 DPSoRegRegFrm, IIC_iALUsr, opc, "\t$Rd, $Rn, $shift",
1429 [(set GPR:$Rd, CPSR, (opnode so_reg_reg:$shift, GPR:$Rn, CPSR))]>,
1435 let Inst{19-16} = Rn;
1436 let Inst{15-12} = Rd;
1437 let Inst{11-8} = shift{11-8};
1439 let Inst{6-5} = shift{6-5};
1441 let Inst{3-0} = shift{3-0};
1446 let canFoldAsLoad = 1, isReMaterializable = 1 in {
1447 multiclass AI_ldr1<bit isByte, string opc, InstrItinClass iii,
1448 InstrItinClass iir, PatFrag opnode> {
1449 // Note: We use the complex addrmode_imm12 rather than just an input
1450 // GPR and a constrained immediate so that we can use this to match
1451 // frame index references and avoid matching constant pool references.
1452 def i12: AI2ldst<0b010, 1, isByte, (outs GPR:$Rt), (ins addrmode_imm12:$addr),
1453 AddrMode_i12, LdFrm, iii, opc, "\t$Rt, $addr",
1454 [(set GPR:$Rt, (opnode addrmode_imm12:$addr))]> {
1457 let Inst{23} = addr{12}; // U (add = ('U' == 1))
1458 let Inst{19-16} = addr{16-13}; // Rn
1459 let Inst{15-12} = Rt;
1460 let Inst{11-0} = addr{11-0}; // imm12
1462 def rs : AI2ldst<0b011, 1, isByte, (outs GPR:$Rt), (ins ldst_so_reg:$shift),
1463 AddrModeNone, LdFrm, iir, opc, "\t$Rt, $shift",
1464 [(set GPR:$Rt, (opnode ldst_so_reg:$shift))]> {
1467 let shift{4} = 0; // Inst{4} = 0
1468 let Inst{23} = shift{12}; // U (add = ('U' == 1))
1469 let Inst{19-16} = shift{16-13}; // Rn
1470 let Inst{15-12} = Rt;
1471 let Inst{11-0} = shift{11-0};
1476 let canFoldAsLoad = 1, isReMaterializable = 1 in {
1477 multiclass AI_ldr1nopc<bit isByte, string opc, InstrItinClass iii,
1478 InstrItinClass iir, PatFrag opnode> {
1479 // Note: We use the complex addrmode_imm12 rather than just an input
1480 // GPR and a constrained immediate so that we can use this to match
1481 // frame index references and avoid matching constant pool references.
1482 def i12: AI2ldst<0b010, 1, isByte, (outs GPRnopc:$Rt),
1483 (ins addrmode_imm12:$addr),
1484 AddrMode_i12, LdFrm, iii, opc, "\t$Rt, $addr",
1485 [(set GPRnopc:$Rt, (opnode addrmode_imm12:$addr))]> {
1488 let Inst{23} = addr{12}; // U (add = ('U' == 1))
1489 let Inst{19-16} = addr{16-13}; // Rn
1490 let Inst{15-12} = Rt;
1491 let Inst{11-0} = addr{11-0}; // imm12
1493 def rs : AI2ldst<0b011, 1, isByte, (outs GPRnopc:$Rt),
1494 (ins ldst_so_reg:$shift),
1495 AddrModeNone, LdFrm, iir, opc, "\t$Rt, $shift",
1496 [(set GPRnopc:$Rt, (opnode ldst_so_reg:$shift))]> {
1499 let shift{4} = 0; // Inst{4} = 0
1500 let Inst{23} = shift{12}; // U (add = ('U' == 1))
1501 let Inst{19-16} = shift{16-13}; // Rn
1502 let Inst{15-12} = Rt;
1503 let Inst{11-0} = shift{11-0};
1509 multiclass AI_str1<bit isByte, string opc, InstrItinClass iii,
1510 InstrItinClass iir, PatFrag opnode> {
1511 // Note: We use the complex addrmode_imm12 rather than just an input
1512 // GPR and a constrained immediate so that we can use this to match
1513 // frame index references and avoid matching constant pool references.
1514 def i12 : AI2ldst<0b010, 0, isByte, (outs),
1515 (ins GPR:$Rt, addrmode_imm12:$addr),
1516 AddrMode_i12, StFrm, iii, opc, "\t$Rt, $addr",
1517 [(opnode GPR:$Rt, addrmode_imm12:$addr)]> {
1520 let Inst{23} = addr{12}; // U (add = ('U' == 1))
1521 let Inst{19-16} = addr{16-13}; // Rn
1522 let Inst{15-12} = Rt;
1523 let Inst{11-0} = addr{11-0}; // imm12
1525 def rs : AI2ldst<0b011, 0, isByte, (outs), (ins GPR:$Rt, ldst_so_reg:$shift),
1526 AddrModeNone, StFrm, iir, opc, "\t$Rt, $shift",
1527 [(opnode GPR:$Rt, ldst_so_reg:$shift)]> {
1530 let shift{4} = 0; // Inst{4} = 0
1531 let Inst{23} = shift{12}; // U (add = ('U' == 1))
1532 let Inst{19-16} = shift{16-13}; // Rn
1533 let Inst{15-12} = Rt;
1534 let Inst{11-0} = shift{11-0};
1538 multiclass AI_str1nopc<bit isByte, string opc, InstrItinClass iii,
1539 InstrItinClass iir, PatFrag opnode> {
1540 // Note: We use the complex addrmode_imm12 rather than just an input
1541 // GPR and a constrained immediate so that we can use this to match
1542 // frame index references and avoid matching constant pool references.
1543 def i12 : AI2ldst<0b010, 0, isByte, (outs),
1544 (ins GPRnopc:$Rt, addrmode_imm12:$addr),
1545 AddrMode_i12, StFrm, iii, opc, "\t$Rt, $addr",
1546 [(opnode GPRnopc:$Rt, addrmode_imm12:$addr)]> {
1549 let Inst{23} = addr{12}; // U (add = ('U' == 1))
1550 let Inst{19-16} = addr{16-13}; // Rn
1551 let Inst{15-12} = Rt;
1552 let Inst{11-0} = addr{11-0}; // imm12
1554 def rs : AI2ldst<0b011, 0, isByte, (outs),
1555 (ins GPRnopc:$Rt, ldst_so_reg:$shift),
1556 AddrModeNone, StFrm, iir, opc, "\t$Rt, $shift",
1557 [(opnode GPRnopc:$Rt, ldst_so_reg:$shift)]> {
1560 let shift{4} = 0; // Inst{4} = 0
1561 let Inst{23} = shift{12}; // U (add = ('U' == 1))
1562 let Inst{19-16} = shift{16-13}; // Rn
1563 let Inst{15-12} = Rt;
1564 let Inst{11-0} = shift{11-0};
1569 //===----------------------------------------------------------------------===//
1571 //===----------------------------------------------------------------------===//
1573 //===----------------------------------------------------------------------===//
1574 // Miscellaneous Instructions.
1577 /// CONSTPOOL_ENTRY - This instruction represents a floating constant pool in
1578 /// the function. The first operand is the ID# for this instruction, the second
1579 /// is the index into the MachineConstantPool that this is, the third is the
1580 /// size in bytes of this constant pool entry.
1581 let neverHasSideEffects = 1, isNotDuplicable = 1 in
1582 def CONSTPOOL_ENTRY :
1583 PseudoInst<(outs), (ins cpinst_operand:$instid, cpinst_operand:$cpidx,
1584 i32imm:$size), NoItinerary, []>;
1586 // FIXME: Marking these as hasSideEffects is necessary to prevent machine DCE
1587 // from removing one half of the matched pairs. That breaks PEI, which assumes
1588 // these will always be in pairs, and asserts if it finds otherwise. Better way?
1589 let Defs = [SP], Uses = [SP], hasSideEffects = 1 in {
1590 def ADJCALLSTACKUP :
1591 PseudoInst<(outs), (ins i32imm:$amt1, i32imm:$amt2, pred:$p), NoItinerary,
1592 [(ARMcallseq_end timm:$amt1, timm:$amt2)]>;
1594 def ADJCALLSTACKDOWN :
1595 PseudoInst<(outs), (ins i32imm:$amt, pred:$p), NoItinerary,
1596 [(ARMcallseq_start timm:$amt)]>;
1599 // Atomic pseudo-insts which will be lowered to ldrexd/strexd loops.
1600 // (These pseudos use a hand-written selection code).
1601 let usesCustomInserter = 1, Defs = [CPSR], mayLoad = 1, mayStore = 1 in {
1602 def ATOMOR6432 : PseudoInst<(outs GPR:$dst1, GPR:$dst2),
1603 (ins GPR:$addr, GPR:$src1, GPR:$src2),
1605 def ATOMXOR6432 : PseudoInst<(outs GPR:$dst1, GPR:$dst2),
1606 (ins GPR:$addr, GPR:$src1, GPR:$src2),
1608 def ATOMADD6432 : PseudoInst<(outs GPR:$dst1, GPR:$dst2),
1609 (ins GPR:$addr, GPR:$src1, GPR:$src2),
1611 def ATOMSUB6432 : PseudoInst<(outs GPR:$dst1, GPR:$dst2),
1612 (ins GPR:$addr, GPR:$src1, GPR:$src2),
1614 def ATOMNAND6432 : PseudoInst<(outs GPR:$dst1, GPR:$dst2),
1615 (ins GPR:$addr, GPR:$src1, GPR:$src2),
1617 def ATOMAND6432 : PseudoInst<(outs GPR:$dst1, GPR:$dst2),
1618 (ins GPR:$addr, GPR:$src1, GPR:$src2),
1620 def ATOMSWAP6432 : PseudoInst<(outs GPR:$dst1, GPR:$dst2),
1621 (ins GPR:$addr, GPR:$src1, GPR:$src2),
1623 def ATOMCMPXCHG6432 : PseudoInst<(outs GPR:$dst1, GPR:$dst2),
1624 (ins GPR:$addr, GPR:$cmp1, GPR:$cmp2,
1625 GPR:$set1, GPR:$set2),
1629 def HINT : AI<(outs), (ins imm0_255:$imm), MiscFrm, NoItinerary,
1630 "hint", "\t$imm", []>, Requires<[IsARM, HasV6]> {
1632 let Inst{27-8} = 0b00110010000011110000;
1633 let Inst{7-0} = imm;
1636 def : InstAlias<"nop$p", (HINT 0, pred:$p)>, Requires<[IsARM, HasV6T2]>;
1637 def : InstAlias<"yield$p", (HINT 1, pred:$p)>, Requires<[IsARM, HasV6T2]>;
1638 def : InstAlias<"wfe$p", (HINT 2, pred:$p)>, Requires<[IsARM, HasV6T2]>;
1639 def : InstAlias<"wfi$p", (HINT 3, pred:$p)>, Requires<[IsARM, HasV6T2]>;
1640 def : InstAlias<"sev$p", (HINT 4, pred:$p)>, Requires<[IsARM, HasV6T2]>;
1642 def SEL : AI<(outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm), DPFrm, NoItinerary, "sel",
1643 "\t$Rd, $Rn, $Rm", []>, Requires<[IsARM, HasV6]> {
1648 let Inst{15-12} = Rd;
1649 let Inst{19-16} = Rn;
1650 let Inst{27-20} = 0b01101000;
1651 let Inst{7-4} = 0b1011;
1652 let Inst{11-8} = 0b1111;
1653 let Unpredictable{11-8} = 0b1111;
1656 // The 16-bit operand $val can be used by a debugger to store more information
1657 // about the breakpoint.
1658 def BKPT : AI<(outs), (ins imm0_65535:$val), MiscFrm, NoItinerary,
1659 "bkpt", "\t$val", []>, Requires<[IsARM]> {
1661 let Inst{3-0} = val{3-0};
1662 let Inst{19-8} = val{15-4};
1663 let Inst{27-20} = 0b00010010;
1664 let Inst{7-4} = 0b0111;
1667 // Change Processor State
1668 // FIXME: We should use InstAlias to handle the optional operands.
1669 class CPS<dag iops, string asm_ops>
1670 : AXI<(outs), iops, MiscFrm, NoItinerary, !strconcat("cps", asm_ops),
1671 []>, Requires<[IsARM]> {
1677 let Inst{31-28} = 0b1111;
1678 let Inst{27-20} = 0b00010000;
1679 let Inst{19-18} = imod;
1680 let Inst{17} = M; // Enabled if mode is set;
1681 let Inst{16-9} = 0b00000000;
1682 let Inst{8-6} = iflags;
1684 let Inst{4-0} = mode;
1687 let DecoderMethod = "DecodeCPSInstruction" in {
1689 def CPS3p : CPS<(ins imod_op:$imod, iflags_op:$iflags, imm0_31:$mode),
1690 "$imod\t$iflags, $mode">;
1691 let mode = 0, M = 0 in
1692 def CPS2p : CPS<(ins imod_op:$imod, iflags_op:$iflags), "$imod\t$iflags">;
1694 let imod = 0, iflags = 0, M = 1 in
1695 def CPS1p : CPS<(ins imm0_31:$mode), "\t$mode">;
1698 // Preload signals the memory system of possible future data/instruction access.
1699 multiclass APreLoad<bits<1> read, bits<1> data, string opc> {
1701 def i12 : AXI<(outs), (ins addrmode_imm12:$addr), MiscFrm, IIC_Preload,
1702 !strconcat(opc, "\t$addr"),
1703 [(ARMPreload addrmode_imm12:$addr, (i32 read), (i32 data))]> {
1706 let Inst{31-26} = 0b111101;
1707 let Inst{25} = 0; // 0 for immediate form
1708 let Inst{24} = data;
1709 let Inst{23} = addr{12}; // U (add = ('U' == 1))
1710 let Inst{22} = read;
1711 let Inst{21-20} = 0b01;
1712 let Inst{19-16} = addr{16-13}; // Rn
1713 let Inst{15-12} = 0b1111;
1714 let Inst{11-0} = addr{11-0}; // imm12
1717 def rs : AXI<(outs), (ins ldst_so_reg:$shift), MiscFrm, IIC_Preload,
1718 !strconcat(opc, "\t$shift"),
1719 [(ARMPreload ldst_so_reg:$shift, (i32 read), (i32 data))]> {
1721 let Inst{31-26} = 0b111101;
1722 let Inst{25} = 1; // 1 for register form
1723 let Inst{24} = data;
1724 let Inst{23} = shift{12}; // U (add = ('U' == 1))
1725 let Inst{22} = read;
1726 let Inst{21-20} = 0b01;
1727 let Inst{19-16} = shift{16-13}; // Rn
1728 let Inst{15-12} = 0b1111;
1729 let Inst{11-0} = shift{11-0};
1734 defm PLD : APreLoad<1, 1, "pld">, Requires<[IsARM]>;
1735 defm PLDW : APreLoad<0, 1, "pldw">, Requires<[IsARM,HasV7,HasMP]>;
1736 defm PLI : APreLoad<1, 0, "pli">, Requires<[IsARM,HasV7]>;
1738 def SETEND : AXI<(outs), (ins setend_op:$end), MiscFrm, NoItinerary,
1739 "setend\t$end", []>, Requires<[IsARM]> {
1741 let Inst{31-10} = 0b1111000100000001000000;
1746 def DBG : AI<(outs), (ins imm0_15:$opt), MiscFrm, NoItinerary, "dbg", "\t$opt",
1747 []>, Requires<[IsARM, HasV7]> {
1749 let Inst{27-4} = 0b001100100000111100001111;
1750 let Inst{3-0} = opt;
1753 // A5.4 Permanently UNDEFINED instructions.
1754 let isBarrier = 1, isTerminator = 1 in
1755 def TRAP : AXI<(outs), (ins), MiscFrm, NoItinerary,
1758 let Inst = 0xe7ffdefe;
1761 // Address computation and loads and stores in PIC mode.
1762 let isNotDuplicable = 1 in {
1763 def PICADD : ARMPseudoInst<(outs GPR:$dst), (ins GPR:$a, pclabel:$cp, pred:$p),
1765 [(set GPR:$dst, (ARMpic_add GPR:$a, imm:$cp))]>;
1767 let AddedComplexity = 10 in {
1768 def PICLDR : ARMPseudoInst<(outs GPR:$dst), (ins addrmodepc:$addr, pred:$p),
1770 [(set GPR:$dst, (load addrmodepc:$addr))]>;
1772 def PICLDRH : ARMPseudoInst<(outs GPR:$Rt), (ins addrmodepc:$addr, pred:$p),
1774 [(set GPR:$Rt, (zextloadi16 addrmodepc:$addr))]>;
1776 def PICLDRB : ARMPseudoInst<(outs GPR:$Rt), (ins addrmodepc:$addr, pred:$p),
1778 [(set GPR:$Rt, (zextloadi8 addrmodepc:$addr))]>;
1780 def PICLDRSH : ARMPseudoInst<(outs GPR:$Rt), (ins addrmodepc:$addr, pred:$p),
1782 [(set GPR:$Rt, (sextloadi16 addrmodepc:$addr))]>;
1784 def PICLDRSB : ARMPseudoInst<(outs GPR:$Rt), (ins addrmodepc:$addr, pred:$p),
1786 [(set GPR:$Rt, (sextloadi8 addrmodepc:$addr))]>;
1788 let AddedComplexity = 10 in {
1789 def PICSTR : ARMPseudoInst<(outs), (ins GPR:$src, addrmodepc:$addr, pred:$p),
1790 4, IIC_iStore_r, [(store GPR:$src, addrmodepc:$addr)]>;
1792 def PICSTRH : ARMPseudoInst<(outs), (ins GPR:$src, addrmodepc:$addr, pred:$p),
1793 4, IIC_iStore_bh_r, [(truncstorei16 GPR:$src,
1794 addrmodepc:$addr)]>;
1796 def PICSTRB : ARMPseudoInst<(outs), (ins GPR:$src, addrmodepc:$addr, pred:$p),
1797 4, IIC_iStore_bh_r, [(truncstorei8 GPR:$src, addrmodepc:$addr)]>;
1799 } // isNotDuplicable = 1
1802 // LEApcrel - Load a pc-relative address into a register without offending the
1804 let neverHasSideEffects = 1, isReMaterializable = 1 in
1805 // The 'adr' mnemonic encodes differently if the label is before or after
1806 // the instruction. The {24-21} opcode bits are set by the fixup, as we don't
1807 // know until then which form of the instruction will be used.
1808 def ADR : AI1<{0,?,?,0}, (outs GPR:$Rd), (ins adrlabel:$label),
1809 MiscFrm, IIC_iALUi, "adr", "\t$Rd, $label", []> {
1812 let Inst{27-25} = 0b001;
1814 let Inst{23-22} = label{13-12};
1817 let Inst{19-16} = 0b1111;
1818 let Inst{15-12} = Rd;
1819 let Inst{11-0} = label{11-0};
1822 let hasSideEffects = 1 in {
1823 def LEApcrel : ARMPseudoInst<(outs GPR:$Rd), (ins i32imm:$label, pred:$p),
1826 def LEApcrelJT : ARMPseudoInst<(outs GPR:$Rd),
1827 (ins i32imm:$label, nohash_imm:$id, pred:$p),
1831 //===----------------------------------------------------------------------===//
1832 // Control Flow Instructions.
1835 let isReturn = 1, isTerminator = 1, isBarrier = 1 in {
1837 def BX_RET : AI<(outs), (ins), BrMiscFrm, IIC_Br,
1838 "bx", "\tlr", [(ARMretflag)]>,
1839 Requires<[IsARM, HasV4T]> {
1840 let Inst{27-0} = 0b0001001011111111111100011110;
1844 def MOVPCLR : AI<(outs), (ins), BrMiscFrm, IIC_Br,
1845 "mov", "\tpc, lr", [(ARMretflag)]>,
1846 Requires<[IsARM, NoV4T]> {
1847 let Inst{27-0} = 0b0001101000001111000000001110;
1851 // Indirect branches
1852 let isBranch = 1, isTerminator = 1, isBarrier = 1, isIndirectBranch = 1 in {
1854 def BX : AXI<(outs), (ins GPR:$dst), BrMiscFrm, IIC_Br, "bx\t$dst",
1855 [(brind GPR:$dst)]>,
1856 Requires<[IsARM, HasV4T]> {
1858 let Inst{31-4} = 0b1110000100101111111111110001;
1859 let Inst{3-0} = dst;
1862 def BX_pred : AI<(outs), (ins GPR:$dst), BrMiscFrm, IIC_Br,
1863 "bx", "\t$dst", [/* pattern left blank */]>,
1864 Requires<[IsARM, HasV4T]> {
1866 let Inst{27-4} = 0b000100101111111111110001;
1867 let Inst{3-0} = dst;
1871 // SP is marked as a use to prevent stack-pointer assignments that appear
1872 // immediately before calls from potentially appearing dead.
1874 // FIXME: Do we really need a non-predicated version? If so, it should
1875 // at least be a pseudo instruction expanding to the predicated version
1876 // at MC lowering time.
1877 Defs = [LR], Uses = [SP] in {
1878 def BL : ABXI<0b1011, (outs), (ins bl_target:$func),
1879 IIC_Br, "bl\t$func",
1880 [(ARMcall tglobaladdr:$func)]>,
1882 let Inst{31-28} = 0b1110;
1884 let Inst{23-0} = func;
1885 let DecoderMethod = "DecodeBranchImmInstruction";
1888 def BL_pred : ABI<0b1011, (outs), (ins bl_target:$func),
1889 IIC_Br, "bl", "\t$func",
1890 [(ARMcall_pred tglobaladdr:$func)]>,
1893 let Inst{23-0} = func;
1894 let DecoderMethod = "DecodeBranchImmInstruction";
1898 def BLX : AXI<(outs), (ins GPR:$func), BrMiscFrm,
1899 IIC_Br, "blx\t$func",
1900 [(ARMcall GPR:$func)]>,
1901 Requires<[IsARM, HasV5T]> {
1903 let Inst{31-4} = 0b1110000100101111111111110011;
1904 let Inst{3-0} = func;
1907 def BLX_pred : AI<(outs), (ins GPR:$func), BrMiscFrm,
1908 IIC_Br, "blx", "\t$func",
1909 [(ARMcall_pred GPR:$func)]>,
1910 Requires<[IsARM, HasV5T]> {
1912 let Inst{27-4} = 0b000100101111111111110011;
1913 let Inst{3-0} = func;
1917 // Note: Restrict $func to the tGPR regclass to prevent it being in LR.
1918 def BX_CALL : ARMPseudoInst<(outs), (ins tGPR:$func),
1919 8, IIC_Br, [(ARMcall_nolink tGPR:$func)]>,
1920 Requires<[IsARM, HasV4T]>;
1923 def BMOVPCRX_CALL : ARMPseudoInst<(outs), (ins tGPR:$func),
1924 8, IIC_Br, [(ARMcall_nolink tGPR:$func)]>,
1925 Requires<[IsARM, NoV4T]>;
1927 // mov lr, pc; b if callee is marked noreturn to avoid confusing the
1928 // return stack predictor.
1929 def BMOVPCB_CALL : ARMPseudoInst<(outs), (ins bl_target:$func),
1930 8, IIC_Br, [(ARMcall_nolink tglobaladdr:$func)]>,
1934 let isBranch = 1, isTerminator = 1 in {
1935 // FIXME: should be able to write a pattern for ARMBrcond, but can't use
1936 // a two-value operand where a dag node expects two operands. :(
1937 def Bcc : ABI<0b1010, (outs), (ins br_target:$target),
1938 IIC_Br, "b", "\t$target",
1939 [/*(ARMbrcond bb:$target, imm:$cc, CCR:$ccr)*/]> {
1941 let Inst{23-0} = target;
1942 let DecoderMethod = "DecodeBranchImmInstruction";
1945 let isBarrier = 1 in {
1946 // B is "predicable" since it's just a Bcc with an 'always' condition.
1947 let isPredicable = 1 in
1948 // FIXME: We shouldn't need this pseudo at all. Just using Bcc directly
1949 // should be sufficient.
1950 // FIXME: Is B really a Barrier? That doesn't seem right.
1951 def B : ARMPseudoExpand<(outs), (ins br_target:$target), 4, IIC_Br,
1952 [(br bb:$target)], (Bcc br_target:$target, (ops 14, zero_reg))>;
1954 let isNotDuplicable = 1, isIndirectBranch = 1 in {
1955 def BR_JTr : ARMPseudoInst<(outs),
1956 (ins GPR:$target, i32imm:$jt, i32imm:$id),
1958 [(ARMbrjt GPR:$target, tjumptable:$jt, imm:$id)]>;
1959 // FIXME: This shouldn't use the generic "addrmode2," but rather be split
1960 // into i12 and rs suffixed versions.
1961 def BR_JTm : ARMPseudoInst<(outs),
1962 (ins addrmode2:$target, i32imm:$jt, i32imm:$id),
1964 [(ARMbrjt (i32 (load addrmode2:$target)), tjumptable:$jt,
1966 def BR_JTadd : ARMPseudoInst<(outs),
1967 (ins GPR:$target, GPR:$idx, i32imm:$jt, i32imm:$id),
1969 [(ARMbrjt (add GPR:$target, GPR:$idx), tjumptable:$jt,
1971 } // isNotDuplicable = 1, isIndirectBranch = 1
1977 def BLXi : AXI<(outs), (ins blx_target:$target), BrMiscFrm, NoItinerary,
1978 "blx\t$target", []>,
1979 Requires<[IsARM, HasV5T]> {
1980 let Inst{31-25} = 0b1111101;
1982 let Inst{23-0} = target{24-1};
1983 let Inst{24} = target{0};
1986 // Branch and Exchange Jazelle
1987 def BXJ : ABI<0b0001, (outs), (ins GPR:$func), NoItinerary, "bxj", "\t$func",
1988 [/* pattern left blank */]> {
1990 let Inst{23-20} = 0b0010;
1991 let Inst{19-8} = 0xfff;
1992 let Inst{7-4} = 0b0010;
1993 let Inst{3-0} = func;
1998 let isCall = 1, isTerminator = 1, isReturn = 1, isBarrier = 1, Uses = [SP] in {
1999 def TCRETURNdi : PseudoInst<(outs), (ins i32imm:$dst), IIC_Br, []>;
2001 def TCRETURNri : PseudoInst<(outs), (ins tcGPR:$dst), IIC_Br, []>;
2003 def TAILJMPd : ARMPseudoExpand<(outs), (ins br_target:$dst),
2005 (Bcc br_target:$dst, (ops 14, zero_reg))>,
2008 def TAILJMPr : ARMPseudoExpand<(outs), (ins tcGPR:$dst),
2014 // Secure Monitor Call is a system instruction.
2015 def SMC : ABI<0b0001, (outs), (ins imm0_15:$opt), NoItinerary, "smc", "\t$opt",
2018 let Inst{23-4} = 0b01100000000000000111;
2019 let Inst{3-0} = opt;
2022 // Supervisor Call (Software Interrupt)
2023 let isCall = 1, Uses = [SP] in {
2024 def SVC : ABI<0b1111, (outs), (ins imm24b:$svc), IIC_Br, "svc", "\t$svc", []> {
2026 let Inst{23-0} = svc;
2030 // Store Return State
2031 class SRSI<bit wb, string asm>
2032 : XI<(outs), (ins imm0_31:$mode), AddrModeNone, 4, IndexModeNone, BrFrm,
2033 NoItinerary, asm, "", []> {
2035 let Inst{31-28} = 0b1111;
2036 let Inst{27-25} = 0b100;
2040 let Inst{19-16} = 0b1101; // SP
2041 let Inst{15-5} = 0b00000101000;
2042 let Inst{4-0} = mode;
2045 def SRSDA : SRSI<0, "srsda\tsp, $mode"> {
2046 let Inst{24-23} = 0;
2048 def SRSDA_UPD : SRSI<1, "srsda\tsp!, $mode"> {
2049 let Inst{24-23} = 0;
2051 def SRSDB : SRSI<0, "srsdb\tsp, $mode"> {
2052 let Inst{24-23} = 0b10;
2054 def SRSDB_UPD : SRSI<1, "srsdb\tsp!, $mode"> {
2055 let Inst{24-23} = 0b10;
2057 def SRSIA : SRSI<0, "srsia\tsp, $mode"> {
2058 let Inst{24-23} = 0b01;
2060 def SRSIA_UPD : SRSI<1, "srsia\tsp!, $mode"> {
2061 let Inst{24-23} = 0b01;
2063 def SRSIB : SRSI<0, "srsib\tsp, $mode"> {
2064 let Inst{24-23} = 0b11;
2066 def SRSIB_UPD : SRSI<1, "srsib\tsp!, $mode"> {
2067 let Inst{24-23} = 0b11;
2070 // Return From Exception
2071 class RFEI<bit wb, string asm>
2072 : XI<(outs), (ins GPR:$Rn), AddrModeNone, 4, IndexModeNone, BrFrm,
2073 NoItinerary, asm, "", []> {
2075 let Inst{31-28} = 0b1111;
2076 let Inst{27-25} = 0b100;
2080 let Inst{19-16} = Rn;
2081 let Inst{15-0} = 0xa00;
2084 def RFEDA : RFEI<0, "rfeda\t$Rn"> {
2085 let Inst{24-23} = 0;
2087 def RFEDA_UPD : RFEI<1, "rfeda\t$Rn!"> {
2088 let Inst{24-23} = 0;
2090 def RFEDB : RFEI<0, "rfedb\t$Rn"> {
2091 let Inst{24-23} = 0b10;
2093 def RFEDB_UPD : RFEI<1, "rfedb\t$Rn!"> {
2094 let Inst{24-23} = 0b10;
2096 def RFEIA : RFEI<0, "rfeia\t$Rn"> {
2097 let Inst{24-23} = 0b01;
2099 def RFEIA_UPD : RFEI<1, "rfeia\t$Rn!"> {
2100 let Inst{24-23} = 0b01;
2102 def RFEIB : RFEI<0, "rfeib\t$Rn"> {
2103 let Inst{24-23} = 0b11;
2105 def RFEIB_UPD : RFEI<1, "rfeib\t$Rn!"> {
2106 let Inst{24-23} = 0b11;
2109 //===----------------------------------------------------------------------===//
2110 // Load / Store Instructions.
2116 defm LDR : AI_ldr1<0, "ldr", IIC_iLoad_r, IIC_iLoad_si,
2117 UnOpFrag<(load node:$Src)>>;
2118 defm LDRB : AI_ldr1nopc<1, "ldrb", IIC_iLoad_bh_r, IIC_iLoad_bh_si,
2119 UnOpFrag<(zextloadi8 node:$Src)>>;
2120 defm STR : AI_str1<0, "str", IIC_iStore_r, IIC_iStore_si,
2121 BinOpFrag<(store node:$LHS, node:$RHS)>>;
2122 defm STRB : AI_str1nopc<1, "strb", IIC_iStore_bh_r, IIC_iStore_bh_si,
2123 BinOpFrag<(truncstorei8 node:$LHS, node:$RHS)>>;
2125 // Special LDR for loads from non-pc-relative constpools.
2126 let canFoldAsLoad = 1, mayLoad = 1, neverHasSideEffects = 1,
2127 isReMaterializable = 1, isCodeGenOnly = 1 in
2128 def LDRcp : AI2ldst<0b010, 1, 0, (outs GPR:$Rt), (ins addrmode_imm12:$addr),
2129 AddrMode_i12, LdFrm, IIC_iLoad_r, "ldr", "\t$Rt, $addr",
2133 let Inst{23} = addr{12}; // U (add = ('U' == 1))
2134 let Inst{19-16} = 0b1111;
2135 let Inst{15-12} = Rt;
2136 let Inst{11-0} = addr{11-0}; // imm12
2139 // Loads with zero extension
2140 def LDRH : AI3ld<0b1011, 1, (outs GPR:$Rt), (ins addrmode3:$addr), LdMiscFrm,
2141 IIC_iLoad_bh_r, "ldrh", "\t$Rt, $addr",
2142 [(set GPR:$Rt, (zextloadi16 addrmode3:$addr))]>;
2144 // Loads with sign extension
2145 def LDRSH : AI3ld<0b1111, 1, (outs GPR:$Rt), (ins addrmode3:$addr), LdMiscFrm,
2146 IIC_iLoad_bh_r, "ldrsh", "\t$Rt, $addr",
2147 [(set GPR:$Rt, (sextloadi16 addrmode3:$addr))]>;
2149 def LDRSB : AI3ld<0b1101, 1, (outs GPR:$Rt), (ins addrmode3:$addr), LdMiscFrm,
2150 IIC_iLoad_bh_r, "ldrsb", "\t$Rt, $addr",
2151 [(set GPR:$Rt, (sextloadi8 addrmode3:$addr))]>;
2153 let mayLoad = 1, neverHasSideEffects = 1, hasExtraDefRegAllocReq = 1 in {
2155 def LDRD : AI3ld<0b1101, 0, (outs GPR:$Rd, GPR:$dst2),
2156 (ins addrmode3:$addr), LdMiscFrm,
2157 IIC_iLoad_d_r, "ldrd", "\t$Rd, $dst2, $addr",
2158 []>, Requires<[IsARM, HasV5TE]>;
2162 multiclass AI2_ldridx<bit isByte, string opc,
2163 InstrItinClass iii, InstrItinClass iir> {
2164 def _PRE_IMM : AI2ldstidx<1, isByte, 1, (outs GPR:$Rt, GPR:$Rn_wb),
2165 (ins addrmode_imm12:$addr), IndexModePre, LdFrm, iii,
2166 opc, "\t$Rt, $addr!", "$addr.base = $Rn_wb", []> {
2169 let Inst{23} = addr{12};
2170 let Inst{19-16} = addr{16-13};
2171 let Inst{11-0} = addr{11-0};
2172 let DecoderMethod = "DecodeLDRPreImm";
2173 let AsmMatchConverter = "cvtLdWriteBackRegAddrModeImm12";
2176 def _PRE_REG : AI2ldstidx<1, isByte, 1, (outs GPR:$Rt, GPR:$Rn_wb),
2177 (ins ldst_so_reg:$addr), IndexModePre, LdFrm, iir,
2178 opc, "\t$Rt, $addr!", "$addr.base = $Rn_wb", []> {
2181 let Inst{23} = addr{12};
2182 let Inst{19-16} = addr{16-13};
2183 let Inst{11-0} = addr{11-0};
2185 let DecoderMethod = "DecodeLDRPreReg";
2186 let AsmMatchConverter = "cvtLdWriteBackRegAddrMode2";
2189 def _POST_REG : AI2ldstidx<1, isByte, 0, (outs GPR:$Rt, GPR:$Rn_wb),
2190 (ins addr_offset_none:$addr, am2offset_reg:$offset),
2191 IndexModePost, LdFrm, iir,
2192 opc, "\t$Rt, $addr, $offset",
2193 "$addr.base = $Rn_wb", []> {
2199 let Inst{23} = offset{12};
2200 let Inst{19-16} = addr;
2201 let Inst{11-0} = offset{11-0};
2203 let DecoderMethod = "DecodeAddrMode2IdxInstruction";
2206 def _POST_IMM : AI2ldstidx<1, isByte, 0, (outs GPR:$Rt, GPR:$Rn_wb),
2207 (ins addr_offset_none:$addr, am2offset_imm:$offset),
2208 IndexModePost, LdFrm, iii,
2209 opc, "\t$Rt, $addr, $offset",
2210 "$addr.base = $Rn_wb", []> {
2216 let Inst{23} = offset{12};
2217 let Inst{19-16} = addr;
2218 let Inst{11-0} = offset{11-0};
2220 let DecoderMethod = "DecodeAddrMode2IdxInstruction";
2225 let mayLoad = 1, neverHasSideEffects = 1 in {
2226 // FIXME: for LDR_PRE_REG etc. the itineray should be either IIC_iLoad_ru or
2227 // IIC_iLoad_siu depending on whether it the offset register is shifted.
2228 defm LDR : AI2_ldridx<0, "ldr", IIC_iLoad_iu, IIC_iLoad_ru>;
2229 defm LDRB : AI2_ldridx<1, "ldrb", IIC_iLoad_bh_iu, IIC_iLoad_bh_ru>;
2232 multiclass AI3_ldridx<bits<4> op, string opc, InstrItinClass itin> {
2233 def _PRE : AI3ldstidx<op, 1, 1, (outs GPR:$Rt, GPR:$Rn_wb),
2234 (ins addrmode3:$addr), IndexModePre,
2236 opc, "\t$Rt, $addr!", "$addr.base = $Rn_wb", []> {
2238 let Inst{23} = addr{8}; // U bit
2239 let Inst{22} = addr{13}; // 1 == imm8, 0 == Rm
2240 let Inst{19-16} = addr{12-9}; // Rn
2241 let Inst{11-8} = addr{7-4}; // imm7_4/zero
2242 let Inst{3-0} = addr{3-0}; // imm3_0/Rm
2243 let AsmMatchConverter = "cvtLdWriteBackRegAddrMode3";
2244 let DecoderMethod = "DecodeAddrMode3Instruction";
2246 def _POST : AI3ldstidx<op, 1, 0, (outs GPR:$Rt, GPR:$Rn_wb),
2247 (ins addr_offset_none:$addr, am3offset:$offset),
2248 IndexModePost, LdMiscFrm, itin,
2249 opc, "\t$Rt, $addr, $offset", "$addr.base = $Rn_wb",
2253 let Inst{23} = offset{8}; // U bit
2254 let Inst{22} = offset{9}; // 1 == imm8, 0 == Rm
2255 let Inst{19-16} = addr;
2256 let Inst{11-8} = offset{7-4}; // imm7_4/zero
2257 let Inst{3-0} = offset{3-0}; // imm3_0/Rm
2258 let DecoderMethod = "DecodeAddrMode3Instruction";
2262 let mayLoad = 1, neverHasSideEffects = 1 in {
2263 defm LDRH : AI3_ldridx<0b1011, "ldrh", IIC_iLoad_bh_ru>;
2264 defm LDRSH : AI3_ldridx<0b1111, "ldrsh", IIC_iLoad_bh_ru>;
2265 defm LDRSB : AI3_ldridx<0b1101, "ldrsb", IIC_iLoad_bh_ru>;
2266 let hasExtraDefRegAllocReq = 1 in {
2267 def LDRD_PRE : AI3ldstidx<0b1101, 0, 1, (outs GPR:$Rt, GPR:$Rt2, GPR:$Rn_wb),
2268 (ins addrmode3:$addr), IndexModePre,
2269 LdMiscFrm, IIC_iLoad_d_ru,
2270 "ldrd", "\t$Rt, $Rt2, $addr!",
2271 "$addr.base = $Rn_wb", []> {
2273 let Inst{23} = addr{8}; // U bit
2274 let Inst{22} = addr{13}; // 1 == imm8, 0 == Rm
2275 let Inst{19-16} = addr{12-9}; // Rn
2276 let Inst{11-8} = addr{7-4}; // imm7_4/zero
2277 let Inst{3-0} = addr{3-0}; // imm3_0/Rm
2278 let DecoderMethod = "DecodeAddrMode3Instruction";
2279 let AsmMatchConverter = "cvtLdrdPre";
2281 def LDRD_POST: AI3ldstidx<0b1101, 0, 0, (outs GPR:$Rt, GPR:$Rt2, GPR:$Rn_wb),
2282 (ins addr_offset_none:$addr, am3offset:$offset),
2283 IndexModePost, LdMiscFrm, IIC_iLoad_d_ru,
2284 "ldrd", "\t$Rt, $Rt2, $addr, $offset",
2285 "$addr.base = $Rn_wb", []> {
2288 let Inst{23} = offset{8}; // U bit
2289 let Inst{22} = offset{9}; // 1 == imm8, 0 == Rm
2290 let Inst{19-16} = addr;
2291 let Inst{11-8} = offset{7-4}; // imm7_4/zero
2292 let Inst{3-0} = offset{3-0}; // imm3_0/Rm
2293 let DecoderMethod = "DecodeAddrMode3Instruction";
2295 } // hasExtraDefRegAllocReq = 1
2296 } // mayLoad = 1, neverHasSideEffects = 1
2298 // LDRT, LDRBT, LDRSBT, LDRHT, LDRSHT.
2299 let mayLoad = 1, neverHasSideEffects = 1 in {
2300 def LDRT_POST_REG : AI2ldstidx<1, 0, 0, (outs GPR:$Rt, GPR:$Rn_wb),
2301 (ins addr_offset_none:$addr, am2offset_reg:$offset),
2302 IndexModePost, LdFrm, IIC_iLoad_ru,
2303 "ldrt", "\t$Rt, $addr, $offset",
2304 "$addr.base = $Rn_wb", []> {
2310 let Inst{23} = offset{12};
2311 let Inst{21} = 1; // overwrite
2312 let Inst{19-16} = addr;
2313 let Inst{11-5} = offset{11-5};
2315 let Inst{3-0} = offset{3-0};
2316 let DecoderMethod = "DecodeAddrMode2IdxInstruction";
2319 def LDRT_POST_IMM : AI2ldstidx<1, 0, 0, (outs GPR:$Rt, GPR:$Rn_wb),
2320 (ins addr_offset_none:$addr, am2offset_imm:$offset),
2321 IndexModePost, LdFrm, IIC_iLoad_ru,
2322 "ldrt", "\t$Rt, $addr, $offset",
2323 "$addr.base = $Rn_wb", []> {
2329 let Inst{23} = offset{12};
2330 let Inst{21} = 1; // overwrite
2331 let Inst{19-16} = addr;
2332 let Inst{11-0} = offset{11-0};
2333 let DecoderMethod = "DecodeAddrMode2IdxInstruction";
2336 def LDRBT_POST_REG : AI2ldstidx<1, 1, 0, (outs GPR:$Rt, GPR:$Rn_wb),
2337 (ins addr_offset_none:$addr, am2offset_reg:$offset),
2338 IndexModePost, LdFrm, IIC_iLoad_bh_ru,
2339 "ldrbt", "\t$Rt, $addr, $offset",
2340 "$addr.base = $Rn_wb", []> {
2346 let Inst{23} = offset{12};
2347 let Inst{21} = 1; // overwrite
2348 let Inst{19-16} = addr;
2349 let Inst{11-5} = offset{11-5};
2351 let Inst{3-0} = offset{3-0};
2352 let DecoderMethod = "DecodeAddrMode2IdxInstruction";
2355 def LDRBT_POST_IMM : AI2ldstidx<1, 1, 0, (outs GPR:$Rt, GPR:$Rn_wb),
2356 (ins addr_offset_none:$addr, am2offset_imm:$offset),
2357 IndexModePost, LdFrm, IIC_iLoad_bh_ru,
2358 "ldrbt", "\t$Rt, $addr, $offset",
2359 "$addr.base = $Rn_wb", []> {
2365 let Inst{23} = offset{12};
2366 let Inst{21} = 1; // overwrite
2367 let Inst{19-16} = addr;
2368 let Inst{11-0} = offset{11-0};
2369 let DecoderMethod = "DecodeAddrMode2IdxInstruction";
2372 multiclass AI3ldrT<bits<4> op, string opc> {
2373 def i : AI3ldstidxT<op, 1, (outs GPR:$Rt, GPR:$base_wb),
2374 (ins addr_offset_none:$addr, postidx_imm8:$offset),
2375 IndexModePost, LdMiscFrm, IIC_iLoad_bh_ru, opc,
2376 "\t$Rt, $addr, $offset", "$addr.base = $base_wb", []> {
2378 let Inst{23} = offset{8};
2380 let Inst{11-8} = offset{7-4};
2381 let Inst{3-0} = offset{3-0};
2382 let AsmMatchConverter = "cvtLdExtTWriteBackImm";
2384 def r : AI3ldstidxT<op, 1, (outs GPRnopc:$Rt, GPRnopc:$base_wb),
2385 (ins addr_offset_none:$addr, postidx_reg:$Rm),
2386 IndexModePost, LdMiscFrm, IIC_iLoad_bh_ru, opc,
2387 "\t$Rt, $addr, $Rm", "$addr.base = $base_wb", []> {
2389 let Inst{23} = Rm{4};
2392 let Unpredictable{11-8} = 0b1111;
2393 let Inst{3-0} = Rm{3-0};
2394 let AsmMatchConverter = "cvtLdExtTWriteBackReg";
2395 let DecoderMethod = "DecodeLDR";
2399 defm LDRSBT : AI3ldrT<0b1101, "ldrsbt">;
2400 defm LDRHT : AI3ldrT<0b1011, "ldrht">;
2401 defm LDRSHT : AI3ldrT<0b1111, "ldrsht">;
2406 // Stores with truncate
2407 def STRH : AI3str<0b1011, (outs), (ins GPR:$Rt, addrmode3:$addr), StMiscFrm,
2408 IIC_iStore_bh_r, "strh", "\t$Rt, $addr",
2409 [(truncstorei16 GPR:$Rt, addrmode3:$addr)]>;
2412 let mayStore = 1, neverHasSideEffects = 1, hasExtraSrcRegAllocReq = 1 in
2413 def STRD : AI3str<0b1111, (outs), (ins GPR:$Rt, GPR:$src2, addrmode3:$addr),
2414 StMiscFrm, IIC_iStore_d_r,
2415 "strd", "\t$Rt, $src2, $addr", []>,
2416 Requires<[IsARM, HasV5TE]> {
2421 multiclass AI2_stridx<bit isByte, string opc,
2422 InstrItinClass iii, InstrItinClass iir> {
2423 def _PRE_IMM : AI2ldstidx<0, isByte, 1, (outs GPR:$Rn_wb),
2424 (ins GPR:$Rt, addrmode_imm12:$addr), IndexModePre,
2426 opc, "\t$Rt, $addr!", "$addr.base = $Rn_wb", []> {
2429 let Inst{23} = addr{12}; // U (add = ('U' == 1))
2430 let Inst{19-16} = addr{16-13}; // Rn
2431 let Inst{11-0} = addr{11-0}; // imm12
2432 let AsmMatchConverter = "cvtStWriteBackRegAddrModeImm12";
2433 let DecoderMethod = "DecodeSTRPreImm";
2436 def _PRE_REG : AI2ldstidx<0, isByte, 1, (outs GPR:$Rn_wb),
2437 (ins GPR:$Rt, ldst_so_reg:$addr),
2438 IndexModePre, StFrm, iir,
2439 opc, "\t$Rt, $addr!", "$addr.base = $Rn_wb", []> {
2442 let Inst{23} = addr{12}; // U (add = ('U' == 1))
2443 let Inst{19-16} = addr{16-13}; // Rn
2444 let Inst{11-0} = addr{11-0};
2445 let Inst{4} = 0; // Inst{4} = 0
2446 let AsmMatchConverter = "cvtStWriteBackRegAddrMode2";
2447 let DecoderMethod = "DecodeSTRPreReg";
2449 def _POST_REG : AI2ldstidx<0, isByte, 0, (outs GPR:$Rn_wb),
2450 (ins GPR:$Rt, addr_offset_none:$addr, am2offset_reg:$offset),
2451 IndexModePost, StFrm, iir,
2452 opc, "\t$Rt, $addr, $offset",
2453 "$addr.base = $Rn_wb", []> {
2459 let Inst{23} = offset{12};
2460 let Inst{19-16} = addr;
2461 let Inst{11-0} = offset{11-0};
2464 let DecoderMethod = "DecodeAddrMode2IdxInstruction";
2467 def _POST_IMM : AI2ldstidx<0, isByte, 0, (outs GPR:$Rn_wb),
2468 (ins GPR:$Rt, addr_offset_none:$addr, am2offset_imm:$offset),
2469 IndexModePost, StFrm, iii,
2470 opc, "\t$Rt, $addr, $offset",
2471 "$addr.base = $Rn_wb", []> {
2477 let Inst{23} = offset{12};
2478 let Inst{19-16} = addr;
2479 let Inst{11-0} = offset{11-0};
2481 let DecoderMethod = "DecodeAddrMode2IdxInstruction";
2485 let mayStore = 1, neverHasSideEffects = 1 in {
2486 // FIXME: for STR_PRE_REG etc. the itineray should be either IIC_iStore_ru or
2487 // IIC_iStore_siu depending on whether it the offset register is shifted.
2488 defm STR : AI2_stridx<0, "str", IIC_iStore_iu, IIC_iStore_ru>;
2489 defm STRB : AI2_stridx<1, "strb", IIC_iStore_bh_iu, IIC_iStore_bh_ru>;
2492 def : ARMPat<(post_store GPR:$Rt, addr_offset_none:$addr,
2493 am2offset_reg:$offset),
2494 (STR_POST_REG GPR:$Rt, addr_offset_none:$addr,
2495 am2offset_reg:$offset)>;
2496 def : ARMPat<(post_store GPR:$Rt, addr_offset_none:$addr,
2497 am2offset_imm:$offset),
2498 (STR_POST_IMM GPR:$Rt, addr_offset_none:$addr,
2499 am2offset_imm:$offset)>;
2500 def : ARMPat<(post_truncsti8 GPR:$Rt, addr_offset_none:$addr,
2501 am2offset_reg:$offset),
2502 (STRB_POST_REG GPR:$Rt, addr_offset_none:$addr,
2503 am2offset_reg:$offset)>;
2504 def : ARMPat<(post_truncsti8 GPR:$Rt, addr_offset_none:$addr,
2505 am2offset_imm:$offset),
2506 (STRB_POST_IMM GPR:$Rt, addr_offset_none:$addr,
2507 am2offset_imm:$offset)>;
2509 // Pseudo-instructions for pattern matching the pre-indexed stores. We can't
2510 // put the patterns on the instruction definitions directly as ISel wants
2511 // the address base and offset to be separate operands, not a single
2512 // complex operand like we represent the instructions themselves. The
2513 // pseudos map between the two.
2514 let usesCustomInserter = 1,
2515 Constraints = "$Rn = $Rn_wb,@earlyclobber $Rn_wb" in {
2516 def STRi_preidx: ARMPseudoInst<(outs GPR:$Rn_wb),
2517 (ins GPR:$Rt, GPR:$Rn, am2offset_imm:$offset, pred:$p),
2520 (pre_store GPR:$Rt, GPR:$Rn, am2offset_imm:$offset))]>;
2521 def STRr_preidx: ARMPseudoInst<(outs GPR:$Rn_wb),
2522 (ins GPR:$Rt, GPR:$Rn, am2offset_reg:$offset, pred:$p),
2525 (pre_store GPR:$Rt, GPR:$Rn, am2offset_reg:$offset))]>;
2526 def STRBi_preidx: ARMPseudoInst<(outs GPR:$Rn_wb),
2527 (ins GPR:$Rt, GPR:$Rn, am2offset_imm:$offset, pred:$p),
2530 (pre_truncsti8 GPR:$Rt, GPR:$Rn, am2offset_imm:$offset))]>;
2531 def STRBr_preidx: ARMPseudoInst<(outs GPR:$Rn_wb),
2532 (ins GPR:$Rt, GPR:$Rn, am2offset_reg:$offset, pred:$p),
2535 (pre_truncsti8 GPR:$Rt, GPR:$Rn, am2offset_reg:$offset))]>;
2536 def STRH_preidx: ARMPseudoInst<(outs GPR:$Rn_wb),
2537 (ins GPR:$Rt, GPR:$Rn, am3offset:$offset, pred:$p),
2540 (pre_truncsti16 GPR:$Rt, GPR:$Rn, am3offset:$offset))]>;
2545 def STRH_PRE : AI3ldstidx<0b1011, 0, 1, (outs GPR:$Rn_wb),
2546 (ins GPR:$Rt, addrmode3:$addr), IndexModePre,
2547 StMiscFrm, IIC_iStore_bh_ru,
2548 "strh", "\t$Rt, $addr!", "$addr.base = $Rn_wb", []> {
2550 let Inst{23} = addr{8}; // U bit
2551 let Inst{22} = addr{13}; // 1 == imm8, 0 == Rm
2552 let Inst{19-16} = addr{12-9}; // Rn
2553 let Inst{11-8} = addr{7-4}; // imm7_4/zero
2554 let Inst{3-0} = addr{3-0}; // imm3_0/Rm
2555 let AsmMatchConverter = "cvtStWriteBackRegAddrMode3";
2556 let DecoderMethod = "DecodeAddrMode3Instruction";
2559 def STRH_POST : AI3ldstidx<0b1011, 0, 0, (outs GPR:$Rn_wb),
2560 (ins GPR:$Rt, addr_offset_none:$addr, am3offset:$offset),
2561 IndexModePost, StMiscFrm, IIC_iStore_bh_ru,
2562 "strh", "\t$Rt, $addr, $offset", "$addr.base = $Rn_wb",
2563 [(set GPR:$Rn_wb, (post_truncsti16 GPR:$Rt,
2564 addr_offset_none:$addr,
2565 am3offset:$offset))]> {
2568 let Inst{23} = offset{8}; // U bit
2569 let Inst{22} = offset{9}; // 1 == imm8, 0 == Rm
2570 let Inst{19-16} = addr;
2571 let Inst{11-8} = offset{7-4}; // imm7_4/zero
2572 let Inst{3-0} = offset{3-0}; // imm3_0/Rm
2573 let DecoderMethod = "DecodeAddrMode3Instruction";
2576 let mayStore = 1, neverHasSideEffects = 1, hasExtraSrcRegAllocReq = 1 in {
2577 def STRD_PRE : AI3ldstidx<0b1111, 0, 1, (outs GPR:$Rn_wb),
2578 (ins GPR:$Rt, GPR:$Rt2, addrmode3:$addr),
2579 IndexModePre, StMiscFrm, IIC_iStore_d_ru,
2580 "strd", "\t$Rt, $Rt2, $addr!",
2581 "$addr.base = $Rn_wb", []> {
2583 let Inst{23} = addr{8}; // U bit
2584 let Inst{22} = addr{13}; // 1 == imm8, 0 == Rm
2585 let Inst{19-16} = addr{12-9}; // Rn
2586 let Inst{11-8} = addr{7-4}; // imm7_4/zero
2587 let Inst{3-0} = addr{3-0}; // imm3_0/Rm
2588 let DecoderMethod = "DecodeAddrMode3Instruction";
2589 let AsmMatchConverter = "cvtStrdPre";
2592 def STRD_POST: AI3ldstidx<0b1111, 0, 0, (outs GPR:$Rn_wb),
2593 (ins GPR:$Rt, GPR:$Rt2, addr_offset_none:$addr,
2595 IndexModePost, StMiscFrm, IIC_iStore_d_ru,
2596 "strd", "\t$Rt, $Rt2, $addr, $offset",
2597 "$addr.base = $Rn_wb", []> {
2600 let Inst{23} = offset{8}; // U bit
2601 let Inst{22} = offset{9}; // 1 == imm8, 0 == Rm
2602 let Inst{19-16} = addr;
2603 let Inst{11-8} = offset{7-4}; // imm7_4/zero
2604 let Inst{3-0} = offset{3-0}; // imm3_0/Rm
2605 let DecoderMethod = "DecodeAddrMode3Instruction";
2607 } // mayStore = 1, neverHasSideEffects = 1, hasExtraSrcRegAllocReq = 1
2609 // STRT, STRBT, and STRHT
2611 def STRBT_POST_REG : AI2ldstidx<0, 1, 0, (outs GPR:$Rn_wb),
2612 (ins GPR:$Rt, addr_offset_none:$addr, am2offset_reg:$offset),
2613 IndexModePost, StFrm, IIC_iStore_bh_ru,
2614 "strbt", "\t$Rt, $addr, $offset",
2615 "$addr.base = $Rn_wb", []> {
2621 let Inst{23} = offset{12};
2622 let Inst{21} = 1; // overwrite
2623 let Inst{19-16} = addr;
2624 let Inst{11-5} = offset{11-5};
2626 let Inst{3-0} = offset{3-0};
2627 let DecoderMethod = "DecodeAddrMode2IdxInstruction";
2630 def STRBT_POST_IMM : AI2ldstidx<0, 1, 0, (outs GPR:$Rn_wb),
2631 (ins GPR:$Rt, addr_offset_none:$addr, am2offset_imm:$offset),
2632 IndexModePost, StFrm, IIC_iStore_bh_ru,
2633 "strbt", "\t$Rt, $addr, $offset",
2634 "$addr.base = $Rn_wb", []> {
2640 let Inst{23} = offset{12};
2641 let Inst{21} = 1; // overwrite
2642 let Inst{19-16} = addr;
2643 let Inst{11-0} = offset{11-0};
2644 let DecoderMethod = "DecodeAddrMode2IdxInstruction";
2647 let mayStore = 1, neverHasSideEffects = 1 in {
2648 def STRT_POST_REG : AI2ldstidx<0, 0, 0, (outs GPR:$Rn_wb),
2649 (ins GPR:$Rt, addr_offset_none:$addr, am2offset_reg:$offset),
2650 IndexModePost, StFrm, IIC_iStore_ru,
2651 "strt", "\t$Rt, $addr, $offset",
2652 "$addr.base = $Rn_wb", []> {
2658 let Inst{23} = offset{12};
2659 let Inst{21} = 1; // overwrite
2660 let Inst{19-16} = addr;
2661 let Inst{11-5} = offset{11-5};
2663 let Inst{3-0} = offset{3-0};
2664 let DecoderMethod = "DecodeAddrMode2IdxInstruction";
2667 def STRT_POST_IMM : AI2ldstidx<0, 0, 0, (outs GPR:$Rn_wb),
2668 (ins GPR:$Rt, addr_offset_none:$addr, am2offset_imm:$offset),
2669 IndexModePost, StFrm, IIC_iStore_ru,
2670 "strt", "\t$Rt, $addr, $offset",
2671 "$addr.base = $Rn_wb", []> {
2677 let Inst{23} = offset{12};
2678 let Inst{21} = 1; // overwrite
2679 let Inst{19-16} = addr;
2680 let Inst{11-0} = offset{11-0};
2681 let DecoderMethod = "DecodeAddrMode2IdxInstruction";
2686 multiclass AI3strT<bits<4> op, string opc> {
2687 def i : AI3ldstidxT<op, 0, (outs GPR:$base_wb),
2688 (ins GPR:$Rt, addr_offset_none:$addr, postidx_imm8:$offset),
2689 IndexModePost, StMiscFrm, IIC_iStore_bh_ru, opc,
2690 "\t$Rt, $addr, $offset", "$addr.base = $base_wb", []> {
2692 let Inst{23} = offset{8};
2694 let Inst{11-8} = offset{7-4};
2695 let Inst{3-0} = offset{3-0};
2696 let AsmMatchConverter = "cvtStExtTWriteBackImm";
2698 def r : AI3ldstidxT<op, 0, (outs GPR:$base_wb),
2699 (ins GPR:$Rt, addr_offset_none:$addr, postidx_reg:$Rm),
2700 IndexModePost, StMiscFrm, IIC_iStore_bh_ru, opc,
2701 "\t$Rt, $addr, $Rm", "$addr.base = $base_wb", []> {
2703 let Inst{23} = Rm{4};
2706 let Inst{3-0} = Rm{3-0};
2707 let AsmMatchConverter = "cvtStExtTWriteBackReg";
2712 defm STRHT : AI3strT<0b1011, "strht">;
2715 //===----------------------------------------------------------------------===//
2716 // Load / store multiple Instructions.
2719 multiclass arm_ldst_mult<string asm, string sfx, bit L_bit, bit P_bit, Format f,
2720 InstrItinClass itin, InstrItinClass itin_upd> {
2721 // IA is the default, so no need for an explicit suffix on the
2722 // mnemonic here. Without it is the canonical spelling.
2724 AXI4<(outs), (ins GPR:$Rn, pred:$p, reglist:$regs, variable_ops),
2725 IndexModeNone, f, itin,
2726 !strconcat(asm, "${p}\t$Rn, $regs", sfx), "", []> {
2727 let Inst{24-23} = 0b01; // Increment After
2728 let Inst{22} = P_bit;
2729 let Inst{21} = 0; // No writeback
2730 let Inst{20} = L_bit;
2733 AXI4<(outs GPR:$wb), (ins GPR:$Rn, pred:$p, reglist:$regs, variable_ops),
2734 IndexModeUpd, f, itin_upd,
2735 !strconcat(asm, "${p}\t$Rn!, $regs", sfx), "$Rn = $wb", []> {
2736 let Inst{24-23} = 0b01; // Increment After
2737 let Inst{22} = P_bit;
2738 let Inst{21} = 1; // Writeback
2739 let Inst{20} = L_bit;
2741 let DecoderMethod = "DecodeMemMultipleWritebackInstruction";
2744 AXI4<(outs), (ins GPR:$Rn, pred:$p, reglist:$regs, variable_ops),
2745 IndexModeNone, f, itin,
2746 !strconcat(asm, "da${p}\t$Rn, $regs", sfx), "", []> {
2747 let Inst{24-23} = 0b00; // Decrement After
2748 let Inst{22} = P_bit;
2749 let Inst{21} = 0; // No writeback
2750 let Inst{20} = L_bit;
2753 AXI4<(outs GPR:$wb), (ins GPR:$Rn, pred:$p, reglist:$regs, variable_ops),
2754 IndexModeUpd, f, itin_upd,
2755 !strconcat(asm, "da${p}\t$Rn!, $regs", sfx), "$Rn = $wb", []> {
2756 let Inst{24-23} = 0b00; // Decrement After
2757 let Inst{22} = P_bit;
2758 let Inst{21} = 1; // Writeback
2759 let Inst{20} = L_bit;
2761 let DecoderMethod = "DecodeMemMultipleWritebackInstruction";
2764 AXI4<(outs), (ins GPR:$Rn, pred:$p, reglist:$regs, variable_ops),
2765 IndexModeNone, f, itin,
2766 !strconcat(asm, "db${p}\t$Rn, $regs", sfx), "", []> {
2767 let Inst{24-23} = 0b10; // Decrement Before
2768 let Inst{22} = P_bit;
2769 let Inst{21} = 0; // No writeback
2770 let Inst{20} = L_bit;
2773 AXI4<(outs GPR:$wb), (ins GPR:$Rn, pred:$p, reglist:$regs, variable_ops),
2774 IndexModeUpd, f, itin_upd,
2775 !strconcat(asm, "db${p}\t$Rn!, $regs", sfx), "$Rn = $wb", []> {
2776 let Inst{24-23} = 0b10; // Decrement Before
2777 let Inst{22} = P_bit;
2778 let Inst{21} = 1; // Writeback
2779 let Inst{20} = L_bit;
2781 let DecoderMethod = "DecodeMemMultipleWritebackInstruction";
2784 AXI4<(outs), (ins GPR:$Rn, pred:$p, reglist:$regs, variable_ops),
2785 IndexModeNone, f, itin,
2786 !strconcat(asm, "ib${p}\t$Rn, $regs", sfx), "", []> {
2787 let Inst{24-23} = 0b11; // Increment Before
2788 let Inst{22} = P_bit;
2789 let Inst{21} = 0; // No writeback
2790 let Inst{20} = L_bit;
2793 AXI4<(outs GPR:$wb), (ins GPR:$Rn, pred:$p, reglist:$regs, variable_ops),
2794 IndexModeUpd, f, itin_upd,
2795 !strconcat(asm, "ib${p}\t$Rn!, $regs", sfx), "$Rn = $wb", []> {
2796 let Inst{24-23} = 0b11; // Increment Before
2797 let Inst{22} = P_bit;
2798 let Inst{21} = 1; // Writeback
2799 let Inst{20} = L_bit;
2801 let DecoderMethod = "DecodeMemMultipleWritebackInstruction";
2805 let neverHasSideEffects = 1 in {
2807 let mayLoad = 1, hasExtraDefRegAllocReq = 1 in
2808 defm LDM : arm_ldst_mult<"ldm", "", 1, 0, LdStMulFrm, IIC_iLoad_m,
2811 let mayStore = 1, hasExtraSrcRegAllocReq = 1 in
2812 defm STM : arm_ldst_mult<"stm", "", 0, 0, LdStMulFrm, IIC_iStore_m,
2815 } // neverHasSideEffects
2817 // FIXME: remove when we have a way to marking a MI with these properties.
2818 // FIXME: Should pc be an implicit operand like PICADD, etc?
2819 let isReturn = 1, isTerminator = 1, isBarrier = 1, mayLoad = 1,
2820 hasExtraDefRegAllocReq = 1, isCodeGenOnly = 1 in
2821 def LDMIA_RET : ARMPseudoExpand<(outs GPR:$wb), (ins GPR:$Rn, pred:$p,
2822 reglist:$regs, variable_ops),
2823 4, IIC_iLoad_mBr, [],
2824 (LDMIA_UPD GPR:$wb, GPR:$Rn, pred:$p, reglist:$regs)>,
2825 RegConstraint<"$Rn = $wb">;
2827 let mayLoad = 1, hasExtraDefRegAllocReq = 1 in
2828 defm sysLDM : arm_ldst_mult<"ldm", " ^", 1, 1, LdStMulFrm, IIC_iLoad_m,
2831 let mayStore = 1, hasExtraSrcRegAllocReq = 1 in
2832 defm sysSTM : arm_ldst_mult<"stm", " ^", 0, 1, LdStMulFrm, IIC_iStore_m,
2837 //===----------------------------------------------------------------------===//
2838 // Move Instructions.
2841 let neverHasSideEffects = 1 in
2842 def MOVr : AsI1<0b1101, (outs GPR:$Rd), (ins GPR:$Rm), DPFrm, IIC_iMOVr,
2843 "mov", "\t$Rd, $Rm", []>, UnaryDP {
2847 let Inst{19-16} = 0b0000;
2848 let Inst{11-4} = 0b00000000;
2851 let Inst{15-12} = Rd;
2854 // A version for the smaller set of tail call registers.
2855 let neverHasSideEffects = 1 in
2856 def MOVr_TC : AsI1<0b1101, (outs tcGPR:$Rd), (ins tcGPR:$Rm), DPFrm,
2857 IIC_iMOVr, "mov", "\t$Rd, $Rm", []>, UnaryDP {
2861 let Inst{11-4} = 0b00000000;
2864 let Inst{15-12} = Rd;
2867 def MOVsr : AsI1<0b1101, (outs GPRnopc:$Rd), (ins shift_so_reg_reg:$src),
2868 DPSoRegRegFrm, IIC_iMOVsr,
2869 "mov", "\t$Rd, $src",
2870 [(set GPRnopc:$Rd, shift_so_reg_reg:$src)]>, UnaryDP {
2873 let Inst{15-12} = Rd;
2874 let Inst{19-16} = 0b0000;
2875 let Inst{11-8} = src{11-8};
2877 let Inst{6-5} = src{6-5};
2879 let Inst{3-0} = src{3-0};
2883 def MOVsi : AsI1<0b1101, (outs GPR:$Rd), (ins shift_so_reg_imm:$src),
2884 DPSoRegImmFrm, IIC_iMOVsr,
2885 "mov", "\t$Rd, $src", [(set GPR:$Rd, shift_so_reg_imm:$src)]>,
2889 let Inst{15-12} = Rd;
2890 let Inst{19-16} = 0b0000;
2891 let Inst{11-5} = src{11-5};
2893 let Inst{3-0} = src{3-0};
2897 let isReMaterializable = 1, isAsCheapAsAMove = 1, isMoveImm = 1 in
2898 def MOVi : AsI1<0b1101, (outs GPR:$Rd), (ins so_imm:$imm), DPFrm, IIC_iMOVi,
2899 "mov", "\t$Rd, $imm", [(set GPR:$Rd, so_imm:$imm)]>, UnaryDP {
2903 let Inst{15-12} = Rd;
2904 let Inst{19-16} = 0b0000;
2905 let Inst{11-0} = imm;
2908 let isReMaterializable = 1, isAsCheapAsAMove = 1, isMoveImm = 1 in
2909 def MOVi16 : AI1<0b1000, (outs GPR:$Rd), (ins imm0_65535_expr:$imm),
2911 "movw", "\t$Rd, $imm",
2912 [(set GPR:$Rd, imm0_65535:$imm)]>,
2913 Requires<[IsARM, HasV6T2]>, UnaryDP {
2916 let Inst{15-12} = Rd;
2917 let Inst{11-0} = imm{11-0};
2918 let Inst{19-16} = imm{15-12};
2921 let DecoderMethod = "DecodeArmMOVTWInstruction";
2924 def : InstAlias<"mov${p} $Rd, $imm",
2925 (MOVi16 GPR:$Rd, imm0_65535_expr:$imm, pred:$p)>,
2928 def MOVi16_ga_pcrel : PseudoInst<(outs GPR:$Rd),
2929 (ins i32imm:$addr, pclabel:$id), IIC_iMOVi, []>;
2931 let Constraints = "$src = $Rd" in {
2932 def MOVTi16 : AI1<0b1010, (outs GPRnopc:$Rd),
2933 (ins GPR:$src, imm0_65535_expr:$imm),
2935 "movt", "\t$Rd, $imm",
2937 (or (and GPR:$src, 0xffff),
2938 lo16AllZero:$imm))]>, UnaryDP,
2939 Requires<[IsARM, HasV6T2]> {
2942 let Inst{15-12} = Rd;
2943 let Inst{11-0} = imm{11-0};
2944 let Inst{19-16} = imm{15-12};
2947 let DecoderMethod = "DecodeArmMOVTWInstruction";
2950 def MOVTi16_ga_pcrel : PseudoInst<(outs GPR:$Rd),
2951 (ins GPR:$src, i32imm:$addr, pclabel:$id), IIC_iMOVi, []>;
2955 def : ARMPat<(or GPR:$src, 0xffff0000), (MOVTi16 GPR:$src, 0xffff)>,
2956 Requires<[IsARM, HasV6T2]>;
2958 let Uses = [CPSR] in
2959 def RRX: PseudoInst<(outs GPR:$Rd), (ins GPR:$Rm), IIC_iMOVsi,
2960 [(set GPR:$Rd, (ARMrrx GPR:$Rm))]>, UnaryDP,
2963 // These aren't really mov instructions, but we have to define them this way
2964 // due to flag operands.
2966 let Defs = [CPSR] in {
2967 def MOVsrl_flag : PseudoInst<(outs GPR:$dst), (ins GPR:$src), IIC_iMOVsi,
2968 [(set GPR:$dst, (ARMsrl_flag GPR:$src))]>, UnaryDP,
2970 def MOVsra_flag : PseudoInst<(outs GPR:$dst), (ins GPR:$src), IIC_iMOVsi,
2971 [(set GPR:$dst, (ARMsra_flag GPR:$src))]>, UnaryDP,
2975 //===----------------------------------------------------------------------===//
2976 // Extend Instructions.
2981 def SXTB : AI_ext_rrot<0b01101010,
2982 "sxtb", UnOpFrag<(sext_inreg node:$Src, i8)>>;
2983 def SXTH : AI_ext_rrot<0b01101011,
2984 "sxth", UnOpFrag<(sext_inreg node:$Src, i16)>>;
2986 def SXTAB : AI_exta_rrot<0b01101010,
2987 "sxtab", BinOpFrag<(add node:$LHS, (sext_inreg node:$RHS, i8))>>;
2988 def SXTAH : AI_exta_rrot<0b01101011,
2989 "sxtah", BinOpFrag<(add node:$LHS, (sext_inreg node:$RHS,i16))>>;
2991 def SXTB16 : AI_ext_rrot_np<0b01101000, "sxtb16">;
2993 def SXTAB16 : AI_exta_rrot_np<0b01101000, "sxtab16">;
2997 let AddedComplexity = 16 in {
2998 def UXTB : AI_ext_rrot<0b01101110,
2999 "uxtb" , UnOpFrag<(and node:$Src, 0x000000FF)>>;
3000 def UXTH : AI_ext_rrot<0b01101111,
3001 "uxth" , UnOpFrag<(and node:$Src, 0x0000FFFF)>>;
3002 def UXTB16 : AI_ext_rrot<0b01101100,
3003 "uxtb16", UnOpFrag<(and node:$Src, 0x00FF00FF)>>;
3005 // FIXME: This pattern incorrectly assumes the shl operator is a rotate.
3006 // The transformation should probably be done as a combiner action
3007 // instead so we can include a check for masking back in the upper
3008 // eight bits of the source into the lower eight bits of the result.
3009 //def : ARMV6Pat<(and (shl GPR:$Src, (i32 8)), 0xFF00FF),
3010 // (UXTB16r_rot GPR:$Src, 3)>;
3011 def : ARMV6Pat<(and (srl GPR:$Src, (i32 8)), 0xFF00FF),
3012 (UXTB16 GPR:$Src, 1)>;
3014 def UXTAB : AI_exta_rrot<0b01101110, "uxtab",
3015 BinOpFrag<(add node:$LHS, (and node:$RHS, 0x00FF))>>;
3016 def UXTAH : AI_exta_rrot<0b01101111, "uxtah",
3017 BinOpFrag<(add node:$LHS, (and node:$RHS, 0xFFFF))>>;
3020 // This isn't safe in general, the add is two 16-bit units, not a 32-bit add.
3021 def UXTAB16 : AI_exta_rrot_np<0b01101100, "uxtab16">;
3024 def SBFX : I<(outs GPRnopc:$Rd),
3025 (ins GPRnopc:$Rn, imm0_31:$lsb, imm1_32:$width),
3026 AddrMode1, 4, IndexModeNone, DPFrm, IIC_iUNAsi,
3027 "sbfx", "\t$Rd, $Rn, $lsb, $width", "", []>,
3028 Requires<[IsARM, HasV6T2]> {
3033 let Inst{27-21} = 0b0111101;
3034 let Inst{6-4} = 0b101;
3035 let Inst{20-16} = width;
3036 let Inst{15-12} = Rd;
3037 let Inst{11-7} = lsb;
3041 def UBFX : I<(outs GPR:$Rd),
3042 (ins GPR:$Rn, imm0_31:$lsb, imm1_32:$width),
3043 AddrMode1, 4, IndexModeNone, DPFrm, IIC_iUNAsi,
3044 "ubfx", "\t$Rd, $Rn, $lsb, $width", "", []>,
3045 Requires<[IsARM, HasV6T2]> {
3050 let Inst{27-21} = 0b0111111;
3051 let Inst{6-4} = 0b101;
3052 let Inst{20-16} = width;
3053 let Inst{15-12} = Rd;
3054 let Inst{11-7} = lsb;
3058 //===----------------------------------------------------------------------===//
3059 // Arithmetic Instructions.
3062 defm ADD : AsI1_bin_irs<0b0100, "add",
3063 IIC_iALUi, IIC_iALUr, IIC_iALUsr,
3064 BinOpFrag<(add node:$LHS, node:$RHS)>, 1>;
3065 defm SUB : AsI1_bin_irs<0b0010, "sub",
3066 IIC_iALUi, IIC_iALUr, IIC_iALUsr,
3067 BinOpFrag<(sub node:$LHS, node:$RHS)>>;
3069 // ADD and SUB with 's' bit set.
3071 // Currently, ADDS/SUBS are pseudo opcodes that exist only in the
3072 // selection DAG. They are "lowered" to real ADD/SUB opcodes by
3073 // AdjustInstrPostInstrSelection where we determine whether or not to
3074 // set the "s" bit based on CPSR liveness.
3076 // FIXME: Eliminate ADDS/SUBS pseudo opcodes after adding tablegen
3077 // support for an optional CPSR definition that corresponds to the DAG
3078 // node's second value. We can then eliminate the implicit def of CPSR.
3079 defm ADDS : AsI1_bin_s_irs<IIC_iALUi, IIC_iALUr, IIC_iALUsr,
3080 BinOpFrag<(ARMaddc node:$LHS, node:$RHS)>, 1>;
3081 defm SUBS : AsI1_bin_s_irs<IIC_iALUi, IIC_iALUr, IIC_iALUsr,
3082 BinOpFrag<(ARMsubc node:$LHS, node:$RHS)>>;
3084 defm ADC : AI1_adde_sube_irs<0b0101, "adc",
3085 BinOpWithFlagFrag<(ARMadde node:$LHS, node:$RHS, node:$FLAG)>, 1>;
3086 defm SBC : AI1_adde_sube_irs<0b0110, "sbc",
3087 BinOpWithFlagFrag<(ARMsube node:$LHS, node:$RHS, node:$FLAG)>>;
3089 defm RSB : AsI1_rbin_irs<0b0011, "rsb",
3090 IIC_iALUi, IIC_iALUr, IIC_iALUsr,
3091 BinOpFrag<(sub node:$LHS, node:$RHS)>>;
3093 // FIXME: Eliminate them if we can write def : Pat patterns which defines
3094 // CPSR and the implicit def of CPSR is not needed.
3095 defm RSBS : AsI1_rbin_s_is<IIC_iALUi, IIC_iALUr, IIC_iALUsr,
3096 BinOpFrag<(ARMsubc node:$LHS, node:$RHS)>>;
3098 defm RSC : AI1_rsc_irs<0b0111, "rsc",
3099 BinOpWithFlagFrag<(ARMsube node:$LHS, node:$RHS, node:$FLAG)>>;
3101 // (sub X, imm) gets canonicalized to (add X, -imm). Match this form.
3102 // The assume-no-carry-in form uses the negation of the input since add/sub
3103 // assume opposite meanings of the carry flag (i.e., carry == !borrow).
3104 // See the definition of AddWithCarry() in the ARM ARM A2.2.1 for the gory
3106 def : ARMPat<(add GPR:$src, so_imm_neg:$imm),
3107 (SUBri GPR:$src, so_imm_neg:$imm)>;
3108 def : ARMPat<(ARMaddc GPR:$src, so_imm_neg:$imm),
3109 (SUBSri GPR:$src, so_imm_neg:$imm)>;
3111 def : ARMPat<(add GPR:$src, imm0_65535_neg:$imm),
3112 (SUBrr GPR:$src, (MOVi16 (imm_neg_XFORM imm:$imm)))>,
3113 Requires<[IsARM, HasV6T2]>;
3114 def : ARMPat<(ARMaddc GPR:$src, imm0_65535_neg:$imm),
3115 (SUBSrr GPR:$src, (MOVi16 (imm_neg_XFORM imm:$imm)))>,
3116 Requires<[IsARM, HasV6T2]>;
3118 // The with-carry-in form matches bitwise not instead of the negation.
3119 // Effectively, the inverse interpretation of the carry flag already accounts
3120 // for part of the negation.
3121 def : ARMPat<(ARMadde GPR:$src, so_imm_not:$imm, CPSR),
3122 (SBCri GPR:$src, so_imm_not:$imm)>;
3124 // Note: These are implemented in C++ code, because they have to generate
3125 // ADD/SUBrs instructions, which use a complex pattern that a xform function
3127 // (mul X, 2^n+1) -> (add (X << n), X)
3128 // (mul X, 2^n-1) -> (rsb X, (X << n))
3130 // ARM Arithmetic Instruction
3131 // GPR:$dst = GPR:$a op GPR:$b
3132 class AAI<bits<8> op27_20, bits<8> op11_4, string opc,
3133 list<dag> pattern = [],
3134 dag iops = (ins GPRnopc:$Rn, GPRnopc:$Rm),
3135 string asm = "\t$Rd, $Rn, $Rm">
3136 : AI<(outs GPRnopc:$Rd), iops, DPFrm, IIC_iALUr, opc, asm, pattern> {
3140 let Inst{27-20} = op27_20;
3141 let Inst{11-4} = op11_4;
3142 let Inst{19-16} = Rn;
3143 let Inst{15-12} = Rd;
3146 let Unpredictable{11-8} = 0b1111;
3149 // Saturating add/subtract
3151 def QADD : AAI<0b00010000, 0b00000101, "qadd",
3152 [(set GPRnopc:$Rd, (int_arm_qadd GPRnopc:$Rm, GPRnopc:$Rn))],
3153 (ins GPRnopc:$Rm, GPRnopc:$Rn), "\t$Rd, $Rm, $Rn">;
3154 def QSUB : AAI<0b00010010, 0b00000101, "qsub",
3155 [(set GPRnopc:$Rd, (int_arm_qsub GPRnopc:$Rm, GPRnopc:$Rn))],
3156 (ins GPRnopc:$Rm, GPRnopc:$Rn), "\t$Rd, $Rm, $Rn">;
3157 def QDADD : AAI<0b00010100, 0b00000101, "qdadd", [],
3158 (ins GPRnopc:$Rm, GPRnopc:$Rn),
3160 def QDSUB : AAI<0b00010110, 0b00000101, "qdsub", [],
3161 (ins GPRnopc:$Rm, GPRnopc:$Rn),
3164 def QADD16 : AAI<0b01100010, 0b11110001, "qadd16">;
3165 def QADD8 : AAI<0b01100010, 0b11111001, "qadd8">;
3166 def QASX : AAI<0b01100010, 0b11110011, "qasx">;
3167 def QSAX : AAI<0b01100010, 0b11110101, "qsax">;
3168 def QSUB16 : AAI<0b01100010, 0b11110111, "qsub16">;
3169 def QSUB8 : AAI<0b01100010, 0b11111111, "qsub8">;
3170 def UQADD16 : AAI<0b01100110, 0b11110001, "uqadd16">;
3171 def UQADD8 : AAI<0b01100110, 0b11111001, "uqadd8">;
3172 def UQASX : AAI<0b01100110, 0b11110011, "uqasx">;
3173 def UQSAX : AAI<0b01100110, 0b11110101, "uqsax">;
3174 def UQSUB16 : AAI<0b01100110, 0b11110111, "uqsub16">;
3175 def UQSUB8 : AAI<0b01100110, 0b11111111, "uqsub8">;
3177 // Signed/Unsigned add/subtract
3179 def SASX : AAI<0b01100001, 0b11110011, "sasx">;
3180 def SADD16 : AAI<0b01100001, 0b11110001, "sadd16">;
3181 def SADD8 : AAI<0b01100001, 0b11111001, "sadd8">;
3182 def SSAX : AAI<0b01100001, 0b11110101, "ssax">;
3183 def SSUB16 : AAI<0b01100001, 0b11110111, "ssub16">;
3184 def SSUB8 : AAI<0b01100001, 0b11111111, "ssub8">;
3185 def UASX : AAI<0b01100101, 0b11110011, "uasx">;
3186 def UADD16 : AAI<0b01100101, 0b11110001, "uadd16">;
3187 def UADD8 : AAI<0b01100101, 0b11111001, "uadd8">;
3188 def USAX : AAI<0b01100101, 0b11110101, "usax">;
3189 def USUB16 : AAI<0b01100101, 0b11110111, "usub16">;
3190 def USUB8 : AAI<0b01100101, 0b11111111, "usub8">;
3192 // Signed/Unsigned halving add/subtract
3194 def SHASX : AAI<0b01100011, 0b11110011, "shasx">;
3195 def SHADD16 : AAI<0b01100011, 0b11110001, "shadd16">;
3196 def SHADD8 : AAI<0b01100011, 0b11111001, "shadd8">;
3197 def SHSAX : AAI<0b01100011, 0b11110101, "shsax">;
3198 def SHSUB16 : AAI<0b01100011, 0b11110111, "shsub16">;
3199 def SHSUB8 : AAI<0b01100011, 0b11111111, "shsub8">;
3200 def UHASX : AAI<0b01100111, 0b11110011, "uhasx">;
3201 def UHADD16 : AAI<0b01100111, 0b11110001, "uhadd16">;
3202 def UHADD8 : AAI<0b01100111, 0b11111001, "uhadd8">;
3203 def UHSAX : AAI<0b01100111, 0b11110101, "uhsax">;
3204 def UHSUB16 : AAI<0b01100111, 0b11110111, "uhsub16">;
3205 def UHSUB8 : AAI<0b01100111, 0b11111111, "uhsub8">;
3207 // Unsigned Sum of Absolute Differences [and Accumulate].
3209 def USAD8 : AI<(outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm),
3210 MulFrm /* for convenience */, NoItinerary, "usad8",
3211 "\t$Rd, $Rn, $Rm", []>,
3212 Requires<[IsARM, HasV6]> {
3216 let Inst{27-20} = 0b01111000;
3217 let Inst{15-12} = 0b1111;
3218 let Inst{7-4} = 0b0001;
3219 let Inst{19-16} = Rd;
3220 let Inst{11-8} = Rm;
3223 def USADA8 : AI<(outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm, GPR:$Ra),
3224 MulFrm /* for convenience */, NoItinerary, "usada8",
3225 "\t$Rd, $Rn, $Rm, $Ra", []>,
3226 Requires<[IsARM, HasV6]> {
3231 let Inst{27-20} = 0b01111000;
3232 let Inst{7-4} = 0b0001;
3233 let Inst{19-16} = Rd;
3234 let Inst{15-12} = Ra;
3235 let Inst{11-8} = Rm;
3239 // Signed/Unsigned saturate
3241 def SSAT : AI<(outs GPRnopc:$Rd),
3242 (ins imm1_32:$sat_imm, GPRnopc:$Rn, shift_imm:$sh),
3243 SatFrm, NoItinerary, "ssat", "\t$Rd, $sat_imm, $Rn$sh", []> {
3248 let Inst{27-21} = 0b0110101;
3249 let Inst{5-4} = 0b01;
3250 let Inst{20-16} = sat_imm;
3251 let Inst{15-12} = Rd;
3252 let Inst{11-7} = sh{4-0};
3253 let Inst{6} = sh{5};
3257 def SSAT16 : AI<(outs GPRnopc:$Rd),
3258 (ins imm1_16:$sat_imm, GPRnopc:$Rn), SatFrm,
3259 NoItinerary, "ssat16", "\t$Rd, $sat_imm, $Rn", []> {
3263 let Inst{27-20} = 0b01101010;
3264 let Inst{11-4} = 0b11110011;
3265 let Inst{15-12} = Rd;
3266 let Inst{19-16} = sat_imm;
3270 def USAT : AI<(outs GPRnopc:$Rd),
3271 (ins imm0_31:$sat_imm, GPRnopc:$Rn, shift_imm:$sh),
3272 SatFrm, NoItinerary, "usat", "\t$Rd, $sat_imm, $Rn$sh", []> {
3277 let Inst{27-21} = 0b0110111;
3278 let Inst{5-4} = 0b01;
3279 let Inst{15-12} = Rd;
3280 let Inst{11-7} = sh{4-0};
3281 let Inst{6} = sh{5};
3282 let Inst{20-16} = sat_imm;
3286 def USAT16 : AI<(outs GPRnopc:$Rd),
3287 (ins imm0_15:$sat_imm, GPRnopc:$Rn), SatFrm,
3288 NoItinerary, "usat16", "\t$Rd, $sat_imm, $Rn", []> {
3292 let Inst{27-20} = 0b01101110;
3293 let Inst{11-4} = 0b11110011;
3294 let Inst{15-12} = Rd;
3295 let Inst{19-16} = sat_imm;
3299 def : ARMV6Pat<(int_arm_ssat GPRnopc:$a, imm:$pos),
3300 (SSAT imm:$pos, GPRnopc:$a, 0)>;
3301 def : ARMV6Pat<(int_arm_usat GPRnopc:$a, imm:$pos),
3302 (USAT imm:$pos, GPRnopc:$a, 0)>;
3304 //===----------------------------------------------------------------------===//
3305 // Bitwise Instructions.
3308 defm AND : AsI1_bin_irs<0b0000, "and",
3309 IIC_iBITi, IIC_iBITr, IIC_iBITsr,
3310 BinOpFrag<(and node:$LHS, node:$RHS)>, 1>;
3311 defm ORR : AsI1_bin_irs<0b1100, "orr",
3312 IIC_iBITi, IIC_iBITr, IIC_iBITsr,
3313 BinOpFrag<(or node:$LHS, node:$RHS)>, 1>;
3314 defm EOR : AsI1_bin_irs<0b0001, "eor",
3315 IIC_iBITi, IIC_iBITr, IIC_iBITsr,
3316 BinOpFrag<(xor node:$LHS, node:$RHS)>, 1>;
3317 defm BIC : AsI1_bin_irs<0b1110, "bic",
3318 IIC_iBITi, IIC_iBITr, IIC_iBITsr,
3319 BinOpFrag<(and node:$LHS, (not node:$RHS))>>;
3321 // FIXME: bf_inv_mask_imm should be two operands, the lsb and the msb, just
3322 // like in the actual instruction encoding. The complexity of mapping the mask
3323 // to the lsb/msb pair should be handled by ISel, not encapsulated in the
3324 // instruction description.
3325 def BFC : I<(outs GPR:$Rd), (ins GPR:$src, bf_inv_mask_imm:$imm),
3326 AddrMode1, 4, IndexModeNone, DPFrm, IIC_iUNAsi,
3327 "bfc", "\t$Rd, $imm", "$src = $Rd",
3328 [(set GPR:$Rd, (and GPR:$src, bf_inv_mask_imm:$imm))]>,
3329 Requires<[IsARM, HasV6T2]> {
3332 let Inst{27-21} = 0b0111110;
3333 let Inst{6-0} = 0b0011111;
3334 let Inst{15-12} = Rd;
3335 let Inst{11-7} = imm{4-0}; // lsb
3336 let Inst{20-16} = imm{9-5}; // msb
3339 // A8.6.18 BFI - Bitfield insert (Encoding A1)
3340 def BFI:I<(outs GPRnopc:$Rd), (ins GPRnopc:$src, GPR:$Rn, bf_inv_mask_imm:$imm),
3341 AddrMode1, 4, IndexModeNone, DPFrm, IIC_iUNAsi,
3342 "bfi", "\t$Rd, $Rn, $imm", "$src = $Rd",
3343 [(set GPRnopc:$Rd, (ARMbfi GPRnopc:$src, GPR:$Rn,
3344 bf_inv_mask_imm:$imm))]>,
3345 Requires<[IsARM, HasV6T2]> {
3349 let Inst{27-21} = 0b0111110;
3350 let Inst{6-4} = 0b001; // Rn: Inst{3-0} != 15
3351 let Inst{15-12} = Rd;
3352 let Inst{11-7} = imm{4-0}; // lsb
3353 let Inst{20-16} = imm{9-5}; // width
3357 def MVNr : AsI1<0b1111, (outs GPR:$Rd), (ins GPR:$Rm), DPFrm, IIC_iMVNr,
3358 "mvn", "\t$Rd, $Rm",
3359 [(set GPR:$Rd, (not GPR:$Rm))]>, UnaryDP {
3363 let Inst{19-16} = 0b0000;
3364 let Inst{11-4} = 0b00000000;
3365 let Inst{15-12} = Rd;
3368 def MVNsi : AsI1<0b1111, (outs GPR:$Rd), (ins so_reg_imm:$shift),
3369 DPSoRegImmFrm, IIC_iMVNsr, "mvn", "\t$Rd, $shift",
3370 [(set GPR:$Rd, (not so_reg_imm:$shift))]>, UnaryDP {
3374 let Inst{19-16} = 0b0000;
3375 let Inst{15-12} = Rd;
3376 let Inst{11-5} = shift{11-5};
3378 let Inst{3-0} = shift{3-0};
3380 def MVNsr : AsI1<0b1111, (outs GPR:$Rd), (ins so_reg_reg:$shift),
3381 DPSoRegRegFrm, IIC_iMVNsr, "mvn", "\t$Rd, $shift",
3382 [(set GPR:$Rd, (not so_reg_reg:$shift))]>, UnaryDP {
3386 let Inst{19-16} = 0b0000;
3387 let Inst{15-12} = Rd;
3388 let Inst{11-8} = shift{11-8};
3390 let Inst{6-5} = shift{6-5};
3392 let Inst{3-0} = shift{3-0};
3394 let isReMaterializable = 1, isAsCheapAsAMove = 1, isMoveImm = 1 in
3395 def MVNi : AsI1<0b1111, (outs GPR:$Rd), (ins so_imm:$imm), DPFrm,
3396 IIC_iMVNi, "mvn", "\t$Rd, $imm",
3397 [(set GPR:$Rd, so_imm_not:$imm)]>,UnaryDP {
3401 let Inst{19-16} = 0b0000;
3402 let Inst{15-12} = Rd;
3403 let Inst{11-0} = imm;
3406 def : ARMPat<(and GPR:$src, so_imm_not:$imm),
3407 (BICri GPR:$src, so_imm_not:$imm)>;
3409 //===----------------------------------------------------------------------===//
3410 // Multiply Instructions.
3412 class AsMul1I32<bits<7> opcod, dag oops, dag iops, InstrItinClass itin,
3413 string opc, string asm, list<dag> pattern>
3414 : AsMul1I<opcod, oops, iops, itin, opc, asm, pattern> {
3418 let Inst{19-16} = Rd;
3419 let Inst{11-8} = Rm;
3422 class AsMul1I64<bits<7> opcod, dag oops, dag iops, InstrItinClass itin,
3423 string opc, string asm, list<dag> pattern>
3424 : AsMul1I<opcod, oops, iops, itin, opc, asm, pattern> {
3429 let Inst{19-16} = RdHi;
3430 let Inst{15-12} = RdLo;
3431 let Inst{11-8} = Rm;
3434 class AsMla1I64<bits<7> opcod, dag oops, dag iops, InstrItinClass itin,
3435 string opc, string asm, list<dag> pattern>
3436 : AsMul1I<opcod, oops, iops, itin, opc, asm, pattern> {
3441 let Inst{19-16} = RdHi;
3442 let Inst{15-12} = RdLo;
3443 let Inst{11-8} = Rm;
3447 // FIXME: The v5 pseudos are only necessary for the additional Constraint
3448 // property. Remove them when it's possible to add those properties
3449 // on an individual MachineInstr, not just an instruction description.
3450 let isCommutable = 1, TwoOperandAliasConstraint = "$Rn = $Rd" in {
3451 def MUL : AsMul1I32<0b0000000, (outs GPRnopc:$Rd),
3452 (ins GPRnopc:$Rn, GPRnopc:$Rm),
3453 IIC_iMUL32, "mul", "\t$Rd, $Rn, $Rm",
3454 [(set GPRnopc:$Rd, (mul GPRnopc:$Rn, GPRnopc:$Rm))]>,
3455 Requires<[IsARM, HasV6]> {
3456 let Inst{15-12} = 0b0000;
3457 let Unpredictable{15-12} = 0b1111;
3460 let Constraints = "@earlyclobber $Rd" in
3461 def MULv5: ARMPseudoExpand<(outs GPRnopc:$Rd), (ins GPRnopc:$Rn, GPRnopc:$Rm,
3462 pred:$p, cc_out:$s),
3464 [(set GPRnopc:$Rd, (mul GPRnopc:$Rn, GPRnopc:$Rm))],
3465 (MUL GPRnopc:$Rd, GPRnopc:$Rn, GPRnopc:$Rm, pred:$p, cc_out:$s)>,
3466 Requires<[IsARM, NoV6, UseMulOps]>;
3469 def MLA : AsMul1I32<0b0000001, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm, GPR:$Ra),
3470 IIC_iMAC32, "mla", "\t$Rd, $Rn, $Rm, $Ra",
3471 [(set GPR:$Rd, (add (mul GPR:$Rn, GPR:$Rm), GPR:$Ra))]>,
3472 Requires<[IsARM, HasV6, UseMulOps]> {
3474 let Inst{15-12} = Ra;
3477 let Constraints = "@earlyclobber $Rd" in
3478 def MLAv5: ARMPseudoExpand<(outs GPR:$Rd),
3479 (ins GPR:$Rn, GPR:$Rm, GPR:$Ra, pred:$p, cc_out:$s),
3481 [(set GPR:$Rd, (add (mul GPR:$Rn, GPR:$Rm), GPR:$Ra))],
3482 (MLA GPR:$Rd, GPR:$Rn, GPR:$Rm, GPR:$Ra, pred:$p, cc_out:$s)>,
3483 Requires<[IsARM, NoV6]>;
3485 def MLS : AMul1I<0b0000011, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm, GPR:$Ra),
3486 IIC_iMAC32, "mls", "\t$Rd, $Rn, $Rm, $Ra",
3487 [(set GPR:$Rd, (sub GPR:$Ra, (mul GPR:$Rn, GPR:$Rm)))]>,
3488 Requires<[IsARM, HasV6T2, UseMulOps]> {
3493 let Inst{19-16} = Rd;
3494 let Inst{15-12} = Ra;
3495 let Inst{11-8} = Rm;
3499 // Extra precision multiplies with low / high results
3500 let neverHasSideEffects = 1 in {
3501 let isCommutable = 1 in {
3502 def SMULL : AsMul1I64<0b0000110, (outs GPR:$RdLo, GPR:$RdHi),
3503 (ins GPR:$Rn, GPR:$Rm), IIC_iMUL64,
3504 "smull", "\t$RdLo, $RdHi, $Rn, $Rm", []>,
3505 Requires<[IsARM, HasV6]>;
3507 def UMULL : AsMul1I64<0b0000100, (outs GPR:$RdLo, GPR:$RdHi),
3508 (ins GPR:$Rn, GPR:$Rm), IIC_iMUL64,
3509 "umull", "\t$RdLo, $RdHi, $Rn, $Rm", []>,
3510 Requires<[IsARM, HasV6]>;
3512 let Constraints = "@earlyclobber $RdLo,@earlyclobber $RdHi" in {
3513 def SMULLv5 : ARMPseudoExpand<(outs GPR:$RdLo, GPR:$RdHi),
3514 (ins GPR:$Rn, GPR:$Rm, pred:$p, cc_out:$s),
3516 (SMULL GPR:$RdLo, GPR:$RdHi, GPR:$Rn, GPR:$Rm, pred:$p, cc_out:$s)>,
3517 Requires<[IsARM, NoV6]>;
3519 def UMULLv5 : ARMPseudoExpand<(outs GPR:$RdLo, GPR:$RdHi),
3520 (ins GPR:$Rn, GPR:$Rm, pred:$p, cc_out:$s),
3522 (UMULL GPR:$RdLo, GPR:$RdHi, GPR:$Rn, GPR:$Rm, pred:$p, cc_out:$s)>,
3523 Requires<[IsARM, NoV6]>;
3527 // Multiply + accumulate
3528 def SMLAL : AsMla1I64<0b0000111, (outs GPR:$RdLo, GPR:$RdHi),
3529 (ins GPR:$Rn, GPR:$Rm, GPR:$RLo, GPR:$RHi), IIC_iMAC64,
3530 "smlal", "\t$RdLo, $RdHi, $Rn, $Rm", []>,
3531 RegConstraint<"$RLo = $RdLo, $RHi = $RdHi">, Requires<[IsARM, HasV6]>;
3532 def UMLAL : AsMla1I64<0b0000101, (outs GPR:$RdLo, GPR:$RdHi),
3533 (ins GPR:$Rn, GPR:$Rm, GPR:$RLo, GPR:$RHi), IIC_iMAC64,
3534 "umlal", "\t$RdLo, $RdHi, $Rn, $Rm", []>,
3535 RegConstraint<"$RLo = $RdLo, $RHi = $RdHi">, Requires<[IsARM, HasV6]>;
3537 def UMAAL : AMul1I <0b0000010, (outs GPR:$RdLo, GPR:$RdHi),
3538 (ins GPR:$Rn, GPR:$Rm), IIC_iMAC64,
3539 "umaal", "\t$RdLo, $RdHi, $Rn, $Rm", []>,
3540 Requires<[IsARM, HasV6]> {
3545 let Inst{19-16} = RdHi;
3546 let Inst{15-12} = RdLo;
3547 let Inst{11-8} = Rm;
3551 let Constraints = "$RLo = $RdLo,$RHi = $RdHi" in {
3552 def SMLALv5 : ARMPseudoExpand<(outs GPR:$RdLo, GPR:$RdHi),
3553 (ins GPR:$Rn, GPR:$Rm, GPR:$RLo, GPR:$RHi, pred:$p, cc_out:$s),
3555 (SMLAL GPR:$RdLo, GPR:$RdHi, GPR:$Rn, GPR:$Rm, GPR:$RLo, GPR:$RHi,
3556 pred:$p, cc_out:$s)>,
3557 Requires<[IsARM, NoV6]>;
3558 def UMLALv5 : ARMPseudoExpand<(outs GPR:$RdLo, GPR:$RdHi),
3559 (ins GPR:$Rn, GPR:$Rm, GPR:$RLo, GPR:$RHi, pred:$p, cc_out:$s),
3561 (UMLAL GPR:$RdLo, GPR:$RdHi, GPR:$Rn, GPR:$Rm, GPR:$RLo, GPR:$RHi,
3562 pred:$p, cc_out:$s)>,
3563 Requires<[IsARM, NoV6]>;
3566 let Constraints = "@earlyclobber $RdLo,@earlyclobber $RdHi" in {
3567 def UMAALv5 : ARMPseudoExpand<(outs GPR:$RdLo, GPR:$RdHi),
3568 (ins GPR:$Rn, GPR:$Rm, pred:$p),
3570 (UMAAL GPR:$RdLo, GPR:$RdHi, GPR:$Rn, GPR:$Rm, pred:$p)>,
3571 Requires<[IsARM, NoV6]>;
3574 } // neverHasSideEffects
3576 // Most significant word multiply
3577 def SMMUL : AMul2I <0b0111010, 0b0001, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm),
3578 IIC_iMUL32, "smmul", "\t$Rd, $Rn, $Rm",
3579 [(set GPR:$Rd, (mulhs GPR:$Rn, GPR:$Rm))]>,
3580 Requires<[IsARM, HasV6]> {
3581 let Inst{15-12} = 0b1111;
3584 def SMMULR : AMul2I <0b0111010, 0b0011, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm),
3585 IIC_iMUL32, "smmulr", "\t$Rd, $Rn, $Rm", []>,
3586 Requires<[IsARM, HasV6]> {
3587 let Inst{15-12} = 0b1111;
3590 def SMMLA : AMul2Ia <0b0111010, 0b0001, (outs GPR:$Rd),
3591 (ins GPR:$Rn, GPR:$Rm, GPR:$Ra),
3592 IIC_iMAC32, "smmla", "\t$Rd, $Rn, $Rm, $Ra",
3593 [(set GPR:$Rd, (add (mulhs GPR:$Rn, GPR:$Rm), GPR:$Ra))]>,
3594 Requires<[IsARM, HasV6, UseMulOps]>;
3596 def SMMLAR : AMul2Ia <0b0111010, 0b0011, (outs GPR:$Rd),
3597 (ins GPR:$Rn, GPR:$Rm, GPR:$Ra),
3598 IIC_iMAC32, "smmlar", "\t$Rd, $Rn, $Rm, $Ra", []>,
3599 Requires<[IsARM, HasV6]>;
3601 def SMMLS : AMul2Ia <0b0111010, 0b1101, (outs GPR:$Rd),
3602 (ins GPR:$Rn, GPR:$Rm, GPR:$Ra),
3603 IIC_iMAC32, "smmls", "\t$Rd, $Rn, $Rm, $Ra", []>,
3604 Requires<[IsARM, HasV6, UseMulOps]>;
3606 def SMMLSR : AMul2Ia <0b0111010, 0b1111, (outs GPR:$Rd),
3607 (ins GPR:$Rn, GPR:$Rm, GPR:$Ra),
3608 IIC_iMAC32, "smmlsr", "\t$Rd, $Rn, $Rm, $Ra", []>,
3609 Requires<[IsARM, HasV6]>;
3611 multiclass AI_smul<string opc, PatFrag opnode> {
3612 def BB : AMulxyI<0b0001011, 0b00, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm),
3613 IIC_iMUL16, !strconcat(opc, "bb"), "\t$Rd, $Rn, $Rm",
3614 [(set GPR:$Rd, (opnode (sext_inreg GPR:$Rn, i16),
3615 (sext_inreg GPR:$Rm, i16)))]>,
3616 Requires<[IsARM, HasV5TE]>;
3618 def BT : AMulxyI<0b0001011, 0b10, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm),
3619 IIC_iMUL16, !strconcat(opc, "bt"), "\t$Rd, $Rn, $Rm",
3620 [(set GPR:$Rd, (opnode (sext_inreg GPR:$Rn, i16),
3621 (sra GPR:$Rm, (i32 16))))]>,
3622 Requires<[IsARM, HasV5TE]>;
3624 def TB : AMulxyI<0b0001011, 0b01, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm),
3625 IIC_iMUL16, !strconcat(opc, "tb"), "\t$Rd, $Rn, $Rm",
3626 [(set GPR:$Rd, (opnode (sra GPR:$Rn, (i32 16)),
3627 (sext_inreg GPR:$Rm, i16)))]>,
3628 Requires<[IsARM, HasV5TE]>;
3630 def TT : AMulxyI<0b0001011, 0b11, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm),
3631 IIC_iMUL16, !strconcat(opc, "tt"), "\t$Rd, $Rn, $Rm",
3632 [(set GPR:$Rd, (opnode (sra GPR:$Rn, (i32 16)),
3633 (sra GPR:$Rm, (i32 16))))]>,
3634 Requires<[IsARM, HasV5TE]>;
3636 def WB : AMulxyI<0b0001001, 0b01, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm),
3637 IIC_iMUL16, !strconcat(opc, "wb"), "\t$Rd, $Rn, $Rm",
3638 [(set GPR:$Rd, (sra (opnode GPR:$Rn,
3639 (sext_inreg GPR:$Rm, i16)), (i32 16)))]>,
3640 Requires<[IsARM, HasV5TE]>;
3642 def WT : AMulxyI<0b0001001, 0b11, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm),
3643 IIC_iMUL16, !strconcat(opc, "wt"), "\t$Rd, $Rn, $Rm",
3644 [(set GPR:$Rd, (sra (opnode GPR:$Rn,
3645 (sra GPR:$Rm, (i32 16))), (i32 16)))]>,
3646 Requires<[IsARM, HasV5TE]>;
3650 multiclass AI_smla<string opc, PatFrag opnode> {
3651 let DecoderMethod = "DecodeSMLAInstruction" in {
3652 def BB : AMulxyIa<0b0001000, 0b00, (outs GPRnopc:$Rd),
3653 (ins GPRnopc:$Rn, GPRnopc:$Rm, GPR:$Ra),
3654 IIC_iMAC16, !strconcat(opc, "bb"), "\t$Rd, $Rn, $Rm, $Ra",
3655 [(set GPRnopc:$Rd, (add GPR:$Ra,
3656 (opnode (sext_inreg GPRnopc:$Rn, i16),
3657 (sext_inreg GPRnopc:$Rm, i16))))]>,
3658 Requires<[IsARM, HasV5TE, UseMulOps]>;
3660 def BT : AMulxyIa<0b0001000, 0b10, (outs GPRnopc:$Rd),
3661 (ins GPRnopc:$Rn, GPRnopc:$Rm, GPR:$Ra),
3662 IIC_iMAC16, !strconcat(opc, "bt"), "\t$Rd, $Rn, $Rm, $Ra",
3664 (add GPR:$Ra, (opnode (sext_inreg GPRnopc:$Rn, i16),
3665 (sra GPRnopc:$Rm, (i32 16)))))]>,
3666 Requires<[IsARM, HasV5TE, UseMulOps]>;
3668 def TB : AMulxyIa<0b0001000, 0b01, (outs GPRnopc:$Rd),
3669 (ins GPRnopc:$Rn, GPRnopc:$Rm, GPR:$Ra),
3670 IIC_iMAC16, !strconcat(opc, "tb"), "\t$Rd, $Rn, $Rm, $Ra",
3672 (add GPR:$Ra, (opnode (sra GPRnopc:$Rn, (i32 16)),
3673 (sext_inreg GPRnopc:$Rm, i16))))]>,
3674 Requires<[IsARM, HasV5TE, UseMulOps]>;
3676 def TT : AMulxyIa<0b0001000, 0b11, (outs GPRnopc:$Rd),
3677 (ins GPRnopc:$Rn, GPRnopc:$Rm, GPR:$Ra),
3678 IIC_iMAC16, !strconcat(opc, "tt"), "\t$Rd, $Rn, $Rm, $Ra",
3680 (add GPR:$Ra, (opnode (sra GPRnopc:$Rn, (i32 16)),
3681 (sra GPRnopc:$Rm, (i32 16)))))]>,
3682 Requires<[IsARM, HasV5TE, UseMulOps]>;
3684 def WB : AMulxyIa<0b0001001, 0b00, (outs GPRnopc:$Rd),
3685 (ins GPRnopc:$Rn, GPRnopc:$Rm, GPR:$Ra),
3686 IIC_iMAC16, !strconcat(opc, "wb"), "\t$Rd, $Rn, $Rm, $Ra",
3688 (add GPR:$Ra, (sra (opnode GPRnopc:$Rn,
3689 (sext_inreg GPRnopc:$Rm, i16)), (i32 16))))]>,
3690 Requires<[IsARM, HasV5TE, UseMulOps]>;
3692 def WT : AMulxyIa<0b0001001, 0b10, (outs GPRnopc:$Rd),
3693 (ins GPRnopc:$Rn, GPRnopc:$Rm, GPR:$Ra),
3694 IIC_iMAC16, !strconcat(opc, "wt"), "\t$Rd, $Rn, $Rm, $Ra",
3696 (add GPR:$Ra, (sra (opnode GPRnopc:$Rn,
3697 (sra GPRnopc:$Rm, (i32 16))), (i32 16))))]>,
3698 Requires<[IsARM, HasV5TE, UseMulOps]>;
3702 defm SMUL : AI_smul<"smul", BinOpFrag<(mul node:$LHS, node:$RHS)>>;
3703 defm SMLA : AI_smla<"smla", BinOpFrag<(mul node:$LHS, node:$RHS)>>;
3705 // Halfword multiply accumulate long: SMLAL<x><y>.
3706 def SMLALBB : AMulxyI64<0b0001010, 0b00, (outs GPRnopc:$RdLo, GPRnopc:$RdHi),
3707 (ins GPRnopc:$Rn, GPRnopc:$Rm),
3708 IIC_iMAC64, "smlalbb", "\t$RdLo, $RdHi, $Rn, $Rm", []>,
3709 Requires<[IsARM, HasV5TE]>;
3711 def SMLALBT : AMulxyI64<0b0001010, 0b10, (outs GPRnopc:$RdLo, GPRnopc:$RdHi),
3712 (ins GPRnopc:$Rn, GPRnopc:$Rm),
3713 IIC_iMAC64, "smlalbt", "\t$RdLo, $RdHi, $Rn, $Rm", []>,
3714 Requires<[IsARM, HasV5TE]>;
3716 def SMLALTB : AMulxyI64<0b0001010, 0b01, (outs GPRnopc:$RdLo, GPRnopc:$RdHi),
3717 (ins GPRnopc:$Rn, GPRnopc:$Rm),
3718 IIC_iMAC64, "smlaltb", "\t$RdLo, $RdHi, $Rn, $Rm", []>,
3719 Requires<[IsARM, HasV5TE]>;
3721 def SMLALTT : AMulxyI64<0b0001010, 0b11, (outs GPRnopc:$RdLo, GPRnopc:$RdHi),
3722 (ins GPRnopc:$Rn, GPRnopc:$Rm),
3723 IIC_iMAC64, "smlaltt", "\t$RdLo, $RdHi, $Rn, $Rm", []>,
3724 Requires<[IsARM, HasV5TE]>;
3726 // Helper class for AI_smld.
3727 class AMulDualIbase<bit long, bit sub, bit swap, dag oops, dag iops,
3728 InstrItinClass itin, string opc, string asm>
3729 : AI<oops, iops, MulFrm, itin, opc, asm, []>, Requires<[IsARM, HasV6]> {
3732 let Inst{27-23} = 0b01110;
3733 let Inst{22} = long;
3734 let Inst{21-20} = 0b00;
3735 let Inst{11-8} = Rm;
3742 class AMulDualI<bit long, bit sub, bit swap, dag oops, dag iops,
3743 InstrItinClass itin, string opc, string asm>
3744 : AMulDualIbase<long, sub, swap, oops, iops, itin, opc, asm> {
3746 let Inst{15-12} = 0b1111;
3747 let Inst{19-16} = Rd;
3749 class AMulDualIa<bit long, bit sub, bit swap, dag oops, dag iops,
3750 InstrItinClass itin, string opc, string asm>
3751 : AMulDualIbase<long, sub, swap, oops, iops, itin, opc, asm> {
3754 let Inst{19-16} = Rd;
3755 let Inst{15-12} = Ra;
3757 class AMulDualI64<bit long, bit sub, bit swap, dag oops, dag iops,
3758 InstrItinClass itin, string opc, string asm>
3759 : AMulDualIbase<long, sub, swap, oops, iops, itin, opc, asm> {
3762 let Inst{19-16} = RdHi;
3763 let Inst{15-12} = RdLo;
3766 multiclass AI_smld<bit sub, string opc> {
3768 def D : AMulDualIa<0, sub, 0, (outs GPRnopc:$Rd),
3769 (ins GPRnopc:$Rn, GPRnopc:$Rm, GPR:$Ra),
3770 NoItinerary, !strconcat(opc, "d"), "\t$Rd, $Rn, $Rm, $Ra">;
3772 def DX: AMulDualIa<0, sub, 1, (outs GPRnopc:$Rd),
3773 (ins GPRnopc:$Rn, GPRnopc:$Rm, GPR:$Ra),
3774 NoItinerary, !strconcat(opc, "dx"), "\t$Rd, $Rn, $Rm, $Ra">;
3776 def LD: AMulDualI64<1, sub, 0, (outs GPRnopc:$RdLo, GPRnopc:$RdHi),
3777 (ins GPRnopc:$Rn, GPRnopc:$Rm), NoItinerary,
3778 !strconcat(opc, "ld"), "\t$RdLo, $RdHi, $Rn, $Rm">;
3780 def LDX : AMulDualI64<1, sub, 1, (outs GPRnopc:$RdLo, GPRnopc:$RdHi),
3781 (ins GPRnopc:$Rn, GPRnopc:$Rm), NoItinerary,
3782 !strconcat(opc, "ldx"),"\t$RdLo, $RdHi, $Rn, $Rm">;
3786 defm SMLA : AI_smld<0, "smla">;
3787 defm SMLS : AI_smld<1, "smls">;
3789 multiclass AI_sdml<bit sub, string opc> {
3791 def D:AMulDualI<0, sub, 0, (outs GPRnopc:$Rd), (ins GPRnopc:$Rn, GPRnopc:$Rm),
3792 NoItinerary, !strconcat(opc, "d"), "\t$Rd, $Rn, $Rm">;
3793 def DX:AMulDualI<0, sub, 1, (outs GPRnopc:$Rd),(ins GPRnopc:$Rn, GPRnopc:$Rm),
3794 NoItinerary, !strconcat(opc, "dx"), "\t$Rd, $Rn, $Rm">;
3797 defm SMUA : AI_sdml<0, "smua">;
3798 defm SMUS : AI_sdml<1, "smus">;
3800 //===----------------------------------------------------------------------===//
3801 // Division Instructions (ARMv7-A with virtualization extension)
3803 def SDIV : ADivA1I<0b001, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm), IIC_iDIV,
3804 "sdiv", "\t$Rd, $Rn, $Rm",
3805 [(set GPR:$Rd, (sdiv GPR:$Rn, GPR:$Rm))]>,
3806 Requires<[IsARM, HasDivideInARM]>;
3808 def UDIV : ADivA1I<0b011, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm), IIC_iDIV,
3809 "udiv", "\t$Rd, $Rn, $Rm",
3810 [(set GPR:$Rd, (udiv GPR:$Rn, GPR:$Rm))]>,
3811 Requires<[IsARM, HasDivideInARM]>;
3813 //===----------------------------------------------------------------------===//
3814 // Misc. Arithmetic Instructions.
3817 def CLZ : AMiscA1I<0b000010110, 0b0001, (outs GPR:$Rd), (ins GPR:$Rm),
3818 IIC_iUNAr, "clz", "\t$Rd, $Rm",
3819 [(set GPR:$Rd, (ctlz GPR:$Rm))]>, Requires<[IsARM, HasV5T]>;
3821 def RBIT : AMiscA1I<0b01101111, 0b0011, (outs GPR:$Rd), (ins GPR:$Rm),
3822 IIC_iUNAr, "rbit", "\t$Rd, $Rm",
3823 [(set GPR:$Rd, (ARMrbit GPR:$Rm))]>,
3824 Requires<[IsARM, HasV6T2]>;
3826 def REV : AMiscA1I<0b01101011, 0b0011, (outs GPR:$Rd), (ins GPR:$Rm),
3827 IIC_iUNAr, "rev", "\t$Rd, $Rm",
3828 [(set GPR:$Rd, (bswap GPR:$Rm))]>, Requires<[IsARM, HasV6]>;
3830 let AddedComplexity = 5 in
3831 def REV16 : AMiscA1I<0b01101011, 0b1011, (outs GPR:$Rd), (ins GPR:$Rm),
3832 IIC_iUNAr, "rev16", "\t$Rd, $Rm",
3833 [(set GPR:$Rd, (rotr (bswap GPR:$Rm), (i32 16)))]>,
3834 Requires<[IsARM, HasV6]>;
3836 let AddedComplexity = 5 in
3837 def REVSH : AMiscA1I<0b01101111, 0b1011, (outs GPR:$Rd), (ins GPR:$Rm),
3838 IIC_iUNAr, "revsh", "\t$Rd, $Rm",
3839 [(set GPR:$Rd, (sra (bswap GPR:$Rm), (i32 16)))]>,
3840 Requires<[IsARM, HasV6]>;
3842 def : ARMV6Pat<(or (sra (shl GPR:$Rm, (i32 24)), (i32 16)),
3843 (and (srl GPR:$Rm, (i32 8)), 0xFF)),
3846 def PKHBT : APKHI<0b01101000, 0, (outs GPRnopc:$Rd),
3847 (ins GPRnopc:$Rn, GPRnopc:$Rm, pkh_lsl_amt:$sh),
3848 IIC_iALUsi, "pkhbt", "\t$Rd, $Rn, $Rm$sh",
3849 [(set GPRnopc:$Rd, (or (and GPRnopc:$Rn, 0xFFFF),
3850 (and (shl GPRnopc:$Rm, pkh_lsl_amt:$sh),
3852 Requires<[IsARM, HasV6]>;
3854 // Alternate cases for PKHBT where identities eliminate some nodes.
3855 def : ARMV6Pat<(or (and GPRnopc:$Rn, 0xFFFF), (and GPRnopc:$Rm, 0xFFFF0000)),
3856 (PKHBT GPRnopc:$Rn, GPRnopc:$Rm, 0)>;
3857 def : ARMV6Pat<(or (and GPRnopc:$Rn, 0xFFFF), (shl GPRnopc:$Rm, imm16_31:$sh)),
3858 (PKHBT GPRnopc:$Rn, GPRnopc:$Rm, imm16_31:$sh)>;
3860 // Note: Shifts of 1-15 bits will be transformed to srl instead of sra and
3861 // will match the pattern below.
3862 def PKHTB : APKHI<0b01101000, 1, (outs GPRnopc:$Rd),
3863 (ins GPRnopc:$Rn, GPRnopc:$Rm, pkh_asr_amt:$sh),
3864 IIC_iBITsi, "pkhtb", "\t$Rd, $Rn, $Rm$sh",
3865 [(set GPRnopc:$Rd, (or (and GPRnopc:$Rn, 0xFFFF0000),
3866 (and (sra GPRnopc:$Rm, pkh_asr_amt:$sh),
3868 Requires<[IsARM, HasV6]>;
3870 // Alternate cases for PKHTB where identities eliminate some nodes. Note that
3871 // a shift amount of 0 is *not legal* here, it is PKHBT instead.
3872 def : ARMV6Pat<(or (and GPRnopc:$src1, 0xFFFF0000),
3873 (srl GPRnopc:$src2, imm16_31:$sh)),
3874 (PKHTB GPRnopc:$src1, GPRnopc:$src2, imm16_31:$sh)>;
3875 def : ARMV6Pat<(or (and GPRnopc:$src1, 0xFFFF0000),
3876 (and (srl GPRnopc:$src2, imm1_15:$sh), 0xFFFF)),
3877 (PKHTB GPRnopc:$src1, GPRnopc:$src2, imm1_15:$sh)>;
3879 //===----------------------------------------------------------------------===//
3880 // Comparison Instructions...
3883 defm CMP : AI1_cmp_irs<0b1010, "cmp",
3884 IIC_iCMPi, IIC_iCMPr, IIC_iCMPsr,
3885 BinOpFrag<(ARMcmp node:$LHS, node:$RHS)>>;
3887 // ARMcmpZ can re-use the above instruction definitions.
3888 def : ARMPat<(ARMcmpZ GPR:$src, so_imm:$imm),
3889 (CMPri GPR:$src, so_imm:$imm)>;
3890 def : ARMPat<(ARMcmpZ GPR:$src, GPR:$rhs),
3891 (CMPrr GPR:$src, GPR:$rhs)>;
3892 def : ARMPat<(ARMcmpZ GPR:$src, so_reg_imm:$rhs),
3893 (CMPrsi GPR:$src, so_reg_imm:$rhs)>;
3894 def : ARMPat<(ARMcmpZ GPR:$src, so_reg_reg:$rhs),
3895 (CMPrsr GPR:$src, so_reg_reg:$rhs)>;
3897 // CMN register-integer
3898 let isCompare = 1, Defs = [CPSR] in {
3899 def CMNri : AI1<0b1011, (outs), (ins GPR:$Rn, so_imm:$imm), DPFrm, IIC_iCMPi,
3900 "cmn", "\t$Rn, $imm",
3901 [(ARMcmn GPR:$Rn, so_imm:$imm)]> {
3906 let Inst{19-16} = Rn;
3907 let Inst{15-12} = 0b0000;
3908 let Inst{11-0} = imm;
3910 let Unpredictable{15-12} = 0b1111;
3913 // CMN register-register/shift
3914 def CMNzrr : AI1<0b1011, (outs), (ins GPR:$Rn, GPR:$Rm), DPFrm, IIC_iCMPr,
3915 "cmn", "\t$Rn, $Rm",
3916 [(BinOpFrag<(ARMcmpZ node:$LHS,(ineg node:$RHS))>
3917 GPR:$Rn, GPR:$Rm)]> {
3920 let isCommutable = 1;
3923 let Inst{19-16} = Rn;
3924 let Inst{15-12} = 0b0000;
3925 let Inst{11-4} = 0b00000000;
3928 let Unpredictable{15-12} = 0b1111;
3931 def CMNzrsi : AI1<0b1011, (outs),
3932 (ins GPR:$Rn, so_reg_imm:$shift), DPSoRegImmFrm, IIC_iCMPsr,
3933 "cmn", "\t$Rn, $shift",
3934 [(BinOpFrag<(ARMcmpZ node:$LHS,(ineg node:$RHS))>
3935 GPR:$Rn, so_reg_imm:$shift)]> {
3940 let Inst{19-16} = Rn;
3941 let Inst{15-12} = 0b0000;
3942 let Inst{11-5} = shift{11-5};
3944 let Inst{3-0} = shift{3-0};
3946 let Unpredictable{15-12} = 0b1111;
3949 def CMNzrsr : AI1<0b1011, (outs),
3950 (ins GPRnopc:$Rn, so_reg_reg:$shift), DPSoRegRegFrm, IIC_iCMPsr,
3951 "cmn", "\t$Rn, $shift",
3952 [(BinOpFrag<(ARMcmpZ node:$LHS,(ineg node:$RHS))>
3953 GPRnopc:$Rn, so_reg_reg:$shift)]> {
3958 let Inst{19-16} = Rn;
3959 let Inst{15-12} = 0b0000;
3960 let Inst{11-8} = shift{11-8};
3962 let Inst{6-5} = shift{6-5};
3964 let Inst{3-0} = shift{3-0};
3966 let Unpredictable{15-12} = 0b1111;
3971 def : ARMPat<(ARMcmp GPR:$src, so_imm_neg:$imm),
3972 (CMNri GPR:$src, so_imm_neg:$imm)>;
3974 def : ARMPat<(ARMcmpZ GPR:$src, so_imm_neg:$imm),
3975 (CMNri GPR:$src, so_imm_neg:$imm)>;
3977 // Note that TST/TEQ don't set all the same flags that CMP does!
3978 defm TST : AI1_cmp_irs<0b1000, "tst",
3979 IIC_iTSTi, IIC_iTSTr, IIC_iTSTsr,
3980 BinOpFrag<(ARMcmpZ (and_su node:$LHS, node:$RHS), 0)>, 1>;
3981 defm TEQ : AI1_cmp_irs<0b1001, "teq",
3982 IIC_iTSTi, IIC_iTSTr, IIC_iTSTsr,
3983 BinOpFrag<(ARMcmpZ (xor_su node:$LHS, node:$RHS), 0)>, 1>;
3985 // Pseudo i64 compares for some floating point compares.
3986 let usesCustomInserter = 1, isBranch = 1, isTerminator = 1,
3988 def BCCi64 : PseudoInst<(outs),
3989 (ins i32imm:$cc, GPR:$lhs1, GPR:$lhs2, GPR:$rhs1, GPR:$rhs2, brtarget:$dst),
3991 [(ARMBcci64 imm:$cc, GPR:$lhs1, GPR:$lhs2, GPR:$rhs1, GPR:$rhs2, bb:$dst)]>;
3993 def BCCZi64 : PseudoInst<(outs),
3994 (ins i32imm:$cc, GPR:$lhs1, GPR:$lhs2, brtarget:$dst), IIC_Br,
3995 [(ARMBcci64 imm:$cc, GPR:$lhs1, GPR:$lhs2, 0, 0, bb:$dst)]>;
3996 } // usesCustomInserter
3999 // Conditional moves
4000 // FIXME: should be able to write a pattern for ARMcmov, but can't use
4001 // a two-value operand where a dag node expects two operands. :(
4002 let neverHasSideEffects = 1 in {
4004 let isCommutable = 1, isSelect = 1 in
4005 def MOVCCr : ARMPseudoInst<(outs GPR:$Rd), (ins GPR:$false, GPR:$Rm, pred:$p),
4007 [/*(set GPR:$Rd, (ARMcmov GPR:$false, GPR:$Rm, imm:$cc, CCR:$ccr))*/]>,
4008 RegConstraint<"$false = $Rd">;
4010 def MOVCCsi : ARMPseudoInst<(outs GPR:$Rd),
4011 (ins GPR:$false, so_reg_imm:$shift, pred:$p),
4013 [/*(set GPR:$Rd, (ARMcmov GPR:$false, so_reg_imm:$shift,
4014 imm:$cc, CCR:$ccr))*/]>,
4015 RegConstraint<"$false = $Rd">;
4016 def MOVCCsr : ARMPseudoInst<(outs GPR:$Rd),
4017 (ins GPR:$false, so_reg_reg:$shift, pred:$p),
4019 [/*(set GPR:$Rd, (ARMcmov GPR:$false, so_reg_reg:$shift,
4020 imm:$cc, CCR:$ccr))*/]>,
4021 RegConstraint<"$false = $Rd">;
4024 let isMoveImm = 1 in
4025 def MOVCCi16 : ARMPseudoInst<(outs GPR:$Rd),
4026 (ins GPR:$false, imm0_65535_expr:$imm, pred:$p),
4029 RegConstraint<"$false = $Rd">, Requires<[IsARM, HasV6T2]>;
4031 let isMoveImm = 1 in
4032 def MOVCCi : ARMPseudoInst<(outs GPR:$Rd),
4033 (ins GPR:$false, so_imm:$imm, pred:$p),
4035 [/*(set GPR:$Rd, (ARMcmov GPR:$false, so_imm:$imm, imm:$cc, CCR:$ccr))*/]>,
4036 RegConstraint<"$false = $Rd">;
4038 // Two instruction predicate mov immediate.
4039 let isMoveImm = 1 in
4040 def MOVCCi32imm : ARMPseudoInst<(outs GPR:$Rd),
4041 (ins GPR:$false, i32imm:$src, pred:$p),
4042 8, IIC_iCMOVix2, []>, RegConstraint<"$false = $Rd">;
4044 let isMoveImm = 1 in
4045 def MVNCCi : ARMPseudoInst<(outs GPR:$Rd),
4046 (ins GPR:$false, so_imm:$imm, pred:$p),
4048 [/*(set GPR:$Rd, (ARMcmov GPR:$false, so_imm_not:$imm, imm:$cc, CCR:$ccr))*/]>,
4049 RegConstraint<"$false = $Rd">;
4051 } // neverHasSideEffects
4054 //===----------------------------------------------------------------------===//
4055 // Atomic operations intrinsics
4058 def MemBarrierOptOperand : AsmOperandClass {
4059 let Name = "MemBarrierOpt";
4060 let ParserMethod = "parseMemBarrierOptOperand";
4062 def memb_opt : Operand<i32> {
4063 let PrintMethod = "printMemBOption";
4064 let ParserMatchClass = MemBarrierOptOperand;
4065 let DecoderMethod = "DecodeMemBarrierOption";
4068 // memory barriers protect the atomic sequences
4069 let hasSideEffects = 1 in {
4070 def DMB : AInoP<(outs), (ins memb_opt:$opt), MiscFrm, NoItinerary,
4071 "dmb", "\t$opt", [(ARMMemBarrier (i32 imm:$opt))]>,
4072 Requires<[IsARM, HasDB]> {
4074 let Inst{31-4} = 0xf57ff05;
4075 let Inst{3-0} = opt;
4079 def DSB : AInoP<(outs), (ins memb_opt:$opt), MiscFrm, NoItinerary,
4080 "dsb", "\t$opt", []>,
4081 Requires<[IsARM, HasDB]> {
4083 let Inst{31-4} = 0xf57ff04;
4084 let Inst{3-0} = opt;
4087 // ISB has only full system option
4088 def ISB : AInoP<(outs), (ins memb_opt:$opt), MiscFrm, NoItinerary,
4089 "isb", "\t$opt", []>,
4090 Requires<[IsARM, HasDB]> {
4092 let Inst{31-4} = 0xf57ff06;
4093 let Inst{3-0} = opt;
4096 // Pseudo instruction that combines movs + predicated rsbmi
4097 // to implement integer ABS
4098 let usesCustomInserter = 1, Defs = [CPSR] in
4099 def ABS : ARMPseudoInst<(outs GPR:$dst), (ins GPR:$src), 8, NoItinerary, []>;
4101 let usesCustomInserter = 1 in {
4102 let Defs = [CPSR] in {
4103 def ATOMIC_LOAD_ADD_I8 : PseudoInst<
4104 (outs GPR:$dst), (ins GPR:$ptr, GPR:$incr), NoItinerary,
4105 [(set GPR:$dst, (atomic_load_add_8 GPR:$ptr, GPR:$incr))]>;
4106 def ATOMIC_LOAD_SUB_I8 : PseudoInst<
4107 (outs GPR:$dst), (ins GPR:$ptr, GPR:$incr), NoItinerary,
4108 [(set GPR:$dst, (atomic_load_sub_8 GPR:$ptr, GPR:$incr))]>;
4109 def ATOMIC_LOAD_AND_I8 : PseudoInst<
4110 (outs GPR:$dst), (ins GPR:$ptr, GPR:$incr), NoItinerary,
4111 [(set GPR:$dst, (atomic_load_and_8 GPR:$ptr, GPR:$incr))]>;
4112 def ATOMIC_LOAD_OR_I8 : PseudoInst<
4113 (outs GPR:$dst), (ins GPR:$ptr, GPR:$incr), NoItinerary,
4114 [(set GPR:$dst, (atomic_load_or_8 GPR:$ptr, GPR:$incr))]>;
4115 def ATOMIC_LOAD_XOR_I8 : PseudoInst<
4116 (outs GPR:$dst), (ins GPR:$ptr, GPR:$incr), NoItinerary,
4117 [(set GPR:$dst, (atomic_load_xor_8 GPR:$ptr, GPR:$incr))]>;
4118 def ATOMIC_LOAD_NAND_I8 : PseudoInst<
4119 (outs GPR:$dst), (ins GPR:$ptr, GPR:$incr), NoItinerary,
4120 [(set GPR:$dst, (atomic_load_nand_8 GPR:$ptr, GPR:$incr))]>;
4121 def ATOMIC_LOAD_MIN_I8 : PseudoInst<
4122 (outs GPR:$dst), (ins GPR:$ptr, GPR:$val), NoItinerary,
4123 [(set GPR:$dst, (atomic_load_min_8 GPR:$ptr, GPR:$val))]>;
4124 def ATOMIC_LOAD_MAX_I8 : PseudoInst<
4125 (outs GPR:$dst), (ins GPR:$ptr, GPR:$val), NoItinerary,
4126 [(set GPR:$dst, (atomic_load_max_8 GPR:$ptr, GPR:$val))]>;
4127 def ATOMIC_LOAD_UMIN_I8 : PseudoInst<
4128 (outs GPR:$dst), (ins GPR:$ptr, GPR:$val), NoItinerary,
4129 [(set GPR:$dst, (atomic_load_umin_8 GPR:$ptr, GPR:$val))]>;
4130 def ATOMIC_LOAD_UMAX_I8 : PseudoInst<
4131 (outs GPR:$dst), (ins GPR:$ptr, GPR:$val), NoItinerary,
4132 [(set GPR:$dst, (atomic_load_umax_8 GPR:$ptr, GPR:$val))]>;
4133 def ATOMIC_LOAD_ADD_I16 : PseudoInst<
4134 (outs GPR:$dst), (ins GPR:$ptr, GPR:$incr), NoItinerary,
4135 [(set GPR:$dst, (atomic_load_add_16 GPR:$ptr, GPR:$incr))]>;
4136 def ATOMIC_LOAD_SUB_I16 : PseudoInst<
4137 (outs GPR:$dst), (ins GPR:$ptr, GPR:$incr), NoItinerary,
4138 [(set GPR:$dst, (atomic_load_sub_16 GPR:$ptr, GPR:$incr))]>;
4139 def ATOMIC_LOAD_AND_I16 : PseudoInst<
4140 (outs GPR:$dst), (ins GPR:$ptr, GPR:$incr), NoItinerary,
4141 [(set GPR:$dst, (atomic_load_and_16 GPR:$ptr, GPR:$incr))]>;
4142 def ATOMIC_LOAD_OR_I16 : PseudoInst<
4143 (outs GPR:$dst), (ins GPR:$ptr, GPR:$incr), NoItinerary,
4144 [(set GPR:$dst, (atomic_load_or_16 GPR:$ptr, GPR:$incr))]>;
4145 def ATOMIC_LOAD_XOR_I16 : PseudoInst<
4146 (outs GPR:$dst), (ins GPR:$ptr, GPR:$incr), NoItinerary,
4147 [(set GPR:$dst, (atomic_load_xor_16 GPR:$ptr, GPR:$incr))]>;
4148 def ATOMIC_LOAD_NAND_I16 : PseudoInst<
4149 (outs GPR:$dst), (ins GPR:$ptr, GPR:$incr), NoItinerary,
4150 [(set GPR:$dst, (atomic_load_nand_16 GPR:$ptr, GPR:$incr))]>;
4151 def ATOMIC_LOAD_MIN_I16 : PseudoInst<
4152 (outs GPR:$dst), (ins GPR:$ptr, GPR:$val), NoItinerary,
4153 [(set GPR:$dst, (atomic_load_min_16 GPR:$ptr, GPR:$val))]>;
4154 def ATOMIC_LOAD_MAX_I16 : PseudoInst<
4155 (outs GPR:$dst), (ins GPR:$ptr, GPR:$val), NoItinerary,
4156 [(set GPR:$dst, (atomic_load_max_16 GPR:$ptr, GPR:$val))]>;
4157 def ATOMIC_LOAD_UMIN_I16 : PseudoInst<
4158 (outs GPR:$dst), (ins GPR:$ptr, GPR:$val), NoItinerary,
4159 [(set GPR:$dst, (atomic_load_umin_16 GPR:$ptr, GPR:$val))]>;
4160 def ATOMIC_LOAD_UMAX_I16 : PseudoInst<
4161 (outs GPR:$dst), (ins GPR:$ptr, GPR:$val), NoItinerary,
4162 [(set GPR:$dst, (atomic_load_umax_16 GPR:$ptr, GPR:$val))]>;
4163 def ATOMIC_LOAD_ADD_I32 : PseudoInst<
4164 (outs GPR:$dst), (ins GPR:$ptr, GPR:$incr), NoItinerary,
4165 [(set GPR:$dst, (atomic_load_add_32 GPR:$ptr, GPR:$incr))]>;
4166 def ATOMIC_LOAD_SUB_I32 : PseudoInst<
4167 (outs GPR:$dst), (ins GPR:$ptr, GPR:$incr), NoItinerary,
4168 [(set GPR:$dst, (atomic_load_sub_32 GPR:$ptr, GPR:$incr))]>;
4169 def ATOMIC_LOAD_AND_I32 : PseudoInst<
4170 (outs GPR:$dst), (ins GPR:$ptr, GPR:$incr), NoItinerary,
4171 [(set GPR:$dst, (atomic_load_and_32 GPR:$ptr, GPR:$incr))]>;
4172 def ATOMIC_LOAD_OR_I32 : PseudoInst<
4173 (outs GPR:$dst), (ins GPR:$ptr, GPR:$incr), NoItinerary,
4174 [(set GPR:$dst, (atomic_load_or_32 GPR:$ptr, GPR:$incr))]>;
4175 def ATOMIC_LOAD_XOR_I32 : PseudoInst<
4176 (outs GPR:$dst), (ins GPR:$ptr, GPR:$incr), NoItinerary,
4177 [(set GPR:$dst, (atomic_load_xor_32 GPR:$ptr, GPR:$incr))]>;
4178 def ATOMIC_LOAD_NAND_I32 : PseudoInst<
4179 (outs GPR:$dst), (ins GPR:$ptr, GPR:$incr), NoItinerary,
4180 [(set GPR:$dst, (atomic_load_nand_32 GPR:$ptr, GPR:$incr))]>;
4181 def ATOMIC_LOAD_MIN_I32 : PseudoInst<
4182 (outs GPR:$dst), (ins GPR:$ptr, GPR:$val), NoItinerary,
4183 [(set GPR:$dst, (atomic_load_min_32 GPR:$ptr, GPR:$val))]>;
4184 def ATOMIC_LOAD_MAX_I32 : PseudoInst<
4185 (outs GPR:$dst), (ins GPR:$ptr, GPR:$val), NoItinerary,
4186 [(set GPR:$dst, (atomic_load_max_32 GPR:$ptr, GPR:$val))]>;
4187 def ATOMIC_LOAD_UMIN_I32 : PseudoInst<
4188 (outs GPR:$dst), (ins GPR:$ptr, GPR:$val), NoItinerary,
4189 [(set GPR:$dst, (atomic_load_umin_32 GPR:$ptr, GPR:$val))]>;
4190 def ATOMIC_LOAD_UMAX_I32 : PseudoInst<
4191 (outs GPR:$dst), (ins GPR:$ptr, GPR:$val), NoItinerary,
4192 [(set GPR:$dst, (atomic_load_umax_32 GPR:$ptr, GPR:$val))]>;
4194 def ATOMIC_SWAP_I8 : PseudoInst<
4195 (outs GPR:$dst), (ins GPR:$ptr, GPR:$new), NoItinerary,
4196 [(set GPR:$dst, (atomic_swap_8 GPR:$ptr, GPR:$new))]>;
4197 def ATOMIC_SWAP_I16 : PseudoInst<
4198 (outs GPR:$dst), (ins GPR:$ptr, GPR:$new), NoItinerary,
4199 [(set GPR:$dst, (atomic_swap_16 GPR:$ptr, GPR:$new))]>;
4200 def ATOMIC_SWAP_I32 : PseudoInst<
4201 (outs GPR:$dst), (ins GPR:$ptr, GPR:$new), NoItinerary,
4202 [(set GPR:$dst, (atomic_swap_32 GPR:$ptr, GPR:$new))]>;
4204 def ATOMIC_CMP_SWAP_I8 : PseudoInst<
4205 (outs GPR:$dst), (ins GPR:$ptr, GPR:$old, GPR:$new), NoItinerary,
4206 [(set GPR:$dst, (atomic_cmp_swap_8 GPR:$ptr, GPR:$old, GPR:$new))]>;
4207 def ATOMIC_CMP_SWAP_I16 : PseudoInst<
4208 (outs GPR:$dst), (ins GPR:$ptr, GPR:$old, GPR:$new), NoItinerary,
4209 [(set GPR:$dst, (atomic_cmp_swap_16 GPR:$ptr, GPR:$old, GPR:$new))]>;
4210 def ATOMIC_CMP_SWAP_I32 : PseudoInst<
4211 (outs GPR:$dst), (ins GPR:$ptr, GPR:$old, GPR:$new), NoItinerary,
4212 [(set GPR:$dst, (atomic_cmp_swap_32 GPR:$ptr, GPR:$old, GPR:$new))]>;
4216 let usesCustomInserter = 1 in {
4217 def COPY_STRUCT_BYVAL_I32 : PseudoInst<
4218 (outs), (ins GPR:$dst, GPR:$src, i32imm:$size, i32imm:$alignment),
4220 [(ARMcopystructbyval GPR:$dst, GPR:$src, imm:$size, imm:$alignment)]>;
4223 let mayLoad = 1 in {
4224 def LDREXB : AIldrex<0b10, (outs GPR:$Rt), (ins addr_offset_none:$addr),
4226 "ldrexb", "\t$Rt, $addr", []>;
4227 def LDREXH : AIldrex<0b11, (outs GPR:$Rt), (ins addr_offset_none:$addr),
4228 NoItinerary, "ldrexh", "\t$Rt, $addr", []>;
4229 def LDREX : AIldrex<0b00, (outs GPR:$Rt), (ins addr_offset_none:$addr),
4230 NoItinerary, "ldrex", "\t$Rt, $addr", []>;
4231 let hasExtraDefRegAllocReq = 1 in
4232 def LDREXD: AIldrex<0b01, (outs GPR:$Rt, GPR:$Rt2),(ins addr_offset_none:$addr),
4233 NoItinerary, "ldrexd", "\t$Rt, $Rt2, $addr", []> {
4234 let DecoderMethod = "DecodeDoubleRegLoad";
4238 let mayStore = 1, Constraints = "@earlyclobber $Rd" in {
4239 def STREXB: AIstrex<0b10, (outs GPR:$Rd), (ins GPR:$Rt, addr_offset_none:$addr),
4240 NoItinerary, "strexb", "\t$Rd, $Rt, $addr", []>;
4241 def STREXH: AIstrex<0b11, (outs GPR:$Rd), (ins GPR:$Rt, addr_offset_none:$addr),
4242 NoItinerary, "strexh", "\t$Rd, $Rt, $addr", []>;
4243 def STREX : AIstrex<0b00, (outs GPR:$Rd), (ins GPR:$Rt, addr_offset_none:$addr),
4244 NoItinerary, "strex", "\t$Rd, $Rt, $addr", []>;
4245 let hasExtraSrcRegAllocReq = 1 in
4246 def STREXD : AIstrex<0b01, (outs GPR:$Rd),
4247 (ins GPR:$Rt, GPR:$Rt2, addr_offset_none:$addr),
4248 NoItinerary, "strexd", "\t$Rd, $Rt, $Rt2, $addr", []> {
4249 let DecoderMethod = "DecodeDoubleRegStore";
4254 def CLREX : AXI<(outs), (ins), MiscFrm, NoItinerary, "clrex", []>,
4255 Requires<[IsARM, HasV7]> {
4256 let Inst{31-0} = 0b11110101011111111111000000011111;
4259 // SWP/SWPB are deprecated in V6/V7.
4260 let mayLoad = 1, mayStore = 1 in {
4261 def SWP : AIswp<0, (outs GPRnopc:$Rt),
4262 (ins GPRnopc:$Rt2, addr_offset_none:$addr), "swp", []>;
4263 def SWPB: AIswp<1, (outs GPRnopc:$Rt),
4264 (ins GPRnopc:$Rt2, addr_offset_none:$addr), "swpb", []>;
4267 //===----------------------------------------------------------------------===//
4268 // Coprocessor Instructions.
4271 def CDP : ABI<0b1110, (outs), (ins p_imm:$cop, imm0_15:$opc1,
4272 c_imm:$CRd, c_imm:$CRn, c_imm:$CRm, imm0_7:$opc2),
4273 NoItinerary, "cdp", "\t$cop, $opc1, $CRd, $CRn, $CRm, $opc2",
4274 [(int_arm_cdp imm:$cop, imm:$opc1, imm:$CRd, imm:$CRn,
4275 imm:$CRm, imm:$opc2)]> {
4283 let Inst{3-0} = CRm;
4285 let Inst{7-5} = opc2;
4286 let Inst{11-8} = cop;
4287 let Inst{15-12} = CRd;
4288 let Inst{19-16} = CRn;
4289 let Inst{23-20} = opc1;
4292 def CDP2 : ABXI<0b1110, (outs), (ins pf_imm:$cop, imm0_15:$opc1,
4293 c_imm:$CRd, c_imm:$CRn, c_imm:$CRm, imm0_7:$opc2),
4294 NoItinerary, "cdp2\t$cop, $opc1, $CRd, $CRn, $CRm, $opc2",
4295 [(int_arm_cdp2 imm:$cop, imm:$opc1, imm:$CRd, imm:$CRn,
4296 imm:$CRm, imm:$opc2)]> {
4297 let Inst{31-28} = 0b1111;
4305 let Inst{3-0} = CRm;
4307 let Inst{7-5} = opc2;
4308 let Inst{11-8} = cop;
4309 let Inst{15-12} = CRd;
4310 let Inst{19-16} = CRn;
4311 let Inst{23-20} = opc1;
4314 class ACI<dag oops, dag iops, string opc, string asm,
4315 IndexMode im = IndexModeNone>
4316 : I<oops, iops, AddrModeNone, 4, im, BrFrm, NoItinerary,
4318 let Inst{27-25} = 0b110;
4320 class ACInoP<dag oops, dag iops, string opc, string asm,
4321 IndexMode im = IndexModeNone>
4322 : InoP<oops, iops, AddrModeNone, 4, im, BrFrm, NoItinerary,
4324 let Inst{31-28} = 0b1111;
4325 let Inst{27-25} = 0b110;
4327 multiclass LdStCop<bit load, bit Dbit, string asm> {
4328 def _OFFSET : ACI<(outs), (ins p_imm:$cop, c_imm:$CRd, addrmode5:$addr),
4329 asm, "\t$cop, $CRd, $addr"> {
4333 let Inst{24} = 1; // P = 1
4334 let Inst{23} = addr{8};
4335 let Inst{22} = Dbit;
4336 let Inst{21} = 0; // W = 0
4337 let Inst{20} = load;
4338 let Inst{19-16} = addr{12-9};
4339 let Inst{15-12} = CRd;
4340 let Inst{11-8} = cop;
4341 let Inst{7-0} = addr{7-0};
4342 let DecoderMethod = "DecodeCopMemInstruction";
4344 def _PRE : ACI<(outs), (ins p_imm:$cop, c_imm:$CRd, addrmode5:$addr),
4345 asm, "\t$cop, $CRd, $addr!", IndexModePre> {
4349 let Inst{24} = 1; // P = 1
4350 let Inst{23} = addr{8};
4351 let Inst{22} = Dbit;
4352 let Inst{21} = 1; // W = 1
4353 let Inst{20} = load;
4354 let Inst{19-16} = addr{12-9};
4355 let Inst{15-12} = CRd;
4356 let Inst{11-8} = cop;
4357 let Inst{7-0} = addr{7-0};
4358 let DecoderMethod = "DecodeCopMemInstruction";
4360 def _POST: ACI<(outs), (ins p_imm:$cop, c_imm:$CRd, addr_offset_none:$addr,
4361 postidx_imm8s4:$offset),
4362 asm, "\t$cop, $CRd, $addr, $offset", IndexModePost> {
4367 let Inst{24} = 0; // P = 0
4368 let Inst{23} = offset{8};
4369 let Inst{22} = Dbit;
4370 let Inst{21} = 1; // W = 1
4371 let Inst{20} = load;
4372 let Inst{19-16} = addr;
4373 let Inst{15-12} = CRd;
4374 let Inst{11-8} = cop;
4375 let Inst{7-0} = offset{7-0};
4376 let DecoderMethod = "DecodeCopMemInstruction";
4378 def _OPTION : ACI<(outs),
4379 (ins p_imm:$cop, c_imm:$CRd, addr_offset_none:$addr,
4380 coproc_option_imm:$option),
4381 asm, "\t$cop, $CRd, $addr, $option"> {
4386 let Inst{24} = 0; // P = 0
4387 let Inst{23} = 1; // U = 1
4388 let Inst{22} = Dbit;
4389 let Inst{21} = 0; // W = 0
4390 let Inst{20} = load;
4391 let Inst{19-16} = addr;
4392 let Inst{15-12} = CRd;
4393 let Inst{11-8} = cop;
4394 let Inst{7-0} = option;
4395 let DecoderMethod = "DecodeCopMemInstruction";
4398 multiclass LdSt2Cop<bit load, bit Dbit, string asm> {
4399 def _OFFSET : ACInoP<(outs), (ins p_imm:$cop, c_imm:$CRd, addrmode5:$addr),
4400 asm, "\t$cop, $CRd, $addr"> {
4404 let Inst{24} = 1; // P = 1
4405 let Inst{23} = addr{8};
4406 let Inst{22} = Dbit;
4407 let Inst{21} = 0; // W = 0
4408 let Inst{20} = load;
4409 let Inst{19-16} = addr{12-9};
4410 let Inst{15-12} = CRd;
4411 let Inst{11-8} = cop;
4412 let Inst{7-0} = addr{7-0};
4413 let DecoderMethod = "DecodeCopMemInstruction";
4415 def _PRE : ACInoP<(outs), (ins p_imm:$cop, c_imm:$CRd, addrmode5:$addr),
4416 asm, "\t$cop, $CRd, $addr!", IndexModePre> {
4420 let Inst{24} = 1; // P = 1
4421 let Inst{23} = addr{8};
4422 let Inst{22} = Dbit;
4423 let Inst{21} = 1; // W = 1
4424 let Inst{20} = load;
4425 let Inst{19-16} = addr{12-9};
4426 let Inst{15-12} = CRd;
4427 let Inst{11-8} = cop;
4428 let Inst{7-0} = addr{7-0};
4429 let DecoderMethod = "DecodeCopMemInstruction";
4431 def _POST: ACInoP<(outs), (ins p_imm:$cop, c_imm:$CRd, addr_offset_none:$addr,
4432 postidx_imm8s4:$offset),
4433 asm, "\t$cop, $CRd, $addr, $offset", IndexModePost> {
4438 let Inst{24} = 0; // P = 0
4439 let Inst{23} = offset{8};
4440 let Inst{22} = Dbit;
4441 let Inst{21} = 1; // W = 1
4442 let Inst{20} = load;
4443 let Inst{19-16} = addr;
4444 let Inst{15-12} = CRd;
4445 let Inst{11-8} = cop;
4446 let Inst{7-0} = offset{7-0};
4447 let DecoderMethod = "DecodeCopMemInstruction";
4449 def _OPTION : ACInoP<(outs),
4450 (ins p_imm:$cop, c_imm:$CRd, addr_offset_none:$addr,
4451 coproc_option_imm:$option),
4452 asm, "\t$cop, $CRd, $addr, $option"> {
4457 let Inst{24} = 0; // P = 0
4458 let Inst{23} = 1; // U = 1
4459 let Inst{22} = Dbit;
4460 let Inst{21} = 0; // W = 0
4461 let Inst{20} = load;
4462 let Inst{19-16} = addr;
4463 let Inst{15-12} = CRd;
4464 let Inst{11-8} = cop;
4465 let Inst{7-0} = option;
4466 let DecoderMethod = "DecodeCopMemInstruction";
4470 defm LDC : LdStCop <1, 0, "ldc">;
4471 defm LDCL : LdStCop <1, 1, "ldcl">;
4472 defm STC : LdStCop <0, 0, "stc">;
4473 defm STCL : LdStCop <0, 1, "stcl">;
4474 defm LDC2 : LdSt2Cop<1, 0, "ldc2">;
4475 defm LDC2L : LdSt2Cop<1, 1, "ldc2l">;
4476 defm STC2 : LdSt2Cop<0, 0, "stc2">;
4477 defm STC2L : LdSt2Cop<0, 1, "stc2l">;
4479 //===----------------------------------------------------------------------===//
4480 // Move between coprocessor and ARM core register.
4483 class MovRCopro<string opc, bit direction, dag oops, dag iops,
4485 : ABI<0b1110, oops, iops, NoItinerary, opc,
4486 "\t$cop, $opc1, $Rt, $CRn, $CRm, $opc2", pattern> {
4487 let Inst{20} = direction;
4497 let Inst{15-12} = Rt;
4498 let Inst{11-8} = cop;
4499 let Inst{23-21} = opc1;
4500 let Inst{7-5} = opc2;
4501 let Inst{3-0} = CRm;
4502 let Inst{19-16} = CRn;
4505 def MCR : MovRCopro<"mcr", 0 /* from ARM core register to coprocessor */,
4507 (ins p_imm:$cop, imm0_7:$opc1, GPR:$Rt, c_imm:$CRn,
4508 c_imm:$CRm, imm0_7:$opc2),
4509 [(int_arm_mcr imm:$cop, imm:$opc1, GPR:$Rt, imm:$CRn,
4510 imm:$CRm, imm:$opc2)]>;
4511 def : ARMInstAlias<"mcr${p} $cop, $opc1, $Rt, $CRn, $CRm",
4512 (MCR p_imm:$cop, imm0_7:$opc1, GPR:$Rt, c_imm:$CRn,
4513 c_imm:$CRm, 0, pred:$p)>;
4514 def MRC : MovRCopro<"mrc", 1 /* from coprocessor to ARM core register */,
4516 (ins p_imm:$cop, imm0_7:$opc1, c_imm:$CRn, c_imm:$CRm,
4518 def : ARMInstAlias<"mrc${p} $cop, $opc1, $Rt, $CRn, $CRm",
4519 (MRC GPR:$Rt, p_imm:$cop, imm0_7:$opc1, c_imm:$CRn,
4520 c_imm:$CRm, 0, pred:$p)>;
4522 def : ARMPat<(int_arm_mrc imm:$cop, imm:$opc1, imm:$CRn, imm:$CRm, imm:$opc2),
4523 (MRC imm:$cop, imm:$opc1, imm:$CRn, imm:$CRm, imm:$opc2)>;
4525 class MovRCopro2<string opc, bit direction, dag oops, dag iops,
4527 : ABXI<0b1110, oops, iops, NoItinerary,
4528 !strconcat(opc, "\t$cop, $opc1, $Rt, $CRn, $CRm, $opc2"), pattern> {
4529 let Inst{31-28} = 0b1111;
4530 let Inst{20} = direction;
4540 let Inst{15-12} = Rt;
4541 let Inst{11-8} = cop;
4542 let Inst{23-21} = opc1;
4543 let Inst{7-5} = opc2;
4544 let Inst{3-0} = CRm;
4545 let Inst{19-16} = CRn;
4548 def MCR2 : MovRCopro2<"mcr2", 0 /* from ARM core register to coprocessor */,
4550 (ins p_imm:$cop, imm0_7:$opc1, GPR:$Rt, c_imm:$CRn,
4551 c_imm:$CRm, imm0_7:$opc2),
4552 [(int_arm_mcr2 imm:$cop, imm:$opc1, GPR:$Rt, imm:$CRn,
4553 imm:$CRm, imm:$opc2)]>;
4554 def : ARMInstAlias<"mcr2$ $cop, $opc1, $Rt, $CRn, $CRm",
4555 (MCR2 p_imm:$cop, imm0_7:$opc1, GPR:$Rt, c_imm:$CRn,
4557 def MRC2 : MovRCopro2<"mrc2", 1 /* from coprocessor to ARM core register */,
4559 (ins p_imm:$cop, imm0_7:$opc1, c_imm:$CRn, c_imm:$CRm,
4561 def : ARMInstAlias<"mrc2$ $cop, $opc1, $Rt, $CRn, $CRm",
4562 (MRC2 GPR:$Rt, p_imm:$cop, imm0_7:$opc1, c_imm:$CRn,
4565 def : ARMV5TPat<(int_arm_mrc2 imm:$cop, imm:$opc1, imm:$CRn,
4566 imm:$CRm, imm:$opc2),
4567 (MRC2 imm:$cop, imm:$opc1, imm:$CRn, imm:$CRm, imm:$opc2)>;
4569 class MovRRCopro<string opc, bit direction, list<dag> pattern = []>
4570 : ABI<0b1100, (outs), (ins p_imm:$cop, imm0_15:$opc1,
4571 GPRnopc:$Rt, GPRnopc:$Rt2, c_imm:$CRm),
4572 NoItinerary, opc, "\t$cop, $opc1, $Rt, $Rt2, $CRm", pattern> {
4573 let Inst{23-21} = 0b010;
4574 let Inst{20} = direction;
4582 let Inst{15-12} = Rt;
4583 let Inst{19-16} = Rt2;
4584 let Inst{11-8} = cop;
4585 let Inst{7-4} = opc1;
4586 let Inst{3-0} = CRm;
4589 def MCRR : MovRRCopro<"mcrr", 0 /* from ARM core register to coprocessor */,
4590 [(int_arm_mcrr imm:$cop, imm:$opc1, GPRnopc:$Rt,
4591 GPRnopc:$Rt2, imm:$CRm)]>;
4592 def MRRC : MovRRCopro<"mrrc", 1 /* from coprocessor to ARM core register */>;
4594 class MovRRCopro2<string opc, bit direction, list<dag> pattern = []>
4595 : ABXI<0b1100, (outs), (ins p_imm:$cop, imm0_15:$opc1,
4596 GPRnopc:$Rt, GPRnopc:$Rt2, c_imm:$CRm), NoItinerary,
4597 !strconcat(opc, "\t$cop, $opc1, $Rt, $Rt2, $CRm"), pattern> {
4598 let Inst{31-28} = 0b1111;
4599 let Inst{23-21} = 0b010;
4600 let Inst{20} = direction;
4608 let Inst{15-12} = Rt;
4609 let Inst{19-16} = Rt2;
4610 let Inst{11-8} = cop;
4611 let Inst{7-4} = opc1;
4612 let Inst{3-0} = CRm;
4614 let DecoderMethod = "DecodeMRRC2";
4617 def MCRR2 : MovRRCopro2<"mcrr2", 0 /* from ARM core register to coprocessor */,
4618 [(int_arm_mcrr2 imm:$cop, imm:$opc1, GPRnopc:$Rt,
4619 GPRnopc:$Rt2, imm:$CRm)]>;
4620 def MRRC2 : MovRRCopro2<"mrrc2", 1 /* from coprocessor to ARM core register */>;
4622 //===----------------------------------------------------------------------===//
4623 // Move between special register and ARM core register
4626 // Move to ARM core register from Special Register
4627 def MRS : ABI<0b0001, (outs GPRnopc:$Rd), (ins), NoItinerary,
4628 "mrs", "\t$Rd, apsr", []> {
4630 let Inst{23-16} = 0b00001111;
4631 let Unpredictable{19-17} = 0b111;
4633 let Inst{15-12} = Rd;
4635 let Inst{11-0} = 0b000000000000;
4636 let Unpredictable{11-0} = 0b110100001111;
4639 def : InstAlias<"mrs${p} $Rd, cpsr", (MRS GPRnopc:$Rd, pred:$p)>,
4642 // The MRSsys instruction is the MRS instruction from the ARM ARM,
4643 // section B9.3.9, with the R bit set to 1.
4644 def MRSsys : ABI<0b0001, (outs GPRnopc:$Rd), (ins), NoItinerary,
4645 "mrs", "\t$Rd, spsr", []> {
4647 let Inst{23-16} = 0b01001111;
4648 let Unpredictable{19-16} = 0b1111;
4650 let Inst{15-12} = Rd;
4652 let Inst{11-0} = 0b000000000000;
4653 let Unpredictable{11-0} = 0b110100001111;
4656 // Move from ARM core register to Special Register
4658 // No need to have both system and application versions, the encodings are the
4659 // same and the assembly parser has no way to distinguish between them. The mask
4660 // operand contains the special register (R Bit) in bit 4 and bits 3-0 contains
4661 // the mask with the fields to be accessed in the special register.
4662 def MSR : ABI<0b0001, (outs), (ins msr_mask:$mask, GPR:$Rn), NoItinerary,
4663 "msr", "\t$mask, $Rn", []> {
4668 let Inst{22} = mask{4}; // R bit
4669 let Inst{21-20} = 0b10;
4670 let Inst{19-16} = mask{3-0};
4671 let Inst{15-12} = 0b1111;
4672 let Inst{11-4} = 0b00000000;
4676 def MSRi : ABI<0b0011, (outs), (ins msr_mask:$mask, so_imm:$a), NoItinerary,
4677 "msr", "\t$mask, $a", []> {
4682 let Inst{22} = mask{4}; // R bit
4683 let Inst{21-20} = 0b10;
4684 let Inst{19-16} = mask{3-0};
4685 let Inst{15-12} = 0b1111;
4689 //===----------------------------------------------------------------------===//
4693 // __aeabi_read_tp preserves the registers r1-r3.
4694 // This is a pseudo inst so that we can get the encoding right,
4695 // complete with fixup for the aeabi_read_tp function.
4697 Defs = [R0, R12, LR, CPSR], Uses = [SP] in {
4698 def TPsoft : PseudoInst<(outs), (ins), IIC_Br,
4699 [(set R0, ARMthread_pointer)]>;
4702 //===----------------------------------------------------------------------===//
4703 // SJLJ Exception handling intrinsics
4704 // eh_sjlj_setjmp() is an instruction sequence to store the return
4705 // address and save #0 in R0 for the non-longjmp case.
4706 // Since by its nature we may be coming from some other function to get
4707 // here, and we're using the stack frame for the containing function to
4708 // save/restore registers, we can't keep anything live in regs across
4709 // the eh_sjlj_setjmp(), else it will almost certainly have been tromped upon
4710 // when we get here from a longjmp(). We force everything out of registers
4711 // except for our own input by listing the relevant registers in Defs. By
4712 // doing so, we also cause the prologue/epilogue code to actively preserve
4713 // all of the callee-saved resgisters, which is exactly what we want.
4714 // A constant value is passed in $val, and we use the location as a scratch.
4716 // These are pseudo-instructions and are lowered to individual MC-insts, so
4717 // no encoding information is necessary.
4719 [ R0, R1, R2, R3, R4, R5, R6, R7, R8, R9, R10, R11, R12, LR, CPSR,
4720 Q0, Q1, Q2, Q3, Q4, Q5, Q6, Q7, Q8, Q9, Q10, Q11, Q12, Q13, Q14, Q15 ],
4721 hasSideEffects = 1, isBarrier = 1, usesCustomInserter = 1 in {
4722 def Int_eh_sjlj_setjmp : PseudoInst<(outs), (ins GPR:$src, GPR:$val),
4724 [(set R0, (ARMeh_sjlj_setjmp GPR:$src, GPR:$val))]>,
4725 Requires<[IsARM, HasVFP2]>;
4729 [ R0, R1, R2, R3, R4, R5, R6, R7, R8, R9, R10, R11, R12, LR, CPSR ],
4730 hasSideEffects = 1, isBarrier = 1, usesCustomInserter = 1 in {
4731 def Int_eh_sjlj_setjmp_nofp : PseudoInst<(outs), (ins GPR:$src, GPR:$val),
4733 [(set R0, (ARMeh_sjlj_setjmp GPR:$src, GPR:$val))]>,
4734 Requires<[IsARM, NoVFP]>;
4737 // FIXME: Non-IOS version(s)
4738 let isBarrier = 1, hasSideEffects = 1, isTerminator = 1,
4739 Defs = [ R7, LR, SP ] in {
4740 def Int_eh_sjlj_longjmp : PseudoInst<(outs), (ins GPR:$src, GPR:$scratch),
4742 [(ARMeh_sjlj_longjmp GPR:$src, GPR:$scratch)]>,
4743 Requires<[IsARM, IsIOS]>;
4746 // eh.sjlj.dispatchsetup pseudo-instructions.
4747 // These pseudos are used for both ARM and Thumb2. Any differences are
4748 // handled when the pseudo is expanded (which happens before any passes
4749 // that need the instruction size).
4751 [ R0, R1, R2, R3, R4, R5, R6, R7, R8, R9, R10, R11, R12, LR, CPSR,
4752 Q0, Q1, Q2, Q3, Q4, Q5, Q6, Q7, Q8, Q9, Q10, Q11, Q12, Q13, Q14, Q15 ],
4754 def Int_eh_sjlj_dispatchsetup : PseudoInst<(outs), (ins), NoItinerary, []>;
4757 [ R0, R1, R2, R3, R4, R5, R6, R7, R8, R9, R10, R11, R12, LR, CPSR ],
4759 def Int_eh_sjlj_dispatchsetup_nofp : PseudoInst<(outs), (ins), NoItinerary, []>;
4762 //===----------------------------------------------------------------------===//
4763 // Non-Instruction Patterns
4766 // ARMv4 indirect branch using (MOVr PC, dst)
4767 let isBranch = 1, isTerminator = 1, isBarrier = 1, isIndirectBranch = 1 in
4768 def MOVPCRX : ARMPseudoExpand<(outs), (ins GPR:$dst),
4769 4, IIC_Br, [(brind GPR:$dst)],
4770 (MOVr PC, GPR:$dst, (ops 14, zero_reg), zero_reg)>,
4771 Requires<[IsARM, NoV4T]>;
4773 // Large immediate handling.
4775 // 32-bit immediate using two piece so_imms or movw + movt.
4776 // This is a single pseudo instruction, the benefit is that it can be remat'd
4777 // as a single unit instead of having to handle reg inputs.
4778 // FIXME: Remove this when we can do generalized remat.
4779 let isReMaterializable = 1, isMoveImm = 1 in
4780 def MOVi32imm : PseudoInst<(outs GPR:$dst), (ins i32imm:$src), IIC_iMOVix2,
4781 [(set GPR:$dst, (arm_i32imm:$src))]>,
4784 // Pseudo instruction that combines movw + movt + add pc (if PIC).
4785 // It also makes it possible to rematerialize the instructions.
4786 // FIXME: Remove this when we can do generalized remat and when machine licm
4787 // can properly the instructions.
4788 let isReMaterializable = 1 in {
4789 def MOV_ga_pcrel : PseudoInst<(outs GPR:$dst), (ins i32imm:$addr),
4791 [(set GPR:$dst, (ARMWrapperPIC tglobaladdr:$addr))]>,
4792 Requires<[IsARM, UseMovt]>;
4794 def MOV_ga_dyn : PseudoInst<(outs GPR:$dst), (ins i32imm:$addr),
4796 [(set GPR:$dst, (ARMWrapperDYN tglobaladdr:$addr))]>,
4797 Requires<[IsARM, UseMovt]>;
4799 let AddedComplexity = 10 in
4800 def MOV_ga_pcrel_ldr : PseudoInst<(outs GPR:$dst), (ins i32imm:$addr),
4802 [(set GPR:$dst, (load (ARMWrapperPIC tglobaladdr:$addr)))]>,
4803 Requires<[IsARM, UseMovt]>;
4804 } // isReMaterializable
4806 // ConstantPool, GlobalAddress, and JumpTable
4807 def : ARMPat<(ARMWrapper tglobaladdr :$dst), (LEApcrel tglobaladdr :$dst)>,
4808 Requires<[IsARM, DontUseMovt]>;
4809 def : ARMPat<(ARMWrapper tconstpool :$dst), (LEApcrel tconstpool :$dst)>;
4810 def : ARMPat<(ARMWrapper tglobaladdr :$dst), (MOVi32imm tglobaladdr :$dst)>,
4811 Requires<[IsARM, UseMovt]>;
4812 def : ARMPat<(ARMWrapperJT tjumptable:$dst, imm:$id),
4813 (LEApcrelJT tjumptable:$dst, imm:$id)>;
4815 // TODO: add,sub,and, 3-instr forms?
4817 // Tail calls. These patterns also apply to Thumb mode.
4818 def : Pat<(ARMtcret tcGPR:$dst), (TCRETURNri tcGPR:$dst)>;
4819 def : Pat<(ARMtcret (i32 tglobaladdr:$dst)), (TCRETURNdi texternalsym:$dst)>;
4820 def : Pat<(ARMtcret (i32 texternalsym:$dst)), (TCRETURNdi texternalsym:$dst)>;
4823 def : ARMPat<(ARMcall texternalsym:$func), (BL texternalsym:$func)>;
4824 def : ARMPat<(ARMcall_nolink texternalsym:$func),
4825 (BMOVPCB_CALL texternalsym:$func)>;
4827 // zextload i1 -> zextload i8
4828 def : ARMPat<(zextloadi1 addrmode_imm12:$addr), (LDRBi12 addrmode_imm12:$addr)>;
4829 def : ARMPat<(zextloadi1 ldst_so_reg:$addr), (LDRBrs ldst_so_reg:$addr)>;
4831 // extload -> zextload
4832 def : ARMPat<(extloadi1 addrmode_imm12:$addr), (LDRBi12 addrmode_imm12:$addr)>;
4833 def : ARMPat<(extloadi1 ldst_so_reg:$addr), (LDRBrs ldst_so_reg:$addr)>;
4834 def : ARMPat<(extloadi8 addrmode_imm12:$addr), (LDRBi12 addrmode_imm12:$addr)>;
4835 def : ARMPat<(extloadi8 ldst_so_reg:$addr), (LDRBrs ldst_so_reg:$addr)>;
4837 def : ARMPat<(extloadi16 addrmode3:$addr), (LDRH addrmode3:$addr)>;
4839 def : ARMPat<(extloadi8 addrmodepc:$addr), (PICLDRB addrmodepc:$addr)>;
4840 def : ARMPat<(extloadi16 addrmodepc:$addr), (PICLDRH addrmodepc:$addr)>;
4843 def : ARMV5TEPat<(mul (sra (shl GPR:$a, (i32 16)), (i32 16)),
4844 (sra (shl GPR:$b, (i32 16)), (i32 16))),
4845 (SMULBB GPR:$a, GPR:$b)>;
4846 def : ARMV5TEPat<(mul sext_16_node:$a, sext_16_node:$b),
4847 (SMULBB GPR:$a, GPR:$b)>;
4848 def : ARMV5TEPat<(mul (sra (shl GPR:$a, (i32 16)), (i32 16)),
4849 (sra GPR:$b, (i32 16))),
4850 (SMULBT GPR:$a, GPR:$b)>;
4851 def : ARMV5TEPat<(mul sext_16_node:$a, (sra GPR:$b, (i32 16))),
4852 (SMULBT GPR:$a, GPR:$b)>;
4853 def : ARMV5TEPat<(mul (sra GPR:$a, (i32 16)),
4854 (sra (shl GPR:$b, (i32 16)), (i32 16))),
4855 (SMULTB GPR:$a, GPR:$b)>;
4856 def : ARMV5TEPat<(mul (sra GPR:$a, (i32 16)), sext_16_node:$b),
4857 (SMULTB GPR:$a, GPR:$b)>;
4858 def : ARMV5TEPat<(sra (mul GPR:$a, (sra (shl GPR:$b, (i32 16)), (i32 16))),
4860 (SMULWB GPR:$a, GPR:$b)>;
4861 def : ARMV5TEPat<(sra (mul GPR:$a, sext_16_node:$b), (i32 16)),
4862 (SMULWB GPR:$a, GPR:$b)>;
4864 def : ARMV5MOPat<(add GPR:$acc,
4865 (mul (sra (shl GPR:$a, (i32 16)), (i32 16)),
4866 (sra (shl GPR:$b, (i32 16)), (i32 16)))),
4867 (SMLABB GPR:$a, GPR:$b, GPR:$acc)>;
4868 def : ARMV5MOPat<(add GPR:$acc,
4869 (mul sext_16_node:$a, sext_16_node:$b)),
4870 (SMLABB GPR:$a, GPR:$b, GPR:$acc)>;
4871 def : ARMV5MOPat<(add GPR:$acc,
4872 (mul (sra (shl GPR:$a, (i32 16)), (i32 16)),
4873 (sra GPR:$b, (i32 16)))),
4874 (SMLABT GPR:$a, GPR:$b, GPR:$acc)>;
4875 def : ARMV5MOPat<(add GPR:$acc,
4876 (mul sext_16_node:$a, (sra GPR:$b, (i32 16)))),
4877 (SMLABT GPR:$a, GPR:$b, GPR:$acc)>;
4878 def : ARMV5MOPat<(add GPR:$acc,
4879 (mul (sra GPR:$a, (i32 16)),
4880 (sra (shl GPR:$b, (i32 16)), (i32 16)))),
4881 (SMLATB GPR:$a, GPR:$b, GPR:$acc)>;
4882 def : ARMV5MOPat<(add GPR:$acc,
4883 (mul (sra GPR:$a, (i32 16)), sext_16_node:$b)),
4884 (SMLATB GPR:$a, GPR:$b, GPR:$acc)>;
4885 def : ARMV5MOPat<(add GPR:$acc,
4886 (sra (mul GPR:$a, (sra (shl GPR:$b, (i32 16)), (i32 16))),
4888 (SMLAWB GPR:$a, GPR:$b, GPR:$acc)>;
4889 def : ARMV5MOPat<(add GPR:$acc,
4890 (sra (mul GPR:$a, sext_16_node:$b), (i32 16))),
4891 (SMLAWB GPR:$a, GPR:$b, GPR:$acc)>;
4894 // Pre-v7 uses MCR for synchronization barriers.
4895 def : ARMPat<(ARMMemBarrierMCR GPR:$zero), (MCR 15, 0, GPR:$zero, 7, 10, 5)>,
4896 Requires<[IsARM, HasV6]>;
4898 // SXT/UXT with no rotate
4899 let AddedComplexity = 16 in {
4900 def : ARMV6Pat<(and GPR:$Src, 0x000000FF), (UXTB GPR:$Src, 0)>;
4901 def : ARMV6Pat<(and GPR:$Src, 0x0000FFFF), (UXTH GPR:$Src, 0)>;
4902 def : ARMV6Pat<(and GPR:$Src, 0x00FF00FF), (UXTB16 GPR:$Src, 0)>;
4903 def : ARMV6Pat<(add GPR:$Rn, (and GPR:$Rm, 0x00FF)),
4904 (UXTAB GPR:$Rn, GPR:$Rm, 0)>;
4905 def : ARMV6Pat<(add GPR:$Rn, (and GPR:$Rm, 0xFFFF)),
4906 (UXTAH GPR:$Rn, GPR:$Rm, 0)>;
4909 def : ARMV6Pat<(sext_inreg GPR:$Src, i8), (SXTB GPR:$Src, 0)>;
4910 def : ARMV6Pat<(sext_inreg GPR:$Src, i16), (SXTH GPR:$Src, 0)>;
4912 def : ARMV6Pat<(add GPR:$Rn, (sext_inreg GPRnopc:$Rm, i8)),
4913 (SXTAB GPR:$Rn, GPRnopc:$Rm, 0)>;
4914 def : ARMV6Pat<(add GPR:$Rn, (sext_inreg GPRnopc:$Rm, i16)),
4915 (SXTAH GPR:$Rn, GPRnopc:$Rm, 0)>;
4917 // Atomic load/store patterns
4918 def : ARMPat<(atomic_load_8 ldst_so_reg:$src),
4919 (LDRBrs ldst_so_reg:$src)>;
4920 def : ARMPat<(atomic_load_8 addrmode_imm12:$src),
4921 (LDRBi12 addrmode_imm12:$src)>;
4922 def : ARMPat<(atomic_load_16 addrmode3:$src),
4923 (LDRH addrmode3:$src)>;
4924 def : ARMPat<(atomic_load_32 ldst_so_reg:$src),
4925 (LDRrs ldst_so_reg:$src)>;
4926 def : ARMPat<(atomic_load_32 addrmode_imm12:$src),
4927 (LDRi12 addrmode_imm12:$src)>;
4928 def : ARMPat<(atomic_store_8 ldst_so_reg:$ptr, GPR:$val),
4929 (STRBrs GPR:$val, ldst_so_reg:$ptr)>;
4930 def : ARMPat<(atomic_store_8 addrmode_imm12:$ptr, GPR:$val),
4931 (STRBi12 GPR:$val, addrmode_imm12:$ptr)>;
4932 def : ARMPat<(atomic_store_16 addrmode3:$ptr, GPR:$val),
4933 (STRH GPR:$val, addrmode3:$ptr)>;
4934 def : ARMPat<(atomic_store_32 ldst_so_reg:$ptr, GPR:$val),
4935 (STRrs GPR:$val, ldst_so_reg:$ptr)>;
4936 def : ARMPat<(atomic_store_32 addrmode_imm12:$ptr, GPR:$val),
4937 (STRi12 GPR:$val, addrmode_imm12:$ptr)>;
4940 //===----------------------------------------------------------------------===//
4944 include "ARMInstrThumb.td"
4946 //===----------------------------------------------------------------------===//
4950 include "ARMInstrThumb2.td"
4952 //===----------------------------------------------------------------------===//
4953 // Floating Point Support
4956 include "ARMInstrVFP.td"
4958 //===----------------------------------------------------------------------===//
4959 // Advanced SIMD (NEON) Support
4962 include "ARMInstrNEON.td"
4964 //===----------------------------------------------------------------------===//
4965 // Assembler aliases
4969 def : InstAlias<"dmb", (DMB 0xf)>, Requires<[IsARM, HasDB]>;
4970 def : InstAlias<"dsb", (DSB 0xf)>, Requires<[IsARM, HasDB]>;
4971 def : InstAlias<"isb", (ISB 0xf)>, Requires<[IsARM, HasDB]>;
4973 // System instructions
4974 def : MnemonicAlias<"swi", "svc">;
4976 // Load / Store Multiple
4977 def : MnemonicAlias<"ldmfd", "ldm">;
4978 def : MnemonicAlias<"ldmia", "ldm">;
4979 def : MnemonicAlias<"ldmea", "ldmdb">;
4980 def : MnemonicAlias<"stmfd", "stmdb">;
4981 def : MnemonicAlias<"stmia", "stm">;
4982 def : MnemonicAlias<"stmea", "stm">;
4984 // PKHBT/PKHTB with default shift amount. PKHTB is equivalent to PKHBT when the
4985 // shift amount is zero (i.e., unspecified).
4986 def : InstAlias<"pkhbt${p} $Rd, $Rn, $Rm",
4987 (PKHBT GPRnopc:$Rd, GPRnopc:$Rn, GPRnopc:$Rm, 0, pred:$p)>,
4988 Requires<[IsARM, HasV6]>;
4989 def : InstAlias<"pkhtb${p} $Rd, $Rn, $Rm",
4990 (PKHBT GPRnopc:$Rd, GPRnopc:$Rn, GPRnopc:$Rm, 0, pred:$p)>,
4991 Requires<[IsARM, HasV6]>;
4993 // PUSH/POP aliases for STM/LDM
4994 def : ARMInstAlias<"push${p} $regs", (STMDB_UPD SP, pred:$p, reglist:$regs)>;
4995 def : ARMInstAlias<"pop${p} $regs", (LDMIA_UPD SP, pred:$p, reglist:$regs)>;
4997 // SSAT/USAT optional shift operand.
4998 def : ARMInstAlias<"ssat${p} $Rd, $sat_imm, $Rn",
4999 (SSAT GPRnopc:$Rd, imm1_32:$sat_imm, GPRnopc:$Rn, 0, pred:$p)>;
5000 def : ARMInstAlias<"usat${p} $Rd, $sat_imm, $Rn",
5001 (USAT GPRnopc:$Rd, imm0_31:$sat_imm, GPRnopc:$Rn, 0, pred:$p)>;
5004 // Extend instruction optional rotate operand.
5005 def : ARMInstAlias<"sxtab${p} $Rd, $Rn, $Rm",
5006 (SXTAB GPRnopc:$Rd, GPR:$Rn, GPRnopc:$Rm, 0, pred:$p)>;
5007 def : ARMInstAlias<"sxtah${p} $Rd, $Rn, $Rm",
5008 (SXTAH GPRnopc:$Rd, GPR:$Rn, GPRnopc:$Rm, 0, pred:$p)>;
5009 def : ARMInstAlias<"sxtab16${p} $Rd, $Rn, $Rm",
5010 (SXTAB16 GPRnopc:$Rd, GPR:$Rn, GPRnopc:$Rm, 0, pred:$p)>;
5011 def : ARMInstAlias<"sxtb${p} $Rd, $Rm",
5012 (SXTB GPRnopc:$Rd, GPRnopc:$Rm, 0, pred:$p)>;
5013 def : ARMInstAlias<"sxtb16${p} $Rd, $Rm",
5014 (SXTB16 GPRnopc:$Rd, GPRnopc:$Rm, 0, pred:$p)>;
5015 def : ARMInstAlias<"sxth${p} $Rd, $Rm",
5016 (SXTH GPRnopc:$Rd, GPRnopc:$Rm, 0, pred:$p)>;
5018 def : ARMInstAlias<"uxtab${p} $Rd, $Rn, $Rm",
5019 (UXTAB GPRnopc:$Rd, GPR:$Rn, GPRnopc:$Rm, 0, pred:$p)>;
5020 def : ARMInstAlias<"uxtah${p} $Rd, $Rn, $Rm",
5021 (UXTAH GPRnopc:$Rd, GPR:$Rn, GPRnopc:$Rm, 0, pred:$p)>;
5022 def : ARMInstAlias<"uxtab16${p} $Rd, $Rn, $Rm",
5023 (UXTAB16 GPRnopc:$Rd, GPR:$Rn, GPRnopc:$Rm, 0, pred:$p)>;
5024 def : ARMInstAlias<"uxtb${p} $Rd, $Rm",
5025 (UXTB GPRnopc:$Rd, GPRnopc:$Rm, 0, pred:$p)>;
5026 def : ARMInstAlias<"uxtb16${p} $Rd, $Rm",
5027 (UXTB16 GPRnopc:$Rd, GPRnopc:$Rm, 0, pred:$p)>;
5028 def : ARMInstAlias<"uxth${p} $Rd, $Rm",
5029 (UXTH GPRnopc:$Rd, GPRnopc:$Rm, 0, pred:$p)>;
5033 def : MnemonicAlias<"rfefa", "rfeda">;
5034 def : MnemonicAlias<"rfeea", "rfedb">;
5035 def : MnemonicAlias<"rfefd", "rfeia">;
5036 def : MnemonicAlias<"rfeed", "rfeib">;
5037 def : MnemonicAlias<"rfe", "rfeia">;
5040 def : MnemonicAlias<"srsfa", "srsda">;
5041 def : MnemonicAlias<"srsea", "srsdb">;
5042 def : MnemonicAlias<"srsfd", "srsia">;
5043 def : MnemonicAlias<"srsed", "srsib">;
5044 def : MnemonicAlias<"srs", "srsia">;
5047 def : MnemonicAlias<"qsubaddx", "qsax">;
5049 def : MnemonicAlias<"saddsubx", "sasx">;
5050 // SHASX == SHADDSUBX
5051 def : MnemonicAlias<"shaddsubx", "shasx">;
5052 // SHSAX == SHSUBADDX
5053 def : MnemonicAlias<"shsubaddx", "shsax">;
5055 def : MnemonicAlias<"ssubaddx", "ssax">;
5057 def : MnemonicAlias<"uaddsubx", "uasx">;
5058 // UHASX == UHADDSUBX
5059 def : MnemonicAlias<"uhaddsubx", "uhasx">;
5060 // UHSAX == UHSUBADDX
5061 def : MnemonicAlias<"uhsubaddx", "uhsax">;
5062 // UQASX == UQADDSUBX
5063 def : MnemonicAlias<"uqaddsubx", "uqasx">;
5064 // UQSAX == UQSUBADDX
5065 def : MnemonicAlias<"uqsubaddx", "uqsax">;
5067 def : MnemonicAlias<"usubaddx", "usax">;
5069 // "mov Rd, so_imm_not" can be handled via "mvn" in assembly, just like
5071 def : ARMInstAlias<"mov${s}${p} $Rd, $imm",
5072 (MVNi rGPR:$Rd, so_imm_not:$imm, pred:$p, cc_out:$s)>;
5073 def : ARMInstAlias<"mvn${s}${p} $Rd, $imm",
5074 (MOVi rGPR:$Rd, so_imm_not:$imm, pred:$p, cc_out:$s)>;
5075 // Same for AND <--> BIC
5076 def : ARMInstAlias<"bic${s}${p} $Rd, $Rn, $imm",
5077 (ANDri rGPR:$Rd, rGPR:$Rn, so_imm_not:$imm,
5078 pred:$p, cc_out:$s)>;
5079 def : ARMInstAlias<"bic${s}${p} $Rdn, $imm",
5080 (ANDri rGPR:$Rdn, rGPR:$Rdn, so_imm_not:$imm,
5081 pred:$p, cc_out:$s)>;
5082 def : ARMInstAlias<"and${s}${p} $Rd, $Rn, $imm",
5083 (BICri rGPR:$Rd, rGPR:$Rn, so_imm_not:$imm,
5084 pred:$p, cc_out:$s)>;
5085 def : ARMInstAlias<"and${s}${p} $Rdn, $imm",
5086 (BICri rGPR:$Rdn, rGPR:$Rdn, so_imm_not:$imm,
5087 pred:$p, cc_out:$s)>;
5089 // Likewise, "add Rd, so_imm_neg" -> sub
5090 def : ARMInstAlias<"add${s}${p} $Rd, $Rn, $imm",
5091 (SUBri GPR:$Rd, GPR:$Rn, so_imm_neg:$imm, pred:$p, cc_out:$s)>;
5092 def : ARMInstAlias<"add${s}${p} $Rd, $imm",
5093 (SUBri GPR:$Rd, GPR:$Rd, so_imm_neg:$imm, pred:$p, cc_out:$s)>;
5094 // Same for CMP <--> CMN via so_imm_neg
5095 def : ARMInstAlias<"cmp${p} $Rd, $imm",
5096 (CMNri rGPR:$Rd, so_imm_neg:$imm, pred:$p)>;
5097 def : ARMInstAlias<"cmn${p} $Rd, $imm",
5098 (CMPri rGPR:$Rd, so_imm_neg:$imm, pred:$p)>;
5100 // The shifter forms of the MOV instruction are aliased to the ASR, LSL,
5101 // LSR, ROR, and RRX instructions.
5102 // FIXME: We need C++ parser hooks to map the alias to the MOV
5103 // encoding. It seems we should be able to do that sort of thing
5104 // in tblgen, but it could get ugly.
5105 let TwoOperandAliasConstraint = "$Rm = $Rd" in {
5106 def ASRi : ARMAsmPseudo<"asr${s}${p} $Rd, $Rm, $imm",
5107 (ins GPR:$Rd, GPR:$Rm, imm0_32:$imm, pred:$p,
5109 def LSRi : ARMAsmPseudo<"lsr${s}${p} $Rd, $Rm, $imm",
5110 (ins GPR:$Rd, GPR:$Rm, imm0_32:$imm, pred:$p,
5112 def LSLi : ARMAsmPseudo<"lsl${s}${p} $Rd, $Rm, $imm",
5113 (ins GPR:$Rd, GPR:$Rm, imm0_31:$imm, pred:$p,
5115 def RORi : ARMAsmPseudo<"ror${s}${p} $Rd, $Rm, $imm",
5116 (ins GPR:$Rd, GPR:$Rm, imm0_31:$imm, pred:$p,
5119 def RRXi : ARMAsmPseudo<"rrx${s}${p} $Rd, $Rm",
5120 (ins GPRnopc:$Rd, GPRnopc:$Rm, pred:$p, cc_out:$s)>;
5121 let TwoOperandAliasConstraint = "$Rn = $Rd" in {
5122 def ASRr : ARMAsmPseudo<"asr${s}${p} $Rd, $Rn, $Rm",
5123 (ins GPRnopc:$Rd, GPRnopc:$Rn, GPRnopc:$Rm, pred:$p,
5125 def LSRr : ARMAsmPseudo<"lsr${s}${p} $Rd, $Rn, $Rm",
5126 (ins GPRnopc:$Rd, GPRnopc:$Rn, GPRnopc:$Rm, pred:$p,
5128 def LSLr : ARMAsmPseudo<"lsl${s}${p} $Rd, $Rn, $Rm",
5129 (ins GPRnopc:$Rd, GPRnopc:$Rn, GPRnopc:$Rm, pred:$p,
5131 def RORr : ARMAsmPseudo<"ror${s}${p} $Rd, $Rn, $Rm",
5132 (ins GPRnopc:$Rd, GPRnopc:$Rn, GPRnopc:$Rm, pred:$p,
5136 // "neg" is and alias for "rsb rd, rn, #0"
5137 def : ARMInstAlias<"neg${s}${p} $Rd, $Rm",
5138 (RSBri GPR:$Rd, GPR:$Rm, 0, pred:$p, cc_out:$s)>;
5140 // Pre-v6, 'mov r0, r0' was used as a NOP encoding.
5141 def : InstAlias<"nop${p}", (MOVr R0, R0, pred:$p, zero_reg)>,
5142 Requires<[IsARM, NoV6]>;
5144 // UMULL/SMULL are available on all arches, but the instruction definitions
5145 // need difference constraints pre-v6. Use these aliases for the assembly
5146 // parsing on pre-v6.
5147 def : InstAlias<"smull${s}${p} $RdLo, $RdHi, $Rn, $Rm",
5148 (SMULL GPR:$RdLo, GPR:$RdHi, GPR:$Rn, GPR:$Rm, pred:$p, cc_out:$s)>,
5149 Requires<[IsARM, NoV6]>;
5150 def : InstAlias<"umull${s}${p} $RdLo, $RdHi, $Rn, $Rm",
5151 (UMULL GPR:$RdLo, GPR:$RdHi, GPR:$Rn, GPR:$Rm, pred:$p, cc_out:$s)>,
5152 Requires<[IsARM, NoV6]>;
5154 // 'it' blocks in ARM mode just validate the predicates. The IT itself
5156 def ITasm : ARMAsmPseudo<"it$mask $cc", (ins it_pred:$cc, it_mask:$mask)>;