1 //===- ARMInstrInfo.td - Target Description for ARM Target -*- tablegen -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file describes the ARM instructions in TableGen format.
12 //===----------------------------------------------------------------------===//
14 //===----------------------------------------------------------------------===//
15 // ARM specific DAG Nodes.
19 def SDT_ARMCallSeqStart : SDCallSeqStart<[ SDTCisVT<0, i32> ]>;
20 def SDT_ARMCallSeqEnd : SDCallSeqEnd<[ SDTCisVT<0, i32>, SDTCisVT<1, i32> ]>;
22 def SDT_ARMSaveCallPC : SDTypeProfile<0, 1, []>;
24 def SDT_ARMcall : SDTypeProfile<0, -1, [SDTCisPtrTy<0>]>;
26 def SDT_ARMCMov : SDTypeProfile<1, 3,
27 [SDTCisSameAs<0, 1>, SDTCisSameAs<0, 2>,
30 def SDT_ARMBrcond : SDTypeProfile<0, 2,
31 [SDTCisVT<0, OtherVT>, SDTCisVT<1, i32>]>;
33 def SDT_ARMBrJT : SDTypeProfile<0, 3,
34 [SDTCisPtrTy<0>, SDTCisVT<1, i32>,
37 def SDT_ARMBr2JT : SDTypeProfile<0, 4,
38 [SDTCisPtrTy<0>, SDTCisVT<1, i32>,
39 SDTCisVT<2, i32>, SDTCisVT<3, i32>]>;
41 def SDT_ARMBCC_i64 : SDTypeProfile<0, 6,
43 SDTCisVT<1, i32>, SDTCisVT<2, i32>,
44 SDTCisVT<3, i32>, SDTCisVT<4, i32>,
45 SDTCisVT<5, OtherVT>]>;
47 def SDT_ARMAnd : SDTypeProfile<1, 2,
48 [SDTCisVT<0, i32>, SDTCisVT<1, i32>,
51 def SDT_ARMCmp : SDTypeProfile<0, 2, [SDTCisSameAs<0, 1>]>;
53 def SDT_ARMPICAdd : SDTypeProfile<1, 2, [SDTCisSameAs<0, 1>,
54 SDTCisPtrTy<1>, SDTCisVT<2, i32>]>;
56 def SDT_ARMThreadPointer : SDTypeProfile<1, 0, [SDTCisPtrTy<0>]>;
57 def SDT_ARMEH_SJLJ_Setjmp : SDTypeProfile<1, 2, [SDTCisInt<0>, SDTCisPtrTy<1>,
59 def SDT_ARMEH_SJLJ_Longjmp: SDTypeProfile<0, 2, [SDTCisPtrTy<0>, SDTCisInt<1>]>;
61 def SDT_ARMEH_SJLJ_DispatchSetup: SDTypeProfile<0, 1, [SDTCisPtrTy<0>]>;
63 def SDT_ARMMEMBARRIER : SDTypeProfile<0, 1, [SDTCisInt<0>]>;
65 def SDT_ARMTCRET : SDTypeProfile<0, 1, [SDTCisPtrTy<0>]>;
67 def SDT_ARMBFI : SDTypeProfile<1, 3, [SDTCisVT<0, i32>, SDTCisVT<1, i32>,
68 SDTCisVT<2, i32>, SDTCisVT<3, i32>]>;
71 def ARMWrapper : SDNode<"ARMISD::Wrapper", SDTIntUnaryOp>;
72 def ARMWrapperJT : SDNode<"ARMISD::WrapperJT", SDTIntBinOp>;
74 def ARMcallseq_start : SDNode<"ISD::CALLSEQ_START", SDT_ARMCallSeqStart,
75 [SDNPHasChain, SDNPOutFlag]>;
76 def ARMcallseq_end : SDNode<"ISD::CALLSEQ_END", SDT_ARMCallSeqEnd,
77 [SDNPHasChain, SDNPOptInFlag, SDNPOutFlag]>;
79 def ARMcall : SDNode<"ARMISD::CALL", SDT_ARMcall,
80 [SDNPHasChain, SDNPOptInFlag, SDNPOutFlag,
82 def ARMcall_pred : SDNode<"ARMISD::CALL_PRED", SDT_ARMcall,
83 [SDNPHasChain, SDNPOptInFlag, SDNPOutFlag,
85 def ARMcall_nolink : SDNode<"ARMISD::CALL_NOLINK", SDT_ARMcall,
86 [SDNPHasChain, SDNPOptInFlag, SDNPOutFlag,
89 def ARMretflag : SDNode<"ARMISD::RET_FLAG", SDTNone,
90 [SDNPHasChain, SDNPOptInFlag]>;
92 def ARMcmov : SDNode<"ARMISD::CMOV", SDT_ARMCMov,
94 def ARMcneg : SDNode<"ARMISD::CNEG", SDT_ARMCMov,
97 def ARMbrcond : SDNode<"ARMISD::BRCOND", SDT_ARMBrcond,
98 [SDNPHasChain, SDNPInFlag, SDNPOutFlag]>;
100 def ARMbrjt : SDNode<"ARMISD::BR_JT", SDT_ARMBrJT,
102 def ARMbr2jt : SDNode<"ARMISD::BR2_JT", SDT_ARMBr2JT,
105 def ARMBcci64 : SDNode<"ARMISD::BCC_i64", SDT_ARMBCC_i64,
108 def ARMcmp : SDNode<"ARMISD::CMP", SDT_ARMCmp,
111 def ARMcmpZ : SDNode<"ARMISD::CMPZ", SDT_ARMCmp,
112 [SDNPOutFlag, SDNPCommutative]>;
114 def ARMpic_add : SDNode<"ARMISD::PIC_ADD", SDT_ARMPICAdd>;
116 def ARMsrl_flag : SDNode<"ARMISD::SRL_FLAG", SDTIntUnaryOp, [SDNPOutFlag]>;
117 def ARMsra_flag : SDNode<"ARMISD::SRA_FLAG", SDTIntUnaryOp, [SDNPOutFlag]>;
118 def ARMrrx : SDNode<"ARMISD::RRX" , SDTIntUnaryOp, [SDNPInFlag ]>;
120 def ARMthread_pointer: SDNode<"ARMISD::THREAD_POINTER", SDT_ARMThreadPointer>;
121 def ARMeh_sjlj_setjmp: SDNode<"ARMISD::EH_SJLJ_SETJMP",
122 SDT_ARMEH_SJLJ_Setjmp, [SDNPHasChain]>;
123 def ARMeh_sjlj_longjmp: SDNode<"ARMISD::EH_SJLJ_LONGJMP",
124 SDT_ARMEH_SJLJ_Longjmp, [SDNPHasChain]>;
125 def ARMeh_sjlj_dispatchsetup: SDNode<"ARMISD::EH_SJLJ_DISPATCHSETUP",
126 SDT_ARMEH_SJLJ_DispatchSetup, [SDNPHasChain]>;
129 def ARMMemBarrier : SDNode<"ARMISD::MEMBARRIER", SDT_ARMMEMBARRIER,
131 def ARMMemBarrierMCR : SDNode<"ARMISD::MEMBARRIER_MCR", SDT_ARMMEMBARRIER,
134 def ARMrbit : SDNode<"ARMISD::RBIT", SDTIntUnaryOp>;
136 def ARMtcret : SDNode<"ARMISD::TC_RETURN", SDT_ARMTCRET,
137 [SDNPHasChain, SDNPOptInFlag, SDNPVariadic]>;
140 def ARMbfi : SDNode<"ARMISD::BFI", SDT_ARMBFI>;
142 //===----------------------------------------------------------------------===//
143 // ARM Instruction Predicate Definitions.
145 def HasV4T : Predicate<"Subtarget->hasV4TOps()">, AssemblerPredicate;
146 def NoV4T : Predicate<"!Subtarget->hasV4TOps()">;
147 def HasV5T : Predicate<"Subtarget->hasV5TOps()">;
148 def HasV5TE : Predicate<"Subtarget->hasV5TEOps()">, AssemblerPredicate;
149 def HasV6 : Predicate<"Subtarget->hasV6Ops()">, AssemblerPredicate;
150 def HasV6T2 : Predicate<"Subtarget->hasV6T2Ops()">, AssemblerPredicate;
151 def NoV6T2 : Predicate<"!Subtarget->hasV6T2Ops()">;
152 def HasV7 : Predicate<"Subtarget->hasV7Ops()">, AssemblerPredicate;
153 def NoVFP : Predicate<"!Subtarget->hasVFP2()">;
154 def HasVFP2 : Predicate<"Subtarget->hasVFP2()">, AssemblerPredicate;
155 def HasVFP3 : Predicate<"Subtarget->hasVFP3()">, AssemblerPredicate;
156 def HasNEON : Predicate<"Subtarget->hasNEON()">, AssemblerPredicate;
157 def HasDivide : Predicate<"Subtarget->hasDivide()">, AssemblerPredicate;
158 def HasT2ExtractPack : Predicate<"Subtarget->hasT2ExtractPack()">,
160 def HasDB : Predicate<"Subtarget->hasDataBarrier()">,
162 def UseNEONForFP : Predicate<"Subtarget->useNEONForSinglePrecisionFP()">;
163 def DontUseNEONForFP : Predicate<"!Subtarget->useNEONForSinglePrecisionFP()">;
164 def IsThumb : Predicate<"Subtarget->isThumb()">, AssemblerPredicate;
165 def IsThumb1Only : Predicate<"Subtarget->isThumb1Only()">;
166 def IsThumb2 : Predicate<"Subtarget->isThumb2()">, AssemblerPredicate;
167 def IsARM : Predicate<"!Subtarget->isThumb()">, AssemblerPredicate;
168 def IsDarwin : Predicate<"Subtarget->isTargetDarwin()">;
169 def IsNotDarwin : Predicate<"!Subtarget->isTargetDarwin()">;
171 // FIXME: Eventually this will be just "hasV6T2Ops".
172 def UseMovt : Predicate<"Subtarget->useMovt()">;
173 def DontUseMovt : Predicate<"!Subtarget->useMovt()">;
174 def UseVMLx : Predicate<"Subtarget->useVMLx()">;
176 //===----------------------------------------------------------------------===//
177 // ARM Flag Definitions.
179 class RegConstraint<string C> {
180 string Constraints = C;
183 //===----------------------------------------------------------------------===//
184 // ARM specific transformation functions and pattern fragments.
187 // so_imm_neg_XFORM - Return a so_imm value packed into the format described for
188 // so_imm_neg def below.
189 def so_imm_neg_XFORM : SDNodeXForm<imm, [{
190 return CurDAG->getTargetConstant(-(int)N->getZExtValue(), MVT::i32);
193 // so_imm_not_XFORM - Return a so_imm value packed into the format described for
194 // so_imm_not def below.
195 def so_imm_not_XFORM : SDNodeXForm<imm, [{
196 return CurDAG->getTargetConstant(~(int)N->getZExtValue(), MVT::i32);
199 /// imm1_15 predicate - True if the 32-bit immediate is in the range [1,15].
200 def imm1_15 : PatLeaf<(i32 imm), [{
201 return (int32_t)N->getZExtValue() >= 1 && (int32_t)N->getZExtValue() < 16;
204 /// imm16_31 predicate - True if the 32-bit immediate is in the range [16,31].
205 def imm16_31 : PatLeaf<(i32 imm), [{
206 return (int32_t)N->getZExtValue() >= 16 && (int32_t)N->getZExtValue() < 32;
211 return ARM_AM::getSOImmVal(-(int)N->getZExtValue()) != -1;
212 }], so_imm_neg_XFORM>;
216 return ARM_AM::getSOImmVal(~(int)N->getZExtValue()) != -1;
217 }], so_imm_not_XFORM>;
219 // sext_16_node predicate - True if the SDNode is sign-extended 16 or more bits.
220 def sext_16_node : PatLeaf<(i32 GPR:$a), [{
221 return CurDAG->ComputeNumSignBits(SDValue(N,0)) >= 17;
224 /// bf_inv_mask_imm predicate - An AND mask to clear an arbitrary width bitfield
226 def bf_inv_mask_imm : Operand<i32>,
228 return ARM::isBitFieldInvertedMask(N->getZExtValue());
230 string EncoderMethod = "getBitfieldInvertedMaskOpValue";
231 let PrintMethod = "printBitfieldInvMaskImmOperand";
234 /// Split a 32-bit immediate into two 16 bit parts.
235 def hi16 : SDNodeXForm<imm, [{
236 return CurDAG->getTargetConstant((uint32_t)N->getZExtValue() >> 16, MVT::i32);
239 def lo16AllZero : PatLeaf<(i32 imm), [{
240 // Returns true if all low 16-bits are 0.
241 return (((uint32_t)N->getZExtValue()) & 0xFFFFUL) == 0;
244 /// imm0_65535 predicate - True if the 32-bit immediate is in the range
246 def imm0_65535 : PatLeaf<(i32 imm), [{
247 return (uint32_t)N->getZExtValue() < 65536;
250 class BinOpFrag<dag res> : PatFrag<(ops node:$LHS, node:$RHS), res>;
251 class UnOpFrag <dag res> : PatFrag<(ops node:$Src), res>;
253 /// adde and sube predicates - True based on whether the carry flag output
254 /// will be needed or not.
255 def adde_dead_carry :
256 PatFrag<(ops node:$LHS, node:$RHS), (adde node:$LHS, node:$RHS),
257 [{return !N->hasAnyUseOfValue(1);}]>;
258 def sube_dead_carry :
259 PatFrag<(ops node:$LHS, node:$RHS), (sube node:$LHS, node:$RHS),
260 [{return !N->hasAnyUseOfValue(1);}]>;
261 def adde_live_carry :
262 PatFrag<(ops node:$LHS, node:$RHS), (adde node:$LHS, node:$RHS),
263 [{return N->hasAnyUseOfValue(1);}]>;
264 def sube_live_carry :
265 PatFrag<(ops node:$LHS, node:$RHS), (sube node:$LHS, node:$RHS),
266 [{return N->hasAnyUseOfValue(1);}]>;
268 //===----------------------------------------------------------------------===//
269 // Operand Definitions.
273 def brtarget : Operand<OtherVT>;
275 // A list of registers separated by comma. Used by load/store multiple.
276 def reglist : Operand<i32> {
277 string EncoderMethod = "getRegisterListOpValue";
278 let PrintMethod = "printRegisterList";
281 // An operand for the CONSTPOOL_ENTRY pseudo-instruction.
282 def cpinst_operand : Operand<i32> {
283 let PrintMethod = "printCPInstOperand";
286 def jtblock_operand : Operand<i32> {
287 let PrintMethod = "printJTBlockOperand";
289 def jt2block_operand : Operand<i32> {
290 let PrintMethod = "printJT2BlockOperand";
294 def pclabel : Operand<i32> {
295 let PrintMethod = "printPCLabel";
298 def neon_vcvt_imm32 : Operand<i32> {
299 string EncoderMethod = "getNEONVcvtImm32OpValue";
302 // rot_imm: An integer that encodes a rotate amount. Must be 8, 16, or 24.
303 def rot_imm : Operand<i32>, PatLeaf<(i32 imm), [{
304 int32_t v = (int32_t)N->getZExtValue();
305 return v == 8 || v == 16 || v == 24; }]> {
306 string EncoderMethod = "getRotImmOpValue";
309 // shift_imm: An integer that encodes a shift amount and the type of shift
310 // (currently either asr or lsl) using the same encoding used for the
311 // immediates in so_reg operands.
312 def shift_imm : Operand<i32> {
313 let PrintMethod = "printShiftImmOperand";
316 // shifter_operand operands: so_reg and so_imm.
317 def so_reg : Operand<i32>, // reg reg imm
318 ComplexPattern<i32, 3, "SelectShifterOperandReg",
319 [shl,srl,sra,rotr]> {
320 string EncoderMethod = "getSORegOpValue";
321 let PrintMethod = "printSORegOperand";
322 let MIOperandInfo = (ops GPR, GPR, i32imm);
324 def shift_so_reg : Operand<i32>, // reg reg imm
325 ComplexPattern<i32, 3, "SelectShiftShifterOperandReg",
326 [shl,srl,sra,rotr]> {
327 string EncoderMethod = "getSORegOpValue";
328 let PrintMethod = "printSORegOperand";
329 let MIOperandInfo = (ops GPR, GPR, i32imm);
332 // so_imm - Match a 32-bit shifter_operand immediate operand, which is an
333 // 8-bit immediate rotated by an arbitrary number of bits. so_imm values are
334 // represented in the imm field in the same 12-bit form that they are encoded
335 // into so_imm instructions: the 8-bit immediate is the least significant bits
336 // [bits 0-7], the 4-bit shift amount is the next 4 bits [bits 8-11].
337 def so_imm : Operand<i32>, PatLeaf<(imm), [{ return Pred_so_imm(N); }]> {
338 string EncoderMethod = "getSOImmOpValue";
339 let PrintMethod = "printSOImmOperand";
342 // Break so_imm's up into two pieces. This handles immediates with up to 16
343 // bits set in them. This uses so_imm2part to match and so_imm2part_[12] to
344 // get the first/second pieces.
345 def so_imm2part : Operand<i32>,
347 return ARM_AM::isSOImmTwoPartVal((unsigned)N->getZExtValue());
349 let PrintMethod = "printSOImm2PartOperand";
352 def so_imm2part_1 : SDNodeXForm<imm, [{
353 unsigned V = ARM_AM::getSOImmTwoPartFirst((unsigned)N->getZExtValue());
354 return CurDAG->getTargetConstant(V, MVT::i32);
357 def so_imm2part_2 : SDNodeXForm<imm, [{
358 unsigned V = ARM_AM::getSOImmTwoPartSecond((unsigned)N->getZExtValue());
359 return CurDAG->getTargetConstant(V, MVT::i32);
362 def so_neg_imm2part : Operand<i32>, PatLeaf<(imm), [{
363 return ARM_AM::isSOImmTwoPartVal(-(int)N->getZExtValue());
365 let PrintMethod = "printSOImm2PartOperand";
368 def so_neg_imm2part_1 : SDNodeXForm<imm, [{
369 unsigned V = ARM_AM::getSOImmTwoPartFirst(-(int)N->getZExtValue());
370 return CurDAG->getTargetConstant(V, MVT::i32);
373 def so_neg_imm2part_2 : SDNodeXForm<imm, [{
374 unsigned V = ARM_AM::getSOImmTwoPartSecond(-(int)N->getZExtValue());
375 return CurDAG->getTargetConstant(V, MVT::i32);
378 /// imm0_31 predicate - True if the 32-bit immediate is in the range [0,31].
379 def imm0_31 : Operand<i32>, PatLeaf<(imm), [{
380 return (int32_t)N->getZExtValue() < 32;
383 /// imm0_31_m1 - Matches and prints like imm0_31, but encodes as 'value - 1'.
384 def imm0_31_m1 : Operand<i32>, PatLeaf<(imm), [{
385 return (int32_t)N->getZExtValue() < 32;
387 string EncoderMethod = "getImmMinusOneOpValue";
390 // Define ARM specific addressing modes.
393 // addrmode_imm12 := reg +/- imm12
395 def addrmode_imm12 : Operand<i32>,
396 ComplexPattern<i32, 2, "SelectAddrModeImm12", []> {
397 // 12-bit immediate operand. Note that instructions using this encode
398 // #0 and #-0 differently. We flag #-0 as the magic value INT32_MIN. All other
399 // immediate values are as normal.
401 string EncoderMethod = "getAddrModeImm12OpValue";
402 let PrintMethod = "printAddrModeImm12Operand";
403 let MIOperandInfo = (ops GPR:$base, i32imm:$offsimm);
405 // ldst_so_reg := reg +/- reg shop imm
407 def ldst_so_reg : Operand<i32>,
408 ComplexPattern<i32, 3, "SelectLdStSOReg", []> {
409 // FIXME: Simplify the printer
410 // FIXME: Add EncoderMethod for this addressing mode
411 let PrintMethod = "printAddrMode2Operand";
412 let MIOperandInfo = (ops GPR:$base, GPR:$offsreg, i32imm:$offsimm);
415 // addrmode2 := reg +/- imm12
416 // := reg +/- reg shop imm
418 def addrmode2 : Operand<i32>,
419 ComplexPattern<i32, 3, "SelectAddrMode2", []> {
420 let PrintMethod = "printAddrMode2Operand";
421 let MIOperandInfo = (ops GPR:$base, GPR:$offsreg, i32imm:$offsimm);
424 def am2offset : Operand<i32>,
425 ComplexPattern<i32, 2, "SelectAddrMode2Offset",
426 [], [SDNPWantRoot]> {
427 let PrintMethod = "printAddrMode2OffsetOperand";
428 let MIOperandInfo = (ops GPR, i32imm);
431 // addrmode3 := reg +/- reg
432 // addrmode3 := reg +/- imm8
434 def addrmode3 : Operand<i32>,
435 ComplexPattern<i32, 3, "SelectAddrMode3", []> {
436 let PrintMethod = "printAddrMode3Operand";
437 let MIOperandInfo = (ops GPR:$base, GPR:$offsreg, i32imm:$offsimm);
440 def am3offset : Operand<i32>,
441 ComplexPattern<i32, 2, "SelectAddrMode3Offset",
442 [], [SDNPWantRoot]> {
443 let PrintMethod = "printAddrMode3OffsetOperand";
444 let MIOperandInfo = (ops GPR, i32imm);
447 // ldstm_mode := {ia, ib, da, db}
449 def ldstm_mode : OptionalDefOperand<OtherVT, (ops i32), (ops (i32 1))> {
450 let PrintMethod = "printLdStmModeOperand";
453 def ARMMemMode5AsmOperand : AsmOperandClass {
454 let Name = "MemMode5";
455 let SuperClasses = [];
458 // addrmode5 := reg +/- imm8*4
460 def addrmode5 : Operand<i32>,
461 ComplexPattern<i32, 2, "SelectAddrMode5", []> {
462 let PrintMethod = "printAddrMode5Operand";
463 let MIOperandInfo = (ops GPR:$base, i32imm);
464 let ParserMatchClass = ARMMemMode5AsmOperand;
465 string EncoderMethod = "getAddrMode5OpValue";
468 // addrmode6 := reg with optional writeback
470 def addrmode6 : Operand<i32>,
471 ComplexPattern<i32, 2, "SelectAddrMode6", [], [SDNPWantParent]>{
472 let PrintMethod = "printAddrMode6Operand";
473 let MIOperandInfo = (ops GPR:$addr, i32imm);
474 string EncoderMethod = "getAddrMode6AddressOpValue";
477 def am6offset : Operand<i32> {
478 let PrintMethod = "printAddrMode6OffsetOperand";
479 let MIOperandInfo = (ops GPR);
480 string EncoderMethod = "getAddrMode6OffsetOpValue";
483 // addrmodepc := pc + reg
485 def addrmodepc : Operand<i32>,
486 ComplexPattern<i32, 2, "SelectAddrModePC", []> {
487 let PrintMethod = "printAddrModePCOperand";
488 let MIOperandInfo = (ops GPR, i32imm);
491 def nohash_imm : Operand<i32> {
492 let PrintMethod = "printNoHashImmediate";
495 //===----------------------------------------------------------------------===//
497 include "ARMInstrFormats.td"
499 //===----------------------------------------------------------------------===//
500 // Multiclass helpers...
503 /// AsI1_bin_irs - Defines a set of (op r, {so_imm|r|so_reg}) patterns for a
504 /// binop that produces a value.
505 multiclass AsI1_bin_irs<bits<4> opcod, string opc,
506 InstrItinClass iii, InstrItinClass iir, InstrItinClass iis,
507 PatFrag opnode, bit Commutable = 0> {
508 // The register-immediate version is re-materializable. This is useful
509 // in particular for taking the address of a local.
510 let isReMaterializable = 1 in {
511 def ri : AsI1<opcod, (outs GPR:$Rd), (ins GPR:$Rn, so_imm:$imm), DPFrm,
512 iii, opc, "\t$Rd, $Rn, $imm",
513 [(set GPR:$Rd, (opnode GPR:$Rn, so_imm:$imm))]> {
518 let Inst{19-16} = Rn;
519 let Inst{15-12} = Rd;
520 let Inst{11-0} = imm;
523 def rr : AsI1<opcod, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm), DPFrm,
524 iir, opc, "\t$Rd, $Rn, $Rm",
525 [(set GPR:$Rd, (opnode GPR:$Rn, GPR:$Rm))]> {
530 let isCommutable = Commutable;
531 let Inst{19-16} = Rn;
532 let Inst{15-12} = Rd;
533 let Inst{11-4} = 0b00000000;
536 def rs : AsI1<opcod, (outs GPR:$Rd), (ins GPR:$Rn, so_reg:$shift), DPSoRegFrm,
537 iis, opc, "\t$Rd, $Rn, $shift",
538 [(set GPR:$Rd, (opnode GPR:$Rn, so_reg:$shift))]> {
543 let Inst{19-16} = Rn;
544 let Inst{15-12} = Rd;
545 let Inst{11-0} = shift;
549 /// AI1_bin_s_irs - Similar to AsI1_bin_irs except it sets the 's' bit so the
550 /// instruction modifies the CPSR register.
551 let Defs = [CPSR] in {
552 multiclass AI1_bin_s_irs<bits<4> opcod, string opc,
553 InstrItinClass iii, InstrItinClass iir, InstrItinClass iis,
554 PatFrag opnode, bit Commutable = 0> {
555 def ri : AI1<opcod, (outs GPR:$Rd), (ins GPR:$Rn, so_imm:$imm), DPFrm,
556 iii, opc, "\t$Rd, $Rn, $imm",
557 [(set GPR:$Rd, (opnode GPR:$Rn, so_imm:$imm))]> {
563 let Inst{19-16} = Rn;
564 let Inst{15-12} = Rd;
565 let Inst{11-0} = imm;
567 def rr : AI1<opcod, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm), DPFrm,
568 iir, opc, "\t$Rd, $Rn, $Rm",
569 [(set GPR:$Rd, (opnode GPR:$Rn, GPR:$Rm))]> {
573 let isCommutable = Commutable;
576 let Inst{19-16} = Rn;
577 let Inst{15-12} = Rd;
578 let Inst{11-4} = 0b00000000;
581 def rs : AI1<opcod, (outs GPR:$Rd), (ins GPR:$Rn, so_reg:$shift), DPSoRegFrm,
582 iis, opc, "\t$Rd, $Rn, $shift",
583 [(set GPR:$Rd, (opnode GPR:$Rn, so_reg:$shift))]> {
589 let Inst{19-16} = Rn;
590 let Inst{15-12} = Rd;
591 let Inst{11-0} = shift;
596 /// AI1_cmp_irs - Defines a set of (op r, {so_imm|r|so_reg}) cmp / test
597 /// patterns. Similar to AsI1_bin_irs except the instruction does not produce
598 /// a explicit result, only implicitly set CPSR.
599 let isCompare = 1, Defs = [CPSR] in {
600 multiclass AI1_cmp_irs<bits<4> opcod, string opc,
601 InstrItinClass iii, InstrItinClass iir, InstrItinClass iis,
602 PatFrag opnode, bit Commutable = 0> {
603 def ri : AI1<opcod, (outs), (ins GPR:$Rn, so_imm:$imm), DPFrm, iii,
605 [(opnode GPR:$Rn, so_imm:$imm)]> {
610 let Inst{19-16} = Rn;
611 let Inst{15-12} = 0b0000;
612 let Inst{11-0} = imm;
614 def rr : AI1<opcod, (outs), (ins GPR:$Rn, GPR:$Rm), DPFrm, iir,
616 [(opnode GPR:$Rn, GPR:$Rm)]> {
619 let isCommutable = Commutable;
622 let Inst{19-16} = Rn;
623 let Inst{15-12} = 0b0000;
624 let Inst{11-4} = 0b00000000;
627 def rs : AI1<opcod, (outs), (ins GPR:$Rn, so_reg:$shift), DPSoRegFrm, iis,
628 opc, "\t$Rn, $shift",
629 [(opnode GPR:$Rn, so_reg:$shift)]> {
634 let Inst{19-16} = Rn;
635 let Inst{15-12} = 0b0000;
636 let Inst{11-0} = shift;
641 /// AI_ext_rrot - A unary operation with two forms: one whose operand is a
642 /// register and one whose operand is a register rotated by 8/16/24.
643 /// FIXME: Remove the 'r' variant. Its rot_imm is zero.
644 multiclass AI_ext_rrot<bits<8> opcod, string opc, PatFrag opnode> {
645 def r : AExtI<opcod, (outs GPR:$Rd), (ins GPR:$Rm),
646 IIC_iEXTr, opc, "\t$Rd, $Rm",
647 [(set GPR:$Rd, (opnode GPR:$Rm))]>,
648 Requires<[IsARM, HasV6]> {
651 let Inst{19-16} = 0b1111;
652 let Inst{15-12} = Rd;
653 let Inst{11-10} = 0b00;
656 def r_rot : AExtI<opcod, (outs GPR:$Rd), (ins GPR:$Rm, rot_imm:$rot),
657 IIC_iEXTr, opc, "\t$Rd, $Rm, ror $rot",
658 [(set GPR:$Rd, (opnode (rotr GPR:$Rm, rot_imm:$rot)))]>,
659 Requires<[IsARM, HasV6]> {
663 let Inst{19-16} = 0b1111;
664 let Inst{15-12} = Rd;
665 let Inst{11-10} = rot;
670 multiclass AI_ext_rrot_np<bits<8> opcod, string opc> {
671 def r : AExtI<opcod, (outs GPR:$Rd), (ins GPR:$Rm),
672 IIC_iEXTr, opc, "\t$Rd, $Rm",
673 [/* For disassembly only; pattern left blank */]>,
674 Requires<[IsARM, HasV6]> {
675 let Inst{19-16} = 0b1111;
676 let Inst{11-10} = 0b00;
678 def r_rot : AExtI<opcod, (outs GPR:$Rd), (ins GPR:$Rm, rot_imm:$rot),
679 IIC_iEXTr, opc, "\t$Rd, $Rm, ror $rot",
680 [/* For disassembly only; pattern left blank */]>,
681 Requires<[IsARM, HasV6]> {
683 let Inst{19-16} = 0b1111;
684 let Inst{11-10} = rot;
688 /// AI_exta_rrot - A binary operation with two forms: one whose operand is a
689 /// register and one whose operand is a register rotated by 8/16/24.
690 multiclass AI_exta_rrot<bits<8> opcod, string opc, PatFrag opnode> {
691 def rr : AExtI<opcod, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm),
692 IIC_iEXTAr, opc, "\t$Rd, $Rn, $Rm",
693 [(set GPR:$Rd, (opnode GPR:$Rn, GPR:$Rm))]>,
694 Requires<[IsARM, HasV6]> {
695 let Inst{11-10} = 0b00;
697 def rr_rot : AExtI<opcod, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm,
699 IIC_iEXTAr, opc, "\t$Rd, $Rn, $Rm, ror $rot",
700 [(set GPR:$Rd, (opnode GPR:$Rn,
701 (rotr GPR:$Rm, rot_imm:$rot)))]>,
702 Requires<[IsARM, HasV6]> {
705 let Inst{19-16} = Rn;
706 let Inst{11-10} = rot;
710 // For disassembly only.
711 multiclass AI_exta_rrot_np<bits<8> opcod, string opc> {
712 def rr : AExtI<opcod, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm),
713 IIC_iEXTAr, opc, "\t$Rd, $Rn, $Rm",
714 [/* For disassembly only; pattern left blank */]>,
715 Requires<[IsARM, HasV6]> {
716 let Inst{11-10} = 0b00;
718 def rr_rot : AExtI<opcod, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm,
720 IIC_iEXTAr, opc, "\t$Rd, $Rn, $Rm, ror $rot",
721 [/* For disassembly only; pattern left blank */]>,
722 Requires<[IsARM, HasV6]> {
725 let Inst{19-16} = Rn;
726 let Inst{11-10} = rot;
730 /// AI1_adde_sube_irs - Define instructions and patterns for adde and sube.
731 let Uses = [CPSR] in {
732 multiclass AI1_adde_sube_irs<bits<4> opcod, string opc, PatFrag opnode,
733 bit Commutable = 0> {
734 def ri : AsI1<opcod, (outs GPR:$Rd), (ins GPR:$Rn, so_imm:$imm),
735 DPFrm, IIC_iALUi, opc, "\t$Rd, $Rn, $imm",
736 [(set GPR:$Rd, (opnode GPR:$Rn, so_imm:$imm))]>,
742 let Inst{15-12} = Rd;
743 let Inst{19-16} = Rn;
744 let Inst{11-0} = imm;
746 def rr : AsI1<opcod, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm),
747 DPFrm, IIC_iALUr, opc, "\t$Rd, $Rn, $Rm",
748 [(set GPR:$Rd, (opnode GPR:$Rn, GPR:$Rm))]>,
753 let Inst{11-4} = 0b00000000;
755 let isCommutable = Commutable;
757 let Inst{15-12} = Rd;
758 let Inst{19-16} = Rn;
760 def rs : AsI1<opcod, (outs GPR:$Rd), (ins GPR:$Rn, so_reg:$shift),
761 DPSoRegFrm, IIC_iALUsr, opc, "\t$Rd, $Rn, $shift",
762 [(set GPR:$Rd, (opnode GPR:$Rn, so_reg:$shift))]>,
768 let Inst{11-0} = shift;
769 let Inst{15-12} = Rd;
770 let Inst{19-16} = Rn;
773 // Carry setting variants
774 let Defs = [CPSR] in {
775 multiclass AI1_adde_sube_s_irs<bits<4> opcod, string opc, PatFrag opnode,
776 bit Commutable = 0> {
777 def Sri : AXI1<opcod, (outs GPR:$Rd), (ins GPR:$Rn, so_imm:$imm),
778 DPFrm, IIC_iALUi, !strconcat(opc, "\t$Rd, $Rn, $imm"),
779 [(set GPR:$Rd, (opnode GPR:$Rn, so_imm:$imm))]>,
784 let Inst{15-12} = Rd;
785 let Inst{19-16} = Rn;
786 let Inst{11-0} = imm;
790 def Srr : AXI1<opcod, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm),
791 DPFrm, IIC_iALUr, !strconcat(opc, "\t$Rd, $Rn, $Rm"),
792 [(set GPR:$Rd, (opnode GPR:$Rn, GPR:$Rm))]>,
797 let Inst{11-4} = 0b00000000;
798 let isCommutable = Commutable;
800 let Inst{15-12} = Rd;
801 let Inst{19-16} = Rn;
805 def Srs : AXI1<opcod, (outs GPR:$Rd), (ins GPR:$Rn, so_reg:$shift),
806 DPSoRegFrm, IIC_iALUsr, !strconcat(opc, "\t$Rd, $Rn, $shift"),
807 [(set GPR:$Rd, (opnode GPR:$Rn, so_reg:$shift))]>,
812 let Inst{11-0} = shift;
813 let Inst{15-12} = Rd;
814 let Inst{19-16} = Rn;
822 let canFoldAsLoad = 1, isReMaterializable = 1 in {
823 multiclass AI_ldr1<bit opc22, string opc, InstrItinClass iii,
824 InstrItinClass iir, PatFrag opnode> {
825 // Note: We use the complex addrmode_imm12 rather than just an input
826 // GPR and a constrained immediate so that we can use this to match
827 // frame index references and avoid matching constant pool references.
828 def i12 : AIldst1<0b010, opc22, 1, (outs GPR:$Rt), (ins addrmode_imm12:$addr),
829 AddrMode_i12, LdFrm, iii, opc, "\t$Rt, $addr",
830 [(set GPR:$Rt, (opnode addrmode_imm12:$addr))]> {
833 let Inst{23} = addr{12}; // U (add = ('U' == 1))
834 let Inst{19-16} = addr{16-13}; // Rn
835 let Inst{15-12} = Rt;
836 let Inst{11-0} = addr{11-0}; // imm12
838 def rs : AIldst1<0b011, opc22, 1, (outs GPR:$Rt), (ins ldst_so_reg:$shift),
839 AddrModeNone, LdFrm, iir, opc, "\t$Rt, $shift",
840 [(set GPR:$Rt, (opnode ldst_so_reg:$shift))]> {
843 let Inst{23} = shift{12}; // U (add = ('U' == 1))
844 let Inst{19-16} = shift{16-13}; // Rn
845 let Inst{11-0} = shift{11-0};
850 multiclass AI_str1<bit opc22, string opc, InstrItinClass iii,
851 InstrItinClass iir, PatFrag opnode> {
852 // Note: We use the complex addrmode_imm12 rather than just an input
853 // GPR and a constrained immediate so that we can use this to match
854 // frame index references and avoid matching constant pool references.
855 def i12 : AIldst1<0b010, opc22, 0, (outs),
856 (ins GPR:$Rt, addrmode_imm12:$addr),
857 AddrMode_i12, StFrm, iii, opc, "\t$Rt, $addr",
858 [(opnode GPR:$Rt, addrmode_imm12:$addr)]> {
861 let Inst{23} = addr{12}; // U (add = ('U' == 1))
862 let Inst{19-16} = addr{16-13}; // Rn
863 let Inst{15-12} = Rt;
864 let Inst{11-0} = addr{11-0}; // imm12
866 def rs : AIldst1<0b011, opc22, 0, (outs), (ins GPR:$Rt, ldst_so_reg:$shift),
867 AddrModeNone, StFrm, iir, opc, "\t$Rt, $shift",
868 [(opnode GPR:$Rt, ldst_so_reg:$shift)]> {
871 let Inst{23} = shift{12}; // U (add = ('U' == 1))
872 let Inst{19-16} = shift{16-13}; // Rn
873 let Inst{11-0} = shift{11-0};
876 //===----------------------------------------------------------------------===//
878 //===----------------------------------------------------------------------===//
880 //===----------------------------------------------------------------------===//
881 // Miscellaneous Instructions.
884 /// CONSTPOOL_ENTRY - This instruction represents a floating constant pool in
885 /// the function. The first operand is the ID# for this instruction, the second
886 /// is the index into the MachineConstantPool that this is, the third is the
887 /// size in bytes of this constant pool entry.
888 let neverHasSideEffects = 1, isNotDuplicable = 1 in
889 def CONSTPOOL_ENTRY :
890 PseudoInst<(outs), (ins cpinst_operand:$instid, cpinst_operand:$cpidx,
891 i32imm:$size), NoItinerary, "", []>;
893 // FIXME: Marking these as hasSideEffects is necessary to prevent machine DCE
894 // from removing one half of the matched pairs. That breaks PEI, which assumes
895 // these will always be in pairs, and asserts if it finds otherwise. Better way?
896 let Defs = [SP], Uses = [SP], hasSideEffects = 1 in {
898 PseudoInst<(outs), (ins i32imm:$amt1, i32imm:$amt2, pred:$p), NoItinerary, "",
899 [(ARMcallseq_end timm:$amt1, timm:$amt2)]>;
901 def ADJCALLSTACKDOWN :
902 PseudoInst<(outs), (ins i32imm:$amt, pred:$p), NoItinerary, "",
903 [(ARMcallseq_start timm:$amt)]>;
906 def NOP : AI<(outs), (ins), MiscFrm, NoItinerary, "nop", "",
907 [/* For disassembly only; pattern left blank */]>,
908 Requires<[IsARM, HasV6T2]> {
909 let Inst{27-16} = 0b001100100000;
910 let Inst{15-8} = 0b11110000;
911 let Inst{7-0} = 0b00000000;
914 def YIELD : AI<(outs), (ins), MiscFrm, NoItinerary, "yield", "",
915 [/* For disassembly only; pattern left blank */]>,
916 Requires<[IsARM, HasV6T2]> {
917 let Inst{27-16} = 0b001100100000;
918 let Inst{15-8} = 0b11110000;
919 let Inst{7-0} = 0b00000001;
922 def WFE : AI<(outs), (ins), MiscFrm, NoItinerary, "wfe", "",
923 [/* For disassembly only; pattern left blank */]>,
924 Requires<[IsARM, HasV6T2]> {
925 let Inst{27-16} = 0b001100100000;
926 let Inst{15-8} = 0b11110000;
927 let Inst{7-0} = 0b00000010;
930 def WFI : AI<(outs), (ins), MiscFrm, NoItinerary, "wfi", "",
931 [/* For disassembly only; pattern left blank */]>,
932 Requires<[IsARM, HasV6T2]> {
933 let Inst{27-16} = 0b001100100000;
934 let Inst{15-8} = 0b11110000;
935 let Inst{7-0} = 0b00000011;
938 def SEL : AI<(outs GPR:$dst), (ins GPR:$a, GPR:$b), DPFrm, NoItinerary, "sel",
940 [/* For disassembly only; pattern left blank */]>,
941 Requires<[IsARM, HasV6]> {
946 let Inst{15-12} = Rd;
947 let Inst{19-16} = Rn;
948 let Inst{27-20} = 0b01101000;
949 let Inst{7-4} = 0b1011;
950 let Inst{11-8} = 0b1111;
953 def SEV : AI<(outs), (ins), MiscFrm, NoItinerary, "sev", "",
954 [/* For disassembly only; pattern left blank */]>,
955 Requires<[IsARM, HasV6T2]> {
956 let Inst{27-16} = 0b001100100000;
957 let Inst{15-8} = 0b11110000;
958 let Inst{7-0} = 0b00000100;
961 // The i32imm operand $val can be used by a debugger to store more information
962 // about the breakpoint.
963 def BKPT : AI<(outs), (ins i32imm:$val), MiscFrm, NoItinerary, "bkpt", "\t$val",
964 [/* For disassembly only; pattern left blank */]>,
967 let Inst{3-0} = val{3-0};
968 let Inst{19-8} = val{15-4};
969 let Inst{27-20} = 0b00010010;
970 let Inst{7-4} = 0b0111;
973 // Change Processor State is a system instruction -- for disassembly only.
974 // The singleton $opt operand contains the following information:
975 // opt{4-0} = mode from Inst{4-0}
976 // opt{5} = changemode from Inst{17}
977 // opt{8-6} = AIF from Inst{8-6}
978 // opt{10-9} = imod from Inst{19-18} with 0b10 as enable and 0b11 as disable
979 // FIXME: Integrated assembler will need these split out.
980 def CPS : AXI<(outs), (ins cps_opt:$opt), MiscFrm, NoItinerary, "cps$opt",
981 [/* For disassembly only; pattern left blank */]>,
983 let Inst{31-28} = 0b1111;
984 let Inst{27-20} = 0b00010000;
989 // Preload signals the memory system of possible future data/instruction access.
990 // These are for disassembly only.
992 // A8.6.117, A8.6.118. Different instructions are generated for #0 and #-0.
993 // The neg_zero operand translates -0 to -1, -1 to -2, ..., etc.
994 multiclass APreLoad<bit data, bit read, string opc> {
996 def i12 : AXI<(outs), (ins addrmode_imm12:$addr), MiscFrm, NoItinerary,
997 !strconcat(opc, "\t$addr"), []> {
1000 let Inst{31-26} = 0b111101;
1001 let Inst{25} = 0; // 0 for immediate form
1002 let Inst{24} = data;
1003 let Inst{23} = addr{12}; // U (add = ('U' == 1))
1004 let Inst{22} = read;
1005 let Inst{21-20} = 0b01;
1006 let Inst{19-16} = addr{16-13}; // Rn
1007 let Inst{15-12} = Rt;
1008 let Inst{11-0} = addr{11-0}; // imm12
1011 def rs : AXI<(outs), (ins ldst_so_reg:$shift), MiscFrm, NoItinerary,
1012 !strconcat(opc, "\t$shift"), []> {
1015 let Inst{31-26} = 0b111101;
1016 let Inst{25} = 1; // 1 for register form
1017 let Inst{24} = data;
1018 let Inst{23} = shift{12}; // U (add = ('U' == 1))
1019 let Inst{22} = read;
1020 let Inst{21-20} = 0b01;
1021 let Inst{19-16} = shift{16-13}; // Rn
1022 let Inst{11-0} = shift{11-0};
1026 defm PLD : APreLoad<1, 1, "pld">;
1027 defm PLDW : APreLoad<1, 0, "pldw">;
1028 defm PLI : APreLoad<0, 1, "pli">;
1030 def SETEND : AXI<(outs),(ins setend_op:$end), MiscFrm, NoItinerary,
1032 [/* For disassembly only; pattern left blank */]>,
1035 let Inst{31-10} = 0b1111000100000001000000;
1040 def DBG : AI<(outs), (ins i32imm:$opt), MiscFrm, NoItinerary, "dbg", "\t$opt",
1041 [/* For disassembly only; pattern left blank */]>,
1042 Requires<[IsARM, HasV7]> {
1044 let Inst{27-4} = 0b001100100000111100001111;
1045 let Inst{3-0} = opt;
1048 // A5.4 Permanently UNDEFINED instructions.
1049 let isBarrier = 1, isTerminator = 1 in
1050 def TRAP : AXI<(outs), (ins), MiscFrm, NoItinerary,
1053 let Inst{27-25} = 0b011;
1054 let Inst{24-20} = 0b11111;
1055 let Inst{7-5} = 0b111;
1059 // Address computation and loads and stores in PIC mode.
1060 // FIXME: These PIC insn patterns are pseudos, but derive from the normal insn
1061 // classes (AXI1, et.al.) and so have encoding information and such,
1062 // which is suboptimal. Once the rest of the code emitter (including
1063 // JIT) is MC-ized we should look at refactoring these into true
1064 // pseudos. As is, the encoding information ends up being ignored,
1065 // as these instructions are lowered to individual MC-insts.
1066 let isNotDuplicable = 1 in {
1067 def PICADD : AXI1<0b0100, (outs GPR:$dst), (ins GPR:$a, pclabel:$cp, pred:$p),
1068 Pseudo, IIC_iALUr, "",
1069 [(set GPR:$dst, (ARMpic_add GPR:$a, imm:$cp))]>;
1071 let AddedComplexity = 10 in {
1072 def PICLDR : AXI2ldw<(outs GPR:$dst), (ins addrmodepc:$addr, pred:$p),
1073 Pseudo, IIC_iLoad_r, "",
1074 [(set GPR:$dst, (load addrmodepc:$addr))]>;
1076 def PICLDRH : AXI3ldh<(outs GPR:$dst), (ins addrmodepc:$addr, pred:$p),
1077 Pseudo, IIC_iLoad_bh_r, "",
1078 [(set GPR:$dst, (zextloadi16 addrmodepc:$addr))]>;
1080 def PICLDRB : AXI2ldb<(outs GPR:$dst), (ins addrmodepc:$addr, pred:$p),
1081 Pseudo, IIC_iLoad_bh_r, "",
1082 [(set GPR:$dst, (zextloadi8 addrmodepc:$addr))]>;
1084 def PICLDRSH : AXI3ldsh<(outs GPR:$dst), (ins addrmodepc:$addr, pred:$p),
1085 Pseudo, IIC_iLoad_bh_r, "",
1086 [(set GPR:$dst, (sextloadi16 addrmodepc:$addr))]>;
1088 def PICLDRSB : AXI3ldsb<(outs GPR:$dst), (ins addrmodepc:$addr, pred:$p),
1089 Pseudo, IIC_iLoad_bh_r, "",
1090 [(set GPR:$dst, (sextloadi8 addrmodepc:$addr))]>;
1092 let AddedComplexity = 10 in {
1093 def PICSTR : AXI2stw<(outs), (ins GPR:$src, addrmodepc:$addr, pred:$p),
1094 Pseudo, IIC_iStore_r, "",
1095 [(store GPR:$src, addrmodepc:$addr)]>;
1097 def PICSTRH : AXI3sth<(outs), (ins GPR:$src, addrmodepc:$addr, pred:$p),
1098 Pseudo, IIC_iStore_bh_r, "",
1099 [(truncstorei16 GPR:$src, addrmodepc:$addr)]>;
1101 def PICSTRB : AXI2stb<(outs), (ins GPR:$src, addrmodepc:$addr, pred:$p),
1102 Pseudo, IIC_iStore_bh_r, "",
1103 [(truncstorei8 GPR:$src, addrmodepc:$addr)]>;
1105 } // isNotDuplicable = 1
1108 // LEApcrel - Load a pc-relative address into a register without offending the
1110 // FIXME: These are marked as pseudos, but they're really not(?). They're just
1111 // the ADR instruction. Is this the right way to handle that? They need
1112 // encoding information regardless.
1113 let neverHasSideEffects = 1 in {
1114 let isReMaterializable = 1 in
1115 def LEApcrel : AXI1<0x0, (outs GPR:$dst), (ins i32imm:$label, pred:$p),
1117 "adr$p\t$dst, #$label", []>;
1119 } // neverHasSideEffects
1120 def LEApcrelJT : AXI1<0x0, (outs GPR:$dst),
1121 (ins i32imm:$label, nohash_imm:$id, pred:$p),
1123 "adr$p\t$dst, #${label}_${id}", []> {
1127 //===----------------------------------------------------------------------===//
1128 // Control Flow Instructions.
1131 let isReturn = 1, isTerminator = 1, isBarrier = 1 in {
1133 def BX_RET : AI<(outs), (ins), BrMiscFrm, IIC_Br,
1134 "bx", "\tlr", [(ARMretflag)]>,
1135 Requires<[IsARM, HasV4T]> {
1136 let Inst{27-0} = 0b0001001011111111111100011110;
1140 def MOVPCLR : AI<(outs), (ins), BrMiscFrm, IIC_Br,
1141 "mov", "\tpc, lr", [(ARMretflag)]>,
1142 Requires<[IsARM, NoV4T]> {
1143 let Inst{27-0} = 0b0001101000001111000000001110;
1147 // Indirect branches
1148 let isBranch = 1, isTerminator = 1, isBarrier = 1, isIndirectBranch = 1 in {
1150 def BRIND : AXI<(outs), (ins GPR:$dst), BrMiscFrm, IIC_Br, "bx\t$dst",
1151 [(brind GPR:$dst)]>,
1152 Requires<[IsARM, HasV4T]> {
1154 let Inst{31-4} = 0b1110000100101111111111110001;
1155 let Inst{3-0} = dst;
1159 def MOVPCRX : AXI<(outs), (ins GPR:$dst), BrMiscFrm, IIC_Br, "mov\tpc, $dst",
1160 [(brind GPR:$dst)]>,
1161 Requires<[IsARM, NoV4T]> {
1163 let Inst{31-4} = 0b1110000110100000111100000000;
1164 let Inst{3-0} = dst;
1168 // FIXME: remove when we have a way to marking a MI with these properties.
1169 // FIXME: Should pc be an implicit operand like PICADD, etc?
1170 let isReturn = 1, isTerminator = 1, isBarrier = 1, mayLoad = 1,
1171 hasExtraDefRegAllocReq = 1, isCodeGenOnly = 1 in
1172 def LDM_RET : AXI4ld<(outs GPR:$wb), (ins GPR:$Rn, ldstm_mode:$mode, pred:$p,
1173 reglist:$dsts, variable_ops),
1174 IndexModeUpd, LdStMulFrm, IIC_iLoad_mBr,
1175 "ldm${mode}${p}\t$Rn!, $dsts",
1178 // On non-Darwin platforms R9 is callee-saved.
1180 Defs = [R0, R1, R2, R3, R12, LR,
1181 D0, D1, D2, D3, D4, D5, D6, D7,
1182 D16, D17, D18, D19, D20, D21, D22, D23,
1183 D24, D25, D26, D27, D28, D29, D30, D31, CPSR, FPSCR] in {
1184 def BL : ABXI<0b1011, (outs), (ins i32imm:$func, variable_ops),
1185 IIC_Br, "bl\t$func",
1186 [(ARMcall tglobaladdr:$func)]>,
1187 Requires<[IsARM, IsNotDarwin]> {
1188 let Inst{31-28} = 0b1110;
1189 // FIXME: Encoding info for $func. Needs fixups bits.
1192 def BL_pred : ABI<0b1011, (outs), (ins i32imm:$func, variable_ops),
1193 IIC_Br, "bl", "\t$func",
1194 [(ARMcall_pred tglobaladdr:$func)]>,
1195 Requires<[IsARM, IsNotDarwin]>;
1198 def BLX : AXI<(outs), (ins GPR:$func, variable_ops), BrMiscFrm,
1199 IIC_Br, "blx\t$func",
1200 [(ARMcall GPR:$func)]>,
1201 Requires<[IsARM, HasV5T, IsNotDarwin]> {
1203 let Inst{27-4} = 0b000100101111111111110011;
1204 let Inst{3-0} = func;
1208 // Note: Restrict $func to the tGPR regclass to prevent it being in LR.
1209 def BX : ABXIx2<(outs), (ins tGPR:$func, variable_ops),
1210 IIC_Br, "mov\tlr, pc\n\tbx\t$func",
1211 [(ARMcall_nolink tGPR:$func)]>,
1212 Requires<[IsARM, HasV4T, IsNotDarwin]> {
1214 let Inst{27-4} = 0b000100101111111111110001;
1215 let Inst{3-0} = func;
1219 def BMOVPCRX : ABXIx2<(outs), (ins tGPR:$func, variable_ops),
1220 IIC_Br, "mov\tlr, pc\n\tmov\tpc, $func",
1221 [(ARMcall_nolink tGPR:$func)]>,
1222 Requires<[IsARM, NoV4T, IsNotDarwin]> {
1224 let Inst{27-4} = 0b000110100000111100000000;
1225 let Inst{3-0} = func;
1229 // On Darwin R9 is call-clobbered.
1231 Defs = [R0, R1, R2, R3, R9, R12, LR,
1232 D0, D1, D2, D3, D4, D5, D6, D7,
1233 D16, D17, D18, D19, D20, D21, D22, D23,
1234 D24, D25, D26, D27, D28, D29, D30, D31, CPSR, FPSCR] in {
1235 def BLr9 : ABXI<0b1011, (outs), (ins i32imm:$func, variable_ops),
1236 IIC_Br, "bl\t$func",
1237 [(ARMcall tglobaladdr:$func)]>, Requires<[IsARM, IsDarwin]> {
1238 let Inst{31-28} = 0b1110;
1239 // FIXME: Encoding info for $func. Needs fixups bits.
1242 def BLr9_pred : ABI<0b1011, (outs), (ins i32imm:$func, variable_ops),
1243 IIC_Br, "bl", "\t$func",
1244 [(ARMcall_pred tglobaladdr:$func)]>,
1245 Requires<[IsARM, IsDarwin]>;
1248 def BLXr9 : AXI<(outs), (ins GPR:$func, variable_ops), BrMiscFrm,
1249 IIC_Br, "blx\t$func",
1250 [(ARMcall GPR:$func)]>, Requires<[IsARM, HasV5T, IsDarwin]> {
1252 let Inst{27-4} = 0b000100101111111111110011;
1253 let Inst{3-0} = func;
1257 // Note: Restrict $func to the tGPR regclass to prevent it being in LR.
1258 def BXr9 : ABXIx2<(outs), (ins tGPR:$func, variable_ops),
1259 IIC_Br, "mov\tlr, pc\n\tbx\t$func",
1260 [(ARMcall_nolink tGPR:$func)]>,
1261 Requires<[IsARM, HasV4T, IsDarwin]> {
1263 let Inst{27-4} = 0b000100101111111111110001;
1264 let Inst{3-0} = func;
1268 def BMOVPCRXr9 : ABXIx2<(outs), (ins tGPR:$func, variable_ops),
1269 IIC_Br, "mov\tlr, pc\n\tmov\tpc, $func",
1270 [(ARMcall_nolink tGPR:$func)]>,
1271 Requires<[IsARM, NoV4T, IsDarwin]> {
1273 let Inst{27-4} = 0b000110100000111100000000;
1274 let Inst{3-0} = func;
1280 // FIXME: These should probably be xformed into the non-TC versions of the
1281 // instructions as part of MC lowering.
1282 let isCall = 1, isTerminator = 1, isReturn = 1, isBarrier = 1 in {
1284 let Defs = [R0, R1, R2, R3, R9, R12,
1285 D0, D1, D2, D3, D4, D5, D6, D7,
1286 D16, D17, D18, D19, D20, D21, D22, D23, D24, D25, D26,
1287 D27, D28, D29, D30, D31, PC],
1289 def TCRETURNdi : AInoP<(outs), (ins i32imm:$dst, variable_ops),
1291 "@TC_RETURN","\t$dst", []>, Requires<[IsDarwin]>;
1293 def TCRETURNri : AInoP<(outs), (ins tcGPR:$dst, variable_ops),
1295 "@TC_RETURN","\t$dst", []>, Requires<[IsDarwin]>;
1297 def TAILJMPd : ABXI<0b1010, (outs), (ins brtarget:$dst, variable_ops),
1298 IIC_Br, "b\t$dst @ TAILCALL",
1299 []>, Requires<[IsDarwin]>;
1301 def TAILJMPdt: ABXI<0b1010, (outs), (ins brtarget:$dst, variable_ops),
1302 IIC_Br, "b.w\t$dst @ TAILCALL",
1303 []>, Requires<[IsDarwin]>;
1305 def TAILJMPr : AXI<(outs), (ins tcGPR:$dst, variable_ops),
1306 BrMiscFrm, IIC_Br, "bx\t$dst @ TAILCALL",
1307 []>, Requires<[IsDarwin]> {
1309 let Inst{31-4} = 0b1110000100101111111111110001;
1310 let Inst{3-0} = dst;
1314 // Non-Darwin versions (the difference is R9).
1315 let Defs = [R0, R1, R2, R3, R12,
1316 D0, D1, D2, D3, D4, D5, D6, D7,
1317 D16, D17, D18, D19, D20, D21, D22, D23, D24, D25, D26,
1318 D27, D28, D29, D30, D31, PC],
1320 def TCRETURNdiND : AInoP<(outs), (ins i32imm:$dst, variable_ops),
1322 "@TC_RETURN","\t$dst", []>, Requires<[IsNotDarwin]>;
1324 def TCRETURNriND : AInoP<(outs), (ins tcGPR:$dst, variable_ops),
1326 "@TC_RETURN","\t$dst", []>, Requires<[IsNotDarwin]>;
1328 def TAILJMPdND : ABXI<0b1010, (outs), (ins brtarget:$dst, variable_ops),
1329 IIC_Br, "b\t$dst @ TAILCALL",
1330 []>, Requires<[IsARM, IsNotDarwin]>;
1332 def TAILJMPdNDt : ABXI<0b1010, (outs), (ins brtarget:$dst, variable_ops),
1333 IIC_Br, "b.w\t$dst @ TAILCALL",
1334 []>, Requires<[IsThumb, IsNotDarwin]>;
1336 def TAILJMPrND : AXI<(outs), (ins tcGPR:$dst, variable_ops),
1337 BrMiscFrm, IIC_Br, "bx\t$dst @ TAILCALL",
1338 []>, Requires<[IsNotDarwin]> {
1340 let Inst{31-4} = 0b1110000100101111111111110001;
1341 let Inst{3-0} = dst;
1346 let isBranch = 1, isTerminator = 1 in {
1347 // B is "predicable" since it can be xformed into a Bcc.
1348 let isBarrier = 1 in {
1349 let isPredicable = 1 in
1350 def B : ABXI<0b1010, (outs), (ins brtarget:$target), IIC_Br,
1351 "b\t$target", [(br bb:$target)]>;
1353 let isNotDuplicable = 1, isIndirectBranch = 1,
1354 // FIXME: $imm field is not specified by asm string. Mark as cgonly.
1355 isCodeGenOnly = 1 in {
1356 def BR_JTr : JTI<(outs), (ins GPR:$target, jtblock_operand:$jt, i32imm:$id),
1357 IIC_Br, "mov\tpc, $target$jt",
1358 [(ARMbrjt GPR:$target, tjumptable:$jt, imm:$id)]> {
1359 let Inst{11-4} = 0b00000000;
1360 let Inst{15-12} = 0b1111;
1361 let Inst{20} = 0; // S Bit
1362 let Inst{24-21} = 0b1101;
1363 let Inst{27-25} = 0b000;
1365 def BR_JTm : JTI<(outs),
1366 (ins addrmode2:$target, jtblock_operand:$jt, i32imm:$id),
1367 IIC_Br, "ldr\tpc, $target$jt",
1368 [(ARMbrjt (i32 (load addrmode2:$target)), tjumptable:$jt,
1370 let Inst{15-12} = 0b1111;
1371 let Inst{20} = 1; // L bit
1372 let Inst{21} = 0; // W bit
1373 let Inst{22} = 0; // B bit
1374 let Inst{24} = 1; // P bit
1375 let Inst{27-25} = 0b011;
1377 def BR_JTadd : JTI<(outs),
1378 (ins GPR:$target, GPR:$idx, jtblock_operand:$jt, i32imm:$id),
1379 IIC_Br, "add\tpc, $target, $idx$jt",
1380 [(ARMbrjt (add GPR:$target, GPR:$idx), tjumptable:$jt,
1382 let Inst{15-12} = 0b1111;
1383 let Inst{20} = 0; // S bit
1384 let Inst{24-21} = 0b0100;
1385 let Inst{27-25} = 0b000;
1387 } // isNotDuplicable = 1, isIndirectBranch = 1
1390 // FIXME: should be able to write a pattern for ARMBrcond, but can't use
1391 // a two-value operand where a dag node expects two operands. :(
1392 def Bcc : ABI<0b1010, (outs), (ins brtarget:$target),
1393 IIC_Br, "b", "\t$target",
1394 [/*(ARMbrcond bb:$target, imm:$cc, CCR:$ccr)*/]>;
1397 // Branch and Exchange Jazelle -- for disassembly only
1398 def BXJ : ABI<0b0001, (outs), (ins GPR:$func), NoItinerary, "bxj", "\t$func",
1399 [/* For disassembly only; pattern left blank */]> {
1400 let Inst{23-20} = 0b0010;
1401 //let Inst{19-8} = 0xfff;
1402 let Inst{7-4} = 0b0010;
1405 // Secure Monitor Call is a system instruction -- for disassembly only
1406 def SMC : ABI<0b0001, (outs), (ins i32imm:$opt), NoItinerary, "smc", "\t$opt",
1407 [/* For disassembly only; pattern left blank */]> {
1409 let Inst{23-4} = 0b01100000000000000111;
1410 let Inst{3-0} = opt;
1413 // Supervisor Call (Software Interrupt) -- for disassembly only
1415 def SVC : ABI<0b1111, (outs), (ins i32imm:$svc), IIC_Br, "svc", "\t$svc",
1416 [/* For disassembly only; pattern left blank */]> {
1418 let Inst{23-0} = svc;
1422 // Store Return State is a system instruction -- for disassembly only
1423 let isCodeGenOnly = 1 in { // FIXME: This should not use submode!
1424 def SRSW : ABXI<{1,0,0,?}, (outs), (ins ldstm_mode:$amode, i32imm:$mode),
1425 NoItinerary, "srs${amode}\tsp!, $mode",
1426 [/* For disassembly only; pattern left blank */]> {
1427 let Inst{31-28} = 0b1111;
1428 let Inst{22-20} = 0b110; // W = 1
1431 def SRS : ABXI<{1,0,0,?}, (outs), (ins ldstm_mode:$amode, i32imm:$mode),
1432 NoItinerary, "srs${amode}\tsp, $mode",
1433 [/* For disassembly only; pattern left blank */]> {
1434 let Inst{31-28} = 0b1111;
1435 let Inst{22-20} = 0b100; // W = 0
1438 // Return From Exception is a system instruction -- for disassembly only
1439 def RFEW : ABXI<{1,0,0,?}, (outs), (ins ldstm_mode:$amode, GPR:$base),
1440 NoItinerary, "rfe${amode}\t$base!",
1441 [/* For disassembly only; pattern left blank */]> {
1442 let Inst{31-28} = 0b1111;
1443 let Inst{22-20} = 0b011; // W = 1
1446 def RFE : ABXI<{1,0,0,?}, (outs), (ins ldstm_mode:$amode, GPR:$base),
1447 NoItinerary, "rfe${amode}\t$base",
1448 [/* For disassembly only; pattern left blank */]> {
1449 let Inst{31-28} = 0b1111;
1450 let Inst{22-20} = 0b001; // W = 0
1452 } // isCodeGenOnly = 1
1454 //===----------------------------------------------------------------------===//
1455 // Load / store Instructions.
1461 defm LDR : AI_ldr1<0, "ldr", IIC_iLoad_r, IIC_iLoad_si,
1462 UnOpFrag<(load node:$Src)>>;
1463 defm LDRB : AI_ldr1<1, "ldrb", IIC_iLoad_bh_r, IIC_iLoad_bh_si,
1464 UnOpFrag<(zextloadi8 node:$Src)>>;
1465 defm STR : AI_str1<0, "str", IIC_iStore_r, IIC_iStore_si,
1466 BinOpFrag<(store node:$LHS, node:$RHS)>>;
1467 defm STRB : AI_str1<1, "strb", IIC_iStore_bh_r, IIC_iStore_bh_si,
1468 BinOpFrag<(truncstorei8 node:$LHS, node:$RHS)>>;
1470 // Special LDR for loads from non-pc-relative constpools.
1471 let canFoldAsLoad = 1, mayLoad = 1, neverHasSideEffects = 1,
1472 isReMaterializable = 1 in
1473 def LDRcp : AIldst1<0b010, 0, 1, (outs GPR:$Rt), (ins addrmode_imm12:$addr),
1474 AddrMode_i12, LdFrm, IIC_iLoad_r, "ldr", "\t$Rt, $addr", []> {
1477 let Inst{23} = addr{12}; // U (add = ('U' == 1))
1478 let Inst{19-16} = 0b1111;
1479 let Inst{15-12} = Rt;
1480 let Inst{11-0} = addr{11-0}; // imm12
1483 // Loads with zero extension
1484 def LDRH : AI3ldh<(outs GPR:$dst), (ins addrmode3:$addr), LdMiscFrm,
1485 IIC_iLoad_bh_r, "ldrh", "\t$dst, $addr",
1486 [(set GPR:$dst, (zextloadi16 addrmode3:$addr))]>;
1488 // Loads with sign extension
1489 def LDRSH : AI3ldsh<(outs GPR:$dst), (ins addrmode3:$addr), LdMiscFrm,
1490 IIC_iLoad_bh_r, "ldrsh", "\t$dst, $addr",
1491 [(set GPR:$dst, (sextloadi16 addrmode3:$addr))]>;
1493 def LDRSB : AI3ldsb<(outs GPR:$dst), (ins addrmode3:$addr), LdMiscFrm,
1494 IIC_iLoad_bh_r, "ldrsb", "\t$dst, $addr",
1495 [(set GPR:$dst, (sextloadi8 addrmode3:$addr))]>;
1497 let mayLoad = 1, neverHasSideEffects = 1, hasExtraDefRegAllocReq = 1,
1498 isCodeGenOnly = 1 in { // $dst2 doesn't exist in asmstring?
1500 def LDRD : AI3ldd<(outs GPR:$dst1, GPR:$dst2), (ins addrmode3:$addr), LdMiscFrm,
1501 IIC_iLoad_d_r, "ldrd", "\t$dst1, $addr",
1502 []>, Requires<[IsARM, HasV5TE]>;
1505 def LDR_PRE : AI2ldwpr<(outs GPR:$dst, GPR:$base_wb),
1506 (ins addrmode2:$addr), LdFrm, IIC_iLoad_ru,
1507 "ldr", "\t$dst, $addr!", "$addr.base = $base_wb", []>;
1509 def LDR_POST : AI2ldwpo<(outs GPR:$dst, GPR:$base_wb),
1510 (ins GPR:$base, am2offset:$offset), LdFrm, IIC_iLoad_ru,
1511 "ldr", "\t$dst, [$base], $offset", "$base = $base_wb", []>;
1513 def LDRH_PRE : AI3ldhpr<(outs GPR:$dst, GPR:$base_wb),
1514 (ins addrmode3:$addr), LdMiscFrm, IIC_iLoad_bh_ru,
1515 "ldrh", "\t$dst, $addr!", "$addr.base = $base_wb", []>;
1517 def LDRH_POST : AI3ldhpo<(outs GPR:$dst, GPR:$base_wb),
1518 (ins GPR:$base,am3offset:$offset), LdMiscFrm, IIC_iLoad_bh_ru,
1519 "ldrh", "\t$dst, [$base], $offset", "$base = $base_wb", []>;
1521 def LDRB_PRE : AI2ldbpr<(outs GPR:$dst, GPR:$base_wb),
1522 (ins addrmode2:$addr), LdFrm, IIC_iLoad_bh_ru,
1523 "ldrb", "\t$dst, $addr!", "$addr.base = $base_wb", []>;
1525 def LDRB_POST : AI2ldbpo<(outs GPR:$dst, GPR:$base_wb),
1526 (ins GPR:$base,am2offset:$offset), LdFrm, IIC_iLoad_bh_ru,
1527 "ldrb", "\t$dst, [$base], $offset", "$base = $base_wb", []>;
1529 def LDRSH_PRE : AI3ldshpr<(outs GPR:$dst, GPR:$base_wb),
1530 (ins addrmode3:$addr), LdMiscFrm, IIC_iLoad_bh_ru,
1531 "ldrsh", "\t$dst, $addr!", "$addr.base = $base_wb", []>;
1533 def LDRSH_POST: AI3ldshpo<(outs GPR:$dst, GPR:$base_wb),
1534 (ins GPR:$base,am3offset:$offset), LdMiscFrm, IIC_iLoad_bh_ru,
1535 "ldrsh", "\t$dst, [$base], $offset", "$base = $base_wb", []>;
1537 def LDRSB_PRE : AI3ldsbpr<(outs GPR:$dst, GPR:$base_wb),
1538 (ins addrmode3:$addr), LdMiscFrm, IIC_iLoad_bh_ru,
1539 "ldrsb", "\t$dst, $addr!", "$addr.base = $base_wb", []>;
1541 def LDRSB_POST: AI3ldsbpo<(outs GPR:$dst, GPR:$base_wb),
1542 (ins GPR:$base,am3offset:$offset), LdMiscFrm, IIC_iLoad_ru,
1543 "ldrsb", "\t$dst, [$base], $offset", "$base = $base_wb", []>;
1545 // For disassembly only
1546 def LDRD_PRE : AI3lddpr<(outs GPR:$dst1, GPR:$dst2, GPR:$base_wb),
1547 (ins addrmode3:$addr), LdMiscFrm, IIC_iLoad_d_ru,
1548 "ldrd", "\t$dst1, $dst2, $addr!", "$addr.base = $base_wb", []>,
1549 Requires<[IsARM, HasV5TE]>;
1551 // For disassembly only
1552 def LDRD_POST : AI3lddpo<(outs GPR:$dst1, GPR:$dst2, GPR:$base_wb),
1553 (ins GPR:$base,am3offset:$offset), LdMiscFrm, IIC_iLoad_d_ru,
1554 "ldrd", "\t$dst1, $dst2, [$base], $offset", "$base = $base_wb", []>,
1555 Requires<[IsARM, HasV5TE]>;
1557 } // mayLoad = 1, neverHasSideEffects = 1, hasExtraDefRegAllocReq = 1
1559 // LDRT, LDRBT, LDRSBT, LDRHT, LDRSHT are for disassembly only.
1561 def LDRT : AI2ldwpo<(outs GPR:$dst, GPR:$base_wb),
1562 (ins GPR:$base, am2offset:$offset), LdFrm, IIC_iLoad_ru,
1563 "ldrt", "\t$dst, [$base], $offset", "$base = $base_wb", []> {
1564 let Inst{21} = 1; // overwrite
1567 def LDRBT : AI2ldbpo<(outs GPR:$dst, GPR:$base_wb),
1568 (ins GPR:$base,am2offset:$offset), LdFrm, IIC_iLoad_bh_ru,
1569 "ldrbt", "\t$dst, [$base], $offset", "$base = $base_wb", []> {
1570 let Inst{21} = 1; // overwrite
1573 def LDRSBT : AI3ldsbpo<(outs GPR:$dst, GPR:$base_wb),
1574 (ins GPR:$base,am3offset:$offset), LdMiscFrm, IIC_iLoad_bh_ru,
1575 "ldrsbt", "\t$dst, [$base], $offset", "$base = $base_wb", []> {
1576 let Inst{21} = 1; // overwrite
1579 def LDRHT : AI3ldhpo<(outs GPR:$dst, GPR:$base_wb),
1580 (ins GPR:$base, am3offset:$offset), LdMiscFrm, IIC_iLoad_bh_ru,
1581 "ldrht", "\t$dst, [$base], $offset", "$base = $base_wb", []> {
1582 let Inst{21} = 1; // overwrite
1585 def LDRSHT : AI3ldshpo<(outs GPR:$dst, GPR:$base_wb),
1586 (ins GPR:$base,am3offset:$offset), LdMiscFrm, IIC_iLoad_bh_ru,
1587 "ldrsht", "\t$dst, [$base], $offset", "$base = $base_wb", []> {
1588 let Inst{21} = 1; // overwrite
1593 // Stores with truncate
1594 def STRH : AI3sth<(outs), (ins GPR:$src, addrmode3:$addr), StMiscFrm,
1595 IIC_iStore_bh_r, "strh", "\t$src, $addr",
1596 [(truncstorei16 GPR:$src, addrmode3:$addr)]>;
1599 let mayStore = 1, neverHasSideEffects = 1, hasExtraSrcRegAllocReq = 1,
1600 isCodeGenOnly = 1 in // $src2 doesn't exist in asm string
1601 def STRD : AI3std<(outs), (ins GPR:$src1, GPR:$src2, addrmode3:$addr),
1602 StMiscFrm, IIC_iStore_d_r,
1603 "strd", "\t$src1, $addr", []>, Requires<[IsARM, HasV5TE]>;
1606 def STR_PRE : AI2stwpr<(outs GPR:$base_wb),
1607 (ins GPR:$src, GPR:$base, am2offset:$offset),
1608 StFrm, IIC_iStore_ru,
1609 "str", "\t$src, [$base, $offset]!", "$base = $base_wb",
1611 (pre_store GPR:$src, GPR:$base, am2offset:$offset))]>;
1613 def STR_POST : AI2stwpo<(outs GPR:$base_wb),
1614 (ins GPR:$src, GPR:$base,am2offset:$offset),
1615 StFrm, IIC_iStore_ru,
1616 "str", "\t$src, [$base], $offset", "$base = $base_wb",
1618 (post_store GPR:$src, GPR:$base, am2offset:$offset))]>;
1620 def STRH_PRE : AI3sthpr<(outs GPR:$base_wb),
1621 (ins GPR:$src, GPR:$base,am3offset:$offset),
1622 StMiscFrm, IIC_iStore_ru,
1623 "strh", "\t$src, [$base, $offset]!", "$base = $base_wb",
1625 (pre_truncsti16 GPR:$src, GPR:$base,am3offset:$offset))]>;
1627 def STRH_POST: AI3sthpo<(outs GPR:$base_wb),
1628 (ins GPR:$src, GPR:$base,am3offset:$offset),
1629 StMiscFrm, IIC_iStore_bh_ru,
1630 "strh", "\t$src, [$base], $offset", "$base = $base_wb",
1631 [(set GPR:$base_wb, (post_truncsti16 GPR:$src,
1632 GPR:$base, am3offset:$offset))]>;
1634 def STRB_PRE : AI2stbpr<(outs GPR:$base_wb),
1635 (ins GPR:$src, GPR:$base,am2offset:$offset),
1636 StFrm, IIC_iStore_bh_ru,
1637 "strb", "\t$src, [$base, $offset]!", "$base = $base_wb",
1638 [(set GPR:$base_wb, (pre_truncsti8 GPR:$src,
1639 GPR:$base, am2offset:$offset))]>;
1641 def STRB_POST: AI2stbpo<(outs GPR:$base_wb),
1642 (ins GPR:$src, GPR:$base,am2offset:$offset),
1643 StFrm, IIC_iStore_bh_ru,
1644 "strb", "\t$src, [$base], $offset", "$base = $base_wb",
1645 [(set GPR:$base_wb, (post_truncsti8 GPR:$src,
1646 GPR:$base, am2offset:$offset))]>;
1648 // For disassembly only
1649 def STRD_PRE : AI3stdpr<(outs GPR:$base_wb),
1650 (ins GPR:$src1, GPR:$src2, GPR:$base, am3offset:$offset),
1651 StMiscFrm, IIC_iStore_d_ru,
1652 "strd", "\t$src1, $src2, [$base, $offset]!",
1653 "$base = $base_wb", []>;
1655 // For disassembly only
1656 def STRD_POST: AI3stdpo<(outs GPR:$base_wb),
1657 (ins GPR:$src1, GPR:$src2, GPR:$base, am3offset:$offset),
1658 StMiscFrm, IIC_iStore_d_ru,
1659 "strd", "\t$src1, $src2, [$base], $offset",
1660 "$base = $base_wb", []>;
1662 // STRT, STRBT, and STRHT are for disassembly only.
1664 def STRT : AI2stwpo<(outs GPR:$base_wb),
1665 (ins GPR:$src, GPR:$base,am2offset:$offset),
1666 StFrm, IIC_iStore_ru,
1667 "strt", "\t$src, [$base], $offset", "$base = $base_wb",
1668 [/* For disassembly only; pattern left blank */]> {
1669 let Inst{21} = 1; // overwrite
1672 def STRBT : AI2stbpo<(outs GPR:$base_wb),
1673 (ins GPR:$src, GPR:$base,am2offset:$offset),
1674 StFrm, IIC_iStore_bh_ru,
1675 "strbt", "\t$src, [$base], $offset", "$base = $base_wb",
1676 [/* For disassembly only; pattern left blank */]> {
1677 let Inst{21} = 1; // overwrite
1680 def STRHT: AI3sthpo<(outs GPR:$base_wb),
1681 (ins GPR:$src, GPR:$base,am3offset:$offset),
1682 StMiscFrm, IIC_iStore_bh_ru,
1683 "strht", "\t$src, [$base], $offset", "$base = $base_wb",
1684 [/* For disassembly only; pattern left blank */]> {
1685 let Inst{21} = 1; // overwrite
1688 //===----------------------------------------------------------------------===//
1689 // Load / store multiple Instructions.
1692 let mayLoad = 1, neverHasSideEffects = 1, hasExtraDefRegAllocReq = 1,
1693 isCodeGenOnly = 1 in {
1694 def LDM : AXI4ld<(outs), (ins GPR:$Rn, ldstm_mode:$amode, pred:$p,
1695 reglist:$dsts, variable_ops),
1696 IndexModeNone, LdStMulFrm, IIC_iLoad_m,
1697 "ldm${amode}${p}\t$Rn, $dsts", "", []>;
1699 def LDM_UPD : AXI4ld<(outs GPR:$wb), (ins GPR:$Rn, ldstm_mode:$amode, pred:$p,
1700 reglist:$dsts, variable_ops),
1701 IndexModeUpd, LdStMulFrm, IIC_iLoad_mu,
1702 "ldm${amode}${p}\t$Rn!, $dsts",
1704 } // mayLoad, neverHasSideEffects, hasExtraDefRegAllocReq
1706 let mayStore = 1, neverHasSideEffects = 1, hasExtraSrcRegAllocReq = 1,
1707 isCodeGenOnly = 1 in {
1708 def STM : AXI4st<(outs), (ins GPR:$Rn, ldstm_mode:$amode, pred:$p,
1709 reglist:$srcs, variable_ops),
1710 IndexModeNone, LdStMulFrm, IIC_iStore_m,
1711 "stm${amode}${p}\t$Rn, $srcs", "", []>;
1713 def STM_UPD : AXI4st<(outs GPR:$wb), (ins GPR:$Rn, ldstm_mode:$amode, pred:$p,
1714 reglist:$srcs, variable_ops),
1715 IndexModeUpd, LdStMulFrm, IIC_iStore_mu,
1716 "stm${amode}${p}\t$Rn!, $srcs",
1718 } // mayStore, neverHasSideEffects, hasExtraSrcRegAllocReq
1720 //===----------------------------------------------------------------------===//
1721 // Move Instructions.
1724 let neverHasSideEffects = 1 in
1725 def MOVr : AsI1<0b1101, (outs GPR:$Rd), (ins GPR:$Rm), DPFrm, IIC_iMOVr,
1726 "mov", "\t$Rd, $Rm", []>, UnaryDP {
1730 let Inst{11-4} = 0b00000000;
1733 let Inst{15-12} = Rd;
1736 // A version for the smaller set of tail call registers.
1737 let neverHasSideEffects = 1 in
1738 def MOVr_TC : AsI1<0b1101, (outs tcGPR:$Rd), (ins tcGPR:$Rm), DPFrm,
1739 IIC_iMOVr, "mov", "\t$Rd, $Rm", []>, UnaryDP {
1743 let Inst{11-4} = 0b00000000;
1746 let Inst{15-12} = Rd;
1749 def MOVs : AsI1<0b1101, (outs GPR:$Rd), (ins shift_so_reg:$src),
1750 DPSoRegFrm, IIC_iMOVsr,
1751 "mov", "\t$Rd, $src", [(set GPR:$Rd, shift_so_reg:$src)]>,
1755 let Inst{15-12} = Rd;
1756 let Inst{11-0} = src;
1760 let isReMaterializable = 1, isAsCheapAsAMove = 1 in
1761 def MOVi : AsI1<0b1101, (outs GPR:$Rd), (ins so_imm:$imm), DPFrm, IIC_iMOVi,
1762 "mov", "\t$Rd, $imm", [(set GPR:$Rd, so_imm:$imm)]>, UnaryDP {
1766 let Inst{15-12} = Rd;
1767 let Inst{19-16} = 0b0000;
1768 let Inst{11-0} = imm;
1771 let isReMaterializable = 1, isAsCheapAsAMove = 1 in
1772 def MOVi16 : AI1<0b1000, (outs GPR:$Rd), (ins i32imm:$imm),
1774 "movw", "\t$Rd, $imm",
1775 [(set GPR:$Rd, imm0_65535:$imm)]>,
1776 Requires<[IsARM, HasV6T2]>, UnaryDP {
1779 let Inst{15-12} = Rd;
1780 let Inst{11-0} = imm{11-0};
1781 let Inst{19-16} = imm{15-12};
1786 let Constraints = "$src = $Rd" in
1787 def MOVTi16 : AI1<0b1010, (outs GPR:$Rd), (ins GPR:$src, i32imm:$imm),
1789 "movt", "\t$Rd, $imm",
1791 (or (and GPR:$src, 0xffff),
1792 lo16AllZero:$imm))]>, UnaryDP,
1793 Requires<[IsARM, HasV6T2]> {
1796 let Inst{15-12} = Rd;
1797 let Inst{11-0} = imm{11-0};
1798 let Inst{19-16} = imm{15-12};
1803 def : ARMPat<(or GPR:$src, 0xffff0000), (MOVTi16 GPR:$src, 0xffff)>,
1804 Requires<[IsARM, HasV6T2]>;
1806 let Uses = [CPSR] in
1807 def RRX: PseudoInst<(outs GPR:$Rd), (ins GPR:$Rm), IIC_iMOVsi, "",
1808 [(set GPR:$Rd, (ARMrrx GPR:$Rm))]>, UnaryDP,
1811 // These aren't really mov instructions, but we have to define them this way
1812 // due to flag operands.
1814 let Defs = [CPSR] in {
1815 def MOVsrl_flag : PseudoInst<(outs GPR:$dst), (ins GPR:$src), IIC_iMOVsi, "",
1816 [(set GPR:$dst, (ARMsrl_flag GPR:$src))]>, UnaryDP,
1818 def MOVsra_flag : PseudoInst<(outs GPR:$dst), (ins GPR:$src), IIC_iMOVsi, "",
1819 [(set GPR:$dst, (ARMsra_flag GPR:$src))]>, UnaryDP,
1823 //===----------------------------------------------------------------------===//
1824 // Extend Instructions.
1829 defm SXTB : AI_ext_rrot<0b01101010,
1830 "sxtb", UnOpFrag<(sext_inreg node:$Src, i8)>>;
1831 defm SXTH : AI_ext_rrot<0b01101011,
1832 "sxth", UnOpFrag<(sext_inreg node:$Src, i16)>>;
1834 defm SXTAB : AI_exta_rrot<0b01101010,
1835 "sxtab", BinOpFrag<(add node:$LHS, (sext_inreg node:$RHS, i8))>>;
1836 defm SXTAH : AI_exta_rrot<0b01101011,
1837 "sxtah", BinOpFrag<(add node:$LHS, (sext_inreg node:$RHS,i16))>>;
1839 // For disassembly only
1840 defm SXTB16 : AI_ext_rrot_np<0b01101000, "sxtb16">;
1842 // For disassembly only
1843 defm SXTAB16 : AI_exta_rrot_np<0b01101000, "sxtab16">;
1847 let AddedComplexity = 16 in {
1848 defm UXTB : AI_ext_rrot<0b01101110,
1849 "uxtb" , UnOpFrag<(and node:$Src, 0x000000FF)>>;
1850 defm UXTH : AI_ext_rrot<0b01101111,
1851 "uxth" , UnOpFrag<(and node:$Src, 0x0000FFFF)>>;
1852 defm UXTB16 : AI_ext_rrot<0b01101100,
1853 "uxtb16", UnOpFrag<(and node:$Src, 0x00FF00FF)>>;
1855 // FIXME: This pattern incorrectly assumes the shl operator is a rotate.
1856 // The transformation should probably be done as a combiner action
1857 // instead so we can include a check for masking back in the upper
1858 // eight bits of the source into the lower eight bits of the result.
1859 //def : ARMV6Pat<(and (shl GPR:$Src, (i32 8)), 0xFF00FF),
1860 // (UXTB16r_rot GPR:$Src, 24)>;
1861 def : ARMV6Pat<(and (srl GPR:$Src, (i32 8)), 0xFF00FF),
1862 (UXTB16r_rot GPR:$Src, 8)>;
1864 defm UXTAB : AI_exta_rrot<0b01101110, "uxtab",
1865 BinOpFrag<(add node:$LHS, (and node:$RHS, 0x00FF))>>;
1866 defm UXTAH : AI_exta_rrot<0b01101111, "uxtah",
1867 BinOpFrag<(add node:$LHS, (and node:$RHS, 0xFFFF))>>;
1870 // This isn't safe in general, the add is two 16-bit units, not a 32-bit add.
1871 // For disassembly only
1872 defm UXTAB16 : AI_exta_rrot_np<0b01101100, "uxtab16">;
1875 def SBFX : I<(outs GPR:$Rd),
1876 (ins GPR:$Rn, imm0_31:$lsb, imm0_31_m1:$width),
1877 AddrMode1, Size4Bytes, IndexModeNone, DPFrm, IIC_iUNAsi,
1878 "sbfx", "\t$Rd, $Rn, $lsb, $width", "", []>,
1879 Requires<[IsARM, HasV6T2]> {
1884 let Inst{27-21} = 0b0111101;
1885 let Inst{6-4} = 0b101;
1886 let Inst{20-16} = width;
1887 let Inst{15-12} = Rd;
1888 let Inst{11-7} = lsb;
1892 def UBFX : I<(outs GPR:$Rd),
1893 (ins GPR:$Rn, imm0_31:$lsb, imm0_31_m1:$width),
1894 AddrMode1, Size4Bytes, IndexModeNone, DPFrm, IIC_iUNAsi,
1895 "ubfx", "\t$Rd, $Rn, $lsb, $width", "", []>,
1896 Requires<[IsARM, HasV6T2]> {
1901 let Inst{27-21} = 0b0111111;
1902 let Inst{6-4} = 0b101;
1903 let Inst{20-16} = width;
1904 let Inst{15-12} = Rd;
1905 let Inst{11-7} = lsb;
1909 //===----------------------------------------------------------------------===//
1910 // Arithmetic Instructions.
1913 defm ADD : AsI1_bin_irs<0b0100, "add",
1914 IIC_iALUi, IIC_iALUr, IIC_iALUsr,
1915 BinOpFrag<(add node:$LHS, node:$RHS)>, 1>;
1916 defm SUB : AsI1_bin_irs<0b0010, "sub",
1917 IIC_iALUi, IIC_iALUr, IIC_iALUsr,
1918 BinOpFrag<(sub node:$LHS, node:$RHS)>>;
1920 // ADD and SUB with 's' bit set.
1921 defm ADDS : AI1_bin_s_irs<0b0100, "adds",
1922 IIC_iALUi, IIC_iALUr, IIC_iALUsr,
1923 BinOpFrag<(addc node:$LHS, node:$RHS)>, 1>;
1924 defm SUBS : AI1_bin_s_irs<0b0010, "subs",
1925 IIC_iALUi, IIC_iALUr, IIC_iALUsr,
1926 BinOpFrag<(subc node:$LHS, node:$RHS)>>;
1928 defm ADC : AI1_adde_sube_irs<0b0101, "adc",
1929 BinOpFrag<(adde_dead_carry node:$LHS, node:$RHS)>, 1>;
1930 defm SBC : AI1_adde_sube_irs<0b0110, "sbc",
1931 BinOpFrag<(sube_dead_carry node:$LHS, node:$RHS)>>;
1932 defm ADCS : AI1_adde_sube_s_irs<0b0101, "adcs",
1933 BinOpFrag<(adde_live_carry node:$LHS, node:$RHS)>, 1>;
1934 defm SBCS : AI1_adde_sube_s_irs<0b0110, "sbcs",
1935 BinOpFrag<(sube_live_carry node:$LHS, node:$RHS) >>;
1937 def RSBri : AsI1<0b0011, (outs GPR:$Rd), (ins GPR:$Rn, so_imm:$imm), DPFrm,
1938 IIC_iALUi, "rsb", "\t$Rd, $Rn, $imm",
1939 [(set GPR:$Rd, (sub so_imm:$imm, GPR:$Rn))]> {
1944 let Inst{15-12} = Rd;
1945 let Inst{19-16} = Rn;
1946 let Inst{11-0} = imm;
1949 // The reg/reg form is only defined for the disassembler; for codegen it is
1950 // equivalent to SUBrr.
1951 def RSBrr : AsI1<0b0011, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm), DPFrm,
1952 IIC_iALUr, "rsb", "\t$Rd, $Rn, $Rm",
1953 [/* For disassembly only; pattern left blank */]> {
1957 let Inst{11-4} = 0b00000000;
1960 let Inst{15-12} = Rd;
1961 let Inst{19-16} = Rn;
1964 def RSBrs : AsI1<0b0011, (outs GPR:$Rd), (ins GPR:$Rn, so_reg:$shift),
1965 DPSoRegFrm, IIC_iALUsr, "rsb", "\t$Rd, $Rn, $shift",
1966 [(set GPR:$Rd, (sub so_reg:$shift, GPR:$Rn))]> {
1971 let Inst{11-0} = shift;
1972 let Inst{15-12} = Rd;
1973 let Inst{19-16} = Rn;
1976 // RSB with 's' bit set.
1977 let Defs = [CPSR] in {
1978 def RSBSri : AI1<0b0011, (outs GPR:$Rd), (ins GPR:$Rn, so_imm:$imm), DPFrm,
1979 IIC_iALUi, "rsbs", "\t$Rd, $Rn, $imm",
1980 [(set GPR:$Rd, (subc so_imm:$imm, GPR:$Rn))]> {
1986 let Inst{15-12} = Rd;
1987 let Inst{19-16} = Rn;
1988 let Inst{11-0} = imm;
1990 def RSBSrs : AI1<0b0011, (outs GPR:$Rd), (ins GPR:$Rn, so_reg:$shift),
1991 DPSoRegFrm, IIC_iALUsr, "rsbs", "\t$Rd, $Rn, $shift",
1992 [(set GPR:$Rd, (subc so_reg:$shift, GPR:$Rn))]> {
1998 let Inst{11-0} = shift;
1999 let Inst{15-12} = Rd;
2000 let Inst{19-16} = Rn;
2004 let Uses = [CPSR] in {
2005 def RSCri : AsI1<0b0111, (outs GPR:$Rd), (ins GPR:$Rn, so_imm:$imm),
2006 DPFrm, IIC_iALUi, "rsc", "\t$Rd, $Rn, $imm",
2007 [(set GPR:$Rd, (sube_dead_carry so_imm:$imm, GPR:$Rn))]>,
2013 let Inst{15-12} = Rd;
2014 let Inst{19-16} = Rn;
2015 let Inst{11-0} = imm;
2017 // The reg/reg form is only defined for the disassembler; for codegen it is
2018 // equivalent to SUBrr.
2019 def RSCrr : AsI1<0b0111, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm),
2020 DPFrm, IIC_iALUr, "rsc", "\t$Rd, $Rn, $Rm",
2021 [/* For disassembly only; pattern left blank */]> {
2025 let Inst{11-4} = 0b00000000;
2028 let Inst{15-12} = Rd;
2029 let Inst{19-16} = Rn;
2031 def RSCrs : AsI1<0b0111, (outs GPR:$Rd), (ins GPR:$Rn, so_reg:$shift),
2032 DPSoRegFrm, IIC_iALUsr, "rsc", "\t$Rd, $Rn, $shift",
2033 [(set GPR:$Rd, (sube_dead_carry so_reg:$shift, GPR:$Rn))]>,
2039 let Inst{11-0} = shift;
2040 let Inst{15-12} = Rd;
2041 let Inst{19-16} = Rn;
2045 // FIXME: Allow these to be predicated.
2046 let Defs = [CPSR], Uses = [CPSR] in {
2047 def RSCSri : AXI1<0b0111, (outs GPR:$Rd), (ins GPR:$Rn, so_imm:$imm),
2048 DPFrm, IIC_iALUi, "rscs\t$Rd, $Rn, $imm",
2049 [(set GPR:$Rd, (sube_dead_carry so_imm:$imm, GPR:$Rn))]>,
2056 let Inst{15-12} = Rd;
2057 let Inst{19-16} = Rn;
2058 let Inst{11-0} = imm;
2060 def RSCSrs : AXI1<0b0111, (outs GPR:$Rd), (ins GPR:$Rn, so_reg:$shift),
2061 DPSoRegFrm, IIC_iALUsr, "rscs\t$Rd, $Rn, $shift",
2062 [(set GPR:$Rd, (sube_dead_carry so_reg:$shift, GPR:$Rn))]>,
2069 let Inst{11-0} = shift;
2070 let Inst{15-12} = Rd;
2071 let Inst{19-16} = Rn;
2075 // (sub X, imm) gets canonicalized to (add X, -imm). Match this form.
2076 // The assume-no-carry-in form uses the negation of the input since add/sub
2077 // assume opposite meanings of the carry flag (i.e., carry == !borrow).
2078 // See the definition of AddWithCarry() in the ARM ARM A2.2.1 for the gory
2080 def : ARMPat<(add GPR:$src, so_imm_neg:$imm),
2081 (SUBri GPR:$src, so_imm_neg:$imm)>;
2082 def : ARMPat<(addc GPR:$src, so_imm_neg:$imm),
2083 (SUBSri GPR:$src, so_imm_neg:$imm)>;
2084 // The with-carry-in form matches bitwise not instead of the negation.
2085 // Effectively, the inverse interpretation of the carry flag already accounts
2086 // for part of the negation.
2087 def : ARMPat<(adde GPR:$src, so_imm_not:$imm),
2088 (SBCri GPR:$src, so_imm_not:$imm)>;
2090 // Note: These are implemented in C++ code, because they have to generate
2091 // ADD/SUBrs instructions, which use a complex pattern that a xform function
2093 // (mul X, 2^n+1) -> (add (X << n), X)
2094 // (mul X, 2^n-1) -> (rsb X, (X << n))
2096 // ARM Arithmetic Instruction -- for disassembly only
2097 // GPR:$dst = GPR:$a op GPR:$b
2098 class AAI<bits<8> op27_20, bits<8> op11_4, string opc,
2099 list<dag> pattern = [/* For disassembly only; pattern left blank */]>
2100 : AI<(outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm), DPFrm, IIC_iALUr,
2101 opc, "\t$Rd, $Rn, $Rm", pattern> {
2105 let Inst{27-20} = op27_20;
2106 let Inst{11-4} = op11_4;
2107 let Inst{19-16} = Rn;
2108 let Inst{15-12} = Rd;
2112 // Saturating add/subtract -- for disassembly only
2114 def QADD : AAI<0b00010000, 0b00000101, "qadd",
2115 [(set GPR:$Rd, (int_arm_qadd GPR:$Rn, GPR:$Rm))]>;
2116 def QSUB : AAI<0b00010010, 0b00000101, "qsub",
2117 [(set GPR:$Rd, (int_arm_qsub GPR:$Rn, GPR:$Rm))]>;
2118 def QDADD : AAI<0b00010100, 0b00000101, "qdadd">;
2119 def QDSUB : AAI<0b00010110, 0b00000101, "qdsub">;
2121 def QADD16 : AAI<0b01100010, 0b11110001, "qadd16">;
2122 def QADD8 : AAI<0b01100010, 0b11111001, "qadd8">;
2123 def QASX : AAI<0b01100010, 0b11110011, "qasx">;
2124 def QSAX : AAI<0b01100010, 0b11110101, "qsax">;
2125 def QSUB16 : AAI<0b01100010, 0b11110111, "qsub16">;
2126 def QSUB8 : AAI<0b01100010, 0b11111111, "qsub8">;
2127 def UQADD16 : AAI<0b01100110, 0b11110001, "uqadd16">;
2128 def UQADD8 : AAI<0b01100110, 0b11111001, "uqadd8">;
2129 def UQASX : AAI<0b01100110, 0b11110011, "uqasx">;
2130 def UQSAX : AAI<0b01100110, 0b11110101, "uqsax">;
2131 def UQSUB16 : AAI<0b01100110, 0b11110111, "uqsub16">;
2132 def UQSUB8 : AAI<0b01100110, 0b11111111, "uqsub8">;
2134 // Signed/Unsigned add/subtract -- for disassembly only
2136 def SASX : AAI<0b01100001, 0b11110011, "sasx">;
2137 def SADD16 : AAI<0b01100001, 0b11110001, "sadd16">;
2138 def SADD8 : AAI<0b01100001, 0b11111001, "sadd8">;
2139 def SSAX : AAI<0b01100001, 0b11110101, "ssax">;
2140 def SSUB16 : AAI<0b01100001, 0b11110111, "ssub16">;
2141 def SSUB8 : AAI<0b01100001, 0b11111111, "ssub8">;
2142 def UASX : AAI<0b01100101, 0b11110011, "uasx">;
2143 def UADD16 : AAI<0b01100101, 0b11110001, "uadd16">;
2144 def UADD8 : AAI<0b01100101, 0b11111001, "uadd8">;
2145 def USAX : AAI<0b01100101, 0b11110101, "usax">;
2146 def USUB16 : AAI<0b01100101, 0b11110111, "usub16">;
2147 def USUB8 : AAI<0b01100101, 0b11111111, "usub8">;
2149 // Signed/Unsigned halving add/subtract -- for disassembly only
2151 def SHASX : AAI<0b01100011, 0b11110011, "shasx">;
2152 def SHADD16 : AAI<0b01100011, 0b11110001, "shadd16">;
2153 def SHADD8 : AAI<0b01100011, 0b11111001, "shadd8">;
2154 def SHSAX : AAI<0b01100011, 0b11110101, "shsax">;
2155 def SHSUB16 : AAI<0b01100011, 0b11110111, "shsub16">;
2156 def SHSUB8 : AAI<0b01100011, 0b11111111, "shsub8">;
2157 def UHASX : AAI<0b01100111, 0b11110011, "uhasx">;
2158 def UHADD16 : AAI<0b01100111, 0b11110001, "uhadd16">;
2159 def UHADD8 : AAI<0b01100111, 0b11111001, "uhadd8">;
2160 def UHSAX : AAI<0b01100111, 0b11110101, "uhsax">;
2161 def UHSUB16 : AAI<0b01100111, 0b11110111, "uhsub16">;
2162 def UHSUB8 : AAI<0b01100111, 0b11111111, "uhsub8">;
2164 // Unsigned Sum of Absolute Differences [and Accumulate] -- for disassembly only
2166 def USAD8 : AI<(outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm),
2167 MulFrm /* for convenience */, NoItinerary, "usad8",
2168 "\t$Rd, $Rn, $Rm", []>,
2169 Requires<[IsARM, HasV6]> {
2173 let Inst{27-20} = 0b01111000;
2174 let Inst{15-12} = 0b1111;
2175 let Inst{7-4} = 0b0001;
2176 let Inst{19-16} = Rd;
2177 let Inst{11-8} = Rm;
2180 def USADA8 : AI<(outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm, GPR:$Ra),
2181 MulFrm /* for convenience */, NoItinerary, "usada8",
2182 "\t$Rd, $Rn, $Rm, $Ra", []>,
2183 Requires<[IsARM, HasV6]> {
2188 let Inst{27-20} = 0b01111000;
2189 let Inst{7-4} = 0b0001;
2190 let Inst{19-16} = Rd;
2191 let Inst{15-12} = Ra;
2192 let Inst{11-8} = Rm;
2196 // Signed/Unsigned saturate -- for disassembly only
2198 def SSAT : AI<(outs GPR:$Rd), (ins i32imm:$sat_imm, GPR:$a, shift_imm:$sh),
2199 SatFrm, NoItinerary, "ssat", "\t$Rd, $sat_imm, $a$sh",
2200 [/* For disassembly only; pattern left blank */]> {
2205 let Inst{27-21} = 0b0110101;
2206 let Inst{5-4} = 0b01;
2207 let Inst{20-16} = sat_imm;
2208 let Inst{15-12} = Rd;
2209 let Inst{11-7} = sh{7-3};
2210 let Inst{6} = sh{0};
2214 def SSAT16 : AI<(outs GPR:$Rd), (ins i32imm:$sat_imm, GPR:$Rn), SatFrm,
2215 NoItinerary, "ssat16", "\t$Rd, $sat_imm, $Rn",
2216 [/* For disassembly only; pattern left blank */]> {
2220 let Inst{27-20} = 0b01101010;
2221 let Inst{11-4} = 0b11110011;
2222 let Inst{15-12} = Rd;
2223 let Inst{19-16} = sat_imm;
2227 def USAT : AI<(outs GPR:$Rd), (ins i32imm:$sat_imm, GPR:$a, shift_imm:$sh),
2228 SatFrm, NoItinerary, "usat", "\t$Rd, $sat_imm, $a$sh",
2229 [/* For disassembly only; pattern left blank */]> {
2234 let Inst{27-21} = 0b0110111;
2235 let Inst{5-4} = 0b01;
2236 let Inst{15-12} = Rd;
2237 let Inst{11-7} = sh{7-3};
2238 let Inst{6} = sh{0};
2239 let Inst{20-16} = sat_imm;
2243 def USAT16 : AI<(outs GPR:$Rd), (ins i32imm:$sat_imm, GPR:$a), SatFrm,
2244 NoItinerary, "usat16", "\t$Rd, $sat_imm, $a",
2245 [/* For disassembly only; pattern left blank */]> {
2249 let Inst{27-20} = 0b01101110;
2250 let Inst{11-4} = 0b11110011;
2251 let Inst{15-12} = Rd;
2252 let Inst{19-16} = sat_imm;
2256 def : ARMV6Pat<(int_arm_ssat GPR:$a, imm:$pos), (SSAT imm:$pos, GPR:$a, 0)>;
2257 def : ARMV6Pat<(int_arm_usat GPR:$a, imm:$pos), (USAT imm:$pos, GPR:$a, 0)>;
2259 //===----------------------------------------------------------------------===//
2260 // Bitwise Instructions.
2263 defm AND : AsI1_bin_irs<0b0000, "and",
2264 IIC_iBITi, IIC_iBITr, IIC_iBITsr,
2265 BinOpFrag<(and node:$LHS, node:$RHS)>, 1>;
2266 defm ORR : AsI1_bin_irs<0b1100, "orr",
2267 IIC_iBITi, IIC_iBITr, IIC_iBITsr,
2268 BinOpFrag<(or node:$LHS, node:$RHS)>, 1>;
2269 defm EOR : AsI1_bin_irs<0b0001, "eor",
2270 IIC_iBITi, IIC_iBITr, IIC_iBITsr,
2271 BinOpFrag<(xor node:$LHS, node:$RHS)>, 1>;
2272 defm BIC : AsI1_bin_irs<0b1110, "bic",
2273 IIC_iBITi, IIC_iBITr, IIC_iBITsr,
2274 BinOpFrag<(and node:$LHS, (not node:$RHS))>>;
2276 def BFC : I<(outs GPR:$Rd), (ins GPR:$src, bf_inv_mask_imm:$imm),
2277 AddrMode1, Size4Bytes, IndexModeNone, DPFrm, IIC_iUNAsi,
2278 "bfc", "\t$Rd, $imm", "$src = $Rd",
2279 [(set GPR:$Rd, (and GPR:$src, bf_inv_mask_imm:$imm))]>,
2280 Requires<[IsARM, HasV6T2]> {
2283 let Inst{27-21} = 0b0111110;
2284 let Inst{6-0} = 0b0011111;
2285 let Inst{15-12} = Rd;
2286 let Inst{11-7} = imm{4-0}; // lsb
2287 let Inst{20-16} = imm{9-5}; // width
2290 // A8.6.18 BFI - Bitfield insert (Encoding A1)
2291 def BFI : I<(outs GPR:$Rd), (ins GPR:$src, GPR:$Rn, bf_inv_mask_imm:$imm),
2292 AddrMode1, Size4Bytes, IndexModeNone, DPFrm, IIC_iUNAsi,
2293 "bfi", "\t$Rd, $Rn, $imm", "$src = $Rd",
2294 [(set GPR:$Rd, (ARMbfi GPR:$src, GPR:$Rn,
2295 bf_inv_mask_imm:$imm))]>,
2296 Requires<[IsARM, HasV6T2]> {
2300 let Inst{27-21} = 0b0111110;
2301 let Inst{6-4} = 0b001; // Rn: Inst{3-0} != 15
2302 let Inst{15-12} = Rd;
2303 let Inst{11-7} = imm{4-0}; // lsb
2304 let Inst{20-16} = imm{9-5}; // width
2308 def MVNr : AsI1<0b1111, (outs GPR:$Rd), (ins GPR:$Rm), DPFrm, IIC_iMVNr,
2309 "mvn", "\t$Rd, $Rm",
2310 [(set GPR:$Rd, (not GPR:$Rm))]>, UnaryDP {
2314 let Inst{19-16} = 0b0000;
2315 let Inst{11-4} = 0b00000000;
2316 let Inst{15-12} = Rd;
2319 def MVNs : AsI1<0b1111, (outs GPR:$Rd), (ins so_reg:$shift), DPSoRegFrm,
2320 IIC_iMVNsr, "mvn", "\t$Rd, $shift",
2321 [(set GPR:$Rd, (not so_reg:$shift))]>, UnaryDP {
2326 let Inst{19-16} = 0b0000;
2327 let Inst{15-12} = Rd;
2328 let Inst{11-0} = shift;
2330 let isReMaterializable = 1, isAsCheapAsAMove = 1 in
2331 def MVNi : AsI1<0b1111, (outs GPR:$Rd), (ins so_imm:$imm), DPFrm,
2332 IIC_iMVNi, "mvn", "\t$Rd, $imm",
2333 [(set GPR:$Rd, so_imm_not:$imm)]>,UnaryDP {
2338 let Inst{19-16} = 0b0000;
2339 let Inst{15-12} = Rd;
2340 let Inst{11-0} = imm;
2343 def : ARMPat<(and GPR:$src, so_imm_not:$imm),
2344 (BICri GPR:$src, so_imm_not:$imm)>;
2346 //===----------------------------------------------------------------------===//
2347 // Multiply Instructions.
2349 class AsMul1I32<bits<7> opcod, dag oops, dag iops, InstrItinClass itin,
2350 string opc, string asm, list<dag> pattern>
2351 : AsMul1I<opcod, oops, iops, itin, opc, asm, pattern> {
2355 let Inst{19-16} = Rd;
2356 let Inst{11-8} = Rm;
2359 class AsMul1I64<bits<7> opcod, dag oops, dag iops, InstrItinClass itin,
2360 string opc, string asm, list<dag> pattern>
2361 : AsMul1I<opcod, oops, iops, itin, opc, asm, pattern> {
2366 let Inst{19-16} = RdHi;
2367 let Inst{15-12} = RdLo;
2368 let Inst{11-8} = Rm;
2372 let isCommutable = 1 in
2373 def MUL : AsMul1I32<0b0000000, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm),
2374 IIC_iMUL32, "mul", "\t$Rd, $Rn, $Rm",
2375 [(set GPR:$Rd, (mul GPR:$Rn, GPR:$Rm))]>;
2377 def MLA : AsMul1I32<0b0000001, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm, GPR:$Ra),
2378 IIC_iMAC32, "mla", "\t$Rd, $Rn, $Rm, $Ra",
2379 [(set GPR:$Rd, (add (mul GPR:$Rn, GPR:$Rm), GPR:$Ra))]> {
2381 let Inst{15-12} = Ra;
2384 def MLS : AMul1I<0b0000011, (outs GPR:$dst), (ins GPR:$a, GPR:$b, GPR:$c),
2385 IIC_iMAC32, "mls", "\t$dst, $a, $b, $c",
2386 [(set GPR:$dst, (sub GPR:$c, (mul GPR:$a, GPR:$b)))]>,
2387 Requires<[IsARM, HasV6T2]> {
2391 let Inst{19-16} = Rd;
2392 let Inst{11-8} = Rm;
2396 // Extra precision multiplies with low / high results
2398 let neverHasSideEffects = 1 in {
2399 let isCommutable = 1 in {
2400 def SMULL : AsMul1I64<0b0000110, (outs GPR:$RdLo, GPR:$RdHi),
2401 (ins GPR:$Rn, GPR:$Rm), IIC_iMUL64,
2402 "smull", "\t$RdLo, $RdHi, $Rn, $Rm", []>;
2404 def UMULL : AsMul1I64<0b0000100, (outs GPR:$RdLo, GPR:$RdHi),
2405 (ins GPR:$Rn, GPR:$Rm), IIC_iMUL64,
2406 "umull", "\t$RdLo, $RdHi, $Rn, $Rm", []>;
2409 // Multiply + accumulate
2410 def SMLAL : AsMul1I64<0b0000111, (outs GPR:$RdLo, GPR:$RdHi),
2411 (ins GPR:$Rn, GPR:$Rm), IIC_iMAC64,
2412 "smlal", "\t$RdLo, $RdHi, $Rn, $Rm", []>;
2414 def UMLAL : AsMul1I64<0b0000101, (outs GPR:$RdLo, GPR:$RdHi),
2415 (ins GPR:$Rn, GPR:$Rm), IIC_iMAC64,
2416 "umlal", "\t$RdLo, $RdHi, $Rn, $Rm", []>;
2418 def UMAAL : AMul1I <0b0000010, (outs GPR:$RdLo, GPR:$RdHi),
2419 (ins GPR:$Rn, GPR:$Rm), IIC_iMAC64,
2420 "umaal", "\t$RdLo, $RdHi, $Rn, $Rm", []>,
2421 Requires<[IsARM, HasV6]> {
2426 let Inst{19-16} = RdLo;
2427 let Inst{15-12} = RdHi;
2428 let Inst{11-8} = Rm;
2431 } // neverHasSideEffects
2433 // Most significant word multiply
2434 def SMMUL : AMul2I <0b0111010, 0b0001, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm),
2435 IIC_iMUL32, "smmul", "\t$Rd, $Rn, $Rm",
2436 [(set GPR:$Rd, (mulhs GPR:$Rn, GPR:$Rm))]>,
2437 Requires<[IsARM, HasV6]> {
2438 let Inst{15-12} = 0b1111;
2441 def SMMULR : AMul2I <0b0111010, 0b0011, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm),
2442 IIC_iMUL32, "smmulr", "\t$Rd, $Rn, $Rm",
2443 [/* For disassembly only; pattern left blank */]>,
2444 Requires<[IsARM, HasV6]> {
2445 let Inst{15-12} = 0b1111;
2448 def SMMLA : AMul2Ia <0b0111010, 0b0001, (outs GPR:$Rd),
2449 (ins GPR:$Rn, GPR:$Rm, GPR:$Ra),
2450 IIC_iMAC32, "smmla", "\t$Rd, $Rn, $Rm, $Ra",
2451 [(set GPR:$Rd, (add (mulhs GPR:$Rn, GPR:$Rm), GPR:$Ra))]>,
2452 Requires<[IsARM, HasV6]>;
2454 def SMMLAR : AMul2Ia <0b0111010, 0b0011, (outs GPR:$Rd),
2455 (ins GPR:$Rn, GPR:$Rm, GPR:$Ra),
2456 IIC_iMAC32, "smmlar", "\t$Rd, $Rn, $Rm, $Ra",
2457 [/* For disassembly only; pattern left blank */]>,
2458 Requires<[IsARM, HasV6]>;
2460 def SMMLS : AMul2Ia <0b0111010, 0b1101, (outs GPR:$Rd),
2461 (ins GPR:$Rn, GPR:$Rm, GPR:$Ra),
2462 IIC_iMAC32, "smmls", "\t$Rd, $Rn, $Rm, $Ra",
2463 [(set GPR:$Rd, (sub GPR:$Ra, (mulhs GPR:$Rn, GPR:$Rm)))]>,
2464 Requires<[IsARM, HasV6]>;
2466 def SMMLSR : AMul2Ia <0b0111010, 0b1111, (outs GPR:$Rd),
2467 (ins GPR:$Rn, GPR:$Rm, GPR:$Ra),
2468 IIC_iMAC32, "smmlsr", "\t$Rd, $Rn, $Rm, $Ra",
2469 [/* For disassembly only; pattern left blank */]>,
2470 Requires<[IsARM, HasV6]>;
2472 multiclass AI_smul<string opc, PatFrag opnode> {
2473 def BB : AMulxyI<0b0001011, 0b00, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm),
2474 IIC_iMUL16, !strconcat(opc, "bb"), "\t$Rd, $Rn, $Rm",
2475 [(set GPR:$Rd, (opnode (sext_inreg GPR:$Rn, i16),
2476 (sext_inreg GPR:$Rm, i16)))]>,
2477 Requires<[IsARM, HasV5TE]>;
2479 def BT : AMulxyI<0b0001011, 0b10, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm),
2480 IIC_iMUL16, !strconcat(opc, "bt"), "\t$Rd, $Rn, $Rm",
2481 [(set GPR:$Rd, (opnode (sext_inreg GPR:$Rn, i16),
2482 (sra GPR:$Rm, (i32 16))))]>,
2483 Requires<[IsARM, HasV5TE]>;
2485 def TB : AMulxyI<0b0001011, 0b01, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm),
2486 IIC_iMUL16, !strconcat(opc, "tb"), "\t$Rd, $Rn, $Rm",
2487 [(set GPR:$Rd, (opnode (sra GPR:$Rn, (i32 16)),
2488 (sext_inreg GPR:$Rm, i16)))]>,
2489 Requires<[IsARM, HasV5TE]>;
2491 def TT : AMulxyI<0b0001011, 0b11, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm),
2492 IIC_iMUL16, !strconcat(opc, "tt"), "\t$Rd, $Rn, $Rm",
2493 [(set GPR:$Rd, (opnode (sra GPR:$Rn, (i32 16)),
2494 (sra GPR:$Rm, (i32 16))))]>,
2495 Requires<[IsARM, HasV5TE]>;
2497 def WB : AMulxyI<0b0001001, 0b01, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm),
2498 IIC_iMUL16, !strconcat(opc, "wb"), "\t$Rd, $Rn, $Rm",
2499 [(set GPR:$Rd, (sra (opnode GPR:$Rn,
2500 (sext_inreg GPR:$Rm, i16)), (i32 16)))]>,
2501 Requires<[IsARM, HasV5TE]>;
2503 def WT : AMulxyI<0b0001001, 0b11, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm),
2504 IIC_iMUL16, !strconcat(opc, "wt"), "\t$Rd, $Rn, $Rm",
2505 [(set GPR:$Rd, (sra (opnode GPR:$Rn,
2506 (sra GPR:$Rm, (i32 16))), (i32 16)))]>,
2507 Requires<[IsARM, HasV5TE]>;
2511 multiclass AI_smla<string opc, PatFrag opnode> {
2512 def BB : AMulxyI<0b0001000, 0b00, (outs GPR:$Rd),
2513 (ins GPR:$Rn, GPR:$Rm, GPR:$Ra),
2514 IIC_iMAC16, !strconcat(opc, "bb"), "\t$Rd, $Rn, $Rm, $Ra",
2515 [(set GPR:$Rd, (add GPR:$Ra,
2516 (opnode (sext_inreg GPR:$Rn, i16),
2517 (sext_inreg GPR:$Rm, i16))))]>,
2518 Requires<[IsARM, HasV5TE]>;
2520 def BT : AMulxyI<0b0001000, 0b10, (outs GPR:$Rd),
2521 (ins GPR:$Rn, GPR:$Rm, GPR:$Ra),
2522 IIC_iMAC16, !strconcat(opc, "bt"), "\t$Rd, $Rn, $Rm, $Ra",
2523 [(set GPR:$Rd, (add GPR:$Ra, (opnode (sext_inreg GPR:$Rn, i16),
2524 (sra GPR:$Rm, (i32 16)))))]>,
2525 Requires<[IsARM, HasV5TE]>;
2527 def TB : AMulxyI<0b0001000, 0b01, (outs GPR:$Rd),
2528 (ins GPR:$Rn, GPR:$Rm, GPR:$Ra),
2529 IIC_iMAC16, !strconcat(opc, "tb"), "\t$Rd, $Rn, $Rm, $Ra",
2530 [(set GPR:$Rd, (add GPR:$Ra, (opnode (sra GPR:$Rn, (i32 16)),
2531 (sext_inreg GPR:$Rm, i16))))]>,
2532 Requires<[IsARM, HasV5TE]>;
2534 def TT : AMulxyI<0b0001000, 0b11, (outs GPR:$Rd),
2535 (ins GPR:$Rn, GPR:$Rm, GPR:$Ra),
2536 IIC_iMAC16, !strconcat(opc, "tt"), "\t$Rd, $Rn, $Rm, $Ra",
2537 [(set GPR:$Rd, (add GPR:$Ra, (opnode (sra GPR:$Rn, (i32 16)),
2538 (sra GPR:$Rm, (i32 16)))))]>,
2539 Requires<[IsARM, HasV5TE]>;
2541 def WB : AMulxyI<0b0001001, 0b00, (outs GPR:$Rd),
2542 (ins GPR:$Rn, GPR:$Rm, GPR:$Ra),
2543 IIC_iMAC16, !strconcat(opc, "wb"), "\t$Rd, $Rn, $Rm, $Ra",
2544 [(set GPR:$Rd, (add GPR:$Ra, (sra (opnode GPR:$Rn,
2545 (sext_inreg GPR:$Rm, i16)), (i32 16))))]>,
2546 Requires<[IsARM, HasV5TE]>;
2548 def WT : AMulxyI<0b0001001, 0b10, (outs GPR:$Rd),
2549 (ins GPR:$Rn, GPR:$Rm, GPR:$Ra),
2550 IIC_iMAC16, !strconcat(opc, "wt"), "\t$Rd, $Rn, $Rm, $Ra",
2551 [(set GPR:$Rd, (add GPR:$Ra, (sra (opnode GPR:$Rn,
2552 (sra GPR:$Rm, (i32 16))), (i32 16))))]>,
2553 Requires<[IsARM, HasV5TE]>;
2556 defm SMUL : AI_smul<"smul", BinOpFrag<(mul node:$LHS, node:$RHS)>>;
2557 defm SMLA : AI_smla<"smla", BinOpFrag<(mul node:$LHS, node:$RHS)>>;
2559 // Halfword multiply accumulate long: SMLAL<x><y> -- for disassembly only
2560 def SMLALBB : AMulxyI64<0b0001010, 0b00, (outs GPR:$RdLo, GPR:$RdHi),
2561 (ins GPR:$Rn, GPR:$Rm),
2562 IIC_iMAC64, "smlalbb", "\t$RdLo, $RdHi, $Rn, $Rm",
2563 [/* For disassembly only; pattern left blank */]>,
2564 Requires<[IsARM, HasV5TE]>;
2566 def SMLALBT : AMulxyI64<0b0001010, 0b10, (outs GPR:$RdLo, GPR:$RdHi),
2567 (ins GPR:$Rn, GPR:$Rm),
2568 IIC_iMAC64, "smlalbt", "\t$RdLo, $RdHi, $Rn, $Rm",
2569 [/* For disassembly only; pattern left blank */]>,
2570 Requires<[IsARM, HasV5TE]>;
2572 def SMLALTB : AMulxyI64<0b0001010, 0b01, (outs GPR:$RdLo, GPR:$RdHi),
2573 (ins GPR:$Rn, GPR:$Rm),
2574 IIC_iMAC64, "smlaltb", "\t$RdLo, $RdHi, $Rn, $Rm",
2575 [/* For disassembly only; pattern left blank */]>,
2576 Requires<[IsARM, HasV5TE]>;
2578 def SMLALTT : AMulxyI64<0b0001010, 0b11, (outs GPR:$RdLo, GPR:$RdHi),
2579 (ins GPR:$Rn, GPR:$Rm),
2580 IIC_iMAC64, "smlaltt", "\t$RdLo, $RdHi, $Rn, $Rm",
2581 [/* For disassembly only; pattern left blank */]>,
2582 Requires<[IsARM, HasV5TE]>;
2584 // Helper class for AI_smld -- for disassembly only
2585 class AMulDualIbase<bit long, bit sub, bit swap, dag oops, dag iops,
2586 InstrItinClass itin, string opc, string asm>
2587 : AI<oops, iops, MulFrm, itin, opc, asm, []>, Requires<[IsARM, HasV6]> {
2594 let Inst{21-20} = 0b00;
2595 let Inst{22} = long;
2596 let Inst{27-23} = 0b01110;
2597 let Inst{11-8} = Rm;
2600 class AMulDualI<bit long, bit sub, bit swap, dag oops, dag iops,
2601 InstrItinClass itin, string opc, string asm>
2602 : AMulDualIbase<long, sub, swap, oops, iops, itin, opc, asm> {
2604 let Inst{15-12} = 0b1111;
2605 let Inst{19-16} = Rd;
2607 class AMulDualIa<bit long, bit sub, bit swap, dag oops, dag iops,
2608 InstrItinClass itin, string opc, string asm>
2609 : AMulDualIbase<long, sub, swap, oops, iops, itin, opc, asm> {
2611 let Inst{15-12} = Ra;
2613 class AMulDualI64<bit long, bit sub, bit swap, dag oops, dag iops,
2614 InstrItinClass itin, string opc, string asm>
2615 : AMulDualIbase<long, sub, swap, oops, iops, itin, opc, asm> {
2618 let Inst{19-16} = RdHi;
2619 let Inst{15-12} = RdLo;
2622 multiclass AI_smld<bit sub, string opc> {
2624 def D : AMulDualIa<0, sub, 0, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm, GPR:$Ra),
2625 NoItinerary, !strconcat(opc, "d"), "\t$Rd, $Rn, $Rm, $Ra">;
2627 def DX: AMulDualIa<0, sub, 1, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm, GPR:$Ra),
2628 NoItinerary, !strconcat(opc, "dx"), "\t$Rd, $Rn, $Rm, $Ra">;
2630 def LD: AMulDualI64<1, sub, 0, (outs GPR:$RdLo,GPR:$RdHi),
2631 (ins GPR:$Rn, GPR:$Rm), NoItinerary,
2632 !strconcat(opc, "ld"), "\t$RdLo, $RdHi, $Rn, $Rm">;
2634 def LDX : AMulDualI64<1, sub, 1, (outs GPR:$RdLo,GPR:$RdHi),
2635 (ins GPR:$Rn, GPR:$Rm), NoItinerary,
2636 !strconcat(opc, "ldx"),"\t$RdLo, $RdHi, $Rn, $Rm">;
2640 defm SMLA : AI_smld<0, "smla">;
2641 defm SMLS : AI_smld<1, "smls">;
2643 multiclass AI_sdml<bit sub, string opc> {
2645 def D : AMulDualI<0, sub, 0, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm),
2646 NoItinerary, !strconcat(opc, "d"), "\t$Rd, $Rn, $Rm">;
2647 def DX : AMulDualI<0, sub, 1, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm),
2648 NoItinerary, !strconcat(opc, "dx"), "\t$Rd, $Rn, $Rm">;
2651 defm SMUA : AI_sdml<0, "smua">;
2652 defm SMUS : AI_sdml<1, "smus">;
2654 //===----------------------------------------------------------------------===//
2655 // Misc. Arithmetic Instructions.
2658 def CLZ : AMiscA1I<0b000010110, 0b0001, (outs GPR:$Rd), (ins GPR:$Rm),
2659 IIC_iUNAr, "clz", "\t$Rd, $Rm",
2660 [(set GPR:$Rd, (ctlz GPR:$Rm))]>, Requires<[IsARM, HasV5T]>;
2662 def RBIT : AMiscA1I<0b01101111, 0b0011, (outs GPR:$Rd), (ins GPR:$Rm),
2663 IIC_iUNAr, "rbit", "\t$Rd, $Rm",
2664 [(set GPR:$Rd, (ARMrbit GPR:$Rm))]>,
2665 Requires<[IsARM, HasV6T2]>;
2667 def REV : AMiscA1I<0b01101011, 0b0011, (outs GPR:$Rd), (ins GPR:$Rm),
2668 IIC_iUNAr, "rev", "\t$Rd, $Rm",
2669 [(set GPR:$Rd, (bswap GPR:$Rm))]>, Requires<[IsARM, HasV6]>;
2671 def REV16 : AMiscA1I<0b01101011, 0b1011, (outs GPR:$Rd), (ins GPR:$Rm),
2672 IIC_iUNAr, "rev16", "\t$Rd, $Rm",
2674 (or (and (srl GPR:$Rm, (i32 8)), 0xFF),
2675 (or (and (shl GPR:$Rm, (i32 8)), 0xFF00),
2676 (or (and (srl GPR:$Rm, (i32 8)), 0xFF0000),
2677 (and (shl GPR:$Rm, (i32 8)), 0xFF000000)))))]>,
2678 Requires<[IsARM, HasV6]>;
2680 def REVSH : AMiscA1I<0b01101111, 0b1011, (outs GPR:$Rd), (ins GPR:$Rm),
2681 IIC_iUNAr, "revsh", "\t$Rd, $Rm",
2684 (or (srl (and GPR:$Rm, 0xFF00), (i32 8)),
2685 (shl GPR:$Rm, (i32 8))), i16))]>,
2686 Requires<[IsARM, HasV6]>;
2688 def lsl_shift_imm : SDNodeXForm<imm, [{
2689 unsigned Sh = ARM_AM::getSORegOpc(ARM_AM::lsl, N->getZExtValue());
2690 return CurDAG->getTargetConstant(Sh, MVT::i32);
2693 def lsl_amt : PatLeaf<(i32 imm), [{
2694 return (N->getZExtValue() < 32);
2697 def PKHBT : APKHI<0b01101000, 0, (outs GPR:$Rd),
2698 (ins GPR:$Rn, GPR:$Rm, shift_imm:$sh),
2699 IIC_iALUsi, "pkhbt", "\t$Rd, $Rn, $Rm$sh",
2700 [(set GPR:$Rd, (or (and GPR:$Rn, 0xFFFF),
2701 (and (shl GPR:$Rm, lsl_amt:$sh),
2703 Requires<[IsARM, HasV6]>;
2705 // Alternate cases for PKHBT where identities eliminate some nodes.
2706 def : ARMV6Pat<(or (and GPR:$Rn, 0xFFFF), (and GPR:$Rm, 0xFFFF0000)),
2707 (PKHBT GPR:$Rn, GPR:$Rm, 0)>;
2708 def : ARMV6Pat<(or (and GPR:$Rn, 0xFFFF), (shl GPR:$Rm, imm16_31:$sh)),
2709 (PKHBT GPR:$Rn, GPR:$Rm, (lsl_shift_imm imm16_31:$sh))>;
2711 def asr_shift_imm : SDNodeXForm<imm, [{
2712 unsigned Sh = ARM_AM::getSORegOpc(ARM_AM::asr, N->getZExtValue());
2713 return CurDAG->getTargetConstant(Sh, MVT::i32);
2716 def asr_amt : PatLeaf<(i32 imm), [{
2717 return (N->getZExtValue() <= 32);
2720 // Note: Shifts of 1-15 bits will be transformed to srl instead of sra and
2721 // will match the pattern below.
2722 def PKHTB : APKHI<0b01101000, 1, (outs GPR:$Rd),
2723 (ins GPR:$Rn, GPR:$Rm, shift_imm:$sh),
2724 IIC_iBITsi, "pkhtb", "\t$Rd, $Rn, $Rm$sh",
2725 [(set GPR:$Rd, (or (and GPR:$Rn, 0xFFFF0000),
2726 (and (sra GPR:$Rm, asr_amt:$sh),
2728 Requires<[IsARM, HasV6]>;
2730 // Alternate cases for PKHTB where identities eliminate some nodes. Note that
2731 // a shift amount of 0 is *not legal* here, it is PKHBT instead.
2732 def : ARMV6Pat<(or (and GPR:$src1, 0xFFFF0000), (srl GPR:$src2, imm16_31:$sh)),
2733 (PKHTB GPR:$src1, GPR:$src2, (asr_shift_imm imm16_31:$sh))>;
2734 def : ARMV6Pat<(or (and GPR:$src1, 0xFFFF0000),
2735 (and (srl GPR:$src2, imm1_15:$sh), 0xFFFF)),
2736 (PKHTB GPR:$src1, GPR:$src2, (asr_shift_imm imm1_15:$sh))>;
2738 //===----------------------------------------------------------------------===//
2739 // Comparison Instructions...
2742 defm CMP : AI1_cmp_irs<0b1010, "cmp",
2743 IIC_iCMPi, IIC_iCMPr, IIC_iCMPsr,
2744 BinOpFrag<(ARMcmp node:$LHS, node:$RHS)>>;
2746 // FIXME: We have to be careful when using the CMN instruction and comparison
2747 // with 0. One would expect these two pieces of code should give identical
2763 // However, the CMN gives the *opposite* result when r1 is 0. This is because
2764 // the carry flag is set in the CMP case but not in the CMN case. In short, the
2765 // CMP instruction doesn't perform a truncate of the (logical) NOT of 0 plus the
2766 // value of r0 and the carry bit (because the "carry bit" parameter to
2767 // AddWithCarry is defined as 1 in this case, the carry flag will always be set
2768 // when r0 >= 0). The CMN instruction doesn't perform a NOT of 0 so there is
2769 // never a "carry" when this AddWithCarry is performed (because the "carry bit"
2770 // parameter to AddWithCarry is defined as 0).
2772 // When x is 0 and unsigned:
2776 // ~x + 1 = 0x1 0000 0000
2777 // (-x = 0) != (0x1 0000 0000 = ~x + 1)
2779 // Therefore, we should disable CMN when comparing against zero, until we can
2780 // limit when the CMN instruction is used (when we know that the RHS is not 0 or
2781 // when it's a comparison which doesn't look at the 'carry' flag).
2783 // (See the ARM docs for the "AddWithCarry" pseudo-code.)
2785 // This is related to <rdar://problem/7569620>.
2787 //defm CMN : AI1_cmp_irs<0b1011, "cmn",
2788 // BinOpFrag<(ARMcmp node:$LHS,(ineg node:$RHS))>>;
2790 // Note that TST/TEQ don't set all the same flags that CMP does!
2791 defm TST : AI1_cmp_irs<0b1000, "tst",
2792 IIC_iTSTi, IIC_iTSTr, IIC_iTSTsr,
2793 BinOpFrag<(ARMcmpZ (and node:$LHS, node:$RHS), 0)>, 1>;
2794 defm TEQ : AI1_cmp_irs<0b1001, "teq",
2795 IIC_iTSTi, IIC_iTSTr, IIC_iTSTsr,
2796 BinOpFrag<(ARMcmpZ (xor node:$LHS, node:$RHS), 0)>, 1>;
2798 defm CMPz : AI1_cmp_irs<0b1010, "cmp",
2799 IIC_iCMPi, IIC_iCMPr, IIC_iCMPsr,
2800 BinOpFrag<(ARMcmpZ node:$LHS, node:$RHS)>>;
2801 defm CMNz : AI1_cmp_irs<0b1011, "cmn",
2802 IIC_iCMPi, IIC_iCMPr, IIC_iCMPsr,
2803 BinOpFrag<(ARMcmpZ node:$LHS,(ineg node:$RHS))>>;
2805 //def : ARMPat<(ARMcmp GPR:$src, so_imm_neg:$imm),
2806 // (CMNri GPR:$src, so_imm_neg:$imm)>;
2808 def : ARMPat<(ARMcmpZ GPR:$src, so_imm_neg:$imm),
2809 (CMNzri GPR:$src, so_imm_neg:$imm)>;
2811 // Pseudo i64 compares for some floating point compares.
2812 let usesCustomInserter = 1, isBranch = 1, isTerminator = 1,
2814 def BCCi64 : PseudoInst<(outs),
2815 (ins i32imm:$cc, GPR:$lhs1, GPR:$lhs2, GPR:$rhs1, GPR:$rhs2, brtarget:$dst),
2817 [(ARMBcci64 imm:$cc, GPR:$lhs1, GPR:$lhs2, GPR:$rhs1, GPR:$rhs2, bb:$dst)]>;
2819 def BCCZi64 : PseudoInst<(outs),
2820 (ins i32imm:$cc, GPR:$lhs1, GPR:$lhs2, brtarget:$dst), IIC_Br, "",
2821 [(ARMBcci64 imm:$cc, GPR:$lhs1, GPR:$lhs2, 0, 0, bb:$dst)]>;
2822 } // usesCustomInserter
2825 // Conditional moves
2826 // FIXME: should be able to write a pattern for ARMcmov, but can't use
2827 // a two-value operand where a dag node expects two operands. :(
2828 // FIXME: These should all be pseudo-instructions that get expanded to
2829 // the normal MOV instructions. That would fix the dependency on
2830 // special casing them in tblgen.
2831 let neverHasSideEffects = 1 in {
2832 def MOVCCr : AI1<0b1101, (outs GPR:$Rd), (ins GPR:$false, GPR:$Rm), DPFrm,
2833 IIC_iCMOVr, "mov", "\t$Rd, $Rm",
2834 [/*(set GPR:$Rd, (ARMcmov GPR:$false, GPR:$Rm, imm:$cc, CCR:$ccr))*/]>,
2835 RegConstraint<"$false = $Rd">, UnaryDP {
2840 let Inst{15-12} = Rd;
2841 let Inst{11-4} = 0b00000000;
2845 def MOVCCs : AI1<0b1101, (outs GPR:$Rd),
2846 (ins GPR:$false, so_reg:$shift), DPSoRegFrm, IIC_iCMOVsr,
2847 "mov", "\t$Rd, $shift",
2848 [/*(set GPR:$Rd, (ARMcmov GPR:$false, so_reg:$shift, imm:$cc, CCR:$ccr))*/]>,
2849 RegConstraint<"$false = $Rd">, UnaryDP {
2855 let Inst{19-16} = Rn;
2856 let Inst{15-12} = Rd;
2857 let Inst{11-0} = shift;
2860 def MOVCCi16 : AI1<0b1000, (outs GPR:$Rd), (ins GPR:$false, i32imm:$imm),
2862 "movw", "\t$Rd, $imm",
2864 RegConstraint<"$false = $Rd">, Requires<[IsARM, HasV6T2]>,
2870 let Inst{19-16} = imm{15-12};
2871 let Inst{15-12} = Rd;
2872 let Inst{11-0} = imm{11-0};
2875 def MOVCCi : AI1<0b1101, (outs GPR:$Rd),
2876 (ins GPR:$false, so_imm:$imm), DPFrm, IIC_iCMOVi,
2877 "mov", "\t$Rd, $imm",
2878 [/*(set GPR:$Rd, (ARMcmov GPR:$false, so_imm:$imm, imm:$cc, CCR:$ccr))*/]>,
2879 RegConstraint<"$false = $Rd">, UnaryDP {
2884 let Inst{19-16} = 0b0000;
2885 let Inst{15-12} = Rd;
2886 let Inst{11-0} = imm;
2888 } // neverHasSideEffects
2890 //===----------------------------------------------------------------------===//
2891 // Atomic operations intrinsics
2894 def memb_opt : Operand<i32> {
2895 let PrintMethod = "printMemBOption";
2898 // memory barriers protect the atomic sequences
2899 let hasSideEffects = 1 in {
2900 def DMB : AInoP<(outs), (ins memb_opt:$opt), MiscFrm, NoItinerary,
2901 "dmb", "\t$opt", [(ARMMemBarrier (i32 imm:$opt))]>,
2902 Requires<[IsARM, HasDB]> {
2904 let Inst{31-4} = 0xf57ff05;
2905 let Inst{3-0} = opt;
2908 def DMB_MCR : AInoP<(outs), (ins GPR:$zero), MiscFrm, NoItinerary,
2909 "mcr", "\tp15, 0, $zero, c7, c10, 5",
2910 [(ARMMemBarrierMCR GPR:$zero)]>,
2911 Requires<[IsARM, HasV6]> {
2912 // FIXME: add encoding
2916 def DSB : AInoP<(outs), (ins memb_opt:$opt), MiscFrm, NoItinerary,
2918 [/* For disassembly only; pattern left blank */]>,
2919 Requires<[IsARM, HasDB]> {
2921 let Inst{31-4} = 0xf57ff04;
2922 let Inst{3-0} = opt;
2925 // ISB has only full system option -- for disassembly only
2926 def ISB : AInoP<(outs), (ins), MiscFrm, NoItinerary, "isb", "", []>,
2927 Requires<[IsARM, HasDB]> {
2928 let Inst{31-4} = 0xf57ff06;
2929 let Inst{3-0} = 0b1111;
2932 let usesCustomInserter = 1 in {
2933 let Uses = [CPSR] in {
2934 def ATOMIC_LOAD_ADD_I8 : PseudoInst<
2935 (outs GPR:$dst), (ins GPR:$ptr, GPR:$incr), NoItinerary, "",
2936 [(set GPR:$dst, (atomic_load_add_8 GPR:$ptr, GPR:$incr))]>;
2937 def ATOMIC_LOAD_SUB_I8 : PseudoInst<
2938 (outs GPR:$dst), (ins GPR:$ptr, GPR:$incr), NoItinerary, "",
2939 [(set GPR:$dst, (atomic_load_sub_8 GPR:$ptr, GPR:$incr))]>;
2940 def ATOMIC_LOAD_AND_I8 : PseudoInst<
2941 (outs GPR:$dst), (ins GPR:$ptr, GPR:$incr), NoItinerary, "",
2942 [(set GPR:$dst, (atomic_load_and_8 GPR:$ptr, GPR:$incr))]>;
2943 def ATOMIC_LOAD_OR_I8 : PseudoInst<
2944 (outs GPR:$dst), (ins GPR:$ptr, GPR:$incr), NoItinerary, "",
2945 [(set GPR:$dst, (atomic_load_or_8 GPR:$ptr, GPR:$incr))]>;
2946 def ATOMIC_LOAD_XOR_I8 : PseudoInst<
2947 (outs GPR:$dst), (ins GPR:$ptr, GPR:$incr), NoItinerary, "",
2948 [(set GPR:$dst, (atomic_load_xor_8 GPR:$ptr, GPR:$incr))]>;
2949 def ATOMIC_LOAD_NAND_I8 : PseudoInst<
2950 (outs GPR:$dst), (ins GPR:$ptr, GPR:$incr), NoItinerary, "",
2951 [(set GPR:$dst, (atomic_load_nand_8 GPR:$ptr, GPR:$incr))]>;
2952 def ATOMIC_LOAD_ADD_I16 : PseudoInst<
2953 (outs GPR:$dst), (ins GPR:$ptr, GPR:$incr), NoItinerary, "",
2954 [(set GPR:$dst, (atomic_load_add_16 GPR:$ptr, GPR:$incr))]>;
2955 def ATOMIC_LOAD_SUB_I16 : PseudoInst<
2956 (outs GPR:$dst), (ins GPR:$ptr, GPR:$incr), NoItinerary, "",
2957 [(set GPR:$dst, (atomic_load_sub_16 GPR:$ptr, GPR:$incr))]>;
2958 def ATOMIC_LOAD_AND_I16 : PseudoInst<
2959 (outs GPR:$dst), (ins GPR:$ptr, GPR:$incr), NoItinerary, "",
2960 [(set GPR:$dst, (atomic_load_and_16 GPR:$ptr, GPR:$incr))]>;
2961 def ATOMIC_LOAD_OR_I16 : PseudoInst<
2962 (outs GPR:$dst), (ins GPR:$ptr, GPR:$incr), NoItinerary, "",
2963 [(set GPR:$dst, (atomic_load_or_16 GPR:$ptr, GPR:$incr))]>;
2964 def ATOMIC_LOAD_XOR_I16 : PseudoInst<
2965 (outs GPR:$dst), (ins GPR:$ptr, GPR:$incr), NoItinerary, "",
2966 [(set GPR:$dst, (atomic_load_xor_16 GPR:$ptr, GPR:$incr))]>;
2967 def ATOMIC_LOAD_NAND_I16 : PseudoInst<
2968 (outs GPR:$dst), (ins GPR:$ptr, GPR:$incr), NoItinerary, "",
2969 [(set GPR:$dst, (atomic_load_nand_16 GPR:$ptr, GPR:$incr))]>;
2970 def ATOMIC_LOAD_ADD_I32 : PseudoInst<
2971 (outs GPR:$dst), (ins GPR:$ptr, GPR:$incr), NoItinerary, "",
2972 [(set GPR:$dst, (atomic_load_add_32 GPR:$ptr, GPR:$incr))]>;
2973 def ATOMIC_LOAD_SUB_I32 : PseudoInst<
2974 (outs GPR:$dst), (ins GPR:$ptr, GPR:$incr), NoItinerary, "",
2975 [(set GPR:$dst, (atomic_load_sub_32 GPR:$ptr, GPR:$incr))]>;
2976 def ATOMIC_LOAD_AND_I32 : PseudoInst<
2977 (outs GPR:$dst), (ins GPR:$ptr, GPR:$incr), NoItinerary, "",
2978 [(set GPR:$dst, (atomic_load_and_32 GPR:$ptr, GPR:$incr))]>;
2979 def ATOMIC_LOAD_OR_I32 : PseudoInst<
2980 (outs GPR:$dst), (ins GPR:$ptr, GPR:$incr), NoItinerary, "",
2981 [(set GPR:$dst, (atomic_load_or_32 GPR:$ptr, GPR:$incr))]>;
2982 def ATOMIC_LOAD_XOR_I32 : PseudoInst<
2983 (outs GPR:$dst), (ins GPR:$ptr, GPR:$incr), NoItinerary, "",
2984 [(set GPR:$dst, (atomic_load_xor_32 GPR:$ptr, GPR:$incr))]>;
2985 def ATOMIC_LOAD_NAND_I32 : PseudoInst<
2986 (outs GPR:$dst), (ins GPR:$ptr, GPR:$incr), NoItinerary, "",
2987 [(set GPR:$dst, (atomic_load_nand_32 GPR:$ptr, GPR:$incr))]>;
2989 def ATOMIC_SWAP_I8 : PseudoInst<
2990 (outs GPR:$dst), (ins GPR:$ptr, GPR:$new), NoItinerary, "",
2991 [(set GPR:$dst, (atomic_swap_8 GPR:$ptr, GPR:$new))]>;
2992 def ATOMIC_SWAP_I16 : PseudoInst<
2993 (outs GPR:$dst), (ins GPR:$ptr, GPR:$new), NoItinerary, "",
2994 [(set GPR:$dst, (atomic_swap_16 GPR:$ptr, GPR:$new))]>;
2995 def ATOMIC_SWAP_I32 : PseudoInst<
2996 (outs GPR:$dst), (ins GPR:$ptr, GPR:$new), NoItinerary, "",
2997 [(set GPR:$dst, (atomic_swap_32 GPR:$ptr, GPR:$new))]>;
2999 def ATOMIC_CMP_SWAP_I8 : PseudoInst<
3000 (outs GPR:$dst), (ins GPR:$ptr, GPR:$old, GPR:$new), NoItinerary, "",
3001 [(set GPR:$dst, (atomic_cmp_swap_8 GPR:$ptr, GPR:$old, GPR:$new))]>;
3002 def ATOMIC_CMP_SWAP_I16 : PseudoInst<
3003 (outs GPR:$dst), (ins GPR:$ptr, GPR:$old, GPR:$new), NoItinerary, "",
3004 [(set GPR:$dst, (atomic_cmp_swap_16 GPR:$ptr, GPR:$old, GPR:$new))]>;
3005 def ATOMIC_CMP_SWAP_I32 : PseudoInst<
3006 (outs GPR:$dst), (ins GPR:$ptr, GPR:$old, GPR:$new), NoItinerary, "",
3007 [(set GPR:$dst, (atomic_cmp_swap_32 GPR:$ptr, GPR:$old, GPR:$new))]>;
3011 let mayLoad = 1 in {
3012 def LDREXB : AIldrex<0b10, (outs GPR:$Rt), (ins GPR:$Rn), NoItinerary,
3013 "ldrexb", "\t$Rt, [$Rn]",
3015 def LDREXH : AIldrex<0b11, (outs GPR:$Rt), (ins GPR:$Rn), NoItinerary,
3016 "ldrexh", "\t$Rt, [$Rn]",
3018 def LDREX : AIldrex<0b00, (outs GPR:$Rt), (ins GPR:$Rn), NoItinerary,
3019 "ldrex", "\t$Rt, [$Rn]",
3021 def LDREXD : AIldrex<0b01, (outs GPR:$Rt, GPR:$Rt2), (ins GPR:$Rn),
3023 "ldrexd", "\t$Rt, $Rt2, [$Rn]",
3027 let mayStore = 1, Constraints = "@earlyclobber $Rd" in {
3028 def STREXB : AIstrex<0b10, (outs GPR:$Rd), (ins GPR:$src, GPR:$Rn),
3030 "strexb", "\t$Rd, $src, [$Rn]",
3032 def STREXH : AIstrex<0b11, (outs GPR:$Rd), (ins GPR:$Rt, GPR:$Rn),
3034 "strexh", "\t$Rd, $Rt, [$Rn]",
3036 def STREX : AIstrex<0b00, (outs GPR:$Rd), (ins GPR:$Rt, GPR:$Rn),
3038 "strex", "\t$Rd, $Rt, [$Rn]",
3040 def STREXD : AIstrex<0b01, (outs GPR:$Rd),
3041 (ins GPR:$Rt, GPR:$Rt2, GPR:$Rn),
3043 "strexd", "\t$Rd, $Rt, $Rt2, [$Rn]",
3047 // Clear-Exclusive is for disassembly only.
3048 def CLREX : AXI<(outs), (ins), MiscFrm, NoItinerary, "clrex",
3049 [/* For disassembly only; pattern left blank */]>,
3050 Requires<[IsARM, HasV7]> {
3051 let Inst{31-0} = 0b11110101011111111111000000011111;
3054 // SWP/SWPB are deprecated in V6/V7 and for disassembly only.
3055 let mayLoad = 1 in {
3056 def SWP : AIswp<0, (outs GPR:$Rt), (ins GPR:$Rt2, GPR:$Rn), "swp",
3057 [/* For disassembly only; pattern left blank */]>;
3058 def SWPB : AIswp<1, (outs GPR:$Rt), (ins GPR:$Rt2, GPR:$Rn), "swpb",
3059 [/* For disassembly only; pattern left blank */]>;
3062 //===----------------------------------------------------------------------===//
3066 // __aeabi_read_tp preserves the registers r1-r3.
3067 // FIXME: This needs to be a pseudo of some sort so that we can get the
3068 // encoding right, complete with fixup for the aeabi_read_tp function.
3070 Defs = [R0, R12, LR, CPSR] in {
3071 def TPsoft : ABXI<0b1011, (outs), (ins), IIC_Br,
3072 "bl\t__aeabi_read_tp",
3073 [(set R0, ARMthread_pointer)]>;
3076 //===----------------------------------------------------------------------===//
3077 // SJLJ Exception handling intrinsics
3078 // eh_sjlj_setjmp() is an instruction sequence to store the return
3079 // address and save #0 in R0 for the non-longjmp case.
3080 // Since by its nature we may be coming from some other function to get
3081 // here, and we're using the stack frame for the containing function to
3082 // save/restore registers, we can't keep anything live in regs across
3083 // the eh_sjlj_setjmp(), else it will almost certainly have been tromped upon
3084 // when we get here from a longjmp(). We force everthing out of registers
3085 // except for our own input by listing the relevant registers in Defs. By
3086 // doing so, we also cause the prologue/epilogue code to actively preserve
3087 // all of the callee-saved resgisters, which is exactly what we want.
3088 // A constant value is passed in $val, and we use the location as a scratch.
3090 // These are pseudo-instructions and are lowered to individual MC-insts, so
3091 // no encoding information is necessary.
3093 [ R0, R1, R2, R3, R4, R5, R6, R7, R8, R9, R10, R11, R12, LR, D0,
3094 D1, D2, D3, D4, D5, D6, D7, D8, D9, D10, D11, D12, D13, D14, D15,
3095 D16, D17, D18, D19, D20, D21, D22, D23, D24, D25, D26, D27, D28, D29, D30,
3096 D31 ], hasSideEffects = 1, isBarrier = 1 in {
3097 def Int_eh_sjlj_setjmp : XI<(outs), (ins GPR:$src, GPR:$val),
3098 AddrModeNone, SizeSpecial, IndexModeNone,
3099 Pseudo, NoItinerary, "", "",
3100 [(set R0, (ARMeh_sjlj_setjmp GPR:$src, GPR:$val))]>,
3101 Requires<[IsARM, HasVFP2]>;
3105 [ R0, R1, R2, R3, R4, R5, R6, R7, R8, R9, R10, R11, R12, LR ],
3106 hasSideEffects = 1, isBarrier = 1 in {
3107 def Int_eh_sjlj_setjmp_nofp : XI<(outs), (ins GPR:$src, GPR:$val),
3108 AddrModeNone, SizeSpecial, IndexModeNone,
3109 Pseudo, NoItinerary, "", "",
3110 [(set R0, (ARMeh_sjlj_setjmp GPR:$src, GPR:$val))]>,
3111 Requires<[IsARM, NoVFP]>;
3114 // FIXME: Non-Darwin version(s)
3115 let isBarrier = 1, hasSideEffects = 1, isTerminator = 1,
3116 Defs = [ R7, LR, SP ] in {
3117 def Int_eh_sjlj_longjmp : XI<(outs), (ins GPR:$src, GPR:$scratch),
3118 AddrModeNone, SizeSpecial, IndexModeNone,
3119 Pseudo, NoItinerary, "", "",
3120 [(ARMeh_sjlj_longjmp GPR:$src, GPR:$scratch)]>,
3121 Requires<[IsARM, IsDarwin]>;
3124 // eh.sjlj.dispatchsetup pseudo-instruction.
3125 // This pseudo is used for ARM, Thumb1 and Thumb2. Any differences are
3126 // handled when the pseudo is expanded (which happens before any passes
3127 // that need the instruction size).
3128 let isBarrier = 1, hasSideEffects = 1 in
3129 def Int_eh_sjlj_dispatchsetup :
3130 PseudoInst<(outs), (ins GPR:$src), NoItinerary, "",
3131 [(ARMeh_sjlj_dispatchsetup GPR:$src)]>,
3132 Requires<[IsDarwin]>;
3134 //===----------------------------------------------------------------------===//
3135 // Non-Instruction Patterns
3138 // Large immediate handling.
3140 // Two piece so_imms.
3141 // FIXME: Remove this when we can do generalized remat.
3142 let isReMaterializable = 1 in
3143 def MOVi2pieces : PseudoInst<(outs GPR:$dst), (ins so_imm2part:$src),
3145 [(set GPR:$dst, (so_imm2part:$src))]>,
3146 Requires<[IsARM, NoV6T2]>;
3148 def : ARMPat<(or GPR:$LHS, so_imm2part:$RHS),
3149 (ORRri (ORRri GPR:$LHS, (so_imm2part_1 imm:$RHS)),
3150 (so_imm2part_2 imm:$RHS))>;
3151 def : ARMPat<(xor GPR:$LHS, so_imm2part:$RHS),
3152 (EORri (EORri GPR:$LHS, (so_imm2part_1 imm:$RHS)),
3153 (so_imm2part_2 imm:$RHS))>;
3154 def : ARMPat<(add GPR:$LHS, so_imm2part:$RHS),
3155 (ADDri (ADDri GPR:$LHS, (so_imm2part_1 imm:$RHS)),
3156 (so_imm2part_2 imm:$RHS))>;
3157 def : ARMPat<(add GPR:$LHS, so_neg_imm2part:$RHS),
3158 (SUBri (SUBri GPR:$LHS, (so_neg_imm2part_1 imm:$RHS)),
3159 (so_neg_imm2part_2 imm:$RHS))>;
3161 // 32-bit immediate using movw + movt.
3162 // This is a single pseudo instruction, the benefit is that it can be remat'd
3163 // as a single unit instead of having to handle reg inputs.
3164 // FIXME: Remove this when we can do generalized remat.
3165 let isReMaterializable = 1 in
3166 def MOVi32imm : PseudoInst<(outs GPR:$dst), (ins i32imm:$src), IIC_iMOVix2, "",
3167 [(set GPR:$dst, (i32 imm:$src))]>,
3168 Requires<[IsARM, HasV6T2]>;
3170 // ConstantPool, GlobalAddress, and JumpTable
3171 def : ARMPat<(ARMWrapper tglobaladdr :$dst), (LEApcrel tglobaladdr :$dst)>,
3172 Requires<[IsARM, DontUseMovt]>;
3173 def : ARMPat<(ARMWrapper tconstpool :$dst), (LEApcrel tconstpool :$dst)>;
3174 def : ARMPat<(ARMWrapper tglobaladdr :$dst), (MOVi32imm tglobaladdr :$dst)>,
3175 Requires<[IsARM, UseMovt]>;
3176 def : ARMPat<(ARMWrapperJT tjumptable:$dst, imm:$id),
3177 (LEApcrelJT tjumptable:$dst, imm:$id)>;
3179 // TODO: add,sub,and, 3-instr forms?
3182 def : ARMPat<(ARMtcret tcGPR:$dst),
3183 (TCRETURNri tcGPR:$dst)>, Requires<[IsDarwin]>;
3185 def : ARMPat<(ARMtcret (i32 tglobaladdr:$dst)),
3186 (TCRETURNdi texternalsym:$dst)>, Requires<[IsDarwin]>;
3188 def : ARMPat<(ARMtcret (i32 texternalsym:$dst)),
3189 (TCRETURNdi texternalsym:$dst)>, Requires<[IsDarwin]>;
3191 def : ARMPat<(ARMtcret tcGPR:$dst),
3192 (TCRETURNriND tcGPR:$dst)>, Requires<[IsNotDarwin]>;
3194 def : ARMPat<(ARMtcret (i32 tglobaladdr:$dst)),
3195 (TCRETURNdiND texternalsym:$dst)>, Requires<[IsNotDarwin]>;
3197 def : ARMPat<(ARMtcret (i32 texternalsym:$dst)),
3198 (TCRETURNdiND texternalsym:$dst)>, Requires<[IsNotDarwin]>;
3201 def : ARMPat<(ARMcall texternalsym:$func), (BL texternalsym:$func)>,
3202 Requires<[IsARM, IsNotDarwin]>;
3203 def : ARMPat<(ARMcall texternalsym:$func), (BLr9 texternalsym:$func)>,
3204 Requires<[IsARM, IsDarwin]>;
3206 // zextload i1 -> zextload i8
3207 def : ARMPat<(zextloadi1 addrmode_imm12:$addr), (LDRBi12 addrmode_imm12:$addr)>;
3208 def : ARMPat<(zextloadi1 ldst_so_reg:$addr), (LDRBrs ldst_so_reg:$addr)>;
3210 // extload -> zextload
3211 def : ARMPat<(extloadi1 addrmode_imm12:$addr), (LDRBi12 addrmode_imm12:$addr)>;
3212 def : ARMPat<(extloadi1 ldst_so_reg:$addr), (LDRBrs ldst_so_reg:$addr)>;
3213 def : ARMPat<(extloadi8 addrmode_imm12:$addr), (LDRBi12 addrmode_imm12:$addr)>;
3214 def : ARMPat<(extloadi8 ldst_so_reg:$addr), (LDRBrs ldst_so_reg:$addr)>;
3216 def : ARMPat<(extloadi16 addrmode3:$addr), (LDRH addrmode3:$addr)>;
3218 def : ARMPat<(extloadi8 addrmodepc:$addr), (PICLDRB addrmodepc:$addr)>;
3219 def : ARMPat<(extloadi16 addrmodepc:$addr), (PICLDRH addrmodepc:$addr)>;
3222 def : ARMV5TEPat<(mul (sra (shl GPR:$a, (i32 16)), (i32 16)),
3223 (sra (shl GPR:$b, (i32 16)), (i32 16))),
3224 (SMULBB GPR:$a, GPR:$b)>;
3225 def : ARMV5TEPat<(mul sext_16_node:$a, sext_16_node:$b),
3226 (SMULBB GPR:$a, GPR:$b)>;
3227 def : ARMV5TEPat<(mul (sra (shl GPR:$a, (i32 16)), (i32 16)),
3228 (sra GPR:$b, (i32 16))),
3229 (SMULBT GPR:$a, GPR:$b)>;
3230 def : ARMV5TEPat<(mul sext_16_node:$a, (sra GPR:$b, (i32 16))),
3231 (SMULBT GPR:$a, GPR:$b)>;
3232 def : ARMV5TEPat<(mul (sra GPR:$a, (i32 16)),
3233 (sra (shl GPR:$b, (i32 16)), (i32 16))),
3234 (SMULTB GPR:$a, GPR:$b)>;
3235 def : ARMV5TEPat<(mul (sra GPR:$a, (i32 16)), sext_16_node:$b),
3236 (SMULTB GPR:$a, GPR:$b)>;
3237 def : ARMV5TEPat<(sra (mul GPR:$a, (sra (shl GPR:$b, (i32 16)), (i32 16))),
3239 (SMULWB GPR:$a, GPR:$b)>;
3240 def : ARMV5TEPat<(sra (mul GPR:$a, sext_16_node:$b), (i32 16)),
3241 (SMULWB GPR:$a, GPR:$b)>;
3243 def : ARMV5TEPat<(add GPR:$acc,
3244 (mul (sra (shl GPR:$a, (i32 16)), (i32 16)),
3245 (sra (shl GPR:$b, (i32 16)), (i32 16)))),
3246 (SMLABB GPR:$a, GPR:$b, GPR:$acc)>;
3247 def : ARMV5TEPat<(add GPR:$acc,
3248 (mul sext_16_node:$a, sext_16_node:$b)),
3249 (SMLABB GPR:$a, GPR:$b, GPR:$acc)>;
3250 def : ARMV5TEPat<(add GPR:$acc,
3251 (mul (sra (shl GPR:$a, (i32 16)), (i32 16)),
3252 (sra GPR:$b, (i32 16)))),
3253 (SMLABT GPR:$a, GPR:$b, GPR:$acc)>;
3254 def : ARMV5TEPat<(add GPR:$acc,
3255 (mul sext_16_node:$a, (sra GPR:$b, (i32 16)))),
3256 (SMLABT GPR:$a, GPR:$b, GPR:$acc)>;
3257 def : ARMV5TEPat<(add GPR:$acc,
3258 (mul (sra GPR:$a, (i32 16)),
3259 (sra (shl GPR:$b, (i32 16)), (i32 16)))),
3260 (SMLATB GPR:$a, GPR:$b, GPR:$acc)>;
3261 def : ARMV5TEPat<(add GPR:$acc,
3262 (mul (sra GPR:$a, (i32 16)), sext_16_node:$b)),
3263 (SMLATB GPR:$a, GPR:$b, GPR:$acc)>;
3264 def : ARMV5TEPat<(add GPR:$acc,
3265 (sra (mul GPR:$a, (sra (shl GPR:$b, (i32 16)), (i32 16))),
3267 (SMLAWB GPR:$a, GPR:$b, GPR:$acc)>;
3268 def : ARMV5TEPat<(add GPR:$acc,
3269 (sra (mul GPR:$a, sext_16_node:$b), (i32 16))),
3270 (SMLAWB GPR:$a, GPR:$b, GPR:$acc)>;
3272 //===----------------------------------------------------------------------===//
3276 include "ARMInstrThumb.td"
3278 //===----------------------------------------------------------------------===//
3282 include "ARMInstrThumb2.td"
3284 //===----------------------------------------------------------------------===//
3285 // Floating Point Support
3288 include "ARMInstrVFP.td"
3290 //===----------------------------------------------------------------------===//
3291 // Advanced SIMD (NEON) Support
3294 include "ARMInstrNEON.td"
3296 //===----------------------------------------------------------------------===//
3297 // Coprocessor Instructions. For disassembly only.
3300 def CDP : ABI<0b1110, (outs), (ins nohash_imm:$cop, i32imm:$opc1,
3301 nohash_imm:$CRd, nohash_imm:$CRn, nohash_imm:$CRm, i32imm:$opc2),
3302 NoItinerary, "cdp", "\tp$cop, $opc1, cr$CRd, cr$CRn, cr$CRm, $opc2",
3303 [/* For disassembly only; pattern left blank */]> {
3307 def CDP2 : ABXI<0b1110, (outs), (ins nohash_imm:$cop, i32imm:$opc1,
3308 nohash_imm:$CRd, nohash_imm:$CRn, nohash_imm:$CRm, i32imm:$opc2),
3309 NoItinerary, "cdp2\tp$cop, $opc1, cr$CRd, cr$CRn, cr$CRm, $opc2",
3310 [/* For disassembly only; pattern left blank */]> {
3311 let Inst{31-28} = 0b1111;
3315 class ACI<dag oops, dag iops, string opc, string asm>
3316 : I<oops, iops, AddrModeNone, Size4Bytes, IndexModeNone, BrFrm, NoItinerary,
3317 opc, asm, "", [/* For disassembly only; pattern left blank */]> {
3318 let Inst{27-25} = 0b110;
3321 multiclass LdStCop<bits<4> op31_28, bit load, string opc> {
3323 def _OFFSET : ACI<(outs),
3324 (ins nohash_imm:$cop, nohash_imm:$CRd, addrmode2:$addr),
3325 opc, "\tp$cop, cr$CRd, $addr"> {
3326 let Inst{31-28} = op31_28;
3327 let Inst{24} = 1; // P = 1
3328 let Inst{21} = 0; // W = 0
3329 let Inst{22} = 0; // D = 0
3330 let Inst{20} = load;
3333 def _PRE : ACI<(outs),
3334 (ins nohash_imm:$cop, nohash_imm:$CRd, addrmode2:$addr),
3335 opc, "\tp$cop, cr$CRd, $addr!"> {
3336 let Inst{31-28} = op31_28;
3337 let Inst{24} = 1; // P = 1
3338 let Inst{21} = 1; // W = 1
3339 let Inst{22} = 0; // D = 0
3340 let Inst{20} = load;
3343 def _POST : ACI<(outs),
3344 (ins nohash_imm:$cop, nohash_imm:$CRd, GPR:$base, am2offset:$offset),
3345 opc, "\tp$cop, cr$CRd, [$base], $offset"> {
3346 let Inst{31-28} = op31_28;
3347 let Inst{24} = 0; // P = 0
3348 let Inst{21} = 1; // W = 1
3349 let Inst{22} = 0; // D = 0
3350 let Inst{20} = load;
3353 def _OPTION : ACI<(outs),
3354 (ins nohash_imm:$cop, nohash_imm:$CRd, GPR:$base, i32imm:$option),
3355 opc, "\tp$cop, cr$CRd, [$base], $option"> {
3356 let Inst{31-28} = op31_28;
3357 let Inst{24} = 0; // P = 0
3358 let Inst{23} = 1; // U = 1
3359 let Inst{21} = 0; // W = 0
3360 let Inst{22} = 0; // D = 0
3361 let Inst{20} = load;
3364 def L_OFFSET : ACI<(outs),
3365 (ins nohash_imm:$cop, nohash_imm:$CRd, addrmode2:$addr),
3366 !strconcat(opc, "l"), "\tp$cop, cr$CRd, $addr"> {
3367 let Inst{31-28} = op31_28;
3368 let Inst{24} = 1; // P = 1
3369 let Inst{21} = 0; // W = 0
3370 let Inst{22} = 1; // D = 1
3371 let Inst{20} = load;
3374 def L_PRE : ACI<(outs),
3375 (ins nohash_imm:$cop, nohash_imm:$CRd, addrmode2:$addr),
3376 !strconcat(opc, "l"), "\tp$cop, cr$CRd, $addr!"> {
3377 let Inst{31-28} = op31_28;
3378 let Inst{24} = 1; // P = 1
3379 let Inst{21} = 1; // W = 1
3380 let Inst{22} = 1; // D = 1
3381 let Inst{20} = load;
3384 def L_POST : ACI<(outs),
3385 (ins nohash_imm:$cop, nohash_imm:$CRd, GPR:$base, am2offset:$offset),
3386 !strconcat(opc, "l"), "\tp$cop, cr$CRd, [$base], $offset"> {
3387 let Inst{31-28} = op31_28;
3388 let Inst{24} = 0; // P = 0
3389 let Inst{21} = 1; // W = 1
3390 let Inst{22} = 1; // D = 1
3391 let Inst{20} = load;
3394 def L_OPTION : ACI<(outs),
3395 (ins nohash_imm:$cop, nohash_imm:$CRd, GPR:$base, nohash_imm:$option),
3396 !strconcat(opc, "l"), "\tp$cop, cr$CRd, [$base], $option"> {
3397 let Inst{31-28} = op31_28;
3398 let Inst{24} = 0; // P = 0
3399 let Inst{23} = 1; // U = 1
3400 let Inst{21} = 0; // W = 0
3401 let Inst{22} = 1; // D = 1
3402 let Inst{20} = load;
3406 defm LDC : LdStCop<{?,?,?,?}, 1, "ldc">;
3407 defm LDC2 : LdStCop<0b1111, 1, "ldc2">;
3408 defm STC : LdStCop<{?,?,?,?}, 0, "stc">;
3409 defm STC2 : LdStCop<0b1111, 0, "stc2">;
3411 def MCR : ABI<0b1110, (outs), (ins nohash_imm:$cop, i32imm:$opc1,
3412 GPR:$Rt, nohash_imm:$CRn, nohash_imm:$CRm, i32imm:$opc2),
3413 NoItinerary, "mcr", "\tp$cop, $opc1, $Rt, cr$CRn, cr$CRm, $opc2",
3414 [/* For disassembly only; pattern left blank */]> {
3419 def MCR2 : ABXI<0b1110, (outs), (ins nohash_imm:$cop, i32imm:$opc1,
3420 GPR:$Rt, nohash_imm:$CRn, nohash_imm:$CRm, i32imm:$opc2),
3421 NoItinerary, "mcr2\tp$cop, $opc1, $Rt, cr$CRn, cr$CRm, $opc2",
3422 [/* For disassembly only; pattern left blank */]> {
3423 let Inst{31-28} = 0b1111;
3428 def MRC : ABI<0b1110, (outs), (ins nohash_imm:$cop, i32imm:$opc1,
3429 GPR:$Rt, nohash_imm:$CRn, nohash_imm:$CRm, i32imm:$opc2),
3430 NoItinerary, "mrc", "\tp$cop, $opc1, $Rt, cr$CRn, cr$CRm, $opc2",
3431 [/* For disassembly only; pattern left blank */]> {
3436 def MRC2 : ABXI<0b1110, (outs), (ins nohash_imm:$cop, i32imm:$opc1,
3437 GPR:$Rt, nohash_imm:$CRn, nohash_imm:$CRm, i32imm:$opc2),
3438 NoItinerary, "mrc2\tp$cop, $opc1, $Rt, cr$CRn, cr$CRm, $opc2",
3439 [/* For disassembly only; pattern left blank */]> {
3440 let Inst{31-28} = 0b1111;
3445 def MCRR : ABI<0b1100, (outs), (ins nohash_imm:$cop, i32imm:$opc,
3446 GPR:$Rt, GPR:$Rt2, nohash_imm:$CRm),
3447 NoItinerary, "mcrr", "\tp$cop, $opc, $Rt, $Rt2, cr$CRm",
3448 [/* For disassembly only; pattern left blank */]> {
3449 let Inst{23-20} = 0b0100;
3452 def MCRR2 : ABXI<0b1100, (outs), (ins nohash_imm:$cop, i32imm:$opc,
3453 GPR:$Rt, GPR:$Rt2, nohash_imm:$CRm),
3454 NoItinerary, "mcrr2\tp$cop, $opc, $Rt, $Rt2, cr$CRm",
3455 [/* For disassembly only; pattern left blank */]> {
3456 let Inst{31-28} = 0b1111;
3457 let Inst{23-20} = 0b0100;
3460 def MRRC : ABI<0b1100, (outs), (ins nohash_imm:$cop, i32imm:$opc,
3461 GPR:$Rt, GPR:$Rt2, nohash_imm:$CRm),
3462 NoItinerary, "mrrc", "\tp$cop, $opc, $Rt, $Rt2, cr$CRm",
3463 [/* For disassembly only; pattern left blank */]> {
3464 let Inst{23-20} = 0b0101;
3467 def MRRC2 : ABXI<0b1100, (outs), (ins nohash_imm:$cop, i32imm:$opc,
3468 GPR:$Rt, GPR:$Rt2, nohash_imm:$CRm),
3469 NoItinerary, "mrrc2\tp$cop, $opc, $Rt, $Rt2, cr$CRm",
3470 [/* For disassembly only; pattern left blank */]> {
3471 let Inst{31-28} = 0b1111;
3472 let Inst{23-20} = 0b0101;
3475 //===----------------------------------------------------------------------===//
3476 // Move between special register and ARM core register -- for disassembly only
3479 def MRS : ABI<0b0001,(outs GPR:$dst),(ins), NoItinerary, "mrs", "\t$dst, cpsr",
3480 [/* For disassembly only; pattern left blank */]> {
3481 let Inst{23-20} = 0b0000;
3482 let Inst{7-4} = 0b0000;
3485 def MRSsys : ABI<0b0001,(outs GPR:$dst),(ins), NoItinerary,"mrs","\t$dst, spsr",
3486 [/* For disassembly only; pattern left blank */]> {
3487 let Inst{23-20} = 0b0100;
3488 let Inst{7-4} = 0b0000;
3491 def MSR : ABI<0b0001, (outs), (ins GPR:$src, msr_mask:$mask), NoItinerary,
3492 "msr", "\tcpsr$mask, $src",
3493 [/* For disassembly only; pattern left blank */]> {
3494 let Inst{23-20} = 0b0010;
3495 let Inst{7-4} = 0b0000;
3498 def MSRi : ABI<0b0011, (outs), (ins so_imm:$a, msr_mask:$mask), NoItinerary,
3499 "msr", "\tcpsr$mask, $a",
3500 [/* For disassembly only; pattern left blank */]> {
3501 let Inst{23-20} = 0b0010;
3502 let Inst{7-4} = 0b0000;
3505 def MSRsys : ABI<0b0001, (outs), (ins GPR:$src, msr_mask:$mask), NoItinerary,
3506 "msr", "\tspsr$mask, $src",
3507 [/* For disassembly only; pattern left blank */]> {
3508 let Inst{23-20} = 0b0110;
3509 let Inst{7-4} = 0b0000;
3512 def MSRsysi : ABI<0b0011, (outs), (ins so_imm:$a, msr_mask:$mask), NoItinerary,
3513 "msr", "\tspsr$mask, $a",
3514 [/* For disassembly only; pattern left blank */]> {
3515 let Inst{23-20} = 0b0110;
3516 let Inst{7-4} = 0b0000;