1 //===- ARMInstrInfo.td - Target Description for ARM Target -*- tablegen -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file describes the ARM instructions in TableGen format.
12 //===----------------------------------------------------------------------===//
14 //===----------------------------------------------------------------------===//
15 // ARM specific DAG Nodes.
19 def SDT_ARMCallSeqStart : SDCallSeqStart<[ SDTCisVT<0, i32> ]>;
20 def SDT_ARMCallSeqEnd : SDCallSeqEnd<[ SDTCisVT<0, i32>, SDTCisVT<1, i32> ]>;
22 def SDT_ARMSaveCallPC : SDTypeProfile<0, 1, []>;
24 def SDT_ARMcall : SDTypeProfile<0, -1, [SDTCisPtrTy<0>]>;
26 def SDT_ARMCMov : SDTypeProfile<1, 3,
27 [SDTCisSameAs<0, 1>, SDTCisSameAs<0, 2>,
30 def SDT_ARMBrcond : SDTypeProfile<0, 2,
31 [SDTCisVT<0, OtherVT>, SDTCisVT<1, i32>]>;
33 def SDT_ARMBrJT : SDTypeProfile<0, 3,
34 [SDTCisPtrTy<0>, SDTCisVT<1, i32>,
37 def SDT_ARMBr2JT : SDTypeProfile<0, 4,
38 [SDTCisPtrTy<0>, SDTCisVT<1, i32>,
39 SDTCisVT<2, i32>, SDTCisVT<3, i32>]>;
41 def SDT_ARMBCC_i64 : SDTypeProfile<0, 6,
43 SDTCisVT<1, i32>, SDTCisVT<2, i32>,
44 SDTCisVT<3, i32>, SDTCisVT<4, i32>,
45 SDTCisVT<5, OtherVT>]>;
47 def SDT_ARMAnd : SDTypeProfile<1, 2,
48 [SDTCisVT<0, i32>, SDTCisVT<1, i32>,
51 def SDT_ARMCmp : SDTypeProfile<0, 2, [SDTCisSameAs<0, 1>]>;
53 def SDT_ARMPICAdd : SDTypeProfile<1, 2, [SDTCisSameAs<0, 1>,
54 SDTCisPtrTy<1>, SDTCisVT<2, i32>]>;
56 def SDT_ARMThreadPointer : SDTypeProfile<1, 0, [SDTCisPtrTy<0>]>;
57 def SDT_ARMEH_SJLJ_Setjmp : SDTypeProfile<1, 2, [SDTCisInt<0>, SDTCisPtrTy<1>,
59 def SDT_ARMEH_SJLJ_Longjmp: SDTypeProfile<0, 2, [SDTCisPtrTy<0>, SDTCisInt<1>]>;
61 def SDT_ARMEH_SJLJ_DispatchSetup: SDTypeProfile<0, 1, [SDTCisPtrTy<0>]>;
63 def SDT_ARMMEMBARRIER : SDTypeProfile<0, 1, [SDTCisInt<0>]>;
65 def SDT_ARMTCRET : SDTypeProfile<0, 1, [SDTCisPtrTy<0>]>;
67 def SDT_ARMBFI : SDTypeProfile<1, 3, [SDTCisVT<0, i32>, SDTCisVT<1, i32>,
68 SDTCisVT<2, i32>, SDTCisVT<3, i32>]>;
71 def ARMWrapper : SDNode<"ARMISD::Wrapper", SDTIntUnaryOp>;
72 def ARMWrapperDYN : SDNode<"ARMISD::WrapperDYN", SDTIntUnaryOp>;
73 def ARMWrapperPIC : SDNode<"ARMISD::WrapperPIC", SDTIntUnaryOp>;
74 def ARMWrapperJT : SDNode<"ARMISD::WrapperJT", SDTIntBinOp>;
76 def ARMcallseq_start : SDNode<"ISD::CALLSEQ_START", SDT_ARMCallSeqStart,
77 [SDNPHasChain, SDNPOutGlue]>;
78 def ARMcallseq_end : SDNode<"ISD::CALLSEQ_END", SDT_ARMCallSeqEnd,
79 [SDNPHasChain, SDNPOptInGlue, SDNPOutGlue]>;
81 def ARMcall : SDNode<"ARMISD::CALL", SDT_ARMcall,
82 [SDNPHasChain, SDNPOptInGlue, SDNPOutGlue,
84 def ARMcall_pred : SDNode<"ARMISD::CALL_PRED", SDT_ARMcall,
85 [SDNPHasChain, SDNPOptInGlue, SDNPOutGlue,
87 def ARMcall_nolink : SDNode<"ARMISD::CALL_NOLINK", SDT_ARMcall,
88 [SDNPHasChain, SDNPOptInGlue, SDNPOutGlue,
91 def ARMretflag : SDNode<"ARMISD::RET_FLAG", SDTNone,
92 [SDNPHasChain, SDNPOptInGlue]>;
94 def ARMcmov : SDNode<"ARMISD::CMOV", SDT_ARMCMov,
97 def ARMbrcond : SDNode<"ARMISD::BRCOND", SDT_ARMBrcond,
98 [SDNPHasChain, SDNPInGlue, SDNPOutGlue]>;
100 def ARMbrjt : SDNode<"ARMISD::BR_JT", SDT_ARMBrJT,
102 def ARMbr2jt : SDNode<"ARMISD::BR2_JT", SDT_ARMBr2JT,
105 def ARMBcci64 : SDNode<"ARMISD::BCC_i64", SDT_ARMBCC_i64,
108 def ARMcmp : SDNode<"ARMISD::CMP", SDT_ARMCmp,
111 def ARMcmpZ : SDNode<"ARMISD::CMPZ", SDT_ARMCmp,
112 [SDNPOutGlue, SDNPCommutative]>;
114 def ARMpic_add : SDNode<"ARMISD::PIC_ADD", SDT_ARMPICAdd>;
116 def ARMsrl_flag : SDNode<"ARMISD::SRL_FLAG", SDTIntUnaryOp, [SDNPOutGlue]>;
117 def ARMsra_flag : SDNode<"ARMISD::SRA_FLAG", SDTIntUnaryOp, [SDNPOutGlue]>;
118 def ARMrrx : SDNode<"ARMISD::RRX" , SDTIntUnaryOp, [SDNPInGlue ]>;
120 def ARMthread_pointer: SDNode<"ARMISD::THREAD_POINTER", SDT_ARMThreadPointer>;
121 def ARMeh_sjlj_setjmp: SDNode<"ARMISD::EH_SJLJ_SETJMP",
122 SDT_ARMEH_SJLJ_Setjmp, [SDNPHasChain]>;
123 def ARMeh_sjlj_longjmp: SDNode<"ARMISD::EH_SJLJ_LONGJMP",
124 SDT_ARMEH_SJLJ_Longjmp, [SDNPHasChain]>;
125 def ARMeh_sjlj_dispatchsetup: SDNode<"ARMISD::EH_SJLJ_DISPATCHSETUP",
126 SDT_ARMEH_SJLJ_DispatchSetup, [SDNPHasChain]>;
129 def ARMMemBarrier : SDNode<"ARMISD::MEMBARRIER", SDT_ARMMEMBARRIER,
131 def ARMMemBarrierMCR : SDNode<"ARMISD::MEMBARRIER_MCR", SDT_ARMMEMBARRIER,
133 def ARMPreload : SDNode<"ARMISD::PRELOAD", SDTPrefetch,
134 [SDNPHasChain, SDNPMayLoad, SDNPMayStore]>;
136 def ARMrbit : SDNode<"ARMISD::RBIT", SDTIntUnaryOp>;
138 def ARMtcret : SDNode<"ARMISD::TC_RETURN", SDT_ARMTCRET,
139 [SDNPHasChain, SDNPOptInGlue, SDNPVariadic]>;
142 def ARMbfi : SDNode<"ARMISD::BFI", SDT_ARMBFI>;
144 //===----------------------------------------------------------------------===//
145 // ARM Instruction Predicate Definitions.
147 def HasV4T : Predicate<"Subtarget->hasV4TOps()">, AssemblerPredicate;
148 def NoV4T : Predicate<"!Subtarget->hasV4TOps()">;
149 def HasV5T : Predicate<"Subtarget->hasV5TOps()">;
150 def HasV5TE : Predicate<"Subtarget->hasV5TEOps()">, AssemblerPredicate;
151 def HasV6 : Predicate<"Subtarget->hasV6Ops()">, AssemblerPredicate;
152 def NoV6 : Predicate<"!Subtarget->hasV6Ops()">;
153 def HasV6T2 : Predicate<"Subtarget->hasV6T2Ops()">, AssemblerPredicate;
154 def NoV6T2 : Predicate<"!Subtarget->hasV6T2Ops()">;
155 def HasV7 : Predicate<"Subtarget->hasV7Ops()">, AssemblerPredicate;
156 def NoVFP : Predicate<"!Subtarget->hasVFP2()">;
157 def HasVFP2 : Predicate<"Subtarget->hasVFP2()">, AssemblerPredicate;
158 def HasVFP3 : Predicate<"Subtarget->hasVFP3()">, AssemblerPredicate;
159 def HasNEON : Predicate<"Subtarget->hasNEON()">, AssemblerPredicate;
160 def HasFP16 : Predicate<"Subtarget->hasFP16()">, AssemblerPredicate;
161 def HasDivide : Predicate<"Subtarget->hasDivide()">, AssemblerPredicate;
162 def HasT2ExtractPack : Predicate<"Subtarget->hasT2ExtractPack()">,
164 def HasDB : Predicate<"Subtarget->hasDataBarrier()">,
166 def HasMP : Predicate<"Subtarget->hasMPExtension()">,
168 def UseNEONForFP : Predicate<"Subtarget->useNEONForSinglePrecisionFP()">;
169 def DontUseNEONForFP : Predicate<"!Subtarget->useNEONForSinglePrecisionFP()">;
170 def IsThumb : Predicate<"Subtarget->isThumb()">, AssemblerPredicate;
171 def IsThumb1Only : Predicate<"Subtarget->isThumb1Only()">;
172 def IsThumb2 : Predicate<"Subtarget->isThumb2()">, AssemblerPredicate;
173 def IsARM : Predicate<"!Subtarget->isThumb()">, AssemblerPredicate;
174 def IsDarwin : Predicate<"Subtarget->isTargetDarwin()">;
175 def IsNotDarwin : Predicate<"!Subtarget->isTargetDarwin()">;
177 // FIXME: Eventually this will be just "hasV6T2Ops".
178 def UseMovt : Predicate<"Subtarget->useMovt()">;
179 def DontUseMovt : Predicate<"!Subtarget->useMovt()">;
180 def UseFPVMLx : Predicate<"Subtarget->useFPVMLx()">;
182 //===----------------------------------------------------------------------===//
183 // ARM Flag Definitions.
185 class RegConstraint<string C> {
186 string Constraints = C;
189 //===----------------------------------------------------------------------===//
190 // ARM specific transformation functions and pattern fragments.
193 // so_imm_neg_XFORM - Return a so_imm value packed into the format described for
194 // so_imm_neg def below.
195 def so_imm_neg_XFORM : SDNodeXForm<imm, [{
196 return CurDAG->getTargetConstant(-(int)N->getZExtValue(), MVT::i32);
199 // so_imm_not_XFORM - Return a so_imm value packed into the format described for
200 // so_imm_not def below.
201 def so_imm_not_XFORM : SDNodeXForm<imm, [{
202 return CurDAG->getTargetConstant(~(int)N->getZExtValue(), MVT::i32);
205 /// imm1_15 predicate - True if the 32-bit immediate is in the range [1,15].
206 def imm1_15 : PatLeaf<(i32 imm), [{
207 return (int32_t)N->getZExtValue() >= 1 && (int32_t)N->getZExtValue() < 16;
210 /// imm16_31 predicate - True if the 32-bit immediate is in the range [16,31].
211 def imm16_31 : PatLeaf<(i32 imm), [{
212 return (int32_t)N->getZExtValue() >= 16 && (int32_t)N->getZExtValue() < 32;
217 return ARM_AM::getSOImmVal(-(uint32_t)N->getZExtValue()) != -1;
218 }], so_imm_neg_XFORM>;
222 return ARM_AM::getSOImmVal(~(uint32_t)N->getZExtValue()) != -1;
223 }], so_imm_not_XFORM>;
225 // sext_16_node predicate - True if the SDNode is sign-extended 16 or more bits.
226 def sext_16_node : PatLeaf<(i32 GPR:$a), [{
227 return CurDAG->ComputeNumSignBits(SDValue(N,0)) >= 17;
230 /// Split a 32-bit immediate into two 16 bit parts.
231 def hi16 : SDNodeXForm<imm, [{
232 return CurDAG->getTargetConstant((uint32_t)N->getZExtValue() >> 16, MVT::i32);
235 def lo16AllZero : PatLeaf<(i32 imm), [{
236 // Returns true if all low 16-bits are 0.
237 return (((uint32_t)N->getZExtValue()) & 0xFFFFUL) == 0;
240 /// imm0_65535 predicate - True if the 32-bit immediate is in the range
242 def imm0_65535 : PatLeaf<(i32 imm), [{
243 return (uint32_t)N->getZExtValue() < 65536;
246 class BinOpFrag<dag res> : PatFrag<(ops node:$LHS, node:$RHS), res>;
247 class UnOpFrag <dag res> : PatFrag<(ops node:$Src), res>;
249 /// adde and sube predicates - True based on whether the carry flag output
250 /// will be needed or not.
251 def adde_dead_carry :
252 PatFrag<(ops node:$LHS, node:$RHS), (adde node:$LHS, node:$RHS),
253 [{return !N->hasAnyUseOfValue(1);}]>;
254 def sube_dead_carry :
255 PatFrag<(ops node:$LHS, node:$RHS), (sube node:$LHS, node:$RHS),
256 [{return !N->hasAnyUseOfValue(1);}]>;
257 def adde_live_carry :
258 PatFrag<(ops node:$LHS, node:$RHS), (adde node:$LHS, node:$RHS),
259 [{return N->hasAnyUseOfValue(1);}]>;
260 def sube_live_carry :
261 PatFrag<(ops node:$LHS, node:$RHS), (sube node:$LHS, node:$RHS),
262 [{return N->hasAnyUseOfValue(1);}]>;
264 // An 'and' node with a single use.
265 def and_su : PatFrag<(ops node:$lhs, node:$rhs), (and node:$lhs, node:$rhs), [{
266 return N->hasOneUse();
269 // An 'xor' node with a single use.
270 def xor_su : PatFrag<(ops node:$lhs, node:$rhs), (xor node:$lhs, node:$rhs), [{
271 return N->hasOneUse();
274 // An 'fmul' node with a single use.
275 def fmul_su : PatFrag<(ops node:$lhs, node:$rhs), (fmul node:$lhs, node:$rhs),[{
276 return N->hasOneUse();
279 // An 'fadd' node which checks for single non-hazardous use.
280 def fadd_mlx : PatFrag<(ops node:$lhs, node:$rhs),(fadd node:$lhs, node:$rhs),[{
281 return hasNoVMLxHazardUse(N);
284 // An 'fsub' node which checks for single non-hazardous use.
285 def fsub_mlx : PatFrag<(ops node:$lhs, node:$rhs),(fsub node:$lhs, node:$rhs),[{
286 return hasNoVMLxHazardUse(N);
289 //===----------------------------------------------------------------------===//
290 // Operand Definitions.
294 // FIXME: rename brtarget to t2_brtarget
295 def brtarget : Operand<OtherVT> {
296 let EncoderMethod = "getBranchTargetOpValue";
299 // FIXME: get rid of this one?
300 def uncondbrtarget : Operand<OtherVT> {
301 let EncoderMethod = "getUnconditionalBranchTargetOpValue";
304 // Branch target for ARM. Handles conditional/unconditional
305 def br_target : Operand<OtherVT> {
306 let EncoderMethod = "getARMBranchTargetOpValue";
310 // FIXME: rename bltarget to t2_bl_target?
311 def bltarget : Operand<i32> {
312 // Encoded the same as branch targets.
313 let EncoderMethod = "getBranchTargetOpValue";
316 // Call target for ARM. Handles conditional/unconditional
317 // FIXME: rename bl_target to t2_bltarget?
318 def bl_target : Operand<i32> {
319 // Encoded the same as branch targets.
320 let EncoderMethod = "getARMBranchTargetOpValue";
324 // A list of registers separated by comma. Used by load/store multiple.
325 def RegListAsmOperand : AsmOperandClass {
326 let Name = "RegList";
327 let SuperClasses = [];
330 def DPRRegListAsmOperand : AsmOperandClass {
331 let Name = "DPRRegList";
332 let SuperClasses = [];
335 def SPRRegListAsmOperand : AsmOperandClass {
336 let Name = "SPRRegList";
337 let SuperClasses = [];
340 def reglist : Operand<i32> {
341 let EncoderMethod = "getRegisterListOpValue";
342 let ParserMatchClass = RegListAsmOperand;
343 let PrintMethod = "printRegisterList";
346 def dpr_reglist : Operand<i32> {
347 let EncoderMethod = "getRegisterListOpValue";
348 let ParserMatchClass = DPRRegListAsmOperand;
349 let PrintMethod = "printRegisterList";
352 def spr_reglist : Operand<i32> {
353 let EncoderMethod = "getRegisterListOpValue";
354 let ParserMatchClass = SPRRegListAsmOperand;
355 let PrintMethod = "printRegisterList";
358 // An operand for the CONSTPOOL_ENTRY pseudo-instruction.
359 def cpinst_operand : Operand<i32> {
360 let PrintMethod = "printCPInstOperand";
364 def pclabel : Operand<i32> {
365 let PrintMethod = "printPCLabel";
368 // ADR instruction labels.
369 def adrlabel : Operand<i32> {
370 let EncoderMethod = "getAdrLabelOpValue";
373 def neon_vcvt_imm32 : Operand<i32> {
374 let EncoderMethod = "getNEONVcvtImm32OpValue";
377 // rot_imm: An integer that encodes a rotate amount. Must be 8, 16, or 24.
378 def rot_imm : Operand<i32>, PatLeaf<(i32 imm), [{
379 int32_t v = (int32_t)N->getZExtValue();
380 return v == 8 || v == 16 || v == 24; }]> {
381 let EncoderMethod = "getRotImmOpValue";
384 // shift_imm: An integer that encodes a shift amount and the type of shift
385 // (currently either asr or lsl) using the same encoding used for the
386 // immediates in so_reg operands.
387 def shift_imm : Operand<i32> {
388 let PrintMethod = "printShiftImmOperand";
391 // shifter_operand operands: so_reg and so_imm.
392 def so_reg : Operand<i32>, // reg reg imm
393 ComplexPattern<i32, 3, "SelectShifterOperandReg",
394 [shl,srl,sra,rotr]> {
395 let EncoderMethod = "getSORegOpValue";
396 let PrintMethod = "printSORegOperand";
397 let MIOperandInfo = (ops GPR, GPR, i32imm);
399 def shift_so_reg : Operand<i32>, // reg reg imm
400 ComplexPattern<i32, 3, "SelectShiftShifterOperandReg",
401 [shl,srl,sra,rotr]> {
402 let EncoderMethod = "getSORegOpValue";
403 let PrintMethod = "printSORegOperand";
404 let MIOperandInfo = (ops GPR, GPR, i32imm);
407 // so_imm - Match a 32-bit shifter_operand immediate operand, which is an
408 // 8-bit immediate rotated by an arbitrary number of bits.
409 def so_imm : Operand<i32>, PatLeaf<(imm), [{ return Pred_so_imm(N); }]> {
410 let EncoderMethod = "getSOImmOpValue";
411 let PrintMethod = "printSOImmOperand";
414 // Break so_imm's up into two pieces. This handles immediates with up to 16
415 // bits set in them. This uses so_imm2part to match and so_imm2part_[12] to
416 // get the first/second pieces.
417 def so_imm2part : PatLeaf<(imm), [{
418 return ARM_AM::isSOImmTwoPartVal((unsigned)N->getZExtValue());
421 /// arm_i32imm - True for +V6T2, or true only if so_imm2part is true.
423 def arm_i32imm : PatLeaf<(imm), [{
424 if (Subtarget->hasV6T2Ops())
426 return ARM_AM::isSOImmTwoPartVal((unsigned)N->getZExtValue());
429 /// imm0_31 predicate - True if the 32-bit immediate is in the range [0,31].
430 def imm0_31 : Operand<i32>, PatLeaf<(imm), [{
431 return (int32_t)N->getZExtValue() < 32;
434 /// imm0_31_m1 - Matches and prints like imm0_31, but encodes as 'value - 1'.
435 def imm0_31_m1 : Operand<i32>, PatLeaf<(imm), [{
436 return (int32_t)N->getZExtValue() < 32;
438 let EncoderMethod = "getImmMinusOneOpValue";
441 // i32imm_hilo16 - For movt/movw - sets the MC Encoder method.
442 // The imm is split into imm{15-12}, imm{11-0}
444 def i32imm_hilo16 : Operand<i32> {
445 let EncoderMethod = "getHiLo16ImmOpValue";
448 /// bf_inv_mask_imm predicate - An AND mask to clear an arbitrary width bitfield
450 def bf_inv_mask_imm : Operand<i32>,
452 return ARM::isBitFieldInvertedMask(N->getZExtValue());
454 let EncoderMethod = "getBitfieldInvertedMaskOpValue";
455 let PrintMethod = "printBitfieldInvMaskImmOperand";
458 /// lsb_pos_imm - position of the lsb bit, used by BFI4p and t2BFI4p
459 def lsb_pos_imm : Operand<i32>, PatLeaf<(imm), [{
460 return isInt<5>(N->getSExtValue());
463 /// width_imm - number of bits to be copied, used by BFI4p and t2BFI4p
464 def width_imm : Operand<i32>, PatLeaf<(imm), [{
465 return N->getSExtValue() > 0 && N->getSExtValue() <= 32;
467 let EncoderMethod = "getMsbOpValue";
470 // Define ARM specific addressing modes.
473 // addrmode_imm12 := reg +/- imm12
475 def addrmode_imm12 : Operand<i32>,
476 ComplexPattern<i32, 2, "SelectAddrModeImm12", []> {
477 // 12-bit immediate operand. Note that instructions using this encode
478 // #0 and #-0 differently. We flag #-0 as the magic value INT32_MIN. All other
479 // immediate values are as normal.
481 let EncoderMethod = "getAddrModeImm12OpValue";
482 let PrintMethod = "printAddrModeImm12Operand";
483 let MIOperandInfo = (ops GPR:$base, i32imm:$offsimm);
485 // ldst_so_reg := reg +/- reg shop imm
487 def ldst_so_reg : Operand<i32>,
488 ComplexPattern<i32, 3, "SelectLdStSOReg", []> {
489 let EncoderMethod = "getLdStSORegOpValue";
490 // FIXME: Simplify the printer
491 let PrintMethod = "printAddrMode2Operand";
492 let MIOperandInfo = (ops GPR:$base, GPR:$offsreg, i32imm:$offsimm);
495 // addrmode2 := reg +/- imm12
496 // := reg +/- reg shop imm
498 def addrmode2 : Operand<i32>,
499 ComplexPattern<i32, 3, "SelectAddrMode2", []> {
500 let EncoderMethod = "getAddrMode2OpValue";
501 let PrintMethod = "printAddrMode2Operand";
502 let MIOperandInfo = (ops GPR:$base, GPR:$offsreg, i32imm:$offsimm);
505 def am2offset : Operand<i32>,
506 ComplexPattern<i32, 2, "SelectAddrMode2Offset",
507 [], [SDNPWantRoot]> {
508 let EncoderMethod = "getAddrMode2OffsetOpValue";
509 let PrintMethod = "printAddrMode2OffsetOperand";
510 let MIOperandInfo = (ops GPR, i32imm);
513 // addrmode3 := reg +/- reg
514 // addrmode3 := reg +/- imm8
516 def addrmode3 : Operand<i32>,
517 ComplexPattern<i32, 3, "SelectAddrMode3", []> {
518 let EncoderMethod = "getAddrMode3OpValue";
519 let PrintMethod = "printAddrMode3Operand";
520 let MIOperandInfo = (ops GPR:$base, GPR:$offsreg, i32imm:$offsimm);
523 def am3offset : Operand<i32>,
524 ComplexPattern<i32, 2, "SelectAddrMode3Offset",
525 [], [SDNPWantRoot]> {
526 let EncoderMethod = "getAddrMode3OffsetOpValue";
527 let PrintMethod = "printAddrMode3OffsetOperand";
528 let MIOperandInfo = (ops GPR, i32imm);
531 // ldstm_mode := {ia, ib, da, db}
533 def ldstm_mode : OptionalDefOperand<OtherVT, (ops i32), (ops (i32 1))> {
534 let EncoderMethod = "getLdStmModeOpValue";
535 let PrintMethod = "printLdStmModeOperand";
538 def MemMode5AsmOperand : AsmOperandClass {
539 let Name = "MemMode5";
540 let SuperClasses = [];
543 // addrmode5 := reg +/- imm8*4
545 def addrmode5 : Operand<i32>,
546 ComplexPattern<i32, 2, "SelectAddrMode5", []> {
547 let PrintMethod = "printAddrMode5Operand";
548 let MIOperandInfo = (ops GPR:$base, i32imm);
549 let ParserMatchClass = MemMode5AsmOperand;
550 let EncoderMethod = "getAddrMode5OpValue";
553 // addrmode6 := reg with optional alignment
555 def addrmode6 : Operand<i32>,
556 ComplexPattern<i32, 2, "SelectAddrMode6", [], [SDNPWantParent]>{
557 let PrintMethod = "printAddrMode6Operand";
558 let MIOperandInfo = (ops GPR:$addr, i32imm);
559 let EncoderMethod = "getAddrMode6AddressOpValue";
562 def am6offset : Operand<i32>,
563 ComplexPattern<i32, 1, "SelectAddrMode6Offset",
564 [], [SDNPWantRoot]> {
565 let PrintMethod = "printAddrMode6OffsetOperand";
566 let MIOperandInfo = (ops GPR);
567 let EncoderMethod = "getAddrMode6OffsetOpValue";
570 // Special version of addrmode6 to handle alignment encoding for VLD-dup
571 // instructions, specifically VLD4-dup.
572 def addrmode6dup : Operand<i32>,
573 ComplexPattern<i32, 2, "SelectAddrMode6", [], [SDNPWantParent]>{
574 let PrintMethod = "printAddrMode6Operand";
575 let MIOperandInfo = (ops GPR:$addr, i32imm);
576 let EncoderMethod = "getAddrMode6DupAddressOpValue";
579 // addrmodepc := pc + reg
581 def addrmodepc : Operand<i32>,
582 ComplexPattern<i32, 2, "SelectAddrModePC", []> {
583 let PrintMethod = "printAddrModePCOperand";
584 let MIOperandInfo = (ops GPR, i32imm);
587 def nohash_imm : Operand<i32> {
588 let PrintMethod = "printNoHashImmediate";
591 def CoprocNumAsmOperand : AsmOperandClass {
592 let Name = "CoprocNum";
593 let SuperClasses = [];
594 let ParserMethod = "tryParseCoprocNumOperand";
597 def CoprocRegAsmOperand : AsmOperandClass {
598 let Name = "CoprocReg";
599 let SuperClasses = [];
600 let ParserMethod = "tryParseCoprocRegOperand";
603 def p_imm : Operand<i32> {
604 let PrintMethod = "printPImmediate";
605 let ParserMatchClass = CoprocNumAsmOperand;
608 def c_imm : Operand<i32> {
609 let PrintMethod = "printCImmediate";
610 let ParserMatchClass = CoprocRegAsmOperand;
613 //===----------------------------------------------------------------------===//
615 include "ARMInstrFormats.td"
617 //===----------------------------------------------------------------------===//
618 // Multiclass helpers...
621 /// AsI1_bin_irs - Defines a set of (op r, {so_imm|r|so_reg}) patterns for a
622 /// binop that produces a value.
623 multiclass AsI1_bin_irs<bits<4> opcod, string opc,
624 InstrItinClass iii, InstrItinClass iir, InstrItinClass iis,
625 PatFrag opnode, bit Commutable = 0> {
626 // The register-immediate version is re-materializable. This is useful
627 // in particular for taking the address of a local.
628 let isReMaterializable = 1 in {
629 def ri : AsI1<opcod, (outs GPR:$Rd), (ins GPR:$Rn, so_imm:$imm), DPFrm,
630 iii, opc, "\t$Rd, $Rn, $imm",
631 [(set GPR:$Rd, (opnode GPR:$Rn, so_imm:$imm))]> {
636 let Inst{19-16} = Rn;
637 let Inst{15-12} = Rd;
638 let Inst{11-0} = imm;
641 def rr : AsI1<opcod, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm), DPFrm,
642 iir, opc, "\t$Rd, $Rn, $Rm",
643 [(set GPR:$Rd, (opnode GPR:$Rn, GPR:$Rm))]> {
648 let isCommutable = Commutable;
649 let Inst{19-16} = Rn;
650 let Inst{15-12} = Rd;
651 let Inst{11-4} = 0b00000000;
654 def rs : AsI1<opcod, (outs GPR:$Rd), (ins GPR:$Rn, so_reg:$shift), DPSoRegFrm,
655 iis, opc, "\t$Rd, $Rn, $shift",
656 [(set GPR:$Rd, (opnode GPR:$Rn, so_reg:$shift))]> {
661 let Inst{19-16} = Rn;
662 let Inst{15-12} = Rd;
663 let Inst{11-0} = shift;
667 /// AI1_bin_s_irs - Similar to AsI1_bin_irs except it sets the 's' bit so the
668 /// instruction modifies the CPSR register.
669 let isCodeGenOnly = 1, Defs = [CPSR] in {
670 multiclass AI1_bin_s_irs<bits<4> opcod, string opc,
671 InstrItinClass iii, InstrItinClass iir, InstrItinClass iis,
672 PatFrag opnode, bit Commutable = 0> {
673 def ri : AI1<opcod, (outs GPR:$Rd), (ins GPR:$Rn, so_imm:$imm), DPFrm,
674 iii, opc, "\t$Rd, $Rn, $imm",
675 [(set GPR:$Rd, (opnode GPR:$Rn, so_imm:$imm))]> {
681 let Inst{19-16} = Rn;
682 let Inst{15-12} = Rd;
683 let Inst{11-0} = imm;
685 def rr : AI1<opcod, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm), DPFrm,
686 iir, opc, "\t$Rd, $Rn, $Rm",
687 [(set GPR:$Rd, (opnode GPR:$Rn, GPR:$Rm))]> {
691 let isCommutable = Commutable;
694 let Inst{19-16} = Rn;
695 let Inst{15-12} = Rd;
696 let Inst{11-4} = 0b00000000;
699 def rs : AI1<opcod, (outs GPR:$Rd), (ins GPR:$Rn, so_reg:$shift), DPSoRegFrm,
700 iis, opc, "\t$Rd, $Rn, $shift",
701 [(set GPR:$Rd, (opnode GPR:$Rn, so_reg:$shift))]> {
707 let Inst{19-16} = Rn;
708 let Inst{15-12} = Rd;
709 let Inst{11-0} = shift;
714 /// AI1_cmp_irs - Defines a set of (op r, {so_imm|r|so_reg}) cmp / test
715 /// patterns. Similar to AsI1_bin_irs except the instruction does not produce
716 /// a explicit result, only implicitly set CPSR.
717 let isCompare = 1, Defs = [CPSR] in {
718 multiclass AI1_cmp_irs<bits<4> opcod, string opc,
719 InstrItinClass iii, InstrItinClass iir, InstrItinClass iis,
720 PatFrag opnode, bit Commutable = 0> {
721 def ri : AI1<opcod, (outs), (ins GPR:$Rn, so_imm:$imm), DPFrm, iii,
723 [(opnode GPR:$Rn, so_imm:$imm)]> {
728 let Inst{19-16} = Rn;
729 let Inst{15-12} = 0b0000;
730 let Inst{11-0} = imm;
732 def rr : AI1<opcod, (outs), (ins GPR:$Rn, GPR:$Rm), DPFrm, iir,
734 [(opnode GPR:$Rn, GPR:$Rm)]> {
737 let isCommutable = Commutable;
740 let Inst{19-16} = Rn;
741 let Inst{15-12} = 0b0000;
742 let Inst{11-4} = 0b00000000;
745 def rs : AI1<opcod, (outs), (ins GPR:$Rn, so_reg:$shift), DPSoRegFrm, iis,
746 opc, "\t$Rn, $shift",
747 [(opnode GPR:$Rn, so_reg:$shift)]> {
752 let Inst{19-16} = Rn;
753 let Inst{15-12} = 0b0000;
754 let Inst{11-0} = shift;
759 /// AI_ext_rrot - A unary operation with two forms: one whose operand is a
760 /// register and one whose operand is a register rotated by 8/16/24.
761 /// FIXME: Remove the 'r' variant. Its rot_imm is zero.
762 multiclass AI_ext_rrot<bits<8> opcod, string opc, PatFrag opnode> {
763 def r : AExtI<opcod, (outs GPR:$Rd), (ins GPR:$Rm),
764 IIC_iEXTr, opc, "\t$Rd, $Rm",
765 [(set GPR:$Rd, (opnode GPR:$Rm))]>,
766 Requires<[IsARM, HasV6]> {
769 let Inst{19-16} = 0b1111;
770 let Inst{15-12} = Rd;
771 let Inst{11-10} = 0b00;
774 def r_rot : AExtI<opcod, (outs GPR:$Rd), (ins GPR:$Rm, rot_imm:$rot),
775 IIC_iEXTr, opc, "\t$Rd, $Rm, ror $rot",
776 [(set GPR:$Rd, (opnode (rotr GPR:$Rm, rot_imm:$rot)))]>,
777 Requires<[IsARM, HasV6]> {
781 let Inst{19-16} = 0b1111;
782 let Inst{15-12} = Rd;
783 let Inst{11-10} = rot;
788 multiclass AI_ext_rrot_np<bits<8> opcod, string opc> {
789 def r : AExtI<opcod, (outs GPR:$Rd), (ins GPR:$Rm),
790 IIC_iEXTr, opc, "\t$Rd, $Rm",
791 [/* For disassembly only; pattern left blank */]>,
792 Requires<[IsARM, HasV6]> {
793 let Inst{19-16} = 0b1111;
794 let Inst{11-10} = 0b00;
796 def r_rot : AExtI<opcod, (outs GPR:$Rd), (ins GPR:$Rm, rot_imm:$rot),
797 IIC_iEXTr, opc, "\t$Rd, $Rm, ror $rot",
798 [/* For disassembly only; pattern left blank */]>,
799 Requires<[IsARM, HasV6]> {
801 let Inst{19-16} = 0b1111;
802 let Inst{11-10} = rot;
806 /// AI_exta_rrot - A binary operation with two forms: one whose operand is a
807 /// register and one whose operand is a register rotated by 8/16/24.
808 multiclass AI_exta_rrot<bits<8> opcod, string opc, PatFrag opnode> {
809 def rr : AExtI<opcod, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm),
810 IIC_iEXTAr, opc, "\t$Rd, $Rn, $Rm",
811 [(set GPR:$Rd, (opnode GPR:$Rn, GPR:$Rm))]>,
812 Requires<[IsARM, HasV6]> {
816 let Inst{19-16} = Rn;
817 let Inst{15-12} = Rd;
818 let Inst{11-10} = 0b00;
819 let Inst{9-4} = 0b000111;
822 def rr_rot : AExtI<opcod, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm,
824 IIC_iEXTAr, opc, "\t$Rd, $Rn, $Rm, ror $rot",
825 [(set GPR:$Rd, (opnode GPR:$Rn,
826 (rotr GPR:$Rm, rot_imm:$rot)))]>,
827 Requires<[IsARM, HasV6]> {
832 let Inst{19-16} = Rn;
833 let Inst{15-12} = Rd;
834 let Inst{11-10} = rot;
835 let Inst{9-4} = 0b000111;
840 // For disassembly only.
841 multiclass AI_exta_rrot_np<bits<8> opcod, string opc> {
842 def rr : AExtI<opcod, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm),
843 IIC_iEXTAr, opc, "\t$Rd, $Rn, $Rm",
844 [/* For disassembly only; pattern left blank */]>,
845 Requires<[IsARM, HasV6]> {
846 let Inst{11-10} = 0b00;
848 def rr_rot : AExtI<opcod, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm,
850 IIC_iEXTAr, opc, "\t$Rd, $Rn, $Rm, ror $rot",
851 [/* For disassembly only; pattern left blank */]>,
852 Requires<[IsARM, HasV6]> {
855 let Inst{19-16} = Rn;
856 let Inst{11-10} = rot;
860 /// AI1_adde_sube_irs - Define instructions and patterns for adde and sube.
861 let Uses = [CPSR] in {
862 multiclass AI1_adde_sube_irs<bits<4> opcod, string opc, PatFrag opnode,
863 bit Commutable = 0> {
864 def ri : AsI1<opcod, (outs GPR:$Rd), (ins GPR:$Rn, so_imm:$imm),
865 DPFrm, IIC_iALUi, opc, "\t$Rd, $Rn, $imm",
866 [(set GPR:$Rd, (opnode GPR:$Rn, so_imm:$imm))]>,
872 let Inst{15-12} = Rd;
873 let Inst{19-16} = Rn;
874 let Inst{11-0} = imm;
876 def rr : AsI1<opcod, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm),
877 DPFrm, IIC_iALUr, opc, "\t$Rd, $Rn, $Rm",
878 [(set GPR:$Rd, (opnode GPR:$Rn, GPR:$Rm))]>,
883 let Inst{11-4} = 0b00000000;
885 let isCommutable = Commutable;
887 let Inst{15-12} = Rd;
888 let Inst{19-16} = Rn;
890 def rs : AsI1<opcod, (outs GPR:$Rd), (ins GPR:$Rn, so_reg:$shift),
891 DPSoRegFrm, IIC_iALUsr, opc, "\t$Rd, $Rn, $shift",
892 [(set GPR:$Rd, (opnode GPR:$Rn, so_reg:$shift))]>,
898 let Inst{11-0} = shift;
899 let Inst{15-12} = Rd;
900 let Inst{19-16} = Rn;
903 // Carry setting variants
904 let isCodeGenOnly = 1, Defs = [CPSR] in {
905 multiclass AI1_adde_sube_s_irs<bits<4> opcod, string opc, PatFrag opnode,
906 bit Commutable = 0> {
907 def Sri : AXI1<opcod, (outs GPR:$Rd), (ins GPR:$Rn, so_imm:$imm),
908 DPFrm, IIC_iALUi, !strconcat(opc, "\t$Rd, $Rn, $imm"),
909 [(set GPR:$Rd, (opnode GPR:$Rn, so_imm:$imm))]>,
914 let Inst{15-12} = Rd;
915 let Inst{19-16} = Rn;
916 let Inst{11-0} = imm;
920 def Srr : AXI1<opcod, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm),
921 DPFrm, IIC_iALUr, !strconcat(opc, "\t$Rd, $Rn, $Rm"),
922 [(set GPR:$Rd, (opnode GPR:$Rn, GPR:$Rm))]>,
927 let Inst{11-4} = 0b00000000;
928 let isCommutable = Commutable;
930 let Inst{15-12} = Rd;
931 let Inst{19-16} = Rn;
935 def Srs : AXI1<opcod, (outs GPR:$Rd), (ins GPR:$Rn, so_reg:$shift),
936 DPSoRegFrm, IIC_iALUsr, !strconcat(opc, "\t$Rd, $Rn, $shift"),
937 [(set GPR:$Rd, (opnode GPR:$Rn, so_reg:$shift))]>,
942 let Inst{11-0} = shift;
943 let Inst{15-12} = Rd;
944 let Inst{19-16} = Rn;
952 let canFoldAsLoad = 1, isReMaterializable = 1 in {
953 multiclass AI_ldr1<bit isByte, string opc, InstrItinClass iii,
954 InstrItinClass iir, PatFrag opnode> {
955 // Note: We use the complex addrmode_imm12 rather than just an input
956 // GPR and a constrained immediate so that we can use this to match
957 // frame index references and avoid matching constant pool references.
958 def i12: AI2ldst<0b010, 1, isByte, (outs GPR:$Rt), (ins addrmode_imm12:$addr),
959 AddrMode_i12, LdFrm, iii, opc, "\t$Rt, $addr",
960 [(set GPR:$Rt, (opnode addrmode_imm12:$addr))]> {
963 let Inst{23} = addr{12}; // U (add = ('U' == 1))
964 let Inst{19-16} = addr{16-13}; // Rn
965 let Inst{15-12} = Rt;
966 let Inst{11-0} = addr{11-0}; // imm12
968 def rs : AI2ldst<0b011, 1, isByte, (outs GPR:$Rt), (ins ldst_so_reg:$shift),
969 AddrModeNone, LdFrm, iir, opc, "\t$Rt, $shift",
970 [(set GPR:$Rt, (opnode ldst_so_reg:$shift))]> {
973 let Inst{23} = shift{12}; // U (add = ('U' == 1))
974 let Inst{19-16} = shift{16-13}; // Rn
975 let Inst{15-12} = Rt;
976 let Inst{11-0} = shift{11-0};
981 multiclass AI_str1<bit isByte, string opc, InstrItinClass iii,
982 InstrItinClass iir, PatFrag opnode> {
983 // Note: We use the complex addrmode_imm12 rather than just an input
984 // GPR and a constrained immediate so that we can use this to match
985 // frame index references and avoid matching constant pool references.
986 def i12 : AI2ldst<0b010, 0, isByte, (outs),
987 (ins GPR:$Rt, addrmode_imm12:$addr),
988 AddrMode_i12, StFrm, iii, opc, "\t$Rt, $addr",
989 [(opnode GPR:$Rt, addrmode_imm12:$addr)]> {
992 let Inst{23} = addr{12}; // U (add = ('U' == 1))
993 let Inst{19-16} = addr{16-13}; // Rn
994 let Inst{15-12} = Rt;
995 let Inst{11-0} = addr{11-0}; // imm12
997 def rs : AI2ldst<0b011, 0, isByte, (outs), (ins GPR:$Rt, ldst_so_reg:$shift),
998 AddrModeNone, StFrm, iir, opc, "\t$Rt, $shift",
999 [(opnode GPR:$Rt, ldst_so_reg:$shift)]> {
1002 let Inst{23} = shift{12}; // U (add = ('U' == 1))
1003 let Inst{19-16} = shift{16-13}; // Rn
1004 let Inst{15-12} = Rt;
1005 let Inst{11-0} = shift{11-0};
1008 //===----------------------------------------------------------------------===//
1010 //===----------------------------------------------------------------------===//
1012 //===----------------------------------------------------------------------===//
1013 // Miscellaneous Instructions.
1016 /// CONSTPOOL_ENTRY - This instruction represents a floating constant pool in
1017 /// the function. The first operand is the ID# for this instruction, the second
1018 /// is the index into the MachineConstantPool that this is, the third is the
1019 /// size in bytes of this constant pool entry.
1020 let neverHasSideEffects = 1, isNotDuplicable = 1 in
1021 def CONSTPOOL_ENTRY :
1022 PseudoInst<(outs), (ins cpinst_operand:$instid, cpinst_operand:$cpidx,
1023 i32imm:$size), NoItinerary, []>;
1025 // FIXME: Marking these as hasSideEffects is necessary to prevent machine DCE
1026 // from removing one half of the matched pairs. That breaks PEI, which assumes
1027 // these will always be in pairs, and asserts if it finds otherwise. Better way?
1028 let Defs = [SP], Uses = [SP], hasSideEffects = 1 in {
1029 def ADJCALLSTACKUP :
1030 PseudoInst<(outs), (ins i32imm:$amt1, i32imm:$amt2, pred:$p), NoItinerary,
1031 [(ARMcallseq_end timm:$amt1, timm:$amt2)]>;
1033 def ADJCALLSTACKDOWN :
1034 PseudoInst<(outs), (ins i32imm:$amt, pred:$p), NoItinerary,
1035 [(ARMcallseq_start timm:$amt)]>;
1038 def NOP : AI<(outs), (ins), MiscFrm, NoItinerary, "nop", "",
1039 [/* For disassembly only; pattern left blank */]>,
1040 Requires<[IsARM, HasV6T2]> {
1041 let Inst{27-16} = 0b001100100000;
1042 let Inst{15-8} = 0b11110000;
1043 let Inst{7-0} = 0b00000000;
1046 def YIELD : AI<(outs), (ins), MiscFrm, NoItinerary, "yield", "",
1047 [/* For disassembly only; pattern left blank */]>,
1048 Requires<[IsARM, HasV6T2]> {
1049 let Inst{27-16} = 0b001100100000;
1050 let Inst{15-8} = 0b11110000;
1051 let Inst{7-0} = 0b00000001;
1054 def WFE : AI<(outs), (ins), MiscFrm, NoItinerary, "wfe", "",
1055 [/* For disassembly only; pattern left blank */]>,
1056 Requires<[IsARM, HasV6T2]> {
1057 let Inst{27-16} = 0b001100100000;
1058 let Inst{15-8} = 0b11110000;
1059 let Inst{7-0} = 0b00000010;
1062 def WFI : AI<(outs), (ins), MiscFrm, NoItinerary, "wfi", "",
1063 [/* For disassembly only; pattern left blank */]>,
1064 Requires<[IsARM, HasV6T2]> {
1065 let Inst{27-16} = 0b001100100000;
1066 let Inst{15-8} = 0b11110000;
1067 let Inst{7-0} = 0b00000011;
1070 def SEL : AI<(outs GPR:$dst), (ins GPR:$a, GPR:$b), DPFrm, NoItinerary, "sel",
1072 [/* For disassembly only; pattern left blank */]>,
1073 Requires<[IsARM, HasV6]> {
1078 let Inst{15-12} = Rd;
1079 let Inst{19-16} = Rn;
1080 let Inst{27-20} = 0b01101000;
1081 let Inst{7-4} = 0b1011;
1082 let Inst{11-8} = 0b1111;
1085 def SEV : AI<(outs), (ins), MiscFrm, NoItinerary, "sev", "",
1086 [/* For disassembly only; pattern left blank */]>,
1087 Requires<[IsARM, HasV6T2]> {
1088 let Inst{27-16} = 0b001100100000;
1089 let Inst{15-8} = 0b11110000;
1090 let Inst{7-0} = 0b00000100;
1093 // The i32imm operand $val can be used by a debugger to store more information
1094 // about the breakpoint.
1095 def BKPT : AI<(outs), (ins i32imm:$val), MiscFrm, NoItinerary, "bkpt", "\t$val",
1096 [/* For disassembly only; pattern left blank */]>,
1099 let Inst{3-0} = val{3-0};
1100 let Inst{19-8} = val{15-4};
1101 let Inst{27-20} = 0b00010010;
1102 let Inst{7-4} = 0b0111;
1105 // Change Processor State is a system instruction -- for disassembly and
1107 // FIXME: Since the asm parser has currently no clean way to handle optional
1108 // operands, create 3 versions of the same instruction. Once there's a clean
1109 // framework to represent optional operands, change this behavior.
1110 class CPS<dag iops, string asm_ops>
1111 : AXI<(outs), iops, MiscFrm, NoItinerary, !strconcat("cps", asm_ops),
1112 [/* For disassembly only; pattern left blank */]>, Requires<[IsARM]> {
1118 let Inst{31-28} = 0b1111;
1119 let Inst{27-20} = 0b00010000;
1120 let Inst{19-18} = imod;
1121 let Inst{17} = M; // Enabled if mode is set;
1123 let Inst{8-6} = iflags;
1125 let Inst{4-0} = mode;
1129 def CPS3p : CPS<(ins imod_op:$imod, iflags_op:$iflags, i32imm:$mode),
1130 "$imod\t$iflags, $mode">;
1131 let mode = 0, M = 0 in
1132 def CPS2p : CPS<(ins imod_op:$imod, iflags_op:$iflags), "$imod\t$iflags">;
1134 let imod = 0, iflags = 0, M = 1 in
1135 def CPS1p : CPS<(ins i32imm:$mode), "\t$mode">;
1137 // Preload signals the memory system of possible future data/instruction access.
1138 // These are for disassembly only.
1139 multiclass APreLoad<bits<1> read, bits<1> data, string opc> {
1141 def i12 : AXI<(outs), (ins addrmode_imm12:$addr), MiscFrm, IIC_Preload,
1142 !strconcat(opc, "\t$addr"),
1143 [(ARMPreload addrmode_imm12:$addr, (i32 read), (i32 data))]> {
1146 let Inst{31-26} = 0b111101;
1147 let Inst{25} = 0; // 0 for immediate form
1148 let Inst{24} = data;
1149 let Inst{23} = addr{12}; // U (add = ('U' == 1))
1150 let Inst{22} = read;
1151 let Inst{21-20} = 0b01;
1152 let Inst{19-16} = addr{16-13}; // Rn
1153 let Inst{15-12} = 0b1111;
1154 let Inst{11-0} = addr{11-0}; // imm12
1157 def rs : AXI<(outs), (ins ldst_so_reg:$shift), MiscFrm, IIC_Preload,
1158 !strconcat(opc, "\t$shift"),
1159 [(ARMPreload ldst_so_reg:$shift, (i32 read), (i32 data))]> {
1161 let Inst{31-26} = 0b111101;
1162 let Inst{25} = 1; // 1 for register form
1163 let Inst{24} = data;
1164 let Inst{23} = shift{12}; // U (add = ('U' == 1))
1165 let Inst{22} = read;
1166 let Inst{21-20} = 0b01;
1167 let Inst{19-16} = shift{16-13}; // Rn
1168 let Inst{15-12} = 0b1111;
1169 let Inst{11-0} = shift{11-0};
1173 defm PLD : APreLoad<1, 1, "pld">, Requires<[IsARM]>;
1174 defm PLDW : APreLoad<0, 1, "pldw">, Requires<[IsARM,HasV7,HasMP]>;
1175 defm PLI : APreLoad<1, 0, "pli">, Requires<[IsARM,HasV7]>;
1177 def SETEND : AXI<(outs),(ins setend_op:$end), MiscFrm, NoItinerary,
1179 [/* For disassembly only; pattern left blank */]>,
1182 let Inst{31-10} = 0b1111000100000001000000;
1187 def DBG : AI<(outs), (ins i32imm:$opt), MiscFrm, NoItinerary, "dbg", "\t$opt",
1188 [/* For disassembly only; pattern left blank */]>,
1189 Requires<[IsARM, HasV7]> {
1191 let Inst{27-4} = 0b001100100000111100001111;
1192 let Inst{3-0} = opt;
1195 // A5.4 Permanently UNDEFINED instructions.
1196 let isBarrier = 1, isTerminator = 1 in
1197 def TRAP : AXI<(outs), (ins), MiscFrm, NoItinerary,
1200 let Inst = 0xe7ffdefe;
1203 // Address computation and loads and stores in PIC mode.
1204 let isNotDuplicable = 1 in {
1205 def PICADD : ARMPseudoInst<(outs GPR:$dst), (ins GPR:$a, pclabel:$cp, pred:$p),
1206 Size4Bytes, IIC_iALUr,
1207 [(set GPR:$dst, (ARMpic_add GPR:$a, imm:$cp))]>;
1209 let AddedComplexity = 10 in {
1210 def PICLDR : ARMPseudoInst<(outs GPR:$dst), (ins addrmodepc:$addr, pred:$p),
1211 Size4Bytes, IIC_iLoad_r,
1212 [(set GPR:$dst, (load addrmodepc:$addr))]>;
1214 def PICLDRH : ARMPseudoInst<(outs GPR:$Rt), (ins addrmodepc:$addr, pred:$p),
1215 Size4Bytes, IIC_iLoad_bh_r,
1216 [(set GPR:$Rt, (zextloadi16 addrmodepc:$addr))]>;
1218 def PICLDRB : ARMPseudoInst<(outs GPR:$Rt), (ins addrmodepc:$addr, pred:$p),
1219 Size4Bytes, IIC_iLoad_bh_r,
1220 [(set GPR:$Rt, (zextloadi8 addrmodepc:$addr))]>;
1222 def PICLDRSH : ARMPseudoInst<(outs GPR:$Rt), (ins addrmodepc:$addr, pred:$p),
1223 Size4Bytes, IIC_iLoad_bh_r,
1224 [(set GPR:$Rt, (sextloadi16 addrmodepc:$addr))]>;
1226 def PICLDRSB : ARMPseudoInst<(outs GPR:$Rt), (ins addrmodepc:$addr, pred:$p),
1227 Size4Bytes, IIC_iLoad_bh_r,
1228 [(set GPR:$Rt, (sextloadi8 addrmodepc:$addr))]>;
1230 let AddedComplexity = 10 in {
1231 def PICSTR : ARMPseudoInst<(outs), (ins GPR:$src, addrmodepc:$addr, pred:$p),
1232 Size4Bytes, IIC_iStore_r, [(store GPR:$src, addrmodepc:$addr)]>;
1234 def PICSTRH : ARMPseudoInst<(outs), (ins GPR:$src, addrmodepc:$addr, pred:$p),
1235 Size4Bytes, IIC_iStore_bh_r, [(truncstorei16 GPR:$src,
1236 addrmodepc:$addr)]>;
1238 def PICSTRB : ARMPseudoInst<(outs), (ins GPR:$src, addrmodepc:$addr, pred:$p),
1239 Size4Bytes, IIC_iStore_bh_r, [(truncstorei8 GPR:$src, addrmodepc:$addr)]>;
1241 } // isNotDuplicable = 1
1244 // LEApcrel - Load a pc-relative address into a register without offending the
1246 let neverHasSideEffects = 1, isReMaterializable = 1 in
1247 // The 'adr' mnemonic encodes differently if the label is before or after
1248 // the instruction. The {24-21} opcode bits are set by the fixup, as we don't
1249 // know until then which form of the instruction will be used.
1250 def ADR : AI1<0, (outs GPR:$Rd), (ins adrlabel:$label),
1251 MiscFrm, IIC_iALUi, "adr", "\t$Rd, #$label", []> {
1254 let Inst{27-25} = 0b001;
1256 let Inst{19-16} = 0b1111;
1257 let Inst{15-12} = Rd;
1258 let Inst{11-0} = label;
1260 def LEApcrel : ARMPseudoInst<(outs GPR:$Rd), (ins i32imm:$label, pred:$p),
1261 Size4Bytes, IIC_iALUi, []>;
1263 def LEApcrelJT : ARMPseudoInst<(outs GPR:$Rd),
1264 (ins i32imm:$label, nohash_imm:$id, pred:$p),
1265 Size4Bytes, IIC_iALUi, []>;
1267 //===----------------------------------------------------------------------===//
1268 // Control Flow Instructions.
1271 let isReturn = 1, isTerminator = 1, isBarrier = 1 in {
1273 def BX_RET : AI<(outs), (ins), BrMiscFrm, IIC_Br,
1274 "bx", "\tlr", [(ARMretflag)]>,
1275 Requires<[IsARM, HasV4T]> {
1276 let Inst{27-0} = 0b0001001011111111111100011110;
1280 def MOVPCLR : AI<(outs), (ins), BrMiscFrm, IIC_Br,
1281 "mov", "\tpc, lr", [(ARMretflag)]>,
1282 Requires<[IsARM, NoV4T]> {
1283 let Inst{27-0} = 0b0001101000001111000000001110;
1287 // Indirect branches
1288 let isBranch = 1, isTerminator = 1, isBarrier = 1, isIndirectBranch = 1 in {
1290 def BX : AXI<(outs), (ins GPR:$dst), BrMiscFrm, IIC_Br, "bx\t$dst",
1291 [(brind GPR:$dst)]>,
1292 Requires<[IsARM, HasV4T]> {
1294 let Inst{31-4} = 0b1110000100101111111111110001;
1295 let Inst{3-0} = dst;
1299 // FIXME: We would really like to define this as a vanilla ARMPat like:
1300 // ARMPat<(brind GPR:$dst), (MOVr PC, GPR:$dst)>
1301 // With that, however, we can't set isBranch, isTerminator, etc..
1302 def MOVPCRX : ARMPseudoInst<(outs), (ins GPR:$dst),
1303 Size4Bytes, IIC_Br, [(brind GPR:$dst)]>,
1304 Requires<[IsARM, NoV4T]>;
1307 // All calls clobber the non-callee saved registers. SP is marked as
1308 // a use to prevent stack-pointer assignments that appear immediately
1309 // before calls from potentially appearing dead.
1311 // On non-Darwin platforms R9 is callee-saved.
1312 Defs = [R0, R1, R2, R3, R12, LR,
1313 D0, D1, D2, D3, D4, D5, D6, D7,
1314 D16, D17, D18, D19, D20, D21, D22, D23,
1315 D24, D25, D26, D27, D28, D29, D30, D31, CPSR, FPSCR],
1317 def BL : ABXI<0b1011, (outs), (ins bl_target:$func, variable_ops),
1318 IIC_Br, "bl\t$func",
1319 [(ARMcall tglobaladdr:$func)]>,
1320 Requires<[IsARM, IsNotDarwin]> {
1321 let Inst{31-28} = 0b1110;
1323 let Inst{23-0} = func;
1326 def BL_pred : ABI<0b1011, (outs), (ins bl_target:$func, variable_ops),
1327 IIC_Br, "bl", "\t$func",
1328 [(ARMcall_pred tglobaladdr:$func)]>,
1329 Requires<[IsARM, IsNotDarwin]> {
1331 let Inst{23-0} = func;
1335 def BLX : AXI<(outs), (ins GPR:$func, variable_ops), BrMiscFrm,
1336 IIC_Br, "blx\t$func",
1337 [(ARMcall GPR:$func)]>,
1338 Requires<[IsARM, HasV5T, IsNotDarwin]> {
1340 let Inst{31-4} = 0b1110000100101111111111110011;
1341 let Inst{3-0} = func;
1344 def BLX_pred : AI<(outs), (ins GPR:$func, variable_ops), BrMiscFrm,
1345 IIC_Br, "blx", "\t$func",
1346 [(ARMcall_pred GPR:$func)]>,
1347 Requires<[IsARM, HasV5T, IsNotDarwin]> {
1349 let Inst{27-4} = 0b000100101111111111110011;
1350 let Inst{3-0} = func;
1354 // Note: Restrict $func to the tGPR regclass to prevent it being in LR.
1355 def BX_CALL : ARMPseudoInst<(outs), (ins tGPR:$func, variable_ops),
1356 Size8Bytes, IIC_Br, [(ARMcall_nolink tGPR:$func)]>,
1357 Requires<[IsARM, HasV4T, IsNotDarwin]>;
1360 def BMOVPCRX_CALL : ARMPseudoInst<(outs), (ins tGPR:$func, variable_ops),
1361 Size8Bytes, IIC_Br, [(ARMcall_nolink tGPR:$func)]>,
1362 Requires<[IsARM, NoV4T, IsNotDarwin]>;
1366 // On Darwin R9 is call-clobbered.
1367 // R7 is marked as a use to prevent frame-pointer assignments from being
1368 // moved above / below calls.
1369 Defs = [R0, R1, R2, R3, R9, R12, LR,
1370 D0, D1, D2, D3, D4, D5, D6, D7,
1371 D16, D17, D18, D19, D20, D21, D22, D23,
1372 D24, D25, D26, D27, D28, D29, D30, D31, CPSR, FPSCR],
1373 Uses = [R7, SP] in {
1374 def BLr9 : ABXI<0b1011, (outs), (ins bltarget:$func, variable_ops),
1375 IIC_Br, "bl\t$func",
1376 [(ARMcall tglobaladdr:$func)]>, Requires<[IsARM, IsDarwin]> {
1377 let Inst{31-28} = 0b1110;
1379 let Inst{23-0} = func;
1382 def BLr9_pred : ABI<0b1011, (outs), (ins bltarget:$func, variable_ops),
1383 IIC_Br, "bl", "\t$func",
1384 [(ARMcall_pred tglobaladdr:$func)]>,
1385 Requires<[IsARM, IsDarwin]> {
1387 let Inst{23-0} = func;
1391 def BLXr9 : AXI<(outs), (ins GPR:$func, variable_ops), BrMiscFrm,
1392 IIC_Br, "blx\t$func",
1393 [(ARMcall GPR:$func)]>, Requires<[IsARM, HasV5T, IsDarwin]> {
1395 let Inst{31-4} = 0b1110000100101111111111110011;
1396 let Inst{3-0} = func;
1399 def BLXr9_pred : AI<(outs), (ins GPR:$func, variable_ops), BrMiscFrm,
1400 IIC_Br, "blx", "\t$func",
1401 [(ARMcall_pred GPR:$func)]>,
1402 Requires<[IsARM, HasV5T, IsDarwin]> {
1404 let Inst{27-4} = 0b000100101111111111110011;
1405 let Inst{3-0} = func;
1409 // Note: Restrict $func to the tGPR regclass to prevent it being in LR.
1410 def BXr9_CALL : ARMPseudoInst<(outs), (ins tGPR:$func, variable_ops),
1411 Size8Bytes, IIC_Br, [(ARMcall_nolink tGPR:$func)]>,
1412 Requires<[IsARM, HasV4T, IsDarwin]>;
1415 def BMOVPCRXr9_CALL : ARMPseudoInst<(outs), (ins tGPR:$func, variable_ops),
1416 Size8Bytes, IIC_Br, [(ARMcall_nolink tGPR:$func)]>,
1417 Requires<[IsARM, NoV4T, IsDarwin]>;
1422 // FIXME: These should probably be xformed into the non-TC versions of the
1423 // instructions as part of MC lowering.
1424 // FIXME: These seem to be used for both Thumb and ARM instruction selection.
1425 // Thumb should have its own version since the instruction is actually
1426 // different, even though the mnemonic is the same.
1427 let isCall = 1, isTerminator = 1, isReturn = 1, isBarrier = 1 in {
1429 let Defs = [R0, R1, R2, R3, R9, R12,
1430 D0, D1, D2, D3, D4, D5, D6, D7,
1431 D16, D17, D18, D19, D20, D21, D22, D23, D24, D25, D26,
1432 D27, D28, D29, D30, D31, PC],
1434 def TCRETURNdi : PseudoInst<(outs), (ins i32imm:$dst, variable_ops),
1435 IIC_Br, []>, Requires<[IsDarwin]>;
1437 def TCRETURNri : PseudoInst<(outs), (ins tcGPR:$dst, variable_ops),
1438 IIC_Br, []>, Requires<[IsDarwin]>;
1440 def TAILJMPd : ABXI<0b1010, (outs), (ins brtarget:$dst, variable_ops),
1441 IIC_Br, "b\t$dst @ TAILCALL",
1442 []>, Requires<[IsARM, IsDarwin]>;
1444 def TAILJMPdt: ABXI<0b1010, (outs), (ins brtarget:$dst, variable_ops),
1445 IIC_Br, "b.w\t$dst @ TAILCALL",
1446 []>, Requires<[IsThumb, IsDarwin]>;
1448 def TAILJMPr : AXI<(outs), (ins tcGPR:$dst, variable_ops),
1449 BrMiscFrm, IIC_Br, "bx\t$dst @ TAILCALL",
1450 []>, Requires<[IsDarwin]> {
1452 let Inst{31-4} = 0b1110000100101111111111110001;
1453 let Inst{3-0} = dst;
1457 // Non-Darwin versions (the difference is R9).
1458 let Defs = [R0, R1, R2, R3, R12,
1459 D0, D1, D2, D3, D4, D5, D6, D7,
1460 D16, D17, D18, D19, D20, D21, D22, D23, D24, D25, D26,
1461 D27, D28, D29, D30, D31, PC],
1463 def TCRETURNdiND : PseudoInst<(outs), (ins i32imm:$dst, variable_ops),
1464 IIC_Br, []>, Requires<[IsNotDarwin]>;
1466 def TCRETURNriND : PseudoInst<(outs), (ins tcGPR:$dst, variable_ops),
1467 IIC_Br, []>, Requires<[IsNotDarwin]>;
1469 def TAILJMPdND : ABXI<0b1010, (outs), (ins brtarget:$dst, variable_ops),
1470 IIC_Br, "b\t$dst @ TAILCALL",
1471 []>, Requires<[IsARM, IsNotDarwin]>;
1473 def TAILJMPdNDt : ABXI<0b1010, (outs), (ins brtarget:$dst, variable_ops),
1474 IIC_Br, "b.w\t$dst @ TAILCALL",
1475 []>, Requires<[IsThumb, IsNotDarwin]>;
1477 def TAILJMPrND : AXI<(outs), (ins tcGPR:$dst, variable_ops),
1478 BrMiscFrm, IIC_Br, "bx\t$dst @ TAILCALL",
1479 []>, Requires<[IsNotDarwin]> {
1481 let Inst{31-4} = 0b1110000100101111111111110001;
1482 let Inst{3-0} = dst;
1487 let isBranch = 1, isTerminator = 1 in {
1488 // B is "predicable" since it can be xformed into a Bcc.
1489 let isBarrier = 1 in {
1490 let isPredicable = 1 in
1491 def B : ABXI<0b1010, (outs), (ins brtarget:$target), IIC_Br,
1492 "b\t$target", [(br bb:$target)]> {
1494 let Inst{31-28} = 0b1110;
1495 let Inst{23-0} = target;
1498 let isNotDuplicable = 1, isIndirectBranch = 1 in {
1499 def BR_JTr : ARMPseudoInst<(outs),
1500 (ins GPR:$target, i32imm:$jt, i32imm:$id),
1501 SizeSpecial, IIC_Br,
1502 [(ARMbrjt GPR:$target, tjumptable:$jt, imm:$id)]>;
1503 // FIXME: This shouldn't use the generic "addrmode2," but rather be split
1504 // into i12 and rs suffixed versions.
1505 def BR_JTm : ARMPseudoInst<(outs),
1506 (ins addrmode2:$target, i32imm:$jt, i32imm:$id),
1507 SizeSpecial, IIC_Br,
1508 [(ARMbrjt (i32 (load addrmode2:$target)), tjumptable:$jt,
1510 def BR_JTadd : ARMPseudoInst<(outs),
1511 (ins GPR:$target, GPR:$idx, i32imm:$jt, i32imm:$id),
1512 SizeSpecial, IIC_Br,
1513 [(ARMbrjt (add GPR:$target, GPR:$idx), tjumptable:$jt,
1515 } // isNotDuplicable = 1, isIndirectBranch = 1
1518 // FIXME: should be able to write a pattern for ARMBrcond, but can't use
1519 // a two-value operand where a dag node expects two operands. :(
1520 def Bcc : ABI<0b1010, (outs), (ins br_target:$target),
1521 IIC_Br, "b", "\t$target",
1522 [/*(ARMbrcond bb:$target, imm:$cc, CCR:$ccr)*/]> {
1524 let Inst{23-0} = target;
1528 // Branch and Exchange Jazelle -- for disassembly only
1529 def BXJ : ABI<0b0001, (outs), (ins GPR:$func), NoItinerary, "bxj", "\t$func",
1530 [/* For disassembly only; pattern left blank */]> {
1531 let Inst{23-20} = 0b0010;
1532 //let Inst{19-8} = 0xfff;
1533 let Inst{7-4} = 0b0010;
1536 // Secure Monitor Call is a system instruction -- for disassembly only
1537 def SMC : ABI<0b0001, (outs), (ins i32imm:$opt), NoItinerary, "smc", "\t$opt",
1538 [/* For disassembly only; pattern left blank */]> {
1540 let Inst{23-4} = 0b01100000000000000111;
1541 let Inst{3-0} = opt;
1544 // Supervisor Call (Software Interrupt) -- for disassembly only
1545 let isCall = 1, Uses = [SP] in {
1546 def SVC : ABI<0b1111, (outs), (ins i32imm:$svc), IIC_Br, "svc", "\t$svc",
1547 [/* For disassembly only; pattern left blank */]> {
1549 let Inst{23-0} = svc;
1553 // Store Return State is a system instruction -- for disassembly only
1554 let isCodeGenOnly = 1 in { // FIXME: This should not use submode!
1555 def SRSW : ABXI<{1,0,0,?}, (outs), (ins ldstm_mode:$amode, i32imm:$mode),
1556 NoItinerary, "srs${amode}\tsp!, $mode",
1557 [/* For disassembly only; pattern left blank */]> {
1558 let Inst{31-28} = 0b1111;
1559 let Inst{22-20} = 0b110; // W = 1
1562 def SRS : ABXI<{1,0,0,?}, (outs), (ins ldstm_mode:$amode, i32imm:$mode),
1563 NoItinerary, "srs${amode}\tsp, $mode",
1564 [/* For disassembly only; pattern left blank */]> {
1565 let Inst{31-28} = 0b1111;
1566 let Inst{22-20} = 0b100; // W = 0
1569 // Return From Exception is a system instruction -- for disassembly only
1570 def RFEW : ABXI<{1,0,0,?}, (outs), (ins ldstm_mode:$amode, GPR:$base),
1571 NoItinerary, "rfe${amode}\t$base!",
1572 [/* For disassembly only; pattern left blank */]> {
1573 let Inst{31-28} = 0b1111;
1574 let Inst{22-20} = 0b011; // W = 1
1577 def RFE : ABXI<{1,0,0,?}, (outs), (ins ldstm_mode:$amode, GPR:$base),
1578 NoItinerary, "rfe${amode}\t$base",
1579 [/* For disassembly only; pattern left blank */]> {
1580 let Inst{31-28} = 0b1111;
1581 let Inst{22-20} = 0b001; // W = 0
1583 } // isCodeGenOnly = 1
1585 //===----------------------------------------------------------------------===//
1586 // Load / store Instructions.
1592 defm LDR : AI_ldr1<0, "ldr", IIC_iLoad_r, IIC_iLoad_si,
1593 UnOpFrag<(load node:$Src)>>;
1594 defm LDRB : AI_ldr1<1, "ldrb", IIC_iLoad_bh_r, IIC_iLoad_bh_si,
1595 UnOpFrag<(zextloadi8 node:$Src)>>;
1596 defm STR : AI_str1<0, "str", IIC_iStore_r, IIC_iStore_si,
1597 BinOpFrag<(store node:$LHS, node:$RHS)>>;
1598 defm STRB : AI_str1<1, "strb", IIC_iStore_bh_r, IIC_iStore_bh_si,
1599 BinOpFrag<(truncstorei8 node:$LHS, node:$RHS)>>;
1601 // Special LDR for loads from non-pc-relative constpools.
1602 let canFoldAsLoad = 1, mayLoad = 1, neverHasSideEffects = 1,
1603 isReMaterializable = 1 in
1604 def LDRcp : AI2ldst<0b010, 1, 0, (outs GPR:$Rt), (ins addrmode_imm12:$addr),
1605 AddrMode_i12, LdFrm, IIC_iLoad_r, "ldr", "\t$Rt, $addr",
1609 let Inst{23} = addr{12}; // U (add = ('U' == 1))
1610 let Inst{19-16} = 0b1111;
1611 let Inst{15-12} = Rt;
1612 let Inst{11-0} = addr{11-0}; // imm12
1615 // Loads with zero extension
1616 def LDRH : AI3ld<0b1011, 1, (outs GPR:$Rt), (ins addrmode3:$addr), LdMiscFrm,
1617 IIC_iLoad_bh_r, "ldrh", "\t$Rt, $addr",
1618 [(set GPR:$Rt, (zextloadi16 addrmode3:$addr))]>;
1620 // Loads with sign extension
1621 def LDRSH : AI3ld<0b1111, 1, (outs GPR:$Rt), (ins addrmode3:$addr), LdMiscFrm,
1622 IIC_iLoad_bh_r, "ldrsh", "\t$Rt, $addr",
1623 [(set GPR:$Rt, (sextloadi16 addrmode3:$addr))]>;
1625 def LDRSB : AI3ld<0b1101, 1, (outs GPR:$Rt), (ins addrmode3:$addr), LdMiscFrm,
1626 IIC_iLoad_bh_r, "ldrsb", "\t$Rt, $addr",
1627 [(set GPR:$Rt, (sextloadi8 addrmode3:$addr))]>;
1629 let mayLoad = 1, neverHasSideEffects = 1, hasExtraDefRegAllocReq = 1,
1630 isCodeGenOnly = 1 in { // $dst2 doesn't exist in asmstring?
1631 // FIXME: $dst2 isn't in the asm string as it's implied by $Rd (dst2 = Rd+1)
1632 // how to represent that such that tblgen is happy and we don't
1633 // mark this codegen only?
1635 def LDRD : AI3ld<0b1101, 0, (outs GPR:$Rd, GPR:$dst2),
1636 (ins addrmode3:$addr), LdMiscFrm,
1637 IIC_iLoad_d_r, "ldrd", "\t$Rd, $addr",
1638 []>, Requires<[IsARM, HasV5TE]>;
1642 multiclass AI2_ldridx<bit isByte, string opc, InstrItinClass itin> {
1643 def _PRE : AI2ldstidx<1, isByte, 1, (outs GPR:$Rt, GPR:$Rn_wb),
1644 (ins addrmode2:$addr), IndexModePre, LdFrm, itin,
1645 opc, "\t$Rt, $addr!", "$addr.base = $Rn_wb", []> {
1647 // {13} 1 == Rm, 0 == imm12
1651 let Inst{25} = addr{13};
1652 let Inst{23} = addr{12};
1653 let Inst{19-16} = addr{17-14};
1654 let Inst{11-0} = addr{11-0};
1656 def _POST : AI2ldstidx<1, isByte, 0, (outs GPR:$Rt, GPR:$Rn_wb),
1657 (ins GPR:$Rn, am2offset:$offset),
1658 IndexModePost, LdFrm, itin,
1659 opc, "\t$Rt, [$Rn], $offset", "$Rn = $Rn_wb", []> {
1660 // {13} 1 == Rm, 0 == imm12
1665 let Inst{25} = offset{13};
1666 let Inst{23} = offset{12};
1667 let Inst{19-16} = Rn;
1668 let Inst{11-0} = offset{11-0};
1672 let mayLoad = 1, neverHasSideEffects = 1 in {
1673 defm LDR : AI2_ldridx<0, "ldr", IIC_iLoad_ru>;
1674 defm LDRB : AI2_ldridx<1, "ldrb", IIC_iLoad_bh_ru>;
1677 multiclass AI3_ldridx<bits<4> op, bit op20, string opc, InstrItinClass itin> {
1678 def _PRE : AI3ldstidx<op, op20, 1, 1, (outs GPR:$Rt, GPR:$Rn_wb),
1679 (ins addrmode3:$addr), IndexModePre,
1681 opc, "\t$Rt, $addr!", "$addr.base = $Rn_wb", []> {
1683 let Inst{23} = addr{8}; // U bit
1684 let Inst{22} = addr{13}; // 1 == imm8, 0 == Rm
1685 let Inst{19-16} = addr{12-9}; // Rn
1686 let Inst{11-8} = addr{7-4}; // imm7_4/zero
1687 let Inst{3-0} = addr{3-0}; // imm3_0/Rm
1689 def _POST : AI3ldstidx<op, op20, 1, 0, (outs GPR:$Rt, GPR:$Rn_wb),
1690 (ins GPR:$Rn, am3offset:$offset), IndexModePost,
1692 opc, "\t$Rt, [$Rn], $offset", "$Rn = $Rn_wb", []> {
1695 let Inst{23} = offset{8}; // U bit
1696 let Inst{22} = offset{9}; // 1 == imm8, 0 == Rm
1697 let Inst{19-16} = Rn;
1698 let Inst{11-8} = offset{7-4}; // imm7_4/zero
1699 let Inst{3-0} = offset{3-0}; // imm3_0/Rm
1703 let mayLoad = 1, neverHasSideEffects = 1 in {
1704 defm LDRH : AI3_ldridx<0b1011, 1, "ldrh", IIC_iLoad_bh_ru>;
1705 defm LDRSH : AI3_ldridx<0b1111, 1, "ldrsh", IIC_iLoad_bh_ru>;
1706 defm LDRSB : AI3_ldridx<0b1101, 1, "ldrsb", IIC_iLoad_bh_ru>;
1707 let hasExtraDefRegAllocReq = 1, isCodeGenOnly = 1 in
1708 defm LDRD : AI3_ldridx<0b1101, 0, "ldrd", IIC_iLoad_d_ru>;
1709 } // mayLoad = 1, neverHasSideEffects = 1
1711 // LDRT, LDRBT, LDRSBT, LDRHT, LDRSHT are for disassembly only.
1712 let mayLoad = 1, neverHasSideEffects = 1 in {
1713 def LDRT : AI2ldstidx<1, 0, 0, (outs GPR:$dst, GPR:$base_wb),
1714 (ins GPR:$base, am2offset:$offset), IndexModeNone,
1715 LdFrm, IIC_iLoad_ru,
1716 "ldrt", "\t$dst, [$base], $offset", "$base = $base_wb", []> {
1717 let Inst{21} = 1; // overwrite
1719 def LDRBT : AI2ldstidx<1, 1, 0, (outs GPR:$dst, GPR:$base_wb),
1720 (ins GPR:$base, am2offset:$offset), IndexModeNone,
1721 LdFrm, IIC_iLoad_bh_ru,
1722 "ldrbt", "\t$dst, [$base], $offset", "$base = $base_wb", []> {
1723 let Inst{21} = 1; // overwrite
1725 def LDRSBT : AI3ldstidx<0b1101, 1, 1, 0, (outs GPR:$dst, GPR:$base_wb),
1726 (ins GPR:$base, am3offset:$offset), IndexModePost,
1727 LdMiscFrm, IIC_iLoad_bh_ru,
1728 "ldrsbt", "\t$dst, [$base], $offset", "$base = $base_wb", []> {
1729 let Inst{21} = 1; // overwrite
1731 def LDRHT : AI3ldstidx<0b1011, 1, 1, 0, (outs GPR:$dst, GPR:$base_wb),
1732 (ins GPR:$base, am3offset:$offset), IndexModePost,
1733 LdMiscFrm, IIC_iLoad_bh_ru,
1734 "ldrht", "\t$dst, [$base], $offset", "$base = $base_wb", []> {
1735 let Inst{21} = 1; // overwrite
1737 def LDRSHT : AI3ldstidx<0b1111, 1, 1, 0, (outs GPR:$dst, GPR:$base_wb),
1738 (ins GPR:$base, am3offset:$offset), IndexModePost,
1739 LdMiscFrm, IIC_iLoad_bh_ru,
1740 "ldrsht", "\t$dst, [$base], $offset", "$base = $base_wb", []> {
1741 let Inst{21} = 1; // overwrite
1747 // Stores with truncate
1748 def STRH : AI3str<0b1011, (outs), (ins GPR:$Rt, addrmode3:$addr), StMiscFrm,
1749 IIC_iStore_bh_r, "strh", "\t$Rt, $addr",
1750 [(truncstorei16 GPR:$Rt, addrmode3:$addr)]>;
1753 let mayStore = 1, neverHasSideEffects = 1, hasExtraSrcRegAllocReq = 1,
1754 isCodeGenOnly = 1 in // $src2 doesn't exist in asm string
1755 def STRD : AI3str<0b1111, (outs), (ins GPR:$src1, GPR:$src2, addrmode3:$addr),
1756 StMiscFrm, IIC_iStore_d_r,
1757 "strd", "\t$src1, $addr", []>, Requires<[IsARM, HasV5TE]>;
1760 def STR_PRE : AI2stridx<0, 1, (outs GPR:$Rn_wb),
1761 (ins GPR:$Rt, GPR:$Rn, am2offset:$offset),
1762 IndexModePre, StFrm, IIC_iStore_ru,
1763 "str", "\t$Rt, [$Rn, $offset]!", "$Rn = $Rn_wb",
1765 (pre_store GPR:$Rt, GPR:$Rn, am2offset:$offset))]>;
1767 def STR_POST : AI2stridx<0, 0, (outs GPR:$Rn_wb),
1768 (ins GPR:$Rt, GPR:$Rn, am2offset:$offset),
1769 IndexModePost, StFrm, IIC_iStore_ru,
1770 "str", "\t$Rt, [$Rn], $offset", "$Rn = $Rn_wb",
1772 (post_store GPR:$Rt, GPR:$Rn, am2offset:$offset))]>;
1774 def STRB_PRE : AI2stridx<1, 1, (outs GPR:$Rn_wb),
1775 (ins GPR:$Rt, GPR:$Rn, am2offset:$offset),
1776 IndexModePre, StFrm, IIC_iStore_bh_ru,
1777 "strb", "\t$Rt, [$Rn, $offset]!", "$Rn = $Rn_wb",
1778 [(set GPR:$Rn_wb, (pre_truncsti8 GPR:$Rt,
1779 GPR:$Rn, am2offset:$offset))]>;
1780 def STRB_POST: AI2stridx<1, 0, (outs GPR:$Rn_wb),
1781 (ins GPR:$Rt, GPR:$Rn, am2offset:$offset),
1782 IndexModePost, StFrm, IIC_iStore_bh_ru,
1783 "strb", "\t$Rt, [$Rn], $offset", "$Rn = $Rn_wb",
1784 [(set GPR:$Rn_wb, (post_truncsti8 GPR:$Rt,
1785 GPR:$Rn, am2offset:$offset))]>;
1787 def STRH_PRE : AI3stridx<0b1011, 0, 1, (outs GPR:$Rn_wb),
1788 (ins GPR:$Rt, GPR:$Rn, am3offset:$offset),
1789 IndexModePre, StMiscFrm, IIC_iStore_ru,
1790 "strh", "\t$Rt, [$Rn, $offset]!", "$Rn = $Rn_wb",
1792 (pre_truncsti16 GPR:$Rt, GPR:$Rn, am3offset:$offset))]>;
1794 def STRH_POST: AI3stridx<0b1011, 0, 0, (outs GPR:$Rn_wb),
1795 (ins GPR:$Rt, GPR:$Rn, am3offset:$offset),
1796 IndexModePost, StMiscFrm, IIC_iStore_bh_ru,
1797 "strh", "\t$Rt, [$Rn], $offset", "$Rn = $Rn_wb",
1798 [(set GPR:$Rn_wb, (post_truncsti16 GPR:$Rt,
1799 GPR:$Rn, am3offset:$offset))]>;
1801 // For disassembly only
1802 def STRD_PRE : AI3stdpr<(outs GPR:$base_wb),
1803 (ins GPR:$src1, GPR:$src2, GPR:$base, am3offset:$offset),
1804 StMiscFrm, IIC_iStore_d_ru,
1805 "strd", "\t$src1, $src2, [$base, $offset]!",
1806 "$base = $base_wb", []>;
1808 // For disassembly only
1809 def STRD_POST: AI3stdpo<(outs GPR:$base_wb),
1810 (ins GPR:$src1, GPR:$src2, GPR:$base, am3offset:$offset),
1811 StMiscFrm, IIC_iStore_d_ru,
1812 "strd", "\t$src1, $src2, [$base], $offset",
1813 "$base = $base_wb", []>;
1815 // STRT, STRBT, and STRHT are for disassembly only.
1817 def STRT : AI2stridx<0, 0, (outs GPR:$Rn_wb),
1818 (ins GPR:$Rt, GPR:$Rn,am2offset:$offset),
1819 IndexModeNone, StFrm, IIC_iStore_ru,
1820 "strt", "\t$Rt, [$Rn], $offset", "$Rn = $Rn_wb",
1821 [/* For disassembly only; pattern left blank */]> {
1822 let Inst{21} = 1; // overwrite
1825 def STRBT : AI2stridx<1, 0, (outs GPR:$Rn_wb),
1826 (ins GPR:$Rt, GPR:$Rn, am2offset:$offset),
1827 IndexModeNone, StFrm, IIC_iStore_bh_ru,
1828 "strbt", "\t$Rt, [$Rn], $offset", "$Rn = $Rn_wb",
1829 [/* For disassembly only; pattern left blank */]> {
1830 let Inst{21} = 1; // overwrite
1833 def STRHT: AI3sthpo<(outs GPR:$base_wb),
1834 (ins GPR:$src, GPR:$base,am3offset:$offset),
1835 StMiscFrm, IIC_iStore_bh_ru,
1836 "strht", "\t$src, [$base], $offset", "$base = $base_wb",
1837 [/* For disassembly only; pattern left blank */]> {
1838 let Inst{21} = 1; // overwrite
1841 //===----------------------------------------------------------------------===//
1842 // Load / store multiple Instructions.
1845 multiclass arm_ldst_mult<string asm, bit L_bit, Format f,
1846 InstrItinClass itin, InstrItinClass itin_upd> {
1848 AXI4<(outs), (ins GPR:$Rn, pred:$p, reglist:$regs, variable_ops),
1849 IndexModeNone, f, itin,
1850 !strconcat(asm, "ia${p}\t$Rn, $regs"), "", []> {
1851 let Inst{24-23} = 0b01; // Increment After
1852 let Inst{21} = 0; // No writeback
1853 let Inst{20} = L_bit;
1856 AXI4<(outs GPR:$wb), (ins GPR:$Rn, pred:$p, reglist:$regs, variable_ops),
1857 IndexModeUpd, f, itin_upd,
1858 !strconcat(asm, "ia${p}\t$Rn!, $regs"), "$Rn = $wb", []> {
1859 let Inst{24-23} = 0b01; // Increment After
1860 let Inst{21} = 1; // Writeback
1861 let Inst{20} = L_bit;
1864 AXI4<(outs), (ins GPR:$Rn, pred:$p, reglist:$regs, variable_ops),
1865 IndexModeNone, f, itin,
1866 !strconcat(asm, "da${p}\t$Rn, $regs"), "", []> {
1867 let Inst{24-23} = 0b00; // Decrement After
1868 let Inst{21} = 0; // No writeback
1869 let Inst{20} = L_bit;
1872 AXI4<(outs GPR:$wb), (ins GPR:$Rn, pred:$p, reglist:$regs, variable_ops),
1873 IndexModeUpd, f, itin_upd,
1874 !strconcat(asm, "da${p}\t$Rn!, $regs"), "$Rn = $wb", []> {
1875 let Inst{24-23} = 0b00; // Decrement After
1876 let Inst{21} = 1; // Writeback
1877 let Inst{20} = L_bit;
1880 AXI4<(outs), (ins GPR:$Rn, pred:$p, reglist:$regs, variable_ops),
1881 IndexModeNone, f, itin,
1882 !strconcat(asm, "db${p}\t$Rn, $regs"), "", []> {
1883 let Inst{24-23} = 0b10; // Decrement Before
1884 let Inst{21} = 0; // No writeback
1885 let Inst{20} = L_bit;
1888 AXI4<(outs GPR:$wb), (ins GPR:$Rn, pred:$p, reglist:$regs, variable_ops),
1889 IndexModeUpd, f, itin_upd,
1890 !strconcat(asm, "db${p}\t$Rn!, $regs"), "$Rn = $wb", []> {
1891 let Inst{24-23} = 0b10; // Decrement Before
1892 let Inst{21} = 1; // Writeback
1893 let Inst{20} = L_bit;
1896 AXI4<(outs), (ins GPR:$Rn, pred:$p, reglist:$regs, variable_ops),
1897 IndexModeNone, f, itin,
1898 !strconcat(asm, "ib${p}\t$Rn, $regs"), "", []> {
1899 let Inst{24-23} = 0b11; // Increment Before
1900 let Inst{21} = 0; // No writeback
1901 let Inst{20} = L_bit;
1904 AXI4<(outs GPR:$wb), (ins GPR:$Rn, pred:$p, reglist:$regs, variable_ops),
1905 IndexModeUpd, f, itin_upd,
1906 !strconcat(asm, "ib${p}\t$Rn!, $regs"), "$Rn = $wb", []> {
1907 let Inst{24-23} = 0b11; // Increment Before
1908 let Inst{21} = 1; // Writeback
1909 let Inst{20} = L_bit;
1913 let neverHasSideEffects = 1 in {
1915 let mayLoad = 1, hasExtraDefRegAllocReq = 1 in
1916 defm LDM : arm_ldst_mult<"ldm", 1, LdStMulFrm, IIC_iLoad_m, IIC_iLoad_mu>;
1918 let mayStore = 1, hasExtraSrcRegAllocReq = 1 in
1919 defm STM : arm_ldst_mult<"stm", 0, LdStMulFrm, IIC_iStore_m, IIC_iStore_mu>;
1921 } // neverHasSideEffects
1923 // Load / Store Multiple Mnemonic Aliases
1924 def : MnemonicAlias<"ldm", "ldmia">;
1925 def : MnemonicAlias<"stm", "stmia">;
1927 // FIXME: remove when we have a way to marking a MI with these properties.
1928 // FIXME: Should pc be an implicit operand like PICADD, etc?
1929 let isReturn = 1, isTerminator = 1, isBarrier = 1, mayLoad = 1,
1930 hasExtraDefRegAllocReq = 1, isCodeGenOnly = 1 in
1931 // FIXME: Should be a pseudo-instruction.
1932 def LDMIA_RET : AXI4<(outs GPR:$wb), (ins GPR:$Rn, pred:$p,
1933 reglist:$regs, variable_ops),
1934 IndexModeUpd, LdStMulFrm, IIC_iLoad_mBr,
1935 "ldmia${p}\t$Rn!, $regs",
1937 let Inst{24-23} = 0b01; // Increment After
1938 let Inst{21} = 1; // Writeback
1939 let Inst{20} = 1; // Load
1942 //===----------------------------------------------------------------------===//
1943 // Move Instructions.
1946 let neverHasSideEffects = 1 in
1947 def MOVr : AsI1<0b1101, (outs GPR:$Rd), (ins GPR:$Rm), DPFrm, IIC_iMOVr,
1948 "mov", "\t$Rd, $Rm", []>, UnaryDP {
1952 let Inst{11-4} = 0b00000000;
1955 let Inst{15-12} = Rd;
1958 // A version for the smaller set of tail call registers.
1959 let neverHasSideEffects = 1 in
1960 def MOVr_TC : AsI1<0b1101, (outs tcGPR:$Rd), (ins tcGPR:$Rm), DPFrm,
1961 IIC_iMOVr, "mov", "\t$Rd, $Rm", []>, UnaryDP {
1965 let Inst{11-4} = 0b00000000;
1968 let Inst{15-12} = Rd;
1971 def MOVs : AsI1<0b1101, (outs GPR:$Rd), (ins shift_so_reg:$src),
1972 DPSoRegFrm, IIC_iMOVsr,
1973 "mov", "\t$Rd, $src", [(set GPR:$Rd, shift_so_reg:$src)]>,
1977 let Inst{15-12} = Rd;
1978 let Inst{11-0} = src;
1982 let isReMaterializable = 1, isAsCheapAsAMove = 1, isMoveImm = 1 in
1983 def MOVi : AsI1<0b1101, (outs GPR:$Rd), (ins so_imm:$imm), DPFrm, IIC_iMOVi,
1984 "mov", "\t$Rd, $imm", [(set GPR:$Rd, so_imm:$imm)]>, UnaryDP {
1988 let Inst{15-12} = Rd;
1989 let Inst{19-16} = 0b0000;
1990 let Inst{11-0} = imm;
1993 let isReMaterializable = 1, isAsCheapAsAMove = 1, isMoveImm = 1 in
1994 def MOVi16 : AI1<0b1000, (outs GPR:$Rd), (ins i32imm_hilo16:$imm),
1996 "movw", "\t$Rd, $imm",
1997 [(set GPR:$Rd, imm0_65535:$imm)]>,
1998 Requires<[IsARM, HasV6T2]>, UnaryDP {
2001 let Inst{15-12} = Rd;
2002 let Inst{11-0} = imm{11-0};
2003 let Inst{19-16} = imm{15-12};
2008 def MOVi16_ga_pcrel : PseudoInst<(outs GPR:$Rd),
2009 (ins i32imm:$addr, pclabel:$id), IIC_iMOVi, []>;
2011 let Constraints = "$src = $Rd" in {
2012 def MOVTi16 : AI1<0b1010, (outs GPR:$Rd), (ins GPR:$src, i32imm_hilo16:$imm),
2014 "movt", "\t$Rd, $imm",
2016 (or (and GPR:$src, 0xffff),
2017 lo16AllZero:$imm))]>, UnaryDP,
2018 Requires<[IsARM, HasV6T2]> {
2021 let Inst{15-12} = Rd;
2022 let Inst{11-0} = imm{11-0};
2023 let Inst{19-16} = imm{15-12};
2028 def MOVTi16_ga_pcrel : PseudoInst<(outs GPR:$Rd),
2029 (ins GPR:$src, i32imm:$addr, pclabel:$id), IIC_iMOVi, []>;
2033 def : ARMPat<(or GPR:$src, 0xffff0000), (MOVTi16 GPR:$src, 0xffff)>,
2034 Requires<[IsARM, HasV6T2]>;
2036 let Uses = [CPSR] in
2037 def RRX: PseudoInst<(outs GPR:$Rd), (ins GPR:$Rm), IIC_iMOVsi,
2038 [(set GPR:$Rd, (ARMrrx GPR:$Rm))]>, UnaryDP,
2041 // These aren't really mov instructions, but we have to define them this way
2042 // due to flag operands.
2044 let Defs = [CPSR] in {
2045 def MOVsrl_flag : PseudoInst<(outs GPR:$dst), (ins GPR:$src), IIC_iMOVsi,
2046 [(set GPR:$dst, (ARMsrl_flag GPR:$src))]>, UnaryDP,
2048 def MOVsra_flag : PseudoInst<(outs GPR:$dst), (ins GPR:$src), IIC_iMOVsi,
2049 [(set GPR:$dst, (ARMsra_flag GPR:$src))]>, UnaryDP,
2053 //===----------------------------------------------------------------------===//
2054 // Extend Instructions.
2059 defm SXTB : AI_ext_rrot<0b01101010,
2060 "sxtb", UnOpFrag<(sext_inreg node:$Src, i8)>>;
2061 defm SXTH : AI_ext_rrot<0b01101011,
2062 "sxth", UnOpFrag<(sext_inreg node:$Src, i16)>>;
2064 defm SXTAB : AI_exta_rrot<0b01101010,
2065 "sxtab", BinOpFrag<(add node:$LHS, (sext_inreg node:$RHS, i8))>>;
2066 defm SXTAH : AI_exta_rrot<0b01101011,
2067 "sxtah", BinOpFrag<(add node:$LHS, (sext_inreg node:$RHS,i16))>>;
2069 // For disassembly only
2070 defm SXTB16 : AI_ext_rrot_np<0b01101000, "sxtb16">;
2072 // For disassembly only
2073 defm SXTAB16 : AI_exta_rrot_np<0b01101000, "sxtab16">;
2077 let AddedComplexity = 16 in {
2078 defm UXTB : AI_ext_rrot<0b01101110,
2079 "uxtb" , UnOpFrag<(and node:$Src, 0x000000FF)>>;
2080 defm UXTH : AI_ext_rrot<0b01101111,
2081 "uxth" , UnOpFrag<(and node:$Src, 0x0000FFFF)>>;
2082 defm UXTB16 : AI_ext_rrot<0b01101100,
2083 "uxtb16", UnOpFrag<(and node:$Src, 0x00FF00FF)>>;
2085 // FIXME: This pattern incorrectly assumes the shl operator is a rotate.
2086 // The transformation should probably be done as a combiner action
2087 // instead so we can include a check for masking back in the upper
2088 // eight bits of the source into the lower eight bits of the result.
2089 //def : ARMV6Pat<(and (shl GPR:$Src, (i32 8)), 0xFF00FF),
2090 // (UXTB16r_rot GPR:$Src, 24)>;
2091 def : ARMV6Pat<(and (srl GPR:$Src, (i32 8)), 0xFF00FF),
2092 (UXTB16r_rot GPR:$Src, 8)>;
2094 defm UXTAB : AI_exta_rrot<0b01101110, "uxtab",
2095 BinOpFrag<(add node:$LHS, (and node:$RHS, 0x00FF))>>;
2096 defm UXTAH : AI_exta_rrot<0b01101111, "uxtah",
2097 BinOpFrag<(add node:$LHS, (and node:$RHS, 0xFFFF))>>;
2100 // This isn't safe in general, the add is two 16-bit units, not a 32-bit add.
2101 // For disassembly only
2102 defm UXTAB16 : AI_exta_rrot_np<0b01101100, "uxtab16">;
2105 def SBFX : I<(outs GPR:$Rd),
2106 (ins GPR:$Rn, imm0_31:$lsb, imm0_31_m1:$width),
2107 AddrMode1, Size4Bytes, IndexModeNone, DPFrm, IIC_iUNAsi,
2108 "sbfx", "\t$Rd, $Rn, $lsb, $width", "", []>,
2109 Requires<[IsARM, HasV6T2]> {
2114 let Inst{27-21} = 0b0111101;
2115 let Inst{6-4} = 0b101;
2116 let Inst{20-16} = width;
2117 let Inst{15-12} = Rd;
2118 let Inst{11-7} = lsb;
2122 def UBFX : I<(outs GPR:$Rd),
2123 (ins GPR:$Rn, imm0_31:$lsb, imm0_31_m1:$width),
2124 AddrMode1, Size4Bytes, IndexModeNone, DPFrm, IIC_iUNAsi,
2125 "ubfx", "\t$Rd, $Rn, $lsb, $width", "", []>,
2126 Requires<[IsARM, HasV6T2]> {
2131 let Inst{27-21} = 0b0111111;
2132 let Inst{6-4} = 0b101;
2133 let Inst{20-16} = width;
2134 let Inst{15-12} = Rd;
2135 let Inst{11-7} = lsb;
2139 //===----------------------------------------------------------------------===//
2140 // Arithmetic Instructions.
2143 defm ADD : AsI1_bin_irs<0b0100, "add",
2144 IIC_iALUi, IIC_iALUr, IIC_iALUsr,
2145 BinOpFrag<(add node:$LHS, node:$RHS)>, 1>;
2146 defm SUB : AsI1_bin_irs<0b0010, "sub",
2147 IIC_iALUi, IIC_iALUr, IIC_iALUsr,
2148 BinOpFrag<(sub node:$LHS, node:$RHS)>>;
2150 // ADD and SUB with 's' bit set.
2151 defm ADDS : AI1_bin_s_irs<0b0100, "adds",
2152 IIC_iALUi, IIC_iALUr, IIC_iALUsr,
2153 BinOpFrag<(addc node:$LHS, node:$RHS)>, 1>;
2154 defm SUBS : AI1_bin_s_irs<0b0010, "subs",
2155 IIC_iALUi, IIC_iALUr, IIC_iALUsr,
2156 BinOpFrag<(subc node:$LHS, node:$RHS)>>;
2158 defm ADC : AI1_adde_sube_irs<0b0101, "adc",
2159 BinOpFrag<(adde_dead_carry node:$LHS, node:$RHS)>, 1>;
2160 defm SBC : AI1_adde_sube_irs<0b0110, "sbc",
2161 BinOpFrag<(sube_dead_carry node:$LHS, node:$RHS)>>;
2163 // ADC and SUBC with 's' bit set.
2164 defm ADCS : AI1_adde_sube_s_irs<0b0101, "adcs",
2165 BinOpFrag<(adde_live_carry node:$LHS, node:$RHS)>, 1>;
2166 defm SBCS : AI1_adde_sube_s_irs<0b0110, "sbcs",
2167 BinOpFrag<(sube_live_carry node:$LHS, node:$RHS) >>;
2169 def RSBri : AsI1<0b0011, (outs GPR:$Rd), (ins GPR:$Rn, so_imm:$imm), DPFrm,
2170 IIC_iALUi, "rsb", "\t$Rd, $Rn, $imm",
2171 [(set GPR:$Rd, (sub so_imm:$imm, GPR:$Rn))]> {
2176 let Inst{15-12} = Rd;
2177 let Inst{19-16} = Rn;
2178 let Inst{11-0} = imm;
2181 // The reg/reg form is only defined for the disassembler; for codegen it is
2182 // equivalent to SUBrr.
2183 def RSBrr : AsI1<0b0011, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm), DPFrm,
2184 IIC_iALUr, "rsb", "\t$Rd, $Rn, $Rm",
2185 [/* For disassembly only; pattern left blank */]> {
2189 let Inst{11-4} = 0b00000000;
2192 let Inst{15-12} = Rd;
2193 let Inst{19-16} = Rn;
2196 def RSBrs : AsI1<0b0011, (outs GPR:$Rd), (ins GPR:$Rn, so_reg:$shift),
2197 DPSoRegFrm, IIC_iALUsr, "rsb", "\t$Rd, $Rn, $shift",
2198 [(set GPR:$Rd, (sub so_reg:$shift, GPR:$Rn))]> {
2203 let Inst{11-0} = shift;
2204 let Inst{15-12} = Rd;
2205 let Inst{19-16} = Rn;
2208 // RSB with 's' bit set.
2209 let isCodeGenOnly = 1, Defs = [CPSR] in {
2210 def RSBSri : AI1<0b0011, (outs GPR:$Rd), (ins GPR:$Rn, so_imm:$imm), DPFrm,
2211 IIC_iALUi, "rsbs", "\t$Rd, $Rn, $imm",
2212 [(set GPR:$Rd, (subc so_imm:$imm, GPR:$Rn))]> {
2218 let Inst{15-12} = Rd;
2219 let Inst{19-16} = Rn;
2220 let Inst{11-0} = imm;
2222 def RSBSrr : AI1<0b0011, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm), DPFrm,
2223 IIC_iALUr, "rsbs", "\t$Rd, $Rn, $Rm",
2224 [/* For disassembly only; pattern left blank */]> {
2228 let Inst{11-4} = 0b00000000;
2232 let Inst{15-12} = Rd;
2233 let Inst{19-16} = Rn;
2235 def RSBSrs : AI1<0b0011, (outs GPR:$Rd), (ins GPR:$Rn, so_reg:$shift),
2236 DPSoRegFrm, IIC_iALUsr, "rsbs", "\t$Rd, $Rn, $shift",
2237 [(set GPR:$Rd, (subc so_reg:$shift, GPR:$Rn))]> {
2243 let Inst{11-0} = shift;
2244 let Inst{15-12} = Rd;
2245 let Inst{19-16} = Rn;
2249 let Uses = [CPSR] in {
2250 def RSCri : AsI1<0b0111, (outs GPR:$Rd), (ins GPR:$Rn, so_imm:$imm),
2251 DPFrm, IIC_iALUi, "rsc", "\t$Rd, $Rn, $imm",
2252 [(set GPR:$Rd, (sube_dead_carry so_imm:$imm, GPR:$Rn))]>,
2258 let Inst{15-12} = Rd;
2259 let Inst{19-16} = Rn;
2260 let Inst{11-0} = imm;
2262 // The reg/reg form is only defined for the disassembler; for codegen it is
2263 // equivalent to SUBrr.
2264 def RSCrr : AsI1<0b0111, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm),
2265 DPFrm, IIC_iALUr, "rsc", "\t$Rd, $Rn, $Rm",
2266 [/* For disassembly only; pattern left blank */]> {
2270 let Inst{11-4} = 0b00000000;
2273 let Inst{15-12} = Rd;
2274 let Inst{19-16} = Rn;
2276 def RSCrs : AsI1<0b0111, (outs GPR:$Rd), (ins GPR:$Rn, so_reg:$shift),
2277 DPSoRegFrm, IIC_iALUsr, "rsc", "\t$Rd, $Rn, $shift",
2278 [(set GPR:$Rd, (sube_dead_carry so_reg:$shift, GPR:$Rn))]>,
2284 let Inst{11-0} = shift;
2285 let Inst{15-12} = Rd;
2286 let Inst{19-16} = Rn;
2290 // FIXME: Allow these to be predicated.
2291 let isCodeGenOnly = 1, Defs = [CPSR], Uses = [CPSR] in {
2292 def RSCSri : AXI1<0b0111, (outs GPR:$Rd), (ins GPR:$Rn, so_imm:$imm),
2293 DPFrm, IIC_iALUi, "rscs\t$Rd, $Rn, $imm",
2294 [(set GPR:$Rd, (sube_dead_carry so_imm:$imm, GPR:$Rn))]>,
2301 let Inst{15-12} = Rd;
2302 let Inst{19-16} = Rn;
2303 let Inst{11-0} = imm;
2305 def RSCSrs : AXI1<0b0111, (outs GPR:$Rd), (ins GPR:$Rn, so_reg:$shift),
2306 DPSoRegFrm, IIC_iALUsr, "rscs\t$Rd, $Rn, $shift",
2307 [(set GPR:$Rd, (sube_dead_carry so_reg:$shift, GPR:$Rn))]>,
2314 let Inst{11-0} = shift;
2315 let Inst{15-12} = Rd;
2316 let Inst{19-16} = Rn;
2320 // (sub X, imm) gets canonicalized to (add X, -imm). Match this form.
2321 // The assume-no-carry-in form uses the negation of the input since add/sub
2322 // assume opposite meanings of the carry flag (i.e., carry == !borrow).
2323 // See the definition of AddWithCarry() in the ARM ARM A2.2.1 for the gory
2325 def : ARMPat<(add GPR:$src, so_imm_neg:$imm),
2326 (SUBri GPR:$src, so_imm_neg:$imm)>;
2327 def : ARMPat<(addc GPR:$src, so_imm_neg:$imm),
2328 (SUBSri GPR:$src, so_imm_neg:$imm)>;
2329 // The with-carry-in form matches bitwise not instead of the negation.
2330 // Effectively, the inverse interpretation of the carry flag already accounts
2331 // for part of the negation.
2332 def : ARMPat<(adde GPR:$src, so_imm_not:$imm),
2333 (SBCri GPR:$src, so_imm_not:$imm)>;
2335 // Note: These are implemented in C++ code, because they have to generate
2336 // ADD/SUBrs instructions, which use a complex pattern that a xform function
2338 // (mul X, 2^n+1) -> (add (X << n), X)
2339 // (mul X, 2^n-1) -> (rsb X, (X << n))
2341 // ARM Arithmetic Instruction -- for disassembly only
2342 // GPR:$dst = GPR:$a op GPR:$b
2343 class AAI<bits<8> op27_20, bits<8> op11_4, string opc,
2344 list<dag> pattern = [/* For disassembly only; pattern left blank */],
2345 dag iops = (ins GPR:$Rn, GPR:$Rm), string asm = "\t$Rd, $Rn, $Rm">
2346 : AI<(outs GPR:$Rd), iops, DPFrm, IIC_iALUr, opc, asm, pattern> {
2350 let Inst{27-20} = op27_20;
2351 let Inst{11-4} = op11_4;
2352 let Inst{19-16} = Rn;
2353 let Inst{15-12} = Rd;
2357 // Saturating add/subtract -- for disassembly only
2359 def QADD : AAI<0b00010000, 0b00000101, "qadd",
2360 [(set GPR:$Rd, (int_arm_qadd GPR:$Rm, GPR:$Rn))],
2361 (ins GPR:$Rm, GPR:$Rn), "\t$Rd, $Rm, $Rn">;
2362 def QSUB : AAI<0b00010010, 0b00000101, "qsub",
2363 [(set GPR:$Rd, (int_arm_qsub GPR:$Rm, GPR:$Rn))],
2364 (ins GPR:$Rm, GPR:$Rn), "\t$Rd, $Rm, $Rn">;
2365 def QDADD : AAI<0b00010100, 0b00000101, "qdadd", [], (ins GPR:$Rm, GPR:$Rn),
2367 def QDSUB : AAI<0b00010110, 0b00000101, "qdsub", [], (ins GPR:$Rm, GPR:$Rn),
2370 def QADD16 : AAI<0b01100010, 0b11110001, "qadd16">;
2371 def QADD8 : AAI<0b01100010, 0b11111001, "qadd8">;
2372 def QASX : AAI<0b01100010, 0b11110011, "qasx">;
2373 def QSAX : AAI<0b01100010, 0b11110101, "qsax">;
2374 def QSUB16 : AAI<0b01100010, 0b11110111, "qsub16">;
2375 def QSUB8 : AAI<0b01100010, 0b11111111, "qsub8">;
2376 def UQADD16 : AAI<0b01100110, 0b11110001, "uqadd16">;
2377 def UQADD8 : AAI<0b01100110, 0b11111001, "uqadd8">;
2378 def UQASX : AAI<0b01100110, 0b11110011, "uqasx">;
2379 def UQSAX : AAI<0b01100110, 0b11110101, "uqsax">;
2380 def UQSUB16 : AAI<0b01100110, 0b11110111, "uqsub16">;
2381 def UQSUB8 : AAI<0b01100110, 0b11111111, "uqsub8">;
2383 // Signed/Unsigned add/subtract -- for disassembly only
2385 def SASX : AAI<0b01100001, 0b11110011, "sasx">;
2386 def SADD16 : AAI<0b01100001, 0b11110001, "sadd16">;
2387 def SADD8 : AAI<0b01100001, 0b11111001, "sadd8">;
2388 def SSAX : AAI<0b01100001, 0b11110101, "ssax">;
2389 def SSUB16 : AAI<0b01100001, 0b11110111, "ssub16">;
2390 def SSUB8 : AAI<0b01100001, 0b11111111, "ssub8">;
2391 def UASX : AAI<0b01100101, 0b11110011, "uasx">;
2392 def UADD16 : AAI<0b01100101, 0b11110001, "uadd16">;
2393 def UADD8 : AAI<0b01100101, 0b11111001, "uadd8">;
2394 def USAX : AAI<0b01100101, 0b11110101, "usax">;
2395 def USUB16 : AAI<0b01100101, 0b11110111, "usub16">;
2396 def USUB8 : AAI<0b01100101, 0b11111111, "usub8">;
2398 // Signed/Unsigned halving add/subtract -- for disassembly only
2400 def SHASX : AAI<0b01100011, 0b11110011, "shasx">;
2401 def SHADD16 : AAI<0b01100011, 0b11110001, "shadd16">;
2402 def SHADD8 : AAI<0b01100011, 0b11111001, "shadd8">;
2403 def SHSAX : AAI<0b01100011, 0b11110101, "shsax">;
2404 def SHSUB16 : AAI<0b01100011, 0b11110111, "shsub16">;
2405 def SHSUB8 : AAI<0b01100011, 0b11111111, "shsub8">;
2406 def UHASX : AAI<0b01100111, 0b11110011, "uhasx">;
2407 def UHADD16 : AAI<0b01100111, 0b11110001, "uhadd16">;
2408 def UHADD8 : AAI<0b01100111, 0b11111001, "uhadd8">;
2409 def UHSAX : AAI<0b01100111, 0b11110101, "uhsax">;
2410 def UHSUB16 : AAI<0b01100111, 0b11110111, "uhsub16">;
2411 def UHSUB8 : AAI<0b01100111, 0b11111111, "uhsub8">;
2413 // Unsigned Sum of Absolute Differences [and Accumulate] -- for disassembly only
2415 def USAD8 : AI<(outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm),
2416 MulFrm /* for convenience */, NoItinerary, "usad8",
2417 "\t$Rd, $Rn, $Rm", []>,
2418 Requires<[IsARM, HasV6]> {
2422 let Inst{27-20} = 0b01111000;
2423 let Inst{15-12} = 0b1111;
2424 let Inst{7-4} = 0b0001;
2425 let Inst{19-16} = Rd;
2426 let Inst{11-8} = Rm;
2429 def USADA8 : AI<(outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm, GPR:$Ra),
2430 MulFrm /* for convenience */, NoItinerary, "usada8",
2431 "\t$Rd, $Rn, $Rm, $Ra", []>,
2432 Requires<[IsARM, HasV6]> {
2437 let Inst{27-20} = 0b01111000;
2438 let Inst{7-4} = 0b0001;
2439 let Inst{19-16} = Rd;
2440 let Inst{15-12} = Ra;
2441 let Inst{11-8} = Rm;
2445 // Signed/Unsigned saturate -- for disassembly only
2447 def SSAT : AI<(outs GPR:$Rd), (ins i32imm:$sat_imm, GPR:$a, shift_imm:$sh),
2448 SatFrm, NoItinerary, "ssat", "\t$Rd, $sat_imm, $a$sh",
2449 [/* For disassembly only; pattern left blank */]> {
2454 let Inst{27-21} = 0b0110101;
2455 let Inst{5-4} = 0b01;
2456 let Inst{20-16} = sat_imm;
2457 let Inst{15-12} = Rd;
2458 let Inst{11-7} = sh{7-3};
2459 let Inst{6} = sh{0};
2463 def SSAT16 : AI<(outs GPR:$Rd), (ins i32imm:$sat_imm, GPR:$Rn), SatFrm,
2464 NoItinerary, "ssat16", "\t$Rd, $sat_imm, $Rn",
2465 [/* For disassembly only; pattern left blank */]> {
2469 let Inst{27-20} = 0b01101010;
2470 let Inst{11-4} = 0b11110011;
2471 let Inst{15-12} = Rd;
2472 let Inst{19-16} = sat_imm;
2476 def USAT : AI<(outs GPR:$Rd), (ins i32imm:$sat_imm, GPR:$a, shift_imm:$sh),
2477 SatFrm, NoItinerary, "usat", "\t$Rd, $sat_imm, $a$sh",
2478 [/* For disassembly only; pattern left blank */]> {
2483 let Inst{27-21} = 0b0110111;
2484 let Inst{5-4} = 0b01;
2485 let Inst{15-12} = Rd;
2486 let Inst{11-7} = sh{7-3};
2487 let Inst{6} = sh{0};
2488 let Inst{20-16} = sat_imm;
2492 def USAT16 : AI<(outs GPR:$Rd), (ins i32imm:$sat_imm, GPR:$a), SatFrm,
2493 NoItinerary, "usat16", "\t$Rd, $sat_imm, $a",
2494 [/* For disassembly only; pattern left blank */]> {
2498 let Inst{27-20} = 0b01101110;
2499 let Inst{11-4} = 0b11110011;
2500 let Inst{15-12} = Rd;
2501 let Inst{19-16} = sat_imm;
2505 def : ARMV6Pat<(int_arm_ssat GPR:$a, imm:$pos), (SSAT imm:$pos, GPR:$a, 0)>;
2506 def : ARMV6Pat<(int_arm_usat GPR:$a, imm:$pos), (USAT imm:$pos, GPR:$a, 0)>;
2508 //===----------------------------------------------------------------------===//
2509 // Bitwise Instructions.
2512 defm AND : AsI1_bin_irs<0b0000, "and",
2513 IIC_iBITi, IIC_iBITr, IIC_iBITsr,
2514 BinOpFrag<(and node:$LHS, node:$RHS)>, 1>;
2515 defm ORR : AsI1_bin_irs<0b1100, "orr",
2516 IIC_iBITi, IIC_iBITr, IIC_iBITsr,
2517 BinOpFrag<(or node:$LHS, node:$RHS)>, 1>;
2518 defm EOR : AsI1_bin_irs<0b0001, "eor",
2519 IIC_iBITi, IIC_iBITr, IIC_iBITsr,
2520 BinOpFrag<(xor node:$LHS, node:$RHS)>, 1>;
2521 defm BIC : AsI1_bin_irs<0b1110, "bic",
2522 IIC_iBITi, IIC_iBITr, IIC_iBITsr,
2523 BinOpFrag<(and node:$LHS, (not node:$RHS))>>;
2525 def BFC : I<(outs GPR:$Rd), (ins GPR:$src, bf_inv_mask_imm:$imm),
2526 AddrMode1, Size4Bytes, IndexModeNone, DPFrm, IIC_iUNAsi,
2527 "bfc", "\t$Rd, $imm", "$src = $Rd",
2528 [(set GPR:$Rd, (and GPR:$src, bf_inv_mask_imm:$imm))]>,
2529 Requires<[IsARM, HasV6T2]> {
2532 let Inst{27-21} = 0b0111110;
2533 let Inst{6-0} = 0b0011111;
2534 let Inst{15-12} = Rd;
2535 let Inst{11-7} = imm{4-0}; // lsb
2536 let Inst{20-16} = imm{9-5}; // width
2539 // A8.6.18 BFI - Bitfield insert (Encoding A1)
2540 def BFI : I<(outs GPR:$Rd), (ins GPR:$src, GPR:$Rn, bf_inv_mask_imm:$imm),
2541 AddrMode1, Size4Bytes, IndexModeNone, DPFrm, IIC_iUNAsi,
2542 "bfi", "\t$Rd, $Rn, $imm", "$src = $Rd",
2543 [(set GPR:$Rd, (ARMbfi GPR:$src, GPR:$Rn,
2544 bf_inv_mask_imm:$imm))]>,
2545 Requires<[IsARM, HasV6T2]> {
2549 let Inst{27-21} = 0b0111110;
2550 let Inst{6-4} = 0b001; // Rn: Inst{3-0} != 15
2551 let Inst{15-12} = Rd;
2552 let Inst{11-7} = imm{4-0}; // lsb
2553 let Inst{20-16} = imm{9-5}; // width
2557 // GNU as only supports this form of bfi (w/ 4 arguments)
2558 let isAsmParserOnly = 1 in
2559 def BFI4p : I<(outs GPR:$Rd), (ins GPR:$src, GPR:$Rn,
2560 lsb_pos_imm:$lsb, width_imm:$width),
2561 AddrMode1, Size4Bytes, IndexModeNone, DPFrm, IIC_iUNAsi,
2562 "bfi", "\t$Rd, $Rn, $lsb, $width", "$src = $Rd",
2563 []>, Requires<[IsARM, HasV6T2]> {
2568 let Inst{27-21} = 0b0111110;
2569 let Inst{6-4} = 0b001; // Rn: Inst{3-0} != 15
2570 let Inst{15-12} = Rd;
2571 let Inst{11-7} = lsb;
2572 let Inst{20-16} = width; // Custom encoder => lsb+width-1
2576 def MVNr : AsI1<0b1111, (outs GPR:$Rd), (ins GPR:$Rm), DPFrm, IIC_iMVNr,
2577 "mvn", "\t$Rd, $Rm",
2578 [(set GPR:$Rd, (not GPR:$Rm))]>, UnaryDP {
2582 let Inst{19-16} = 0b0000;
2583 let Inst{11-4} = 0b00000000;
2584 let Inst{15-12} = Rd;
2587 def MVNs : AsI1<0b1111, (outs GPR:$Rd), (ins so_reg:$shift), DPSoRegFrm,
2588 IIC_iMVNsr, "mvn", "\t$Rd, $shift",
2589 [(set GPR:$Rd, (not so_reg:$shift))]>, UnaryDP {
2593 let Inst{19-16} = 0b0000;
2594 let Inst{15-12} = Rd;
2595 let Inst{11-0} = shift;
2597 let isReMaterializable = 1, isAsCheapAsAMove = 1, isMoveImm = 1 in
2598 def MVNi : AsI1<0b1111, (outs GPR:$Rd), (ins so_imm:$imm), DPFrm,
2599 IIC_iMVNi, "mvn", "\t$Rd, $imm",
2600 [(set GPR:$Rd, so_imm_not:$imm)]>,UnaryDP {
2604 let Inst{19-16} = 0b0000;
2605 let Inst{15-12} = Rd;
2606 let Inst{11-0} = imm;
2609 def : ARMPat<(and GPR:$src, so_imm_not:$imm),
2610 (BICri GPR:$src, so_imm_not:$imm)>;
2612 //===----------------------------------------------------------------------===//
2613 // Multiply Instructions.
2615 class AsMul1I32<bits<7> opcod, dag oops, dag iops, InstrItinClass itin,
2616 string opc, string asm, list<dag> pattern>
2617 : AsMul1I<opcod, oops, iops, itin, opc, asm, pattern> {
2621 let Inst{19-16} = Rd;
2622 let Inst{11-8} = Rm;
2625 class AsMul1I64<bits<7> opcod, dag oops, dag iops, InstrItinClass itin,
2626 string opc, string asm, list<dag> pattern>
2627 : AsMul1I<opcod, oops, iops, itin, opc, asm, pattern> {
2632 let Inst{19-16} = RdHi;
2633 let Inst{15-12} = RdLo;
2634 let Inst{11-8} = Rm;
2638 let isCommutable = 1 in {
2639 let Constraints = "@earlyclobber $Rd" in
2640 def MULv5: ARMPseudoInst<(outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm,
2641 pred:$p, cc_out:$s),
2642 Size4Bytes, IIC_iMUL32,
2643 [(set GPR:$Rd, (mul GPR:$Rn, GPR:$Rm))]>,
2644 Requires<[IsARM, NoV6]>;
2646 def MUL : AsMul1I32<0b0000000, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm),
2647 IIC_iMUL32, "mul", "\t$Rd, $Rn, $Rm",
2648 [(set GPR:$Rd, (mul GPR:$Rn, GPR:$Rm))]>,
2649 Requires<[IsARM, HasV6]>;
2652 let Constraints = "@earlyclobber $Rd" in
2653 def MLAv5: ARMPseudoInst<(outs GPR:$Rd),
2654 (ins GPR:$Rn, GPR:$Rm, GPR:$Ra, pred:$p, cc_out:$s),
2655 Size4Bytes, IIC_iMAC32,
2656 [(set GPR:$Rd, (add (mul GPR:$Rn, GPR:$Rm), GPR:$Ra))]>,
2657 Requires<[IsARM, NoV6]> {
2659 let Inst{15-12} = Ra;
2661 def MLA : AsMul1I32<0b0000001, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm, GPR:$Ra),
2662 IIC_iMAC32, "mla", "\t$Rd, $Rn, $Rm, $Ra",
2663 [(set GPR:$Rd, (add (mul GPR:$Rn, GPR:$Rm), GPR:$Ra))]>,
2664 Requires<[IsARM, HasV6]> {
2666 let Inst{15-12} = Ra;
2669 def MLS : AMul1I<0b0000011, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm, GPR:$Ra),
2670 IIC_iMAC32, "mls", "\t$Rd, $Rn, $Rm, $Ra",
2671 [(set GPR:$Rd, (sub GPR:$Ra, (mul GPR:$Rn, GPR:$Rm)))]>,
2672 Requires<[IsARM, HasV6T2]> {
2677 let Inst{19-16} = Rd;
2678 let Inst{15-12} = Ra;
2679 let Inst{11-8} = Rm;
2683 // Extra precision multiplies with low / high results
2685 let neverHasSideEffects = 1 in {
2686 let isCommutable = 1 in {
2687 let Constraints = "@earlyclobber $RdLo,@earlyclobber $RdHi" in {
2688 def SMULLv5 : ARMPseudoInst<(outs GPR:$RdLo, GPR:$RdHi),
2689 (ins GPR:$Rn, GPR:$Rm, pred:$p, cc_out:$s),
2690 Size4Bytes, IIC_iMUL64, []>,
2691 Requires<[IsARM, NoV6]>;
2693 def UMULLv5 : ARMPseudoInst<(outs GPR:$RdLo, GPR:$RdHi),
2694 (ins GPR:$Rn, GPR:$Rm, pred:$p, cc_out:$s),
2695 Size4Bytes, IIC_iMUL64, []>,
2696 Requires<[IsARM, NoV6]>;
2699 def SMULL : AsMul1I64<0b0000110, (outs GPR:$RdLo, GPR:$RdHi),
2700 (ins GPR:$Rn, GPR:$Rm), IIC_iMUL64,
2701 "smull", "\t$RdLo, $RdHi, $Rn, $Rm", []>,
2702 Requires<[IsARM, HasV6]>;
2704 def UMULL : AsMul1I64<0b0000100, (outs GPR:$RdLo, GPR:$RdHi),
2705 (ins GPR:$Rn, GPR:$Rm), IIC_iMUL64,
2706 "umull", "\t$RdLo, $RdHi, $Rn, $Rm", []>,
2707 Requires<[IsARM, HasV6]>;
2710 // Multiply + accumulate
2711 let Constraints = "@earlyclobber $RdLo,@earlyclobber $RdHi" in {
2712 def SMLALv5 : ARMPseudoInst<(outs GPR:$RdLo, GPR:$RdHi),
2713 (ins GPR:$Rn, GPR:$Rm, pred:$p, cc_out:$s),
2714 Size4Bytes, IIC_iMAC64, []>,
2715 Requires<[IsARM, NoV6]>;
2716 def UMLALv5 : ARMPseudoInst<(outs GPR:$RdLo, GPR:$RdHi),
2717 (ins GPR:$Rn, GPR:$Rm, pred:$p, cc_out:$s),
2718 Size4Bytes, IIC_iMAC64, []>,
2719 Requires<[IsARM, NoV6]>;
2720 def UMAALv5 : ARMPseudoInst<(outs GPR:$RdLo, GPR:$RdHi),
2721 (ins GPR:$Rn, GPR:$Rm, pred:$p, cc_out:$s),
2722 Size4Bytes, IIC_iMAC64, []>,
2723 Requires<[IsARM, NoV6]>;
2727 def SMLAL : AsMul1I64<0b0000111, (outs GPR:$RdLo, GPR:$RdHi),
2728 (ins GPR:$Rn, GPR:$Rm), IIC_iMAC64,
2729 "smlal", "\t$RdLo, $RdHi, $Rn, $Rm", []>,
2730 Requires<[IsARM, HasV6]>;
2731 def UMLAL : AsMul1I64<0b0000101, (outs GPR:$RdLo, GPR:$RdHi),
2732 (ins GPR:$Rn, GPR:$Rm), IIC_iMAC64,
2733 "umlal", "\t$RdLo, $RdHi, $Rn, $Rm", []>,
2734 Requires<[IsARM, HasV6]>;
2736 def UMAAL : AMul1I <0b0000010, (outs GPR:$RdLo, GPR:$RdHi),
2737 (ins GPR:$Rn, GPR:$Rm), IIC_iMAC64,
2738 "umaal", "\t$RdLo, $RdHi, $Rn, $Rm", []>,
2739 Requires<[IsARM, HasV6]> {
2744 let Inst{19-16} = RdLo;
2745 let Inst{15-12} = RdHi;
2746 let Inst{11-8} = Rm;
2749 } // neverHasSideEffects
2751 // Most significant word multiply
2752 def SMMUL : AMul2I <0b0111010, 0b0001, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm),
2753 IIC_iMUL32, "smmul", "\t$Rd, $Rn, $Rm",
2754 [(set GPR:$Rd, (mulhs GPR:$Rn, GPR:$Rm))]>,
2755 Requires<[IsARM, HasV6]> {
2756 let Inst{15-12} = 0b1111;
2759 def SMMULR : AMul2I <0b0111010, 0b0011, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm),
2760 IIC_iMUL32, "smmulr", "\t$Rd, $Rn, $Rm",
2761 [/* For disassembly only; pattern left blank */]>,
2762 Requires<[IsARM, HasV6]> {
2763 let Inst{15-12} = 0b1111;
2766 def SMMLA : AMul2Ia <0b0111010, 0b0001, (outs GPR:$Rd),
2767 (ins GPR:$Rn, GPR:$Rm, GPR:$Ra),
2768 IIC_iMAC32, "smmla", "\t$Rd, $Rn, $Rm, $Ra",
2769 [(set GPR:$Rd, (add (mulhs GPR:$Rn, GPR:$Rm), GPR:$Ra))]>,
2770 Requires<[IsARM, HasV6]>;
2772 def SMMLAR : AMul2Ia <0b0111010, 0b0011, (outs GPR:$Rd),
2773 (ins GPR:$Rn, GPR:$Rm, GPR:$Ra),
2774 IIC_iMAC32, "smmlar", "\t$Rd, $Rn, $Rm, $Ra",
2775 [/* For disassembly only; pattern left blank */]>,
2776 Requires<[IsARM, HasV6]>;
2778 def SMMLS : AMul2Ia <0b0111010, 0b1101, (outs GPR:$Rd),
2779 (ins GPR:$Rn, GPR:$Rm, GPR:$Ra),
2780 IIC_iMAC32, "smmls", "\t$Rd, $Rn, $Rm, $Ra",
2781 [(set GPR:$Rd, (sub GPR:$Ra, (mulhs GPR:$Rn, GPR:$Rm)))]>,
2782 Requires<[IsARM, HasV6]>;
2784 def SMMLSR : AMul2Ia <0b0111010, 0b1111, (outs GPR:$Rd),
2785 (ins GPR:$Rn, GPR:$Rm, GPR:$Ra),
2786 IIC_iMAC32, "smmlsr", "\t$Rd, $Rn, $Rm, $Ra",
2787 [/* For disassembly only; pattern left blank */]>,
2788 Requires<[IsARM, HasV6]>;
2790 multiclass AI_smul<string opc, PatFrag opnode> {
2791 def BB : AMulxyI<0b0001011, 0b00, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm),
2792 IIC_iMUL16, !strconcat(opc, "bb"), "\t$Rd, $Rn, $Rm",
2793 [(set GPR:$Rd, (opnode (sext_inreg GPR:$Rn, i16),
2794 (sext_inreg GPR:$Rm, i16)))]>,
2795 Requires<[IsARM, HasV5TE]>;
2797 def BT : AMulxyI<0b0001011, 0b10, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm),
2798 IIC_iMUL16, !strconcat(opc, "bt"), "\t$Rd, $Rn, $Rm",
2799 [(set GPR:$Rd, (opnode (sext_inreg GPR:$Rn, i16),
2800 (sra GPR:$Rm, (i32 16))))]>,
2801 Requires<[IsARM, HasV5TE]>;
2803 def TB : AMulxyI<0b0001011, 0b01, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm),
2804 IIC_iMUL16, !strconcat(opc, "tb"), "\t$Rd, $Rn, $Rm",
2805 [(set GPR:$Rd, (opnode (sra GPR:$Rn, (i32 16)),
2806 (sext_inreg GPR:$Rm, i16)))]>,
2807 Requires<[IsARM, HasV5TE]>;
2809 def TT : AMulxyI<0b0001011, 0b11, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm),
2810 IIC_iMUL16, !strconcat(opc, "tt"), "\t$Rd, $Rn, $Rm",
2811 [(set GPR:$Rd, (opnode (sra GPR:$Rn, (i32 16)),
2812 (sra GPR:$Rm, (i32 16))))]>,
2813 Requires<[IsARM, HasV5TE]>;
2815 def WB : AMulxyI<0b0001001, 0b01, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm),
2816 IIC_iMUL16, !strconcat(opc, "wb"), "\t$Rd, $Rn, $Rm",
2817 [(set GPR:$Rd, (sra (opnode GPR:$Rn,
2818 (sext_inreg GPR:$Rm, i16)), (i32 16)))]>,
2819 Requires<[IsARM, HasV5TE]>;
2821 def WT : AMulxyI<0b0001001, 0b11, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm),
2822 IIC_iMUL16, !strconcat(opc, "wt"), "\t$Rd, $Rn, $Rm",
2823 [(set GPR:$Rd, (sra (opnode GPR:$Rn,
2824 (sra GPR:$Rm, (i32 16))), (i32 16)))]>,
2825 Requires<[IsARM, HasV5TE]>;
2829 multiclass AI_smla<string opc, PatFrag opnode> {
2830 def BB : AMulxyIa<0b0001000, 0b00, (outs GPR:$Rd),
2831 (ins GPR:$Rn, GPR:$Rm, GPR:$Ra),
2832 IIC_iMAC16, !strconcat(opc, "bb"), "\t$Rd, $Rn, $Rm, $Ra",
2833 [(set GPR:$Rd, (add GPR:$Ra,
2834 (opnode (sext_inreg GPR:$Rn, i16),
2835 (sext_inreg GPR:$Rm, i16))))]>,
2836 Requires<[IsARM, HasV5TE]>;
2838 def BT : AMulxyIa<0b0001000, 0b10, (outs GPR:$Rd),
2839 (ins GPR:$Rn, GPR:$Rm, GPR:$Ra),
2840 IIC_iMAC16, !strconcat(opc, "bt"), "\t$Rd, $Rn, $Rm, $Ra",
2841 [(set GPR:$Rd, (add GPR:$Ra, (opnode (sext_inreg GPR:$Rn, i16),
2842 (sra GPR:$Rm, (i32 16)))))]>,
2843 Requires<[IsARM, HasV5TE]>;
2845 def TB : AMulxyIa<0b0001000, 0b01, (outs GPR:$Rd),
2846 (ins GPR:$Rn, GPR:$Rm, GPR:$Ra),
2847 IIC_iMAC16, !strconcat(opc, "tb"), "\t$Rd, $Rn, $Rm, $Ra",
2848 [(set GPR:$Rd, (add GPR:$Ra, (opnode (sra GPR:$Rn, (i32 16)),
2849 (sext_inreg GPR:$Rm, i16))))]>,
2850 Requires<[IsARM, HasV5TE]>;
2852 def TT : AMulxyIa<0b0001000, 0b11, (outs GPR:$Rd),
2853 (ins GPR:$Rn, GPR:$Rm, GPR:$Ra),
2854 IIC_iMAC16, !strconcat(opc, "tt"), "\t$Rd, $Rn, $Rm, $Ra",
2855 [(set GPR:$Rd, (add GPR:$Ra, (opnode (sra GPR:$Rn, (i32 16)),
2856 (sra GPR:$Rm, (i32 16)))))]>,
2857 Requires<[IsARM, HasV5TE]>;
2859 def WB : AMulxyIa<0b0001001, 0b00, (outs GPR:$Rd),
2860 (ins GPR:$Rn, GPR:$Rm, GPR:$Ra),
2861 IIC_iMAC16, !strconcat(opc, "wb"), "\t$Rd, $Rn, $Rm, $Ra",
2862 [(set GPR:$Rd, (add GPR:$Ra, (sra (opnode GPR:$Rn,
2863 (sext_inreg GPR:$Rm, i16)), (i32 16))))]>,
2864 Requires<[IsARM, HasV5TE]>;
2866 def WT : AMulxyIa<0b0001001, 0b10, (outs GPR:$Rd),
2867 (ins GPR:$Rn, GPR:$Rm, GPR:$Ra),
2868 IIC_iMAC16, !strconcat(opc, "wt"), "\t$Rd, $Rn, $Rm, $Ra",
2869 [(set GPR:$Rd, (add GPR:$Ra, (sra (opnode GPR:$Rn,
2870 (sra GPR:$Rm, (i32 16))), (i32 16))))]>,
2871 Requires<[IsARM, HasV5TE]>;
2874 defm SMUL : AI_smul<"smul", BinOpFrag<(mul node:$LHS, node:$RHS)>>;
2875 defm SMLA : AI_smla<"smla", BinOpFrag<(mul node:$LHS, node:$RHS)>>;
2877 // Halfword multiply accumulate long: SMLAL<x><y> -- for disassembly only
2878 def SMLALBB : AMulxyI64<0b0001010, 0b00, (outs GPR:$RdLo, GPR:$RdHi),
2879 (ins GPR:$Rn, GPR:$Rm),
2880 IIC_iMAC64, "smlalbb", "\t$RdLo, $RdHi, $Rn, $Rm",
2881 [/* For disassembly only; pattern left blank */]>,
2882 Requires<[IsARM, HasV5TE]>;
2884 def SMLALBT : AMulxyI64<0b0001010, 0b10, (outs GPR:$RdLo, GPR:$RdHi),
2885 (ins GPR:$Rn, GPR:$Rm),
2886 IIC_iMAC64, "smlalbt", "\t$RdLo, $RdHi, $Rn, $Rm",
2887 [/* For disassembly only; pattern left blank */]>,
2888 Requires<[IsARM, HasV5TE]>;
2890 def SMLALTB : AMulxyI64<0b0001010, 0b01, (outs GPR:$RdLo, GPR:$RdHi),
2891 (ins GPR:$Rn, GPR:$Rm),
2892 IIC_iMAC64, "smlaltb", "\t$RdLo, $RdHi, $Rn, $Rm",
2893 [/* For disassembly only; pattern left blank */]>,
2894 Requires<[IsARM, HasV5TE]>;
2896 def SMLALTT : AMulxyI64<0b0001010, 0b11, (outs GPR:$RdLo, GPR:$RdHi),
2897 (ins GPR:$Rn, GPR:$Rm),
2898 IIC_iMAC64, "smlaltt", "\t$RdLo, $RdHi, $Rn, $Rm",
2899 [/* For disassembly only; pattern left blank */]>,
2900 Requires<[IsARM, HasV5TE]>;
2902 // Helper class for AI_smld -- for disassembly only
2903 class AMulDualIbase<bit long, bit sub, bit swap, dag oops, dag iops,
2904 InstrItinClass itin, string opc, string asm>
2905 : AI<oops, iops, MulFrm, itin, opc, asm, []>, Requires<[IsARM, HasV6]> {
2912 let Inst{21-20} = 0b00;
2913 let Inst{22} = long;
2914 let Inst{27-23} = 0b01110;
2915 let Inst{11-8} = Rm;
2918 class AMulDualI<bit long, bit sub, bit swap, dag oops, dag iops,
2919 InstrItinClass itin, string opc, string asm>
2920 : AMulDualIbase<long, sub, swap, oops, iops, itin, opc, asm> {
2922 let Inst{15-12} = 0b1111;
2923 let Inst{19-16} = Rd;
2925 class AMulDualIa<bit long, bit sub, bit swap, dag oops, dag iops,
2926 InstrItinClass itin, string opc, string asm>
2927 : AMulDualIbase<long, sub, swap, oops, iops, itin, opc, asm> {
2929 let Inst{15-12} = Ra;
2931 class AMulDualI64<bit long, bit sub, bit swap, dag oops, dag iops,
2932 InstrItinClass itin, string opc, string asm>
2933 : AMulDualIbase<long, sub, swap, oops, iops, itin, opc, asm> {
2936 let Inst{19-16} = RdHi;
2937 let Inst{15-12} = RdLo;
2940 multiclass AI_smld<bit sub, string opc> {
2942 def D : AMulDualIa<0, sub, 0, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm, GPR:$Ra),
2943 NoItinerary, !strconcat(opc, "d"), "\t$Rd, $Rn, $Rm, $Ra">;
2945 def DX: AMulDualIa<0, sub, 1, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm, GPR:$Ra),
2946 NoItinerary, !strconcat(opc, "dx"), "\t$Rd, $Rn, $Rm, $Ra">;
2948 def LD: AMulDualI64<1, sub, 0, (outs GPR:$RdLo,GPR:$RdHi),
2949 (ins GPR:$Rn, GPR:$Rm), NoItinerary,
2950 !strconcat(opc, "ld"), "\t$RdLo, $RdHi, $Rn, $Rm">;
2952 def LDX : AMulDualI64<1, sub, 1, (outs GPR:$RdLo,GPR:$RdHi),
2953 (ins GPR:$Rn, GPR:$Rm), NoItinerary,
2954 !strconcat(opc, "ldx"),"\t$RdLo, $RdHi, $Rn, $Rm">;
2958 defm SMLA : AI_smld<0, "smla">;
2959 defm SMLS : AI_smld<1, "smls">;
2961 multiclass AI_sdml<bit sub, string opc> {
2963 def D : AMulDualI<0, sub, 0, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm),
2964 NoItinerary, !strconcat(opc, "d"), "\t$Rd, $Rn, $Rm">;
2965 def DX : AMulDualI<0, sub, 1, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm),
2966 NoItinerary, !strconcat(opc, "dx"), "\t$Rd, $Rn, $Rm">;
2969 defm SMUA : AI_sdml<0, "smua">;
2970 defm SMUS : AI_sdml<1, "smus">;
2972 //===----------------------------------------------------------------------===//
2973 // Misc. Arithmetic Instructions.
2976 def CLZ : AMiscA1I<0b000010110, 0b0001, (outs GPR:$Rd), (ins GPR:$Rm),
2977 IIC_iUNAr, "clz", "\t$Rd, $Rm",
2978 [(set GPR:$Rd, (ctlz GPR:$Rm))]>, Requires<[IsARM, HasV5T]>;
2980 def RBIT : AMiscA1I<0b01101111, 0b0011, (outs GPR:$Rd), (ins GPR:$Rm),
2981 IIC_iUNAr, "rbit", "\t$Rd, $Rm",
2982 [(set GPR:$Rd, (ARMrbit GPR:$Rm))]>,
2983 Requires<[IsARM, HasV6T2]>;
2985 def REV : AMiscA1I<0b01101011, 0b0011, (outs GPR:$Rd), (ins GPR:$Rm),
2986 IIC_iUNAr, "rev", "\t$Rd, $Rm",
2987 [(set GPR:$Rd, (bswap GPR:$Rm))]>, Requires<[IsARM, HasV6]>;
2989 def REV16 : AMiscA1I<0b01101011, 0b1011, (outs GPR:$Rd), (ins GPR:$Rm),
2990 IIC_iUNAr, "rev16", "\t$Rd, $Rm",
2992 (or (and (srl GPR:$Rm, (i32 8)), 0xFF),
2993 (or (and (shl GPR:$Rm, (i32 8)), 0xFF00),
2994 (or (and (srl GPR:$Rm, (i32 8)), 0xFF0000),
2995 (and (shl GPR:$Rm, (i32 8)), 0xFF000000)))))]>,
2996 Requires<[IsARM, HasV6]>;
2998 def REVSH : AMiscA1I<0b01101111, 0b1011, (outs GPR:$Rd), (ins GPR:$Rm),
2999 IIC_iUNAr, "revsh", "\t$Rd, $Rm",
3002 (or (srl (and GPR:$Rm, 0xFF00), (i32 8)),
3003 (shl GPR:$Rm, (i32 8))), i16))]>,
3004 Requires<[IsARM, HasV6]>;
3006 def lsl_shift_imm : SDNodeXForm<imm, [{
3007 unsigned Sh = ARM_AM::getSORegOpc(ARM_AM::lsl, N->getZExtValue());
3008 return CurDAG->getTargetConstant(Sh, MVT::i32);
3011 def lsl_amt : PatLeaf<(i32 imm), [{
3012 return (N->getZExtValue() < 32);
3015 def PKHBT : APKHI<0b01101000, 0, (outs GPR:$Rd),
3016 (ins GPR:$Rn, GPR:$Rm, shift_imm:$sh),
3017 IIC_iALUsi, "pkhbt", "\t$Rd, $Rn, $Rm$sh",
3018 [(set GPR:$Rd, (or (and GPR:$Rn, 0xFFFF),
3019 (and (shl GPR:$Rm, lsl_amt:$sh),
3021 Requires<[IsARM, HasV6]>;
3023 // Alternate cases for PKHBT where identities eliminate some nodes.
3024 def : ARMV6Pat<(or (and GPR:$Rn, 0xFFFF), (and GPR:$Rm, 0xFFFF0000)),
3025 (PKHBT GPR:$Rn, GPR:$Rm, 0)>;
3026 def : ARMV6Pat<(or (and GPR:$Rn, 0xFFFF), (shl GPR:$Rm, imm16_31:$sh)),
3027 (PKHBT GPR:$Rn, GPR:$Rm, (lsl_shift_imm imm16_31:$sh))>;
3029 def asr_shift_imm : SDNodeXForm<imm, [{
3030 unsigned Sh = ARM_AM::getSORegOpc(ARM_AM::asr, N->getZExtValue());
3031 return CurDAG->getTargetConstant(Sh, MVT::i32);
3034 def asr_amt : PatLeaf<(i32 imm), [{
3035 return (N->getZExtValue() <= 32);
3038 // Note: Shifts of 1-15 bits will be transformed to srl instead of sra and
3039 // will match the pattern below.
3040 def PKHTB : APKHI<0b01101000, 1, (outs GPR:$Rd),
3041 (ins GPR:$Rn, GPR:$Rm, shift_imm:$sh),
3042 IIC_iBITsi, "pkhtb", "\t$Rd, $Rn, $Rm$sh",
3043 [(set GPR:$Rd, (or (and GPR:$Rn, 0xFFFF0000),
3044 (and (sra GPR:$Rm, asr_amt:$sh),
3046 Requires<[IsARM, HasV6]>;
3048 // Alternate cases for PKHTB where identities eliminate some nodes. Note that
3049 // a shift amount of 0 is *not legal* here, it is PKHBT instead.
3050 def : ARMV6Pat<(or (and GPR:$src1, 0xFFFF0000), (srl GPR:$src2, imm16_31:$sh)),
3051 (PKHTB GPR:$src1, GPR:$src2, (asr_shift_imm imm16_31:$sh))>;
3052 def : ARMV6Pat<(or (and GPR:$src1, 0xFFFF0000),
3053 (and (srl GPR:$src2, imm1_15:$sh), 0xFFFF)),
3054 (PKHTB GPR:$src1, GPR:$src2, (asr_shift_imm imm1_15:$sh))>;
3056 //===----------------------------------------------------------------------===//
3057 // Comparison Instructions...
3060 defm CMP : AI1_cmp_irs<0b1010, "cmp",
3061 IIC_iCMPi, IIC_iCMPr, IIC_iCMPsr,
3062 BinOpFrag<(ARMcmp node:$LHS, node:$RHS)>>;
3064 // ARMcmpZ can re-use the above instruction definitions.
3065 def : ARMPat<(ARMcmpZ GPR:$src, so_imm:$imm),
3066 (CMPri GPR:$src, so_imm:$imm)>;
3067 def : ARMPat<(ARMcmpZ GPR:$src, GPR:$rhs),
3068 (CMPrr GPR:$src, GPR:$rhs)>;
3069 def : ARMPat<(ARMcmpZ GPR:$src, so_reg:$rhs),
3070 (CMPrs GPR:$src, so_reg:$rhs)>;
3072 // FIXME: We have to be careful when using the CMN instruction and comparison
3073 // with 0. One would expect these two pieces of code should give identical
3089 // However, the CMN gives the *opposite* result when r1 is 0. This is because
3090 // the carry flag is set in the CMP case but not in the CMN case. In short, the
3091 // CMP instruction doesn't perform a truncate of the (logical) NOT of 0 plus the
3092 // value of r0 and the carry bit (because the "carry bit" parameter to
3093 // AddWithCarry is defined as 1 in this case, the carry flag will always be set
3094 // when r0 >= 0). The CMN instruction doesn't perform a NOT of 0 so there is
3095 // never a "carry" when this AddWithCarry is performed (because the "carry bit"
3096 // parameter to AddWithCarry is defined as 0).
3098 // When x is 0 and unsigned:
3102 // ~x + 1 = 0x1 0000 0000
3103 // (-x = 0) != (0x1 0000 0000 = ~x + 1)
3105 // Therefore, we should disable CMN when comparing against zero, until we can
3106 // limit when the CMN instruction is used (when we know that the RHS is not 0 or
3107 // when it's a comparison which doesn't look at the 'carry' flag).
3109 // (See the ARM docs for the "AddWithCarry" pseudo-code.)
3111 // This is related to <rdar://problem/7569620>.
3113 //defm CMN : AI1_cmp_irs<0b1011, "cmn",
3114 // BinOpFrag<(ARMcmp node:$LHS,(ineg node:$RHS))>>;
3116 // Note that TST/TEQ don't set all the same flags that CMP does!
3117 defm TST : AI1_cmp_irs<0b1000, "tst",
3118 IIC_iTSTi, IIC_iTSTr, IIC_iTSTsr,
3119 BinOpFrag<(ARMcmpZ (and_su node:$LHS, node:$RHS), 0)>, 1>;
3120 defm TEQ : AI1_cmp_irs<0b1001, "teq",
3121 IIC_iTSTi, IIC_iTSTr, IIC_iTSTsr,
3122 BinOpFrag<(ARMcmpZ (xor_su node:$LHS, node:$RHS), 0)>, 1>;
3124 defm CMNz : AI1_cmp_irs<0b1011, "cmn",
3125 IIC_iCMPi, IIC_iCMPr, IIC_iCMPsr,
3126 BinOpFrag<(ARMcmpZ node:$LHS,(ineg node:$RHS))>>;
3128 //def : ARMPat<(ARMcmp GPR:$src, so_imm_neg:$imm),
3129 // (CMNri GPR:$src, so_imm_neg:$imm)>;
3131 def : ARMPat<(ARMcmpZ GPR:$src, so_imm_neg:$imm),
3132 (CMNzri GPR:$src, so_imm_neg:$imm)>;
3134 // Pseudo i64 compares for some floating point compares.
3135 let usesCustomInserter = 1, isBranch = 1, isTerminator = 1,
3137 def BCCi64 : PseudoInst<(outs),
3138 (ins i32imm:$cc, GPR:$lhs1, GPR:$lhs2, GPR:$rhs1, GPR:$rhs2, brtarget:$dst),
3140 [(ARMBcci64 imm:$cc, GPR:$lhs1, GPR:$lhs2, GPR:$rhs1, GPR:$rhs2, bb:$dst)]>;
3142 def BCCZi64 : PseudoInst<(outs),
3143 (ins i32imm:$cc, GPR:$lhs1, GPR:$lhs2, brtarget:$dst), IIC_Br,
3144 [(ARMBcci64 imm:$cc, GPR:$lhs1, GPR:$lhs2, 0, 0, bb:$dst)]>;
3145 } // usesCustomInserter
3148 // Conditional moves
3149 // FIXME: should be able to write a pattern for ARMcmov, but can't use
3150 // a two-value operand where a dag node expects two operands. :(
3151 // FIXME: These should all be pseudo-instructions that get expanded to
3152 // the normal MOV instructions. That would fix the dependency on
3153 // special casing them in tblgen.
3154 let neverHasSideEffects = 1 in {
3155 def MOVCCr : AI1<0b1101, (outs GPR:$Rd), (ins GPR:$false, GPR:$Rm), DPFrm,
3156 IIC_iCMOVr, "mov", "\t$Rd, $Rm",
3157 [/*(set GPR:$Rd, (ARMcmov GPR:$false, GPR:$Rm, imm:$cc, CCR:$ccr))*/]>,
3158 RegConstraint<"$false = $Rd">, UnaryDP {
3163 let Inst{15-12} = Rd;
3164 let Inst{11-4} = 0b00000000;
3168 def MOVCCs : AI1<0b1101, (outs GPR:$Rd),
3169 (ins GPR:$false, so_reg:$shift), DPSoRegFrm, IIC_iCMOVsr,
3170 "mov", "\t$Rd, $shift",
3171 [/*(set GPR:$Rd, (ARMcmov GPR:$false, so_reg:$shift, imm:$cc, CCR:$ccr))*/]>,
3172 RegConstraint<"$false = $Rd">, UnaryDP {
3177 let Inst{19-16} = 0;
3178 let Inst{15-12} = Rd;
3179 let Inst{11-0} = shift;
3182 let isMoveImm = 1 in
3183 def MOVCCi16 : AI1<0b1000, (outs GPR:$Rd), (ins GPR:$false, i32imm_hilo16:$imm),
3185 "movw", "\t$Rd, $imm",
3187 RegConstraint<"$false = $Rd">, Requires<[IsARM, HasV6T2]>,
3193 let Inst{19-16} = imm{15-12};
3194 let Inst{15-12} = Rd;
3195 let Inst{11-0} = imm{11-0};
3198 let isMoveImm = 1 in
3199 def MOVCCi : AI1<0b1101, (outs GPR:$Rd),
3200 (ins GPR:$false, so_imm:$imm), DPFrm, IIC_iCMOVi,
3201 "mov", "\t$Rd, $imm",
3202 [/*(set GPR:$Rd, (ARMcmov GPR:$false, so_imm:$imm, imm:$cc, CCR:$ccr))*/]>,
3203 RegConstraint<"$false = $Rd">, UnaryDP {
3208 let Inst{19-16} = 0b0000;
3209 let Inst{15-12} = Rd;
3210 let Inst{11-0} = imm;
3213 // Two instruction predicate mov immediate.
3214 let isMoveImm = 1 in
3215 def MOVCCi32imm : PseudoInst<(outs GPR:$Rd),
3216 (ins GPR:$false, i32imm:$src, pred:$p),
3217 IIC_iCMOVix2, []>, RegConstraint<"$false = $Rd">;
3219 let isMoveImm = 1 in
3220 def MVNCCi : AI1<0b1111, (outs GPR:$Rd),
3221 (ins GPR:$false, so_imm:$imm), DPFrm, IIC_iCMOVi,
3222 "mvn", "\t$Rd, $imm",
3223 [/*(set GPR:$Rd, (ARMcmov GPR:$false, so_imm_not:$imm, imm:$cc, CCR:$ccr))*/]>,
3224 RegConstraint<"$false = $Rd">, UnaryDP {
3229 let Inst{19-16} = 0b0000;
3230 let Inst{15-12} = Rd;
3231 let Inst{11-0} = imm;
3233 } // neverHasSideEffects
3235 //===----------------------------------------------------------------------===//
3236 // Atomic operations intrinsics
3239 def memb_opt : Operand<i32> {
3240 let PrintMethod = "printMemBOption";
3241 let ParserMatchClass = MemBarrierOptOperand;
3244 // memory barriers protect the atomic sequences
3245 let hasSideEffects = 1 in {
3246 def DMB : AInoP<(outs), (ins memb_opt:$opt), MiscFrm, NoItinerary,
3247 "dmb", "\t$opt", [(ARMMemBarrier (i32 imm:$opt))]>,
3248 Requires<[IsARM, HasDB]> {
3250 let Inst{31-4} = 0xf57ff05;
3251 let Inst{3-0} = opt;
3254 def DMB_MCR : AInoP<(outs), (ins GPR:$zero), MiscFrm, NoItinerary,
3255 "mcr", "\tp15, 0, $zero, c7, c10, 5",
3256 [(ARMMemBarrierMCR GPR:$zero)]>,
3257 Requires<[IsARM, HasV6]> {
3258 // FIXME: add encoding
3262 def DSB : AInoP<(outs), (ins memb_opt:$opt), MiscFrm, NoItinerary,
3264 [/* For disassembly only; pattern left blank */]>,
3265 Requires<[IsARM, HasDB]> {
3267 let Inst{31-4} = 0xf57ff04;
3268 let Inst{3-0} = opt;
3271 // ISB has only full system option -- for disassembly only
3272 def ISB : AInoP<(outs), (ins), MiscFrm, NoItinerary, "isb", "", []>,
3273 Requires<[IsARM, HasDB]> {
3274 let Inst{31-4} = 0xf57ff06;
3275 let Inst{3-0} = 0b1111;
3278 let usesCustomInserter = 1 in {
3279 let Uses = [CPSR] in {
3280 def ATOMIC_LOAD_ADD_I8 : PseudoInst<
3281 (outs GPR:$dst), (ins GPR:$ptr, GPR:$incr), NoItinerary,
3282 [(set GPR:$dst, (atomic_load_add_8 GPR:$ptr, GPR:$incr))]>;
3283 def ATOMIC_LOAD_SUB_I8 : PseudoInst<
3284 (outs GPR:$dst), (ins GPR:$ptr, GPR:$incr), NoItinerary,
3285 [(set GPR:$dst, (atomic_load_sub_8 GPR:$ptr, GPR:$incr))]>;
3286 def ATOMIC_LOAD_AND_I8 : PseudoInst<
3287 (outs GPR:$dst), (ins GPR:$ptr, GPR:$incr), NoItinerary,
3288 [(set GPR:$dst, (atomic_load_and_8 GPR:$ptr, GPR:$incr))]>;
3289 def ATOMIC_LOAD_OR_I8 : PseudoInst<
3290 (outs GPR:$dst), (ins GPR:$ptr, GPR:$incr), NoItinerary,
3291 [(set GPR:$dst, (atomic_load_or_8 GPR:$ptr, GPR:$incr))]>;
3292 def ATOMIC_LOAD_XOR_I8 : PseudoInst<
3293 (outs GPR:$dst), (ins GPR:$ptr, GPR:$incr), NoItinerary,
3294 [(set GPR:$dst, (atomic_load_xor_8 GPR:$ptr, GPR:$incr))]>;
3295 def ATOMIC_LOAD_NAND_I8 : PseudoInst<
3296 (outs GPR:$dst), (ins GPR:$ptr, GPR:$incr), NoItinerary,
3297 [(set GPR:$dst, (atomic_load_nand_8 GPR:$ptr, GPR:$incr))]>;
3298 def ATOMIC_LOAD_ADD_I16 : PseudoInst<
3299 (outs GPR:$dst), (ins GPR:$ptr, GPR:$incr), NoItinerary,
3300 [(set GPR:$dst, (atomic_load_add_16 GPR:$ptr, GPR:$incr))]>;
3301 def ATOMIC_LOAD_SUB_I16 : PseudoInst<
3302 (outs GPR:$dst), (ins GPR:$ptr, GPR:$incr), NoItinerary,
3303 [(set GPR:$dst, (atomic_load_sub_16 GPR:$ptr, GPR:$incr))]>;
3304 def ATOMIC_LOAD_AND_I16 : PseudoInst<
3305 (outs GPR:$dst), (ins GPR:$ptr, GPR:$incr), NoItinerary,
3306 [(set GPR:$dst, (atomic_load_and_16 GPR:$ptr, GPR:$incr))]>;
3307 def ATOMIC_LOAD_OR_I16 : PseudoInst<
3308 (outs GPR:$dst), (ins GPR:$ptr, GPR:$incr), NoItinerary,
3309 [(set GPR:$dst, (atomic_load_or_16 GPR:$ptr, GPR:$incr))]>;
3310 def ATOMIC_LOAD_XOR_I16 : PseudoInst<
3311 (outs GPR:$dst), (ins GPR:$ptr, GPR:$incr), NoItinerary,
3312 [(set GPR:$dst, (atomic_load_xor_16 GPR:$ptr, GPR:$incr))]>;
3313 def ATOMIC_LOAD_NAND_I16 : PseudoInst<
3314 (outs GPR:$dst), (ins GPR:$ptr, GPR:$incr), NoItinerary,
3315 [(set GPR:$dst, (atomic_load_nand_16 GPR:$ptr, GPR:$incr))]>;
3316 def ATOMIC_LOAD_ADD_I32 : PseudoInst<
3317 (outs GPR:$dst), (ins GPR:$ptr, GPR:$incr), NoItinerary,
3318 [(set GPR:$dst, (atomic_load_add_32 GPR:$ptr, GPR:$incr))]>;
3319 def ATOMIC_LOAD_SUB_I32 : PseudoInst<
3320 (outs GPR:$dst), (ins GPR:$ptr, GPR:$incr), NoItinerary,
3321 [(set GPR:$dst, (atomic_load_sub_32 GPR:$ptr, GPR:$incr))]>;
3322 def ATOMIC_LOAD_AND_I32 : PseudoInst<
3323 (outs GPR:$dst), (ins GPR:$ptr, GPR:$incr), NoItinerary,
3324 [(set GPR:$dst, (atomic_load_and_32 GPR:$ptr, GPR:$incr))]>;
3325 def ATOMIC_LOAD_OR_I32 : PseudoInst<
3326 (outs GPR:$dst), (ins GPR:$ptr, GPR:$incr), NoItinerary,
3327 [(set GPR:$dst, (atomic_load_or_32 GPR:$ptr, GPR:$incr))]>;
3328 def ATOMIC_LOAD_XOR_I32 : PseudoInst<
3329 (outs GPR:$dst), (ins GPR:$ptr, GPR:$incr), NoItinerary,
3330 [(set GPR:$dst, (atomic_load_xor_32 GPR:$ptr, GPR:$incr))]>;
3331 def ATOMIC_LOAD_NAND_I32 : PseudoInst<
3332 (outs GPR:$dst), (ins GPR:$ptr, GPR:$incr), NoItinerary,
3333 [(set GPR:$dst, (atomic_load_nand_32 GPR:$ptr, GPR:$incr))]>;
3335 def ATOMIC_SWAP_I8 : PseudoInst<
3336 (outs GPR:$dst), (ins GPR:$ptr, GPR:$new), NoItinerary,
3337 [(set GPR:$dst, (atomic_swap_8 GPR:$ptr, GPR:$new))]>;
3338 def ATOMIC_SWAP_I16 : PseudoInst<
3339 (outs GPR:$dst), (ins GPR:$ptr, GPR:$new), NoItinerary,
3340 [(set GPR:$dst, (atomic_swap_16 GPR:$ptr, GPR:$new))]>;
3341 def ATOMIC_SWAP_I32 : PseudoInst<
3342 (outs GPR:$dst), (ins GPR:$ptr, GPR:$new), NoItinerary,
3343 [(set GPR:$dst, (atomic_swap_32 GPR:$ptr, GPR:$new))]>;
3345 def ATOMIC_CMP_SWAP_I8 : PseudoInst<
3346 (outs GPR:$dst), (ins GPR:$ptr, GPR:$old, GPR:$new), NoItinerary,
3347 [(set GPR:$dst, (atomic_cmp_swap_8 GPR:$ptr, GPR:$old, GPR:$new))]>;
3348 def ATOMIC_CMP_SWAP_I16 : PseudoInst<
3349 (outs GPR:$dst), (ins GPR:$ptr, GPR:$old, GPR:$new), NoItinerary,
3350 [(set GPR:$dst, (atomic_cmp_swap_16 GPR:$ptr, GPR:$old, GPR:$new))]>;
3351 def ATOMIC_CMP_SWAP_I32 : PseudoInst<
3352 (outs GPR:$dst), (ins GPR:$ptr, GPR:$old, GPR:$new), NoItinerary,
3353 [(set GPR:$dst, (atomic_cmp_swap_32 GPR:$ptr, GPR:$old, GPR:$new))]>;
3357 let mayLoad = 1 in {
3358 def LDREXB : AIldrex<0b10, (outs GPR:$Rt), (ins GPR:$Rn), NoItinerary,
3359 "ldrexb", "\t$Rt, [$Rn]",
3361 def LDREXH : AIldrex<0b11, (outs GPR:$Rt), (ins GPR:$Rn), NoItinerary,
3362 "ldrexh", "\t$Rt, [$Rn]",
3364 def LDREX : AIldrex<0b00, (outs GPR:$Rt), (ins GPR:$Rn), NoItinerary,
3365 "ldrex", "\t$Rt, [$Rn]",
3367 def LDREXD : AIldrex<0b01, (outs GPR:$Rt, GPR:$Rt2), (ins GPR:$Rn),
3369 "ldrexd", "\t$Rt, $Rt2, [$Rn]",
3373 let mayStore = 1, Constraints = "@earlyclobber $Rd" in {
3374 def STREXB : AIstrex<0b10, (outs GPR:$Rd), (ins GPR:$src, GPR:$Rn),
3376 "strexb", "\t$Rd, $src, [$Rn]",
3378 def STREXH : AIstrex<0b11, (outs GPR:$Rd), (ins GPR:$Rt, GPR:$Rn),
3380 "strexh", "\t$Rd, $Rt, [$Rn]",
3382 def STREX : AIstrex<0b00, (outs GPR:$Rd), (ins GPR:$Rt, GPR:$Rn),
3384 "strex", "\t$Rd, $Rt, [$Rn]",
3386 def STREXD : AIstrex<0b01, (outs GPR:$Rd),
3387 (ins GPR:$Rt, GPR:$Rt2, GPR:$Rn),
3389 "strexd", "\t$Rd, $Rt, $Rt2, [$Rn]",
3393 // Clear-Exclusive is for disassembly only.
3394 def CLREX : AXI<(outs), (ins), MiscFrm, NoItinerary, "clrex",
3395 [/* For disassembly only; pattern left blank */]>,
3396 Requires<[IsARM, HasV7]> {
3397 let Inst{31-0} = 0b11110101011111111111000000011111;
3400 // SWP/SWPB are deprecated in V6/V7 and for disassembly only.
3401 let mayLoad = 1 in {
3402 def SWP : AIswp<0, (outs GPR:$Rt), (ins GPR:$Rt2, GPR:$Rn), "swp",
3403 [/* For disassembly only; pattern left blank */]>;
3404 def SWPB : AIswp<1, (outs GPR:$Rt), (ins GPR:$Rt2, GPR:$Rn), "swpb",
3405 [/* For disassembly only; pattern left blank */]>;
3408 //===----------------------------------------------------------------------===//
3409 // Coprocessor Instructions.
3412 def CDP : ABI<0b1110, (outs), (ins p_imm:$cop, i32imm:$opc1,
3413 c_imm:$CRd, c_imm:$CRn, c_imm:$CRm, i32imm:$opc2),
3414 NoItinerary, "cdp", "\t$cop, $opc1, $CRd, $CRn, $CRm, $opc2",
3415 [/* For disassembly only; pattern left blank */]> {
3423 let Inst{3-0} = CRm;
3425 let Inst{7-5} = opc2;
3426 let Inst{11-8} = cop;
3427 let Inst{15-12} = CRd;
3428 let Inst{19-16} = CRn;
3429 let Inst{23-20} = opc1;
3432 def CDP2 : ABXI<0b1110, (outs), (ins p_imm:$cop, i32imm:$opc1,
3433 c_imm:$CRd, c_imm:$CRn, c_imm:$CRm, i32imm:$opc2),
3434 NoItinerary, "cdp2\t$cop, $opc1, $CRd, $CRn, $CRm, $opc2",
3435 [/* For disassembly only; pattern left blank */]> {
3436 let Inst{31-28} = 0b1111;
3444 let Inst{3-0} = CRm;
3446 let Inst{7-5} = opc2;
3447 let Inst{11-8} = cop;
3448 let Inst{15-12} = CRd;
3449 let Inst{19-16} = CRn;
3450 let Inst{23-20} = opc1;
3453 class ACI<dag oops, dag iops, string opc, string asm>
3454 : I<oops, iops, AddrModeNone, Size4Bytes, IndexModeNone, BrFrm, NoItinerary,
3455 opc, asm, "", [/* For disassembly only; pattern left blank */]> {
3456 let Inst{27-25} = 0b110;
3459 multiclass LdStCop<bits<4> op31_28, bit load, string opc> {
3461 def _OFFSET : ACI<(outs),
3462 (ins nohash_imm:$cop, nohash_imm:$CRd, addrmode2:$addr),
3463 opc, "\tp$cop, cr$CRd, $addr"> {
3464 let Inst{31-28} = op31_28;
3465 let Inst{24} = 1; // P = 1
3466 let Inst{21} = 0; // W = 0
3467 let Inst{22} = 0; // D = 0
3468 let Inst{20} = load;
3471 def _PRE : ACI<(outs),
3472 (ins nohash_imm:$cop, nohash_imm:$CRd, addrmode2:$addr),
3473 opc, "\tp$cop, cr$CRd, $addr!"> {
3474 let Inst{31-28} = op31_28;
3475 let Inst{24} = 1; // P = 1
3476 let Inst{21} = 1; // W = 1
3477 let Inst{22} = 0; // D = 0
3478 let Inst{20} = load;
3481 def _POST : ACI<(outs),
3482 (ins nohash_imm:$cop, nohash_imm:$CRd, GPR:$base, am2offset:$offset),
3483 opc, "\tp$cop, cr$CRd, [$base], $offset"> {
3484 let Inst{31-28} = op31_28;
3485 let Inst{24} = 0; // P = 0
3486 let Inst{21} = 1; // W = 1
3487 let Inst{22} = 0; // D = 0
3488 let Inst{20} = load;
3491 def _OPTION : ACI<(outs),
3492 (ins nohash_imm:$cop, nohash_imm:$CRd, GPR:$base, i32imm:$option),
3493 opc, "\tp$cop, cr$CRd, [$base], $option"> {
3494 let Inst{31-28} = op31_28;
3495 let Inst{24} = 0; // P = 0
3496 let Inst{23} = 1; // U = 1
3497 let Inst{21} = 0; // W = 0
3498 let Inst{22} = 0; // D = 0
3499 let Inst{20} = load;
3502 def L_OFFSET : ACI<(outs),
3503 (ins nohash_imm:$cop, nohash_imm:$CRd, addrmode2:$addr),
3504 !strconcat(opc, "l"), "\tp$cop, cr$CRd, $addr"> {
3505 let Inst{31-28} = op31_28;
3506 let Inst{24} = 1; // P = 1
3507 let Inst{21} = 0; // W = 0
3508 let Inst{22} = 1; // D = 1
3509 let Inst{20} = load;
3512 def L_PRE : ACI<(outs),
3513 (ins nohash_imm:$cop, nohash_imm:$CRd, addrmode2:$addr),
3514 !strconcat(opc, "l"), "\tp$cop, cr$CRd, $addr!"> {
3515 let Inst{31-28} = op31_28;
3516 let Inst{24} = 1; // P = 1
3517 let Inst{21} = 1; // W = 1
3518 let Inst{22} = 1; // D = 1
3519 let Inst{20} = load;
3522 def L_POST : ACI<(outs),
3523 (ins nohash_imm:$cop, nohash_imm:$CRd, GPR:$base, am2offset:$offset),
3524 !strconcat(opc, "l"), "\tp$cop, cr$CRd, [$base], $offset"> {
3525 let Inst{31-28} = op31_28;
3526 let Inst{24} = 0; // P = 0
3527 let Inst{21} = 1; // W = 1
3528 let Inst{22} = 1; // D = 1
3529 let Inst{20} = load;
3532 def L_OPTION : ACI<(outs),
3533 (ins nohash_imm:$cop, nohash_imm:$CRd, GPR:$base, nohash_imm:$option),
3534 !strconcat(opc, "l"), "\tp$cop, cr$CRd, [$base], $option"> {
3535 let Inst{31-28} = op31_28;
3536 let Inst{24} = 0; // P = 0
3537 let Inst{23} = 1; // U = 1
3538 let Inst{21} = 0; // W = 0
3539 let Inst{22} = 1; // D = 1
3540 let Inst{20} = load;
3544 defm LDC : LdStCop<{?,?,?,?}, 1, "ldc">;
3545 defm LDC2 : LdStCop<0b1111, 1, "ldc2">;
3546 defm STC : LdStCop<{?,?,?,?}, 0, "stc">;
3547 defm STC2 : LdStCop<0b1111, 0, "stc2">;
3549 //===----------------------------------------------------------------------===//
3550 // Move between coprocessor and ARM core register -- for disassembly only
3553 class MovRCopro<string opc, bit direction>
3554 : ABI<0b1110, (outs), (ins p_imm:$cop, i32imm:$opc1,
3555 GPR:$Rt, c_imm:$CRn, c_imm:$CRm, i32imm:$opc2),
3556 NoItinerary, opc, "\t$cop, $opc1, $Rt, $CRn, $CRm, $opc2",
3557 [/* For disassembly only; pattern left blank */]> {
3558 let Inst{20} = direction;
3568 let Inst{15-12} = Rt;
3569 let Inst{11-8} = cop;
3570 let Inst{23-21} = opc1;
3571 let Inst{7-5} = opc2;
3572 let Inst{3-0} = CRm;
3573 let Inst{19-16} = CRn;
3576 def MCR : MovRCopro<"mcr", 0 /* from ARM core register to coprocessor */>;
3577 def MRC : MovRCopro<"mrc", 1 /* from coprocessor to ARM core register */>;
3579 class MovRCopro2<string opc, bit direction>
3580 : ABXI<0b1110, (outs), (ins p_imm:$cop, i32imm:$opc1,
3581 GPR:$Rt, c_imm:$CRn, c_imm:$CRm, i32imm:$opc2),
3582 NoItinerary, !strconcat(opc, "\t$cop, $opc1, $Rt, $CRn, $CRm, $opc2"),
3583 [/* For disassembly only; pattern left blank */]> {
3584 let Inst{31-28} = 0b1111;
3585 let Inst{20} = direction;
3595 let Inst{15-12} = Rt;
3596 let Inst{11-8} = cop;
3597 let Inst{23-21} = opc1;
3598 let Inst{7-5} = opc2;
3599 let Inst{3-0} = CRm;
3600 let Inst{19-16} = CRn;
3603 def MCR2 : MovRCopro2<"mcr2", 0 /* from ARM core register to coprocessor */>;
3604 def MRC2 : MovRCopro2<"mrc2", 1 /* from coprocessor to ARM core register */>;
3606 class MovRRCopro<string opc, bit direction>
3607 : ABI<0b1100, (outs), (ins p_imm:$cop, i32imm:$opc1,
3608 GPR:$Rt, GPR:$Rt2, c_imm:$CRm),
3609 NoItinerary, opc, "\t$cop, $opc1, $Rt, $Rt2, $CRm",
3610 [/* For disassembly only; pattern left blank */]> {
3611 let Inst{23-21} = 0b010;
3612 let Inst{20} = direction;
3620 let Inst{15-12} = Rt;
3621 let Inst{19-16} = Rt2;
3622 let Inst{11-8} = cop;
3623 let Inst{7-4} = opc1;
3624 let Inst{3-0} = CRm;
3627 def MCRR : MovRRCopro<"mcrr", 0 /* from ARM core register to coprocessor */>;
3628 def MRRC : MovRRCopro<"mrrc", 1 /* from coprocessor to ARM core register */>;
3630 class MovRRCopro2<string opc, bit direction>
3631 : ABXI<0b1100, (outs), (ins p_imm:$cop, i32imm:$opc1,
3632 GPR:$Rt, GPR:$Rt2, c_imm:$CRm),
3633 NoItinerary, !strconcat(opc, "\t$cop, $opc1, $Rt, $Rt2, $CRm"),
3634 [/* For disassembly only; pattern left blank */]> {
3635 let Inst{31-28} = 0b1111;
3636 let Inst{23-21} = 0b010;
3637 let Inst{20} = direction;
3645 let Inst{15-12} = Rt;
3646 let Inst{19-16} = Rt2;
3647 let Inst{11-8} = cop;
3648 let Inst{7-4} = opc1;
3649 let Inst{3-0} = CRm;
3652 def MCRR2 : MovRRCopro2<"mcrr2", 0 /* from ARM core register to coprocessor */>;
3653 def MRRC2 : MovRRCopro2<"mrrc2", 1 /* from coprocessor to ARM core register */>;
3655 //===----------------------------------------------------------------------===//
3656 // Move between special register and ARM core register -- for disassembly only
3659 // Move to ARM core register from Special Register
3660 def MRS : ABI<0b0001, (outs GPR:$Rd), (ins), NoItinerary, "mrs", "\t$Rd, cpsr",
3661 [/* For disassembly only; pattern left blank */]> {
3663 let Inst{23-16} = 0b00001111;
3664 let Inst{15-12} = Rd;
3665 let Inst{7-4} = 0b0000;
3668 def MRSsys : ABI<0b0001, (outs GPR:$Rd), (ins), NoItinerary,"mrs","\t$Rd, spsr",
3669 [/* For disassembly only; pattern left blank */]> {
3671 let Inst{23-16} = 0b01001111;
3672 let Inst{15-12} = Rd;
3673 let Inst{7-4} = 0b0000;
3676 // Move from ARM core register to Special Register
3678 // No need to have both system and application versions, the encodings are the
3679 // same and the assembly parser has no way to distinguish between them. The mask
3680 // operand contains the special register (R Bit) in bit 4 and bits 3-0 contains
3681 // the mask with the fields to be accessed in the special register.
3682 def MSR : ABI<0b0001, (outs), (ins msr_mask:$mask, GPR:$Rn), NoItinerary,
3683 "msr", "\t$mask, $Rn",
3684 [/* For disassembly only; pattern left blank */]> {
3689 let Inst{22} = mask{4}; // R bit
3690 let Inst{21-20} = 0b10;
3691 let Inst{19-16} = mask{3-0};
3692 let Inst{15-12} = 0b1111;
3693 let Inst{11-4} = 0b00000000;
3697 def MSRi : ABI<0b0011, (outs), (ins msr_mask:$mask, so_imm:$a), NoItinerary,
3698 "msr", "\t$mask, $a",
3699 [/* For disassembly only; pattern left blank */]> {
3704 let Inst{22} = mask{4}; // R bit
3705 let Inst{21-20} = 0b10;
3706 let Inst{19-16} = mask{3-0};
3707 let Inst{15-12} = 0b1111;
3711 //===----------------------------------------------------------------------===//
3715 // __aeabi_read_tp preserves the registers r1-r3.
3716 // This is a pseudo inst so that we can get the encoding right,
3717 // complete with fixup for the aeabi_read_tp function.
3719 Defs = [R0, R12, LR, CPSR], Uses = [SP] in {
3720 def TPsoft : PseudoInst<(outs), (ins), IIC_Br,
3721 [(set R0, ARMthread_pointer)]>;
3724 //===----------------------------------------------------------------------===//
3725 // SJLJ Exception handling intrinsics
3726 // eh_sjlj_setjmp() is an instruction sequence to store the return
3727 // address and save #0 in R0 for the non-longjmp case.
3728 // Since by its nature we may be coming from some other function to get
3729 // here, and we're using the stack frame for the containing function to
3730 // save/restore registers, we can't keep anything live in regs across
3731 // the eh_sjlj_setjmp(), else it will almost certainly have been tromped upon
3732 // when we get here from a longjmp(). We force everthing out of registers
3733 // except for our own input by listing the relevant registers in Defs. By
3734 // doing so, we also cause the prologue/epilogue code to actively preserve
3735 // all of the callee-saved resgisters, which is exactly what we want.
3736 // A constant value is passed in $val, and we use the location as a scratch.
3738 // These are pseudo-instructions and are lowered to individual MC-insts, so
3739 // no encoding information is necessary.
3741 [ R0, R1, R2, R3, R4, R5, R6, R7, R8, R9, R10, R11, R12, LR, D0,
3742 D1, D2, D3, D4, D5, D6, D7, D8, D9, D10, D11, D12, D13, D14, D15,
3743 D16, D17, D18, D19, D20, D21, D22, D23, D24, D25, D26, D27, D28, D29, D30,
3744 D31 ], hasSideEffects = 1, isBarrier = 1 in {
3745 def Int_eh_sjlj_setjmp : PseudoInst<(outs), (ins GPR:$src, GPR:$val),
3747 [(set R0, (ARMeh_sjlj_setjmp GPR:$src, GPR:$val))]>,
3748 Requires<[IsARM, HasVFP2]>;
3752 [ R0, R1, R2, R3, R4, R5, R6, R7, R8, R9, R10, R11, R12, LR ],
3753 hasSideEffects = 1, isBarrier = 1 in {
3754 def Int_eh_sjlj_setjmp_nofp : PseudoInst<(outs), (ins GPR:$src, GPR:$val),
3756 [(set R0, (ARMeh_sjlj_setjmp GPR:$src, GPR:$val))]>,
3757 Requires<[IsARM, NoVFP]>;
3760 // FIXME: Non-Darwin version(s)
3761 let isBarrier = 1, hasSideEffects = 1, isTerminator = 1,
3762 Defs = [ R7, LR, SP ] in {
3763 def Int_eh_sjlj_longjmp : PseudoInst<(outs), (ins GPR:$src, GPR:$scratch),
3765 [(ARMeh_sjlj_longjmp GPR:$src, GPR:$scratch)]>,
3766 Requires<[IsARM, IsDarwin]>;
3769 // eh.sjlj.dispatchsetup pseudo-instruction.
3770 // This pseudo is used for ARM, Thumb1 and Thumb2. Any differences are
3771 // handled when the pseudo is expanded (which happens before any passes
3772 // that need the instruction size).
3773 let isBarrier = 1, hasSideEffects = 1 in
3774 def Int_eh_sjlj_dispatchsetup :
3775 PseudoInst<(outs), (ins GPR:$src), NoItinerary,
3776 [(ARMeh_sjlj_dispatchsetup GPR:$src)]>,
3777 Requires<[IsDarwin]>;
3779 //===----------------------------------------------------------------------===//
3780 // Non-Instruction Patterns
3783 // Large immediate handling.
3785 // 32-bit immediate using two piece so_imms or movw + movt.
3786 // This is a single pseudo instruction, the benefit is that it can be remat'd
3787 // as a single unit instead of having to handle reg inputs.
3788 // FIXME: Remove this when we can do generalized remat.
3789 let isReMaterializable = 1, isMoveImm = 1 in
3790 def MOVi32imm : PseudoInst<(outs GPR:$dst), (ins i32imm:$src), IIC_iMOVix2,
3791 [(set GPR:$dst, (arm_i32imm:$src))]>,
3794 // Pseudo instruction that combines movw + movt + add pc (if PIC).
3795 // It also makes it possible to rematerialize the instructions.
3796 // FIXME: Remove this when we can do generalized remat and when machine licm
3797 // can properly the instructions.
3798 let isReMaterializable = 1 in {
3799 def MOV_ga_pcrel : PseudoInst<(outs GPR:$dst), (ins i32imm:$addr),
3801 [(set GPR:$dst, (ARMWrapperPIC tglobaladdr:$addr))]>,
3802 Requires<[IsARM, UseMovt]>;
3804 def MOV_ga_dyn : PseudoInst<(outs GPR:$dst), (ins i32imm:$addr),
3806 [(set GPR:$dst, (ARMWrapperDYN tglobaladdr:$addr))]>,
3807 Requires<[IsARM, UseMovt]>;
3809 let AddedComplexity = 10 in
3810 def MOV_ga_pcrel_ldr : PseudoInst<(outs GPR:$dst), (ins i32imm:$addr),
3812 [(set GPR:$dst, (load (ARMWrapperPIC tglobaladdr:$addr)))]>,
3813 Requires<[IsARM, UseMovt]>;
3814 } // isReMaterializable
3816 // ConstantPool, GlobalAddress, and JumpTable
3817 def : ARMPat<(ARMWrapper tglobaladdr :$dst), (LEApcrel tglobaladdr :$dst)>,
3818 Requires<[IsARM, DontUseMovt]>;
3819 def : ARMPat<(ARMWrapper tconstpool :$dst), (LEApcrel tconstpool :$dst)>;
3820 def : ARMPat<(ARMWrapper tglobaladdr :$dst), (MOVi32imm tglobaladdr :$dst)>,
3821 Requires<[IsARM, UseMovt]>;
3822 def : ARMPat<(ARMWrapperJT tjumptable:$dst, imm:$id),
3823 (LEApcrelJT tjumptable:$dst, imm:$id)>;
3825 // TODO: add,sub,and, 3-instr forms?
3828 def : ARMPat<(ARMtcret tcGPR:$dst),
3829 (TCRETURNri tcGPR:$dst)>, Requires<[IsDarwin]>;
3831 def : ARMPat<(ARMtcret (i32 tglobaladdr:$dst)),
3832 (TCRETURNdi texternalsym:$dst)>, Requires<[IsDarwin]>;
3834 def : ARMPat<(ARMtcret (i32 texternalsym:$dst)),
3835 (TCRETURNdi texternalsym:$dst)>, Requires<[IsDarwin]>;
3837 def : ARMPat<(ARMtcret tcGPR:$dst),
3838 (TCRETURNriND tcGPR:$dst)>, Requires<[IsNotDarwin]>;
3840 def : ARMPat<(ARMtcret (i32 tglobaladdr:$dst)),
3841 (TCRETURNdiND texternalsym:$dst)>, Requires<[IsNotDarwin]>;
3843 def : ARMPat<(ARMtcret (i32 texternalsym:$dst)),
3844 (TCRETURNdiND texternalsym:$dst)>, Requires<[IsNotDarwin]>;
3847 def : ARMPat<(ARMcall texternalsym:$func), (BL texternalsym:$func)>,
3848 Requires<[IsARM, IsNotDarwin]>;
3849 def : ARMPat<(ARMcall texternalsym:$func), (BLr9 texternalsym:$func)>,
3850 Requires<[IsARM, IsDarwin]>;
3852 // zextload i1 -> zextload i8
3853 def : ARMPat<(zextloadi1 addrmode_imm12:$addr), (LDRBi12 addrmode_imm12:$addr)>;
3854 def : ARMPat<(zextloadi1 ldst_so_reg:$addr), (LDRBrs ldst_so_reg:$addr)>;
3856 // extload -> zextload
3857 def : ARMPat<(extloadi1 addrmode_imm12:$addr), (LDRBi12 addrmode_imm12:$addr)>;
3858 def : ARMPat<(extloadi1 ldst_so_reg:$addr), (LDRBrs ldst_so_reg:$addr)>;
3859 def : ARMPat<(extloadi8 addrmode_imm12:$addr), (LDRBi12 addrmode_imm12:$addr)>;
3860 def : ARMPat<(extloadi8 ldst_so_reg:$addr), (LDRBrs ldst_so_reg:$addr)>;
3862 def : ARMPat<(extloadi16 addrmode3:$addr), (LDRH addrmode3:$addr)>;
3864 def : ARMPat<(extloadi8 addrmodepc:$addr), (PICLDRB addrmodepc:$addr)>;
3865 def : ARMPat<(extloadi16 addrmodepc:$addr), (PICLDRH addrmodepc:$addr)>;
3868 def : ARMV5TEPat<(mul (sra (shl GPR:$a, (i32 16)), (i32 16)),
3869 (sra (shl GPR:$b, (i32 16)), (i32 16))),
3870 (SMULBB GPR:$a, GPR:$b)>;
3871 def : ARMV5TEPat<(mul sext_16_node:$a, sext_16_node:$b),
3872 (SMULBB GPR:$a, GPR:$b)>;
3873 def : ARMV5TEPat<(mul (sra (shl GPR:$a, (i32 16)), (i32 16)),
3874 (sra GPR:$b, (i32 16))),
3875 (SMULBT GPR:$a, GPR:$b)>;
3876 def : ARMV5TEPat<(mul sext_16_node:$a, (sra GPR:$b, (i32 16))),
3877 (SMULBT GPR:$a, GPR:$b)>;
3878 def : ARMV5TEPat<(mul (sra GPR:$a, (i32 16)),
3879 (sra (shl GPR:$b, (i32 16)), (i32 16))),
3880 (SMULTB GPR:$a, GPR:$b)>;
3881 def : ARMV5TEPat<(mul (sra GPR:$a, (i32 16)), sext_16_node:$b),
3882 (SMULTB GPR:$a, GPR:$b)>;
3883 def : ARMV5TEPat<(sra (mul GPR:$a, (sra (shl GPR:$b, (i32 16)), (i32 16))),
3885 (SMULWB GPR:$a, GPR:$b)>;
3886 def : ARMV5TEPat<(sra (mul GPR:$a, sext_16_node:$b), (i32 16)),
3887 (SMULWB GPR:$a, GPR:$b)>;
3889 def : ARMV5TEPat<(add GPR:$acc,
3890 (mul (sra (shl GPR:$a, (i32 16)), (i32 16)),
3891 (sra (shl GPR:$b, (i32 16)), (i32 16)))),
3892 (SMLABB GPR:$a, GPR:$b, GPR:$acc)>;
3893 def : ARMV5TEPat<(add GPR:$acc,
3894 (mul sext_16_node:$a, sext_16_node:$b)),
3895 (SMLABB GPR:$a, GPR:$b, GPR:$acc)>;
3896 def : ARMV5TEPat<(add GPR:$acc,
3897 (mul (sra (shl GPR:$a, (i32 16)), (i32 16)),
3898 (sra GPR:$b, (i32 16)))),
3899 (SMLABT GPR:$a, GPR:$b, GPR:$acc)>;
3900 def : ARMV5TEPat<(add GPR:$acc,
3901 (mul sext_16_node:$a, (sra GPR:$b, (i32 16)))),
3902 (SMLABT GPR:$a, GPR:$b, GPR:$acc)>;
3903 def : ARMV5TEPat<(add GPR:$acc,
3904 (mul (sra GPR:$a, (i32 16)),
3905 (sra (shl GPR:$b, (i32 16)), (i32 16)))),
3906 (SMLATB GPR:$a, GPR:$b, GPR:$acc)>;
3907 def : ARMV5TEPat<(add GPR:$acc,
3908 (mul (sra GPR:$a, (i32 16)), sext_16_node:$b)),
3909 (SMLATB GPR:$a, GPR:$b, GPR:$acc)>;
3910 def : ARMV5TEPat<(add GPR:$acc,
3911 (sra (mul GPR:$a, (sra (shl GPR:$b, (i32 16)), (i32 16))),
3913 (SMLAWB GPR:$a, GPR:$b, GPR:$acc)>;
3914 def : ARMV5TEPat<(add GPR:$acc,
3915 (sra (mul GPR:$a, sext_16_node:$b), (i32 16))),
3916 (SMLAWB GPR:$a, GPR:$b, GPR:$acc)>;
3918 //===----------------------------------------------------------------------===//
3922 include "ARMInstrThumb.td"
3924 //===----------------------------------------------------------------------===//
3928 include "ARMInstrThumb2.td"
3930 //===----------------------------------------------------------------------===//
3931 // Floating Point Support
3934 include "ARMInstrVFP.td"
3936 //===----------------------------------------------------------------------===//
3937 // Advanced SIMD (NEON) Support
3940 include "ARMInstrNEON.td"