1 //===- ARMInstrInfo.td - Target Description for ARM Target -*- tablegen -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file describes the ARM instructions in TableGen format.
12 //===----------------------------------------------------------------------===//
14 //===----------------------------------------------------------------------===//
15 // ARM specific DAG Nodes.
19 def SDT_ARMCallSeqStart : SDCallSeqStart<[ SDTCisVT<0, i32> ]>;
20 def SDT_ARMCallSeqEnd : SDCallSeqEnd<[ SDTCisVT<0, i32>, SDTCisVT<1, i32> ]>;
21 def SDT_ARMStructByVal : SDTypeProfile<0, 4,
22 [SDTCisVT<0, i32>, SDTCisVT<1, i32>,
23 SDTCisVT<2, i32>, SDTCisVT<3, i32>]>;
25 def SDT_ARMSaveCallPC : SDTypeProfile<0, 1, []>;
27 def SDT_ARMcall : SDTypeProfile<0, -1, [SDTCisPtrTy<0>]>;
29 def SDT_ARMCMov : SDTypeProfile<1, 3,
30 [SDTCisSameAs<0, 1>, SDTCisSameAs<0, 2>,
33 def SDT_ARMBrcond : SDTypeProfile<0, 2,
34 [SDTCisVT<0, OtherVT>, SDTCisVT<1, i32>]>;
36 def SDT_ARMBrJT : SDTypeProfile<0, 2,
37 [SDTCisPtrTy<0>, SDTCisVT<1, i32>]>;
39 def SDT_ARMBr2JT : SDTypeProfile<0, 3,
40 [SDTCisPtrTy<0>, SDTCisVT<1, i32>,
43 def SDT_ARMBCC_i64 : SDTypeProfile<0, 6,
45 SDTCisVT<1, i32>, SDTCisVT<2, i32>,
46 SDTCisVT<3, i32>, SDTCisVT<4, i32>,
47 SDTCisVT<5, OtherVT>]>;
49 def SDT_ARMAnd : SDTypeProfile<1, 2,
50 [SDTCisVT<0, i32>, SDTCisVT<1, i32>,
53 def SDT_ARMCmp : SDTypeProfile<0, 2, [SDTCisSameAs<0, 1>]>;
55 def SDT_ARMPICAdd : SDTypeProfile<1, 2, [SDTCisSameAs<0, 1>,
56 SDTCisPtrTy<1>, SDTCisVT<2, i32>]>;
58 def SDT_ARMThreadPointer : SDTypeProfile<1, 0, [SDTCisPtrTy<0>]>;
59 def SDT_ARMEH_SJLJ_Setjmp : SDTypeProfile<1, 2, [SDTCisInt<0>, SDTCisPtrTy<1>,
61 def SDT_ARMEH_SJLJ_Longjmp: SDTypeProfile<0, 2, [SDTCisPtrTy<0>, SDTCisInt<1>]>;
62 def SDT_ARMEH_SJLJ_SetupDispatch: SDTypeProfile<0, 0, []>;
64 def SDT_ARMMEMBARRIER : SDTypeProfile<0, 1, [SDTCisInt<0>]>;
66 def SDT_ARMPREFETCH : SDTypeProfile<0, 3, [SDTCisPtrTy<0>, SDTCisSameAs<1, 2>,
69 def SDT_ARMTCRET : SDTypeProfile<0, 1, [SDTCisPtrTy<0>]>;
71 def SDT_ARMBFI : SDTypeProfile<1, 3, [SDTCisVT<0, i32>, SDTCisVT<1, i32>,
72 SDTCisVT<2, i32>, SDTCisVT<3, i32>]>;
74 def SDT_WIN__DBZCHK : SDTypeProfile<0, 1, [SDTCisVT<0, i32>]>;
76 def SDT_ARMMEMCPY : SDTypeProfile<2, 3, [SDTCisVT<0, i32>, SDTCisVT<1, i32>,
77 SDTCisVT<2, i32>, SDTCisVT<3, i32>,
80 def SDTBinaryArithWithFlags : SDTypeProfile<2, 2,
83 SDTCisInt<0>, SDTCisVT<1, i32>]>;
85 // SDTBinaryArithWithFlagsInOut - RES1, CPSR = op LHS, RHS, CPSR
86 def SDTBinaryArithWithFlagsInOut : SDTypeProfile<2, 3,
93 def SDT_ARM64bitmlal : SDTypeProfile<2,4, [ SDTCisVT<0, i32>, SDTCisVT<1, i32>,
94 SDTCisVT<2, i32>, SDTCisVT<3, i32>,
95 SDTCisVT<4, i32>, SDTCisVT<5, i32> ] >;
96 def ARMUmlal : SDNode<"ARMISD::UMLAL", SDT_ARM64bitmlal>;
97 def ARMSmlal : SDNode<"ARMISD::SMLAL", SDT_ARM64bitmlal>;
100 def ARMWrapper : SDNode<"ARMISD::Wrapper", SDTIntUnaryOp>;
101 def ARMWrapperPIC : SDNode<"ARMISD::WrapperPIC", SDTIntUnaryOp>;
102 def ARMWrapperJT : SDNode<"ARMISD::WrapperJT", SDTIntUnaryOp>;
104 def ARMcallseq_start : SDNode<"ISD::CALLSEQ_START", SDT_ARMCallSeqStart,
105 [SDNPHasChain, SDNPSideEffect, SDNPOutGlue]>;
106 def ARMcallseq_end : SDNode<"ISD::CALLSEQ_END", SDT_ARMCallSeqEnd,
107 [SDNPHasChain, SDNPSideEffect,
108 SDNPOptInGlue, SDNPOutGlue]>;
109 def ARMcopystructbyval : SDNode<"ARMISD::COPY_STRUCT_BYVAL" ,
111 [SDNPHasChain, SDNPInGlue, SDNPOutGlue,
112 SDNPMayStore, SDNPMayLoad]>;
114 def ARMcall : SDNode<"ARMISD::CALL", SDT_ARMcall,
115 [SDNPHasChain, SDNPOptInGlue, SDNPOutGlue,
117 def ARMcall_pred : SDNode<"ARMISD::CALL_PRED", SDT_ARMcall,
118 [SDNPHasChain, SDNPOptInGlue, SDNPOutGlue,
120 def ARMcall_nolink : SDNode<"ARMISD::CALL_NOLINK", SDT_ARMcall,
121 [SDNPHasChain, SDNPOptInGlue, SDNPOutGlue,
124 def ARMretflag : SDNode<"ARMISD::RET_FLAG", SDTNone,
125 [SDNPHasChain, SDNPOptInGlue, SDNPVariadic]>;
126 def ARMintretflag : SDNode<"ARMISD::INTRET_FLAG", SDT_ARMcall,
127 [SDNPHasChain, SDNPOptInGlue, SDNPVariadic]>;
128 def ARMcmov : SDNode<"ARMISD::CMOV", SDT_ARMCMov,
131 def ARMbrcond : SDNode<"ARMISD::BRCOND", SDT_ARMBrcond,
132 [SDNPHasChain, SDNPInGlue, SDNPOutGlue]>;
134 def ARMbrjt : SDNode<"ARMISD::BR_JT", SDT_ARMBrJT,
136 def ARMbr2jt : SDNode<"ARMISD::BR2_JT", SDT_ARMBr2JT,
139 def ARMBcci64 : SDNode<"ARMISD::BCC_i64", SDT_ARMBCC_i64,
142 def ARMcmp : SDNode<"ARMISD::CMP", SDT_ARMCmp,
145 def ARMcmn : SDNode<"ARMISD::CMN", SDT_ARMCmp,
148 def ARMcmpZ : SDNode<"ARMISD::CMPZ", SDT_ARMCmp,
149 [SDNPOutGlue, SDNPCommutative]>;
151 def ARMpic_add : SDNode<"ARMISD::PIC_ADD", SDT_ARMPICAdd>;
153 def ARMsrl_flag : SDNode<"ARMISD::SRL_FLAG", SDTIntUnaryOp, [SDNPOutGlue]>;
154 def ARMsra_flag : SDNode<"ARMISD::SRA_FLAG", SDTIntUnaryOp, [SDNPOutGlue]>;
155 def ARMrrx : SDNode<"ARMISD::RRX" , SDTIntUnaryOp, [SDNPInGlue ]>;
157 def ARMaddc : SDNode<"ARMISD::ADDC", SDTBinaryArithWithFlags,
159 def ARMsubc : SDNode<"ARMISD::SUBC", SDTBinaryArithWithFlags>;
160 def ARMadde : SDNode<"ARMISD::ADDE", SDTBinaryArithWithFlagsInOut>;
161 def ARMsube : SDNode<"ARMISD::SUBE", SDTBinaryArithWithFlagsInOut>;
163 def ARMthread_pointer: SDNode<"ARMISD::THREAD_POINTER", SDT_ARMThreadPointer>;
164 def ARMeh_sjlj_setjmp: SDNode<"ARMISD::EH_SJLJ_SETJMP",
165 SDT_ARMEH_SJLJ_Setjmp,
166 [SDNPHasChain, SDNPSideEffect]>;
167 def ARMeh_sjlj_longjmp: SDNode<"ARMISD::EH_SJLJ_LONGJMP",
168 SDT_ARMEH_SJLJ_Longjmp,
169 [SDNPHasChain, SDNPSideEffect]>;
170 def ARMeh_sjlj_setup_dispatch: SDNode<"ARMISD::EH_SJLJ_SETUP_DISPATCH",
171 SDT_ARMEH_SJLJ_SetupDispatch,
172 [SDNPHasChain, SDNPSideEffect]>;
174 def ARMMemBarrierMCR : SDNode<"ARMISD::MEMBARRIER_MCR", SDT_ARMMEMBARRIER,
175 [SDNPHasChain, SDNPSideEffect]>;
176 def ARMPreload : SDNode<"ARMISD::PRELOAD", SDT_ARMPREFETCH,
177 [SDNPHasChain, SDNPMayLoad, SDNPMayStore]>;
179 def ARMtcret : SDNode<"ARMISD::TC_RETURN", SDT_ARMTCRET,
180 [SDNPHasChain, SDNPOptInGlue, SDNPVariadic]>;
182 def ARMbfi : SDNode<"ARMISD::BFI", SDT_ARMBFI>;
184 def ARMmemcopy : SDNode<"ARMISD::MEMCPY", SDT_ARMMEMCPY,
185 [SDNPHasChain, SDNPInGlue, SDNPOutGlue,
186 SDNPMayStore, SDNPMayLoad]>;
188 //===----------------------------------------------------------------------===//
189 // ARM Instruction Predicate Definitions.
191 def HasV4T : Predicate<"Subtarget->hasV4TOps()">,
192 AssemblerPredicate<"HasV4TOps", "armv4t">;
193 def NoV4T : Predicate<"!Subtarget->hasV4TOps()">;
194 def HasV5T : Predicate<"Subtarget->hasV5TOps()">,
195 AssemblerPredicate<"HasV5TOps", "armv5t">;
196 def HasV5TE : Predicate<"Subtarget->hasV5TEOps()">,
197 AssemblerPredicate<"HasV5TEOps", "armv5te">;
198 def HasV6 : Predicate<"Subtarget->hasV6Ops()">,
199 AssemblerPredicate<"HasV6Ops", "armv6">;
200 def NoV6 : Predicate<"!Subtarget->hasV6Ops()">;
201 def HasV6M : Predicate<"Subtarget->hasV6MOps()">,
202 AssemblerPredicate<"HasV6MOps",
203 "armv6m or armv6t2">;
204 def HasV6T2 : Predicate<"Subtarget->hasV6T2Ops()">,
205 AssemblerPredicate<"HasV6T2Ops", "armv6t2">;
206 def NoV6T2 : Predicate<"!Subtarget->hasV6T2Ops()">;
207 def HasV6K : Predicate<"Subtarget->hasV6KOps()">,
208 AssemblerPredicate<"HasV6KOps", "armv6k">;
209 def NoV6K : Predicate<"!Subtarget->hasV6KOps()">;
210 def HasV7 : Predicate<"Subtarget->hasV7Ops()">,
211 AssemblerPredicate<"HasV7Ops", "armv7">;
212 def HasV8 : Predicate<"Subtarget->hasV8Ops()">,
213 AssemblerPredicate<"HasV8Ops", "armv8">;
214 def PreV8 : Predicate<"!Subtarget->hasV8Ops()">,
215 AssemblerPredicate<"!HasV8Ops", "armv7 or earlier">;
216 def HasV8_1a : Predicate<"Subtarget->hasV8_1aOps()">,
217 AssemblerPredicate<"HasV8_1aOps", "armv8.1a">;
218 def HasV8_2a : Predicate<"Subtarget->hasV8_2aOps()">,
219 AssemblerPredicate<"HasV8_2aOps", "armv8.2a">;
220 def NoVFP : Predicate<"!Subtarget->hasVFP2()">;
221 def HasVFP2 : Predicate<"Subtarget->hasVFP2()">,
222 AssemblerPredicate<"FeatureVFP2", "VFP2">;
223 def HasVFP3 : Predicate<"Subtarget->hasVFP3()">,
224 AssemblerPredicate<"FeatureVFP3", "VFP3">;
225 def HasVFP4 : Predicate<"Subtarget->hasVFP4()">,
226 AssemblerPredicate<"FeatureVFP4", "VFP4">;
227 def HasDPVFP : Predicate<"!Subtarget->isFPOnlySP()">,
228 AssemblerPredicate<"!FeatureVFPOnlySP",
229 "double precision VFP">;
230 def HasFPARMv8 : Predicate<"Subtarget->hasFPARMv8()">,
231 AssemblerPredicate<"FeatureFPARMv8", "FPARMv8">;
232 def HasNEON : Predicate<"Subtarget->hasNEON()">,
233 AssemblerPredicate<"FeatureNEON", "NEON">;
234 def HasCrypto : Predicate<"Subtarget->hasCrypto()">,
235 AssemblerPredicate<"FeatureCrypto", "crypto">;
236 def HasCRC : Predicate<"Subtarget->hasCRC()">,
237 AssemblerPredicate<"FeatureCRC", "crc">;
238 def HasFP16 : Predicate<"Subtarget->hasFP16()">,
239 AssemblerPredicate<"FeatureFP16","half-float conversions">;
240 def HasFullFP16 : Predicate<"Subtarget->hasFullFP16()">,
241 AssemblerPredicate<"FeatureFullFP16","full half-float">;
242 def HasDivide : Predicate<"Subtarget->hasDivide()">,
243 AssemblerPredicate<"FeatureHWDiv", "divide in THUMB">;
244 def HasDivideInARM : Predicate<"Subtarget->hasDivideInARMMode()">,
245 AssemblerPredicate<"FeatureHWDivARM", "divide in ARM">;
246 def HasT2ExtractPack : Predicate<"Subtarget->hasT2ExtractPack()">,
247 AssemblerPredicate<"FeatureT2XtPk",
249 def HasDSP : Predicate<"Subtarget->hasDSP()">,
250 AssemblerPredicate<"FeatureDSP", "dsp">;
251 def HasDB : Predicate<"Subtarget->hasDataBarrier()">,
252 AssemblerPredicate<"FeatureDB",
254 def HasMP : Predicate<"Subtarget->hasMPExtension()">,
255 AssemblerPredicate<"FeatureMP",
257 def HasVirtualization: Predicate<"false">,
258 AssemblerPredicate<"FeatureVirtualization",
259 "virtualization-extensions">;
260 def HasTrustZone : Predicate<"Subtarget->hasTrustZone()">,
261 AssemblerPredicate<"FeatureTrustZone",
263 def HasZCZ : Predicate<"Subtarget->hasZeroCycleZeroing()">;
264 def UseNEONForFP : Predicate<"Subtarget->useNEONForSinglePrecisionFP()">;
265 def DontUseNEONForFP : Predicate<"!Subtarget->useNEONForSinglePrecisionFP()">;
266 def IsThumb : Predicate<"Subtarget->isThumb()">,
267 AssemblerPredicate<"ModeThumb", "thumb">;
268 def IsThumb1Only : Predicate<"Subtarget->isThumb1Only()">;
269 def IsThumb2 : Predicate<"Subtarget->isThumb2()">,
270 AssemblerPredicate<"ModeThumb,FeatureThumb2",
272 def IsMClass : Predicate<"Subtarget->isMClass()">,
273 AssemblerPredicate<"FeatureMClass", "armv*m">;
274 def IsNotMClass : Predicate<"!Subtarget->isMClass()">,
275 AssemblerPredicate<"!FeatureMClass",
277 def IsARM : Predicate<"!Subtarget->isThumb()">,
278 AssemblerPredicate<"!ModeThumb", "arm-mode">;
279 def IsMachO : Predicate<"Subtarget->isTargetMachO()">;
280 def IsNotMachO : Predicate<"!Subtarget->isTargetMachO()">;
281 def IsNaCl : Predicate<"Subtarget->isTargetNaCl()">;
282 def UseNaClTrap : Predicate<"Subtarget->useNaClTrap()">,
283 AssemblerPredicate<"FeatureNaClTrap", "NaCl">;
284 def DontUseNaClTrap : Predicate<"!Subtarget->useNaClTrap()">;
286 // FIXME: Eventually this will be just "hasV6T2Ops".
287 def UseMovt : Predicate<"Subtarget->useMovt(*MF)">;
288 def DontUseMovt : Predicate<"!Subtarget->useMovt(*MF)">;
289 def UseFPVMLx : Predicate<"Subtarget->useFPVMLx()">;
290 def UseMulOps : Predicate<"Subtarget->useMulOps()">;
292 // Prefer fused MAC for fp mul + add over fp VMLA / VMLS if they are available.
293 // But only select them if more precision in FP computation is allowed.
294 // Do not use them for Darwin platforms.
295 def UseFusedMAC : Predicate<"(TM.Options.AllowFPOpFusion =="
296 " FPOpFusion::Fast && "
297 " Subtarget->hasVFP4()) && "
298 "!Subtarget->isTargetDarwin()">;
299 def DontUseFusedMAC : Predicate<"!(TM.Options.AllowFPOpFusion =="
300 " FPOpFusion::Fast &&"
301 " Subtarget->hasVFP4()) || "
302 "Subtarget->isTargetDarwin()">;
304 // VGETLNi32 is microcoded on Swift - prefer VMOV.
305 def HasFastVGETLNi32 : Predicate<"!Subtarget->isSwift()">;
306 def HasSlowVGETLNi32 : Predicate<"Subtarget->isSwift()">;
308 // VDUP.32 is microcoded on Swift - prefer VMOV.
309 def HasFastVDUP32 : Predicate<"!Subtarget->isSwift()">;
310 def HasSlowVDUP32 : Predicate<"Subtarget->isSwift()">;
312 // Cortex-A9 prefers VMOVSR to VMOVDRR even when using NEON for scalar FP, as
313 // this allows more effective execution domain optimization. See
314 // setExecutionDomain().
315 def UseVMOVSR : Predicate<"Subtarget->isCortexA9() || !Subtarget->useNEONForSinglePrecisionFP()">;
316 def DontUseVMOVSR : Predicate<"!Subtarget->isCortexA9() && Subtarget->useNEONForSinglePrecisionFP()">;
318 def IsLE : Predicate<"MF->getDataLayout().isLittleEndian()">;
319 def IsBE : Predicate<"MF->getDataLayout().isBigEndian()">;
321 //===----------------------------------------------------------------------===//
322 // ARM Flag Definitions.
324 class RegConstraint<string C> {
325 string Constraints = C;
328 //===----------------------------------------------------------------------===//
329 // ARM specific transformation functions and pattern fragments.
332 // imm_neg_XFORM - Return the negation of an i32 immediate value.
333 def imm_neg_XFORM : SDNodeXForm<imm, [{
334 return CurDAG->getTargetConstant(-(int)N->getZExtValue(), SDLoc(N), MVT::i32);
337 // imm_not_XFORM - Return the complement of a i32 immediate value.
338 def imm_not_XFORM : SDNodeXForm<imm, [{
339 return CurDAG->getTargetConstant(~(int)N->getZExtValue(), SDLoc(N), MVT::i32);
342 /// imm16_31 predicate - True if the 32-bit immediate is in the range [16,31].
343 def imm16_31 : ImmLeaf<i32, [{
344 return (int32_t)Imm >= 16 && (int32_t)Imm < 32;
347 // sext_16_node predicate - True if the SDNode is sign-extended 16 or more bits.
348 def sext_16_node : PatLeaf<(i32 GPR:$a), [{
349 return CurDAG->ComputeNumSignBits(SDValue(N,0)) >= 17;
352 /// Split a 32-bit immediate into two 16 bit parts.
353 def hi16 : SDNodeXForm<imm, [{
354 return CurDAG->getTargetConstant((uint32_t)N->getZExtValue() >> 16, SDLoc(N),
358 def lo16AllZero : PatLeaf<(i32 imm), [{
359 // Returns true if all low 16-bits are 0.
360 return (((uint32_t)N->getZExtValue()) & 0xFFFFUL) == 0;
363 class BinOpWithFlagFrag<dag res> :
364 PatFrag<(ops node:$LHS, node:$RHS, node:$FLAG), res>;
365 class BinOpFrag<dag res> : PatFrag<(ops node:$LHS, node:$RHS), res>;
366 class UnOpFrag <dag res> : PatFrag<(ops node:$Src), res>;
368 // An 'and' node with a single use.
369 def and_su : PatFrag<(ops node:$lhs, node:$rhs), (and node:$lhs, node:$rhs), [{
370 return N->hasOneUse();
373 // An 'xor' node with a single use.
374 def xor_su : PatFrag<(ops node:$lhs, node:$rhs), (xor node:$lhs, node:$rhs), [{
375 return N->hasOneUse();
378 // An 'fmul' node with a single use.
379 def fmul_su : PatFrag<(ops node:$lhs, node:$rhs), (fmul node:$lhs, node:$rhs),[{
380 return N->hasOneUse();
383 // An 'fadd' node which checks for single non-hazardous use.
384 def fadd_mlx : PatFrag<(ops node:$lhs, node:$rhs),(fadd node:$lhs, node:$rhs),[{
385 return hasNoVMLxHazardUse(N);
388 // An 'fsub' node which checks for single non-hazardous use.
389 def fsub_mlx : PatFrag<(ops node:$lhs, node:$rhs),(fsub node:$lhs, node:$rhs),[{
390 return hasNoVMLxHazardUse(N);
393 //===----------------------------------------------------------------------===//
394 // Operand Definitions.
397 // Immediate operands with a shared generic asm render method.
398 class ImmAsmOperand : AsmOperandClass { let RenderMethod = "addImmOperands"; }
400 // Operands that are part of a memory addressing mode.
401 class MemOperand : Operand<i32> { let OperandType = "OPERAND_MEMORY"; }
404 // FIXME: rename brtarget to t2_brtarget
405 def brtarget : Operand<OtherVT> {
406 let EncoderMethod = "getBranchTargetOpValue";
407 let OperandType = "OPERAND_PCREL";
408 let DecoderMethod = "DecodeT2BROperand";
411 // FIXME: get rid of this one?
412 def uncondbrtarget : Operand<OtherVT> {
413 let EncoderMethod = "getUnconditionalBranchTargetOpValue";
414 let OperandType = "OPERAND_PCREL";
417 // Branch target for ARM. Handles conditional/unconditional
418 def br_target : Operand<OtherVT> {
419 let EncoderMethod = "getARMBranchTargetOpValue";
420 let OperandType = "OPERAND_PCREL";
424 // FIXME: rename bltarget to t2_bl_target?
425 def bltarget : Operand<i32> {
426 // Encoded the same as branch targets.
427 let EncoderMethod = "getBranchTargetOpValue";
428 let OperandType = "OPERAND_PCREL";
431 // Call target for ARM. Handles conditional/unconditional
432 // FIXME: rename bl_target to t2_bltarget?
433 def bl_target : Operand<i32> {
434 let EncoderMethod = "getARMBLTargetOpValue";
435 let OperandType = "OPERAND_PCREL";
438 def blx_target : Operand<i32> {
439 let EncoderMethod = "getARMBLXTargetOpValue";
440 let OperandType = "OPERAND_PCREL";
443 // A list of registers separated by comma. Used by load/store multiple.
444 def RegListAsmOperand : AsmOperandClass { let Name = "RegList"; }
445 def reglist : Operand<i32> {
446 let EncoderMethod = "getRegisterListOpValue";
447 let ParserMatchClass = RegListAsmOperand;
448 let PrintMethod = "printRegisterList";
449 let DecoderMethod = "DecodeRegListOperand";
452 def GPRPairOp : RegisterOperand<GPRPair, "printGPRPairOperand">;
454 def DPRRegListAsmOperand : AsmOperandClass { let Name = "DPRRegList"; }
455 def dpr_reglist : Operand<i32> {
456 let EncoderMethod = "getRegisterListOpValue";
457 let ParserMatchClass = DPRRegListAsmOperand;
458 let PrintMethod = "printRegisterList";
459 let DecoderMethod = "DecodeDPRRegListOperand";
462 def SPRRegListAsmOperand : AsmOperandClass { let Name = "SPRRegList"; }
463 def spr_reglist : Operand<i32> {
464 let EncoderMethod = "getRegisterListOpValue";
465 let ParserMatchClass = SPRRegListAsmOperand;
466 let PrintMethod = "printRegisterList";
467 let DecoderMethod = "DecodeSPRRegListOperand";
470 // An operand for the CONSTPOOL_ENTRY pseudo-instruction.
471 def cpinst_operand : Operand<i32> {
472 let PrintMethod = "printCPInstOperand";
476 def pclabel : Operand<i32> {
477 let PrintMethod = "printPCLabel";
480 // ADR instruction labels.
481 def AdrLabelAsmOperand : AsmOperandClass { let Name = "AdrLabel"; }
482 def adrlabel : Operand<i32> {
483 let EncoderMethod = "getAdrLabelOpValue";
484 let ParserMatchClass = AdrLabelAsmOperand;
485 let PrintMethod = "printAdrLabelOperand<0>";
488 def neon_vcvt_imm32 : Operand<i32> {
489 let EncoderMethod = "getNEONVcvtImm32OpValue";
490 let DecoderMethod = "DecodeVCVTImmOperand";
493 // rot_imm: An integer that encodes a rotate amount. Must be 8, 16, or 24.
494 def rot_imm_XFORM: SDNodeXForm<imm, [{
495 switch (N->getZExtValue()){
496 default: llvm_unreachable(nullptr);
497 case 0: return CurDAG->getTargetConstant(0, SDLoc(N), MVT::i32);
498 case 8: return CurDAG->getTargetConstant(1, SDLoc(N), MVT::i32);
499 case 16: return CurDAG->getTargetConstant(2, SDLoc(N), MVT::i32);
500 case 24: return CurDAG->getTargetConstant(3, SDLoc(N), MVT::i32);
503 def RotImmAsmOperand : AsmOperandClass {
505 let ParserMethod = "parseRotImm";
507 def rot_imm : Operand<i32>, PatLeaf<(i32 imm), [{
508 int32_t v = N->getZExtValue();
509 return v == 8 || v == 16 || v == 24; }],
511 let PrintMethod = "printRotImmOperand";
512 let ParserMatchClass = RotImmAsmOperand;
515 // shift_imm: An integer that encodes a shift amount and the type of shift
516 // (asr or lsl). The 6-bit immediate encodes as:
519 // {4-0} imm5 shift amount.
520 // asr #32 encoded as imm5 == 0.
521 def ShifterImmAsmOperand : AsmOperandClass {
522 let Name = "ShifterImm";
523 let ParserMethod = "parseShifterImm";
525 def shift_imm : Operand<i32> {
526 let PrintMethod = "printShiftImmOperand";
527 let ParserMatchClass = ShifterImmAsmOperand;
530 // shifter_operand operands: so_reg_reg, so_reg_imm, and mod_imm.
531 def ShiftedRegAsmOperand : AsmOperandClass { let Name = "RegShiftedReg"; }
532 def so_reg_reg : Operand<i32>, // reg reg imm
533 ComplexPattern<i32, 3, "SelectRegShifterOperand",
534 [shl, srl, sra, rotr]> {
535 let EncoderMethod = "getSORegRegOpValue";
536 let PrintMethod = "printSORegRegOperand";
537 let DecoderMethod = "DecodeSORegRegOperand";
538 let ParserMatchClass = ShiftedRegAsmOperand;
539 let MIOperandInfo = (ops GPRnopc, GPRnopc, i32imm);
542 def ShiftedImmAsmOperand : AsmOperandClass { let Name = "RegShiftedImm"; }
543 def so_reg_imm : Operand<i32>, // reg imm
544 ComplexPattern<i32, 2, "SelectImmShifterOperand",
545 [shl, srl, sra, rotr]> {
546 let EncoderMethod = "getSORegImmOpValue";
547 let PrintMethod = "printSORegImmOperand";
548 let DecoderMethod = "DecodeSORegImmOperand";
549 let ParserMatchClass = ShiftedImmAsmOperand;
550 let MIOperandInfo = (ops GPR, i32imm);
553 // FIXME: Does this need to be distinct from so_reg?
554 def shift_so_reg_reg : Operand<i32>, // reg reg imm
555 ComplexPattern<i32, 3, "SelectShiftRegShifterOperand",
556 [shl,srl,sra,rotr]> {
557 let EncoderMethod = "getSORegRegOpValue";
558 let PrintMethod = "printSORegRegOperand";
559 let DecoderMethod = "DecodeSORegRegOperand";
560 let ParserMatchClass = ShiftedRegAsmOperand;
561 let MIOperandInfo = (ops GPR, GPR, i32imm);
564 // FIXME: Does this need to be distinct from so_reg?
565 def shift_so_reg_imm : Operand<i32>, // reg reg imm
566 ComplexPattern<i32, 2, "SelectShiftImmShifterOperand",
567 [shl,srl,sra,rotr]> {
568 let EncoderMethod = "getSORegImmOpValue";
569 let PrintMethod = "printSORegImmOperand";
570 let DecoderMethod = "DecodeSORegImmOperand";
571 let ParserMatchClass = ShiftedImmAsmOperand;
572 let MIOperandInfo = (ops GPR, i32imm);
575 // mod_imm: match a 32-bit immediate operand, which can be encoded into
576 // a 12-bit immediate; an 8-bit integer and a 4-bit rotator (See ARMARM
577 // - "Modified Immediate Constants"). Within the MC layer we keep this
578 // immediate in its encoded form.
579 def ModImmAsmOperand: AsmOperandClass {
581 let ParserMethod = "parseModImm";
583 def mod_imm : Operand<i32>, ImmLeaf<i32, [{
584 return ARM_AM::getSOImmVal(Imm) != -1;
586 let EncoderMethod = "getModImmOpValue";
587 let PrintMethod = "printModImmOperand";
588 let ParserMatchClass = ModImmAsmOperand;
591 // Note: the patterns mod_imm_not and mod_imm_neg do not require an encoder
592 // method and such, as they are only used on aliases (Pat<> and InstAlias<>).
593 // The actual parsing, encoding, decoding are handled by the destination
594 // instructions, which use mod_imm.
596 def ModImmNotAsmOperand : AsmOperandClass { let Name = "ModImmNot"; }
597 def mod_imm_not : Operand<i32>, PatLeaf<(imm), [{
598 return ARM_AM::getSOImmVal(~(uint32_t)N->getZExtValue()) != -1;
600 let ParserMatchClass = ModImmNotAsmOperand;
603 def ModImmNegAsmOperand : AsmOperandClass { let Name = "ModImmNeg"; }
604 def mod_imm_neg : Operand<i32>, PatLeaf<(imm), [{
605 unsigned Value = -(unsigned)N->getZExtValue();
606 return Value && ARM_AM::getSOImmVal(Value) != -1;
608 let ParserMatchClass = ModImmNegAsmOperand;
611 /// arm_i32imm - True for +V6T2, or when isSOImmTwoParVal()
612 def arm_i32imm : PatLeaf<(imm), [{
613 if (Subtarget->useMovt(*MF))
615 return ARM_AM::isSOImmTwoPartVal((unsigned)N->getZExtValue());
618 /// imm0_1 predicate - Immediate in the range [0,1].
619 def Imm0_1AsmOperand: ImmAsmOperand { let Name = "Imm0_1"; }
620 def imm0_1 : Operand<i32> { let ParserMatchClass = Imm0_1AsmOperand; }
622 /// imm0_3 predicate - Immediate in the range [0,3].
623 def Imm0_3AsmOperand: ImmAsmOperand { let Name = "Imm0_3"; }
624 def imm0_3 : Operand<i32> { let ParserMatchClass = Imm0_3AsmOperand; }
626 /// imm0_7 predicate - Immediate in the range [0,7].
627 def Imm0_7AsmOperand: ImmAsmOperand { let Name = "Imm0_7"; }
628 def imm0_7 : Operand<i32>, ImmLeaf<i32, [{
629 return Imm >= 0 && Imm < 8;
631 let ParserMatchClass = Imm0_7AsmOperand;
634 /// imm8 predicate - Immediate is exactly 8.
635 def Imm8AsmOperand: ImmAsmOperand { let Name = "Imm8"; }
636 def imm8 : Operand<i32>, ImmLeaf<i32, [{ return Imm == 8; }]> {
637 let ParserMatchClass = Imm8AsmOperand;
640 /// imm16 predicate - Immediate is exactly 16.
641 def Imm16AsmOperand: ImmAsmOperand { let Name = "Imm16"; }
642 def imm16 : Operand<i32>, ImmLeaf<i32, [{ return Imm == 16; }]> {
643 let ParserMatchClass = Imm16AsmOperand;
646 /// imm32 predicate - Immediate is exactly 32.
647 def Imm32AsmOperand: ImmAsmOperand { let Name = "Imm32"; }
648 def imm32 : Operand<i32>, ImmLeaf<i32, [{ return Imm == 32; }]> {
649 let ParserMatchClass = Imm32AsmOperand;
652 def imm8_or_16 : ImmLeaf<i32, [{ return Imm == 8 || Imm == 16;}]>;
654 /// imm1_7 predicate - Immediate in the range [1,7].
655 def Imm1_7AsmOperand: ImmAsmOperand { let Name = "Imm1_7"; }
656 def imm1_7 : Operand<i32>, ImmLeaf<i32, [{ return Imm > 0 && Imm < 8; }]> {
657 let ParserMatchClass = Imm1_7AsmOperand;
660 /// imm1_15 predicate - Immediate in the range [1,15].
661 def Imm1_15AsmOperand: ImmAsmOperand { let Name = "Imm1_15"; }
662 def imm1_15 : Operand<i32>, ImmLeaf<i32, [{ return Imm > 0 && Imm < 16; }]> {
663 let ParserMatchClass = Imm1_15AsmOperand;
666 /// imm1_31 predicate - Immediate in the range [1,31].
667 def Imm1_31AsmOperand: ImmAsmOperand { let Name = "Imm1_31"; }
668 def imm1_31 : Operand<i32>, ImmLeaf<i32, [{ return Imm > 0 && Imm < 32; }]> {
669 let ParserMatchClass = Imm1_31AsmOperand;
672 /// imm0_15 predicate - Immediate in the range [0,15].
673 def Imm0_15AsmOperand: ImmAsmOperand {
674 let Name = "Imm0_15";
675 let DiagnosticType = "ImmRange0_15";
677 def imm0_15 : Operand<i32>, ImmLeaf<i32, [{
678 return Imm >= 0 && Imm < 16;
680 let ParserMatchClass = Imm0_15AsmOperand;
683 /// imm0_31 predicate - True if the 32-bit immediate is in the range [0,31].
684 def Imm0_31AsmOperand: ImmAsmOperand { let Name = "Imm0_31"; }
685 def imm0_31 : Operand<i32>, ImmLeaf<i32, [{
686 return Imm >= 0 && Imm < 32;
688 let ParserMatchClass = Imm0_31AsmOperand;
691 /// imm0_32 predicate - True if the 32-bit immediate is in the range [0,32].
692 def Imm0_32AsmOperand: ImmAsmOperand { let Name = "Imm0_32"; }
693 def imm0_32 : Operand<i32>, ImmLeaf<i32, [{
694 return Imm >= 0 && Imm < 32;
696 let ParserMatchClass = Imm0_32AsmOperand;
699 /// imm0_63 predicate - True if the 32-bit immediate is in the range [0,63].
700 def Imm0_63AsmOperand: ImmAsmOperand { let Name = "Imm0_63"; }
701 def imm0_63 : Operand<i32>, ImmLeaf<i32, [{
702 return Imm >= 0 && Imm < 64;
704 let ParserMatchClass = Imm0_63AsmOperand;
707 /// imm0_239 predicate - Immediate in the range [0,239].
708 def Imm0_239AsmOperand : ImmAsmOperand {
709 let Name = "Imm0_239";
710 let DiagnosticType = "ImmRange0_239";
712 def imm0_239 : Operand<i32>, ImmLeaf<i32, [{ return Imm >= 0 && Imm < 240; }]> {
713 let ParserMatchClass = Imm0_239AsmOperand;
716 /// imm0_255 predicate - Immediate in the range [0,255].
717 def Imm0_255AsmOperand : ImmAsmOperand { let Name = "Imm0_255"; }
718 def imm0_255 : Operand<i32>, ImmLeaf<i32, [{ return Imm >= 0 && Imm < 256; }]> {
719 let ParserMatchClass = Imm0_255AsmOperand;
722 /// imm0_65535 - An immediate is in the range [0.65535].
723 def Imm0_65535AsmOperand: ImmAsmOperand { let Name = "Imm0_65535"; }
724 def imm0_65535 : Operand<i32>, ImmLeaf<i32, [{
725 return Imm >= 0 && Imm < 65536;
727 let ParserMatchClass = Imm0_65535AsmOperand;
730 // imm0_65535_neg - An immediate whose negative value is in the range [0.65535].
731 def imm0_65535_neg : Operand<i32>, ImmLeaf<i32, [{
732 return -Imm >= 0 && -Imm < 65536;
735 // imm0_65535_expr - For movt/movw - 16-bit immediate that can also reference
736 // a relocatable expression.
738 // FIXME: This really needs a Thumb version separate from the ARM version.
739 // While the range is the same, and can thus use the same match class,
740 // the encoding is different so it should have a different encoder method.
741 def Imm0_65535ExprAsmOperand: ImmAsmOperand { let Name = "Imm0_65535Expr"; }
742 def imm0_65535_expr : Operand<i32> {
743 let EncoderMethod = "getHiLo16ImmOpValue";
744 let ParserMatchClass = Imm0_65535ExprAsmOperand;
747 def Imm256_65535ExprAsmOperand: ImmAsmOperand { let Name = "Imm256_65535Expr"; }
748 def imm256_65535_expr : Operand<i32> {
749 let ParserMatchClass = Imm256_65535ExprAsmOperand;
752 /// imm24b - True if the 32-bit immediate is encodable in 24 bits.
753 def Imm24bitAsmOperand: ImmAsmOperand { let Name = "Imm24bit"; }
754 def imm24b : Operand<i32>, ImmLeaf<i32, [{
755 return Imm >= 0 && Imm <= 0xffffff;
757 let ParserMatchClass = Imm24bitAsmOperand;
761 /// bf_inv_mask_imm predicate - An AND mask to clear an arbitrary width bitfield
763 def BitfieldAsmOperand : AsmOperandClass {
764 let Name = "Bitfield";
765 let ParserMethod = "parseBitfield";
768 def bf_inv_mask_imm : Operand<i32>,
770 return ARM::isBitFieldInvertedMask(N->getZExtValue());
772 let EncoderMethod = "getBitfieldInvertedMaskOpValue";
773 let PrintMethod = "printBitfieldInvMaskImmOperand";
774 let DecoderMethod = "DecodeBitfieldMaskOperand";
775 let ParserMatchClass = BitfieldAsmOperand;
778 def imm1_32_XFORM: SDNodeXForm<imm, [{
779 return CurDAG->getTargetConstant((int)N->getZExtValue() - 1, SDLoc(N),
782 def Imm1_32AsmOperand: AsmOperandClass { let Name = "Imm1_32"; }
783 def imm1_32 : Operand<i32>, PatLeaf<(imm), [{
784 uint64_t Imm = N->getZExtValue();
785 return Imm > 0 && Imm <= 32;
788 let PrintMethod = "printImmPlusOneOperand";
789 let ParserMatchClass = Imm1_32AsmOperand;
792 def imm1_16_XFORM: SDNodeXForm<imm, [{
793 return CurDAG->getTargetConstant((int)N->getZExtValue() - 1, SDLoc(N),
796 def Imm1_16AsmOperand: AsmOperandClass { let Name = "Imm1_16"; }
797 def imm1_16 : Operand<i32>, PatLeaf<(imm), [{ return Imm > 0 && Imm <= 16; }],
799 let PrintMethod = "printImmPlusOneOperand";
800 let ParserMatchClass = Imm1_16AsmOperand;
803 // Define ARM specific addressing modes.
804 // addrmode_imm12 := reg +/- imm12
806 def MemImm12OffsetAsmOperand : AsmOperandClass { let Name = "MemImm12Offset"; }
807 class AddrMode_Imm12 : MemOperand,
808 ComplexPattern<i32, 2, "SelectAddrModeImm12", []> {
809 // 12-bit immediate operand. Note that instructions using this encode
810 // #0 and #-0 differently. We flag #-0 as the magic value INT32_MIN. All other
811 // immediate values are as normal.
813 let EncoderMethod = "getAddrModeImm12OpValue";
814 let DecoderMethod = "DecodeAddrModeImm12Operand";
815 let ParserMatchClass = MemImm12OffsetAsmOperand;
816 let MIOperandInfo = (ops GPR:$base, i32imm:$offsimm);
819 def addrmode_imm12 : AddrMode_Imm12 {
820 let PrintMethod = "printAddrModeImm12Operand<false>";
823 def addrmode_imm12_pre : AddrMode_Imm12 {
824 let PrintMethod = "printAddrModeImm12Operand<true>";
827 // ldst_so_reg := reg +/- reg shop imm
829 def MemRegOffsetAsmOperand : AsmOperandClass { let Name = "MemRegOffset"; }
830 def ldst_so_reg : MemOperand,
831 ComplexPattern<i32, 3, "SelectLdStSOReg", []> {
832 let EncoderMethod = "getLdStSORegOpValue";
833 // FIXME: Simplify the printer
834 let PrintMethod = "printAddrMode2Operand";
835 let DecoderMethod = "DecodeSORegMemOperand";
836 let ParserMatchClass = MemRegOffsetAsmOperand;
837 let MIOperandInfo = (ops GPR:$base, GPRnopc:$offsreg, i32imm:$shift);
840 // postidx_imm8 := +/- [0,255]
843 // {8} 1 is imm8 is non-negative. 0 otherwise.
844 // {7-0} [0,255] imm8 value.
845 def PostIdxImm8AsmOperand : AsmOperandClass { let Name = "PostIdxImm8"; }
846 def postidx_imm8 : MemOperand {
847 let PrintMethod = "printPostIdxImm8Operand";
848 let ParserMatchClass = PostIdxImm8AsmOperand;
849 let MIOperandInfo = (ops i32imm);
852 // postidx_imm8s4 := +/- [0,1020]
855 // {8} 1 is imm8 is non-negative. 0 otherwise.
856 // {7-0} [0,255] imm8 value, scaled by 4.
857 def PostIdxImm8s4AsmOperand : AsmOperandClass { let Name = "PostIdxImm8s4"; }
858 def postidx_imm8s4 : MemOperand {
859 let PrintMethod = "printPostIdxImm8s4Operand";
860 let ParserMatchClass = PostIdxImm8s4AsmOperand;
861 let MIOperandInfo = (ops i32imm);
865 // postidx_reg := +/- reg
867 def PostIdxRegAsmOperand : AsmOperandClass {
868 let Name = "PostIdxReg";
869 let ParserMethod = "parsePostIdxReg";
871 def postidx_reg : MemOperand {
872 let EncoderMethod = "getPostIdxRegOpValue";
873 let DecoderMethod = "DecodePostIdxReg";
874 let PrintMethod = "printPostIdxRegOperand";
875 let ParserMatchClass = PostIdxRegAsmOperand;
876 let MIOperandInfo = (ops GPRnopc, i32imm);
880 // addrmode2 := reg +/- imm12
881 // := reg +/- reg shop imm
883 // FIXME: addrmode2 should be refactored the rest of the way to always
884 // use explicit imm vs. reg versions above (addrmode_imm12 and ldst_so_reg).
885 def AddrMode2AsmOperand : AsmOperandClass { let Name = "AddrMode2"; }
886 def addrmode2 : MemOperand,
887 ComplexPattern<i32, 3, "SelectAddrMode2", []> {
888 let EncoderMethod = "getAddrMode2OpValue";
889 let PrintMethod = "printAddrMode2Operand";
890 let ParserMatchClass = AddrMode2AsmOperand;
891 let MIOperandInfo = (ops GPR:$base, GPR:$offsreg, i32imm:$offsimm);
894 def PostIdxRegShiftedAsmOperand : AsmOperandClass {
895 let Name = "PostIdxRegShifted";
896 let ParserMethod = "parsePostIdxReg";
898 def am2offset_reg : MemOperand,
899 ComplexPattern<i32, 2, "SelectAddrMode2OffsetReg",
900 [], [SDNPWantRoot]> {
901 let EncoderMethod = "getAddrMode2OffsetOpValue";
902 let PrintMethod = "printAddrMode2OffsetOperand";
903 // When using this for assembly, it's always as a post-index offset.
904 let ParserMatchClass = PostIdxRegShiftedAsmOperand;
905 let MIOperandInfo = (ops GPRnopc, i32imm);
908 // FIXME: am2offset_imm should only need the immediate, not the GPR. Having
909 // the GPR is purely vestigal at this point.
910 def AM2OffsetImmAsmOperand : AsmOperandClass { let Name = "AM2OffsetImm"; }
911 def am2offset_imm : MemOperand,
912 ComplexPattern<i32, 2, "SelectAddrMode2OffsetImm",
913 [], [SDNPWantRoot]> {
914 let EncoderMethod = "getAddrMode2OffsetOpValue";
915 let PrintMethod = "printAddrMode2OffsetOperand";
916 let ParserMatchClass = AM2OffsetImmAsmOperand;
917 let MIOperandInfo = (ops GPRnopc, i32imm);
921 // addrmode3 := reg +/- reg
922 // addrmode3 := reg +/- imm8
924 // FIXME: split into imm vs. reg versions.
925 def AddrMode3AsmOperand : AsmOperandClass { let Name = "AddrMode3"; }
926 class AddrMode3 : MemOperand,
927 ComplexPattern<i32, 3, "SelectAddrMode3", []> {
928 let EncoderMethod = "getAddrMode3OpValue";
929 let ParserMatchClass = AddrMode3AsmOperand;
930 let MIOperandInfo = (ops GPR:$base, GPR:$offsreg, i32imm:$offsimm);
933 def addrmode3 : AddrMode3
935 let PrintMethod = "printAddrMode3Operand<false>";
938 def addrmode3_pre : AddrMode3
940 let PrintMethod = "printAddrMode3Operand<true>";
943 // FIXME: split into imm vs. reg versions.
944 // FIXME: parser method to handle +/- register.
945 def AM3OffsetAsmOperand : AsmOperandClass {
946 let Name = "AM3Offset";
947 let ParserMethod = "parseAM3Offset";
949 def am3offset : MemOperand,
950 ComplexPattern<i32, 2, "SelectAddrMode3Offset",
951 [], [SDNPWantRoot]> {
952 let EncoderMethod = "getAddrMode3OffsetOpValue";
953 let PrintMethod = "printAddrMode3OffsetOperand";
954 let ParserMatchClass = AM3OffsetAsmOperand;
955 let MIOperandInfo = (ops GPR, i32imm);
958 // ldstm_mode := {ia, ib, da, db}
960 def ldstm_mode : OptionalDefOperand<OtherVT, (ops i32), (ops (i32 1))> {
961 let EncoderMethod = "getLdStmModeOpValue";
962 let PrintMethod = "printLdStmModeOperand";
965 // addrmode5 := reg +/- imm8*4
967 def AddrMode5AsmOperand : AsmOperandClass { let Name = "AddrMode5"; }
968 class AddrMode5 : MemOperand,
969 ComplexPattern<i32, 2, "SelectAddrMode5", []> {
970 let EncoderMethod = "getAddrMode5OpValue";
971 let DecoderMethod = "DecodeAddrMode5Operand";
972 let ParserMatchClass = AddrMode5AsmOperand;
973 let MIOperandInfo = (ops GPR:$base, i32imm);
976 def addrmode5 : AddrMode5 {
977 let PrintMethod = "printAddrMode5Operand<false>";
980 def addrmode5_pre : AddrMode5 {
981 let PrintMethod = "printAddrMode5Operand<true>";
984 // addrmode6 := reg with optional alignment
986 def AddrMode6AsmOperand : AsmOperandClass { let Name = "AlignedMemory"; }
987 def addrmode6 : MemOperand,
988 ComplexPattern<i32, 2, "SelectAddrMode6", [], [SDNPWantParent]>{
989 let PrintMethod = "printAddrMode6Operand";
990 let MIOperandInfo = (ops GPR:$addr, i32imm:$align);
991 let EncoderMethod = "getAddrMode6AddressOpValue";
992 let DecoderMethod = "DecodeAddrMode6Operand";
993 let ParserMatchClass = AddrMode6AsmOperand;
996 def am6offset : MemOperand,
997 ComplexPattern<i32, 1, "SelectAddrMode6Offset",
998 [], [SDNPWantRoot]> {
999 let PrintMethod = "printAddrMode6OffsetOperand";
1000 let MIOperandInfo = (ops GPR);
1001 let EncoderMethod = "getAddrMode6OffsetOpValue";
1002 let DecoderMethod = "DecodeGPRRegisterClass";
1005 // Special version of addrmode6 to handle alignment encoding for VST1/VLD1
1006 // (single element from one lane) for size 32.
1007 def addrmode6oneL32 : MemOperand,
1008 ComplexPattern<i32, 2, "SelectAddrMode6", [], [SDNPWantParent]>{
1009 let PrintMethod = "printAddrMode6Operand";
1010 let MIOperandInfo = (ops GPR:$addr, i32imm);
1011 let EncoderMethod = "getAddrMode6OneLane32AddressOpValue";
1014 // Base class for addrmode6 with specific alignment restrictions.
1015 class AddrMode6Align : MemOperand,
1016 ComplexPattern<i32, 2, "SelectAddrMode6", [], [SDNPWantParent]>{
1017 let PrintMethod = "printAddrMode6Operand";
1018 let MIOperandInfo = (ops GPR:$addr, i32imm:$align);
1019 let EncoderMethod = "getAddrMode6AddressOpValue";
1020 let DecoderMethod = "DecodeAddrMode6Operand";
1023 // Special version of addrmode6 to handle no allowed alignment encoding for
1024 // VLD/VST instructions and checking the alignment is not specified.
1025 def AddrMode6AlignNoneAsmOperand : AsmOperandClass {
1026 let Name = "AlignedMemoryNone";
1027 let DiagnosticType = "AlignedMemoryRequiresNone";
1029 def addrmode6alignNone : AddrMode6Align {
1030 // The alignment specifier can only be omitted.
1031 let ParserMatchClass = AddrMode6AlignNoneAsmOperand;
1034 // Special version of addrmode6 to handle 16-bit alignment encoding for
1035 // VLD/VST instructions and checking the alignment value.
1036 def AddrMode6Align16AsmOperand : AsmOperandClass {
1037 let Name = "AlignedMemory16";
1038 let DiagnosticType = "AlignedMemoryRequires16";
1040 def addrmode6align16 : AddrMode6Align {
1041 // The alignment specifier can only be 16 or omitted.
1042 let ParserMatchClass = AddrMode6Align16AsmOperand;
1045 // Special version of addrmode6 to handle 32-bit alignment encoding for
1046 // VLD/VST instructions and checking the alignment value.
1047 def AddrMode6Align32AsmOperand : AsmOperandClass {
1048 let Name = "AlignedMemory32";
1049 let DiagnosticType = "AlignedMemoryRequires32";
1051 def addrmode6align32 : AddrMode6Align {
1052 // The alignment specifier can only be 32 or omitted.
1053 let ParserMatchClass = AddrMode6Align32AsmOperand;
1056 // Special version of addrmode6 to handle 64-bit alignment encoding for
1057 // VLD/VST instructions and checking the alignment value.
1058 def AddrMode6Align64AsmOperand : AsmOperandClass {
1059 let Name = "AlignedMemory64";
1060 let DiagnosticType = "AlignedMemoryRequires64";
1062 def addrmode6align64 : AddrMode6Align {
1063 // The alignment specifier can only be 64 or omitted.
1064 let ParserMatchClass = AddrMode6Align64AsmOperand;
1067 // Special version of addrmode6 to handle 64-bit or 128-bit alignment encoding
1068 // for VLD/VST instructions and checking the alignment value.
1069 def AddrMode6Align64or128AsmOperand : AsmOperandClass {
1070 let Name = "AlignedMemory64or128";
1071 let DiagnosticType = "AlignedMemoryRequires64or128";
1073 def addrmode6align64or128 : AddrMode6Align {
1074 // The alignment specifier can only be 64, 128 or omitted.
1075 let ParserMatchClass = AddrMode6Align64or128AsmOperand;
1078 // Special version of addrmode6 to handle 64-bit, 128-bit or 256-bit alignment
1079 // encoding for VLD/VST instructions and checking the alignment value.
1080 def AddrMode6Align64or128or256AsmOperand : AsmOperandClass {
1081 let Name = "AlignedMemory64or128or256";
1082 let DiagnosticType = "AlignedMemoryRequires64or128or256";
1084 def addrmode6align64or128or256 : AddrMode6Align {
1085 // The alignment specifier can only be 64, 128, 256 or omitted.
1086 let ParserMatchClass = AddrMode6Align64or128or256AsmOperand;
1089 // Special version of addrmode6 to handle alignment encoding for VLD-dup
1090 // instructions, specifically VLD4-dup.
1091 def addrmode6dup : MemOperand,
1092 ComplexPattern<i32, 2, "SelectAddrMode6", [], [SDNPWantParent]>{
1093 let PrintMethod = "printAddrMode6Operand";
1094 let MIOperandInfo = (ops GPR:$addr, i32imm);
1095 let EncoderMethod = "getAddrMode6DupAddressOpValue";
1096 // FIXME: This is close, but not quite right. The alignment specifier is
1098 let ParserMatchClass = AddrMode6AsmOperand;
1101 // Base class for addrmode6dup with specific alignment restrictions.
1102 class AddrMode6DupAlign : MemOperand,
1103 ComplexPattern<i32, 2, "SelectAddrMode6", [], [SDNPWantParent]>{
1104 let PrintMethod = "printAddrMode6Operand";
1105 let MIOperandInfo = (ops GPR:$addr, i32imm);
1106 let EncoderMethod = "getAddrMode6DupAddressOpValue";
1109 // Special version of addrmode6 to handle no allowed alignment encoding for
1110 // VLD-dup instruction and checking the alignment is not specified.
1111 def AddrMode6dupAlignNoneAsmOperand : AsmOperandClass {
1112 let Name = "DupAlignedMemoryNone";
1113 let DiagnosticType = "DupAlignedMemoryRequiresNone";
1115 def addrmode6dupalignNone : AddrMode6DupAlign {
1116 // The alignment specifier can only be omitted.
1117 let ParserMatchClass = AddrMode6dupAlignNoneAsmOperand;
1120 // Special version of addrmode6 to handle 16-bit alignment encoding for VLD-dup
1121 // instruction and checking the alignment value.
1122 def AddrMode6dupAlign16AsmOperand : AsmOperandClass {
1123 let Name = "DupAlignedMemory16";
1124 let DiagnosticType = "DupAlignedMemoryRequires16";
1126 def addrmode6dupalign16 : AddrMode6DupAlign {
1127 // The alignment specifier can only be 16 or omitted.
1128 let ParserMatchClass = AddrMode6dupAlign16AsmOperand;
1131 // Special version of addrmode6 to handle 32-bit alignment encoding for VLD-dup
1132 // instruction and checking the alignment value.
1133 def AddrMode6dupAlign32AsmOperand : AsmOperandClass {
1134 let Name = "DupAlignedMemory32";
1135 let DiagnosticType = "DupAlignedMemoryRequires32";
1137 def addrmode6dupalign32 : AddrMode6DupAlign {
1138 // The alignment specifier can only be 32 or omitted.
1139 let ParserMatchClass = AddrMode6dupAlign32AsmOperand;
1142 // Special version of addrmode6 to handle 64-bit alignment encoding for VLD
1143 // instructions and checking the alignment value.
1144 def AddrMode6dupAlign64AsmOperand : AsmOperandClass {
1145 let Name = "DupAlignedMemory64";
1146 let DiagnosticType = "DupAlignedMemoryRequires64";
1148 def addrmode6dupalign64 : AddrMode6DupAlign {
1149 // The alignment specifier can only be 64 or omitted.
1150 let ParserMatchClass = AddrMode6dupAlign64AsmOperand;
1153 // Special version of addrmode6 to handle 64-bit or 128-bit alignment encoding
1154 // for VLD instructions and checking the alignment value.
1155 def AddrMode6dupAlign64or128AsmOperand : AsmOperandClass {
1156 let Name = "DupAlignedMemory64or128";
1157 let DiagnosticType = "DupAlignedMemoryRequires64or128";
1159 def addrmode6dupalign64or128 : AddrMode6DupAlign {
1160 // The alignment specifier can only be 64, 128 or omitted.
1161 let ParserMatchClass = AddrMode6dupAlign64or128AsmOperand;
1164 // addrmodepc := pc + reg
1166 def addrmodepc : MemOperand,
1167 ComplexPattern<i32, 2, "SelectAddrModePC", []> {
1168 let PrintMethod = "printAddrModePCOperand";
1169 let MIOperandInfo = (ops GPR, i32imm);
1172 // addr_offset_none := reg
1174 def MemNoOffsetAsmOperand : AsmOperandClass { let Name = "MemNoOffset"; }
1175 def addr_offset_none : MemOperand,
1176 ComplexPattern<i32, 1, "SelectAddrOffsetNone", []> {
1177 let PrintMethod = "printAddrMode7Operand";
1178 let DecoderMethod = "DecodeAddrMode7Operand";
1179 let ParserMatchClass = MemNoOffsetAsmOperand;
1180 let MIOperandInfo = (ops GPR:$base);
1183 def nohash_imm : Operand<i32> {
1184 let PrintMethod = "printNoHashImmediate";
1187 def CoprocNumAsmOperand : AsmOperandClass {
1188 let Name = "CoprocNum";
1189 let ParserMethod = "parseCoprocNumOperand";
1191 def p_imm : Operand<i32> {
1192 let PrintMethod = "printPImmediate";
1193 let ParserMatchClass = CoprocNumAsmOperand;
1194 let DecoderMethod = "DecodeCoprocessor";
1197 def CoprocRegAsmOperand : AsmOperandClass {
1198 let Name = "CoprocReg";
1199 let ParserMethod = "parseCoprocRegOperand";
1201 def c_imm : Operand<i32> {
1202 let PrintMethod = "printCImmediate";
1203 let ParserMatchClass = CoprocRegAsmOperand;
1205 def CoprocOptionAsmOperand : AsmOperandClass {
1206 let Name = "CoprocOption";
1207 let ParserMethod = "parseCoprocOptionOperand";
1209 def coproc_option_imm : Operand<i32> {
1210 let PrintMethod = "printCoprocOptionImm";
1211 let ParserMatchClass = CoprocOptionAsmOperand;
1214 //===----------------------------------------------------------------------===//
1216 include "ARMInstrFormats.td"
1218 //===----------------------------------------------------------------------===//
1219 // Multiclass helpers...
1222 /// AsI1_bin_irs - Defines a set of (op r, {mod_imm|r|so_reg}) patterns for a
1223 /// binop that produces a value.
1224 let TwoOperandAliasConstraint = "$Rn = $Rd" in
1225 multiclass AsI1_bin_irs<bits<4> opcod, string opc,
1226 InstrItinClass iii, InstrItinClass iir, InstrItinClass iis,
1227 PatFrag opnode, bit Commutable = 0> {
1228 // The register-immediate version is re-materializable. This is useful
1229 // in particular for taking the address of a local.
1230 let isReMaterializable = 1 in {
1231 def ri : AsI1<opcod, (outs GPR:$Rd), (ins GPR:$Rn, mod_imm:$imm), DPFrm,
1232 iii, opc, "\t$Rd, $Rn, $imm",
1233 [(set GPR:$Rd, (opnode GPR:$Rn, mod_imm:$imm))]>,
1234 Sched<[WriteALU, ReadALU]> {
1239 let Inst{19-16} = Rn;
1240 let Inst{15-12} = Rd;
1241 let Inst{11-0} = imm;
1244 def rr : AsI1<opcod, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm), DPFrm,
1245 iir, opc, "\t$Rd, $Rn, $Rm",
1246 [(set GPR:$Rd, (opnode GPR:$Rn, GPR:$Rm))]>,
1247 Sched<[WriteALU, ReadALU, ReadALU]> {
1252 let isCommutable = Commutable;
1253 let Inst{19-16} = Rn;
1254 let Inst{15-12} = Rd;
1255 let Inst{11-4} = 0b00000000;
1259 def rsi : AsI1<opcod, (outs GPR:$Rd),
1260 (ins GPR:$Rn, so_reg_imm:$shift), DPSoRegImmFrm,
1261 iis, opc, "\t$Rd, $Rn, $shift",
1262 [(set GPR:$Rd, (opnode GPR:$Rn, so_reg_imm:$shift))]>,
1263 Sched<[WriteALUsi, ReadALU]> {
1268 let Inst{19-16} = Rn;
1269 let Inst{15-12} = Rd;
1270 let Inst{11-5} = shift{11-5};
1272 let Inst{3-0} = shift{3-0};
1275 def rsr : AsI1<opcod, (outs GPR:$Rd),
1276 (ins GPR:$Rn, so_reg_reg:$shift), DPSoRegRegFrm,
1277 iis, opc, "\t$Rd, $Rn, $shift",
1278 [(set GPR:$Rd, (opnode GPR:$Rn, so_reg_reg:$shift))]>,
1279 Sched<[WriteALUsr, ReadALUsr]> {
1284 let Inst{19-16} = Rn;
1285 let Inst{15-12} = Rd;
1286 let Inst{11-8} = shift{11-8};
1288 let Inst{6-5} = shift{6-5};
1290 let Inst{3-0} = shift{3-0};
1294 /// AsI1_rbin_irs - Same as AsI1_bin_irs except the order of operands are
1295 /// reversed. The 'rr' form is only defined for the disassembler; for codegen
1296 /// it is equivalent to the AsI1_bin_irs counterpart.
1297 let TwoOperandAliasConstraint = "$Rn = $Rd" in
1298 multiclass AsI1_rbin_irs<bits<4> opcod, string opc,
1299 InstrItinClass iii, InstrItinClass iir, InstrItinClass iis,
1300 PatFrag opnode, bit Commutable = 0> {
1301 // The register-immediate version is re-materializable. This is useful
1302 // in particular for taking the address of a local.
1303 let isReMaterializable = 1 in {
1304 def ri : AsI1<opcod, (outs GPR:$Rd), (ins GPR:$Rn, mod_imm:$imm), DPFrm,
1305 iii, opc, "\t$Rd, $Rn, $imm",
1306 [(set GPR:$Rd, (opnode mod_imm:$imm, GPR:$Rn))]>,
1307 Sched<[WriteALU, ReadALU]> {
1312 let Inst{19-16} = Rn;
1313 let Inst{15-12} = Rd;
1314 let Inst{11-0} = imm;
1317 def rr : AsI1<opcod, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm), DPFrm,
1318 iir, opc, "\t$Rd, $Rn, $Rm",
1319 [/* pattern left blank */]>,
1320 Sched<[WriteALU, ReadALU, ReadALU]> {
1324 let Inst{11-4} = 0b00000000;
1327 let Inst{15-12} = Rd;
1328 let Inst{19-16} = Rn;
1331 def rsi : AsI1<opcod, (outs GPR:$Rd),
1332 (ins GPR:$Rn, so_reg_imm:$shift), DPSoRegImmFrm,
1333 iis, opc, "\t$Rd, $Rn, $shift",
1334 [(set GPR:$Rd, (opnode so_reg_imm:$shift, GPR:$Rn))]>,
1335 Sched<[WriteALUsi, ReadALU]> {
1340 let Inst{19-16} = Rn;
1341 let Inst{15-12} = Rd;
1342 let Inst{11-5} = shift{11-5};
1344 let Inst{3-0} = shift{3-0};
1347 def rsr : AsI1<opcod, (outs GPR:$Rd),
1348 (ins GPR:$Rn, so_reg_reg:$shift), DPSoRegRegFrm,
1349 iis, opc, "\t$Rd, $Rn, $shift",
1350 [(set GPR:$Rd, (opnode so_reg_reg:$shift, GPR:$Rn))]>,
1351 Sched<[WriteALUsr, ReadALUsr]> {
1356 let Inst{19-16} = Rn;
1357 let Inst{15-12} = Rd;
1358 let Inst{11-8} = shift{11-8};
1360 let Inst{6-5} = shift{6-5};
1362 let Inst{3-0} = shift{3-0};
1366 /// AsI1_bin_s_irs - Same as AsI1_bin_irs except it sets the 's' bit by default.
1368 /// These opcodes will be converted to the real non-S opcodes by
1369 /// AdjustInstrPostInstrSelection after giving them an optional CPSR operand.
1370 let hasPostISelHook = 1, Defs = [CPSR] in {
1371 multiclass AsI1_bin_s_irs<InstrItinClass iii, InstrItinClass iir,
1372 InstrItinClass iis, PatFrag opnode,
1373 bit Commutable = 0> {
1374 def ri : ARMPseudoInst<(outs GPR:$Rd), (ins GPR:$Rn, mod_imm:$imm, pred:$p),
1376 [(set GPR:$Rd, CPSR, (opnode GPR:$Rn, mod_imm:$imm))]>,
1377 Sched<[WriteALU, ReadALU]>;
1379 def rr : ARMPseudoInst<(outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm, pred:$p),
1381 [(set GPR:$Rd, CPSR, (opnode GPR:$Rn, GPR:$Rm))]>,
1382 Sched<[WriteALU, ReadALU, ReadALU]> {
1383 let isCommutable = Commutable;
1385 def rsi : ARMPseudoInst<(outs GPR:$Rd),
1386 (ins GPR:$Rn, so_reg_imm:$shift, pred:$p),
1388 [(set GPR:$Rd, CPSR, (opnode GPR:$Rn,
1389 so_reg_imm:$shift))]>,
1390 Sched<[WriteALUsi, ReadALU]>;
1392 def rsr : ARMPseudoInst<(outs GPR:$Rd),
1393 (ins GPR:$Rn, so_reg_reg:$shift, pred:$p),
1395 [(set GPR:$Rd, CPSR, (opnode GPR:$Rn,
1396 so_reg_reg:$shift))]>,
1397 Sched<[WriteALUSsr, ReadALUsr]>;
1401 /// AsI1_rbin_s_is - Same as AsI1_bin_s_irs, except selection DAG
1402 /// operands are reversed.
1403 let hasPostISelHook = 1, Defs = [CPSR] in {
1404 multiclass AsI1_rbin_s_is<InstrItinClass iii, InstrItinClass iir,
1405 InstrItinClass iis, PatFrag opnode,
1406 bit Commutable = 0> {
1407 def ri : ARMPseudoInst<(outs GPR:$Rd), (ins GPR:$Rn, mod_imm:$imm, pred:$p),
1409 [(set GPR:$Rd, CPSR, (opnode mod_imm:$imm, GPR:$Rn))]>,
1410 Sched<[WriteALU, ReadALU]>;
1412 def rsi : ARMPseudoInst<(outs GPR:$Rd),
1413 (ins GPR:$Rn, so_reg_imm:$shift, pred:$p),
1415 [(set GPR:$Rd, CPSR, (opnode so_reg_imm:$shift,
1417 Sched<[WriteALUsi, ReadALU]>;
1419 def rsr : ARMPseudoInst<(outs GPR:$Rd),
1420 (ins GPR:$Rn, so_reg_reg:$shift, pred:$p),
1422 [(set GPR:$Rd, CPSR, (opnode so_reg_reg:$shift,
1424 Sched<[WriteALUSsr, ReadALUsr]>;
1428 /// AI1_cmp_irs - Defines a set of (op r, {mod_imm|r|so_reg}) cmp / test
1429 /// patterns. Similar to AsI1_bin_irs except the instruction does not produce
1430 /// a explicit result, only implicitly set CPSR.
1431 let isCompare = 1, Defs = [CPSR] in {
1432 multiclass AI1_cmp_irs<bits<4> opcod, string opc,
1433 InstrItinClass iii, InstrItinClass iir, InstrItinClass iis,
1434 PatFrag opnode, bit Commutable = 0,
1435 string rrDecoderMethod = ""> {
1436 def ri : AI1<opcod, (outs), (ins GPR:$Rn, mod_imm:$imm), DPFrm, iii,
1438 [(opnode GPR:$Rn, mod_imm:$imm)]>,
1439 Sched<[WriteCMP, ReadALU]> {
1444 let Inst{19-16} = Rn;
1445 let Inst{15-12} = 0b0000;
1446 let Inst{11-0} = imm;
1448 let Unpredictable{15-12} = 0b1111;
1450 def rr : AI1<opcod, (outs), (ins GPR:$Rn, GPR:$Rm), DPFrm, iir,
1452 [(opnode GPR:$Rn, GPR:$Rm)]>,
1453 Sched<[WriteCMP, ReadALU, ReadALU]> {
1456 let isCommutable = Commutable;
1459 let Inst{19-16} = Rn;
1460 let Inst{15-12} = 0b0000;
1461 let Inst{11-4} = 0b00000000;
1463 let DecoderMethod = rrDecoderMethod;
1465 let Unpredictable{15-12} = 0b1111;
1467 def rsi : AI1<opcod, (outs),
1468 (ins GPR:$Rn, so_reg_imm:$shift), DPSoRegImmFrm, iis,
1469 opc, "\t$Rn, $shift",
1470 [(opnode GPR:$Rn, so_reg_imm:$shift)]>,
1471 Sched<[WriteCMPsi, ReadALU]> {
1476 let Inst{19-16} = Rn;
1477 let Inst{15-12} = 0b0000;
1478 let Inst{11-5} = shift{11-5};
1480 let Inst{3-0} = shift{3-0};
1482 let Unpredictable{15-12} = 0b1111;
1484 def rsr : AI1<opcod, (outs),
1485 (ins GPRnopc:$Rn, so_reg_reg:$shift), DPSoRegRegFrm, iis,
1486 opc, "\t$Rn, $shift",
1487 [(opnode GPRnopc:$Rn, so_reg_reg:$shift)]>,
1488 Sched<[WriteCMPsr, ReadALU]> {
1493 let Inst{19-16} = Rn;
1494 let Inst{15-12} = 0b0000;
1495 let Inst{11-8} = shift{11-8};
1497 let Inst{6-5} = shift{6-5};
1499 let Inst{3-0} = shift{3-0};
1501 let Unpredictable{15-12} = 0b1111;
1507 /// AI_ext_rrot - A unary operation with two forms: one whose operand is a
1508 /// register and one whose operand is a register rotated by 8/16/24.
1509 /// FIXME: Remove the 'r' variant. Its rot_imm is zero.
1510 class AI_ext_rrot<bits<8> opcod, string opc, PatFrag opnode>
1511 : AExtI<opcod, (outs GPRnopc:$Rd), (ins GPRnopc:$Rm, rot_imm:$rot),
1512 IIC_iEXTr, opc, "\t$Rd, $Rm$rot",
1513 [(set GPRnopc:$Rd, (opnode (rotr GPRnopc:$Rm, rot_imm:$rot)))]>,
1514 Requires<[IsARM, HasV6]>, Sched<[WriteALUsi]> {
1518 let Inst{19-16} = 0b1111;
1519 let Inst{15-12} = Rd;
1520 let Inst{11-10} = rot;
1524 class AI_ext_rrot_np<bits<8> opcod, string opc>
1525 : AExtI<opcod, (outs GPRnopc:$Rd), (ins GPRnopc:$Rm, rot_imm:$rot),
1526 IIC_iEXTr, opc, "\t$Rd, $Rm$rot", []>,
1527 Requires<[IsARM, HasV6]>, Sched<[WriteALUsi]> {
1529 let Inst{19-16} = 0b1111;
1530 let Inst{11-10} = rot;
1533 /// AI_exta_rrot - A binary operation with two forms: one whose operand is a
1534 /// register and one whose operand is a register rotated by 8/16/24.
1535 class AI_exta_rrot<bits<8> opcod, string opc, PatFrag opnode>
1536 : AExtI<opcod, (outs GPRnopc:$Rd), (ins GPR:$Rn, GPRnopc:$Rm, rot_imm:$rot),
1537 IIC_iEXTAr, opc, "\t$Rd, $Rn, $Rm$rot",
1538 [(set GPRnopc:$Rd, (opnode GPR:$Rn,
1539 (rotr GPRnopc:$Rm, rot_imm:$rot)))]>,
1540 Requires<[IsARM, HasV6]>, Sched<[WriteALUsr]> {
1545 let Inst{19-16} = Rn;
1546 let Inst{15-12} = Rd;
1547 let Inst{11-10} = rot;
1548 let Inst{9-4} = 0b000111;
1552 class AI_exta_rrot_np<bits<8> opcod, string opc>
1553 : AExtI<opcod, (outs GPRnopc:$Rd), (ins GPR:$Rn, GPRnopc:$Rm, rot_imm:$rot),
1554 IIC_iEXTAr, opc, "\t$Rd, $Rn, $Rm$rot", []>,
1555 Requires<[IsARM, HasV6]>, Sched<[WriteALUsr]> {
1558 let Inst{19-16} = Rn;
1559 let Inst{11-10} = rot;
1562 /// AI1_adde_sube_irs - Define instructions and patterns for adde and sube.
1563 let TwoOperandAliasConstraint = "$Rn = $Rd" in
1564 multiclass AI1_adde_sube_irs<bits<4> opcod, string opc, PatFrag opnode,
1565 bit Commutable = 0> {
1566 let hasPostISelHook = 1, Defs = [CPSR], Uses = [CPSR] in {
1567 def ri : AsI1<opcod, (outs GPR:$Rd), (ins GPR:$Rn, mod_imm:$imm),
1568 DPFrm, IIC_iALUi, opc, "\t$Rd, $Rn, $imm",
1569 [(set GPR:$Rd, CPSR, (opnode GPR:$Rn, mod_imm:$imm, CPSR))]>,
1571 Sched<[WriteALU, ReadALU]> {
1576 let Inst{15-12} = Rd;
1577 let Inst{19-16} = Rn;
1578 let Inst{11-0} = imm;
1580 def rr : AsI1<opcod, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm),
1581 DPFrm, IIC_iALUr, opc, "\t$Rd, $Rn, $Rm",
1582 [(set GPR:$Rd, CPSR, (opnode GPR:$Rn, GPR:$Rm, CPSR))]>,
1584 Sched<[WriteALU, ReadALU, ReadALU]> {
1588 let Inst{11-4} = 0b00000000;
1590 let isCommutable = Commutable;
1592 let Inst{15-12} = Rd;
1593 let Inst{19-16} = Rn;
1595 def rsi : AsI1<opcod, (outs GPR:$Rd),
1596 (ins GPR:$Rn, so_reg_imm:$shift),
1597 DPSoRegImmFrm, IIC_iALUsr, opc, "\t$Rd, $Rn, $shift",
1598 [(set GPR:$Rd, CPSR, (opnode GPR:$Rn, so_reg_imm:$shift, CPSR))]>,
1600 Sched<[WriteALUsi, ReadALU]> {
1605 let Inst{19-16} = Rn;
1606 let Inst{15-12} = Rd;
1607 let Inst{11-5} = shift{11-5};
1609 let Inst{3-0} = shift{3-0};
1611 def rsr : AsI1<opcod, (outs GPRnopc:$Rd),
1612 (ins GPRnopc:$Rn, so_reg_reg:$shift),
1613 DPSoRegRegFrm, IIC_iALUsr, opc, "\t$Rd, $Rn, $shift",
1614 [(set GPRnopc:$Rd, CPSR,
1615 (opnode GPRnopc:$Rn, so_reg_reg:$shift, CPSR))]>,
1617 Sched<[WriteALUsr, ReadALUsr]> {
1622 let Inst{19-16} = Rn;
1623 let Inst{15-12} = Rd;
1624 let Inst{11-8} = shift{11-8};
1626 let Inst{6-5} = shift{6-5};
1628 let Inst{3-0} = shift{3-0};
1633 /// AI1_rsc_irs - Define instructions and patterns for rsc
1634 let TwoOperandAliasConstraint = "$Rn = $Rd" in
1635 multiclass AI1_rsc_irs<bits<4> opcod, string opc, PatFrag opnode> {
1636 let hasPostISelHook = 1, Defs = [CPSR], Uses = [CPSR] in {
1637 def ri : AsI1<opcod, (outs GPR:$Rd), (ins GPR:$Rn, mod_imm:$imm),
1638 DPFrm, IIC_iALUi, opc, "\t$Rd, $Rn, $imm",
1639 [(set GPR:$Rd, CPSR, (opnode mod_imm:$imm, GPR:$Rn, CPSR))]>,
1641 Sched<[WriteALU, ReadALU]> {
1646 let Inst{15-12} = Rd;
1647 let Inst{19-16} = Rn;
1648 let Inst{11-0} = imm;
1650 def rr : AsI1<opcod, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm),
1651 DPFrm, IIC_iALUr, opc, "\t$Rd, $Rn, $Rm",
1652 [/* pattern left blank */]>,
1653 Sched<[WriteALU, ReadALU, ReadALU]> {
1657 let Inst{11-4} = 0b00000000;
1660 let Inst{15-12} = Rd;
1661 let Inst{19-16} = Rn;
1663 def rsi : AsI1<opcod, (outs GPR:$Rd), (ins GPR:$Rn, so_reg_imm:$shift),
1664 DPSoRegImmFrm, IIC_iALUsr, opc, "\t$Rd, $Rn, $shift",
1665 [(set GPR:$Rd, CPSR, (opnode so_reg_imm:$shift, GPR:$Rn, CPSR))]>,
1667 Sched<[WriteALUsi, ReadALU]> {
1672 let Inst{19-16} = Rn;
1673 let Inst{15-12} = Rd;
1674 let Inst{11-5} = shift{11-5};
1676 let Inst{3-0} = shift{3-0};
1678 def rsr : AsI1<opcod, (outs GPR:$Rd), (ins GPR:$Rn, so_reg_reg:$shift),
1679 DPSoRegRegFrm, IIC_iALUsr, opc, "\t$Rd, $Rn, $shift",
1680 [(set GPR:$Rd, CPSR, (opnode so_reg_reg:$shift, GPR:$Rn, CPSR))]>,
1682 Sched<[WriteALUsr, ReadALUsr]> {
1687 let Inst{19-16} = Rn;
1688 let Inst{15-12} = Rd;
1689 let Inst{11-8} = shift{11-8};
1691 let Inst{6-5} = shift{6-5};
1693 let Inst{3-0} = shift{3-0};
1698 let canFoldAsLoad = 1, isReMaterializable = 1 in {
1699 multiclass AI_ldr1<bit isByte, string opc, InstrItinClass iii,
1700 InstrItinClass iir, PatFrag opnode> {
1701 // Note: We use the complex addrmode_imm12 rather than just an input
1702 // GPR and a constrained immediate so that we can use this to match
1703 // frame index references and avoid matching constant pool references.
1704 def i12: AI2ldst<0b010, 1, isByte, (outs GPR:$Rt), (ins addrmode_imm12:$addr),
1705 AddrMode_i12, LdFrm, iii, opc, "\t$Rt, $addr",
1706 [(set GPR:$Rt, (opnode addrmode_imm12:$addr))]> {
1709 let Inst{23} = addr{12}; // U (add = ('U' == 1))
1710 let Inst{19-16} = addr{16-13}; // Rn
1711 let Inst{15-12} = Rt;
1712 let Inst{11-0} = addr{11-0}; // imm12
1714 def rs : AI2ldst<0b011, 1, isByte, (outs GPR:$Rt), (ins ldst_so_reg:$shift),
1715 AddrModeNone, LdFrm, iir, opc, "\t$Rt, $shift",
1716 [(set GPR:$Rt, (opnode ldst_so_reg:$shift))]> {
1719 let shift{4} = 0; // Inst{4} = 0
1720 let Inst{23} = shift{12}; // U (add = ('U' == 1))
1721 let Inst{19-16} = shift{16-13}; // Rn
1722 let Inst{15-12} = Rt;
1723 let Inst{11-0} = shift{11-0};
1728 let canFoldAsLoad = 1, isReMaterializable = 1 in {
1729 multiclass AI_ldr1nopc<bit isByte, string opc, InstrItinClass iii,
1730 InstrItinClass iir, PatFrag opnode> {
1731 // Note: We use the complex addrmode_imm12 rather than just an input
1732 // GPR and a constrained immediate so that we can use this to match
1733 // frame index references and avoid matching constant pool references.
1734 def i12: AI2ldst<0b010, 1, isByte, (outs GPRnopc:$Rt),
1735 (ins addrmode_imm12:$addr),
1736 AddrMode_i12, LdFrm, iii, opc, "\t$Rt, $addr",
1737 [(set GPRnopc:$Rt, (opnode addrmode_imm12:$addr))]> {
1740 let Inst{23} = addr{12}; // U (add = ('U' == 1))
1741 let Inst{19-16} = addr{16-13}; // Rn
1742 let Inst{15-12} = Rt;
1743 let Inst{11-0} = addr{11-0}; // imm12
1745 def rs : AI2ldst<0b011, 1, isByte, (outs GPRnopc:$Rt),
1746 (ins ldst_so_reg:$shift),
1747 AddrModeNone, LdFrm, iir, opc, "\t$Rt, $shift",
1748 [(set GPRnopc:$Rt, (opnode ldst_so_reg:$shift))]> {
1751 let shift{4} = 0; // Inst{4} = 0
1752 let Inst{23} = shift{12}; // U (add = ('U' == 1))
1753 let Inst{19-16} = shift{16-13}; // Rn
1754 let Inst{15-12} = Rt;
1755 let Inst{11-0} = shift{11-0};
1761 multiclass AI_str1<bit isByte, string opc, InstrItinClass iii,
1762 InstrItinClass iir, PatFrag opnode> {
1763 // Note: We use the complex addrmode_imm12 rather than just an input
1764 // GPR and a constrained immediate so that we can use this to match
1765 // frame index references and avoid matching constant pool references.
1766 def i12 : AI2ldst<0b010, 0, isByte, (outs),
1767 (ins GPR:$Rt, addrmode_imm12:$addr),
1768 AddrMode_i12, StFrm, iii, opc, "\t$Rt, $addr",
1769 [(opnode GPR:$Rt, addrmode_imm12:$addr)]> {
1772 let Inst{23} = addr{12}; // U (add = ('U' == 1))
1773 let Inst{19-16} = addr{16-13}; // Rn
1774 let Inst{15-12} = Rt;
1775 let Inst{11-0} = addr{11-0}; // imm12
1777 def rs : AI2ldst<0b011, 0, isByte, (outs), (ins GPR:$Rt, ldst_so_reg:$shift),
1778 AddrModeNone, StFrm, iir, opc, "\t$Rt, $shift",
1779 [(opnode GPR:$Rt, ldst_so_reg:$shift)]> {
1782 let shift{4} = 0; // Inst{4} = 0
1783 let Inst{23} = shift{12}; // U (add = ('U' == 1))
1784 let Inst{19-16} = shift{16-13}; // Rn
1785 let Inst{15-12} = Rt;
1786 let Inst{11-0} = shift{11-0};
1790 multiclass AI_str1nopc<bit isByte, string opc, InstrItinClass iii,
1791 InstrItinClass iir, PatFrag opnode> {
1792 // Note: We use the complex addrmode_imm12 rather than just an input
1793 // GPR and a constrained immediate so that we can use this to match
1794 // frame index references and avoid matching constant pool references.
1795 def i12 : AI2ldst<0b010, 0, isByte, (outs),
1796 (ins GPRnopc:$Rt, addrmode_imm12:$addr),
1797 AddrMode_i12, StFrm, iii, opc, "\t$Rt, $addr",
1798 [(opnode GPRnopc:$Rt, addrmode_imm12:$addr)]> {
1801 let Inst{23} = addr{12}; // U (add = ('U' == 1))
1802 let Inst{19-16} = addr{16-13}; // Rn
1803 let Inst{15-12} = Rt;
1804 let Inst{11-0} = addr{11-0}; // imm12
1806 def rs : AI2ldst<0b011, 0, isByte, (outs),
1807 (ins GPRnopc:$Rt, ldst_so_reg:$shift),
1808 AddrModeNone, StFrm, iir, opc, "\t$Rt, $shift",
1809 [(opnode GPRnopc:$Rt, ldst_so_reg:$shift)]> {
1812 let shift{4} = 0; // Inst{4} = 0
1813 let Inst{23} = shift{12}; // U (add = ('U' == 1))
1814 let Inst{19-16} = shift{16-13}; // Rn
1815 let Inst{15-12} = Rt;
1816 let Inst{11-0} = shift{11-0};
1821 //===----------------------------------------------------------------------===//
1823 //===----------------------------------------------------------------------===//
1825 //===----------------------------------------------------------------------===//
1826 // Miscellaneous Instructions.
1829 /// CONSTPOOL_ENTRY - This instruction represents a floating constant pool in
1830 /// the function. The first operand is the ID# for this instruction, the second
1831 /// is the index into the MachineConstantPool that this is, the third is the
1832 /// size in bytes of this constant pool entry.
1833 let hasSideEffects = 0, isNotDuplicable = 1 in
1834 def CONSTPOOL_ENTRY :
1835 PseudoInst<(outs), (ins cpinst_operand:$instid, cpinst_operand:$cpidx,
1836 i32imm:$size), NoItinerary, []>;
1838 /// A jumptable consisting of direct 32-bit addresses of the destination basic
1839 /// blocks (either absolute, or relative to the start of the jump-table in PIC
1840 /// mode). Used mostly in ARM and Thumb-1 modes.
1841 def JUMPTABLE_ADDRS :
1842 PseudoInst<(outs), (ins cpinst_operand:$instid, cpinst_operand:$cpidx,
1843 i32imm:$size), NoItinerary, []>;
1845 /// A jumptable consisting of 32-bit jump instructions. Used for Thumb-2 tables
1846 /// that cannot be optimised to use TBB or TBH.
1847 def JUMPTABLE_INSTS :
1848 PseudoInst<(outs), (ins cpinst_operand:$instid, cpinst_operand:$cpidx,
1849 i32imm:$size), NoItinerary, []>;
1851 /// A jumptable consisting of 8-bit unsigned integers representing offsets from
1852 /// a TBB instruction.
1854 PseudoInst<(outs), (ins cpinst_operand:$instid, cpinst_operand:$cpidx,
1855 i32imm:$size), NoItinerary, []>;
1857 /// A jumptable consisting of 16-bit unsigned integers representing offsets from
1858 /// a TBH instruction.
1860 PseudoInst<(outs), (ins cpinst_operand:$instid, cpinst_operand:$cpidx,
1861 i32imm:$size), NoItinerary, []>;
1864 // FIXME: Marking these as hasSideEffects is necessary to prevent machine DCE
1865 // from removing one half of the matched pairs. That breaks PEI, which assumes
1866 // these will always be in pairs, and asserts if it finds otherwise. Better way?
1867 let Defs = [SP], Uses = [SP], hasSideEffects = 1 in {
1868 def ADJCALLSTACKUP :
1869 PseudoInst<(outs), (ins i32imm:$amt1, i32imm:$amt2, pred:$p), NoItinerary,
1870 [(ARMcallseq_end timm:$amt1, timm:$amt2)]>;
1872 def ADJCALLSTACKDOWN :
1873 PseudoInst<(outs), (ins i32imm:$amt, pred:$p), NoItinerary,
1874 [(ARMcallseq_start timm:$amt)]>;
1877 def HINT : AI<(outs), (ins imm0_239:$imm), MiscFrm, NoItinerary,
1878 "hint", "\t$imm", [(int_arm_hint imm0_239:$imm)]>,
1879 Requires<[IsARM, HasV6]> {
1881 let Inst{27-8} = 0b00110010000011110000;
1882 let Inst{7-0} = imm;
1885 def : InstAlias<"nop$p", (HINT 0, pred:$p)>, Requires<[IsARM, HasV6K]>;
1886 def : InstAlias<"yield$p", (HINT 1, pred:$p)>, Requires<[IsARM, HasV6K]>;
1887 def : InstAlias<"wfe$p", (HINT 2, pred:$p)>, Requires<[IsARM, HasV6K]>;
1888 def : InstAlias<"wfi$p", (HINT 3, pred:$p)>, Requires<[IsARM, HasV6K]>;
1889 def : InstAlias<"sev$p", (HINT 4, pred:$p)>, Requires<[IsARM, HasV6K]>;
1890 def : InstAlias<"sevl$p", (HINT 5, pred:$p)>, Requires<[IsARM, HasV8]>;
1892 def SEL : AI<(outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm), DPFrm, NoItinerary, "sel",
1893 "\t$Rd, $Rn, $Rm", []>, Requires<[IsARM, HasV6]> {
1898 let Inst{15-12} = Rd;
1899 let Inst{19-16} = Rn;
1900 let Inst{27-20} = 0b01101000;
1901 let Inst{7-4} = 0b1011;
1902 let Inst{11-8} = 0b1111;
1903 let Unpredictable{11-8} = 0b1111;
1906 // The 16-bit operand $val can be used by a debugger to store more information
1907 // about the breakpoint.
1908 def BKPT : AInoP<(outs), (ins imm0_65535:$val), MiscFrm, NoItinerary,
1909 "bkpt", "\t$val", []>, Requires<[IsARM]> {
1911 let Inst{3-0} = val{3-0};
1912 let Inst{19-8} = val{15-4};
1913 let Inst{27-20} = 0b00010010;
1914 let Inst{31-28} = 0xe; // AL
1915 let Inst{7-4} = 0b0111;
1917 // default immediate for breakpoint mnemonic
1918 def : InstAlias<"bkpt", (BKPT 0)>, Requires<[IsARM]>;
1920 def HLT : AInoP<(outs), (ins imm0_65535:$val), MiscFrm, NoItinerary,
1921 "hlt", "\t$val", []>, Requires<[IsARM, HasV8]> {
1923 let Inst{3-0} = val{3-0};
1924 let Inst{19-8} = val{15-4};
1925 let Inst{27-20} = 0b00010000;
1926 let Inst{31-28} = 0xe; // AL
1927 let Inst{7-4} = 0b0111;
1930 // Change Processor State
1931 // FIXME: We should use InstAlias to handle the optional operands.
1932 class CPS<dag iops, string asm_ops>
1933 : AXI<(outs), iops, MiscFrm, NoItinerary, !strconcat("cps", asm_ops),
1934 []>, Requires<[IsARM]> {
1940 let Inst{31-28} = 0b1111;
1941 let Inst{27-20} = 0b00010000;
1942 let Inst{19-18} = imod;
1943 let Inst{17} = M; // Enabled if mode is set;
1944 let Inst{16-9} = 0b00000000;
1945 let Inst{8-6} = iflags;
1947 let Inst{4-0} = mode;
1950 let DecoderMethod = "DecodeCPSInstruction" in {
1952 def CPS3p : CPS<(ins imod_op:$imod, iflags_op:$iflags, imm0_31:$mode),
1953 "$imod\t$iflags, $mode">;
1954 let mode = 0, M = 0 in
1955 def CPS2p : CPS<(ins imod_op:$imod, iflags_op:$iflags), "$imod\t$iflags">;
1957 let imod = 0, iflags = 0, M = 1 in
1958 def CPS1p : CPS<(ins imm0_31:$mode), "\t$mode">;
1961 // Preload signals the memory system of possible future data/instruction access.
1962 multiclass APreLoad<bits<1> read, bits<1> data, string opc> {
1964 def i12 : AXIM<(outs), (ins addrmode_imm12:$addr), AddrMode_i12, MiscFrm,
1965 IIC_Preload, !strconcat(opc, "\t$addr"),
1966 [(ARMPreload addrmode_imm12:$addr, (i32 read), (i32 data))]>,
1967 Sched<[WritePreLd]> {
1970 let Inst{31-26} = 0b111101;
1971 let Inst{25} = 0; // 0 for immediate form
1972 let Inst{24} = data;
1973 let Inst{23} = addr{12}; // U (add = ('U' == 1))
1974 let Inst{22} = read;
1975 let Inst{21-20} = 0b01;
1976 let Inst{19-16} = addr{16-13}; // Rn
1977 let Inst{15-12} = 0b1111;
1978 let Inst{11-0} = addr{11-0}; // imm12
1981 def rs : AXI<(outs), (ins ldst_so_reg:$shift), MiscFrm, IIC_Preload,
1982 !strconcat(opc, "\t$shift"),
1983 [(ARMPreload ldst_so_reg:$shift, (i32 read), (i32 data))]>,
1984 Sched<[WritePreLd]> {
1986 let Inst{31-26} = 0b111101;
1987 let Inst{25} = 1; // 1 for register form
1988 let Inst{24} = data;
1989 let Inst{23} = shift{12}; // U (add = ('U' == 1))
1990 let Inst{22} = read;
1991 let Inst{21-20} = 0b01;
1992 let Inst{19-16} = shift{16-13}; // Rn
1993 let Inst{15-12} = 0b1111;
1994 let Inst{11-0} = shift{11-0};
1999 defm PLD : APreLoad<1, 1, "pld">, Requires<[IsARM]>;
2000 defm PLDW : APreLoad<0, 1, "pldw">, Requires<[IsARM,HasV7,HasMP]>;
2001 defm PLI : APreLoad<1, 0, "pli">, Requires<[IsARM,HasV7]>;
2003 def SETEND : AXI<(outs), (ins setend_op:$end), MiscFrm, NoItinerary,
2004 "setend\t$end", []>, Requires<[IsARM]>, Deprecated<HasV8Ops> {
2006 let Inst{31-10} = 0b1111000100000001000000;
2011 def DBG : AI<(outs), (ins imm0_15:$opt), MiscFrm, NoItinerary, "dbg", "\t$opt",
2012 [(int_arm_dbg imm0_15:$opt)]>, Requires<[IsARM, HasV7]> {
2014 let Inst{27-4} = 0b001100100000111100001111;
2015 let Inst{3-0} = opt;
2018 // A8.8.247 UDF - Undefined (Encoding A1)
2019 def UDF : AInoP<(outs), (ins imm0_65535:$imm16), MiscFrm, NoItinerary,
2020 "udf", "\t$imm16", [(int_arm_undefined imm0_65535:$imm16)]> {
2022 let Inst{31-28} = 0b1110; // AL
2023 let Inst{27-25} = 0b011;
2024 let Inst{24-20} = 0b11111;
2025 let Inst{19-8} = imm16{15-4};
2026 let Inst{7-4} = 0b1111;
2027 let Inst{3-0} = imm16{3-0};
2031 * A5.4 Permanently UNDEFINED instructions.
2033 * For most targets use UDF #65006, for which the OS will generate SIGTRAP.
2034 * Other UDF encodings generate SIGILL.
2036 * NaCl's OS instead chooses an ARM UDF encoding that's also a UDF in Thumb.
2038 * 1110 0111 1111 iiii iiii iiii 1111 iiii
2040 * 1101 1110 iiii iiii
2041 * It uses the following encoding:
2042 * 1110 0111 1111 1110 1101 1110 1111 0000
2043 * - In ARM: UDF #60896;
2044 * - In Thumb: UDF #254 followed by a branch-to-self.
2046 let isBarrier = 1, isTerminator = 1 in
2047 def TRAPNaCl : AXI<(outs), (ins), MiscFrm, NoItinerary,
2049 Requires<[IsARM,UseNaClTrap]> {
2050 let Inst = 0xe7fedef0;
2052 let isBarrier = 1, isTerminator = 1 in
2053 def TRAP : AXI<(outs), (ins), MiscFrm, NoItinerary,
2055 Requires<[IsARM,DontUseNaClTrap]> {
2056 let Inst = 0xe7ffdefe;
2059 // Address computation and loads and stores in PIC mode.
2060 let isNotDuplicable = 1 in {
2061 def PICADD : ARMPseudoInst<(outs GPR:$dst), (ins GPR:$a, pclabel:$cp, pred:$p),
2063 [(set GPR:$dst, (ARMpic_add GPR:$a, imm:$cp))]>,
2064 Sched<[WriteALU, ReadALU]>;
2066 let AddedComplexity = 10 in {
2067 def PICLDR : ARMPseudoInst<(outs GPR:$dst), (ins addrmodepc:$addr, pred:$p),
2069 [(set GPR:$dst, (load addrmodepc:$addr))]>;
2071 def PICLDRH : ARMPseudoInst<(outs GPR:$Rt), (ins addrmodepc:$addr, pred:$p),
2073 [(set GPR:$Rt, (zextloadi16 addrmodepc:$addr))]>;
2075 def PICLDRB : ARMPseudoInst<(outs GPR:$Rt), (ins addrmodepc:$addr, pred:$p),
2077 [(set GPR:$Rt, (zextloadi8 addrmodepc:$addr))]>;
2079 def PICLDRSH : ARMPseudoInst<(outs GPR:$Rt), (ins addrmodepc:$addr, pred:$p),
2081 [(set GPR:$Rt, (sextloadi16 addrmodepc:$addr))]>;
2083 def PICLDRSB : ARMPseudoInst<(outs GPR:$Rt), (ins addrmodepc:$addr, pred:$p),
2085 [(set GPR:$Rt, (sextloadi8 addrmodepc:$addr))]>;
2087 let AddedComplexity = 10 in {
2088 def PICSTR : ARMPseudoInst<(outs), (ins GPR:$src, addrmodepc:$addr, pred:$p),
2089 4, IIC_iStore_r, [(store GPR:$src, addrmodepc:$addr)]>;
2091 def PICSTRH : ARMPseudoInst<(outs), (ins GPR:$src, addrmodepc:$addr, pred:$p),
2092 4, IIC_iStore_bh_r, [(truncstorei16 GPR:$src,
2093 addrmodepc:$addr)]>;
2095 def PICSTRB : ARMPseudoInst<(outs), (ins GPR:$src, addrmodepc:$addr, pred:$p),
2096 4, IIC_iStore_bh_r, [(truncstorei8 GPR:$src, addrmodepc:$addr)]>;
2098 } // isNotDuplicable = 1
2101 // LEApcrel - Load a pc-relative address into a register without offending the
2103 let hasSideEffects = 0, isReMaterializable = 1 in
2104 // The 'adr' mnemonic encodes differently if the label is before or after
2105 // the instruction. The {24-21} opcode bits are set by the fixup, as we don't
2106 // know until then which form of the instruction will be used.
2107 def ADR : AI1<{0,?,?,0}, (outs GPR:$Rd), (ins adrlabel:$label),
2108 MiscFrm, IIC_iALUi, "adr", "\t$Rd, $label", []>,
2109 Sched<[WriteALU, ReadALU]> {
2112 let Inst{27-25} = 0b001;
2114 let Inst{23-22} = label{13-12};
2117 let Inst{19-16} = 0b1111;
2118 let Inst{15-12} = Rd;
2119 let Inst{11-0} = label{11-0};
2122 let hasSideEffects = 1 in {
2123 def LEApcrel : ARMPseudoInst<(outs GPR:$Rd), (ins i32imm:$label, pred:$p),
2124 4, IIC_iALUi, []>, Sched<[WriteALU, ReadALU]>;
2126 def LEApcrelJT : ARMPseudoInst<(outs GPR:$Rd),
2127 (ins i32imm:$label, pred:$p),
2128 4, IIC_iALUi, []>, Sched<[WriteALU, ReadALU]>;
2131 //===----------------------------------------------------------------------===//
2132 // Control Flow Instructions.
2135 let isReturn = 1, isTerminator = 1, isBarrier = 1 in {
2137 def BX_RET : AI<(outs), (ins), BrMiscFrm, IIC_Br,
2138 "bx", "\tlr", [(ARMretflag)]>,
2139 Requires<[IsARM, HasV4T]>, Sched<[WriteBr]> {
2140 let Inst{27-0} = 0b0001001011111111111100011110;
2144 def MOVPCLR : AI<(outs), (ins), BrMiscFrm, IIC_Br,
2145 "mov", "\tpc, lr", [(ARMretflag)]>,
2146 Requires<[IsARM, NoV4T]>, Sched<[WriteBr]> {
2147 let Inst{27-0} = 0b0001101000001111000000001110;
2150 // Exception return: N.b. doesn't set CPSR as far as we're concerned (it sets
2151 // the user-space one).
2152 def SUBS_PC_LR : ARMPseudoInst<(outs), (ins i32imm:$offset, pred:$p),
2154 [(ARMintretflag imm:$offset)]>;
2157 // Indirect branches
2158 let isBranch = 1, isTerminator = 1, isBarrier = 1, isIndirectBranch = 1 in {
2160 def BX : AXI<(outs), (ins GPR:$dst), BrMiscFrm, IIC_Br, "bx\t$dst",
2161 [(brind GPR:$dst)]>,
2162 Requires<[IsARM, HasV4T]>, Sched<[WriteBr]> {
2164 let Inst{31-4} = 0b1110000100101111111111110001;
2165 let Inst{3-0} = dst;
2168 def BX_pred : AI<(outs), (ins GPR:$dst), BrMiscFrm, IIC_Br,
2169 "bx", "\t$dst", [/* pattern left blank */]>,
2170 Requires<[IsARM, HasV4T]>, Sched<[WriteBr]> {
2172 let Inst{27-4} = 0b000100101111111111110001;
2173 let Inst{3-0} = dst;
2177 // SP is marked as a use to prevent stack-pointer assignments that appear
2178 // immediately before calls from potentially appearing dead.
2180 // FIXME: Do we really need a non-predicated version? If so, it should
2181 // at least be a pseudo instruction expanding to the predicated version
2182 // at MC lowering time.
2183 Defs = [LR], Uses = [SP] in {
2184 def BL : ABXI<0b1011, (outs), (ins bl_target:$func),
2185 IIC_Br, "bl\t$func",
2186 [(ARMcall tglobaladdr:$func)]>,
2187 Requires<[IsARM]>, Sched<[WriteBrL]> {
2188 let Inst{31-28} = 0b1110;
2190 let Inst{23-0} = func;
2191 let DecoderMethod = "DecodeBranchImmInstruction";
2194 def BL_pred : ABI<0b1011, (outs), (ins bl_target:$func),
2195 IIC_Br, "bl", "\t$func",
2196 [(ARMcall_pred tglobaladdr:$func)]>,
2197 Requires<[IsARM]>, Sched<[WriteBrL]> {
2199 let Inst{23-0} = func;
2200 let DecoderMethod = "DecodeBranchImmInstruction";
2204 def BLX : AXI<(outs), (ins GPR:$func), BrMiscFrm,
2205 IIC_Br, "blx\t$func",
2206 [(ARMcall GPR:$func)]>,
2207 Requires<[IsARM, HasV5T]>, Sched<[WriteBrL]> {
2209 let Inst{31-4} = 0b1110000100101111111111110011;
2210 let Inst{3-0} = func;
2213 def BLX_pred : AI<(outs), (ins GPR:$func), BrMiscFrm,
2214 IIC_Br, "blx", "\t$func",
2215 [(ARMcall_pred GPR:$func)]>,
2216 Requires<[IsARM, HasV5T]>, Sched<[WriteBrL]> {
2218 let Inst{27-4} = 0b000100101111111111110011;
2219 let Inst{3-0} = func;
2223 // Note: Restrict $func to the tGPR regclass to prevent it being in LR.
2224 def BX_CALL : ARMPseudoInst<(outs), (ins tGPR:$func),
2225 8, IIC_Br, [(ARMcall_nolink tGPR:$func)]>,
2226 Requires<[IsARM, HasV4T]>, Sched<[WriteBr]>;
2229 def BMOVPCRX_CALL : ARMPseudoInst<(outs), (ins tGPR:$func),
2230 8, IIC_Br, [(ARMcall_nolink tGPR:$func)]>,
2231 Requires<[IsARM, NoV4T]>, Sched<[WriteBr]>;
2233 // mov lr, pc; b if callee is marked noreturn to avoid confusing the
2234 // return stack predictor.
2235 def BMOVPCB_CALL : ARMPseudoInst<(outs), (ins bl_target:$func),
2236 8, IIC_Br, [(ARMcall_nolink tglobaladdr:$func)]>,
2237 Requires<[IsARM]>, Sched<[WriteBr]>;
2240 let isBranch = 1, isTerminator = 1 in {
2241 // FIXME: should be able to write a pattern for ARMBrcond, but can't use
2242 // a two-value operand where a dag node expects two operands. :(
2243 def Bcc : ABI<0b1010, (outs), (ins br_target:$target),
2244 IIC_Br, "b", "\t$target",
2245 [/*(ARMbrcond bb:$target, imm:$cc, CCR:$ccr)*/]>,
2248 let Inst{23-0} = target;
2249 let DecoderMethod = "DecodeBranchImmInstruction";
2252 let isBarrier = 1 in {
2253 // B is "predicable" since it's just a Bcc with an 'always' condition.
2254 let isPredicable = 1 in
2255 // FIXME: We shouldn't need this pseudo at all. Just using Bcc directly
2256 // should be sufficient.
2257 // FIXME: Is B really a Barrier? That doesn't seem right.
2258 def B : ARMPseudoExpand<(outs), (ins br_target:$target), 4, IIC_Br,
2259 [(br bb:$target)], (Bcc br_target:$target, (ops 14, zero_reg))>,
2262 let Size = 4, isNotDuplicable = 1, isIndirectBranch = 1 in {
2263 def BR_JTr : ARMPseudoInst<(outs),
2264 (ins GPR:$target, i32imm:$jt),
2266 [(ARMbrjt GPR:$target, tjumptable:$jt)]>,
2268 // FIXME: This shouldn't use the generic "addrmode2," but rather be split
2269 // into i12 and rs suffixed versions.
2270 def BR_JTm : ARMPseudoInst<(outs),
2271 (ins addrmode2:$target, i32imm:$jt),
2273 [(ARMbrjt (i32 (load addrmode2:$target)),
2274 tjumptable:$jt)]>, Sched<[WriteBrTbl]>;
2275 def BR_JTadd : ARMPseudoInst<(outs),
2276 (ins GPR:$target, GPR:$idx, i32imm:$jt),
2278 [(ARMbrjt (add GPR:$target, GPR:$idx), tjumptable:$jt)]>,
2279 Sched<[WriteBrTbl]>;
2280 } // isNotDuplicable = 1, isIndirectBranch = 1
2286 def BLXi : AXI<(outs), (ins blx_target:$target), BrMiscFrm, NoItinerary,
2287 "blx\t$target", []>,
2288 Requires<[IsARM, HasV5T]>, Sched<[WriteBrL]> {
2289 let Inst{31-25} = 0b1111101;
2291 let Inst{23-0} = target{24-1};
2292 let Inst{24} = target{0};
2296 // Branch and Exchange Jazelle
2297 def BXJ : ABI<0b0001, (outs), (ins GPR:$func), NoItinerary, "bxj", "\t$func",
2298 [/* pattern left blank */]>, Sched<[WriteBr]> {
2300 let Inst{23-20} = 0b0010;
2301 let Inst{19-8} = 0xfff;
2302 let Inst{7-4} = 0b0010;
2303 let Inst{3-0} = func;
2309 let isCall = 1, isTerminator = 1, isReturn = 1, isBarrier = 1, Uses = [SP] in {
2310 def TCRETURNdi : PseudoInst<(outs), (ins i32imm:$dst), IIC_Br, []>,
2313 def TCRETURNri : PseudoInst<(outs), (ins tcGPR:$dst), IIC_Br, []>,
2316 def TAILJMPd : ARMPseudoExpand<(outs), (ins br_target:$dst),
2318 (Bcc br_target:$dst, (ops 14, zero_reg))>,
2319 Requires<[IsARM]>, Sched<[WriteBr]>;
2321 def TAILJMPr : ARMPseudoExpand<(outs), (ins tcGPR:$dst),
2323 (BX GPR:$dst)>, Sched<[WriteBr]>,
2327 // Secure Monitor Call is a system instruction.
2328 def SMC : ABI<0b0001, (outs), (ins imm0_15:$opt), NoItinerary, "smc", "\t$opt",
2329 []>, Requires<[IsARM, HasTrustZone]> {
2331 let Inst{23-4} = 0b01100000000000000111;
2332 let Inst{3-0} = opt;
2334 def : MnemonicAlias<"smi", "smc">;
2336 // Supervisor Call (Software Interrupt)
2337 let isCall = 1, Uses = [SP] in {
2338 def SVC : ABI<0b1111, (outs), (ins imm24b:$svc), IIC_Br, "svc", "\t$svc", []>,
2341 let Inst{23-0} = svc;
2345 // Store Return State
2346 class SRSI<bit wb, string asm>
2347 : XI<(outs), (ins imm0_31:$mode), AddrModeNone, 4, IndexModeNone, BrFrm,
2348 NoItinerary, asm, "", []> {
2350 let Inst{31-28} = 0b1111;
2351 let Inst{27-25} = 0b100;
2355 let Inst{19-16} = 0b1101; // SP
2356 let Inst{15-5} = 0b00000101000;
2357 let Inst{4-0} = mode;
2360 def SRSDA : SRSI<0, "srsda\tsp, $mode"> {
2361 let Inst{24-23} = 0;
2363 def SRSDA_UPD : SRSI<1, "srsda\tsp!, $mode"> {
2364 let Inst{24-23} = 0;
2366 def SRSDB : SRSI<0, "srsdb\tsp, $mode"> {
2367 let Inst{24-23} = 0b10;
2369 def SRSDB_UPD : SRSI<1, "srsdb\tsp!, $mode"> {
2370 let Inst{24-23} = 0b10;
2372 def SRSIA : SRSI<0, "srsia\tsp, $mode"> {
2373 let Inst{24-23} = 0b01;
2375 def SRSIA_UPD : SRSI<1, "srsia\tsp!, $mode"> {
2376 let Inst{24-23} = 0b01;
2378 def SRSIB : SRSI<0, "srsib\tsp, $mode"> {
2379 let Inst{24-23} = 0b11;
2381 def SRSIB_UPD : SRSI<1, "srsib\tsp!, $mode"> {
2382 let Inst{24-23} = 0b11;
2385 def : ARMInstAlias<"srsda $mode", (SRSDA imm0_31:$mode)>;
2386 def : ARMInstAlias<"srsda $mode!", (SRSDA_UPD imm0_31:$mode)>;
2388 def : ARMInstAlias<"srsdb $mode", (SRSDB imm0_31:$mode)>;
2389 def : ARMInstAlias<"srsdb $mode!", (SRSDB_UPD imm0_31:$mode)>;
2391 def : ARMInstAlias<"srsia $mode", (SRSIA imm0_31:$mode)>;
2392 def : ARMInstAlias<"srsia $mode!", (SRSIA_UPD imm0_31:$mode)>;
2394 def : ARMInstAlias<"srsib $mode", (SRSIB imm0_31:$mode)>;
2395 def : ARMInstAlias<"srsib $mode!", (SRSIB_UPD imm0_31:$mode)>;
2397 // Return From Exception
2398 class RFEI<bit wb, string asm>
2399 : XI<(outs), (ins GPR:$Rn), AddrModeNone, 4, IndexModeNone, BrFrm,
2400 NoItinerary, asm, "", []> {
2402 let Inst{31-28} = 0b1111;
2403 let Inst{27-25} = 0b100;
2407 let Inst{19-16} = Rn;
2408 let Inst{15-0} = 0xa00;
2411 def RFEDA : RFEI<0, "rfeda\t$Rn"> {
2412 let Inst{24-23} = 0;
2414 def RFEDA_UPD : RFEI<1, "rfeda\t$Rn!"> {
2415 let Inst{24-23} = 0;
2417 def RFEDB : RFEI<0, "rfedb\t$Rn"> {
2418 let Inst{24-23} = 0b10;
2420 def RFEDB_UPD : RFEI<1, "rfedb\t$Rn!"> {
2421 let Inst{24-23} = 0b10;
2423 def RFEIA : RFEI<0, "rfeia\t$Rn"> {
2424 let Inst{24-23} = 0b01;
2426 def RFEIA_UPD : RFEI<1, "rfeia\t$Rn!"> {
2427 let Inst{24-23} = 0b01;
2429 def RFEIB : RFEI<0, "rfeib\t$Rn"> {
2430 let Inst{24-23} = 0b11;
2432 def RFEIB_UPD : RFEI<1, "rfeib\t$Rn!"> {
2433 let Inst{24-23} = 0b11;
2436 // Hypervisor Call is a system instruction
2438 def HVC : AInoP< (outs), (ins imm0_65535:$imm), BrFrm, NoItinerary,
2439 "hvc", "\t$imm", []>,
2440 Requires<[IsARM, HasVirtualization]> {
2443 // Even though HVC isn't predicable, it's encoding includes a condition field.
2444 // The instruction is undefined if the condition field is 0xf otherwise it is
2445 // unpredictable if it isn't condition AL (0xe).
2446 let Inst{31-28} = 0b1110;
2447 let Unpredictable{31-28} = 0b1111;
2448 let Inst{27-24} = 0b0001;
2449 let Inst{23-20} = 0b0100;
2450 let Inst{19-8} = imm{15-4};
2451 let Inst{7-4} = 0b0111;
2452 let Inst{3-0} = imm{3-0};
2456 // Return from exception in Hypervisor mode.
2457 let isReturn = 1, isBarrier = 1, isTerminator = 1, Defs = [PC] in
2458 def ERET : ABI<0b0001, (outs), (ins), NoItinerary, "eret", "", []>,
2459 Requires<[IsARM, HasVirtualization]> {
2460 let Inst{23-0} = 0b011000000000000001101110;
2463 //===----------------------------------------------------------------------===//
2464 // Load / Store Instructions.
2470 defm LDR : AI_ldr1<0, "ldr", IIC_iLoad_r, IIC_iLoad_si,
2471 UnOpFrag<(load node:$Src)>>;
2472 defm LDRB : AI_ldr1nopc<1, "ldrb", IIC_iLoad_bh_r, IIC_iLoad_bh_si,
2473 UnOpFrag<(zextloadi8 node:$Src)>>;
2474 defm STR : AI_str1<0, "str", IIC_iStore_r, IIC_iStore_si,
2475 BinOpFrag<(store node:$LHS, node:$RHS)>>;
2476 defm STRB : AI_str1nopc<1, "strb", IIC_iStore_bh_r, IIC_iStore_bh_si,
2477 BinOpFrag<(truncstorei8 node:$LHS, node:$RHS)>>;
2479 // Special LDR for loads from non-pc-relative constpools.
2480 let canFoldAsLoad = 1, mayLoad = 1, hasSideEffects = 0,
2481 isReMaterializable = 1, isCodeGenOnly = 1 in
2482 def LDRcp : AI2ldst<0b010, 1, 0, (outs GPR:$Rt), (ins addrmode_imm12:$addr),
2483 AddrMode_i12, LdFrm, IIC_iLoad_r, "ldr", "\t$Rt, $addr",
2487 let Inst{23} = addr{12}; // U (add = ('U' == 1))
2488 let Inst{19-16} = 0b1111;
2489 let Inst{15-12} = Rt;
2490 let Inst{11-0} = addr{11-0}; // imm12
2493 // Loads with zero extension
2494 def LDRH : AI3ld<0b1011, 1, (outs GPR:$Rt), (ins addrmode3:$addr), LdMiscFrm,
2495 IIC_iLoad_bh_r, "ldrh", "\t$Rt, $addr",
2496 [(set GPR:$Rt, (zextloadi16 addrmode3:$addr))]>;
2498 // Loads with sign extension
2499 def LDRSH : AI3ld<0b1111, 1, (outs GPR:$Rt), (ins addrmode3:$addr), LdMiscFrm,
2500 IIC_iLoad_bh_r, "ldrsh", "\t$Rt, $addr",
2501 [(set GPR:$Rt, (sextloadi16 addrmode3:$addr))]>;
2503 def LDRSB : AI3ld<0b1101, 1, (outs GPR:$Rt), (ins addrmode3:$addr), LdMiscFrm,
2504 IIC_iLoad_bh_r, "ldrsb", "\t$Rt, $addr",
2505 [(set GPR:$Rt, (sextloadi8 addrmode3:$addr))]>;
2507 let mayLoad = 1, hasSideEffects = 0, hasExtraDefRegAllocReq = 1 in {
2509 def LDRD : AI3ld<0b1101, 0, (outs GPR:$Rt, GPR:$Rt2), (ins addrmode3:$addr),
2510 LdMiscFrm, IIC_iLoad_d_r, "ldrd", "\t$Rt, $Rt2, $addr", []>,
2511 Requires<[IsARM, HasV5TE]>;
2514 def LDA : AIldracq<0b00, (outs GPR:$Rt), (ins addr_offset_none:$addr),
2515 NoItinerary, "lda", "\t$Rt, $addr", []>;
2516 def LDAB : AIldracq<0b10, (outs GPR:$Rt), (ins addr_offset_none:$addr),
2517 NoItinerary, "ldab", "\t$Rt, $addr", []>;
2518 def LDAH : AIldracq<0b11, (outs GPR:$Rt), (ins addr_offset_none:$addr),
2519 NoItinerary, "ldah", "\t$Rt, $addr", []>;
2522 multiclass AI2_ldridx<bit isByte, string opc,
2523 InstrItinClass iii, InstrItinClass iir> {
2524 def _PRE_IMM : AI2ldstidx<1, isByte, 1, (outs GPR:$Rt, GPR:$Rn_wb),
2525 (ins addrmode_imm12_pre:$addr), IndexModePre, LdFrm, iii,
2526 opc, "\t$Rt, $addr!", "$addr.base = $Rn_wb", []> {
2529 let Inst{23} = addr{12};
2530 let Inst{19-16} = addr{16-13};
2531 let Inst{11-0} = addr{11-0};
2532 let DecoderMethod = "DecodeLDRPreImm";
2535 def _PRE_REG : AI2ldstidx<1, isByte, 1, (outs GPR:$Rt, GPR:$Rn_wb),
2536 (ins ldst_so_reg:$addr), IndexModePre, LdFrm, iir,
2537 opc, "\t$Rt, $addr!", "$addr.base = $Rn_wb", []> {
2540 let Inst{23} = addr{12};
2541 let Inst{19-16} = addr{16-13};
2542 let Inst{11-0} = addr{11-0};
2544 let DecoderMethod = "DecodeLDRPreReg";
2547 def _POST_REG : AI2ldstidx<1, isByte, 0, (outs GPR:$Rt, GPR:$Rn_wb),
2548 (ins addr_offset_none:$addr, am2offset_reg:$offset),
2549 IndexModePost, LdFrm, iir,
2550 opc, "\t$Rt, $addr, $offset",
2551 "$addr.base = $Rn_wb", []> {
2557 let Inst{23} = offset{12};
2558 let Inst{19-16} = addr;
2559 let Inst{11-0} = offset{11-0};
2562 let DecoderMethod = "DecodeAddrMode2IdxInstruction";
2565 def _POST_IMM : AI2ldstidx<1, isByte, 0, (outs GPR:$Rt, GPR:$Rn_wb),
2566 (ins addr_offset_none:$addr, am2offset_imm:$offset),
2567 IndexModePost, LdFrm, iii,
2568 opc, "\t$Rt, $addr, $offset",
2569 "$addr.base = $Rn_wb", []> {
2575 let Inst{23} = offset{12};
2576 let Inst{19-16} = addr;
2577 let Inst{11-0} = offset{11-0};
2579 let DecoderMethod = "DecodeAddrMode2IdxInstruction";
2584 let mayLoad = 1, hasSideEffects = 0 in {
2585 // FIXME: for LDR_PRE_REG etc. the itineray should be either IIC_iLoad_ru or
2586 // IIC_iLoad_siu depending on whether it the offset register is shifted.
2587 defm LDR : AI2_ldridx<0, "ldr", IIC_iLoad_iu, IIC_iLoad_ru>;
2588 defm LDRB : AI2_ldridx<1, "ldrb", IIC_iLoad_bh_iu, IIC_iLoad_bh_ru>;
2591 multiclass AI3_ldridx<bits<4> op, string opc, InstrItinClass itin> {
2592 def _PRE : AI3ldstidx<op, 1, 1, (outs GPR:$Rt, GPR:$Rn_wb),
2593 (ins addrmode3_pre:$addr), IndexModePre,
2595 opc, "\t$Rt, $addr!", "$addr.base = $Rn_wb", []> {
2597 let Inst{23} = addr{8}; // U bit
2598 let Inst{22} = addr{13}; // 1 == imm8, 0 == Rm
2599 let Inst{19-16} = addr{12-9}; // Rn
2600 let Inst{11-8} = addr{7-4}; // imm7_4/zero
2601 let Inst{3-0} = addr{3-0}; // imm3_0/Rm
2602 let DecoderMethod = "DecodeAddrMode3Instruction";
2604 def _POST : AI3ldstidx<op, 1, 0, (outs GPR:$Rt, GPR:$Rn_wb),
2605 (ins addr_offset_none:$addr, am3offset:$offset),
2606 IndexModePost, LdMiscFrm, itin,
2607 opc, "\t$Rt, $addr, $offset", "$addr.base = $Rn_wb",
2611 let Inst{23} = offset{8}; // U bit
2612 let Inst{22} = offset{9}; // 1 == imm8, 0 == Rm
2613 let Inst{19-16} = addr;
2614 let Inst{11-8} = offset{7-4}; // imm7_4/zero
2615 let Inst{3-0} = offset{3-0}; // imm3_0/Rm
2616 let DecoderMethod = "DecodeAddrMode3Instruction";
2620 let mayLoad = 1, hasSideEffects = 0 in {
2621 defm LDRH : AI3_ldridx<0b1011, "ldrh", IIC_iLoad_bh_ru>;
2622 defm LDRSH : AI3_ldridx<0b1111, "ldrsh", IIC_iLoad_bh_ru>;
2623 defm LDRSB : AI3_ldridx<0b1101, "ldrsb", IIC_iLoad_bh_ru>;
2624 let hasExtraDefRegAllocReq = 1 in {
2625 def LDRD_PRE : AI3ldstidx<0b1101, 0, 1, (outs GPR:$Rt, GPR:$Rt2, GPR:$Rn_wb),
2626 (ins addrmode3_pre:$addr), IndexModePre,
2627 LdMiscFrm, IIC_iLoad_d_ru,
2628 "ldrd", "\t$Rt, $Rt2, $addr!",
2629 "$addr.base = $Rn_wb", []> {
2631 let Inst{23} = addr{8}; // U bit
2632 let Inst{22} = addr{13}; // 1 == imm8, 0 == Rm
2633 let Inst{19-16} = addr{12-9}; // Rn
2634 let Inst{11-8} = addr{7-4}; // imm7_4/zero
2635 let Inst{3-0} = addr{3-0}; // imm3_0/Rm
2636 let DecoderMethod = "DecodeAddrMode3Instruction";
2638 def LDRD_POST: AI3ldstidx<0b1101, 0, 0, (outs GPR:$Rt, GPR:$Rt2, GPR:$Rn_wb),
2639 (ins addr_offset_none:$addr, am3offset:$offset),
2640 IndexModePost, LdMiscFrm, IIC_iLoad_d_ru,
2641 "ldrd", "\t$Rt, $Rt2, $addr, $offset",
2642 "$addr.base = $Rn_wb", []> {
2645 let Inst{23} = offset{8}; // U bit
2646 let Inst{22} = offset{9}; // 1 == imm8, 0 == Rm
2647 let Inst{19-16} = addr;
2648 let Inst{11-8} = offset{7-4}; // imm7_4/zero
2649 let Inst{3-0} = offset{3-0}; // imm3_0/Rm
2650 let DecoderMethod = "DecodeAddrMode3Instruction";
2652 } // hasExtraDefRegAllocReq = 1
2653 } // mayLoad = 1, hasSideEffects = 0
2655 // LDRT, LDRBT, LDRSBT, LDRHT, LDRSHT.
2656 let mayLoad = 1, hasSideEffects = 0 in {
2657 def LDRT_POST_REG : AI2ldstidx<1, 0, 0, (outs GPR:$Rt, GPR:$Rn_wb),
2658 (ins addr_offset_none:$addr, am2offset_reg:$offset),
2659 IndexModePost, LdFrm, IIC_iLoad_ru,
2660 "ldrt", "\t$Rt, $addr, $offset",
2661 "$addr.base = $Rn_wb", []> {
2667 let Inst{23} = offset{12};
2668 let Inst{21} = 1; // overwrite
2669 let Inst{19-16} = addr;
2670 let Inst{11-5} = offset{11-5};
2672 let Inst{3-0} = offset{3-0};
2673 let DecoderMethod = "DecodeAddrMode2IdxInstruction";
2677 : AI2ldstidx<1, 0, 0, (outs GPR:$Rt, GPR:$Rn_wb),
2678 (ins addr_offset_none:$addr, am2offset_imm:$offset),
2679 IndexModePost, LdFrm, IIC_iLoad_ru,
2680 "ldrt", "\t$Rt, $addr, $offset", "$addr.base = $Rn_wb", []> {
2686 let Inst{23} = offset{12};
2687 let Inst{21} = 1; // overwrite
2688 let Inst{19-16} = addr;
2689 let Inst{11-0} = offset{11-0};
2690 let DecoderMethod = "DecodeAddrMode2IdxInstruction";
2693 def LDRBT_POST_REG : AI2ldstidx<1, 1, 0, (outs GPR:$Rt, GPR:$Rn_wb),
2694 (ins addr_offset_none:$addr, am2offset_reg:$offset),
2695 IndexModePost, LdFrm, IIC_iLoad_bh_ru,
2696 "ldrbt", "\t$Rt, $addr, $offset",
2697 "$addr.base = $Rn_wb", []> {
2703 let Inst{23} = offset{12};
2704 let Inst{21} = 1; // overwrite
2705 let Inst{19-16} = addr;
2706 let Inst{11-5} = offset{11-5};
2708 let Inst{3-0} = offset{3-0};
2709 let DecoderMethod = "DecodeAddrMode2IdxInstruction";
2713 : AI2ldstidx<1, 1, 0, (outs GPR:$Rt, GPR:$Rn_wb),
2714 (ins addr_offset_none:$addr, am2offset_imm:$offset),
2715 IndexModePost, LdFrm, IIC_iLoad_bh_ru,
2716 "ldrbt", "\t$Rt, $addr, $offset", "$addr.base = $Rn_wb", []> {
2722 let Inst{23} = offset{12};
2723 let Inst{21} = 1; // overwrite
2724 let Inst{19-16} = addr;
2725 let Inst{11-0} = offset{11-0};
2726 let DecoderMethod = "DecodeAddrMode2IdxInstruction";
2729 multiclass AI3ldrT<bits<4> op, string opc> {
2730 def i : AI3ldstidxT<op, 1, (outs GPR:$Rt, GPR:$base_wb),
2731 (ins addr_offset_none:$addr, postidx_imm8:$offset),
2732 IndexModePost, LdMiscFrm, IIC_iLoad_bh_ru, opc,
2733 "\t$Rt, $addr, $offset", "$addr.base = $base_wb", []> {
2735 let Inst{23} = offset{8};
2737 let Inst{11-8} = offset{7-4};
2738 let Inst{3-0} = offset{3-0};
2740 def r : AI3ldstidxT<op, 1, (outs GPRnopc:$Rt, GPRnopc:$base_wb),
2741 (ins addr_offset_none:$addr, postidx_reg:$Rm),
2742 IndexModePost, LdMiscFrm, IIC_iLoad_bh_ru, opc,
2743 "\t$Rt, $addr, $Rm", "$addr.base = $base_wb", []> {
2745 let Inst{23} = Rm{4};
2748 let Unpredictable{11-8} = 0b1111;
2749 let Inst{3-0} = Rm{3-0};
2750 let DecoderMethod = "DecodeLDR";
2754 defm LDRSBT : AI3ldrT<0b1101, "ldrsbt">;
2755 defm LDRHT : AI3ldrT<0b1011, "ldrht">;
2756 defm LDRSHT : AI3ldrT<0b1111, "ldrsht">;
2760 : ARMAsmPseudo<"ldrt${q} $Rt, $addr", (ins addr_offset_none:$addr, pred:$q),
2764 : ARMAsmPseudo<"ldrbt${q} $Rt, $addr", (ins addr_offset_none:$addr, pred:$q),
2769 // Stores with truncate
2770 def STRH : AI3str<0b1011, (outs), (ins GPR:$Rt, addrmode3:$addr), StMiscFrm,
2771 IIC_iStore_bh_r, "strh", "\t$Rt, $addr",
2772 [(truncstorei16 GPR:$Rt, addrmode3:$addr)]>;
2775 let mayStore = 1, hasSideEffects = 0, hasExtraSrcRegAllocReq = 1 in {
2776 def STRD : AI3str<0b1111, (outs), (ins GPR:$Rt, GPR:$Rt2, addrmode3:$addr),
2777 StMiscFrm, IIC_iStore_d_r, "strd", "\t$Rt, $Rt2, $addr", []>,
2778 Requires<[IsARM, HasV5TE]> {
2784 multiclass AI2_stridx<bit isByte, string opc,
2785 InstrItinClass iii, InstrItinClass iir> {
2786 def _PRE_IMM : AI2ldstidx<0, isByte, 1, (outs GPR:$Rn_wb),
2787 (ins GPR:$Rt, addrmode_imm12_pre:$addr), IndexModePre,
2789 opc, "\t$Rt, $addr!",
2790 "$addr.base = $Rn_wb,@earlyclobber $Rn_wb", []> {
2793 let Inst{23} = addr{12}; // U (add = ('U' == 1))
2794 let Inst{19-16} = addr{16-13}; // Rn
2795 let Inst{11-0} = addr{11-0}; // imm12
2796 let DecoderMethod = "DecodeSTRPreImm";
2799 def _PRE_REG : AI2ldstidx<0, isByte, 1, (outs GPR:$Rn_wb),
2800 (ins GPR:$Rt, ldst_so_reg:$addr),
2801 IndexModePre, StFrm, iir,
2802 opc, "\t$Rt, $addr!",
2803 "$addr.base = $Rn_wb,@earlyclobber $Rn_wb", []> {
2806 let Inst{23} = addr{12}; // U (add = ('U' == 1))
2807 let Inst{19-16} = addr{16-13}; // Rn
2808 let Inst{11-0} = addr{11-0};
2809 let Inst{4} = 0; // Inst{4} = 0
2810 let DecoderMethod = "DecodeSTRPreReg";
2812 def _POST_REG : AI2ldstidx<0, isByte, 0, (outs GPR:$Rn_wb),
2813 (ins GPR:$Rt, addr_offset_none:$addr, am2offset_reg:$offset),
2814 IndexModePost, StFrm, iir,
2815 opc, "\t$Rt, $addr, $offset",
2816 "$addr.base = $Rn_wb,@earlyclobber $Rn_wb", []> {
2822 let Inst{23} = offset{12};
2823 let Inst{19-16} = addr;
2824 let Inst{11-0} = offset{11-0};
2827 let DecoderMethod = "DecodeAddrMode2IdxInstruction";
2830 def _POST_IMM : AI2ldstidx<0, isByte, 0, (outs GPR:$Rn_wb),
2831 (ins GPR:$Rt, addr_offset_none:$addr, am2offset_imm:$offset),
2832 IndexModePost, StFrm, iii,
2833 opc, "\t$Rt, $addr, $offset",
2834 "$addr.base = $Rn_wb,@earlyclobber $Rn_wb", []> {
2840 let Inst{23} = offset{12};
2841 let Inst{19-16} = addr;
2842 let Inst{11-0} = offset{11-0};
2844 let DecoderMethod = "DecodeAddrMode2IdxInstruction";
2848 let mayStore = 1, hasSideEffects = 0 in {
2849 // FIXME: for STR_PRE_REG etc. the itineray should be either IIC_iStore_ru or
2850 // IIC_iStore_siu depending on whether it the offset register is shifted.
2851 defm STR : AI2_stridx<0, "str", IIC_iStore_iu, IIC_iStore_ru>;
2852 defm STRB : AI2_stridx<1, "strb", IIC_iStore_bh_iu, IIC_iStore_bh_ru>;
2855 def : ARMPat<(post_store GPR:$Rt, addr_offset_none:$addr,
2856 am2offset_reg:$offset),
2857 (STR_POST_REG GPR:$Rt, addr_offset_none:$addr,
2858 am2offset_reg:$offset)>;
2859 def : ARMPat<(post_store GPR:$Rt, addr_offset_none:$addr,
2860 am2offset_imm:$offset),
2861 (STR_POST_IMM GPR:$Rt, addr_offset_none:$addr,
2862 am2offset_imm:$offset)>;
2863 def : ARMPat<(post_truncsti8 GPR:$Rt, addr_offset_none:$addr,
2864 am2offset_reg:$offset),
2865 (STRB_POST_REG GPR:$Rt, addr_offset_none:$addr,
2866 am2offset_reg:$offset)>;
2867 def : ARMPat<(post_truncsti8 GPR:$Rt, addr_offset_none:$addr,
2868 am2offset_imm:$offset),
2869 (STRB_POST_IMM GPR:$Rt, addr_offset_none:$addr,
2870 am2offset_imm:$offset)>;
2872 // Pseudo-instructions for pattern matching the pre-indexed stores. We can't
2873 // put the patterns on the instruction definitions directly as ISel wants
2874 // the address base and offset to be separate operands, not a single
2875 // complex operand like we represent the instructions themselves. The
2876 // pseudos map between the two.
2877 let usesCustomInserter = 1,
2878 Constraints = "$Rn = $Rn_wb,@earlyclobber $Rn_wb" in {
2879 def STRi_preidx: ARMPseudoInst<(outs GPR:$Rn_wb),
2880 (ins GPR:$Rt, GPR:$Rn, am2offset_imm:$offset, pred:$p),
2883 (pre_store GPR:$Rt, GPR:$Rn, am2offset_imm:$offset))]>;
2884 def STRr_preidx: ARMPseudoInst<(outs GPR:$Rn_wb),
2885 (ins GPR:$Rt, GPR:$Rn, am2offset_reg:$offset, pred:$p),
2888 (pre_store GPR:$Rt, GPR:$Rn, am2offset_reg:$offset))]>;
2889 def STRBi_preidx: ARMPseudoInst<(outs GPR:$Rn_wb),
2890 (ins GPR:$Rt, GPR:$Rn, am2offset_imm:$offset, pred:$p),
2893 (pre_truncsti8 GPR:$Rt, GPR:$Rn, am2offset_imm:$offset))]>;
2894 def STRBr_preidx: ARMPseudoInst<(outs GPR:$Rn_wb),
2895 (ins GPR:$Rt, GPR:$Rn, am2offset_reg:$offset, pred:$p),
2898 (pre_truncsti8 GPR:$Rt, GPR:$Rn, am2offset_reg:$offset))]>;
2899 def STRH_preidx: ARMPseudoInst<(outs GPR:$Rn_wb),
2900 (ins GPR:$Rt, GPR:$Rn, am3offset:$offset, pred:$p),
2903 (pre_truncsti16 GPR:$Rt, GPR:$Rn, am3offset:$offset))]>;
2908 def STRH_PRE : AI3ldstidx<0b1011, 0, 1, (outs GPR:$Rn_wb),
2909 (ins GPR:$Rt, addrmode3_pre:$addr), IndexModePre,
2910 StMiscFrm, IIC_iStore_bh_ru,
2911 "strh", "\t$Rt, $addr!",
2912 "$addr.base = $Rn_wb,@earlyclobber $Rn_wb", []> {
2914 let Inst{23} = addr{8}; // U bit
2915 let Inst{22} = addr{13}; // 1 == imm8, 0 == Rm
2916 let Inst{19-16} = addr{12-9}; // Rn
2917 let Inst{11-8} = addr{7-4}; // imm7_4/zero
2918 let Inst{3-0} = addr{3-0}; // imm3_0/Rm
2919 let DecoderMethod = "DecodeAddrMode3Instruction";
2922 def STRH_POST : AI3ldstidx<0b1011, 0, 0, (outs GPR:$Rn_wb),
2923 (ins GPR:$Rt, addr_offset_none:$addr, am3offset:$offset),
2924 IndexModePost, StMiscFrm, IIC_iStore_bh_ru,
2925 "strh", "\t$Rt, $addr, $offset",
2926 "$addr.base = $Rn_wb,@earlyclobber $Rn_wb",
2927 [(set GPR:$Rn_wb, (post_truncsti16 GPR:$Rt,
2928 addr_offset_none:$addr,
2929 am3offset:$offset))]> {
2932 let Inst{23} = offset{8}; // U bit
2933 let Inst{22} = offset{9}; // 1 == imm8, 0 == Rm
2934 let Inst{19-16} = addr;
2935 let Inst{11-8} = offset{7-4}; // imm7_4/zero
2936 let Inst{3-0} = offset{3-0}; // imm3_0/Rm
2937 let DecoderMethod = "DecodeAddrMode3Instruction";
2940 let mayStore = 1, hasSideEffects = 0, hasExtraSrcRegAllocReq = 1 in {
2941 def STRD_PRE : AI3ldstidx<0b1111, 0, 1, (outs GPR:$Rn_wb),
2942 (ins GPR:$Rt, GPR:$Rt2, addrmode3_pre:$addr),
2943 IndexModePre, StMiscFrm, IIC_iStore_d_ru,
2944 "strd", "\t$Rt, $Rt2, $addr!",
2945 "$addr.base = $Rn_wb", []> {
2947 let Inst{23} = addr{8}; // U bit
2948 let Inst{22} = addr{13}; // 1 == imm8, 0 == Rm
2949 let Inst{19-16} = addr{12-9}; // Rn
2950 let Inst{11-8} = addr{7-4}; // imm7_4/zero
2951 let Inst{3-0} = addr{3-0}; // imm3_0/Rm
2952 let DecoderMethod = "DecodeAddrMode3Instruction";
2955 def STRD_POST: AI3ldstidx<0b1111, 0, 0, (outs GPR:$Rn_wb),
2956 (ins GPR:$Rt, GPR:$Rt2, addr_offset_none:$addr,
2958 IndexModePost, StMiscFrm, IIC_iStore_d_ru,
2959 "strd", "\t$Rt, $Rt2, $addr, $offset",
2960 "$addr.base = $Rn_wb", []> {
2963 let Inst{23} = offset{8}; // U bit
2964 let Inst{22} = offset{9}; // 1 == imm8, 0 == Rm
2965 let Inst{19-16} = addr;
2966 let Inst{11-8} = offset{7-4}; // imm7_4/zero
2967 let Inst{3-0} = offset{3-0}; // imm3_0/Rm
2968 let DecoderMethod = "DecodeAddrMode3Instruction";
2970 } // mayStore = 1, hasSideEffects = 0, hasExtraSrcRegAllocReq = 1
2972 // STRT, STRBT, and STRHT
2974 def STRBT_POST_REG : AI2ldstidx<0, 1, 0, (outs GPR:$Rn_wb),
2975 (ins GPR:$Rt, addr_offset_none:$addr, am2offset_reg:$offset),
2976 IndexModePost, StFrm, IIC_iStore_bh_ru,
2977 "strbt", "\t$Rt, $addr, $offset",
2978 "$addr.base = $Rn_wb", []> {
2984 let Inst{23} = offset{12};
2985 let Inst{21} = 1; // overwrite
2986 let Inst{19-16} = addr;
2987 let Inst{11-5} = offset{11-5};
2989 let Inst{3-0} = offset{3-0};
2990 let DecoderMethod = "DecodeAddrMode2IdxInstruction";
2994 : AI2ldstidx<0, 1, 0, (outs GPR:$Rn_wb),
2995 (ins GPR:$Rt, addr_offset_none:$addr, am2offset_imm:$offset),
2996 IndexModePost, StFrm, IIC_iStore_bh_ru,
2997 "strbt", "\t$Rt, $addr, $offset", "$addr.base = $Rn_wb", []> {
3003 let Inst{23} = offset{12};
3004 let Inst{21} = 1; // overwrite
3005 let Inst{19-16} = addr;
3006 let Inst{11-0} = offset{11-0};
3007 let DecoderMethod = "DecodeAddrMode2IdxInstruction";
3011 : ARMAsmPseudo<"strbt${q} $Rt, $addr",
3012 (ins GPR:$Rt, addr_offset_none:$addr, pred:$q)>;
3014 let mayStore = 1, hasSideEffects = 0 in {
3015 def STRT_POST_REG : AI2ldstidx<0, 0, 0, (outs GPR:$Rn_wb),
3016 (ins GPR:$Rt, addr_offset_none:$addr, am2offset_reg:$offset),
3017 IndexModePost, StFrm, IIC_iStore_ru,
3018 "strt", "\t$Rt, $addr, $offset",
3019 "$addr.base = $Rn_wb", []> {
3025 let Inst{23} = offset{12};
3026 let Inst{21} = 1; // overwrite
3027 let Inst{19-16} = addr;
3028 let Inst{11-5} = offset{11-5};
3030 let Inst{3-0} = offset{3-0};
3031 let DecoderMethod = "DecodeAddrMode2IdxInstruction";
3035 : AI2ldstidx<0, 0, 0, (outs GPR:$Rn_wb),
3036 (ins GPR:$Rt, addr_offset_none:$addr, am2offset_imm:$offset),
3037 IndexModePost, StFrm, IIC_iStore_ru,
3038 "strt", "\t$Rt, $addr, $offset", "$addr.base = $Rn_wb", []> {
3044 let Inst{23} = offset{12};
3045 let Inst{21} = 1; // overwrite
3046 let Inst{19-16} = addr;
3047 let Inst{11-0} = offset{11-0};
3048 let DecoderMethod = "DecodeAddrMode2IdxInstruction";
3053 : ARMAsmPseudo<"strt${q} $Rt, $addr",
3054 (ins GPR:$Rt, addr_offset_none:$addr, pred:$q)>;
3056 multiclass AI3strT<bits<4> op, string opc> {
3057 def i : AI3ldstidxT<op, 0, (outs GPR:$base_wb),
3058 (ins GPR:$Rt, addr_offset_none:$addr, postidx_imm8:$offset),
3059 IndexModePost, StMiscFrm, IIC_iStore_bh_ru, opc,
3060 "\t$Rt, $addr, $offset", "$addr.base = $base_wb", []> {
3062 let Inst{23} = offset{8};
3064 let Inst{11-8} = offset{7-4};
3065 let Inst{3-0} = offset{3-0};
3067 def r : AI3ldstidxT<op, 0, (outs GPR:$base_wb),
3068 (ins GPR:$Rt, addr_offset_none:$addr, postidx_reg:$Rm),
3069 IndexModePost, StMiscFrm, IIC_iStore_bh_ru, opc,
3070 "\t$Rt, $addr, $Rm", "$addr.base = $base_wb", []> {
3072 let Inst{23} = Rm{4};
3075 let Inst{3-0} = Rm{3-0};
3080 defm STRHT : AI3strT<0b1011, "strht">;
3082 def STL : AIstrrel<0b00, (outs), (ins GPR:$Rt, addr_offset_none:$addr),
3083 NoItinerary, "stl", "\t$Rt, $addr", []>;
3084 def STLB : AIstrrel<0b10, (outs), (ins GPR:$Rt, addr_offset_none:$addr),
3085 NoItinerary, "stlb", "\t$Rt, $addr", []>;
3086 def STLH : AIstrrel<0b11, (outs), (ins GPR:$Rt, addr_offset_none:$addr),
3087 NoItinerary, "stlh", "\t$Rt, $addr", []>;
3089 //===----------------------------------------------------------------------===//
3090 // Load / store multiple Instructions.
3093 multiclass arm_ldst_mult<string asm, string sfx, bit L_bit, bit P_bit, Format f,
3094 InstrItinClass itin, InstrItinClass itin_upd> {
3095 // IA is the default, so no need for an explicit suffix on the
3096 // mnemonic here. Without it is the canonical spelling.
3098 AXI4<(outs), (ins GPR:$Rn, pred:$p, reglist:$regs, variable_ops),
3099 IndexModeNone, f, itin,
3100 !strconcat(asm, "${p}\t$Rn, $regs", sfx), "", []> {
3101 let Inst{24-23} = 0b01; // Increment After
3102 let Inst{22} = P_bit;
3103 let Inst{21} = 0; // No writeback
3104 let Inst{20} = L_bit;
3107 AXI4<(outs GPR:$wb), (ins GPR:$Rn, pred:$p, reglist:$regs, variable_ops),
3108 IndexModeUpd, f, itin_upd,
3109 !strconcat(asm, "${p}\t$Rn!, $regs", sfx), "$Rn = $wb", []> {
3110 let Inst{24-23} = 0b01; // Increment After
3111 let Inst{22} = P_bit;
3112 let Inst{21} = 1; // Writeback
3113 let Inst{20} = L_bit;
3115 let DecoderMethod = "DecodeMemMultipleWritebackInstruction";
3118 AXI4<(outs), (ins GPR:$Rn, pred:$p, reglist:$regs, variable_ops),
3119 IndexModeNone, f, itin,
3120 !strconcat(asm, "da${p}\t$Rn, $regs", sfx), "", []> {
3121 let Inst{24-23} = 0b00; // Decrement After
3122 let Inst{22} = P_bit;
3123 let Inst{21} = 0; // No writeback
3124 let Inst{20} = L_bit;
3127 AXI4<(outs GPR:$wb), (ins GPR:$Rn, pred:$p, reglist:$regs, variable_ops),
3128 IndexModeUpd, f, itin_upd,
3129 !strconcat(asm, "da${p}\t$Rn!, $regs", sfx), "$Rn = $wb", []> {
3130 let Inst{24-23} = 0b00; // Decrement After
3131 let Inst{22} = P_bit;
3132 let Inst{21} = 1; // Writeback
3133 let Inst{20} = L_bit;
3135 let DecoderMethod = "DecodeMemMultipleWritebackInstruction";
3138 AXI4<(outs), (ins GPR:$Rn, pred:$p, reglist:$regs, variable_ops),
3139 IndexModeNone, f, itin,
3140 !strconcat(asm, "db${p}\t$Rn, $regs", sfx), "", []> {
3141 let Inst{24-23} = 0b10; // Decrement Before
3142 let Inst{22} = P_bit;
3143 let Inst{21} = 0; // No writeback
3144 let Inst{20} = L_bit;
3147 AXI4<(outs GPR:$wb), (ins GPR:$Rn, pred:$p, reglist:$regs, variable_ops),
3148 IndexModeUpd, f, itin_upd,
3149 !strconcat(asm, "db${p}\t$Rn!, $regs", sfx), "$Rn = $wb", []> {
3150 let Inst{24-23} = 0b10; // Decrement Before
3151 let Inst{22} = P_bit;
3152 let Inst{21} = 1; // Writeback
3153 let Inst{20} = L_bit;
3155 let DecoderMethod = "DecodeMemMultipleWritebackInstruction";
3158 AXI4<(outs), (ins GPR:$Rn, pred:$p, reglist:$regs, variable_ops),
3159 IndexModeNone, f, itin,
3160 !strconcat(asm, "ib${p}\t$Rn, $regs", sfx), "", []> {
3161 let Inst{24-23} = 0b11; // Increment Before
3162 let Inst{22} = P_bit;
3163 let Inst{21} = 0; // No writeback
3164 let Inst{20} = L_bit;
3167 AXI4<(outs GPR:$wb), (ins GPR:$Rn, pred:$p, reglist:$regs, variable_ops),
3168 IndexModeUpd, f, itin_upd,
3169 !strconcat(asm, "ib${p}\t$Rn!, $regs", sfx), "$Rn = $wb", []> {
3170 let Inst{24-23} = 0b11; // Increment Before
3171 let Inst{22} = P_bit;
3172 let Inst{21} = 1; // Writeback
3173 let Inst{20} = L_bit;
3175 let DecoderMethod = "DecodeMemMultipleWritebackInstruction";
3179 let hasSideEffects = 0 in {
3181 let mayLoad = 1, hasExtraDefRegAllocReq = 1 in
3182 defm LDM : arm_ldst_mult<"ldm", "", 1, 0, LdStMulFrm, IIC_iLoad_m,
3183 IIC_iLoad_mu>, ComplexDeprecationPredicate<"ARMLoad">;
3185 let mayStore = 1, hasExtraSrcRegAllocReq = 1 in
3186 defm STM : arm_ldst_mult<"stm", "", 0, 0, LdStMulFrm, IIC_iStore_m,
3188 ComplexDeprecationPredicate<"ARMStore">;
3192 // FIXME: remove when we have a way to marking a MI with these properties.
3193 // FIXME: Should pc be an implicit operand like PICADD, etc?
3194 let isReturn = 1, isTerminator = 1, isBarrier = 1, mayLoad = 1,
3195 hasExtraDefRegAllocReq = 1, isCodeGenOnly = 1 in
3196 def LDMIA_RET : ARMPseudoExpand<(outs GPR:$wb), (ins GPR:$Rn, pred:$p,
3197 reglist:$regs, variable_ops),
3198 4, IIC_iLoad_mBr, [],
3199 (LDMIA_UPD GPR:$wb, GPR:$Rn, pred:$p, reglist:$regs)>,
3200 RegConstraint<"$Rn = $wb">;
3202 let mayLoad = 1, hasExtraDefRegAllocReq = 1 in
3203 defm sysLDM : arm_ldst_mult<"ldm", " ^", 1, 1, LdStMulFrm, IIC_iLoad_m,
3206 let mayStore = 1, hasExtraSrcRegAllocReq = 1 in
3207 defm sysSTM : arm_ldst_mult<"stm", " ^", 0, 1, LdStMulFrm, IIC_iStore_m,
3212 //===----------------------------------------------------------------------===//
3213 // Move Instructions.
3216 let hasSideEffects = 0 in
3217 def MOVr : AsI1<0b1101, (outs GPR:$Rd), (ins GPR:$Rm), DPFrm, IIC_iMOVr,
3218 "mov", "\t$Rd, $Rm", []>, UnaryDP, Sched<[WriteALU]> {
3222 let Inst{19-16} = 0b0000;
3223 let Inst{11-4} = 0b00000000;
3226 let Inst{15-12} = Rd;
3229 // A version for the smaller set of tail call registers.
3230 let hasSideEffects = 0 in
3231 def MOVr_TC : AsI1<0b1101, (outs tcGPR:$Rd), (ins tcGPR:$Rm), DPFrm,
3232 IIC_iMOVr, "mov", "\t$Rd, $Rm", []>, UnaryDP, Sched<[WriteALU]> {
3236 let Inst{11-4} = 0b00000000;
3239 let Inst{15-12} = Rd;
3242 def MOVsr : AsI1<0b1101, (outs GPRnopc:$Rd), (ins shift_so_reg_reg:$src),
3243 DPSoRegRegFrm, IIC_iMOVsr,
3244 "mov", "\t$Rd, $src",
3245 [(set GPRnopc:$Rd, shift_so_reg_reg:$src)]>, UnaryDP,
3249 let Inst{15-12} = Rd;
3250 let Inst{19-16} = 0b0000;
3251 let Inst{11-8} = src{11-8};
3253 let Inst{6-5} = src{6-5};
3255 let Inst{3-0} = src{3-0};
3259 def MOVsi : AsI1<0b1101, (outs GPR:$Rd), (ins shift_so_reg_imm:$src),
3260 DPSoRegImmFrm, IIC_iMOVsr,
3261 "mov", "\t$Rd, $src", [(set GPR:$Rd, shift_so_reg_imm:$src)]>,
3262 UnaryDP, Sched<[WriteALU]> {
3265 let Inst{15-12} = Rd;
3266 let Inst{19-16} = 0b0000;
3267 let Inst{11-5} = src{11-5};
3269 let Inst{3-0} = src{3-0};
3273 let isReMaterializable = 1, isAsCheapAsAMove = 1, isMoveImm = 1 in
3274 def MOVi : AsI1<0b1101, (outs GPR:$Rd), (ins mod_imm:$imm), DPFrm, IIC_iMOVi,
3275 "mov", "\t$Rd, $imm", [(set GPR:$Rd, mod_imm:$imm)]>, UnaryDP,
3280 let Inst{15-12} = Rd;
3281 let Inst{19-16} = 0b0000;
3282 let Inst{11-0} = imm;
3285 let isReMaterializable = 1, isAsCheapAsAMove = 1, isMoveImm = 1 in
3286 def MOVi16 : AI1<0b1000, (outs GPR:$Rd), (ins imm0_65535_expr:$imm),
3288 "movw", "\t$Rd, $imm",
3289 [(set GPR:$Rd, imm0_65535:$imm)]>,
3290 Requires<[IsARM, HasV6T2]>, UnaryDP, Sched<[WriteALU]> {
3293 let Inst{15-12} = Rd;
3294 let Inst{11-0} = imm{11-0};
3295 let Inst{19-16} = imm{15-12};
3298 let DecoderMethod = "DecodeArmMOVTWInstruction";
3301 def : InstAlias<"mov${p} $Rd, $imm",
3302 (MOVi16 GPR:$Rd, imm0_65535_expr:$imm, pred:$p)>,
3305 def MOVi16_ga_pcrel : PseudoInst<(outs GPR:$Rd),
3306 (ins i32imm:$addr, pclabel:$id), IIC_iMOVi, []>,
3309 let Constraints = "$src = $Rd" in {
3310 def MOVTi16 : AI1<0b1010, (outs GPRnopc:$Rd),
3311 (ins GPR:$src, imm0_65535_expr:$imm),
3313 "movt", "\t$Rd, $imm",
3315 (or (and GPR:$src, 0xffff),
3316 lo16AllZero:$imm))]>, UnaryDP,
3317 Requires<[IsARM, HasV6T2]>, Sched<[WriteALU]> {
3320 let Inst{15-12} = Rd;
3321 let Inst{11-0} = imm{11-0};
3322 let Inst{19-16} = imm{15-12};
3325 let DecoderMethod = "DecodeArmMOVTWInstruction";
3328 def MOVTi16_ga_pcrel : PseudoInst<(outs GPR:$Rd),
3329 (ins GPR:$src, i32imm:$addr, pclabel:$id), IIC_iMOVi, []>,
3334 def : ARMPat<(or GPR:$src, 0xffff0000), (MOVTi16 GPR:$src, 0xffff)>,
3335 Requires<[IsARM, HasV6T2]>;
3337 let Uses = [CPSR] in
3338 def RRX: PseudoInst<(outs GPR:$Rd), (ins GPR:$Rm), IIC_iMOVsi,
3339 [(set GPR:$Rd, (ARMrrx GPR:$Rm))]>, UnaryDP,
3340 Requires<[IsARM]>, Sched<[WriteALU]>;
3342 // These aren't really mov instructions, but we have to define them this way
3343 // due to flag operands.
3345 let Defs = [CPSR] in {
3346 def MOVsrl_flag : PseudoInst<(outs GPR:$dst), (ins GPR:$src), IIC_iMOVsi,
3347 [(set GPR:$dst, (ARMsrl_flag GPR:$src))]>, UnaryDP,
3348 Sched<[WriteALU]>, Requires<[IsARM]>;
3349 def MOVsra_flag : PseudoInst<(outs GPR:$dst), (ins GPR:$src), IIC_iMOVsi,
3350 [(set GPR:$dst, (ARMsra_flag GPR:$src))]>, UnaryDP,
3351 Sched<[WriteALU]>, Requires<[IsARM]>;
3354 //===----------------------------------------------------------------------===//
3355 // Extend Instructions.
3360 def SXTB : AI_ext_rrot<0b01101010,
3361 "sxtb", UnOpFrag<(sext_inreg node:$Src, i8)>>;
3362 def SXTH : AI_ext_rrot<0b01101011,
3363 "sxth", UnOpFrag<(sext_inreg node:$Src, i16)>>;
3365 def SXTAB : AI_exta_rrot<0b01101010,
3366 "sxtab", BinOpFrag<(add node:$LHS, (sext_inreg node:$RHS, i8))>>;
3367 def SXTAH : AI_exta_rrot<0b01101011,
3368 "sxtah", BinOpFrag<(add node:$LHS, (sext_inreg node:$RHS,i16))>>;
3370 def SXTB16 : AI_ext_rrot_np<0b01101000, "sxtb16">;
3372 def SXTAB16 : AI_exta_rrot_np<0b01101000, "sxtab16">;
3376 let AddedComplexity = 16 in {
3377 def UXTB : AI_ext_rrot<0b01101110,
3378 "uxtb" , UnOpFrag<(and node:$Src, 0x000000FF)>>;
3379 def UXTH : AI_ext_rrot<0b01101111,
3380 "uxth" , UnOpFrag<(and node:$Src, 0x0000FFFF)>>;
3381 def UXTB16 : AI_ext_rrot<0b01101100,
3382 "uxtb16", UnOpFrag<(and node:$Src, 0x00FF00FF)>>;
3384 // FIXME: This pattern incorrectly assumes the shl operator is a rotate.
3385 // The transformation should probably be done as a combiner action
3386 // instead so we can include a check for masking back in the upper
3387 // eight bits of the source into the lower eight bits of the result.
3388 //def : ARMV6Pat<(and (shl GPR:$Src, (i32 8)), 0xFF00FF),
3389 // (UXTB16r_rot GPR:$Src, 3)>;
3390 def : ARMV6Pat<(and (srl GPR:$Src, (i32 8)), 0xFF00FF),
3391 (UXTB16 GPR:$Src, 1)>;
3393 def UXTAB : AI_exta_rrot<0b01101110, "uxtab",
3394 BinOpFrag<(add node:$LHS, (and node:$RHS, 0x00FF))>>;
3395 def UXTAH : AI_exta_rrot<0b01101111, "uxtah",
3396 BinOpFrag<(add node:$LHS, (and node:$RHS, 0xFFFF))>>;
3399 // This isn't safe in general, the add is two 16-bit units, not a 32-bit add.
3400 def UXTAB16 : AI_exta_rrot_np<0b01101100, "uxtab16">;
3403 def SBFX : I<(outs GPRnopc:$Rd),
3404 (ins GPRnopc:$Rn, imm0_31:$lsb, imm1_32:$width),
3405 AddrMode1, 4, IndexModeNone, DPFrm, IIC_iUNAsi,
3406 "sbfx", "\t$Rd, $Rn, $lsb, $width", "", []>,
3407 Requires<[IsARM, HasV6T2]> {
3412 let Inst{27-21} = 0b0111101;
3413 let Inst{6-4} = 0b101;
3414 let Inst{20-16} = width;
3415 let Inst{15-12} = Rd;
3416 let Inst{11-7} = lsb;
3420 def UBFX : I<(outs GPRnopc:$Rd),
3421 (ins GPRnopc:$Rn, imm0_31:$lsb, imm1_32:$width),
3422 AddrMode1, 4, IndexModeNone, DPFrm, IIC_iUNAsi,
3423 "ubfx", "\t$Rd, $Rn, $lsb, $width", "", []>,
3424 Requires<[IsARM, HasV6T2]> {
3429 let Inst{27-21} = 0b0111111;
3430 let Inst{6-4} = 0b101;
3431 let Inst{20-16} = width;
3432 let Inst{15-12} = Rd;
3433 let Inst{11-7} = lsb;
3437 //===----------------------------------------------------------------------===//
3438 // Arithmetic Instructions.
3441 defm ADD : AsI1_bin_irs<0b0100, "add",
3442 IIC_iALUi, IIC_iALUr, IIC_iALUsr,
3443 BinOpFrag<(add node:$LHS, node:$RHS)>, 1>;
3444 defm SUB : AsI1_bin_irs<0b0010, "sub",
3445 IIC_iALUi, IIC_iALUr, IIC_iALUsr,
3446 BinOpFrag<(sub node:$LHS, node:$RHS)>>;
3448 // ADD and SUB with 's' bit set.
3450 // Currently, ADDS/SUBS are pseudo opcodes that exist only in the
3451 // selection DAG. They are "lowered" to real ADD/SUB opcodes by
3452 // AdjustInstrPostInstrSelection where we determine whether or not to
3453 // set the "s" bit based on CPSR liveness.
3455 // FIXME: Eliminate ADDS/SUBS pseudo opcodes after adding tablegen
3456 // support for an optional CPSR definition that corresponds to the DAG
3457 // node's second value. We can then eliminate the implicit def of CPSR.
3458 defm ADDS : AsI1_bin_s_irs<IIC_iALUi, IIC_iALUr, IIC_iALUsr,
3459 BinOpFrag<(ARMaddc node:$LHS, node:$RHS)>, 1>;
3460 defm SUBS : AsI1_bin_s_irs<IIC_iALUi, IIC_iALUr, IIC_iALUsr,
3461 BinOpFrag<(ARMsubc node:$LHS, node:$RHS)>>;
3463 defm ADC : AI1_adde_sube_irs<0b0101, "adc",
3464 BinOpWithFlagFrag<(ARMadde node:$LHS, node:$RHS, node:$FLAG)>, 1>;
3465 defm SBC : AI1_adde_sube_irs<0b0110, "sbc",
3466 BinOpWithFlagFrag<(ARMsube node:$LHS, node:$RHS, node:$FLAG)>>;
3468 defm RSB : AsI1_rbin_irs<0b0011, "rsb",
3469 IIC_iALUi, IIC_iALUr, IIC_iALUsr,
3470 BinOpFrag<(sub node:$LHS, node:$RHS)>>;
3472 // FIXME: Eliminate them if we can write def : Pat patterns which defines
3473 // CPSR and the implicit def of CPSR is not needed.
3474 defm RSBS : AsI1_rbin_s_is<IIC_iALUi, IIC_iALUr, IIC_iALUsr,
3475 BinOpFrag<(ARMsubc node:$LHS, node:$RHS)>>;
3477 defm RSC : AI1_rsc_irs<0b0111, "rsc",
3478 BinOpWithFlagFrag<(ARMsube node:$LHS, node:$RHS, node:$FLAG)>>;
3480 // (sub X, imm) gets canonicalized to (add X, -imm). Match this form.
3481 // The assume-no-carry-in form uses the negation of the input since add/sub
3482 // assume opposite meanings of the carry flag (i.e., carry == !borrow).
3483 // See the definition of AddWithCarry() in the ARM ARM A2.2.1 for the gory
3485 def : ARMPat<(add GPR:$src, mod_imm_neg:$imm),
3486 (SUBri GPR:$src, mod_imm_neg:$imm)>;
3487 def : ARMPat<(ARMaddc GPR:$src, mod_imm_neg:$imm),
3488 (SUBSri GPR:$src, mod_imm_neg:$imm)>;
3490 def : ARMPat<(add GPR:$src, imm0_65535_neg:$imm),
3491 (SUBrr GPR:$src, (MOVi16 (imm_neg_XFORM imm:$imm)))>,
3492 Requires<[IsARM, HasV6T2]>;
3493 def : ARMPat<(ARMaddc GPR:$src, imm0_65535_neg:$imm),
3494 (SUBSrr GPR:$src, (MOVi16 (imm_neg_XFORM imm:$imm)))>,
3495 Requires<[IsARM, HasV6T2]>;
3497 // The with-carry-in form matches bitwise not instead of the negation.
3498 // Effectively, the inverse interpretation of the carry flag already accounts
3499 // for part of the negation.
3500 def : ARMPat<(ARMadde GPR:$src, mod_imm_not:$imm, CPSR),
3501 (SBCri GPR:$src, mod_imm_not:$imm)>;
3502 def : ARMPat<(ARMadde GPR:$src, imm0_65535_neg:$imm, CPSR),
3503 (SBCrr GPR:$src, (MOVi16 (imm_not_XFORM imm:$imm)))>,
3504 Requires<[IsARM, HasV6T2]>;
3506 // Note: These are implemented in C++ code, because they have to generate
3507 // ADD/SUBrs instructions, which use a complex pattern that a xform function
3509 // (mul X, 2^n+1) -> (add (X << n), X)
3510 // (mul X, 2^n-1) -> (rsb X, (X << n))
3512 // ARM Arithmetic Instruction
3513 // GPR:$dst = GPR:$a op GPR:$b
3514 class AAI<bits<8> op27_20, bits<8> op11_4, string opc,
3515 list<dag> pattern = [],
3516 dag iops = (ins GPRnopc:$Rn, GPRnopc:$Rm),
3517 string asm = "\t$Rd, $Rn, $Rm">
3518 : AI<(outs GPRnopc:$Rd), iops, DPFrm, IIC_iALUr, opc, asm, pattern>,
3519 Sched<[WriteALU, ReadALU, ReadALU]> {
3523 let Inst{27-20} = op27_20;
3524 let Inst{11-4} = op11_4;
3525 let Inst{19-16} = Rn;
3526 let Inst{15-12} = Rd;
3529 let Unpredictable{11-8} = 0b1111;
3532 // Saturating add/subtract
3534 let DecoderMethod = "DecodeQADDInstruction" in
3535 def QADD : AAI<0b00010000, 0b00000101, "qadd",
3536 [(set GPRnopc:$Rd, (int_arm_qadd GPRnopc:$Rm, GPRnopc:$Rn))],
3537 (ins GPRnopc:$Rm, GPRnopc:$Rn), "\t$Rd, $Rm, $Rn">;
3539 def QSUB : AAI<0b00010010, 0b00000101, "qsub",
3540 [(set GPRnopc:$Rd, (int_arm_qsub GPRnopc:$Rm, GPRnopc:$Rn))],
3541 (ins GPRnopc:$Rm, GPRnopc:$Rn), "\t$Rd, $Rm, $Rn">;
3542 def QDADD : AAI<0b00010100, 0b00000101, "qdadd", [],
3543 (ins GPRnopc:$Rm, GPRnopc:$Rn),
3545 def QDSUB : AAI<0b00010110, 0b00000101, "qdsub", [],
3546 (ins GPRnopc:$Rm, GPRnopc:$Rn),
3549 def QADD16 : AAI<0b01100010, 0b11110001, "qadd16">;
3550 def QADD8 : AAI<0b01100010, 0b11111001, "qadd8">;
3551 def QASX : AAI<0b01100010, 0b11110011, "qasx">;
3552 def QSAX : AAI<0b01100010, 0b11110101, "qsax">;
3553 def QSUB16 : AAI<0b01100010, 0b11110111, "qsub16">;
3554 def QSUB8 : AAI<0b01100010, 0b11111111, "qsub8">;
3555 def UQADD16 : AAI<0b01100110, 0b11110001, "uqadd16">;
3556 def UQADD8 : AAI<0b01100110, 0b11111001, "uqadd8">;
3557 def UQASX : AAI<0b01100110, 0b11110011, "uqasx">;
3558 def UQSAX : AAI<0b01100110, 0b11110101, "uqsax">;
3559 def UQSUB16 : AAI<0b01100110, 0b11110111, "uqsub16">;
3560 def UQSUB8 : AAI<0b01100110, 0b11111111, "uqsub8">;
3562 // Signed/Unsigned add/subtract
3564 def SASX : AAI<0b01100001, 0b11110011, "sasx">;
3565 def SADD16 : AAI<0b01100001, 0b11110001, "sadd16">;
3566 def SADD8 : AAI<0b01100001, 0b11111001, "sadd8">;
3567 def SSAX : AAI<0b01100001, 0b11110101, "ssax">;
3568 def SSUB16 : AAI<0b01100001, 0b11110111, "ssub16">;
3569 def SSUB8 : AAI<0b01100001, 0b11111111, "ssub8">;
3570 def UASX : AAI<0b01100101, 0b11110011, "uasx">;
3571 def UADD16 : AAI<0b01100101, 0b11110001, "uadd16">;
3572 def UADD8 : AAI<0b01100101, 0b11111001, "uadd8">;
3573 def USAX : AAI<0b01100101, 0b11110101, "usax">;
3574 def USUB16 : AAI<0b01100101, 0b11110111, "usub16">;
3575 def USUB8 : AAI<0b01100101, 0b11111111, "usub8">;
3577 // Signed/Unsigned halving add/subtract
3579 def SHASX : AAI<0b01100011, 0b11110011, "shasx">;
3580 def SHADD16 : AAI<0b01100011, 0b11110001, "shadd16">;
3581 def SHADD8 : AAI<0b01100011, 0b11111001, "shadd8">;
3582 def SHSAX : AAI<0b01100011, 0b11110101, "shsax">;
3583 def SHSUB16 : AAI<0b01100011, 0b11110111, "shsub16">;
3584 def SHSUB8 : AAI<0b01100011, 0b11111111, "shsub8">;
3585 def UHASX : AAI<0b01100111, 0b11110011, "uhasx">;
3586 def UHADD16 : AAI<0b01100111, 0b11110001, "uhadd16">;
3587 def UHADD8 : AAI<0b01100111, 0b11111001, "uhadd8">;
3588 def UHSAX : AAI<0b01100111, 0b11110101, "uhsax">;
3589 def UHSUB16 : AAI<0b01100111, 0b11110111, "uhsub16">;
3590 def UHSUB8 : AAI<0b01100111, 0b11111111, "uhsub8">;
3592 // Unsigned Sum of Absolute Differences [and Accumulate].
3594 def USAD8 : AI<(outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm),
3595 MulFrm /* for convenience */, NoItinerary, "usad8",
3596 "\t$Rd, $Rn, $Rm", []>,
3597 Requires<[IsARM, HasV6]>, Sched<[WriteALU, ReadALU, ReadALU]> {
3601 let Inst{27-20} = 0b01111000;
3602 let Inst{15-12} = 0b1111;
3603 let Inst{7-4} = 0b0001;
3604 let Inst{19-16} = Rd;
3605 let Inst{11-8} = Rm;
3608 def USADA8 : AI<(outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm, GPR:$Ra),
3609 MulFrm /* for convenience */, NoItinerary, "usada8",
3610 "\t$Rd, $Rn, $Rm, $Ra", []>,
3611 Requires<[IsARM, HasV6]>, Sched<[WriteALU, ReadALU, ReadALU]>{
3616 let Inst{27-20} = 0b01111000;
3617 let Inst{7-4} = 0b0001;
3618 let Inst{19-16} = Rd;
3619 let Inst{15-12} = Ra;
3620 let Inst{11-8} = Rm;
3624 // Signed/Unsigned saturate
3626 def SSAT : AI<(outs GPRnopc:$Rd),
3627 (ins imm1_32:$sat_imm, GPRnopc:$Rn, shift_imm:$sh),
3628 SatFrm, NoItinerary, "ssat", "\t$Rd, $sat_imm, $Rn$sh", []> {
3633 let Inst{27-21} = 0b0110101;
3634 let Inst{5-4} = 0b01;
3635 let Inst{20-16} = sat_imm;
3636 let Inst{15-12} = Rd;
3637 let Inst{11-7} = sh{4-0};
3638 let Inst{6} = sh{5};
3642 def SSAT16 : AI<(outs GPRnopc:$Rd),
3643 (ins imm1_16:$sat_imm, GPRnopc:$Rn), SatFrm,
3644 NoItinerary, "ssat16", "\t$Rd, $sat_imm, $Rn", []> {
3648 let Inst{27-20} = 0b01101010;
3649 let Inst{11-4} = 0b11110011;
3650 let Inst{15-12} = Rd;
3651 let Inst{19-16} = sat_imm;
3655 def USAT : AI<(outs GPRnopc:$Rd),
3656 (ins imm0_31:$sat_imm, GPRnopc:$Rn, shift_imm:$sh),
3657 SatFrm, NoItinerary, "usat", "\t$Rd, $sat_imm, $Rn$sh", []> {
3662 let Inst{27-21} = 0b0110111;
3663 let Inst{5-4} = 0b01;
3664 let Inst{15-12} = Rd;
3665 let Inst{11-7} = sh{4-0};
3666 let Inst{6} = sh{5};
3667 let Inst{20-16} = sat_imm;
3671 def USAT16 : AI<(outs GPRnopc:$Rd),
3672 (ins imm0_15:$sat_imm, GPRnopc:$Rn), SatFrm,
3673 NoItinerary, "usat16", "\t$Rd, $sat_imm, $Rn", []> {
3677 let Inst{27-20} = 0b01101110;
3678 let Inst{11-4} = 0b11110011;
3679 let Inst{15-12} = Rd;
3680 let Inst{19-16} = sat_imm;
3684 def : ARMV6Pat<(int_arm_ssat GPRnopc:$a, imm1_32:$pos),
3685 (SSAT imm1_32:$pos, GPRnopc:$a, 0)>;
3686 def : ARMV6Pat<(int_arm_usat GPRnopc:$a, imm0_31:$pos),
3687 (USAT imm0_31:$pos, GPRnopc:$a, 0)>;
3689 //===----------------------------------------------------------------------===//
3690 // Bitwise Instructions.
3693 defm AND : AsI1_bin_irs<0b0000, "and",
3694 IIC_iBITi, IIC_iBITr, IIC_iBITsr,
3695 BinOpFrag<(and node:$LHS, node:$RHS)>, 1>;
3696 defm ORR : AsI1_bin_irs<0b1100, "orr",
3697 IIC_iBITi, IIC_iBITr, IIC_iBITsr,
3698 BinOpFrag<(or node:$LHS, node:$RHS)>, 1>;
3699 defm EOR : AsI1_bin_irs<0b0001, "eor",
3700 IIC_iBITi, IIC_iBITr, IIC_iBITsr,
3701 BinOpFrag<(xor node:$LHS, node:$RHS)>, 1>;
3702 defm BIC : AsI1_bin_irs<0b1110, "bic",
3703 IIC_iBITi, IIC_iBITr, IIC_iBITsr,
3704 BinOpFrag<(and node:$LHS, (not node:$RHS))>>;
3706 // FIXME: bf_inv_mask_imm should be two operands, the lsb and the msb, just
3707 // like in the actual instruction encoding. The complexity of mapping the mask
3708 // to the lsb/msb pair should be handled by ISel, not encapsulated in the
3709 // instruction description.
3710 def BFC : I<(outs GPR:$Rd), (ins GPR:$src, bf_inv_mask_imm:$imm),
3711 AddrMode1, 4, IndexModeNone, DPFrm, IIC_iUNAsi,
3712 "bfc", "\t$Rd, $imm", "$src = $Rd",
3713 [(set GPR:$Rd, (and GPR:$src, bf_inv_mask_imm:$imm))]>,
3714 Requires<[IsARM, HasV6T2]> {
3717 let Inst{27-21} = 0b0111110;
3718 let Inst{6-0} = 0b0011111;
3719 let Inst{15-12} = Rd;
3720 let Inst{11-7} = imm{4-0}; // lsb
3721 let Inst{20-16} = imm{9-5}; // msb
3724 // A8.6.18 BFI - Bitfield insert (Encoding A1)
3725 def BFI:I<(outs GPRnopc:$Rd), (ins GPRnopc:$src, GPR:$Rn, bf_inv_mask_imm:$imm),
3726 AddrMode1, 4, IndexModeNone, DPFrm, IIC_iUNAsi,
3727 "bfi", "\t$Rd, $Rn, $imm", "$src = $Rd",
3728 [(set GPRnopc:$Rd, (ARMbfi GPRnopc:$src, GPR:$Rn,
3729 bf_inv_mask_imm:$imm))]>,
3730 Requires<[IsARM, HasV6T2]> {
3734 let Inst{27-21} = 0b0111110;
3735 let Inst{6-4} = 0b001; // Rn: Inst{3-0} != 15
3736 let Inst{15-12} = Rd;
3737 let Inst{11-7} = imm{4-0}; // lsb
3738 let Inst{20-16} = imm{9-5}; // width
3742 def MVNr : AsI1<0b1111, (outs GPR:$Rd), (ins GPR:$Rm), DPFrm, IIC_iMVNr,
3743 "mvn", "\t$Rd, $Rm",
3744 [(set GPR:$Rd, (not GPR:$Rm))]>, UnaryDP, Sched<[WriteALU]> {
3748 let Inst{19-16} = 0b0000;
3749 let Inst{11-4} = 0b00000000;
3750 let Inst{15-12} = Rd;
3753 def MVNsi : AsI1<0b1111, (outs GPR:$Rd), (ins so_reg_imm:$shift),
3754 DPSoRegImmFrm, IIC_iMVNsr, "mvn", "\t$Rd, $shift",
3755 [(set GPR:$Rd, (not so_reg_imm:$shift))]>, UnaryDP,
3760 let Inst{19-16} = 0b0000;
3761 let Inst{15-12} = Rd;
3762 let Inst{11-5} = shift{11-5};
3764 let Inst{3-0} = shift{3-0};
3766 def MVNsr : AsI1<0b1111, (outs GPR:$Rd), (ins so_reg_reg:$shift),
3767 DPSoRegRegFrm, IIC_iMVNsr, "mvn", "\t$Rd, $shift",
3768 [(set GPR:$Rd, (not so_reg_reg:$shift))]>, UnaryDP,
3773 let Inst{19-16} = 0b0000;
3774 let Inst{15-12} = Rd;
3775 let Inst{11-8} = shift{11-8};
3777 let Inst{6-5} = shift{6-5};
3779 let Inst{3-0} = shift{3-0};
3781 let isReMaterializable = 1, isAsCheapAsAMove = 1, isMoveImm = 1 in
3782 def MVNi : AsI1<0b1111, (outs GPR:$Rd), (ins mod_imm:$imm), DPFrm,
3783 IIC_iMVNi, "mvn", "\t$Rd, $imm",
3784 [(set GPR:$Rd, mod_imm_not:$imm)]>,UnaryDP, Sched<[WriteALU]> {
3788 let Inst{19-16} = 0b0000;
3789 let Inst{15-12} = Rd;
3790 let Inst{11-0} = imm;
3793 def : ARMPat<(and GPR:$src, mod_imm_not:$imm),
3794 (BICri GPR:$src, mod_imm_not:$imm)>;
3796 //===----------------------------------------------------------------------===//
3797 // Multiply Instructions.
3799 class AsMul1I32<bits<7> opcod, dag oops, dag iops, InstrItinClass itin,
3800 string opc, string asm, list<dag> pattern>
3801 : AsMul1I<opcod, oops, iops, itin, opc, asm, pattern> {
3805 let Inst{19-16} = Rd;
3806 let Inst{11-8} = Rm;
3809 class AsMul1I64<bits<7> opcod, dag oops, dag iops, InstrItinClass itin,
3810 string opc, string asm, list<dag> pattern>
3811 : AsMul1I<opcod, oops, iops, itin, opc, asm, pattern> {
3816 let Inst{19-16} = RdHi;
3817 let Inst{15-12} = RdLo;
3818 let Inst{11-8} = Rm;
3821 class AsMla1I64<bits<7> opcod, dag oops, dag iops, InstrItinClass itin,
3822 string opc, string asm, list<dag> pattern>
3823 : AsMul1I<opcod, oops, iops, itin, opc, asm, pattern> {
3828 let Inst{19-16} = RdHi;
3829 let Inst{15-12} = RdLo;
3830 let Inst{11-8} = Rm;
3834 // FIXME: The v5 pseudos are only necessary for the additional Constraint
3835 // property. Remove them when it's possible to add those properties
3836 // on an individual MachineInstr, not just an instruction description.
3837 let isCommutable = 1, TwoOperandAliasConstraint = "$Rn = $Rd" in {
3838 def MUL : AsMul1I32<0b0000000, (outs GPRnopc:$Rd),
3839 (ins GPRnopc:$Rn, GPRnopc:$Rm),
3840 IIC_iMUL32, "mul", "\t$Rd, $Rn, $Rm",
3841 [(set GPRnopc:$Rd, (mul GPRnopc:$Rn, GPRnopc:$Rm))]>,
3842 Requires<[IsARM, HasV6]> {
3843 let Inst{15-12} = 0b0000;
3844 let Unpredictable{15-12} = 0b1111;
3847 let Constraints = "@earlyclobber $Rd" in
3848 def MULv5: ARMPseudoExpand<(outs GPRnopc:$Rd), (ins GPRnopc:$Rn, GPRnopc:$Rm,
3849 pred:$p, cc_out:$s),
3851 [(set GPRnopc:$Rd, (mul GPRnopc:$Rn, GPRnopc:$Rm))],
3852 (MUL GPRnopc:$Rd, GPRnopc:$Rn, GPRnopc:$Rm, pred:$p, cc_out:$s)>,
3853 Requires<[IsARM, NoV6, UseMulOps]>;
3856 def MLA : AsMul1I32<0b0000001, (outs GPRnopc:$Rd),
3857 (ins GPRnopc:$Rn, GPRnopc:$Rm, GPRnopc:$Ra),
3858 IIC_iMAC32, "mla", "\t$Rd, $Rn, $Rm, $Ra",
3859 [(set GPRnopc:$Rd, (add (mul GPRnopc:$Rn, GPRnopc:$Rm), GPRnopc:$Ra))]>,
3860 Requires<[IsARM, HasV6, UseMulOps]> {
3862 let Inst{15-12} = Ra;
3865 let Constraints = "@earlyclobber $Rd" in
3866 def MLAv5: ARMPseudoExpand<(outs GPRnopc:$Rd),
3867 (ins GPRnopc:$Rn, GPRnopc:$Rm, GPRnopc:$Ra,
3868 pred:$p, cc_out:$s), 4, IIC_iMAC32,
3869 [(set GPRnopc:$Rd, (add (mul GPRnopc:$Rn, GPRnopc:$Rm), GPRnopc:$Ra))],
3870 (MLA GPRnopc:$Rd, GPRnopc:$Rn, GPRnopc:$Rm, GPRnopc:$Ra, pred:$p, cc_out:$s)>,
3871 Requires<[IsARM, NoV6]>;
3873 def MLS : AMul1I<0b0000011, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm, GPR:$Ra),
3874 IIC_iMAC32, "mls", "\t$Rd, $Rn, $Rm, $Ra",
3875 [(set GPR:$Rd, (sub GPR:$Ra, (mul GPR:$Rn, GPR:$Rm)))]>,
3876 Requires<[IsARM, HasV6T2, UseMulOps]> {
3881 let Inst{19-16} = Rd;
3882 let Inst{15-12} = Ra;
3883 let Inst{11-8} = Rm;
3887 // Extra precision multiplies with low / high results
3888 let hasSideEffects = 0 in {
3889 let isCommutable = 1 in {
3890 def SMULL : AsMul1I64<0b0000110, (outs GPR:$RdLo, GPR:$RdHi),
3891 (ins GPR:$Rn, GPR:$Rm), IIC_iMUL64,
3892 "smull", "\t$RdLo, $RdHi, $Rn, $Rm", []>,
3893 Requires<[IsARM, HasV6]>;
3895 def UMULL : AsMul1I64<0b0000100, (outs GPR:$RdLo, GPR:$RdHi),
3896 (ins GPR:$Rn, GPR:$Rm), IIC_iMUL64,
3897 "umull", "\t$RdLo, $RdHi, $Rn, $Rm", []>,
3898 Requires<[IsARM, HasV6]>;
3900 let Constraints = "@earlyclobber $RdLo,@earlyclobber $RdHi" in {
3901 def SMULLv5 : ARMPseudoExpand<(outs GPR:$RdLo, GPR:$RdHi),
3902 (ins GPR:$Rn, GPR:$Rm, pred:$p, cc_out:$s),
3904 (SMULL GPR:$RdLo, GPR:$RdHi, GPR:$Rn, GPR:$Rm, pred:$p, cc_out:$s)>,
3905 Requires<[IsARM, NoV6]>;
3907 def UMULLv5 : ARMPseudoExpand<(outs GPR:$RdLo, GPR:$RdHi),
3908 (ins GPR:$Rn, GPR:$Rm, pred:$p, cc_out:$s),
3910 (UMULL GPR:$RdLo, GPR:$RdHi, GPR:$Rn, GPR:$Rm, pred:$p, cc_out:$s)>,
3911 Requires<[IsARM, NoV6]>;
3915 // Multiply + accumulate
3916 def SMLAL : AsMla1I64<0b0000111, (outs GPR:$RdLo, GPR:$RdHi),
3917 (ins GPR:$Rn, GPR:$Rm, GPR:$RLo, GPR:$RHi), IIC_iMAC64,
3918 "smlal", "\t$RdLo, $RdHi, $Rn, $Rm", []>,
3919 RegConstraint<"$RLo = $RdLo, $RHi = $RdHi">, Requires<[IsARM, HasV6]>;
3920 def UMLAL : AsMla1I64<0b0000101, (outs GPR:$RdLo, GPR:$RdHi),
3921 (ins GPR:$Rn, GPR:$Rm, GPR:$RLo, GPR:$RHi), IIC_iMAC64,
3922 "umlal", "\t$RdLo, $RdHi, $Rn, $Rm", []>,
3923 RegConstraint<"$RLo = $RdLo, $RHi = $RdHi">, Requires<[IsARM, HasV6]>;
3925 def UMAAL : AMul1I <0b0000010, (outs GPR:$RdLo, GPR:$RdHi),
3926 (ins GPR:$Rn, GPR:$Rm), IIC_iMAC64,
3927 "umaal", "\t$RdLo, $RdHi, $Rn, $Rm", []>,
3928 Requires<[IsARM, HasV6]> {
3933 let Inst{19-16} = RdHi;
3934 let Inst{15-12} = RdLo;
3935 let Inst{11-8} = Rm;
3940 "@earlyclobber $RdLo,@earlyclobber $RdHi,$RLo = $RdLo,$RHi = $RdHi" in {
3941 def SMLALv5 : ARMPseudoExpand<(outs GPR:$RdLo, GPR:$RdHi),
3942 (ins GPR:$Rn, GPR:$Rm, GPR:$RLo, GPR:$RHi, pred:$p, cc_out:$s),
3944 (SMLAL GPR:$RdLo, GPR:$RdHi, GPR:$Rn, GPR:$Rm, GPR:$RLo, GPR:$RHi,
3945 pred:$p, cc_out:$s)>,
3946 Requires<[IsARM, NoV6]>;
3947 def UMLALv5 : ARMPseudoExpand<(outs GPR:$RdLo, GPR:$RdHi),
3948 (ins GPR:$Rn, GPR:$Rm, GPR:$RLo, GPR:$RHi, pred:$p, cc_out:$s),
3950 (UMLAL GPR:$RdLo, GPR:$RdHi, GPR:$Rn, GPR:$Rm, GPR:$RLo, GPR:$RHi,
3951 pred:$p, cc_out:$s)>,
3952 Requires<[IsARM, NoV6]>;
3957 // Most significant word multiply
3958 def SMMUL : AMul2I <0b0111010, 0b0001, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm),
3959 IIC_iMUL32, "smmul", "\t$Rd, $Rn, $Rm",
3960 [(set GPR:$Rd, (mulhs GPR:$Rn, GPR:$Rm))]>,
3961 Requires<[IsARM, HasV6]> {
3962 let Inst{15-12} = 0b1111;
3965 def SMMULR : AMul2I <0b0111010, 0b0011, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm),
3966 IIC_iMUL32, "smmulr", "\t$Rd, $Rn, $Rm", []>,
3967 Requires<[IsARM, HasV6]> {
3968 let Inst{15-12} = 0b1111;
3971 def SMMLA : AMul2Ia <0b0111010, 0b0001, (outs GPR:$Rd),
3972 (ins GPR:$Rn, GPR:$Rm, GPR:$Ra),
3973 IIC_iMAC32, "smmla", "\t$Rd, $Rn, $Rm, $Ra",
3974 [(set GPR:$Rd, (add (mulhs GPR:$Rn, GPR:$Rm), GPR:$Ra))]>,
3975 Requires<[IsARM, HasV6, UseMulOps]>;
3977 def SMMLAR : AMul2Ia <0b0111010, 0b0011, (outs GPR:$Rd),
3978 (ins GPR:$Rn, GPR:$Rm, GPR:$Ra),
3979 IIC_iMAC32, "smmlar", "\t$Rd, $Rn, $Rm, $Ra", []>,
3980 Requires<[IsARM, HasV6]>;
3982 def SMMLS : AMul2Ia <0b0111010, 0b1101, (outs GPR:$Rd),
3983 (ins GPR:$Rn, GPR:$Rm, GPR:$Ra),
3984 IIC_iMAC32, "smmls", "\t$Rd, $Rn, $Rm, $Ra", []>,
3985 Requires<[IsARM, HasV6, UseMulOps]>;
3987 def SMMLSR : AMul2Ia <0b0111010, 0b1111, (outs GPR:$Rd),
3988 (ins GPR:$Rn, GPR:$Rm, GPR:$Ra),
3989 IIC_iMAC32, "smmlsr", "\t$Rd, $Rn, $Rm, $Ra", []>,
3990 Requires<[IsARM, HasV6]>;
3992 multiclass AI_smul<string opc, PatFrag opnode> {
3993 def BB : AMulxyI<0b0001011, 0b00, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm),
3994 IIC_iMUL16, !strconcat(opc, "bb"), "\t$Rd, $Rn, $Rm",
3995 [(set GPR:$Rd, (opnode (sext_inreg GPR:$Rn, i16),
3996 (sext_inreg GPR:$Rm, i16)))]>,
3997 Requires<[IsARM, HasV5TE]>;
3999 def BT : AMulxyI<0b0001011, 0b10, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm),
4000 IIC_iMUL16, !strconcat(opc, "bt"), "\t$Rd, $Rn, $Rm",
4001 [(set GPR:$Rd, (opnode (sext_inreg GPR:$Rn, i16),
4002 (sra GPR:$Rm, (i32 16))))]>,
4003 Requires<[IsARM, HasV5TE]>;
4005 def TB : AMulxyI<0b0001011, 0b01, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm),
4006 IIC_iMUL16, !strconcat(opc, "tb"), "\t$Rd, $Rn, $Rm",
4007 [(set GPR:$Rd, (opnode (sra GPR:$Rn, (i32 16)),
4008 (sext_inreg GPR:$Rm, i16)))]>,
4009 Requires<[IsARM, HasV5TE]>;
4011 def TT : AMulxyI<0b0001011, 0b11, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm),
4012 IIC_iMUL16, !strconcat(opc, "tt"), "\t$Rd, $Rn, $Rm",
4013 [(set GPR:$Rd, (opnode (sra GPR:$Rn, (i32 16)),
4014 (sra GPR:$Rm, (i32 16))))]>,
4015 Requires<[IsARM, HasV5TE]>;
4017 def WB : AMulxyI<0b0001001, 0b01, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm),
4018 IIC_iMUL16, !strconcat(opc, "wb"), "\t$Rd, $Rn, $Rm",
4020 Requires<[IsARM, HasV5TE]>;
4022 def WT : AMulxyI<0b0001001, 0b11, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm),
4023 IIC_iMUL16, !strconcat(opc, "wt"), "\t$Rd, $Rn, $Rm",
4025 Requires<[IsARM, HasV5TE]>;
4029 multiclass AI_smla<string opc, PatFrag opnode> {
4030 let DecoderMethod = "DecodeSMLAInstruction" in {
4031 def BB : AMulxyIa<0b0001000, 0b00, (outs GPRnopc:$Rd),
4032 (ins GPRnopc:$Rn, GPRnopc:$Rm, GPR:$Ra),
4033 IIC_iMAC16, !strconcat(opc, "bb"), "\t$Rd, $Rn, $Rm, $Ra",
4034 [(set GPRnopc:$Rd, (add GPR:$Ra,
4035 (opnode (sext_inreg GPRnopc:$Rn, i16),
4036 (sext_inreg GPRnopc:$Rm, i16))))]>,
4037 Requires<[IsARM, HasV5TE, UseMulOps]>;
4039 def BT : AMulxyIa<0b0001000, 0b10, (outs GPRnopc:$Rd),
4040 (ins GPRnopc:$Rn, GPRnopc:$Rm, GPR:$Ra),
4041 IIC_iMAC16, !strconcat(opc, "bt"), "\t$Rd, $Rn, $Rm, $Ra",
4043 (add GPR:$Ra, (opnode (sext_inreg GPRnopc:$Rn, i16),
4044 (sra GPRnopc:$Rm, (i32 16)))))]>,
4045 Requires<[IsARM, HasV5TE, UseMulOps]>;
4047 def TB : AMulxyIa<0b0001000, 0b01, (outs GPRnopc:$Rd),
4048 (ins GPRnopc:$Rn, GPRnopc:$Rm, GPR:$Ra),
4049 IIC_iMAC16, !strconcat(opc, "tb"), "\t$Rd, $Rn, $Rm, $Ra",
4051 (add GPR:$Ra, (opnode (sra GPRnopc:$Rn, (i32 16)),
4052 (sext_inreg GPRnopc:$Rm, i16))))]>,
4053 Requires<[IsARM, HasV5TE, UseMulOps]>;
4055 def TT : AMulxyIa<0b0001000, 0b11, (outs GPRnopc:$Rd),
4056 (ins GPRnopc:$Rn, GPRnopc:$Rm, GPR:$Ra),
4057 IIC_iMAC16, !strconcat(opc, "tt"), "\t$Rd, $Rn, $Rm, $Ra",
4059 (add GPR:$Ra, (opnode (sra GPRnopc:$Rn, (i32 16)),
4060 (sra GPRnopc:$Rm, (i32 16)))))]>,
4061 Requires<[IsARM, HasV5TE, UseMulOps]>;
4063 def WB : AMulxyIa<0b0001001, 0b00, (outs GPRnopc:$Rd),
4064 (ins GPRnopc:$Rn, GPRnopc:$Rm, GPR:$Ra),
4065 IIC_iMAC16, !strconcat(opc, "wb"), "\t$Rd, $Rn, $Rm, $Ra",
4067 Requires<[IsARM, HasV5TE, UseMulOps]>;
4069 def WT : AMulxyIa<0b0001001, 0b10, (outs GPRnopc:$Rd),
4070 (ins GPRnopc:$Rn, GPRnopc:$Rm, GPR:$Ra),
4071 IIC_iMAC16, !strconcat(opc, "wt"), "\t$Rd, $Rn, $Rm, $Ra",
4073 Requires<[IsARM, HasV5TE, UseMulOps]>;
4077 defm SMUL : AI_smul<"smul", BinOpFrag<(mul node:$LHS, node:$RHS)>>;
4078 defm SMLA : AI_smla<"smla", BinOpFrag<(mul node:$LHS, node:$RHS)>>;
4080 // Halfword multiply accumulate long: SMLAL<x><y>.
4081 def SMLALBB : AMulxyI64<0b0001010, 0b00, (outs GPRnopc:$RdLo, GPRnopc:$RdHi),
4082 (ins GPRnopc:$Rn, GPRnopc:$Rm),
4083 IIC_iMAC64, "smlalbb", "\t$RdLo, $RdHi, $Rn, $Rm", []>,
4084 Requires<[IsARM, HasV5TE]>;
4086 def SMLALBT : AMulxyI64<0b0001010, 0b10, (outs GPRnopc:$RdLo, GPRnopc:$RdHi),
4087 (ins GPRnopc:$Rn, GPRnopc:$Rm),
4088 IIC_iMAC64, "smlalbt", "\t$RdLo, $RdHi, $Rn, $Rm", []>,
4089 Requires<[IsARM, HasV5TE]>;
4091 def SMLALTB : AMulxyI64<0b0001010, 0b01, (outs GPRnopc:$RdLo, GPRnopc:$RdHi),
4092 (ins GPRnopc:$Rn, GPRnopc:$Rm),
4093 IIC_iMAC64, "smlaltb", "\t$RdLo, $RdHi, $Rn, $Rm", []>,
4094 Requires<[IsARM, HasV5TE]>;
4096 def SMLALTT : AMulxyI64<0b0001010, 0b11, (outs GPRnopc:$RdLo, GPRnopc:$RdHi),
4097 (ins GPRnopc:$Rn, GPRnopc:$Rm),
4098 IIC_iMAC64, "smlaltt", "\t$RdLo, $RdHi, $Rn, $Rm", []>,
4099 Requires<[IsARM, HasV5TE]>;
4101 // Helper class for AI_smld.
4102 class AMulDualIbase<bit long, bit sub, bit swap, dag oops, dag iops,
4103 InstrItinClass itin, string opc, string asm>
4104 : AI<oops, iops, MulFrm, itin, opc, asm, []>, Requires<[IsARM, HasV6]> {
4107 let Inst{27-23} = 0b01110;
4108 let Inst{22} = long;
4109 let Inst{21-20} = 0b00;
4110 let Inst{11-8} = Rm;
4117 class AMulDualI<bit long, bit sub, bit swap, dag oops, dag iops,
4118 InstrItinClass itin, string opc, string asm>
4119 : AMulDualIbase<long, sub, swap, oops, iops, itin, opc, asm> {
4121 let Inst{15-12} = 0b1111;
4122 let Inst{19-16} = Rd;
4124 class AMulDualIa<bit long, bit sub, bit swap, dag oops, dag iops,
4125 InstrItinClass itin, string opc, string asm>
4126 : AMulDualIbase<long, sub, swap, oops, iops, itin, opc, asm> {
4129 let Inst{19-16} = Rd;
4130 let Inst{15-12} = Ra;
4132 class AMulDualI64<bit long, bit sub, bit swap, dag oops, dag iops,
4133 InstrItinClass itin, string opc, string asm>
4134 : AMulDualIbase<long, sub, swap, oops, iops, itin, opc, asm> {
4137 let Inst{19-16} = RdHi;
4138 let Inst{15-12} = RdLo;
4141 multiclass AI_smld<bit sub, string opc> {
4143 def D : AMulDualIa<0, sub, 0, (outs GPRnopc:$Rd),
4144 (ins GPRnopc:$Rn, GPRnopc:$Rm, GPR:$Ra),
4145 NoItinerary, !strconcat(opc, "d"), "\t$Rd, $Rn, $Rm, $Ra">;
4147 def DX: AMulDualIa<0, sub, 1, (outs GPRnopc:$Rd),
4148 (ins GPRnopc:$Rn, GPRnopc:$Rm, GPR:$Ra),
4149 NoItinerary, !strconcat(opc, "dx"), "\t$Rd, $Rn, $Rm, $Ra">;
4151 def LD: AMulDualI64<1, sub, 0, (outs GPRnopc:$RdLo, GPRnopc:$RdHi),
4152 (ins GPRnopc:$Rn, GPRnopc:$Rm), NoItinerary,
4153 !strconcat(opc, "ld"), "\t$RdLo, $RdHi, $Rn, $Rm">;
4155 def LDX : AMulDualI64<1, sub, 1, (outs GPRnopc:$RdLo, GPRnopc:$RdHi),
4156 (ins GPRnopc:$Rn, GPRnopc:$Rm), NoItinerary,
4157 !strconcat(opc, "ldx"),"\t$RdLo, $RdHi, $Rn, $Rm">;
4161 defm SMLA : AI_smld<0, "smla">;
4162 defm SMLS : AI_smld<1, "smls">;
4164 multiclass AI_sdml<bit sub, string opc> {
4166 def D:AMulDualI<0, sub, 0, (outs GPRnopc:$Rd), (ins GPRnopc:$Rn, GPRnopc:$Rm),
4167 NoItinerary, !strconcat(opc, "d"), "\t$Rd, $Rn, $Rm">;
4168 def DX:AMulDualI<0, sub, 1, (outs GPRnopc:$Rd),(ins GPRnopc:$Rn, GPRnopc:$Rm),
4169 NoItinerary, !strconcat(opc, "dx"), "\t$Rd, $Rn, $Rm">;
4172 defm SMUA : AI_sdml<0, "smua">;
4173 defm SMUS : AI_sdml<1, "smus">;
4175 //===----------------------------------------------------------------------===//
4176 // Division Instructions (ARMv7-A with virtualization extension)
4178 def SDIV : ADivA1I<0b001, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm), IIC_iDIV,
4179 "sdiv", "\t$Rd, $Rn, $Rm",
4180 [(set GPR:$Rd, (sdiv GPR:$Rn, GPR:$Rm))]>,
4181 Requires<[IsARM, HasDivideInARM]>;
4183 def UDIV : ADivA1I<0b011, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm), IIC_iDIV,
4184 "udiv", "\t$Rd, $Rn, $Rm",
4185 [(set GPR:$Rd, (udiv GPR:$Rn, GPR:$Rm))]>,
4186 Requires<[IsARM, HasDivideInARM]>;
4188 //===----------------------------------------------------------------------===//
4189 // Misc. Arithmetic Instructions.
4192 def CLZ : AMiscA1I<0b00010110, 0b0001, (outs GPR:$Rd), (ins GPR:$Rm),
4193 IIC_iUNAr, "clz", "\t$Rd, $Rm",
4194 [(set GPR:$Rd, (ctlz GPR:$Rm))]>, Requires<[IsARM, HasV5T]>,
4197 def RBIT : AMiscA1I<0b01101111, 0b0011, (outs GPR:$Rd), (ins GPR:$Rm),
4198 IIC_iUNAr, "rbit", "\t$Rd, $Rm",
4199 [(set GPR:$Rd, (bitreverse GPR:$Rm))]>,
4200 Requires<[IsARM, HasV6T2]>,
4203 def REV : AMiscA1I<0b01101011, 0b0011, (outs GPR:$Rd), (ins GPR:$Rm),
4204 IIC_iUNAr, "rev", "\t$Rd, $Rm",
4205 [(set GPR:$Rd, (bswap GPR:$Rm))]>, Requires<[IsARM, HasV6]>,
4208 let AddedComplexity = 5 in
4209 def REV16 : AMiscA1I<0b01101011, 0b1011, (outs GPR:$Rd), (ins GPR:$Rm),
4210 IIC_iUNAr, "rev16", "\t$Rd, $Rm",
4211 [(set GPR:$Rd, (rotr (bswap GPR:$Rm), (i32 16)))]>,
4212 Requires<[IsARM, HasV6]>,
4215 def : ARMV6Pat<(srl (bswap (extloadi16 addrmode3:$addr)), (i32 16)),
4216 (REV16 (LDRH addrmode3:$addr))>;
4217 def : ARMV6Pat<(truncstorei16 (srl (bswap GPR:$Rn), (i32 16)), addrmode3:$addr),
4218 (STRH (REV16 GPR:$Rn), addrmode3:$addr)>;
4220 let AddedComplexity = 5 in
4221 def REVSH : AMiscA1I<0b01101111, 0b1011, (outs GPR:$Rd), (ins GPR:$Rm),
4222 IIC_iUNAr, "revsh", "\t$Rd, $Rm",
4223 [(set GPR:$Rd, (sra (bswap GPR:$Rm), (i32 16)))]>,
4224 Requires<[IsARM, HasV6]>,
4227 def : ARMV6Pat<(or (sra (shl GPR:$Rm, (i32 24)), (i32 16)),
4228 (and (srl GPR:$Rm, (i32 8)), 0xFF)),
4231 def PKHBT : APKHI<0b01101000, 0, (outs GPRnopc:$Rd),
4232 (ins GPRnopc:$Rn, GPRnopc:$Rm, pkh_lsl_amt:$sh),
4233 IIC_iALUsi, "pkhbt", "\t$Rd, $Rn, $Rm$sh",
4234 [(set GPRnopc:$Rd, (or (and GPRnopc:$Rn, 0xFFFF),
4235 (and (shl GPRnopc:$Rm, pkh_lsl_amt:$sh),
4237 Requires<[IsARM, HasV6]>,
4238 Sched<[WriteALUsi, ReadALU]>;
4240 // Alternate cases for PKHBT where identities eliminate some nodes.
4241 def : ARMV6Pat<(or (and GPRnopc:$Rn, 0xFFFF), (and GPRnopc:$Rm, 0xFFFF0000)),
4242 (PKHBT GPRnopc:$Rn, GPRnopc:$Rm, 0)>;
4243 def : ARMV6Pat<(or (and GPRnopc:$Rn, 0xFFFF), (shl GPRnopc:$Rm, imm16_31:$sh)),
4244 (PKHBT GPRnopc:$Rn, GPRnopc:$Rm, imm16_31:$sh)>;
4246 // Note: Shifts of 1-15 bits will be transformed to srl instead of sra and
4247 // will match the pattern below.
4248 def PKHTB : APKHI<0b01101000, 1, (outs GPRnopc:$Rd),
4249 (ins GPRnopc:$Rn, GPRnopc:$Rm, pkh_asr_amt:$sh),
4250 IIC_iBITsi, "pkhtb", "\t$Rd, $Rn, $Rm$sh",
4251 [(set GPRnopc:$Rd, (or (and GPRnopc:$Rn, 0xFFFF0000),
4252 (and (sra GPRnopc:$Rm, pkh_asr_amt:$sh),
4254 Requires<[IsARM, HasV6]>,
4255 Sched<[WriteALUsi, ReadALU]>;
4257 // Alternate cases for PKHTB where identities eliminate some nodes. Note that
4258 // a shift amount of 0 is *not legal* here, it is PKHBT instead.
4259 // We also can not replace a srl (17..31) by an arithmetic shift we would use in
4260 // pkhtb src1, src2, asr (17..31).
4261 def : ARMV6Pat<(or (and GPRnopc:$src1, 0xFFFF0000),
4262 (srl GPRnopc:$src2, imm16:$sh)),
4263 (PKHTB GPRnopc:$src1, GPRnopc:$src2, imm16:$sh)>;
4264 def : ARMV6Pat<(or (and GPRnopc:$src1, 0xFFFF0000),
4265 (sra GPRnopc:$src2, imm16_31:$sh)),
4266 (PKHTB GPRnopc:$src1, GPRnopc:$src2, imm16_31:$sh)>;
4267 def : ARMV6Pat<(or (and GPRnopc:$src1, 0xFFFF0000),
4268 (and (srl GPRnopc:$src2, imm1_15:$sh), 0xFFFF)),
4269 (PKHTB GPRnopc:$src1, GPRnopc:$src2, imm1_15:$sh)>;
4271 //===----------------------------------------------------------------------===//
4275 // + CRC32{B,H,W} 0x04C11DB7
4276 // + CRC32C{B,H,W} 0x1EDC6F41
4279 class AI_crc32<bit C, bits<2> sz, string suffix, SDPatternOperator builtin>
4280 : AInoP<(outs GPRnopc:$Rd), (ins GPRnopc:$Rn, GPRnopc:$Rm), MiscFrm, NoItinerary,
4281 !strconcat("crc32", suffix), "\t$Rd, $Rn, $Rm",
4282 [(set GPRnopc:$Rd, (builtin GPRnopc:$Rn, GPRnopc:$Rm))]>,
4283 Requires<[IsARM, HasV8, HasCRC]> {
4288 let Inst{31-28} = 0b1110;
4289 let Inst{27-23} = 0b00010;
4290 let Inst{22-21} = sz;
4292 let Inst{19-16} = Rn;
4293 let Inst{15-12} = Rd;
4294 let Inst{11-10} = 0b00;
4297 let Inst{7-4} = 0b0100;
4300 let Unpredictable{11-8} = 0b1101;
4303 def CRC32B : AI_crc32<0, 0b00, "b", int_arm_crc32b>;
4304 def CRC32CB : AI_crc32<1, 0b00, "cb", int_arm_crc32cb>;
4305 def CRC32H : AI_crc32<0, 0b01, "h", int_arm_crc32h>;
4306 def CRC32CH : AI_crc32<1, 0b01, "ch", int_arm_crc32ch>;
4307 def CRC32W : AI_crc32<0, 0b10, "w", int_arm_crc32w>;
4308 def CRC32CW : AI_crc32<1, 0b10, "cw", int_arm_crc32cw>;
4310 //===----------------------------------------------------------------------===//
4311 // ARMv8.1a Privilege Access Never extension
4315 def SETPAN : AInoP<(outs), (ins imm0_1:$imm), MiscFrm, NoItinerary, "setpan",
4316 "\t$imm", []>, Requires<[IsARM, HasV8, HasV8_1a]> {
4319 let Inst{31-28} = 0b1111;
4320 let Inst{27-20} = 0b00010001;
4321 let Inst{19-16} = 0b0000;
4322 let Inst{15-10} = 0b000000;
4325 let Inst{7-4} = 0b0000;
4326 let Inst{3-0} = 0b0000;
4328 let Unpredictable{19-16} = 0b1111;
4329 let Unpredictable{15-10} = 0b111111;
4330 let Unpredictable{8} = 0b1;
4331 let Unpredictable{3-0} = 0b1111;
4334 //===----------------------------------------------------------------------===//
4335 // Comparison Instructions...
4338 defm CMP : AI1_cmp_irs<0b1010, "cmp",
4339 IIC_iCMPi, IIC_iCMPr, IIC_iCMPsr,
4340 BinOpFrag<(ARMcmp node:$LHS, node:$RHS)>>;
4342 // ARMcmpZ can re-use the above instruction definitions.
4343 def : ARMPat<(ARMcmpZ GPR:$src, mod_imm:$imm),
4344 (CMPri GPR:$src, mod_imm:$imm)>;
4345 def : ARMPat<(ARMcmpZ GPR:$src, GPR:$rhs),
4346 (CMPrr GPR:$src, GPR:$rhs)>;
4347 def : ARMPat<(ARMcmpZ GPR:$src, so_reg_imm:$rhs),
4348 (CMPrsi GPR:$src, so_reg_imm:$rhs)>;
4349 def : ARMPat<(ARMcmpZ GPR:$src, so_reg_reg:$rhs),
4350 (CMPrsr GPR:$src, so_reg_reg:$rhs)>;
4352 // CMN register-integer
4353 let isCompare = 1, Defs = [CPSR] in {
4354 def CMNri : AI1<0b1011, (outs), (ins GPR:$Rn, mod_imm:$imm), DPFrm, IIC_iCMPi,
4355 "cmn", "\t$Rn, $imm",
4356 [(ARMcmn GPR:$Rn, mod_imm:$imm)]>,
4357 Sched<[WriteCMP, ReadALU]> {
4362 let Inst{19-16} = Rn;
4363 let Inst{15-12} = 0b0000;
4364 let Inst{11-0} = imm;
4366 let Unpredictable{15-12} = 0b1111;
4369 // CMN register-register/shift
4370 def CMNzrr : AI1<0b1011, (outs), (ins GPR:$Rn, GPR:$Rm), DPFrm, IIC_iCMPr,
4371 "cmn", "\t$Rn, $Rm",
4372 [(BinOpFrag<(ARMcmpZ node:$LHS,(ineg node:$RHS))>
4373 GPR:$Rn, GPR:$Rm)]>, Sched<[WriteCMP, ReadALU, ReadALU]> {
4376 let isCommutable = 1;
4379 let Inst{19-16} = Rn;
4380 let Inst{15-12} = 0b0000;
4381 let Inst{11-4} = 0b00000000;
4384 let Unpredictable{15-12} = 0b1111;
4387 def CMNzrsi : AI1<0b1011, (outs),
4388 (ins GPR:$Rn, so_reg_imm:$shift), DPSoRegImmFrm, IIC_iCMPsr,
4389 "cmn", "\t$Rn, $shift",
4390 [(BinOpFrag<(ARMcmpZ node:$LHS,(ineg node:$RHS))>
4391 GPR:$Rn, so_reg_imm:$shift)]>,
4392 Sched<[WriteCMPsi, ReadALU]> {
4397 let Inst{19-16} = Rn;
4398 let Inst{15-12} = 0b0000;
4399 let Inst{11-5} = shift{11-5};
4401 let Inst{3-0} = shift{3-0};
4403 let Unpredictable{15-12} = 0b1111;
4406 def CMNzrsr : AI1<0b1011, (outs),
4407 (ins GPRnopc:$Rn, so_reg_reg:$shift), DPSoRegRegFrm, IIC_iCMPsr,
4408 "cmn", "\t$Rn, $shift",
4409 [(BinOpFrag<(ARMcmpZ node:$LHS,(ineg node:$RHS))>
4410 GPRnopc:$Rn, so_reg_reg:$shift)]>,
4411 Sched<[WriteCMPsr, ReadALU]> {
4416 let Inst{19-16} = Rn;
4417 let Inst{15-12} = 0b0000;
4418 let Inst{11-8} = shift{11-8};
4420 let Inst{6-5} = shift{6-5};
4422 let Inst{3-0} = shift{3-0};
4424 let Unpredictable{15-12} = 0b1111;
4429 def : ARMPat<(ARMcmp GPR:$src, mod_imm_neg:$imm),
4430 (CMNri GPR:$src, mod_imm_neg:$imm)>;
4432 def : ARMPat<(ARMcmpZ GPR:$src, mod_imm_neg:$imm),
4433 (CMNri GPR:$src, mod_imm_neg:$imm)>;
4435 // Note that TST/TEQ don't set all the same flags that CMP does!
4436 defm TST : AI1_cmp_irs<0b1000, "tst",
4437 IIC_iTSTi, IIC_iTSTr, IIC_iTSTsr,
4438 BinOpFrag<(ARMcmpZ (and_su node:$LHS, node:$RHS), 0)>, 1,
4439 "DecodeTSTInstruction">;
4440 defm TEQ : AI1_cmp_irs<0b1001, "teq",
4441 IIC_iTSTi, IIC_iTSTr, IIC_iTSTsr,
4442 BinOpFrag<(ARMcmpZ (xor_su node:$LHS, node:$RHS), 0)>, 1>;
4444 // Pseudo i64 compares for some floating point compares.
4445 let usesCustomInserter = 1, isBranch = 1, isTerminator = 1,
4447 def BCCi64 : PseudoInst<(outs),
4448 (ins i32imm:$cc, GPR:$lhs1, GPR:$lhs2, GPR:$rhs1, GPR:$rhs2, brtarget:$dst),
4450 [(ARMBcci64 imm:$cc, GPR:$lhs1, GPR:$lhs2, GPR:$rhs1, GPR:$rhs2, bb:$dst)]>,
4453 def BCCZi64 : PseudoInst<(outs),
4454 (ins i32imm:$cc, GPR:$lhs1, GPR:$lhs2, brtarget:$dst), IIC_Br,
4455 [(ARMBcci64 imm:$cc, GPR:$lhs1, GPR:$lhs2, 0, 0, bb:$dst)]>,
4457 } // usesCustomInserter
4460 // Conditional moves
4461 let hasSideEffects = 0 in {
4463 let isCommutable = 1, isSelect = 1 in
4464 def MOVCCr : ARMPseudoInst<(outs GPR:$Rd),
4465 (ins GPR:$false, GPR:$Rm, cmovpred:$p),
4467 [(set GPR:$Rd, (ARMcmov GPR:$false, GPR:$Rm,
4469 RegConstraint<"$false = $Rd">, Sched<[WriteALU]>;
4471 def MOVCCsi : ARMPseudoInst<(outs GPR:$Rd),
4472 (ins GPR:$false, so_reg_imm:$shift, cmovpred:$p),
4475 (ARMcmov GPR:$false, so_reg_imm:$shift,
4477 RegConstraint<"$false = $Rd">, Sched<[WriteALU]>;
4478 def MOVCCsr : ARMPseudoInst<(outs GPR:$Rd),
4479 (ins GPR:$false, so_reg_reg:$shift, cmovpred:$p),
4481 [(set GPR:$Rd, (ARMcmov GPR:$false, so_reg_reg:$shift,
4483 RegConstraint<"$false = $Rd">, Sched<[WriteALU]>;
4486 let isMoveImm = 1 in
4488 : ARMPseudoInst<(outs GPR:$Rd),
4489 (ins GPR:$false, imm0_65535_expr:$imm, cmovpred:$p),
4491 [(set GPR:$Rd, (ARMcmov GPR:$false, imm0_65535:$imm,
4493 RegConstraint<"$false = $Rd">, Requires<[IsARM, HasV6T2]>,
4496 let isMoveImm = 1 in
4497 def MOVCCi : ARMPseudoInst<(outs GPR:$Rd),
4498 (ins GPR:$false, mod_imm:$imm, cmovpred:$p),
4500 [(set GPR:$Rd, (ARMcmov GPR:$false, mod_imm:$imm,
4502 RegConstraint<"$false = $Rd">, Sched<[WriteALU]>;
4504 // Two instruction predicate mov immediate.
4505 let isMoveImm = 1 in
4507 : ARMPseudoInst<(outs GPR:$Rd),
4508 (ins GPR:$false, i32imm:$src, cmovpred:$p),
4510 [(set GPR:$Rd, (ARMcmov GPR:$false, imm:$src,
4512 RegConstraint<"$false = $Rd">, Requires<[IsARM, HasV6T2]>;
4514 let isMoveImm = 1 in
4515 def MVNCCi : ARMPseudoInst<(outs GPR:$Rd),
4516 (ins GPR:$false, mod_imm:$imm, cmovpred:$p),
4518 [(set GPR:$Rd, (ARMcmov GPR:$false, mod_imm_not:$imm,
4520 RegConstraint<"$false = $Rd">, Sched<[WriteALU]>;
4525 //===----------------------------------------------------------------------===//
4526 // Atomic operations intrinsics
4529 def MemBarrierOptOperand : AsmOperandClass {
4530 let Name = "MemBarrierOpt";
4531 let ParserMethod = "parseMemBarrierOptOperand";
4533 def memb_opt : Operand<i32> {
4534 let PrintMethod = "printMemBOption";
4535 let ParserMatchClass = MemBarrierOptOperand;
4536 let DecoderMethod = "DecodeMemBarrierOption";
4539 def InstSyncBarrierOptOperand : AsmOperandClass {
4540 let Name = "InstSyncBarrierOpt";
4541 let ParserMethod = "parseInstSyncBarrierOptOperand";
4543 def instsyncb_opt : Operand<i32> {
4544 let PrintMethod = "printInstSyncBOption";
4545 let ParserMatchClass = InstSyncBarrierOptOperand;
4546 let DecoderMethod = "DecodeInstSyncBarrierOption";
4549 // Memory barriers protect the atomic sequences
4550 let hasSideEffects = 1 in {
4551 def DMB : AInoP<(outs), (ins memb_opt:$opt), MiscFrm, NoItinerary,
4552 "dmb", "\t$opt", [(int_arm_dmb (i32 imm0_15:$opt))]>,
4553 Requires<[IsARM, HasDB]> {
4555 let Inst{31-4} = 0xf57ff05;
4556 let Inst{3-0} = opt;
4559 def DSB : AInoP<(outs), (ins memb_opt:$opt), MiscFrm, NoItinerary,
4560 "dsb", "\t$opt", [(int_arm_dsb (i32 imm0_15:$opt))]>,
4561 Requires<[IsARM, HasDB]> {
4563 let Inst{31-4} = 0xf57ff04;
4564 let Inst{3-0} = opt;
4567 // ISB has only full system option
4568 def ISB : AInoP<(outs), (ins instsyncb_opt:$opt), MiscFrm, NoItinerary,
4569 "isb", "\t$opt", [(int_arm_isb (i32 imm0_15:$opt))]>,
4570 Requires<[IsARM, HasDB]> {
4572 let Inst{31-4} = 0xf57ff06;
4573 let Inst{3-0} = opt;
4577 let usesCustomInserter = 1, Defs = [CPSR] in {
4579 // Pseudo instruction that combines movs + predicated rsbmi
4580 // to implement integer ABS
4581 def ABS : ARMPseudoInst<(outs GPR:$dst), (ins GPR:$src), 8, NoItinerary, []>;
4584 let usesCustomInserter = 1 in {
4585 def COPY_STRUCT_BYVAL_I32 : PseudoInst<
4586 (outs), (ins GPR:$dst, GPR:$src, i32imm:$size, i32imm:$alignment),
4588 [(ARMcopystructbyval GPR:$dst, GPR:$src, imm:$size, imm:$alignment)]>;
4591 let hasPostISelHook = 1, Constraints = "$newdst = $dst, $newsrc = $src" in {
4592 // %newsrc, %newdst = MEMCPY %dst, %src, N, ...N scratch regs...
4593 // Copies N registers worth of memory from address %src to address %dst
4594 // and returns the incremented addresses. N scratch register will
4595 // be attached for the copy to use.
4596 def MEMCPY : PseudoInst<
4597 (outs GPR:$newdst, GPR:$newsrc),
4598 (ins GPR:$dst, GPR:$src, i32imm:$nreg, variable_ops),
4600 [(set GPR:$newdst, GPR:$newsrc,
4601 (ARMmemcopy GPR:$dst, GPR:$src, imm:$nreg))]>;
4604 def ldrex_1 : PatFrag<(ops node:$ptr), (int_arm_ldrex node:$ptr), [{
4605 return cast<MemIntrinsicSDNode>(N)->getMemoryVT() == MVT::i8;
4608 def ldrex_2 : PatFrag<(ops node:$ptr), (int_arm_ldrex node:$ptr), [{
4609 return cast<MemIntrinsicSDNode>(N)->getMemoryVT() == MVT::i16;
4612 def ldrex_4 : PatFrag<(ops node:$ptr), (int_arm_ldrex node:$ptr), [{
4613 return cast<MemIntrinsicSDNode>(N)->getMemoryVT() == MVT::i32;
4616 def strex_1 : PatFrag<(ops node:$val, node:$ptr),
4617 (int_arm_strex node:$val, node:$ptr), [{
4618 return cast<MemIntrinsicSDNode>(N)->getMemoryVT() == MVT::i8;
4621 def strex_2 : PatFrag<(ops node:$val, node:$ptr),
4622 (int_arm_strex node:$val, node:$ptr), [{
4623 return cast<MemIntrinsicSDNode>(N)->getMemoryVT() == MVT::i16;
4626 def strex_4 : PatFrag<(ops node:$val, node:$ptr),
4627 (int_arm_strex node:$val, node:$ptr), [{
4628 return cast<MemIntrinsicSDNode>(N)->getMemoryVT() == MVT::i32;
4631 def ldaex_1 : PatFrag<(ops node:$ptr), (int_arm_ldaex node:$ptr), [{
4632 return cast<MemIntrinsicSDNode>(N)->getMemoryVT() == MVT::i8;
4635 def ldaex_2 : PatFrag<(ops node:$ptr), (int_arm_ldaex node:$ptr), [{
4636 return cast<MemIntrinsicSDNode>(N)->getMemoryVT() == MVT::i16;
4639 def ldaex_4 : PatFrag<(ops node:$ptr), (int_arm_ldaex node:$ptr), [{
4640 return cast<MemIntrinsicSDNode>(N)->getMemoryVT() == MVT::i32;
4643 def stlex_1 : PatFrag<(ops node:$val, node:$ptr),
4644 (int_arm_stlex node:$val, node:$ptr), [{
4645 return cast<MemIntrinsicSDNode>(N)->getMemoryVT() == MVT::i8;
4648 def stlex_2 : PatFrag<(ops node:$val, node:$ptr),
4649 (int_arm_stlex node:$val, node:$ptr), [{
4650 return cast<MemIntrinsicSDNode>(N)->getMemoryVT() == MVT::i16;
4653 def stlex_4 : PatFrag<(ops node:$val, node:$ptr),
4654 (int_arm_stlex node:$val, node:$ptr), [{
4655 return cast<MemIntrinsicSDNode>(N)->getMemoryVT() == MVT::i32;
4658 let mayLoad = 1 in {
4659 def LDREXB : AIldrex<0b10, (outs GPR:$Rt), (ins addr_offset_none:$addr),
4660 NoItinerary, "ldrexb", "\t$Rt, $addr",
4661 [(set GPR:$Rt, (ldrex_1 addr_offset_none:$addr))]>;
4662 def LDREXH : AIldrex<0b11, (outs GPR:$Rt), (ins addr_offset_none:$addr),
4663 NoItinerary, "ldrexh", "\t$Rt, $addr",
4664 [(set GPR:$Rt, (ldrex_2 addr_offset_none:$addr))]>;
4665 def LDREX : AIldrex<0b00, (outs GPR:$Rt), (ins addr_offset_none:$addr),
4666 NoItinerary, "ldrex", "\t$Rt, $addr",
4667 [(set GPR:$Rt, (ldrex_4 addr_offset_none:$addr))]>;
4668 let hasExtraDefRegAllocReq = 1 in
4669 def LDREXD : AIldrex<0b01, (outs GPRPairOp:$Rt),(ins addr_offset_none:$addr),
4670 NoItinerary, "ldrexd", "\t$Rt, $addr", []> {
4671 let DecoderMethod = "DecodeDoubleRegLoad";
4674 def LDAEXB : AIldaex<0b10, (outs GPR:$Rt), (ins addr_offset_none:$addr),
4675 NoItinerary, "ldaexb", "\t$Rt, $addr",
4676 [(set GPR:$Rt, (ldaex_1 addr_offset_none:$addr))]>;
4677 def LDAEXH : AIldaex<0b11, (outs GPR:$Rt), (ins addr_offset_none:$addr),
4678 NoItinerary, "ldaexh", "\t$Rt, $addr",
4679 [(set GPR:$Rt, (ldaex_2 addr_offset_none:$addr))]>;
4680 def LDAEX : AIldaex<0b00, (outs GPR:$Rt), (ins addr_offset_none:$addr),
4681 NoItinerary, "ldaex", "\t$Rt, $addr",
4682 [(set GPR:$Rt, (ldaex_4 addr_offset_none:$addr))]>;
4683 let hasExtraDefRegAllocReq = 1 in
4684 def LDAEXD : AIldaex<0b01, (outs GPRPairOp:$Rt),(ins addr_offset_none:$addr),
4685 NoItinerary, "ldaexd", "\t$Rt, $addr", []> {
4686 let DecoderMethod = "DecodeDoubleRegLoad";
4690 let mayStore = 1, Constraints = "@earlyclobber $Rd" in {
4691 def STREXB: AIstrex<0b10, (outs GPR:$Rd), (ins GPR:$Rt, addr_offset_none:$addr),
4692 NoItinerary, "strexb", "\t$Rd, $Rt, $addr",
4693 [(set GPR:$Rd, (strex_1 GPR:$Rt,
4694 addr_offset_none:$addr))]>;
4695 def STREXH: AIstrex<0b11, (outs GPR:$Rd), (ins GPR:$Rt, addr_offset_none:$addr),
4696 NoItinerary, "strexh", "\t$Rd, $Rt, $addr",
4697 [(set GPR:$Rd, (strex_2 GPR:$Rt,
4698 addr_offset_none:$addr))]>;
4699 def STREX : AIstrex<0b00, (outs GPR:$Rd), (ins GPR:$Rt, addr_offset_none:$addr),
4700 NoItinerary, "strex", "\t$Rd, $Rt, $addr",
4701 [(set GPR:$Rd, (strex_4 GPR:$Rt,
4702 addr_offset_none:$addr))]>;
4703 let hasExtraSrcRegAllocReq = 1 in
4704 def STREXD : AIstrex<0b01, (outs GPR:$Rd),
4705 (ins GPRPairOp:$Rt, addr_offset_none:$addr),
4706 NoItinerary, "strexd", "\t$Rd, $Rt, $addr", []> {
4707 let DecoderMethod = "DecodeDoubleRegStore";
4709 def STLEXB: AIstlex<0b10, (outs GPR:$Rd), (ins GPR:$Rt, addr_offset_none:$addr),
4710 NoItinerary, "stlexb", "\t$Rd, $Rt, $addr",
4712 (stlex_1 GPR:$Rt, addr_offset_none:$addr))]>;
4713 def STLEXH: AIstlex<0b11, (outs GPR:$Rd), (ins GPR:$Rt, addr_offset_none:$addr),
4714 NoItinerary, "stlexh", "\t$Rd, $Rt, $addr",
4716 (stlex_2 GPR:$Rt, addr_offset_none:$addr))]>;
4717 def STLEX : AIstlex<0b00, (outs GPR:$Rd), (ins GPR:$Rt, addr_offset_none:$addr),
4718 NoItinerary, "stlex", "\t$Rd, $Rt, $addr",
4720 (stlex_4 GPR:$Rt, addr_offset_none:$addr))]>;
4721 let hasExtraSrcRegAllocReq = 1 in
4722 def STLEXD : AIstlex<0b01, (outs GPR:$Rd),
4723 (ins GPRPairOp:$Rt, addr_offset_none:$addr),
4724 NoItinerary, "stlexd", "\t$Rd, $Rt, $addr", []> {
4725 let DecoderMethod = "DecodeDoubleRegStore";
4729 def CLREX : AXI<(outs), (ins), MiscFrm, NoItinerary, "clrex",
4731 Requires<[IsARM, HasV6K]> {
4732 let Inst{31-0} = 0b11110101011111111111000000011111;
4735 def : ARMPat<(strex_1 (and GPR:$Rt, 0xff), addr_offset_none:$addr),
4736 (STREXB GPR:$Rt, addr_offset_none:$addr)>;
4737 def : ARMPat<(strex_2 (and GPR:$Rt, 0xffff), addr_offset_none:$addr),
4738 (STREXH GPR:$Rt, addr_offset_none:$addr)>;
4740 def : ARMPat<(stlex_1 (and GPR:$Rt, 0xff), addr_offset_none:$addr),
4741 (STLEXB GPR:$Rt, addr_offset_none:$addr)>;
4742 def : ARMPat<(stlex_2 (and GPR:$Rt, 0xffff), addr_offset_none:$addr),
4743 (STLEXH GPR:$Rt, addr_offset_none:$addr)>;
4745 class acquiring_load<PatFrag base>
4746 : PatFrag<(ops node:$ptr), (base node:$ptr), [{
4747 AtomicOrdering Ordering = cast<AtomicSDNode>(N)->getOrdering();
4748 return isAtLeastAcquire(Ordering);
4751 def atomic_load_acquire_8 : acquiring_load<atomic_load_8>;
4752 def atomic_load_acquire_16 : acquiring_load<atomic_load_16>;
4753 def atomic_load_acquire_32 : acquiring_load<atomic_load_32>;
4755 class releasing_store<PatFrag base>
4756 : PatFrag<(ops node:$ptr, node:$val), (base node:$ptr, node:$val), [{
4757 AtomicOrdering Ordering = cast<AtomicSDNode>(N)->getOrdering();
4758 return isAtLeastRelease(Ordering);
4761 def atomic_store_release_8 : releasing_store<atomic_store_8>;
4762 def atomic_store_release_16 : releasing_store<atomic_store_16>;
4763 def atomic_store_release_32 : releasing_store<atomic_store_32>;
4765 let AddedComplexity = 8 in {
4766 def : ARMPat<(atomic_load_acquire_8 addr_offset_none:$addr), (LDAB addr_offset_none:$addr)>;
4767 def : ARMPat<(atomic_load_acquire_16 addr_offset_none:$addr), (LDAH addr_offset_none:$addr)>;
4768 def : ARMPat<(atomic_load_acquire_32 addr_offset_none:$addr), (LDA addr_offset_none:$addr)>;
4769 def : ARMPat<(atomic_store_release_8 addr_offset_none:$addr, GPR:$val), (STLB GPR:$val, addr_offset_none:$addr)>;
4770 def : ARMPat<(atomic_store_release_16 addr_offset_none:$addr, GPR:$val), (STLH GPR:$val, addr_offset_none:$addr)>;
4771 def : ARMPat<(atomic_store_release_32 addr_offset_none:$addr, GPR:$val), (STL GPR:$val, addr_offset_none:$addr)>;
4774 // SWP/SWPB are deprecated in V6/V7.
4775 let mayLoad = 1, mayStore = 1 in {
4776 def SWP : AIswp<0, (outs GPRnopc:$Rt),
4777 (ins GPRnopc:$Rt2, addr_offset_none:$addr), "swp", []>,
4779 def SWPB: AIswp<1, (outs GPRnopc:$Rt),
4780 (ins GPRnopc:$Rt2, addr_offset_none:$addr), "swpb", []>,
4784 //===----------------------------------------------------------------------===//
4785 // Coprocessor Instructions.
4788 def CDP : ABI<0b1110, (outs), (ins p_imm:$cop, imm0_15:$opc1,
4789 c_imm:$CRd, c_imm:$CRn, c_imm:$CRm, imm0_7:$opc2),
4790 NoItinerary, "cdp", "\t$cop, $opc1, $CRd, $CRn, $CRm, $opc2",
4791 [(int_arm_cdp imm:$cop, imm:$opc1, imm:$CRd, imm:$CRn,
4792 imm:$CRm, imm:$opc2)]>,
4801 let Inst{3-0} = CRm;
4803 let Inst{7-5} = opc2;
4804 let Inst{11-8} = cop;
4805 let Inst{15-12} = CRd;
4806 let Inst{19-16} = CRn;
4807 let Inst{23-20} = opc1;
4810 def CDP2 : ABXI<0b1110, (outs), (ins p_imm:$cop, imm0_15:$opc1,
4811 c_imm:$CRd, c_imm:$CRn, c_imm:$CRm, imm0_7:$opc2),
4812 NoItinerary, "cdp2\t$cop, $opc1, $CRd, $CRn, $CRm, $opc2",
4813 [(int_arm_cdp2 imm:$cop, imm:$opc1, imm:$CRd, imm:$CRn,
4814 imm:$CRm, imm:$opc2)]>,
4816 let Inst{31-28} = 0b1111;
4824 let Inst{3-0} = CRm;
4826 let Inst{7-5} = opc2;
4827 let Inst{11-8} = cop;
4828 let Inst{15-12} = CRd;
4829 let Inst{19-16} = CRn;
4830 let Inst{23-20} = opc1;
4833 class ACI<dag oops, dag iops, string opc, string asm,
4834 IndexMode im = IndexModeNone>
4835 : I<oops, iops, AddrModeNone, 4, im, BrFrm, NoItinerary,
4837 let Inst{27-25} = 0b110;
4839 class ACInoP<dag oops, dag iops, string opc, string asm,
4840 IndexMode im = IndexModeNone>
4841 : InoP<oops, iops, AddrModeNone, 4, im, BrFrm, NoItinerary,
4843 let Inst{31-28} = 0b1111;
4844 let Inst{27-25} = 0b110;
4846 multiclass LdStCop<bit load, bit Dbit, string asm> {
4847 def _OFFSET : ACI<(outs), (ins p_imm:$cop, c_imm:$CRd, addrmode5:$addr),
4848 asm, "\t$cop, $CRd, $addr"> {
4852 let Inst{24} = 1; // P = 1
4853 let Inst{23} = addr{8};
4854 let Inst{22} = Dbit;
4855 let Inst{21} = 0; // W = 0
4856 let Inst{20} = load;
4857 let Inst{19-16} = addr{12-9};
4858 let Inst{15-12} = CRd;
4859 let Inst{11-8} = cop;
4860 let Inst{7-0} = addr{7-0};
4861 let DecoderMethod = "DecodeCopMemInstruction";
4863 def _PRE : ACI<(outs), (ins p_imm:$cop, c_imm:$CRd, addrmode5_pre:$addr),
4864 asm, "\t$cop, $CRd, $addr!", IndexModePre> {
4868 let Inst{24} = 1; // P = 1
4869 let Inst{23} = addr{8};
4870 let Inst{22} = Dbit;
4871 let Inst{21} = 1; // W = 1
4872 let Inst{20} = load;
4873 let Inst{19-16} = addr{12-9};
4874 let Inst{15-12} = CRd;
4875 let Inst{11-8} = cop;
4876 let Inst{7-0} = addr{7-0};
4877 let DecoderMethod = "DecodeCopMemInstruction";
4879 def _POST: ACI<(outs), (ins p_imm:$cop, c_imm:$CRd, addr_offset_none:$addr,
4880 postidx_imm8s4:$offset),
4881 asm, "\t$cop, $CRd, $addr, $offset", IndexModePost> {
4886 let Inst{24} = 0; // P = 0
4887 let Inst{23} = offset{8};
4888 let Inst{22} = Dbit;
4889 let Inst{21} = 1; // W = 1
4890 let Inst{20} = load;
4891 let Inst{19-16} = addr;
4892 let Inst{15-12} = CRd;
4893 let Inst{11-8} = cop;
4894 let Inst{7-0} = offset{7-0};
4895 let DecoderMethod = "DecodeCopMemInstruction";
4897 def _OPTION : ACI<(outs),
4898 (ins p_imm:$cop, c_imm:$CRd, addr_offset_none:$addr,
4899 coproc_option_imm:$option),
4900 asm, "\t$cop, $CRd, $addr, $option"> {
4905 let Inst{24} = 0; // P = 0
4906 let Inst{23} = 1; // U = 1
4907 let Inst{22} = Dbit;
4908 let Inst{21} = 0; // W = 0
4909 let Inst{20} = load;
4910 let Inst{19-16} = addr;
4911 let Inst{15-12} = CRd;
4912 let Inst{11-8} = cop;
4913 let Inst{7-0} = option;
4914 let DecoderMethod = "DecodeCopMemInstruction";
4917 multiclass LdSt2Cop<bit load, bit Dbit, string asm> {
4918 def _OFFSET : ACInoP<(outs), (ins p_imm:$cop, c_imm:$CRd, addrmode5:$addr),
4919 asm, "\t$cop, $CRd, $addr"> {
4923 let Inst{24} = 1; // P = 1
4924 let Inst{23} = addr{8};
4925 let Inst{22} = Dbit;
4926 let Inst{21} = 0; // W = 0
4927 let Inst{20} = load;
4928 let Inst{19-16} = addr{12-9};
4929 let Inst{15-12} = CRd;
4930 let Inst{11-8} = cop;
4931 let Inst{7-0} = addr{7-0};
4932 let DecoderMethod = "DecodeCopMemInstruction";
4934 def _PRE : ACInoP<(outs), (ins p_imm:$cop, c_imm:$CRd, addrmode5_pre:$addr),
4935 asm, "\t$cop, $CRd, $addr!", IndexModePre> {
4939 let Inst{24} = 1; // P = 1
4940 let Inst{23} = addr{8};
4941 let Inst{22} = Dbit;
4942 let Inst{21} = 1; // W = 1
4943 let Inst{20} = load;
4944 let Inst{19-16} = addr{12-9};
4945 let Inst{15-12} = CRd;
4946 let Inst{11-8} = cop;
4947 let Inst{7-0} = addr{7-0};
4948 let DecoderMethod = "DecodeCopMemInstruction";
4950 def _POST: ACInoP<(outs), (ins p_imm:$cop, c_imm:$CRd, addr_offset_none:$addr,
4951 postidx_imm8s4:$offset),
4952 asm, "\t$cop, $CRd, $addr, $offset", IndexModePost> {
4957 let Inst{24} = 0; // P = 0
4958 let Inst{23} = offset{8};
4959 let Inst{22} = Dbit;
4960 let Inst{21} = 1; // W = 1
4961 let Inst{20} = load;
4962 let Inst{19-16} = addr;
4963 let Inst{15-12} = CRd;
4964 let Inst{11-8} = cop;
4965 let Inst{7-0} = offset{7-0};
4966 let DecoderMethod = "DecodeCopMemInstruction";
4968 def _OPTION : ACInoP<(outs),
4969 (ins p_imm:$cop, c_imm:$CRd, addr_offset_none:$addr,
4970 coproc_option_imm:$option),
4971 asm, "\t$cop, $CRd, $addr, $option"> {
4976 let Inst{24} = 0; // P = 0
4977 let Inst{23} = 1; // U = 1
4978 let Inst{22} = Dbit;
4979 let Inst{21} = 0; // W = 0
4980 let Inst{20} = load;
4981 let Inst{19-16} = addr;
4982 let Inst{15-12} = CRd;
4983 let Inst{11-8} = cop;
4984 let Inst{7-0} = option;
4985 let DecoderMethod = "DecodeCopMemInstruction";
4989 defm LDC : LdStCop <1, 0, "ldc">;
4990 defm LDCL : LdStCop <1, 1, "ldcl">;
4991 defm STC : LdStCop <0, 0, "stc">;
4992 defm STCL : LdStCop <0, 1, "stcl">;
4993 defm LDC2 : LdSt2Cop<1, 0, "ldc2">, Requires<[PreV8]>;
4994 defm LDC2L : LdSt2Cop<1, 1, "ldc2l">, Requires<[PreV8]>;
4995 defm STC2 : LdSt2Cop<0, 0, "stc2">, Requires<[PreV8]>;
4996 defm STC2L : LdSt2Cop<0, 1, "stc2l">, Requires<[PreV8]>;
4998 //===----------------------------------------------------------------------===//
4999 // Move between coprocessor and ARM core register.
5002 class MovRCopro<string opc, bit direction, dag oops, dag iops,
5004 : ABI<0b1110, oops, iops, NoItinerary, opc,
5005 "\t$cop, $opc1, $Rt, $CRn, $CRm, $opc2", pattern> {
5006 let Inst{20} = direction;
5016 let Inst{15-12} = Rt;
5017 let Inst{11-8} = cop;
5018 let Inst{23-21} = opc1;
5019 let Inst{7-5} = opc2;
5020 let Inst{3-0} = CRm;
5021 let Inst{19-16} = CRn;
5024 def MCR : MovRCopro<"mcr", 0 /* from ARM core register to coprocessor */,
5026 (ins p_imm:$cop, imm0_7:$opc1, GPR:$Rt, c_imm:$CRn,
5027 c_imm:$CRm, imm0_7:$opc2),
5028 [(int_arm_mcr imm:$cop, imm:$opc1, GPR:$Rt, imm:$CRn,
5029 imm:$CRm, imm:$opc2)]>,
5030 ComplexDeprecationPredicate<"MCR">;
5031 def : ARMInstAlias<"mcr${p} $cop, $opc1, $Rt, $CRn, $CRm",
5032 (MCR p_imm:$cop, imm0_7:$opc1, GPR:$Rt, c_imm:$CRn,
5033 c_imm:$CRm, 0, pred:$p)>;
5034 def MRC : MovRCopro<"mrc", 1 /* from coprocessor to ARM core register */,
5035 (outs GPRwithAPSR:$Rt),
5036 (ins p_imm:$cop, imm0_7:$opc1, c_imm:$CRn, c_imm:$CRm,
5038 def : ARMInstAlias<"mrc${p} $cop, $opc1, $Rt, $CRn, $CRm",
5039 (MRC GPRwithAPSR:$Rt, p_imm:$cop, imm0_7:$opc1, c_imm:$CRn,
5040 c_imm:$CRm, 0, pred:$p)>;
5042 def : ARMPat<(int_arm_mrc imm:$cop, imm:$opc1, imm:$CRn, imm:$CRm, imm:$opc2),
5043 (MRC imm:$cop, imm:$opc1, imm:$CRn, imm:$CRm, imm:$opc2)>;
5045 class MovRCopro2<string opc, bit direction, dag oops, dag iops,
5047 : ABXI<0b1110, oops, iops, NoItinerary,
5048 !strconcat(opc, "\t$cop, $opc1, $Rt, $CRn, $CRm, $opc2"), pattern> {
5049 let Inst{31-24} = 0b11111110;
5050 let Inst{20} = direction;
5060 let Inst{15-12} = Rt;
5061 let Inst{11-8} = cop;
5062 let Inst{23-21} = opc1;
5063 let Inst{7-5} = opc2;
5064 let Inst{3-0} = CRm;
5065 let Inst{19-16} = CRn;
5068 def MCR2 : MovRCopro2<"mcr2", 0 /* from ARM core register to coprocessor */,
5070 (ins p_imm:$cop, imm0_7:$opc1, GPR:$Rt, c_imm:$CRn,
5071 c_imm:$CRm, imm0_7:$opc2),
5072 [(int_arm_mcr2 imm:$cop, imm:$opc1, GPR:$Rt, imm:$CRn,
5073 imm:$CRm, imm:$opc2)]>,
5075 def : ARMInstAlias<"mcr2 $cop, $opc1, $Rt, $CRn, $CRm",
5076 (MCR2 p_imm:$cop, imm0_7:$opc1, GPR:$Rt, c_imm:$CRn,
5078 def MRC2 : MovRCopro2<"mrc2", 1 /* from coprocessor to ARM core register */,
5079 (outs GPRwithAPSR:$Rt),
5080 (ins p_imm:$cop, imm0_7:$opc1, c_imm:$CRn, c_imm:$CRm,
5083 def : ARMInstAlias<"mrc2 $cop, $opc1, $Rt, $CRn, $CRm",
5084 (MRC2 GPRwithAPSR:$Rt, p_imm:$cop, imm0_7:$opc1, c_imm:$CRn,
5087 def : ARMV5TPat<(int_arm_mrc2 imm:$cop, imm:$opc1, imm:$CRn,
5088 imm:$CRm, imm:$opc2),
5089 (MRC2 imm:$cop, imm:$opc1, imm:$CRn, imm:$CRm, imm:$opc2)>;
5091 class MovRRCopro<string opc, bit direction, dag oops, dag iops, list<dag>
5093 : ABI<0b1100, oops, iops, NoItinerary, opc, "\t$cop, $opc1, $Rt, $Rt2, $CRm",
5096 let Inst{23-21} = 0b010;
5097 let Inst{20} = direction;
5105 let Inst{15-12} = Rt;
5106 let Inst{19-16} = Rt2;
5107 let Inst{11-8} = cop;
5108 let Inst{7-4} = opc1;
5109 let Inst{3-0} = CRm;
5112 def MCRR : MovRRCopro<"mcrr", 0 /* from ARM core register to coprocessor */,
5113 (outs), (ins p_imm:$cop, imm0_15:$opc1, GPRnopc:$Rt,
5114 GPRnopc:$Rt2, c_imm:$CRm),
5115 [(int_arm_mcrr imm:$cop, imm:$opc1, GPRnopc:$Rt,
5116 GPRnopc:$Rt2, imm:$CRm)]>;
5117 def MRRC : MovRRCopro<"mrrc", 1 /* from coprocessor to ARM core register */,
5118 (outs GPRnopc:$Rt, GPRnopc:$Rt2),
5119 (ins p_imm:$cop, imm0_15:$opc1, c_imm:$CRm), []>;
5121 class MovRRCopro2<string opc, bit direction, list<dag> pattern = []>
5122 : ABXI<0b1100, (outs), (ins p_imm:$cop, imm0_15:$opc1,
5123 GPRnopc:$Rt, GPRnopc:$Rt2, c_imm:$CRm), NoItinerary,
5124 !strconcat(opc, "\t$cop, $opc1, $Rt, $Rt2, $CRm"), pattern>,
5126 let Inst{31-28} = 0b1111;
5127 let Inst{23-21} = 0b010;
5128 let Inst{20} = direction;
5136 let Inst{15-12} = Rt;
5137 let Inst{19-16} = Rt2;
5138 let Inst{11-8} = cop;
5139 let Inst{7-4} = opc1;
5140 let Inst{3-0} = CRm;
5142 let DecoderMethod = "DecodeMRRC2";
5145 def MCRR2 : MovRRCopro2<"mcrr2", 0 /* from ARM core register to coprocessor */,
5146 [(int_arm_mcrr2 imm:$cop, imm:$opc1, GPRnopc:$Rt,
5147 GPRnopc:$Rt2, imm:$CRm)]>;
5148 def MRRC2 : MovRRCopro2<"mrrc2", 1 /* from coprocessor to ARM core register */>;
5150 //===----------------------------------------------------------------------===//
5151 // Move between special register and ARM core register
5154 // Move to ARM core register from Special Register
5155 def MRS : ABI<0b0001, (outs GPRnopc:$Rd), (ins), NoItinerary,
5156 "mrs", "\t$Rd, apsr", []> {
5158 let Inst{23-16} = 0b00001111;
5159 let Unpredictable{19-17} = 0b111;
5161 let Inst{15-12} = Rd;
5163 let Inst{11-0} = 0b000000000000;
5164 let Unpredictable{11-0} = 0b110100001111;
5167 def : InstAlias<"mrs${p} $Rd, cpsr", (MRS GPRnopc:$Rd, pred:$p)>,
5170 // The MRSsys instruction is the MRS instruction from the ARM ARM,
5171 // section B9.3.9, with the R bit set to 1.
5172 def MRSsys : ABI<0b0001, (outs GPRnopc:$Rd), (ins), NoItinerary,
5173 "mrs", "\t$Rd, spsr", []> {
5175 let Inst{23-16} = 0b01001111;
5176 let Unpredictable{19-16} = 0b1111;
5178 let Inst{15-12} = Rd;
5180 let Inst{11-0} = 0b000000000000;
5181 let Unpredictable{11-0} = 0b110100001111;
5184 // However, the MRS (banked register) system instruction (ARMv7VE) *does* have a
5185 // separate encoding (distinguished by bit 5.
5186 def MRSbanked : ABI<0b0001, (outs GPRnopc:$Rd), (ins banked_reg:$banked),
5187 NoItinerary, "mrs", "\t$Rd, $banked", []>,
5188 Requires<[IsARM, HasVirtualization]> {
5193 let Inst{22} = banked{5}; // R bit
5194 let Inst{21-20} = 0b00;
5195 let Inst{19-16} = banked{3-0};
5196 let Inst{15-12} = Rd;
5197 let Inst{11-9} = 0b001;
5198 let Inst{8} = banked{4};
5199 let Inst{7-0} = 0b00000000;
5202 // Move from ARM core register to Special Register
5204 // No need to have both system and application versions of MSR (immediate) or
5205 // MSR (register), the encodings are the same and the assembly parser has no way
5206 // to distinguish between them. The mask operand contains the special register
5207 // (R Bit) in bit 4 and bits 3-0 contains the mask with the fields to be
5208 // accessed in the special register.
5209 def MSR : ABI<0b0001, (outs), (ins msr_mask:$mask, GPR:$Rn), NoItinerary,
5210 "msr", "\t$mask, $Rn", []> {
5215 let Inst{22} = mask{4}; // R bit
5216 let Inst{21-20} = 0b10;
5217 let Inst{19-16} = mask{3-0};
5218 let Inst{15-12} = 0b1111;
5219 let Inst{11-4} = 0b00000000;
5223 def MSRi : ABI<0b0011, (outs), (ins msr_mask:$mask, mod_imm:$imm), NoItinerary,
5224 "msr", "\t$mask, $imm", []> {
5229 let Inst{22} = mask{4}; // R bit
5230 let Inst{21-20} = 0b10;
5231 let Inst{19-16} = mask{3-0};
5232 let Inst{15-12} = 0b1111;
5233 let Inst{11-0} = imm;
5236 // However, the MSR (banked register) system instruction (ARMv7VE) *does* have a
5237 // separate encoding (distinguished by bit 5.
5238 def MSRbanked : ABI<0b0001, (outs), (ins banked_reg:$banked, GPRnopc:$Rn),
5239 NoItinerary, "msr", "\t$banked, $Rn", []>,
5240 Requires<[IsARM, HasVirtualization]> {
5245 let Inst{22} = banked{5}; // R bit
5246 let Inst{21-20} = 0b10;
5247 let Inst{19-16} = banked{3-0};
5248 let Inst{15-12} = 0b1111;
5249 let Inst{11-9} = 0b001;
5250 let Inst{8} = banked{4};
5251 let Inst{7-4} = 0b0000;
5255 // Dynamic stack allocation yields a _chkstk for Windows targets. These calls
5256 // are needed to probe the stack when allocating more than
5257 // 4k bytes in one go. Touching the stack at 4K increments is necessary to
5258 // ensure that the guard pages used by the OS virtual memory manager are
5259 // allocated in correct sequence.
5260 // The main point of having separate instruction are extra unmodelled effects
5261 // (compared to ordinary calls) like stack pointer change.
5263 def win__chkstk : SDNode<"ARMISD::WIN__CHKSTK", SDTNone,
5264 [SDNPHasChain, SDNPSideEffect]>;
5265 let usesCustomInserter = 1, Uses = [R4], Defs = [R4, SP] in
5266 def WIN__CHKSTK : PseudoInst<(outs), (ins), NoItinerary, [(win__chkstk)]>;
5268 def win__dbzchk : SDNode<"ARMISD::WIN__DBZCHK", SDT_WIN__DBZCHK,
5269 [SDNPHasChain, SDNPSideEffect, SDNPOutGlue]>;
5270 let usesCustomInserter = 1, Defs = [CPSR] in
5271 def WIN__DBZCHK : PseudoInst<(outs), (ins GPR:$divisor), NoItinerary,
5272 [(win__dbzchk GPR:$divisor)]>;
5274 //===----------------------------------------------------------------------===//
5278 // __aeabi_read_tp preserves the registers r1-r3.
5279 // This is a pseudo inst so that we can get the encoding right,
5280 // complete with fixup for the aeabi_read_tp function.
5281 // TPsoft is valid for ARM mode only, in case of Thumb mode a tTPsoft pattern
5282 // is defined in "ARMInstrThumb.td".
5284 Defs = [R0, R12, LR, CPSR], Uses = [SP] in {
5285 def TPsoft : ARMPseudoInst<(outs), (ins), 4, IIC_Br,
5286 [(set R0, ARMthread_pointer)]>, Sched<[WriteBr]>;
5289 //===----------------------------------------------------------------------===//
5290 // SJLJ Exception handling intrinsics
5291 // eh_sjlj_setjmp() is an instruction sequence to store the return
5292 // address and save #0 in R0 for the non-longjmp case.
5293 // Since by its nature we may be coming from some other function to get
5294 // here, and we're using the stack frame for the containing function to
5295 // save/restore registers, we can't keep anything live in regs across
5296 // the eh_sjlj_setjmp(), else it will almost certainly have been tromped upon
5297 // when we get here from a longjmp(). We force everything out of registers
5298 // except for our own input by listing the relevant registers in Defs. By
5299 // doing so, we also cause the prologue/epilogue code to actively preserve
5300 // all of the callee-saved resgisters, which is exactly what we want.
5301 // A constant value is passed in $val, and we use the location as a scratch.
5303 // These are pseudo-instructions and are lowered to individual MC-insts, so
5304 // no encoding information is necessary.
5306 [ R0, R1, R2, R3, R4, R5, R6, R7, R8, R9, R10, R11, R12, LR, CPSR,
5307 Q0, Q1, Q2, Q3, Q4, Q5, Q6, Q7, Q8, Q9, Q10, Q11, Q12, Q13, Q14, Q15 ],
5308 hasSideEffects = 1, isBarrier = 1, usesCustomInserter = 1 in {
5309 def Int_eh_sjlj_setjmp : PseudoInst<(outs), (ins GPR:$src, GPR:$val),
5311 [(set R0, (ARMeh_sjlj_setjmp GPR:$src, GPR:$val))]>,
5312 Requires<[IsARM, HasVFP2]>;
5316 [ R0, R1, R2, R3, R4, R5, R6, R7, R8, R9, R10, R11, R12, LR, CPSR ],
5317 hasSideEffects = 1, isBarrier = 1, usesCustomInserter = 1 in {
5318 def Int_eh_sjlj_setjmp_nofp : PseudoInst<(outs), (ins GPR:$src, GPR:$val),
5320 [(set R0, (ARMeh_sjlj_setjmp GPR:$src, GPR:$val))]>,
5321 Requires<[IsARM, NoVFP]>;
5324 // FIXME: Non-IOS version(s)
5325 let isBarrier = 1, hasSideEffects = 1, isTerminator = 1,
5326 Defs = [ R7, LR, SP ] in {
5327 def Int_eh_sjlj_longjmp : PseudoInst<(outs), (ins GPR:$src, GPR:$scratch),
5329 [(ARMeh_sjlj_longjmp GPR:$src, GPR:$scratch)]>,
5333 let isBarrier = 1, hasSideEffects = 1, usesCustomInserter = 1 in
5334 def Int_eh_sjlj_setup_dispatch : PseudoInst<(outs), (ins), NoItinerary,
5335 [(ARMeh_sjlj_setup_dispatch)]>;
5337 // eh.sjlj.dispatchsetup pseudo-instruction.
5338 // This pseudo is used for both ARM and Thumb. Any differences are handled when
5339 // the pseudo is expanded (which happens before any passes that need the
5340 // instruction size).
5341 let isBarrier = 1 in
5342 def Int_eh_sjlj_dispatchsetup : PseudoInst<(outs), (ins), NoItinerary, []>;
5345 //===----------------------------------------------------------------------===//
5346 // Non-Instruction Patterns
5349 // ARMv4 indirect branch using (MOVr PC, dst)
5350 let isBranch = 1, isTerminator = 1, isBarrier = 1, isIndirectBranch = 1 in
5351 def MOVPCRX : ARMPseudoExpand<(outs), (ins GPR:$dst),
5352 4, IIC_Br, [(brind GPR:$dst)],
5353 (MOVr PC, GPR:$dst, (ops 14, zero_reg), zero_reg)>,
5354 Requires<[IsARM, NoV4T]>, Sched<[WriteBr]>;
5356 // Large immediate handling.
5358 // 32-bit immediate using two piece mod_imms or movw + movt.
5359 // This is a single pseudo instruction, the benefit is that it can be remat'd
5360 // as a single unit instead of having to handle reg inputs.
5361 // FIXME: Remove this when we can do generalized remat.
5362 let isReMaterializable = 1, isMoveImm = 1 in
5363 def MOVi32imm : PseudoInst<(outs GPR:$dst), (ins i32imm:$src), IIC_iMOVix2,
5364 [(set GPR:$dst, (arm_i32imm:$src))]>,
5367 def LDRLIT_ga_abs : PseudoInst<(outs GPR:$dst), (ins i32imm:$src), IIC_iLoad_i,
5368 [(set GPR:$dst, (ARMWrapper tglobaladdr:$src))]>,
5369 Requires<[IsARM, DontUseMovt]>;
5371 // Pseudo instruction that combines movw + movt + add pc (if PIC).
5372 // It also makes it possible to rematerialize the instructions.
5373 // FIXME: Remove this when we can do generalized remat and when machine licm
5374 // can properly the instructions.
5375 let isReMaterializable = 1 in {
5376 def MOV_ga_pcrel : PseudoInst<(outs GPR:$dst), (ins i32imm:$addr),
5378 [(set GPR:$dst, (ARMWrapperPIC tglobaladdr:$addr))]>,
5379 Requires<[IsARM, UseMovt]>;
5381 def LDRLIT_ga_pcrel : PseudoInst<(outs GPR:$dst), (ins i32imm:$addr),
5384 (ARMWrapperPIC tglobaladdr:$addr))]>,
5385 Requires<[IsARM, DontUseMovt]>;
5387 let AddedComplexity = 10 in
5388 def LDRLIT_ga_pcrel_ldr : PseudoInst<(outs GPR:$dst), (ins i32imm:$addr),
5391 (load (ARMWrapperPIC tglobaladdr:$addr)))]>,
5392 Requires<[IsARM, DontUseMovt]>;
5394 let AddedComplexity = 10 in
5395 def MOV_ga_pcrel_ldr : PseudoInst<(outs GPR:$dst), (ins i32imm:$addr),
5397 [(set GPR:$dst, (load (ARMWrapperPIC tglobaladdr:$addr)))]>,
5398 Requires<[IsARM, UseMovt]>;
5399 } // isReMaterializable
5401 // The many different faces of TLS access.
5402 def : ARMPat<(ARMWrapper tglobaltlsaddr :$dst),
5403 (MOVi32imm tglobaltlsaddr :$dst)>,
5404 Requires<[IsARM, UseMovt]>;
5406 def : Pat<(ARMWrapper tglobaltlsaddr:$src),
5407 (LDRLIT_ga_abs tglobaltlsaddr:$src)>,
5408 Requires<[IsARM, DontUseMovt]>;
5410 def : Pat<(ARMWrapperPIC tglobaltlsaddr:$addr),
5411 (MOV_ga_pcrel tglobaltlsaddr:$addr)>, Requires<[IsARM, UseMovt]>;
5413 def : Pat<(ARMWrapperPIC tglobaltlsaddr:$addr),
5414 (LDRLIT_ga_pcrel tglobaltlsaddr:$addr)>,
5415 Requires<[IsARM, DontUseMovt]>;
5416 let AddedComplexity = 10 in
5417 def : Pat<(load (ARMWrapperPIC tglobaltlsaddr:$addr)),
5418 (MOV_ga_pcrel_ldr tglobaltlsaddr:$addr)>,
5419 Requires<[IsARM, UseMovt]>;
5422 // ConstantPool, GlobalAddress, and JumpTable
5423 def : ARMPat<(ARMWrapper tconstpool :$dst), (LEApcrel tconstpool :$dst)>;
5424 def : ARMPat<(ARMWrapper tglobaladdr :$dst), (MOVi32imm tglobaladdr :$dst)>,
5425 Requires<[IsARM, UseMovt]>;
5426 def : ARMPat<(ARMWrapperJT tjumptable:$dst),
5427 (LEApcrelJT tjumptable:$dst)>;
5429 // TODO: add,sub,and, 3-instr forms?
5431 // Tail calls. These patterns also apply to Thumb mode.
5432 def : Pat<(ARMtcret tcGPR:$dst), (TCRETURNri tcGPR:$dst)>;
5433 def : Pat<(ARMtcret (i32 tglobaladdr:$dst)), (TCRETURNdi texternalsym:$dst)>;
5434 def : Pat<(ARMtcret (i32 texternalsym:$dst)), (TCRETURNdi texternalsym:$dst)>;
5437 def : ARMPat<(ARMcall texternalsym:$func), (BL texternalsym:$func)>;
5438 def : ARMPat<(ARMcall_nolink texternalsym:$func),
5439 (BMOVPCB_CALL texternalsym:$func)>;
5441 // zextload i1 -> zextload i8
5442 def : ARMPat<(zextloadi1 addrmode_imm12:$addr), (LDRBi12 addrmode_imm12:$addr)>;
5443 def : ARMPat<(zextloadi1 ldst_so_reg:$addr), (LDRBrs ldst_so_reg:$addr)>;
5445 // extload -> zextload
5446 def : ARMPat<(extloadi1 addrmode_imm12:$addr), (LDRBi12 addrmode_imm12:$addr)>;
5447 def : ARMPat<(extloadi1 ldst_so_reg:$addr), (LDRBrs ldst_so_reg:$addr)>;
5448 def : ARMPat<(extloadi8 addrmode_imm12:$addr), (LDRBi12 addrmode_imm12:$addr)>;
5449 def : ARMPat<(extloadi8 ldst_so_reg:$addr), (LDRBrs ldst_so_reg:$addr)>;
5451 def : ARMPat<(extloadi16 addrmode3:$addr), (LDRH addrmode3:$addr)>;
5453 def : ARMPat<(extloadi8 addrmodepc:$addr), (PICLDRB addrmodepc:$addr)>;
5454 def : ARMPat<(extloadi16 addrmodepc:$addr), (PICLDRH addrmodepc:$addr)>;
5457 def : ARMV5TEPat<(mul (sra (shl GPR:$a, (i32 16)), (i32 16)),
5458 (sra (shl GPR:$b, (i32 16)), (i32 16))),
5459 (SMULBB GPR:$a, GPR:$b)>;
5460 def : ARMV5TEPat<(mul sext_16_node:$a, sext_16_node:$b),
5461 (SMULBB GPR:$a, GPR:$b)>;
5462 def : ARMV5TEPat<(mul (sra (shl GPR:$a, (i32 16)), (i32 16)),
5463 (sra GPR:$b, (i32 16))),
5464 (SMULBT GPR:$a, GPR:$b)>;
5465 def : ARMV5TEPat<(mul sext_16_node:$a, (sra GPR:$b, (i32 16))),
5466 (SMULBT GPR:$a, GPR:$b)>;
5467 def : ARMV5TEPat<(mul (sra GPR:$a, (i32 16)),
5468 (sra (shl GPR:$b, (i32 16)), (i32 16))),
5469 (SMULTB GPR:$a, GPR:$b)>;
5470 def : ARMV5TEPat<(mul (sra GPR:$a, (i32 16)), sext_16_node:$b),
5471 (SMULTB GPR:$a, GPR:$b)>;
5473 def : ARMV5MOPat<(add GPR:$acc,
5474 (mul (sra (shl GPR:$a, (i32 16)), (i32 16)),
5475 (sra (shl GPR:$b, (i32 16)), (i32 16)))),
5476 (SMLABB GPR:$a, GPR:$b, GPR:$acc)>;
5477 def : ARMV5MOPat<(add GPR:$acc,
5478 (mul sext_16_node:$a, sext_16_node:$b)),
5479 (SMLABB GPR:$a, GPR:$b, GPR:$acc)>;
5480 def : ARMV5MOPat<(add GPR:$acc,
5481 (mul (sra (shl GPR:$a, (i32 16)), (i32 16)),
5482 (sra GPR:$b, (i32 16)))),
5483 (SMLABT GPR:$a, GPR:$b, GPR:$acc)>;
5484 def : ARMV5MOPat<(add GPR:$acc,
5485 (mul sext_16_node:$a, (sra GPR:$b, (i32 16)))),
5486 (SMLABT GPR:$a, GPR:$b, GPR:$acc)>;
5487 def : ARMV5MOPat<(add GPR:$acc,
5488 (mul (sra GPR:$a, (i32 16)),
5489 (sra (shl GPR:$b, (i32 16)), (i32 16)))),
5490 (SMLATB GPR:$a, GPR:$b, GPR:$acc)>;
5491 def : ARMV5MOPat<(add GPR:$acc,
5492 (mul (sra GPR:$a, (i32 16)), sext_16_node:$b)),
5493 (SMLATB GPR:$a, GPR:$b, GPR:$acc)>;
5496 // Pre-v7 uses MCR for synchronization barriers.
5497 def : ARMPat<(ARMMemBarrierMCR GPR:$zero), (MCR 15, 0, GPR:$zero, 7, 10, 5)>,
5498 Requires<[IsARM, HasV6]>;
5500 // SXT/UXT with no rotate
5501 let AddedComplexity = 16 in {
5502 def : ARMV6Pat<(and GPR:$Src, 0x000000FF), (UXTB GPR:$Src, 0)>;
5503 def : ARMV6Pat<(and GPR:$Src, 0x0000FFFF), (UXTH GPR:$Src, 0)>;
5504 def : ARMV6Pat<(and GPR:$Src, 0x00FF00FF), (UXTB16 GPR:$Src, 0)>;
5505 def : ARMV6Pat<(add GPR:$Rn, (and GPR:$Rm, 0x00FF)),
5506 (UXTAB GPR:$Rn, GPR:$Rm, 0)>;
5507 def : ARMV6Pat<(add GPR:$Rn, (and GPR:$Rm, 0xFFFF)),
5508 (UXTAH GPR:$Rn, GPR:$Rm, 0)>;
5511 def : ARMV6Pat<(sext_inreg GPR:$Src, i8), (SXTB GPR:$Src, 0)>;
5512 def : ARMV6Pat<(sext_inreg GPR:$Src, i16), (SXTH GPR:$Src, 0)>;
5514 def : ARMV6Pat<(add GPR:$Rn, (sext_inreg GPRnopc:$Rm, i8)),
5515 (SXTAB GPR:$Rn, GPRnopc:$Rm, 0)>;
5516 def : ARMV6Pat<(add GPR:$Rn, (sext_inreg GPRnopc:$Rm, i16)),
5517 (SXTAH GPR:$Rn, GPRnopc:$Rm, 0)>;
5519 // Atomic load/store patterns
5520 def : ARMPat<(atomic_load_8 ldst_so_reg:$src),
5521 (LDRBrs ldst_so_reg:$src)>;
5522 def : ARMPat<(atomic_load_8 addrmode_imm12:$src),
5523 (LDRBi12 addrmode_imm12:$src)>;
5524 def : ARMPat<(atomic_load_16 addrmode3:$src),
5525 (LDRH addrmode3:$src)>;
5526 def : ARMPat<(atomic_load_32 ldst_so_reg:$src),
5527 (LDRrs ldst_so_reg:$src)>;
5528 def : ARMPat<(atomic_load_32 addrmode_imm12:$src),
5529 (LDRi12 addrmode_imm12:$src)>;
5530 def : ARMPat<(atomic_store_8 ldst_so_reg:$ptr, GPR:$val),
5531 (STRBrs GPR:$val, ldst_so_reg:$ptr)>;
5532 def : ARMPat<(atomic_store_8 addrmode_imm12:$ptr, GPR:$val),
5533 (STRBi12 GPR:$val, addrmode_imm12:$ptr)>;
5534 def : ARMPat<(atomic_store_16 addrmode3:$ptr, GPR:$val),
5535 (STRH GPR:$val, addrmode3:$ptr)>;
5536 def : ARMPat<(atomic_store_32 ldst_so_reg:$ptr, GPR:$val),
5537 (STRrs GPR:$val, ldst_so_reg:$ptr)>;
5538 def : ARMPat<(atomic_store_32 addrmode_imm12:$ptr, GPR:$val),
5539 (STRi12 GPR:$val, addrmode_imm12:$ptr)>;
5542 //===----------------------------------------------------------------------===//
5546 include "ARMInstrThumb.td"
5548 //===----------------------------------------------------------------------===//
5552 include "ARMInstrThumb2.td"
5554 //===----------------------------------------------------------------------===//
5555 // Floating Point Support
5558 include "ARMInstrVFP.td"
5560 //===----------------------------------------------------------------------===//
5561 // Advanced SIMD (NEON) Support
5564 include "ARMInstrNEON.td"
5566 //===----------------------------------------------------------------------===//
5567 // Assembler aliases
5571 def : InstAlias<"dmb", (DMB 0xf)>, Requires<[IsARM, HasDB]>;
5572 def : InstAlias<"dsb", (DSB 0xf)>, Requires<[IsARM, HasDB]>;
5573 def : InstAlias<"isb", (ISB 0xf)>, Requires<[IsARM, HasDB]>;
5575 // System instructions
5576 def : MnemonicAlias<"swi", "svc">;
5578 // Load / Store Multiple
5579 def : MnemonicAlias<"ldmfd", "ldm">;
5580 def : MnemonicAlias<"ldmia", "ldm">;
5581 def : MnemonicAlias<"ldmea", "ldmdb">;
5582 def : MnemonicAlias<"stmfd", "stmdb">;
5583 def : MnemonicAlias<"stmia", "stm">;
5584 def : MnemonicAlias<"stmea", "stm">;
5586 // PKHBT/PKHTB with default shift amount. PKHTB is equivalent to PKHBT when the
5587 // shift amount is zero (i.e., unspecified).
5588 def : InstAlias<"pkhbt${p} $Rd, $Rn, $Rm",
5589 (PKHBT GPRnopc:$Rd, GPRnopc:$Rn, GPRnopc:$Rm, 0, pred:$p)>,
5590 Requires<[IsARM, HasV6]>;
5591 def : InstAlias<"pkhtb${p} $Rd, $Rn, $Rm",
5592 (PKHBT GPRnopc:$Rd, GPRnopc:$Rn, GPRnopc:$Rm, 0, pred:$p)>,
5593 Requires<[IsARM, HasV6]>;
5595 // PUSH/POP aliases for STM/LDM
5596 def : ARMInstAlias<"push${p} $regs", (STMDB_UPD SP, pred:$p, reglist:$regs)>;
5597 def : ARMInstAlias<"pop${p} $regs", (LDMIA_UPD SP, pred:$p, reglist:$regs)>;
5599 // SSAT/USAT optional shift operand.
5600 def : ARMInstAlias<"ssat${p} $Rd, $sat_imm, $Rn",
5601 (SSAT GPRnopc:$Rd, imm1_32:$sat_imm, GPRnopc:$Rn, 0, pred:$p)>;
5602 def : ARMInstAlias<"usat${p} $Rd, $sat_imm, $Rn",
5603 (USAT GPRnopc:$Rd, imm0_31:$sat_imm, GPRnopc:$Rn, 0, pred:$p)>;
5606 // Extend instruction optional rotate operand.
5607 def : ARMInstAlias<"sxtab${p} $Rd, $Rn, $Rm",
5608 (SXTAB GPRnopc:$Rd, GPR:$Rn, GPRnopc:$Rm, 0, pred:$p)>;
5609 def : ARMInstAlias<"sxtah${p} $Rd, $Rn, $Rm",
5610 (SXTAH GPRnopc:$Rd, GPR:$Rn, GPRnopc:$Rm, 0, pred:$p)>;
5611 def : ARMInstAlias<"sxtab16${p} $Rd, $Rn, $Rm",
5612 (SXTAB16 GPRnopc:$Rd, GPR:$Rn, GPRnopc:$Rm, 0, pred:$p)>;
5613 def : ARMInstAlias<"sxtb${p} $Rd, $Rm",
5614 (SXTB GPRnopc:$Rd, GPRnopc:$Rm, 0, pred:$p)>;
5615 def : ARMInstAlias<"sxtb16${p} $Rd, $Rm",
5616 (SXTB16 GPRnopc:$Rd, GPRnopc:$Rm, 0, pred:$p)>;
5617 def : ARMInstAlias<"sxth${p} $Rd, $Rm",
5618 (SXTH GPRnopc:$Rd, GPRnopc:$Rm, 0, pred:$p)>;
5620 def : ARMInstAlias<"uxtab${p} $Rd, $Rn, $Rm",
5621 (UXTAB GPRnopc:$Rd, GPR:$Rn, GPRnopc:$Rm, 0, pred:$p)>;
5622 def : ARMInstAlias<"uxtah${p} $Rd, $Rn, $Rm",
5623 (UXTAH GPRnopc:$Rd, GPR:$Rn, GPRnopc:$Rm, 0, pred:$p)>;
5624 def : ARMInstAlias<"uxtab16${p} $Rd, $Rn, $Rm",
5625 (UXTAB16 GPRnopc:$Rd, GPR:$Rn, GPRnopc:$Rm, 0, pred:$p)>;
5626 def : ARMInstAlias<"uxtb${p} $Rd, $Rm",
5627 (UXTB GPRnopc:$Rd, GPRnopc:$Rm, 0, pred:$p)>;
5628 def : ARMInstAlias<"uxtb16${p} $Rd, $Rm",
5629 (UXTB16 GPRnopc:$Rd, GPRnopc:$Rm, 0, pred:$p)>;
5630 def : ARMInstAlias<"uxth${p} $Rd, $Rm",
5631 (UXTH GPRnopc:$Rd, GPRnopc:$Rm, 0, pred:$p)>;
5635 def : MnemonicAlias<"rfefa", "rfeda">;
5636 def : MnemonicAlias<"rfeea", "rfedb">;
5637 def : MnemonicAlias<"rfefd", "rfeia">;
5638 def : MnemonicAlias<"rfeed", "rfeib">;
5639 def : MnemonicAlias<"rfe", "rfeia">;
5642 def : MnemonicAlias<"srsfa", "srsib">;
5643 def : MnemonicAlias<"srsea", "srsia">;
5644 def : MnemonicAlias<"srsfd", "srsdb">;
5645 def : MnemonicAlias<"srsed", "srsda">;
5646 def : MnemonicAlias<"srs", "srsia">;
5649 def : MnemonicAlias<"qsubaddx", "qsax">;
5651 def : MnemonicAlias<"saddsubx", "sasx">;
5652 // SHASX == SHADDSUBX
5653 def : MnemonicAlias<"shaddsubx", "shasx">;
5654 // SHSAX == SHSUBADDX
5655 def : MnemonicAlias<"shsubaddx", "shsax">;
5657 def : MnemonicAlias<"ssubaddx", "ssax">;
5659 def : MnemonicAlias<"uaddsubx", "uasx">;
5660 // UHASX == UHADDSUBX
5661 def : MnemonicAlias<"uhaddsubx", "uhasx">;
5662 // UHSAX == UHSUBADDX
5663 def : MnemonicAlias<"uhsubaddx", "uhsax">;
5664 // UQASX == UQADDSUBX
5665 def : MnemonicAlias<"uqaddsubx", "uqasx">;
5666 // UQSAX == UQSUBADDX
5667 def : MnemonicAlias<"uqsubaddx", "uqsax">;
5669 def : MnemonicAlias<"usubaddx", "usax">;
5671 // "mov Rd, mod_imm_not" can be handled via "mvn" in assembly, just like
5673 def : ARMInstAlias<"mov${s}${p} $Rd, $imm",
5674 (MVNi rGPR:$Rd, mod_imm_not:$imm, pred:$p, cc_out:$s)>;
5675 def : ARMInstAlias<"mvn${s}${p} $Rd, $imm",
5676 (MOVi rGPR:$Rd, mod_imm_not:$imm, pred:$p, cc_out:$s)>;
5677 // Same for AND <--> BIC
5678 def : ARMInstAlias<"bic${s}${p} $Rd, $Rn, $imm",
5679 (ANDri GPR:$Rd, GPR:$Rn, mod_imm_not:$imm,
5680 pred:$p, cc_out:$s)>;
5681 def : ARMInstAlias<"bic${s}${p} $Rdn, $imm",
5682 (ANDri GPR:$Rdn, GPR:$Rdn, mod_imm_not:$imm,
5683 pred:$p, cc_out:$s)>;
5684 def : ARMInstAlias<"and${s}${p} $Rd, $Rn, $imm",
5685 (BICri GPR:$Rd, GPR:$Rn, mod_imm_not:$imm,
5686 pred:$p, cc_out:$s)>;
5687 def : ARMInstAlias<"and${s}${p} $Rdn, $imm",
5688 (BICri GPR:$Rdn, GPR:$Rdn, mod_imm_not:$imm,
5689 pred:$p, cc_out:$s)>;
5691 // Likewise, "add Rd, mod_imm_neg" -> sub
5692 def : ARMInstAlias<"add${s}${p} $Rd, $Rn, $imm",
5693 (SUBri GPR:$Rd, GPR:$Rn, mod_imm_neg:$imm, pred:$p, cc_out:$s)>;
5694 def : ARMInstAlias<"add${s}${p} $Rd, $imm",
5695 (SUBri GPR:$Rd, GPR:$Rd, mod_imm_neg:$imm, pred:$p, cc_out:$s)>;
5696 // Same for CMP <--> CMN via mod_imm_neg
5697 def : ARMInstAlias<"cmp${p} $Rd, $imm",
5698 (CMNri rGPR:$Rd, mod_imm_neg:$imm, pred:$p)>;
5699 def : ARMInstAlias<"cmn${p} $Rd, $imm",
5700 (CMPri rGPR:$Rd, mod_imm_neg:$imm, pred:$p)>;
5702 // The shifter forms of the MOV instruction are aliased to the ASR, LSL,
5703 // LSR, ROR, and RRX instructions.
5704 // FIXME: We need C++ parser hooks to map the alias to the MOV
5705 // encoding. It seems we should be able to do that sort of thing
5706 // in tblgen, but it could get ugly.
5707 let TwoOperandAliasConstraint = "$Rm = $Rd" in {
5708 def ASRi : ARMAsmPseudo<"asr${s}${p} $Rd, $Rm, $imm",
5709 (ins GPR:$Rd, GPR:$Rm, imm0_32:$imm, pred:$p,
5711 def LSRi : ARMAsmPseudo<"lsr${s}${p} $Rd, $Rm, $imm",
5712 (ins GPR:$Rd, GPR:$Rm, imm0_32:$imm, pred:$p,
5714 def LSLi : ARMAsmPseudo<"lsl${s}${p} $Rd, $Rm, $imm",
5715 (ins GPR:$Rd, GPR:$Rm, imm0_31:$imm, pred:$p,
5717 def RORi : ARMAsmPseudo<"ror${s}${p} $Rd, $Rm, $imm",
5718 (ins GPR:$Rd, GPR:$Rm, imm0_31:$imm, pred:$p,
5721 def RRXi : ARMAsmPseudo<"rrx${s}${p} $Rd, $Rm",
5722 (ins GPR:$Rd, GPR:$Rm, pred:$p, cc_out:$s)>;
5723 let TwoOperandAliasConstraint = "$Rn = $Rd" in {
5724 def ASRr : ARMAsmPseudo<"asr${s}${p} $Rd, $Rn, $Rm",
5725 (ins GPRnopc:$Rd, GPRnopc:$Rn, GPRnopc:$Rm, pred:$p,
5727 def LSRr : ARMAsmPseudo<"lsr${s}${p} $Rd, $Rn, $Rm",
5728 (ins GPRnopc:$Rd, GPRnopc:$Rn, GPRnopc:$Rm, pred:$p,
5730 def LSLr : ARMAsmPseudo<"lsl${s}${p} $Rd, $Rn, $Rm",
5731 (ins GPRnopc:$Rd, GPRnopc:$Rn, GPRnopc:$Rm, pred:$p,
5733 def RORr : ARMAsmPseudo<"ror${s}${p} $Rd, $Rn, $Rm",
5734 (ins GPRnopc:$Rd, GPRnopc:$Rn, GPRnopc:$Rm, pred:$p,
5738 // "neg" is and alias for "rsb rd, rn, #0"
5739 def : ARMInstAlias<"neg${s}${p} $Rd, $Rm",
5740 (RSBri GPR:$Rd, GPR:$Rm, 0, pred:$p, cc_out:$s)>;
5742 // Pre-v6, 'mov r0, r0' was used as a NOP encoding.
5743 def : InstAlias<"nop${p}", (MOVr R0, R0, pred:$p, zero_reg)>,
5744 Requires<[IsARM, NoV6]>;
5746 // MUL/UMLAL/SMLAL/UMULL/SMULL are available on all arches, but
5747 // the instruction definitions need difference constraints pre-v6.
5748 // Use these aliases for the assembly parsing on pre-v6.
5749 def : InstAlias<"mul${s}${p} $Rd, $Rn, $Rm",
5750 (MUL GPRnopc:$Rd, GPRnopc:$Rn, GPRnopc:$Rm, pred:$p, cc_out:$s)>,
5751 Requires<[IsARM, NoV6]>;
5752 def : InstAlias<"mla${s}${p} $Rd, $Rn, $Rm, $Ra",
5753 (MLA GPRnopc:$Rd, GPRnopc:$Rn, GPRnopc:$Rm, GPRnopc:$Ra,
5754 pred:$p, cc_out:$s)>,
5755 Requires<[IsARM, NoV6]>;
5756 def : InstAlias<"smlal${s}${p} $RdLo, $RdHi, $Rn, $Rm",
5757 (SMLAL GPR:$RdLo, GPR:$RdHi, GPR:$Rn, GPR:$Rm, pred:$p, cc_out:$s)>,
5758 Requires<[IsARM, NoV6]>;
5759 def : InstAlias<"umlal${s}${p} $RdLo, $RdHi, $Rn, $Rm",
5760 (UMLAL GPR:$RdLo, GPR:$RdHi, GPR:$Rn, GPR:$Rm, pred:$p, cc_out:$s)>,
5761 Requires<[IsARM, NoV6]>;
5762 def : InstAlias<"smull${s}${p} $RdLo, $RdHi, $Rn, $Rm",
5763 (SMULL GPR:$RdLo, GPR:$RdHi, GPR:$Rn, GPR:$Rm, pred:$p, cc_out:$s)>,
5764 Requires<[IsARM, NoV6]>;
5765 def : InstAlias<"umull${s}${p} $RdLo, $RdHi, $Rn, $Rm",
5766 (UMULL GPR:$RdLo, GPR:$RdHi, GPR:$Rn, GPR:$Rm, pred:$p, cc_out:$s)>,
5767 Requires<[IsARM, NoV6]>;
5769 // 'it' blocks in ARM mode just validate the predicates. The IT itself
5771 def ITasm : ARMAsmPseudo<"it$mask $cc", (ins it_pred:$cc, it_mask:$mask)>,
5772 ComplexDeprecationPredicate<"IT">;
5774 let mayLoad = 1, mayStore =1, hasSideEffects = 1 in
5775 def SPACE : PseudoInst<(outs GPR:$Rd), (ins i32imm:$size, GPR:$Rn),
5777 [(set GPR:$Rd, (int_arm_space imm:$size, GPR:$Rn))]>;