1 //===- ARMInstrInfo.td - Target Description for ARM Target -*- tablegen -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file describes the ARM instructions in TableGen format.
12 //===----------------------------------------------------------------------===//
14 //===----------------------------------------------------------------------===//
15 // ARM specific DAG Nodes.
19 def SDT_ARMCallSeqStart : SDCallSeqStart<[ SDTCisVT<0, i32> ]>;
20 def SDT_ARMCallSeqEnd : SDCallSeqEnd<[ SDTCisVT<0, i32>, SDTCisVT<1, i32> ]>;
22 def SDT_ARMSaveCallPC : SDTypeProfile<0, 1, []>;
24 def SDT_ARMcall : SDTypeProfile<0, -1, [SDTCisInt<0>]>;
26 def SDT_ARMCMov : SDTypeProfile<1, 3,
27 [SDTCisSameAs<0, 1>, SDTCisSameAs<0, 2>,
30 def SDT_ARMBrcond : SDTypeProfile<0, 2,
31 [SDTCisVT<0, OtherVT>, SDTCisVT<1, i32>]>;
33 def SDT_ARMBrJT : SDTypeProfile<0, 3,
34 [SDTCisPtrTy<0>, SDTCisVT<1, i32>,
37 def SDT_ARMBr2JT : SDTypeProfile<0, 4,
38 [SDTCisPtrTy<0>, SDTCisVT<1, i32>,
39 SDTCisVT<2, i32>, SDTCisVT<3, i32>]>;
41 def SDT_ARMCmp : SDTypeProfile<0, 2, [SDTCisSameAs<0, 1>]>;
43 def SDT_ARMPICAdd : SDTypeProfile<1, 2, [SDTCisSameAs<0, 1>,
44 SDTCisPtrTy<1>, SDTCisVT<2, i32>]>;
46 def SDT_ARMThreadPointer : SDTypeProfile<1, 0, [SDTCisPtrTy<0>]>;
47 def SDT_ARMEH_SJLJ_Setjmp : SDTypeProfile<1, 2, [SDTCisInt<0>, SDTCisPtrTy<1>,
50 def SDT_ARMMEMBARRIERV7 : SDTypeProfile<0, 0, []>;
51 def SDT_ARMSYNCBARRIERV7 : SDTypeProfile<0, 0, []>;
52 def SDT_ARMMEMBARRIERV6 : SDTypeProfile<0, 1, [SDTCisInt<0>]>;
53 def SDT_ARMSYNCBARRIERV6 : SDTypeProfile<0, 1, [SDTCisInt<0>]>;
56 def ARMWrapper : SDNode<"ARMISD::Wrapper", SDTIntUnaryOp>;
57 def ARMWrapperJT : SDNode<"ARMISD::WrapperJT", SDTIntBinOp>;
59 def ARMcallseq_start : SDNode<"ISD::CALLSEQ_START", SDT_ARMCallSeqStart,
60 [SDNPHasChain, SDNPOutFlag]>;
61 def ARMcallseq_end : SDNode<"ISD::CALLSEQ_END", SDT_ARMCallSeqEnd,
62 [SDNPHasChain, SDNPOptInFlag, SDNPOutFlag]>;
64 def ARMcall : SDNode<"ARMISD::CALL", SDT_ARMcall,
65 [SDNPHasChain, SDNPOptInFlag, SDNPOutFlag]>;
66 def ARMcall_pred : SDNode<"ARMISD::CALL_PRED", SDT_ARMcall,
67 [SDNPHasChain, SDNPOptInFlag, SDNPOutFlag]>;
68 def ARMcall_nolink : SDNode<"ARMISD::CALL_NOLINK", SDT_ARMcall,
69 [SDNPHasChain, SDNPOptInFlag, SDNPOutFlag]>;
71 def ARMretflag : SDNode<"ARMISD::RET_FLAG", SDTNone,
72 [SDNPHasChain, SDNPOptInFlag]>;
74 def ARMcmov : SDNode<"ARMISD::CMOV", SDT_ARMCMov,
76 def ARMcneg : SDNode<"ARMISD::CNEG", SDT_ARMCMov,
79 def ARMbrcond : SDNode<"ARMISD::BRCOND", SDT_ARMBrcond,
80 [SDNPHasChain, SDNPInFlag, SDNPOutFlag]>;
82 def ARMbrjt : SDNode<"ARMISD::BR_JT", SDT_ARMBrJT,
84 def ARMbr2jt : SDNode<"ARMISD::BR2_JT", SDT_ARMBr2JT,
87 def ARMcmp : SDNode<"ARMISD::CMP", SDT_ARMCmp,
90 def ARMcmpZ : SDNode<"ARMISD::CMPZ", SDT_ARMCmp,
91 [SDNPOutFlag,SDNPCommutative]>;
93 def ARMpic_add : SDNode<"ARMISD::PIC_ADD", SDT_ARMPICAdd>;
95 def ARMsrl_flag : SDNode<"ARMISD::SRL_FLAG", SDTIntUnaryOp, [SDNPOutFlag]>;
96 def ARMsra_flag : SDNode<"ARMISD::SRA_FLAG", SDTIntUnaryOp, [SDNPOutFlag]>;
97 def ARMrrx : SDNode<"ARMISD::RRX" , SDTIntUnaryOp, [SDNPInFlag ]>;
99 def ARMthread_pointer: SDNode<"ARMISD::THREAD_POINTER", SDT_ARMThreadPointer>;
100 def ARMeh_sjlj_setjmp: SDNode<"ARMISD::EH_SJLJ_SETJMP", SDT_ARMEH_SJLJ_Setjmp>;
102 def ARMMemBarrierV7 : SDNode<"ARMISD::MEMBARRIER", SDT_ARMMEMBARRIERV7,
104 def ARMSyncBarrierV7 : SDNode<"ARMISD::SYNCBARRIER", SDT_ARMMEMBARRIERV7,
106 def ARMMemBarrierV6 : SDNode<"ARMISD::MEMBARRIER", SDT_ARMMEMBARRIERV6,
108 def ARMSyncBarrierV6 : SDNode<"ARMISD::SYNCBARRIER", SDT_ARMMEMBARRIERV6,
111 def ARMrbit : SDNode<"ARMISD::RBIT", SDTIntUnaryOp>;
113 //===----------------------------------------------------------------------===//
114 // ARM Instruction Predicate Definitions.
116 def HasV5T : Predicate<"Subtarget->hasV5TOps()">;
117 def HasV5TE : Predicate<"Subtarget->hasV5TEOps()">;
118 def HasV6 : Predicate<"Subtarget->hasV6Ops()">;
119 def HasV6T2 : Predicate<"Subtarget->hasV6T2Ops()">;
120 def NoV6T2 : Predicate<"!Subtarget->hasV6T2Ops()">;
121 def HasV7 : Predicate<"Subtarget->hasV7Ops()">;
122 def HasVFP2 : Predicate<"Subtarget->hasVFP2()">;
123 def HasVFP3 : Predicate<"Subtarget->hasVFP3()">;
124 def HasNEON : Predicate<"Subtarget->hasNEON()">;
125 def UseNEONForFP : Predicate<"Subtarget->useNEONForSinglePrecisionFP()">;
126 def DontUseNEONForFP : Predicate<"!Subtarget->useNEONForSinglePrecisionFP()">;
127 def IsThumb : Predicate<"Subtarget->isThumb()">;
128 def IsThumb1Only : Predicate<"Subtarget->isThumb1Only()">;
129 def IsThumb2 : Predicate<"Subtarget->isThumb2()">;
130 def IsARM : Predicate<"!Subtarget->isThumb()">;
131 def IsDarwin : Predicate<"Subtarget->isTargetDarwin()">;
132 def IsNotDarwin : Predicate<"!Subtarget->isTargetDarwin()">;
133 def CarryDefIsUnused : Predicate<"!N->hasAnyUseOfValue(1)">;
134 def CarryDefIsUsed : Predicate<"N->hasAnyUseOfValue(1)">;
136 // FIXME: Eventually this will be just "hasV6T2Ops".
137 def UseMovt : Predicate<"Subtarget->useMovt()">;
138 def DontUseMovt : Predicate<"!Subtarget->useMovt()">;
140 //===----------------------------------------------------------------------===//
141 // ARM Flag Definitions.
143 class RegConstraint<string C> {
144 string Constraints = C;
147 //===----------------------------------------------------------------------===//
148 // ARM specific transformation functions and pattern fragments.
151 // so_imm_neg_XFORM - Return a so_imm value packed into the format described for
152 // so_imm_neg def below.
153 def so_imm_neg_XFORM : SDNodeXForm<imm, [{
154 return CurDAG->getTargetConstant(-(int)N->getZExtValue(), MVT::i32);
157 // so_imm_not_XFORM - Return a so_imm value packed into the format described for
158 // so_imm_not def below.
159 def so_imm_not_XFORM : SDNodeXForm<imm, [{
160 return CurDAG->getTargetConstant(~(int)N->getZExtValue(), MVT::i32);
163 // rot_imm predicate - True if the 32-bit immediate is equal to 8, 16, or 24.
164 def rot_imm : PatLeaf<(i32 imm), [{
165 int32_t v = (int32_t)N->getZExtValue();
166 return v == 8 || v == 16 || v == 24;
169 /// imm1_15 predicate - True if the 32-bit immediate is in the range [1,15].
170 def imm1_15 : PatLeaf<(i32 imm), [{
171 return (int32_t)N->getZExtValue() >= 1 && (int32_t)N->getZExtValue() < 16;
174 /// imm16_31 predicate - True if the 32-bit immediate is in the range [16,31].
175 def imm16_31 : PatLeaf<(i32 imm), [{
176 return (int32_t)N->getZExtValue() >= 16 && (int32_t)N->getZExtValue() < 32;
181 return ARM_AM::getSOImmVal(-(int)N->getZExtValue()) != -1;
182 }], so_imm_neg_XFORM>;
186 return ARM_AM::getSOImmVal(~(int)N->getZExtValue()) != -1;
187 }], so_imm_not_XFORM>;
189 // sext_16_node predicate - True if the SDNode is sign-extended 16 or more bits.
190 def sext_16_node : PatLeaf<(i32 GPR:$a), [{
191 return CurDAG->ComputeNumSignBits(SDValue(N,0)) >= 17;
194 /// bf_inv_mask_imm predicate - An AND mask to clear an arbitrary width bitfield
196 def bf_inv_mask_imm : Operand<i32>,
198 uint32_t v = (uint32_t)N->getZExtValue();
201 // there can be 1's on either or both "outsides", all the "inside"
203 unsigned int lsb = 0, msb = 31;
204 while (v & (1 << msb)) --msb;
205 while (v & (1 << lsb)) ++lsb;
206 for (unsigned int i = lsb; i <= msb; ++i) {
212 let PrintMethod = "printBitfieldInvMaskImmOperand";
215 /// Split a 32-bit immediate into two 16 bit parts.
216 def lo16 : SDNodeXForm<imm, [{
217 return CurDAG->getTargetConstant((uint32_t)N->getZExtValue() & 0xffff,
221 def hi16 : SDNodeXForm<imm, [{
222 return CurDAG->getTargetConstant((uint32_t)N->getZExtValue() >> 16, MVT::i32);
225 def lo16AllZero : PatLeaf<(i32 imm), [{
226 // Returns true if all low 16-bits are 0.
227 return (((uint32_t)N->getZExtValue()) & 0xFFFFUL) == 0;
230 /// imm0_65535 predicate - True if the 32-bit immediate is in the range
232 def imm0_65535 : PatLeaf<(i32 imm), [{
233 return (uint32_t)N->getZExtValue() < 65536;
236 class BinOpFrag<dag res> : PatFrag<(ops node:$LHS, node:$RHS), res>;
237 class UnOpFrag <dag res> : PatFrag<(ops node:$Src), res>;
239 //===----------------------------------------------------------------------===//
240 // Operand Definitions.
244 def brtarget : Operand<OtherVT>;
246 // A list of registers separated by comma. Used by load/store multiple.
247 def reglist : Operand<i32> {
248 let PrintMethod = "printRegisterList";
251 // An operand for the CONSTPOOL_ENTRY pseudo-instruction.
252 def cpinst_operand : Operand<i32> {
253 let PrintMethod = "printCPInstOperand";
256 def jtblock_operand : Operand<i32> {
257 let PrintMethod = "printJTBlockOperand";
259 def jt2block_operand : Operand<i32> {
260 let PrintMethod = "printJT2BlockOperand";
264 def pclabel : Operand<i32> {
265 let PrintMethod = "printPCLabel";
268 // shifter_operand operands: so_reg and so_imm.
269 def so_reg : Operand<i32>, // reg reg imm
270 ComplexPattern<i32, 3, "SelectShifterOperandReg",
271 [shl,srl,sra,rotr]> {
272 let PrintMethod = "printSORegOperand";
273 let MIOperandInfo = (ops GPR, GPR, i32imm);
276 // so_imm - Match a 32-bit shifter_operand immediate operand, which is an
277 // 8-bit immediate rotated by an arbitrary number of bits. so_imm values are
278 // represented in the imm field in the same 12-bit form that they are encoded
279 // into so_imm instructions: the 8-bit immediate is the least significant bits
280 // [bits 0-7], the 4-bit shift amount is the next 4 bits [bits 8-11].
281 def so_imm : Operand<i32>,
283 return ARM_AM::getSOImmVal(N->getZExtValue()) != -1;
285 let PrintMethod = "printSOImmOperand";
288 // Break so_imm's up into two pieces. This handles immediates with up to 16
289 // bits set in them. This uses so_imm2part to match and so_imm2part_[12] to
290 // get the first/second pieces.
291 def so_imm2part : Operand<i32>,
293 return ARM_AM::isSOImmTwoPartVal((unsigned)N->getZExtValue());
295 let PrintMethod = "printSOImm2PartOperand";
298 def so_imm2part_1 : SDNodeXForm<imm, [{
299 unsigned V = ARM_AM::getSOImmTwoPartFirst((unsigned)N->getZExtValue());
300 return CurDAG->getTargetConstant(V, MVT::i32);
303 def so_imm2part_2 : SDNodeXForm<imm, [{
304 unsigned V = ARM_AM::getSOImmTwoPartSecond((unsigned)N->getZExtValue());
305 return CurDAG->getTargetConstant(V, MVT::i32);
308 def so_neg_imm2part : Operand<i32>, PatLeaf<(imm), [{
309 return ARM_AM::isSOImmTwoPartVal(-(int)N->getZExtValue());
311 let PrintMethod = "printSOImm2PartOperand";
314 def so_neg_imm2part_1 : SDNodeXForm<imm, [{
315 unsigned V = ARM_AM::getSOImmTwoPartFirst(-(int)N->getZExtValue());
316 return CurDAG->getTargetConstant(V, MVT::i32);
319 def so_neg_imm2part_2 : SDNodeXForm<imm, [{
320 unsigned V = ARM_AM::getSOImmTwoPartSecond(-(int)N->getZExtValue());
321 return CurDAG->getTargetConstant(V, MVT::i32);
324 /// imm0_31 predicate - True if the 32-bit immediate is in the range [0,31].
325 def imm0_31 : Operand<i32>, PatLeaf<(imm), [{
326 return (int32_t)N->getZExtValue() < 32;
329 // Define ARM specific addressing modes.
331 // addrmode2 := reg +/- reg shop imm
332 // addrmode2 := reg +/- imm12
334 def addrmode2 : Operand<i32>,
335 ComplexPattern<i32, 3, "SelectAddrMode2", []> {
336 let PrintMethod = "printAddrMode2Operand";
337 let MIOperandInfo = (ops GPR:$base, GPR:$offsreg, i32imm:$offsimm);
340 def am2offset : Operand<i32>,
341 ComplexPattern<i32, 2, "SelectAddrMode2Offset", []> {
342 let PrintMethod = "printAddrMode2OffsetOperand";
343 let MIOperandInfo = (ops GPR, i32imm);
346 // addrmode3 := reg +/- reg
347 // addrmode3 := reg +/- imm8
349 def addrmode3 : Operand<i32>,
350 ComplexPattern<i32, 3, "SelectAddrMode3", []> {
351 let PrintMethod = "printAddrMode3Operand";
352 let MIOperandInfo = (ops GPR:$base, GPR:$offsreg, i32imm:$offsimm);
355 def am3offset : Operand<i32>,
356 ComplexPattern<i32, 2, "SelectAddrMode3Offset", []> {
357 let PrintMethod = "printAddrMode3OffsetOperand";
358 let MIOperandInfo = (ops GPR, i32imm);
361 // addrmode4 := reg, <mode|W>
363 def addrmode4 : Operand<i32>,
364 ComplexPattern<i32, 2, "SelectAddrMode4", []> {
365 let PrintMethod = "printAddrMode4Operand";
366 let MIOperandInfo = (ops GPR, i32imm);
369 // addrmode5 := reg +/- imm8*4
371 def addrmode5 : Operand<i32>,
372 ComplexPattern<i32, 2, "SelectAddrMode5", []> {
373 let PrintMethod = "printAddrMode5Operand";
374 let MIOperandInfo = (ops GPR, i32imm);
377 // addrmode6 := reg with optional writeback
379 def addrmode6 : Operand<i32>,
380 ComplexPattern<i32, 4, "SelectAddrMode6", []> {
381 let PrintMethod = "printAddrMode6Operand";
382 let MIOperandInfo = (ops GPR:$addr, GPR:$upd, i32imm, i32imm);
385 // addrmodepc := pc + reg
387 def addrmodepc : Operand<i32>,
388 ComplexPattern<i32, 2, "SelectAddrModePC", []> {
389 let PrintMethod = "printAddrModePCOperand";
390 let MIOperandInfo = (ops GPR, i32imm);
393 def nohash_imm : Operand<i32> {
394 let PrintMethod = "printNoHashImmediate";
397 //===----------------------------------------------------------------------===//
399 include "ARMInstrFormats.td"
401 //===----------------------------------------------------------------------===//
402 // Multiclass helpers...
405 /// AsI1_bin_irs - Defines a set of (op r, {so_imm|r|so_reg}) patterns for a
406 /// binop that produces a value.
407 multiclass AsI1_bin_irs<bits<4> opcod, string opc, PatFrag opnode,
408 bit Commutable = 0> {
409 def ri : AsI1<opcod, (outs GPR:$dst), (ins GPR:$a, so_imm:$b), DPFrm,
410 IIC_iALUi, opc, "\t$dst, $a, $b",
411 [(set GPR:$dst, (opnode GPR:$a, so_imm:$b))]> {
414 def rr : AsI1<opcod, (outs GPR:$dst), (ins GPR:$a, GPR:$b), DPFrm,
415 IIC_iALUr, opc, "\t$dst, $a, $b",
416 [(set GPR:$dst, (opnode GPR:$a, GPR:$b))]> {
417 let Inst{11-4} = 0b00000000;
419 let isCommutable = Commutable;
421 def rs : AsI1<opcod, (outs GPR:$dst), (ins GPR:$a, so_reg:$b), DPSoRegFrm,
422 IIC_iALUsr, opc, "\t$dst, $a, $b",
423 [(set GPR:$dst, (opnode GPR:$a, so_reg:$b))]> {
428 /// AI1_bin_s_irs - Similar to AsI1_bin_irs except it sets the 's' bit so the
429 /// instruction modifies the CPSR register.
430 let Defs = [CPSR] in {
431 multiclass AI1_bin_s_irs<bits<4> opcod, string opc, PatFrag opnode,
432 bit Commutable = 0> {
433 def ri : AI1<opcod, (outs GPR:$dst), (ins GPR:$a, so_imm:$b), DPFrm,
434 IIC_iALUi, opc, "\t$dst, $a, $b",
435 [(set GPR:$dst, (opnode GPR:$a, so_imm:$b))]> {
439 def rr : AI1<opcod, (outs GPR:$dst), (ins GPR:$a, GPR:$b), DPFrm,
440 IIC_iALUr, opc, "\t$dst, $a, $b",
441 [(set GPR:$dst, (opnode GPR:$a, GPR:$b))]> {
442 let isCommutable = Commutable;
443 let Inst{11-4} = 0b00000000;
447 def rs : AI1<opcod, (outs GPR:$dst), (ins GPR:$a, so_reg:$b), DPSoRegFrm,
448 IIC_iALUsr, opc, "\t$dst, $a, $b",
449 [(set GPR:$dst, (opnode GPR:$a, so_reg:$b))]> {
456 /// AI1_cmp_irs - Defines a set of (op r, {so_imm|r|so_reg}) cmp / test
457 /// patterns. Similar to AsI1_bin_irs except the instruction does not produce
458 /// a explicit result, only implicitly set CPSR.
459 let Defs = [CPSR] in {
460 multiclass AI1_cmp_irs<bits<4> opcod, string opc, PatFrag opnode,
461 bit Commutable = 0> {
462 def ri : AI1<opcod, (outs), (ins GPR:$a, so_imm:$b), DPFrm, IIC_iCMPi,
464 [(opnode GPR:$a, so_imm:$b)]> {
468 def rr : AI1<opcod, (outs), (ins GPR:$a, GPR:$b), DPFrm, IIC_iCMPr,
470 [(opnode GPR:$a, GPR:$b)]> {
471 let Inst{11-4} = 0b00000000;
474 let isCommutable = Commutable;
476 def rs : AI1<opcod, (outs), (ins GPR:$a, so_reg:$b), DPSoRegFrm, IIC_iCMPsr,
478 [(opnode GPR:$a, so_reg:$b)]> {
485 /// AI_unary_rrot - A unary operation with two forms: one whose operand is a
486 /// register and one whose operand is a register rotated by 8/16/24.
487 /// FIXME: Remove the 'r' variant. Its rot_imm is zero.
488 multiclass AI_unary_rrot<bits<8> opcod, string opc, PatFrag opnode> {
489 def r : AExtI<opcod, (outs GPR:$dst), (ins GPR:$src),
490 IIC_iUNAr, opc, "\t$dst, $src",
491 [(set GPR:$dst, (opnode GPR:$src))]>,
492 Requires<[IsARM, HasV6]> {
493 let Inst{11-10} = 0b00;
494 let Inst{19-16} = 0b1111;
496 def r_rot : AExtI<opcod, (outs GPR:$dst), (ins GPR:$src, i32imm:$rot),
497 IIC_iUNAsi, opc, "\t$dst, $src, ror $rot",
498 [(set GPR:$dst, (opnode (rotr GPR:$src, rot_imm:$rot)))]>,
499 Requires<[IsARM, HasV6]> {
500 let Inst{19-16} = 0b1111;
504 /// AI_bin_rrot - A binary operation with two forms: one whose operand is a
505 /// register and one whose operand is a register rotated by 8/16/24.
506 multiclass AI_bin_rrot<bits<8> opcod, string opc, PatFrag opnode> {
507 def rr : AExtI<opcod, (outs GPR:$dst), (ins GPR:$LHS, GPR:$RHS),
508 IIC_iALUr, opc, "\t$dst, $LHS, $RHS",
509 [(set GPR:$dst, (opnode GPR:$LHS, GPR:$RHS))]>,
510 Requires<[IsARM, HasV6]> {
511 let Inst{11-10} = 0b00;
513 def rr_rot : AExtI<opcod, (outs GPR:$dst), (ins GPR:$LHS, GPR:$RHS, i32imm:$rot),
514 IIC_iALUsi, opc, "\t$dst, $LHS, $RHS, ror $rot",
515 [(set GPR:$dst, (opnode GPR:$LHS,
516 (rotr GPR:$RHS, rot_imm:$rot)))]>,
517 Requires<[IsARM, HasV6]>;
520 /// AI1_adde_sube_irs - Define instructions and patterns for adde and sube.
521 let Uses = [CPSR] in {
522 multiclass AI1_adde_sube_irs<bits<4> opcod, string opc, PatFrag opnode,
523 bit Commutable = 0> {
524 def ri : AsI1<opcod, (outs GPR:$dst), (ins GPR:$a, so_imm:$b),
525 DPFrm, IIC_iALUi, opc, "\t$dst, $a, $b",
526 [(set GPR:$dst, (opnode GPR:$a, so_imm:$b))]>,
527 Requires<[IsARM, CarryDefIsUnused]> {
530 def rr : AsI1<opcod, (outs GPR:$dst), (ins GPR:$a, GPR:$b),
531 DPFrm, IIC_iALUr, opc, "\t$dst, $a, $b",
532 [(set GPR:$dst, (opnode GPR:$a, GPR:$b))]>,
533 Requires<[IsARM, CarryDefIsUnused]> {
534 let isCommutable = Commutable;
535 let Inst{11-4} = 0b00000000;
538 def rs : AsI1<opcod, (outs GPR:$dst), (ins GPR:$a, so_reg:$b),
539 DPSoRegFrm, IIC_iALUsr, opc, "\t$dst, $a, $b",
540 [(set GPR:$dst, (opnode GPR:$a, so_reg:$b))]>,
541 Requires<[IsARM, CarryDefIsUnused]> {
545 // Carry setting variants
546 let Defs = [CPSR] in {
547 multiclass AI1_adde_sube_s_irs<bits<4> opcod, string opc, PatFrag opnode,
548 bit Commutable = 0> {
549 def Sri : AXI1<opcod, (outs GPR:$dst), (ins GPR:$a, so_imm:$b),
550 DPFrm, IIC_iALUi, !strconcat(opc, "\t$dst, $a, $b"),
551 [(set GPR:$dst, (opnode GPR:$a, so_imm:$b))]>,
552 Requires<[IsARM, CarryDefIsUsed]> {
557 def Srr : AXI1<opcod, (outs GPR:$dst), (ins GPR:$a, GPR:$b),
558 DPFrm, IIC_iALUr, !strconcat(opc, "\t$dst, $a, $b"),
559 [(set GPR:$dst, (opnode GPR:$a, GPR:$b))]>,
560 Requires<[IsARM, CarryDefIsUsed]> {
562 let Inst{11-4} = 0b00000000;
566 def Srs : AXI1<opcod, (outs GPR:$dst), (ins GPR:$a, so_reg:$b),
567 DPSoRegFrm, IIC_iALUsr, !strconcat(opc, "\t$dst, $a, $b"),
568 [(set GPR:$dst, (opnode GPR:$a, so_reg:$b))]>,
569 Requires<[IsARM, CarryDefIsUsed]> {
578 //===----------------------------------------------------------------------===//
580 //===----------------------------------------------------------------------===//
582 //===----------------------------------------------------------------------===//
583 // Miscellaneous Instructions.
586 /// CONSTPOOL_ENTRY - This instruction represents a floating constant pool in
587 /// the function. The first operand is the ID# for this instruction, the second
588 /// is the index into the MachineConstantPool that this is, the third is the
589 /// size in bytes of this constant pool entry.
590 let neverHasSideEffects = 1, isNotDuplicable = 1 in
591 def CONSTPOOL_ENTRY :
592 PseudoInst<(outs), (ins cpinst_operand:$instid, cpinst_operand:$cpidx,
593 i32imm:$size), NoItinerary,
594 "${instid:label} ${cpidx:cpentry}", []>;
596 let Defs = [SP], Uses = [SP] in {
598 PseudoInst<(outs), (ins i32imm:$amt1, i32imm:$amt2, pred:$p), NoItinerary,
599 "@ ADJCALLSTACKUP $amt1",
600 [(ARMcallseq_end timm:$amt1, timm:$amt2)]>;
602 def ADJCALLSTACKDOWN :
603 PseudoInst<(outs), (ins i32imm:$amt, pred:$p), NoItinerary,
604 "@ ADJCALLSTACKDOWN $amt",
605 [(ARMcallseq_start timm:$amt)]>;
608 def NOP : AI<(outs), (ins), MiscFrm, NoItinerary, "nop", "",
609 [/* For disassembly only; pattern left blank */]>,
610 Requires<[IsARM, HasV6T2]> {
611 let Inst{27-16} = 0b001100100000;
612 let Inst{7-0} = 0b00000000;
615 def YIELD : AI<(outs), (ins), MiscFrm, NoItinerary, "yield", "",
616 [/* For disassembly only; pattern left blank */]>,
617 Requires<[IsARM, HasV6T2]> {
618 let Inst{27-16} = 0b001100100000;
619 let Inst{7-0} = 0b00000001;
622 def WFE : AI<(outs), (ins), MiscFrm, NoItinerary, "wfe", "",
623 [/* For disassembly only; pattern left blank */]>,
624 Requires<[IsARM, HasV6T2]> {
625 let Inst{27-16} = 0b001100100000;
626 let Inst{7-0} = 0b00000010;
629 def WFI : AI<(outs), (ins), MiscFrm, NoItinerary, "wfi", "",
630 [/* For disassembly only; pattern left blank */]>,
631 Requires<[IsARM, HasV6T2]> {
632 let Inst{27-16} = 0b001100100000;
633 let Inst{7-0} = 0b00000011;
636 def SEV : AI<(outs), (ins), MiscFrm, NoItinerary, "sev", "",
637 [/* For disassembly only; pattern left blank */]>,
638 Requires<[IsARM, HasV6T2]> {
639 let Inst{27-16} = 0b001100100000;
640 let Inst{7-0} = 0b00000100;
643 // The i32imm operand $val can be used by a debugger to store more information
644 // about the breakpoint.
645 def BKPT : AI<(outs), (ins i32imm:$val), MiscFrm, NoItinerary, "bkpt", "\t$val",
646 [/* For disassembly only; pattern left blank */]>,
648 let Inst{27-20} = 0b00010010;
649 let Inst{7-4} = 0b0111;
652 // Change Processor State is a system instruction -- for disassembly only.
653 // The singleton $opt operand contains the following information:
654 // opt{4-0} = mode from Inst{4-0}
655 // opt{5} = changemode from Inst{17}
656 // opt{8-6} = AIF from Inst{8-6}
657 // opt{10-9} = imod from Inst{19-18} with 0b10 as enable and 0b11 as disable
658 def CPS : AXI<(outs),(ins i32imm:$opt), MiscFrm, NoItinerary, "cps${opt:cps}",
659 [/* For disassembly only; pattern left blank */]>,
661 let Inst{31-28} = 0b1111;
662 let Inst{27-20} = 0b00010000;
667 def SETENDBE : AXI<(outs),(ins), MiscFrm, NoItinerary, "setend\tbe",
668 [/* For disassembly only; pattern left blank */]>,
670 let Inst{31-28} = 0b1111;
671 let Inst{27-20} = 0b00010000;
674 let Inst{7-4} = 0b0000;
677 def SETENDLE : AXI<(outs),(ins), MiscFrm, NoItinerary, "setend\tle",
678 [/* For disassembly only; pattern left blank */]>,
680 let Inst{31-28} = 0b1111;
681 let Inst{27-20} = 0b00010000;
684 let Inst{7-4} = 0b0000;
687 def DBG : AI<(outs), (ins i32imm:$opt), MiscFrm, NoItinerary, "dbg", "\t$opt",
688 [/* For disassembly only; pattern left blank */]>,
689 Requires<[IsARM, HasV7]> {
690 let Inst{27-16} = 0b001100100000;
691 let Inst{7-4} = 0b1111;
694 // A5.4 Permanently UNDEFINED instructions.
695 def TRAP : AI<(outs), (ins), MiscFrm, NoItinerary, "trap", "",
696 [/* For disassembly only; pattern left blank */]>,
698 let Inst{27-25} = 0b011;
699 let Inst{24-20} = 0b11111;
700 let Inst{7-5} = 0b111;
704 // Address computation and loads and stores in PIC mode.
705 let isNotDuplicable = 1 in {
706 def PICADD : AXI1<0b0100, (outs GPR:$dst), (ins GPR:$a, pclabel:$cp, pred:$p),
707 Pseudo, IIC_iALUr, "\n$cp:\n\tadd$p\t$dst, pc, $a",
708 [(set GPR:$dst, (ARMpic_add GPR:$a, imm:$cp))]>;
710 let AddedComplexity = 10 in {
711 def PICLDR : AXI2ldw<(outs GPR:$dst), (ins addrmodepc:$addr, pred:$p),
712 Pseudo, IIC_iLoadr, "\n${addr:label}:\n\tldr$p\t$dst, $addr",
713 [(set GPR:$dst, (load addrmodepc:$addr))]>;
715 def PICLDRH : AXI3ldh<(outs GPR:$dst), (ins addrmodepc:$addr, pred:$p),
716 Pseudo, IIC_iLoadr, "\n${addr:label}:\n\tldrh${p}\t$dst, $addr",
717 [(set GPR:$dst, (zextloadi16 addrmodepc:$addr))]>;
719 def PICLDRB : AXI2ldb<(outs GPR:$dst), (ins addrmodepc:$addr, pred:$p),
720 Pseudo, IIC_iLoadr, "\n${addr:label}:\n\tldrb${p}\t$dst, $addr",
721 [(set GPR:$dst, (zextloadi8 addrmodepc:$addr))]>;
723 def PICLDRSH : AXI3ldsh<(outs GPR:$dst), (ins addrmodepc:$addr, pred:$p),
724 Pseudo, IIC_iLoadr, "\n${addr:label}:\n\tldrsh${p}\t$dst, $addr",
725 [(set GPR:$dst, (sextloadi16 addrmodepc:$addr))]>;
727 def PICLDRSB : AXI3ldsb<(outs GPR:$dst), (ins addrmodepc:$addr, pred:$p),
728 Pseudo, IIC_iLoadr, "\n${addr:label}:\n\tldrsb${p}\t$dst, $addr",
729 [(set GPR:$dst, (sextloadi8 addrmodepc:$addr))]>;
731 let AddedComplexity = 10 in {
732 def PICSTR : AXI2stw<(outs), (ins GPR:$src, addrmodepc:$addr, pred:$p),
733 Pseudo, IIC_iStorer, "\n${addr:label}:\n\tstr$p\t$src, $addr",
734 [(store GPR:$src, addrmodepc:$addr)]>;
736 def PICSTRH : AXI3sth<(outs), (ins GPR:$src, addrmodepc:$addr, pred:$p),
737 Pseudo, IIC_iStorer, "\n${addr:label}:\n\tstrh${p}\t$src, $addr",
738 [(truncstorei16 GPR:$src, addrmodepc:$addr)]>;
740 def PICSTRB : AXI2stb<(outs), (ins GPR:$src, addrmodepc:$addr, pred:$p),
741 Pseudo, IIC_iStorer, "\n${addr:label}:\n\tstrb${p}\t$src, $addr",
742 [(truncstorei8 GPR:$src, addrmodepc:$addr)]>;
744 } // isNotDuplicable = 1
747 // LEApcrel - Load a pc-relative address into a register without offending the
749 def LEApcrel : AXI1<0x0, (outs GPR:$dst), (ins i32imm:$label, pred:$p),
751 !strconcat(!strconcat(".set ${:private}PCRELV${:uid}, ($label-(",
752 "${:private}PCRELL${:uid}+8))\n"),
753 !strconcat("${:private}PCRELL${:uid}:\n\t",
754 "add$p\t$dst, pc, #${:private}PCRELV${:uid}")),
757 def LEApcrelJT : AXI1<0x0, (outs GPR:$dst),
758 (ins i32imm:$label, nohash_imm:$id, pred:$p),
760 !strconcat(!strconcat(".set ${:private}PCRELV${:uid}, "
762 "${:private}PCRELL${:uid}+8))\n"),
763 !strconcat("${:private}PCRELL${:uid}:\n\t",
764 "add$p\t$dst, pc, #${:private}PCRELV${:uid}")),
769 //===----------------------------------------------------------------------===//
770 // Control Flow Instructions.
773 let isReturn = 1, isTerminator = 1, isBarrier = 1 in
774 def BX_RET : AI<(outs), (ins), BrMiscFrm, IIC_Br,
775 "bx", "\tlr", [(ARMretflag)]> {
776 let Inst{3-0} = 0b1110;
777 let Inst{7-4} = 0b0001;
778 let Inst{19-8} = 0b111111111111;
779 let Inst{27-20} = 0b00010010;
783 let isBranch = 1, isTerminator = 1, isBarrier = 1, isIndirectBranch = 1 in {
784 def BRIND : AXI<(outs), (ins GPR:$dst), BrMiscFrm, IIC_Br, "bx\t$dst",
785 [(brind GPR:$dst)]> {
786 let Inst{7-4} = 0b0001;
787 let Inst{19-8} = 0b111111111111;
788 let Inst{27-20} = 0b00010010;
789 let Inst{31-28} = 0b1110;
793 // FIXME: remove when we have a way to marking a MI with these properties.
794 // FIXME: Should pc be an implicit operand like PICADD, etc?
795 let isReturn = 1, isTerminator = 1, isBarrier = 1, mayLoad = 1,
796 hasExtraDefRegAllocReq = 1 in
797 def LDM_RET : AXI4ld<(outs),
798 (ins addrmode4:$addr, pred:$p, reglist:$wb, variable_ops),
799 LdStMulFrm, IIC_Br, "ldm${addr:submode}${p}\t$addr, $wb",
802 // On non-Darwin platforms R9 is callee-saved.
804 Defs = [R0, R1, R2, R3, R12, LR,
805 D0, D1, D2, D3, D4, D5, D6, D7,
806 D16, D17, D18, D19, D20, D21, D22, D23,
807 D24, D25, D26, D27, D28, D29, D30, D31, CPSR, FPSCR] in {
808 def BL : ABXI<0b1011, (outs), (ins i32imm:$func, variable_ops),
809 IIC_Br, "bl\t${func:call}",
810 [(ARMcall tglobaladdr:$func)]>,
811 Requires<[IsARM, IsNotDarwin]> {
812 let Inst{31-28} = 0b1110;
815 def BL_pred : ABI<0b1011, (outs), (ins i32imm:$func, variable_ops),
816 IIC_Br, "bl", "\t${func:call}",
817 [(ARMcall_pred tglobaladdr:$func)]>,
818 Requires<[IsARM, IsNotDarwin]>;
821 def BLX : AXI<(outs), (ins GPR:$func, variable_ops), BrMiscFrm,
822 IIC_Br, "blx\t$func",
823 [(ARMcall GPR:$func)]>,
824 Requires<[IsARM, HasV5T, IsNotDarwin]> {
825 let Inst{7-4} = 0b0011;
826 let Inst{19-8} = 0b111111111111;
827 let Inst{27-20} = 0b00010010;
831 def BX : ABXIx2<(outs), (ins GPR:$func, variable_ops),
832 IIC_Br, "mov\tlr, pc\n\tbx\t$func",
833 [(ARMcall_nolink GPR:$func)]>,
834 Requires<[IsARM, IsNotDarwin]> {
835 let Inst{7-4} = 0b0001;
836 let Inst{19-8} = 0b111111111111;
837 let Inst{27-20} = 0b00010010;
841 // On Darwin R9 is call-clobbered.
843 Defs = [R0, R1, R2, R3, R9, R12, LR,
844 D0, D1, D2, D3, D4, D5, D6, D7,
845 D16, D17, D18, D19, D20, D21, D22, D23,
846 D24, D25, D26, D27, D28, D29, D30, D31, CPSR, FPSCR] in {
847 def BLr9 : ABXI<0b1011, (outs), (ins i32imm:$func, variable_ops),
848 IIC_Br, "bl\t${func:call}",
849 [(ARMcall tglobaladdr:$func)]>, Requires<[IsARM, IsDarwin]> {
850 let Inst{31-28} = 0b1110;
853 def BLr9_pred : ABI<0b1011, (outs), (ins i32imm:$func, variable_ops),
854 IIC_Br, "bl", "\t${func:call}",
855 [(ARMcall_pred tglobaladdr:$func)]>,
856 Requires<[IsARM, IsDarwin]>;
859 def BLXr9 : AXI<(outs), (ins GPR:$func, variable_ops), BrMiscFrm,
860 IIC_Br, "blx\t$func",
861 [(ARMcall GPR:$func)]>, Requires<[IsARM, HasV5T, IsDarwin]> {
862 let Inst{7-4} = 0b0011;
863 let Inst{19-8} = 0b111111111111;
864 let Inst{27-20} = 0b00010010;
868 def BXr9 : ABXIx2<(outs), (ins GPR:$func, variable_ops),
869 IIC_Br, "mov\tlr, pc\n\tbx\t$func",
870 [(ARMcall_nolink GPR:$func)]>, Requires<[IsARM, IsDarwin]> {
871 let Inst{7-4} = 0b0001;
872 let Inst{19-8} = 0b111111111111;
873 let Inst{27-20} = 0b00010010;
877 let isBranch = 1, isTerminator = 1 in {
878 // B is "predicable" since it can be xformed into a Bcc.
879 let isBarrier = 1 in {
880 let isPredicable = 1 in
881 def B : ABXI<0b1010, (outs), (ins brtarget:$target), IIC_Br,
882 "b\t$target", [(br bb:$target)]>;
884 let isNotDuplicable = 1, isIndirectBranch = 1 in {
885 def BR_JTr : JTI<(outs), (ins GPR:$target, jtblock_operand:$jt, i32imm:$id),
886 IIC_Br, "mov\tpc, $target \n$jt",
887 [(ARMbrjt GPR:$target, tjumptable:$jt, imm:$id)]> {
888 let Inst{11-4} = 0b00000000;
889 let Inst{15-12} = 0b1111;
890 let Inst{20} = 0; // S Bit
891 let Inst{24-21} = 0b1101;
892 let Inst{27-25} = 0b000;
894 def BR_JTm : JTI<(outs),
895 (ins addrmode2:$target, jtblock_operand:$jt, i32imm:$id),
896 IIC_Br, "ldr\tpc, $target \n$jt",
897 [(ARMbrjt (i32 (load addrmode2:$target)), tjumptable:$jt,
899 let Inst{15-12} = 0b1111;
900 let Inst{20} = 1; // L bit
901 let Inst{21} = 0; // W bit
902 let Inst{22} = 0; // B bit
903 let Inst{24} = 1; // P bit
904 let Inst{27-25} = 0b011;
906 def BR_JTadd : JTI<(outs),
907 (ins GPR:$target, GPR:$idx, jtblock_operand:$jt, i32imm:$id),
908 IIC_Br, "add\tpc, $target, $idx \n$jt",
909 [(ARMbrjt (add GPR:$target, GPR:$idx), tjumptable:$jt,
911 let Inst{15-12} = 0b1111;
912 let Inst{20} = 0; // S bit
913 let Inst{24-21} = 0b0100;
914 let Inst{27-25} = 0b000;
916 } // isNotDuplicable = 1, isIndirectBranch = 1
919 // FIXME: should be able to write a pattern for ARMBrcond, but can't use
920 // a two-value operand where a dag node expects two operands. :(
921 def Bcc : ABI<0b1010, (outs), (ins brtarget:$target),
922 IIC_Br, "b", "\t$target",
923 [/*(ARMbrcond bb:$target, imm:$cc, CCR:$ccr)*/]>;
926 // Branch and Exchange Jazelle -- for disassembly only
927 def BXJ : ABI<0b0001, (outs), (ins GPR:$func), NoItinerary, "bxj", "\t$func",
928 [/* For disassembly only; pattern left blank */]> {
929 let Inst{23-20} = 0b0010;
930 //let Inst{19-8} = 0xfff;
931 let Inst{7-4} = 0b0010;
934 // Supervisor call (software interrupt) -- for disassembly only
936 def SVC : ABI<0b1111, (outs), (ins i32imm:$svc), IIC_Br, "svc", "\t$svc",
937 [/* For disassembly only; pattern left blank */]>;
940 //===----------------------------------------------------------------------===//
941 // Load / store Instructions.
945 let canFoldAsLoad = 1, isReMaterializable = 1, mayHaveSideEffects = 1 in
946 def LDR : AI2ldw<(outs GPR:$dst), (ins addrmode2:$addr), LdFrm, IIC_iLoadr,
947 "ldr", "\t$dst, $addr",
948 [(set GPR:$dst, (load addrmode2:$addr))]>;
950 // Special LDR for loads from non-pc-relative constpools.
951 let canFoldAsLoad = 1, mayLoad = 1, isReMaterializable = 1,
952 mayHaveSideEffects = 1 in
953 def LDRcp : AI2ldw<(outs GPR:$dst), (ins addrmode2:$addr), LdFrm, IIC_iLoadr,
954 "ldr", "\t$dst, $addr", []>;
956 // Loads with zero extension
957 def LDRH : AI3ldh<(outs GPR:$dst), (ins addrmode3:$addr), LdMiscFrm,
958 IIC_iLoadr, "ldrh", "\t$dst, $addr",
959 [(set GPR:$dst, (zextloadi16 addrmode3:$addr))]>;
961 def LDRB : AI2ldb<(outs GPR:$dst), (ins addrmode2:$addr), LdFrm,
962 IIC_iLoadr, "ldrb", "\t$dst, $addr",
963 [(set GPR:$dst, (zextloadi8 addrmode2:$addr))]>;
965 // Loads with sign extension
966 def LDRSH : AI3ldsh<(outs GPR:$dst), (ins addrmode3:$addr), LdMiscFrm,
967 IIC_iLoadr, "ldrsh", "\t$dst, $addr",
968 [(set GPR:$dst, (sextloadi16 addrmode3:$addr))]>;
970 def LDRSB : AI3ldsb<(outs GPR:$dst), (ins addrmode3:$addr), LdMiscFrm,
971 IIC_iLoadr, "ldrsb", "\t$dst, $addr",
972 [(set GPR:$dst, (sextloadi8 addrmode3:$addr))]>;
974 let mayLoad = 1, hasExtraDefRegAllocReq = 1 in {
976 def LDRD : AI3ldd<(outs GPR:$dst1, GPR:$dst2), (ins addrmode3:$addr), LdMiscFrm,
977 IIC_iLoadr, "ldrd", "\t$dst1, $addr",
978 []>, Requires<[IsARM, HasV5TE]>;
981 def LDR_PRE : AI2ldwpr<(outs GPR:$dst, GPR:$base_wb),
982 (ins addrmode2:$addr), LdFrm, IIC_iLoadru,
983 "ldr", "\t$dst, $addr!", "$addr.base = $base_wb", []>;
985 def LDR_POST : AI2ldwpo<(outs GPR:$dst, GPR:$base_wb),
986 (ins GPR:$base, am2offset:$offset), LdFrm, IIC_iLoadru,
987 "ldr", "\t$dst, [$base], $offset", "$base = $base_wb", []>;
989 def LDRH_PRE : AI3ldhpr<(outs GPR:$dst, GPR:$base_wb),
990 (ins addrmode3:$addr), LdMiscFrm, IIC_iLoadru,
991 "ldrh", "\t$dst, $addr!", "$addr.base = $base_wb", []>;
993 def LDRH_POST : AI3ldhpo<(outs GPR:$dst, GPR:$base_wb),
994 (ins GPR:$base,am3offset:$offset), LdMiscFrm, IIC_iLoadru,
995 "ldrh", "\t$dst, [$base], $offset", "$base = $base_wb", []>;
997 def LDRB_PRE : AI2ldbpr<(outs GPR:$dst, GPR:$base_wb),
998 (ins addrmode2:$addr), LdFrm, IIC_iLoadru,
999 "ldrb", "\t$dst, $addr!", "$addr.base = $base_wb", []>;
1001 def LDRB_POST : AI2ldbpo<(outs GPR:$dst, GPR:$base_wb),
1002 (ins GPR:$base,am2offset:$offset), LdFrm, IIC_iLoadru,
1003 "ldrb", "\t$dst, [$base], $offset", "$base = $base_wb", []>;
1005 def LDRSH_PRE : AI3ldshpr<(outs GPR:$dst, GPR:$base_wb),
1006 (ins addrmode3:$addr), LdMiscFrm, IIC_iLoadru,
1007 "ldrsh", "\t$dst, $addr!", "$addr.base = $base_wb", []>;
1009 def LDRSH_POST: AI3ldshpo<(outs GPR:$dst, GPR:$base_wb),
1010 (ins GPR:$base,am3offset:$offset), LdMiscFrm, IIC_iLoadru,
1011 "ldrsh", "\t$dst, [$base], $offset", "$base = $base_wb", []>;
1013 def LDRSB_PRE : AI3ldsbpr<(outs GPR:$dst, GPR:$base_wb),
1014 (ins addrmode3:$addr), LdMiscFrm, IIC_iLoadru,
1015 "ldrsb", "\t$dst, $addr!", "$addr.base = $base_wb", []>;
1017 def LDRSB_POST: AI3ldsbpo<(outs GPR:$dst, GPR:$base_wb),
1018 (ins GPR:$base,am3offset:$offset), LdMiscFrm, IIC_iLoadru,
1019 "ldrsb", "\t$dst, [$base], $offset", "$base = $base_wb", []>;
1022 // LDRT and LDRBT are for disassembly only.
1024 def LDRT : AI2ldwpo<(outs GPR:$dst, GPR:$base_wb),
1025 (ins GPR:$base, am2offset:$offset), LdFrm, IIC_iLoadru,
1026 "ldrt", "\t$dst, [$base], $offset", "$base = $base_wb", []> {
1027 let Inst{21} = 1; // overwrite
1030 def LDRBT : AI2ldbpo<(outs GPR:$dst, GPR:$base_wb),
1031 (ins GPR:$base,am2offset:$offset), LdFrm, IIC_iLoadru,
1032 "ldrb", "\t$dst, [$base], $offset", "$base = $base_wb", []> {
1033 let Inst{21} = 1; // overwrite
1037 def STR : AI2stw<(outs), (ins GPR:$src, addrmode2:$addr), StFrm, IIC_iStorer,
1038 "str", "\t$src, $addr",
1039 [(store GPR:$src, addrmode2:$addr)]>;
1041 // Stores with truncate
1042 def STRH : AI3sth<(outs), (ins GPR:$src, addrmode3:$addr), StMiscFrm, IIC_iStorer,
1043 "strh", "\t$src, $addr",
1044 [(truncstorei16 GPR:$src, addrmode3:$addr)]>;
1046 def STRB : AI2stb<(outs), (ins GPR:$src, addrmode2:$addr), StFrm, IIC_iStorer,
1047 "strb", "\t$src, $addr",
1048 [(truncstorei8 GPR:$src, addrmode2:$addr)]>;
1051 let mayStore = 1, hasExtraSrcRegAllocReq = 1 in
1052 def STRD : AI3std<(outs), (ins GPR:$src1, GPR:$src2, addrmode3:$addr),
1053 StMiscFrm, IIC_iStorer,
1054 "strd", "\t$src1, $addr", []>, Requires<[IsARM, HasV5TE]>;
1057 def STR_PRE : AI2stwpr<(outs GPR:$base_wb),
1058 (ins GPR:$src, GPR:$base, am2offset:$offset),
1059 StFrm, IIC_iStoreru,
1060 "str", "\t$src, [$base, $offset]!", "$base = $base_wb",
1062 (pre_store GPR:$src, GPR:$base, am2offset:$offset))]>;
1064 def STR_POST : AI2stwpo<(outs GPR:$base_wb),
1065 (ins GPR:$src, GPR:$base,am2offset:$offset),
1066 StFrm, IIC_iStoreru,
1067 "str", "\t$src, [$base], $offset", "$base = $base_wb",
1069 (post_store GPR:$src, GPR:$base, am2offset:$offset))]>;
1071 def STRH_PRE : AI3sthpr<(outs GPR:$base_wb),
1072 (ins GPR:$src, GPR:$base,am3offset:$offset),
1073 StMiscFrm, IIC_iStoreru,
1074 "strh", "\t$src, [$base, $offset]!", "$base = $base_wb",
1076 (pre_truncsti16 GPR:$src, GPR:$base,am3offset:$offset))]>;
1078 def STRH_POST: AI3sthpo<(outs GPR:$base_wb),
1079 (ins GPR:$src, GPR:$base,am3offset:$offset),
1080 StMiscFrm, IIC_iStoreru,
1081 "strh", "\t$src, [$base], $offset", "$base = $base_wb",
1082 [(set GPR:$base_wb, (post_truncsti16 GPR:$src,
1083 GPR:$base, am3offset:$offset))]>;
1085 def STRB_PRE : AI2stbpr<(outs GPR:$base_wb),
1086 (ins GPR:$src, GPR:$base,am2offset:$offset),
1087 StFrm, IIC_iStoreru,
1088 "strb", "\t$src, [$base, $offset]!", "$base = $base_wb",
1089 [(set GPR:$base_wb, (pre_truncsti8 GPR:$src,
1090 GPR:$base, am2offset:$offset))]>;
1092 def STRB_POST: AI2stbpo<(outs GPR:$base_wb),
1093 (ins GPR:$src, GPR:$base,am2offset:$offset),
1094 StFrm, IIC_iStoreru,
1095 "strb", "\t$src, [$base], $offset", "$base = $base_wb",
1096 [(set GPR:$base_wb, (post_truncsti8 GPR:$src,
1097 GPR:$base, am2offset:$offset))]>;
1099 // STRT and STRBT are for disassembly only.
1101 def STRT : AI2stwpo<(outs GPR:$base_wb),
1102 (ins GPR:$src, GPR:$base,am2offset:$offset),
1103 StFrm, IIC_iStoreru,
1104 "strt", "\t$src, [$base], $offset", "$base = $base_wb",
1105 [/* For disassembly only; pattern left blank */]> {
1106 let Inst{21} = 1; // overwrite
1109 def STRBT : AI2stbpo<(outs GPR:$base_wb),
1110 (ins GPR:$src, GPR:$base,am2offset:$offset),
1111 StFrm, IIC_iStoreru,
1112 "strbt", "\t$src, [$base], $offset", "$base = $base_wb",
1113 [/* For disassembly only; pattern left blank */]> {
1114 let Inst{21} = 1; // overwrite
1117 //===----------------------------------------------------------------------===//
1118 // Load / store multiple Instructions.
1121 let mayLoad = 1, hasExtraDefRegAllocReq = 1 in
1122 def LDM : AXI4ld<(outs),
1123 (ins addrmode4:$addr, pred:$p, reglist:$wb, variable_ops),
1124 LdStMulFrm, IIC_iLoadm, "ldm${addr:submode}${p}\t$addr, $wb",
1127 let mayStore = 1, hasExtraSrcRegAllocReq = 1 in
1128 def STM : AXI4st<(outs),
1129 (ins addrmode4:$addr, pred:$p, reglist:$wb, variable_ops),
1130 LdStMulFrm, IIC_iStorem, "stm${addr:submode}${p}\t$addr, $wb",
1133 //===----------------------------------------------------------------------===//
1134 // Move Instructions.
1137 let neverHasSideEffects = 1 in
1138 def MOVr : AsI1<0b1101, (outs GPR:$dst), (ins GPR:$src), DPFrm, IIC_iMOVr,
1139 "mov", "\t$dst, $src", []>, UnaryDP {
1140 let Inst{11-4} = 0b00000000;
1144 def MOVs : AsI1<0b1101, (outs GPR:$dst), (ins so_reg:$src),
1145 DPSoRegFrm, IIC_iMOVsr,
1146 "mov", "\t$dst, $src", [(set GPR:$dst, so_reg:$src)]>, UnaryDP {
1150 let isReMaterializable = 1, isAsCheapAsAMove = 1 in
1151 def MOVi : AsI1<0b1101, (outs GPR:$dst), (ins so_imm:$src), DPFrm, IIC_iMOVi,
1152 "mov", "\t$dst, $src", [(set GPR:$dst, so_imm:$src)]>, UnaryDP {
1156 let isReMaterializable = 1, isAsCheapAsAMove = 1 in
1157 def MOVi16 : AI1<0b1000, (outs GPR:$dst), (ins i32imm:$src),
1159 "movw", "\t$dst, $src",
1160 [(set GPR:$dst, imm0_65535:$src)]>,
1161 Requires<[IsARM, HasV6T2]>, UnaryDP {
1166 let Constraints = "$src = $dst" in
1167 def MOVTi16 : AI1<0b1010, (outs GPR:$dst), (ins GPR:$src, i32imm:$imm),
1169 "movt", "\t$dst, $imm",
1171 (or (and GPR:$src, 0xffff),
1172 lo16AllZero:$imm))]>, UnaryDP,
1173 Requires<[IsARM, HasV6T2]> {
1178 def : ARMPat<(or GPR:$src, 0xffff0000), (MOVTi16 GPR:$src, 0xffff)>,
1179 Requires<[IsARM, HasV6T2]>;
1181 let Uses = [CPSR] in
1182 def MOVrx : AsI1<0b1101, (outs GPR:$dst), (ins GPR:$src), Pseudo, IIC_iMOVsi,
1183 "mov", "\t$dst, $src, rrx",
1184 [(set GPR:$dst, (ARMrrx GPR:$src))]>, UnaryDP;
1186 // These aren't really mov instructions, but we have to define them this way
1187 // due to flag operands.
1189 let Defs = [CPSR] in {
1190 def MOVsrl_flag : AI1<0b1101, (outs GPR:$dst), (ins GPR:$src), Pseudo,
1191 IIC_iMOVsi, "movs", "\t$dst, $src, lsr #1",
1192 [(set GPR:$dst, (ARMsrl_flag GPR:$src))]>, UnaryDP;
1193 def MOVsra_flag : AI1<0b1101, (outs GPR:$dst), (ins GPR:$src), Pseudo,
1194 IIC_iMOVsi, "movs", "\t$dst, $src, asr #1",
1195 [(set GPR:$dst, (ARMsra_flag GPR:$src))]>, UnaryDP;
1198 //===----------------------------------------------------------------------===//
1199 // Extend Instructions.
1204 defm SXTB : AI_unary_rrot<0b01101010,
1205 "sxtb", UnOpFrag<(sext_inreg node:$Src, i8)>>;
1206 defm SXTH : AI_unary_rrot<0b01101011,
1207 "sxth", UnOpFrag<(sext_inreg node:$Src, i16)>>;
1209 defm SXTAB : AI_bin_rrot<0b01101010,
1210 "sxtab", BinOpFrag<(add node:$LHS, (sext_inreg node:$RHS, i8))>>;
1211 defm SXTAH : AI_bin_rrot<0b01101011,
1212 "sxtah", BinOpFrag<(add node:$LHS, (sext_inreg node:$RHS,i16))>>;
1214 // TODO: SXT(A){B|H}16
1218 let AddedComplexity = 16 in {
1219 defm UXTB : AI_unary_rrot<0b01101110,
1220 "uxtb" , UnOpFrag<(and node:$Src, 0x000000FF)>>;
1221 defm UXTH : AI_unary_rrot<0b01101111,
1222 "uxth" , UnOpFrag<(and node:$Src, 0x0000FFFF)>>;
1223 defm UXTB16 : AI_unary_rrot<0b01101100,
1224 "uxtb16", UnOpFrag<(and node:$Src, 0x00FF00FF)>>;
1226 def : ARMV6Pat<(and (shl GPR:$Src, (i32 8)), 0xFF00FF),
1227 (UXTB16r_rot GPR:$Src, 24)>;
1228 def : ARMV6Pat<(and (srl GPR:$Src, (i32 8)), 0xFF00FF),
1229 (UXTB16r_rot GPR:$Src, 8)>;
1231 defm UXTAB : AI_bin_rrot<0b01101110, "uxtab",
1232 BinOpFrag<(add node:$LHS, (and node:$RHS, 0x00FF))>>;
1233 defm UXTAH : AI_bin_rrot<0b01101111, "uxtah",
1234 BinOpFrag<(add node:$LHS, (and node:$RHS, 0xFFFF))>>;
1237 // This isn't safe in general, the add is two 16-bit units, not a 32-bit add.
1238 //defm UXTAB16 : xxx<"uxtab16", 0xff00ff>;
1240 // TODO: UXT(A){B|H}16
1242 def SBFX : I<(outs GPR:$dst),
1243 (ins GPR:$src, imm0_31:$lsb, imm0_31:$width),
1244 AddrMode1, Size4Bytes, IndexModeNone, DPFrm, IIC_iALUi,
1245 "sbfx", "\t$dst, $src, $lsb, $width", "", []>,
1246 Requires<[IsARM, HasV6T2]> {
1247 let Inst{27-21} = 0b0111101;
1248 let Inst{6-4} = 0b101;
1251 def UBFX : I<(outs GPR:$dst),
1252 (ins GPR:$src, imm0_31:$lsb, imm0_31:$width),
1253 AddrMode1, Size4Bytes, IndexModeNone, DPFrm, IIC_iALUi,
1254 "ubfx", "\t$dst, $src, $lsb, $width", "", []>,
1255 Requires<[IsARM, HasV6T2]> {
1256 let Inst{27-21} = 0b0111111;
1257 let Inst{6-4} = 0b101;
1260 //===----------------------------------------------------------------------===//
1261 // Arithmetic Instructions.
1264 defm ADD : AsI1_bin_irs<0b0100, "add",
1265 BinOpFrag<(add node:$LHS, node:$RHS)>, 1>;
1266 defm SUB : AsI1_bin_irs<0b0010, "sub",
1267 BinOpFrag<(sub node:$LHS, node:$RHS)>>;
1269 // ADD and SUB with 's' bit set.
1270 defm ADDS : AI1_bin_s_irs<0b0100, "adds",
1271 BinOpFrag<(addc node:$LHS, node:$RHS)>, 1>;
1272 defm SUBS : AI1_bin_s_irs<0b0010, "subs",
1273 BinOpFrag<(subc node:$LHS, node:$RHS)>>;
1275 defm ADC : AI1_adde_sube_irs<0b0101, "adc",
1276 BinOpFrag<(adde node:$LHS, node:$RHS)>, 1>;
1277 defm SBC : AI1_adde_sube_irs<0b0110, "sbc",
1278 BinOpFrag<(sube node:$LHS, node:$RHS)>>;
1279 defm ADCS : AI1_adde_sube_s_irs<0b0101, "adcs",
1280 BinOpFrag<(adde node:$LHS, node:$RHS)>, 1>;
1281 defm SBCS : AI1_adde_sube_s_irs<0b0110, "sbcs",
1282 BinOpFrag<(sube node:$LHS, node:$RHS)>>;
1284 // These don't define reg/reg forms, because they are handled above.
1285 def RSBri : AsI1<0b0011, (outs GPR:$dst), (ins GPR:$a, so_imm:$b), DPFrm,
1286 IIC_iALUi, "rsb", "\t$dst, $a, $b",
1287 [(set GPR:$dst, (sub so_imm:$b, GPR:$a))]> {
1291 def RSBrs : AsI1<0b0011, (outs GPR:$dst), (ins GPR:$a, so_reg:$b), DPSoRegFrm,
1292 IIC_iALUsr, "rsb", "\t$dst, $a, $b",
1293 [(set GPR:$dst, (sub so_reg:$b, GPR:$a))]> {
1297 // RSB with 's' bit set.
1298 let Defs = [CPSR] in {
1299 def RSBSri : AI1<0b0011, (outs GPR:$dst), (ins GPR:$a, so_imm:$b), DPFrm,
1300 IIC_iALUi, "rsbs", "\t$dst, $a, $b",
1301 [(set GPR:$dst, (subc so_imm:$b, GPR:$a))]> {
1305 def RSBSrs : AI1<0b0011, (outs GPR:$dst), (ins GPR:$a, so_reg:$b), DPSoRegFrm,
1306 IIC_iALUsr, "rsbs", "\t$dst, $a, $b",
1307 [(set GPR:$dst, (subc so_reg:$b, GPR:$a))]> {
1313 let Uses = [CPSR] in {
1314 def RSCri : AsI1<0b0111, (outs GPR:$dst), (ins GPR:$a, so_imm:$b),
1315 DPFrm, IIC_iALUi, "rsc", "\t$dst, $a, $b",
1316 [(set GPR:$dst, (sube so_imm:$b, GPR:$a))]>,
1317 Requires<[IsARM, CarryDefIsUnused]> {
1320 def RSCrs : AsI1<0b0111, (outs GPR:$dst), (ins GPR:$a, so_reg:$b),
1321 DPSoRegFrm, IIC_iALUsr, "rsc", "\t$dst, $a, $b",
1322 [(set GPR:$dst, (sube so_reg:$b, GPR:$a))]>,
1323 Requires<[IsARM, CarryDefIsUnused]> {
1328 // FIXME: Allow these to be predicated.
1329 let Defs = [CPSR], Uses = [CPSR] in {
1330 def RSCSri : AXI1<0b0111, (outs GPR:$dst), (ins GPR:$a, so_imm:$b),
1331 DPFrm, IIC_iALUi, "rscs\t$dst, $a, $b",
1332 [(set GPR:$dst, (sube so_imm:$b, GPR:$a))]>,
1333 Requires<[IsARM, CarryDefIsUnused]> {
1337 def RSCSrs : AXI1<0b0111, (outs GPR:$dst), (ins GPR:$a, so_reg:$b),
1338 DPSoRegFrm, IIC_iALUsr, "rscs\t$dst, $a, $b",
1339 [(set GPR:$dst, (sube so_reg:$b, GPR:$a))]>,
1340 Requires<[IsARM, CarryDefIsUnused]> {
1346 // (sub X, imm) gets canonicalized to (add X, -imm). Match this form.
1347 def : ARMPat<(add GPR:$src, so_imm_neg:$imm),
1348 (SUBri GPR:$src, so_imm_neg:$imm)>;
1350 //def : ARMPat<(addc GPR:$src, so_imm_neg:$imm),
1351 // (SUBSri GPR:$src, so_imm_neg:$imm)>;
1352 //def : ARMPat<(adde GPR:$src, so_imm_neg:$imm),
1353 // (SBCri GPR:$src, so_imm_neg:$imm)>;
1355 // Note: These are implemented in C++ code, because they have to generate
1356 // ADD/SUBrs instructions, which use a complex pattern that a xform function
1358 // (mul X, 2^n+1) -> (add (X << n), X)
1359 // (mul X, 2^n-1) -> (rsb X, (X << n))
1361 // Saturating adds/subtracts -- for disassembly only
1363 // GPR:$dst = GPR:$a op GPR:$b
1364 class AQI<bits<8> op27_20, bits<4> op7_4, string opc, list<dag> pattern>
1365 : AI<(outs GPR:$dst), (ins GPR:$a, GPR:$b), DPFrm, IIC_iALUr,
1366 opc, "\t$dst, $a, $b", pattern> {
1367 let Inst{27-20} = op27_20;
1368 let Inst{7-4} = op7_4;
1371 def QADD : AQI<0b00010000, 0b0101, "qadd",
1372 [/* For disassembly only; pattern left blank */]>;
1374 def QADD16 : AQI<0b01100010, 0b0001, "qadd16",
1375 [/* For disassembly only; pattern left blank */]>;
1377 def QADD8 : AQI<0b01100010, 0b1001, "qadd8",
1378 [/* For disassembly only; pattern left blank */]>;
1380 def QASX : AQI<0b01100010, 0b0011, "qasx",
1381 [/* For disassembly only; pattern left blank */]>;
1383 def QDADD : AQI<0b00010100, 0b0101, "qdadd",
1384 [/* For disassembly only; pattern left blank */]>;
1386 def QDSUB : AQI<0b00010110, 0b0101, "qdsub",
1387 [/* For disassembly only; pattern left blank */]>;
1389 def QSAX : AQI<0b01100010, 0b0101, "qsax",
1390 [/* For disassembly only; pattern left blank */]>;
1392 def QSUB : AQI<0b00010010, 0b0101, "qsub",
1393 [/* For disassembly only; pattern left blank */]>;
1395 def QSUB16 : AQI<0b01100010, 0b0111, "qsub16",
1396 [/* For disassembly only; pattern left blank */]>;
1398 def QSUB8 : AQI<0b01100010, 0b1111, "qsub8",
1399 [/* For disassembly only; pattern left blank */]>;
1401 def UQADD16 : AQI<0b01100110, 0b0001, "uqadd16",
1402 [/* For disassembly only; pattern left blank */]>;
1404 def UQADD8 : AQI<0b01100110, 0b1001, "uqadd8",
1405 [/* For disassembly only; pattern left blank */]>;
1407 def UQASX : AQI<0b01100110, 0b0011, "uqasx",
1408 [/* For disassembly only; pattern left blank */]>;
1410 def UQSAX : AQI<0b01100110, 0b0101, "uqsax",
1411 [/* For disassembly only; pattern left blank */]>;
1413 def UQSUB16 : AQI<0b01100110, 0b0111, "uqsub16",
1414 [/* For disassembly only; pattern left blank */]>;
1416 def UQSUB8 : AQI<0b01100110, 0b1111, "uqsub8",
1417 [/* For disassembly only; pattern left blank */]>;
1419 //===----------------------------------------------------------------------===//
1420 // Bitwise Instructions.
1423 defm AND : AsI1_bin_irs<0b0000, "and",
1424 BinOpFrag<(and node:$LHS, node:$RHS)>, 1>;
1425 defm ORR : AsI1_bin_irs<0b1100, "orr",
1426 BinOpFrag<(or node:$LHS, node:$RHS)>, 1>;
1427 defm EOR : AsI1_bin_irs<0b0001, "eor",
1428 BinOpFrag<(xor node:$LHS, node:$RHS)>, 1>;
1429 defm BIC : AsI1_bin_irs<0b1110, "bic",
1430 BinOpFrag<(and node:$LHS, (not node:$RHS))>>;
1432 def BFC : I<(outs GPR:$dst), (ins GPR:$src, bf_inv_mask_imm:$imm),
1433 AddrMode1, Size4Bytes, IndexModeNone, DPFrm, IIC_iUNAsi,
1434 "bfc", "\t$dst, $imm", "$src = $dst",
1435 [(set GPR:$dst, (and GPR:$src, bf_inv_mask_imm:$imm))]>,
1436 Requires<[IsARM, HasV6T2]> {
1437 let Inst{27-21} = 0b0111110;
1438 let Inst{6-0} = 0b0011111;
1441 def MVNr : AsI1<0b1111, (outs GPR:$dst), (ins GPR:$src), DPFrm, IIC_iMOVr,
1442 "mvn", "\t$dst, $src",
1443 [(set GPR:$dst, (not GPR:$src))]>, UnaryDP {
1445 let Inst{11-4} = 0b00000000;
1447 def MVNs : AsI1<0b1111, (outs GPR:$dst), (ins so_reg:$src), DPSoRegFrm,
1448 IIC_iMOVsr, "mvn", "\t$dst, $src",
1449 [(set GPR:$dst, (not so_reg:$src))]>, UnaryDP {
1452 let isReMaterializable = 1, isAsCheapAsAMove = 1 in
1453 def MVNi : AsI1<0b1111, (outs GPR:$dst), (ins so_imm:$imm), DPFrm,
1454 IIC_iMOVi, "mvn", "\t$dst, $imm",
1455 [(set GPR:$dst, so_imm_not:$imm)]>,UnaryDP {
1459 def : ARMPat<(and GPR:$src, so_imm_not:$imm),
1460 (BICri GPR:$src, so_imm_not:$imm)>;
1462 //===----------------------------------------------------------------------===//
1463 // Multiply Instructions.
1466 let isCommutable = 1 in
1467 def MUL : AsMul1I<0b0000000, (outs GPR:$dst), (ins GPR:$a, GPR:$b),
1468 IIC_iMUL32, "mul", "\t$dst, $a, $b",
1469 [(set GPR:$dst, (mul GPR:$a, GPR:$b))]>;
1471 def MLA : AsMul1I<0b0000001, (outs GPR:$dst), (ins GPR:$a, GPR:$b, GPR:$c),
1472 IIC_iMAC32, "mla", "\t$dst, $a, $b, $c",
1473 [(set GPR:$dst, (add (mul GPR:$a, GPR:$b), GPR:$c))]>;
1475 def MLS : AMul1I<0b0000011, (outs GPR:$dst), (ins GPR:$a, GPR:$b, GPR:$c),
1476 IIC_iMAC32, "mls", "\t$dst, $a, $b, $c",
1477 [(set GPR:$dst, (sub GPR:$c, (mul GPR:$a, GPR:$b)))]>,
1478 Requires<[IsARM, HasV6T2]>;
1480 // Extra precision multiplies with low / high results
1481 let neverHasSideEffects = 1 in {
1482 let isCommutable = 1 in {
1483 def SMULL : AsMul1I<0b0000110, (outs GPR:$ldst, GPR:$hdst),
1484 (ins GPR:$a, GPR:$b), IIC_iMUL64,
1485 "smull", "\t$ldst, $hdst, $a, $b", []>;
1487 def UMULL : AsMul1I<0b0000100, (outs GPR:$ldst, GPR:$hdst),
1488 (ins GPR:$a, GPR:$b), IIC_iMUL64,
1489 "umull", "\t$ldst, $hdst, $a, $b", []>;
1492 // Multiply + accumulate
1493 def SMLAL : AsMul1I<0b0000111, (outs GPR:$ldst, GPR:$hdst),
1494 (ins GPR:$a, GPR:$b), IIC_iMAC64,
1495 "smlal", "\t$ldst, $hdst, $a, $b", []>;
1497 def UMLAL : AsMul1I<0b0000101, (outs GPR:$ldst, GPR:$hdst),
1498 (ins GPR:$a, GPR:$b), IIC_iMAC64,
1499 "umlal", "\t$ldst, $hdst, $a, $b", []>;
1501 def UMAAL : AMul1I <0b0000010, (outs GPR:$ldst, GPR:$hdst),
1502 (ins GPR:$a, GPR:$b), IIC_iMAC64,
1503 "umaal", "\t$ldst, $hdst, $a, $b", []>,
1504 Requires<[IsARM, HasV6]>;
1505 } // neverHasSideEffects
1507 // Most significant word multiply
1508 def SMMUL : AMul2I <0b0111010, (outs GPR:$dst), (ins GPR:$a, GPR:$b),
1509 IIC_iMUL32, "smmul", "\t$dst, $a, $b",
1510 [(set GPR:$dst, (mulhs GPR:$a, GPR:$b))]>,
1511 Requires<[IsARM, HasV6]> {
1512 let Inst{7-4} = 0b0001;
1513 let Inst{15-12} = 0b1111;
1516 def SMMLA : AMul2I <0b0111010, (outs GPR:$dst), (ins GPR:$a, GPR:$b, GPR:$c),
1517 IIC_iMAC32, "smmla", "\t$dst, $a, $b, $c",
1518 [(set GPR:$dst, (add (mulhs GPR:$a, GPR:$b), GPR:$c))]>,
1519 Requires<[IsARM, HasV6]> {
1520 let Inst{7-4} = 0b0001;
1524 def SMMLS : AMul2I <0b0111010, (outs GPR:$dst), (ins GPR:$a, GPR:$b, GPR:$c),
1525 IIC_iMAC32, "smmls", "\t$dst, $a, $b, $c",
1526 [(set GPR:$dst, (sub GPR:$c, (mulhs GPR:$a, GPR:$b)))]>,
1527 Requires<[IsARM, HasV6]> {
1528 let Inst{7-4} = 0b1101;
1531 multiclass AI_smul<string opc, PatFrag opnode> {
1532 def BB : AMulxyI<0b0001011, (outs GPR:$dst), (ins GPR:$a, GPR:$b),
1533 IIC_iMUL32, !strconcat(opc, "bb"), "\t$dst, $a, $b",
1534 [(set GPR:$dst, (opnode (sext_inreg GPR:$a, i16),
1535 (sext_inreg GPR:$b, i16)))]>,
1536 Requires<[IsARM, HasV5TE]> {
1541 def BT : AMulxyI<0b0001011, (outs GPR:$dst), (ins GPR:$a, GPR:$b),
1542 IIC_iMUL32, !strconcat(opc, "bt"), "\t$dst, $a, $b",
1543 [(set GPR:$dst, (opnode (sext_inreg GPR:$a, i16),
1544 (sra GPR:$b, (i32 16))))]>,
1545 Requires<[IsARM, HasV5TE]> {
1550 def TB : AMulxyI<0b0001011, (outs GPR:$dst), (ins GPR:$a, GPR:$b),
1551 IIC_iMUL32, !strconcat(opc, "tb"), "\t$dst, $a, $b",
1552 [(set GPR:$dst, (opnode (sra GPR:$a, (i32 16)),
1553 (sext_inreg GPR:$b, i16)))]>,
1554 Requires<[IsARM, HasV5TE]> {
1559 def TT : AMulxyI<0b0001011, (outs GPR:$dst), (ins GPR:$a, GPR:$b),
1560 IIC_iMUL32, !strconcat(opc, "tt"), "\t$dst, $a, $b",
1561 [(set GPR:$dst, (opnode (sra GPR:$a, (i32 16)),
1562 (sra GPR:$b, (i32 16))))]>,
1563 Requires<[IsARM, HasV5TE]> {
1568 def WB : AMulxyI<0b0001001, (outs GPR:$dst), (ins GPR:$a, GPR:$b),
1569 IIC_iMUL16, !strconcat(opc, "wb"), "\t$dst, $a, $b",
1570 [(set GPR:$dst, (sra (opnode GPR:$a,
1571 (sext_inreg GPR:$b, i16)), (i32 16)))]>,
1572 Requires<[IsARM, HasV5TE]> {
1577 def WT : AMulxyI<0b0001001, (outs GPR:$dst), (ins GPR:$a, GPR:$b),
1578 IIC_iMUL16, !strconcat(opc, "wt"), "\t$dst, $a, $b",
1579 [(set GPR:$dst, (sra (opnode GPR:$a,
1580 (sra GPR:$b, (i32 16))), (i32 16)))]>,
1581 Requires<[IsARM, HasV5TE]> {
1588 multiclass AI_smla<string opc, PatFrag opnode> {
1589 def BB : AMulxyI<0b0001000, (outs GPR:$dst), (ins GPR:$a, GPR:$b, GPR:$acc),
1590 IIC_iMAC16, !strconcat(opc, "bb"), "\t$dst, $a, $b, $acc",
1591 [(set GPR:$dst, (add GPR:$acc,
1592 (opnode (sext_inreg GPR:$a, i16),
1593 (sext_inreg GPR:$b, i16))))]>,
1594 Requires<[IsARM, HasV5TE]> {
1599 def BT : AMulxyI<0b0001000, (outs GPR:$dst), (ins GPR:$a, GPR:$b, GPR:$acc),
1600 IIC_iMAC16, !strconcat(opc, "bt"), "\t$dst, $a, $b, $acc",
1601 [(set GPR:$dst, (add GPR:$acc, (opnode (sext_inreg GPR:$a, i16),
1602 (sra GPR:$b, (i32 16)))))]>,
1603 Requires<[IsARM, HasV5TE]> {
1608 def TB : AMulxyI<0b0001000, (outs GPR:$dst), (ins GPR:$a, GPR:$b, GPR:$acc),
1609 IIC_iMAC16, !strconcat(opc, "tb"), "\t$dst, $a, $b, $acc",
1610 [(set GPR:$dst, (add GPR:$acc, (opnode (sra GPR:$a, (i32 16)),
1611 (sext_inreg GPR:$b, i16))))]>,
1612 Requires<[IsARM, HasV5TE]> {
1617 def TT : AMulxyI<0b0001000, (outs GPR:$dst), (ins GPR:$a, GPR:$b, GPR:$acc),
1618 IIC_iMAC16, !strconcat(opc, "tt"), "\t$dst, $a, $b, $acc",
1619 [(set GPR:$dst, (add GPR:$acc, (opnode (sra GPR:$a, (i32 16)),
1620 (sra GPR:$b, (i32 16)))))]>,
1621 Requires<[IsARM, HasV5TE]> {
1626 def WB : AMulxyI<0b0001001, (outs GPR:$dst), (ins GPR:$a, GPR:$b, GPR:$acc),
1627 IIC_iMAC16, !strconcat(opc, "wb"), "\t$dst, $a, $b, $acc",
1628 [(set GPR:$dst, (add GPR:$acc, (sra (opnode GPR:$a,
1629 (sext_inreg GPR:$b, i16)), (i32 16))))]>,
1630 Requires<[IsARM, HasV5TE]> {
1635 def WT : AMulxyI<0b0001001, (outs GPR:$dst), (ins GPR:$a, GPR:$b, GPR:$acc),
1636 IIC_iMAC16, !strconcat(opc, "wt"), "\t$dst, $a, $b, $acc",
1637 [(set GPR:$dst, (add GPR:$acc, (sra (opnode GPR:$a,
1638 (sra GPR:$b, (i32 16))), (i32 16))))]>,
1639 Requires<[IsARM, HasV5TE]> {
1645 defm SMUL : AI_smul<"smul", BinOpFrag<(mul node:$LHS, node:$RHS)>>;
1646 defm SMLA : AI_smla<"smla", BinOpFrag<(mul node:$LHS, node:$RHS)>>;
1648 // Halfword multiply accumulate long: SMLAL<x><y> -- for disassembly only
1649 def SMLALBB : AMulxyI<0b0001010,(outs GPR:$ldst,GPR:$hdst),(ins GPR:$a,GPR:$b),
1650 IIC_iMAC64, "smlalbb", "\t$ldst, $hdst, $a, $b",
1651 [/* For disassembly only; pattern left blank */]>,
1652 Requires<[IsARM, HasV5TE]> {
1657 def SMLALBT : AMulxyI<0b0001010,(outs GPR:$ldst,GPR:$hdst),(ins GPR:$a,GPR:$b),
1658 IIC_iMAC64, "smlalbt", "\t$ldst, $hdst, $a, $b",
1659 [/* For disassembly only; pattern left blank */]>,
1660 Requires<[IsARM, HasV5TE]> {
1665 def SMLALTB : AMulxyI<0b0001010,(outs GPR:$ldst,GPR:$hdst),(ins GPR:$a,GPR:$b),
1666 IIC_iMAC64, "smlaltb", "\t$ldst, $hdst, $a, $b",
1667 [/* For disassembly only; pattern left blank */]>,
1668 Requires<[IsARM, HasV5TE]> {
1673 def SMLALTT : AMulxyI<0b0001010,(outs GPR:$ldst,GPR:$hdst),(ins GPR:$a,GPR:$b),
1674 IIC_iMAC64, "smlaltt", "\t$ldst, $hdst, $a, $b",
1675 [/* For disassembly only; pattern left blank */]>,
1676 Requires<[IsARM, HasV5TE]> {
1681 // TODO: Dual halfword multiple: SMUAD, SMUSD, SMLAD, SMLSD, SMLALD, SMLSLD
1683 //===----------------------------------------------------------------------===//
1684 // Misc. Arithmetic Instructions.
1687 def CLZ : AMiscA1I<0b000010110, (outs GPR:$dst), (ins GPR:$src), IIC_iUNAr,
1688 "clz", "\t$dst, $src",
1689 [(set GPR:$dst, (ctlz GPR:$src))]>, Requires<[IsARM, HasV5T]> {
1690 let Inst{7-4} = 0b0001;
1691 let Inst{11-8} = 0b1111;
1692 let Inst{19-16} = 0b1111;
1695 def RBIT : AMiscA1I<0b01101111, (outs GPR:$dst), (ins GPR:$src), IIC_iUNAr,
1696 "rbit", "\t$dst, $src",
1697 [(set GPR:$dst, (ARMrbit GPR:$src))]>,
1698 Requires<[IsARM, HasV6T2]> {
1699 let Inst{7-4} = 0b0011;
1700 let Inst{11-8} = 0b1111;
1701 let Inst{19-16} = 0b1111;
1704 def REV : AMiscA1I<0b01101011, (outs GPR:$dst), (ins GPR:$src), IIC_iUNAr,
1705 "rev", "\t$dst, $src",
1706 [(set GPR:$dst, (bswap GPR:$src))]>, Requires<[IsARM, HasV6]> {
1707 let Inst{7-4} = 0b0011;
1708 let Inst{11-8} = 0b1111;
1709 let Inst{19-16} = 0b1111;
1712 def REV16 : AMiscA1I<0b01101011, (outs GPR:$dst), (ins GPR:$src), IIC_iUNAr,
1713 "rev16", "\t$dst, $src",
1715 (or (and (srl GPR:$src, (i32 8)), 0xFF),
1716 (or (and (shl GPR:$src, (i32 8)), 0xFF00),
1717 (or (and (srl GPR:$src, (i32 8)), 0xFF0000),
1718 (and (shl GPR:$src, (i32 8)), 0xFF000000)))))]>,
1719 Requires<[IsARM, HasV6]> {
1720 let Inst{7-4} = 0b1011;
1721 let Inst{11-8} = 0b1111;
1722 let Inst{19-16} = 0b1111;
1725 def REVSH : AMiscA1I<0b01101111, (outs GPR:$dst), (ins GPR:$src), IIC_iUNAr,
1726 "revsh", "\t$dst, $src",
1729 (or (srl (and GPR:$src, 0xFF00), (i32 8)),
1730 (shl GPR:$src, (i32 8))), i16))]>,
1731 Requires<[IsARM, HasV6]> {
1732 let Inst{7-4} = 0b1011;
1733 let Inst{11-8} = 0b1111;
1734 let Inst{19-16} = 0b1111;
1737 def PKHBT : AMiscA1I<0b01101000, (outs GPR:$dst),
1738 (ins GPR:$src1, GPR:$src2, i32imm:$shamt),
1739 IIC_iALUsi, "pkhbt", "\t$dst, $src1, $src2, LSL $shamt",
1740 [(set GPR:$dst, (or (and GPR:$src1, 0xFFFF),
1741 (and (shl GPR:$src2, (i32 imm:$shamt)),
1743 Requires<[IsARM, HasV6]> {
1744 let Inst{6-4} = 0b001;
1747 // Alternate cases for PKHBT where identities eliminate some nodes.
1748 def : ARMV6Pat<(or (and GPR:$src1, 0xFFFF), (and GPR:$src2, 0xFFFF0000)),
1749 (PKHBT GPR:$src1, GPR:$src2, 0)>;
1750 def : ARMV6Pat<(or (and GPR:$src1, 0xFFFF), (shl GPR:$src2, imm16_31:$shamt)),
1751 (PKHBT GPR:$src1, GPR:$src2, imm16_31:$shamt)>;
1754 def PKHTB : AMiscA1I<0b01101000, (outs GPR:$dst),
1755 (ins GPR:$src1, GPR:$src2, i32imm:$shamt),
1756 IIC_iALUsi, "pkhtb", "\t$dst, $src1, $src2, ASR $shamt",
1757 [(set GPR:$dst, (or (and GPR:$src1, 0xFFFF0000),
1758 (and (sra GPR:$src2, imm16_31:$shamt),
1759 0xFFFF)))]>, Requires<[IsARM, HasV6]> {
1760 let Inst{6-4} = 0b101;
1763 // Alternate cases for PKHTB where identities eliminate some nodes. Note that
1764 // a shift amount of 0 is *not legal* here, it is PKHBT instead.
1765 def : ARMV6Pat<(or (and GPR:$src1, 0xFFFF0000), (srl GPR:$src2, (i32 16))),
1766 (PKHTB GPR:$src1, GPR:$src2, 16)>;
1767 def : ARMV6Pat<(or (and GPR:$src1, 0xFFFF0000),
1768 (and (srl GPR:$src2, imm1_15:$shamt), 0xFFFF)),
1769 (PKHTB GPR:$src1, GPR:$src2, imm1_15:$shamt)>;
1771 //===----------------------------------------------------------------------===//
1772 // Comparison Instructions...
1775 defm CMP : AI1_cmp_irs<0b1010, "cmp",
1776 BinOpFrag<(ARMcmp node:$LHS, node:$RHS)>>;
1777 //FIXME: Disable CMN, as CCodes are backwards from compare expectations
1778 // Compare-to-zero still works out, just not the relationals
1779 //defm CMN : AI1_cmp_irs<0b1011, "cmn",
1780 // BinOpFrag<(ARMcmp node:$LHS,(ineg node:$RHS))>>;
1782 // Note that TST/TEQ don't set all the same flags that CMP does!
1783 defm TST : AI1_cmp_irs<0b1000, "tst",
1784 BinOpFrag<(ARMcmpZ (and node:$LHS, node:$RHS), 0)>, 1>;
1785 defm TEQ : AI1_cmp_irs<0b1001, "teq",
1786 BinOpFrag<(ARMcmpZ (xor node:$LHS, node:$RHS), 0)>, 1>;
1788 defm CMPz : AI1_cmp_irs<0b1010, "cmp",
1789 BinOpFrag<(ARMcmpZ node:$LHS, node:$RHS)>>;
1790 defm CMNz : AI1_cmp_irs<0b1011, "cmn",
1791 BinOpFrag<(ARMcmpZ node:$LHS,(ineg node:$RHS))>>;
1793 //def : ARMPat<(ARMcmp GPR:$src, so_imm_neg:$imm),
1794 // (CMNri GPR:$src, so_imm_neg:$imm)>;
1796 def : ARMPat<(ARMcmpZ GPR:$src, so_imm_neg:$imm),
1797 (CMNzri GPR:$src, so_imm_neg:$imm)>;
1800 // Conditional moves
1801 // FIXME: should be able to write a pattern for ARMcmov, but can't use
1802 // a two-value operand where a dag node expects two operands. :(
1803 def MOVCCr : AI1<0b1101, (outs GPR:$dst), (ins GPR:$false, GPR:$true), DPFrm,
1804 IIC_iCMOVr, "mov", "\t$dst, $true",
1805 [/*(set GPR:$dst, (ARMcmov GPR:$false, GPR:$true, imm:$cc, CCR:$ccr))*/]>,
1806 RegConstraint<"$false = $dst">, UnaryDP {
1807 let Inst{11-4} = 0b00000000;
1811 def MOVCCs : AI1<0b1101, (outs GPR:$dst),
1812 (ins GPR:$false, so_reg:$true), DPSoRegFrm, IIC_iCMOVsr,
1813 "mov", "\t$dst, $true",
1814 [/*(set GPR:$dst, (ARMcmov GPR:$false, so_reg:$true, imm:$cc, CCR:$ccr))*/]>,
1815 RegConstraint<"$false = $dst">, UnaryDP {
1819 def MOVCCi : AI1<0b1101, (outs GPR:$dst),
1820 (ins GPR:$false, so_imm:$true), DPFrm, IIC_iCMOVi,
1821 "mov", "\t$dst, $true",
1822 [/*(set GPR:$dst, (ARMcmov GPR:$false, so_imm:$true, imm:$cc, CCR:$ccr))*/]>,
1823 RegConstraint<"$false = $dst">, UnaryDP {
1827 //===----------------------------------------------------------------------===//
1828 // Atomic operations intrinsics
1831 // memory barriers protect the atomic sequences
1832 let hasSideEffects = 1 in {
1833 def Int_MemBarrierV7 : AInoP<(outs), (ins),
1834 Pseudo, NoItinerary,
1836 [(ARMMemBarrierV7)]>,
1837 Requires<[IsARM, HasV7]> {
1838 let Inst{31-4} = 0xf57ff05;
1839 // FIXME: add support for options other than a full system DMB
1840 let Inst{3-0} = 0b1111;
1843 def Int_SyncBarrierV7 : AInoP<(outs), (ins),
1844 Pseudo, NoItinerary,
1846 [(ARMSyncBarrierV7)]>,
1847 Requires<[IsARM, HasV7]> {
1848 let Inst{31-4} = 0xf57ff04;
1849 // FIXME: add support for options other than a full system DSB
1850 let Inst{3-0} = 0b1111;
1853 def Int_MemBarrierV6 : AInoP<(outs), (ins GPR:$zero),
1854 Pseudo, NoItinerary,
1855 "mcr", "\tp15, 0, $zero, c7, c10, 5",
1856 [(ARMMemBarrierV6 GPR:$zero)]>,
1857 Requires<[IsARM, HasV6]> {
1858 // FIXME: add support for options other than a full system DMB
1859 // FIXME: add encoding
1862 def Int_SyncBarrierV6 : AInoP<(outs), (ins GPR:$zero),
1863 Pseudo, NoItinerary,
1864 "mcr", "\tp15, 0, $zero, c7, c10, 4",
1865 [(ARMSyncBarrierV6 GPR:$zero)]>,
1866 Requires<[IsARM, HasV6]> {
1867 // FIXME: add support for options other than a full system DSB
1868 // FIXME: add encoding
1872 let usesCustomInserter = 1 in {
1873 let Uses = [CPSR] in {
1874 def ATOMIC_LOAD_ADD_I8 : PseudoInst<
1875 (outs GPR:$dst), (ins GPR:$ptr, GPR:$incr), NoItinerary,
1876 "${:comment} ATOMIC_LOAD_ADD_I8 PSEUDO!",
1877 [(set GPR:$dst, (atomic_load_add_8 GPR:$ptr, GPR:$incr))]>;
1878 def ATOMIC_LOAD_SUB_I8 : PseudoInst<
1879 (outs GPR:$dst), (ins GPR:$ptr, GPR:$incr), NoItinerary,
1880 "${:comment} ATOMIC_LOAD_SUB_I8 PSEUDO!",
1881 [(set GPR:$dst, (atomic_load_sub_8 GPR:$ptr, GPR:$incr))]>;
1882 def ATOMIC_LOAD_AND_I8 : PseudoInst<
1883 (outs GPR:$dst), (ins GPR:$ptr, GPR:$incr), NoItinerary,
1884 "${:comment} ATOMIC_LOAD_AND_I8 PSEUDO!",
1885 [(set GPR:$dst, (atomic_load_and_8 GPR:$ptr, GPR:$incr))]>;
1886 def ATOMIC_LOAD_OR_I8 : PseudoInst<
1887 (outs GPR:$dst), (ins GPR:$ptr, GPR:$incr), NoItinerary,
1888 "${:comment} ATOMIC_LOAD_OR_I8 PSEUDO!",
1889 [(set GPR:$dst, (atomic_load_or_8 GPR:$ptr, GPR:$incr))]>;
1890 def ATOMIC_LOAD_XOR_I8 : PseudoInst<
1891 (outs GPR:$dst), (ins GPR:$ptr, GPR:$incr), NoItinerary,
1892 "${:comment} ATOMIC_LOAD_XOR_I8 PSEUDO!",
1893 [(set GPR:$dst, (atomic_load_xor_8 GPR:$ptr, GPR:$incr))]>;
1894 def ATOMIC_LOAD_NAND_I8 : PseudoInst<
1895 (outs GPR:$dst), (ins GPR:$ptr, GPR:$incr), NoItinerary,
1896 "${:comment} ATOMIC_LOAD_NAND_I8 PSEUDO!",
1897 [(set GPR:$dst, (atomic_load_nand_8 GPR:$ptr, GPR:$incr))]>;
1898 def ATOMIC_LOAD_ADD_I16 : PseudoInst<
1899 (outs GPR:$dst), (ins GPR:$ptr, GPR:$incr), NoItinerary,
1900 "${:comment} ATOMIC_LOAD_ADD_I16 PSEUDO!",
1901 [(set GPR:$dst, (atomic_load_add_16 GPR:$ptr, GPR:$incr))]>;
1902 def ATOMIC_LOAD_SUB_I16 : PseudoInst<
1903 (outs GPR:$dst), (ins GPR:$ptr, GPR:$incr), NoItinerary,
1904 "${:comment} ATOMIC_LOAD_SUB_I16 PSEUDO!",
1905 [(set GPR:$dst, (atomic_load_sub_16 GPR:$ptr, GPR:$incr))]>;
1906 def ATOMIC_LOAD_AND_I16 : PseudoInst<
1907 (outs GPR:$dst), (ins GPR:$ptr, GPR:$incr), NoItinerary,
1908 "${:comment} ATOMIC_LOAD_AND_I16 PSEUDO!",
1909 [(set GPR:$dst, (atomic_load_and_16 GPR:$ptr, GPR:$incr))]>;
1910 def ATOMIC_LOAD_OR_I16 : PseudoInst<
1911 (outs GPR:$dst), (ins GPR:$ptr, GPR:$incr), NoItinerary,
1912 "${:comment} ATOMIC_LOAD_OR_I16 PSEUDO!",
1913 [(set GPR:$dst, (atomic_load_or_16 GPR:$ptr, GPR:$incr))]>;
1914 def ATOMIC_LOAD_XOR_I16 : PseudoInst<
1915 (outs GPR:$dst), (ins GPR:$ptr, GPR:$incr), NoItinerary,
1916 "${:comment} ATOMIC_LOAD_XOR_I16 PSEUDO!",
1917 [(set GPR:$dst, (atomic_load_xor_16 GPR:$ptr, GPR:$incr))]>;
1918 def ATOMIC_LOAD_NAND_I16 : PseudoInst<
1919 (outs GPR:$dst), (ins GPR:$ptr, GPR:$incr), NoItinerary,
1920 "${:comment} ATOMIC_LOAD_NAND_I16 PSEUDO!",
1921 [(set GPR:$dst, (atomic_load_nand_16 GPR:$ptr, GPR:$incr))]>;
1922 def ATOMIC_LOAD_ADD_I32 : PseudoInst<
1923 (outs GPR:$dst), (ins GPR:$ptr, GPR:$incr), NoItinerary,
1924 "${:comment} ATOMIC_LOAD_ADD_I32 PSEUDO!",
1925 [(set GPR:$dst, (atomic_load_add_32 GPR:$ptr, GPR:$incr))]>;
1926 def ATOMIC_LOAD_SUB_I32 : PseudoInst<
1927 (outs GPR:$dst), (ins GPR:$ptr, GPR:$incr), NoItinerary,
1928 "${:comment} ATOMIC_LOAD_SUB_I32 PSEUDO!",
1929 [(set GPR:$dst, (atomic_load_sub_32 GPR:$ptr, GPR:$incr))]>;
1930 def ATOMIC_LOAD_AND_I32 : PseudoInst<
1931 (outs GPR:$dst), (ins GPR:$ptr, GPR:$incr), NoItinerary,
1932 "${:comment} ATOMIC_LOAD_AND_I32 PSEUDO!",
1933 [(set GPR:$dst, (atomic_load_and_32 GPR:$ptr, GPR:$incr))]>;
1934 def ATOMIC_LOAD_OR_I32 : PseudoInst<
1935 (outs GPR:$dst), (ins GPR:$ptr, GPR:$incr), NoItinerary,
1936 "${:comment} ATOMIC_LOAD_OR_I32 PSEUDO!",
1937 [(set GPR:$dst, (atomic_load_or_32 GPR:$ptr, GPR:$incr))]>;
1938 def ATOMIC_LOAD_XOR_I32 : PseudoInst<
1939 (outs GPR:$dst), (ins GPR:$ptr, GPR:$incr), NoItinerary,
1940 "${:comment} ATOMIC_LOAD_XOR_I32 PSEUDO!",
1941 [(set GPR:$dst, (atomic_load_xor_32 GPR:$ptr, GPR:$incr))]>;
1942 def ATOMIC_LOAD_NAND_I32 : PseudoInst<
1943 (outs GPR:$dst), (ins GPR:$ptr, GPR:$incr), NoItinerary,
1944 "${:comment} ATOMIC_LOAD_NAND_I32 PSEUDO!",
1945 [(set GPR:$dst, (atomic_load_nand_32 GPR:$ptr, GPR:$incr))]>;
1947 def ATOMIC_SWAP_I8 : PseudoInst<
1948 (outs GPR:$dst), (ins GPR:$ptr, GPR:$new), NoItinerary,
1949 "${:comment} ATOMIC_SWAP_I8 PSEUDO!",
1950 [(set GPR:$dst, (atomic_swap_8 GPR:$ptr, GPR:$new))]>;
1951 def ATOMIC_SWAP_I16 : PseudoInst<
1952 (outs GPR:$dst), (ins GPR:$ptr, GPR:$new), NoItinerary,
1953 "${:comment} ATOMIC_SWAP_I16 PSEUDO!",
1954 [(set GPR:$dst, (atomic_swap_16 GPR:$ptr, GPR:$new))]>;
1955 def ATOMIC_SWAP_I32 : PseudoInst<
1956 (outs GPR:$dst), (ins GPR:$ptr, GPR:$new), NoItinerary,
1957 "${:comment} ATOMIC_SWAP_I32 PSEUDO!",
1958 [(set GPR:$dst, (atomic_swap_32 GPR:$ptr, GPR:$new))]>;
1960 def ATOMIC_CMP_SWAP_I8 : PseudoInst<
1961 (outs GPR:$dst), (ins GPR:$ptr, GPR:$old, GPR:$new), NoItinerary,
1962 "${:comment} ATOMIC_CMP_SWAP_I8 PSEUDO!",
1963 [(set GPR:$dst, (atomic_cmp_swap_8 GPR:$ptr, GPR:$old, GPR:$new))]>;
1964 def ATOMIC_CMP_SWAP_I16 : PseudoInst<
1965 (outs GPR:$dst), (ins GPR:$ptr, GPR:$old, GPR:$new), NoItinerary,
1966 "${:comment} ATOMIC_CMP_SWAP_I16 PSEUDO!",
1967 [(set GPR:$dst, (atomic_cmp_swap_16 GPR:$ptr, GPR:$old, GPR:$new))]>;
1968 def ATOMIC_CMP_SWAP_I32 : PseudoInst<
1969 (outs GPR:$dst), (ins GPR:$ptr, GPR:$old, GPR:$new), NoItinerary,
1970 "${:comment} ATOMIC_CMP_SWAP_I32 PSEUDO!",
1971 [(set GPR:$dst, (atomic_cmp_swap_32 GPR:$ptr, GPR:$old, GPR:$new))]>;
1975 let mayLoad = 1 in {
1976 def LDREXB : AIldrex<0b10, (outs GPR:$dest), (ins GPR:$ptr), NoItinerary,
1977 "ldrexb", "\t$dest, [$ptr]",
1979 def LDREXH : AIldrex<0b11, (outs GPR:$dest), (ins GPR:$ptr), NoItinerary,
1980 "ldrexh", "\t$dest, [$ptr]",
1982 def LDREX : AIldrex<0b00, (outs GPR:$dest), (ins GPR:$ptr), NoItinerary,
1983 "ldrex", "\t$dest, [$ptr]",
1985 def LDREXD : AIldrex<0b01, (outs GPR:$dest, GPR:$dest2), (ins GPR:$ptr),
1987 "ldrexd", "\t$dest, $dest2, [$ptr]",
1991 let mayStore = 1, Constraints = "@earlyclobber $success" in {
1992 def STREXB : AIstrex<0b10, (outs GPR:$success), (ins GPR:$src, GPR:$ptr),
1994 "strexb", "\t$success, $src, [$ptr]",
1996 def STREXH : AIstrex<0b11, (outs GPR:$success), (ins GPR:$src, GPR:$ptr),
1998 "strexh", "\t$success, $src, [$ptr]",
2000 def STREX : AIstrex<0b00, (outs GPR:$success), (ins GPR:$src, GPR:$ptr),
2002 "strex", "\t$success, $src, [$ptr]",
2004 def STREXD : AIstrex<0b01, (outs GPR:$success),
2005 (ins GPR:$src, GPR:$src2, GPR:$ptr),
2007 "strexd", "\t$success, $src, $src2, [$ptr]",
2011 // SWP/SWPB are deprecated in V6/V7 and for disassembly only.
2012 let mayLoad = 1 in {
2013 def SWP : AI<(outs GPR:$dst), (ins GPR:$src, GPR:$ptr), LdStExFrm, NoItinerary,
2014 "swp", "\t$dst, $src, [$ptr]",
2015 [/* For disassembly only; pattern left blank */]> {
2016 let Inst{27-23} = 0b00010;
2017 let Inst{22} = 0; // B = 0
2018 let Inst{21-20} = 0b00;
2019 let Inst{7-4} = 0b1001;
2022 def SWPB : AI<(outs GPR:$dst), (ins GPR:$src, GPR:$ptr), LdStExFrm, NoItinerary,
2023 "swpb", "\t$dst, $src, [$ptr]",
2024 [/* For disassembly only; pattern left blank */]> {
2025 let Inst{27-23} = 0b00010;
2026 let Inst{22} = 1; // B = 1
2027 let Inst{21-20} = 0b00;
2028 let Inst{7-4} = 0b1001;
2032 //===----------------------------------------------------------------------===//
2036 // __aeabi_read_tp preserves the registers r1-r3.
2038 Defs = [R0, R12, LR, CPSR] in {
2039 def TPsoft : ABXI<0b1011, (outs), (ins), IIC_Br,
2040 "bl\t__aeabi_read_tp",
2041 [(set R0, ARMthread_pointer)]>;
2044 //===----------------------------------------------------------------------===//
2045 // SJLJ Exception handling intrinsics
2046 // eh_sjlj_setjmp() is an instruction sequence to store the return
2047 // address and save #0 in R0 for the non-longjmp case.
2048 // Since by its nature we may be coming from some other function to get
2049 // here, and we're using the stack frame for the containing function to
2050 // save/restore registers, we can't keep anything live in regs across
2051 // the eh_sjlj_setjmp(), else it will almost certainly have been tromped upon
2052 // when we get here from a longjmp(). We force everthing out of registers
2053 // except for our own input by listing the relevant registers in Defs. By
2054 // doing so, we also cause the prologue/epilogue code to actively preserve
2055 // all of the callee-saved resgisters, which is exactly what we want.
2056 // A constant value is passed in $val, and we use the location as a scratch.
2058 [ R0, R1, R2, R3, R4, R5, R6, R7, R8, R9, R10, R11, R12, LR, D0,
2059 D1, D2, D3, D4, D5, D6, D7, D8, D9, D10, D11, D12, D13, D14, D15,
2060 D16, D17, D18, D19, D20, D21, D22, D23, D24, D25, D26, D27, D28, D29, D30,
2062 def Int_eh_sjlj_setjmp : XI<(outs), (ins GPR:$src, GPR:$val),
2063 AddrModeNone, SizeSpecial, IndexModeNone,
2064 Pseudo, NoItinerary,
2065 "str\tsp, [$src, #+8] @ eh_setjmp begin\n\t"
2066 "add\t$val, pc, #8\n\t"
2067 "str\t$val, [$src, #+4]\n\t"
2069 "add\tpc, pc, #0\n\t"
2070 "mov\tr0, #1 @ eh_setjmp end", "",
2071 [(set R0, (ARMeh_sjlj_setjmp GPR:$src, GPR:$val))]>;
2074 //===----------------------------------------------------------------------===//
2075 // Non-Instruction Patterns
2078 // Large immediate handling.
2080 // Two piece so_imms.
2081 let isReMaterializable = 1 in
2082 def MOVi2pieces : AI1x2<(outs GPR:$dst), (ins so_imm2part:$src),
2084 "mov", "\t$dst, $src",
2085 [(set GPR:$dst, so_imm2part:$src)]>,
2086 Requires<[IsARM, NoV6T2]>;
2088 def : ARMPat<(or GPR:$LHS, so_imm2part:$RHS),
2089 (ORRri (ORRri GPR:$LHS, (so_imm2part_1 imm:$RHS)),
2090 (so_imm2part_2 imm:$RHS))>;
2091 def : ARMPat<(xor GPR:$LHS, so_imm2part:$RHS),
2092 (EORri (EORri GPR:$LHS, (so_imm2part_1 imm:$RHS)),
2093 (so_imm2part_2 imm:$RHS))>;
2094 def : ARMPat<(add GPR:$LHS, so_imm2part:$RHS),
2095 (ADDri (ADDri GPR:$LHS, (so_imm2part_1 imm:$RHS)),
2096 (so_imm2part_2 imm:$RHS))>;
2097 def : ARMPat<(add GPR:$LHS, so_neg_imm2part:$RHS),
2098 (SUBri (SUBri GPR:$LHS, (so_neg_imm2part_1 imm:$RHS)),
2099 (so_neg_imm2part_2 imm:$RHS))>;
2101 // 32-bit immediate using movw + movt.
2102 // This is a single pseudo instruction, the benefit is that it can be remat'd
2103 // as a single unit instead of having to handle reg inputs.
2104 // FIXME: Remove this when we can do generalized remat.
2105 let isReMaterializable = 1 in
2106 def MOVi32imm : AI1x2<(outs GPR:$dst), (ins i32imm:$src), Pseudo, IIC_iMOVi,
2107 "movw", "\t$dst, ${src:lo16}\n\tmovt${p}\t$dst, ${src:hi16}",
2108 [(set GPR:$dst, (i32 imm:$src))]>,
2109 Requires<[IsARM, HasV6T2]>;
2111 // ConstantPool, GlobalAddress, and JumpTable
2112 def : ARMPat<(ARMWrapper tglobaladdr :$dst), (LEApcrel tglobaladdr :$dst)>,
2113 Requires<[IsARM, DontUseMovt]>;
2114 def : ARMPat<(ARMWrapper tconstpool :$dst), (LEApcrel tconstpool :$dst)>;
2115 def : ARMPat<(ARMWrapper tglobaladdr :$dst), (MOVi32imm tglobaladdr :$dst)>,
2116 Requires<[IsARM, UseMovt]>;
2117 def : ARMPat<(ARMWrapperJT tjumptable:$dst, imm:$id),
2118 (LEApcrelJT tjumptable:$dst, imm:$id)>;
2120 // TODO: add,sub,and, 3-instr forms?
2124 def : ARMPat<(ARMcall texternalsym:$func), (BL texternalsym:$func)>,
2125 Requires<[IsARM, IsNotDarwin]>;
2126 def : ARMPat<(ARMcall texternalsym:$func), (BLr9 texternalsym:$func)>,
2127 Requires<[IsARM, IsDarwin]>;
2129 // zextload i1 -> zextload i8
2130 def : ARMPat<(zextloadi1 addrmode2:$addr), (LDRB addrmode2:$addr)>;
2132 // extload -> zextload
2133 def : ARMPat<(extloadi1 addrmode2:$addr), (LDRB addrmode2:$addr)>;
2134 def : ARMPat<(extloadi8 addrmode2:$addr), (LDRB addrmode2:$addr)>;
2135 def : ARMPat<(extloadi16 addrmode3:$addr), (LDRH addrmode3:$addr)>;
2137 def : ARMPat<(extloadi8 addrmodepc:$addr), (PICLDRB addrmodepc:$addr)>;
2138 def : ARMPat<(extloadi16 addrmodepc:$addr), (PICLDRH addrmodepc:$addr)>;
2141 def : ARMV5TEPat<(mul (sra (shl GPR:$a, (i32 16)), (i32 16)),
2142 (sra (shl GPR:$b, (i32 16)), (i32 16))),
2143 (SMULBB GPR:$a, GPR:$b)>;
2144 def : ARMV5TEPat<(mul sext_16_node:$a, sext_16_node:$b),
2145 (SMULBB GPR:$a, GPR:$b)>;
2146 def : ARMV5TEPat<(mul (sra (shl GPR:$a, (i32 16)), (i32 16)),
2147 (sra GPR:$b, (i32 16))),
2148 (SMULBT GPR:$a, GPR:$b)>;
2149 def : ARMV5TEPat<(mul sext_16_node:$a, (sra GPR:$b, (i32 16))),
2150 (SMULBT GPR:$a, GPR:$b)>;
2151 def : ARMV5TEPat<(mul (sra GPR:$a, (i32 16)),
2152 (sra (shl GPR:$b, (i32 16)), (i32 16))),
2153 (SMULTB GPR:$a, GPR:$b)>;
2154 def : ARMV5TEPat<(mul (sra GPR:$a, (i32 16)), sext_16_node:$b),
2155 (SMULTB GPR:$a, GPR:$b)>;
2156 def : ARMV5TEPat<(sra (mul GPR:$a, (sra (shl GPR:$b, (i32 16)), (i32 16))),
2158 (SMULWB GPR:$a, GPR:$b)>;
2159 def : ARMV5TEPat<(sra (mul GPR:$a, sext_16_node:$b), (i32 16)),
2160 (SMULWB GPR:$a, GPR:$b)>;
2162 def : ARMV5TEPat<(add GPR:$acc,
2163 (mul (sra (shl GPR:$a, (i32 16)), (i32 16)),
2164 (sra (shl GPR:$b, (i32 16)), (i32 16)))),
2165 (SMLABB GPR:$a, GPR:$b, GPR:$acc)>;
2166 def : ARMV5TEPat<(add GPR:$acc,
2167 (mul sext_16_node:$a, sext_16_node:$b)),
2168 (SMLABB GPR:$a, GPR:$b, GPR:$acc)>;
2169 def : ARMV5TEPat<(add GPR:$acc,
2170 (mul (sra (shl GPR:$a, (i32 16)), (i32 16)),
2171 (sra GPR:$b, (i32 16)))),
2172 (SMLABT GPR:$a, GPR:$b, GPR:$acc)>;
2173 def : ARMV5TEPat<(add GPR:$acc,
2174 (mul sext_16_node:$a, (sra GPR:$b, (i32 16)))),
2175 (SMLABT GPR:$a, GPR:$b, GPR:$acc)>;
2176 def : ARMV5TEPat<(add GPR:$acc,
2177 (mul (sra GPR:$a, (i32 16)),
2178 (sra (shl GPR:$b, (i32 16)), (i32 16)))),
2179 (SMLATB GPR:$a, GPR:$b, GPR:$acc)>;
2180 def : ARMV5TEPat<(add GPR:$acc,
2181 (mul (sra GPR:$a, (i32 16)), sext_16_node:$b)),
2182 (SMLATB GPR:$a, GPR:$b, GPR:$acc)>;
2183 def : ARMV5TEPat<(add GPR:$acc,
2184 (sra (mul GPR:$a, (sra (shl GPR:$b, (i32 16)), (i32 16))),
2186 (SMLAWB GPR:$a, GPR:$b, GPR:$acc)>;
2187 def : ARMV5TEPat<(add GPR:$acc,
2188 (sra (mul GPR:$a, sext_16_node:$b), (i32 16))),
2189 (SMLAWB GPR:$a, GPR:$b, GPR:$acc)>;
2191 //===----------------------------------------------------------------------===//
2195 include "ARMInstrThumb.td"
2197 //===----------------------------------------------------------------------===//
2201 include "ARMInstrThumb2.td"
2203 //===----------------------------------------------------------------------===//
2204 // Floating Point Support
2207 include "ARMInstrVFP.td"
2209 //===----------------------------------------------------------------------===//
2210 // Advanced SIMD (NEON) Support
2213 include "ARMInstrNEON.td"
2215 //===----------------------------------------------------------------------===//
2216 // Coprocessor Instructions. For disassembly only.
2219 def CDP : ABI<0b1110, (outs), (ins nohash_imm:$cop, i32imm:$opc1,
2220 nohash_imm:$CRd, nohash_imm:$CRn, nohash_imm:$CRm, i32imm:$opc2),
2221 NoItinerary, "cdp", "\tp$cop, $opc1, cr$CRd, cr$CRn, cr$CRm, $opc2",
2222 [/* For disassembly only; pattern left blank */]> {
2226 def CDP2 : ABXI<0b1110, (outs), (ins nohash_imm:$cop, i32imm:$opc1,
2227 nohash_imm:$CRd, nohash_imm:$CRn, nohash_imm:$CRm, i32imm:$opc2),
2228 NoItinerary, "cdp2\tp$cop, $opc1, cr$CRd, cr$CRn, cr$CRm, $opc2",
2229 [/* For disassembly only; pattern left blank */]> {
2230 let Inst{31-28} = 0b1111;
2234 def MCR : ABI<0b1110, (outs), (ins nohash_imm:$cop, i32imm:$opc1,
2235 GPR:$Rt, nohash_imm:$CRn, nohash_imm:$CRm, i32imm:$opc2),
2236 NoItinerary, "mcr", "\tp$cop, $opc1, $Rt, cr$CRn, cr$CRm, $opc2",
2237 [/* For disassembly only; pattern left blank */]> {
2242 def MCR2 : ABXI<0b1110, (outs), (ins nohash_imm:$cop, i32imm:$opc1,
2243 GPR:$Rt, nohash_imm:$CRn, nohash_imm:$CRm, i32imm:$opc2),
2244 NoItinerary, "mcr2\tp$cop, $opc1, $Rt, cr$CRn, cr$CRm, $opc2",
2245 [/* For disassembly only; pattern left blank */]> {
2246 let Inst{31-28} = 0b1111;
2251 def MRC : ABI<0b1110, (outs), (ins nohash_imm:$cop, i32imm:$opc1,
2252 GPR:$Rt, nohash_imm:$CRn, nohash_imm:$CRm, i32imm:$opc2),
2253 NoItinerary, "mrc", "\tp$cop, $opc1, $Rt, cr$CRn, cr$CRm, $opc2",
2254 [/* For disassembly only; pattern left blank */]> {
2259 def MRC2 : ABXI<0b1110, (outs), (ins nohash_imm:$cop, i32imm:$opc1,
2260 GPR:$Rt, nohash_imm:$CRn, nohash_imm:$CRm, i32imm:$opc2),
2261 NoItinerary, "mrc2\tp$cop, $opc1, $Rt, cr$CRn, cr$CRm, $opc2",
2262 [/* For disassembly only; pattern left blank */]> {
2263 let Inst{31-28} = 0b1111;
2268 def MCRR : ABI<0b1100, (outs), (ins nohash_imm:$cop, i32imm:$opc,
2269 GPR:$Rt, GPR:$Rt2, nohash_imm:$CRm),
2270 NoItinerary, "mcrr", "\tp$cop, $opc, $Rt, $Rt2, cr$CRm",
2271 [/* For disassembly only; pattern left blank */]> {
2272 let Inst{23-20} = 0b0100;
2275 def MCRR2 : ABXI<0b1100, (outs), (ins nohash_imm:$cop, i32imm:$opc,
2276 GPR:$Rt, GPR:$Rt2, nohash_imm:$CRm),
2277 NoItinerary, "mcrr2\tp$cop, $opc, $Rt, $Rt2, cr$CRm",
2278 [/* For disassembly only; pattern left blank */]> {
2279 let Inst{31-28} = 0b1111;
2280 let Inst{23-20} = 0b0100;
2283 def MRRC : ABI<0b1100, (outs), (ins nohash_imm:$cop, i32imm:$opc,
2284 GPR:$Rt, GPR:$Rt2, nohash_imm:$CRm),
2285 NoItinerary, "mrrc", "\tp$cop, $opc, $Rt, $Rt2, cr$CRm",
2286 [/* For disassembly only; pattern left blank */]> {
2287 let Inst{23-20} = 0b0101;
2290 def MRRC2 : ABXI<0b1100, (outs), (ins nohash_imm:$cop, i32imm:$opc,
2291 GPR:$Rt, GPR:$Rt2, nohash_imm:$CRm),
2292 NoItinerary, "mrrc2\tp$cop, $opc, $Rt, $Rt2, cr$CRm",
2293 [/* For disassembly only; pattern left blank */]> {
2294 let Inst{31-28} = 0b1111;
2295 let Inst{23-20} = 0b0101;
2298 //===----------------------------------------------------------------------===//
2299 // Move between special register and ARM core register -- for disassembly only
2302 def MRS : ABI<0b0001,(outs GPR:$dst),(ins), NoItinerary, "mrs", "\t$dst, cpsr",
2303 [/* For disassembly only; pattern left blank */]> {
2304 let Inst{23-20} = 0b0000;
2305 let Inst{7-4} = 0b0000;
2308 def MRSsys : ABI<0b0001,(outs GPR:$dst),(ins), NoItinerary,"mrs","\t$dst, spsr",
2309 [/* For disassembly only; pattern left blank */]> {
2310 let Inst{23-20} = 0b0100;
2311 let Inst{7-4} = 0b0000;
2314 // FIXME: mask is ignored for the time being.
2315 def MSR : ABI<0b0001,(outs),(ins GPR:$src), NoItinerary, "mrs", "\tcpsr, $src",
2316 [/* For disassembly only; pattern left blank */]> {
2317 let Inst{23-20} = 0b0010;
2318 let Inst{7-4} = 0b0000;
2321 // FIXME: mask is ignored for the time being.
2322 def MSRsys : ABI<0b0001,(outs),(ins GPR:$src),NoItinerary,"mrs","\tspsr, $src",
2323 [/* For disassembly only; pattern left blank */]> {
2324 let Inst{23-20} = 0b0110;
2325 let Inst{7-4} = 0b0000;