1 //===- ARMInstrInfo.td - Target Description for ARM Target -*- tablegen -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file describes the ARM instructions in TableGen format.
12 //===----------------------------------------------------------------------===//
14 //===----------------------------------------------------------------------===//
15 // ARM specific DAG Nodes.
19 def SDT_ARMCallSeqStart : SDCallSeqStart<[ SDTCisVT<0, i32> ]>;
20 def SDT_ARMCallSeqEnd : SDCallSeqEnd<[ SDTCisVT<0, i32>, SDTCisVT<1, i32> ]>;
22 def SDT_ARMSaveCallPC : SDTypeProfile<0, 1, []>;
24 def SDT_ARMcall : SDTypeProfile<0, -1, [SDTCisPtrTy<0>]>;
26 def SDT_ARMCMov : SDTypeProfile<1, 3,
27 [SDTCisSameAs<0, 1>, SDTCisSameAs<0, 2>,
30 def SDT_ARMBrcond : SDTypeProfile<0, 2,
31 [SDTCisVT<0, OtherVT>, SDTCisVT<1, i32>]>;
33 def SDT_ARMBrJT : SDTypeProfile<0, 3,
34 [SDTCisPtrTy<0>, SDTCisVT<1, i32>,
37 def SDT_ARMBr2JT : SDTypeProfile<0, 4,
38 [SDTCisPtrTy<0>, SDTCisVT<1, i32>,
39 SDTCisVT<2, i32>, SDTCisVT<3, i32>]>;
41 def SDT_ARMBCC_i64 : SDTypeProfile<0, 6,
43 SDTCisVT<1, i32>, SDTCisVT<2, i32>,
44 SDTCisVT<3, i32>, SDTCisVT<4, i32>,
45 SDTCisVT<5, OtherVT>]>;
47 def SDT_ARMAnd : SDTypeProfile<1, 2,
48 [SDTCisVT<0, i32>, SDTCisVT<1, i32>,
51 def SDT_ARMCmp : SDTypeProfile<0, 2, [SDTCisSameAs<0, 1>]>;
53 def SDT_ARMPICAdd : SDTypeProfile<1, 2, [SDTCisSameAs<0, 1>,
54 SDTCisPtrTy<1>, SDTCisVT<2, i32>]>;
56 def SDT_ARMThreadPointer : SDTypeProfile<1, 0, [SDTCisPtrTy<0>]>;
57 def SDT_ARMEH_SJLJ_Setjmp : SDTypeProfile<1, 2, [SDTCisInt<0>, SDTCisPtrTy<1>,
59 def SDT_ARMEH_SJLJ_Longjmp: SDTypeProfile<0, 2, [SDTCisPtrTy<0>, SDTCisInt<1>]>;
61 def SDT_ARMEH_SJLJ_DispatchSetup: SDTypeProfile<0, 1, [SDTCisInt<0>]>;
63 def SDT_ARMMEMBARRIER : SDTypeProfile<0, 1, [SDTCisInt<0>]>;
65 def SDT_ARMPREFETCH : SDTypeProfile<0, 3, [SDTCisPtrTy<0>, SDTCisSameAs<1, 2>,
68 def SDT_ARMTCRET : SDTypeProfile<0, 1, [SDTCisPtrTy<0>]>;
70 def SDT_ARMBFI : SDTypeProfile<1, 3, [SDTCisVT<0, i32>, SDTCisVT<1, i32>,
71 SDTCisVT<2, i32>, SDTCisVT<3, i32>]>;
73 def SDTBinaryArithWithFlags : SDTypeProfile<2, 2,
76 SDTCisInt<0>, SDTCisVT<1, i32>]>;
78 // SDTBinaryArithWithFlagsInOut - RES1, CPSR = op LHS, RHS, CPSR
79 def SDTBinaryArithWithFlagsInOut : SDTypeProfile<2, 3,
86 def ARMWrapper : SDNode<"ARMISD::Wrapper", SDTIntUnaryOp>;
87 def ARMWrapperDYN : SDNode<"ARMISD::WrapperDYN", SDTIntUnaryOp>;
88 def ARMWrapperPIC : SDNode<"ARMISD::WrapperPIC", SDTIntUnaryOp>;
89 def ARMWrapperJT : SDNode<"ARMISD::WrapperJT", SDTIntBinOp>;
91 def ARMcallseq_start : SDNode<"ISD::CALLSEQ_START", SDT_ARMCallSeqStart,
92 [SDNPHasChain, SDNPOutGlue]>;
93 def ARMcallseq_end : SDNode<"ISD::CALLSEQ_END", SDT_ARMCallSeqEnd,
94 [SDNPHasChain, SDNPOptInGlue, SDNPOutGlue]>;
96 def ARMcall : SDNode<"ARMISD::CALL", SDT_ARMcall,
97 [SDNPHasChain, SDNPOptInGlue, SDNPOutGlue,
99 def ARMcall_pred : SDNode<"ARMISD::CALL_PRED", SDT_ARMcall,
100 [SDNPHasChain, SDNPOptInGlue, SDNPOutGlue,
102 def ARMcall_nolink : SDNode<"ARMISD::CALL_NOLINK", SDT_ARMcall,
103 [SDNPHasChain, SDNPOptInGlue, SDNPOutGlue,
106 def ARMretflag : SDNode<"ARMISD::RET_FLAG", SDTNone,
107 [SDNPHasChain, SDNPOptInGlue]>;
109 def ARMcmov : SDNode<"ARMISD::CMOV", SDT_ARMCMov,
112 def ARMbrcond : SDNode<"ARMISD::BRCOND", SDT_ARMBrcond,
113 [SDNPHasChain, SDNPInGlue, SDNPOutGlue]>;
115 def ARMbrjt : SDNode<"ARMISD::BR_JT", SDT_ARMBrJT,
117 def ARMbr2jt : SDNode<"ARMISD::BR2_JT", SDT_ARMBr2JT,
120 def ARMBcci64 : SDNode<"ARMISD::BCC_i64", SDT_ARMBCC_i64,
123 def ARMcmp : SDNode<"ARMISD::CMP", SDT_ARMCmp,
126 def ARMcmpZ : SDNode<"ARMISD::CMPZ", SDT_ARMCmp,
127 [SDNPOutGlue, SDNPCommutative]>;
129 def ARMpic_add : SDNode<"ARMISD::PIC_ADD", SDT_ARMPICAdd>;
131 def ARMsrl_flag : SDNode<"ARMISD::SRL_FLAG", SDTIntUnaryOp, [SDNPOutGlue]>;
132 def ARMsra_flag : SDNode<"ARMISD::SRA_FLAG", SDTIntUnaryOp, [SDNPOutGlue]>;
133 def ARMrrx : SDNode<"ARMISD::RRX" , SDTIntUnaryOp, [SDNPInGlue ]>;
135 def ARMaddc : SDNode<"ARMISD::ADDC", SDTBinaryArithWithFlags,
137 def ARMsubc : SDNode<"ARMISD::SUBC", SDTBinaryArithWithFlags>;
138 def ARMadde : SDNode<"ARMISD::ADDE", SDTBinaryArithWithFlagsInOut>;
139 def ARMsube : SDNode<"ARMISD::SUBE", SDTBinaryArithWithFlagsInOut>;
141 def ARMthread_pointer: SDNode<"ARMISD::THREAD_POINTER", SDT_ARMThreadPointer>;
142 def ARMeh_sjlj_setjmp: SDNode<"ARMISD::EH_SJLJ_SETJMP",
143 SDT_ARMEH_SJLJ_Setjmp, [SDNPHasChain]>;
144 def ARMeh_sjlj_longjmp: SDNode<"ARMISD::EH_SJLJ_LONGJMP",
145 SDT_ARMEH_SJLJ_Longjmp, [SDNPHasChain]>;
146 def ARMeh_sjlj_dispatchsetup: SDNode<"ARMISD::EH_SJLJ_DISPATCHSETUP",
147 SDT_ARMEH_SJLJ_DispatchSetup, [SDNPHasChain]>;
150 def ARMMemBarrier : SDNode<"ARMISD::MEMBARRIER", SDT_ARMMEMBARRIER,
152 def ARMMemBarrierMCR : SDNode<"ARMISD::MEMBARRIER_MCR", SDT_ARMMEMBARRIER,
154 def ARMPreload : SDNode<"ARMISD::PRELOAD", SDT_ARMPREFETCH,
155 [SDNPHasChain, SDNPMayLoad, SDNPMayStore]>;
157 def ARMrbit : SDNode<"ARMISD::RBIT", SDTIntUnaryOp>;
159 def ARMtcret : SDNode<"ARMISD::TC_RETURN", SDT_ARMTCRET,
160 [SDNPHasChain, SDNPOptInGlue, SDNPVariadic]>;
163 def ARMbfi : SDNode<"ARMISD::BFI", SDT_ARMBFI>;
165 //===----------------------------------------------------------------------===//
166 // ARM Instruction Predicate Definitions.
168 def HasV4T : Predicate<"Subtarget->hasV4TOps()">,
169 AssemblerPredicate<"HasV4TOps">;
170 def NoV4T : Predicate<"!Subtarget->hasV4TOps()">;
171 def HasV5T : Predicate<"Subtarget->hasV5TOps()">;
172 def HasV5TE : Predicate<"Subtarget->hasV5TEOps()">,
173 AssemblerPredicate<"HasV5TEOps">;
174 def HasV6 : Predicate<"Subtarget->hasV6Ops()">,
175 AssemblerPredicate<"HasV6Ops">;
176 def NoV6 : Predicate<"!Subtarget->hasV6Ops()">;
177 def HasV6T2 : Predicate<"Subtarget->hasV6T2Ops()">,
178 AssemblerPredicate<"HasV6T2Ops">;
179 def NoV6T2 : Predicate<"!Subtarget->hasV6T2Ops()">;
180 def HasV7 : Predicate<"Subtarget->hasV7Ops()">,
181 AssemblerPredicate<"HasV7Ops">;
182 def NoVFP : Predicate<"!Subtarget->hasVFP2()">;
183 def HasVFP2 : Predicate<"Subtarget->hasVFP2()">,
184 AssemblerPredicate<"FeatureVFP2">;
185 def HasVFP3 : Predicate<"Subtarget->hasVFP3()">,
186 AssemblerPredicate<"FeatureVFP3">;
187 def HasNEON : Predicate<"Subtarget->hasNEON()">,
188 AssemblerPredicate<"FeatureNEON">;
189 def HasFP16 : Predicate<"Subtarget->hasFP16()">,
190 AssemblerPredicate<"FeatureFP16">;
191 def HasDivide : Predicate<"Subtarget->hasDivide()">,
192 AssemblerPredicate<"FeatureHWDiv">;
193 def HasT2ExtractPack : Predicate<"Subtarget->hasT2ExtractPack()">,
194 AssemblerPredicate<"FeatureT2XtPk">;
195 def HasThumb2DSP : Predicate<"Subtarget->hasThumb2DSP()">,
196 AssemblerPredicate<"FeatureDSPThumb2">;
197 def HasDB : Predicate<"Subtarget->hasDataBarrier()">,
198 AssemblerPredicate<"FeatureDB">;
199 def HasMP : Predicate<"Subtarget->hasMPExtension()">,
200 AssemblerPredicate<"FeatureMP">;
201 def UseNEONForFP : Predicate<"Subtarget->useNEONForSinglePrecisionFP()">;
202 def DontUseNEONForFP : Predicate<"!Subtarget->useNEONForSinglePrecisionFP()">;
203 def IsThumb : Predicate<"Subtarget->isThumb()">,
204 AssemblerPredicate<"ModeThumb">;
205 def IsThumb1Only : Predicate<"Subtarget->isThumb1Only()">;
206 def IsThumb2 : Predicate<"Subtarget->isThumb2()">,
207 AssemblerPredicate<"ModeThumb,FeatureThumb2">;
208 def IsARM : Predicate<"!Subtarget->isThumb()">,
209 AssemblerPredicate<"!ModeThumb">;
210 def IsDarwin : Predicate<"Subtarget->isTargetDarwin()">;
211 def IsNotDarwin : Predicate<"!Subtarget->isTargetDarwin()">;
212 def IsNaCl : Predicate<"Subtarget->isTargetNaCl()">,
213 AssemblerPredicate<"ModeNaCl">;
215 // FIXME: Eventually this will be just "hasV6T2Ops".
216 def UseMovt : Predicate<"Subtarget->useMovt()">;
217 def DontUseMovt : Predicate<"!Subtarget->useMovt()">;
218 def UseFPVMLx : Predicate<"Subtarget->useFPVMLx()">;
220 //===----------------------------------------------------------------------===//
221 // ARM Flag Definitions.
223 class RegConstraint<string C> {
224 string Constraints = C;
227 //===----------------------------------------------------------------------===//
228 // ARM specific transformation functions and pattern fragments.
231 // so_imm_neg_XFORM - Return a so_imm value packed into the format described for
232 // so_imm_neg def below.
233 def so_imm_neg_XFORM : SDNodeXForm<imm, [{
234 return CurDAG->getTargetConstant(-(int)N->getZExtValue(), MVT::i32);
237 // so_imm_not_XFORM - Return a so_imm value packed into the format described for
238 // so_imm_not def below.
239 def so_imm_not_XFORM : SDNodeXForm<imm, [{
240 return CurDAG->getTargetConstant(~(int)N->getZExtValue(), MVT::i32);
243 /// imm1_15 predicate - True if the 32-bit immediate is in the range [1,15].
244 def imm1_15 : ImmLeaf<i32, [{
245 return (int32_t)Imm >= 1 && (int32_t)Imm < 16;
248 /// imm16_31 predicate - True if the 32-bit immediate is in the range [16,31].
249 def imm16_31 : ImmLeaf<i32, [{
250 return (int32_t)Imm >= 16 && (int32_t)Imm < 32;
255 return ARM_AM::getSOImmVal(-(uint32_t)N->getZExtValue()) != -1;
256 }], so_imm_neg_XFORM>;
260 return ARM_AM::getSOImmVal(~(uint32_t)N->getZExtValue()) != -1;
261 }], so_imm_not_XFORM>;
263 // sext_16_node predicate - True if the SDNode is sign-extended 16 or more bits.
264 def sext_16_node : PatLeaf<(i32 GPR:$a), [{
265 return CurDAG->ComputeNumSignBits(SDValue(N,0)) >= 17;
268 /// Split a 32-bit immediate into two 16 bit parts.
269 def hi16 : SDNodeXForm<imm, [{
270 return CurDAG->getTargetConstant((uint32_t)N->getZExtValue() >> 16, MVT::i32);
273 def lo16AllZero : PatLeaf<(i32 imm), [{
274 // Returns true if all low 16-bits are 0.
275 return (((uint32_t)N->getZExtValue()) & 0xFFFFUL) == 0;
278 /// imm0_65535 - An immediate is in the range [0.65535].
279 def Imm0_65535AsmOperand: AsmOperandClass { let Name = "Imm0_65535"; }
280 def imm0_65535 : Operand<i32>, ImmLeaf<i32, [{
281 return Imm >= 0 && Imm < 65536;
283 let ParserMatchClass = Imm0_65535AsmOperand;
286 class BinOpWithFlagFrag<dag res> :
287 PatFrag<(ops node:$LHS, node:$RHS, node:$FLAG), res>;
288 class BinOpFrag<dag res> : PatFrag<(ops node:$LHS, node:$RHS), res>;
289 class UnOpFrag <dag res> : PatFrag<(ops node:$Src), res>;
291 // An 'and' node with a single use.
292 def and_su : PatFrag<(ops node:$lhs, node:$rhs), (and node:$lhs, node:$rhs), [{
293 return N->hasOneUse();
296 // An 'xor' node with a single use.
297 def xor_su : PatFrag<(ops node:$lhs, node:$rhs), (xor node:$lhs, node:$rhs), [{
298 return N->hasOneUse();
301 // An 'fmul' node with a single use.
302 def fmul_su : PatFrag<(ops node:$lhs, node:$rhs), (fmul node:$lhs, node:$rhs),[{
303 return N->hasOneUse();
306 // An 'fadd' node which checks for single non-hazardous use.
307 def fadd_mlx : PatFrag<(ops node:$lhs, node:$rhs),(fadd node:$lhs, node:$rhs),[{
308 return hasNoVMLxHazardUse(N);
311 // An 'fsub' node which checks for single non-hazardous use.
312 def fsub_mlx : PatFrag<(ops node:$lhs, node:$rhs),(fsub node:$lhs, node:$rhs),[{
313 return hasNoVMLxHazardUse(N);
316 //===----------------------------------------------------------------------===//
317 // Operand Definitions.
321 // FIXME: rename brtarget to t2_brtarget
322 def brtarget : Operand<OtherVT> {
323 let EncoderMethod = "getBranchTargetOpValue";
324 let OperandType = "OPERAND_PCREL";
325 let DecoderMethod = "DecodeT2BROperand";
328 // FIXME: get rid of this one?
329 def uncondbrtarget : Operand<OtherVT> {
330 let EncoderMethod = "getUnconditionalBranchTargetOpValue";
331 let OperandType = "OPERAND_PCREL";
334 // Branch target for ARM. Handles conditional/unconditional
335 def br_target : Operand<OtherVT> {
336 let EncoderMethod = "getARMBranchTargetOpValue";
337 let OperandType = "OPERAND_PCREL";
341 // FIXME: rename bltarget to t2_bl_target?
342 def bltarget : Operand<i32> {
343 // Encoded the same as branch targets.
344 let EncoderMethod = "getBranchTargetOpValue";
345 let OperandType = "OPERAND_PCREL";
348 // Call target for ARM. Handles conditional/unconditional
349 // FIXME: rename bl_target to t2_bltarget?
350 def bl_target : Operand<i32> {
351 // Encoded the same as branch targets.
352 let EncoderMethod = "getARMBranchTargetOpValue";
353 let OperandType = "OPERAND_PCREL";
356 def blx_target : Operand<i32> {
357 // Encoded the same as branch targets.
358 let EncoderMethod = "getARMBLXTargetOpValue";
359 let OperandType = "OPERAND_PCREL";
362 // A list of registers separated by comma. Used by load/store multiple.
363 def RegListAsmOperand : AsmOperandClass { let Name = "RegList"; }
364 def reglist : Operand<i32> {
365 let EncoderMethod = "getRegisterListOpValue";
366 let ParserMatchClass = RegListAsmOperand;
367 let PrintMethod = "printRegisterList";
368 let DecoderMethod = "DecodeRegListOperand";
371 def DPRRegListAsmOperand : AsmOperandClass { let Name = "DPRRegList"; }
372 def dpr_reglist : Operand<i32> {
373 let EncoderMethod = "getRegisterListOpValue";
374 let ParserMatchClass = DPRRegListAsmOperand;
375 let PrintMethod = "printRegisterList";
376 let DecoderMethod = "DecodeDPRRegListOperand";
379 def SPRRegListAsmOperand : AsmOperandClass { let Name = "SPRRegList"; }
380 def spr_reglist : Operand<i32> {
381 let EncoderMethod = "getRegisterListOpValue";
382 let ParserMatchClass = SPRRegListAsmOperand;
383 let PrintMethod = "printRegisterList";
384 let DecoderMethod = "DecodeSPRRegListOperand";
387 // An operand for the CONSTPOOL_ENTRY pseudo-instruction.
388 def cpinst_operand : Operand<i32> {
389 let PrintMethod = "printCPInstOperand";
393 def pclabel : Operand<i32> {
394 let PrintMethod = "printPCLabel";
397 // ADR instruction labels.
398 def adrlabel : Operand<i32> {
399 let EncoderMethod = "getAdrLabelOpValue";
402 def neon_vcvt_imm32 : Operand<i32> {
403 let EncoderMethod = "getNEONVcvtImm32OpValue";
404 let DecoderMethod = "DecodeVCVTImmOperand";
407 // rot_imm: An integer that encodes a rotate amount. Must be 8, 16, or 24.
408 def rot_imm_XFORM: SDNodeXForm<imm, [{
409 switch (N->getZExtValue()){
411 case 0: return CurDAG->getTargetConstant(0, MVT::i32);
412 case 8: return CurDAG->getTargetConstant(1, MVT::i32);
413 case 16: return CurDAG->getTargetConstant(2, MVT::i32);
414 case 24: return CurDAG->getTargetConstant(3, MVT::i32);
417 def RotImmAsmOperand : AsmOperandClass {
419 let ParserMethod = "parseRotImm";
421 def rot_imm : Operand<i32>, PatLeaf<(i32 imm), [{
422 int32_t v = N->getZExtValue();
423 return v == 8 || v == 16 || v == 24; }],
425 let PrintMethod = "printRotImmOperand";
426 let ParserMatchClass = RotImmAsmOperand;
429 // shift_imm: An integer that encodes a shift amount and the type of shift
430 // (asr or lsl). The 6-bit immediate encodes as:
433 // {4-0} imm5 shift amount.
434 // asr #32 encoded as imm5 == 0.
435 def ShifterImmAsmOperand : AsmOperandClass {
436 let Name = "ShifterImm";
437 let ParserMethod = "parseShifterImm";
439 def shift_imm : Operand<i32> {
440 let PrintMethod = "printShiftImmOperand";
441 let ParserMatchClass = ShifterImmAsmOperand;
444 // shifter_operand operands: so_reg_reg, so_reg_imm, and so_imm.
445 def ShiftedRegAsmOperand : AsmOperandClass { let Name = "RegShiftedReg"; }
446 def so_reg_reg : Operand<i32>, // reg reg imm
447 ComplexPattern<i32, 3, "SelectRegShifterOperand",
448 [shl, srl, sra, rotr]> {
449 let EncoderMethod = "getSORegRegOpValue";
450 let PrintMethod = "printSORegRegOperand";
451 let DecoderMethod = "DecodeSORegRegOperand";
452 let ParserMatchClass = ShiftedRegAsmOperand;
453 let MIOperandInfo = (ops GPRnopc, GPRnopc, i32imm);
456 def ShiftedImmAsmOperand : AsmOperandClass { let Name = "RegShiftedImm"; }
457 def so_reg_imm : Operand<i32>, // reg imm
458 ComplexPattern<i32, 2, "SelectImmShifterOperand",
459 [shl, srl, sra, rotr]> {
460 let EncoderMethod = "getSORegImmOpValue";
461 let PrintMethod = "printSORegImmOperand";
462 let DecoderMethod = "DecodeSORegImmOperand";
463 let ParserMatchClass = ShiftedImmAsmOperand;
464 let MIOperandInfo = (ops GPR, i32imm);
467 // FIXME: Does this need to be distinct from so_reg?
468 def shift_so_reg_reg : Operand<i32>, // reg reg imm
469 ComplexPattern<i32, 3, "SelectShiftRegShifterOperand",
470 [shl,srl,sra,rotr]> {
471 let EncoderMethod = "getSORegRegOpValue";
472 let PrintMethod = "printSORegRegOperand";
473 let DecoderMethod = "DecodeSORegRegOperand";
474 let MIOperandInfo = (ops GPR, GPR, i32imm);
477 // FIXME: Does this need to be distinct from so_reg?
478 def shift_so_reg_imm : Operand<i32>, // reg reg imm
479 ComplexPattern<i32, 2, "SelectShiftImmShifterOperand",
480 [shl,srl,sra,rotr]> {
481 let EncoderMethod = "getSORegImmOpValue";
482 let PrintMethod = "printSORegImmOperand";
483 let DecoderMethod = "DecodeSORegImmOperand";
484 let MIOperandInfo = (ops GPR, i32imm);
488 // so_imm - Match a 32-bit shifter_operand immediate operand, which is an
489 // 8-bit immediate rotated by an arbitrary number of bits.
490 def SOImmAsmOperand: AsmOperandClass { let Name = "ARMSOImm"; }
491 def so_imm : Operand<i32>, ImmLeaf<i32, [{
492 return ARM_AM::getSOImmVal(Imm) != -1;
494 let EncoderMethod = "getSOImmOpValue";
495 let ParserMatchClass = SOImmAsmOperand;
496 let DecoderMethod = "DecodeSOImmOperand";
499 // Break so_imm's up into two pieces. This handles immediates with up to 16
500 // bits set in them. This uses so_imm2part to match and so_imm2part_[12] to
501 // get the first/second pieces.
502 def so_imm2part : PatLeaf<(imm), [{
503 return ARM_AM::isSOImmTwoPartVal((unsigned)N->getZExtValue());
506 /// arm_i32imm - True for +V6T2, or true only if so_imm2part is true.
508 def arm_i32imm : PatLeaf<(imm), [{
509 if (Subtarget->hasV6T2Ops())
511 return ARM_AM::isSOImmTwoPartVal((unsigned)N->getZExtValue());
514 /// imm0_7 predicate - Immediate in the range [0,7].
515 def Imm0_7AsmOperand: AsmOperandClass { let Name = "Imm0_7"; }
516 def imm0_7 : Operand<i32>, ImmLeaf<i32, [{
517 return Imm >= 0 && Imm < 8;
519 let ParserMatchClass = Imm0_7AsmOperand;
522 /// imm0_15 predicate - Immediate in the range [0,15].
523 def Imm0_15AsmOperand: AsmOperandClass { let Name = "Imm0_15"; }
524 def imm0_15 : Operand<i32>, ImmLeaf<i32, [{
525 return Imm >= 0 && Imm < 16;
527 let ParserMatchClass = Imm0_15AsmOperand;
530 /// imm0_31 predicate - True if the 32-bit immediate is in the range [0,31].
531 def Imm0_31AsmOperand: AsmOperandClass { let Name = "Imm0_31"; }
532 def imm0_31 : Operand<i32>, ImmLeaf<i32, [{
533 return Imm >= 0 && Imm < 32;
535 let ParserMatchClass = Imm0_31AsmOperand;
538 /// imm0_255 predicate - Immediate in the range [0,255].
539 def Imm0_255AsmOperand : AsmOperandClass { let Name = "Imm0_255"; }
540 def imm0_255 : Operand<i32>, ImmLeaf<i32, [{ return Imm >= 0 && Imm < 256; }]> {
541 let ParserMatchClass = Imm0_255AsmOperand;
544 // imm0_65535_expr - For movt/movw - 16-bit immediate that can also reference
545 // a relocatable expression.
547 // FIXME: This really needs a Thumb version separate from the ARM version.
548 // While the range is the same, and can thus use the same match class,
549 // the encoding is different so it should have a different encoder method.
550 def Imm0_65535ExprAsmOperand: AsmOperandClass { let Name = "Imm0_65535Expr"; }
551 def imm0_65535_expr : Operand<i32> {
552 let EncoderMethod = "getHiLo16ImmOpValue";
553 let ParserMatchClass = Imm0_65535ExprAsmOperand;
556 /// imm24b - True if the 32-bit immediate is encodable in 24 bits.
557 def Imm24bitAsmOperand: AsmOperandClass { let Name = "Imm24bit"; }
558 def imm24b : Operand<i32>, ImmLeaf<i32, [{
559 return Imm >= 0 && Imm <= 0xffffff;
561 let ParserMatchClass = Imm24bitAsmOperand;
565 /// bf_inv_mask_imm predicate - An AND mask to clear an arbitrary width bitfield
567 def BitfieldAsmOperand : AsmOperandClass {
568 let Name = "Bitfield";
569 let ParserMethod = "parseBitfield";
571 def bf_inv_mask_imm : Operand<i32>,
573 return ARM::isBitFieldInvertedMask(N->getZExtValue());
575 let EncoderMethod = "getBitfieldInvertedMaskOpValue";
576 let PrintMethod = "printBitfieldInvMaskImmOperand";
577 let DecoderMethod = "DecodeBitfieldMaskOperand";
578 let ParserMatchClass = BitfieldAsmOperand;
581 /// lsb_pos_imm - position of the lsb bit, used by BFI4p and t2BFI4p
582 def lsb_pos_imm : Operand<i32>, ImmLeaf<i32, [{
583 return isInt<5>(Imm);
586 /// width_imm - number of bits to be copied, used by BFI4p and t2BFI4p
587 def width_imm : Operand<i32>, ImmLeaf<i32, [{
588 return Imm > 0 && Imm <= 32;
590 let EncoderMethod = "getMsbOpValue";
593 def imm1_32_XFORM: SDNodeXForm<imm, [{
594 return CurDAG->getTargetConstant((int)N->getZExtValue() - 1, MVT::i32);
596 def Imm1_32AsmOperand: AsmOperandClass { let Name = "Imm1_32"; }
597 def imm1_32 : Operand<i32>, PatLeaf<(imm), [{
598 uint64_t Imm = N->getZExtValue();
599 return Imm > 0 && Imm <= 32;
602 let PrintMethod = "printImmPlusOneOperand";
603 let ParserMatchClass = Imm1_32AsmOperand;
606 def imm1_16_XFORM: SDNodeXForm<imm, [{
607 return CurDAG->getTargetConstant((int)N->getZExtValue() - 1, MVT::i32);
609 def Imm1_16AsmOperand: AsmOperandClass { let Name = "Imm1_16"; }
610 def imm1_16 : Operand<i32>, PatLeaf<(imm), [{ return Imm > 0 && Imm <= 16; }],
612 let PrintMethod = "printImmPlusOneOperand";
613 let ParserMatchClass = Imm1_16AsmOperand;
616 // Define ARM specific addressing modes.
617 // addrmode_imm12 := reg +/- imm12
619 def MemImm12OffsetAsmOperand : AsmOperandClass { let Name = "MemImm12Offset"; }
620 def addrmode_imm12 : Operand<i32>,
621 ComplexPattern<i32, 2, "SelectAddrModeImm12", []> {
622 // 12-bit immediate operand. Note that instructions using this encode
623 // #0 and #-0 differently. We flag #-0 as the magic value INT32_MIN. All other
624 // immediate values are as normal.
626 let EncoderMethod = "getAddrModeImm12OpValue";
627 let PrintMethod = "printAddrModeImm12Operand";
628 let DecoderMethod = "DecodeAddrModeImm12Operand";
629 let ParserMatchClass = MemImm12OffsetAsmOperand;
630 let MIOperandInfo = (ops GPR:$base, i32imm:$offsimm);
632 // ldst_so_reg := reg +/- reg shop imm
634 def MemRegOffsetAsmOperand : AsmOperandClass { let Name = "MemRegOffset"; }
635 def ldst_so_reg : Operand<i32>,
636 ComplexPattern<i32, 3, "SelectLdStSOReg", []> {
637 let EncoderMethod = "getLdStSORegOpValue";
638 // FIXME: Simplify the printer
639 let PrintMethod = "printAddrMode2Operand";
640 let DecoderMethod = "DecodeSORegMemOperand";
641 let ParserMatchClass = MemRegOffsetAsmOperand;
642 let MIOperandInfo = (ops GPR:$base, GPRnopc:$offsreg, i32imm:$shift);
645 // postidx_imm8 := +/- [0,255]
648 // {8} 1 is imm8 is non-negative. 0 otherwise.
649 // {7-0} [0,255] imm8 value.
650 def PostIdxImm8AsmOperand : AsmOperandClass { let Name = "PostIdxImm8"; }
651 def postidx_imm8 : Operand<i32> {
652 let PrintMethod = "printPostIdxImm8Operand";
653 let ParserMatchClass = PostIdxImm8AsmOperand;
654 let MIOperandInfo = (ops i32imm);
657 // postidx_imm8s4 := +/- [0,1020]
660 // {8} 1 is imm8 is non-negative. 0 otherwise.
661 // {7-0} [0,255] imm8 value, scaled by 4.
662 def postidx_imm8s4 : Operand<i32> {
663 let PrintMethod = "printPostIdxImm8s4Operand";
664 let MIOperandInfo = (ops i32imm);
668 // postidx_reg := +/- reg
670 def PostIdxRegAsmOperand : AsmOperandClass {
671 let Name = "PostIdxReg";
672 let ParserMethod = "parsePostIdxReg";
674 def postidx_reg : Operand<i32> {
675 let EncoderMethod = "getPostIdxRegOpValue";
676 let DecoderMethod = "DecodePostIdxReg";
677 let PrintMethod = "printPostIdxRegOperand";
678 let ParserMatchClass = PostIdxRegAsmOperand;
679 let MIOperandInfo = (ops GPR, i32imm);
683 // addrmode2 := reg +/- imm12
684 // := reg +/- reg shop imm
686 // FIXME: addrmode2 should be refactored the rest of the way to always
687 // use explicit imm vs. reg versions above (addrmode_imm12 and ldst_so_reg).
688 def AddrMode2AsmOperand : AsmOperandClass { let Name = "AddrMode2"; }
689 def addrmode2 : Operand<i32>,
690 ComplexPattern<i32, 3, "SelectAddrMode2", []> {
691 let EncoderMethod = "getAddrMode2OpValue";
692 let PrintMethod = "printAddrMode2Operand";
693 let ParserMatchClass = AddrMode2AsmOperand;
694 let MIOperandInfo = (ops GPR:$base, GPR:$offsreg, i32imm:$offsimm);
697 def PostIdxRegShiftedAsmOperand : AsmOperandClass {
698 let Name = "PostIdxRegShifted";
699 let ParserMethod = "parsePostIdxReg";
701 def am2offset_reg : Operand<i32>,
702 ComplexPattern<i32, 2, "SelectAddrMode2OffsetReg",
703 [], [SDNPWantRoot]> {
704 let EncoderMethod = "getAddrMode2OffsetOpValue";
705 let PrintMethod = "printAddrMode2OffsetOperand";
706 // When using this for assembly, it's always as a post-index offset.
707 let ParserMatchClass = PostIdxRegShiftedAsmOperand;
708 let MIOperandInfo = (ops GPR, i32imm);
711 // FIXME: am2offset_imm should only need the immediate, not the GPR. Having
712 // the GPR is purely vestigal at this point.
713 def AM2OffsetImmAsmOperand : AsmOperandClass { let Name = "AM2OffsetImm"; }
714 def am2offset_imm : Operand<i32>,
715 ComplexPattern<i32, 2, "SelectAddrMode2OffsetImm",
716 [], [SDNPWantRoot]> {
717 let EncoderMethod = "getAddrMode2OffsetOpValue";
718 let PrintMethod = "printAddrMode2OffsetOperand";
719 let ParserMatchClass = AM2OffsetImmAsmOperand;
720 let MIOperandInfo = (ops GPR, i32imm);
724 // addrmode3 := reg +/- reg
725 // addrmode3 := reg +/- imm8
727 // FIXME: split into imm vs. reg versions.
728 def AddrMode3AsmOperand : AsmOperandClass { let Name = "AddrMode3"; }
729 def addrmode3 : Operand<i32>,
730 ComplexPattern<i32, 3, "SelectAddrMode3", []> {
731 let EncoderMethod = "getAddrMode3OpValue";
732 let PrintMethod = "printAddrMode3Operand";
733 let ParserMatchClass = AddrMode3AsmOperand;
734 let MIOperandInfo = (ops GPR:$base, GPR:$offsreg, i32imm:$offsimm);
737 // FIXME: split into imm vs. reg versions.
738 // FIXME: parser method to handle +/- register.
739 def AM3OffsetAsmOperand : AsmOperandClass {
740 let Name = "AM3Offset";
741 let ParserMethod = "parseAM3Offset";
743 def am3offset : Operand<i32>,
744 ComplexPattern<i32, 2, "SelectAddrMode3Offset",
745 [], [SDNPWantRoot]> {
746 let EncoderMethod = "getAddrMode3OffsetOpValue";
747 let PrintMethod = "printAddrMode3OffsetOperand";
748 let ParserMatchClass = AM3OffsetAsmOperand;
749 let MIOperandInfo = (ops GPR, i32imm);
752 // ldstm_mode := {ia, ib, da, db}
754 def ldstm_mode : OptionalDefOperand<OtherVT, (ops i32), (ops (i32 1))> {
755 let EncoderMethod = "getLdStmModeOpValue";
756 let PrintMethod = "printLdStmModeOperand";
759 // addrmode5 := reg +/- imm8*4
761 def AddrMode5AsmOperand : AsmOperandClass { let Name = "AddrMode5"; }
762 def addrmode5 : Operand<i32>,
763 ComplexPattern<i32, 2, "SelectAddrMode5", []> {
764 let PrintMethod = "printAddrMode5Operand";
765 let EncoderMethod = "getAddrMode5OpValue";
766 let DecoderMethod = "DecodeAddrMode5Operand";
767 let ParserMatchClass = AddrMode5AsmOperand;
768 let MIOperandInfo = (ops GPR:$base, i32imm);
771 // addrmode6 := reg with optional alignment
773 def addrmode6 : Operand<i32>,
774 ComplexPattern<i32, 2, "SelectAddrMode6", [], [SDNPWantParent]>{
775 let PrintMethod = "printAddrMode6Operand";
776 let MIOperandInfo = (ops GPR:$addr, i32imm);
777 let EncoderMethod = "getAddrMode6AddressOpValue";
778 let DecoderMethod = "DecodeAddrMode6Operand";
781 def am6offset : Operand<i32>,
782 ComplexPattern<i32, 1, "SelectAddrMode6Offset",
783 [], [SDNPWantRoot]> {
784 let PrintMethod = "printAddrMode6OffsetOperand";
785 let MIOperandInfo = (ops GPR);
786 let EncoderMethod = "getAddrMode6OffsetOpValue";
787 let DecoderMethod = "DecodeGPRRegisterClass";
790 // Special version of addrmode6 to handle alignment encoding for VST1/VLD1
791 // (single element from one lane) for size 32.
792 def addrmode6oneL32 : Operand<i32>,
793 ComplexPattern<i32, 2, "SelectAddrMode6", [], [SDNPWantParent]>{
794 let PrintMethod = "printAddrMode6Operand";
795 let MIOperandInfo = (ops GPR:$addr, i32imm);
796 let EncoderMethod = "getAddrMode6OneLane32AddressOpValue";
799 // Special version of addrmode6 to handle alignment encoding for VLD-dup
800 // instructions, specifically VLD4-dup.
801 def addrmode6dup : Operand<i32>,
802 ComplexPattern<i32, 2, "SelectAddrMode6", [], [SDNPWantParent]>{
803 let PrintMethod = "printAddrMode6Operand";
804 let MIOperandInfo = (ops GPR:$addr, i32imm);
805 let EncoderMethod = "getAddrMode6DupAddressOpValue";
808 // addrmodepc := pc + reg
810 def addrmodepc : Operand<i32>,
811 ComplexPattern<i32, 2, "SelectAddrModePC", []> {
812 let PrintMethod = "printAddrModePCOperand";
813 let MIOperandInfo = (ops GPR, i32imm);
816 // addr_offset_none := reg
818 def MemNoOffsetAsmOperand : AsmOperandClass { let Name = "MemNoOffset"; }
819 def addr_offset_none : Operand<i32>,
820 ComplexPattern<i32, 1, "SelectAddrOffsetNone", []> {
821 let PrintMethod = "printAddrMode7Operand";
822 let DecoderMethod = "DecodeAddrMode7Operand";
823 let ParserMatchClass = MemNoOffsetAsmOperand;
824 let MIOperandInfo = (ops GPR:$base);
827 def nohash_imm : Operand<i32> {
828 let PrintMethod = "printNoHashImmediate";
831 def CoprocNumAsmOperand : AsmOperandClass {
832 let Name = "CoprocNum";
833 let ParserMethod = "parseCoprocNumOperand";
835 def p_imm : Operand<i32> {
836 let PrintMethod = "printPImmediate";
837 let ParserMatchClass = CoprocNumAsmOperand;
838 let DecoderMethod = "DecodeCoprocessor";
841 def CoprocRegAsmOperand : AsmOperandClass {
842 let Name = "CoprocReg";
843 let ParserMethod = "parseCoprocRegOperand";
845 def c_imm : Operand<i32> {
846 let PrintMethod = "printCImmediate";
847 let ParserMatchClass = CoprocRegAsmOperand;
850 //===----------------------------------------------------------------------===//
852 include "ARMInstrFormats.td"
854 //===----------------------------------------------------------------------===//
855 // Multiclass helpers...
858 /// AsI1_bin_irs - Defines a set of (op r, {so_imm|r|so_reg}) patterns for a
859 /// binop that produces a value.
860 multiclass AsI1_bin_irs<bits<4> opcod, string opc,
861 InstrItinClass iii, InstrItinClass iir, InstrItinClass iis,
862 PatFrag opnode, string baseOpc, bit Commutable = 0> {
863 // The register-immediate version is re-materializable. This is useful
864 // in particular for taking the address of a local.
865 let isReMaterializable = 1 in {
866 def ri : AsI1<opcod, (outs GPR:$Rd), (ins GPR:$Rn, so_imm:$imm), DPFrm,
867 iii, opc, "\t$Rd, $Rn, $imm",
868 [(set GPR:$Rd, (opnode GPR:$Rn, so_imm:$imm))]> {
873 let Inst{19-16} = Rn;
874 let Inst{15-12} = Rd;
875 let Inst{11-0} = imm;
878 def rr : AsI1<opcod, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm), DPFrm,
879 iir, opc, "\t$Rd, $Rn, $Rm",
880 [(set GPR:$Rd, (opnode GPR:$Rn, GPR:$Rm))]> {
885 let isCommutable = Commutable;
886 let Inst{19-16} = Rn;
887 let Inst{15-12} = Rd;
888 let Inst{11-4} = 0b00000000;
892 def rsi : AsI1<opcod, (outs GPR:$Rd),
893 (ins GPR:$Rn, so_reg_imm:$shift), DPSoRegImmFrm,
894 iis, opc, "\t$Rd, $Rn, $shift",
895 [(set GPR:$Rd, (opnode GPR:$Rn, so_reg_imm:$shift))]> {
900 let Inst{19-16} = Rn;
901 let Inst{15-12} = Rd;
902 let Inst{11-5} = shift{11-5};
904 let Inst{3-0} = shift{3-0};
907 def rsr : AsI1<opcod, (outs GPR:$Rd),
908 (ins GPR:$Rn, so_reg_reg:$shift), DPSoRegRegFrm,
909 iis, opc, "\t$Rd, $Rn, $shift",
910 [(set GPR:$Rd, (opnode GPR:$Rn, so_reg_reg:$shift))]> {
915 let Inst{19-16} = Rn;
916 let Inst{15-12} = Rd;
917 let Inst{11-8} = shift{11-8};
919 let Inst{6-5} = shift{6-5};
921 let Inst{3-0} = shift{3-0};
924 // Assembly aliases for optional destination operand when it's the same
925 // as the source operand.
926 def : InstAlias<!strconcat(opc, "${s}${p} $Rdn, $imm"),
927 (!cast<Instruction>(!strconcat(baseOpc, "ri")) GPR:$Rdn, GPR:$Rdn,
928 so_imm:$imm, pred:$p,
931 def : InstAlias<!strconcat(opc, "${s}${p} $Rdn, $Rm"),
932 (!cast<Instruction>(!strconcat(baseOpc, "rr")) GPR:$Rdn, GPR:$Rdn,
936 def : InstAlias<!strconcat(opc, "${s}${p} $Rdn, $shift"),
937 (!cast<Instruction>(!strconcat(baseOpc, "rsi")) GPR:$Rdn, GPR:$Rdn,
938 so_reg_imm:$shift, pred:$p,
941 def : InstAlias<!strconcat(opc, "${s}${p} $Rdn, $shift"),
942 (!cast<Instruction>(!strconcat(baseOpc, "rsr")) GPR:$Rdn, GPR:$Rdn,
943 so_reg_reg:$shift, pred:$p,
949 /// AsI1_rbin_irs - Same as AsI1_bin_irs except the order of operands are
950 /// reversed. The 'rr' form is only defined for the disassembler; for codegen
951 /// it is equivalent to the AsI1_bin_irs counterpart.
952 multiclass AsI1_rbin_irs<bits<4> opcod, string opc,
953 InstrItinClass iii, InstrItinClass iir, InstrItinClass iis,
954 PatFrag opnode, string baseOpc, bit Commutable = 0> {
955 // The register-immediate version is re-materializable. This is useful
956 // in particular for taking the address of a local.
957 let isReMaterializable = 1 in {
958 def ri : AsI1<opcod, (outs GPR:$Rd), (ins GPR:$Rn, so_imm:$imm), DPFrm,
959 iii, opc, "\t$Rd, $Rn, $imm",
960 [(set GPR:$Rd, (opnode so_imm:$imm, GPR:$Rn))]> {
965 let Inst{19-16} = Rn;
966 let Inst{15-12} = Rd;
967 let Inst{11-0} = imm;
970 def rr : AsI1<opcod, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm), DPFrm,
971 iir, opc, "\t$Rd, $Rn, $Rm",
972 [/* pattern left blank */]> {
976 let Inst{11-4} = 0b00000000;
979 let Inst{15-12} = Rd;
980 let Inst{19-16} = Rn;
983 def rsi : AsI1<opcod, (outs GPR:$Rd),
984 (ins GPR:$Rn, so_reg_imm:$shift), DPSoRegImmFrm,
985 iis, opc, "\t$Rd, $Rn, $shift",
986 [(set GPR:$Rd, (opnode so_reg_imm:$shift, GPR:$Rn))]> {
991 let Inst{19-16} = Rn;
992 let Inst{15-12} = Rd;
993 let Inst{11-5} = shift{11-5};
995 let Inst{3-0} = shift{3-0};
998 def rsr : AsI1<opcod, (outs GPR:$Rd),
999 (ins GPR:$Rn, so_reg_reg:$shift), DPSoRegRegFrm,
1000 iis, opc, "\t$Rd, $Rn, $shift",
1001 [(set GPR:$Rd, (opnode so_reg_reg:$shift, GPR:$Rn))]> {
1006 let Inst{19-16} = Rn;
1007 let Inst{15-12} = Rd;
1008 let Inst{11-8} = shift{11-8};
1010 let Inst{6-5} = shift{6-5};
1012 let Inst{3-0} = shift{3-0};
1015 // Assembly aliases for optional destination operand when it's the same
1016 // as the source operand.
1017 def : InstAlias<!strconcat(opc, "${s}${p} $Rdn, $imm"),
1018 (!cast<Instruction>(!strconcat(baseOpc, "ri")) GPR:$Rdn, GPR:$Rdn,
1019 so_imm:$imm, pred:$p,
1022 def : InstAlias<!strconcat(opc, "${s}${p} $Rdn, $Rm"),
1023 (!cast<Instruction>(!strconcat(baseOpc, "rr")) GPR:$Rdn, GPR:$Rdn,
1027 def : InstAlias<!strconcat(opc, "${s}${p} $Rdn, $shift"),
1028 (!cast<Instruction>(!strconcat(baseOpc, "rsi")) GPR:$Rdn, GPR:$Rdn,
1029 so_reg_imm:$shift, pred:$p,
1032 def : InstAlias<!strconcat(opc, "${s}${p} $Rdn, $shift"),
1033 (!cast<Instruction>(!strconcat(baseOpc, "rsr")) GPR:$Rdn, GPR:$Rdn,
1034 so_reg_reg:$shift, pred:$p,
1040 /// AsI1_rbin_s_is - Same as AsI1_rbin_s_is except it sets 's' bit by default.
1041 let hasPostISelHook = 1, isCodeGenOnly = 1, Defs = [CPSR] in {
1042 multiclass AsI1_rbin_s_is<bits<4> opcod, string opc,
1043 InstrItinClass iii, InstrItinClass iir, InstrItinClass iis,
1044 PatFrag opnode, bit Commutable = 0> {
1045 def ri : AsI1<opcod, (outs GPR:$Rd), (ins GPR:$Rn, so_imm:$imm), DPFrm,
1046 iii, opc, "\t$Rd, $Rn, $imm",
1047 [(set GPR:$Rd, CPSR, (opnode so_imm:$imm, GPR:$Rn))]> {
1052 let Inst{19-16} = Rn;
1053 let Inst{15-12} = Rd;
1054 let Inst{11-0} = imm;
1057 def rr : AsI1<opcod, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm), DPFrm,
1058 iir, opc, "\t$Rd, $Rn, $Rm",
1059 [/* pattern left blank */]> {
1063 let Inst{11-4} = 0b00000000;
1066 let Inst{15-12} = Rd;
1067 let Inst{19-16} = Rn;
1070 def rsi : AsI1<opcod, (outs GPR:$Rd),
1071 (ins GPR:$Rn, so_reg_imm:$shift), DPSoRegImmFrm,
1072 iis, opc, "\t$Rd, $Rn, $shift",
1073 [(set GPR:$Rd, CPSR, (opnode so_reg_imm:$shift, GPR:$Rn))]> {
1078 let Inst{19-16} = Rn;
1079 let Inst{15-12} = Rd;
1080 let Inst{11-5} = shift{11-5};
1082 let Inst{3-0} = shift{3-0};
1085 def rsr : AsI1<opcod, (outs GPR:$Rd),
1086 (ins GPR:$Rn, so_reg_reg:$shift), DPSoRegRegFrm,
1087 iis, opc, "\t$Rd, $Rn, $shift",
1088 [(set GPR:$Rd, CPSR, (opnode so_reg_reg:$shift, GPR:$Rn))]> {
1093 let Inst{19-16} = Rn;
1094 let Inst{15-12} = Rd;
1095 let Inst{11-8} = shift{11-8};
1097 let Inst{6-5} = shift{6-5};
1099 let Inst{3-0} = shift{3-0};
1104 /// AsI1_bin_s_irs - Same as AsI1_bin_irs except it sets the 's' bit by default.
1105 let hasPostISelHook = 1, isCodeGenOnly = 1, Defs = [CPSR] in {
1106 multiclass AsI1_bin_s_irs<bits<4> opcod, string opc,
1107 InstrItinClass iii, InstrItinClass iir, InstrItinClass iis,
1108 PatFrag opnode, bit Commutable = 0> {
1109 let isReMaterializable = 1 in {
1110 def ri : AsI1<opcod, (outs GPR:$Rd), (ins GPR:$Rn, so_imm:$imm), DPFrm,
1111 iii, opc, "\t$Rd, $Rn, $imm",
1112 [(set GPR:$Rd, CPSR, (opnode GPR:$Rn, so_imm:$imm))]> {
1117 let Inst{19-16} = Rn;
1118 let Inst{15-12} = Rd;
1119 let Inst{11-0} = imm;
1122 def rr : AsI1<opcod, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm), DPFrm,
1123 iir, opc, "\t$Rd, $Rn, $Rm",
1124 [(set GPR:$Rd, CPSR, (opnode GPR:$Rn, GPR:$Rm))]> {
1128 let isCommutable = Commutable;
1130 let Inst{19-16} = Rn;
1131 let Inst{15-12} = Rd;
1132 let Inst{11-4} = 0b00000000;
1135 def rsi : AsI1<opcod, (outs GPR:$Rd),
1136 (ins GPR:$Rn, so_reg_imm:$shift), DPSoRegImmFrm,
1137 iis, opc, "\t$Rd, $Rn, $shift",
1138 [(set GPR:$Rd, CPSR, (opnode GPR:$Rn, so_reg_imm:$shift))]> {
1143 let Inst{19-16} = Rn;
1144 let Inst{15-12} = Rd;
1145 let Inst{11-5} = shift{11-5};
1147 let Inst{3-0} = shift{3-0};
1150 def rsr : AsI1<opcod, (outs GPR:$Rd),
1151 (ins GPR:$Rn, so_reg_reg:$shift), DPSoRegRegFrm,
1152 iis, opc, "\t$Rd, $Rn, $shift",
1153 [(set GPR:$Rd, CPSR, (opnode GPR:$Rn, so_reg_reg:$shift))]> {
1159 let Inst{19-16} = Rn;
1160 let Inst{15-12} = Rd;
1161 let Inst{11-8} = shift{11-8};
1163 let Inst{6-5} = shift{6-5};
1165 let Inst{3-0} = shift{3-0};
1170 /// AI1_cmp_irs - Defines a set of (op r, {so_imm|r|so_reg}) cmp / test
1171 /// patterns. Similar to AsI1_bin_irs except the instruction does not produce
1172 /// a explicit result, only implicitly set CPSR.
1173 let isCompare = 1, Defs = [CPSR] in {
1174 multiclass AI1_cmp_irs<bits<4> opcod, string opc,
1175 InstrItinClass iii, InstrItinClass iir, InstrItinClass iis,
1176 PatFrag opnode, bit Commutable = 0> {
1177 def ri : AI1<opcod, (outs), (ins GPR:$Rn, so_imm:$imm), DPFrm, iii,
1179 [(opnode GPR:$Rn, so_imm:$imm)]> {
1184 let Inst{19-16} = Rn;
1185 let Inst{15-12} = 0b0000;
1186 let Inst{11-0} = imm;
1188 def rr : AI1<opcod, (outs), (ins GPR:$Rn, GPR:$Rm), DPFrm, iir,
1190 [(opnode GPR:$Rn, GPR:$Rm)]> {
1193 let isCommutable = Commutable;
1196 let Inst{19-16} = Rn;
1197 let Inst{15-12} = 0b0000;
1198 let Inst{11-4} = 0b00000000;
1201 def rsi : AI1<opcod, (outs),
1202 (ins GPR:$Rn, so_reg_imm:$shift), DPSoRegImmFrm, iis,
1203 opc, "\t$Rn, $shift",
1204 [(opnode GPR:$Rn, so_reg_imm:$shift)]> {
1209 let Inst{19-16} = Rn;
1210 let Inst{15-12} = 0b0000;
1211 let Inst{11-5} = shift{11-5};
1213 let Inst{3-0} = shift{3-0};
1215 def rsr : AI1<opcod, (outs),
1216 (ins GPR:$Rn, so_reg_reg:$shift), DPSoRegRegFrm, iis,
1217 opc, "\t$Rn, $shift",
1218 [(opnode GPR:$Rn, so_reg_reg:$shift)]> {
1223 let Inst{19-16} = Rn;
1224 let Inst{15-12} = 0b0000;
1225 let Inst{11-8} = shift{11-8};
1227 let Inst{6-5} = shift{6-5};
1229 let Inst{3-0} = shift{3-0};
1235 /// AI_ext_rrot - A unary operation with two forms: one whose operand is a
1236 /// register and one whose operand is a register rotated by 8/16/24.
1237 /// FIXME: Remove the 'r' variant. Its rot_imm is zero.
1238 class AI_ext_rrot<bits<8> opcod, string opc, PatFrag opnode>
1239 : AExtI<opcod, (outs GPRnopc:$Rd), (ins GPRnopc:$Rm, rot_imm:$rot),
1240 IIC_iEXTr, opc, "\t$Rd, $Rm$rot",
1241 [(set GPRnopc:$Rd, (opnode (rotr GPRnopc:$Rm, rot_imm:$rot)))]>,
1242 Requires<[IsARM, HasV6]> {
1246 let Inst{19-16} = 0b1111;
1247 let Inst{15-12} = Rd;
1248 let Inst{11-10} = rot;
1252 class AI_ext_rrot_np<bits<8> opcod, string opc>
1253 : AExtI<opcod, (outs GPRnopc:$Rd), (ins GPRnopc:$Rm, rot_imm:$rot),
1254 IIC_iEXTr, opc, "\t$Rd, $Rm$rot", []>,
1255 Requires<[IsARM, HasV6]> {
1257 let Inst{19-16} = 0b1111;
1258 let Inst{11-10} = rot;
1261 /// AI_exta_rrot - A binary operation with two forms: one whose operand is a
1262 /// register and one whose operand is a register rotated by 8/16/24.
1263 class AI_exta_rrot<bits<8> opcod, string opc, PatFrag opnode>
1264 : AExtI<opcod, (outs GPRnopc:$Rd), (ins GPR:$Rn, GPRnopc:$Rm, rot_imm:$rot),
1265 IIC_iEXTAr, opc, "\t$Rd, $Rn, $Rm$rot",
1266 [(set GPRnopc:$Rd, (opnode GPR:$Rn,
1267 (rotr GPRnopc:$Rm, rot_imm:$rot)))]>,
1268 Requires<[IsARM, HasV6]> {
1273 let Inst{19-16} = Rn;
1274 let Inst{15-12} = Rd;
1275 let Inst{11-10} = rot;
1276 let Inst{9-4} = 0b000111;
1280 class AI_exta_rrot_np<bits<8> opcod, string opc>
1281 : AExtI<opcod, (outs GPRnopc:$Rd), (ins GPR:$Rn, GPRnopc:$Rm, rot_imm:$rot),
1282 IIC_iEXTAr, opc, "\t$Rd, $Rn, $Rm$rot", []>,
1283 Requires<[IsARM, HasV6]> {
1286 let Inst{19-16} = Rn;
1287 let Inst{11-10} = rot;
1290 /// AI1_adde_sube_irs - Define instructions and patterns for adde and sube.
1291 multiclass AI1_adde_sube_irs<bits<4> opcod, string opc, PatFrag opnode,
1292 string baseOpc, bit Commutable = 0> {
1293 let hasPostISelHook = 1, Defs = [CPSR], Uses = [CPSR] in {
1294 def ri : AsI1<opcod, (outs GPR:$Rd), (ins GPR:$Rn, so_imm:$imm),
1295 DPFrm, IIC_iALUi, opc, "\t$Rd, $Rn, $imm",
1296 [(set GPR:$Rd, CPSR, (opnode GPR:$Rn, so_imm:$imm, CPSR))]>,
1302 let Inst{15-12} = Rd;
1303 let Inst{19-16} = Rn;
1304 let Inst{11-0} = imm;
1306 def rr : AsI1<opcod, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm),
1307 DPFrm, IIC_iALUr, opc, "\t$Rd, $Rn, $Rm",
1308 [(set GPR:$Rd, CPSR, (opnode GPR:$Rn, GPR:$Rm, CPSR))]>,
1313 let Inst{11-4} = 0b00000000;
1315 let isCommutable = Commutable;
1317 let Inst{15-12} = Rd;
1318 let Inst{19-16} = Rn;
1320 def rsi : AsI1<opcod, (outs GPR:$Rd),
1321 (ins GPR:$Rn, so_reg_imm:$shift),
1322 DPSoRegImmFrm, IIC_iALUsr, opc, "\t$Rd, $Rn, $shift",
1323 [(set GPR:$Rd, CPSR, (opnode GPR:$Rn, so_reg_imm:$shift, CPSR))]>,
1329 let Inst{19-16} = Rn;
1330 let Inst{15-12} = Rd;
1331 let Inst{11-5} = shift{11-5};
1333 let Inst{3-0} = shift{3-0};
1335 def rsr : AsI1<opcod, (outs GPR:$Rd),
1336 (ins GPR:$Rn, so_reg_reg:$shift),
1337 DPSoRegRegFrm, IIC_iALUsr, opc, "\t$Rd, $Rn, $shift",
1338 [(set GPR:$Rd, CPSR, (opnode GPR:$Rn, so_reg_reg:$shift, CPSR))]>,
1344 let Inst{19-16} = Rn;
1345 let Inst{15-12} = Rd;
1346 let Inst{11-8} = shift{11-8};
1348 let Inst{6-5} = shift{6-5};
1350 let Inst{3-0} = shift{3-0};
1354 // Assembly aliases for optional destination operand when it's the same
1355 // as the source operand.
1356 def : InstAlias<!strconcat(opc, "${s}${p} $Rdn, $imm"),
1357 (!cast<Instruction>(!strconcat(baseOpc, "ri")) GPR:$Rdn, GPR:$Rdn,
1358 so_imm:$imm, pred:$p,
1361 def : InstAlias<!strconcat(opc, "${s}${p} $Rdn, $Rm"),
1362 (!cast<Instruction>(!strconcat(baseOpc, "rr")) GPR:$Rdn, GPR:$Rdn,
1366 def : InstAlias<!strconcat(opc, "${s}${p} $Rdn, $shift"),
1367 (!cast<Instruction>(!strconcat(baseOpc, "rsi")) GPR:$Rdn, GPR:$Rdn,
1368 so_reg_imm:$shift, pred:$p,
1371 def : InstAlias<!strconcat(opc, "${s}${p} $Rdn, $shift"),
1372 (!cast<Instruction>(!strconcat(baseOpc, "rsr")) GPR:$Rdn, GPR:$Rdn,
1373 so_reg_reg:$shift, pred:$p,
1378 /// AI1_rsc_irs - Define instructions and patterns for rsc
1379 multiclass AI1_rsc_irs<bits<4> opcod, string opc, PatFrag opnode,
1381 let hasPostISelHook = 1, Defs = [CPSR], Uses = [CPSR] in {
1382 def ri : AsI1<opcod, (outs GPR:$Rd), (ins GPR:$Rn, so_imm:$imm),
1383 DPFrm, IIC_iALUi, opc, "\t$Rd, $Rn, $imm",
1384 [(set GPR:$Rd, CPSR, (opnode so_imm:$imm, GPR:$Rn, CPSR))]>,
1390 let Inst{15-12} = Rd;
1391 let Inst{19-16} = Rn;
1392 let Inst{11-0} = imm;
1394 def rr : AsI1<opcod, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm),
1395 DPFrm, IIC_iALUr, opc, "\t$Rd, $Rn, $Rm",
1396 [/* pattern left blank */]> {
1400 let Inst{11-4} = 0b00000000;
1403 let Inst{15-12} = Rd;
1404 let Inst{19-16} = Rn;
1406 def rsi : AsI1<opcod, (outs GPR:$Rd), (ins GPR:$Rn, so_reg_imm:$shift),
1407 DPSoRegImmFrm, IIC_iALUsr, opc, "\t$Rd, $Rn, $shift",
1408 [(set GPR:$Rd, CPSR, (opnode so_reg_imm:$shift, GPR:$Rn, CPSR))]>,
1414 let Inst{19-16} = Rn;
1415 let Inst{15-12} = Rd;
1416 let Inst{11-5} = shift{11-5};
1418 let Inst{3-0} = shift{3-0};
1420 def rsr : AsI1<opcod, (outs GPR:$Rd), (ins GPR:$Rn, so_reg_reg:$shift),
1421 DPSoRegRegFrm, IIC_iALUsr, opc, "\t$Rd, $Rn, $shift",
1422 [(set GPR:$Rd, CPSR, (opnode so_reg_reg:$shift, GPR:$Rn, CPSR))]>,
1428 let Inst{19-16} = Rn;
1429 let Inst{15-12} = Rd;
1430 let Inst{11-8} = shift{11-8};
1432 let Inst{6-5} = shift{6-5};
1434 let Inst{3-0} = shift{3-0};
1438 // Assembly aliases for optional destination operand when it's the same
1439 // as the source operand.
1440 def : InstAlias<!strconcat(opc, "${s}${p} $Rdn, $imm"),
1441 (!cast<Instruction>(!strconcat(baseOpc, "ri")) GPR:$Rdn, GPR:$Rdn,
1442 so_imm:$imm, pred:$p,
1445 def : InstAlias<!strconcat(opc, "${s}${p} $Rdn, $Rm"),
1446 (!cast<Instruction>(!strconcat(baseOpc, "rr")) GPR:$Rdn, GPR:$Rdn,
1450 def : InstAlias<!strconcat(opc, "${s}${p} $Rdn, $shift"),
1451 (!cast<Instruction>(!strconcat(baseOpc, "rsi")) GPR:$Rdn, GPR:$Rdn,
1452 so_reg_imm:$shift, pred:$p,
1455 def : InstAlias<!strconcat(opc, "${s}${p} $Rdn, $shift"),
1456 (!cast<Instruction>(!strconcat(baseOpc, "rsr")) GPR:$Rdn, GPR:$Rdn,
1457 so_reg_reg:$shift, pred:$p,
1462 let canFoldAsLoad = 1, isReMaterializable = 1 in {
1463 multiclass AI_ldr1<bit isByte, string opc, InstrItinClass iii,
1464 InstrItinClass iir, PatFrag opnode> {
1465 // Note: We use the complex addrmode_imm12 rather than just an input
1466 // GPR and a constrained immediate so that we can use this to match
1467 // frame index references and avoid matching constant pool references.
1468 def i12: AI2ldst<0b010, 1, isByte, (outs GPR:$Rt), (ins addrmode_imm12:$addr),
1469 AddrMode_i12, LdFrm, iii, opc, "\t$Rt, $addr",
1470 [(set GPR:$Rt, (opnode addrmode_imm12:$addr))]> {
1473 let Inst{23} = addr{12}; // U (add = ('U' == 1))
1474 let Inst{19-16} = addr{16-13}; // Rn
1475 let Inst{15-12} = Rt;
1476 let Inst{11-0} = addr{11-0}; // imm12
1478 def rs : AI2ldst<0b011, 1, isByte, (outs GPR:$Rt), (ins ldst_so_reg:$shift),
1479 AddrModeNone, LdFrm, iir, opc, "\t$Rt, $shift",
1480 [(set GPR:$Rt, (opnode ldst_so_reg:$shift))]> {
1483 let shift{4} = 0; // Inst{4} = 0
1484 let Inst{23} = shift{12}; // U (add = ('U' == 1))
1485 let Inst{19-16} = shift{16-13}; // Rn
1486 let Inst{15-12} = Rt;
1487 let Inst{11-0} = shift{11-0};
1492 let canFoldAsLoad = 1, isReMaterializable = 1 in {
1493 multiclass AI_ldr1nopc<bit isByte, string opc, InstrItinClass iii,
1494 InstrItinClass iir, PatFrag opnode> {
1495 // Note: We use the complex addrmode_imm12 rather than just an input
1496 // GPR and a constrained immediate so that we can use this to match
1497 // frame index references and avoid matching constant pool references.
1498 def i12: AI2ldst<0b010, 1, isByte, (outs GPRnopc:$Rt), (ins addrmode_imm12:$addr),
1499 AddrMode_i12, LdFrm, iii, opc, "\t$Rt, $addr",
1500 [(set GPRnopc:$Rt, (opnode addrmode_imm12:$addr))]> {
1503 let Inst{23} = addr{12}; // U (add = ('U' == 1))
1504 let Inst{19-16} = addr{16-13}; // Rn
1505 let Inst{15-12} = Rt;
1506 let Inst{11-0} = addr{11-0}; // imm12
1508 def rs : AI2ldst<0b011, 1, isByte, (outs GPRnopc:$Rt), (ins ldst_so_reg:$shift),
1509 AddrModeNone, LdFrm, iir, opc, "\t$Rt, $shift",
1510 [(set GPRnopc:$Rt, (opnode ldst_so_reg:$shift))]> {
1513 let shift{4} = 0; // Inst{4} = 0
1514 let Inst{23} = shift{12}; // U (add = ('U' == 1))
1515 let Inst{19-16} = shift{16-13}; // Rn
1516 let Inst{15-12} = Rt;
1517 let Inst{11-0} = shift{11-0};
1523 multiclass AI_str1<bit isByte, string opc, InstrItinClass iii,
1524 InstrItinClass iir, PatFrag opnode> {
1525 // Note: We use the complex addrmode_imm12 rather than just an input
1526 // GPR and a constrained immediate so that we can use this to match
1527 // frame index references and avoid matching constant pool references.
1528 def i12 : AI2ldst<0b010, 0, isByte, (outs),
1529 (ins GPR:$Rt, addrmode_imm12:$addr),
1530 AddrMode_i12, StFrm, iii, opc, "\t$Rt, $addr",
1531 [(opnode GPR:$Rt, addrmode_imm12:$addr)]> {
1534 let Inst{23} = addr{12}; // U (add = ('U' == 1))
1535 let Inst{19-16} = addr{16-13}; // Rn
1536 let Inst{15-12} = Rt;
1537 let Inst{11-0} = addr{11-0}; // imm12
1539 def rs : AI2ldst<0b011, 0, isByte, (outs), (ins GPR:$Rt, ldst_so_reg:$shift),
1540 AddrModeNone, StFrm, iir, opc, "\t$Rt, $shift",
1541 [(opnode GPR:$Rt, ldst_so_reg:$shift)]> {
1544 let shift{4} = 0; // Inst{4} = 0
1545 let Inst{23} = shift{12}; // U (add = ('U' == 1))
1546 let Inst{19-16} = shift{16-13}; // Rn
1547 let Inst{15-12} = Rt;
1548 let Inst{11-0} = shift{11-0};
1552 multiclass AI_str1nopc<bit isByte, string opc, InstrItinClass iii,
1553 InstrItinClass iir, PatFrag opnode> {
1554 // Note: We use the complex addrmode_imm12 rather than just an input
1555 // GPR and a constrained immediate so that we can use this to match
1556 // frame index references and avoid matching constant pool references.
1557 def i12 : AI2ldst<0b010, 0, isByte, (outs),
1558 (ins GPRnopc:$Rt, addrmode_imm12:$addr),
1559 AddrMode_i12, StFrm, iii, opc, "\t$Rt, $addr",
1560 [(opnode GPRnopc:$Rt, addrmode_imm12:$addr)]> {
1563 let Inst{23} = addr{12}; // U (add = ('U' == 1))
1564 let Inst{19-16} = addr{16-13}; // Rn
1565 let Inst{15-12} = Rt;
1566 let Inst{11-0} = addr{11-0}; // imm12
1568 def rs : AI2ldst<0b011, 0, isByte, (outs), (ins GPRnopc:$Rt, ldst_so_reg:$shift),
1569 AddrModeNone, StFrm, iir, opc, "\t$Rt, $shift",
1570 [(opnode GPRnopc:$Rt, ldst_so_reg:$shift)]> {
1573 let shift{4} = 0; // Inst{4} = 0
1574 let Inst{23} = shift{12}; // U (add = ('U' == 1))
1575 let Inst{19-16} = shift{16-13}; // Rn
1576 let Inst{15-12} = Rt;
1577 let Inst{11-0} = shift{11-0};
1582 //===----------------------------------------------------------------------===//
1584 //===----------------------------------------------------------------------===//
1586 //===----------------------------------------------------------------------===//
1587 // Miscellaneous Instructions.
1590 /// CONSTPOOL_ENTRY - This instruction represents a floating constant pool in
1591 /// the function. The first operand is the ID# for this instruction, the second
1592 /// is the index into the MachineConstantPool that this is, the third is the
1593 /// size in bytes of this constant pool entry.
1594 let neverHasSideEffects = 1, isNotDuplicable = 1 in
1595 def CONSTPOOL_ENTRY :
1596 PseudoInst<(outs), (ins cpinst_operand:$instid, cpinst_operand:$cpidx,
1597 i32imm:$size), NoItinerary, []>;
1599 // FIXME: Marking these as hasSideEffects is necessary to prevent machine DCE
1600 // from removing one half of the matched pairs. That breaks PEI, which assumes
1601 // these will always be in pairs, and asserts if it finds otherwise. Better way?
1602 let Defs = [SP], Uses = [SP], hasSideEffects = 1 in {
1603 def ADJCALLSTACKUP :
1604 PseudoInst<(outs), (ins i32imm:$amt1, i32imm:$amt2, pred:$p), NoItinerary,
1605 [(ARMcallseq_end timm:$amt1, timm:$amt2)]>;
1607 def ADJCALLSTACKDOWN :
1608 PseudoInst<(outs), (ins i32imm:$amt, pred:$p), NoItinerary,
1609 [(ARMcallseq_start timm:$amt)]>;
1612 // Atomic pseudo-insts which will be lowered to ldrexd/strexd loops.
1613 // (These psuedos use a hand-written selection code).
1614 let usesCustomInserter = 1, Defs = [CPSR], mayLoad = 1, mayStore = 1 in {
1615 def ATOMOR6432 : PseudoInst<(outs GPR:$dst1, GPR:$dst2),
1616 (ins GPR:$addr, GPR:$src1, GPR:$src2),
1618 def ATOMXOR6432 : PseudoInst<(outs GPR:$dst1, GPR:$dst2),
1619 (ins GPR:$addr, GPR:$src1, GPR:$src2),
1621 def ATOMADD6432 : PseudoInst<(outs GPR:$dst1, GPR:$dst2),
1622 (ins GPR:$addr, GPR:$src1, GPR:$src2),
1624 def ATOMSUB6432 : PseudoInst<(outs GPR:$dst1, GPR:$dst2),
1625 (ins GPR:$addr, GPR:$src1, GPR:$src2),
1627 def ATOMNAND6432 : PseudoInst<(outs GPR:$dst1, GPR:$dst2),
1628 (ins GPR:$addr, GPR:$src1, GPR:$src2),
1630 def ATOMAND6432 : PseudoInst<(outs GPR:$dst1, GPR:$dst2),
1631 (ins GPR:$addr, GPR:$src1, GPR:$src2),
1633 def ATOMSWAP6432 : PseudoInst<(outs GPR:$dst1, GPR:$dst2),
1634 (ins GPR:$addr, GPR:$src1, GPR:$src2),
1636 def ATOMCMPXCHG6432 : PseudoInst<(outs GPR:$dst1, GPR:$dst2),
1637 (ins GPR:$addr, GPR:$cmp1, GPR:$cmp2,
1638 GPR:$set1, GPR:$set2),
1642 def NOP : AI<(outs), (ins), MiscFrm, NoItinerary, "nop", "", []>,
1643 Requires<[IsARM, HasV6T2]> {
1644 let Inst{27-16} = 0b001100100000;
1645 let Inst{15-8} = 0b11110000;
1646 let Inst{7-0} = 0b00000000;
1649 def YIELD : AI<(outs), (ins), MiscFrm, NoItinerary, "yield", "", []>,
1650 Requires<[IsARM, HasV6T2]> {
1651 let Inst{27-16} = 0b001100100000;
1652 let Inst{15-8} = 0b11110000;
1653 let Inst{7-0} = 0b00000001;
1656 def WFE : AI<(outs), (ins), MiscFrm, NoItinerary, "wfe", "", []>,
1657 Requires<[IsARM, HasV6T2]> {
1658 let Inst{27-16} = 0b001100100000;
1659 let Inst{15-8} = 0b11110000;
1660 let Inst{7-0} = 0b00000010;
1663 def WFI : AI<(outs), (ins), MiscFrm, NoItinerary, "wfi", "", []>,
1664 Requires<[IsARM, HasV6T2]> {
1665 let Inst{27-16} = 0b001100100000;
1666 let Inst{15-8} = 0b11110000;
1667 let Inst{7-0} = 0b00000011;
1670 def SEL : AI<(outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm), DPFrm, NoItinerary, "sel",
1671 "\t$Rd, $Rn, $Rm", []>, Requires<[IsARM, HasV6]> {
1676 let Inst{15-12} = Rd;
1677 let Inst{19-16} = Rn;
1678 let Inst{27-20} = 0b01101000;
1679 let Inst{7-4} = 0b1011;
1680 let Inst{11-8} = 0b1111;
1683 def SEV : AI<(outs), (ins), MiscFrm, NoItinerary, "sev", "",
1684 []>, Requires<[IsARM, HasV6T2]> {
1685 let Inst{27-16} = 0b001100100000;
1686 let Inst{15-8} = 0b11110000;
1687 let Inst{7-0} = 0b00000100;
1690 // The i32imm operand $val can be used by a debugger to store more information
1691 // about the breakpoint.
1692 def BKPT : AI<(outs), (ins imm0_65535:$val), MiscFrm, NoItinerary,
1693 "bkpt", "\t$val", []>, Requires<[IsARM]> {
1695 let Inst{3-0} = val{3-0};
1696 let Inst{19-8} = val{15-4};
1697 let Inst{27-20} = 0b00010010;
1698 let Inst{7-4} = 0b0111;
1701 // Change Processor State
1702 // FIXME: We should use InstAlias to handle the optional operands.
1703 class CPS<dag iops, string asm_ops>
1704 : AXI<(outs), iops, MiscFrm, NoItinerary, !strconcat("cps", asm_ops),
1705 []>, Requires<[IsARM]> {
1711 let Inst{31-28} = 0b1111;
1712 let Inst{27-20} = 0b00010000;
1713 let Inst{19-18} = imod;
1714 let Inst{17} = M; // Enabled if mode is set;
1716 let Inst{8-6} = iflags;
1718 let Inst{4-0} = mode;
1721 let DecoderMethod = "DecodeCPSInstruction" in {
1723 def CPS3p : CPS<(ins imod_op:$imod, iflags_op:$iflags, imm0_31:$mode),
1724 "$imod\t$iflags, $mode">;
1725 let mode = 0, M = 0 in
1726 def CPS2p : CPS<(ins imod_op:$imod, iflags_op:$iflags), "$imod\t$iflags">;
1728 let imod = 0, iflags = 0, M = 1 in
1729 def CPS1p : CPS<(ins imm0_31:$mode), "\t$mode">;
1732 // Preload signals the memory system of possible future data/instruction access.
1733 multiclass APreLoad<bits<1> read, bits<1> data, string opc> {
1735 def i12 : AXI<(outs), (ins addrmode_imm12:$addr), MiscFrm, IIC_Preload,
1736 !strconcat(opc, "\t$addr"),
1737 [(ARMPreload addrmode_imm12:$addr, (i32 read), (i32 data))]> {
1740 let Inst{31-26} = 0b111101;
1741 let Inst{25} = 0; // 0 for immediate form
1742 let Inst{24} = data;
1743 let Inst{23} = addr{12}; // U (add = ('U' == 1))
1744 let Inst{22} = read;
1745 let Inst{21-20} = 0b01;
1746 let Inst{19-16} = addr{16-13}; // Rn
1747 let Inst{15-12} = 0b1111;
1748 let Inst{11-0} = addr{11-0}; // imm12
1751 def rs : AXI<(outs), (ins ldst_so_reg:$shift), MiscFrm, IIC_Preload,
1752 !strconcat(opc, "\t$shift"),
1753 [(ARMPreload ldst_so_reg:$shift, (i32 read), (i32 data))]> {
1755 let Inst{31-26} = 0b111101;
1756 let Inst{25} = 1; // 1 for register form
1757 let Inst{24} = data;
1758 let Inst{23} = shift{12}; // U (add = ('U' == 1))
1759 let Inst{22} = read;
1760 let Inst{21-20} = 0b01;
1761 let Inst{19-16} = shift{16-13}; // Rn
1762 let Inst{15-12} = 0b1111;
1763 let Inst{11-0} = shift{11-0};
1768 defm PLD : APreLoad<1, 1, "pld">, Requires<[IsARM]>;
1769 defm PLDW : APreLoad<0, 1, "pldw">, Requires<[IsARM,HasV7,HasMP]>;
1770 defm PLI : APreLoad<1, 0, "pli">, Requires<[IsARM,HasV7]>;
1772 def SETEND : AXI<(outs), (ins setend_op:$end), MiscFrm, NoItinerary,
1773 "setend\t$end", []>, Requires<[IsARM]> {
1775 let Inst{31-10} = 0b1111000100000001000000;
1780 def DBG : AI<(outs), (ins imm0_15:$opt), MiscFrm, NoItinerary, "dbg", "\t$opt",
1781 []>, Requires<[IsARM, HasV7]> {
1783 let Inst{27-4} = 0b001100100000111100001111;
1784 let Inst{3-0} = opt;
1787 // A5.4 Permanently UNDEFINED instructions.
1788 let isBarrier = 1, isTerminator = 1 in
1789 def TRAP : AXI<(outs), (ins), MiscFrm, NoItinerary,
1792 let Inst = 0xe7ffdefe;
1795 // Address computation and loads and stores in PIC mode.
1796 let isNotDuplicable = 1 in {
1797 def PICADD : ARMPseudoInst<(outs GPR:$dst), (ins GPR:$a, pclabel:$cp, pred:$p),
1799 [(set GPR:$dst, (ARMpic_add GPR:$a, imm:$cp))]>;
1801 let AddedComplexity = 10 in {
1802 def PICLDR : ARMPseudoInst<(outs GPR:$dst), (ins addrmodepc:$addr, pred:$p),
1804 [(set GPR:$dst, (load addrmodepc:$addr))]>;
1806 def PICLDRH : ARMPseudoInst<(outs GPR:$Rt), (ins addrmodepc:$addr, pred:$p),
1808 [(set GPR:$Rt, (zextloadi16 addrmodepc:$addr))]>;
1810 def PICLDRB : ARMPseudoInst<(outs GPR:$Rt), (ins addrmodepc:$addr, pred:$p),
1812 [(set GPR:$Rt, (zextloadi8 addrmodepc:$addr))]>;
1814 def PICLDRSH : ARMPseudoInst<(outs GPR:$Rt), (ins addrmodepc:$addr, pred:$p),
1816 [(set GPR:$Rt, (sextloadi16 addrmodepc:$addr))]>;
1818 def PICLDRSB : ARMPseudoInst<(outs GPR:$Rt), (ins addrmodepc:$addr, pred:$p),
1820 [(set GPR:$Rt, (sextloadi8 addrmodepc:$addr))]>;
1822 let AddedComplexity = 10 in {
1823 def PICSTR : ARMPseudoInst<(outs), (ins GPR:$src, addrmodepc:$addr, pred:$p),
1824 4, IIC_iStore_r, [(store GPR:$src, addrmodepc:$addr)]>;
1826 def PICSTRH : ARMPseudoInst<(outs), (ins GPR:$src, addrmodepc:$addr, pred:$p),
1827 4, IIC_iStore_bh_r, [(truncstorei16 GPR:$src,
1828 addrmodepc:$addr)]>;
1830 def PICSTRB : ARMPseudoInst<(outs), (ins GPR:$src, addrmodepc:$addr, pred:$p),
1831 4, IIC_iStore_bh_r, [(truncstorei8 GPR:$src, addrmodepc:$addr)]>;
1833 } // isNotDuplicable = 1
1836 // LEApcrel - Load a pc-relative address into a register without offending the
1838 let neverHasSideEffects = 1, isReMaterializable = 1 in
1839 // The 'adr' mnemonic encodes differently if the label is before or after
1840 // the instruction. The {24-21} opcode bits are set by the fixup, as we don't
1841 // know until then which form of the instruction will be used.
1842 def ADR : AI1<{0,?,?,0}, (outs GPR:$Rd), (ins adrlabel:$label),
1843 MiscFrm, IIC_iALUi, "adr", "\t$Rd, $label", []> {
1846 let Inst{27-25} = 0b001;
1848 let Inst{23-22} = label{13-12};
1851 let Inst{19-16} = 0b1111;
1852 let Inst{15-12} = Rd;
1853 let Inst{11-0} = label{11-0};
1855 def LEApcrel : ARMPseudoInst<(outs GPR:$Rd), (ins i32imm:$label, pred:$p),
1858 def LEApcrelJT : ARMPseudoInst<(outs GPR:$Rd),
1859 (ins i32imm:$label, nohash_imm:$id, pred:$p),
1862 //===----------------------------------------------------------------------===//
1863 // Control Flow Instructions.
1866 let isReturn = 1, isTerminator = 1, isBarrier = 1 in {
1868 def BX_RET : AI<(outs), (ins), BrMiscFrm, IIC_Br,
1869 "bx", "\tlr", [(ARMretflag)]>,
1870 Requires<[IsARM, HasV4T]> {
1871 let Inst{27-0} = 0b0001001011111111111100011110;
1875 def MOVPCLR : AI<(outs), (ins), BrMiscFrm, IIC_Br,
1876 "mov", "\tpc, lr", [(ARMretflag)]>,
1877 Requires<[IsARM, NoV4T]> {
1878 let Inst{27-0} = 0b0001101000001111000000001110;
1882 // Indirect branches
1883 let isBranch = 1, isTerminator = 1, isBarrier = 1, isIndirectBranch = 1 in {
1885 def BX : AXI<(outs), (ins GPR:$dst), BrMiscFrm, IIC_Br, "bx\t$dst",
1886 [(brind GPR:$dst)]>,
1887 Requires<[IsARM, HasV4T]> {
1889 let Inst{31-4} = 0b1110000100101111111111110001;
1890 let Inst{3-0} = dst;
1893 def BX_pred : AI<(outs), (ins GPR:$dst), BrMiscFrm, IIC_Br,
1894 "bx", "\t$dst", [/* pattern left blank */]>,
1895 Requires<[IsARM, HasV4T]> {
1897 let Inst{27-4} = 0b000100101111111111110001;
1898 let Inst{3-0} = dst;
1902 // All calls clobber the non-callee saved registers. SP is marked as
1903 // a use to prevent stack-pointer assignments that appear immediately
1904 // before calls from potentially appearing dead.
1906 // On non-Darwin platforms R9 is callee-saved.
1907 // FIXME: Do we really need a non-predicated version? If so, it should
1908 // at least be a pseudo instruction expanding to the predicated version
1909 // at MC lowering time.
1910 Defs = [R0, R1, R2, R3, R12, LR, QQQQ0, QQQQ2, QQQQ3, CPSR, FPSCR],
1912 def BL : ABXI<0b1011, (outs), (ins bl_target:$func, variable_ops),
1913 IIC_Br, "bl\t$func",
1914 [(ARMcall tglobaladdr:$func)]>,
1915 Requires<[IsARM, IsNotDarwin]> {
1916 let Inst{31-28} = 0b1110;
1918 let Inst{23-0} = func;
1919 let DecoderMethod = "DecodeBranchImmInstruction";
1922 def BL_pred : ABI<0b1011, (outs), (ins bl_target:$func, variable_ops),
1923 IIC_Br, "bl", "\t$func",
1924 [(ARMcall_pred tglobaladdr:$func)]>,
1925 Requires<[IsARM, IsNotDarwin]> {
1927 let Inst{23-0} = func;
1928 let DecoderMethod = "DecodeBranchImmInstruction";
1932 def BLX : AXI<(outs), (ins GPR:$func, variable_ops), BrMiscFrm,
1933 IIC_Br, "blx\t$func",
1934 [(ARMcall GPR:$func)]>,
1935 Requires<[IsARM, HasV5T, IsNotDarwin]> {
1937 let Inst{31-4} = 0b1110000100101111111111110011;
1938 let Inst{3-0} = func;
1941 def BLX_pred : AI<(outs), (ins GPR:$func, variable_ops), BrMiscFrm,
1942 IIC_Br, "blx", "\t$func",
1943 [(ARMcall_pred GPR:$func)]>,
1944 Requires<[IsARM, HasV5T, IsNotDarwin]> {
1946 let Inst{27-4} = 0b000100101111111111110011;
1947 let Inst{3-0} = func;
1951 // Note: Restrict $func to the tGPR regclass to prevent it being in LR.
1952 def BX_CALL : ARMPseudoInst<(outs), (ins tGPR:$func, variable_ops),
1953 8, IIC_Br, [(ARMcall_nolink tGPR:$func)]>,
1954 Requires<[IsARM, HasV4T, IsNotDarwin]>;
1957 def BMOVPCRX_CALL : ARMPseudoInst<(outs), (ins tGPR:$func, variable_ops),
1958 8, IIC_Br, [(ARMcall_nolink tGPR:$func)]>,
1959 Requires<[IsARM, NoV4T, IsNotDarwin]>;
1963 // On Darwin R9 is call-clobbered.
1964 // R7 is marked as a use to prevent frame-pointer assignments from being
1965 // moved above / below calls.
1966 Defs = [R0, R1, R2, R3, R9, R12, LR, QQQQ0, QQQQ2, QQQQ3, CPSR, FPSCR],
1967 Uses = [R7, SP] in {
1968 def BLr9 : ARMPseudoExpand<(outs), (ins bl_target:$func, variable_ops),
1970 [(ARMcall tglobaladdr:$func)], (BL bl_target:$func)>,
1971 Requires<[IsARM, IsDarwin]>;
1973 def BLr9_pred : ARMPseudoExpand<(outs),
1974 (ins bl_target:$func, pred:$p, variable_ops),
1976 [(ARMcall_pred tglobaladdr:$func)],
1977 (BL_pred bl_target:$func, pred:$p)>,
1978 Requires<[IsARM, IsDarwin]>;
1981 def BLXr9 : ARMPseudoExpand<(outs), (ins GPR:$func, variable_ops),
1983 [(ARMcall GPR:$func)],
1985 Requires<[IsARM, HasV5T, IsDarwin]>;
1987 def BLXr9_pred: ARMPseudoExpand<(outs), (ins GPR:$func, pred:$p,variable_ops),
1989 [(ARMcall_pred GPR:$func)],
1990 (BLX_pred GPR:$func, pred:$p)>,
1991 Requires<[IsARM, HasV5T, IsDarwin]>;
1994 // Note: Restrict $func to the tGPR regclass to prevent it being in LR.
1995 def BXr9_CALL : ARMPseudoInst<(outs), (ins tGPR:$func, variable_ops),
1996 8, IIC_Br, [(ARMcall_nolink tGPR:$func)]>,
1997 Requires<[IsARM, HasV4T, IsDarwin]>;
2000 def BMOVPCRXr9_CALL : ARMPseudoInst<(outs), (ins tGPR:$func, variable_ops),
2001 8, IIC_Br, [(ARMcall_nolink tGPR:$func)]>,
2002 Requires<[IsARM, NoV4T, IsDarwin]>;
2005 let isBranch = 1, isTerminator = 1 in {
2006 // FIXME: should be able to write a pattern for ARMBrcond, but can't use
2007 // a two-value operand where a dag node expects two operands. :(
2008 def Bcc : ABI<0b1010, (outs), (ins br_target:$target),
2009 IIC_Br, "b", "\t$target",
2010 [/*(ARMbrcond bb:$target, imm:$cc, CCR:$ccr)*/]> {
2012 let Inst{23-0} = target;
2013 let DecoderMethod = "DecodeBranchImmInstruction";
2016 let isBarrier = 1 in {
2017 // B is "predicable" since it's just a Bcc with an 'always' condition.
2018 let isPredicable = 1 in
2019 // FIXME: We shouldn't need this pseudo at all. Just using Bcc directly
2020 // should be sufficient.
2021 // FIXME: Is B really a Barrier? That doesn't seem right.
2022 def B : ARMPseudoExpand<(outs), (ins br_target:$target), 4, IIC_Br,
2023 [(br bb:$target)], (Bcc br_target:$target, (ops 14, zero_reg))>;
2025 let isNotDuplicable = 1, isIndirectBranch = 1 in {
2026 def BR_JTr : ARMPseudoInst<(outs),
2027 (ins GPR:$target, i32imm:$jt, i32imm:$id),
2029 [(ARMbrjt GPR:$target, tjumptable:$jt, imm:$id)]>;
2030 // FIXME: This shouldn't use the generic "addrmode2," but rather be split
2031 // into i12 and rs suffixed versions.
2032 def BR_JTm : ARMPseudoInst<(outs),
2033 (ins addrmode2:$target, i32imm:$jt, i32imm:$id),
2035 [(ARMbrjt (i32 (load addrmode2:$target)), tjumptable:$jt,
2037 def BR_JTadd : ARMPseudoInst<(outs),
2038 (ins GPR:$target, GPR:$idx, i32imm:$jt, i32imm:$id),
2040 [(ARMbrjt (add GPR:$target, GPR:$idx), tjumptable:$jt,
2042 } // isNotDuplicable = 1, isIndirectBranch = 1
2048 def BLXi : AXI<(outs), (ins blx_target:$target), BrMiscFrm, NoItinerary,
2049 "blx\t$target", []>,
2050 Requires<[IsARM, HasV5T]> {
2051 let Inst{31-25} = 0b1111101;
2053 let Inst{23-0} = target{24-1};
2054 let Inst{24} = target{0};
2057 // Branch and Exchange Jazelle
2058 def BXJ : ABI<0b0001, (outs), (ins GPR:$func), NoItinerary, "bxj", "\t$func",
2059 [/* pattern left blank */]> {
2061 let Inst{23-20} = 0b0010;
2062 let Inst{19-8} = 0xfff;
2063 let Inst{7-4} = 0b0010;
2064 let Inst{3-0} = func;
2069 let isCall = 1, isTerminator = 1, isReturn = 1, isBarrier = 1 in {
2071 let Defs = [R0, R1, R2, R3, R9, R12, QQQQ0, QQQQ2, QQQQ3, PC],
2073 def TCRETURNdi : PseudoInst<(outs), (ins i32imm:$dst, variable_ops),
2074 IIC_Br, []>, Requires<[IsDarwin]>;
2076 def TCRETURNri : PseudoInst<(outs), (ins tcGPR:$dst, variable_ops),
2077 IIC_Br, []>, Requires<[IsDarwin]>;
2079 def TAILJMPd : ARMPseudoExpand<(outs), (ins br_target:$dst, variable_ops),
2081 (Bcc br_target:$dst, (ops 14, zero_reg))>,
2082 Requires<[IsARM, IsDarwin]>;
2084 def TAILJMPr : ARMPseudoExpand<(outs), (ins tcGPR:$dst, variable_ops),
2087 Requires<[IsARM, IsDarwin]>;
2091 // Non-Darwin versions (the difference is R9).
2092 let Defs = [R0, R1, R2, R3, R12, QQQQ0, QQQQ2, QQQQ3, PC],
2094 def TCRETURNdiND : PseudoInst<(outs), (ins i32imm:$dst, variable_ops),
2095 IIC_Br, []>, Requires<[IsNotDarwin]>;
2097 def TCRETURNriND : PseudoInst<(outs), (ins tcGPR:$dst, variable_ops),
2098 IIC_Br, []>, Requires<[IsNotDarwin]>;
2100 def TAILJMPdND : ARMPseudoExpand<(outs), (ins brtarget:$dst, variable_ops),
2102 (Bcc br_target:$dst, (ops 14, zero_reg))>,
2103 Requires<[IsARM, IsNotDarwin]>;
2105 def TAILJMPrND : ARMPseudoExpand<(outs), (ins tcGPR:$dst, variable_ops),
2108 Requires<[IsARM, IsNotDarwin]>;
2112 // Secure Monitor Call is a system instruction.
2113 def SMC : ABI<0b0001, (outs), (ins imm0_15:$opt), NoItinerary, "smc", "\t$opt",
2116 let Inst{23-4} = 0b01100000000000000111;
2117 let Inst{3-0} = opt;
2120 // Supervisor Call (Software Interrupt)
2121 let isCall = 1, Uses = [SP] in {
2122 def SVC : ABI<0b1111, (outs), (ins imm24b:$svc), IIC_Br, "svc", "\t$svc", []> {
2124 let Inst{23-0} = svc;
2128 // Store Return State
2129 class SRSI<bit wb, string asm>
2130 : XI<(outs), (ins imm0_31:$mode), AddrModeNone, 4, IndexModeNone, BrFrm,
2131 NoItinerary, asm, "", []> {
2133 let Inst{31-28} = 0b1111;
2134 let Inst{27-25} = 0b100;
2138 let Inst{19-16} = 0b1101; // SP
2139 let Inst{15-5} = 0b00000101000;
2140 let Inst{4-0} = mode;
2143 def SRSDA : SRSI<0, "srsda\tsp, $mode"> {
2144 let Inst{24-23} = 0;
2146 def SRSDA_UPD : SRSI<1, "srsda\tsp!, $mode"> {
2147 let Inst{24-23} = 0;
2149 def SRSDB : SRSI<0, "srsdb\tsp, $mode"> {
2150 let Inst{24-23} = 0b10;
2152 def SRSDB_UPD : SRSI<1, "srsdb\tsp!, $mode"> {
2153 let Inst{24-23} = 0b10;
2155 def SRSIA : SRSI<0, "srsia\tsp, $mode"> {
2156 let Inst{24-23} = 0b01;
2158 def SRSIA_UPD : SRSI<1, "srsia\tsp!, $mode"> {
2159 let Inst{24-23} = 0b01;
2161 def SRSIB : SRSI<0, "srsib\tsp, $mode"> {
2162 let Inst{24-23} = 0b11;
2164 def SRSIB_UPD : SRSI<1, "srsib\tsp!, $mode"> {
2165 let Inst{24-23} = 0b11;
2168 // Return From Exception
2169 class RFEI<bit wb, string asm>
2170 : XI<(outs), (ins GPR:$Rn), AddrModeNone, 4, IndexModeNone, BrFrm,
2171 NoItinerary, asm, "", []> {
2173 let Inst{31-28} = 0b1111;
2174 let Inst{27-25} = 0b100;
2178 let Inst{19-16} = Rn;
2179 let Inst{15-0} = 0xa00;
2182 def RFEDA : RFEI<0, "rfeda\t$Rn"> {
2183 let Inst{24-23} = 0;
2185 def RFEDA_UPD : RFEI<1, "rfeda\t$Rn!"> {
2186 let Inst{24-23} = 0;
2188 def RFEDB : RFEI<0, "rfedb\t$Rn"> {
2189 let Inst{24-23} = 0b10;
2191 def RFEDB_UPD : RFEI<1, "rfedb\t$Rn!"> {
2192 let Inst{24-23} = 0b10;
2194 def RFEIA : RFEI<0, "rfeia\t$Rn"> {
2195 let Inst{24-23} = 0b01;
2197 def RFEIA_UPD : RFEI<1, "rfeia\t$Rn!"> {
2198 let Inst{24-23} = 0b01;
2200 def RFEIB : RFEI<0, "rfeib\t$Rn"> {
2201 let Inst{24-23} = 0b11;
2203 def RFEIB_UPD : RFEI<1, "rfeib\t$Rn!"> {
2204 let Inst{24-23} = 0b11;
2207 //===----------------------------------------------------------------------===//
2208 // Load / store Instructions.
2214 defm LDR : AI_ldr1<0, "ldr", IIC_iLoad_r, IIC_iLoad_si,
2215 UnOpFrag<(load node:$Src)>>;
2216 defm LDRB : AI_ldr1nopc<1, "ldrb", IIC_iLoad_bh_r, IIC_iLoad_bh_si,
2217 UnOpFrag<(zextloadi8 node:$Src)>>;
2218 defm STR : AI_str1<0, "str", IIC_iStore_r, IIC_iStore_si,
2219 BinOpFrag<(store node:$LHS, node:$RHS)>>;
2220 defm STRB : AI_str1nopc<1, "strb", IIC_iStore_bh_r, IIC_iStore_bh_si,
2221 BinOpFrag<(truncstorei8 node:$LHS, node:$RHS)>>;
2223 // Special LDR for loads from non-pc-relative constpools.
2224 let canFoldAsLoad = 1, mayLoad = 1, neverHasSideEffects = 1,
2225 isReMaterializable = 1, isCodeGenOnly = 1 in
2226 def LDRcp : AI2ldst<0b010, 1, 0, (outs GPR:$Rt), (ins addrmode_imm12:$addr),
2227 AddrMode_i12, LdFrm, IIC_iLoad_r, "ldr", "\t$Rt, $addr",
2231 let Inst{23} = addr{12}; // U (add = ('U' == 1))
2232 let Inst{19-16} = 0b1111;
2233 let Inst{15-12} = Rt;
2234 let Inst{11-0} = addr{11-0}; // imm12
2237 // Loads with zero extension
2238 def LDRH : AI3ld<0b1011, 1, (outs GPR:$Rt), (ins addrmode3:$addr), LdMiscFrm,
2239 IIC_iLoad_bh_r, "ldrh", "\t$Rt, $addr",
2240 [(set GPR:$Rt, (zextloadi16 addrmode3:$addr))]>;
2242 // Loads with sign extension
2243 def LDRSH : AI3ld<0b1111, 1, (outs GPR:$Rt), (ins addrmode3:$addr), LdMiscFrm,
2244 IIC_iLoad_bh_r, "ldrsh", "\t$Rt, $addr",
2245 [(set GPR:$Rt, (sextloadi16 addrmode3:$addr))]>;
2247 def LDRSB : AI3ld<0b1101, 1, (outs GPR:$Rt), (ins addrmode3:$addr), LdMiscFrm,
2248 IIC_iLoad_bh_r, "ldrsb", "\t$Rt, $addr",
2249 [(set GPR:$Rt, (sextloadi8 addrmode3:$addr))]>;
2251 let mayLoad = 1, neverHasSideEffects = 1, hasExtraDefRegAllocReq = 1 in {
2253 def LDRD : AI3ld<0b1101, 0, (outs GPR:$Rd, GPR:$dst2),
2254 (ins addrmode3:$addr), LdMiscFrm,
2255 IIC_iLoad_d_r, "ldrd", "\t$Rd, $dst2, $addr",
2256 []>, Requires<[IsARM, HasV5TE]>;
2260 multiclass AI2_ldridx<bit isByte, string opc, InstrItinClass itin> {
2261 def _PRE_IMM : AI2ldstidx<1, isByte, 1, (outs GPR:$Rt, GPR:$Rn_wb),
2262 (ins addrmode_imm12:$addr), IndexModePre, LdFrm, itin,
2263 opc, "\t$Rt, $addr!", "$addr.base = $Rn_wb", []> {
2266 let Inst{23} = addr{12};
2267 let Inst{19-16} = addr{16-13};
2268 let Inst{11-0} = addr{11-0};
2269 let DecoderMethod = "DecodeLDRPreImm";
2270 let AsmMatchConverter = "cvtLdWriteBackRegAddrModeImm12";
2273 def _PRE_REG : AI2ldstidx<1, isByte, 1, (outs GPR:$Rt, GPR:$Rn_wb),
2274 (ins ldst_so_reg:$addr), IndexModePre, LdFrm, itin,
2275 opc, "\t$Rt, $addr!", "$addr.base = $Rn_wb", []> {
2278 let Inst{23} = addr{12};
2279 let Inst{19-16} = addr{16-13};
2280 let Inst{11-0} = addr{11-0};
2282 let DecoderMethod = "DecodeLDRPreReg";
2283 let AsmMatchConverter = "cvtLdWriteBackRegAddrMode2";
2286 def _POST_REG : AI2ldstidx<1, isByte, 0, (outs GPR:$Rt, GPR:$Rn_wb),
2287 (ins addr_offset_none:$addr, am2offset_reg:$offset),
2288 IndexModePost, LdFrm, itin,
2289 opc, "\t$Rt, $addr, $offset",
2290 "$addr.base = $Rn_wb", []> {
2296 let Inst{23} = offset{12};
2297 let Inst{19-16} = addr;
2298 let Inst{11-0} = offset{11-0};
2300 let DecoderMethod = "DecodeAddrMode2IdxInstruction";
2303 def _POST_IMM : AI2ldstidx<1, isByte, 0, (outs GPR:$Rt, GPR:$Rn_wb),
2304 (ins addr_offset_none:$addr, am2offset_imm:$offset),
2305 IndexModePost, LdFrm, itin,
2306 opc, "\t$Rt, $addr, $offset",
2307 "$addr.base = $Rn_wb", []> {
2313 let Inst{23} = offset{12};
2314 let Inst{19-16} = addr;
2315 let Inst{11-0} = offset{11-0};
2317 let DecoderMethod = "DecodeAddrMode2IdxInstruction";
2322 let mayLoad = 1, neverHasSideEffects = 1 in {
2323 defm LDR : AI2_ldridx<0, "ldr", IIC_iLoad_ru>;
2324 defm LDRB : AI2_ldridx<1, "ldrb", IIC_iLoad_bh_ru>;
2327 multiclass AI3_ldridx<bits<4> op, string opc, InstrItinClass itin> {
2328 def _PRE : AI3ldstidx<op, 1, 1, (outs GPR:$Rt, GPR:$Rn_wb),
2329 (ins addrmode3:$addr), IndexModePre,
2331 opc, "\t$Rt, $addr!", "$addr.base = $Rn_wb", []> {
2333 let Inst{23} = addr{8}; // U bit
2334 let Inst{22} = addr{13}; // 1 == imm8, 0 == Rm
2335 let Inst{19-16} = addr{12-9}; // Rn
2336 let Inst{11-8} = addr{7-4}; // imm7_4/zero
2337 let Inst{3-0} = addr{3-0}; // imm3_0/Rm
2338 let AsmMatchConverter = "cvtLdWriteBackRegAddrMode3";
2339 let DecoderMethod = "DecodeAddrMode3Instruction";
2341 def _POST : AI3ldstidx<op, 1, 0, (outs GPR:$Rt, GPR:$Rn_wb),
2342 (ins addr_offset_none:$addr, am3offset:$offset),
2343 IndexModePost, LdMiscFrm, itin,
2344 opc, "\t$Rt, $addr, $offset", "$addr.base = $Rn_wb",
2348 let Inst{23} = offset{8}; // U bit
2349 let Inst{22} = offset{9}; // 1 == imm8, 0 == Rm
2350 let Inst{19-16} = addr;
2351 let Inst{11-8} = offset{7-4}; // imm7_4/zero
2352 let Inst{3-0} = offset{3-0}; // imm3_0/Rm
2353 let DecoderMethod = "DecodeAddrMode3Instruction";
2357 let mayLoad = 1, neverHasSideEffects = 1 in {
2358 defm LDRH : AI3_ldridx<0b1011, "ldrh", IIC_iLoad_bh_ru>;
2359 defm LDRSH : AI3_ldridx<0b1111, "ldrsh", IIC_iLoad_bh_ru>;
2360 defm LDRSB : AI3_ldridx<0b1101, "ldrsb", IIC_iLoad_bh_ru>;
2361 let hasExtraDefRegAllocReq = 1 in {
2362 def LDRD_PRE : AI3ldstidx<0b1101, 0, 1, (outs GPR:$Rt, GPR:$Rt2, GPR:$Rn_wb),
2363 (ins addrmode3:$addr), IndexModePre,
2364 LdMiscFrm, IIC_iLoad_d_ru,
2365 "ldrd", "\t$Rt, $Rt2, $addr!",
2366 "$addr.base = $Rn_wb", []> {
2368 let Inst{23} = addr{8}; // U bit
2369 let Inst{22} = addr{13}; // 1 == imm8, 0 == Rm
2370 let Inst{19-16} = addr{12-9}; // Rn
2371 let Inst{11-8} = addr{7-4}; // imm7_4/zero
2372 let Inst{3-0} = addr{3-0}; // imm3_0/Rm
2373 let DecoderMethod = "DecodeAddrMode3Instruction";
2374 let AsmMatchConverter = "cvtLdrdPre";
2376 def LDRD_POST: AI3ldstidx<0b1101, 0, 0, (outs GPR:$Rt, GPR:$Rt2, GPR:$Rn_wb),
2377 (ins addr_offset_none:$addr, am3offset:$offset),
2378 IndexModePost, LdMiscFrm, IIC_iLoad_d_ru,
2379 "ldrd", "\t$Rt, $Rt2, $addr, $offset",
2380 "$addr.base = $Rn_wb", []> {
2383 let Inst{23} = offset{8}; // U bit
2384 let Inst{22} = offset{9}; // 1 == imm8, 0 == Rm
2385 let Inst{19-16} = addr;
2386 let Inst{11-8} = offset{7-4}; // imm7_4/zero
2387 let Inst{3-0} = offset{3-0}; // imm3_0/Rm
2388 let DecoderMethod = "DecodeAddrMode3Instruction";
2390 } // hasExtraDefRegAllocReq = 1
2391 } // mayLoad = 1, neverHasSideEffects = 1
2393 // LDRT, LDRBT, LDRSBT, LDRHT, LDRSHT.
2394 let mayLoad = 1, neverHasSideEffects = 1 in {
2395 def LDRT_POST_REG : AI2ldstidx<1, 0, 0, (outs GPR:$Rt, GPR:$Rn_wb),
2396 (ins addr_offset_none:$addr, am2offset_reg:$offset),
2397 IndexModePost, LdFrm, IIC_iLoad_ru,
2398 "ldrt", "\t$Rt, $addr, $offset",
2399 "$addr.base = $Rn_wb", []> {
2405 let Inst{23} = offset{12};
2406 let Inst{21} = 1; // overwrite
2407 let Inst{19-16} = addr;
2408 let Inst{11-5} = offset{11-5};
2410 let Inst{3-0} = offset{3-0};
2411 let DecoderMethod = "DecodeAddrMode2IdxInstruction";
2414 def LDRT_POST_IMM : AI2ldstidx<1, 0, 0, (outs GPR:$Rt, GPR:$Rn_wb),
2415 (ins addr_offset_none:$addr, am2offset_imm:$offset),
2416 IndexModePost, LdFrm, IIC_iLoad_ru,
2417 "ldrt", "\t$Rt, $addr, $offset",
2418 "$addr.base = $Rn_wb", []> {
2424 let Inst{23} = offset{12};
2425 let Inst{21} = 1; // overwrite
2426 let Inst{19-16} = addr;
2427 let Inst{11-0} = offset{11-0};
2428 let DecoderMethod = "DecodeAddrMode2IdxInstruction";
2431 def LDRBT_POST_REG : AI2ldstidx<1, 1, 0, (outs GPR:$Rt, GPR:$Rn_wb),
2432 (ins addr_offset_none:$addr, am2offset_reg:$offset),
2433 IndexModePost, LdFrm, IIC_iLoad_bh_ru,
2434 "ldrbt", "\t$Rt, $addr, $offset",
2435 "$addr.base = $Rn_wb", []> {
2441 let Inst{23} = offset{12};
2442 let Inst{21} = 1; // overwrite
2443 let Inst{19-16} = addr;
2444 let Inst{11-5} = offset{11-5};
2446 let Inst{3-0} = offset{3-0};
2447 let DecoderMethod = "DecodeAddrMode2IdxInstruction";
2450 def LDRBT_POST_IMM : AI2ldstidx<1, 1, 0, (outs GPR:$Rt, GPR:$Rn_wb),
2451 (ins addr_offset_none:$addr, am2offset_imm:$offset),
2452 IndexModePost, LdFrm, IIC_iLoad_bh_ru,
2453 "ldrbt", "\t$Rt, $addr, $offset",
2454 "$addr.base = $Rn_wb", []> {
2460 let Inst{23} = offset{12};
2461 let Inst{21} = 1; // overwrite
2462 let Inst{19-16} = addr;
2463 let Inst{11-0} = offset{11-0};
2464 let DecoderMethod = "DecodeAddrMode2IdxInstruction";
2467 multiclass AI3ldrT<bits<4> op, string opc> {
2468 def i : AI3ldstidxT<op, 1, (outs GPR:$Rt, GPR:$base_wb),
2469 (ins addr_offset_none:$addr, postidx_imm8:$offset),
2470 IndexModePost, LdMiscFrm, IIC_iLoad_bh_ru, opc,
2471 "\t$Rt, $addr, $offset", "$addr.base = $base_wb", []> {
2473 let Inst{23} = offset{8};
2475 let Inst{11-8} = offset{7-4};
2476 let Inst{3-0} = offset{3-0};
2477 let AsmMatchConverter = "cvtLdExtTWriteBackImm";
2479 def r : AI3ldstidxT<op, 1, (outs GPR:$Rt, GPR:$base_wb),
2480 (ins addr_offset_none:$addr, postidx_reg:$Rm),
2481 IndexModePost, LdMiscFrm, IIC_iLoad_bh_ru, opc,
2482 "\t$Rt, $addr, $Rm", "$addr.base = $base_wb", []> {
2484 let Inst{23} = Rm{4};
2487 let Inst{3-0} = Rm{3-0};
2488 let AsmMatchConverter = "cvtLdExtTWriteBackReg";
2492 defm LDRSBT : AI3ldrT<0b1101, "ldrsbt">;
2493 defm LDRHT : AI3ldrT<0b1011, "ldrht">;
2494 defm LDRSHT : AI3ldrT<0b1111, "ldrsht">;
2499 // Stores with truncate
2500 def STRH : AI3str<0b1011, (outs), (ins GPR:$Rt, addrmode3:$addr), StMiscFrm,
2501 IIC_iStore_bh_r, "strh", "\t$Rt, $addr",
2502 [(truncstorei16 GPR:$Rt, addrmode3:$addr)]>;
2505 let mayStore = 1, neverHasSideEffects = 1, hasExtraSrcRegAllocReq = 1 in
2506 def STRD : AI3str<0b1111, (outs), (ins GPR:$Rt, GPR:$src2, addrmode3:$addr),
2507 StMiscFrm, IIC_iStore_d_r,
2508 "strd", "\t$Rt, $src2, $addr", []>,
2509 Requires<[IsARM, HasV5TE]> {
2514 multiclass AI2_stridx<bit isByte, string opc, InstrItinClass itin> {
2515 def _PRE_IMM : AI2ldstidx<0, isByte, 1, (outs GPR:$Rn_wb),
2516 (ins GPR:$Rt, addrmode_imm12:$addr), IndexModePre,
2518 opc, "\t$Rt, $addr!", "$addr.base = $Rn_wb", []> {
2521 let Inst{23} = addr{12}; // U (add = ('U' == 1))
2522 let Inst{19-16} = addr{16-13}; // Rn
2523 let Inst{11-0} = addr{11-0}; // imm12
2524 let AsmMatchConverter = "cvtStWriteBackRegAddrModeImm12";
2525 let DecoderMethod = "DecodeSTRPreImm";
2528 def _PRE_REG : AI2ldstidx<0, isByte, 1, (outs GPR:$Rn_wb),
2529 (ins GPR:$Rt, ldst_so_reg:$addr),
2530 IndexModePre, StFrm, itin,
2531 opc, "\t$Rt, $addr!", "$addr.base = $Rn_wb", []> {
2534 let Inst{23} = addr{12}; // U (add = ('U' == 1))
2535 let Inst{19-16} = addr{16-13}; // Rn
2536 let Inst{11-0} = addr{11-0};
2537 let Inst{4} = 0; // Inst{4} = 0
2538 let AsmMatchConverter = "cvtStWriteBackRegAddrMode2";
2539 let DecoderMethod = "DecodeSTRPreReg";
2541 def _POST_REG : AI2ldstidx<0, isByte, 0, (outs GPR:$Rn_wb),
2542 (ins GPR:$Rt, addr_offset_none:$addr, am2offset_reg:$offset),
2543 IndexModePost, StFrm, itin,
2544 opc, "\t$Rt, $addr, $offset",
2545 "$addr.base = $Rn_wb", []> {
2551 let Inst{23} = offset{12};
2552 let Inst{19-16} = addr;
2553 let Inst{11-0} = offset{11-0};
2555 let DecoderMethod = "DecodeAddrMode2IdxInstruction";
2558 def _POST_IMM : AI2ldstidx<0, isByte, 0, (outs GPR:$Rn_wb),
2559 (ins GPR:$Rt, addr_offset_none:$addr, am2offset_imm:$offset),
2560 IndexModePost, StFrm, itin,
2561 opc, "\t$Rt, $addr, $offset",
2562 "$addr.base = $Rn_wb", []> {
2568 let Inst{23} = offset{12};
2569 let Inst{19-16} = addr;
2570 let Inst{11-0} = offset{11-0};
2572 let DecoderMethod = "DecodeAddrMode2IdxInstruction";
2576 let mayStore = 1, neverHasSideEffects = 1 in {
2577 defm STR : AI2_stridx<0, "str", IIC_iStore_ru>;
2578 defm STRB : AI2_stridx<1, "strb", IIC_iStore_bh_ru>;
2581 def : ARMPat<(post_store GPR:$Rt, addr_offset_none:$addr,
2582 am2offset_reg:$offset),
2583 (STR_POST_REG GPR:$Rt, addr_offset_none:$addr,
2584 am2offset_reg:$offset)>;
2585 def : ARMPat<(post_store GPR:$Rt, addr_offset_none:$addr,
2586 am2offset_imm:$offset),
2587 (STR_POST_IMM GPR:$Rt, addr_offset_none:$addr,
2588 am2offset_imm:$offset)>;
2589 def : ARMPat<(post_truncsti8 GPR:$Rt, addr_offset_none:$addr,
2590 am2offset_reg:$offset),
2591 (STRB_POST_REG GPR:$Rt, addr_offset_none:$addr,
2592 am2offset_reg:$offset)>;
2593 def : ARMPat<(post_truncsti8 GPR:$Rt, addr_offset_none:$addr,
2594 am2offset_imm:$offset),
2595 (STRB_POST_IMM GPR:$Rt, addr_offset_none:$addr,
2596 am2offset_imm:$offset)>;
2598 // Pseudo-instructions for pattern matching the pre-indexed stores. We can't
2599 // put the patterns on the instruction definitions directly as ISel wants
2600 // the address base and offset to be separate operands, not a single
2601 // complex operand like we represent the instructions themselves. The
2602 // pseudos map between the two.
2603 let usesCustomInserter = 1,
2604 Constraints = "$Rn = $Rn_wb,@earlyclobber $Rn_wb" in {
2605 def STRi_preidx: ARMPseudoInst<(outs GPR:$Rn_wb),
2606 (ins GPR:$Rt, GPR:$Rn, am2offset_imm:$offset, pred:$p),
2609 (pre_store GPR:$Rt, GPR:$Rn, am2offset_imm:$offset))]>;
2610 def STRr_preidx: ARMPseudoInst<(outs GPR:$Rn_wb),
2611 (ins GPR:$Rt, GPR:$Rn, am2offset_reg:$offset, pred:$p),
2614 (pre_store GPR:$Rt, GPR:$Rn, am2offset_reg:$offset))]>;
2615 def STRBi_preidx: ARMPseudoInst<(outs GPR:$Rn_wb),
2616 (ins GPR:$Rt, GPR:$Rn, am2offset_imm:$offset, pred:$p),
2619 (pre_truncsti8 GPR:$Rt, GPR:$Rn, am2offset_imm:$offset))]>;
2620 def STRBr_preidx: ARMPseudoInst<(outs GPR:$Rn_wb),
2621 (ins GPR:$Rt, GPR:$Rn, am2offset_reg:$offset, pred:$p),
2624 (pre_truncsti8 GPR:$Rt, GPR:$Rn, am2offset_reg:$offset))]>;
2625 def STRH_preidx: ARMPseudoInst<(outs GPR:$Rn_wb),
2626 (ins GPR:$Rt, GPR:$Rn, am3offset:$offset, pred:$p),
2629 (pre_truncsti16 GPR:$Rt, GPR:$Rn, am3offset:$offset))]>;
2634 def STRH_PRE : AI3ldstidx<0b1011, 0, 1, (outs GPR:$Rn_wb),
2635 (ins GPR:$Rt, addrmode3:$addr), IndexModePre,
2636 StMiscFrm, IIC_iStore_bh_ru,
2637 "strh", "\t$Rt, $addr!", "$addr.base = $Rn_wb", []> {
2639 let Inst{23} = addr{8}; // U bit
2640 let Inst{22} = addr{13}; // 1 == imm8, 0 == Rm
2641 let Inst{19-16} = addr{12-9}; // Rn
2642 let Inst{11-8} = addr{7-4}; // imm7_4/zero
2643 let Inst{3-0} = addr{3-0}; // imm3_0/Rm
2644 let AsmMatchConverter = "cvtStWriteBackRegAddrMode3";
2645 let DecoderMethod = "DecodeAddrMode3Instruction";
2648 def STRH_POST : AI3ldstidx<0b1011, 0, 0, (outs GPR:$Rn_wb),
2649 (ins GPR:$Rt, addr_offset_none:$addr, am3offset:$offset),
2650 IndexModePost, StMiscFrm, IIC_iStore_bh_ru,
2651 "strh", "\t$Rt, $addr, $offset", "$addr.base = $Rn_wb",
2652 [(set GPR:$Rn_wb, (post_truncsti16 GPR:$Rt,
2653 addr_offset_none:$addr,
2654 am3offset:$offset))]> {
2657 let Inst{23} = offset{8}; // U bit
2658 let Inst{22} = offset{9}; // 1 == imm8, 0 == Rm
2659 let Inst{19-16} = addr;
2660 let Inst{11-8} = offset{7-4}; // imm7_4/zero
2661 let Inst{3-0} = offset{3-0}; // imm3_0/Rm
2662 let DecoderMethod = "DecodeAddrMode3Instruction";
2665 let mayStore = 1, neverHasSideEffects = 1, hasExtraSrcRegAllocReq = 1 in {
2666 def STRD_PRE : AI3ldstidx<0b1111, 0, 1, (outs GPR:$Rn_wb),
2667 (ins GPR:$Rt, GPR:$Rt2, addrmode3:$addr),
2668 IndexModePre, StMiscFrm, IIC_iStore_d_ru,
2669 "strd", "\t$Rt, $Rt2, $addr!",
2670 "$addr.base = $Rn_wb", []> {
2672 let Inst{23} = addr{8}; // U bit
2673 let Inst{22} = addr{13}; // 1 == imm8, 0 == Rm
2674 let Inst{19-16} = addr{12-9}; // Rn
2675 let Inst{11-8} = addr{7-4}; // imm7_4/zero
2676 let Inst{3-0} = addr{3-0}; // imm3_0/Rm
2677 let DecoderMethod = "DecodeAddrMode3Instruction";
2678 let AsmMatchConverter = "cvtStrdPre";
2681 def STRD_POST: AI3ldstidx<0b1111, 0, 0, (outs GPR:$Rn_wb),
2682 (ins GPR:$Rt, GPR:$Rt2, addr_offset_none:$addr,
2684 IndexModePost, StMiscFrm, IIC_iStore_d_ru,
2685 "strd", "\t$Rt, $Rt2, $addr, $offset",
2686 "$addr.base = $Rn_wb", []> {
2689 let Inst{23} = offset{8}; // U bit
2690 let Inst{22} = offset{9}; // 1 == imm8, 0 == Rm
2691 let Inst{19-16} = addr;
2692 let Inst{11-8} = offset{7-4}; // imm7_4/zero
2693 let Inst{3-0} = offset{3-0}; // imm3_0/Rm
2694 let DecoderMethod = "DecodeAddrMode3Instruction";
2696 } // mayStore = 1, neverHasSideEffects = 1, hasExtraSrcRegAllocReq = 1
2698 // STRT, STRBT, and STRHT
2700 def STRBT_POST_REG : AI2ldstidx<0, 1, 0, (outs GPR:$Rn_wb),
2701 (ins GPR:$Rt, addr_offset_none:$addr, am2offset_reg:$offset),
2702 IndexModePost, StFrm, IIC_iStore_bh_ru,
2703 "strbt", "\t$Rt, $addr, $offset",
2704 "$addr.base = $Rn_wb", []> {
2710 let Inst{23} = offset{12};
2711 let Inst{21} = 1; // overwrite
2712 let Inst{19-16} = addr;
2713 let Inst{11-5} = offset{11-5};
2715 let Inst{3-0} = offset{3-0};
2716 let DecoderMethod = "DecodeAddrMode2IdxInstruction";
2719 def STRBT_POST_IMM : AI2ldstidx<0, 1, 0, (outs GPR:$Rn_wb),
2720 (ins GPR:$Rt, addr_offset_none:$addr, am2offset_imm:$offset),
2721 IndexModePost, StFrm, IIC_iStore_bh_ru,
2722 "strbt", "\t$Rt, $addr, $offset",
2723 "$addr.base = $Rn_wb", []> {
2729 let Inst{23} = offset{12};
2730 let Inst{21} = 1; // overwrite
2731 let Inst{19-16} = addr;
2732 let Inst{11-0} = offset{11-0};
2733 let DecoderMethod = "DecodeAddrMode2IdxInstruction";
2736 let mayStore = 1, neverHasSideEffects = 1 in {
2737 def STRT_POST_REG : AI2ldstidx<0, 0, 0, (outs GPR:$Rn_wb),
2738 (ins GPR:$Rt, addr_offset_none:$addr, am2offset_reg:$offset),
2739 IndexModePost, StFrm, IIC_iStore_ru,
2740 "strt", "\t$Rt, $addr, $offset",
2741 "$addr.base = $Rn_wb", []> {
2747 let Inst{23} = offset{12};
2748 let Inst{21} = 1; // overwrite
2749 let Inst{19-16} = addr;
2750 let Inst{11-5} = offset{11-5};
2752 let Inst{3-0} = offset{3-0};
2753 let DecoderMethod = "DecodeAddrMode2IdxInstruction";
2756 def STRT_POST_IMM : AI2ldstidx<0, 0, 0, (outs GPR:$Rn_wb),
2757 (ins GPR:$Rt, addr_offset_none:$addr, am2offset_imm:$offset),
2758 IndexModePost, StFrm, IIC_iStore_ru,
2759 "strt", "\t$Rt, $addr, $offset",
2760 "$addr.base = $Rn_wb", []> {
2766 let Inst{23} = offset{12};
2767 let Inst{21} = 1; // overwrite
2768 let Inst{19-16} = addr;
2769 let Inst{11-0} = offset{11-0};
2770 let DecoderMethod = "DecodeAddrMode2IdxInstruction";
2775 multiclass AI3strT<bits<4> op, string opc> {
2776 def i : AI3ldstidxT<op, 0, (outs GPR:$base_wb),
2777 (ins GPR:$Rt, addr_offset_none:$addr, postidx_imm8:$offset),
2778 IndexModePost, StMiscFrm, IIC_iStore_bh_ru, opc,
2779 "\t$Rt, $addr, $offset", "$addr.base = $base_wb", []> {
2781 let Inst{23} = offset{8};
2783 let Inst{11-8} = offset{7-4};
2784 let Inst{3-0} = offset{3-0};
2785 let AsmMatchConverter = "cvtStExtTWriteBackImm";
2787 def r : AI3ldstidxT<op, 0, (outs GPR:$base_wb),
2788 (ins GPR:$Rt, addr_offset_none:$addr, postidx_reg:$Rm),
2789 IndexModePost, StMiscFrm, IIC_iStore_bh_ru, opc,
2790 "\t$Rt, $addr, $Rm", "$addr.base = $base_wb", []> {
2792 let Inst{23} = Rm{4};
2795 let Inst{3-0} = Rm{3-0};
2796 let AsmMatchConverter = "cvtStExtTWriteBackReg";
2801 defm STRHT : AI3strT<0b1011, "strht">;
2804 //===----------------------------------------------------------------------===//
2805 // Load / store multiple Instructions.
2808 multiclass arm_ldst_mult<string asm, bit L_bit, Format f,
2809 InstrItinClass itin, InstrItinClass itin_upd> {
2810 // IA is the default, so no need for an explicit suffix on the
2811 // mnemonic here. Without it is the cannonical spelling.
2813 AXI4<(outs), (ins GPR:$Rn, pred:$p, reglist:$regs, variable_ops),
2814 IndexModeNone, f, itin,
2815 !strconcat(asm, "${p}\t$Rn, $regs"), "", []> {
2816 let Inst{24-23} = 0b01; // Increment After
2817 let Inst{21} = 0; // No writeback
2818 let Inst{20} = L_bit;
2821 AXI4<(outs GPR:$wb), (ins GPR:$Rn, pred:$p, reglist:$regs, variable_ops),
2822 IndexModeUpd, f, itin_upd,
2823 !strconcat(asm, "${p}\t$Rn!, $regs"), "$Rn = $wb", []> {
2824 let Inst{24-23} = 0b01; // Increment After
2825 let Inst{21} = 1; // Writeback
2826 let Inst{20} = L_bit;
2828 let DecoderMethod = "DecodeMemMultipleWritebackInstruction";
2831 AXI4<(outs), (ins GPR:$Rn, pred:$p, reglist:$regs, variable_ops),
2832 IndexModeNone, f, itin,
2833 !strconcat(asm, "da${p}\t$Rn, $regs"), "", []> {
2834 let Inst{24-23} = 0b00; // Decrement After
2835 let Inst{21} = 0; // No writeback
2836 let Inst{20} = L_bit;
2839 AXI4<(outs GPR:$wb), (ins GPR:$Rn, pred:$p, reglist:$regs, variable_ops),
2840 IndexModeUpd, f, itin_upd,
2841 !strconcat(asm, "da${p}\t$Rn!, $regs"), "$Rn = $wb", []> {
2842 let Inst{24-23} = 0b00; // Decrement After
2843 let Inst{21} = 1; // Writeback
2844 let Inst{20} = L_bit;
2846 let DecoderMethod = "DecodeMemMultipleWritebackInstruction";
2849 AXI4<(outs), (ins GPR:$Rn, pred:$p, reglist:$regs, variable_ops),
2850 IndexModeNone, f, itin,
2851 !strconcat(asm, "db${p}\t$Rn, $regs"), "", []> {
2852 let Inst{24-23} = 0b10; // Decrement Before
2853 let Inst{21} = 0; // No writeback
2854 let Inst{20} = L_bit;
2857 AXI4<(outs GPR:$wb), (ins GPR:$Rn, pred:$p, reglist:$regs, variable_ops),
2858 IndexModeUpd, f, itin_upd,
2859 !strconcat(asm, "db${p}\t$Rn!, $regs"), "$Rn = $wb", []> {
2860 let Inst{24-23} = 0b10; // Decrement Before
2861 let Inst{21} = 1; // Writeback
2862 let Inst{20} = L_bit;
2864 let DecoderMethod = "DecodeMemMultipleWritebackInstruction";
2867 AXI4<(outs), (ins GPR:$Rn, pred:$p, reglist:$regs, variable_ops),
2868 IndexModeNone, f, itin,
2869 !strconcat(asm, "ib${p}\t$Rn, $regs"), "", []> {
2870 let Inst{24-23} = 0b11; // Increment Before
2871 let Inst{21} = 0; // No writeback
2872 let Inst{20} = L_bit;
2875 AXI4<(outs GPR:$wb), (ins GPR:$Rn, pred:$p, reglist:$regs, variable_ops),
2876 IndexModeUpd, f, itin_upd,
2877 !strconcat(asm, "ib${p}\t$Rn!, $regs"), "$Rn = $wb", []> {
2878 let Inst{24-23} = 0b11; // Increment Before
2879 let Inst{21} = 1; // Writeback
2880 let Inst{20} = L_bit;
2882 let DecoderMethod = "DecodeMemMultipleWritebackInstruction";
2886 let neverHasSideEffects = 1 in {
2888 let mayLoad = 1, hasExtraDefRegAllocReq = 1 in
2889 defm LDM : arm_ldst_mult<"ldm", 1, LdStMulFrm, IIC_iLoad_m, IIC_iLoad_mu>;
2891 let mayStore = 1, hasExtraSrcRegAllocReq = 1 in
2892 defm STM : arm_ldst_mult<"stm", 0, LdStMulFrm, IIC_iStore_m, IIC_iStore_mu>;
2894 } // neverHasSideEffects
2896 // FIXME: remove when we have a way to marking a MI with these properties.
2897 // FIXME: Should pc be an implicit operand like PICADD, etc?
2898 let isReturn = 1, isTerminator = 1, isBarrier = 1, mayLoad = 1,
2899 hasExtraDefRegAllocReq = 1, isCodeGenOnly = 1 in
2900 def LDMIA_RET : ARMPseudoExpand<(outs GPR:$wb), (ins GPR:$Rn, pred:$p,
2901 reglist:$regs, variable_ops),
2902 4, IIC_iLoad_mBr, [],
2903 (LDMIA_UPD GPR:$wb, GPR:$Rn, pred:$p, reglist:$regs)>,
2904 RegConstraint<"$Rn = $wb">;
2906 //===----------------------------------------------------------------------===//
2907 // Move Instructions.
2910 let neverHasSideEffects = 1 in
2911 def MOVr : AsI1<0b1101, (outs GPR:$Rd), (ins GPR:$Rm), DPFrm, IIC_iMOVr,
2912 "mov", "\t$Rd, $Rm", []>, UnaryDP {
2916 let Inst{19-16} = 0b0000;
2917 let Inst{11-4} = 0b00000000;
2920 let Inst{15-12} = Rd;
2923 // A version for the smaller set of tail call registers.
2924 let neverHasSideEffects = 1 in
2925 def MOVr_TC : AsI1<0b1101, (outs tcGPR:$Rd), (ins tcGPR:$Rm), DPFrm,
2926 IIC_iMOVr, "mov", "\t$Rd, $Rm", []>, UnaryDP {
2930 let Inst{11-4} = 0b00000000;
2933 let Inst{15-12} = Rd;
2936 def MOVsr : AsI1<0b1101, (outs GPRnopc:$Rd), (ins shift_so_reg_reg:$src),
2937 DPSoRegRegFrm, IIC_iMOVsr,
2938 "mov", "\t$Rd, $src",
2939 [(set GPRnopc:$Rd, shift_so_reg_reg:$src)]>, UnaryDP {
2942 let Inst{15-12} = Rd;
2943 let Inst{19-16} = 0b0000;
2944 let Inst{11-8} = src{11-8};
2946 let Inst{6-5} = src{6-5};
2948 let Inst{3-0} = src{3-0};
2952 def MOVsi : AsI1<0b1101, (outs GPR:$Rd), (ins shift_so_reg_imm:$src),
2953 DPSoRegImmFrm, IIC_iMOVsr,
2954 "mov", "\t$Rd, $src", [(set GPR:$Rd, shift_so_reg_imm:$src)]>,
2958 let Inst{15-12} = Rd;
2959 let Inst{19-16} = 0b0000;
2960 let Inst{11-5} = src{11-5};
2962 let Inst{3-0} = src{3-0};
2966 let isReMaterializable = 1, isAsCheapAsAMove = 1, isMoveImm = 1 in
2967 def MOVi : AsI1<0b1101, (outs GPR:$Rd), (ins so_imm:$imm), DPFrm, IIC_iMOVi,
2968 "mov", "\t$Rd, $imm", [(set GPR:$Rd, so_imm:$imm)]>, UnaryDP {
2972 let Inst{15-12} = Rd;
2973 let Inst{19-16} = 0b0000;
2974 let Inst{11-0} = imm;
2977 let isReMaterializable = 1, isAsCheapAsAMove = 1, isMoveImm = 1 in
2978 def MOVi16 : AI1<0b1000, (outs GPR:$Rd), (ins imm0_65535_expr:$imm),
2980 "movw", "\t$Rd, $imm",
2981 [(set GPR:$Rd, imm0_65535:$imm)]>,
2982 Requires<[IsARM, HasV6T2]>, UnaryDP {
2985 let Inst{15-12} = Rd;
2986 let Inst{11-0} = imm{11-0};
2987 let Inst{19-16} = imm{15-12};
2992 def : InstAlias<"mov${p} $Rd, $imm",
2993 (MOVi16 GPR:$Rd, imm0_65535_expr:$imm, pred:$p)>,
2996 def MOVi16_ga_pcrel : PseudoInst<(outs GPR:$Rd),
2997 (ins i32imm:$addr, pclabel:$id), IIC_iMOVi, []>;
2999 let Constraints = "$src = $Rd" in {
3000 def MOVTi16 : AI1<0b1010, (outs GPRnopc:$Rd),
3001 (ins GPR:$src, imm0_65535_expr:$imm),
3003 "movt", "\t$Rd, $imm",
3005 (or (and GPR:$src, 0xffff),
3006 lo16AllZero:$imm))]>, UnaryDP,
3007 Requires<[IsARM, HasV6T2]> {
3010 let Inst{15-12} = Rd;
3011 let Inst{11-0} = imm{11-0};
3012 let Inst{19-16} = imm{15-12};
3017 def MOVTi16_ga_pcrel : PseudoInst<(outs GPR:$Rd),
3018 (ins GPR:$src, i32imm:$addr, pclabel:$id), IIC_iMOVi, []>;
3022 def : ARMPat<(or GPR:$src, 0xffff0000), (MOVTi16 GPR:$src, 0xffff)>,
3023 Requires<[IsARM, HasV6T2]>;
3025 let Uses = [CPSR] in
3026 def RRX: PseudoInst<(outs GPR:$Rd), (ins GPR:$Rm), IIC_iMOVsi,
3027 [(set GPR:$Rd, (ARMrrx GPR:$Rm))]>, UnaryDP,
3030 // These aren't really mov instructions, but we have to define them this way
3031 // due to flag operands.
3033 let Defs = [CPSR] in {
3034 def MOVsrl_flag : PseudoInst<(outs GPR:$dst), (ins GPR:$src), IIC_iMOVsi,
3035 [(set GPR:$dst, (ARMsrl_flag GPR:$src))]>, UnaryDP,
3037 def MOVsra_flag : PseudoInst<(outs GPR:$dst), (ins GPR:$src), IIC_iMOVsi,
3038 [(set GPR:$dst, (ARMsra_flag GPR:$src))]>, UnaryDP,
3042 //===----------------------------------------------------------------------===//
3043 // Extend Instructions.
3048 def SXTB : AI_ext_rrot<0b01101010,
3049 "sxtb", UnOpFrag<(sext_inreg node:$Src, i8)>>;
3050 def SXTH : AI_ext_rrot<0b01101011,
3051 "sxth", UnOpFrag<(sext_inreg node:$Src, i16)>>;
3053 def SXTAB : AI_exta_rrot<0b01101010,
3054 "sxtab", BinOpFrag<(add node:$LHS, (sext_inreg node:$RHS, i8))>>;
3055 def SXTAH : AI_exta_rrot<0b01101011,
3056 "sxtah", BinOpFrag<(add node:$LHS, (sext_inreg node:$RHS,i16))>>;
3058 def SXTB16 : AI_ext_rrot_np<0b01101000, "sxtb16">;
3060 def SXTAB16 : AI_exta_rrot_np<0b01101000, "sxtab16">;
3064 let AddedComplexity = 16 in {
3065 def UXTB : AI_ext_rrot<0b01101110,
3066 "uxtb" , UnOpFrag<(and node:$Src, 0x000000FF)>>;
3067 def UXTH : AI_ext_rrot<0b01101111,
3068 "uxth" , UnOpFrag<(and node:$Src, 0x0000FFFF)>>;
3069 def UXTB16 : AI_ext_rrot<0b01101100,
3070 "uxtb16", UnOpFrag<(and node:$Src, 0x00FF00FF)>>;
3072 // FIXME: This pattern incorrectly assumes the shl operator is a rotate.
3073 // The transformation should probably be done as a combiner action
3074 // instead so we can include a check for masking back in the upper
3075 // eight bits of the source into the lower eight bits of the result.
3076 //def : ARMV6Pat<(and (shl GPR:$Src, (i32 8)), 0xFF00FF),
3077 // (UXTB16r_rot GPR:$Src, 3)>;
3078 def : ARMV6Pat<(and (srl GPR:$Src, (i32 8)), 0xFF00FF),
3079 (UXTB16 GPR:$Src, 1)>;
3081 def UXTAB : AI_exta_rrot<0b01101110, "uxtab",
3082 BinOpFrag<(add node:$LHS, (and node:$RHS, 0x00FF))>>;
3083 def UXTAH : AI_exta_rrot<0b01101111, "uxtah",
3084 BinOpFrag<(add node:$LHS, (and node:$RHS, 0xFFFF))>>;
3087 // This isn't safe in general, the add is two 16-bit units, not a 32-bit add.
3088 def UXTAB16 : AI_exta_rrot_np<0b01101100, "uxtab16">;
3091 def SBFX : I<(outs GPRnopc:$Rd),
3092 (ins GPRnopc:$Rn, imm0_31:$lsb, imm1_32:$width),
3093 AddrMode1, 4, IndexModeNone, DPFrm, IIC_iUNAsi,
3094 "sbfx", "\t$Rd, $Rn, $lsb, $width", "", []>,
3095 Requires<[IsARM, HasV6T2]> {
3100 let Inst{27-21} = 0b0111101;
3101 let Inst{6-4} = 0b101;
3102 let Inst{20-16} = width;
3103 let Inst{15-12} = Rd;
3104 let Inst{11-7} = lsb;
3108 def UBFX : I<(outs GPR:$Rd),
3109 (ins GPR:$Rn, imm0_31:$lsb, imm1_32:$width),
3110 AddrMode1, 4, IndexModeNone, DPFrm, IIC_iUNAsi,
3111 "ubfx", "\t$Rd, $Rn, $lsb, $width", "", []>,
3112 Requires<[IsARM, HasV6T2]> {
3117 let Inst{27-21} = 0b0111111;
3118 let Inst{6-4} = 0b101;
3119 let Inst{20-16} = width;
3120 let Inst{15-12} = Rd;
3121 let Inst{11-7} = lsb;
3125 //===----------------------------------------------------------------------===//
3126 // Arithmetic Instructions.
3129 defm ADD : AsI1_bin_irs<0b0100, "add",
3130 IIC_iALUi, IIC_iALUr, IIC_iALUsr,
3131 BinOpFrag<(add node:$LHS, node:$RHS)>, "ADD", 1>;
3132 defm SUB : AsI1_bin_irs<0b0010, "sub",
3133 IIC_iALUi, IIC_iALUr, IIC_iALUsr,
3134 BinOpFrag<(sub node:$LHS, node:$RHS)>, "SUB">;
3136 // ADD and SUB with 's' bit set.
3137 // FIXME: Eliminate them if we can write def : Pat patterns which defines
3138 // CPSR and the implicit def of CPSR is not needed.
3139 defm ADDS : AsI1_bin_s_irs<0b0100, "add",
3140 IIC_iALUi, IIC_iALUr, IIC_iALUsr,
3141 BinOpFrag<(ARMaddc node:$LHS, node:$RHS)>, 1>;
3142 defm SUBS : AsI1_bin_s_irs<0b0010, "sub",
3143 IIC_iALUi, IIC_iALUr, IIC_iALUsr,
3144 BinOpFrag<(ARMsubc node:$LHS, node:$RHS)>>;
3146 defm ADC : AI1_adde_sube_irs<0b0101, "adc",
3147 BinOpWithFlagFrag<(ARMadde node:$LHS, node:$RHS, node:$FLAG)>,
3149 defm SBC : AI1_adde_sube_irs<0b0110, "sbc",
3150 BinOpWithFlagFrag<(ARMsube node:$LHS, node:$RHS, node:$FLAG)>,
3153 defm RSB : AsI1_rbin_irs <0b0011, "rsb",
3154 IIC_iALUi, IIC_iALUr, IIC_iALUsr,
3155 BinOpFrag<(sub node:$LHS, node:$RHS)>, "RSB">;
3157 // FIXME: Eliminate them if we can write def : Pat patterns which defines
3158 // CPSR and the implicit def of CPSR is not needed.
3159 defm RSBS : AsI1_rbin_s_is<0b0011, "rsb",
3160 IIC_iALUi, IIC_iALUr, IIC_iALUsr,
3161 BinOpFrag<(ARMsubc node:$LHS, node:$RHS)>>;
3163 defm RSC : AI1_rsc_irs<0b0111, "rsc",
3164 BinOpWithFlagFrag<(ARMsube node:$LHS, node:$RHS, node:$FLAG)>,
3167 // (sub X, imm) gets canonicalized to (add X, -imm). Match this form.
3168 // The assume-no-carry-in form uses the negation of the input since add/sub
3169 // assume opposite meanings of the carry flag (i.e., carry == !borrow).
3170 // See the definition of AddWithCarry() in the ARM ARM A2.2.1 for the gory
3172 def : ARMPat<(add GPR:$src, so_imm_neg:$imm),
3173 (SUBri GPR:$src, so_imm_neg:$imm)>;
3174 def : ARMPat<(ARMaddc GPR:$src, so_imm_neg:$imm),
3175 (SUBSri GPR:$src, so_imm_neg:$imm)>;
3177 // The with-carry-in form matches bitwise not instead of the negation.
3178 // Effectively, the inverse interpretation of the carry flag already accounts
3179 // for part of the negation.
3180 def : ARMPat<(ARMadde GPR:$src, so_imm_not:$imm, CPSR),
3181 (SBCri GPR:$src, so_imm_not:$imm)>;
3183 // Note: These are implemented in C++ code, because they have to generate
3184 // ADD/SUBrs instructions, which use a complex pattern that a xform function
3186 // (mul X, 2^n+1) -> (add (X << n), X)
3187 // (mul X, 2^n-1) -> (rsb X, (X << n))
3189 // ARM Arithmetic Instruction
3190 // GPR:$dst = GPR:$a op GPR:$b
3191 class AAI<bits<8> op27_20, bits<8> op11_4, string opc,
3192 list<dag> pattern = [],
3193 dag iops = (ins GPRnopc:$Rn, GPRnopc:$Rm),
3194 string asm = "\t$Rd, $Rn, $Rm">
3195 : AI<(outs GPRnopc:$Rd), iops, DPFrm, IIC_iALUr, opc, asm, pattern> {
3199 let Inst{27-20} = op27_20;
3200 let Inst{11-4} = op11_4;
3201 let Inst{19-16} = Rn;
3202 let Inst{15-12} = Rd;
3206 // Saturating add/subtract
3208 def QADD : AAI<0b00010000, 0b00000101, "qadd",
3209 [(set GPRnopc:$Rd, (int_arm_qadd GPRnopc:$Rm, GPRnopc:$Rn))],
3210 (ins GPRnopc:$Rm, GPRnopc:$Rn), "\t$Rd, $Rm, $Rn">;
3211 def QSUB : AAI<0b00010010, 0b00000101, "qsub",
3212 [(set GPRnopc:$Rd, (int_arm_qsub GPRnopc:$Rm, GPRnopc:$Rn))],
3213 (ins GPRnopc:$Rm, GPRnopc:$Rn), "\t$Rd, $Rm, $Rn">;
3214 def QDADD : AAI<0b00010100, 0b00000101, "qdadd", [],
3215 (ins GPRnopc:$Rm, GPRnopc:$Rn),
3217 def QDSUB : AAI<0b00010110, 0b00000101, "qdsub", [],
3218 (ins GPRnopc:$Rm, GPRnopc:$Rn),
3221 def QADD16 : AAI<0b01100010, 0b11110001, "qadd16">;
3222 def QADD8 : AAI<0b01100010, 0b11111001, "qadd8">;
3223 def QASX : AAI<0b01100010, 0b11110011, "qasx">;
3224 def QSAX : AAI<0b01100010, 0b11110101, "qsax">;
3225 def QSUB16 : AAI<0b01100010, 0b11110111, "qsub16">;
3226 def QSUB8 : AAI<0b01100010, 0b11111111, "qsub8">;
3227 def UQADD16 : AAI<0b01100110, 0b11110001, "uqadd16">;
3228 def UQADD8 : AAI<0b01100110, 0b11111001, "uqadd8">;
3229 def UQASX : AAI<0b01100110, 0b11110011, "uqasx">;
3230 def UQSAX : AAI<0b01100110, 0b11110101, "uqsax">;
3231 def UQSUB16 : AAI<0b01100110, 0b11110111, "uqsub16">;
3232 def UQSUB8 : AAI<0b01100110, 0b11111111, "uqsub8">;
3234 // Signed/Unsigned add/subtract
3236 def SASX : AAI<0b01100001, 0b11110011, "sasx">;
3237 def SADD16 : AAI<0b01100001, 0b11110001, "sadd16">;
3238 def SADD8 : AAI<0b01100001, 0b11111001, "sadd8">;
3239 def SSAX : AAI<0b01100001, 0b11110101, "ssax">;
3240 def SSUB16 : AAI<0b01100001, 0b11110111, "ssub16">;
3241 def SSUB8 : AAI<0b01100001, 0b11111111, "ssub8">;
3242 def UASX : AAI<0b01100101, 0b11110011, "uasx">;
3243 def UADD16 : AAI<0b01100101, 0b11110001, "uadd16">;
3244 def UADD8 : AAI<0b01100101, 0b11111001, "uadd8">;
3245 def USAX : AAI<0b01100101, 0b11110101, "usax">;
3246 def USUB16 : AAI<0b01100101, 0b11110111, "usub16">;
3247 def USUB8 : AAI<0b01100101, 0b11111111, "usub8">;
3249 // Signed/Unsigned halving add/subtract
3251 def SHASX : AAI<0b01100011, 0b11110011, "shasx">;
3252 def SHADD16 : AAI<0b01100011, 0b11110001, "shadd16">;
3253 def SHADD8 : AAI<0b01100011, 0b11111001, "shadd8">;
3254 def SHSAX : AAI<0b01100011, 0b11110101, "shsax">;
3255 def SHSUB16 : AAI<0b01100011, 0b11110111, "shsub16">;
3256 def SHSUB8 : AAI<0b01100011, 0b11111111, "shsub8">;
3257 def UHASX : AAI<0b01100111, 0b11110011, "uhasx">;
3258 def UHADD16 : AAI<0b01100111, 0b11110001, "uhadd16">;
3259 def UHADD8 : AAI<0b01100111, 0b11111001, "uhadd8">;
3260 def UHSAX : AAI<0b01100111, 0b11110101, "uhsax">;
3261 def UHSUB16 : AAI<0b01100111, 0b11110111, "uhsub16">;
3262 def UHSUB8 : AAI<0b01100111, 0b11111111, "uhsub8">;
3264 // Unsigned Sum of Absolute Differences [and Accumulate].
3266 def USAD8 : AI<(outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm),
3267 MulFrm /* for convenience */, NoItinerary, "usad8",
3268 "\t$Rd, $Rn, $Rm", []>,
3269 Requires<[IsARM, HasV6]> {
3273 let Inst{27-20} = 0b01111000;
3274 let Inst{15-12} = 0b1111;
3275 let Inst{7-4} = 0b0001;
3276 let Inst{19-16} = Rd;
3277 let Inst{11-8} = Rm;
3280 def USADA8 : AI<(outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm, GPR:$Ra),
3281 MulFrm /* for convenience */, NoItinerary, "usada8",
3282 "\t$Rd, $Rn, $Rm, $Ra", []>,
3283 Requires<[IsARM, HasV6]> {
3288 let Inst{27-20} = 0b01111000;
3289 let Inst{7-4} = 0b0001;
3290 let Inst{19-16} = Rd;
3291 let Inst{15-12} = Ra;
3292 let Inst{11-8} = Rm;
3296 // Signed/Unsigned saturate
3298 def SSAT : AI<(outs GPRnopc:$Rd),
3299 (ins imm1_32:$sat_imm, GPRnopc:$Rn, shift_imm:$sh),
3300 SatFrm, NoItinerary, "ssat", "\t$Rd, $sat_imm, $Rn$sh", []> {
3305 let Inst{27-21} = 0b0110101;
3306 let Inst{5-4} = 0b01;
3307 let Inst{20-16} = sat_imm;
3308 let Inst{15-12} = Rd;
3309 let Inst{11-7} = sh{4-0};
3310 let Inst{6} = sh{5};
3314 def SSAT16 : AI<(outs GPRnopc:$Rd),
3315 (ins imm1_16:$sat_imm, GPRnopc:$Rn), SatFrm,
3316 NoItinerary, "ssat16", "\t$Rd, $sat_imm, $Rn", []> {
3320 let Inst{27-20} = 0b01101010;
3321 let Inst{11-4} = 0b11110011;
3322 let Inst{15-12} = Rd;
3323 let Inst{19-16} = sat_imm;
3327 def USAT : AI<(outs GPRnopc:$Rd),
3328 (ins imm0_31:$sat_imm, GPRnopc:$Rn, shift_imm:$sh),
3329 SatFrm, NoItinerary, "usat", "\t$Rd, $sat_imm, $Rn$sh", []> {
3334 let Inst{27-21} = 0b0110111;
3335 let Inst{5-4} = 0b01;
3336 let Inst{15-12} = Rd;
3337 let Inst{11-7} = sh{4-0};
3338 let Inst{6} = sh{5};
3339 let Inst{20-16} = sat_imm;
3343 def USAT16 : AI<(outs GPRnopc:$Rd),
3344 (ins imm0_15:$sat_imm, GPRnopc:$Rn), SatFrm,
3345 NoItinerary, "usat16", "\t$Rd, $sat_imm, $Rn", []> {
3349 let Inst{27-20} = 0b01101110;
3350 let Inst{11-4} = 0b11110011;
3351 let Inst{15-12} = Rd;
3352 let Inst{19-16} = sat_imm;
3356 def : ARMV6Pat<(int_arm_ssat GPRnopc:$a, imm:$pos),
3357 (SSAT imm:$pos, GPRnopc:$a, 0)>;
3358 def : ARMV6Pat<(int_arm_usat GPRnopc:$a, imm:$pos),
3359 (USAT imm:$pos, GPRnopc:$a, 0)>;
3361 //===----------------------------------------------------------------------===//
3362 // Bitwise Instructions.
3365 defm AND : AsI1_bin_irs<0b0000, "and",
3366 IIC_iBITi, IIC_iBITr, IIC_iBITsr,
3367 BinOpFrag<(and node:$LHS, node:$RHS)>, "AND", 1>;
3368 defm ORR : AsI1_bin_irs<0b1100, "orr",
3369 IIC_iBITi, IIC_iBITr, IIC_iBITsr,
3370 BinOpFrag<(or node:$LHS, node:$RHS)>, "ORR", 1>;
3371 defm EOR : AsI1_bin_irs<0b0001, "eor",
3372 IIC_iBITi, IIC_iBITr, IIC_iBITsr,
3373 BinOpFrag<(xor node:$LHS, node:$RHS)>, "EOR", 1>;
3374 defm BIC : AsI1_bin_irs<0b1110, "bic",
3375 IIC_iBITi, IIC_iBITr, IIC_iBITsr,
3376 BinOpFrag<(and node:$LHS, (not node:$RHS))>, "BIC">;
3378 // FIXME: bf_inv_mask_imm should be two operands, the lsb and the msb, just
3379 // like in the actual instruction encoding. The complexity of mapping the mask
3380 // to the lsb/msb pair should be handled by ISel, not encapsulated in the
3381 // instruction description.
3382 def BFC : I<(outs GPR:$Rd), (ins GPR:$src, bf_inv_mask_imm:$imm),
3383 AddrMode1, 4, IndexModeNone, DPFrm, IIC_iUNAsi,
3384 "bfc", "\t$Rd, $imm", "$src = $Rd",
3385 [(set GPR:$Rd, (and GPR:$src, bf_inv_mask_imm:$imm))]>,
3386 Requires<[IsARM, HasV6T2]> {
3389 let Inst{27-21} = 0b0111110;
3390 let Inst{6-0} = 0b0011111;
3391 let Inst{15-12} = Rd;
3392 let Inst{11-7} = imm{4-0}; // lsb
3393 let Inst{20-16} = imm{9-5}; // msb
3396 // A8.6.18 BFI - Bitfield insert (Encoding A1)
3397 def BFI:I<(outs GPRnopc:$Rd), (ins GPRnopc:$src, GPR:$Rn, bf_inv_mask_imm:$imm),
3398 AddrMode1, 4, IndexModeNone, DPFrm, IIC_iUNAsi,
3399 "bfi", "\t$Rd, $Rn, $imm", "$src = $Rd",
3400 [(set GPRnopc:$Rd, (ARMbfi GPRnopc:$src, GPR:$Rn,
3401 bf_inv_mask_imm:$imm))]>,
3402 Requires<[IsARM, HasV6T2]> {
3406 let Inst{27-21} = 0b0111110;
3407 let Inst{6-4} = 0b001; // Rn: Inst{3-0} != 15
3408 let Inst{15-12} = Rd;
3409 let Inst{11-7} = imm{4-0}; // lsb
3410 let Inst{20-16} = imm{9-5}; // width
3414 // GNU as only supports this form of bfi (w/ 4 arguments)
3415 let isAsmParserOnly = 1 in
3416 def BFI4p : I<(outs GPRnopc:$Rd), (ins GPRnopc:$src, GPR:$Rn,
3417 lsb_pos_imm:$lsb, width_imm:$width),
3418 AddrMode1, 4, IndexModeNone, DPFrm, IIC_iUNAsi,
3419 "bfi", "\t$Rd, $Rn, $lsb, $width", "$src = $Rd",
3420 []>, Requires<[IsARM, HasV6T2]> {
3425 let Inst{27-21} = 0b0111110;
3426 let Inst{6-4} = 0b001; // Rn: Inst{3-0} != 15
3427 let Inst{15-12} = Rd;
3428 let Inst{11-7} = lsb;
3429 let Inst{20-16} = width; // Custom encoder => lsb+width-1
3433 def MVNr : AsI1<0b1111, (outs GPR:$Rd), (ins GPR:$Rm), DPFrm, IIC_iMVNr,
3434 "mvn", "\t$Rd, $Rm",
3435 [(set GPR:$Rd, (not GPR:$Rm))]>, UnaryDP {
3439 let Inst{19-16} = 0b0000;
3440 let Inst{11-4} = 0b00000000;
3441 let Inst{15-12} = Rd;
3444 def MVNsi : AsI1<0b1111, (outs GPR:$Rd), (ins so_reg_imm:$shift),
3445 DPSoRegImmFrm, IIC_iMVNsr, "mvn", "\t$Rd, $shift",
3446 [(set GPR:$Rd, (not so_reg_imm:$shift))]>, UnaryDP {
3450 let Inst{19-16} = 0b0000;
3451 let Inst{15-12} = Rd;
3452 let Inst{11-5} = shift{11-5};
3454 let Inst{3-0} = shift{3-0};
3456 def MVNsr : AsI1<0b1111, (outs GPR:$Rd), (ins so_reg_reg:$shift),
3457 DPSoRegRegFrm, IIC_iMVNsr, "mvn", "\t$Rd, $shift",
3458 [(set GPR:$Rd, (not so_reg_reg:$shift))]>, UnaryDP {
3462 let Inst{19-16} = 0b0000;
3463 let Inst{15-12} = Rd;
3464 let Inst{11-8} = shift{11-8};
3466 let Inst{6-5} = shift{6-5};
3468 let Inst{3-0} = shift{3-0};
3470 let isReMaterializable = 1, isAsCheapAsAMove = 1, isMoveImm = 1 in
3471 def MVNi : AsI1<0b1111, (outs GPR:$Rd), (ins so_imm:$imm), DPFrm,
3472 IIC_iMVNi, "mvn", "\t$Rd, $imm",
3473 [(set GPR:$Rd, so_imm_not:$imm)]>,UnaryDP {
3477 let Inst{19-16} = 0b0000;
3478 let Inst{15-12} = Rd;
3479 let Inst{11-0} = imm;
3482 def : ARMPat<(and GPR:$src, so_imm_not:$imm),
3483 (BICri GPR:$src, so_imm_not:$imm)>;
3485 //===----------------------------------------------------------------------===//
3486 // Multiply Instructions.
3488 class AsMul1I32<bits<7> opcod, dag oops, dag iops, InstrItinClass itin,
3489 string opc, string asm, list<dag> pattern>
3490 : AsMul1I<opcod, oops, iops, itin, opc, asm, pattern> {
3494 let Inst{19-16} = Rd;
3495 let Inst{11-8} = Rm;
3498 class AsMul1I64<bits<7> opcod, dag oops, dag iops, InstrItinClass itin,
3499 string opc, string asm, list<dag> pattern>
3500 : AsMul1I<opcod, oops, iops, itin, opc, asm, pattern> {
3505 let Inst{19-16} = RdHi;
3506 let Inst{15-12} = RdLo;
3507 let Inst{11-8} = Rm;
3511 // FIXME: The v5 pseudos are only necessary for the additional Constraint
3512 // property. Remove them when it's possible to add those properties
3513 // on an individual MachineInstr, not just an instuction description.
3514 let isCommutable = 1 in {
3515 def MUL : AsMul1I32<0b0000000, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm),
3516 IIC_iMUL32, "mul", "\t$Rd, $Rn, $Rm",
3517 [(set GPR:$Rd, (mul GPR:$Rn, GPR:$Rm))]>,
3518 Requires<[IsARM, HasV6]> {
3519 let Inst{15-12} = 0b0000;
3522 let Constraints = "@earlyclobber $Rd" in
3523 def MULv5: ARMPseudoExpand<(outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm,
3524 pred:$p, cc_out:$s),
3526 [(set GPR:$Rd, (mul GPR:$Rn, GPR:$Rm))],
3527 (MUL GPR:$Rd, GPR:$Rn, GPR:$Rm, pred:$p, cc_out:$s)>,
3528 Requires<[IsARM, NoV6]>;
3531 def MLA : AsMul1I32<0b0000001, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm, GPR:$Ra),
3532 IIC_iMAC32, "mla", "\t$Rd, $Rn, $Rm, $Ra",
3533 [(set GPR:$Rd, (add (mul GPR:$Rn, GPR:$Rm), GPR:$Ra))]>,
3534 Requires<[IsARM, HasV6]> {
3536 let Inst{15-12} = Ra;
3539 let Constraints = "@earlyclobber $Rd" in
3540 def MLAv5: ARMPseudoExpand<(outs GPR:$Rd),
3541 (ins GPR:$Rn, GPR:$Rm, GPR:$Ra, pred:$p, cc_out:$s),
3543 [(set GPR:$Rd, (add (mul GPR:$Rn, GPR:$Rm), GPR:$Ra))],
3544 (MLA GPR:$Rd, GPR:$Rn, GPR:$Rm, GPR:$Ra, pred:$p, cc_out:$s)>,
3545 Requires<[IsARM, NoV6]>;
3547 def MLS : AMul1I<0b0000011, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm, GPR:$Ra),
3548 IIC_iMAC32, "mls", "\t$Rd, $Rn, $Rm, $Ra",
3549 [(set GPR:$Rd, (sub GPR:$Ra, (mul GPR:$Rn, GPR:$Rm)))]>,
3550 Requires<[IsARM, HasV6T2]> {
3555 let Inst{19-16} = Rd;
3556 let Inst{15-12} = Ra;
3557 let Inst{11-8} = Rm;
3561 // Extra precision multiplies with low / high results
3562 let neverHasSideEffects = 1 in {
3563 let isCommutable = 1 in {
3564 def SMULL : AsMul1I64<0b0000110, (outs GPR:$RdLo, GPR:$RdHi),
3565 (ins GPR:$Rn, GPR:$Rm), IIC_iMUL64,
3566 "smull", "\t$RdLo, $RdHi, $Rn, $Rm", []>,
3567 Requires<[IsARM, HasV6]>;
3569 def UMULL : AsMul1I64<0b0000100, (outs GPR:$RdLo, GPR:$RdHi),
3570 (ins GPR:$Rn, GPR:$Rm), IIC_iMUL64,
3571 "umull", "\t$RdLo, $RdHi, $Rn, $Rm", []>,
3572 Requires<[IsARM, HasV6]>;
3574 let Constraints = "@earlyclobber $RdLo,@earlyclobber $RdHi" in {
3575 def SMULLv5 : ARMPseudoExpand<(outs GPR:$RdLo, GPR:$RdHi),
3576 (ins GPR:$Rn, GPR:$Rm, pred:$p, cc_out:$s),
3578 (SMULL GPR:$RdLo, GPR:$RdHi, GPR:$Rn, GPR:$Rm, pred:$p, cc_out:$s)>,
3579 Requires<[IsARM, NoV6]>;
3581 def UMULLv5 : ARMPseudoExpand<(outs GPR:$RdLo, GPR:$RdHi),
3582 (ins GPR:$Rn, GPR:$Rm, pred:$p, cc_out:$s),
3584 (UMULL GPR:$RdLo, GPR:$RdHi, GPR:$Rn, GPR:$Rm, pred:$p, cc_out:$s)>,
3585 Requires<[IsARM, NoV6]>;
3589 // Multiply + accumulate
3590 def SMLAL : AsMul1I64<0b0000111, (outs GPR:$RdLo, GPR:$RdHi),
3591 (ins GPR:$Rn, GPR:$Rm), IIC_iMAC64,
3592 "smlal", "\t$RdLo, $RdHi, $Rn, $Rm", []>,
3593 Requires<[IsARM, HasV6]>;
3594 def UMLAL : AsMul1I64<0b0000101, (outs GPR:$RdLo, GPR:$RdHi),
3595 (ins GPR:$Rn, GPR:$Rm), IIC_iMAC64,
3596 "umlal", "\t$RdLo, $RdHi, $Rn, $Rm", []>,
3597 Requires<[IsARM, HasV6]>;
3599 def UMAAL : AMul1I <0b0000010, (outs GPR:$RdLo, GPR:$RdHi),
3600 (ins GPR:$Rn, GPR:$Rm), IIC_iMAC64,
3601 "umaal", "\t$RdLo, $RdHi, $Rn, $Rm", []>,
3602 Requires<[IsARM, HasV6]> {
3607 let Inst{19-16} = RdHi;
3608 let Inst{15-12} = RdLo;
3609 let Inst{11-8} = Rm;
3613 let Constraints = "@earlyclobber $RdLo,@earlyclobber $RdHi" in {
3614 def SMLALv5 : ARMPseudoExpand<(outs GPR:$RdLo, GPR:$RdHi),
3615 (ins GPR:$Rn, GPR:$Rm, pred:$p, cc_out:$s),
3617 (SMLAL GPR:$RdLo, GPR:$RdHi, GPR:$Rn, GPR:$Rm, pred:$p, cc_out:$s)>,
3618 Requires<[IsARM, NoV6]>;
3619 def UMLALv5 : ARMPseudoExpand<(outs GPR:$RdLo, GPR:$RdHi),
3620 (ins GPR:$Rn, GPR:$Rm, pred:$p, cc_out:$s),
3622 (UMLAL GPR:$RdLo, GPR:$RdHi, GPR:$Rn, GPR:$Rm, pred:$p, cc_out:$s)>,
3623 Requires<[IsARM, NoV6]>;
3624 def UMAALv5 : ARMPseudoExpand<(outs GPR:$RdLo, GPR:$RdHi),
3625 (ins GPR:$Rn, GPR:$Rm, pred:$p),
3627 (UMAAL GPR:$RdLo, GPR:$RdHi, GPR:$Rn, GPR:$Rm, pred:$p)>,
3628 Requires<[IsARM, NoV6]>;
3631 } // neverHasSideEffects
3633 // Most significant word multiply
3634 def SMMUL : AMul2I <0b0111010, 0b0001, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm),
3635 IIC_iMUL32, "smmul", "\t$Rd, $Rn, $Rm",
3636 [(set GPR:$Rd, (mulhs GPR:$Rn, GPR:$Rm))]>,
3637 Requires<[IsARM, HasV6]> {
3638 let Inst{15-12} = 0b1111;
3641 def SMMULR : AMul2I <0b0111010, 0b0011, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm),
3642 IIC_iMUL32, "smmulr", "\t$Rd, $Rn, $Rm", []>,
3643 Requires<[IsARM, HasV6]> {
3644 let Inst{15-12} = 0b1111;
3647 def SMMLA : AMul2Ia <0b0111010, 0b0001, (outs GPR:$Rd),
3648 (ins GPR:$Rn, GPR:$Rm, GPR:$Ra),
3649 IIC_iMAC32, "smmla", "\t$Rd, $Rn, $Rm, $Ra",
3650 [(set GPR:$Rd, (add (mulhs GPR:$Rn, GPR:$Rm), GPR:$Ra))]>,
3651 Requires<[IsARM, HasV6]>;
3653 def SMMLAR : AMul2Ia <0b0111010, 0b0011, (outs GPR:$Rd),
3654 (ins GPR:$Rn, GPR:$Rm, GPR:$Ra),
3655 IIC_iMAC32, "smmlar", "\t$Rd, $Rn, $Rm, $Ra", []>,
3656 Requires<[IsARM, HasV6]>;
3658 def SMMLS : AMul2Ia <0b0111010, 0b1101, (outs GPR:$Rd),
3659 (ins GPR:$Rn, GPR:$Rm, GPR:$Ra),
3660 IIC_iMAC32, "smmls", "\t$Rd, $Rn, $Rm, $Ra",
3661 [(set GPR:$Rd, (sub GPR:$Ra, (mulhs GPR:$Rn, GPR:$Rm)))]>,
3662 Requires<[IsARM, HasV6]>;
3664 def SMMLSR : AMul2Ia <0b0111010, 0b1111, (outs GPR:$Rd),
3665 (ins GPR:$Rn, GPR:$Rm, GPR:$Ra),
3666 IIC_iMAC32, "smmlsr", "\t$Rd, $Rn, $Rm, $Ra", []>,
3667 Requires<[IsARM, HasV6]>;
3669 multiclass AI_smul<string opc, PatFrag opnode> {
3670 def BB : AMulxyI<0b0001011, 0b00, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm),
3671 IIC_iMUL16, !strconcat(opc, "bb"), "\t$Rd, $Rn, $Rm",
3672 [(set GPR:$Rd, (opnode (sext_inreg GPR:$Rn, i16),
3673 (sext_inreg GPR:$Rm, i16)))]>,
3674 Requires<[IsARM, HasV5TE]>;
3676 def BT : AMulxyI<0b0001011, 0b10, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm),
3677 IIC_iMUL16, !strconcat(opc, "bt"), "\t$Rd, $Rn, $Rm",
3678 [(set GPR:$Rd, (opnode (sext_inreg GPR:$Rn, i16),
3679 (sra GPR:$Rm, (i32 16))))]>,
3680 Requires<[IsARM, HasV5TE]>;
3682 def TB : AMulxyI<0b0001011, 0b01, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm),
3683 IIC_iMUL16, !strconcat(opc, "tb"), "\t$Rd, $Rn, $Rm",
3684 [(set GPR:$Rd, (opnode (sra GPR:$Rn, (i32 16)),
3685 (sext_inreg GPR:$Rm, i16)))]>,
3686 Requires<[IsARM, HasV5TE]>;
3688 def TT : AMulxyI<0b0001011, 0b11, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm),
3689 IIC_iMUL16, !strconcat(opc, "tt"), "\t$Rd, $Rn, $Rm",
3690 [(set GPR:$Rd, (opnode (sra GPR:$Rn, (i32 16)),
3691 (sra GPR:$Rm, (i32 16))))]>,
3692 Requires<[IsARM, HasV5TE]>;
3694 def WB : AMulxyI<0b0001001, 0b01, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm),
3695 IIC_iMUL16, !strconcat(opc, "wb"), "\t$Rd, $Rn, $Rm",
3696 [(set GPR:$Rd, (sra (opnode GPR:$Rn,
3697 (sext_inreg GPR:$Rm, i16)), (i32 16)))]>,
3698 Requires<[IsARM, HasV5TE]>;
3700 def WT : AMulxyI<0b0001001, 0b11, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm),
3701 IIC_iMUL16, !strconcat(opc, "wt"), "\t$Rd, $Rn, $Rm",
3702 [(set GPR:$Rd, (sra (opnode GPR:$Rn,
3703 (sra GPR:$Rm, (i32 16))), (i32 16)))]>,
3704 Requires<[IsARM, HasV5TE]>;
3708 multiclass AI_smla<string opc, PatFrag opnode> {
3709 let DecoderMethod = "DecodeSMLAInstruction" in {
3710 def BB : AMulxyIa<0b0001000, 0b00, (outs GPRnopc:$Rd),
3711 (ins GPRnopc:$Rn, GPRnopc:$Rm, GPR:$Ra),
3712 IIC_iMAC16, !strconcat(opc, "bb"), "\t$Rd, $Rn, $Rm, $Ra",
3713 [(set GPRnopc:$Rd, (add GPR:$Ra,
3714 (opnode (sext_inreg GPRnopc:$Rn, i16),
3715 (sext_inreg GPRnopc:$Rm, i16))))]>,
3716 Requires<[IsARM, HasV5TE]>;
3718 def BT : AMulxyIa<0b0001000, 0b10, (outs GPRnopc:$Rd),
3719 (ins GPRnopc:$Rn, GPRnopc:$Rm, GPR:$Ra),
3720 IIC_iMAC16, !strconcat(opc, "bt"), "\t$Rd, $Rn, $Rm, $Ra",
3722 (add GPR:$Ra, (opnode (sext_inreg GPRnopc:$Rn, i16),
3723 (sra GPRnopc:$Rm, (i32 16)))))]>,
3724 Requires<[IsARM, HasV5TE]>;
3726 def TB : AMulxyIa<0b0001000, 0b01, (outs GPRnopc:$Rd),
3727 (ins GPRnopc:$Rn, GPRnopc:$Rm, GPR:$Ra),
3728 IIC_iMAC16, !strconcat(opc, "tb"), "\t$Rd, $Rn, $Rm, $Ra",
3730 (add GPR:$Ra, (opnode (sra GPRnopc:$Rn, (i32 16)),
3731 (sext_inreg GPRnopc:$Rm, i16))))]>,
3732 Requires<[IsARM, HasV5TE]>;
3734 def TT : AMulxyIa<0b0001000, 0b11, (outs GPRnopc:$Rd),
3735 (ins GPRnopc:$Rn, GPRnopc:$Rm, GPR:$Ra),
3736 IIC_iMAC16, !strconcat(opc, "tt"), "\t$Rd, $Rn, $Rm, $Ra",
3738 (add GPR:$Ra, (opnode (sra GPRnopc:$Rn, (i32 16)),
3739 (sra GPRnopc:$Rm, (i32 16)))))]>,
3740 Requires<[IsARM, HasV5TE]>;
3742 def WB : AMulxyIa<0b0001001, 0b00, (outs GPRnopc:$Rd),
3743 (ins GPRnopc:$Rn, GPRnopc:$Rm, GPR:$Ra),
3744 IIC_iMAC16, !strconcat(opc, "wb"), "\t$Rd, $Rn, $Rm, $Ra",
3746 (add GPR:$Ra, (sra (opnode GPRnopc:$Rn,
3747 (sext_inreg GPRnopc:$Rm, i16)), (i32 16))))]>,
3748 Requires<[IsARM, HasV5TE]>;
3750 def WT : AMulxyIa<0b0001001, 0b10, (outs GPRnopc:$Rd),
3751 (ins GPRnopc:$Rn, GPRnopc:$Rm, GPR:$Ra),
3752 IIC_iMAC16, !strconcat(opc, "wt"), "\t$Rd, $Rn, $Rm, $Ra",
3754 (add GPR:$Ra, (sra (opnode GPRnopc:$Rn,
3755 (sra GPRnopc:$Rm, (i32 16))), (i32 16))))]>,
3756 Requires<[IsARM, HasV5TE]>;
3760 defm SMUL : AI_smul<"smul", BinOpFrag<(mul node:$LHS, node:$RHS)>>;
3761 defm SMLA : AI_smla<"smla", BinOpFrag<(mul node:$LHS, node:$RHS)>>;
3763 // Halfword multiply accumulate long: SMLAL<x><y>.
3764 def SMLALBB : AMulxyI64<0b0001010, 0b00, (outs GPRnopc:$RdLo, GPRnopc:$RdHi),
3765 (ins GPRnopc:$Rn, GPRnopc:$Rm),
3766 IIC_iMAC64, "smlalbb", "\t$RdLo, $RdHi, $Rn, $Rm", []>,
3767 Requires<[IsARM, HasV5TE]>;
3769 def SMLALBT : AMulxyI64<0b0001010, 0b10, (outs GPRnopc:$RdLo, GPRnopc:$RdHi),
3770 (ins GPRnopc:$Rn, GPRnopc:$Rm),
3771 IIC_iMAC64, "smlalbt", "\t$RdLo, $RdHi, $Rn, $Rm", []>,
3772 Requires<[IsARM, HasV5TE]>;
3774 def SMLALTB : AMulxyI64<0b0001010, 0b01, (outs GPRnopc:$RdLo, GPRnopc:$RdHi),
3775 (ins GPRnopc:$Rn, GPRnopc:$Rm),
3776 IIC_iMAC64, "smlaltb", "\t$RdLo, $RdHi, $Rn, $Rm", []>,
3777 Requires<[IsARM, HasV5TE]>;
3779 def SMLALTT : AMulxyI64<0b0001010, 0b11, (outs GPRnopc:$RdLo, GPRnopc:$RdHi),
3780 (ins GPRnopc:$Rn, GPRnopc:$Rm),
3781 IIC_iMAC64, "smlaltt", "\t$RdLo, $RdHi, $Rn, $Rm", []>,
3782 Requires<[IsARM, HasV5TE]>;
3784 // Helper class for AI_smld.
3785 class AMulDualIbase<bit long, bit sub, bit swap, dag oops, dag iops,
3786 InstrItinClass itin, string opc, string asm>
3787 : AI<oops, iops, MulFrm, itin, opc, asm, []>, Requires<[IsARM, HasV6]> {
3790 let Inst{27-23} = 0b01110;
3791 let Inst{22} = long;
3792 let Inst{21-20} = 0b00;
3793 let Inst{11-8} = Rm;
3800 class AMulDualI<bit long, bit sub, bit swap, dag oops, dag iops,
3801 InstrItinClass itin, string opc, string asm>
3802 : AMulDualIbase<long, sub, swap, oops, iops, itin, opc, asm> {
3804 let Inst{15-12} = 0b1111;
3805 let Inst{19-16} = Rd;
3807 class AMulDualIa<bit long, bit sub, bit swap, dag oops, dag iops,
3808 InstrItinClass itin, string opc, string asm>
3809 : AMulDualIbase<long, sub, swap, oops, iops, itin, opc, asm> {
3812 let Inst{19-16} = Rd;
3813 let Inst{15-12} = Ra;
3815 class AMulDualI64<bit long, bit sub, bit swap, dag oops, dag iops,
3816 InstrItinClass itin, string opc, string asm>
3817 : AMulDualIbase<long, sub, swap, oops, iops, itin, opc, asm> {
3820 let Inst{19-16} = RdHi;
3821 let Inst{15-12} = RdLo;
3824 multiclass AI_smld<bit sub, string opc> {
3826 def D : AMulDualIa<0, sub, 0, (outs GPRnopc:$Rd),
3827 (ins GPRnopc:$Rn, GPRnopc:$Rm, GPR:$Ra),
3828 NoItinerary, !strconcat(opc, "d"), "\t$Rd, $Rn, $Rm, $Ra">;
3830 def DX: AMulDualIa<0, sub, 1, (outs GPRnopc:$Rd),
3831 (ins GPRnopc:$Rn, GPRnopc:$Rm, GPR:$Ra),
3832 NoItinerary, !strconcat(opc, "dx"), "\t$Rd, $Rn, $Rm, $Ra">;
3834 def LD: AMulDualI64<1, sub, 0, (outs GPRnopc:$RdLo, GPRnopc:$RdHi),
3835 (ins GPRnopc:$Rn, GPRnopc:$Rm), NoItinerary,
3836 !strconcat(opc, "ld"), "\t$RdLo, $RdHi, $Rn, $Rm">;
3838 def LDX : AMulDualI64<1, sub, 1, (outs GPRnopc:$RdLo, GPRnopc:$RdHi),
3839 (ins GPRnopc:$Rn, GPRnopc:$Rm), NoItinerary,
3840 !strconcat(opc, "ldx"),"\t$RdLo, $RdHi, $Rn, $Rm">;
3844 defm SMLA : AI_smld<0, "smla">;
3845 defm SMLS : AI_smld<1, "smls">;
3847 multiclass AI_sdml<bit sub, string opc> {
3849 def D:AMulDualI<0, sub, 0, (outs GPRnopc:$Rd), (ins GPRnopc:$Rn, GPRnopc:$Rm),
3850 NoItinerary, !strconcat(opc, "d"), "\t$Rd, $Rn, $Rm">;
3851 def DX:AMulDualI<0, sub, 1, (outs GPRnopc:$Rd),(ins GPRnopc:$Rn, GPRnopc:$Rm),
3852 NoItinerary, !strconcat(opc, "dx"), "\t$Rd, $Rn, $Rm">;
3855 defm SMUA : AI_sdml<0, "smua">;
3856 defm SMUS : AI_sdml<1, "smus">;
3858 //===----------------------------------------------------------------------===//
3859 // Misc. Arithmetic Instructions.
3862 def CLZ : AMiscA1I<0b000010110, 0b0001, (outs GPR:$Rd), (ins GPR:$Rm),
3863 IIC_iUNAr, "clz", "\t$Rd, $Rm",
3864 [(set GPR:$Rd, (ctlz GPR:$Rm))]>, Requires<[IsARM, HasV5T]>;
3866 def RBIT : AMiscA1I<0b01101111, 0b0011, (outs GPR:$Rd), (ins GPR:$Rm),
3867 IIC_iUNAr, "rbit", "\t$Rd, $Rm",
3868 [(set GPR:$Rd, (ARMrbit GPR:$Rm))]>,
3869 Requires<[IsARM, HasV6T2]>;
3871 def REV : AMiscA1I<0b01101011, 0b0011, (outs GPR:$Rd), (ins GPR:$Rm),
3872 IIC_iUNAr, "rev", "\t$Rd, $Rm",
3873 [(set GPR:$Rd, (bswap GPR:$Rm))]>, Requires<[IsARM, HasV6]>;
3875 let AddedComplexity = 5 in
3876 def REV16 : AMiscA1I<0b01101011, 0b1011, (outs GPR:$Rd), (ins GPR:$Rm),
3877 IIC_iUNAr, "rev16", "\t$Rd, $Rm",
3878 [(set GPR:$Rd, (rotr (bswap GPR:$Rm), (i32 16)))]>,
3879 Requires<[IsARM, HasV6]>;
3881 let AddedComplexity = 5 in
3882 def REVSH : AMiscA1I<0b01101111, 0b1011, (outs GPR:$Rd), (ins GPR:$Rm),
3883 IIC_iUNAr, "revsh", "\t$Rd, $Rm",
3884 [(set GPR:$Rd, (sra (bswap GPR:$Rm), (i32 16)))]>,
3885 Requires<[IsARM, HasV6]>;
3887 def : ARMV6Pat<(or (sra (shl GPR:$Rm, (i32 24)), (i32 16)),
3888 (and (srl GPR:$Rm, (i32 8)), 0xFF)),
3891 def PKHBT : APKHI<0b01101000, 0, (outs GPR:$Rd),
3892 (ins GPR:$Rn, GPR:$Rm, pkh_lsl_amt:$sh),
3893 IIC_iALUsi, "pkhbt", "\t$Rd, $Rn, $Rm$sh",
3894 [(set GPR:$Rd, (or (and GPR:$Rn, 0xFFFF),
3895 (and (shl GPR:$Rm, pkh_lsl_amt:$sh),
3897 Requires<[IsARM, HasV6]>;
3899 // Alternate cases for PKHBT where identities eliminate some nodes.
3900 def : ARMV6Pat<(or (and GPR:$Rn, 0xFFFF), (and GPR:$Rm, 0xFFFF0000)),
3901 (PKHBT GPR:$Rn, GPR:$Rm, 0)>;
3902 def : ARMV6Pat<(or (and GPR:$Rn, 0xFFFF), (shl GPR:$Rm, imm16_31:$sh)),
3903 (PKHBT GPR:$Rn, GPR:$Rm, imm16_31:$sh)>;
3905 // Note: Shifts of 1-15 bits will be transformed to srl instead of sra and
3906 // will match the pattern below.
3907 def PKHTB : APKHI<0b01101000, 1, (outs GPR:$Rd),
3908 (ins GPR:$Rn, GPR:$Rm, pkh_asr_amt:$sh),
3909 IIC_iBITsi, "pkhtb", "\t$Rd, $Rn, $Rm$sh",
3910 [(set GPR:$Rd, (or (and GPR:$Rn, 0xFFFF0000),
3911 (and (sra GPR:$Rm, pkh_asr_amt:$sh),
3913 Requires<[IsARM, HasV6]>;
3915 // Alternate cases for PKHTB where identities eliminate some nodes. Note that
3916 // a shift amount of 0 is *not legal* here, it is PKHBT instead.
3917 def : ARMV6Pat<(or (and GPR:$src1, 0xFFFF0000), (srl GPR:$src2, imm16_31:$sh)),
3918 (PKHTB GPR:$src1, GPR:$src2, imm16_31:$sh)>;
3919 def : ARMV6Pat<(or (and GPR:$src1, 0xFFFF0000),
3920 (and (srl GPR:$src2, imm1_15:$sh), 0xFFFF)),
3921 (PKHTB GPR:$src1, GPR:$src2, imm1_15:$sh)>;
3923 //===----------------------------------------------------------------------===//
3924 // Comparison Instructions...
3927 defm CMP : AI1_cmp_irs<0b1010, "cmp",
3928 IIC_iCMPi, IIC_iCMPr, IIC_iCMPsr,
3929 BinOpFrag<(ARMcmp node:$LHS, node:$RHS)>>;
3931 // ARMcmpZ can re-use the above instruction definitions.
3932 def : ARMPat<(ARMcmpZ GPR:$src, so_imm:$imm),
3933 (CMPri GPR:$src, so_imm:$imm)>;
3934 def : ARMPat<(ARMcmpZ GPR:$src, GPR:$rhs),
3935 (CMPrr GPR:$src, GPR:$rhs)>;
3936 def : ARMPat<(ARMcmpZ GPR:$src, so_reg_imm:$rhs),
3937 (CMPrsi GPR:$src, so_reg_imm:$rhs)>;
3938 def : ARMPat<(ARMcmpZ GPR:$src, so_reg_reg:$rhs),
3939 (CMPrsr GPR:$src, so_reg_reg:$rhs)>;
3941 // FIXME: We have to be careful when using the CMN instruction and comparison
3942 // with 0. One would expect these two pieces of code should give identical
3958 // However, the CMN gives the *opposite* result when r1 is 0. This is because
3959 // the carry flag is set in the CMP case but not in the CMN case. In short, the
3960 // CMP instruction doesn't perform a truncate of the (logical) NOT of 0 plus the
3961 // value of r0 and the carry bit (because the "carry bit" parameter to
3962 // AddWithCarry is defined as 1 in this case, the carry flag will always be set
3963 // when r0 >= 0). The CMN instruction doesn't perform a NOT of 0 so there is
3964 // never a "carry" when this AddWithCarry is performed (because the "carry bit"
3965 // parameter to AddWithCarry is defined as 0).
3967 // When x is 0 and unsigned:
3971 // ~x + 1 = 0x1 0000 0000
3972 // (-x = 0) != (0x1 0000 0000 = ~x + 1)
3974 // Therefore, we should disable CMN when comparing against zero, until we can
3975 // limit when the CMN instruction is used (when we know that the RHS is not 0 or
3976 // when it's a comparison which doesn't look at the 'carry' flag).
3978 // (See the ARM docs for the "AddWithCarry" pseudo-code.)
3980 // This is related to <rdar://problem/7569620>.
3982 //defm CMN : AI1_cmp_irs<0b1011, "cmn",
3983 // BinOpFrag<(ARMcmp node:$LHS,(ineg node:$RHS))>>;
3985 // Note that TST/TEQ don't set all the same flags that CMP does!
3986 defm TST : AI1_cmp_irs<0b1000, "tst",
3987 IIC_iTSTi, IIC_iTSTr, IIC_iTSTsr,
3988 BinOpFrag<(ARMcmpZ (and_su node:$LHS, node:$RHS), 0)>, 1>;
3989 defm TEQ : AI1_cmp_irs<0b1001, "teq",
3990 IIC_iTSTi, IIC_iTSTr, IIC_iTSTsr,
3991 BinOpFrag<(ARMcmpZ (xor_su node:$LHS, node:$RHS), 0)>, 1>;
3993 defm CMNz : AI1_cmp_irs<0b1011, "cmn",
3994 IIC_iCMPi, IIC_iCMPr, IIC_iCMPsr,
3995 BinOpFrag<(ARMcmpZ node:$LHS,(ineg node:$RHS))>>;
3997 //def : ARMPat<(ARMcmp GPR:$src, so_imm_neg:$imm),
3998 // (CMNri GPR:$src, so_imm_neg:$imm)>;
4000 def : ARMPat<(ARMcmpZ GPR:$src, so_imm_neg:$imm),
4001 (CMNzri GPR:$src, so_imm_neg:$imm)>;
4003 // Pseudo i64 compares for some floating point compares.
4004 let usesCustomInserter = 1, isBranch = 1, isTerminator = 1,
4006 def BCCi64 : PseudoInst<(outs),
4007 (ins i32imm:$cc, GPR:$lhs1, GPR:$lhs2, GPR:$rhs1, GPR:$rhs2, brtarget:$dst),
4009 [(ARMBcci64 imm:$cc, GPR:$lhs1, GPR:$lhs2, GPR:$rhs1, GPR:$rhs2, bb:$dst)]>;
4011 def BCCZi64 : PseudoInst<(outs),
4012 (ins i32imm:$cc, GPR:$lhs1, GPR:$lhs2, brtarget:$dst), IIC_Br,
4013 [(ARMBcci64 imm:$cc, GPR:$lhs1, GPR:$lhs2, 0, 0, bb:$dst)]>;
4014 } // usesCustomInserter
4017 // Conditional moves
4018 // FIXME: should be able to write a pattern for ARMcmov, but can't use
4019 // a two-value operand where a dag node expects two operands. :(
4020 let neverHasSideEffects = 1 in {
4021 def MOVCCr : ARMPseudoInst<(outs GPR:$Rd), (ins GPR:$false, GPR:$Rm, pred:$p),
4023 [/*(set GPR:$Rd, (ARMcmov GPR:$false, GPR:$Rm, imm:$cc, CCR:$ccr))*/]>,
4024 RegConstraint<"$false = $Rd">;
4025 def MOVCCsi : ARMPseudoInst<(outs GPR:$Rd),
4026 (ins GPR:$false, so_reg_imm:$shift, pred:$p),
4028 [/*(set GPR:$Rd, (ARMcmov GPR:$false, so_reg_imm:$shift,
4029 imm:$cc, CCR:$ccr))*/]>,
4030 RegConstraint<"$false = $Rd">;
4031 def MOVCCsr : ARMPseudoInst<(outs GPR:$Rd),
4032 (ins GPR:$false, so_reg_reg:$shift, pred:$p),
4034 [/*(set GPR:$Rd, (ARMcmov GPR:$false, so_reg_reg:$shift,
4035 imm:$cc, CCR:$ccr))*/]>,
4036 RegConstraint<"$false = $Rd">;
4039 let isMoveImm = 1 in
4040 def MOVCCi16 : ARMPseudoInst<(outs GPR:$Rd),
4041 (ins GPR:$false, imm0_65535_expr:$imm, pred:$p),
4044 RegConstraint<"$false = $Rd">, Requires<[IsARM, HasV6T2]>;
4046 let isMoveImm = 1 in
4047 def MOVCCi : ARMPseudoInst<(outs GPR:$Rd),
4048 (ins GPR:$false, so_imm:$imm, pred:$p),
4050 [/*(set GPR:$Rd, (ARMcmov GPR:$false, so_imm:$imm, imm:$cc, CCR:$ccr))*/]>,
4051 RegConstraint<"$false = $Rd">;
4053 // Two instruction predicate mov immediate.
4054 let isMoveImm = 1 in
4055 def MOVCCi32imm : ARMPseudoInst<(outs GPR:$Rd),
4056 (ins GPR:$false, i32imm:$src, pred:$p),
4057 8, IIC_iCMOVix2, []>, RegConstraint<"$false = $Rd">;
4059 let isMoveImm = 1 in
4060 def MVNCCi : ARMPseudoInst<(outs GPR:$Rd),
4061 (ins GPR:$false, so_imm:$imm, pred:$p),
4063 [/*(set GPR:$Rd, (ARMcmov GPR:$false, so_imm_not:$imm, imm:$cc, CCR:$ccr))*/]>,
4064 RegConstraint<"$false = $Rd">;
4065 } // neverHasSideEffects
4067 //===----------------------------------------------------------------------===//
4068 // Atomic operations intrinsics
4071 def MemBarrierOptOperand : AsmOperandClass {
4072 let Name = "MemBarrierOpt";
4073 let ParserMethod = "parseMemBarrierOptOperand";
4075 def memb_opt : Operand<i32> {
4076 let PrintMethod = "printMemBOption";
4077 let ParserMatchClass = MemBarrierOptOperand;
4078 let DecoderMethod = "DecodeMemBarrierOption";
4081 // memory barriers protect the atomic sequences
4082 let hasSideEffects = 1 in {
4083 def DMB : AInoP<(outs), (ins memb_opt:$opt), MiscFrm, NoItinerary,
4084 "dmb", "\t$opt", [(ARMMemBarrier (i32 imm:$opt))]>,
4085 Requires<[IsARM, HasDB]> {
4087 let Inst{31-4} = 0xf57ff05;
4088 let Inst{3-0} = opt;
4092 def DSB : AInoP<(outs), (ins memb_opt:$opt), MiscFrm, NoItinerary,
4093 "dsb", "\t$opt", []>,
4094 Requires<[IsARM, HasDB]> {
4096 let Inst{31-4} = 0xf57ff04;
4097 let Inst{3-0} = opt;
4100 // ISB has only full system option
4101 def ISB : AInoP<(outs), (ins memb_opt:$opt), MiscFrm, NoItinerary,
4102 "isb", "\t$opt", []>,
4103 Requires<[IsARM, HasDB]> {
4105 let Inst{31-4} = 0xf57ff06;
4106 let Inst{3-0} = opt;
4109 let usesCustomInserter = 1 in {
4110 let Defs = [CPSR] in {
4111 def ATOMIC_LOAD_ADD_I8 : PseudoInst<
4112 (outs GPR:$dst), (ins GPR:$ptr, GPR:$incr), NoItinerary,
4113 [(set GPR:$dst, (atomic_load_add_8 GPR:$ptr, GPR:$incr))]>;
4114 def ATOMIC_LOAD_SUB_I8 : PseudoInst<
4115 (outs GPR:$dst), (ins GPR:$ptr, GPR:$incr), NoItinerary,
4116 [(set GPR:$dst, (atomic_load_sub_8 GPR:$ptr, GPR:$incr))]>;
4117 def ATOMIC_LOAD_AND_I8 : PseudoInst<
4118 (outs GPR:$dst), (ins GPR:$ptr, GPR:$incr), NoItinerary,
4119 [(set GPR:$dst, (atomic_load_and_8 GPR:$ptr, GPR:$incr))]>;
4120 def ATOMIC_LOAD_OR_I8 : PseudoInst<
4121 (outs GPR:$dst), (ins GPR:$ptr, GPR:$incr), NoItinerary,
4122 [(set GPR:$dst, (atomic_load_or_8 GPR:$ptr, GPR:$incr))]>;
4123 def ATOMIC_LOAD_XOR_I8 : PseudoInst<
4124 (outs GPR:$dst), (ins GPR:$ptr, GPR:$incr), NoItinerary,
4125 [(set GPR:$dst, (atomic_load_xor_8 GPR:$ptr, GPR:$incr))]>;
4126 def ATOMIC_LOAD_NAND_I8 : PseudoInst<
4127 (outs GPR:$dst), (ins GPR:$ptr, GPR:$incr), NoItinerary,
4128 [(set GPR:$dst, (atomic_load_nand_8 GPR:$ptr, GPR:$incr))]>;
4129 def ATOMIC_LOAD_MIN_I8 : PseudoInst<
4130 (outs GPR:$dst), (ins GPR:$ptr, GPR:$val), NoItinerary,
4131 [(set GPR:$dst, (atomic_load_min_8 GPR:$ptr, GPR:$val))]>;
4132 def ATOMIC_LOAD_MAX_I8 : PseudoInst<
4133 (outs GPR:$dst), (ins GPR:$ptr, GPR:$val), NoItinerary,
4134 [(set GPR:$dst, (atomic_load_max_8 GPR:$ptr, GPR:$val))]>;
4135 def ATOMIC_LOAD_UMIN_I8 : PseudoInst<
4136 (outs GPR:$dst), (ins GPR:$ptr, GPR:$val), NoItinerary,
4137 [(set GPR:$dst, (atomic_load_min_8 GPR:$ptr, GPR:$val))]>;
4138 def ATOMIC_LOAD_UMAX_I8 : PseudoInst<
4139 (outs GPR:$dst), (ins GPR:$ptr, GPR:$val), NoItinerary,
4140 [(set GPR:$dst, (atomic_load_max_8 GPR:$ptr, GPR:$val))]>;
4141 def ATOMIC_LOAD_ADD_I16 : PseudoInst<
4142 (outs GPR:$dst), (ins GPR:$ptr, GPR:$incr), NoItinerary,
4143 [(set GPR:$dst, (atomic_load_add_16 GPR:$ptr, GPR:$incr))]>;
4144 def ATOMIC_LOAD_SUB_I16 : PseudoInst<
4145 (outs GPR:$dst), (ins GPR:$ptr, GPR:$incr), NoItinerary,
4146 [(set GPR:$dst, (atomic_load_sub_16 GPR:$ptr, GPR:$incr))]>;
4147 def ATOMIC_LOAD_AND_I16 : PseudoInst<
4148 (outs GPR:$dst), (ins GPR:$ptr, GPR:$incr), NoItinerary,
4149 [(set GPR:$dst, (atomic_load_and_16 GPR:$ptr, GPR:$incr))]>;
4150 def ATOMIC_LOAD_OR_I16 : PseudoInst<
4151 (outs GPR:$dst), (ins GPR:$ptr, GPR:$incr), NoItinerary,
4152 [(set GPR:$dst, (atomic_load_or_16 GPR:$ptr, GPR:$incr))]>;
4153 def ATOMIC_LOAD_XOR_I16 : PseudoInst<
4154 (outs GPR:$dst), (ins GPR:$ptr, GPR:$incr), NoItinerary,
4155 [(set GPR:$dst, (atomic_load_xor_16 GPR:$ptr, GPR:$incr))]>;
4156 def ATOMIC_LOAD_NAND_I16 : PseudoInst<
4157 (outs GPR:$dst), (ins GPR:$ptr, GPR:$incr), NoItinerary,
4158 [(set GPR:$dst, (atomic_load_nand_16 GPR:$ptr, GPR:$incr))]>;
4159 def ATOMIC_LOAD_MIN_I16 : PseudoInst<
4160 (outs GPR:$dst), (ins GPR:$ptr, GPR:$val), NoItinerary,
4161 [(set GPR:$dst, (atomic_load_min_16 GPR:$ptr, GPR:$val))]>;
4162 def ATOMIC_LOAD_MAX_I16 : PseudoInst<
4163 (outs GPR:$dst), (ins GPR:$ptr, GPR:$val), NoItinerary,
4164 [(set GPR:$dst, (atomic_load_max_16 GPR:$ptr, GPR:$val))]>;
4165 def ATOMIC_LOAD_UMIN_I16 : PseudoInst<
4166 (outs GPR:$dst), (ins GPR:$ptr, GPR:$val), NoItinerary,
4167 [(set GPR:$dst, (atomic_load_min_16 GPR:$ptr, GPR:$val))]>;
4168 def ATOMIC_LOAD_UMAX_I16 : PseudoInst<
4169 (outs GPR:$dst), (ins GPR:$ptr, GPR:$val), NoItinerary,
4170 [(set GPR:$dst, (atomic_load_max_16 GPR:$ptr, GPR:$val))]>;
4171 def ATOMIC_LOAD_ADD_I32 : PseudoInst<
4172 (outs GPR:$dst), (ins GPR:$ptr, GPR:$incr), NoItinerary,
4173 [(set GPR:$dst, (atomic_load_add_32 GPR:$ptr, GPR:$incr))]>;
4174 def ATOMIC_LOAD_SUB_I32 : PseudoInst<
4175 (outs GPR:$dst), (ins GPR:$ptr, GPR:$incr), NoItinerary,
4176 [(set GPR:$dst, (atomic_load_sub_32 GPR:$ptr, GPR:$incr))]>;
4177 def ATOMIC_LOAD_AND_I32 : PseudoInst<
4178 (outs GPR:$dst), (ins GPR:$ptr, GPR:$incr), NoItinerary,
4179 [(set GPR:$dst, (atomic_load_and_32 GPR:$ptr, GPR:$incr))]>;
4180 def ATOMIC_LOAD_OR_I32 : PseudoInst<
4181 (outs GPR:$dst), (ins GPR:$ptr, GPR:$incr), NoItinerary,
4182 [(set GPR:$dst, (atomic_load_or_32 GPR:$ptr, GPR:$incr))]>;
4183 def ATOMIC_LOAD_XOR_I32 : PseudoInst<
4184 (outs GPR:$dst), (ins GPR:$ptr, GPR:$incr), NoItinerary,
4185 [(set GPR:$dst, (atomic_load_xor_32 GPR:$ptr, GPR:$incr))]>;
4186 def ATOMIC_LOAD_NAND_I32 : PseudoInst<
4187 (outs GPR:$dst), (ins GPR:$ptr, GPR:$incr), NoItinerary,
4188 [(set GPR:$dst, (atomic_load_nand_32 GPR:$ptr, GPR:$incr))]>;
4189 def ATOMIC_LOAD_MIN_I32 : PseudoInst<
4190 (outs GPR:$dst), (ins GPR:$ptr, GPR:$val), NoItinerary,
4191 [(set GPR:$dst, (atomic_load_min_32 GPR:$ptr, GPR:$val))]>;
4192 def ATOMIC_LOAD_MAX_I32 : PseudoInst<
4193 (outs GPR:$dst), (ins GPR:$ptr, GPR:$val), NoItinerary,
4194 [(set GPR:$dst, (atomic_load_max_32 GPR:$ptr, GPR:$val))]>;
4195 def ATOMIC_LOAD_UMIN_I32 : PseudoInst<
4196 (outs GPR:$dst), (ins GPR:$ptr, GPR:$val), NoItinerary,
4197 [(set GPR:$dst, (atomic_load_min_32 GPR:$ptr, GPR:$val))]>;
4198 def ATOMIC_LOAD_UMAX_I32 : PseudoInst<
4199 (outs GPR:$dst), (ins GPR:$ptr, GPR:$val), NoItinerary,
4200 [(set GPR:$dst, (atomic_load_max_32 GPR:$ptr, GPR:$val))]>;
4202 def ATOMIC_SWAP_I8 : PseudoInst<
4203 (outs GPR:$dst), (ins GPR:$ptr, GPR:$new), NoItinerary,
4204 [(set GPR:$dst, (atomic_swap_8 GPR:$ptr, GPR:$new))]>;
4205 def ATOMIC_SWAP_I16 : PseudoInst<
4206 (outs GPR:$dst), (ins GPR:$ptr, GPR:$new), NoItinerary,
4207 [(set GPR:$dst, (atomic_swap_16 GPR:$ptr, GPR:$new))]>;
4208 def ATOMIC_SWAP_I32 : PseudoInst<
4209 (outs GPR:$dst), (ins GPR:$ptr, GPR:$new), NoItinerary,
4210 [(set GPR:$dst, (atomic_swap_32 GPR:$ptr, GPR:$new))]>;
4212 def ATOMIC_CMP_SWAP_I8 : PseudoInst<
4213 (outs GPR:$dst), (ins GPR:$ptr, GPR:$old, GPR:$new), NoItinerary,
4214 [(set GPR:$dst, (atomic_cmp_swap_8 GPR:$ptr, GPR:$old, GPR:$new))]>;
4215 def ATOMIC_CMP_SWAP_I16 : PseudoInst<
4216 (outs GPR:$dst), (ins GPR:$ptr, GPR:$old, GPR:$new), NoItinerary,
4217 [(set GPR:$dst, (atomic_cmp_swap_16 GPR:$ptr, GPR:$old, GPR:$new))]>;
4218 def ATOMIC_CMP_SWAP_I32 : PseudoInst<
4219 (outs GPR:$dst), (ins GPR:$ptr, GPR:$old, GPR:$new), NoItinerary,
4220 [(set GPR:$dst, (atomic_cmp_swap_32 GPR:$ptr, GPR:$old, GPR:$new))]>;
4224 let mayLoad = 1 in {
4225 def LDREXB : AIldrex<0b10, (outs GPR:$Rt), (ins addr_offset_none:$addr),
4227 "ldrexb", "\t$Rt, $addr", []>;
4228 def LDREXH : AIldrex<0b11, (outs GPR:$Rt), (ins addr_offset_none:$addr),
4229 NoItinerary, "ldrexh", "\t$Rt, $addr", []>;
4230 def LDREX : AIldrex<0b00, (outs GPR:$Rt), (ins addr_offset_none:$addr),
4231 NoItinerary, "ldrex", "\t$Rt, $addr", []>;
4232 let hasExtraDefRegAllocReq = 1 in
4233 def LDREXD: AIldrex<0b01, (outs GPR:$Rt, GPR:$Rt2),(ins addr_offset_none:$addr),
4234 NoItinerary, "ldrexd", "\t$Rt, $Rt2, $addr", []> {
4235 let DecoderMethod = "DecodeDoubleRegLoad";
4239 let mayStore = 1, Constraints = "@earlyclobber $Rd" in {
4240 def STREXB: AIstrex<0b10, (outs GPR:$Rd), (ins GPR:$Rt, addr_offset_none:$addr),
4241 NoItinerary, "strexb", "\t$Rd, $Rt, $addr", []>;
4242 def STREXH: AIstrex<0b11, (outs GPR:$Rd), (ins GPR:$Rt, addr_offset_none:$addr),
4243 NoItinerary, "strexh", "\t$Rd, $Rt, $addr", []>;
4244 def STREX : AIstrex<0b00, (outs GPR:$Rd), (ins GPR:$Rt, addr_offset_none:$addr),
4245 NoItinerary, "strex", "\t$Rd, $Rt, $addr", []>;
4248 let hasExtraSrcRegAllocReq = 1, Constraints = "@earlyclobber $Rd" in
4249 def STREXD : AIstrex<0b01, (outs GPR:$Rd),
4250 (ins GPR:$Rt, GPR:$Rt2, addr_offset_none:$addr),
4251 NoItinerary, "strexd", "\t$Rd, $Rt, $Rt2, $addr", []> {
4252 let DecoderMethod = "DecodeDoubleRegStore";
4255 def CLREX : AXI<(outs), (ins), MiscFrm, NoItinerary, "clrex", []>,
4256 Requires<[IsARM, HasV7]> {
4257 let Inst{31-0} = 0b11110101011111111111000000011111;
4260 // SWP/SWPB are deprecated in V6/V7.
4261 let mayLoad = 1, mayStore = 1 in {
4262 def SWP : AIswp<0, (outs GPR:$Rt), (ins GPR:$Rt2, addr_offset_none:$addr),
4264 def SWPB: AIswp<1, (outs GPR:$Rt), (ins GPR:$Rt2, addr_offset_none:$addr),
4268 //===----------------------------------------------------------------------===//
4269 // Coprocessor Instructions.
4272 def CDP : ABI<0b1110, (outs), (ins p_imm:$cop, imm0_15:$opc1,
4273 c_imm:$CRd, c_imm:$CRn, c_imm:$CRm, imm0_7:$opc2),
4274 NoItinerary, "cdp", "\t$cop, $opc1, $CRd, $CRn, $CRm, $opc2",
4275 [(int_arm_cdp imm:$cop, imm:$opc1, imm:$CRd, imm:$CRn,
4276 imm:$CRm, imm:$opc2)]> {
4284 let Inst{3-0} = CRm;
4286 let Inst{7-5} = opc2;
4287 let Inst{11-8} = cop;
4288 let Inst{15-12} = CRd;
4289 let Inst{19-16} = CRn;
4290 let Inst{23-20} = opc1;
4293 def CDP2 : ABXI<0b1110, (outs), (ins p_imm:$cop, imm0_15:$opc1,
4294 c_imm:$CRd, c_imm:$CRn, c_imm:$CRm, imm0_7:$opc2),
4295 NoItinerary, "cdp2\t$cop, $opc1, $CRd, $CRn, $CRm, $opc2",
4296 [(int_arm_cdp2 imm:$cop, imm:$opc1, imm:$CRd, imm:$CRn,
4297 imm:$CRm, imm:$opc2)]> {
4298 let Inst{31-28} = 0b1111;
4306 let Inst{3-0} = CRm;
4308 let Inst{7-5} = opc2;
4309 let Inst{11-8} = cop;
4310 let Inst{15-12} = CRd;
4311 let Inst{19-16} = CRn;
4312 let Inst{23-20} = opc1;
4315 class ACI<dag oops, dag iops, string opc, string asm,
4316 IndexMode im = IndexModeNone>
4317 : InoP<oops, iops, AddrModeNone, 4, im, BrFrm, NoItinerary,
4319 let Inst{27-25} = 0b110;
4322 multiclass LdStCop<bits<4> op31_28, bit load, dag ops, string opc, string cond>{
4323 def _OFFSET : ACI<(outs),
4324 !con((ins nohash_imm:$cop, nohash_imm:$CRd, addrmode2:$addr), ops),
4325 !strconcat(opc, cond), "\tp$cop, cr$CRd, $addr"> {
4326 let Inst{31-28} = op31_28;
4327 let Inst{24} = 1; // P = 1
4328 let Inst{21} = 0; // W = 0
4329 let Inst{22} = 0; // D = 0
4330 let Inst{20} = load;
4331 let DecoderMethod = "DecodeCopMemInstruction";
4334 def _PRE : ACI<(outs),
4335 !con((ins nohash_imm:$cop, nohash_imm:$CRd, addrmode2:$addr), ops),
4336 !strconcat(opc, cond), "\tp$cop, cr$CRd, $addr!", IndexModePre> {
4337 let Inst{31-28} = op31_28;
4338 let Inst{24} = 1; // P = 1
4339 let Inst{21} = 1; // W = 1
4340 let Inst{22} = 0; // D = 0
4341 let Inst{20} = load;
4342 let DecoderMethod = "DecodeCopMemInstruction";
4345 def _POST : ACI<(outs),
4346 !con((ins nohash_imm:$cop, nohash_imm:$CRd, addrmode2:$addr), ops),
4347 !strconcat(opc, cond), "\tp$cop, cr$CRd, $addr", IndexModePost> {
4348 let Inst{31-28} = op31_28;
4349 let Inst{24} = 0; // P = 0
4350 let Inst{21} = 1; // W = 1
4351 let Inst{22} = 0; // D = 0
4352 let Inst{20} = load;
4353 let DecoderMethod = "DecodeCopMemInstruction";
4356 def _OPTION : ACI<(outs),
4357 !con((ins nohash_imm:$cop,nohash_imm:$CRd,GPR:$base, nohash_imm:$option),
4359 !strconcat(opc, cond), "\tp$cop, cr$CRd, [$base], \\{$option\\}"> {
4360 let Inst{31-28} = op31_28;
4361 let Inst{24} = 0; // P = 0
4362 let Inst{23} = 1; // U = 1
4363 let Inst{21} = 0; // W = 0
4364 let Inst{22} = 0; // D = 0
4365 let Inst{20} = load;
4366 let DecoderMethod = "DecodeCopMemInstruction";
4369 def L_OFFSET : ACI<(outs),
4370 !con((ins nohash_imm:$cop, nohash_imm:$CRd, addrmode2:$addr), ops),
4371 !strconcat(!strconcat(opc, "l"), cond), "\tp$cop, cr$CRd, $addr"> {
4372 let Inst{31-28} = op31_28;
4373 let Inst{24} = 1; // P = 1
4374 let Inst{21} = 0; // W = 0
4375 let Inst{22} = 1; // D = 1
4376 let Inst{20} = load;
4377 let DecoderMethod = "DecodeCopMemInstruction";
4380 def L_PRE : ACI<(outs),
4381 !con((ins nohash_imm:$cop, nohash_imm:$CRd, addrmode2:$addr), ops),
4382 !strconcat(!strconcat(opc, "l"), cond), "\tp$cop, cr$CRd, $addr!",
4384 let Inst{31-28} = op31_28;
4385 let Inst{24} = 1; // P = 1
4386 let Inst{21} = 1; // W = 1
4387 let Inst{22} = 1; // D = 1
4388 let Inst{20} = load;
4389 let DecoderMethod = "DecodeCopMemInstruction";
4392 def L_POST : ACI<(outs),
4393 !con((ins nohash_imm:$cop, nohash_imm:$CRd, addr_offset_none:$addr,
4394 postidx_imm8s4:$offset), ops),
4395 !strconcat(!strconcat(opc, "l"), cond), "\tp$cop, cr$CRd, $addr, $offset",
4397 let Inst{31-28} = op31_28;
4398 let Inst{24} = 0; // P = 0
4399 let Inst{21} = 1; // W = 1
4400 let Inst{22} = 1; // D = 1
4401 let Inst{20} = load;
4402 let DecoderMethod = "DecodeCopMemInstruction";
4405 def L_OPTION : ACI<(outs),
4406 !con((ins nohash_imm:$cop, nohash_imm:$CRd,GPR:$base,nohash_imm:$option),
4408 !strconcat(!strconcat(opc, "l"), cond),
4409 "\tp$cop, cr$CRd, [$base], \\{$option\\}"> {
4410 let Inst{31-28} = op31_28;
4411 let Inst{24} = 0; // P = 0
4412 let Inst{23} = 1; // U = 1
4413 let Inst{21} = 0; // W = 0
4414 let Inst{22} = 1; // D = 1
4415 let Inst{20} = load;
4416 let DecoderMethod = "DecodeCopMemInstruction";
4420 defm LDC : LdStCop<{?,?,?,?}, 1, (ins pred:$p), "ldc", "${p}">;
4421 defm LDC2 : LdStCop<0b1111, 1, (ins), "ldc2", "">;
4422 defm STC : LdStCop<{?,?,?,?}, 0, (ins pred:$p), "stc", "${p}">;
4423 defm STC2 : LdStCop<0b1111, 0, (ins), "stc2", "">;
4425 //===----------------------------------------------------------------------===//
4426 // Move between coprocessor and ARM core register.
4429 class MovRCopro<string opc, bit direction, dag oops, dag iops,
4431 : ABI<0b1110, oops, iops, NoItinerary, opc,
4432 "\t$cop, $opc1, $Rt, $CRn, $CRm, $opc2", pattern> {
4433 let Inst{20} = direction;
4443 let Inst{15-12} = Rt;
4444 let Inst{11-8} = cop;
4445 let Inst{23-21} = opc1;
4446 let Inst{7-5} = opc2;
4447 let Inst{3-0} = CRm;
4448 let Inst{19-16} = CRn;
4451 def MCR : MovRCopro<"mcr", 0 /* from ARM core register to coprocessor */,
4453 (ins p_imm:$cop, imm0_7:$opc1, GPR:$Rt, c_imm:$CRn,
4454 c_imm:$CRm, imm0_7:$opc2),
4455 [(int_arm_mcr imm:$cop, imm:$opc1, GPR:$Rt, imm:$CRn,
4456 imm:$CRm, imm:$opc2)]>;
4457 def MRC : MovRCopro<"mrc", 1 /* from coprocessor to ARM core register */,
4459 (ins p_imm:$cop, imm0_7:$opc1, c_imm:$CRn, c_imm:$CRm,
4462 def : ARMPat<(int_arm_mrc imm:$cop, imm:$opc1, imm:$CRn, imm:$CRm, imm:$opc2),
4463 (MRC imm:$cop, imm:$opc1, imm:$CRn, imm:$CRm, imm:$opc2)>;
4465 class MovRCopro2<string opc, bit direction, dag oops, dag iops,
4467 : ABXI<0b1110, oops, iops, NoItinerary,
4468 !strconcat(opc, "\t$cop, $opc1, $Rt, $CRn, $CRm, $opc2"), pattern> {
4469 let Inst{31-28} = 0b1111;
4470 let Inst{20} = direction;
4480 let Inst{15-12} = Rt;
4481 let Inst{11-8} = cop;
4482 let Inst{23-21} = opc1;
4483 let Inst{7-5} = opc2;
4484 let Inst{3-0} = CRm;
4485 let Inst{19-16} = CRn;
4488 def MCR2 : MovRCopro2<"mcr2", 0 /* from ARM core register to coprocessor */,
4490 (ins p_imm:$cop, imm0_7:$opc1, GPR:$Rt, c_imm:$CRn,
4491 c_imm:$CRm, imm0_7:$opc2),
4492 [(int_arm_mcr2 imm:$cop, imm:$opc1, GPR:$Rt, imm:$CRn,
4493 imm:$CRm, imm:$opc2)]>;
4494 def MRC2 : MovRCopro2<"mrc2", 1 /* from coprocessor to ARM core register */,
4496 (ins p_imm:$cop, imm0_7:$opc1, c_imm:$CRn, c_imm:$CRm,
4499 def : ARMV5TPat<(int_arm_mrc2 imm:$cop, imm:$opc1, imm:$CRn,
4500 imm:$CRm, imm:$opc2),
4501 (MRC2 imm:$cop, imm:$opc1, imm:$CRn, imm:$CRm, imm:$opc2)>;
4503 class MovRRCopro<string opc, bit direction, list<dag> pattern = []>
4504 : ABI<0b1100, (outs), (ins p_imm:$cop, imm0_15:$opc1,
4505 GPR:$Rt, GPR:$Rt2, c_imm:$CRm),
4506 NoItinerary, opc, "\t$cop, $opc1, $Rt, $Rt2, $CRm", pattern> {
4507 let Inst{23-21} = 0b010;
4508 let Inst{20} = direction;
4516 let Inst{15-12} = Rt;
4517 let Inst{19-16} = Rt2;
4518 let Inst{11-8} = cop;
4519 let Inst{7-4} = opc1;
4520 let Inst{3-0} = CRm;
4523 def MCRR : MovRRCopro<"mcrr", 0 /* from ARM core register to coprocessor */,
4524 [(int_arm_mcrr imm:$cop, imm:$opc1, GPR:$Rt, GPR:$Rt2,
4526 def MRRC : MovRRCopro<"mrrc", 1 /* from coprocessor to ARM core register */>;
4528 class MovRRCopro2<string opc, bit direction, list<dag> pattern = []>
4529 : ABXI<0b1100, (outs), (ins p_imm:$cop, imm0_15:$opc1,
4530 GPR:$Rt, GPR:$Rt2, c_imm:$CRm), NoItinerary,
4531 !strconcat(opc, "\t$cop, $opc1, $Rt, $Rt2, $CRm"), pattern> {
4532 let Inst{31-28} = 0b1111;
4533 let Inst{23-21} = 0b010;
4534 let Inst{20} = direction;
4542 let Inst{15-12} = Rt;
4543 let Inst{19-16} = Rt2;
4544 let Inst{11-8} = cop;
4545 let Inst{7-4} = opc1;
4546 let Inst{3-0} = CRm;
4549 def MCRR2 : MovRRCopro2<"mcrr2", 0 /* from ARM core register to coprocessor */,
4550 [(int_arm_mcrr2 imm:$cop, imm:$opc1, GPR:$Rt, GPR:$Rt2,
4552 def MRRC2 : MovRRCopro2<"mrrc2", 1 /* from coprocessor to ARM core register */>;
4554 //===----------------------------------------------------------------------===//
4555 // Move between special register and ARM core register
4558 // Move to ARM core register from Special Register
4559 def MRS : ABI<0b0001, (outs GPR:$Rd), (ins), NoItinerary,
4560 "mrs", "\t$Rd, apsr", []> {
4562 let Inst{23-16} = 0b00001111;
4563 let Inst{15-12} = Rd;
4564 let Inst{7-4} = 0b0000;
4567 def : InstAlias<"mrs${p} $Rd, cpsr", (MRS GPR:$Rd, pred:$p)>, Requires<[IsARM]>;
4569 def MRSsys : ABI<0b0001, (outs GPR:$Rd), (ins), NoItinerary,
4570 "mrs", "\t$Rd, spsr", []> {
4572 let Inst{23-16} = 0b01001111;
4573 let Inst{15-12} = Rd;
4574 let Inst{7-4} = 0b0000;
4577 // Move from ARM core register to Special Register
4579 // No need to have both system and application versions, the encodings are the
4580 // same and the assembly parser has no way to distinguish between them. The mask
4581 // operand contains the special register (R Bit) in bit 4 and bits 3-0 contains
4582 // the mask with the fields to be accessed in the special register.
4583 def MSR : ABI<0b0001, (outs), (ins msr_mask:$mask, GPR:$Rn), NoItinerary,
4584 "msr", "\t$mask, $Rn", []> {
4589 let Inst{22} = mask{4}; // R bit
4590 let Inst{21-20} = 0b10;
4591 let Inst{19-16} = mask{3-0};
4592 let Inst{15-12} = 0b1111;
4593 let Inst{11-4} = 0b00000000;
4597 def MSRi : ABI<0b0011, (outs), (ins msr_mask:$mask, so_imm:$a), NoItinerary,
4598 "msr", "\t$mask, $a", []> {
4603 let Inst{22} = mask{4}; // R bit
4604 let Inst{21-20} = 0b10;
4605 let Inst{19-16} = mask{3-0};
4606 let Inst{15-12} = 0b1111;
4610 //===----------------------------------------------------------------------===//
4614 // __aeabi_read_tp preserves the registers r1-r3.
4615 // This is a pseudo inst so that we can get the encoding right,
4616 // complete with fixup for the aeabi_read_tp function.
4618 Defs = [R0, R12, LR, CPSR], Uses = [SP] in {
4619 def TPsoft : PseudoInst<(outs), (ins), IIC_Br,
4620 [(set R0, ARMthread_pointer)]>;
4623 //===----------------------------------------------------------------------===//
4624 // SJLJ Exception handling intrinsics
4625 // eh_sjlj_setjmp() is an instruction sequence to store the return
4626 // address and save #0 in R0 for the non-longjmp case.
4627 // Since by its nature we may be coming from some other function to get
4628 // here, and we're using the stack frame for the containing function to
4629 // save/restore registers, we can't keep anything live in regs across
4630 // the eh_sjlj_setjmp(), else it will almost certainly have been tromped upon
4631 // when we get here from a longjmp(). We force everything out of registers
4632 // except for our own input by listing the relevant registers in Defs. By
4633 // doing so, we also cause the prologue/epilogue code to actively preserve
4634 // all of the callee-saved resgisters, which is exactly what we want.
4635 // A constant value is passed in $val, and we use the location as a scratch.
4637 // These are pseudo-instructions and are lowered to individual MC-insts, so
4638 // no encoding information is necessary.
4640 [ R0, R1, R2, R3, R4, R5, R6, R7, R8, R9, R10, R11, R12, LR, CPSR,
4641 QQQQ0, QQQQ1, QQQQ2, QQQQ3 ], hasSideEffects = 1, isBarrier = 1 in {
4642 def Int_eh_sjlj_setjmp : PseudoInst<(outs), (ins GPR:$src, GPR:$val),
4644 [(set R0, (ARMeh_sjlj_setjmp GPR:$src, GPR:$val))]>,
4645 Requires<[IsARM, HasVFP2]>;
4649 [ R0, R1, R2, R3, R4, R5, R6, R7, R8, R9, R10, R11, R12, LR, CPSR ],
4650 hasSideEffects = 1, isBarrier = 1 in {
4651 def Int_eh_sjlj_setjmp_nofp : PseudoInst<(outs), (ins GPR:$src, GPR:$val),
4653 [(set R0, (ARMeh_sjlj_setjmp GPR:$src, GPR:$val))]>,
4654 Requires<[IsARM, NoVFP]>;
4657 // FIXME: Non-Darwin version(s)
4658 let isBarrier = 1, hasSideEffects = 1, isTerminator = 1,
4659 Defs = [ R7, LR, SP ] in {
4660 def Int_eh_sjlj_longjmp : PseudoInst<(outs), (ins GPR:$src, GPR:$scratch),
4662 [(ARMeh_sjlj_longjmp GPR:$src, GPR:$scratch)]>,
4663 Requires<[IsARM, IsDarwin]>;
4666 // eh.sjlj.dispatchsetup pseudo-instruction.
4667 // This pseudo is used for ARM, Thumb1 and Thumb2. Any differences are
4668 // handled when the pseudo is expanded (which happens before any passes
4669 // that need the instruction size).
4670 let isBarrier = 1, hasSideEffects = 1 in
4671 def Int_eh_sjlj_dispatchsetup :
4672 PseudoInst<(outs), (ins GPR:$src), NoItinerary,
4673 [(ARMeh_sjlj_dispatchsetup GPR:$src)]>,
4674 Requires<[IsDarwin]>;
4676 //===----------------------------------------------------------------------===//
4677 // Non-Instruction Patterns
4680 // ARMv4 indirect branch using (MOVr PC, dst)
4681 let isBranch = 1, isTerminator = 1, isBarrier = 1, isIndirectBranch = 1 in
4682 def MOVPCRX : ARMPseudoExpand<(outs), (ins GPR:$dst),
4683 4, IIC_Br, [(brind GPR:$dst)],
4684 (MOVr PC, GPR:$dst, (ops 14, zero_reg), zero_reg)>,
4685 Requires<[IsARM, NoV4T]>;
4687 // Large immediate handling.
4689 // 32-bit immediate using two piece so_imms or movw + movt.
4690 // This is a single pseudo instruction, the benefit is that it can be remat'd
4691 // as a single unit instead of having to handle reg inputs.
4692 // FIXME: Remove this when we can do generalized remat.
4693 let isReMaterializable = 1, isMoveImm = 1 in
4694 def MOVi32imm : PseudoInst<(outs GPR:$dst), (ins i32imm:$src), IIC_iMOVix2,
4695 [(set GPR:$dst, (arm_i32imm:$src))]>,
4698 // Pseudo instruction that combines movw + movt + add pc (if PIC).
4699 // It also makes it possible to rematerialize the instructions.
4700 // FIXME: Remove this when we can do generalized remat and when machine licm
4701 // can properly the instructions.
4702 let isReMaterializable = 1 in {
4703 def MOV_ga_pcrel : PseudoInst<(outs GPR:$dst), (ins i32imm:$addr),
4705 [(set GPR:$dst, (ARMWrapperPIC tglobaladdr:$addr))]>,
4706 Requires<[IsARM, UseMovt]>;
4708 def MOV_ga_dyn : PseudoInst<(outs GPR:$dst), (ins i32imm:$addr),
4710 [(set GPR:$dst, (ARMWrapperDYN tglobaladdr:$addr))]>,
4711 Requires<[IsARM, UseMovt]>;
4713 let AddedComplexity = 10 in
4714 def MOV_ga_pcrel_ldr : PseudoInst<(outs GPR:$dst), (ins i32imm:$addr),
4716 [(set GPR:$dst, (load (ARMWrapperPIC tglobaladdr:$addr)))]>,
4717 Requires<[IsARM, UseMovt]>;
4718 } // isReMaterializable
4720 // ConstantPool, GlobalAddress, and JumpTable
4721 def : ARMPat<(ARMWrapper tglobaladdr :$dst), (LEApcrel tglobaladdr :$dst)>,
4722 Requires<[IsARM, DontUseMovt]>;
4723 def : ARMPat<(ARMWrapper tconstpool :$dst), (LEApcrel tconstpool :$dst)>;
4724 def : ARMPat<(ARMWrapper tglobaladdr :$dst), (MOVi32imm tglobaladdr :$dst)>,
4725 Requires<[IsARM, UseMovt]>;
4726 def : ARMPat<(ARMWrapperJT tjumptable:$dst, imm:$id),
4727 (LEApcrelJT tjumptable:$dst, imm:$id)>;
4729 // TODO: add,sub,and, 3-instr forms?
4732 def : ARMPat<(ARMtcret tcGPR:$dst),
4733 (TCRETURNri tcGPR:$dst)>, Requires<[IsDarwin]>;
4735 def : ARMPat<(ARMtcret (i32 tglobaladdr:$dst)),
4736 (TCRETURNdi texternalsym:$dst)>, Requires<[IsDarwin]>;
4738 def : ARMPat<(ARMtcret (i32 texternalsym:$dst)),
4739 (TCRETURNdi texternalsym:$dst)>, Requires<[IsDarwin]>;
4741 def : ARMPat<(ARMtcret tcGPR:$dst),
4742 (TCRETURNriND tcGPR:$dst)>, Requires<[IsNotDarwin]>;
4744 def : ARMPat<(ARMtcret (i32 tglobaladdr:$dst)),
4745 (TCRETURNdiND texternalsym:$dst)>, Requires<[IsNotDarwin]>;
4747 def : ARMPat<(ARMtcret (i32 texternalsym:$dst)),
4748 (TCRETURNdiND texternalsym:$dst)>, Requires<[IsNotDarwin]>;
4751 def : ARMPat<(ARMcall texternalsym:$func), (BL texternalsym:$func)>,
4752 Requires<[IsARM, IsNotDarwin]>;
4753 def : ARMPat<(ARMcall texternalsym:$func), (BLr9 texternalsym:$func)>,
4754 Requires<[IsARM, IsDarwin]>;
4756 // zextload i1 -> zextload i8
4757 def : ARMPat<(zextloadi1 addrmode_imm12:$addr), (LDRBi12 addrmode_imm12:$addr)>;
4758 def : ARMPat<(zextloadi1 ldst_so_reg:$addr), (LDRBrs ldst_so_reg:$addr)>;
4760 // extload -> zextload
4761 def : ARMPat<(extloadi1 addrmode_imm12:$addr), (LDRBi12 addrmode_imm12:$addr)>;
4762 def : ARMPat<(extloadi1 ldst_so_reg:$addr), (LDRBrs ldst_so_reg:$addr)>;
4763 def : ARMPat<(extloadi8 addrmode_imm12:$addr), (LDRBi12 addrmode_imm12:$addr)>;
4764 def : ARMPat<(extloadi8 ldst_so_reg:$addr), (LDRBrs ldst_so_reg:$addr)>;
4766 def : ARMPat<(extloadi16 addrmode3:$addr), (LDRH addrmode3:$addr)>;
4768 def : ARMPat<(extloadi8 addrmodepc:$addr), (PICLDRB addrmodepc:$addr)>;
4769 def : ARMPat<(extloadi16 addrmodepc:$addr), (PICLDRH addrmodepc:$addr)>;
4772 def : ARMV5TEPat<(mul (sra (shl GPR:$a, (i32 16)), (i32 16)),
4773 (sra (shl GPR:$b, (i32 16)), (i32 16))),
4774 (SMULBB GPR:$a, GPR:$b)>;
4775 def : ARMV5TEPat<(mul sext_16_node:$a, sext_16_node:$b),
4776 (SMULBB GPR:$a, GPR:$b)>;
4777 def : ARMV5TEPat<(mul (sra (shl GPR:$a, (i32 16)), (i32 16)),
4778 (sra GPR:$b, (i32 16))),
4779 (SMULBT GPR:$a, GPR:$b)>;
4780 def : ARMV5TEPat<(mul sext_16_node:$a, (sra GPR:$b, (i32 16))),
4781 (SMULBT GPR:$a, GPR:$b)>;
4782 def : ARMV5TEPat<(mul (sra GPR:$a, (i32 16)),
4783 (sra (shl GPR:$b, (i32 16)), (i32 16))),
4784 (SMULTB GPR:$a, GPR:$b)>;
4785 def : ARMV5TEPat<(mul (sra GPR:$a, (i32 16)), sext_16_node:$b),
4786 (SMULTB GPR:$a, GPR:$b)>;
4787 def : ARMV5TEPat<(sra (mul GPR:$a, (sra (shl GPR:$b, (i32 16)), (i32 16))),
4789 (SMULWB GPR:$a, GPR:$b)>;
4790 def : ARMV5TEPat<(sra (mul GPR:$a, sext_16_node:$b), (i32 16)),
4791 (SMULWB GPR:$a, GPR:$b)>;
4793 def : ARMV5TEPat<(add GPR:$acc,
4794 (mul (sra (shl GPR:$a, (i32 16)), (i32 16)),
4795 (sra (shl GPR:$b, (i32 16)), (i32 16)))),
4796 (SMLABB GPR:$a, GPR:$b, GPR:$acc)>;
4797 def : ARMV5TEPat<(add GPR:$acc,
4798 (mul sext_16_node:$a, sext_16_node:$b)),
4799 (SMLABB GPR:$a, GPR:$b, GPR:$acc)>;
4800 def : ARMV5TEPat<(add GPR:$acc,
4801 (mul (sra (shl GPR:$a, (i32 16)), (i32 16)),
4802 (sra GPR:$b, (i32 16)))),
4803 (SMLABT GPR:$a, GPR:$b, GPR:$acc)>;
4804 def : ARMV5TEPat<(add GPR:$acc,
4805 (mul sext_16_node:$a, (sra GPR:$b, (i32 16)))),
4806 (SMLABT GPR:$a, GPR:$b, GPR:$acc)>;
4807 def : ARMV5TEPat<(add GPR:$acc,
4808 (mul (sra GPR:$a, (i32 16)),
4809 (sra (shl GPR:$b, (i32 16)), (i32 16)))),
4810 (SMLATB GPR:$a, GPR:$b, GPR:$acc)>;
4811 def : ARMV5TEPat<(add GPR:$acc,
4812 (mul (sra GPR:$a, (i32 16)), sext_16_node:$b)),
4813 (SMLATB GPR:$a, GPR:$b, GPR:$acc)>;
4814 def : ARMV5TEPat<(add GPR:$acc,
4815 (sra (mul GPR:$a, (sra (shl GPR:$b, (i32 16)), (i32 16))),
4817 (SMLAWB GPR:$a, GPR:$b, GPR:$acc)>;
4818 def : ARMV5TEPat<(add GPR:$acc,
4819 (sra (mul GPR:$a, sext_16_node:$b), (i32 16))),
4820 (SMLAWB GPR:$a, GPR:$b, GPR:$acc)>;
4823 // Pre-v7 uses MCR for synchronization barriers.
4824 def : ARMPat<(ARMMemBarrierMCR GPR:$zero), (MCR 15, 0, GPR:$zero, 7, 10, 5)>,
4825 Requires<[IsARM, HasV6]>;
4827 // SXT/UXT with no rotate
4828 let AddedComplexity = 16 in {
4829 def : ARMV6Pat<(and GPR:$Src, 0x000000FF), (UXTB GPR:$Src, 0)>;
4830 def : ARMV6Pat<(and GPR:$Src, 0x0000FFFF), (UXTH GPR:$Src, 0)>;
4831 def : ARMV6Pat<(and GPR:$Src, 0x00FF00FF), (UXTB16 GPR:$Src, 0)>;
4832 def : ARMV6Pat<(add GPR:$Rn, (and GPR:$Rm, 0x00FF)),
4833 (UXTAB GPR:$Rn, GPR:$Rm, 0)>;
4834 def : ARMV6Pat<(add GPR:$Rn, (and GPR:$Rm, 0xFFFF)),
4835 (UXTAH GPR:$Rn, GPR:$Rm, 0)>;
4838 def : ARMV6Pat<(sext_inreg GPR:$Src, i8), (SXTB GPR:$Src, 0)>;
4839 def : ARMV6Pat<(sext_inreg GPR:$Src, i16), (SXTH GPR:$Src, 0)>;
4841 def : ARMV6Pat<(add GPR:$Rn, (sext_inreg GPRnopc:$Rm, i8)),
4842 (SXTAB GPR:$Rn, GPRnopc:$Rm, 0)>;
4843 def : ARMV6Pat<(add GPR:$Rn, (sext_inreg GPRnopc:$Rm, i16)),
4844 (SXTAH GPR:$Rn, GPRnopc:$Rm, 0)>;
4846 // Atomic load/store patterns
4847 def : ARMPat<(atomic_load_8 ldst_so_reg:$src),
4848 (LDRBrs ldst_so_reg:$src)>;
4849 def : ARMPat<(atomic_load_8 addrmode_imm12:$src),
4850 (LDRBi12 addrmode_imm12:$src)>;
4851 def : ARMPat<(atomic_load_16 addrmode3:$src),
4852 (LDRH addrmode3:$src)>;
4853 def : ARMPat<(atomic_load_32 ldst_so_reg:$src),
4854 (LDRrs ldst_so_reg:$src)>;
4855 def : ARMPat<(atomic_load_32 addrmode_imm12:$src),
4856 (LDRi12 addrmode_imm12:$src)>;
4857 def : ARMPat<(atomic_store_8 ldst_so_reg:$ptr, GPR:$val),
4858 (STRBrs GPR:$val, ldst_so_reg:$ptr)>;
4859 def : ARMPat<(atomic_store_8 addrmode_imm12:$ptr, GPR:$val),
4860 (STRBi12 GPR:$val, addrmode_imm12:$ptr)>;
4861 def : ARMPat<(atomic_store_16 addrmode3:$ptr, GPR:$val),
4862 (STRH GPR:$val, addrmode3:$ptr)>;
4863 def : ARMPat<(atomic_store_32 ldst_so_reg:$ptr, GPR:$val),
4864 (STRrs GPR:$val, ldst_so_reg:$ptr)>;
4865 def : ARMPat<(atomic_store_32 addrmode_imm12:$ptr, GPR:$val),
4866 (STRi12 GPR:$val, addrmode_imm12:$ptr)>;
4869 //===----------------------------------------------------------------------===//
4873 include "ARMInstrThumb.td"
4875 //===----------------------------------------------------------------------===//
4879 include "ARMInstrThumb2.td"
4881 //===----------------------------------------------------------------------===//
4882 // Floating Point Support
4885 include "ARMInstrVFP.td"
4887 //===----------------------------------------------------------------------===//
4888 // Advanced SIMD (NEON) Support
4891 include "ARMInstrNEON.td"
4893 //===----------------------------------------------------------------------===//
4894 // Assembler aliases
4898 def : InstAlias<"dmb", (DMB 0xf)>, Requires<[IsARM, HasDB]>;
4899 def : InstAlias<"dsb", (DSB 0xf)>, Requires<[IsARM, HasDB]>;
4900 def : InstAlias<"isb", (ISB 0xf)>, Requires<[IsARM, HasDB]>;
4902 // System instructions
4903 def : MnemonicAlias<"swi", "svc">;
4905 // Load / Store Multiple
4906 def : MnemonicAlias<"ldmfd", "ldm">;
4907 def : MnemonicAlias<"ldmia", "ldm">;
4908 def : MnemonicAlias<"ldmea", "ldmdb">;
4909 def : MnemonicAlias<"stmfd", "stmdb">;
4910 def : MnemonicAlias<"stmia", "stm">;
4911 def : MnemonicAlias<"stmea", "stm">;
4913 // PKHBT/PKHTB with default shift amount. PKHTB is equivalent to PKHBT when the
4914 // shift amount is zero (i.e., unspecified).
4915 def : InstAlias<"pkhbt${p} $Rd, $Rn, $Rm",
4916 (PKHBT GPR:$Rd, GPR:$Rn, GPR:$Rm, 0, pred:$p)>,
4917 Requires<[IsARM, HasV6]>;
4918 def : InstAlias<"pkhtb${p} $Rd, $Rn, $Rm",
4919 (PKHBT GPR:$Rd, GPR:$Rn, GPR:$Rm, 0, pred:$p)>,
4920 Requires<[IsARM, HasV6]>;
4922 // PUSH/POP aliases for STM/LDM
4923 def : ARMInstAlias<"push${p} $regs", (STMDB_UPD SP, pred:$p, reglist:$regs)>;
4924 def : ARMInstAlias<"pop${p} $regs", (LDMIA_UPD SP, pred:$p, reglist:$regs)>;
4926 // SSAT/USAT optional shift operand.
4927 def : ARMInstAlias<"ssat${p} $Rd, $sat_imm, $Rn",
4928 (SSAT GPRnopc:$Rd, imm1_32:$sat_imm, GPRnopc:$Rn, 0, pred:$p)>;
4929 def : ARMInstAlias<"usat${p} $Rd, $sat_imm, $Rn",
4930 (USAT GPRnopc:$Rd, imm0_31:$sat_imm, GPRnopc:$Rn, 0, pred:$p)>;
4933 // Extend instruction optional rotate operand.
4934 def : ARMInstAlias<"sxtab${p} $Rd, $Rn, $Rm",
4935 (SXTAB GPRnopc:$Rd, GPR:$Rn, GPRnopc:$Rm, 0, pred:$p)>;
4936 def : ARMInstAlias<"sxtah${p} $Rd, $Rn, $Rm",
4937 (SXTAH GPRnopc:$Rd, GPR:$Rn, GPRnopc:$Rm, 0, pred:$p)>;
4938 def : ARMInstAlias<"sxtab16${p} $Rd, $Rn, $Rm",
4939 (SXTAB16 GPRnopc:$Rd, GPR:$Rn, GPRnopc:$Rm, 0, pred:$p)>;
4940 def : ARMInstAlias<"sxtb${p} $Rd, $Rm",
4941 (SXTB GPRnopc:$Rd, GPRnopc:$Rm, 0, pred:$p)>;
4942 def : ARMInstAlias<"sxtb16${p} $Rd, $Rm",
4943 (SXTB16 GPRnopc:$Rd, GPRnopc:$Rm, 0, pred:$p)>;
4944 def : ARMInstAlias<"sxth${p} $Rd, $Rm",
4945 (SXTH GPRnopc:$Rd, GPRnopc:$Rm, 0, pred:$p)>;
4947 def : ARMInstAlias<"uxtab${p} $Rd, $Rn, $Rm",
4948 (UXTAB GPRnopc:$Rd, GPR:$Rn, GPRnopc:$Rm, 0, pred:$p)>;
4949 def : ARMInstAlias<"uxtah${p} $Rd, $Rn, $Rm",
4950 (UXTAH GPRnopc:$Rd, GPR:$Rn, GPRnopc:$Rm, 0, pred:$p)>;
4951 def : ARMInstAlias<"uxtab16${p} $Rd, $Rn, $Rm",
4952 (UXTAB16 GPRnopc:$Rd, GPR:$Rn, GPRnopc:$Rm, 0, pred:$p)>;
4953 def : ARMInstAlias<"uxtb${p} $Rd, $Rm",
4954 (UXTB GPRnopc:$Rd, GPRnopc:$Rm, 0, pred:$p)>;
4955 def : ARMInstAlias<"uxtb16${p} $Rd, $Rm",
4956 (UXTB16 GPRnopc:$Rd, GPRnopc:$Rm, 0, pred:$p)>;
4957 def : ARMInstAlias<"uxth${p} $Rd, $Rm",
4958 (UXTH GPRnopc:$Rd, GPRnopc:$Rm, 0, pred:$p)>;
4962 def : MnemonicAlias<"rfefa", "rfeda">;
4963 def : MnemonicAlias<"rfeea", "rfedb">;
4964 def : MnemonicAlias<"rfefd", "rfeia">;
4965 def : MnemonicAlias<"rfeed", "rfeib">;
4966 def : MnemonicAlias<"rfe", "rfeia">;
4969 def : MnemonicAlias<"srsfa", "srsda">;
4970 def : MnemonicAlias<"srsea", "srsdb">;
4971 def : MnemonicAlias<"srsfd", "srsia">;
4972 def : MnemonicAlias<"srsed", "srsib">;
4973 def : MnemonicAlias<"srs", "srsia">;
4975 // LDRSBT/LDRHT/LDRSHT post-index offset if optional.
4976 // Note that the write-back output register is a dummy operand for MC (it's
4977 // only meaningful for codegen), so we just pass zero here.
4978 // FIXME: tblgen not cooperating with argument conversions.
4979 //def : InstAlias<"ldrsbt${p} $Rt, $addr",
4980 // (LDRSBTi GPR:$Rt, GPR:$Rt, addr_offset_none:$addr, 0,pred:$p)>;
4981 //def : InstAlias<"ldrht${p} $Rt, $addr",
4982 // (LDRHTi GPR:$Rt, GPR:$Rt, addr_offset_none:$addr, 0, pred:$p)>;
4983 //def : InstAlias<"ldrsht${p} $Rt, $addr",
4984 // (LDRSHTi GPR:$Rt, GPR:$Rt, addr_offset_none:$addr, 0, pred:$p)>;