1 //===- ARMInstrInfo.td - Target Description for ARM Target ----------------===//
3 // The LLVM Compiler Infrastructure
5 // This file was developed by the "Instituto Nokia de Tecnologia" and
6 // is distributed under the University of Illinois Open Source
7 // License. See LICENSE.TXT for details.
9 //===----------------------------------------------------------------------===//
11 // This file describes the ARM instructions in TableGen format.
13 //===----------------------------------------------------------------------===//
16 def op_addr_mode1 : Operand<iPTR> {
17 let PrintMethod = "printAddrMode1";
18 let NumMIOperands = 3;
19 let MIOperandInfo = (ops ptr_rc, ptr_rc, i32imm);
22 def memri : Operand<iPTR> {
23 let PrintMethod = "printMemRegImm";
24 let NumMIOperands = 2;
25 let MIOperandInfo = (ops i32imm, ptr_rc);
28 // Define ARM specific addressing mode.
29 //Addressing Mode 1: data processing operands
30 def addr_mode1 : ComplexPattern<iPTR, 3, "SelectAddrMode1", [imm, sra, shl, srl],
33 //register plus/minus 12 bit offset
34 def iaddr : ComplexPattern<iPTR, 2, "SelectAddrRegImm", [frameindex], []>;
35 //register plus scaled register
36 //def raddr : ComplexPattern<iPTR, 2, "SelectAddrRegReg", [], []>;
38 //===----------------------------------------------------------------------===//
39 // Instruction Class Templates
40 //===----------------------------------------------------------------------===//
41 class InstARM<dag ops, string asmstr, list<dag> pattern> : Instruction {
42 let Namespace = "ARM";
44 dag OperandList = ops;
45 let AsmString = asmstr;
46 let Pattern = pattern;
49 class IntBinOp<string OpcStr, SDNode OpNode> :
50 InstARM<(ops IntRegs:$dst, IntRegs:$a, IntRegs:$b),
51 !strconcat(OpcStr, " $dst, $a, $b"),
52 [(set IntRegs:$dst, (OpNode IntRegs:$a, IntRegs:$b))]>;
54 class FPBinOp<string OpcStr, SDNode OpNode> :
55 InstARM<(ops FPRegs:$dst, FPRegs:$a, FPRegs:$b),
56 !strconcat(OpcStr, " $dst, $a, $b"),
57 [(set FPRegs:$dst, (OpNode FPRegs:$a, FPRegs:$b))]>;
59 class DFPBinOp<string OpcStr, SDNode OpNode> :
60 InstARM<(ops DFPRegs:$dst, DFPRegs:$a, DFPRegs:$b),
61 !strconcat(OpcStr, " $dst, $a, $b"),
62 [(set DFPRegs:$dst, (OpNode DFPRegs:$a, DFPRegs:$b))]>;
64 class Addr1BinOp<string OpcStr, SDNode OpNode> :
65 InstARM<(ops IntRegs:$dst, IntRegs:$a, op_addr_mode1:$b),
66 !strconcat(OpcStr, " $dst, $a, $b"),
67 [(set IntRegs:$dst, (OpNode IntRegs:$a, addr_mode1:$b))]>;
69 //===----------------------------------------------------------------------===//
71 //===----------------------------------------------------------------------===//
73 def brtarget : Operand<OtherVT>;
75 // Operand for printing out a condition code.
76 let PrintMethod = "printCCOperand" in
77 def CCOp : Operand<i32>;
79 def SDT_ARMCallSeq : SDTypeProfile<0, 1, [ SDTCisVT<0, i32> ]>;
80 def callseq_start : SDNode<"ISD::CALLSEQ_START", SDT_ARMCallSeq,
81 [SDNPHasChain, SDNPOutFlag]>;
82 def callseq_end : SDNode<"ISD::CALLSEQ_END", SDT_ARMCallSeq,
83 [SDNPHasChain, SDNPOutFlag]>;
85 def SDT_ARMcall : SDTypeProfile<0, -1, [SDTCisInt<0>]>;
86 def ARMcall : SDNode<"ARMISD::CALL", SDT_ARMcall,
87 [SDNPHasChain, SDNPOptInFlag, SDNPOutFlag]>;
88 def retflag : SDNode<"ARMISD::RET_FLAG", SDTRet,
89 [SDNPHasChain, SDNPOptInFlag]>;
91 def SDTarmselect : SDTypeProfile<1, 3, [SDTCisSameAs<0, 1>, SDTCisSameAs<0, 2>, SDTCisInt<0>, SDTCisVT<2, i32>]>;
92 def armselect : SDNode<"ARMISD::SELECT", SDTarmselect, [SDNPInFlag, SDNPOutFlag]>;
94 def SDTarmfmstat : SDTypeProfile<0, 0, []>;
95 def armfmstat : SDNode<"ARMISD::FMSTAT", SDTarmfmstat, [SDNPInFlag, SDNPOutFlag]>;
97 def SDTarmbr : SDTypeProfile<0, 2, [SDTCisVT<0, OtherVT>, SDTCisVT<1, i32>]>;
98 def armbr : SDNode<"ARMISD::BR", SDTarmbr, [SDNPHasChain, SDNPInFlag]>;
100 def SDTVoidBinOp : SDTypeProfile<0, 2, [SDTCisSameAs<0, 1>]>;
101 def armcmp : SDNode<"ARMISD::CMP", SDTVoidBinOp, [SDNPOutFlag]>;
103 def armfsitos : SDNode<"ARMISD::FSITOS", SDTUnaryOp>;
104 def armftosis : SDNode<"ARMISD::FTOSIS", SDTUnaryOp>;
105 def armfsitod : SDNode<"ARMISD::FSITOD", SDTUnaryOp>;
106 def armftosid : SDNode<"ARMISD::FTOSID", SDTUnaryOp>;
107 def armfuitos : SDNode<"ARMISD::FUITOS", SDTUnaryOp>;
108 def armftouis : SDNode<"ARMISD::FTOUIS", SDTUnaryOp>;
109 def armfuitod : SDNode<"ARMISD::FUITOD", SDTUnaryOp>;
110 def armftouid : SDNode<"ARMISD::FTOUID", SDTUnaryOp>;
112 def SDTarmfmrrd : SDTypeProfile<0, 3, [SDTCisInt<0>, SDTCisInt<1>, SDTCisFP<2>]>;
113 def armfmrrd : SDNode<"ARMISD::FMRRD", SDTarmfmrrd,
114 [SDNPHasChain, SDNPOptInFlag, SDNPOutFlag]>;
116 def SDTarmfmdrr : SDTypeProfile<1, 2, [SDTCisFP<0>, SDTCisInt<1>, SDTCisInt<2>]>;
117 def armfmdrr : SDNode<"ARMISD::FMDRR", SDTarmfmdrr, []>;
119 def ADJCALLSTACKUP : InstARM<(ops i32imm:$amt),
120 "!ADJCALLSTACKUP $amt",
121 [(callseq_end imm:$amt)]>, Imp<[R13],[R13]>;
123 def ADJCALLSTACKDOWN : InstARM<(ops i32imm:$amt),
124 "!ADJCALLSTACKDOWN $amt",
125 [(callseq_start imm:$amt)]>, Imp<[R13],[R13]>;
127 let isReturn = 1 in {
128 def bx: InstARM<(ops), "bx r14", [(retflag)]>;
131 let noResults = 1, Defs = [R0, R1, R2, R3, R14] in {
132 def bl: InstARM<(ops i32imm:$func, variable_ops), "bl $func", []>;
135 def ldr : InstARM<(ops IntRegs:$dst, memri:$addr),
137 [(set IntRegs:$dst, (load iaddr:$addr))]>;
139 def LDRB : InstARM<(ops IntRegs:$dst, IntRegs:$addr),
140 "ldrb $dst, [$addr]",
141 [(set IntRegs:$dst, (zextloadi8 IntRegs:$addr))]>;
143 def LDRSB : InstARM<(ops IntRegs:$dst, IntRegs:$addr),
144 "ldrsb $dst, [$addr]",
145 [(set IntRegs:$dst, (sextloadi8 IntRegs:$addr))]>;
147 def LDRH : InstARM<(ops IntRegs:$dst, IntRegs:$addr),
148 "ldrh $dst, [$addr]",
149 [(set IntRegs:$dst, (zextloadi16 IntRegs:$addr))]>;
151 def LDRSH : InstARM<(ops IntRegs:$dst, IntRegs:$addr),
152 "ldrsh $dst, [$addr]",
153 [(set IntRegs:$dst, (sextloadi16 IntRegs:$addr))]>;
155 def str : InstARM<(ops IntRegs:$src, memri:$addr),
157 [(store IntRegs:$src, iaddr:$addr)]>;
159 def MOV : InstARM<(ops IntRegs:$dst, op_addr_mode1:$src),
160 "mov $dst, $src", [(set IntRegs:$dst, addr_mode1:$src)]>;
162 def ADD : Addr1BinOp<"add", add>;
163 def ADCS : Addr1BinOp<"adcs", adde>;
164 def ADDS : Addr1BinOp<"adds", addc>;
166 // "LEA" forms of add
167 def lea_addri : InstARM<(ops IntRegs:$dst, memri:$addr),
168 "add $dst, ${addr:arith}",
169 [(set IntRegs:$dst, iaddr:$addr)]>;
172 def SUB : Addr1BinOp<"sub", sub>;
173 def SBCS : Addr1BinOp<"sbcs", sube>;
174 def SUBS : Addr1BinOp<"subs", subc>;
175 def AND : Addr1BinOp<"and", and>;
176 def EOR : Addr1BinOp<"eor", xor>;
177 def ORR : Addr1BinOp<"orr", or>;
179 let isTwoAddress = 1 in {
180 def movcond : InstARM<(ops IntRegs:$dst, IntRegs:$false,
181 op_addr_mode1:$true, CCOp:$cc),
182 "mov$cc $dst, $true",
183 [(set IntRegs:$dst, (armselect addr_mode1:$true,
184 IntRegs:$false, imm:$cc))]>;
187 def MUL : IntBinOp<"mul", mul>;
190 def SMULL : IntBinOp<"smull r12,", mulhs>;
191 def UMULL : IntBinOp<"umull r12,", mulhu>;
194 def bcond : InstARM<(ops brtarget:$dst, CCOp:$cc),
196 [(armbr bb:$dst, imm:$cc)]>;
198 def b : InstARM<(ops brtarget:$dst),
202 def cmp : InstARM<(ops IntRegs:$a, op_addr_mode1:$b),
204 [(armcmp IntRegs:$a, addr_mode1:$b)]>;
206 // Floating Point Compare
207 def fcmps : InstARM<(ops FPRegs:$a, FPRegs:$b),
209 [(armcmp FPRegs:$a, FPRegs:$b)]>;
211 def fcmpd : InstARM<(ops DFPRegs:$a, DFPRegs:$b),
213 [(armcmp DFPRegs:$a, DFPRegs:$b)]>;
215 // Floating Point Conversion
216 // We use bitconvert for moving the data between the register classes.
217 // The format conversion is done with ARM specific nodes
219 def FMSR : InstARM<(ops FPRegs:$dst, IntRegs:$src),
220 "fmsr $dst, $src", [(set FPRegs:$dst, (bitconvert IntRegs:$src))]>;
222 def FMRS : InstARM<(ops IntRegs:$dst, FPRegs:$src),
223 "fmrs $dst, $src", [(set IntRegs:$dst, (bitconvert FPRegs:$src))]>;
225 def FMRRD : InstARM<(ops IntRegs:$i0, IntRegs:$i1, DFPRegs:$src),
226 "fmrrd $i0, $i1, $src", [(armfmrrd IntRegs:$i0, IntRegs:$i1, DFPRegs:$src)]>;
228 def FMDRR : InstARM<(ops DFPRegs:$dst, IntRegs:$i0, IntRegs:$i1),
229 "fmdrr $dst, $i0, $i1", [(set DFPRegs:$dst, (armfmdrr IntRegs:$i0, IntRegs:$i1))]>;
231 def FSITOS : InstARM<(ops FPRegs:$dst, FPRegs:$src),
232 "fsitos $dst, $src", [(set FPRegs:$dst, (armfsitos FPRegs:$src))]>;
234 def FTOSIS : InstARM<(ops FPRegs:$dst, FPRegs:$src),
235 "ftosis $dst, $src", [(set FPRegs:$dst, (armftosis FPRegs:$src))]>;
237 def FSITOD : InstARM<(ops DFPRegs:$dst, FPRegs:$src),
238 "fsitod $dst, $src", [(set DFPRegs:$dst, (armfsitod FPRegs:$src))]>;
240 def FTOSID : InstARM<(ops FPRegs:$dst, DFPRegs:$src),
241 "ftosid $dst, $src", [(set FPRegs:$dst, (armftosid DFPRegs:$src))]>;
243 def FUITOS : InstARM<(ops FPRegs:$dst, FPRegs:$src),
244 "fuitos $dst, $src", [(set FPRegs:$dst, (armfuitos FPRegs:$src))]>;
246 def FTOUIS : InstARM<(ops FPRegs:$dst, FPRegs:$src),
247 "ftouis $dst, $src", [(set FPRegs:$dst, (armftouis FPRegs:$src))]>;
249 def FUITOD : InstARM<(ops DFPRegs:$dst, FPRegs:$src),
250 "fuitod $dst, $src", [(set DFPRegs:$dst, (armfuitod FPRegs:$src))]>;
252 def FTOUID : InstARM<(ops FPRegs:$dst, DFPRegs:$src),
253 "ftouid $dst, $src", [(set FPRegs:$dst, (armftouid DFPRegs:$src))]>;
255 def FCVTDS : InstARM<(ops DFPRegs:$dst, FPRegs:$src),
256 "fcvtds $dst, $src", [(set DFPRegs:$dst, (fextend FPRegs:$src))]>;
258 def FCVTSD : InstARM<(ops FPRegs:$dst, DFPRegs:$src),
259 "fcvtsd $dst, $src", [(set FPRegs:$dst, (fround DFPRegs:$src))]>;
261 def FMSTAT : InstARM<(ops ), "fmstat", [(armfmstat)]>;
263 // Floating Point Arithmetic
264 def FADDS : FPBinOp<"fadds", fadd>;
265 def FADDD : DFPBinOp<"faddd", fadd>;
266 def FSUBS : FPBinOp<"fsubs", fsub>;
267 def FSUBD : DFPBinOp<"fsubd", fsub>;
269 def FNEGS : InstARM<(ops FPRegs:$dst, FPRegs:$src),
271 [(set FPRegs:$dst, (fneg FPRegs:$src))]>;
273 def FNEGD : InstARM<(ops DFPRegs:$dst, DFPRegs:$src),
275 [(set DFPRegs:$dst, (fneg DFPRegs:$src))]>;
277 def FMULS : FPBinOp<"fmuls", fmul>;
278 def FMULD : DFPBinOp<"fmuld", fmul>;
281 // Floating Point Load
282 def FLDS : InstARM<(ops FPRegs:$dst, IntRegs:$addr),
284 [(set FPRegs:$dst, (load IntRegs:$addr))]>;
286 def FLDD : InstARM<(ops DFPRegs:$dst, IntRegs:$addr),
288 [(set DFPRegs:$dst, (load IntRegs:$addr))]>;
290 def : Pat<(ARMcall tglobaladdr:$dst),
291 (bl tglobaladdr:$dst)>;
293 def : Pat<(ARMcall texternalsym:$dst),
294 (bl texternalsym:$dst)>;