1 //===- ARMInstrInfo.td - Target Description for ARM Target -*- tablegen -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file describes the ARM instructions in TableGen format.
12 //===----------------------------------------------------------------------===//
14 //===----------------------------------------------------------------------===//
15 // ARM specific DAG Nodes.
19 def SDT_ARMCallSeqStart : SDCallSeqStart<[ SDTCisVT<0, i32> ]>;
20 def SDT_ARMCallSeqEnd : SDCallSeqEnd<[ SDTCisVT<0, i32>, SDTCisVT<1, i32> ]>;
22 def SDT_ARMSaveCallPC : SDTypeProfile<0, 1, []>;
24 def SDT_ARMcall : SDTypeProfile<0, -1, [SDTCisPtrTy<0>]>;
26 def SDT_ARMCMov : SDTypeProfile<1, 3,
27 [SDTCisSameAs<0, 1>, SDTCisSameAs<0, 2>,
30 def SDT_ARMBrcond : SDTypeProfile<0, 2,
31 [SDTCisVT<0, OtherVT>, SDTCisVT<1, i32>]>;
33 def SDT_ARMBrJT : SDTypeProfile<0, 3,
34 [SDTCisPtrTy<0>, SDTCisVT<1, i32>,
37 def SDT_ARMBr2JT : SDTypeProfile<0, 4,
38 [SDTCisPtrTy<0>, SDTCisVT<1, i32>,
39 SDTCisVT<2, i32>, SDTCisVT<3, i32>]>;
41 def SDT_ARMBCC_i64 : SDTypeProfile<0, 6,
43 SDTCisVT<1, i32>, SDTCisVT<2, i32>,
44 SDTCisVT<3, i32>, SDTCisVT<4, i32>,
45 SDTCisVT<5, OtherVT>]>;
47 def SDT_ARMAnd : SDTypeProfile<1, 2,
48 [SDTCisVT<0, i32>, SDTCisVT<1, i32>,
51 def SDT_ARMCmp : SDTypeProfile<0, 2, [SDTCisSameAs<0, 1>]>;
53 def SDT_ARMPICAdd : SDTypeProfile<1, 2, [SDTCisSameAs<0, 1>,
54 SDTCisPtrTy<1>, SDTCisVT<2, i32>]>;
56 def SDT_ARMThreadPointer : SDTypeProfile<1, 0, [SDTCisPtrTy<0>]>;
57 def SDT_ARMEH_SJLJ_Setjmp : SDTypeProfile<1, 2, [SDTCisInt<0>, SDTCisPtrTy<1>,
59 def SDT_ARMEH_SJLJ_Longjmp: SDTypeProfile<0, 2, [SDTCisPtrTy<0>, SDTCisInt<1>]>;
61 def SDT_ARMEH_SJLJ_DispatchSetup: SDTypeProfile<0, 0, []>;
63 def SDT_ARMMEMBARRIER : SDTypeProfile<0, 1, [SDTCisInt<0>]>;
65 def SDT_ARMTCRET : SDTypeProfile<0, 1, [SDTCisPtrTy<0>]>;
67 def SDT_ARMBFI : SDTypeProfile<1, 3, [SDTCisVT<0, i32>, SDTCisVT<1, i32>,
68 SDTCisVT<2, i32>, SDTCisVT<3, i32>]>;
71 def ARMWrapper : SDNode<"ARMISD::Wrapper", SDTIntUnaryOp>;
72 def ARMWrapperDYN : SDNode<"ARMISD::WrapperDYN", SDTIntUnaryOp>;
73 def ARMWrapperPIC : SDNode<"ARMISD::WrapperPIC", SDTIntUnaryOp>;
74 def ARMWrapperJT : SDNode<"ARMISD::WrapperJT", SDTIntBinOp>;
76 def ARMcallseq_start : SDNode<"ISD::CALLSEQ_START", SDT_ARMCallSeqStart,
77 [SDNPHasChain, SDNPOutGlue]>;
78 def ARMcallseq_end : SDNode<"ISD::CALLSEQ_END", SDT_ARMCallSeqEnd,
79 [SDNPHasChain, SDNPOptInGlue, SDNPOutGlue]>;
81 def ARMcall : SDNode<"ARMISD::CALL", SDT_ARMcall,
82 [SDNPHasChain, SDNPOptInGlue, SDNPOutGlue,
84 def ARMcall_pred : SDNode<"ARMISD::CALL_PRED", SDT_ARMcall,
85 [SDNPHasChain, SDNPOptInGlue, SDNPOutGlue,
87 def ARMcall_nolink : SDNode<"ARMISD::CALL_NOLINK", SDT_ARMcall,
88 [SDNPHasChain, SDNPOptInGlue, SDNPOutGlue,
91 def ARMretflag : SDNode<"ARMISD::RET_FLAG", SDTNone,
92 [SDNPHasChain, SDNPOptInGlue]>;
94 def ARMcmov : SDNode<"ARMISD::CMOV", SDT_ARMCMov,
97 def ARMbrcond : SDNode<"ARMISD::BRCOND", SDT_ARMBrcond,
98 [SDNPHasChain, SDNPInGlue, SDNPOutGlue]>;
100 def ARMbrjt : SDNode<"ARMISD::BR_JT", SDT_ARMBrJT,
102 def ARMbr2jt : SDNode<"ARMISD::BR2_JT", SDT_ARMBr2JT,
105 def ARMBcci64 : SDNode<"ARMISD::BCC_i64", SDT_ARMBCC_i64,
108 def ARMcmp : SDNode<"ARMISD::CMP", SDT_ARMCmp,
111 def ARMcmpZ : SDNode<"ARMISD::CMPZ", SDT_ARMCmp,
112 [SDNPOutGlue, SDNPCommutative]>;
114 def ARMpic_add : SDNode<"ARMISD::PIC_ADD", SDT_ARMPICAdd>;
116 def ARMsrl_flag : SDNode<"ARMISD::SRL_FLAG", SDTIntUnaryOp, [SDNPOutGlue]>;
117 def ARMsra_flag : SDNode<"ARMISD::SRA_FLAG", SDTIntUnaryOp, [SDNPOutGlue]>;
118 def ARMrrx : SDNode<"ARMISD::RRX" , SDTIntUnaryOp, [SDNPInGlue ]>;
120 def ARMthread_pointer: SDNode<"ARMISD::THREAD_POINTER", SDT_ARMThreadPointer>;
121 def ARMeh_sjlj_setjmp: SDNode<"ARMISD::EH_SJLJ_SETJMP",
122 SDT_ARMEH_SJLJ_Setjmp, [SDNPHasChain]>;
123 def ARMeh_sjlj_longjmp: SDNode<"ARMISD::EH_SJLJ_LONGJMP",
124 SDT_ARMEH_SJLJ_Longjmp, [SDNPHasChain]>;
125 def ARMeh_sjlj_dispatchsetup: SDNode<"ARMISD::EH_SJLJ_DISPATCHSETUP",
126 SDT_ARMEH_SJLJ_DispatchSetup, [SDNPHasChain]>;
129 def ARMMemBarrier : SDNode<"ARMISD::MEMBARRIER", SDT_ARMMEMBARRIER,
131 def ARMMemBarrierMCR : SDNode<"ARMISD::MEMBARRIER_MCR", SDT_ARMMEMBARRIER,
133 def ARMPreload : SDNode<"ARMISD::PRELOAD", SDTPrefetch,
134 [SDNPHasChain, SDNPMayLoad, SDNPMayStore]>;
136 def ARMrbit : SDNode<"ARMISD::RBIT", SDTIntUnaryOp>;
138 def ARMtcret : SDNode<"ARMISD::TC_RETURN", SDT_ARMTCRET,
139 [SDNPHasChain, SDNPOptInGlue, SDNPVariadic]>;
142 def ARMbfi : SDNode<"ARMISD::BFI", SDT_ARMBFI>;
144 //===----------------------------------------------------------------------===//
145 // ARM Instruction Predicate Definitions.
147 def HasV4T : Predicate<"Subtarget->hasV4TOps()">, AssemblerPredicate;
148 def NoV4T : Predicate<"!Subtarget->hasV4TOps()">;
149 def HasV5T : Predicate<"Subtarget->hasV5TOps()">;
150 def HasV5TE : Predicate<"Subtarget->hasV5TEOps()">, AssemblerPredicate;
151 def HasV6 : Predicate<"Subtarget->hasV6Ops()">, AssemblerPredicate;
152 def NoV6 : Predicate<"!Subtarget->hasV6Ops()">;
153 def HasV6T2 : Predicate<"Subtarget->hasV6T2Ops()">, AssemblerPredicate;
154 def NoV6T2 : Predicate<"!Subtarget->hasV6T2Ops()">;
155 def HasV7 : Predicate<"Subtarget->hasV7Ops()">, AssemblerPredicate;
156 def NoVFP : Predicate<"!Subtarget->hasVFP2()">;
157 def HasVFP2 : Predicate<"Subtarget->hasVFP2()">, AssemblerPredicate;
158 def HasVFP3 : Predicate<"Subtarget->hasVFP3()">, AssemblerPredicate;
159 def HasNEON : Predicate<"Subtarget->hasNEON()">, AssemblerPredicate;
160 def HasFP16 : Predicate<"Subtarget->hasFP16()">, AssemblerPredicate;
161 def HasDivide : Predicate<"Subtarget->hasDivide()">, AssemblerPredicate;
162 def HasT2ExtractPack : Predicate<"Subtarget->hasT2ExtractPack()">,
164 def HasDB : Predicate<"Subtarget->hasDataBarrier()">,
166 def HasMP : Predicate<"Subtarget->hasMPExtension()">,
168 def UseNEONForFP : Predicate<"Subtarget->useNEONForSinglePrecisionFP()">;
169 def DontUseNEONForFP : Predicate<"!Subtarget->useNEONForSinglePrecisionFP()">;
170 def IsThumb : Predicate<"Subtarget->isThumb()">, AssemblerPredicate;
171 def IsThumb1Only : Predicate<"Subtarget->isThumb1Only()">;
172 def IsThumb2 : Predicate<"Subtarget->isThumb2()">, AssemblerPredicate;
173 def IsARM : Predicate<"!Subtarget->isThumb()">, AssemblerPredicate;
174 def IsDarwin : Predicate<"Subtarget->isTargetDarwin()">;
175 def IsNotDarwin : Predicate<"!Subtarget->isTargetDarwin()">;
177 // FIXME: Eventually this will be just "hasV6T2Ops".
178 def UseMovt : Predicate<"Subtarget->useMovt()">;
179 def DontUseMovt : Predicate<"!Subtarget->useMovt()">;
180 def UseFPVMLx : Predicate<"Subtarget->useFPVMLx()">;
182 //===----------------------------------------------------------------------===//
183 // ARM Flag Definitions.
185 class RegConstraint<string C> {
186 string Constraints = C;
189 //===----------------------------------------------------------------------===//
190 // ARM specific transformation functions and pattern fragments.
193 // so_imm_neg_XFORM - Return a so_imm value packed into the format described for
194 // so_imm_neg def below.
195 def so_imm_neg_XFORM : SDNodeXForm<imm, [{
196 return CurDAG->getTargetConstant(-(int)N->getZExtValue(), MVT::i32);
199 // so_imm_not_XFORM - Return a so_imm value packed into the format described for
200 // so_imm_not def below.
201 def so_imm_not_XFORM : SDNodeXForm<imm, [{
202 return CurDAG->getTargetConstant(~(int)N->getZExtValue(), MVT::i32);
205 /// imm1_15 predicate - True if the 32-bit immediate is in the range [1,15].
206 def imm1_15 : ImmLeaf<i32, [{
207 return (int32_t)Imm >= 1 && (int32_t)Imm < 16;
210 /// imm16_31 predicate - True if the 32-bit immediate is in the range [16,31].
211 def imm16_31 : ImmLeaf<i32, [{
212 return (int32_t)Imm >= 16 && (int32_t)Imm < 32;
217 return ARM_AM::getSOImmVal(-(uint32_t)N->getZExtValue()) != -1;
218 }], so_imm_neg_XFORM>;
222 return ARM_AM::getSOImmVal(~(uint32_t)N->getZExtValue()) != -1;
223 }], so_imm_not_XFORM>;
225 // sext_16_node predicate - True if the SDNode is sign-extended 16 or more bits.
226 def sext_16_node : PatLeaf<(i32 GPR:$a), [{
227 return CurDAG->ComputeNumSignBits(SDValue(N,0)) >= 17;
230 /// Split a 32-bit immediate into two 16 bit parts.
231 def hi16 : SDNodeXForm<imm, [{
232 return CurDAG->getTargetConstant((uint32_t)N->getZExtValue() >> 16, MVT::i32);
235 def lo16AllZero : PatLeaf<(i32 imm), [{
236 // Returns true if all low 16-bits are 0.
237 return (((uint32_t)N->getZExtValue()) & 0xFFFFUL) == 0;
240 /// imm0_65535 predicate - True if the 32-bit immediate is in the range
242 def imm0_65535 : ImmLeaf<i32, [{
243 return Imm >= 0 && Imm < 65536;
246 class BinOpFrag<dag res> : PatFrag<(ops node:$LHS, node:$RHS), res>;
247 class UnOpFrag <dag res> : PatFrag<(ops node:$Src), res>;
249 /// adde and sube predicates - True based on whether the carry flag output
250 /// will be needed or not.
251 def adde_dead_carry :
252 PatFrag<(ops node:$LHS, node:$RHS), (adde node:$LHS, node:$RHS),
253 [{return !N->hasAnyUseOfValue(1);}]>;
254 def sube_dead_carry :
255 PatFrag<(ops node:$LHS, node:$RHS), (sube node:$LHS, node:$RHS),
256 [{return !N->hasAnyUseOfValue(1);}]>;
257 def adde_live_carry :
258 PatFrag<(ops node:$LHS, node:$RHS), (adde node:$LHS, node:$RHS),
259 [{return N->hasAnyUseOfValue(1);}]>;
260 def sube_live_carry :
261 PatFrag<(ops node:$LHS, node:$RHS), (sube node:$LHS, node:$RHS),
262 [{return N->hasAnyUseOfValue(1);}]>;
264 // An 'and' node with a single use.
265 def and_su : PatFrag<(ops node:$lhs, node:$rhs), (and node:$lhs, node:$rhs), [{
266 return N->hasOneUse();
269 // An 'xor' node with a single use.
270 def xor_su : PatFrag<(ops node:$lhs, node:$rhs), (xor node:$lhs, node:$rhs), [{
271 return N->hasOneUse();
274 // An 'fmul' node with a single use.
275 def fmul_su : PatFrag<(ops node:$lhs, node:$rhs), (fmul node:$lhs, node:$rhs),[{
276 return N->hasOneUse();
279 // An 'fadd' node which checks for single non-hazardous use.
280 def fadd_mlx : PatFrag<(ops node:$lhs, node:$rhs),(fadd node:$lhs, node:$rhs),[{
281 return hasNoVMLxHazardUse(N);
284 // An 'fsub' node which checks for single non-hazardous use.
285 def fsub_mlx : PatFrag<(ops node:$lhs, node:$rhs),(fsub node:$lhs, node:$rhs),[{
286 return hasNoVMLxHazardUse(N);
289 //===----------------------------------------------------------------------===//
290 // Operand Definitions.
294 // FIXME: rename brtarget to t2_brtarget
295 def brtarget : Operand<OtherVT> {
296 let EncoderMethod = "getBranchTargetOpValue";
299 // FIXME: get rid of this one?
300 def uncondbrtarget : Operand<OtherVT> {
301 let EncoderMethod = "getUnconditionalBranchTargetOpValue";
304 // Branch target for ARM. Handles conditional/unconditional
305 def br_target : Operand<OtherVT> {
306 let EncoderMethod = "getARMBranchTargetOpValue";
310 // FIXME: rename bltarget to t2_bl_target?
311 def bltarget : Operand<i32> {
312 // Encoded the same as branch targets.
313 let EncoderMethod = "getBranchTargetOpValue";
316 // Call target for ARM. Handles conditional/unconditional
317 // FIXME: rename bl_target to t2_bltarget?
318 def bl_target : Operand<i32> {
319 // Encoded the same as branch targets.
320 let EncoderMethod = "getARMBranchTargetOpValue";
324 // A list of registers separated by comma. Used by load/store multiple.
325 def RegListAsmOperand : AsmOperandClass {
326 let Name = "RegList";
327 let SuperClasses = [];
330 def DPRRegListAsmOperand : AsmOperandClass {
331 let Name = "DPRRegList";
332 let SuperClasses = [];
335 def SPRRegListAsmOperand : AsmOperandClass {
336 let Name = "SPRRegList";
337 let SuperClasses = [];
340 def reglist : Operand<i32> {
341 let EncoderMethod = "getRegisterListOpValue";
342 let ParserMatchClass = RegListAsmOperand;
343 let PrintMethod = "printRegisterList";
346 def dpr_reglist : Operand<i32> {
347 let EncoderMethod = "getRegisterListOpValue";
348 let ParserMatchClass = DPRRegListAsmOperand;
349 let PrintMethod = "printRegisterList";
352 def spr_reglist : Operand<i32> {
353 let EncoderMethod = "getRegisterListOpValue";
354 let ParserMatchClass = SPRRegListAsmOperand;
355 let PrintMethod = "printRegisterList";
358 // An operand for the CONSTPOOL_ENTRY pseudo-instruction.
359 def cpinst_operand : Operand<i32> {
360 let PrintMethod = "printCPInstOperand";
364 def pclabel : Operand<i32> {
365 let PrintMethod = "printPCLabel";
368 // ADR instruction labels.
369 def adrlabel : Operand<i32> {
370 let EncoderMethod = "getAdrLabelOpValue";
373 def neon_vcvt_imm32 : Operand<i32> {
374 let EncoderMethod = "getNEONVcvtImm32OpValue";
377 // rot_imm: An integer that encodes a rotate amount. Must be 8, 16, or 24.
378 def rot_imm : Operand<i32>, ImmLeaf<i32, [{
379 int32_t v = (int32_t)Imm;
380 return v == 8 || v == 16 || v == 24; }]> {
381 let EncoderMethod = "getRotImmOpValue";
384 def ShifterAsmOperand : AsmOperandClass {
385 let Name = "Shifter";
386 let SuperClasses = [];
389 // shift_imm: An integer that encodes a shift amount and the type of shift
390 // (currently either asr or lsl) using the same encoding used for the
391 // immediates in so_reg operands.
392 def shift_imm : Operand<i32> {
393 let PrintMethod = "printShiftImmOperand";
394 let ParserMatchClass = ShifterAsmOperand;
397 // shifter_operand operands: so_reg and so_imm.
398 def so_reg : Operand<i32>, // reg reg imm
399 ComplexPattern<i32, 3, "SelectShifterOperandReg",
400 [shl,srl,sra,rotr]> {
401 let EncoderMethod = "getSORegOpValue";
402 let PrintMethod = "printSORegOperand";
403 let MIOperandInfo = (ops GPR, GPR, shift_imm);
405 def shift_so_reg : Operand<i32>, // reg reg imm
406 ComplexPattern<i32, 3, "SelectShiftShifterOperandReg",
407 [shl,srl,sra,rotr]> {
408 let EncoderMethod = "getSORegOpValue";
409 let PrintMethod = "printSORegOperand";
410 let MIOperandInfo = (ops GPR, GPR, shift_imm);
413 // so_imm - Match a 32-bit shifter_operand immediate operand, which is an
414 // 8-bit immediate rotated by an arbitrary number of bits.
415 def so_imm : Operand<i32>, ImmLeaf<i32, [{
416 return ARM_AM::getSOImmVal(Imm) != -1;
418 let EncoderMethod = "getSOImmOpValue";
419 let PrintMethod = "printSOImmOperand";
422 // Break so_imm's up into two pieces. This handles immediates with up to 16
423 // bits set in them. This uses so_imm2part to match and so_imm2part_[12] to
424 // get the first/second pieces.
425 def so_imm2part : PatLeaf<(imm), [{
426 return ARM_AM::isSOImmTwoPartVal((unsigned)N->getZExtValue());
429 /// arm_i32imm - True for +V6T2, or true only if so_imm2part is true.
431 def arm_i32imm : PatLeaf<(imm), [{
432 if (Subtarget->hasV6T2Ops())
434 return ARM_AM::isSOImmTwoPartVal((unsigned)N->getZExtValue());
437 /// imm0_31 predicate - True if the 32-bit immediate is in the range [0,31].
438 def imm0_31 : Operand<i32>, ImmLeaf<i32, [{
439 return Imm >= 0 && Imm < 32;
442 /// imm0_31_m1 - Matches and prints like imm0_31, but encodes as 'value - 1'.
443 def imm0_31_m1 : Operand<i32>, ImmLeaf<i32, [{
444 return Imm >= 0 && Imm < 32;
446 let EncoderMethod = "getImmMinusOneOpValue";
449 // i32imm_hilo16 - For movt/movw - sets the MC Encoder method.
450 // The imm is split into imm{15-12}, imm{11-0}
452 def i32imm_hilo16 : Operand<i32> {
453 let EncoderMethod = "getHiLo16ImmOpValue";
456 /// bf_inv_mask_imm predicate - An AND mask to clear an arbitrary width bitfield
458 def bf_inv_mask_imm : Operand<i32>,
460 return ARM::isBitFieldInvertedMask(N->getZExtValue());
462 let EncoderMethod = "getBitfieldInvertedMaskOpValue";
463 let PrintMethod = "printBitfieldInvMaskImmOperand";
466 /// lsb_pos_imm - position of the lsb bit, used by BFI4p and t2BFI4p
467 def lsb_pos_imm : Operand<i32>, ImmLeaf<i32, [{
468 return isInt<5>(Imm);
471 /// width_imm - number of bits to be copied, used by BFI4p and t2BFI4p
472 def width_imm : Operand<i32>, ImmLeaf<i32, [{
473 return Imm > 0 && Imm <= 32;
475 let EncoderMethod = "getMsbOpValue";
478 // Define ARM specific addressing modes.
480 def MemMode2AsmOperand : AsmOperandClass {
481 let Name = "MemMode2";
482 let SuperClasses = [];
483 let ParserMethod = "tryParseMemMode2Operand";
486 def MemMode3AsmOperand : AsmOperandClass {
487 let Name = "MemMode3";
488 let SuperClasses = [];
489 let ParserMethod = "tryParseMemMode3Operand";
492 // addrmode_imm12 := reg +/- imm12
494 def addrmode_imm12 : Operand<i32>,
495 ComplexPattern<i32, 2, "SelectAddrModeImm12", []> {
496 // 12-bit immediate operand. Note that instructions using this encode
497 // #0 and #-0 differently. We flag #-0 as the magic value INT32_MIN. All other
498 // immediate values are as normal.
500 let EncoderMethod = "getAddrModeImm12OpValue";
501 let PrintMethod = "printAddrModeImm12Operand";
502 let MIOperandInfo = (ops GPR:$base, i32imm:$offsimm);
504 // ldst_so_reg := reg +/- reg shop imm
506 def ldst_so_reg : Operand<i32>,
507 ComplexPattern<i32, 3, "SelectLdStSOReg", []> {
508 let EncoderMethod = "getLdStSORegOpValue";
509 // FIXME: Simplify the printer
510 let PrintMethod = "printAddrMode2Operand";
511 let MIOperandInfo = (ops GPR:$base, GPR:$offsreg, i32imm:$offsimm);
514 // addrmode2 := reg +/- imm12
515 // := reg +/- reg shop imm
517 def addrmode2 : Operand<i32>,
518 ComplexPattern<i32, 3, "SelectAddrMode2", []> {
519 let EncoderMethod = "getAddrMode2OpValue";
520 let PrintMethod = "printAddrMode2Operand";
521 let ParserMatchClass = MemMode2AsmOperand;
522 let MIOperandInfo = (ops GPR:$base, GPR:$offsreg, i32imm:$offsimm);
525 def am2offset : Operand<i32>,
526 ComplexPattern<i32, 2, "SelectAddrMode2Offset",
527 [], [SDNPWantRoot]> {
528 let EncoderMethod = "getAddrMode2OffsetOpValue";
529 let PrintMethod = "printAddrMode2OffsetOperand";
530 let MIOperandInfo = (ops GPR, i32imm);
533 // addrmode3 := reg +/- reg
534 // addrmode3 := reg +/- imm8
536 def addrmode3 : Operand<i32>,
537 ComplexPattern<i32, 3, "SelectAddrMode3", []> {
538 let EncoderMethod = "getAddrMode3OpValue";
539 let PrintMethod = "printAddrMode3Operand";
540 let ParserMatchClass = MemMode3AsmOperand;
541 let MIOperandInfo = (ops GPR:$base, GPR:$offsreg, i32imm:$offsimm);
544 def am3offset : Operand<i32>,
545 ComplexPattern<i32, 2, "SelectAddrMode3Offset",
546 [], [SDNPWantRoot]> {
547 let EncoderMethod = "getAddrMode3OffsetOpValue";
548 let PrintMethod = "printAddrMode3OffsetOperand";
549 let MIOperandInfo = (ops GPR, i32imm);
552 // ldstm_mode := {ia, ib, da, db}
554 def ldstm_mode : OptionalDefOperand<OtherVT, (ops i32), (ops (i32 1))> {
555 let EncoderMethod = "getLdStmModeOpValue";
556 let PrintMethod = "printLdStmModeOperand";
559 def MemMode5AsmOperand : AsmOperandClass {
560 let Name = "MemMode5";
561 let SuperClasses = [];
564 // addrmode5 := reg +/- imm8*4
566 def addrmode5 : Operand<i32>,
567 ComplexPattern<i32, 2, "SelectAddrMode5", []> {
568 let PrintMethod = "printAddrMode5Operand";
569 let MIOperandInfo = (ops GPR:$base, i32imm);
570 let ParserMatchClass = MemMode5AsmOperand;
571 let EncoderMethod = "getAddrMode5OpValue";
574 // addrmode6 := reg with optional alignment
576 def addrmode6 : Operand<i32>,
577 ComplexPattern<i32, 2, "SelectAddrMode6", [], [SDNPWantParent]>{
578 let PrintMethod = "printAddrMode6Operand";
579 let MIOperandInfo = (ops GPR:$addr, i32imm);
580 let EncoderMethod = "getAddrMode6AddressOpValue";
583 def am6offset : Operand<i32>,
584 ComplexPattern<i32, 1, "SelectAddrMode6Offset",
585 [], [SDNPWantRoot]> {
586 let PrintMethod = "printAddrMode6OffsetOperand";
587 let MIOperandInfo = (ops GPR);
588 let EncoderMethod = "getAddrMode6OffsetOpValue";
591 // Special version of addrmode6 to handle alignment encoding for VLD-dup
592 // instructions, specifically VLD4-dup.
593 def addrmode6dup : Operand<i32>,
594 ComplexPattern<i32, 2, "SelectAddrMode6", [], [SDNPWantParent]>{
595 let PrintMethod = "printAddrMode6Operand";
596 let MIOperandInfo = (ops GPR:$addr, i32imm);
597 let EncoderMethod = "getAddrMode6DupAddressOpValue";
600 // addrmodepc := pc + reg
602 def addrmodepc : Operand<i32>,
603 ComplexPattern<i32, 2, "SelectAddrModePC", []> {
604 let PrintMethod = "printAddrModePCOperand";
605 let MIOperandInfo = (ops GPR, i32imm);
608 def MemMode7AsmOperand : AsmOperandClass {
609 let Name = "MemMode7";
610 let SuperClasses = [];
614 // Used by load/store exclusive instructions. Useful to enable right assembly
615 // parsing and printing. Not used for any codegen matching.
617 def addrmode7 : Operand<i32> {
618 let PrintMethod = "printAddrMode7Operand";
619 let MIOperandInfo = (ops GPR);
620 let ParserMatchClass = MemMode7AsmOperand;
623 def nohash_imm : Operand<i32> {
624 let PrintMethod = "printNoHashImmediate";
627 def CoprocNumAsmOperand : AsmOperandClass {
628 let Name = "CoprocNum";
629 let SuperClasses = [];
630 let ParserMethod = "tryParseCoprocNumOperand";
633 def CoprocRegAsmOperand : AsmOperandClass {
634 let Name = "CoprocReg";
635 let SuperClasses = [];
636 let ParserMethod = "tryParseCoprocRegOperand";
639 def p_imm : Operand<i32> {
640 let PrintMethod = "printPImmediate";
641 let ParserMatchClass = CoprocNumAsmOperand;
644 def c_imm : Operand<i32> {
645 let PrintMethod = "printCImmediate";
646 let ParserMatchClass = CoprocRegAsmOperand;
649 //===----------------------------------------------------------------------===//
651 include "ARMInstrFormats.td"
653 //===----------------------------------------------------------------------===//
654 // Multiclass helpers...
657 /// AsI1_bin_irs - Defines a set of (op r, {so_imm|r|so_reg}) patterns for a
658 /// binop that produces a value.
659 multiclass AsI1_bin_irs<bits<4> opcod, string opc,
660 InstrItinClass iii, InstrItinClass iir, InstrItinClass iis,
661 PatFrag opnode, bit Commutable = 0> {
662 // The register-immediate version is re-materializable. This is useful
663 // in particular for taking the address of a local.
664 let isReMaterializable = 1 in {
665 def ri : AsI1<opcod, (outs GPR:$Rd), (ins GPR:$Rn, so_imm:$imm), DPFrm,
666 iii, opc, "\t$Rd, $Rn, $imm",
667 [(set GPR:$Rd, (opnode GPR:$Rn, so_imm:$imm))]> {
672 let Inst{19-16} = Rn;
673 let Inst{15-12} = Rd;
674 let Inst{11-0} = imm;
677 def rr : AsI1<opcod, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm), DPFrm,
678 iir, opc, "\t$Rd, $Rn, $Rm",
679 [(set GPR:$Rd, (opnode GPR:$Rn, GPR:$Rm))]> {
684 let isCommutable = Commutable;
685 let Inst{19-16} = Rn;
686 let Inst{15-12} = Rd;
687 let Inst{11-4} = 0b00000000;
690 def rs : AsI1<opcod, (outs GPR:$Rd), (ins GPR:$Rn, so_reg:$shift), DPSoRegFrm,
691 iis, opc, "\t$Rd, $Rn, $shift",
692 [(set GPR:$Rd, (opnode GPR:$Rn, so_reg:$shift))]> {
697 let Inst{19-16} = Rn;
698 let Inst{15-12} = Rd;
699 let Inst{11-0} = shift;
703 /// AI1_bin_s_irs - Similar to AsI1_bin_irs except it sets the 's' bit so the
704 /// instruction modifies the CPSR register.
705 let isCodeGenOnly = 1, Defs = [CPSR] in {
706 multiclass AI1_bin_s_irs<bits<4> opcod, string opc,
707 InstrItinClass iii, InstrItinClass iir, InstrItinClass iis,
708 PatFrag opnode, bit Commutable = 0> {
709 def ri : AI1<opcod, (outs GPR:$Rd), (ins GPR:$Rn, so_imm:$imm), DPFrm,
710 iii, opc, "\t$Rd, $Rn, $imm",
711 [(set GPR:$Rd, (opnode GPR:$Rn, so_imm:$imm))]> {
717 let Inst{19-16} = Rn;
718 let Inst{15-12} = Rd;
719 let Inst{11-0} = imm;
721 def rr : AI1<opcod, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm), DPFrm,
722 iir, opc, "\t$Rd, $Rn, $Rm",
723 [(set GPR:$Rd, (opnode GPR:$Rn, GPR:$Rm))]> {
727 let isCommutable = Commutable;
730 let Inst{19-16} = Rn;
731 let Inst{15-12} = Rd;
732 let Inst{11-4} = 0b00000000;
735 def rs : AI1<opcod, (outs GPR:$Rd), (ins GPR:$Rn, so_reg:$shift), DPSoRegFrm,
736 iis, opc, "\t$Rd, $Rn, $shift",
737 [(set GPR:$Rd, (opnode GPR:$Rn, so_reg:$shift))]> {
743 let Inst{19-16} = Rn;
744 let Inst{15-12} = Rd;
745 let Inst{11-0} = shift;
750 /// AI1_cmp_irs - Defines a set of (op r, {so_imm|r|so_reg}) cmp / test
751 /// patterns. Similar to AsI1_bin_irs except the instruction does not produce
752 /// a explicit result, only implicitly set CPSR.
753 let isCompare = 1, Defs = [CPSR] in {
754 multiclass AI1_cmp_irs<bits<4> opcod, string opc,
755 InstrItinClass iii, InstrItinClass iir, InstrItinClass iis,
756 PatFrag opnode, bit Commutable = 0> {
757 def ri : AI1<opcod, (outs), (ins GPR:$Rn, so_imm:$imm), DPFrm, iii,
759 [(opnode GPR:$Rn, so_imm:$imm)]> {
764 let Inst{19-16} = Rn;
765 let Inst{15-12} = 0b0000;
766 let Inst{11-0} = imm;
768 def rr : AI1<opcod, (outs), (ins GPR:$Rn, GPR:$Rm), DPFrm, iir,
770 [(opnode GPR:$Rn, GPR:$Rm)]> {
773 let isCommutable = Commutable;
776 let Inst{19-16} = Rn;
777 let Inst{15-12} = 0b0000;
778 let Inst{11-4} = 0b00000000;
781 def rs : AI1<opcod, (outs), (ins GPR:$Rn, so_reg:$shift), DPSoRegFrm, iis,
782 opc, "\t$Rn, $shift",
783 [(opnode GPR:$Rn, so_reg:$shift)]> {
788 let Inst{19-16} = Rn;
789 let Inst{15-12} = 0b0000;
790 let Inst{11-0} = shift;
795 /// AI_ext_rrot - A unary operation with two forms: one whose operand is a
796 /// register and one whose operand is a register rotated by 8/16/24.
797 /// FIXME: Remove the 'r' variant. Its rot_imm is zero.
798 multiclass AI_ext_rrot<bits<8> opcod, string opc, PatFrag opnode> {
799 def r : AExtI<opcod, (outs GPR:$Rd), (ins GPR:$Rm),
800 IIC_iEXTr, opc, "\t$Rd, $Rm",
801 [(set GPR:$Rd, (opnode GPR:$Rm))]>,
802 Requires<[IsARM, HasV6]> {
805 let Inst{19-16} = 0b1111;
806 let Inst{15-12} = Rd;
807 let Inst{11-10} = 0b00;
810 def r_rot : AExtI<opcod, (outs GPR:$Rd), (ins GPR:$Rm, rot_imm:$rot),
811 IIC_iEXTr, opc, "\t$Rd, $Rm, ror $rot",
812 [(set GPR:$Rd, (opnode (rotr GPR:$Rm, rot_imm:$rot)))]>,
813 Requires<[IsARM, HasV6]> {
817 let Inst{19-16} = 0b1111;
818 let Inst{15-12} = Rd;
819 let Inst{11-10} = rot;
824 multiclass AI_ext_rrot_np<bits<8> opcod, string opc> {
825 def r : AExtI<opcod, (outs GPR:$Rd), (ins GPR:$Rm),
826 IIC_iEXTr, opc, "\t$Rd, $Rm",
827 [/* For disassembly only; pattern left blank */]>,
828 Requires<[IsARM, HasV6]> {
829 let Inst{19-16} = 0b1111;
830 let Inst{11-10} = 0b00;
832 def r_rot : AExtI<opcod, (outs GPR:$Rd), (ins GPR:$Rm, rot_imm:$rot),
833 IIC_iEXTr, opc, "\t$Rd, $Rm, ror $rot",
834 [/* For disassembly only; pattern left blank */]>,
835 Requires<[IsARM, HasV6]> {
837 let Inst{19-16} = 0b1111;
838 let Inst{11-10} = rot;
842 /// AI_exta_rrot - A binary operation with two forms: one whose operand is a
843 /// register and one whose operand is a register rotated by 8/16/24.
844 multiclass AI_exta_rrot<bits<8> opcod, string opc, PatFrag opnode> {
845 def rr : AExtI<opcod, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm),
846 IIC_iEXTAr, opc, "\t$Rd, $Rn, $Rm",
847 [(set GPR:$Rd, (opnode GPR:$Rn, GPR:$Rm))]>,
848 Requires<[IsARM, HasV6]> {
852 let Inst{19-16} = Rn;
853 let Inst{15-12} = Rd;
854 let Inst{11-10} = 0b00;
855 let Inst{9-4} = 0b000111;
858 def rr_rot : AExtI<opcod, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm,
860 IIC_iEXTAr, opc, "\t$Rd, $Rn, $Rm, ror $rot",
861 [(set GPR:$Rd, (opnode GPR:$Rn,
862 (rotr GPR:$Rm, rot_imm:$rot)))]>,
863 Requires<[IsARM, HasV6]> {
868 let Inst{19-16} = Rn;
869 let Inst{15-12} = Rd;
870 let Inst{11-10} = rot;
871 let Inst{9-4} = 0b000111;
876 // For disassembly only.
877 multiclass AI_exta_rrot_np<bits<8> opcod, string opc> {
878 def rr : AExtI<opcod, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm),
879 IIC_iEXTAr, opc, "\t$Rd, $Rn, $Rm",
880 [/* For disassembly only; pattern left blank */]>,
881 Requires<[IsARM, HasV6]> {
882 let Inst{11-10} = 0b00;
884 def rr_rot : AExtI<opcod, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm,
886 IIC_iEXTAr, opc, "\t$Rd, $Rn, $Rm, ror $rot",
887 [/* For disassembly only; pattern left blank */]>,
888 Requires<[IsARM, HasV6]> {
891 let Inst{19-16} = Rn;
892 let Inst{11-10} = rot;
896 /// AI1_adde_sube_irs - Define instructions and patterns for adde and sube.
897 let Uses = [CPSR] in {
898 multiclass AI1_adde_sube_irs<bits<4> opcod, string opc, PatFrag opnode,
899 bit Commutable = 0> {
900 def ri : AsI1<opcod, (outs GPR:$Rd), (ins GPR:$Rn, so_imm:$imm),
901 DPFrm, IIC_iALUi, opc, "\t$Rd, $Rn, $imm",
902 [(set GPR:$Rd, (opnode GPR:$Rn, so_imm:$imm))]>,
908 let Inst{15-12} = Rd;
909 let Inst{19-16} = Rn;
910 let Inst{11-0} = imm;
912 def rr : AsI1<opcod, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm),
913 DPFrm, IIC_iALUr, opc, "\t$Rd, $Rn, $Rm",
914 [(set GPR:$Rd, (opnode GPR:$Rn, GPR:$Rm))]>,
919 let Inst{11-4} = 0b00000000;
921 let isCommutable = Commutable;
923 let Inst{15-12} = Rd;
924 let Inst{19-16} = Rn;
926 def rs : AsI1<opcod, (outs GPR:$Rd), (ins GPR:$Rn, so_reg:$shift),
927 DPSoRegFrm, IIC_iALUsr, opc, "\t$Rd, $Rn, $shift",
928 [(set GPR:$Rd, (opnode GPR:$Rn, so_reg:$shift))]>,
934 let Inst{11-0} = shift;
935 let Inst{15-12} = Rd;
936 let Inst{19-16} = Rn;
941 // Carry setting variants
942 // NOTE: CPSR def omitted because it will be handled by the custom inserter.
943 let usesCustomInserter = 1 in {
944 multiclass AI1_adde_sube_s_irs<PatFrag opnode, bit Commutable = 0> {
945 def ri : ARMPseudoInst<(outs GPR:$Rd), (ins GPR:$Rn, so_imm:$imm),
946 Size4Bytes, IIC_iALUi,
947 [(set GPR:$Rd, (opnode GPR:$Rn, so_imm:$imm))]>;
948 def rr : ARMPseudoInst<(outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm),
949 Size4Bytes, IIC_iALUr,
950 [(set GPR:$Rd, (opnode GPR:$Rn, GPR:$Rm))]> {
951 let isCommutable = Commutable;
953 def rs : ARMPseudoInst<(outs GPR:$Rd), (ins GPR:$Rn, so_reg:$shift),
954 Size4Bytes, IIC_iALUsr,
955 [(set GPR:$Rd, (opnode GPR:$Rn, so_reg:$shift))]>;
959 let canFoldAsLoad = 1, isReMaterializable = 1 in {
960 multiclass AI_ldr1<bit isByte, string opc, InstrItinClass iii,
961 InstrItinClass iir, PatFrag opnode> {
962 // Note: We use the complex addrmode_imm12 rather than just an input
963 // GPR and a constrained immediate so that we can use this to match
964 // frame index references and avoid matching constant pool references.
965 def i12: AI2ldst<0b010, 1, isByte, (outs GPR:$Rt), (ins addrmode_imm12:$addr),
966 AddrMode_i12, LdFrm, iii, opc, "\t$Rt, $addr",
967 [(set GPR:$Rt, (opnode addrmode_imm12:$addr))]> {
970 let Inst{23} = addr{12}; // U (add = ('U' == 1))
971 let Inst{19-16} = addr{16-13}; // Rn
972 let Inst{15-12} = Rt;
973 let Inst{11-0} = addr{11-0}; // imm12
975 def rs : AI2ldst<0b011, 1, isByte, (outs GPR:$Rt), (ins ldst_so_reg:$shift),
976 AddrModeNone, LdFrm, iir, opc, "\t$Rt, $shift",
977 [(set GPR:$Rt, (opnode ldst_so_reg:$shift))]> {
980 let shift{4} = 0; // Inst{4} = 0
981 let Inst{23} = shift{12}; // U (add = ('U' == 1))
982 let Inst{19-16} = shift{16-13}; // Rn
983 let Inst{15-12} = Rt;
984 let Inst{11-0} = shift{11-0};
989 multiclass AI_str1<bit isByte, string opc, InstrItinClass iii,
990 InstrItinClass iir, PatFrag opnode> {
991 // Note: We use the complex addrmode_imm12 rather than just an input
992 // GPR and a constrained immediate so that we can use this to match
993 // frame index references and avoid matching constant pool references.
994 def i12 : AI2ldst<0b010, 0, isByte, (outs),
995 (ins GPR:$Rt, addrmode_imm12:$addr),
996 AddrMode_i12, StFrm, iii, opc, "\t$Rt, $addr",
997 [(opnode GPR:$Rt, addrmode_imm12:$addr)]> {
1000 let Inst{23} = addr{12}; // U (add = ('U' == 1))
1001 let Inst{19-16} = addr{16-13}; // Rn
1002 let Inst{15-12} = Rt;
1003 let Inst{11-0} = addr{11-0}; // imm12
1005 def rs : AI2ldst<0b011, 0, isByte, (outs), (ins GPR:$Rt, ldst_so_reg:$shift),
1006 AddrModeNone, StFrm, iir, opc, "\t$Rt, $shift",
1007 [(opnode GPR:$Rt, ldst_so_reg:$shift)]> {
1010 let shift{4} = 0; // Inst{4} = 0
1011 let Inst{23} = shift{12}; // U (add = ('U' == 1))
1012 let Inst{19-16} = shift{16-13}; // Rn
1013 let Inst{15-12} = Rt;
1014 let Inst{11-0} = shift{11-0};
1017 //===----------------------------------------------------------------------===//
1019 //===----------------------------------------------------------------------===//
1021 //===----------------------------------------------------------------------===//
1022 // Miscellaneous Instructions.
1025 /// CONSTPOOL_ENTRY - This instruction represents a floating constant pool in
1026 /// the function. The first operand is the ID# for this instruction, the second
1027 /// is the index into the MachineConstantPool that this is, the third is the
1028 /// size in bytes of this constant pool entry.
1029 let neverHasSideEffects = 1, isNotDuplicable = 1 in
1030 def CONSTPOOL_ENTRY :
1031 PseudoInst<(outs), (ins cpinst_operand:$instid, cpinst_operand:$cpidx,
1032 i32imm:$size), NoItinerary, []>;
1034 // FIXME: Marking these as hasSideEffects is necessary to prevent machine DCE
1035 // from removing one half of the matched pairs. That breaks PEI, which assumes
1036 // these will always be in pairs, and asserts if it finds otherwise. Better way?
1037 let Defs = [SP], Uses = [SP], hasSideEffects = 1 in {
1038 def ADJCALLSTACKUP :
1039 PseudoInst<(outs), (ins i32imm:$amt1, i32imm:$amt2, pred:$p), NoItinerary,
1040 [(ARMcallseq_end timm:$amt1, timm:$amt2)]>;
1042 def ADJCALLSTACKDOWN :
1043 PseudoInst<(outs), (ins i32imm:$amt, pred:$p), NoItinerary,
1044 [(ARMcallseq_start timm:$amt)]>;
1047 def NOP : AI<(outs), (ins), MiscFrm, NoItinerary, "nop", "",
1048 [/* For disassembly only; pattern left blank */]>,
1049 Requires<[IsARM, HasV6T2]> {
1050 let Inst{27-16} = 0b001100100000;
1051 let Inst{15-8} = 0b11110000;
1052 let Inst{7-0} = 0b00000000;
1055 def YIELD : AI<(outs), (ins), MiscFrm, NoItinerary, "yield", "",
1056 [/* For disassembly only; pattern left blank */]>,
1057 Requires<[IsARM, HasV6T2]> {
1058 let Inst{27-16} = 0b001100100000;
1059 let Inst{15-8} = 0b11110000;
1060 let Inst{7-0} = 0b00000001;
1063 def WFE : AI<(outs), (ins), MiscFrm, NoItinerary, "wfe", "",
1064 [/* For disassembly only; pattern left blank */]>,
1065 Requires<[IsARM, HasV6T2]> {
1066 let Inst{27-16} = 0b001100100000;
1067 let Inst{15-8} = 0b11110000;
1068 let Inst{7-0} = 0b00000010;
1071 def WFI : AI<(outs), (ins), MiscFrm, NoItinerary, "wfi", "",
1072 [/* For disassembly only; pattern left blank */]>,
1073 Requires<[IsARM, HasV6T2]> {
1074 let Inst{27-16} = 0b001100100000;
1075 let Inst{15-8} = 0b11110000;
1076 let Inst{7-0} = 0b00000011;
1079 def SEL : AI<(outs GPR:$dst), (ins GPR:$a, GPR:$b), DPFrm, NoItinerary, "sel",
1081 [/* For disassembly only; pattern left blank */]>,
1082 Requires<[IsARM, HasV6]> {
1087 let Inst{15-12} = Rd;
1088 let Inst{19-16} = Rn;
1089 let Inst{27-20} = 0b01101000;
1090 let Inst{7-4} = 0b1011;
1091 let Inst{11-8} = 0b1111;
1094 def SEV : AI<(outs), (ins), MiscFrm, NoItinerary, "sev", "",
1095 [/* For disassembly only; pattern left blank */]>,
1096 Requires<[IsARM, HasV6T2]> {
1097 let Inst{27-16} = 0b001100100000;
1098 let Inst{15-8} = 0b11110000;
1099 let Inst{7-0} = 0b00000100;
1102 // The i32imm operand $val can be used by a debugger to store more information
1103 // about the breakpoint.
1104 def BKPT : AI<(outs), (ins i32imm:$val), MiscFrm, NoItinerary, "bkpt", "\t$val",
1105 [/* For disassembly only; pattern left blank */]>,
1108 let Inst{3-0} = val{3-0};
1109 let Inst{19-8} = val{15-4};
1110 let Inst{27-20} = 0b00010010;
1111 let Inst{7-4} = 0b0111;
1114 // Change Processor State is a system instruction -- for disassembly and
1116 // FIXME: Since the asm parser has currently no clean way to handle optional
1117 // operands, create 3 versions of the same instruction. Once there's a clean
1118 // framework to represent optional operands, change this behavior.
1119 class CPS<dag iops, string asm_ops>
1120 : AXI<(outs), iops, MiscFrm, NoItinerary, !strconcat("cps", asm_ops),
1121 [/* For disassembly only; pattern left blank */]>, Requires<[IsARM]> {
1127 let Inst{31-28} = 0b1111;
1128 let Inst{27-20} = 0b00010000;
1129 let Inst{19-18} = imod;
1130 let Inst{17} = M; // Enabled if mode is set;
1132 let Inst{8-6} = iflags;
1134 let Inst{4-0} = mode;
1138 def CPS3p : CPS<(ins imod_op:$imod, iflags_op:$iflags, i32imm:$mode),
1139 "$imod\t$iflags, $mode">;
1140 let mode = 0, M = 0 in
1141 def CPS2p : CPS<(ins imod_op:$imod, iflags_op:$iflags), "$imod\t$iflags">;
1143 let imod = 0, iflags = 0, M = 1 in
1144 def CPS1p : CPS<(ins i32imm:$mode), "\t$mode">;
1146 // Preload signals the memory system of possible future data/instruction access.
1147 // These are for disassembly only.
1148 multiclass APreLoad<bits<1> read, bits<1> data, string opc> {
1150 def i12 : AXI<(outs), (ins addrmode_imm12:$addr), MiscFrm, IIC_Preload,
1151 !strconcat(opc, "\t$addr"),
1152 [(ARMPreload addrmode_imm12:$addr, (i32 read), (i32 data))]> {
1155 let Inst{31-26} = 0b111101;
1156 let Inst{25} = 0; // 0 for immediate form
1157 let Inst{24} = data;
1158 let Inst{23} = addr{12}; // U (add = ('U' == 1))
1159 let Inst{22} = read;
1160 let Inst{21-20} = 0b01;
1161 let Inst{19-16} = addr{16-13}; // Rn
1162 let Inst{15-12} = 0b1111;
1163 let Inst{11-0} = addr{11-0}; // imm12
1166 def rs : AXI<(outs), (ins ldst_so_reg:$shift), MiscFrm, IIC_Preload,
1167 !strconcat(opc, "\t$shift"),
1168 [(ARMPreload ldst_so_reg:$shift, (i32 read), (i32 data))]> {
1170 let Inst{31-26} = 0b111101;
1171 let Inst{25} = 1; // 1 for register form
1172 let Inst{24} = data;
1173 let Inst{23} = shift{12}; // U (add = ('U' == 1))
1174 let Inst{22} = read;
1175 let Inst{21-20} = 0b01;
1176 let Inst{19-16} = shift{16-13}; // Rn
1177 let Inst{15-12} = 0b1111;
1178 let Inst{11-0} = shift{11-0};
1182 defm PLD : APreLoad<1, 1, "pld">, Requires<[IsARM]>;
1183 defm PLDW : APreLoad<0, 1, "pldw">, Requires<[IsARM,HasV7,HasMP]>;
1184 defm PLI : APreLoad<1, 0, "pli">, Requires<[IsARM,HasV7]>;
1186 def SETEND : AXI<(outs),(ins setend_op:$end), MiscFrm, NoItinerary,
1188 [/* For disassembly only; pattern left blank */]>,
1191 let Inst{31-10} = 0b1111000100000001000000;
1196 def DBG : AI<(outs), (ins i32imm:$opt), MiscFrm, NoItinerary, "dbg", "\t$opt",
1197 [/* For disassembly only; pattern left blank */]>,
1198 Requires<[IsARM, HasV7]> {
1200 let Inst{27-4} = 0b001100100000111100001111;
1201 let Inst{3-0} = opt;
1204 // A5.4 Permanently UNDEFINED instructions.
1205 let isBarrier = 1, isTerminator = 1 in
1206 def TRAP : AXI<(outs), (ins), MiscFrm, NoItinerary,
1209 let Inst = 0xe7ffdefe;
1212 // Address computation and loads and stores in PIC mode.
1213 let isNotDuplicable = 1 in {
1214 def PICADD : ARMPseudoInst<(outs GPR:$dst), (ins GPR:$a, pclabel:$cp, pred:$p),
1215 Size4Bytes, IIC_iALUr,
1216 [(set GPR:$dst, (ARMpic_add GPR:$a, imm:$cp))]>;
1218 let AddedComplexity = 10 in {
1219 def PICLDR : ARMPseudoInst<(outs GPR:$dst), (ins addrmodepc:$addr, pred:$p),
1220 Size4Bytes, IIC_iLoad_r,
1221 [(set GPR:$dst, (load addrmodepc:$addr))]>;
1223 def PICLDRH : ARMPseudoInst<(outs GPR:$Rt), (ins addrmodepc:$addr, pred:$p),
1224 Size4Bytes, IIC_iLoad_bh_r,
1225 [(set GPR:$Rt, (zextloadi16 addrmodepc:$addr))]>;
1227 def PICLDRB : ARMPseudoInst<(outs GPR:$Rt), (ins addrmodepc:$addr, pred:$p),
1228 Size4Bytes, IIC_iLoad_bh_r,
1229 [(set GPR:$Rt, (zextloadi8 addrmodepc:$addr))]>;
1231 def PICLDRSH : ARMPseudoInst<(outs GPR:$Rt), (ins addrmodepc:$addr, pred:$p),
1232 Size4Bytes, IIC_iLoad_bh_r,
1233 [(set GPR:$Rt, (sextloadi16 addrmodepc:$addr))]>;
1235 def PICLDRSB : ARMPseudoInst<(outs GPR:$Rt), (ins addrmodepc:$addr, pred:$p),
1236 Size4Bytes, IIC_iLoad_bh_r,
1237 [(set GPR:$Rt, (sextloadi8 addrmodepc:$addr))]>;
1239 let AddedComplexity = 10 in {
1240 def PICSTR : ARMPseudoInst<(outs), (ins GPR:$src, addrmodepc:$addr, pred:$p),
1241 Size4Bytes, IIC_iStore_r, [(store GPR:$src, addrmodepc:$addr)]>;
1243 def PICSTRH : ARMPseudoInst<(outs), (ins GPR:$src, addrmodepc:$addr, pred:$p),
1244 Size4Bytes, IIC_iStore_bh_r, [(truncstorei16 GPR:$src,
1245 addrmodepc:$addr)]>;
1247 def PICSTRB : ARMPseudoInst<(outs), (ins GPR:$src, addrmodepc:$addr, pred:$p),
1248 Size4Bytes, IIC_iStore_bh_r, [(truncstorei8 GPR:$src, addrmodepc:$addr)]>;
1250 } // isNotDuplicable = 1
1253 // LEApcrel - Load a pc-relative address into a register without offending the
1255 let neverHasSideEffects = 1, isReMaterializable = 1 in
1256 // The 'adr' mnemonic encodes differently if the label is before or after
1257 // the instruction. The {24-21} opcode bits are set by the fixup, as we don't
1258 // know until then which form of the instruction will be used.
1259 def ADR : AI1<{0,?,?,0}, (outs GPR:$Rd), (ins adrlabel:$label),
1260 MiscFrm, IIC_iALUi, "adr", "\t$Rd, #$label", []> {
1263 let Inst{27-25} = 0b001;
1265 let Inst{19-16} = 0b1111;
1266 let Inst{15-12} = Rd;
1267 let Inst{11-0} = label;
1269 def LEApcrel : ARMPseudoInst<(outs GPR:$Rd), (ins i32imm:$label, pred:$p),
1270 Size4Bytes, IIC_iALUi, []>;
1272 def LEApcrelJT : ARMPseudoInst<(outs GPR:$Rd),
1273 (ins i32imm:$label, nohash_imm:$id, pred:$p),
1274 Size4Bytes, IIC_iALUi, []>;
1276 //===----------------------------------------------------------------------===//
1277 // Control Flow Instructions.
1280 let isReturn = 1, isTerminator = 1, isBarrier = 1 in {
1282 def BX_RET : AI<(outs), (ins), BrMiscFrm, IIC_Br,
1283 "bx", "\tlr", [(ARMretflag)]>,
1284 Requires<[IsARM, HasV4T]> {
1285 let Inst{27-0} = 0b0001001011111111111100011110;
1289 def MOVPCLR : AI<(outs), (ins), BrMiscFrm, IIC_Br,
1290 "mov", "\tpc, lr", [(ARMretflag)]>,
1291 Requires<[IsARM, NoV4T]> {
1292 let Inst{27-0} = 0b0001101000001111000000001110;
1296 // Indirect branches
1297 let isBranch = 1, isTerminator = 1, isBarrier = 1, isIndirectBranch = 1 in {
1299 def BX : AXI<(outs), (ins GPR:$dst), BrMiscFrm, IIC_Br, "bx\t$dst",
1300 [(brind GPR:$dst)]>,
1301 Requires<[IsARM, HasV4T]> {
1303 let Inst{31-4} = 0b1110000100101111111111110001;
1304 let Inst{3-0} = dst;
1308 // FIXME: We would really like to define this as a vanilla ARMPat like:
1309 // ARMPat<(brind GPR:$dst), (MOVr PC, GPR:$dst)>
1310 // With that, however, we can't set isBranch, isTerminator, etc..
1311 def MOVPCRX : ARMPseudoInst<(outs), (ins GPR:$dst),
1312 Size4Bytes, IIC_Br, [(brind GPR:$dst)]>,
1313 Requires<[IsARM, NoV4T]>;
1316 // All calls clobber the non-callee saved registers. SP is marked as
1317 // a use to prevent stack-pointer assignments that appear immediately
1318 // before calls from potentially appearing dead.
1320 // On non-Darwin platforms R9 is callee-saved.
1321 // FIXME: Do we really need a non-predicated version? If so, it should
1322 // at least be a pseudo instruction expanding to the predicated version
1323 // at MC lowering time.
1324 Defs = [R0, R1, R2, R3, R12, LR,
1325 D0, D1, D2, D3, D4, D5, D6, D7,
1326 D16, D17, D18, D19, D20, D21, D22, D23,
1327 D24, D25, D26, D27, D28, D29, D30, D31, CPSR, FPSCR],
1329 def BL : ABXI<0b1011, (outs), (ins bl_target:$func, variable_ops),
1330 IIC_Br, "bl\t$func",
1331 [(ARMcall tglobaladdr:$func)]>,
1332 Requires<[IsARM, IsNotDarwin]> {
1333 let Inst{31-28} = 0b1110;
1335 let Inst{23-0} = func;
1338 def BL_pred : ABI<0b1011, (outs), (ins bl_target:$func, variable_ops),
1339 IIC_Br, "bl", "\t$func",
1340 [(ARMcall_pred tglobaladdr:$func)]>,
1341 Requires<[IsARM, IsNotDarwin]> {
1343 let Inst{23-0} = func;
1347 def BLX : AXI<(outs), (ins GPR:$func, variable_ops), BrMiscFrm,
1348 IIC_Br, "blx\t$func",
1349 [(ARMcall GPR:$func)]>,
1350 Requires<[IsARM, HasV5T, IsNotDarwin]> {
1352 let Inst{31-4} = 0b1110000100101111111111110011;
1353 let Inst{3-0} = func;
1356 def BLX_pred : AI<(outs), (ins GPR:$func, variable_ops), BrMiscFrm,
1357 IIC_Br, "blx", "\t$func",
1358 [(ARMcall_pred GPR:$func)]>,
1359 Requires<[IsARM, HasV5T, IsNotDarwin]> {
1361 let Inst{27-4} = 0b000100101111111111110011;
1362 let Inst{3-0} = func;
1366 // Note: Restrict $func to the tGPR regclass to prevent it being in LR.
1367 def BX_CALL : ARMPseudoInst<(outs), (ins tGPR:$func, variable_ops),
1368 Size8Bytes, IIC_Br, [(ARMcall_nolink tGPR:$func)]>,
1369 Requires<[IsARM, HasV4T, IsNotDarwin]>;
1372 def BMOVPCRX_CALL : ARMPseudoInst<(outs), (ins tGPR:$func, variable_ops),
1373 Size8Bytes, IIC_Br, [(ARMcall_nolink tGPR:$func)]>,
1374 Requires<[IsARM, NoV4T, IsNotDarwin]>;
1378 // On Darwin R9 is call-clobbered.
1379 // R7 is marked as a use to prevent frame-pointer assignments from being
1380 // moved above / below calls.
1381 Defs = [R0, R1, R2, R3, R9, R12, LR,
1382 D0, D1, D2, D3, D4, D5, D6, D7,
1383 D16, D17, D18, D19, D20, D21, D22, D23,
1384 D24, D25, D26, D27, D28, D29, D30, D31, CPSR, FPSCR],
1385 Uses = [R7, SP] in {
1386 def BLr9 : ARMPseudoInst<(outs), (ins bltarget:$func, variable_ops),
1388 [(ARMcall tglobaladdr:$func)]>, Requires<[IsARM, IsDarwin]>;
1390 def BLr9_pred : ARMPseudoInst<(outs),
1391 (ins bltarget:$func, pred:$p, variable_ops),
1393 [(ARMcall_pred tglobaladdr:$func)]>,
1394 Requires<[IsARM, IsDarwin]>;
1397 def BLXr9 : ARMPseudoInst<(outs), (ins GPR:$func, variable_ops),
1399 [(ARMcall GPR:$func)]>, Requires<[IsARM, HasV5T, IsDarwin]>;
1401 def BLXr9_pred: ARMPseudoInst<(outs), (ins GPR:$func, pred:$p, variable_ops),
1403 [(ARMcall_pred GPR:$func)]>,
1404 Requires<[IsARM, HasV5T, IsDarwin]>;
1407 // Note: Restrict $func to the tGPR regclass to prevent it being in LR.
1408 def BXr9_CALL : ARMPseudoInst<(outs), (ins tGPR:$func, variable_ops),
1409 Size8Bytes, IIC_Br, [(ARMcall_nolink tGPR:$func)]>,
1410 Requires<[IsARM, HasV4T, IsDarwin]>;
1413 def BMOVPCRXr9_CALL : ARMPseudoInst<(outs), (ins tGPR:$func, variable_ops),
1414 Size8Bytes, IIC_Br, [(ARMcall_nolink tGPR:$func)]>,
1415 Requires<[IsARM, NoV4T, IsDarwin]>;
1420 // FIXME: The Thumb versions of these should live in ARMInstrThumb.td
1421 let isCall = 1, isTerminator = 1, isReturn = 1, isBarrier = 1 in {
1423 let Defs = [R0, R1, R2, R3, R9, R12,
1424 D0, D1, D2, D3, D4, D5, D6, D7,
1425 D16, D17, D18, D19, D20, D21, D22, D23, D24, D25, D26,
1426 D27, D28, D29, D30, D31, PC],
1428 def TCRETURNdi : PseudoInst<(outs), (ins i32imm:$dst, variable_ops),
1429 IIC_Br, []>, Requires<[IsDarwin]>;
1431 def TCRETURNri : PseudoInst<(outs), (ins tcGPR:$dst, variable_ops),
1432 IIC_Br, []>, Requires<[IsDarwin]>;
1434 def TAILJMPd : ARMPseudoInst<(outs), (ins brtarget:$dst, variable_ops),
1436 []>, Requires<[IsARM, IsDarwin]>;
1438 def tTAILJMPd: tPseudoInst<(outs), (ins brtarget:$dst, variable_ops),
1440 []>, Requires<[IsThumb, IsDarwin]>;
1442 def TAILJMPr : ARMPseudoInst<(outs), (ins tcGPR:$dst, variable_ops),
1444 []>, Requires<[IsARM, IsDarwin]>;
1446 def tTAILJMPr : tPseudoInst<(outs), (ins tcGPR:$dst, variable_ops),
1448 []>, Requires<[IsThumb, IsDarwin]>;
1451 // Non-Darwin versions (the difference is R9).
1452 let Defs = [R0, R1, R2, R3, R12,
1453 D0, D1, D2, D3, D4, D5, D6, D7,
1454 D16, D17, D18, D19, D20, D21, D22, D23, D24, D25, D26,
1455 D27, D28, D29, D30, D31, PC],
1457 def TCRETURNdiND : PseudoInst<(outs), (ins i32imm:$dst, variable_ops),
1458 IIC_Br, []>, Requires<[IsNotDarwin]>;
1460 def TCRETURNriND : PseudoInst<(outs), (ins tcGPR:$dst, variable_ops),
1461 IIC_Br, []>, Requires<[IsNotDarwin]>;
1463 def TAILJMPdND : ARMPseudoInst<(outs), (ins brtarget:$dst, variable_ops),
1465 []>, Requires<[IsARM, IsNotDarwin]>;
1467 def tTAILJMPdND : tPseudoInst<(outs), (ins brtarget:$dst, variable_ops),
1469 []>, Requires<[IsThumb, IsNotDarwin]>;
1471 def TAILJMPrND : ARMPseudoInst<(outs), (ins tcGPR:$dst, variable_ops),
1473 []>, Requires<[IsARM, IsNotDarwin]>;
1474 def tTAILJMPrND : tPseudoInst<(outs), (ins tcGPR:$dst, variable_ops),
1476 []>, Requires<[IsThumb, IsNotDarwin]>;
1480 let isBranch = 1, isTerminator = 1 in {
1481 // B is "predicable" since it's just a Bcc with an 'always' condition.
1482 let isBarrier = 1 in {
1483 let isPredicable = 1 in
1484 // FIXME: We shouldn't need this pseudo at all. Just using Bcc directly
1485 // should be sufficient.
1486 def B : ARMPseudoInst<(outs), (ins brtarget:$target), Size4Bytes, IIC_Br,
1489 let isNotDuplicable = 1, isIndirectBranch = 1 in {
1490 def BR_JTr : ARMPseudoInst<(outs),
1491 (ins GPR:$target, i32imm:$jt, i32imm:$id),
1492 SizeSpecial, IIC_Br,
1493 [(ARMbrjt GPR:$target, tjumptable:$jt, imm:$id)]>;
1494 // FIXME: This shouldn't use the generic "addrmode2," but rather be split
1495 // into i12 and rs suffixed versions.
1496 def BR_JTm : ARMPseudoInst<(outs),
1497 (ins addrmode2:$target, i32imm:$jt, i32imm:$id),
1498 SizeSpecial, IIC_Br,
1499 [(ARMbrjt (i32 (load addrmode2:$target)), tjumptable:$jt,
1501 def BR_JTadd : ARMPseudoInst<(outs),
1502 (ins GPR:$target, GPR:$idx, i32imm:$jt, i32imm:$id),
1503 SizeSpecial, IIC_Br,
1504 [(ARMbrjt (add GPR:$target, GPR:$idx), tjumptable:$jt,
1506 } // isNotDuplicable = 1, isIndirectBranch = 1
1509 // FIXME: should be able to write a pattern for ARMBrcond, but can't use
1510 // a two-value operand where a dag node expects two operands. :(
1511 def Bcc : ABI<0b1010, (outs), (ins br_target:$target),
1512 IIC_Br, "b", "\t$target",
1513 [/*(ARMbrcond bb:$target, imm:$cc, CCR:$ccr)*/]> {
1515 let Inst{23-0} = target;
1519 // BLX (immediate) -- for disassembly only
1520 def BLXi : AXI<(outs), (ins br_target:$target), BrMiscFrm, NoItinerary,
1521 "blx\t$target", [/* pattern left blank */]>,
1522 Requires<[IsARM, HasV5T]> {
1523 let Inst{31-25} = 0b1111101;
1525 let Inst{23-0} = target{24-1};
1526 let Inst{24} = target{0};
1529 // Branch and Exchange Jazelle -- for disassembly only
1530 def BXJ : ABI<0b0001, (outs), (ins GPR:$func), NoItinerary, "bxj", "\t$func",
1531 [/* For disassembly only; pattern left blank */]> {
1532 let Inst{23-20} = 0b0010;
1533 //let Inst{19-8} = 0xfff;
1534 let Inst{7-4} = 0b0010;
1537 // Secure Monitor Call is a system instruction -- for disassembly only
1538 def SMC : ABI<0b0001, (outs), (ins i32imm:$opt), NoItinerary, "smc", "\t$opt",
1539 [/* For disassembly only; pattern left blank */]> {
1541 let Inst{23-4} = 0b01100000000000000111;
1542 let Inst{3-0} = opt;
1545 // Supervisor Call (Software Interrupt) -- for disassembly only
1546 let isCall = 1, Uses = [SP] in {
1547 def SVC : ABI<0b1111, (outs), (ins i32imm:$svc), IIC_Br, "svc", "\t$svc",
1548 [/* For disassembly only; pattern left blank */]> {
1550 let Inst{23-0} = svc;
1553 def : MnemonicAlias<"swi", "svc">;
1555 // Store Return State is a system instruction -- for disassembly only
1556 let isCodeGenOnly = 1 in { // FIXME: This should not use submode!
1557 def SRSW : ABXI<{1,0,0,?}, (outs), (ins ldstm_mode:$amode, i32imm:$mode),
1558 NoItinerary, "srs${amode}\tsp!, $mode",
1559 [/* For disassembly only; pattern left blank */]> {
1560 let Inst{31-28} = 0b1111;
1561 let Inst{22-20} = 0b110; // W = 1
1562 let Inst{19-8} = 0xd05;
1563 let Inst{7-5} = 0b000;
1566 def SRS : ABXI<{1,0,0,?}, (outs), (ins ldstm_mode:$amode, i32imm:$mode),
1567 NoItinerary, "srs${amode}\tsp, $mode",
1568 [/* For disassembly only; pattern left blank */]> {
1569 let Inst{31-28} = 0b1111;
1570 let Inst{22-20} = 0b100; // W = 0
1571 let Inst{19-8} = 0xd05;
1572 let Inst{7-5} = 0b000;
1575 // Return From Exception is a system instruction -- for disassembly only
1576 def RFEW : ABXI<{1,0,0,?}, (outs), (ins ldstm_mode:$amode, GPR:$base),
1577 NoItinerary, "rfe${amode}\t$base!",
1578 [/* For disassembly only; pattern left blank */]> {
1579 let Inst{31-28} = 0b1111;
1580 let Inst{22-20} = 0b011; // W = 1
1581 let Inst{15-0} = 0x0a00;
1584 def RFE : ABXI<{1,0,0,?}, (outs), (ins ldstm_mode:$amode, GPR:$base),
1585 NoItinerary, "rfe${amode}\t$base",
1586 [/* For disassembly only; pattern left blank */]> {
1587 let Inst{31-28} = 0b1111;
1588 let Inst{22-20} = 0b001; // W = 0
1589 let Inst{15-0} = 0x0a00;
1591 } // isCodeGenOnly = 1
1593 //===----------------------------------------------------------------------===//
1594 // Load / store Instructions.
1600 defm LDR : AI_ldr1<0, "ldr", IIC_iLoad_r, IIC_iLoad_si,
1601 UnOpFrag<(load node:$Src)>>;
1602 defm LDRB : AI_ldr1<1, "ldrb", IIC_iLoad_bh_r, IIC_iLoad_bh_si,
1603 UnOpFrag<(zextloadi8 node:$Src)>>;
1604 defm STR : AI_str1<0, "str", IIC_iStore_r, IIC_iStore_si,
1605 BinOpFrag<(store node:$LHS, node:$RHS)>>;
1606 defm STRB : AI_str1<1, "strb", IIC_iStore_bh_r, IIC_iStore_bh_si,
1607 BinOpFrag<(truncstorei8 node:$LHS, node:$RHS)>>;
1609 // Special LDR for loads from non-pc-relative constpools.
1610 let canFoldAsLoad = 1, mayLoad = 1, neverHasSideEffects = 1,
1611 isReMaterializable = 1 in
1612 def LDRcp : AI2ldst<0b010, 1, 0, (outs GPR:$Rt), (ins addrmode_imm12:$addr),
1613 AddrMode_i12, LdFrm, IIC_iLoad_r, "ldr", "\t$Rt, $addr",
1617 let Inst{23} = addr{12}; // U (add = ('U' == 1))
1618 let Inst{19-16} = 0b1111;
1619 let Inst{15-12} = Rt;
1620 let Inst{11-0} = addr{11-0}; // imm12
1623 // Loads with zero extension
1624 def LDRH : AI3ld<0b1011, 1, (outs GPR:$Rt), (ins addrmode3:$addr), LdMiscFrm,
1625 IIC_iLoad_bh_r, "ldrh", "\t$Rt, $addr",
1626 [(set GPR:$Rt, (zextloadi16 addrmode3:$addr))]>;
1628 // Loads with sign extension
1629 def LDRSH : AI3ld<0b1111, 1, (outs GPR:$Rt), (ins addrmode3:$addr), LdMiscFrm,
1630 IIC_iLoad_bh_r, "ldrsh", "\t$Rt, $addr",
1631 [(set GPR:$Rt, (sextloadi16 addrmode3:$addr))]>;
1633 def LDRSB : AI3ld<0b1101, 1, (outs GPR:$Rt), (ins addrmode3:$addr), LdMiscFrm,
1634 IIC_iLoad_bh_r, "ldrsb", "\t$Rt, $addr",
1635 [(set GPR:$Rt, (sextloadi8 addrmode3:$addr))]>;
1637 let mayLoad = 1, neverHasSideEffects = 1, hasExtraDefRegAllocReq = 1 in {
1639 def LDRD : AI3ld<0b1101, 0, (outs GPR:$Rd, GPR:$dst2),
1640 (ins addrmode3:$addr), LdMiscFrm,
1641 IIC_iLoad_d_r, "ldrd", "\t$Rd, $dst2, $addr",
1642 []>, Requires<[IsARM, HasV5TE]>;
1646 multiclass AI2_ldridx<bit isByte, string opc, InstrItinClass itin> {
1647 def _PRE : AI2ldstidx<1, isByte, 1, (outs GPR:$Rt, GPR:$Rn_wb),
1648 (ins addrmode2:$addr), IndexModePre, LdFrm, itin,
1649 opc, "\t$Rt, $addr!", "$addr.base = $Rn_wb", []> {
1651 // {13} 1 == Rm, 0 == imm12
1655 let Inst{25} = addr{13};
1656 let Inst{23} = addr{12};
1657 let Inst{19-16} = addr{17-14};
1658 let Inst{11-0} = addr{11-0};
1659 let AsmMatchConverter = "CvtLdWriteBackRegAddrMode2";
1661 def _POST : AI2ldstidx<1, isByte, 0, (outs GPR:$Rt, GPR:$Rn_wb),
1662 (ins GPR:$Rn, am2offset:$offset),
1663 IndexModePost, LdFrm, itin,
1664 opc, "\t$Rt, [$Rn], $offset", "$Rn = $Rn_wb", []> {
1665 // {13} 1 == Rm, 0 == imm12
1670 let Inst{25} = offset{13};
1671 let Inst{23} = offset{12};
1672 let Inst{19-16} = Rn;
1673 let Inst{11-0} = offset{11-0};
1677 let mayLoad = 1, neverHasSideEffects = 1 in {
1678 defm LDR : AI2_ldridx<0, "ldr", IIC_iLoad_ru>;
1679 defm LDRB : AI2_ldridx<1, "ldrb", IIC_iLoad_bh_ru>;
1682 multiclass AI3_ldridx<bits<4> op, bit op20, string opc, InstrItinClass itin> {
1683 def _PRE : AI3ldstidx<op, op20, 1, 1, (outs GPR:$Rt, GPR:$Rn_wb),
1684 (ins addrmode3:$addr), IndexModePre,
1686 opc, "\t$Rt, $addr!", "$addr.base = $Rn_wb", []> {
1688 let Inst{23} = addr{8}; // U bit
1689 let Inst{22} = addr{13}; // 1 == imm8, 0 == Rm
1690 let Inst{19-16} = addr{12-9}; // Rn
1691 let Inst{11-8} = addr{7-4}; // imm7_4/zero
1692 let Inst{3-0} = addr{3-0}; // imm3_0/Rm
1694 def _POST : AI3ldstidx<op, op20, 1, 0, (outs GPR:$Rt, GPR:$Rn_wb),
1695 (ins GPR:$Rn, am3offset:$offset), IndexModePost,
1697 opc, "\t$Rt, [$Rn], $offset", "$Rn = $Rn_wb", []> {
1700 let Inst{23} = offset{8}; // U bit
1701 let Inst{22} = offset{9}; // 1 == imm8, 0 == Rm
1702 let Inst{19-16} = Rn;
1703 let Inst{11-8} = offset{7-4}; // imm7_4/zero
1704 let Inst{3-0} = offset{3-0}; // imm3_0/Rm
1708 let mayLoad = 1, neverHasSideEffects = 1 in {
1709 defm LDRH : AI3_ldridx<0b1011, 1, "ldrh", IIC_iLoad_bh_ru>;
1710 defm LDRSH : AI3_ldridx<0b1111, 1, "ldrsh", IIC_iLoad_bh_ru>;
1711 defm LDRSB : AI3_ldridx<0b1101, 1, "ldrsb", IIC_iLoad_bh_ru>;
1712 let hasExtraDefRegAllocReq = 1 in {
1713 def LDRD_PRE : AI3ldstidx<0b1101, 0, 1, 1, (outs GPR:$Rt, GPR:$Rt2, GPR:$Rn_wb),
1714 (ins addrmode3:$addr), IndexModePre,
1715 LdMiscFrm, IIC_iLoad_d_ru,
1716 "ldrd", "\t$Rt, $Rt2, $addr!",
1717 "$addr.base = $Rn_wb", []> {
1719 let Inst{23} = addr{8}; // U bit
1720 let Inst{22} = addr{13}; // 1 == imm8, 0 == Rm
1721 let Inst{19-16} = addr{12-9}; // Rn
1722 let Inst{11-8} = addr{7-4}; // imm7_4/zero
1723 let Inst{3-0} = addr{3-0}; // imm3_0/Rm
1725 def LDRD_POST: AI3ldstidx<0b1101, 0, 1, 0, (outs GPR:$Rt, GPR:$Rt2, GPR:$Rn_wb),
1726 (ins GPR:$Rn, am3offset:$offset), IndexModePost,
1727 LdMiscFrm, IIC_iLoad_d_ru,
1728 "ldrd", "\t$Rt, $Rt2, [$Rn], $offset",
1729 "$Rn = $Rn_wb", []> {
1732 let Inst{23} = offset{8}; // U bit
1733 let Inst{22} = offset{9}; // 1 == imm8, 0 == Rm
1734 let Inst{19-16} = Rn;
1735 let Inst{11-8} = offset{7-4}; // imm7_4/zero
1736 let Inst{3-0} = offset{3-0}; // imm3_0/Rm
1738 } // hasExtraDefRegAllocReq = 1
1739 } // mayLoad = 1, neverHasSideEffects = 1
1741 // LDRT, LDRBT, LDRSBT, LDRHT, LDRSHT are for disassembly only.
1742 let mayLoad = 1, neverHasSideEffects = 1 in {
1743 def LDRT : AI2ldstidx<1, 0, 0, (outs GPR:$Rt, GPR:$base_wb),
1744 (ins addrmode2:$addr), IndexModePost, LdFrm, IIC_iLoad_ru,
1745 "ldrt", "\t$Rt, $addr", "$addr.base = $base_wb", []> {
1747 // {13} 1 == Rm, 0 == imm12
1751 let Inst{25} = addr{13};
1752 let Inst{23} = addr{12};
1753 let Inst{21} = 1; // overwrite
1754 let Inst{19-16} = addr{17-14};
1755 let Inst{11-0} = addr{11-0};
1756 let AsmMatchConverter = "CvtLdWriteBackRegAddrMode2";
1758 def LDRBT : AI2ldstidx<1, 1, 0, (outs GPR:$Rt, GPR:$base_wb),
1759 (ins addrmode2:$addr), IndexModePost, LdFrm, IIC_iLoad_bh_ru,
1760 "ldrbt", "\t$Rt, $addr", "$addr.base = $base_wb", []> {
1762 // {13} 1 == Rm, 0 == imm12
1766 let Inst{25} = addr{13};
1767 let Inst{23} = addr{12};
1768 let Inst{21} = 1; // overwrite
1769 let Inst{19-16} = addr{17-14};
1770 let Inst{11-0} = addr{11-0};
1771 let AsmMatchConverter = "CvtLdWriteBackRegAddrMode2";
1773 def LDRSBT : AI3ldstidxT<0b1101, 1, 1, 0, (outs GPR:$Rt, GPR:$base_wb),
1774 (ins addrmode3:$addr), IndexModePost, LdMiscFrm, IIC_iLoad_bh_ru,
1775 "ldrsbt", "\t$Rt, $addr", "$addr.base = $base_wb", []> {
1776 let Inst{21} = 1; // overwrite
1778 def LDRHT : AI3ldstidxT<0b1011, 1, 1, 0, (outs GPR:$Rt, GPR:$base_wb),
1779 (ins addrmode3:$addr), IndexModePost, LdMiscFrm, IIC_iLoad_bh_ru,
1780 "ldrht", "\t$Rt, $addr", "$addr.base = $base_wb", []> {
1781 let Inst{21} = 1; // overwrite
1783 def LDRSHT : AI3ldstidxT<0b1111, 1, 1, 0, (outs GPR:$Rt, GPR:$base_wb),
1784 (ins addrmode3:$addr), IndexModePost, LdMiscFrm, IIC_iLoad_bh_ru,
1785 "ldrsht", "\t$Rt, $addr", "$addr.base = $base_wb", []> {
1786 let Inst{21} = 1; // overwrite
1792 // Stores with truncate
1793 def STRH : AI3str<0b1011, (outs), (ins GPR:$Rt, addrmode3:$addr), StMiscFrm,
1794 IIC_iStore_bh_r, "strh", "\t$Rt, $addr",
1795 [(truncstorei16 GPR:$Rt, addrmode3:$addr)]>;
1798 let mayStore = 1, neverHasSideEffects = 1, hasExtraSrcRegAllocReq = 1 in
1799 def STRD : AI3str<0b1111, (outs), (ins GPR:$Rt, GPR:$src2, addrmode3:$addr),
1800 StMiscFrm, IIC_iStore_d_r,
1801 "strd", "\t$Rt, $src2, $addr", []>, Requires<[IsARM, HasV5TE]>;
1804 def STR_PRE : AI2stridx<0, 1, (outs GPR:$Rn_wb),
1805 (ins GPR:$Rt, GPR:$Rn, am2offset:$offset),
1806 IndexModePre, StFrm, IIC_iStore_ru,
1807 "str", "\t$Rt, [$Rn, $offset]!",
1808 "$Rn = $Rn_wb,@earlyclobber $Rn_wb",
1810 (pre_store GPR:$Rt, GPR:$Rn, am2offset:$offset))]>;
1812 def STR_POST : AI2stridx<0, 0, (outs GPR:$Rn_wb),
1813 (ins GPR:$Rt, GPR:$Rn, am2offset:$offset),
1814 IndexModePost, StFrm, IIC_iStore_ru,
1815 "str", "\t$Rt, [$Rn], $offset",
1816 "$Rn = $Rn_wb,@earlyclobber $Rn_wb",
1818 (post_store GPR:$Rt, GPR:$Rn, am2offset:$offset))]>;
1820 def STRB_PRE : AI2stridx<1, 1, (outs GPR:$Rn_wb),
1821 (ins GPR:$Rt, GPR:$Rn, am2offset:$offset),
1822 IndexModePre, StFrm, IIC_iStore_bh_ru,
1823 "strb", "\t$Rt, [$Rn, $offset]!",
1824 "$Rn = $Rn_wb,@earlyclobber $Rn_wb",
1825 [(set GPR:$Rn_wb, (pre_truncsti8 GPR:$Rt,
1826 GPR:$Rn, am2offset:$offset))]>;
1827 def STRB_POST: AI2stridx<1, 0, (outs GPR:$Rn_wb),
1828 (ins GPR:$Rt, GPR:$Rn, am2offset:$offset),
1829 IndexModePost, StFrm, IIC_iStore_bh_ru,
1830 "strb", "\t$Rt, [$Rn], $offset",
1831 "$Rn = $Rn_wb,@earlyclobber $Rn_wb",
1832 [(set GPR:$Rn_wb, (post_truncsti8 GPR:$Rt,
1833 GPR:$Rn, am2offset:$offset))]>;
1835 def STRH_PRE : AI3stridx<0b1011, 0, 1, (outs GPR:$Rn_wb),
1836 (ins GPR:$Rt, GPR:$Rn, am3offset:$offset),
1837 IndexModePre, StMiscFrm, IIC_iStore_ru,
1838 "strh", "\t$Rt, [$Rn, $offset]!",
1839 "$Rn = $Rn_wb,@earlyclobber $Rn_wb",
1841 (pre_truncsti16 GPR:$Rt, GPR:$Rn, am3offset:$offset))]>;
1843 def STRH_POST: AI3stridx<0b1011, 0, 0, (outs GPR:$Rn_wb),
1844 (ins GPR:$Rt, GPR:$Rn, am3offset:$offset),
1845 IndexModePost, StMiscFrm, IIC_iStore_bh_ru,
1846 "strh", "\t$Rt, [$Rn], $offset",
1847 "$Rn = $Rn_wb,@earlyclobber $Rn_wb",
1848 [(set GPR:$Rn_wb, (post_truncsti16 GPR:$Rt,
1849 GPR:$Rn, am3offset:$offset))]>;
1851 // For disassembly only
1852 let mayStore = 1, neverHasSideEffects = 1, hasExtraSrcRegAllocReq = 1 in {
1853 def STRD_PRE : AI3stdpr<(outs GPR:$base_wb),
1854 (ins GPR:$src1, GPR:$src2, GPR:$base, am3offset:$offset),
1855 StMiscFrm, IIC_iStore_d_ru,
1856 "strd", "\t$src1, $src2, [$base, $offset]!",
1857 "$base = $base_wb", []>;
1859 // For disassembly only
1860 def STRD_POST: AI3stdpo<(outs GPR:$base_wb),
1861 (ins GPR:$src1, GPR:$src2, GPR:$base, am3offset:$offset),
1862 StMiscFrm, IIC_iStore_d_ru,
1863 "strd", "\t$src1, $src2, [$base], $offset",
1864 "$base = $base_wb", []>;
1865 } // mayStore = 1, neverHasSideEffects = 1, hasExtraSrcRegAllocReq = 1
1867 // STRT, STRBT, and STRHT are for disassembly only.
1869 def STRT : AI2stridxT<0, 0, (outs GPR:$Rn_wb), (ins GPR:$Rt, addrmode2:$addr),
1870 IndexModePost, StFrm, IIC_iStore_ru,
1871 "strt", "\t$Rt, $addr", "$addr.base = $Rn_wb",
1872 [/* For disassembly only; pattern left blank */]> {
1873 let Inst{21} = 1; // overwrite
1874 let AsmMatchConverter = "CvtStWriteBackRegAddrMode2";
1877 def STRBT : AI2stridxT<1, 0, (outs GPR:$Rn_wb), (ins GPR:$Rt, addrmode2:$addr),
1878 IndexModePost, StFrm, IIC_iStore_bh_ru,
1879 "strbt", "\t$Rt, $addr", "$addr.base = $Rn_wb",
1880 [/* For disassembly only; pattern left blank */]> {
1881 let Inst{21} = 1; // overwrite
1882 let AsmMatchConverter = "CvtStWriteBackRegAddrMode2";
1885 def STRHT: AI3sthpo<(outs GPR:$base_wb), (ins GPR:$Rt, addrmode3:$addr),
1886 StMiscFrm, IIC_iStore_bh_ru,
1887 "strht", "\t$Rt, $addr", "$addr.base = $base_wb",
1888 [/* For disassembly only; pattern left blank */]> {
1889 let Inst{21} = 1; // overwrite
1890 let AsmMatchConverter = "CvtStWriteBackRegAddrMode3";
1893 //===----------------------------------------------------------------------===//
1894 // Load / store multiple Instructions.
1897 multiclass arm_ldst_mult<string asm, bit L_bit, Format f,
1898 InstrItinClass itin, InstrItinClass itin_upd> {
1900 AXI4<(outs), (ins GPR:$Rn, pred:$p, reglist:$regs, variable_ops),
1901 IndexModeNone, f, itin,
1902 !strconcat(asm, "ia${p}\t$Rn, $regs"), "", []> {
1903 let Inst{24-23} = 0b01; // Increment After
1904 let Inst{21} = 0; // No writeback
1905 let Inst{20} = L_bit;
1908 AXI4<(outs GPR:$wb), (ins GPR:$Rn, pred:$p, reglist:$regs, variable_ops),
1909 IndexModeUpd, f, itin_upd,
1910 !strconcat(asm, "ia${p}\t$Rn!, $regs"), "$Rn = $wb", []> {
1911 let Inst{24-23} = 0b01; // Increment After
1912 let Inst{21} = 1; // Writeback
1913 let Inst{20} = L_bit;
1916 AXI4<(outs), (ins GPR:$Rn, pred:$p, reglist:$regs, variable_ops),
1917 IndexModeNone, f, itin,
1918 !strconcat(asm, "da${p}\t$Rn, $regs"), "", []> {
1919 let Inst{24-23} = 0b00; // Decrement After
1920 let Inst{21} = 0; // No writeback
1921 let Inst{20} = L_bit;
1924 AXI4<(outs GPR:$wb), (ins GPR:$Rn, pred:$p, reglist:$regs, variable_ops),
1925 IndexModeUpd, f, itin_upd,
1926 !strconcat(asm, "da${p}\t$Rn!, $regs"), "$Rn = $wb", []> {
1927 let Inst{24-23} = 0b00; // Decrement After
1928 let Inst{21} = 1; // Writeback
1929 let Inst{20} = L_bit;
1932 AXI4<(outs), (ins GPR:$Rn, pred:$p, reglist:$regs, variable_ops),
1933 IndexModeNone, f, itin,
1934 !strconcat(asm, "db${p}\t$Rn, $regs"), "", []> {
1935 let Inst{24-23} = 0b10; // Decrement Before
1936 let Inst{21} = 0; // No writeback
1937 let Inst{20} = L_bit;
1940 AXI4<(outs GPR:$wb), (ins GPR:$Rn, pred:$p, reglist:$regs, variable_ops),
1941 IndexModeUpd, f, itin_upd,
1942 !strconcat(asm, "db${p}\t$Rn!, $regs"), "$Rn = $wb", []> {
1943 let Inst{24-23} = 0b10; // Decrement Before
1944 let Inst{21} = 1; // Writeback
1945 let Inst{20} = L_bit;
1948 AXI4<(outs), (ins GPR:$Rn, pred:$p, reglist:$regs, variable_ops),
1949 IndexModeNone, f, itin,
1950 !strconcat(asm, "ib${p}\t$Rn, $regs"), "", []> {
1951 let Inst{24-23} = 0b11; // Increment Before
1952 let Inst{21} = 0; // No writeback
1953 let Inst{20} = L_bit;
1956 AXI4<(outs GPR:$wb), (ins GPR:$Rn, pred:$p, reglist:$regs, variable_ops),
1957 IndexModeUpd, f, itin_upd,
1958 !strconcat(asm, "ib${p}\t$Rn!, $regs"), "$Rn = $wb", []> {
1959 let Inst{24-23} = 0b11; // Increment Before
1960 let Inst{21} = 1; // Writeback
1961 let Inst{20} = L_bit;
1965 let neverHasSideEffects = 1 in {
1967 let mayLoad = 1, hasExtraDefRegAllocReq = 1 in
1968 defm LDM : arm_ldst_mult<"ldm", 1, LdStMulFrm, IIC_iLoad_m, IIC_iLoad_mu>;
1970 let mayStore = 1, hasExtraSrcRegAllocReq = 1 in
1971 defm STM : arm_ldst_mult<"stm", 0, LdStMulFrm, IIC_iStore_m, IIC_iStore_mu>;
1973 } // neverHasSideEffects
1975 // Load / Store Multiple Mnemonic Aliases
1976 def : MnemonicAlias<"ldm", "ldmia">;
1977 def : MnemonicAlias<"stm", "stmia">;
1979 // FIXME: remove when we have a way to marking a MI with these properties.
1980 // FIXME: Should pc be an implicit operand like PICADD, etc?
1981 let isReturn = 1, isTerminator = 1, isBarrier = 1, mayLoad = 1,
1982 hasExtraDefRegAllocReq = 1, isCodeGenOnly = 1 in
1983 def LDMIA_RET : ARMPseudoInst<(outs GPR:$wb), (ins GPR:$Rn, pred:$p,
1984 reglist:$regs, variable_ops),
1985 Size4Bytes, IIC_iLoad_mBr, []>,
1986 RegConstraint<"$Rn = $wb">;
1988 //===----------------------------------------------------------------------===//
1989 // Move Instructions.
1992 let neverHasSideEffects = 1 in
1993 def MOVr : AsI1<0b1101, (outs GPR:$Rd), (ins GPR:$Rm), DPFrm, IIC_iMOVr,
1994 "mov", "\t$Rd, $Rm", []>, UnaryDP {
1998 let Inst{19-16} = 0b0000;
1999 let Inst{11-4} = 0b00000000;
2002 let Inst{15-12} = Rd;
2005 // A version for the smaller set of tail call registers.
2006 let neverHasSideEffects = 1 in
2007 def MOVr_TC : AsI1<0b1101, (outs tcGPR:$Rd), (ins tcGPR:$Rm), DPFrm,
2008 IIC_iMOVr, "mov", "\t$Rd, $Rm", []>, UnaryDP {
2012 let Inst{11-4} = 0b00000000;
2015 let Inst{15-12} = Rd;
2018 def MOVs : AsI1<0b1101, (outs GPR:$Rd), (ins shift_so_reg:$src),
2019 DPSoRegFrm, IIC_iMOVsr,
2020 "mov", "\t$Rd, $src", [(set GPR:$Rd, shift_so_reg:$src)]>,
2024 let Inst{15-12} = Rd;
2025 let Inst{19-16} = 0b0000;
2026 let Inst{11-0} = src;
2030 let isReMaterializable = 1, isAsCheapAsAMove = 1, isMoveImm = 1 in
2031 def MOVi : AsI1<0b1101, (outs GPR:$Rd), (ins so_imm:$imm), DPFrm, IIC_iMOVi,
2032 "mov", "\t$Rd, $imm", [(set GPR:$Rd, so_imm:$imm)]>, UnaryDP {
2036 let Inst{15-12} = Rd;
2037 let Inst{19-16} = 0b0000;
2038 let Inst{11-0} = imm;
2041 let isReMaterializable = 1, isAsCheapAsAMove = 1, isMoveImm = 1 in
2042 def MOVi16 : AI1<0b1000, (outs GPR:$Rd), (ins i32imm_hilo16:$imm),
2044 "movw", "\t$Rd, $imm",
2045 [(set GPR:$Rd, imm0_65535:$imm)]>,
2046 Requires<[IsARM, HasV6T2]>, UnaryDP {
2049 let Inst{15-12} = Rd;
2050 let Inst{11-0} = imm{11-0};
2051 let Inst{19-16} = imm{15-12};
2056 def MOVi16_ga_pcrel : PseudoInst<(outs GPR:$Rd),
2057 (ins i32imm:$addr, pclabel:$id), IIC_iMOVi, []>;
2059 let Constraints = "$src = $Rd" in {
2060 def MOVTi16 : AI1<0b1010, (outs GPR:$Rd), (ins GPR:$src, i32imm_hilo16:$imm),
2062 "movt", "\t$Rd, $imm",
2064 (or (and GPR:$src, 0xffff),
2065 lo16AllZero:$imm))]>, UnaryDP,
2066 Requires<[IsARM, HasV6T2]> {
2069 let Inst{15-12} = Rd;
2070 let Inst{11-0} = imm{11-0};
2071 let Inst{19-16} = imm{15-12};
2076 def MOVTi16_ga_pcrel : PseudoInst<(outs GPR:$Rd),
2077 (ins GPR:$src, i32imm:$addr, pclabel:$id), IIC_iMOVi, []>;
2081 def : ARMPat<(or GPR:$src, 0xffff0000), (MOVTi16 GPR:$src, 0xffff)>,
2082 Requires<[IsARM, HasV6T2]>;
2084 let Uses = [CPSR] in
2085 def RRX: PseudoInst<(outs GPR:$Rd), (ins GPR:$Rm), IIC_iMOVsi,
2086 [(set GPR:$Rd, (ARMrrx GPR:$Rm))]>, UnaryDP,
2089 // These aren't really mov instructions, but we have to define them this way
2090 // due to flag operands.
2092 let Defs = [CPSR] in {
2093 def MOVsrl_flag : PseudoInst<(outs GPR:$dst), (ins GPR:$src), IIC_iMOVsi,
2094 [(set GPR:$dst, (ARMsrl_flag GPR:$src))]>, UnaryDP,
2096 def MOVsra_flag : PseudoInst<(outs GPR:$dst), (ins GPR:$src), IIC_iMOVsi,
2097 [(set GPR:$dst, (ARMsra_flag GPR:$src))]>, UnaryDP,
2101 //===----------------------------------------------------------------------===//
2102 // Extend Instructions.
2107 defm SXTB : AI_ext_rrot<0b01101010,
2108 "sxtb", UnOpFrag<(sext_inreg node:$Src, i8)>>;
2109 defm SXTH : AI_ext_rrot<0b01101011,
2110 "sxth", UnOpFrag<(sext_inreg node:$Src, i16)>>;
2112 defm SXTAB : AI_exta_rrot<0b01101010,
2113 "sxtab", BinOpFrag<(add node:$LHS, (sext_inreg node:$RHS, i8))>>;
2114 defm SXTAH : AI_exta_rrot<0b01101011,
2115 "sxtah", BinOpFrag<(add node:$LHS, (sext_inreg node:$RHS,i16))>>;
2117 // For disassembly only
2118 defm SXTB16 : AI_ext_rrot_np<0b01101000, "sxtb16">;
2120 // For disassembly only
2121 defm SXTAB16 : AI_exta_rrot_np<0b01101000, "sxtab16">;
2125 let AddedComplexity = 16 in {
2126 defm UXTB : AI_ext_rrot<0b01101110,
2127 "uxtb" , UnOpFrag<(and node:$Src, 0x000000FF)>>;
2128 defm UXTH : AI_ext_rrot<0b01101111,
2129 "uxth" , UnOpFrag<(and node:$Src, 0x0000FFFF)>>;
2130 defm UXTB16 : AI_ext_rrot<0b01101100,
2131 "uxtb16", UnOpFrag<(and node:$Src, 0x00FF00FF)>>;
2133 // FIXME: This pattern incorrectly assumes the shl operator is a rotate.
2134 // The transformation should probably be done as a combiner action
2135 // instead so we can include a check for masking back in the upper
2136 // eight bits of the source into the lower eight bits of the result.
2137 //def : ARMV6Pat<(and (shl GPR:$Src, (i32 8)), 0xFF00FF),
2138 // (UXTB16r_rot GPR:$Src, 24)>;
2139 def : ARMV6Pat<(and (srl GPR:$Src, (i32 8)), 0xFF00FF),
2140 (UXTB16r_rot GPR:$Src, 8)>;
2142 defm UXTAB : AI_exta_rrot<0b01101110, "uxtab",
2143 BinOpFrag<(add node:$LHS, (and node:$RHS, 0x00FF))>>;
2144 defm UXTAH : AI_exta_rrot<0b01101111, "uxtah",
2145 BinOpFrag<(add node:$LHS, (and node:$RHS, 0xFFFF))>>;
2148 // This isn't safe in general, the add is two 16-bit units, not a 32-bit add.
2149 // For disassembly only
2150 defm UXTAB16 : AI_exta_rrot_np<0b01101100, "uxtab16">;
2153 def SBFX : I<(outs GPR:$Rd),
2154 (ins GPR:$Rn, imm0_31:$lsb, imm0_31_m1:$width),
2155 AddrMode1, Size4Bytes, IndexModeNone, DPFrm, IIC_iUNAsi,
2156 "sbfx", "\t$Rd, $Rn, $lsb, $width", "", []>,
2157 Requires<[IsARM, HasV6T2]> {
2162 let Inst{27-21} = 0b0111101;
2163 let Inst{6-4} = 0b101;
2164 let Inst{20-16} = width;
2165 let Inst{15-12} = Rd;
2166 let Inst{11-7} = lsb;
2170 def UBFX : I<(outs GPR:$Rd),
2171 (ins GPR:$Rn, imm0_31:$lsb, imm0_31_m1:$width),
2172 AddrMode1, Size4Bytes, IndexModeNone, DPFrm, IIC_iUNAsi,
2173 "ubfx", "\t$Rd, $Rn, $lsb, $width", "", []>,
2174 Requires<[IsARM, HasV6T2]> {
2179 let Inst{27-21} = 0b0111111;
2180 let Inst{6-4} = 0b101;
2181 let Inst{20-16} = width;
2182 let Inst{15-12} = Rd;
2183 let Inst{11-7} = lsb;
2187 //===----------------------------------------------------------------------===//
2188 // Arithmetic Instructions.
2191 defm ADD : AsI1_bin_irs<0b0100, "add",
2192 IIC_iALUi, IIC_iALUr, IIC_iALUsr,
2193 BinOpFrag<(add node:$LHS, node:$RHS)>, 1>;
2194 defm SUB : AsI1_bin_irs<0b0010, "sub",
2195 IIC_iALUi, IIC_iALUr, IIC_iALUsr,
2196 BinOpFrag<(sub node:$LHS, node:$RHS)>>;
2198 // ADD and SUB with 's' bit set.
2199 defm ADDS : AI1_bin_s_irs<0b0100, "adds",
2200 IIC_iALUi, IIC_iALUr, IIC_iALUsr,
2201 BinOpFrag<(addc node:$LHS, node:$RHS)>, 1>;
2202 defm SUBS : AI1_bin_s_irs<0b0010, "subs",
2203 IIC_iALUi, IIC_iALUr, IIC_iALUsr,
2204 BinOpFrag<(subc node:$LHS, node:$RHS)>>;
2206 defm ADC : AI1_adde_sube_irs<0b0101, "adc",
2207 BinOpFrag<(adde_dead_carry node:$LHS, node:$RHS)>, 1>;
2208 defm SBC : AI1_adde_sube_irs<0b0110, "sbc",
2209 BinOpFrag<(sube_dead_carry node:$LHS, node:$RHS)>>;
2211 // ADC and SUBC with 's' bit set.
2212 let usesCustomInserter = 1 in {
2213 defm ADCS : AI1_adde_sube_s_irs<
2214 BinOpFrag<(adde_live_carry node:$LHS, node:$RHS)>, 1>;
2215 defm SBCS : AI1_adde_sube_s_irs<
2216 BinOpFrag<(sube_live_carry node:$LHS, node:$RHS) >>;
2219 def RSBri : AsI1<0b0011, (outs GPR:$Rd), (ins GPR:$Rn, so_imm:$imm), DPFrm,
2220 IIC_iALUi, "rsb", "\t$Rd, $Rn, $imm",
2221 [(set GPR:$Rd, (sub so_imm:$imm, GPR:$Rn))]> {
2226 let Inst{15-12} = Rd;
2227 let Inst{19-16} = Rn;
2228 let Inst{11-0} = imm;
2231 // The reg/reg form is only defined for the disassembler; for codegen it is
2232 // equivalent to SUBrr.
2233 def RSBrr : AsI1<0b0011, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm), DPFrm,
2234 IIC_iALUr, "rsb", "\t$Rd, $Rn, $Rm",
2235 [/* For disassembly only; pattern left blank */]> {
2239 let Inst{11-4} = 0b00000000;
2242 let Inst{15-12} = Rd;
2243 let Inst{19-16} = Rn;
2246 def RSBrs : AsI1<0b0011, (outs GPR:$Rd), (ins GPR:$Rn, so_reg:$shift),
2247 DPSoRegFrm, IIC_iALUsr, "rsb", "\t$Rd, $Rn, $shift",
2248 [(set GPR:$Rd, (sub so_reg:$shift, GPR:$Rn))]> {
2253 let Inst{11-0} = shift;
2254 let Inst{15-12} = Rd;
2255 let Inst{19-16} = Rn;
2258 // RSB with 's' bit set.
2259 // NOTE: CPSR def omitted because it will be handled by the custom inserter.
2260 let usesCustomInserter = 1 in {
2261 def RSBSri : ARMPseudoInst<(outs GPR:$Rd), (ins GPR:$Rn, so_imm:$imm),
2262 Size4Bytes, IIC_iALUi,
2263 [(set GPR:$Rd, (subc so_imm:$imm, GPR:$Rn))]>;
2264 def RSBSrr : ARMPseudoInst<(outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm),
2265 Size4Bytes, IIC_iALUr,
2266 [/* For disassembly only; pattern left blank */]>;
2267 def RSBSrs : ARMPseudoInst<(outs GPR:$Rd), (ins GPR:$Rn, so_reg:$shift),
2268 Size4Bytes, IIC_iALUsr,
2269 [(set GPR:$Rd, (subc so_reg:$shift, GPR:$Rn))]>;
2272 let Uses = [CPSR] in {
2273 def RSCri : AsI1<0b0111, (outs GPR:$Rd), (ins GPR:$Rn, so_imm:$imm),
2274 DPFrm, IIC_iALUi, "rsc", "\t$Rd, $Rn, $imm",
2275 [(set GPR:$Rd, (sube_dead_carry so_imm:$imm, GPR:$Rn))]>,
2281 let Inst{15-12} = Rd;
2282 let Inst{19-16} = Rn;
2283 let Inst{11-0} = imm;
2285 // The reg/reg form is only defined for the disassembler; for codegen it is
2286 // equivalent to SUBrr.
2287 def RSCrr : AsI1<0b0111, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm),
2288 DPFrm, IIC_iALUr, "rsc", "\t$Rd, $Rn, $Rm",
2289 [/* For disassembly only; pattern left blank */]> {
2293 let Inst{11-4} = 0b00000000;
2296 let Inst{15-12} = Rd;
2297 let Inst{19-16} = Rn;
2299 def RSCrs : AsI1<0b0111, (outs GPR:$Rd), (ins GPR:$Rn, so_reg:$shift),
2300 DPSoRegFrm, IIC_iALUsr, "rsc", "\t$Rd, $Rn, $shift",
2301 [(set GPR:$Rd, (sube_dead_carry so_reg:$shift, GPR:$Rn))]>,
2307 let Inst{11-0} = shift;
2308 let Inst{15-12} = Rd;
2309 let Inst{19-16} = Rn;
2313 // NOTE: CPSR def omitted because it will be handled by the custom inserter.
2314 let usesCustomInserter = 1, Uses = [CPSR] in {
2315 def RSCSri : ARMPseudoInst<(outs GPR:$Rd), (ins GPR:$Rn, so_imm:$imm),
2316 Size4Bytes, IIC_iALUi,
2317 [(set GPR:$Rd, (sube_dead_carry so_imm:$imm, GPR:$Rn))]>;
2318 def RSCSrs : ARMPseudoInst<(outs GPR:$Rd), (ins GPR:$Rn, so_reg:$shift),
2319 Size4Bytes, IIC_iALUsr,
2320 [(set GPR:$Rd, (sube_dead_carry so_reg:$shift, GPR:$Rn))]>;
2323 // (sub X, imm) gets canonicalized to (add X, -imm). Match this form.
2324 // The assume-no-carry-in form uses the negation of the input since add/sub
2325 // assume opposite meanings of the carry flag (i.e., carry == !borrow).
2326 // See the definition of AddWithCarry() in the ARM ARM A2.2.1 for the gory
2328 def : ARMPat<(add GPR:$src, so_imm_neg:$imm),
2329 (SUBri GPR:$src, so_imm_neg:$imm)>;
2330 def : ARMPat<(addc GPR:$src, so_imm_neg:$imm),
2331 (SUBSri GPR:$src, so_imm_neg:$imm)>;
2332 // The with-carry-in form matches bitwise not instead of the negation.
2333 // Effectively, the inverse interpretation of the carry flag already accounts
2334 // for part of the negation.
2335 def : ARMPat<(adde_dead_carry GPR:$src, so_imm_not:$imm),
2336 (SBCri GPR:$src, so_imm_not:$imm)>;
2337 def : ARMPat<(adde_live_carry GPR:$src, so_imm_not:$imm),
2338 (SBCSri GPR:$src, so_imm_not:$imm)>;
2340 // Note: These are implemented in C++ code, because they have to generate
2341 // ADD/SUBrs instructions, which use a complex pattern that a xform function
2343 // (mul X, 2^n+1) -> (add (X << n), X)
2344 // (mul X, 2^n-1) -> (rsb X, (X << n))
2346 // ARM Arithmetic Instruction -- for disassembly only
2347 // GPR:$dst = GPR:$a op GPR:$b
2348 class AAI<bits<8> op27_20, bits<8> op11_4, string opc,
2349 list<dag> pattern = [/* For disassembly only; pattern left blank */],
2350 dag iops = (ins GPR:$Rn, GPR:$Rm), string asm = "\t$Rd, $Rn, $Rm">
2351 : AI<(outs GPR:$Rd), iops, DPFrm, IIC_iALUr, opc, asm, pattern> {
2355 let Inst{27-20} = op27_20;
2356 let Inst{11-4} = op11_4;
2357 let Inst{19-16} = Rn;
2358 let Inst{15-12} = Rd;
2362 // Saturating add/subtract -- for disassembly only
2364 def QADD : AAI<0b00010000, 0b00000101, "qadd",
2365 [(set GPR:$Rd, (int_arm_qadd GPR:$Rm, GPR:$Rn))],
2366 (ins GPR:$Rm, GPR:$Rn), "\t$Rd, $Rm, $Rn">;
2367 def QSUB : AAI<0b00010010, 0b00000101, "qsub",
2368 [(set GPR:$Rd, (int_arm_qsub GPR:$Rm, GPR:$Rn))],
2369 (ins GPR:$Rm, GPR:$Rn), "\t$Rd, $Rm, $Rn">;
2370 def QDADD : AAI<0b00010100, 0b00000101, "qdadd", [], (ins GPR:$Rm, GPR:$Rn),
2372 def QDSUB : AAI<0b00010110, 0b00000101, "qdsub", [], (ins GPR:$Rm, GPR:$Rn),
2375 def QADD16 : AAI<0b01100010, 0b11110001, "qadd16">;
2376 def QADD8 : AAI<0b01100010, 0b11111001, "qadd8">;
2377 def QASX : AAI<0b01100010, 0b11110011, "qasx">;
2378 def QSAX : AAI<0b01100010, 0b11110101, "qsax">;
2379 def QSUB16 : AAI<0b01100010, 0b11110111, "qsub16">;
2380 def QSUB8 : AAI<0b01100010, 0b11111111, "qsub8">;
2381 def UQADD16 : AAI<0b01100110, 0b11110001, "uqadd16">;
2382 def UQADD8 : AAI<0b01100110, 0b11111001, "uqadd8">;
2383 def UQASX : AAI<0b01100110, 0b11110011, "uqasx">;
2384 def UQSAX : AAI<0b01100110, 0b11110101, "uqsax">;
2385 def UQSUB16 : AAI<0b01100110, 0b11110111, "uqsub16">;
2386 def UQSUB8 : AAI<0b01100110, 0b11111111, "uqsub8">;
2388 // Signed/Unsigned add/subtract -- for disassembly only
2390 def SASX : AAI<0b01100001, 0b11110011, "sasx">;
2391 def SADD16 : AAI<0b01100001, 0b11110001, "sadd16">;
2392 def SADD8 : AAI<0b01100001, 0b11111001, "sadd8">;
2393 def SSAX : AAI<0b01100001, 0b11110101, "ssax">;
2394 def SSUB16 : AAI<0b01100001, 0b11110111, "ssub16">;
2395 def SSUB8 : AAI<0b01100001, 0b11111111, "ssub8">;
2396 def UASX : AAI<0b01100101, 0b11110011, "uasx">;
2397 def UADD16 : AAI<0b01100101, 0b11110001, "uadd16">;
2398 def UADD8 : AAI<0b01100101, 0b11111001, "uadd8">;
2399 def USAX : AAI<0b01100101, 0b11110101, "usax">;
2400 def USUB16 : AAI<0b01100101, 0b11110111, "usub16">;
2401 def USUB8 : AAI<0b01100101, 0b11111111, "usub8">;
2403 // Signed/Unsigned halving add/subtract -- for disassembly only
2405 def SHASX : AAI<0b01100011, 0b11110011, "shasx">;
2406 def SHADD16 : AAI<0b01100011, 0b11110001, "shadd16">;
2407 def SHADD8 : AAI<0b01100011, 0b11111001, "shadd8">;
2408 def SHSAX : AAI<0b01100011, 0b11110101, "shsax">;
2409 def SHSUB16 : AAI<0b01100011, 0b11110111, "shsub16">;
2410 def SHSUB8 : AAI<0b01100011, 0b11111111, "shsub8">;
2411 def UHASX : AAI<0b01100111, 0b11110011, "uhasx">;
2412 def UHADD16 : AAI<0b01100111, 0b11110001, "uhadd16">;
2413 def UHADD8 : AAI<0b01100111, 0b11111001, "uhadd8">;
2414 def UHSAX : AAI<0b01100111, 0b11110101, "uhsax">;
2415 def UHSUB16 : AAI<0b01100111, 0b11110111, "uhsub16">;
2416 def UHSUB8 : AAI<0b01100111, 0b11111111, "uhsub8">;
2418 // Unsigned Sum of Absolute Differences [and Accumulate] -- for disassembly only
2420 def USAD8 : AI<(outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm),
2421 MulFrm /* for convenience */, NoItinerary, "usad8",
2422 "\t$Rd, $Rn, $Rm", []>,
2423 Requires<[IsARM, HasV6]> {
2427 let Inst{27-20} = 0b01111000;
2428 let Inst{15-12} = 0b1111;
2429 let Inst{7-4} = 0b0001;
2430 let Inst{19-16} = Rd;
2431 let Inst{11-8} = Rm;
2434 def USADA8 : AI<(outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm, GPR:$Ra),
2435 MulFrm /* for convenience */, NoItinerary, "usada8",
2436 "\t$Rd, $Rn, $Rm, $Ra", []>,
2437 Requires<[IsARM, HasV6]> {
2442 let Inst{27-20} = 0b01111000;
2443 let Inst{7-4} = 0b0001;
2444 let Inst{19-16} = Rd;
2445 let Inst{15-12} = Ra;
2446 let Inst{11-8} = Rm;
2450 // Signed/Unsigned saturate -- for disassembly only
2452 def SSAT : AI<(outs GPR:$Rd), (ins i32imm:$sat_imm, GPR:$a, shift_imm:$sh),
2453 SatFrm, NoItinerary, "ssat", "\t$Rd, $sat_imm, $a$sh",
2454 [/* For disassembly only; pattern left blank */]> {
2459 let Inst{27-21} = 0b0110101;
2460 let Inst{5-4} = 0b01;
2461 let Inst{20-16} = sat_imm;
2462 let Inst{15-12} = Rd;
2463 let Inst{11-7} = sh{7-3};
2464 let Inst{6} = sh{0};
2468 def SSAT16 : AI<(outs GPR:$Rd), (ins i32imm:$sat_imm, GPR:$Rn), SatFrm,
2469 NoItinerary, "ssat16", "\t$Rd, $sat_imm, $Rn",
2470 [/* For disassembly only; pattern left blank */]> {
2474 let Inst{27-20} = 0b01101010;
2475 let Inst{11-4} = 0b11110011;
2476 let Inst{15-12} = Rd;
2477 let Inst{19-16} = sat_imm;
2481 def USAT : AI<(outs GPR:$Rd), (ins i32imm:$sat_imm, GPR:$a, shift_imm:$sh),
2482 SatFrm, NoItinerary, "usat", "\t$Rd, $sat_imm, $a$sh",
2483 [/* For disassembly only; pattern left blank */]> {
2488 let Inst{27-21} = 0b0110111;
2489 let Inst{5-4} = 0b01;
2490 let Inst{15-12} = Rd;
2491 let Inst{11-7} = sh{7-3};
2492 let Inst{6} = sh{0};
2493 let Inst{20-16} = sat_imm;
2497 def USAT16 : AI<(outs GPR:$Rd), (ins i32imm:$sat_imm, GPR:$a), SatFrm,
2498 NoItinerary, "usat16", "\t$Rd, $sat_imm, $a",
2499 [/* For disassembly only; pattern left blank */]> {
2503 let Inst{27-20} = 0b01101110;
2504 let Inst{11-4} = 0b11110011;
2505 let Inst{15-12} = Rd;
2506 let Inst{19-16} = sat_imm;
2510 def : ARMV6Pat<(int_arm_ssat GPR:$a, imm:$pos), (SSAT imm:$pos, GPR:$a, 0)>;
2511 def : ARMV6Pat<(int_arm_usat GPR:$a, imm:$pos), (USAT imm:$pos, GPR:$a, 0)>;
2513 //===----------------------------------------------------------------------===//
2514 // Bitwise Instructions.
2517 defm AND : AsI1_bin_irs<0b0000, "and",
2518 IIC_iBITi, IIC_iBITr, IIC_iBITsr,
2519 BinOpFrag<(and node:$LHS, node:$RHS)>, 1>;
2520 defm ORR : AsI1_bin_irs<0b1100, "orr",
2521 IIC_iBITi, IIC_iBITr, IIC_iBITsr,
2522 BinOpFrag<(or node:$LHS, node:$RHS)>, 1>;
2523 defm EOR : AsI1_bin_irs<0b0001, "eor",
2524 IIC_iBITi, IIC_iBITr, IIC_iBITsr,
2525 BinOpFrag<(xor node:$LHS, node:$RHS)>, 1>;
2526 defm BIC : AsI1_bin_irs<0b1110, "bic",
2527 IIC_iBITi, IIC_iBITr, IIC_iBITsr,
2528 BinOpFrag<(and node:$LHS, (not node:$RHS))>>;
2530 def BFC : I<(outs GPR:$Rd), (ins GPR:$src, bf_inv_mask_imm:$imm),
2531 AddrMode1, Size4Bytes, IndexModeNone, DPFrm, IIC_iUNAsi,
2532 "bfc", "\t$Rd, $imm", "$src = $Rd",
2533 [(set GPR:$Rd, (and GPR:$src, bf_inv_mask_imm:$imm))]>,
2534 Requires<[IsARM, HasV6T2]> {
2537 let Inst{27-21} = 0b0111110;
2538 let Inst{6-0} = 0b0011111;
2539 let Inst{15-12} = Rd;
2540 let Inst{11-7} = imm{4-0}; // lsb
2541 let Inst{20-16} = imm{9-5}; // width
2544 // A8.6.18 BFI - Bitfield insert (Encoding A1)
2545 def BFI : I<(outs GPR:$Rd), (ins GPR:$src, GPR:$Rn, bf_inv_mask_imm:$imm),
2546 AddrMode1, Size4Bytes, IndexModeNone, DPFrm, IIC_iUNAsi,
2547 "bfi", "\t$Rd, $Rn, $imm", "$src = $Rd",
2548 [(set GPR:$Rd, (ARMbfi GPR:$src, GPR:$Rn,
2549 bf_inv_mask_imm:$imm))]>,
2550 Requires<[IsARM, HasV6T2]> {
2554 let Inst{27-21} = 0b0111110;
2555 let Inst{6-4} = 0b001; // Rn: Inst{3-0} != 15
2556 let Inst{15-12} = Rd;
2557 let Inst{11-7} = imm{4-0}; // lsb
2558 let Inst{20-16} = imm{9-5}; // width
2562 // GNU as only supports this form of bfi (w/ 4 arguments)
2563 let isAsmParserOnly = 1 in
2564 def BFI4p : I<(outs GPR:$Rd), (ins GPR:$src, GPR:$Rn,
2565 lsb_pos_imm:$lsb, width_imm:$width),
2566 AddrMode1, Size4Bytes, IndexModeNone, DPFrm, IIC_iUNAsi,
2567 "bfi", "\t$Rd, $Rn, $lsb, $width", "$src = $Rd",
2568 []>, Requires<[IsARM, HasV6T2]> {
2573 let Inst{27-21} = 0b0111110;
2574 let Inst{6-4} = 0b001; // Rn: Inst{3-0} != 15
2575 let Inst{15-12} = Rd;
2576 let Inst{11-7} = lsb;
2577 let Inst{20-16} = width; // Custom encoder => lsb+width-1
2581 def MVNr : AsI1<0b1111, (outs GPR:$Rd), (ins GPR:$Rm), DPFrm, IIC_iMVNr,
2582 "mvn", "\t$Rd, $Rm",
2583 [(set GPR:$Rd, (not GPR:$Rm))]>, UnaryDP {
2587 let Inst{19-16} = 0b0000;
2588 let Inst{11-4} = 0b00000000;
2589 let Inst{15-12} = Rd;
2592 def MVNs : AsI1<0b1111, (outs GPR:$Rd), (ins so_reg:$shift), DPSoRegFrm,
2593 IIC_iMVNsr, "mvn", "\t$Rd, $shift",
2594 [(set GPR:$Rd, (not so_reg:$shift))]>, UnaryDP {
2598 let Inst{19-16} = 0b0000;
2599 let Inst{15-12} = Rd;
2600 let Inst{11-0} = shift;
2602 let isReMaterializable = 1, isAsCheapAsAMove = 1, isMoveImm = 1 in
2603 def MVNi : AsI1<0b1111, (outs GPR:$Rd), (ins so_imm:$imm), DPFrm,
2604 IIC_iMVNi, "mvn", "\t$Rd, $imm",
2605 [(set GPR:$Rd, so_imm_not:$imm)]>,UnaryDP {
2609 let Inst{19-16} = 0b0000;
2610 let Inst{15-12} = Rd;
2611 let Inst{11-0} = imm;
2614 def : ARMPat<(and GPR:$src, so_imm_not:$imm),
2615 (BICri GPR:$src, so_imm_not:$imm)>;
2617 //===----------------------------------------------------------------------===//
2618 // Multiply Instructions.
2620 class AsMul1I32<bits<7> opcod, dag oops, dag iops, InstrItinClass itin,
2621 string opc, string asm, list<dag> pattern>
2622 : AsMul1I<opcod, oops, iops, itin, opc, asm, pattern> {
2626 let Inst{19-16} = Rd;
2627 let Inst{11-8} = Rm;
2630 class AsMul1I64<bits<7> opcod, dag oops, dag iops, InstrItinClass itin,
2631 string opc, string asm, list<dag> pattern>
2632 : AsMul1I<opcod, oops, iops, itin, opc, asm, pattern> {
2637 let Inst{19-16} = RdHi;
2638 let Inst{15-12} = RdLo;
2639 let Inst{11-8} = Rm;
2643 let isCommutable = 1 in {
2644 let Constraints = "@earlyclobber $Rd" in
2645 def MULv5: ARMPseudoInst<(outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm,
2646 pred:$p, cc_out:$s),
2647 Size4Bytes, IIC_iMUL32,
2648 [(set GPR:$Rd, (mul GPR:$Rn, GPR:$Rm))]>,
2649 Requires<[IsARM, NoV6]>;
2651 def MUL : AsMul1I32<0b0000000, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm),
2652 IIC_iMUL32, "mul", "\t$Rd, $Rn, $Rm",
2653 [(set GPR:$Rd, (mul GPR:$Rn, GPR:$Rm))]>,
2654 Requires<[IsARM, HasV6]> {
2655 let Inst{15-12} = 0b0000;
2659 let Constraints = "@earlyclobber $Rd" in
2660 def MLAv5: ARMPseudoInst<(outs GPR:$Rd),
2661 (ins GPR:$Rn, GPR:$Rm, GPR:$Ra, pred:$p, cc_out:$s),
2662 Size4Bytes, IIC_iMAC32,
2663 [(set GPR:$Rd, (add (mul GPR:$Rn, GPR:$Rm), GPR:$Ra))]>,
2664 Requires<[IsARM, NoV6]> {
2666 let Inst{15-12} = Ra;
2668 def MLA : AsMul1I32<0b0000001, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm, GPR:$Ra),
2669 IIC_iMAC32, "mla", "\t$Rd, $Rn, $Rm, $Ra",
2670 [(set GPR:$Rd, (add (mul GPR:$Rn, GPR:$Rm), GPR:$Ra))]>,
2671 Requires<[IsARM, HasV6]> {
2673 let Inst{15-12} = Ra;
2676 def MLS : AMul1I<0b0000011, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm, GPR:$Ra),
2677 IIC_iMAC32, "mls", "\t$Rd, $Rn, $Rm, $Ra",
2678 [(set GPR:$Rd, (sub GPR:$Ra, (mul GPR:$Rn, GPR:$Rm)))]>,
2679 Requires<[IsARM, HasV6T2]> {
2684 let Inst{19-16} = Rd;
2685 let Inst{15-12} = Ra;
2686 let Inst{11-8} = Rm;
2690 // Extra precision multiplies with low / high results
2692 let neverHasSideEffects = 1 in {
2693 let isCommutable = 1 in {
2694 let Constraints = "@earlyclobber $RdLo,@earlyclobber $RdHi" in {
2695 def SMULLv5 : ARMPseudoInst<(outs GPR:$RdLo, GPR:$RdHi),
2696 (ins GPR:$Rn, GPR:$Rm, pred:$p, cc_out:$s),
2697 Size4Bytes, IIC_iMUL64, []>,
2698 Requires<[IsARM, NoV6]>;
2700 def UMULLv5 : ARMPseudoInst<(outs GPR:$RdLo, GPR:$RdHi),
2701 (ins GPR:$Rn, GPR:$Rm, pred:$p, cc_out:$s),
2702 Size4Bytes, IIC_iMUL64, []>,
2703 Requires<[IsARM, NoV6]>;
2706 def SMULL : AsMul1I64<0b0000110, (outs GPR:$RdLo, GPR:$RdHi),
2707 (ins GPR:$Rn, GPR:$Rm), IIC_iMUL64,
2708 "smull", "\t$RdLo, $RdHi, $Rn, $Rm", []>,
2709 Requires<[IsARM, HasV6]>;
2711 def UMULL : AsMul1I64<0b0000100, (outs GPR:$RdLo, GPR:$RdHi),
2712 (ins GPR:$Rn, GPR:$Rm), IIC_iMUL64,
2713 "umull", "\t$RdLo, $RdHi, $Rn, $Rm", []>,
2714 Requires<[IsARM, HasV6]>;
2717 // Multiply + accumulate
2718 let Constraints = "@earlyclobber $RdLo,@earlyclobber $RdHi" in {
2719 def SMLALv5 : ARMPseudoInst<(outs GPR:$RdLo, GPR:$RdHi),
2720 (ins GPR:$Rn, GPR:$Rm, pred:$p, cc_out:$s),
2721 Size4Bytes, IIC_iMAC64, []>,
2722 Requires<[IsARM, NoV6]>;
2723 def UMLALv5 : ARMPseudoInst<(outs GPR:$RdLo, GPR:$RdHi),
2724 (ins GPR:$Rn, GPR:$Rm, pred:$p, cc_out:$s),
2725 Size4Bytes, IIC_iMAC64, []>,
2726 Requires<[IsARM, NoV6]>;
2727 def UMAALv5 : ARMPseudoInst<(outs GPR:$RdLo, GPR:$RdHi),
2728 (ins GPR:$Rn, GPR:$Rm, pred:$p, cc_out:$s),
2729 Size4Bytes, IIC_iMAC64, []>,
2730 Requires<[IsARM, NoV6]>;
2734 def SMLAL : AsMul1I64<0b0000111, (outs GPR:$RdLo, GPR:$RdHi),
2735 (ins GPR:$Rn, GPR:$Rm), IIC_iMAC64,
2736 "smlal", "\t$RdLo, $RdHi, $Rn, $Rm", []>,
2737 Requires<[IsARM, HasV6]>;
2738 def UMLAL : AsMul1I64<0b0000101, (outs GPR:$RdLo, GPR:$RdHi),
2739 (ins GPR:$Rn, GPR:$Rm), IIC_iMAC64,
2740 "umlal", "\t$RdLo, $RdHi, $Rn, $Rm", []>,
2741 Requires<[IsARM, HasV6]>;
2743 def UMAAL : AMul1I <0b0000010, (outs GPR:$RdLo, GPR:$RdHi),
2744 (ins GPR:$Rn, GPR:$Rm), IIC_iMAC64,
2745 "umaal", "\t$RdLo, $RdHi, $Rn, $Rm", []>,
2746 Requires<[IsARM, HasV6]> {
2751 let Inst{19-16} = RdLo;
2752 let Inst{15-12} = RdHi;
2753 let Inst{11-8} = Rm;
2756 } // neverHasSideEffects
2758 // Most significant word multiply
2759 def SMMUL : AMul2I <0b0111010, 0b0001, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm),
2760 IIC_iMUL32, "smmul", "\t$Rd, $Rn, $Rm",
2761 [(set GPR:$Rd, (mulhs GPR:$Rn, GPR:$Rm))]>,
2762 Requires<[IsARM, HasV6]> {
2763 let Inst{15-12} = 0b1111;
2766 def SMMULR : AMul2I <0b0111010, 0b0011, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm),
2767 IIC_iMUL32, "smmulr", "\t$Rd, $Rn, $Rm",
2768 [/* For disassembly only; pattern left blank */]>,
2769 Requires<[IsARM, HasV6]> {
2770 let Inst{15-12} = 0b1111;
2773 def SMMLA : AMul2Ia <0b0111010, 0b0001, (outs GPR:$Rd),
2774 (ins GPR:$Rn, GPR:$Rm, GPR:$Ra),
2775 IIC_iMAC32, "smmla", "\t$Rd, $Rn, $Rm, $Ra",
2776 [(set GPR:$Rd, (add (mulhs GPR:$Rn, GPR:$Rm), GPR:$Ra))]>,
2777 Requires<[IsARM, HasV6]>;
2779 def SMMLAR : AMul2Ia <0b0111010, 0b0011, (outs GPR:$Rd),
2780 (ins GPR:$Rn, GPR:$Rm, GPR:$Ra),
2781 IIC_iMAC32, "smmlar", "\t$Rd, $Rn, $Rm, $Ra",
2782 [/* For disassembly only; pattern left blank */]>,
2783 Requires<[IsARM, HasV6]>;
2785 def SMMLS : AMul2Ia <0b0111010, 0b1101, (outs GPR:$Rd),
2786 (ins GPR:$Rn, GPR:$Rm, GPR:$Ra),
2787 IIC_iMAC32, "smmls", "\t$Rd, $Rn, $Rm, $Ra",
2788 [(set GPR:$Rd, (sub GPR:$Ra, (mulhs GPR:$Rn, GPR:$Rm)))]>,
2789 Requires<[IsARM, HasV6]>;
2791 def SMMLSR : AMul2Ia <0b0111010, 0b1111, (outs GPR:$Rd),
2792 (ins GPR:$Rn, GPR:$Rm, GPR:$Ra),
2793 IIC_iMAC32, "smmlsr", "\t$Rd, $Rn, $Rm, $Ra",
2794 [/* For disassembly only; pattern left blank */]>,
2795 Requires<[IsARM, HasV6]>;
2797 multiclass AI_smul<string opc, PatFrag opnode> {
2798 def BB : AMulxyI<0b0001011, 0b00, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm),
2799 IIC_iMUL16, !strconcat(opc, "bb"), "\t$Rd, $Rn, $Rm",
2800 [(set GPR:$Rd, (opnode (sext_inreg GPR:$Rn, i16),
2801 (sext_inreg GPR:$Rm, i16)))]>,
2802 Requires<[IsARM, HasV5TE]>;
2804 def BT : AMulxyI<0b0001011, 0b10, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm),
2805 IIC_iMUL16, !strconcat(opc, "bt"), "\t$Rd, $Rn, $Rm",
2806 [(set GPR:$Rd, (opnode (sext_inreg GPR:$Rn, i16),
2807 (sra GPR:$Rm, (i32 16))))]>,
2808 Requires<[IsARM, HasV5TE]>;
2810 def TB : AMulxyI<0b0001011, 0b01, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm),
2811 IIC_iMUL16, !strconcat(opc, "tb"), "\t$Rd, $Rn, $Rm",
2812 [(set GPR:$Rd, (opnode (sra GPR:$Rn, (i32 16)),
2813 (sext_inreg GPR:$Rm, i16)))]>,
2814 Requires<[IsARM, HasV5TE]>;
2816 def TT : AMulxyI<0b0001011, 0b11, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm),
2817 IIC_iMUL16, !strconcat(opc, "tt"), "\t$Rd, $Rn, $Rm",
2818 [(set GPR:$Rd, (opnode (sra GPR:$Rn, (i32 16)),
2819 (sra GPR:$Rm, (i32 16))))]>,
2820 Requires<[IsARM, HasV5TE]>;
2822 def WB : AMulxyI<0b0001001, 0b01, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm),
2823 IIC_iMUL16, !strconcat(opc, "wb"), "\t$Rd, $Rn, $Rm",
2824 [(set GPR:$Rd, (sra (opnode GPR:$Rn,
2825 (sext_inreg GPR:$Rm, i16)), (i32 16)))]>,
2826 Requires<[IsARM, HasV5TE]>;
2828 def WT : AMulxyI<0b0001001, 0b11, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm),
2829 IIC_iMUL16, !strconcat(opc, "wt"), "\t$Rd, $Rn, $Rm",
2830 [(set GPR:$Rd, (sra (opnode GPR:$Rn,
2831 (sra GPR:$Rm, (i32 16))), (i32 16)))]>,
2832 Requires<[IsARM, HasV5TE]>;
2836 multiclass AI_smla<string opc, PatFrag opnode> {
2837 def BB : AMulxyIa<0b0001000, 0b00, (outs GPR:$Rd),
2838 (ins GPR:$Rn, GPR:$Rm, GPR:$Ra),
2839 IIC_iMAC16, !strconcat(opc, "bb"), "\t$Rd, $Rn, $Rm, $Ra",
2840 [(set GPR:$Rd, (add GPR:$Ra,
2841 (opnode (sext_inreg GPR:$Rn, i16),
2842 (sext_inreg GPR:$Rm, i16))))]>,
2843 Requires<[IsARM, HasV5TE]>;
2845 def BT : AMulxyIa<0b0001000, 0b10, (outs GPR:$Rd),
2846 (ins GPR:$Rn, GPR:$Rm, GPR:$Ra),
2847 IIC_iMAC16, !strconcat(opc, "bt"), "\t$Rd, $Rn, $Rm, $Ra",
2848 [(set GPR:$Rd, (add GPR:$Ra, (opnode (sext_inreg GPR:$Rn, i16),
2849 (sra GPR:$Rm, (i32 16)))))]>,
2850 Requires<[IsARM, HasV5TE]>;
2852 def TB : AMulxyIa<0b0001000, 0b01, (outs GPR:$Rd),
2853 (ins GPR:$Rn, GPR:$Rm, GPR:$Ra),
2854 IIC_iMAC16, !strconcat(opc, "tb"), "\t$Rd, $Rn, $Rm, $Ra",
2855 [(set GPR:$Rd, (add GPR:$Ra, (opnode (sra GPR:$Rn, (i32 16)),
2856 (sext_inreg GPR:$Rm, i16))))]>,
2857 Requires<[IsARM, HasV5TE]>;
2859 def TT : AMulxyIa<0b0001000, 0b11, (outs GPR:$Rd),
2860 (ins GPR:$Rn, GPR:$Rm, GPR:$Ra),
2861 IIC_iMAC16, !strconcat(opc, "tt"), "\t$Rd, $Rn, $Rm, $Ra",
2862 [(set GPR:$Rd, (add GPR:$Ra, (opnode (sra GPR:$Rn, (i32 16)),
2863 (sra GPR:$Rm, (i32 16)))))]>,
2864 Requires<[IsARM, HasV5TE]>;
2866 def WB : AMulxyIa<0b0001001, 0b00, (outs GPR:$Rd),
2867 (ins GPR:$Rn, GPR:$Rm, GPR:$Ra),
2868 IIC_iMAC16, !strconcat(opc, "wb"), "\t$Rd, $Rn, $Rm, $Ra",
2869 [(set GPR:$Rd, (add GPR:$Ra, (sra (opnode GPR:$Rn,
2870 (sext_inreg GPR:$Rm, i16)), (i32 16))))]>,
2871 Requires<[IsARM, HasV5TE]>;
2873 def WT : AMulxyIa<0b0001001, 0b10, (outs GPR:$Rd),
2874 (ins GPR:$Rn, GPR:$Rm, GPR:$Ra),
2875 IIC_iMAC16, !strconcat(opc, "wt"), "\t$Rd, $Rn, $Rm, $Ra",
2876 [(set GPR:$Rd, (add GPR:$Ra, (sra (opnode GPR:$Rn,
2877 (sra GPR:$Rm, (i32 16))), (i32 16))))]>,
2878 Requires<[IsARM, HasV5TE]>;
2881 defm SMUL : AI_smul<"smul", BinOpFrag<(mul node:$LHS, node:$RHS)>>;
2882 defm SMLA : AI_smla<"smla", BinOpFrag<(mul node:$LHS, node:$RHS)>>;
2884 // Halfword multiply accumulate long: SMLAL<x><y> -- for disassembly only
2885 def SMLALBB : AMulxyI64<0b0001010, 0b00, (outs GPR:$RdLo, GPR:$RdHi),
2886 (ins GPR:$Rn, GPR:$Rm),
2887 IIC_iMAC64, "smlalbb", "\t$RdLo, $RdHi, $Rn, $Rm",
2888 [/* For disassembly only; pattern left blank */]>,
2889 Requires<[IsARM, HasV5TE]>;
2891 def SMLALBT : AMulxyI64<0b0001010, 0b10, (outs GPR:$RdLo, GPR:$RdHi),
2892 (ins GPR:$Rn, GPR:$Rm),
2893 IIC_iMAC64, "smlalbt", "\t$RdLo, $RdHi, $Rn, $Rm",
2894 [/* For disassembly only; pattern left blank */]>,
2895 Requires<[IsARM, HasV5TE]>;
2897 def SMLALTB : AMulxyI64<0b0001010, 0b01, (outs GPR:$RdLo, GPR:$RdHi),
2898 (ins GPR:$Rn, GPR:$Rm),
2899 IIC_iMAC64, "smlaltb", "\t$RdLo, $RdHi, $Rn, $Rm",
2900 [/* For disassembly only; pattern left blank */]>,
2901 Requires<[IsARM, HasV5TE]>;
2903 def SMLALTT : AMulxyI64<0b0001010, 0b11, (outs GPR:$RdLo, GPR:$RdHi),
2904 (ins GPR:$Rn, GPR:$Rm),
2905 IIC_iMAC64, "smlaltt", "\t$RdLo, $RdHi, $Rn, $Rm",
2906 [/* For disassembly only; pattern left blank */]>,
2907 Requires<[IsARM, HasV5TE]>;
2909 // Helper class for AI_smld -- for disassembly only
2910 class AMulDualIbase<bit long, bit sub, bit swap, dag oops, dag iops,
2911 InstrItinClass itin, string opc, string asm>
2912 : AI<oops, iops, MulFrm, itin, opc, asm, []>, Requires<[IsARM, HasV6]> {
2919 let Inst{21-20} = 0b00;
2920 let Inst{22} = long;
2921 let Inst{27-23} = 0b01110;
2922 let Inst{11-8} = Rm;
2925 class AMulDualI<bit long, bit sub, bit swap, dag oops, dag iops,
2926 InstrItinClass itin, string opc, string asm>
2927 : AMulDualIbase<long, sub, swap, oops, iops, itin, opc, asm> {
2929 let Inst{15-12} = 0b1111;
2930 let Inst{19-16} = Rd;
2932 class AMulDualIa<bit long, bit sub, bit swap, dag oops, dag iops,
2933 InstrItinClass itin, string opc, string asm>
2934 : AMulDualIbase<long, sub, swap, oops, iops, itin, opc, asm> {
2936 let Inst{15-12} = Ra;
2938 class AMulDualI64<bit long, bit sub, bit swap, dag oops, dag iops,
2939 InstrItinClass itin, string opc, string asm>
2940 : AMulDualIbase<long, sub, swap, oops, iops, itin, opc, asm> {
2943 let Inst{19-16} = RdHi;
2944 let Inst{15-12} = RdLo;
2947 multiclass AI_smld<bit sub, string opc> {
2949 def D : AMulDualIa<0, sub, 0, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm, GPR:$Ra),
2950 NoItinerary, !strconcat(opc, "d"), "\t$Rd, $Rn, $Rm, $Ra">;
2952 def DX: AMulDualIa<0, sub, 1, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm, GPR:$Ra),
2953 NoItinerary, !strconcat(opc, "dx"), "\t$Rd, $Rn, $Rm, $Ra">;
2955 def LD: AMulDualI64<1, sub, 0, (outs GPR:$RdLo,GPR:$RdHi),
2956 (ins GPR:$Rn, GPR:$Rm), NoItinerary,
2957 !strconcat(opc, "ld"), "\t$RdLo, $RdHi, $Rn, $Rm">;
2959 def LDX : AMulDualI64<1, sub, 1, (outs GPR:$RdLo,GPR:$RdHi),
2960 (ins GPR:$Rn, GPR:$Rm), NoItinerary,
2961 !strconcat(opc, "ldx"),"\t$RdLo, $RdHi, $Rn, $Rm">;
2965 defm SMLA : AI_smld<0, "smla">;
2966 defm SMLS : AI_smld<1, "smls">;
2968 multiclass AI_sdml<bit sub, string opc> {
2970 def D : AMulDualI<0, sub, 0, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm),
2971 NoItinerary, !strconcat(opc, "d"), "\t$Rd, $Rn, $Rm">;
2972 def DX : AMulDualI<0, sub, 1, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm),
2973 NoItinerary, !strconcat(opc, "dx"), "\t$Rd, $Rn, $Rm">;
2976 defm SMUA : AI_sdml<0, "smua">;
2977 defm SMUS : AI_sdml<1, "smus">;
2979 //===----------------------------------------------------------------------===//
2980 // Misc. Arithmetic Instructions.
2983 def CLZ : AMiscA1I<0b000010110, 0b0001, (outs GPR:$Rd), (ins GPR:$Rm),
2984 IIC_iUNAr, "clz", "\t$Rd, $Rm",
2985 [(set GPR:$Rd, (ctlz GPR:$Rm))]>, Requires<[IsARM, HasV5T]>;
2987 def RBIT : AMiscA1I<0b01101111, 0b0011, (outs GPR:$Rd), (ins GPR:$Rm),
2988 IIC_iUNAr, "rbit", "\t$Rd, $Rm",
2989 [(set GPR:$Rd, (ARMrbit GPR:$Rm))]>,
2990 Requires<[IsARM, HasV6T2]>;
2992 def REV : AMiscA1I<0b01101011, 0b0011, (outs GPR:$Rd), (ins GPR:$Rm),
2993 IIC_iUNAr, "rev", "\t$Rd, $Rm",
2994 [(set GPR:$Rd, (bswap GPR:$Rm))]>, Requires<[IsARM, HasV6]>;
2996 def REV16 : AMiscA1I<0b01101011, 0b1011, (outs GPR:$Rd), (ins GPR:$Rm),
2997 IIC_iUNAr, "rev16", "\t$Rd, $Rm",
2999 (or (and (srl GPR:$Rm, (i32 8)), 0xFF),
3000 (or (and (shl GPR:$Rm, (i32 8)), 0xFF00),
3001 (or (and (srl GPR:$Rm, (i32 8)), 0xFF0000),
3002 (and (shl GPR:$Rm, (i32 8)), 0xFF000000)))))]>,
3003 Requires<[IsARM, HasV6]>;
3005 def REVSH : AMiscA1I<0b01101111, 0b1011, (outs GPR:$Rd), (ins GPR:$Rm),
3006 IIC_iUNAr, "revsh", "\t$Rd, $Rm",
3009 (or (srl GPR:$Rm, (i32 8)),
3010 (shl GPR:$Rm, (i32 8))), i16))]>,
3011 Requires<[IsARM, HasV6]>;
3013 def : ARMV6Pat<(sext_inreg (or (srl (and GPR:$Rm, 0xFF00), (i32 8)),
3014 (shl GPR:$Rm, (i32 8))), i16),
3017 // Need the AddedComplexity or else MOVs + REV would be chosen.
3018 let AddedComplexity = 5 in
3019 def : ARMV6Pat<(sra (bswap GPR:$Rm), (i32 16)), (REVSH GPR:$Rm)>;
3021 def lsl_shift_imm : SDNodeXForm<imm, [{
3022 unsigned Sh = ARM_AM::getSORegOpc(ARM_AM::lsl, N->getZExtValue());
3023 return CurDAG->getTargetConstant(Sh, MVT::i32);
3026 def lsl_amt : ImmLeaf<i32, [{
3027 return Imm > 0 && Imm < 32;
3030 def PKHBT : APKHI<0b01101000, 0, (outs GPR:$Rd),
3031 (ins GPR:$Rn, GPR:$Rm, shift_imm:$sh),
3032 IIC_iALUsi, "pkhbt", "\t$Rd, $Rn, $Rm$sh",
3033 [(set GPR:$Rd, (or (and GPR:$Rn, 0xFFFF),
3034 (and (shl GPR:$Rm, lsl_amt:$sh),
3036 Requires<[IsARM, HasV6]>;
3038 // Alternate cases for PKHBT where identities eliminate some nodes.
3039 def : ARMV6Pat<(or (and GPR:$Rn, 0xFFFF), (and GPR:$Rm, 0xFFFF0000)),
3040 (PKHBT GPR:$Rn, GPR:$Rm, 0)>;
3041 def : ARMV6Pat<(or (and GPR:$Rn, 0xFFFF), (shl GPR:$Rm, imm16_31:$sh)),
3042 (PKHBT GPR:$Rn, GPR:$Rm, (lsl_shift_imm imm16_31:$sh))>;
3044 def asr_shift_imm : SDNodeXForm<imm, [{
3045 unsigned Sh = ARM_AM::getSORegOpc(ARM_AM::asr, N->getZExtValue());
3046 return CurDAG->getTargetConstant(Sh, MVT::i32);
3049 def asr_amt : ImmLeaf<i32, [{
3050 return Imm > 0 && Imm <= 32;
3053 // Note: Shifts of 1-15 bits will be transformed to srl instead of sra and
3054 // will match the pattern below.
3055 def PKHTB : APKHI<0b01101000, 1, (outs GPR:$Rd),
3056 (ins GPR:$Rn, GPR:$Rm, shift_imm:$sh),
3057 IIC_iBITsi, "pkhtb", "\t$Rd, $Rn, $Rm$sh",
3058 [(set GPR:$Rd, (or (and GPR:$Rn, 0xFFFF0000),
3059 (and (sra GPR:$Rm, asr_amt:$sh),
3061 Requires<[IsARM, HasV6]>;
3063 // Alternate cases for PKHTB where identities eliminate some nodes. Note that
3064 // a shift amount of 0 is *not legal* here, it is PKHBT instead.
3065 def : ARMV6Pat<(or (and GPR:$src1, 0xFFFF0000), (srl GPR:$src2, imm16_31:$sh)),
3066 (PKHTB GPR:$src1, GPR:$src2, (asr_shift_imm imm16_31:$sh))>;
3067 def : ARMV6Pat<(or (and GPR:$src1, 0xFFFF0000),
3068 (and (srl GPR:$src2, imm1_15:$sh), 0xFFFF)),
3069 (PKHTB GPR:$src1, GPR:$src2, (asr_shift_imm imm1_15:$sh))>;
3071 //===----------------------------------------------------------------------===//
3072 // Comparison Instructions...
3075 defm CMP : AI1_cmp_irs<0b1010, "cmp",
3076 IIC_iCMPi, IIC_iCMPr, IIC_iCMPsr,
3077 BinOpFrag<(ARMcmp node:$LHS, node:$RHS)>>;
3079 // ARMcmpZ can re-use the above instruction definitions.
3080 def : ARMPat<(ARMcmpZ GPR:$src, so_imm:$imm),
3081 (CMPri GPR:$src, so_imm:$imm)>;
3082 def : ARMPat<(ARMcmpZ GPR:$src, GPR:$rhs),
3083 (CMPrr GPR:$src, GPR:$rhs)>;
3084 def : ARMPat<(ARMcmpZ GPR:$src, so_reg:$rhs),
3085 (CMPrs GPR:$src, so_reg:$rhs)>;
3087 // FIXME: We have to be careful when using the CMN instruction and comparison
3088 // with 0. One would expect these two pieces of code should give identical
3104 // However, the CMN gives the *opposite* result when r1 is 0. This is because
3105 // the carry flag is set in the CMP case but not in the CMN case. In short, the
3106 // CMP instruction doesn't perform a truncate of the (logical) NOT of 0 plus the
3107 // value of r0 and the carry bit (because the "carry bit" parameter to
3108 // AddWithCarry is defined as 1 in this case, the carry flag will always be set
3109 // when r0 >= 0). The CMN instruction doesn't perform a NOT of 0 so there is
3110 // never a "carry" when this AddWithCarry is performed (because the "carry bit"
3111 // parameter to AddWithCarry is defined as 0).
3113 // When x is 0 and unsigned:
3117 // ~x + 1 = 0x1 0000 0000
3118 // (-x = 0) != (0x1 0000 0000 = ~x + 1)
3120 // Therefore, we should disable CMN when comparing against zero, until we can
3121 // limit when the CMN instruction is used (when we know that the RHS is not 0 or
3122 // when it's a comparison which doesn't look at the 'carry' flag).
3124 // (See the ARM docs for the "AddWithCarry" pseudo-code.)
3126 // This is related to <rdar://problem/7569620>.
3128 //defm CMN : AI1_cmp_irs<0b1011, "cmn",
3129 // BinOpFrag<(ARMcmp node:$LHS,(ineg node:$RHS))>>;
3131 // Note that TST/TEQ don't set all the same flags that CMP does!
3132 defm TST : AI1_cmp_irs<0b1000, "tst",
3133 IIC_iTSTi, IIC_iTSTr, IIC_iTSTsr,
3134 BinOpFrag<(ARMcmpZ (and_su node:$LHS, node:$RHS), 0)>, 1>;
3135 defm TEQ : AI1_cmp_irs<0b1001, "teq",
3136 IIC_iTSTi, IIC_iTSTr, IIC_iTSTsr,
3137 BinOpFrag<(ARMcmpZ (xor_su node:$LHS, node:$RHS), 0)>, 1>;
3139 defm CMNz : AI1_cmp_irs<0b1011, "cmn",
3140 IIC_iCMPi, IIC_iCMPr, IIC_iCMPsr,
3141 BinOpFrag<(ARMcmpZ node:$LHS,(ineg node:$RHS))>>;
3143 //def : ARMPat<(ARMcmp GPR:$src, so_imm_neg:$imm),
3144 // (CMNri GPR:$src, so_imm_neg:$imm)>;
3146 def : ARMPat<(ARMcmpZ GPR:$src, so_imm_neg:$imm),
3147 (CMNzri GPR:$src, so_imm_neg:$imm)>;
3149 // Pseudo i64 compares for some floating point compares.
3150 let usesCustomInserter = 1, isBranch = 1, isTerminator = 1,
3152 def BCCi64 : PseudoInst<(outs),
3153 (ins i32imm:$cc, GPR:$lhs1, GPR:$lhs2, GPR:$rhs1, GPR:$rhs2, brtarget:$dst),
3155 [(ARMBcci64 imm:$cc, GPR:$lhs1, GPR:$lhs2, GPR:$rhs1, GPR:$rhs2, bb:$dst)]>;
3157 def BCCZi64 : PseudoInst<(outs),
3158 (ins i32imm:$cc, GPR:$lhs1, GPR:$lhs2, brtarget:$dst), IIC_Br,
3159 [(ARMBcci64 imm:$cc, GPR:$lhs1, GPR:$lhs2, 0, 0, bb:$dst)]>;
3160 } // usesCustomInserter
3163 // Conditional moves
3164 // FIXME: should be able to write a pattern for ARMcmov, but can't use
3165 // a two-value operand where a dag node expects two operands. :(
3166 let neverHasSideEffects = 1 in {
3167 def MOVCCr : ARMPseudoInst<(outs GPR:$Rd), (ins GPR:$false, GPR:$Rm, pred:$p),
3168 Size4Bytes, IIC_iCMOVr,
3169 [/*(set GPR:$Rd, (ARMcmov GPR:$false, GPR:$Rm, imm:$cc, CCR:$ccr))*/]>,
3170 RegConstraint<"$false = $Rd">;
3171 def MOVCCs : ARMPseudoInst<(outs GPR:$Rd),
3172 (ins GPR:$false, so_reg:$shift, pred:$p),
3173 Size4Bytes, IIC_iCMOVsr,
3174 [/*(set GPR:$Rd, (ARMcmov GPR:$false, so_reg:$shift, imm:$cc, CCR:$ccr))*/]>,
3175 RegConstraint<"$false = $Rd">;
3177 let isMoveImm = 1 in
3178 def MOVCCi16 : ARMPseudoInst<(outs GPR:$Rd),
3179 (ins GPR:$false, i32imm_hilo16:$imm, pred:$p),
3180 Size4Bytes, IIC_iMOVi,
3182 RegConstraint<"$false = $Rd">, Requires<[IsARM, HasV6T2]>;
3184 let isMoveImm = 1 in
3185 def MOVCCi : ARMPseudoInst<(outs GPR:$Rd),
3186 (ins GPR:$false, so_imm:$imm, pred:$p),
3187 Size4Bytes, IIC_iCMOVi,
3188 [/*(set GPR:$Rd, (ARMcmov GPR:$false, so_imm:$imm, imm:$cc, CCR:$ccr))*/]>,
3189 RegConstraint<"$false = $Rd">;
3191 // Two instruction predicate mov immediate.
3192 let isMoveImm = 1 in
3193 def MOVCCi32imm : ARMPseudoInst<(outs GPR:$Rd),
3194 (ins GPR:$false, i32imm:$src, pred:$p),
3195 Size8Bytes, IIC_iCMOVix2, []>, RegConstraint<"$false = $Rd">;
3197 let isMoveImm = 1 in
3198 def MVNCCi : ARMPseudoInst<(outs GPR:$Rd),
3199 (ins GPR:$false, so_imm:$imm, pred:$p),
3200 Size4Bytes, IIC_iCMOVi,
3201 [/*(set GPR:$Rd, (ARMcmov GPR:$false, so_imm_not:$imm, imm:$cc, CCR:$ccr))*/]>,
3202 RegConstraint<"$false = $Rd">;
3203 } // neverHasSideEffects
3205 //===----------------------------------------------------------------------===//
3206 // Atomic operations intrinsics
3209 def memb_opt : Operand<i32> {
3210 let PrintMethod = "printMemBOption";
3211 let ParserMatchClass = MemBarrierOptOperand;
3214 // memory barriers protect the atomic sequences
3215 let hasSideEffects = 1 in {
3216 def DMB : AInoP<(outs), (ins memb_opt:$opt), MiscFrm, NoItinerary,
3217 "dmb", "\t$opt", [(ARMMemBarrier (i32 imm:$opt))]>,
3218 Requires<[IsARM, HasDB]> {
3220 let Inst{31-4} = 0xf57ff05;
3221 let Inst{3-0} = opt;
3225 def DSB : AInoP<(outs), (ins memb_opt:$opt), MiscFrm, NoItinerary,
3227 [/* For disassembly only; pattern left blank */]>,
3228 Requires<[IsARM, HasDB]> {
3230 let Inst{31-4} = 0xf57ff04;
3231 let Inst{3-0} = opt;
3234 // ISB has only full system option -- for disassembly only
3235 def ISB : AInoP<(outs), (ins), MiscFrm, NoItinerary, "isb", "", []>,
3236 Requires<[IsARM, HasDB]> {
3237 let Inst{31-4} = 0xf57ff06;
3238 let Inst{3-0} = 0b1111;
3241 let usesCustomInserter = 1 in {
3242 let Uses = [CPSR] in {
3243 def ATOMIC_LOAD_ADD_I8 : PseudoInst<
3244 (outs GPR:$dst), (ins GPR:$ptr, GPR:$incr), NoItinerary,
3245 [(set GPR:$dst, (atomic_load_add_8 GPR:$ptr, GPR:$incr))]>;
3246 def ATOMIC_LOAD_SUB_I8 : PseudoInst<
3247 (outs GPR:$dst), (ins GPR:$ptr, GPR:$incr), NoItinerary,
3248 [(set GPR:$dst, (atomic_load_sub_8 GPR:$ptr, GPR:$incr))]>;
3249 def ATOMIC_LOAD_AND_I8 : PseudoInst<
3250 (outs GPR:$dst), (ins GPR:$ptr, GPR:$incr), NoItinerary,
3251 [(set GPR:$dst, (atomic_load_and_8 GPR:$ptr, GPR:$incr))]>;
3252 def ATOMIC_LOAD_OR_I8 : PseudoInst<
3253 (outs GPR:$dst), (ins GPR:$ptr, GPR:$incr), NoItinerary,
3254 [(set GPR:$dst, (atomic_load_or_8 GPR:$ptr, GPR:$incr))]>;
3255 def ATOMIC_LOAD_XOR_I8 : PseudoInst<
3256 (outs GPR:$dst), (ins GPR:$ptr, GPR:$incr), NoItinerary,
3257 [(set GPR:$dst, (atomic_load_xor_8 GPR:$ptr, GPR:$incr))]>;
3258 def ATOMIC_LOAD_NAND_I8 : PseudoInst<
3259 (outs GPR:$dst), (ins GPR:$ptr, GPR:$incr), NoItinerary,
3260 [(set GPR:$dst, (atomic_load_nand_8 GPR:$ptr, GPR:$incr))]>;
3261 def ATOMIC_LOAD_MIN_I8 : PseudoInst<
3262 (outs GPR:$dst), (ins GPR:$ptr, GPR:$val), NoItinerary,
3263 [(set GPR:$dst, (atomic_load_min_8 GPR:$ptr, GPR:$val))]>;
3264 def ATOMIC_LOAD_MAX_I8 : PseudoInst<
3265 (outs GPR:$dst), (ins GPR:$ptr, GPR:$val), NoItinerary,
3266 [(set GPR:$dst, (atomic_load_max_8 GPR:$ptr, GPR:$val))]>;
3267 def ATOMIC_LOAD_UMIN_I8 : PseudoInst<
3268 (outs GPR:$dst), (ins GPR:$ptr, GPR:$val), NoItinerary,
3269 [(set GPR:$dst, (atomic_load_min_8 GPR:$ptr, GPR:$val))]>;
3270 def ATOMIC_LOAD_UMAX_I8 : PseudoInst<
3271 (outs GPR:$dst), (ins GPR:$ptr, GPR:$val), NoItinerary,
3272 [(set GPR:$dst, (atomic_load_max_8 GPR:$ptr, GPR:$val))]>;
3273 def ATOMIC_LOAD_ADD_I16 : PseudoInst<
3274 (outs GPR:$dst), (ins GPR:$ptr, GPR:$incr), NoItinerary,
3275 [(set GPR:$dst, (atomic_load_add_16 GPR:$ptr, GPR:$incr))]>;
3276 def ATOMIC_LOAD_SUB_I16 : PseudoInst<
3277 (outs GPR:$dst), (ins GPR:$ptr, GPR:$incr), NoItinerary,
3278 [(set GPR:$dst, (atomic_load_sub_16 GPR:$ptr, GPR:$incr))]>;
3279 def ATOMIC_LOAD_AND_I16 : PseudoInst<
3280 (outs GPR:$dst), (ins GPR:$ptr, GPR:$incr), NoItinerary,
3281 [(set GPR:$dst, (atomic_load_and_16 GPR:$ptr, GPR:$incr))]>;
3282 def ATOMIC_LOAD_OR_I16 : PseudoInst<
3283 (outs GPR:$dst), (ins GPR:$ptr, GPR:$incr), NoItinerary,
3284 [(set GPR:$dst, (atomic_load_or_16 GPR:$ptr, GPR:$incr))]>;
3285 def ATOMIC_LOAD_XOR_I16 : PseudoInst<
3286 (outs GPR:$dst), (ins GPR:$ptr, GPR:$incr), NoItinerary,
3287 [(set GPR:$dst, (atomic_load_xor_16 GPR:$ptr, GPR:$incr))]>;
3288 def ATOMIC_LOAD_NAND_I16 : PseudoInst<
3289 (outs GPR:$dst), (ins GPR:$ptr, GPR:$incr), NoItinerary,
3290 [(set GPR:$dst, (atomic_load_nand_16 GPR:$ptr, GPR:$incr))]>;
3291 def ATOMIC_LOAD_MIN_I16 : PseudoInst<
3292 (outs GPR:$dst), (ins GPR:$ptr, GPR:$val), NoItinerary,
3293 [(set GPR:$dst, (atomic_load_min_16 GPR:$ptr, GPR:$val))]>;
3294 def ATOMIC_LOAD_MAX_I16 : PseudoInst<
3295 (outs GPR:$dst), (ins GPR:$ptr, GPR:$val), NoItinerary,
3296 [(set GPR:$dst, (atomic_load_max_16 GPR:$ptr, GPR:$val))]>;
3297 def ATOMIC_LOAD_UMIN_I16 : PseudoInst<
3298 (outs GPR:$dst), (ins GPR:$ptr, GPR:$val), NoItinerary,
3299 [(set GPR:$dst, (atomic_load_min_16 GPR:$ptr, GPR:$val))]>;
3300 def ATOMIC_LOAD_UMAX_I16 : PseudoInst<
3301 (outs GPR:$dst), (ins GPR:$ptr, GPR:$val), NoItinerary,
3302 [(set GPR:$dst, (atomic_load_max_16 GPR:$ptr, GPR:$val))]>;
3303 def ATOMIC_LOAD_ADD_I32 : PseudoInst<
3304 (outs GPR:$dst), (ins GPR:$ptr, GPR:$incr), NoItinerary,
3305 [(set GPR:$dst, (atomic_load_add_32 GPR:$ptr, GPR:$incr))]>;
3306 def ATOMIC_LOAD_SUB_I32 : PseudoInst<
3307 (outs GPR:$dst), (ins GPR:$ptr, GPR:$incr), NoItinerary,
3308 [(set GPR:$dst, (atomic_load_sub_32 GPR:$ptr, GPR:$incr))]>;
3309 def ATOMIC_LOAD_AND_I32 : PseudoInst<
3310 (outs GPR:$dst), (ins GPR:$ptr, GPR:$incr), NoItinerary,
3311 [(set GPR:$dst, (atomic_load_and_32 GPR:$ptr, GPR:$incr))]>;
3312 def ATOMIC_LOAD_OR_I32 : PseudoInst<
3313 (outs GPR:$dst), (ins GPR:$ptr, GPR:$incr), NoItinerary,
3314 [(set GPR:$dst, (atomic_load_or_32 GPR:$ptr, GPR:$incr))]>;
3315 def ATOMIC_LOAD_XOR_I32 : PseudoInst<
3316 (outs GPR:$dst), (ins GPR:$ptr, GPR:$incr), NoItinerary,
3317 [(set GPR:$dst, (atomic_load_xor_32 GPR:$ptr, GPR:$incr))]>;
3318 def ATOMIC_LOAD_NAND_I32 : PseudoInst<
3319 (outs GPR:$dst), (ins GPR:$ptr, GPR:$incr), NoItinerary,
3320 [(set GPR:$dst, (atomic_load_nand_32 GPR:$ptr, GPR:$incr))]>;
3321 def ATOMIC_LOAD_MIN_I32 : PseudoInst<
3322 (outs GPR:$dst), (ins GPR:$ptr, GPR:$val), NoItinerary,
3323 [(set GPR:$dst, (atomic_load_min_32 GPR:$ptr, GPR:$val))]>;
3324 def ATOMIC_LOAD_MAX_I32 : PseudoInst<
3325 (outs GPR:$dst), (ins GPR:$ptr, GPR:$val), NoItinerary,
3326 [(set GPR:$dst, (atomic_load_max_32 GPR:$ptr, GPR:$val))]>;
3327 def ATOMIC_LOAD_UMIN_I32 : PseudoInst<
3328 (outs GPR:$dst), (ins GPR:$ptr, GPR:$val), NoItinerary,
3329 [(set GPR:$dst, (atomic_load_min_32 GPR:$ptr, GPR:$val))]>;
3330 def ATOMIC_LOAD_UMAX_I32 : PseudoInst<
3331 (outs GPR:$dst), (ins GPR:$ptr, GPR:$val), NoItinerary,
3332 [(set GPR:$dst, (atomic_load_max_32 GPR:$ptr, GPR:$val))]>;
3334 def ATOMIC_SWAP_I8 : PseudoInst<
3335 (outs GPR:$dst), (ins GPR:$ptr, GPR:$new), NoItinerary,
3336 [(set GPR:$dst, (atomic_swap_8 GPR:$ptr, GPR:$new))]>;
3337 def ATOMIC_SWAP_I16 : PseudoInst<
3338 (outs GPR:$dst), (ins GPR:$ptr, GPR:$new), NoItinerary,
3339 [(set GPR:$dst, (atomic_swap_16 GPR:$ptr, GPR:$new))]>;
3340 def ATOMIC_SWAP_I32 : PseudoInst<
3341 (outs GPR:$dst), (ins GPR:$ptr, GPR:$new), NoItinerary,
3342 [(set GPR:$dst, (atomic_swap_32 GPR:$ptr, GPR:$new))]>;
3344 def ATOMIC_CMP_SWAP_I8 : PseudoInst<
3345 (outs GPR:$dst), (ins GPR:$ptr, GPR:$old, GPR:$new), NoItinerary,
3346 [(set GPR:$dst, (atomic_cmp_swap_8 GPR:$ptr, GPR:$old, GPR:$new))]>;
3347 def ATOMIC_CMP_SWAP_I16 : PseudoInst<
3348 (outs GPR:$dst), (ins GPR:$ptr, GPR:$old, GPR:$new), NoItinerary,
3349 [(set GPR:$dst, (atomic_cmp_swap_16 GPR:$ptr, GPR:$old, GPR:$new))]>;
3350 def ATOMIC_CMP_SWAP_I32 : PseudoInst<
3351 (outs GPR:$dst), (ins GPR:$ptr, GPR:$old, GPR:$new), NoItinerary,
3352 [(set GPR:$dst, (atomic_cmp_swap_32 GPR:$ptr, GPR:$old, GPR:$new))]>;
3356 let mayLoad = 1 in {
3357 def LDREXB : AIldrex<0b10, (outs GPR:$Rt), (ins addrmode7:$addr), NoItinerary,
3358 "ldrexb", "\t$Rt, $addr", []>;
3359 def LDREXH : AIldrex<0b11, (outs GPR:$Rt), (ins addrmode7:$addr), NoItinerary,
3360 "ldrexh", "\t$Rt, $addr", []>;
3361 def LDREX : AIldrex<0b00, (outs GPR:$Rt), (ins addrmode7:$addr), NoItinerary,
3362 "ldrex", "\t$Rt, $addr", []>;
3363 def LDREXD : AIldrex<0b01, (outs GPR:$Rt, GPR:$Rt2), (ins addrmode7:$addr),
3364 NoItinerary, "ldrexd", "\t$Rt, $Rt2, $addr", []>;
3367 let mayStore = 1, Constraints = "@earlyclobber $Rd" in {
3368 def STREXB : AIstrex<0b10, (outs GPR:$Rd), (ins GPR:$Rt, addrmode7:$addr),
3369 NoItinerary, "strexb", "\t$Rd, $Rt, $addr", []>;
3370 def STREXH : AIstrex<0b11, (outs GPR:$Rd), (ins GPR:$Rt, addrmode7:$addr),
3371 NoItinerary, "strexh", "\t$Rd, $Rt, $addr", []>;
3372 def STREX : AIstrex<0b00, (outs GPR:$Rd), (ins GPR:$Rt, addrmode7:$addr),
3373 NoItinerary, "strex", "\t$Rd, $Rt, $addr", []>;
3374 def STREXD : AIstrex<0b01, (outs GPR:$Rd),
3375 (ins GPR:$Rt, GPR:$Rt2, addrmode7:$addr),
3376 NoItinerary, "strexd", "\t$Rd, $Rt, $Rt2, $addr", []>;
3379 // Clear-Exclusive is for disassembly only.
3380 def CLREX : AXI<(outs), (ins), MiscFrm, NoItinerary, "clrex",
3381 [/* For disassembly only; pattern left blank */]>,
3382 Requires<[IsARM, HasV7]> {
3383 let Inst{31-0} = 0b11110101011111111111000000011111;
3386 // SWP/SWPB are deprecated in V6/V7 and for disassembly only.
3387 let mayLoad = 1 in {
3388 def SWP : AIswp<0, (outs GPR:$Rt), (ins GPR:$Rt2, GPR:$Rn), "swp",
3389 [/* For disassembly only; pattern left blank */]>;
3390 def SWPB : AIswp<1, (outs GPR:$Rt), (ins GPR:$Rt2, GPR:$Rn), "swpb",
3391 [/* For disassembly only; pattern left blank */]>;
3394 //===----------------------------------------------------------------------===//
3395 // Coprocessor Instructions.
3398 def CDP : ABI<0b1110, (outs), (ins p_imm:$cop, i32imm:$opc1,
3399 c_imm:$CRd, c_imm:$CRn, c_imm:$CRm, i32imm:$opc2),
3400 NoItinerary, "cdp", "\t$cop, $opc1, $CRd, $CRn, $CRm, $opc2",
3401 [/* For disassembly only; pattern left blank */]> {
3409 let Inst{3-0} = CRm;
3411 let Inst{7-5} = opc2;
3412 let Inst{11-8} = cop;
3413 let Inst{15-12} = CRd;
3414 let Inst{19-16} = CRn;
3415 let Inst{23-20} = opc1;
3418 def : ARMPat<(int_arm_cdp imm:$cop, imm:$opc1, imm:$CRd, imm:$CRn,
3419 imm:$CRm, imm:$opc2),
3420 (CDP imm:$cop, imm:$opc1, imm:$CRd, imm:$CRn, imm:$CRm,imm:$opc2)>;
3422 def CDP2 : ABXI<0b1110, (outs), (ins p_imm:$cop, i32imm:$opc1,
3423 c_imm:$CRd, c_imm:$CRn, c_imm:$CRm, i32imm:$opc2),
3424 NoItinerary, "cdp2\t$cop, $opc1, $CRd, $CRn, $CRm, $opc2",
3425 [/* For disassembly only; pattern left blank */]> {
3426 let Inst{31-28} = 0b1111;
3434 let Inst{3-0} = CRm;
3436 let Inst{7-5} = opc2;
3437 let Inst{11-8} = cop;
3438 let Inst{15-12} = CRd;
3439 let Inst{19-16} = CRn;
3440 let Inst{23-20} = opc1;
3443 def : ARMPat<(int_arm_cdp2 imm:$cop, imm:$opc1, imm:$CRd, imm:$CRn,
3444 imm:$CRm, imm:$opc2),
3445 (CDP2 imm:$cop, imm:$opc1, imm:$CRd, imm:$CRn, imm:$CRm,
3448 class ACI<dag oops, dag iops, string opc, string asm,
3449 IndexMode im = IndexModeNone>
3450 : InoP<oops, iops, AddrModeNone, Size4Bytes, im, BrFrm, NoItinerary,
3451 opc, asm, "", [/* For disassembly only; pattern left blank */]> {
3452 let Inst{27-25} = 0b110;
3455 multiclass LdStCop<bits<4> op31_28, bit load, dag ops, string opc, string cond>{
3457 def _OFFSET : ACI<(outs),
3458 !con((ins nohash_imm:$cop, nohash_imm:$CRd, addrmode2:$addr), ops),
3459 !strconcat(opc, cond), "\tp$cop, cr$CRd, $addr"> {
3460 let Inst{31-28} = op31_28;
3461 let Inst{24} = 1; // P = 1
3462 let Inst{21} = 0; // W = 0
3463 let Inst{22} = 0; // D = 0
3464 let Inst{20} = load;
3467 def _PRE : ACI<(outs),
3468 !con((ins nohash_imm:$cop, nohash_imm:$CRd, addrmode2:$addr), ops),
3469 !strconcat(opc, cond), "\tp$cop, cr$CRd, $addr!", IndexModePre> {
3470 let Inst{31-28} = op31_28;
3471 let Inst{24} = 1; // P = 1
3472 let Inst{21} = 1; // W = 1
3473 let Inst{22} = 0; // D = 0
3474 let Inst{20} = load;
3477 def _POST : ACI<(outs),
3478 !con((ins nohash_imm:$cop, nohash_imm:$CRd, addrmode2:$addr), ops),
3479 !strconcat(opc, cond), "\tp$cop, cr$CRd, $addr", IndexModePost> {
3480 let Inst{31-28} = op31_28;
3481 let Inst{24} = 0; // P = 0
3482 let Inst{21} = 1; // W = 1
3483 let Inst{22} = 0; // D = 0
3484 let Inst{20} = load;
3487 def _OPTION : ACI<(outs),
3488 !con((ins nohash_imm:$cop,nohash_imm:$CRd,GPR:$base, nohash_imm:$option),
3490 !strconcat(opc, cond), "\tp$cop, cr$CRd, [$base], \\{$option\\}"> {
3491 let Inst{31-28} = op31_28;
3492 let Inst{24} = 0; // P = 0
3493 let Inst{23} = 1; // U = 1
3494 let Inst{21} = 0; // W = 0
3495 let Inst{22} = 0; // D = 0
3496 let Inst{20} = load;
3499 def L_OFFSET : ACI<(outs),
3500 !con((ins nohash_imm:$cop, nohash_imm:$CRd, addrmode2:$addr), ops),
3501 !strconcat(!strconcat(opc, "l"), cond), "\tp$cop, cr$CRd, $addr"> {
3502 let Inst{31-28} = op31_28;
3503 let Inst{24} = 1; // P = 1
3504 let Inst{21} = 0; // W = 0
3505 let Inst{22} = 1; // D = 1
3506 let Inst{20} = load;
3509 def L_PRE : ACI<(outs),
3510 !con((ins nohash_imm:$cop, nohash_imm:$CRd, addrmode2:$addr), ops),
3511 !strconcat(!strconcat(opc, "l"), cond), "\tp$cop, cr$CRd, $addr!",
3513 let Inst{31-28} = op31_28;
3514 let Inst{24} = 1; // P = 1
3515 let Inst{21} = 1; // W = 1
3516 let Inst{22} = 1; // D = 1
3517 let Inst{20} = load;
3520 def L_POST : ACI<(outs),
3521 !con((ins nohash_imm:$cop, nohash_imm:$CRd, addrmode2:$addr), ops),
3522 !strconcat(!strconcat(opc, "l"), cond), "\tp$cop, cr$CRd, $addr",
3524 let Inst{31-28} = op31_28;
3525 let Inst{24} = 0; // P = 0
3526 let Inst{21} = 1; // W = 1
3527 let Inst{22} = 1; // D = 1
3528 let Inst{20} = load;
3531 def L_OPTION : ACI<(outs),
3532 !con((ins nohash_imm:$cop, nohash_imm:$CRd,GPR:$base,nohash_imm:$option),
3534 !strconcat(!strconcat(opc, "l"), cond),
3535 "\tp$cop, cr$CRd, [$base], \\{$option\\}"> {
3536 let Inst{31-28} = op31_28;
3537 let Inst{24} = 0; // P = 0
3538 let Inst{23} = 1; // U = 1
3539 let Inst{21} = 0; // W = 0
3540 let Inst{22} = 1; // D = 1
3541 let Inst{20} = load;
3545 defm LDC : LdStCop<{?,?,?,?}, 1, (ins pred:$p), "ldc", "${p}">;
3546 defm LDC2 : LdStCop<0b1111, 1, (ins), "ldc2", "">;
3547 defm STC : LdStCop<{?,?,?,?}, 0, (ins pred:$p), "stc", "${p}">;
3548 defm STC2 : LdStCop<0b1111, 0, (ins), "stc2", "">;
3550 //===----------------------------------------------------------------------===//
3551 // Move between coprocessor and ARM core register -- for disassembly only
3554 class MovRCopro<string opc, bit direction, dag oops, dag iops>
3555 : ABI<0b1110, oops, iops, NoItinerary, opc,
3556 "\t$cop, $opc1, $Rt, $CRn, $CRm, $opc2",
3557 [/* For disassembly only; pattern left blank */]> {
3558 let Inst{20} = direction;
3568 let Inst{15-12} = Rt;
3569 let Inst{11-8} = cop;
3570 let Inst{23-21} = opc1;
3571 let Inst{7-5} = opc2;
3572 let Inst{3-0} = CRm;
3573 let Inst{19-16} = CRn;
3576 def MCR : MovRCopro<"mcr", 0 /* from ARM core register to coprocessor */,
3577 (outs), (ins p_imm:$cop, i32imm:$opc1,
3578 GPR:$Rt, c_imm:$CRn, c_imm:$CRm,
3580 def MRC : MovRCopro<"mrc", 1 /* from coprocessor to ARM core register */,
3581 (outs GPR:$Rt), (ins p_imm:$cop, i32imm:$opc1,
3582 c_imm:$CRn, c_imm:$CRm, i32imm:$opc2)>;
3584 def : ARMPat<(int_arm_mcr imm:$cop, imm:$opc1, GPR:$Rt, imm:$CRn,
3585 imm:$CRm, imm:$opc2),
3586 (MCR imm:$cop, imm:$opc1, GPR:$Rt, imm:$CRn, imm:$CRm, imm:$opc2)>;
3587 def : ARMPat<(int_arm_mrc imm:$cop, imm:$opc1, imm:$CRn, imm:$CRm, imm:$opc2),
3588 (MRC imm:$cop, imm:$opc1, imm:$CRn, imm:$CRm, imm:$opc2)>;
3590 class MovRCopro2<string opc, bit direction, dag oops, dag iops>
3591 : ABXI<0b1110, oops, iops, NoItinerary,
3592 !strconcat(opc, "\t$cop, $opc1, $Rt, $CRn, $CRm, $opc2"),
3593 [/* For disassembly only; pattern left blank */]> {
3594 let Inst{31-28} = 0b1111;
3595 let Inst{20} = direction;
3605 let Inst{15-12} = Rt;
3606 let Inst{11-8} = cop;
3607 let Inst{23-21} = opc1;
3608 let Inst{7-5} = opc2;
3609 let Inst{3-0} = CRm;
3610 let Inst{19-16} = CRn;
3613 def MCR2 : MovRCopro2<"mcr2", 0 /* from ARM core register to coprocessor */,
3614 (outs), (ins p_imm:$cop, i32imm:$opc1,
3615 GPR:$Rt, c_imm:$CRn, c_imm:$CRm,
3617 def MRC2 : MovRCopro2<"mrc2", 1 /* from coprocessor to ARM core register */,
3618 (outs GPR:$Rt), (ins p_imm:$cop, i32imm:$opc1,
3619 c_imm:$CRn, c_imm:$CRm,
3622 def : ARMV5TPat<(int_arm_mcr2 imm:$cop, imm:$opc1, GPR:$Rt, imm:$CRn,
3623 imm:$CRm, imm:$opc2),
3624 (MCR2 imm:$cop, imm:$opc1, GPR:$Rt, imm:$CRn,
3625 imm:$CRm, imm:$opc2)>;
3626 def : ARMV5TPat<(int_arm_mrc2 imm:$cop, imm:$opc1, imm:$CRn,
3627 imm:$CRm, imm:$opc2),
3628 (MRC2 imm:$cop, imm:$opc1, imm:$CRn, imm:$CRm, imm:$opc2)>;
3630 class MovRRCopro<string opc, bit direction>
3631 : ABI<0b1100, (outs), (ins p_imm:$cop, i32imm:$opc1,
3632 GPR:$Rt, GPR:$Rt2, c_imm:$CRm),
3633 NoItinerary, opc, "\t$cop, $opc1, $Rt, $Rt2, $CRm",
3634 [/* For disassembly only; pattern left blank */]> {
3635 let Inst{23-21} = 0b010;
3636 let Inst{20} = direction;
3644 let Inst{15-12} = Rt;
3645 let Inst{19-16} = Rt2;
3646 let Inst{11-8} = cop;
3647 let Inst{7-4} = opc1;
3648 let Inst{3-0} = CRm;
3651 def MCRR : MovRRCopro<"mcrr", 0 /* from ARM core register to coprocessor */>;
3652 def MRRC : MovRRCopro<"mrrc", 1 /* from coprocessor to ARM core register */>;
3654 def : ARMV5TEPat<(int_arm_mcrr imm:$cop, imm:$opc1, GPR:$Rt, GPR:$Rt2,
3656 (MCRR imm:$cop, imm:$opc1, GPR:$Rt, GPR:$Rt2, imm:$CRm)>;
3658 class MovRRCopro2<string opc, bit direction>
3659 : ABXI<0b1100, (outs), (ins p_imm:$cop, i32imm:$opc1,
3660 GPR:$Rt, GPR:$Rt2, c_imm:$CRm),
3661 NoItinerary, !strconcat(opc, "\t$cop, $opc1, $Rt, $Rt2, $CRm"),
3662 [/* For disassembly only; pattern left blank */]> {
3663 let Inst{31-28} = 0b1111;
3664 let Inst{23-21} = 0b010;
3665 let Inst{20} = direction;
3673 let Inst{15-12} = Rt;
3674 let Inst{19-16} = Rt2;
3675 let Inst{11-8} = cop;
3676 let Inst{7-4} = opc1;
3677 let Inst{3-0} = CRm;
3680 def MCRR2 : MovRRCopro2<"mcrr2", 0 /* from ARM core register to coprocessor */>;
3681 def MRRC2 : MovRRCopro2<"mrrc2", 1 /* from coprocessor to ARM core register */>;
3683 def : ARMV6Pat<(int_arm_mcrr2 imm:$cop, imm:$opc1, GPR:$Rt, GPR:$Rt2, imm:$CRm),
3684 (MCRR2 imm:$cop, imm:$opc1, GPR:$Rt, GPR:$Rt2, imm:$CRm)>;
3686 //===----------------------------------------------------------------------===//
3687 // Move between special register and ARM core register -- for disassembly only
3690 // Move to ARM core register from Special Register
3691 def MRS : ABI<0b0001, (outs GPR:$Rd), (ins), NoItinerary, "mrs", "\t$Rd, cpsr",
3692 [/* For disassembly only; pattern left blank */]> {
3694 let Inst{23-16} = 0b00001111;
3695 let Inst{15-12} = Rd;
3696 let Inst{7-4} = 0b0000;
3699 def MRSsys : ABI<0b0001, (outs GPR:$Rd), (ins), NoItinerary,"mrs","\t$Rd, spsr",
3700 [/* For disassembly only; pattern left blank */]> {
3702 let Inst{23-16} = 0b01001111;
3703 let Inst{15-12} = Rd;
3704 let Inst{7-4} = 0b0000;
3707 // Move from ARM core register to Special Register
3709 // No need to have both system and application versions, the encodings are the
3710 // same and the assembly parser has no way to distinguish between them. The mask
3711 // operand contains the special register (R Bit) in bit 4 and bits 3-0 contains
3712 // the mask with the fields to be accessed in the special register.
3713 def MSR : ABI<0b0001, (outs), (ins msr_mask:$mask, GPR:$Rn), NoItinerary,
3714 "msr", "\t$mask, $Rn",
3715 [/* For disassembly only; pattern left blank */]> {
3720 let Inst{22} = mask{4}; // R bit
3721 let Inst{21-20} = 0b10;
3722 let Inst{19-16} = mask{3-0};
3723 let Inst{15-12} = 0b1111;
3724 let Inst{11-4} = 0b00000000;
3728 def MSRi : ABI<0b0011, (outs), (ins msr_mask:$mask, so_imm:$a), NoItinerary,
3729 "msr", "\t$mask, $a",
3730 [/* For disassembly only; pattern left blank */]> {
3735 let Inst{22} = mask{4}; // R bit
3736 let Inst{21-20} = 0b10;
3737 let Inst{19-16} = mask{3-0};
3738 let Inst{15-12} = 0b1111;
3742 //===----------------------------------------------------------------------===//
3746 // __aeabi_read_tp preserves the registers r1-r3.
3747 // This is a pseudo inst so that we can get the encoding right,
3748 // complete with fixup for the aeabi_read_tp function.
3750 Defs = [R0, R12, LR, CPSR], Uses = [SP] in {
3751 def TPsoft : PseudoInst<(outs), (ins), IIC_Br,
3752 [(set R0, ARMthread_pointer)]>;
3755 //===----------------------------------------------------------------------===//
3756 // SJLJ Exception handling intrinsics
3757 // eh_sjlj_setjmp() is an instruction sequence to store the return
3758 // address and save #0 in R0 for the non-longjmp case.
3759 // Since by its nature we may be coming from some other function to get
3760 // here, and we're using the stack frame for the containing function to
3761 // save/restore registers, we can't keep anything live in regs across
3762 // the eh_sjlj_setjmp(), else it will almost certainly have been tromped upon
3763 // when we get here from a longjmp(). We force everything out of registers
3764 // except for our own input by listing the relevant registers in Defs. By
3765 // doing so, we also cause the prologue/epilogue code to actively preserve
3766 // all of the callee-saved resgisters, which is exactly what we want.
3767 // A constant value is passed in $val, and we use the location as a scratch.
3769 // These are pseudo-instructions and are lowered to individual MC-insts, so
3770 // no encoding information is necessary.
3772 [ R0, R1, R2, R3, R4, R5, R6, R7, R8, R9, R10, R11, R12, LR, D0,
3773 D1, D2, D3, D4, D5, D6, D7, D8, D9, D10, D11, D12, D13, D14, D15,
3774 D16, D17, D18, D19, D20, D21, D22, D23, D24, D25, D26, D27, D28, D29, D30,
3775 D31 ], hasSideEffects = 1, isBarrier = 1 in {
3776 def Int_eh_sjlj_setjmp : PseudoInst<(outs), (ins GPR:$src, GPR:$val),
3778 [(set R0, (ARMeh_sjlj_setjmp GPR:$src, GPR:$val))]>,
3779 Requires<[IsARM, HasVFP2]>;
3783 [ R0, R1, R2, R3, R4, R5, R6, R7, R8, R9, R10, R11, R12, LR ],
3784 hasSideEffects = 1, isBarrier = 1 in {
3785 def Int_eh_sjlj_setjmp_nofp : PseudoInst<(outs), (ins GPR:$src, GPR:$val),
3787 [(set R0, (ARMeh_sjlj_setjmp GPR:$src, GPR:$val))]>,
3788 Requires<[IsARM, NoVFP]>;
3791 // FIXME: Non-Darwin version(s)
3792 let isBarrier = 1, hasSideEffects = 1, isTerminator = 1,
3793 Defs = [ R7, LR, SP ] in {
3794 def Int_eh_sjlj_longjmp : PseudoInst<(outs), (ins GPR:$src, GPR:$scratch),
3796 [(ARMeh_sjlj_longjmp GPR:$src, GPR:$scratch)]>,
3797 Requires<[IsARM, IsDarwin]>;
3800 // eh.sjlj.dispatchsetup pseudo-instruction.
3801 // This pseudo is used for ARM, Thumb1 and Thumb2. Any differences are
3802 // handled when the pseudo is expanded (which happens before any passes
3803 // that need the instruction size).
3804 let isBarrier = 1, hasSideEffects = 1 in
3805 def Int_eh_sjlj_dispatchsetup :
3806 PseudoInst<(outs), (ins), NoItinerary,
3807 [(ARMeh_sjlj_dispatchsetup)]>,
3808 Requires<[IsDarwin]>;
3810 //===----------------------------------------------------------------------===//
3811 // Non-Instruction Patterns
3814 // Large immediate handling.
3816 // 32-bit immediate using two piece so_imms or movw + movt.
3817 // This is a single pseudo instruction, the benefit is that it can be remat'd
3818 // as a single unit instead of having to handle reg inputs.
3819 // FIXME: Remove this when we can do generalized remat.
3820 let isReMaterializable = 1, isMoveImm = 1 in
3821 def MOVi32imm : PseudoInst<(outs GPR:$dst), (ins i32imm:$src), IIC_iMOVix2,
3822 [(set GPR:$dst, (arm_i32imm:$src))]>,
3825 // Pseudo instruction that combines movw + movt + add pc (if PIC).
3826 // It also makes it possible to rematerialize the instructions.
3827 // FIXME: Remove this when we can do generalized remat and when machine licm
3828 // can properly the instructions.
3829 let isReMaterializable = 1 in {
3830 def MOV_ga_pcrel : PseudoInst<(outs GPR:$dst), (ins i32imm:$addr),
3832 [(set GPR:$dst, (ARMWrapperPIC tglobaladdr:$addr))]>,
3833 Requires<[IsARM, UseMovt]>;
3835 def MOV_ga_dyn : PseudoInst<(outs GPR:$dst), (ins i32imm:$addr),
3837 [(set GPR:$dst, (ARMWrapperDYN tglobaladdr:$addr))]>,
3838 Requires<[IsARM, UseMovt]>;
3840 let AddedComplexity = 10 in
3841 def MOV_ga_pcrel_ldr : PseudoInst<(outs GPR:$dst), (ins i32imm:$addr),
3843 [(set GPR:$dst, (load (ARMWrapperPIC tglobaladdr:$addr)))]>,
3844 Requires<[IsARM, UseMovt]>;
3845 } // isReMaterializable
3847 // ConstantPool, GlobalAddress, and JumpTable
3848 def : ARMPat<(ARMWrapper tglobaladdr :$dst), (LEApcrel tglobaladdr :$dst)>,
3849 Requires<[IsARM, DontUseMovt]>;
3850 def : ARMPat<(ARMWrapper tconstpool :$dst), (LEApcrel tconstpool :$dst)>;
3851 def : ARMPat<(ARMWrapper tglobaladdr :$dst), (MOVi32imm tglobaladdr :$dst)>,
3852 Requires<[IsARM, UseMovt]>;
3853 def : ARMPat<(ARMWrapperJT tjumptable:$dst, imm:$id),
3854 (LEApcrelJT tjumptable:$dst, imm:$id)>;
3856 // TODO: add,sub,and, 3-instr forms?
3859 def : ARMPat<(ARMtcret tcGPR:$dst),
3860 (TCRETURNri tcGPR:$dst)>, Requires<[IsDarwin]>;
3862 def : ARMPat<(ARMtcret (i32 tglobaladdr:$dst)),
3863 (TCRETURNdi texternalsym:$dst)>, Requires<[IsDarwin]>;
3865 def : ARMPat<(ARMtcret (i32 texternalsym:$dst)),
3866 (TCRETURNdi texternalsym:$dst)>, Requires<[IsDarwin]>;
3868 def : ARMPat<(ARMtcret tcGPR:$dst),
3869 (TCRETURNriND tcGPR:$dst)>, Requires<[IsNotDarwin]>;
3871 def : ARMPat<(ARMtcret (i32 tglobaladdr:$dst)),
3872 (TCRETURNdiND texternalsym:$dst)>, Requires<[IsNotDarwin]>;
3874 def : ARMPat<(ARMtcret (i32 texternalsym:$dst)),
3875 (TCRETURNdiND texternalsym:$dst)>, Requires<[IsNotDarwin]>;
3878 def : ARMPat<(ARMcall texternalsym:$func), (BL texternalsym:$func)>,
3879 Requires<[IsARM, IsNotDarwin]>;
3880 def : ARMPat<(ARMcall texternalsym:$func), (BLr9 texternalsym:$func)>,
3881 Requires<[IsARM, IsDarwin]>;
3883 // zextload i1 -> zextload i8
3884 def : ARMPat<(zextloadi1 addrmode_imm12:$addr), (LDRBi12 addrmode_imm12:$addr)>;
3885 def : ARMPat<(zextloadi1 ldst_so_reg:$addr), (LDRBrs ldst_so_reg:$addr)>;
3887 // extload -> zextload
3888 def : ARMPat<(extloadi1 addrmode_imm12:$addr), (LDRBi12 addrmode_imm12:$addr)>;
3889 def : ARMPat<(extloadi1 ldst_so_reg:$addr), (LDRBrs ldst_so_reg:$addr)>;
3890 def : ARMPat<(extloadi8 addrmode_imm12:$addr), (LDRBi12 addrmode_imm12:$addr)>;
3891 def : ARMPat<(extloadi8 ldst_so_reg:$addr), (LDRBrs ldst_so_reg:$addr)>;
3893 def : ARMPat<(extloadi16 addrmode3:$addr), (LDRH addrmode3:$addr)>;
3895 def : ARMPat<(extloadi8 addrmodepc:$addr), (PICLDRB addrmodepc:$addr)>;
3896 def : ARMPat<(extloadi16 addrmodepc:$addr), (PICLDRH addrmodepc:$addr)>;
3899 def : ARMV5TEPat<(mul (sra (shl GPR:$a, (i32 16)), (i32 16)),
3900 (sra (shl GPR:$b, (i32 16)), (i32 16))),
3901 (SMULBB GPR:$a, GPR:$b)>;
3902 def : ARMV5TEPat<(mul sext_16_node:$a, sext_16_node:$b),
3903 (SMULBB GPR:$a, GPR:$b)>;
3904 def : ARMV5TEPat<(mul (sra (shl GPR:$a, (i32 16)), (i32 16)),
3905 (sra GPR:$b, (i32 16))),
3906 (SMULBT GPR:$a, GPR:$b)>;
3907 def : ARMV5TEPat<(mul sext_16_node:$a, (sra GPR:$b, (i32 16))),
3908 (SMULBT GPR:$a, GPR:$b)>;
3909 def : ARMV5TEPat<(mul (sra GPR:$a, (i32 16)),
3910 (sra (shl GPR:$b, (i32 16)), (i32 16))),
3911 (SMULTB GPR:$a, GPR:$b)>;
3912 def : ARMV5TEPat<(mul (sra GPR:$a, (i32 16)), sext_16_node:$b),
3913 (SMULTB GPR:$a, GPR:$b)>;
3914 def : ARMV5TEPat<(sra (mul GPR:$a, (sra (shl GPR:$b, (i32 16)), (i32 16))),
3916 (SMULWB GPR:$a, GPR:$b)>;
3917 def : ARMV5TEPat<(sra (mul GPR:$a, sext_16_node:$b), (i32 16)),
3918 (SMULWB GPR:$a, GPR:$b)>;
3920 def : ARMV5TEPat<(add GPR:$acc,
3921 (mul (sra (shl GPR:$a, (i32 16)), (i32 16)),
3922 (sra (shl GPR:$b, (i32 16)), (i32 16)))),
3923 (SMLABB GPR:$a, GPR:$b, GPR:$acc)>;
3924 def : ARMV5TEPat<(add GPR:$acc,
3925 (mul sext_16_node:$a, sext_16_node:$b)),
3926 (SMLABB GPR:$a, GPR:$b, GPR:$acc)>;
3927 def : ARMV5TEPat<(add GPR:$acc,
3928 (mul (sra (shl GPR:$a, (i32 16)), (i32 16)),
3929 (sra GPR:$b, (i32 16)))),
3930 (SMLABT GPR:$a, GPR:$b, GPR:$acc)>;
3931 def : ARMV5TEPat<(add GPR:$acc,
3932 (mul sext_16_node:$a, (sra GPR:$b, (i32 16)))),
3933 (SMLABT GPR:$a, GPR:$b, GPR:$acc)>;
3934 def : ARMV5TEPat<(add GPR:$acc,
3935 (mul (sra GPR:$a, (i32 16)),
3936 (sra (shl GPR:$b, (i32 16)), (i32 16)))),
3937 (SMLATB GPR:$a, GPR:$b, GPR:$acc)>;
3938 def : ARMV5TEPat<(add GPR:$acc,
3939 (mul (sra GPR:$a, (i32 16)), sext_16_node:$b)),
3940 (SMLATB GPR:$a, GPR:$b, GPR:$acc)>;
3941 def : ARMV5TEPat<(add GPR:$acc,
3942 (sra (mul GPR:$a, (sra (shl GPR:$b, (i32 16)), (i32 16))),
3944 (SMLAWB GPR:$a, GPR:$b, GPR:$acc)>;
3945 def : ARMV5TEPat<(add GPR:$acc,
3946 (sra (mul GPR:$a, sext_16_node:$b), (i32 16))),
3947 (SMLAWB GPR:$a, GPR:$b, GPR:$acc)>;
3950 // Pre-v7 uses MCR for synchronization barriers.
3951 def : ARMPat<(ARMMemBarrierMCR GPR:$zero), (MCR 15, 0, GPR:$zero, 7, 10, 5)>,
3952 Requires<[IsARM, HasV6]>;
3955 //===----------------------------------------------------------------------===//
3959 include "ARMInstrThumb.td"
3961 //===----------------------------------------------------------------------===//
3965 include "ARMInstrThumb2.td"
3967 //===----------------------------------------------------------------------===//
3968 // Floating Point Support
3971 include "ARMInstrVFP.td"
3973 //===----------------------------------------------------------------------===//
3974 // Advanced SIMD (NEON) Support
3977 include "ARMInstrNEON.td"