1 //===- ARMInstrInfo.td - Target Description for ARM Target -*- tablegen -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file describes the ARM instructions in TableGen format.
12 //===----------------------------------------------------------------------===//
14 //===----------------------------------------------------------------------===//
15 // ARM specific DAG Nodes.
19 def SDT_ARMCallSeqStart : SDCallSeqStart<[ SDTCisVT<0, i32> ]>;
20 def SDT_ARMCallSeqEnd : SDCallSeqEnd<[ SDTCisVT<0, i32>, SDTCisVT<1, i32> ]>;
22 def SDT_ARMSaveCallPC : SDTypeProfile<0, 1, []>;
24 def SDT_ARMcall : SDTypeProfile<0, -1, [SDTCisPtrTy<0>]>;
26 def SDT_ARMCMov : SDTypeProfile<1, 3,
27 [SDTCisSameAs<0, 1>, SDTCisSameAs<0, 2>,
30 def SDT_ARMBrcond : SDTypeProfile<0, 2,
31 [SDTCisVT<0, OtherVT>, SDTCisVT<1, i32>]>;
33 def SDT_ARMBrJT : SDTypeProfile<0, 3,
34 [SDTCisPtrTy<0>, SDTCisVT<1, i32>,
37 def SDT_ARMBr2JT : SDTypeProfile<0, 4,
38 [SDTCisPtrTy<0>, SDTCisVT<1, i32>,
39 SDTCisVT<2, i32>, SDTCisVT<3, i32>]>;
41 def SDT_ARMBCC_i64 : SDTypeProfile<0, 6,
43 SDTCisVT<1, i32>, SDTCisVT<2, i32>,
44 SDTCisVT<3, i32>, SDTCisVT<4, i32>,
45 SDTCisVT<5, OtherVT>]>;
47 def SDT_ARMAnd : SDTypeProfile<1, 2,
48 [SDTCisVT<0, i32>, SDTCisVT<1, i32>,
51 def SDT_ARMCmp : SDTypeProfile<0, 2, [SDTCisSameAs<0, 1>]>;
53 def SDT_ARMPICAdd : SDTypeProfile<1, 2, [SDTCisSameAs<0, 1>,
54 SDTCisPtrTy<1>, SDTCisVT<2, i32>]>;
56 def SDT_ARMThreadPointer : SDTypeProfile<1, 0, [SDTCisPtrTy<0>]>;
57 def SDT_ARMEH_SJLJ_Setjmp : SDTypeProfile<1, 2, [SDTCisInt<0>, SDTCisPtrTy<1>,
59 def SDT_ARMEH_SJLJ_Longjmp: SDTypeProfile<0, 2, [SDTCisPtrTy<0>, SDTCisInt<1>]>;
61 def SDT_ARMEH_SJLJ_DispatchSetup: SDTypeProfile<0, 1, [SDTCisInt<0>]>;
63 def SDT_ARMMEMBARRIER : SDTypeProfile<0, 1, [SDTCisInt<0>]>;
65 def SDT_ARMPREFETCH : SDTypeProfile<0, 3, [SDTCisPtrTy<0>, SDTCisSameAs<1, 2>,
68 def SDT_ARMTCRET : SDTypeProfile<0, 1, [SDTCisPtrTy<0>]>;
70 def SDT_ARMBFI : SDTypeProfile<1, 3, [SDTCisVT<0, i32>, SDTCisVT<1, i32>,
71 SDTCisVT<2, i32>, SDTCisVT<3, i32>]>;
73 def SDTBinaryArithWithFlags : SDTypeProfile<2, 2,
76 SDTCisInt<0>, SDTCisVT<1, i32>]>;
78 // SDTBinaryArithWithFlagsInOut - RES1, CPSR = op LHS, RHS, CPSR
79 def SDTBinaryArithWithFlagsInOut : SDTypeProfile<2, 3,
86 def ARMWrapper : SDNode<"ARMISD::Wrapper", SDTIntUnaryOp>;
87 def ARMWrapperDYN : SDNode<"ARMISD::WrapperDYN", SDTIntUnaryOp>;
88 def ARMWrapperPIC : SDNode<"ARMISD::WrapperPIC", SDTIntUnaryOp>;
89 def ARMWrapperJT : SDNode<"ARMISD::WrapperJT", SDTIntBinOp>;
91 def ARMcallseq_start : SDNode<"ISD::CALLSEQ_START", SDT_ARMCallSeqStart,
92 [SDNPHasChain, SDNPOutGlue]>;
93 def ARMcallseq_end : SDNode<"ISD::CALLSEQ_END", SDT_ARMCallSeqEnd,
94 [SDNPHasChain, SDNPOptInGlue, SDNPOutGlue]>;
96 def ARMcall : SDNode<"ARMISD::CALL", SDT_ARMcall,
97 [SDNPHasChain, SDNPOptInGlue, SDNPOutGlue,
99 def ARMcall_pred : SDNode<"ARMISD::CALL_PRED", SDT_ARMcall,
100 [SDNPHasChain, SDNPOptInGlue, SDNPOutGlue,
102 def ARMcall_nolink : SDNode<"ARMISD::CALL_NOLINK", SDT_ARMcall,
103 [SDNPHasChain, SDNPOptInGlue, SDNPOutGlue,
106 def ARMretflag : SDNode<"ARMISD::RET_FLAG", SDTNone,
107 [SDNPHasChain, SDNPOptInGlue]>;
109 def ARMcmov : SDNode<"ARMISD::CMOV", SDT_ARMCMov,
112 def ARMbrcond : SDNode<"ARMISD::BRCOND", SDT_ARMBrcond,
113 [SDNPHasChain, SDNPInGlue, SDNPOutGlue]>;
115 def ARMbrjt : SDNode<"ARMISD::BR_JT", SDT_ARMBrJT,
117 def ARMbr2jt : SDNode<"ARMISD::BR2_JT", SDT_ARMBr2JT,
120 def ARMBcci64 : SDNode<"ARMISD::BCC_i64", SDT_ARMBCC_i64,
123 def ARMcmp : SDNode<"ARMISD::CMP", SDT_ARMCmp,
126 def ARMcmpZ : SDNode<"ARMISD::CMPZ", SDT_ARMCmp,
127 [SDNPOutGlue, SDNPCommutative]>;
129 def ARMpic_add : SDNode<"ARMISD::PIC_ADD", SDT_ARMPICAdd>;
131 def ARMsrl_flag : SDNode<"ARMISD::SRL_FLAG", SDTIntUnaryOp, [SDNPOutGlue]>;
132 def ARMsra_flag : SDNode<"ARMISD::SRA_FLAG", SDTIntUnaryOp, [SDNPOutGlue]>;
133 def ARMrrx : SDNode<"ARMISD::RRX" , SDTIntUnaryOp, [SDNPInGlue ]>;
135 def ARMaddc : SDNode<"ARMISD::ADDC", SDTBinaryArithWithFlags,
137 def ARMsubc : SDNode<"ARMISD::SUBC", SDTBinaryArithWithFlags>;
138 def ARMadde : SDNode<"ARMISD::ADDE", SDTBinaryArithWithFlagsInOut>;
139 def ARMsube : SDNode<"ARMISD::SUBE", SDTBinaryArithWithFlagsInOut>;
141 def ARMthread_pointer: SDNode<"ARMISD::THREAD_POINTER", SDT_ARMThreadPointer>;
142 def ARMeh_sjlj_setjmp: SDNode<"ARMISD::EH_SJLJ_SETJMP",
143 SDT_ARMEH_SJLJ_Setjmp, [SDNPHasChain]>;
144 def ARMeh_sjlj_longjmp: SDNode<"ARMISD::EH_SJLJ_LONGJMP",
145 SDT_ARMEH_SJLJ_Longjmp, [SDNPHasChain]>;
146 def ARMeh_sjlj_dispatchsetup: SDNode<"ARMISD::EH_SJLJ_DISPATCHSETUP",
147 SDT_ARMEH_SJLJ_DispatchSetup, [SDNPHasChain]>;
150 def ARMMemBarrier : SDNode<"ARMISD::MEMBARRIER", SDT_ARMMEMBARRIER,
152 def ARMMemBarrierMCR : SDNode<"ARMISD::MEMBARRIER_MCR", SDT_ARMMEMBARRIER,
154 def ARMPreload : SDNode<"ARMISD::PRELOAD", SDT_ARMPREFETCH,
155 [SDNPHasChain, SDNPMayLoad, SDNPMayStore]>;
157 def ARMrbit : SDNode<"ARMISD::RBIT", SDTIntUnaryOp>;
159 def ARMtcret : SDNode<"ARMISD::TC_RETURN", SDT_ARMTCRET,
160 [SDNPHasChain, SDNPOptInGlue, SDNPVariadic]>;
163 def ARMbfi : SDNode<"ARMISD::BFI", SDT_ARMBFI>;
165 //===----------------------------------------------------------------------===//
166 // ARM Instruction Predicate Definitions.
168 def HasV4T : Predicate<"Subtarget->hasV4TOps()">,
169 AssemblerPredicate<"HasV4TOps">;
170 def NoV4T : Predicate<"!Subtarget->hasV4TOps()">;
171 def HasV5T : Predicate<"Subtarget->hasV5TOps()">;
172 def HasV5TE : Predicate<"Subtarget->hasV5TEOps()">,
173 AssemblerPredicate<"HasV5TEOps">;
174 def HasV6 : Predicate<"Subtarget->hasV6Ops()">,
175 AssemblerPredicate<"HasV6Ops">;
176 def NoV6 : Predicate<"!Subtarget->hasV6Ops()">;
177 def HasV6T2 : Predicate<"Subtarget->hasV6T2Ops()">,
178 AssemblerPredicate<"HasV6T2Ops">;
179 def NoV6T2 : Predicate<"!Subtarget->hasV6T2Ops()">;
180 def HasV7 : Predicate<"Subtarget->hasV7Ops()">,
181 AssemblerPredicate<"HasV7Ops">;
182 def NoVFP : Predicate<"!Subtarget->hasVFP2()">;
183 def HasVFP2 : Predicate<"Subtarget->hasVFP2()">,
184 AssemblerPredicate<"FeatureVFP2">;
185 def HasVFP3 : Predicate<"Subtarget->hasVFP3()">,
186 AssemblerPredicate<"FeatureVFP3">;
187 def HasNEON : Predicate<"Subtarget->hasNEON()">,
188 AssemblerPredicate<"FeatureNEON">;
189 def HasFP16 : Predicate<"Subtarget->hasFP16()">,
190 AssemblerPredicate<"FeatureFP16">;
191 def HasDivide : Predicate<"Subtarget->hasDivide()">,
192 AssemblerPredicate<"FeatureHWDiv">;
193 def HasT2ExtractPack : Predicate<"Subtarget->hasT2ExtractPack()">,
194 AssemblerPredicate<"FeatureT2XtPk">;
195 def HasThumb2DSP : Predicate<"Subtarget->hasThumb2DSP()">,
196 AssemblerPredicate<"FeatureDSPThumb2">;
197 def HasDB : Predicate<"Subtarget->hasDataBarrier()">,
198 AssemblerPredicate<"FeatureDB">;
199 def HasMP : Predicate<"Subtarget->hasMPExtension()">,
200 AssemblerPredicate<"FeatureMP">;
201 def UseNEONForFP : Predicate<"Subtarget->useNEONForSinglePrecisionFP()">;
202 def DontUseNEONForFP : Predicate<"!Subtarget->useNEONForSinglePrecisionFP()">;
203 def IsThumb : Predicate<"Subtarget->isThumb()">,
204 AssemblerPredicate<"ModeThumb">;
205 def IsThumb1Only : Predicate<"Subtarget->isThumb1Only()">;
206 def IsThumb2 : Predicate<"Subtarget->isThumb2()">,
207 AssemblerPredicate<"ModeThumb,FeatureThumb2">;
208 def IsMClass : Predicate<"Subtarget->isMClass()">,
209 AssemblerPredicate<"FeatureMClass">;
210 def IsARClass : Predicate<"!Subtarget->isMClass()">,
211 AssemblerPredicate<"!FeatureMClass">;
212 def IsARM : Predicate<"!Subtarget->isThumb()">,
213 AssemblerPredicate<"!ModeThumb">;
214 def IsDarwin : Predicate<"Subtarget->isTargetDarwin()">;
215 def IsNotDarwin : Predicate<"!Subtarget->isTargetDarwin()">;
216 def IsNaCl : Predicate<"Subtarget->isTargetNaCl()">;
218 // FIXME: Eventually this will be just "hasV6T2Ops".
219 def UseMovt : Predicate<"Subtarget->useMovt()">;
220 def DontUseMovt : Predicate<"!Subtarget->useMovt()">;
221 def UseFPVMLx : Predicate<"Subtarget->useFPVMLx()">;
223 //===----------------------------------------------------------------------===//
224 // ARM Flag Definitions.
226 class RegConstraint<string C> {
227 string Constraints = C;
230 //===----------------------------------------------------------------------===//
231 // ARM specific transformation functions and pattern fragments.
234 // so_imm_neg_XFORM - Return a so_imm value packed into the format described for
235 // so_imm_neg def below.
236 def so_imm_neg_XFORM : SDNodeXForm<imm, [{
237 return CurDAG->getTargetConstant(-(int)N->getZExtValue(), MVT::i32);
240 // so_imm_not_XFORM - Return a so_imm value packed into the format described for
241 // so_imm_not def below.
242 def so_imm_not_XFORM : SDNodeXForm<imm, [{
243 return CurDAG->getTargetConstant(~(int)N->getZExtValue(), MVT::i32);
246 /// imm1_15 predicate - True if the 32-bit immediate is in the range [1,15].
247 def imm1_15 : ImmLeaf<i32, [{
248 return (int32_t)Imm >= 1 && (int32_t)Imm < 16;
251 /// imm16_31 predicate - True if the 32-bit immediate is in the range [16,31].
252 def imm16_31 : ImmLeaf<i32, [{
253 return (int32_t)Imm >= 16 && (int32_t)Imm < 32;
258 return ARM_AM::getSOImmVal(-(uint32_t)N->getZExtValue()) != -1;
259 }], so_imm_neg_XFORM>;
261 // Note: this pattern doesn't require an encoder method and such, as it's
262 // only used on aliases (Pat<> and InstAlias<>). The actual encoding
263 // is handled by the destination instructions, which use t2_so_imm.
264 def so_imm_not_asmoperand : AsmOperandClass { let Name = "ARMSOImmNot"; }
266 Operand<i32>, PatLeaf<(imm), [{
267 return ARM_AM::getSOImmVal(~(uint32_t)N->getZExtValue()) != -1;
268 }], so_imm_not_XFORM> {
269 let ParserMatchClass = so_imm_not_asmoperand;
272 // sext_16_node predicate - True if the SDNode is sign-extended 16 or more bits.
273 def sext_16_node : PatLeaf<(i32 GPR:$a), [{
274 return CurDAG->ComputeNumSignBits(SDValue(N,0)) >= 17;
277 /// Split a 32-bit immediate into two 16 bit parts.
278 def hi16 : SDNodeXForm<imm, [{
279 return CurDAG->getTargetConstant((uint32_t)N->getZExtValue() >> 16, MVT::i32);
282 def lo16AllZero : PatLeaf<(i32 imm), [{
283 // Returns true if all low 16-bits are 0.
284 return (((uint32_t)N->getZExtValue()) & 0xFFFFUL) == 0;
287 class BinOpWithFlagFrag<dag res> :
288 PatFrag<(ops node:$LHS, node:$RHS, node:$FLAG), res>;
289 class BinOpFrag<dag res> : PatFrag<(ops node:$LHS, node:$RHS), res>;
290 class UnOpFrag <dag res> : PatFrag<(ops node:$Src), res>;
292 // An 'and' node with a single use.
293 def and_su : PatFrag<(ops node:$lhs, node:$rhs), (and node:$lhs, node:$rhs), [{
294 return N->hasOneUse();
297 // An 'xor' node with a single use.
298 def xor_su : PatFrag<(ops node:$lhs, node:$rhs), (xor node:$lhs, node:$rhs), [{
299 return N->hasOneUse();
302 // An 'fmul' node with a single use.
303 def fmul_su : PatFrag<(ops node:$lhs, node:$rhs), (fmul node:$lhs, node:$rhs),[{
304 return N->hasOneUse();
307 // An 'fadd' node which checks for single non-hazardous use.
308 def fadd_mlx : PatFrag<(ops node:$lhs, node:$rhs),(fadd node:$lhs, node:$rhs),[{
309 return hasNoVMLxHazardUse(N);
312 // An 'fsub' node which checks for single non-hazardous use.
313 def fsub_mlx : PatFrag<(ops node:$lhs, node:$rhs),(fsub node:$lhs, node:$rhs),[{
314 return hasNoVMLxHazardUse(N);
317 //===----------------------------------------------------------------------===//
318 // Operand Definitions.
321 // Immediate operands with a shared generic asm render method.
322 class ImmAsmOperand : AsmOperandClass { let RenderMethod = "addImmOperands"; }
325 // FIXME: rename brtarget to t2_brtarget
326 def brtarget : Operand<OtherVT> {
327 let EncoderMethod = "getBranchTargetOpValue";
328 let OperandType = "OPERAND_PCREL";
329 let DecoderMethod = "DecodeT2BROperand";
332 // FIXME: get rid of this one?
333 def uncondbrtarget : Operand<OtherVT> {
334 let EncoderMethod = "getUnconditionalBranchTargetOpValue";
335 let OperandType = "OPERAND_PCREL";
338 // Branch target for ARM. Handles conditional/unconditional
339 def br_target : Operand<OtherVT> {
340 let EncoderMethod = "getARMBranchTargetOpValue";
341 let OperandType = "OPERAND_PCREL";
345 // FIXME: rename bltarget to t2_bl_target?
346 def bltarget : Operand<i32> {
347 // Encoded the same as branch targets.
348 let EncoderMethod = "getBranchTargetOpValue";
349 let OperandType = "OPERAND_PCREL";
352 // Call target for ARM. Handles conditional/unconditional
353 // FIXME: rename bl_target to t2_bltarget?
354 def bl_target : Operand<i32> {
355 // Encoded the same as branch targets.
356 let EncoderMethod = "getARMBranchTargetOpValue";
357 let OperandType = "OPERAND_PCREL";
360 def blx_target : Operand<i32> {
361 // Encoded the same as branch targets.
362 let EncoderMethod = "getARMBLXTargetOpValue";
363 let OperandType = "OPERAND_PCREL";
366 // A list of registers separated by comma. Used by load/store multiple.
367 def RegListAsmOperand : AsmOperandClass { let Name = "RegList"; }
368 def reglist : Operand<i32> {
369 let EncoderMethod = "getRegisterListOpValue";
370 let ParserMatchClass = RegListAsmOperand;
371 let PrintMethod = "printRegisterList";
372 let DecoderMethod = "DecodeRegListOperand";
375 def DPRRegListAsmOperand : AsmOperandClass { let Name = "DPRRegList"; }
376 def dpr_reglist : Operand<i32> {
377 let EncoderMethod = "getRegisterListOpValue";
378 let ParserMatchClass = DPRRegListAsmOperand;
379 let PrintMethod = "printRegisterList";
380 let DecoderMethod = "DecodeDPRRegListOperand";
383 def SPRRegListAsmOperand : AsmOperandClass { let Name = "SPRRegList"; }
384 def spr_reglist : Operand<i32> {
385 let EncoderMethod = "getRegisterListOpValue";
386 let ParserMatchClass = SPRRegListAsmOperand;
387 let PrintMethod = "printRegisterList";
388 let DecoderMethod = "DecodeSPRRegListOperand";
391 // An operand for the CONSTPOOL_ENTRY pseudo-instruction.
392 def cpinst_operand : Operand<i32> {
393 let PrintMethod = "printCPInstOperand";
397 def pclabel : Operand<i32> {
398 let PrintMethod = "printPCLabel";
401 // ADR instruction labels.
402 def adrlabel : Operand<i32> {
403 let EncoderMethod = "getAdrLabelOpValue";
406 def neon_vcvt_imm32 : Operand<i32> {
407 let EncoderMethod = "getNEONVcvtImm32OpValue";
408 let DecoderMethod = "DecodeVCVTImmOperand";
411 // rot_imm: An integer that encodes a rotate amount. Must be 8, 16, or 24.
412 def rot_imm_XFORM: SDNodeXForm<imm, [{
413 switch (N->getZExtValue()){
415 case 0: return CurDAG->getTargetConstant(0, MVT::i32);
416 case 8: return CurDAG->getTargetConstant(1, MVT::i32);
417 case 16: return CurDAG->getTargetConstant(2, MVT::i32);
418 case 24: return CurDAG->getTargetConstant(3, MVT::i32);
421 def RotImmAsmOperand : AsmOperandClass {
423 let ParserMethod = "parseRotImm";
425 def rot_imm : Operand<i32>, PatLeaf<(i32 imm), [{
426 int32_t v = N->getZExtValue();
427 return v == 8 || v == 16 || v == 24; }],
429 let PrintMethod = "printRotImmOperand";
430 let ParserMatchClass = RotImmAsmOperand;
433 // shift_imm: An integer that encodes a shift amount and the type of shift
434 // (asr or lsl). The 6-bit immediate encodes as:
437 // {4-0} imm5 shift amount.
438 // asr #32 encoded as imm5 == 0.
439 def ShifterImmAsmOperand : AsmOperandClass {
440 let Name = "ShifterImm";
441 let ParserMethod = "parseShifterImm";
443 def shift_imm : Operand<i32> {
444 let PrintMethod = "printShiftImmOperand";
445 let ParserMatchClass = ShifterImmAsmOperand;
448 // shifter_operand operands: so_reg_reg, so_reg_imm, and so_imm.
449 def ShiftedRegAsmOperand : AsmOperandClass { let Name = "RegShiftedReg"; }
450 def so_reg_reg : Operand<i32>, // reg reg imm
451 ComplexPattern<i32, 3, "SelectRegShifterOperand",
452 [shl, srl, sra, rotr]> {
453 let EncoderMethod = "getSORegRegOpValue";
454 let PrintMethod = "printSORegRegOperand";
455 let DecoderMethod = "DecodeSORegRegOperand";
456 let ParserMatchClass = ShiftedRegAsmOperand;
457 let MIOperandInfo = (ops GPRnopc, GPRnopc, i32imm);
460 def ShiftedImmAsmOperand : AsmOperandClass { let Name = "RegShiftedImm"; }
461 def so_reg_imm : Operand<i32>, // reg imm
462 ComplexPattern<i32, 2, "SelectImmShifterOperand",
463 [shl, srl, sra, rotr]> {
464 let EncoderMethod = "getSORegImmOpValue";
465 let PrintMethod = "printSORegImmOperand";
466 let DecoderMethod = "DecodeSORegImmOperand";
467 let ParserMatchClass = ShiftedImmAsmOperand;
468 let MIOperandInfo = (ops GPR, i32imm);
471 // FIXME: Does this need to be distinct from so_reg?
472 def shift_so_reg_reg : Operand<i32>, // reg reg imm
473 ComplexPattern<i32, 3, "SelectShiftRegShifterOperand",
474 [shl,srl,sra,rotr]> {
475 let EncoderMethod = "getSORegRegOpValue";
476 let PrintMethod = "printSORegRegOperand";
477 let DecoderMethod = "DecodeSORegRegOperand";
478 let MIOperandInfo = (ops GPR, GPR, i32imm);
481 // FIXME: Does this need to be distinct from so_reg?
482 def shift_so_reg_imm : Operand<i32>, // reg reg imm
483 ComplexPattern<i32, 2, "SelectShiftImmShifterOperand",
484 [shl,srl,sra,rotr]> {
485 let EncoderMethod = "getSORegImmOpValue";
486 let PrintMethod = "printSORegImmOperand";
487 let DecoderMethod = "DecodeSORegImmOperand";
488 let MIOperandInfo = (ops GPR, i32imm);
492 // so_imm - Match a 32-bit shifter_operand immediate operand, which is an
493 // 8-bit immediate rotated by an arbitrary number of bits.
494 def SOImmAsmOperand: ImmAsmOperand { let Name = "ARMSOImm"; }
495 def so_imm : Operand<i32>, ImmLeaf<i32, [{
496 return ARM_AM::getSOImmVal(Imm) != -1;
498 let EncoderMethod = "getSOImmOpValue";
499 let ParserMatchClass = SOImmAsmOperand;
500 let DecoderMethod = "DecodeSOImmOperand";
503 // Break so_imm's up into two pieces. This handles immediates with up to 16
504 // bits set in them. This uses so_imm2part to match and so_imm2part_[12] to
505 // get the first/second pieces.
506 def so_imm2part : PatLeaf<(imm), [{
507 return ARM_AM::isSOImmTwoPartVal((unsigned)N->getZExtValue());
510 /// arm_i32imm - True for +V6T2, or true only if so_imm2part is true.
512 def arm_i32imm : PatLeaf<(imm), [{
513 if (Subtarget->hasV6T2Ops())
515 return ARM_AM::isSOImmTwoPartVal((unsigned)N->getZExtValue());
518 /// imm0_7 predicate - Immediate in the range [0,7].
519 def Imm0_7AsmOperand: ImmAsmOperand { let Name = "Imm0_7"; }
520 def imm0_7 : Operand<i32>, ImmLeaf<i32, [{
521 return Imm >= 0 && Imm < 8;
523 let ParserMatchClass = Imm0_7AsmOperand;
526 /// imm0_15 predicate - Immediate in the range [0,15].
527 def Imm0_15AsmOperand: ImmAsmOperand { let Name = "Imm0_15"; }
528 def imm0_15 : Operand<i32>, ImmLeaf<i32, [{
529 return Imm >= 0 && Imm < 16;
531 let ParserMatchClass = Imm0_15AsmOperand;
534 /// imm0_31 predicate - True if the 32-bit immediate is in the range [0,31].
535 def Imm0_31AsmOperand: ImmAsmOperand { let Name = "Imm0_31"; }
536 def imm0_31 : Operand<i32>, ImmLeaf<i32, [{
537 return Imm >= 0 && Imm < 32;
539 let ParserMatchClass = Imm0_31AsmOperand;
542 /// imm0_32 predicate - True if the 32-bit immediate is in the range [0,32].
543 def Imm0_32AsmOperand: ImmAsmOperand { let Name = "Imm0_32"; }
544 def imm0_32 : Operand<i32>, ImmLeaf<i32, [{
545 return Imm >= 0 && Imm < 32;
547 let ParserMatchClass = Imm0_32AsmOperand;
550 /// imm0_255 predicate - Immediate in the range [0,255].
551 def Imm0_255AsmOperand : ImmAsmOperand { let Name = "Imm0_255"; }
552 def imm0_255 : Operand<i32>, ImmLeaf<i32, [{ return Imm >= 0 && Imm < 256; }]> {
553 let ParserMatchClass = Imm0_255AsmOperand;
556 /// imm0_65535 - An immediate is in the range [0.65535].
557 def Imm0_65535AsmOperand: ImmAsmOperand { let Name = "Imm0_65535"; }
558 def imm0_65535 : Operand<i32>, ImmLeaf<i32, [{
559 return Imm >= 0 && Imm < 65536;
561 let ParserMatchClass = Imm0_65535AsmOperand;
564 // imm0_65535_expr - For movt/movw - 16-bit immediate that can also reference
565 // a relocatable expression.
567 // FIXME: This really needs a Thumb version separate from the ARM version.
568 // While the range is the same, and can thus use the same match class,
569 // the encoding is different so it should have a different encoder method.
570 def Imm0_65535ExprAsmOperand: ImmAsmOperand { let Name = "Imm0_65535Expr"; }
571 def imm0_65535_expr : Operand<i32> {
572 let EncoderMethod = "getHiLo16ImmOpValue";
573 let ParserMatchClass = Imm0_65535ExprAsmOperand;
576 /// imm24b - True if the 32-bit immediate is encodable in 24 bits.
577 def Imm24bitAsmOperand: ImmAsmOperand { let Name = "Imm24bit"; }
578 def imm24b : Operand<i32>, ImmLeaf<i32, [{
579 return Imm >= 0 && Imm <= 0xffffff;
581 let ParserMatchClass = Imm24bitAsmOperand;
585 /// bf_inv_mask_imm predicate - An AND mask to clear an arbitrary width bitfield
587 def BitfieldAsmOperand : AsmOperandClass {
588 let Name = "Bitfield";
589 let ParserMethod = "parseBitfield";
591 def bf_inv_mask_imm : Operand<i32>,
593 return ARM::isBitFieldInvertedMask(N->getZExtValue());
595 let EncoderMethod = "getBitfieldInvertedMaskOpValue";
596 let PrintMethod = "printBitfieldInvMaskImmOperand";
597 let DecoderMethod = "DecodeBitfieldMaskOperand";
598 let ParserMatchClass = BitfieldAsmOperand;
601 def imm1_32_XFORM: SDNodeXForm<imm, [{
602 return CurDAG->getTargetConstant((int)N->getZExtValue() - 1, MVT::i32);
604 def Imm1_32AsmOperand: AsmOperandClass { let Name = "Imm1_32"; }
605 def imm1_32 : Operand<i32>, PatLeaf<(imm), [{
606 uint64_t Imm = N->getZExtValue();
607 return Imm > 0 && Imm <= 32;
610 let PrintMethod = "printImmPlusOneOperand";
611 let ParserMatchClass = Imm1_32AsmOperand;
614 def imm1_16_XFORM: SDNodeXForm<imm, [{
615 return CurDAG->getTargetConstant((int)N->getZExtValue() - 1, MVT::i32);
617 def Imm1_16AsmOperand: AsmOperandClass { let Name = "Imm1_16"; }
618 def imm1_16 : Operand<i32>, PatLeaf<(imm), [{ return Imm > 0 && Imm <= 16; }],
620 let PrintMethod = "printImmPlusOneOperand";
621 let ParserMatchClass = Imm1_16AsmOperand;
624 // Define ARM specific addressing modes.
625 // addrmode_imm12 := reg +/- imm12
627 def MemImm12OffsetAsmOperand : AsmOperandClass { let Name = "MemImm12Offset"; }
628 def addrmode_imm12 : Operand<i32>,
629 ComplexPattern<i32, 2, "SelectAddrModeImm12", []> {
630 // 12-bit immediate operand. Note that instructions using this encode
631 // #0 and #-0 differently. We flag #-0 as the magic value INT32_MIN. All other
632 // immediate values are as normal.
634 let EncoderMethod = "getAddrModeImm12OpValue";
635 let PrintMethod = "printAddrModeImm12Operand";
636 let DecoderMethod = "DecodeAddrModeImm12Operand";
637 let ParserMatchClass = MemImm12OffsetAsmOperand;
638 let MIOperandInfo = (ops GPR:$base, i32imm:$offsimm);
640 // ldst_so_reg := reg +/- reg shop imm
642 def MemRegOffsetAsmOperand : AsmOperandClass { let Name = "MemRegOffset"; }
643 def ldst_so_reg : Operand<i32>,
644 ComplexPattern<i32, 3, "SelectLdStSOReg", []> {
645 let EncoderMethod = "getLdStSORegOpValue";
646 // FIXME: Simplify the printer
647 let PrintMethod = "printAddrMode2Operand";
648 let DecoderMethod = "DecodeSORegMemOperand";
649 let ParserMatchClass = MemRegOffsetAsmOperand;
650 let MIOperandInfo = (ops GPR:$base, GPRnopc:$offsreg, i32imm:$shift);
653 // postidx_imm8 := +/- [0,255]
656 // {8} 1 is imm8 is non-negative. 0 otherwise.
657 // {7-0} [0,255] imm8 value.
658 def PostIdxImm8AsmOperand : AsmOperandClass { let Name = "PostIdxImm8"; }
659 def postidx_imm8 : Operand<i32> {
660 let PrintMethod = "printPostIdxImm8Operand";
661 let ParserMatchClass = PostIdxImm8AsmOperand;
662 let MIOperandInfo = (ops i32imm);
665 // postidx_imm8s4 := +/- [0,1020]
668 // {8} 1 is imm8 is non-negative. 0 otherwise.
669 // {7-0} [0,255] imm8 value, scaled by 4.
670 def PostIdxImm8s4AsmOperand : AsmOperandClass { let Name = "PostIdxImm8s4"; }
671 def postidx_imm8s4 : Operand<i32> {
672 let PrintMethod = "printPostIdxImm8s4Operand";
673 let ParserMatchClass = PostIdxImm8s4AsmOperand;
674 let MIOperandInfo = (ops i32imm);
678 // postidx_reg := +/- reg
680 def PostIdxRegAsmOperand : AsmOperandClass {
681 let Name = "PostIdxReg";
682 let ParserMethod = "parsePostIdxReg";
684 def postidx_reg : Operand<i32> {
685 let EncoderMethod = "getPostIdxRegOpValue";
686 let DecoderMethod = "DecodePostIdxReg";
687 let PrintMethod = "printPostIdxRegOperand";
688 let ParserMatchClass = PostIdxRegAsmOperand;
689 let MIOperandInfo = (ops GPR, i32imm);
693 // addrmode2 := reg +/- imm12
694 // := reg +/- reg shop imm
696 // FIXME: addrmode2 should be refactored the rest of the way to always
697 // use explicit imm vs. reg versions above (addrmode_imm12 and ldst_so_reg).
698 def AddrMode2AsmOperand : AsmOperandClass { let Name = "AddrMode2"; }
699 def addrmode2 : Operand<i32>,
700 ComplexPattern<i32, 3, "SelectAddrMode2", []> {
701 let EncoderMethod = "getAddrMode2OpValue";
702 let PrintMethod = "printAddrMode2Operand";
703 let ParserMatchClass = AddrMode2AsmOperand;
704 let MIOperandInfo = (ops GPR:$base, GPR:$offsreg, i32imm:$offsimm);
707 def PostIdxRegShiftedAsmOperand : AsmOperandClass {
708 let Name = "PostIdxRegShifted";
709 let ParserMethod = "parsePostIdxReg";
711 def am2offset_reg : Operand<i32>,
712 ComplexPattern<i32, 2, "SelectAddrMode2OffsetReg",
713 [], [SDNPWantRoot]> {
714 let EncoderMethod = "getAddrMode2OffsetOpValue";
715 let PrintMethod = "printAddrMode2OffsetOperand";
716 // When using this for assembly, it's always as a post-index offset.
717 let ParserMatchClass = PostIdxRegShiftedAsmOperand;
718 let MIOperandInfo = (ops GPR, i32imm);
721 // FIXME: am2offset_imm should only need the immediate, not the GPR. Having
722 // the GPR is purely vestigal at this point.
723 def AM2OffsetImmAsmOperand : AsmOperandClass { let Name = "AM2OffsetImm"; }
724 def am2offset_imm : Operand<i32>,
725 ComplexPattern<i32, 2, "SelectAddrMode2OffsetImm",
726 [], [SDNPWantRoot]> {
727 let EncoderMethod = "getAddrMode2OffsetOpValue";
728 let PrintMethod = "printAddrMode2OffsetOperand";
729 let ParserMatchClass = AM2OffsetImmAsmOperand;
730 let MIOperandInfo = (ops GPR, i32imm);
734 // addrmode3 := reg +/- reg
735 // addrmode3 := reg +/- imm8
737 // FIXME: split into imm vs. reg versions.
738 def AddrMode3AsmOperand : AsmOperandClass { let Name = "AddrMode3"; }
739 def addrmode3 : Operand<i32>,
740 ComplexPattern<i32, 3, "SelectAddrMode3", []> {
741 let EncoderMethod = "getAddrMode3OpValue";
742 let PrintMethod = "printAddrMode3Operand";
743 let ParserMatchClass = AddrMode3AsmOperand;
744 let MIOperandInfo = (ops GPR:$base, GPR:$offsreg, i32imm:$offsimm);
747 // FIXME: split into imm vs. reg versions.
748 // FIXME: parser method to handle +/- register.
749 def AM3OffsetAsmOperand : AsmOperandClass {
750 let Name = "AM3Offset";
751 let ParserMethod = "parseAM3Offset";
753 def am3offset : Operand<i32>,
754 ComplexPattern<i32, 2, "SelectAddrMode3Offset",
755 [], [SDNPWantRoot]> {
756 let EncoderMethod = "getAddrMode3OffsetOpValue";
757 let PrintMethod = "printAddrMode3OffsetOperand";
758 let ParserMatchClass = AM3OffsetAsmOperand;
759 let MIOperandInfo = (ops GPR, i32imm);
762 // ldstm_mode := {ia, ib, da, db}
764 def ldstm_mode : OptionalDefOperand<OtherVT, (ops i32), (ops (i32 1))> {
765 let EncoderMethod = "getLdStmModeOpValue";
766 let PrintMethod = "printLdStmModeOperand";
769 // addrmode5 := reg +/- imm8*4
771 def AddrMode5AsmOperand : AsmOperandClass { let Name = "AddrMode5"; }
772 def addrmode5 : Operand<i32>,
773 ComplexPattern<i32, 2, "SelectAddrMode5", []> {
774 let PrintMethod = "printAddrMode5Operand";
775 let EncoderMethod = "getAddrMode5OpValue";
776 let DecoderMethod = "DecodeAddrMode5Operand";
777 let ParserMatchClass = AddrMode5AsmOperand;
778 let MIOperandInfo = (ops GPR:$base, i32imm);
781 // addrmode6 := reg with optional alignment
783 def AddrMode6AsmOperand : AsmOperandClass { let Name = "AlignedMemory"; }
784 def addrmode6 : Operand<i32>,
785 ComplexPattern<i32, 2, "SelectAddrMode6", [], [SDNPWantParent]>{
786 let PrintMethod = "printAddrMode6Operand";
787 let MIOperandInfo = (ops GPR:$addr, i32imm:$align);
788 let EncoderMethod = "getAddrMode6AddressOpValue";
789 let DecoderMethod = "DecodeAddrMode6Operand";
790 let ParserMatchClass = AddrMode6AsmOperand;
793 def am6offset : Operand<i32>,
794 ComplexPattern<i32, 1, "SelectAddrMode6Offset",
795 [], [SDNPWantRoot]> {
796 let PrintMethod = "printAddrMode6OffsetOperand";
797 let MIOperandInfo = (ops GPR);
798 let EncoderMethod = "getAddrMode6OffsetOpValue";
799 let DecoderMethod = "DecodeGPRRegisterClass";
802 // Special version of addrmode6 to handle alignment encoding for VST1/VLD1
803 // (single element from one lane) for size 32.
804 def addrmode6oneL32 : Operand<i32>,
805 ComplexPattern<i32, 2, "SelectAddrMode6", [], [SDNPWantParent]>{
806 let PrintMethod = "printAddrMode6Operand";
807 let MIOperandInfo = (ops GPR:$addr, i32imm);
808 let EncoderMethod = "getAddrMode6OneLane32AddressOpValue";
811 // Special version of addrmode6 to handle alignment encoding for VLD-dup
812 // instructions, specifically VLD4-dup.
813 def addrmode6dup : Operand<i32>,
814 ComplexPattern<i32, 2, "SelectAddrMode6", [], [SDNPWantParent]>{
815 let PrintMethod = "printAddrMode6Operand";
816 let MIOperandInfo = (ops GPR:$addr, i32imm);
817 let EncoderMethod = "getAddrMode6DupAddressOpValue";
820 // addrmodepc := pc + reg
822 def addrmodepc : Operand<i32>,
823 ComplexPattern<i32, 2, "SelectAddrModePC", []> {
824 let PrintMethod = "printAddrModePCOperand";
825 let MIOperandInfo = (ops GPR, i32imm);
828 // addr_offset_none := reg
830 def MemNoOffsetAsmOperand : AsmOperandClass { let Name = "MemNoOffset"; }
831 def addr_offset_none : Operand<i32>,
832 ComplexPattern<i32, 1, "SelectAddrOffsetNone", []> {
833 let PrintMethod = "printAddrMode7Operand";
834 let DecoderMethod = "DecodeAddrMode7Operand";
835 let ParserMatchClass = MemNoOffsetAsmOperand;
836 let MIOperandInfo = (ops GPR:$base);
839 def nohash_imm : Operand<i32> {
840 let PrintMethod = "printNoHashImmediate";
843 def CoprocNumAsmOperand : AsmOperandClass {
844 let Name = "CoprocNum";
845 let ParserMethod = "parseCoprocNumOperand";
847 def p_imm : Operand<i32> {
848 let PrintMethod = "printPImmediate";
849 let ParserMatchClass = CoprocNumAsmOperand;
850 let DecoderMethod = "DecodeCoprocessor";
853 def CoprocRegAsmOperand : AsmOperandClass {
854 let Name = "CoprocReg";
855 let ParserMethod = "parseCoprocRegOperand";
857 def c_imm : Operand<i32> {
858 let PrintMethod = "printCImmediate";
859 let ParserMatchClass = CoprocRegAsmOperand;
861 def CoprocOptionAsmOperand : AsmOperandClass {
862 let Name = "CoprocOption";
863 let ParserMethod = "parseCoprocOptionOperand";
865 def coproc_option_imm : Operand<i32> {
866 let PrintMethod = "printCoprocOptionImm";
867 let ParserMatchClass = CoprocOptionAsmOperand;
870 //===----------------------------------------------------------------------===//
872 include "ARMInstrFormats.td"
874 //===----------------------------------------------------------------------===//
875 // Multiclass helpers...
878 /// AsI1_bin_irs - Defines a set of (op r, {so_imm|r|so_reg}) patterns for a
879 /// binop that produces a value.
880 multiclass AsI1_bin_irs<bits<4> opcod, string opc,
881 InstrItinClass iii, InstrItinClass iir, InstrItinClass iis,
882 PatFrag opnode, string baseOpc, bit Commutable = 0> {
883 // The register-immediate version is re-materializable. This is useful
884 // in particular for taking the address of a local.
885 let isReMaterializable = 1 in {
886 def ri : AsI1<opcod, (outs GPR:$Rd), (ins GPR:$Rn, so_imm:$imm), DPFrm,
887 iii, opc, "\t$Rd, $Rn, $imm",
888 [(set GPR:$Rd, (opnode GPR:$Rn, so_imm:$imm))]> {
893 let Inst{19-16} = Rn;
894 let Inst{15-12} = Rd;
895 let Inst{11-0} = imm;
898 def rr : AsI1<opcod, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm), DPFrm,
899 iir, opc, "\t$Rd, $Rn, $Rm",
900 [(set GPR:$Rd, (opnode GPR:$Rn, GPR:$Rm))]> {
905 let isCommutable = Commutable;
906 let Inst{19-16} = Rn;
907 let Inst{15-12} = Rd;
908 let Inst{11-4} = 0b00000000;
912 def rsi : AsI1<opcod, (outs GPR:$Rd),
913 (ins GPR:$Rn, so_reg_imm:$shift), DPSoRegImmFrm,
914 iis, opc, "\t$Rd, $Rn, $shift",
915 [(set GPR:$Rd, (opnode GPR:$Rn, so_reg_imm:$shift))]> {
920 let Inst{19-16} = Rn;
921 let Inst{15-12} = Rd;
922 let Inst{11-5} = shift{11-5};
924 let Inst{3-0} = shift{3-0};
927 def rsr : AsI1<opcod, (outs GPR:$Rd),
928 (ins GPR:$Rn, so_reg_reg:$shift), DPSoRegRegFrm,
929 iis, opc, "\t$Rd, $Rn, $shift",
930 [(set GPR:$Rd, (opnode GPR:$Rn, so_reg_reg:$shift))]> {
935 let Inst{19-16} = Rn;
936 let Inst{15-12} = Rd;
937 let Inst{11-8} = shift{11-8};
939 let Inst{6-5} = shift{6-5};
941 let Inst{3-0} = shift{3-0};
944 // Assembly aliases for optional destination operand when it's the same
945 // as the source operand.
946 def : InstAlias<!strconcat(opc, "${s}${p} $Rdn, $imm"),
947 (!cast<Instruction>(!strconcat(baseOpc, "ri")) GPR:$Rdn, GPR:$Rdn,
948 so_imm:$imm, pred:$p,
951 def : InstAlias<!strconcat(opc, "${s}${p} $Rdn, $Rm"),
952 (!cast<Instruction>(!strconcat(baseOpc, "rr")) GPR:$Rdn, GPR:$Rdn,
956 def : InstAlias<!strconcat(opc, "${s}${p} $Rdn, $shift"),
957 (!cast<Instruction>(!strconcat(baseOpc, "rsi")) GPR:$Rdn, GPR:$Rdn,
958 so_reg_imm:$shift, pred:$p,
961 def : InstAlias<!strconcat(opc, "${s}${p} $Rdn, $shift"),
962 (!cast<Instruction>(!strconcat(baseOpc, "rsr")) GPR:$Rdn, GPR:$Rdn,
963 so_reg_reg:$shift, pred:$p,
969 /// AsI1_rbin_irs - Same as AsI1_bin_irs except the order of operands are
970 /// reversed. The 'rr' form is only defined for the disassembler; for codegen
971 /// it is equivalent to the AsI1_bin_irs counterpart.
972 multiclass AsI1_rbin_irs<bits<4> opcod, string opc,
973 InstrItinClass iii, InstrItinClass iir, InstrItinClass iis,
974 PatFrag opnode, string baseOpc, bit Commutable = 0> {
975 // The register-immediate version is re-materializable. This is useful
976 // in particular for taking the address of a local.
977 let isReMaterializable = 1 in {
978 def ri : AsI1<opcod, (outs GPR:$Rd), (ins GPR:$Rn, so_imm:$imm), DPFrm,
979 iii, opc, "\t$Rd, $Rn, $imm",
980 [(set GPR:$Rd, (opnode so_imm:$imm, GPR:$Rn))]> {
985 let Inst{19-16} = Rn;
986 let Inst{15-12} = Rd;
987 let Inst{11-0} = imm;
990 def rr : AsI1<opcod, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm), DPFrm,
991 iir, opc, "\t$Rd, $Rn, $Rm",
992 [/* pattern left blank */]> {
996 let Inst{11-4} = 0b00000000;
999 let Inst{15-12} = Rd;
1000 let Inst{19-16} = Rn;
1003 def rsi : AsI1<opcod, (outs GPR:$Rd),
1004 (ins GPR:$Rn, so_reg_imm:$shift), DPSoRegImmFrm,
1005 iis, opc, "\t$Rd, $Rn, $shift",
1006 [(set GPR:$Rd, (opnode so_reg_imm:$shift, GPR:$Rn))]> {
1011 let Inst{19-16} = Rn;
1012 let Inst{15-12} = Rd;
1013 let Inst{11-5} = shift{11-5};
1015 let Inst{3-0} = shift{3-0};
1018 def rsr : AsI1<opcod, (outs GPR:$Rd),
1019 (ins GPR:$Rn, so_reg_reg:$shift), DPSoRegRegFrm,
1020 iis, opc, "\t$Rd, $Rn, $shift",
1021 [(set GPR:$Rd, (opnode so_reg_reg:$shift, GPR:$Rn))]> {
1026 let Inst{19-16} = Rn;
1027 let Inst{15-12} = Rd;
1028 let Inst{11-8} = shift{11-8};
1030 let Inst{6-5} = shift{6-5};
1032 let Inst{3-0} = shift{3-0};
1035 // Assembly aliases for optional destination operand when it's the same
1036 // as the source operand.
1037 def : InstAlias<!strconcat(opc, "${s}${p} $Rdn, $imm"),
1038 (!cast<Instruction>(!strconcat(baseOpc, "ri")) GPR:$Rdn, GPR:$Rdn,
1039 so_imm:$imm, pred:$p,
1042 def : InstAlias<!strconcat(opc, "${s}${p} $Rdn, $Rm"),
1043 (!cast<Instruction>(!strconcat(baseOpc, "rr")) GPR:$Rdn, GPR:$Rdn,
1047 def : InstAlias<!strconcat(opc, "${s}${p} $Rdn, $shift"),
1048 (!cast<Instruction>(!strconcat(baseOpc, "rsi")) GPR:$Rdn, GPR:$Rdn,
1049 so_reg_imm:$shift, pred:$p,
1052 def : InstAlias<!strconcat(opc, "${s}${p} $Rdn, $shift"),
1053 (!cast<Instruction>(!strconcat(baseOpc, "rsr")) GPR:$Rdn, GPR:$Rdn,
1054 so_reg_reg:$shift, pred:$p,
1060 /// AsI1_bin_s_irs - Same as AsI1_bin_irs except it sets the 's' bit by default.
1062 /// These opcodes will be converted to the real non-S opcodes by
1063 /// AdjustInstrPostInstrSelection after giving them an optional CPSR operand.
1064 let hasPostISelHook = 1, Defs = [CPSR] in {
1065 multiclass AsI1_bin_s_irs<InstrItinClass iii, InstrItinClass iir,
1066 InstrItinClass iis, PatFrag opnode,
1067 bit Commutable = 0> {
1068 def ri : ARMPseudoInst<(outs GPR:$Rd), (ins GPR:$Rn, so_imm:$imm, pred:$p),
1070 [(set GPR:$Rd, CPSR, (opnode GPR:$Rn, so_imm:$imm))]>;
1072 def rr : ARMPseudoInst<(outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm, pred:$p),
1074 [(set GPR:$Rd, CPSR, (opnode GPR:$Rn, GPR:$Rm))]> {
1075 let isCommutable = Commutable;
1077 def rsi : ARMPseudoInst<(outs GPR:$Rd),
1078 (ins GPR:$Rn, so_reg_imm:$shift, pred:$p),
1080 [(set GPR:$Rd, CPSR, (opnode GPR:$Rn,
1081 so_reg_imm:$shift))]>;
1083 def rsr : ARMPseudoInst<(outs GPR:$Rd),
1084 (ins GPR:$Rn, so_reg_reg:$shift, pred:$p),
1086 [(set GPR:$Rd, CPSR, (opnode GPR:$Rn,
1087 so_reg_reg:$shift))]>;
1091 /// AsI1_rbin_s_is - Same as AsI1_bin_s_irs, except selection DAG
1092 /// operands are reversed.
1093 let hasPostISelHook = 1, Defs = [CPSR] in {
1094 multiclass AsI1_rbin_s_is<InstrItinClass iii, InstrItinClass iir,
1095 InstrItinClass iis, PatFrag opnode,
1096 bit Commutable = 0> {
1097 def ri : ARMPseudoInst<(outs GPR:$Rd), (ins GPR:$Rn, so_imm:$imm, pred:$p),
1099 [(set GPR:$Rd, CPSR, (opnode so_imm:$imm, GPR:$Rn))]>;
1101 def rsi : ARMPseudoInst<(outs GPR:$Rd),
1102 (ins GPR:$Rn, so_reg_imm:$shift, pred:$p),
1104 [(set GPR:$Rd, CPSR, (opnode so_reg_imm:$shift,
1107 def rsr : ARMPseudoInst<(outs GPR:$Rd),
1108 (ins GPR:$Rn, so_reg_reg:$shift, pred:$p),
1110 [(set GPR:$Rd, CPSR, (opnode so_reg_reg:$shift,
1115 /// AI1_cmp_irs - Defines a set of (op r, {so_imm|r|so_reg}) cmp / test
1116 /// patterns. Similar to AsI1_bin_irs except the instruction does not produce
1117 /// a explicit result, only implicitly set CPSR.
1118 let isCompare = 1, Defs = [CPSR] in {
1119 multiclass AI1_cmp_irs<bits<4> opcod, string opc,
1120 InstrItinClass iii, InstrItinClass iir, InstrItinClass iis,
1121 PatFrag opnode, bit Commutable = 0> {
1122 def ri : AI1<opcod, (outs), (ins GPR:$Rn, so_imm:$imm), DPFrm, iii,
1124 [(opnode GPR:$Rn, so_imm:$imm)]> {
1129 let Inst{19-16} = Rn;
1130 let Inst{15-12} = 0b0000;
1131 let Inst{11-0} = imm;
1133 def rr : AI1<opcod, (outs), (ins GPR:$Rn, GPR:$Rm), DPFrm, iir,
1135 [(opnode GPR:$Rn, GPR:$Rm)]> {
1138 let isCommutable = Commutable;
1141 let Inst{19-16} = Rn;
1142 let Inst{15-12} = 0b0000;
1143 let Inst{11-4} = 0b00000000;
1146 def rsi : AI1<opcod, (outs),
1147 (ins GPR:$Rn, so_reg_imm:$shift), DPSoRegImmFrm, iis,
1148 opc, "\t$Rn, $shift",
1149 [(opnode GPR:$Rn, so_reg_imm:$shift)]> {
1154 let Inst{19-16} = Rn;
1155 let Inst{15-12} = 0b0000;
1156 let Inst{11-5} = shift{11-5};
1158 let Inst{3-0} = shift{3-0};
1160 def rsr : AI1<opcod, (outs),
1161 (ins GPR:$Rn, so_reg_reg:$shift), DPSoRegRegFrm, iis,
1162 opc, "\t$Rn, $shift",
1163 [(opnode GPR:$Rn, so_reg_reg:$shift)]> {
1168 let Inst{19-16} = Rn;
1169 let Inst{15-12} = 0b0000;
1170 let Inst{11-8} = shift{11-8};
1172 let Inst{6-5} = shift{6-5};
1174 let Inst{3-0} = shift{3-0};
1180 /// AI_ext_rrot - A unary operation with two forms: one whose operand is a
1181 /// register and one whose operand is a register rotated by 8/16/24.
1182 /// FIXME: Remove the 'r' variant. Its rot_imm is zero.
1183 class AI_ext_rrot<bits<8> opcod, string opc, PatFrag opnode>
1184 : AExtI<opcod, (outs GPRnopc:$Rd), (ins GPRnopc:$Rm, rot_imm:$rot),
1185 IIC_iEXTr, opc, "\t$Rd, $Rm$rot",
1186 [(set GPRnopc:$Rd, (opnode (rotr GPRnopc:$Rm, rot_imm:$rot)))]>,
1187 Requires<[IsARM, HasV6]> {
1191 let Inst{19-16} = 0b1111;
1192 let Inst{15-12} = Rd;
1193 let Inst{11-10} = rot;
1197 class AI_ext_rrot_np<bits<8> opcod, string opc>
1198 : AExtI<opcod, (outs GPRnopc:$Rd), (ins GPRnopc:$Rm, rot_imm:$rot),
1199 IIC_iEXTr, opc, "\t$Rd, $Rm$rot", []>,
1200 Requires<[IsARM, HasV6]> {
1202 let Inst{19-16} = 0b1111;
1203 let Inst{11-10} = rot;
1206 /// AI_exta_rrot - A binary operation with two forms: one whose operand is a
1207 /// register and one whose operand is a register rotated by 8/16/24.
1208 class AI_exta_rrot<bits<8> opcod, string opc, PatFrag opnode>
1209 : AExtI<opcod, (outs GPRnopc:$Rd), (ins GPR:$Rn, GPRnopc:$Rm, rot_imm:$rot),
1210 IIC_iEXTAr, opc, "\t$Rd, $Rn, $Rm$rot",
1211 [(set GPRnopc:$Rd, (opnode GPR:$Rn,
1212 (rotr GPRnopc:$Rm, rot_imm:$rot)))]>,
1213 Requires<[IsARM, HasV6]> {
1218 let Inst{19-16} = Rn;
1219 let Inst{15-12} = Rd;
1220 let Inst{11-10} = rot;
1221 let Inst{9-4} = 0b000111;
1225 class AI_exta_rrot_np<bits<8> opcod, string opc>
1226 : AExtI<opcod, (outs GPRnopc:$Rd), (ins GPR:$Rn, GPRnopc:$Rm, rot_imm:$rot),
1227 IIC_iEXTAr, opc, "\t$Rd, $Rn, $Rm$rot", []>,
1228 Requires<[IsARM, HasV6]> {
1231 let Inst{19-16} = Rn;
1232 let Inst{11-10} = rot;
1235 /// AI1_adde_sube_irs - Define instructions and patterns for adde and sube.
1236 multiclass AI1_adde_sube_irs<bits<4> opcod, string opc, PatFrag opnode,
1237 string baseOpc, bit Commutable = 0> {
1238 let hasPostISelHook = 1, Defs = [CPSR], Uses = [CPSR] in {
1239 def ri : AsI1<opcod, (outs GPR:$Rd), (ins GPR:$Rn, so_imm:$imm),
1240 DPFrm, IIC_iALUi, opc, "\t$Rd, $Rn, $imm",
1241 [(set GPR:$Rd, CPSR, (opnode GPR:$Rn, so_imm:$imm, CPSR))]>,
1247 let Inst{15-12} = Rd;
1248 let Inst{19-16} = Rn;
1249 let Inst{11-0} = imm;
1251 def rr : AsI1<opcod, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm),
1252 DPFrm, IIC_iALUr, opc, "\t$Rd, $Rn, $Rm",
1253 [(set GPR:$Rd, CPSR, (opnode GPR:$Rn, GPR:$Rm, CPSR))]>,
1258 let Inst{11-4} = 0b00000000;
1260 let isCommutable = Commutable;
1262 let Inst{15-12} = Rd;
1263 let Inst{19-16} = Rn;
1265 def rsi : AsI1<opcod, (outs GPR:$Rd),
1266 (ins GPR:$Rn, so_reg_imm:$shift),
1267 DPSoRegImmFrm, IIC_iALUsr, opc, "\t$Rd, $Rn, $shift",
1268 [(set GPR:$Rd, CPSR, (opnode GPR:$Rn, so_reg_imm:$shift, CPSR))]>,
1274 let Inst{19-16} = Rn;
1275 let Inst{15-12} = Rd;
1276 let Inst{11-5} = shift{11-5};
1278 let Inst{3-0} = shift{3-0};
1280 def rsr : AsI1<opcod, (outs GPR:$Rd),
1281 (ins GPR:$Rn, so_reg_reg:$shift),
1282 DPSoRegRegFrm, IIC_iALUsr, opc, "\t$Rd, $Rn, $shift",
1283 [(set GPR:$Rd, CPSR, (opnode GPR:$Rn, so_reg_reg:$shift, CPSR))]>,
1289 let Inst{19-16} = Rn;
1290 let Inst{15-12} = Rd;
1291 let Inst{11-8} = shift{11-8};
1293 let Inst{6-5} = shift{6-5};
1295 let Inst{3-0} = shift{3-0};
1299 // Assembly aliases for optional destination operand when it's the same
1300 // as the source operand.
1301 def : InstAlias<!strconcat(opc, "${s}${p} $Rdn, $imm"),
1302 (!cast<Instruction>(!strconcat(baseOpc, "ri")) GPR:$Rdn, GPR:$Rdn,
1303 so_imm:$imm, pred:$p,
1306 def : InstAlias<!strconcat(opc, "${s}${p} $Rdn, $Rm"),
1307 (!cast<Instruction>(!strconcat(baseOpc, "rr")) GPR:$Rdn, GPR:$Rdn,
1311 def : InstAlias<!strconcat(opc, "${s}${p} $Rdn, $shift"),
1312 (!cast<Instruction>(!strconcat(baseOpc, "rsi")) GPR:$Rdn, GPR:$Rdn,
1313 so_reg_imm:$shift, pred:$p,
1316 def : InstAlias<!strconcat(opc, "${s}${p} $Rdn, $shift"),
1317 (!cast<Instruction>(!strconcat(baseOpc, "rsr")) GPR:$Rdn, GPR:$Rdn,
1318 so_reg_reg:$shift, pred:$p,
1323 /// AI1_rsc_irs - Define instructions and patterns for rsc
1324 multiclass AI1_rsc_irs<bits<4> opcod, string opc, PatFrag opnode,
1326 let hasPostISelHook = 1, Defs = [CPSR], Uses = [CPSR] in {
1327 def ri : AsI1<opcod, (outs GPR:$Rd), (ins GPR:$Rn, so_imm:$imm),
1328 DPFrm, IIC_iALUi, opc, "\t$Rd, $Rn, $imm",
1329 [(set GPR:$Rd, CPSR, (opnode so_imm:$imm, GPR:$Rn, CPSR))]>,
1335 let Inst{15-12} = Rd;
1336 let Inst{19-16} = Rn;
1337 let Inst{11-0} = imm;
1339 def rr : AsI1<opcod, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm),
1340 DPFrm, IIC_iALUr, opc, "\t$Rd, $Rn, $Rm",
1341 [/* pattern left blank */]> {
1345 let Inst{11-4} = 0b00000000;
1348 let Inst{15-12} = Rd;
1349 let Inst{19-16} = Rn;
1351 def rsi : AsI1<opcod, (outs GPR:$Rd), (ins GPR:$Rn, so_reg_imm:$shift),
1352 DPSoRegImmFrm, IIC_iALUsr, opc, "\t$Rd, $Rn, $shift",
1353 [(set GPR:$Rd, CPSR, (opnode so_reg_imm:$shift, GPR:$Rn, CPSR))]>,
1359 let Inst{19-16} = Rn;
1360 let Inst{15-12} = Rd;
1361 let Inst{11-5} = shift{11-5};
1363 let Inst{3-0} = shift{3-0};
1365 def rsr : AsI1<opcod, (outs GPR:$Rd), (ins GPR:$Rn, so_reg_reg:$shift),
1366 DPSoRegRegFrm, IIC_iALUsr, opc, "\t$Rd, $Rn, $shift",
1367 [(set GPR:$Rd, CPSR, (opnode so_reg_reg:$shift, GPR:$Rn, CPSR))]>,
1373 let Inst{19-16} = Rn;
1374 let Inst{15-12} = Rd;
1375 let Inst{11-8} = shift{11-8};
1377 let Inst{6-5} = shift{6-5};
1379 let Inst{3-0} = shift{3-0};
1383 // Assembly aliases for optional destination operand when it's the same
1384 // as the source operand.
1385 def : InstAlias<!strconcat(opc, "${s}${p} $Rdn, $imm"),
1386 (!cast<Instruction>(!strconcat(baseOpc, "ri")) GPR:$Rdn, GPR:$Rdn,
1387 so_imm:$imm, pred:$p,
1390 def : InstAlias<!strconcat(opc, "${s}${p} $Rdn, $Rm"),
1391 (!cast<Instruction>(!strconcat(baseOpc, "rr")) GPR:$Rdn, GPR:$Rdn,
1395 def : InstAlias<!strconcat(opc, "${s}${p} $Rdn, $shift"),
1396 (!cast<Instruction>(!strconcat(baseOpc, "rsi")) GPR:$Rdn, GPR:$Rdn,
1397 so_reg_imm:$shift, pred:$p,
1400 def : InstAlias<!strconcat(opc, "${s}${p} $Rdn, $shift"),
1401 (!cast<Instruction>(!strconcat(baseOpc, "rsr")) GPR:$Rdn, GPR:$Rdn,
1402 so_reg_reg:$shift, pred:$p,
1407 let canFoldAsLoad = 1, isReMaterializable = 1 in {
1408 multiclass AI_ldr1<bit isByte, string opc, InstrItinClass iii,
1409 InstrItinClass iir, PatFrag opnode> {
1410 // Note: We use the complex addrmode_imm12 rather than just an input
1411 // GPR and a constrained immediate so that we can use this to match
1412 // frame index references and avoid matching constant pool references.
1413 def i12: AI2ldst<0b010, 1, isByte, (outs GPR:$Rt), (ins addrmode_imm12:$addr),
1414 AddrMode_i12, LdFrm, iii, opc, "\t$Rt, $addr",
1415 [(set GPR:$Rt, (opnode addrmode_imm12:$addr))]> {
1418 let Inst{23} = addr{12}; // U (add = ('U' == 1))
1419 let Inst{19-16} = addr{16-13}; // Rn
1420 let Inst{15-12} = Rt;
1421 let Inst{11-0} = addr{11-0}; // imm12
1423 def rs : AI2ldst<0b011, 1, isByte, (outs GPR:$Rt), (ins ldst_so_reg:$shift),
1424 AddrModeNone, LdFrm, iir, opc, "\t$Rt, $shift",
1425 [(set GPR:$Rt, (opnode ldst_so_reg:$shift))]> {
1428 let shift{4} = 0; // Inst{4} = 0
1429 let Inst{23} = shift{12}; // U (add = ('U' == 1))
1430 let Inst{19-16} = shift{16-13}; // Rn
1431 let Inst{15-12} = Rt;
1432 let Inst{11-0} = shift{11-0};
1437 let canFoldAsLoad = 1, isReMaterializable = 1 in {
1438 multiclass AI_ldr1nopc<bit isByte, string opc, InstrItinClass iii,
1439 InstrItinClass iir, PatFrag opnode> {
1440 // Note: We use the complex addrmode_imm12 rather than just an input
1441 // GPR and a constrained immediate so that we can use this to match
1442 // frame index references and avoid matching constant pool references.
1443 def i12: AI2ldst<0b010, 1, isByte, (outs GPRnopc:$Rt), (ins addrmode_imm12:$addr),
1444 AddrMode_i12, LdFrm, iii, opc, "\t$Rt, $addr",
1445 [(set GPRnopc:$Rt, (opnode addrmode_imm12:$addr))]> {
1448 let Inst{23} = addr{12}; // U (add = ('U' == 1))
1449 let Inst{19-16} = addr{16-13}; // Rn
1450 let Inst{15-12} = Rt;
1451 let Inst{11-0} = addr{11-0}; // imm12
1453 def rs : AI2ldst<0b011, 1, isByte, (outs GPRnopc:$Rt), (ins ldst_so_reg:$shift),
1454 AddrModeNone, LdFrm, iir, opc, "\t$Rt, $shift",
1455 [(set GPRnopc:$Rt, (opnode ldst_so_reg:$shift))]> {
1458 let shift{4} = 0; // Inst{4} = 0
1459 let Inst{23} = shift{12}; // U (add = ('U' == 1))
1460 let Inst{19-16} = shift{16-13}; // Rn
1461 let Inst{15-12} = Rt;
1462 let Inst{11-0} = shift{11-0};
1468 multiclass AI_str1<bit isByte, string opc, InstrItinClass iii,
1469 InstrItinClass iir, PatFrag opnode> {
1470 // Note: We use the complex addrmode_imm12 rather than just an input
1471 // GPR and a constrained immediate so that we can use this to match
1472 // frame index references and avoid matching constant pool references.
1473 def i12 : AI2ldst<0b010, 0, isByte, (outs),
1474 (ins GPR:$Rt, addrmode_imm12:$addr),
1475 AddrMode_i12, StFrm, iii, opc, "\t$Rt, $addr",
1476 [(opnode GPR:$Rt, addrmode_imm12:$addr)]> {
1479 let Inst{23} = addr{12}; // U (add = ('U' == 1))
1480 let Inst{19-16} = addr{16-13}; // Rn
1481 let Inst{15-12} = Rt;
1482 let Inst{11-0} = addr{11-0}; // imm12
1484 def rs : AI2ldst<0b011, 0, isByte, (outs), (ins GPR:$Rt, ldst_so_reg:$shift),
1485 AddrModeNone, StFrm, iir, opc, "\t$Rt, $shift",
1486 [(opnode GPR:$Rt, ldst_so_reg:$shift)]> {
1489 let shift{4} = 0; // Inst{4} = 0
1490 let Inst{23} = shift{12}; // U (add = ('U' == 1))
1491 let Inst{19-16} = shift{16-13}; // Rn
1492 let Inst{15-12} = Rt;
1493 let Inst{11-0} = shift{11-0};
1497 multiclass AI_str1nopc<bit isByte, string opc, InstrItinClass iii,
1498 InstrItinClass iir, PatFrag opnode> {
1499 // Note: We use the complex addrmode_imm12 rather than just an input
1500 // GPR and a constrained immediate so that we can use this to match
1501 // frame index references and avoid matching constant pool references.
1502 def i12 : AI2ldst<0b010, 0, isByte, (outs),
1503 (ins GPRnopc:$Rt, addrmode_imm12:$addr),
1504 AddrMode_i12, StFrm, iii, opc, "\t$Rt, $addr",
1505 [(opnode GPRnopc:$Rt, addrmode_imm12:$addr)]> {
1508 let Inst{23} = addr{12}; // U (add = ('U' == 1))
1509 let Inst{19-16} = addr{16-13}; // Rn
1510 let Inst{15-12} = Rt;
1511 let Inst{11-0} = addr{11-0}; // imm12
1513 def rs : AI2ldst<0b011, 0, isByte, (outs), (ins GPRnopc:$Rt, ldst_so_reg:$shift),
1514 AddrModeNone, StFrm, iir, opc, "\t$Rt, $shift",
1515 [(opnode GPRnopc:$Rt, ldst_so_reg:$shift)]> {
1518 let shift{4} = 0; // Inst{4} = 0
1519 let Inst{23} = shift{12}; // U (add = ('U' == 1))
1520 let Inst{19-16} = shift{16-13}; // Rn
1521 let Inst{15-12} = Rt;
1522 let Inst{11-0} = shift{11-0};
1527 //===----------------------------------------------------------------------===//
1529 //===----------------------------------------------------------------------===//
1531 //===----------------------------------------------------------------------===//
1532 // Miscellaneous Instructions.
1535 /// CONSTPOOL_ENTRY - This instruction represents a floating constant pool in
1536 /// the function. The first operand is the ID# for this instruction, the second
1537 /// is the index into the MachineConstantPool that this is, the third is the
1538 /// size in bytes of this constant pool entry.
1539 let neverHasSideEffects = 1, isNotDuplicable = 1 in
1540 def CONSTPOOL_ENTRY :
1541 PseudoInst<(outs), (ins cpinst_operand:$instid, cpinst_operand:$cpidx,
1542 i32imm:$size), NoItinerary, []>;
1544 // FIXME: Marking these as hasSideEffects is necessary to prevent machine DCE
1545 // from removing one half of the matched pairs. That breaks PEI, which assumes
1546 // these will always be in pairs, and asserts if it finds otherwise. Better way?
1547 let Defs = [SP], Uses = [SP], hasSideEffects = 1 in {
1548 def ADJCALLSTACKUP :
1549 PseudoInst<(outs), (ins i32imm:$amt1, i32imm:$amt2, pred:$p), NoItinerary,
1550 [(ARMcallseq_end timm:$amt1, timm:$amt2)]>;
1552 def ADJCALLSTACKDOWN :
1553 PseudoInst<(outs), (ins i32imm:$amt, pred:$p), NoItinerary,
1554 [(ARMcallseq_start timm:$amt)]>;
1557 // Atomic pseudo-insts which will be lowered to ldrexd/strexd loops.
1558 // (These pseudos use a hand-written selection code).
1559 let usesCustomInserter = 1, Defs = [CPSR], mayLoad = 1, mayStore = 1 in {
1560 def ATOMOR6432 : PseudoInst<(outs GPR:$dst1, GPR:$dst2),
1561 (ins GPR:$addr, GPR:$src1, GPR:$src2),
1563 def ATOMXOR6432 : PseudoInst<(outs GPR:$dst1, GPR:$dst2),
1564 (ins GPR:$addr, GPR:$src1, GPR:$src2),
1566 def ATOMADD6432 : PseudoInst<(outs GPR:$dst1, GPR:$dst2),
1567 (ins GPR:$addr, GPR:$src1, GPR:$src2),
1569 def ATOMSUB6432 : PseudoInst<(outs GPR:$dst1, GPR:$dst2),
1570 (ins GPR:$addr, GPR:$src1, GPR:$src2),
1572 def ATOMNAND6432 : PseudoInst<(outs GPR:$dst1, GPR:$dst2),
1573 (ins GPR:$addr, GPR:$src1, GPR:$src2),
1575 def ATOMAND6432 : PseudoInst<(outs GPR:$dst1, GPR:$dst2),
1576 (ins GPR:$addr, GPR:$src1, GPR:$src2),
1578 def ATOMSWAP6432 : PseudoInst<(outs GPR:$dst1, GPR:$dst2),
1579 (ins GPR:$addr, GPR:$src1, GPR:$src2),
1581 def ATOMCMPXCHG6432 : PseudoInst<(outs GPR:$dst1, GPR:$dst2),
1582 (ins GPR:$addr, GPR:$cmp1, GPR:$cmp2,
1583 GPR:$set1, GPR:$set2),
1587 def NOP : AI<(outs), (ins), MiscFrm, NoItinerary, "nop", "", []>,
1588 Requires<[IsARM, HasV6T2]> {
1589 let Inst{27-16} = 0b001100100000;
1590 let Inst{15-8} = 0b11110000;
1591 let Inst{7-0} = 0b00000000;
1594 def YIELD : AI<(outs), (ins), MiscFrm, NoItinerary, "yield", "", []>,
1595 Requires<[IsARM, HasV6T2]> {
1596 let Inst{27-16} = 0b001100100000;
1597 let Inst{15-8} = 0b11110000;
1598 let Inst{7-0} = 0b00000001;
1601 def WFE : AI<(outs), (ins), MiscFrm, NoItinerary, "wfe", "", []>,
1602 Requires<[IsARM, HasV6T2]> {
1603 let Inst{27-16} = 0b001100100000;
1604 let Inst{15-8} = 0b11110000;
1605 let Inst{7-0} = 0b00000010;
1608 def WFI : AI<(outs), (ins), MiscFrm, NoItinerary, "wfi", "", []>,
1609 Requires<[IsARM, HasV6T2]> {
1610 let Inst{27-16} = 0b001100100000;
1611 let Inst{15-8} = 0b11110000;
1612 let Inst{7-0} = 0b00000011;
1615 def SEL : AI<(outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm), DPFrm, NoItinerary, "sel",
1616 "\t$Rd, $Rn, $Rm", []>, Requires<[IsARM, HasV6]> {
1621 let Inst{15-12} = Rd;
1622 let Inst{19-16} = Rn;
1623 let Inst{27-20} = 0b01101000;
1624 let Inst{7-4} = 0b1011;
1625 let Inst{11-8} = 0b1111;
1628 def SEV : AI<(outs), (ins), MiscFrm, NoItinerary, "sev", "",
1629 []>, Requires<[IsARM, HasV6T2]> {
1630 let Inst{27-16} = 0b001100100000;
1631 let Inst{15-8} = 0b11110000;
1632 let Inst{7-0} = 0b00000100;
1635 // The i32imm operand $val can be used by a debugger to store more information
1636 // about the breakpoint.
1637 def BKPT : AI<(outs), (ins imm0_65535:$val), MiscFrm, NoItinerary,
1638 "bkpt", "\t$val", []>, Requires<[IsARM]> {
1640 let Inst{3-0} = val{3-0};
1641 let Inst{19-8} = val{15-4};
1642 let Inst{27-20} = 0b00010010;
1643 let Inst{7-4} = 0b0111;
1646 // Change Processor State
1647 // FIXME: We should use InstAlias to handle the optional operands.
1648 class CPS<dag iops, string asm_ops>
1649 : AXI<(outs), iops, MiscFrm, NoItinerary, !strconcat("cps", asm_ops),
1650 []>, Requires<[IsARM]> {
1656 let Inst{31-28} = 0b1111;
1657 let Inst{27-20} = 0b00010000;
1658 let Inst{19-18} = imod;
1659 let Inst{17} = M; // Enabled if mode is set;
1660 let Inst{16-9} = 0b00000000;
1661 let Inst{8-6} = iflags;
1663 let Inst{4-0} = mode;
1666 let DecoderMethod = "DecodeCPSInstruction" in {
1668 def CPS3p : CPS<(ins imod_op:$imod, iflags_op:$iflags, imm0_31:$mode),
1669 "$imod\t$iflags, $mode">;
1670 let mode = 0, M = 0 in
1671 def CPS2p : CPS<(ins imod_op:$imod, iflags_op:$iflags), "$imod\t$iflags">;
1673 let imod = 0, iflags = 0, M = 1 in
1674 def CPS1p : CPS<(ins imm0_31:$mode), "\t$mode">;
1677 // Preload signals the memory system of possible future data/instruction access.
1678 multiclass APreLoad<bits<1> read, bits<1> data, string opc> {
1680 def i12 : AXI<(outs), (ins addrmode_imm12:$addr), MiscFrm, IIC_Preload,
1681 !strconcat(opc, "\t$addr"),
1682 [(ARMPreload addrmode_imm12:$addr, (i32 read), (i32 data))]> {
1685 let Inst{31-26} = 0b111101;
1686 let Inst{25} = 0; // 0 for immediate form
1687 let Inst{24} = data;
1688 let Inst{23} = addr{12}; // U (add = ('U' == 1))
1689 let Inst{22} = read;
1690 let Inst{21-20} = 0b01;
1691 let Inst{19-16} = addr{16-13}; // Rn
1692 let Inst{15-12} = 0b1111;
1693 let Inst{11-0} = addr{11-0}; // imm12
1696 def rs : AXI<(outs), (ins ldst_so_reg:$shift), MiscFrm, IIC_Preload,
1697 !strconcat(opc, "\t$shift"),
1698 [(ARMPreload ldst_so_reg:$shift, (i32 read), (i32 data))]> {
1700 let Inst{31-26} = 0b111101;
1701 let Inst{25} = 1; // 1 for register form
1702 let Inst{24} = data;
1703 let Inst{23} = shift{12}; // U (add = ('U' == 1))
1704 let Inst{22} = read;
1705 let Inst{21-20} = 0b01;
1706 let Inst{19-16} = shift{16-13}; // Rn
1707 let Inst{15-12} = 0b1111;
1708 let Inst{11-0} = shift{11-0};
1713 defm PLD : APreLoad<1, 1, "pld">, Requires<[IsARM]>;
1714 defm PLDW : APreLoad<0, 1, "pldw">, Requires<[IsARM,HasV7,HasMP]>;
1715 defm PLI : APreLoad<1, 0, "pli">, Requires<[IsARM,HasV7]>;
1717 def SETEND : AXI<(outs), (ins setend_op:$end), MiscFrm, NoItinerary,
1718 "setend\t$end", []>, Requires<[IsARM]> {
1720 let Inst{31-10} = 0b1111000100000001000000;
1725 def DBG : AI<(outs), (ins imm0_15:$opt), MiscFrm, NoItinerary, "dbg", "\t$opt",
1726 []>, Requires<[IsARM, HasV7]> {
1728 let Inst{27-4} = 0b001100100000111100001111;
1729 let Inst{3-0} = opt;
1732 // A5.4 Permanently UNDEFINED instructions.
1733 let isBarrier = 1, isTerminator = 1 in
1734 def TRAP : AXI<(outs), (ins), MiscFrm, NoItinerary,
1737 let Inst = 0xe7ffdefe;
1740 // Address computation and loads and stores in PIC mode.
1741 let isNotDuplicable = 1 in {
1742 def PICADD : ARMPseudoInst<(outs GPR:$dst), (ins GPR:$a, pclabel:$cp, pred:$p),
1744 [(set GPR:$dst, (ARMpic_add GPR:$a, imm:$cp))]>;
1746 let AddedComplexity = 10 in {
1747 def PICLDR : ARMPseudoInst<(outs GPR:$dst), (ins addrmodepc:$addr, pred:$p),
1749 [(set GPR:$dst, (load addrmodepc:$addr))]>;
1751 def PICLDRH : ARMPseudoInst<(outs GPR:$Rt), (ins addrmodepc:$addr, pred:$p),
1753 [(set GPR:$Rt, (zextloadi16 addrmodepc:$addr))]>;
1755 def PICLDRB : ARMPseudoInst<(outs GPR:$Rt), (ins addrmodepc:$addr, pred:$p),
1757 [(set GPR:$Rt, (zextloadi8 addrmodepc:$addr))]>;
1759 def PICLDRSH : ARMPseudoInst<(outs GPR:$Rt), (ins addrmodepc:$addr, pred:$p),
1761 [(set GPR:$Rt, (sextloadi16 addrmodepc:$addr))]>;
1763 def PICLDRSB : ARMPseudoInst<(outs GPR:$Rt), (ins addrmodepc:$addr, pred:$p),
1765 [(set GPR:$Rt, (sextloadi8 addrmodepc:$addr))]>;
1767 let AddedComplexity = 10 in {
1768 def PICSTR : ARMPseudoInst<(outs), (ins GPR:$src, addrmodepc:$addr, pred:$p),
1769 4, IIC_iStore_r, [(store GPR:$src, addrmodepc:$addr)]>;
1771 def PICSTRH : ARMPseudoInst<(outs), (ins GPR:$src, addrmodepc:$addr, pred:$p),
1772 4, IIC_iStore_bh_r, [(truncstorei16 GPR:$src,
1773 addrmodepc:$addr)]>;
1775 def PICSTRB : ARMPseudoInst<(outs), (ins GPR:$src, addrmodepc:$addr, pred:$p),
1776 4, IIC_iStore_bh_r, [(truncstorei8 GPR:$src, addrmodepc:$addr)]>;
1778 } // isNotDuplicable = 1
1781 // LEApcrel - Load a pc-relative address into a register without offending the
1783 let neverHasSideEffects = 1, isReMaterializable = 1 in
1784 // The 'adr' mnemonic encodes differently if the label is before or after
1785 // the instruction. The {24-21} opcode bits are set by the fixup, as we don't
1786 // know until then which form of the instruction will be used.
1787 def ADR : AI1<{0,?,?,0}, (outs GPR:$Rd), (ins adrlabel:$label),
1788 MiscFrm, IIC_iALUi, "adr", "\t$Rd, $label", []> {
1791 let Inst{27-25} = 0b001;
1793 let Inst{23-22} = label{13-12};
1796 let Inst{19-16} = 0b1111;
1797 let Inst{15-12} = Rd;
1798 let Inst{11-0} = label{11-0};
1800 def LEApcrel : ARMPseudoInst<(outs GPR:$Rd), (ins i32imm:$label, pred:$p),
1803 def LEApcrelJT : ARMPseudoInst<(outs GPR:$Rd),
1804 (ins i32imm:$label, nohash_imm:$id, pred:$p),
1807 //===----------------------------------------------------------------------===//
1808 // Control Flow Instructions.
1811 let isReturn = 1, isTerminator = 1, isBarrier = 1 in {
1813 def BX_RET : AI<(outs), (ins), BrMiscFrm, IIC_Br,
1814 "bx", "\tlr", [(ARMretflag)]>,
1815 Requires<[IsARM, HasV4T]> {
1816 let Inst{27-0} = 0b0001001011111111111100011110;
1820 def MOVPCLR : AI<(outs), (ins), BrMiscFrm, IIC_Br,
1821 "mov", "\tpc, lr", [(ARMretflag)]>,
1822 Requires<[IsARM, NoV4T]> {
1823 let Inst{27-0} = 0b0001101000001111000000001110;
1827 // Indirect branches
1828 let isBranch = 1, isTerminator = 1, isBarrier = 1, isIndirectBranch = 1 in {
1830 def BX : AXI<(outs), (ins GPR:$dst), BrMiscFrm, IIC_Br, "bx\t$dst",
1831 [(brind GPR:$dst)]>,
1832 Requires<[IsARM, HasV4T]> {
1834 let Inst{31-4} = 0b1110000100101111111111110001;
1835 let Inst{3-0} = dst;
1838 def BX_pred : AI<(outs), (ins GPR:$dst), BrMiscFrm, IIC_Br,
1839 "bx", "\t$dst", [/* pattern left blank */]>,
1840 Requires<[IsARM, HasV4T]> {
1842 let Inst{27-4} = 0b000100101111111111110001;
1843 let Inst{3-0} = dst;
1847 // All calls clobber the non-callee saved registers. SP is marked as
1848 // a use to prevent stack-pointer assignments that appear immediately
1849 // before calls from potentially appearing dead.
1851 // On non-Darwin platforms R9 is callee-saved.
1852 // FIXME: Do we really need a non-predicated version? If so, it should
1853 // at least be a pseudo instruction expanding to the predicated version
1854 // at MC lowering time.
1855 Defs = [R0, R1, R2, R3, R12, LR, QQQQ0, QQQQ2, QQQQ3, CPSR, FPSCR],
1857 def BL : ABXI<0b1011, (outs), (ins bl_target:$func, variable_ops),
1858 IIC_Br, "bl\t$func",
1859 [(ARMcall tglobaladdr:$func)]>,
1860 Requires<[IsARM, IsNotDarwin]> {
1861 let Inst{31-28} = 0b1110;
1863 let Inst{23-0} = func;
1864 let DecoderMethod = "DecodeBranchImmInstruction";
1867 def BL_pred : ABI<0b1011, (outs), (ins bl_target:$func, variable_ops),
1868 IIC_Br, "bl", "\t$func",
1869 [(ARMcall_pred tglobaladdr:$func)]>,
1870 Requires<[IsARM, IsNotDarwin]> {
1872 let Inst{23-0} = func;
1873 let DecoderMethod = "DecodeBranchImmInstruction";
1877 def BLX : AXI<(outs), (ins GPR:$func, variable_ops), BrMiscFrm,
1878 IIC_Br, "blx\t$func",
1879 [(ARMcall GPR:$func)]>,
1880 Requires<[IsARM, HasV5T, IsNotDarwin]> {
1882 let Inst{31-4} = 0b1110000100101111111111110011;
1883 let Inst{3-0} = func;
1886 def BLX_pred : AI<(outs), (ins GPR:$func, variable_ops), BrMiscFrm,
1887 IIC_Br, "blx", "\t$func",
1888 [(ARMcall_pred GPR:$func)]>,
1889 Requires<[IsARM, HasV5T, IsNotDarwin]> {
1891 let Inst{27-4} = 0b000100101111111111110011;
1892 let Inst{3-0} = func;
1896 // Note: Restrict $func to the tGPR regclass to prevent it being in LR.
1897 def BX_CALL : ARMPseudoInst<(outs), (ins tGPR:$func, variable_ops),
1898 8, IIC_Br, [(ARMcall_nolink tGPR:$func)]>,
1899 Requires<[IsARM, HasV4T, IsNotDarwin]>;
1902 def BMOVPCRX_CALL : ARMPseudoInst<(outs), (ins tGPR:$func, variable_ops),
1903 8, IIC_Br, [(ARMcall_nolink tGPR:$func)]>,
1904 Requires<[IsARM, NoV4T, IsNotDarwin]>;
1908 // On Darwin R9 is call-clobbered.
1909 // R7 is marked as a use to prevent frame-pointer assignments from being
1910 // moved above / below calls.
1911 Defs = [R0, R1, R2, R3, R9, R12, LR, QQQQ0, QQQQ2, QQQQ3, CPSR, FPSCR],
1912 Uses = [R7, SP] in {
1913 def BLr9 : ARMPseudoExpand<(outs), (ins bl_target:$func, variable_ops),
1915 [(ARMcall tglobaladdr:$func)], (BL bl_target:$func)>,
1916 Requires<[IsARM, IsDarwin]>;
1918 def BLr9_pred : ARMPseudoExpand<(outs),
1919 (ins bl_target:$func, pred:$p, variable_ops),
1921 [(ARMcall_pred tglobaladdr:$func)],
1922 (BL_pred bl_target:$func, pred:$p)>,
1923 Requires<[IsARM, IsDarwin]>;
1926 def BLXr9 : ARMPseudoExpand<(outs), (ins GPR:$func, variable_ops),
1928 [(ARMcall GPR:$func)],
1930 Requires<[IsARM, HasV5T, IsDarwin]>;
1932 def BLXr9_pred: ARMPseudoExpand<(outs), (ins GPR:$func, pred:$p,variable_ops),
1934 [(ARMcall_pred GPR:$func)],
1935 (BLX_pred GPR:$func, pred:$p)>,
1936 Requires<[IsARM, HasV5T, IsDarwin]>;
1939 // Note: Restrict $func to the tGPR regclass to prevent it being in LR.
1940 def BXr9_CALL : ARMPseudoInst<(outs), (ins tGPR:$func, variable_ops),
1941 8, IIC_Br, [(ARMcall_nolink tGPR:$func)]>,
1942 Requires<[IsARM, HasV4T, IsDarwin]>;
1945 def BMOVPCRXr9_CALL : ARMPseudoInst<(outs), (ins tGPR:$func, variable_ops),
1946 8, IIC_Br, [(ARMcall_nolink tGPR:$func)]>,
1947 Requires<[IsARM, NoV4T, IsDarwin]>;
1950 let isBranch = 1, isTerminator = 1 in {
1951 // FIXME: should be able to write a pattern for ARMBrcond, but can't use
1952 // a two-value operand where a dag node expects two operands. :(
1953 def Bcc : ABI<0b1010, (outs), (ins br_target:$target),
1954 IIC_Br, "b", "\t$target",
1955 [/*(ARMbrcond bb:$target, imm:$cc, CCR:$ccr)*/]> {
1957 let Inst{23-0} = target;
1958 let DecoderMethod = "DecodeBranchImmInstruction";
1961 let isBarrier = 1 in {
1962 // B is "predicable" since it's just a Bcc with an 'always' condition.
1963 let isPredicable = 1 in
1964 // FIXME: We shouldn't need this pseudo at all. Just using Bcc directly
1965 // should be sufficient.
1966 // FIXME: Is B really a Barrier? That doesn't seem right.
1967 def B : ARMPseudoExpand<(outs), (ins br_target:$target), 4, IIC_Br,
1968 [(br bb:$target)], (Bcc br_target:$target, (ops 14, zero_reg))>;
1970 let isNotDuplicable = 1, isIndirectBranch = 1 in {
1971 def BR_JTr : ARMPseudoInst<(outs),
1972 (ins GPR:$target, i32imm:$jt, i32imm:$id),
1974 [(ARMbrjt GPR:$target, tjumptable:$jt, imm:$id)]>;
1975 // FIXME: This shouldn't use the generic "addrmode2," but rather be split
1976 // into i12 and rs suffixed versions.
1977 def BR_JTm : ARMPseudoInst<(outs),
1978 (ins addrmode2:$target, i32imm:$jt, i32imm:$id),
1980 [(ARMbrjt (i32 (load addrmode2:$target)), tjumptable:$jt,
1982 def BR_JTadd : ARMPseudoInst<(outs),
1983 (ins GPR:$target, GPR:$idx, i32imm:$jt, i32imm:$id),
1985 [(ARMbrjt (add GPR:$target, GPR:$idx), tjumptable:$jt,
1987 } // isNotDuplicable = 1, isIndirectBranch = 1
1993 def BLXi : AXI<(outs), (ins blx_target:$target), BrMiscFrm, NoItinerary,
1994 "blx\t$target", []>,
1995 Requires<[IsARM, HasV5T]> {
1996 let Inst{31-25} = 0b1111101;
1998 let Inst{23-0} = target{24-1};
1999 let Inst{24} = target{0};
2002 // Branch and Exchange Jazelle
2003 def BXJ : ABI<0b0001, (outs), (ins GPR:$func), NoItinerary, "bxj", "\t$func",
2004 [/* pattern left blank */]> {
2006 let Inst{23-20} = 0b0010;
2007 let Inst{19-8} = 0xfff;
2008 let Inst{7-4} = 0b0010;
2009 let Inst{3-0} = func;
2014 let isCall = 1, isTerminator = 1, isReturn = 1, isBarrier = 1 in {
2016 let Defs = [R0, R1, R2, R3, R9, R12, QQQQ0, QQQQ2, QQQQ3, PC],
2018 def TCRETURNdi : PseudoInst<(outs), (ins i32imm:$dst, variable_ops),
2019 IIC_Br, []>, Requires<[IsDarwin]>;
2021 def TCRETURNri : PseudoInst<(outs), (ins tcGPR:$dst, variable_ops),
2022 IIC_Br, []>, Requires<[IsDarwin]>;
2024 def TAILJMPd : ARMPseudoExpand<(outs), (ins br_target:$dst, variable_ops),
2026 (Bcc br_target:$dst, (ops 14, zero_reg))>,
2027 Requires<[IsARM, IsDarwin]>;
2029 def TAILJMPr : ARMPseudoExpand<(outs), (ins tcGPR:$dst, variable_ops),
2032 Requires<[IsARM, IsDarwin]>;
2036 // Non-Darwin versions (the difference is R9).
2037 let Defs = [R0, R1, R2, R3, R12, QQQQ0, QQQQ2, QQQQ3, PC],
2039 def TCRETURNdiND : PseudoInst<(outs), (ins i32imm:$dst, variable_ops),
2040 IIC_Br, []>, Requires<[IsNotDarwin]>;
2042 def TCRETURNriND : PseudoInst<(outs), (ins tcGPR:$dst, variable_ops),
2043 IIC_Br, []>, Requires<[IsNotDarwin]>;
2045 def TAILJMPdND : ARMPseudoExpand<(outs), (ins brtarget:$dst, variable_ops),
2047 (Bcc br_target:$dst, (ops 14, zero_reg))>,
2048 Requires<[IsARM, IsNotDarwin]>;
2050 def TAILJMPrND : ARMPseudoExpand<(outs), (ins tcGPR:$dst, variable_ops),
2053 Requires<[IsARM, IsNotDarwin]>;
2057 // Secure Monitor Call is a system instruction.
2058 def SMC : ABI<0b0001, (outs), (ins imm0_15:$opt), NoItinerary, "smc", "\t$opt",
2061 let Inst{23-4} = 0b01100000000000000111;
2062 let Inst{3-0} = opt;
2065 // Supervisor Call (Software Interrupt)
2066 let isCall = 1, Uses = [SP] in {
2067 def SVC : ABI<0b1111, (outs), (ins imm24b:$svc), IIC_Br, "svc", "\t$svc", []> {
2069 let Inst{23-0} = svc;
2073 // Store Return State
2074 class SRSI<bit wb, string asm>
2075 : XI<(outs), (ins imm0_31:$mode), AddrModeNone, 4, IndexModeNone, BrFrm,
2076 NoItinerary, asm, "", []> {
2078 let Inst{31-28} = 0b1111;
2079 let Inst{27-25} = 0b100;
2083 let Inst{19-16} = 0b1101; // SP
2084 let Inst{15-5} = 0b00000101000;
2085 let Inst{4-0} = mode;
2088 def SRSDA : SRSI<0, "srsda\tsp, $mode"> {
2089 let Inst{24-23} = 0;
2091 def SRSDA_UPD : SRSI<1, "srsda\tsp!, $mode"> {
2092 let Inst{24-23} = 0;
2094 def SRSDB : SRSI<0, "srsdb\tsp, $mode"> {
2095 let Inst{24-23} = 0b10;
2097 def SRSDB_UPD : SRSI<1, "srsdb\tsp!, $mode"> {
2098 let Inst{24-23} = 0b10;
2100 def SRSIA : SRSI<0, "srsia\tsp, $mode"> {
2101 let Inst{24-23} = 0b01;
2103 def SRSIA_UPD : SRSI<1, "srsia\tsp!, $mode"> {
2104 let Inst{24-23} = 0b01;
2106 def SRSIB : SRSI<0, "srsib\tsp, $mode"> {
2107 let Inst{24-23} = 0b11;
2109 def SRSIB_UPD : SRSI<1, "srsib\tsp!, $mode"> {
2110 let Inst{24-23} = 0b11;
2113 // Return From Exception
2114 class RFEI<bit wb, string asm>
2115 : XI<(outs), (ins GPR:$Rn), AddrModeNone, 4, IndexModeNone, BrFrm,
2116 NoItinerary, asm, "", []> {
2118 let Inst{31-28} = 0b1111;
2119 let Inst{27-25} = 0b100;
2123 let Inst{19-16} = Rn;
2124 let Inst{15-0} = 0xa00;
2127 def RFEDA : RFEI<0, "rfeda\t$Rn"> {
2128 let Inst{24-23} = 0;
2130 def RFEDA_UPD : RFEI<1, "rfeda\t$Rn!"> {
2131 let Inst{24-23} = 0;
2133 def RFEDB : RFEI<0, "rfedb\t$Rn"> {
2134 let Inst{24-23} = 0b10;
2136 def RFEDB_UPD : RFEI<1, "rfedb\t$Rn!"> {
2137 let Inst{24-23} = 0b10;
2139 def RFEIA : RFEI<0, "rfeia\t$Rn"> {
2140 let Inst{24-23} = 0b01;
2142 def RFEIA_UPD : RFEI<1, "rfeia\t$Rn!"> {
2143 let Inst{24-23} = 0b01;
2145 def RFEIB : RFEI<0, "rfeib\t$Rn"> {
2146 let Inst{24-23} = 0b11;
2148 def RFEIB_UPD : RFEI<1, "rfeib\t$Rn!"> {
2149 let Inst{24-23} = 0b11;
2152 //===----------------------------------------------------------------------===//
2153 // Load / Store Instructions.
2159 defm LDR : AI_ldr1<0, "ldr", IIC_iLoad_r, IIC_iLoad_si,
2160 UnOpFrag<(load node:$Src)>>;
2161 defm LDRB : AI_ldr1nopc<1, "ldrb", IIC_iLoad_bh_r, IIC_iLoad_bh_si,
2162 UnOpFrag<(zextloadi8 node:$Src)>>;
2163 defm STR : AI_str1<0, "str", IIC_iStore_r, IIC_iStore_si,
2164 BinOpFrag<(store node:$LHS, node:$RHS)>>;
2165 defm STRB : AI_str1nopc<1, "strb", IIC_iStore_bh_r, IIC_iStore_bh_si,
2166 BinOpFrag<(truncstorei8 node:$LHS, node:$RHS)>>;
2168 // Special LDR for loads from non-pc-relative constpools.
2169 let canFoldAsLoad = 1, mayLoad = 1, neverHasSideEffects = 1,
2170 isReMaterializable = 1, isCodeGenOnly = 1 in
2171 def LDRcp : AI2ldst<0b010, 1, 0, (outs GPR:$Rt), (ins addrmode_imm12:$addr),
2172 AddrMode_i12, LdFrm, IIC_iLoad_r, "ldr", "\t$Rt, $addr",
2176 let Inst{23} = addr{12}; // U (add = ('U' == 1))
2177 let Inst{19-16} = 0b1111;
2178 let Inst{15-12} = Rt;
2179 let Inst{11-0} = addr{11-0}; // imm12
2182 // Loads with zero extension
2183 def LDRH : AI3ld<0b1011, 1, (outs GPR:$Rt), (ins addrmode3:$addr), LdMiscFrm,
2184 IIC_iLoad_bh_r, "ldrh", "\t$Rt, $addr",
2185 [(set GPR:$Rt, (zextloadi16 addrmode3:$addr))]>;
2187 // Loads with sign extension
2188 def LDRSH : AI3ld<0b1111, 1, (outs GPR:$Rt), (ins addrmode3:$addr), LdMiscFrm,
2189 IIC_iLoad_bh_r, "ldrsh", "\t$Rt, $addr",
2190 [(set GPR:$Rt, (sextloadi16 addrmode3:$addr))]>;
2192 def LDRSB : AI3ld<0b1101, 1, (outs GPR:$Rt), (ins addrmode3:$addr), LdMiscFrm,
2193 IIC_iLoad_bh_r, "ldrsb", "\t$Rt, $addr",
2194 [(set GPR:$Rt, (sextloadi8 addrmode3:$addr))]>;
2196 let mayLoad = 1, neverHasSideEffects = 1, hasExtraDefRegAllocReq = 1 in {
2198 def LDRD : AI3ld<0b1101, 0, (outs GPR:$Rd, GPR:$dst2),
2199 (ins addrmode3:$addr), LdMiscFrm,
2200 IIC_iLoad_d_r, "ldrd", "\t$Rd, $dst2, $addr",
2201 []>, Requires<[IsARM, HasV5TE]>;
2205 multiclass AI2_ldridx<bit isByte, string opc,
2206 InstrItinClass iii, InstrItinClass iir> {
2207 def _PRE_IMM : AI2ldstidx<1, isByte, 1, (outs GPR:$Rt, GPR:$Rn_wb),
2208 (ins addrmode_imm12:$addr), IndexModePre, LdFrm, iii,
2209 opc, "\t$Rt, $addr!", "$addr.base = $Rn_wb", []> {
2212 let Inst{23} = addr{12};
2213 let Inst{19-16} = addr{16-13};
2214 let Inst{11-0} = addr{11-0};
2215 let DecoderMethod = "DecodeLDRPreImm";
2216 let AsmMatchConverter = "cvtLdWriteBackRegAddrModeImm12";
2219 def _PRE_REG : AI2ldstidx<1, isByte, 1, (outs GPR:$Rt, GPR:$Rn_wb),
2220 (ins ldst_so_reg:$addr), IndexModePre, LdFrm, iir,
2221 opc, "\t$Rt, $addr!", "$addr.base = $Rn_wb", []> {
2224 let Inst{23} = addr{12};
2225 let Inst{19-16} = addr{16-13};
2226 let Inst{11-0} = addr{11-0};
2228 let DecoderMethod = "DecodeLDRPreReg";
2229 let AsmMatchConverter = "cvtLdWriteBackRegAddrMode2";
2232 def _POST_REG : AI2ldstidx<1, isByte, 0, (outs GPR:$Rt, GPR:$Rn_wb),
2233 (ins addr_offset_none:$addr, am2offset_reg:$offset),
2234 IndexModePost, LdFrm, iir,
2235 opc, "\t$Rt, $addr, $offset",
2236 "$addr.base = $Rn_wb", []> {
2242 let Inst{23} = offset{12};
2243 let Inst{19-16} = addr;
2244 let Inst{11-0} = offset{11-0};
2246 let DecoderMethod = "DecodeAddrMode2IdxInstruction";
2249 def _POST_IMM : AI2ldstidx<1, isByte, 0, (outs GPR:$Rt, GPR:$Rn_wb),
2250 (ins addr_offset_none:$addr, am2offset_imm:$offset),
2251 IndexModePost, LdFrm, iii,
2252 opc, "\t$Rt, $addr, $offset",
2253 "$addr.base = $Rn_wb", []> {
2259 let Inst{23} = offset{12};
2260 let Inst{19-16} = addr;
2261 let Inst{11-0} = offset{11-0};
2263 let DecoderMethod = "DecodeAddrMode2IdxInstruction";
2268 let mayLoad = 1, neverHasSideEffects = 1 in {
2269 // FIXME: for LDR_PRE_REG etc. the itineray should be either IIC_iLoad_ru or
2270 // IIC_iLoad_siu depending on whether it the offset register is shifted.
2271 defm LDR : AI2_ldridx<0, "ldr", IIC_iLoad_iu, IIC_iLoad_ru>;
2272 defm LDRB : AI2_ldridx<1, "ldrb", IIC_iLoad_bh_iu, IIC_iLoad_bh_ru>;
2275 multiclass AI3_ldridx<bits<4> op, string opc, InstrItinClass itin> {
2276 def _PRE : AI3ldstidx<op, 1, 1, (outs GPR:$Rt, GPR:$Rn_wb),
2277 (ins addrmode3:$addr), IndexModePre,
2279 opc, "\t$Rt, $addr!", "$addr.base = $Rn_wb", []> {
2281 let Inst{23} = addr{8}; // U bit
2282 let Inst{22} = addr{13}; // 1 == imm8, 0 == Rm
2283 let Inst{19-16} = addr{12-9}; // Rn
2284 let Inst{11-8} = addr{7-4}; // imm7_4/zero
2285 let Inst{3-0} = addr{3-0}; // imm3_0/Rm
2286 let AsmMatchConverter = "cvtLdWriteBackRegAddrMode3";
2287 let DecoderMethod = "DecodeAddrMode3Instruction";
2289 def _POST : AI3ldstidx<op, 1, 0, (outs GPR:$Rt, GPR:$Rn_wb),
2290 (ins addr_offset_none:$addr, am3offset:$offset),
2291 IndexModePost, LdMiscFrm, itin,
2292 opc, "\t$Rt, $addr, $offset", "$addr.base = $Rn_wb",
2296 let Inst{23} = offset{8}; // U bit
2297 let Inst{22} = offset{9}; // 1 == imm8, 0 == Rm
2298 let Inst{19-16} = addr;
2299 let Inst{11-8} = offset{7-4}; // imm7_4/zero
2300 let Inst{3-0} = offset{3-0}; // imm3_0/Rm
2301 let DecoderMethod = "DecodeAddrMode3Instruction";
2305 let mayLoad = 1, neverHasSideEffects = 1 in {
2306 defm LDRH : AI3_ldridx<0b1011, "ldrh", IIC_iLoad_bh_ru>;
2307 defm LDRSH : AI3_ldridx<0b1111, "ldrsh", IIC_iLoad_bh_ru>;
2308 defm LDRSB : AI3_ldridx<0b1101, "ldrsb", IIC_iLoad_bh_ru>;
2309 let hasExtraDefRegAllocReq = 1 in {
2310 def LDRD_PRE : AI3ldstidx<0b1101, 0, 1, (outs GPR:$Rt, GPR:$Rt2, GPR:$Rn_wb),
2311 (ins addrmode3:$addr), IndexModePre,
2312 LdMiscFrm, IIC_iLoad_d_ru,
2313 "ldrd", "\t$Rt, $Rt2, $addr!",
2314 "$addr.base = $Rn_wb", []> {
2316 let Inst{23} = addr{8}; // U bit
2317 let Inst{22} = addr{13}; // 1 == imm8, 0 == Rm
2318 let Inst{19-16} = addr{12-9}; // Rn
2319 let Inst{11-8} = addr{7-4}; // imm7_4/zero
2320 let Inst{3-0} = addr{3-0}; // imm3_0/Rm
2321 let DecoderMethod = "DecodeAddrMode3Instruction";
2322 let AsmMatchConverter = "cvtLdrdPre";
2324 def LDRD_POST: AI3ldstidx<0b1101, 0, 0, (outs GPR:$Rt, GPR:$Rt2, GPR:$Rn_wb),
2325 (ins addr_offset_none:$addr, am3offset:$offset),
2326 IndexModePost, LdMiscFrm, IIC_iLoad_d_ru,
2327 "ldrd", "\t$Rt, $Rt2, $addr, $offset",
2328 "$addr.base = $Rn_wb", []> {
2331 let Inst{23} = offset{8}; // U bit
2332 let Inst{22} = offset{9}; // 1 == imm8, 0 == Rm
2333 let Inst{19-16} = addr;
2334 let Inst{11-8} = offset{7-4}; // imm7_4/zero
2335 let Inst{3-0} = offset{3-0}; // imm3_0/Rm
2336 let DecoderMethod = "DecodeAddrMode3Instruction";
2338 } // hasExtraDefRegAllocReq = 1
2339 } // mayLoad = 1, neverHasSideEffects = 1
2341 // LDRT, LDRBT, LDRSBT, LDRHT, LDRSHT.
2342 let mayLoad = 1, neverHasSideEffects = 1 in {
2343 def LDRT_POST_REG : AI2ldstidx<1, 0, 0, (outs GPR:$Rt, GPR:$Rn_wb),
2344 (ins addr_offset_none:$addr, am2offset_reg:$offset),
2345 IndexModePost, LdFrm, IIC_iLoad_ru,
2346 "ldrt", "\t$Rt, $addr, $offset",
2347 "$addr.base = $Rn_wb", []> {
2353 let Inst{23} = offset{12};
2354 let Inst{21} = 1; // overwrite
2355 let Inst{19-16} = addr;
2356 let Inst{11-5} = offset{11-5};
2358 let Inst{3-0} = offset{3-0};
2359 let DecoderMethod = "DecodeAddrMode2IdxInstruction";
2362 def LDRT_POST_IMM : AI2ldstidx<1, 0, 0, (outs GPR:$Rt, GPR:$Rn_wb),
2363 (ins addr_offset_none:$addr, am2offset_imm:$offset),
2364 IndexModePost, LdFrm, IIC_iLoad_ru,
2365 "ldrt", "\t$Rt, $addr, $offset",
2366 "$addr.base = $Rn_wb", []> {
2372 let Inst{23} = offset{12};
2373 let Inst{21} = 1; // overwrite
2374 let Inst{19-16} = addr;
2375 let Inst{11-0} = offset{11-0};
2376 let DecoderMethod = "DecodeAddrMode2IdxInstruction";
2379 def LDRBT_POST_REG : AI2ldstidx<1, 1, 0, (outs GPR:$Rt, GPR:$Rn_wb),
2380 (ins addr_offset_none:$addr, am2offset_reg:$offset),
2381 IndexModePost, LdFrm, IIC_iLoad_bh_ru,
2382 "ldrbt", "\t$Rt, $addr, $offset",
2383 "$addr.base = $Rn_wb", []> {
2389 let Inst{23} = offset{12};
2390 let Inst{21} = 1; // overwrite
2391 let Inst{19-16} = addr;
2392 let Inst{11-5} = offset{11-5};
2394 let Inst{3-0} = offset{3-0};
2395 let DecoderMethod = "DecodeAddrMode2IdxInstruction";
2398 def LDRBT_POST_IMM : AI2ldstidx<1, 1, 0, (outs GPR:$Rt, GPR:$Rn_wb),
2399 (ins addr_offset_none:$addr, am2offset_imm:$offset),
2400 IndexModePost, LdFrm, IIC_iLoad_bh_ru,
2401 "ldrbt", "\t$Rt, $addr, $offset",
2402 "$addr.base = $Rn_wb", []> {
2408 let Inst{23} = offset{12};
2409 let Inst{21} = 1; // overwrite
2410 let Inst{19-16} = addr;
2411 let Inst{11-0} = offset{11-0};
2412 let DecoderMethod = "DecodeAddrMode2IdxInstruction";
2415 multiclass AI3ldrT<bits<4> op, string opc> {
2416 def i : AI3ldstidxT<op, 1, (outs GPR:$Rt, GPR:$base_wb),
2417 (ins addr_offset_none:$addr, postidx_imm8:$offset),
2418 IndexModePost, LdMiscFrm, IIC_iLoad_bh_ru, opc,
2419 "\t$Rt, $addr, $offset", "$addr.base = $base_wb", []> {
2421 let Inst{23} = offset{8};
2423 let Inst{11-8} = offset{7-4};
2424 let Inst{3-0} = offset{3-0};
2425 let AsmMatchConverter = "cvtLdExtTWriteBackImm";
2427 def r : AI3ldstidxT<op, 1, (outs GPR:$Rt, GPR:$base_wb),
2428 (ins addr_offset_none:$addr, postidx_reg:$Rm),
2429 IndexModePost, LdMiscFrm, IIC_iLoad_bh_ru, opc,
2430 "\t$Rt, $addr, $Rm", "$addr.base = $base_wb", []> {
2432 let Inst{23} = Rm{4};
2435 let Inst{3-0} = Rm{3-0};
2436 let AsmMatchConverter = "cvtLdExtTWriteBackReg";
2440 defm LDRSBT : AI3ldrT<0b1101, "ldrsbt">;
2441 defm LDRHT : AI3ldrT<0b1011, "ldrht">;
2442 defm LDRSHT : AI3ldrT<0b1111, "ldrsht">;
2447 // Stores with truncate
2448 def STRH : AI3str<0b1011, (outs), (ins GPR:$Rt, addrmode3:$addr), StMiscFrm,
2449 IIC_iStore_bh_r, "strh", "\t$Rt, $addr",
2450 [(truncstorei16 GPR:$Rt, addrmode3:$addr)]>;
2453 let mayStore = 1, neverHasSideEffects = 1, hasExtraSrcRegAllocReq = 1 in
2454 def STRD : AI3str<0b1111, (outs), (ins GPR:$Rt, GPR:$src2, addrmode3:$addr),
2455 StMiscFrm, IIC_iStore_d_r,
2456 "strd", "\t$Rt, $src2, $addr", []>,
2457 Requires<[IsARM, HasV5TE]> {
2462 multiclass AI2_stridx<bit isByte, string opc,
2463 InstrItinClass iii, InstrItinClass iir> {
2464 def _PRE_IMM : AI2ldstidx<0, isByte, 1, (outs GPR:$Rn_wb),
2465 (ins GPR:$Rt, addrmode_imm12:$addr), IndexModePre,
2467 opc, "\t$Rt, $addr!", "$addr.base = $Rn_wb", []> {
2470 let Inst{23} = addr{12}; // U (add = ('U' == 1))
2471 let Inst{19-16} = addr{16-13}; // Rn
2472 let Inst{11-0} = addr{11-0}; // imm12
2473 let AsmMatchConverter = "cvtStWriteBackRegAddrModeImm12";
2474 let DecoderMethod = "DecodeSTRPreImm";
2477 def _PRE_REG : AI2ldstidx<0, isByte, 1, (outs GPR:$Rn_wb),
2478 (ins GPR:$Rt, ldst_so_reg:$addr),
2479 IndexModePre, StFrm, iir,
2480 opc, "\t$Rt, $addr!", "$addr.base = $Rn_wb", []> {
2483 let Inst{23} = addr{12}; // U (add = ('U' == 1))
2484 let Inst{19-16} = addr{16-13}; // Rn
2485 let Inst{11-0} = addr{11-0};
2486 let Inst{4} = 0; // Inst{4} = 0
2487 let AsmMatchConverter = "cvtStWriteBackRegAddrMode2";
2488 let DecoderMethod = "DecodeSTRPreReg";
2490 def _POST_REG : AI2ldstidx<0, isByte, 0, (outs GPR:$Rn_wb),
2491 (ins GPR:$Rt, addr_offset_none:$addr, am2offset_reg:$offset),
2492 IndexModePost, StFrm, iir,
2493 opc, "\t$Rt, $addr, $offset",
2494 "$addr.base = $Rn_wb", []> {
2500 let Inst{23} = offset{12};
2501 let Inst{19-16} = addr;
2502 let Inst{11-0} = offset{11-0};
2504 let DecoderMethod = "DecodeAddrMode2IdxInstruction";
2507 def _POST_IMM : AI2ldstidx<0, isByte, 0, (outs GPR:$Rn_wb),
2508 (ins GPR:$Rt, addr_offset_none:$addr, am2offset_imm:$offset),
2509 IndexModePost, StFrm, iii,
2510 opc, "\t$Rt, $addr, $offset",
2511 "$addr.base = $Rn_wb", []> {
2517 let Inst{23} = offset{12};
2518 let Inst{19-16} = addr;
2519 let Inst{11-0} = offset{11-0};
2521 let DecoderMethod = "DecodeAddrMode2IdxInstruction";
2525 let mayStore = 1, neverHasSideEffects = 1 in {
2526 // FIXME: for STR_PRE_REG etc. the itineray should be either IIC_iStore_ru or
2527 // IIC_iStore_siu depending on whether it the offset register is shifted.
2528 defm STR : AI2_stridx<0, "str", IIC_iStore_iu, IIC_iStore_ru>;
2529 defm STRB : AI2_stridx<1, "strb", IIC_iStore_bh_iu, IIC_iStore_bh_ru>;
2532 def : ARMPat<(post_store GPR:$Rt, addr_offset_none:$addr,
2533 am2offset_reg:$offset),
2534 (STR_POST_REG GPR:$Rt, addr_offset_none:$addr,
2535 am2offset_reg:$offset)>;
2536 def : ARMPat<(post_store GPR:$Rt, addr_offset_none:$addr,
2537 am2offset_imm:$offset),
2538 (STR_POST_IMM GPR:$Rt, addr_offset_none:$addr,
2539 am2offset_imm:$offset)>;
2540 def : ARMPat<(post_truncsti8 GPR:$Rt, addr_offset_none:$addr,
2541 am2offset_reg:$offset),
2542 (STRB_POST_REG GPR:$Rt, addr_offset_none:$addr,
2543 am2offset_reg:$offset)>;
2544 def : ARMPat<(post_truncsti8 GPR:$Rt, addr_offset_none:$addr,
2545 am2offset_imm:$offset),
2546 (STRB_POST_IMM GPR:$Rt, addr_offset_none:$addr,
2547 am2offset_imm:$offset)>;
2549 // Pseudo-instructions for pattern matching the pre-indexed stores. We can't
2550 // put the patterns on the instruction definitions directly as ISel wants
2551 // the address base and offset to be separate operands, not a single
2552 // complex operand like we represent the instructions themselves. The
2553 // pseudos map between the two.
2554 let usesCustomInserter = 1,
2555 Constraints = "$Rn = $Rn_wb,@earlyclobber $Rn_wb" in {
2556 def STRi_preidx: ARMPseudoInst<(outs GPR:$Rn_wb),
2557 (ins GPR:$Rt, GPR:$Rn, am2offset_imm:$offset, pred:$p),
2560 (pre_store GPR:$Rt, GPR:$Rn, am2offset_imm:$offset))]>;
2561 def STRr_preidx: ARMPseudoInst<(outs GPR:$Rn_wb),
2562 (ins GPR:$Rt, GPR:$Rn, am2offset_reg:$offset, pred:$p),
2565 (pre_store GPR:$Rt, GPR:$Rn, am2offset_reg:$offset))]>;
2566 def STRBi_preidx: ARMPseudoInst<(outs GPR:$Rn_wb),
2567 (ins GPR:$Rt, GPR:$Rn, am2offset_imm:$offset, pred:$p),
2570 (pre_truncsti8 GPR:$Rt, GPR:$Rn, am2offset_imm:$offset))]>;
2571 def STRBr_preidx: ARMPseudoInst<(outs GPR:$Rn_wb),
2572 (ins GPR:$Rt, GPR:$Rn, am2offset_reg:$offset, pred:$p),
2575 (pre_truncsti8 GPR:$Rt, GPR:$Rn, am2offset_reg:$offset))]>;
2576 def STRH_preidx: ARMPseudoInst<(outs GPR:$Rn_wb),
2577 (ins GPR:$Rt, GPR:$Rn, am3offset:$offset, pred:$p),
2580 (pre_truncsti16 GPR:$Rt, GPR:$Rn, am3offset:$offset))]>;
2585 def STRH_PRE : AI3ldstidx<0b1011, 0, 1, (outs GPR:$Rn_wb),
2586 (ins GPR:$Rt, addrmode3:$addr), IndexModePre,
2587 StMiscFrm, IIC_iStore_bh_ru,
2588 "strh", "\t$Rt, $addr!", "$addr.base = $Rn_wb", []> {
2590 let Inst{23} = addr{8}; // U bit
2591 let Inst{22} = addr{13}; // 1 == imm8, 0 == Rm
2592 let Inst{19-16} = addr{12-9}; // Rn
2593 let Inst{11-8} = addr{7-4}; // imm7_4/zero
2594 let Inst{3-0} = addr{3-0}; // imm3_0/Rm
2595 let AsmMatchConverter = "cvtStWriteBackRegAddrMode3";
2596 let DecoderMethod = "DecodeAddrMode3Instruction";
2599 def STRH_POST : AI3ldstidx<0b1011, 0, 0, (outs GPR:$Rn_wb),
2600 (ins GPR:$Rt, addr_offset_none:$addr, am3offset:$offset),
2601 IndexModePost, StMiscFrm, IIC_iStore_bh_ru,
2602 "strh", "\t$Rt, $addr, $offset", "$addr.base = $Rn_wb",
2603 [(set GPR:$Rn_wb, (post_truncsti16 GPR:$Rt,
2604 addr_offset_none:$addr,
2605 am3offset:$offset))]> {
2608 let Inst{23} = offset{8}; // U bit
2609 let Inst{22} = offset{9}; // 1 == imm8, 0 == Rm
2610 let Inst{19-16} = addr;
2611 let Inst{11-8} = offset{7-4}; // imm7_4/zero
2612 let Inst{3-0} = offset{3-0}; // imm3_0/Rm
2613 let DecoderMethod = "DecodeAddrMode3Instruction";
2616 let mayStore = 1, neverHasSideEffects = 1, hasExtraSrcRegAllocReq = 1 in {
2617 def STRD_PRE : AI3ldstidx<0b1111, 0, 1, (outs GPR:$Rn_wb),
2618 (ins GPR:$Rt, GPR:$Rt2, addrmode3:$addr),
2619 IndexModePre, StMiscFrm, IIC_iStore_d_ru,
2620 "strd", "\t$Rt, $Rt2, $addr!",
2621 "$addr.base = $Rn_wb", []> {
2623 let Inst{23} = addr{8}; // U bit
2624 let Inst{22} = addr{13}; // 1 == imm8, 0 == Rm
2625 let Inst{19-16} = addr{12-9}; // Rn
2626 let Inst{11-8} = addr{7-4}; // imm7_4/zero
2627 let Inst{3-0} = addr{3-0}; // imm3_0/Rm
2628 let DecoderMethod = "DecodeAddrMode3Instruction";
2629 let AsmMatchConverter = "cvtStrdPre";
2632 def STRD_POST: AI3ldstidx<0b1111, 0, 0, (outs GPR:$Rn_wb),
2633 (ins GPR:$Rt, GPR:$Rt2, addr_offset_none:$addr,
2635 IndexModePost, StMiscFrm, IIC_iStore_d_ru,
2636 "strd", "\t$Rt, $Rt2, $addr, $offset",
2637 "$addr.base = $Rn_wb", []> {
2640 let Inst{23} = offset{8}; // U bit
2641 let Inst{22} = offset{9}; // 1 == imm8, 0 == Rm
2642 let Inst{19-16} = addr;
2643 let Inst{11-8} = offset{7-4}; // imm7_4/zero
2644 let Inst{3-0} = offset{3-0}; // imm3_0/Rm
2645 let DecoderMethod = "DecodeAddrMode3Instruction";
2647 } // mayStore = 1, neverHasSideEffects = 1, hasExtraSrcRegAllocReq = 1
2649 // STRT, STRBT, and STRHT
2651 def STRBT_POST_REG : AI2ldstidx<0, 1, 0, (outs GPR:$Rn_wb),
2652 (ins GPR:$Rt, addr_offset_none:$addr, am2offset_reg:$offset),
2653 IndexModePost, StFrm, IIC_iStore_bh_ru,
2654 "strbt", "\t$Rt, $addr, $offset",
2655 "$addr.base = $Rn_wb", []> {
2661 let Inst{23} = offset{12};
2662 let Inst{21} = 1; // overwrite
2663 let Inst{19-16} = addr;
2664 let Inst{11-5} = offset{11-5};
2666 let Inst{3-0} = offset{3-0};
2667 let DecoderMethod = "DecodeAddrMode2IdxInstruction";
2670 def STRBT_POST_IMM : AI2ldstidx<0, 1, 0, (outs GPR:$Rn_wb),
2671 (ins GPR:$Rt, addr_offset_none:$addr, am2offset_imm:$offset),
2672 IndexModePost, StFrm, IIC_iStore_bh_ru,
2673 "strbt", "\t$Rt, $addr, $offset",
2674 "$addr.base = $Rn_wb", []> {
2680 let Inst{23} = offset{12};
2681 let Inst{21} = 1; // overwrite
2682 let Inst{19-16} = addr;
2683 let Inst{11-0} = offset{11-0};
2684 let DecoderMethod = "DecodeAddrMode2IdxInstruction";
2687 let mayStore = 1, neverHasSideEffects = 1 in {
2688 def STRT_POST_REG : AI2ldstidx<0, 0, 0, (outs GPR:$Rn_wb),
2689 (ins GPR:$Rt, addr_offset_none:$addr, am2offset_reg:$offset),
2690 IndexModePost, StFrm, IIC_iStore_ru,
2691 "strt", "\t$Rt, $addr, $offset",
2692 "$addr.base = $Rn_wb", []> {
2698 let Inst{23} = offset{12};
2699 let Inst{21} = 1; // overwrite
2700 let Inst{19-16} = addr;
2701 let Inst{11-5} = offset{11-5};
2703 let Inst{3-0} = offset{3-0};
2704 let DecoderMethod = "DecodeAddrMode2IdxInstruction";
2707 def STRT_POST_IMM : AI2ldstidx<0, 0, 0, (outs GPR:$Rn_wb),
2708 (ins GPR:$Rt, addr_offset_none:$addr, am2offset_imm:$offset),
2709 IndexModePost, StFrm, IIC_iStore_ru,
2710 "strt", "\t$Rt, $addr, $offset",
2711 "$addr.base = $Rn_wb", []> {
2717 let Inst{23} = offset{12};
2718 let Inst{21} = 1; // overwrite
2719 let Inst{19-16} = addr;
2720 let Inst{11-0} = offset{11-0};
2721 let DecoderMethod = "DecodeAddrMode2IdxInstruction";
2726 multiclass AI3strT<bits<4> op, string opc> {
2727 def i : AI3ldstidxT<op, 0, (outs GPR:$base_wb),
2728 (ins GPR:$Rt, addr_offset_none:$addr, postidx_imm8:$offset),
2729 IndexModePost, StMiscFrm, IIC_iStore_bh_ru, opc,
2730 "\t$Rt, $addr, $offset", "$addr.base = $base_wb", []> {
2732 let Inst{23} = offset{8};
2734 let Inst{11-8} = offset{7-4};
2735 let Inst{3-0} = offset{3-0};
2736 let AsmMatchConverter = "cvtStExtTWriteBackImm";
2738 def r : AI3ldstidxT<op, 0, (outs GPR:$base_wb),
2739 (ins GPR:$Rt, addr_offset_none:$addr, postidx_reg:$Rm),
2740 IndexModePost, StMiscFrm, IIC_iStore_bh_ru, opc,
2741 "\t$Rt, $addr, $Rm", "$addr.base = $base_wb", []> {
2743 let Inst{23} = Rm{4};
2746 let Inst{3-0} = Rm{3-0};
2747 let AsmMatchConverter = "cvtStExtTWriteBackReg";
2752 defm STRHT : AI3strT<0b1011, "strht">;
2755 //===----------------------------------------------------------------------===//
2756 // Load / store multiple Instructions.
2759 multiclass arm_ldst_mult<string asm, bit L_bit, Format f,
2760 InstrItinClass itin, InstrItinClass itin_upd> {
2761 // IA is the default, so no need for an explicit suffix on the
2762 // mnemonic here. Without it is the cannonical spelling.
2764 AXI4<(outs), (ins GPR:$Rn, pred:$p, reglist:$regs, variable_ops),
2765 IndexModeNone, f, itin,
2766 !strconcat(asm, "${p}\t$Rn, $regs"), "", []> {
2767 let Inst{24-23} = 0b01; // Increment After
2768 let Inst{21} = 0; // No writeback
2769 let Inst{20} = L_bit;
2772 AXI4<(outs GPR:$wb), (ins GPR:$Rn, pred:$p, reglist:$regs, variable_ops),
2773 IndexModeUpd, f, itin_upd,
2774 !strconcat(asm, "${p}\t$Rn!, $regs"), "$Rn = $wb", []> {
2775 let Inst{24-23} = 0b01; // Increment After
2776 let Inst{21} = 1; // Writeback
2777 let Inst{20} = L_bit;
2779 let DecoderMethod = "DecodeMemMultipleWritebackInstruction";
2782 AXI4<(outs), (ins GPR:$Rn, pred:$p, reglist:$regs, variable_ops),
2783 IndexModeNone, f, itin,
2784 !strconcat(asm, "da${p}\t$Rn, $regs"), "", []> {
2785 let Inst{24-23} = 0b00; // Decrement After
2786 let Inst{21} = 0; // No writeback
2787 let Inst{20} = L_bit;
2790 AXI4<(outs GPR:$wb), (ins GPR:$Rn, pred:$p, reglist:$regs, variable_ops),
2791 IndexModeUpd, f, itin_upd,
2792 !strconcat(asm, "da${p}\t$Rn!, $regs"), "$Rn = $wb", []> {
2793 let Inst{24-23} = 0b00; // Decrement After
2794 let Inst{21} = 1; // Writeback
2795 let Inst{20} = L_bit;
2797 let DecoderMethod = "DecodeMemMultipleWritebackInstruction";
2800 AXI4<(outs), (ins GPR:$Rn, pred:$p, reglist:$regs, variable_ops),
2801 IndexModeNone, f, itin,
2802 !strconcat(asm, "db${p}\t$Rn, $regs"), "", []> {
2803 let Inst{24-23} = 0b10; // Decrement Before
2804 let Inst{21} = 0; // No writeback
2805 let Inst{20} = L_bit;
2808 AXI4<(outs GPR:$wb), (ins GPR:$Rn, pred:$p, reglist:$regs, variable_ops),
2809 IndexModeUpd, f, itin_upd,
2810 !strconcat(asm, "db${p}\t$Rn!, $regs"), "$Rn = $wb", []> {
2811 let Inst{24-23} = 0b10; // Decrement Before
2812 let Inst{21} = 1; // Writeback
2813 let Inst{20} = L_bit;
2815 let DecoderMethod = "DecodeMemMultipleWritebackInstruction";
2818 AXI4<(outs), (ins GPR:$Rn, pred:$p, reglist:$regs, variable_ops),
2819 IndexModeNone, f, itin,
2820 !strconcat(asm, "ib${p}\t$Rn, $regs"), "", []> {
2821 let Inst{24-23} = 0b11; // Increment Before
2822 let Inst{21} = 0; // No writeback
2823 let Inst{20} = L_bit;
2826 AXI4<(outs GPR:$wb), (ins GPR:$Rn, pred:$p, reglist:$regs, variable_ops),
2827 IndexModeUpd, f, itin_upd,
2828 !strconcat(asm, "ib${p}\t$Rn!, $regs"), "$Rn = $wb", []> {
2829 let Inst{24-23} = 0b11; // Increment Before
2830 let Inst{21} = 1; // Writeback
2831 let Inst{20} = L_bit;
2833 let DecoderMethod = "DecodeMemMultipleWritebackInstruction";
2837 let neverHasSideEffects = 1 in {
2839 let mayLoad = 1, hasExtraDefRegAllocReq = 1 in
2840 defm LDM : arm_ldst_mult<"ldm", 1, LdStMulFrm, IIC_iLoad_m, IIC_iLoad_mu>;
2842 let mayStore = 1, hasExtraSrcRegAllocReq = 1 in
2843 defm STM : arm_ldst_mult<"stm", 0, LdStMulFrm, IIC_iStore_m, IIC_iStore_mu>;
2845 } // neverHasSideEffects
2847 // FIXME: remove when we have a way to marking a MI with these properties.
2848 // FIXME: Should pc be an implicit operand like PICADD, etc?
2849 let isReturn = 1, isTerminator = 1, isBarrier = 1, mayLoad = 1,
2850 hasExtraDefRegAllocReq = 1, isCodeGenOnly = 1 in
2851 def LDMIA_RET : ARMPseudoExpand<(outs GPR:$wb), (ins GPR:$Rn, pred:$p,
2852 reglist:$regs, variable_ops),
2853 4, IIC_iLoad_mBr, [],
2854 (LDMIA_UPD GPR:$wb, GPR:$Rn, pred:$p, reglist:$regs)>,
2855 RegConstraint<"$Rn = $wb">;
2857 //===----------------------------------------------------------------------===//
2858 // Move Instructions.
2861 let neverHasSideEffects = 1 in
2862 def MOVr : AsI1<0b1101, (outs GPR:$Rd), (ins GPR:$Rm), DPFrm, IIC_iMOVr,
2863 "mov", "\t$Rd, $Rm", []>, UnaryDP {
2867 let Inst{19-16} = 0b0000;
2868 let Inst{11-4} = 0b00000000;
2871 let Inst{15-12} = Rd;
2874 def : ARMInstAlias<"movs${p} $Rd, $Rm",
2875 (MOVr GPR:$Rd, GPR:$Rm, pred:$p, CPSR)>;
2877 // A version for the smaller set of tail call registers.
2878 let neverHasSideEffects = 1 in
2879 def MOVr_TC : AsI1<0b1101, (outs tcGPR:$Rd), (ins tcGPR:$Rm), DPFrm,
2880 IIC_iMOVr, "mov", "\t$Rd, $Rm", []>, UnaryDP {
2884 let Inst{11-4} = 0b00000000;
2887 let Inst{15-12} = Rd;
2890 def MOVsr : AsI1<0b1101, (outs GPRnopc:$Rd), (ins shift_so_reg_reg:$src),
2891 DPSoRegRegFrm, IIC_iMOVsr,
2892 "mov", "\t$Rd, $src",
2893 [(set GPRnopc:$Rd, shift_so_reg_reg:$src)]>, UnaryDP {
2896 let Inst{15-12} = Rd;
2897 let Inst{19-16} = 0b0000;
2898 let Inst{11-8} = src{11-8};
2900 let Inst{6-5} = src{6-5};
2902 let Inst{3-0} = src{3-0};
2906 def MOVsi : AsI1<0b1101, (outs GPR:$Rd), (ins shift_so_reg_imm:$src),
2907 DPSoRegImmFrm, IIC_iMOVsr,
2908 "mov", "\t$Rd, $src", [(set GPR:$Rd, shift_so_reg_imm:$src)]>,
2912 let Inst{15-12} = Rd;
2913 let Inst{19-16} = 0b0000;
2914 let Inst{11-5} = src{11-5};
2916 let Inst{3-0} = src{3-0};
2920 let isReMaterializable = 1, isAsCheapAsAMove = 1, isMoveImm = 1 in
2921 def MOVi : AsI1<0b1101, (outs GPR:$Rd), (ins so_imm:$imm), DPFrm, IIC_iMOVi,
2922 "mov", "\t$Rd, $imm", [(set GPR:$Rd, so_imm:$imm)]>, UnaryDP {
2926 let Inst{15-12} = Rd;
2927 let Inst{19-16} = 0b0000;
2928 let Inst{11-0} = imm;
2931 let isReMaterializable = 1, isAsCheapAsAMove = 1, isMoveImm = 1 in
2932 def MOVi16 : AI1<0b1000, (outs GPR:$Rd), (ins imm0_65535_expr:$imm),
2934 "movw", "\t$Rd, $imm",
2935 [(set GPR:$Rd, imm0_65535:$imm)]>,
2936 Requires<[IsARM, HasV6T2]>, UnaryDP {
2939 let Inst{15-12} = Rd;
2940 let Inst{11-0} = imm{11-0};
2941 let Inst{19-16} = imm{15-12};
2944 let DecoderMethod = "DecodeArmMOVTWInstruction";
2947 def : InstAlias<"mov${p} $Rd, $imm",
2948 (MOVi16 GPR:$Rd, imm0_65535_expr:$imm, pred:$p)>,
2951 def MOVi16_ga_pcrel : PseudoInst<(outs GPR:$Rd),
2952 (ins i32imm:$addr, pclabel:$id), IIC_iMOVi, []>;
2954 let Constraints = "$src = $Rd" in {
2955 def MOVTi16 : AI1<0b1010, (outs GPRnopc:$Rd),
2956 (ins GPR:$src, imm0_65535_expr:$imm),
2958 "movt", "\t$Rd, $imm",
2960 (or (and GPR:$src, 0xffff),
2961 lo16AllZero:$imm))]>, UnaryDP,
2962 Requires<[IsARM, HasV6T2]> {
2965 let Inst{15-12} = Rd;
2966 let Inst{11-0} = imm{11-0};
2967 let Inst{19-16} = imm{15-12};
2970 let DecoderMethod = "DecodeArmMOVTWInstruction";
2973 def MOVTi16_ga_pcrel : PseudoInst<(outs GPR:$Rd),
2974 (ins GPR:$src, i32imm:$addr, pclabel:$id), IIC_iMOVi, []>;
2978 def : ARMPat<(or GPR:$src, 0xffff0000), (MOVTi16 GPR:$src, 0xffff)>,
2979 Requires<[IsARM, HasV6T2]>;
2981 let Uses = [CPSR] in
2982 def RRX: PseudoInst<(outs GPR:$Rd), (ins GPR:$Rm), IIC_iMOVsi,
2983 [(set GPR:$Rd, (ARMrrx GPR:$Rm))]>, UnaryDP,
2986 // These aren't really mov instructions, but we have to define them this way
2987 // due to flag operands.
2989 let Defs = [CPSR] in {
2990 def MOVsrl_flag : PseudoInst<(outs GPR:$dst), (ins GPR:$src), IIC_iMOVsi,
2991 [(set GPR:$dst, (ARMsrl_flag GPR:$src))]>, UnaryDP,
2993 def MOVsra_flag : PseudoInst<(outs GPR:$dst), (ins GPR:$src), IIC_iMOVsi,
2994 [(set GPR:$dst, (ARMsra_flag GPR:$src))]>, UnaryDP,
2998 //===----------------------------------------------------------------------===//
2999 // Extend Instructions.
3004 def SXTB : AI_ext_rrot<0b01101010,
3005 "sxtb", UnOpFrag<(sext_inreg node:$Src, i8)>>;
3006 def SXTH : AI_ext_rrot<0b01101011,
3007 "sxth", UnOpFrag<(sext_inreg node:$Src, i16)>>;
3009 def SXTAB : AI_exta_rrot<0b01101010,
3010 "sxtab", BinOpFrag<(add node:$LHS, (sext_inreg node:$RHS, i8))>>;
3011 def SXTAH : AI_exta_rrot<0b01101011,
3012 "sxtah", BinOpFrag<(add node:$LHS, (sext_inreg node:$RHS,i16))>>;
3014 def SXTB16 : AI_ext_rrot_np<0b01101000, "sxtb16">;
3016 def SXTAB16 : AI_exta_rrot_np<0b01101000, "sxtab16">;
3020 let AddedComplexity = 16 in {
3021 def UXTB : AI_ext_rrot<0b01101110,
3022 "uxtb" , UnOpFrag<(and node:$Src, 0x000000FF)>>;
3023 def UXTH : AI_ext_rrot<0b01101111,
3024 "uxth" , UnOpFrag<(and node:$Src, 0x0000FFFF)>>;
3025 def UXTB16 : AI_ext_rrot<0b01101100,
3026 "uxtb16", UnOpFrag<(and node:$Src, 0x00FF00FF)>>;
3028 // FIXME: This pattern incorrectly assumes the shl operator is a rotate.
3029 // The transformation should probably be done as a combiner action
3030 // instead so we can include a check for masking back in the upper
3031 // eight bits of the source into the lower eight bits of the result.
3032 //def : ARMV6Pat<(and (shl GPR:$Src, (i32 8)), 0xFF00FF),
3033 // (UXTB16r_rot GPR:$Src, 3)>;
3034 def : ARMV6Pat<(and (srl GPR:$Src, (i32 8)), 0xFF00FF),
3035 (UXTB16 GPR:$Src, 1)>;
3037 def UXTAB : AI_exta_rrot<0b01101110, "uxtab",
3038 BinOpFrag<(add node:$LHS, (and node:$RHS, 0x00FF))>>;
3039 def UXTAH : AI_exta_rrot<0b01101111, "uxtah",
3040 BinOpFrag<(add node:$LHS, (and node:$RHS, 0xFFFF))>>;
3043 // This isn't safe in general, the add is two 16-bit units, not a 32-bit add.
3044 def UXTAB16 : AI_exta_rrot_np<0b01101100, "uxtab16">;
3047 def SBFX : I<(outs GPRnopc:$Rd),
3048 (ins GPRnopc:$Rn, imm0_31:$lsb, imm1_32:$width),
3049 AddrMode1, 4, IndexModeNone, DPFrm, IIC_iUNAsi,
3050 "sbfx", "\t$Rd, $Rn, $lsb, $width", "", []>,
3051 Requires<[IsARM, HasV6T2]> {
3056 let Inst{27-21} = 0b0111101;
3057 let Inst{6-4} = 0b101;
3058 let Inst{20-16} = width;
3059 let Inst{15-12} = Rd;
3060 let Inst{11-7} = lsb;
3064 def UBFX : I<(outs GPR:$Rd),
3065 (ins GPR:$Rn, imm0_31:$lsb, imm1_32:$width),
3066 AddrMode1, 4, IndexModeNone, DPFrm, IIC_iUNAsi,
3067 "ubfx", "\t$Rd, $Rn, $lsb, $width", "", []>,
3068 Requires<[IsARM, HasV6T2]> {
3073 let Inst{27-21} = 0b0111111;
3074 let Inst{6-4} = 0b101;
3075 let Inst{20-16} = width;
3076 let Inst{15-12} = Rd;
3077 let Inst{11-7} = lsb;
3081 //===----------------------------------------------------------------------===//
3082 // Arithmetic Instructions.
3085 defm ADD : AsI1_bin_irs<0b0100, "add",
3086 IIC_iALUi, IIC_iALUr, IIC_iALUsr,
3087 BinOpFrag<(add node:$LHS, node:$RHS)>, "ADD", 1>;
3088 defm SUB : AsI1_bin_irs<0b0010, "sub",
3089 IIC_iALUi, IIC_iALUr, IIC_iALUsr,
3090 BinOpFrag<(sub node:$LHS, node:$RHS)>, "SUB">;
3092 // ADD and SUB with 's' bit set.
3094 // Currently, ADDS/SUBS are pseudo opcodes that exist only in the
3095 // selection DAG. They are "lowered" to real ADD/SUB opcodes by
3096 // AdjustInstrPostInstrSelection where we determine whether or not to
3097 // set the "s" bit based on CPSR liveness.
3099 // FIXME: Eliminate ADDS/SUBS pseudo opcodes after adding tablegen
3100 // support for an optional CPSR definition that corresponds to the DAG
3101 // node's second value. We can then eliminate the implicit def of CPSR.
3102 defm ADDS : AsI1_bin_s_irs<IIC_iALUi, IIC_iALUr, IIC_iALUsr,
3103 BinOpFrag<(ARMaddc node:$LHS, node:$RHS)>, 1>;
3104 defm SUBS : AsI1_bin_s_irs<IIC_iALUi, IIC_iALUr, IIC_iALUsr,
3105 BinOpFrag<(ARMsubc node:$LHS, node:$RHS)>>;
3107 defm ADC : AI1_adde_sube_irs<0b0101, "adc",
3108 BinOpWithFlagFrag<(ARMadde node:$LHS, node:$RHS, node:$FLAG)>,
3110 defm SBC : AI1_adde_sube_irs<0b0110, "sbc",
3111 BinOpWithFlagFrag<(ARMsube node:$LHS, node:$RHS, node:$FLAG)>,
3114 defm RSB : AsI1_rbin_irs <0b0011, "rsb",
3115 IIC_iALUi, IIC_iALUr, IIC_iALUsr,
3116 BinOpFrag<(sub node:$LHS, node:$RHS)>, "RSB">;
3118 // FIXME: Eliminate them if we can write def : Pat patterns which defines
3119 // CPSR and the implicit def of CPSR is not needed.
3120 defm RSBS : AsI1_rbin_s_is<IIC_iALUi, IIC_iALUr, IIC_iALUsr,
3121 BinOpFrag<(ARMsubc node:$LHS, node:$RHS)>>;
3123 defm RSC : AI1_rsc_irs<0b0111, "rsc",
3124 BinOpWithFlagFrag<(ARMsube node:$LHS, node:$RHS, node:$FLAG)>,
3127 // (sub X, imm) gets canonicalized to (add X, -imm). Match this form.
3128 // The assume-no-carry-in form uses the negation of the input since add/sub
3129 // assume opposite meanings of the carry flag (i.e., carry == !borrow).
3130 // See the definition of AddWithCarry() in the ARM ARM A2.2.1 for the gory
3132 def : ARMPat<(add GPR:$src, so_imm_neg:$imm),
3133 (SUBri GPR:$src, so_imm_neg:$imm)>;
3134 def : ARMPat<(ARMaddc GPR:$src, so_imm_neg:$imm),
3135 (SUBSri GPR:$src, so_imm_neg:$imm)>;
3137 // The with-carry-in form matches bitwise not instead of the negation.
3138 // Effectively, the inverse interpretation of the carry flag already accounts
3139 // for part of the negation.
3140 def : ARMPat<(ARMadde GPR:$src, so_imm_not:$imm, CPSR),
3141 (SBCri GPR:$src, so_imm_not:$imm)>;
3143 // Note: These are implemented in C++ code, because they have to generate
3144 // ADD/SUBrs instructions, which use a complex pattern that a xform function
3146 // (mul X, 2^n+1) -> (add (X << n), X)
3147 // (mul X, 2^n-1) -> (rsb X, (X << n))
3149 // ARM Arithmetic Instruction
3150 // GPR:$dst = GPR:$a op GPR:$b
3151 class AAI<bits<8> op27_20, bits<8> op11_4, string opc,
3152 list<dag> pattern = [],
3153 dag iops = (ins GPRnopc:$Rn, GPRnopc:$Rm),
3154 string asm = "\t$Rd, $Rn, $Rm">
3155 : AI<(outs GPRnopc:$Rd), iops, DPFrm, IIC_iALUr, opc, asm, pattern> {
3159 let Inst{27-20} = op27_20;
3160 let Inst{11-4} = op11_4;
3161 let Inst{19-16} = Rn;
3162 let Inst{15-12} = Rd;
3166 // Saturating add/subtract
3168 def QADD : AAI<0b00010000, 0b00000101, "qadd",
3169 [(set GPRnopc:$Rd, (int_arm_qadd GPRnopc:$Rm, GPRnopc:$Rn))],
3170 (ins GPRnopc:$Rm, GPRnopc:$Rn), "\t$Rd, $Rm, $Rn">;
3171 def QSUB : AAI<0b00010010, 0b00000101, "qsub",
3172 [(set GPRnopc:$Rd, (int_arm_qsub GPRnopc:$Rm, GPRnopc:$Rn))],
3173 (ins GPRnopc:$Rm, GPRnopc:$Rn), "\t$Rd, $Rm, $Rn">;
3174 def QDADD : AAI<0b00010100, 0b00000101, "qdadd", [],
3175 (ins GPRnopc:$Rm, GPRnopc:$Rn),
3177 def QDSUB : AAI<0b00010110, 0b00000101, "qdsub", [],
3178 (ins GPRnopc:$Rm, GPRnopc:$Rn),
3181 def QADD16 : AAI<0b01100010, 0b11110001, "qadd16">;
3182 def QADD8 : AAI<0b01100010, 0b11111001, "qadd8">;
3183 def QASX : AAI<0b01100010, 0b11110011, "qasx">;
3184 def QSAX : AAI<0b01100010, 0b11110101, "qsax">;
3185 def QSUB16 : AAI<0b01100010, 0b11110111, "qsub16">;
3186 def QSUB8 : AAI<0b01100010, 0b11111111, "qsub8">;
3187 def UQADD16 : AAI<0b01100110, 0b11110001, "uqadd16">;
3188 def UQADD8 : AAI<0b01100110, 0b11111001, "uqadd8">;
3189 def UQASX : AAI<0b01100110, 0b11110011, "uqasx">;
3190 def UQSAX : AAI<0b01100110, 0b11110101, "uqsax">;
3191 def UQSUB16 : AAI<0b01100110, 0b11110111, "uqsub16">;
3192 def UQSUB8 : AAI<0b01100110, 0b11111111, "uqsub8">;
3194 // Signed/Unsigned add/subtract
3196 def SASX : AAI<0b01100001, 0b11110011, "sasx">;
3197 def SADD16 : AAI<0b01100001, 0b11110001, "sadd16">;
3198 def SADD8 : AAI<0b01100001, 0b11111001, "sadd8">;
3199 def SSAX : AAI<0b01100001, 0b11110101, "ssax">;
3200 def SSUB16 : AAI<0b01100001, 0b11110111, "ssub16">;
3201 def SSUB8 : AAI<0b01100001, 0b11111111, "ssub8">;
3202 def UASX : AAI<0b01100101, 0b11110011, "uasx">;
3203 def UADD16 : AAI<0b01100101, 0b11110001, "uadd16">;
3204 def UADD8 : AAI<0b01100101, 0b11111001, "uadd8">;
3205 def USAX : AAI<0b01100101, 0b11110101, "usax">;
3206 def USUB16 : AAI<0b01100101, 0b11110111, "usub16">;
3207 def USUB8 : AAI<0b01100101, 0b11111111, "usub8">;
3209 // Signed/Unsigned halving add/subtract
3211 def SHASX : AAI<0b01100011, 0b11110011, "shasx">;
3212 def SHADD16 : AAI<0b01100011, 0b11110001, "shadd16">;
3213 def SHADD8 : AAI<0b01100011, 0b11111001, "shadd8">;
3214 def SHSAX : AAI<0b01100011, 0b11110101, "shsax">;
3215 def SHSUB16 : AAI<0b01100011, 0b11110111, "shsub16">;
3216 def SHSUB8 : AAI<0b01100011, 0b11111111, "shsub8">;
3217 def UHASX : AAI<0b01100111, 0b11110011, "uhasx">;
3218 def UHADD16 : AAI<0b01100111, 0b11110001, "uhadd16">;
3219 def UHADD8 : AAI<0b01100111, 0b11111001, "uhadd8">;
3220 def UHSAX : AAI<0b01100111, 0b11110101, "uhsax">;
3221 def UHSUB16 : AAI<0b01100111, 0b11110111, "uhsub16">;
3222 def UHSUB8 : AAI<0b01100111, 0b11111111, "uhsub8">;
3224 // Unsigned Sum of Absolute Differences [and Accumulate].
3226 def USAD8 : AI<(outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm),
3227 MulFrm /* for convenience */, NoItinerary, "usad8",
3228 "\t$Rd, $Rn, $Rm", []>,
3229 Requires<[IsARM, HasV6]> {
3233 let Inst{27-20} = 0b01111000;
3234 let Inst{15-12} = 0b1111;
3235 let Inst{7-4} = 0b0001;
3236 let Inst{19-16} = Rd;
3237 let Inst{11-8} = Rm;
3240 def USADA8 : AI<(outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm, GPR:$Ra),
3241 MulFrm /* for convenience */, NoItinerary, "usada8",
3242 "\t$Rd, $Rn, $Rm, $Ra", []>,
3243 Requires<[IsARM, HasV6]> {
3248 let Inst{27-20} = 0b01111000;
3249 let Inst{7-4} = 0b0001;
3250 let Inst{19-16} = Rd;
3251 let Inst{15-12} = Ra;
3252 let Inst{11-8} = Rm;
3256 // Signed/Unsigned saturate
3258 def SSAT : AI<(outs GPRnopc:$Rd),
3259 (ins imm1_32:$sat_imm, GPRnopc:$Rn, shift_imm:$sh),
3260 SatFrm, NoItinerary, "ssat", "\t$Rd, $sat_imm, $Rn$sh", []> {
3265 let Inst{27-21} = 0b0110101;
3266 let Inst{5-4} = 0b01;
3267 let Inst{20-16} = sat_imm;
3268 let Inst{15-12} = Rd;
3269 let Inst{11-7} = sh{4-0};
3270 let Inst{6} = sh{5};
3274 def SSAT16 : AI<(outs GPRnopc:$Rd),
3275 (ins imm1_16:$sat_imm, GPRnopc:$Rn), SatFrm,
3276 NoItinerary, "ssat16", "\t$Rd, $sat_imm, $Rn", []> {
3280 let Inst{27-20} = 0b01101010;
3281 let Inst{11-4} = 0b11110011;
3282 let Inst{15-12} = Rd;
3283 let Inst{19-16} = sat_imm;
3287 def USAT : AI<(outs GPRnopc:$Rd),
3288 (ins imm0_31:$sat_imm, GPRnopc:$Rn, shift_imm:$sh),
3289 SatFrm, NoItinerary, "usat", "\t$Rd, $sat_imm, $Rn$sh", []> {
3294 let Inst{27-21} = 0b0110111;
3295 let Inst{5-4} = 0b01;
3296 let Inst{15-12} = Rd;
3297 let Inst{11-7} = sh{4-0};
3298 let Inst{6} = sh{5};
3299 let Inst{20-16} = sat_imm;
3303 def USAT16 : AI<(outs GPRnopc:$Rd),
3304 (ins imm0_15:$sat_imm, GPRnopc:$Rn), SatFrm,
3305 NoItinerary, "usat16", "\t$Rd, $sat_imm, $Rn", []> {
3309 let Inst{27-20} = 0b01101110;
3310 let Inst{11-4} = 0b11110011;
3311 let Inst{15-12} = Rd;
3312 let Inst{19-16} = sat_imm;
3316 def : ARMV6Pat<(int_arm_ssat GPRnopc:$a, imm:$pos),
3317 (SSAT imm:$pos, GPRnopc:$a, 0)>;
3318 def : ARMV6Pat<(int_arm_usat GPRnopc:$a, imm:$pos),
3319 (USAT imm:$pos, GPRnopc:$a, 0)>;
3321 //===----------------------------------------------------------------------===//
3322 // Bitwise Instructions.
3325 defm AND : AsI1_bin_irs<0b0000, "and",
3326 IIC_iBITi, IIC_iBITr, IIC_iBITsr,
3327 BinOpFrag<(and node:$LHS, node:$RHS)>, "AND", 1>;
3328 defm ORR : AsI1_bin_irs<0b1100, "orr",
3329 IIC_iBITi, IIC_iBITr, IIC_iBITsr,
3330 BinOpFrag<(or node:$LHS, node:$RHS)>, "ORR", 1>;
3331 defm EOR : AsI1_bin_irs<0b0001, "eor",
3332 IIC_iBITi, IIC_iBITr, IIC_iBITsr,
3333 BinOpFrag<(xor node:$LHS, node:$RHS)>, "EOR", 1>;
3334 defm BIC : AsI1_bin_irs<0b1110, "bic",
3335 IIC_iBITi, IIC_iBITr, IIC_iBITsr,
3336 BinOpFrag<(and node:$LHS, (not node:$RHS))>, "BIC">;
3338 // FIXME: bf_inv_mask_imm should be two operands, the lsb and the msb, just
3339 // like in the actual instruction encoding. The complexity of mapping the mask
3340 // to the lsb/msb pair should be handled by ISel, not encapsulated in the
3341 // instruction description.
3342 def BFC : I<(outs GPR:$Rd), (ins GPR:$src, bf_inv_mask_imm:$imm),
3343 AddrMode1, 4, IndexModeNone, DPFrm, IIC_iUNAsi,
3344 "bfc", "\t$Rd, $imm", "$src = $Rd",
3345 [(set GPR:$Rd, (and GPR:$src, bf_inv_mask_imm:$imm))]>,
3346 Requires<[IsARM, HasV6T2]> {
3349 let Inst{27-21} = 0b0111110;
3350 let Inst{6-0} = 0b0011111;
3351 let Inst{15-12} = Rd;
3352 let Inst{11-7} = imm{4-0}; // lsb
3353 let Inst{20-16} = imm{9-5}; // msb
3356 // A8.6.18 BFI - Bitfield insert (Encoding A1)
3357 def BFI:I<(outs GPRnopc:$Rd), (ins GPRnopc:$src, GPR:$Rn, bf_inv_mask_imm:$imm),
3358 AddrMode1, 4, IndexModeNone, DPFrm, IIC_iUNAsi,
3359 "bfi", "\t$Rd, $Rn, $imm", "$src = $Rd",
3360 [(set GPRnopc:$Rd, (ARMbfi GPRnopc:$src, GPR:$Rn,
3361 bf_inv_mask_imm:$imm))]>,
3362 Requires<[IsARM, HasV6T2]> {
3366 let Inst{27-21} = 0b0111110;
3367 let Inst{6-4} = 0b001; // Rn: Inst{3-0} != 15
3368 let Inst{15-12} = Rd;
3369 let Inst{11-7} = imm{4-0}; // lsb
3370 let Inst{20-16} = imm{9-5}; // width
3374 def MVNr : AsI1<0b1111, (outs GPR:$Rd), (ins GPR:$Rm), DPFrm, IIC_iMVNr,
3375 "mvn", "\t$Rd, $Rm",
3376 [(set GPR:$Rd, (not GPR:$Rm))]>, UnaryDP {
3380 let Inst{19-16} = 0b0000;
3381 let Inst{11-4} = 0b00000000;
3382 let Inst{15-12} = Rd;
3385 def MVNsi : AsI1<0b1111, (outs GPR:$Rd), (ins so_reg_imm:$shift),
3386 DPSoRegImmFrm, IIC_iMVNsr, "mvn", "\t$Rd, $shift",
3387 [(set GPR:$Rd, (not so_reg_imm:$shift))]>, UnaryDP {
3391 let Inst{19-16} = 0b0000;
3392 let Inst{15-12} = Rd;
3393 let Inst{11-5} = shift{11-5};
3395 let Inst{3-0} = shift{3-0};
3397 def MVNsr : AsI1<0b1111, (outs GPR:$Rd), (ins so_reg_reg:$shift),
3398 DPSoRegRegFrm, IIC_iMVNsr, "mvn", "\t$Rd, $shift",
3399 [(set GPR:$Rd, (not so_reg_reg:$shift))]>, UnaryDP {
3403 let Inst{19-16} = 0b0000;
3404 let Inst{15-12} = Rd;
3405 let Inst{11-8} = shift{11-8};
3407 let Inst{6-5} = shift{6-5};
3409 let Inst{3-0} = shift{3-0};
3411 let isReMaterializable = 1, isAsCheapAsAMove = 1, isMoveImm = 1 in
3412 def MVNi : AsI1<0b1111, (outs GPR:$Rd), (ins so_imm:$imm), DPFrm,
3413 IIC_iMVNi, "mvn", "\t$Rd, $imm",
3414 [(set GPR:$Rd, so_imm_not:$imm)]>,UnaryDP {
3418 let Inst{19-16} = 0b0000;
3419 let Inst{15-12} = Rd;
3420 let Inst{11-0} = imm;
3423 def : ARMPat<(and GPR:$src, so_imm_not:$imm),
3424 (BICri GPR:$src, so_imm_not:$imm)>;
3426 //===----------------------------------------------------------------------===//
3427 // Multiply Instructions.
3429 class AsMul1I32<bits<7> opcod, dag oops, dag iops, InstrItinClass itin,
3430 string opc, string asm, list<dag> pattern>
3431 : AsMul1I<opcod, oops, iops, itin, opc, asm, pattern> {
3435 let Inst{19-16} = Rd;
3436 let Inst{11-8} = Rm;
3439 class AsMul1I64<bits<7> opcod, dag oops, dag iops, InstrItinClass itin,
3440 string opc, string asm, list<dag> pattern>
3441 : AsMul1I<opcod, oops, iops, itin, opc, asm, pattern> {
3446 let Inst{19-16} = RdHi;
3447 let Inst{15-12} = RdLo;
3448 let Inst{11-8} = Rm;
3452 // FIXME: The v5 pseudos are only necessary for the additional Constraint
3453 // property. Remove them when it's possible to add those properties
3454 // on an individual MachineInstr, not just an instuction description.
3455 let isCommutable = 1 in {
3456 def MUL : AsMul1I32<0b0000000, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm),
3457 IIC_iMUL32, "mul", "\t$Rd, $Rn, $Rm",
3458 [(set GPR:$Rd, (mul GPR:$Rn, GPR:$Rm))]>,
3459 Requires<[IsARM, HasV6]> {
3460 let Inst{15-12} = 0b0000;
3463 let Constraints = "@earlyclobber $Rd" in
3464 def MULv5: ARMPseudoExpand<(outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm,
3465 pred:$p, cc_out:$s),
3467 [(set GPR:$Rd, (mul GPR:$Rn, GPR:$Rm))],
3468 (MUL GPR:$Rd, GPR:$Rn, GPR:$Rm, pred:$p, cc_out:$s)>,
3469 Requires<[IsARM, NoV6]>;
3472 def MLA : AsMul1I32<0b0000001, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm, GPR:$Ra),
3473 IIC_iMAC32, "mla", "\t$Rd, $Rn, $Rm, $Ra",
3474 [(set GPR:$Rd, (add (mul GPR:$Rn, GPR:$Rm), GPR:$Ra))]>,
3475 Requires<[IsARM, HasV6]> {
3477 let Inst{15-12} = Ra;
3480 let Constraints = "@earlyclobber $Rd" in
3481 def MLAv5: ARMPseudoExpand<(outs GPR:$Rd),
3482 (ins GPR:$Rn, GPR:$Rm, GPR:$Ra, pred:$p, cc_out:$s),
3484 [(set GPR:$Rd, (add (mul GPR:$Rn, GPR:$Rm), GPR:$Ra))],
3485 (MLA GPR:$Rd, GPR:$Rn, GPR:$Rm, GPR:$Ra, pred:$p, cc_out:$s)>,
3486 Requires<[IsARM, NoV6]>;
3488 def MLS : AMul1I<0b0000011, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm, GPR:$Ra),
3489 IIC_iMAC32, "mls", "\t$Rd, $Rn, $Rm, $Ra",
3490 [(set GPR:$Rd, (sub GPR:$Ra, (mul GPR:$Rn, GPR:$Rm)))]>,
3491 Requires<[IsARM, HasV6T2]> {
3496 let Inst{19-16} = Rd;
3497 let Inst{15-12} = Ra;
3498 let Inst{11-8} = Rm;
3502 // Extra precision multiplies with low / high results
3503 let neverHasSideEffects = 1 in {
3504 let isCommutable = 1 in {
3505 def SMULL : AsMul1I64<0b0000110, (outs GPR:$RdLo, GPR:$RdHi),
3506 (ins GPR:$Rn, GPR:$Rm), IIC_iMUL64,
3507 "smull", "\t$RdLo, $RdHi, $Rn, $Rm", []>,
3508 Requires<[IsARM, HasV6]>;
3510 def UMULL : AsMul1I64<0b0000100, (outs GPR:$RdLo, GPR:$RdHi),
3511 (ins GPR:$Rn, GPR:$Rm), IIC_iMUL64,
3512 "umull", "\t$RdLo, $RdHi, $Rn, $Rm", []>,
3513 Requires<[IsARM, HasV6]>;
3515 let Constraints = "@earlyclobber $RdLo,@earlyclobber $RdHi" in {
3516 def SMULLv5 : ARMPseudoExpand<(outs GPR:$RdLo, GPR:$RdHi),
3517 (ins GPR:$Rn, GPR:$Rm, pred:$p, cc_out:$s),
3519 (SMULL GPR:$RdLo, GPR:$RdHi, GPR:$Rn, GPR:$Rm, pred:$p, cc_out:$s)>,
3520 Requires<[IsARM, NoV6]>;
3522 def UMULLv5 : ARMPseudoExpand<(outs GPR:$RdLo, GPR:$RdHi),
3523 (ins GPR:$Rn, GPR:$Rm, pred:$p, cc_out:$s),
3525 (UMULL GPR:$RdLo, GPR:$RdHi, GPR:$Rn, GPR:$Rm, pred:$p, cc_out:$s)>,
3526 Requires<[IsARM, NoV6]>;
3530 // Multiply + accumulate
3531 def SMLAL : AsMul1I64<0b0000111, (outs GPR:$RdLo, GPR:$RdHi),
3532 (ins GPR:$Rn, GPR:$Rm), IIC_iMAC64,
3533 "smlal", "\t$RdLo, $RdHi, $Rn, $Rm", []>,
3534 Requires<[IsARM, HasV6]>;
3535 def UMLAL : AsMul1I64<0b0000101, (outs GPR:$RdLo, GPR:$RdHi),
3536 (ins GPR:$Rn, GPR:$Rm), IIC_iMAC64,
3537 "umlal", "\t$RdLo, $RdHi, $Rn, $Rm", []>,
3538 Requires<[IsARM, HasV6]>;
3540 def UMAAL : AMul1I <0b0000010, (outs GPR:$RdLo, GPR:$RdHi),
3541 (ins GPR:$Rn, GPR:$Rm), IIC_iMAC64,
3542 "umaal", "\t$RdLo, $RdHi, $Rn, $Rm", []>,
3543 Requires<[IsARM, HasV6]> {
3548 let Inst{19-16} = RdHi;
3549 let Inst{15-12} = RdLo;
3550 let Inst{11-8} = Rm;
3554 let Constraints = "@earlyclobber $RdLo,@earlyclobber $RdHi" in {
3555 def SMLALv5 : ARMPseudoExpand<(outs GPR:$RdLo, GPR:$RdHi),
3556 (ins GPR:$Rn, GPR:$Rm, pred:$p, cc_out:$s),
3558 (SMLAL GPR:$RdLo, GPR:$RdHi, GPR:$Rn, GPR:$Rm, pred:$p, cc_out:$s)>,
3559 Requires<[IsARM, NoV6]>;
3560 def UMLALv5 : ARMPseudoExpand<(outs GPR:$RdLo, GPR:$RdHi),
3561 (ins GPR:$Rn, GPR:$Rm, pred:$p, cc_out:$s),
3563 (UMLAL GPR:$RdLo, GPR:$RdHi, GPR:$Rn, GPR:$Rm, pred:$p, cc_out:$s)>,
3564 Requires<[IsARM, NoV6]>;
3565 def UMAALv5 : ARMPseudoExpand<(outs GPR:$RdLo, GPR:$RdHi),
3566 (ins GPR:$Rn, GPR:$Rm, pred:$p),
3568 (UMAAL GPR:$RdLo, GPR:$RdHi, GPR:$Rn, GPR:$Rm, pred:$p)>,
3569 Requires<[IsARM, NoV6]>;
3572 } // neverHasSideEffects
3574 // Most significant word multiply
3575 def SMMUL : AMul2I <0b0111010, 0b0001, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm),
3576 IIC_iMUL32, "smmul", "\t$Rd, $Rn, $Rm",
3577 [(set GPR:$Rd, (mulhs GPR:$Rn, GPR:$Rm))]>,
3578 Requires<[IsARM, HasV6]> {
3579 let Inst{15-12} = 0b1111;
3582 def SMMULR : AMul2I <0b0111010, 0b0011, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm),
3583 IIC_iMUL32, "smmulr", "\t$Rd, $Rn, $Rm", []>,
3584 Requires<[IsARM, HasV6]> {
3585 let Inst{15-12} = 0b1111;
3588 def SMMLA : AMul2Ia <0b0111010, 0b0001, (outs GPR:$Rd),
3589 (ins GPR:$Rn, GPR:$Rm, GPR:$Ra),
3590 IIC_iMAC32, "smmla", "\t$Rd, $Rn, $Rm, $Ra",
3591 [(set GPR:$Rd, (add (mulhs GPR:$Rn, GPR:$Rm), GPR:$Ra))]>,
3592 Requires<[IsARM, HasV6]>;
3594 def SMMLAR : AMul2Ia <0b0111010, 0b0011, (outs GPR:$Rd),
3595 (ins GPR:$Rn, GPR:$Rm, GPR:$Ra),
3596 IIC_iMAC32, "smmlar", "\t$Rd, $Rn, $Rm, $Ra", []>,
3597 Requires<[IsARM, HasV6]>;
3599 def SMMLS : AMul2Ia <0b0111010, 0b1101, (outs GPR:$Rd),
3600 (ins GPR:$Rn, GPR:$Rm, GPR:$Ra),
3601 IIC_iMAC32, "smmls", "\t$Rd, $Rn, $Rm, $Ra",
3602 [(set GPR:$Rd, (sub GPR:$Ra, (mulhs GPR:$Rn, GPR:$Rm)))]>,
3603 Requires<[IsARM, HasV6]>;
3605 def SMMLSR : AMul2Ia <0b0111010, 0b1111, (outs GPR:$Rd),
3606 (ins GPR:$Rn, GPR:$Rm, GPR:$Ra),
3607 IIC_iMAC32, "smmlsr", "\t$Rd, $Rn, $Rm, $Ra", []>,
3608 Requires<[IsARM, HasV6]>;
3610 multiclass AI_smul<string opc, PatFrag opnode> {
3611 def BB : AMulxyI<0b0001011, 0b00, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm),
3612 IIC_iMUL16, !strconcat(opc, "bb"), "\t$Rd, $Rn, $Rm",
3613 [(set GPR:$Rd, (opnode (sext_inreg GPR:$Rn, i16),
3614 (sext_inreg GPR:$Rm, i16)))]>,
3615 Requires<[IsARM, HasV5TE]>;
3617 def BT : AMulxyI<0b0001011, 0b10, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm),
3618 IIC_iMUL16, !strconcat(opc, "bt"), "\t$Rd, $Rn, $Rm",
3619 [(set GPR:$Rd, (opnode (sext_inreg GPR:$Rn, i16),
3620 (sra GPR:$Rm, (i32 16))))]>,
3621 Requires<[IsARM, HasV5TE]>;
3623 def TB : AMulxyI<0b0001011, 0b01, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm),
3624 IIC_iMUL16, !strconcat(opc, "tb"), "\t$Rd, $Rn, $Rm",
3625 [(set GPR:$Rd, (opnode (sra GPR:$Rn, (i32 16)),
3626 (sext_inreg GPR:$Rm, i16)))]>,
3627 Requires<[IsARM, HasV5TE]>;
3629 def TT : AMulxyI<0b0001011, 0b11, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm),
3630 IIC_iMUL16, !strconcat(opc, "tt"), "\t$Rd, $Rn, $Rm",
3631 [(set GPR:$Rd, (opnode (sra GPR:$Rn, (i32 16)),
3632 (sra GPR:$Rm, (i32 16))))]>,
3633 Requires<[IsARM, HasV5TE]>;
3635 def WB : AMulxyI<0b0001001, 0b01, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm),
3636 IIC_iMUL16, !strconcat(opc, "wb"), "\t$Rd, $Rn, $Rm",
3637 [(set GPR:$Rd, (sra (opnode GPR:$Rn,
3638 (sext_inreg GPR:$Rm, i16)), (i32 16)))]>,
3639 Requires<[IsARM, HasV5TE]>;
3641 def WT : AMulxyI<0b0001001, 0b11, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm),
3642 IIC_iMUL16, !strconcat(opc, "wt"), "\t$Rd, $Rn, $Rm",
3643 [(set GPR:$Rd, (sra (opnode GPR:$Rn,
3644 (sra GPR:$Rm, (i32 16))), (i32 16)))]>,
3645 Requires<[IsARM, HasV5TE]>;
3649 multiclass AI_smla<string opc, PatFrag opnode> {
3650 let DecoderMethod = "DecodeSMLAInstruction" in {
3651 def BB : AMulxyIa<0b0001000, 0b00, (outs GPRnopc:$Rd),
3652 (ins GPRnopc:$Rn, GPRnopc:$Rm, GPR:$Ra),
3653 IIC_iMAC16, !strconcat(opc, "bb"), "\t$Rd, $Rn, $Rm, $Ra",
3654 [(set GPRnopc:$Rd, (add GPR:$Ra,
3655 (opnode (sext_inreg GPRnopc:$Rn, i16),
3656 (sext_inreg GPRnopc:$Rm, i16))))]>,
3657 Requires<[IsARM, HasV5TE]>;
3659 def BT : AMulxyIa<0b0001000, 0b10, (outs GPRnopc:$Rd),
3660 (ins GPRnopc:$Rn, GPRnopc:$Rm, GPR:$Ra),
3661 IIC_iMAC16, !strconcat(opc, "bt"), "\t$Rd, $Rn, $Rm, $Ra",
3663 (add GPR:$Ra, (opnode (sext_inreg GPRnopc:$Rn, i16),
3664 (sra GPRnopc:$Rm, (i32 16)))))]>,
3665 Requires<[IsARM, HasV5TE]>;
3667 def TB : AMulxyIa<0b0001000, 0b01, (outs GPRnopc:$Rd),
3668 (ins GPRnopc:$Rn, GPRnopc:$Rm, GPR:$Ra),
3669 IIC_iMAC16, !strconcat(opc, "tb"), "\t$Rd, $Rn, $Rm, $Ra",
3671 (add GPR:$Ra, (opnode (sra GPRnopc:$Rn, (i32 16)),
3672 (sext_inreg GPRnopc:$Rm, i16))))]>,
3673 Requires<[IsARM, HasV5TE]>;
3675 def TT : AMulxyIa<0b0001000, 0b11, (outs GPRnopc:$Rd),
3676 (ins GPRnopc:$Rn, GPRnopc:$Rm, GPR:$Ra),
3677 IIC_iMAC16, !strconcat(opc, "tt"), "\t$Rd, $Rn, $Rm, $Ra",
3679 (add GPR:$Ra, (opnode (sra GPRnopc:$Rn, (i32 16)),
3680 (sra GPRnopc:$Rm, (i32 16)))))]>,
3681 Requires<[IsARM, HasV5TE]>;
3683 def WB : AMulxyIa<0b0001001, 0b00, (outs GPRnopc:$Rd),
3684 (ins GPRnopc:$Rn, GPRnopc:$Rm, GPR:$Ra),
3685 IIC_iMAC16, !strconcat(opc, "wb"), "\t$Rd, $Rn, $Rm, $Ra",
3687 (add GPR:$Ra, (sra (opnode GPRnopc:$Rn,
3688 (sext_inreg GPRnopc:$Rm, i16)), (i32 16))))]>,
3689 Requires<[IsARM, HasV5TE]>;
3691 def WT : AMulxyIa<0b0001001, 0b10, (outs GPRnopc:$Rd),
3692 (ins GPRnopc:$Rn, GPRnopc:$Rm, GPR:$Ra),
3693 IIC_iMAC16, !strconcat(opc, "wt"), "\t$Rd, $Rn, $Rm, $Ra",
3695 (add GPR:$Ra, (sra (opnode GPRnopc:$Rn,
3696 (sra GPRnopc:$Rm, (i32 16))), (i32 16))))]>,
3697 Requires<[IsARM, HasV5TE]>;
3701 defm SMUL : AI_smul<"smul", BinOpFrag<(mul node:$LHS, node:$RHS)>>;
3702 defm SMLA : AI_smla<"smla", BinOpFrag<(mul node:$LHS, node:$RHS)>>;
3704 // Halfword multiply accumulate long: SMLAL<x><y>.
3705 def SMLALBB : AMulxyI64<0b0001010, 0b00, (outs GPRnopc:$RdLo, GPRnopc:$RdHi),
3706 (ins GPRnopc:$Rn, GPRnopc:$Rm),
3707 IIC_iMAC64, "smlalbb", "\t$RdLo, $RdHi, $Rn, $Rm", []>,
3708 Requires<[IsARM, HasV5TE]>;
3710 def SMLALBT : AMulxyI64<0b0001010, 0b10, (outs GPRnopc:$RdLo, GPRnopc:$RdHi),
3711 (ins GPRnopc:$Rn, GPRnopc:$Rm),
3712 IIC_iMAC64, "smlalbt", "\t$RdLo, $RdHi, $Rn, $Rm", []>,
3713 Requires<[IsARM, HasV5TE]>;
3715 def SMLALTB : AMulxyI64<0b0001010, 0b01, (outs GPRnopc:$RdLo, GPRnopc:$RdHi),
3716 (ins GPRnopc:$Rn, GPRnopc:$Rm),
3717 IIC_iMAC64, "smlaltb", "\t$RdLo, $RdHi, $Rn, $Rm", []>,
3718 Requires<[IsARM, HasV5TE]>;
3720 def SMLALTT : AMulxyI64<0b0001010, 0b11, (outs GPRnopc:$RdLo, GPRnopc:$RdHi),
3721 (ins GPRnopc:$Rn, GPRnopc:$Rm),
3722 IIC_iMAC64, "smlaltt", "\t$RdLo, $RdHi, $Rn, $Rm", []>,
3723 Requires<[IsARM, HasV5TE]>;
3725 // Helper class for AI_smld.
3726 class AMulDualIbase<bit long, bit sub, bit swap, dag oops, dag iops,
3727 InstrItinClass itin, string opc, string asm>
3728 : AI<oops, iops, MulFrm, itin, opc, asm, []>, Requires<[IsARM, HasV6]> {
3731 let Inst{27-23} = 0b01110;
3732 let Inst{22} = long;
3733 let Inst{21-20} = 0b00;
3734 let Inst{11-8} = Rm;
3741 class AMulDualI<bit long, bit sub, bit swap, dag oops, dag iops,
3742 InstrItinClass itin, string opc, string asm>
3743 : AMulDualIbase<long, sub, swap, oops, iops, itin, opc, asm> {
3745 let Inst{15-12} = 0b1111;
3746 let Inst{19-16} = Rd;
3748 class AMulDualIa<bit long, bit sub, bit swap, dag oops, dag iops,
3749 InstrItinClass itin, string opc, string asm>
3750 : AMulDualIbase<long, sub, swap, oops, iops, itin, opc, asm> {
3753 let Inst{19-16} = Rd;
3754 let Inst{15-12} = Ra;
3756 class AMulDualI64<bit long, bit sub, bit swap, dag oops, dag iops,
3757 InstrItinClass itin, string opc, string asm>
3758 : AMulDualIbase<long, sub, swap, oops, iops, itin, opc, asm> {
3761 let Inst{19-16} = RdHi;
3762 let Inst{15-12} = RdLo;
3765 multiclass AI_smld<bit sub, string opc> {
3767 def D : AMulDualIa<0, sub, 0, (outs GPRnopc:$Rd),
3768 (ins GPRnopc:$Rn, GPRnopc:$Rm, GPR:$Ra),
3769 NoItinerary, !strconcat(opc, "d"), "\t$Rd, $Rn, $Rm, $Ra">;
3771 def DX: AMulDualIa<0, sub, 1, (outs GPRnopc:$Rd),
3772 (ins GPRnopc:$Rn, GPRnopc:$Rm, GPR:$Ra),
3773 NoItinerary, !strconcat(opc, "dx"), "\t$Rd, $Rn, $Rm, $Ra">;
3775 def LD: AMulDualI64<1, sub, 0, (outs GPRnopc:$RdLo, GPRnopc:$RdHi),
3776 (ins GPRnopc:$Rn, GPRnopc:$Rm), NoItinerary,
3777 !strconcat(opc, "ld"), "\t$RdLo, $RdHi, $Rn, $Rm">;
3779 def LDX : AMulDualI64<1, sub, 1, (outs GPRnopc:$RdLo, GPRnopc:$RdHi),
3780 (ins GPRnopc:$Rn, GPRnopc:$Rm), NoItinerary,
3781 !strconcat(opc, "ldx"),"\t$RdLo, $RdHi, $Rn, $Rm">;
3785 defm SMLA : AI_smld<0, "smla">;
3786 defm SMLS : AI_smld<1, "smls">;
3788 multiclass AI_sdml<bit sub, string opc> {
3790 def D:AMulDualI<0, sub, 0, (outs GPRnopc:$Rd), (ins GPRnopc:$Rn, GPRnopc:$Rm),
3791 NoItinerary, !strconcat(opc, "d"), "\t$Rd, $Rn, $Rm">;
3792 def DX:AMulDualI<0, sub, 1, (outs GPRnopc:$Rd),(ins GPRnopc:$Rn, GPRnopc:$Rm),
3793 NoItinerary, !strconcat(opc, "dx"), "\t$Rd, $Rn, $Rm">;
3796 defm SMUA : AI_sdml<0, "smua">;
3797 defm SMUS : AI_sdml<1, "smus">;
3799 //===----------------------------------------------------------------------===//
3800 // Misc. Arithmetic Instructions.
3803 def CLZ : AMiscA1I<0b000010110, 0b0001, (outs GPR:$Rd), (ins GPR:$Rm),
3804 IIC_iUNAr, "clz", "\t$Rd, $Rm",
3805 [(set GPR:$Rd, (ctlz GPR:$Rm))]>, Requires<[IsARM, HasV5T]>;
3807 def RBIT : AMiscA1I<0b01101111, 0b0011, (outs GPR:$Rd), (ins GPR:$Rm),
3808 IIC_iUNAr, "rbit", "\t$Rd, $Rm",
3809 [(set GPR:$Rd, (ARMrbit GPR:$Rm))]>,
3810 Requires<[IsARM, HasV6T2]>;
3812 def REV : AMiscA1I<0b01101011, 0b0011, (outs GPR:$Rd), (ins GPR:$Rm),
3813 IIC_iUNAr, "rev", "\t$Rd, $Rm",
3814 [(set GPR:$Rd, (bswap GPR:$Rm))]>, Requires<[IsARM, HasV6]>;
3816 let AddedComplexity = 5 in
3817 def REV16 : AMiscA1I<0b01101011, 0b1011, (outs GPR:$Rd), (ins GPR:$Rm),
3818 IIC_iUNAr, "rev16", "\t$Rd, $Rm",
3819 [(set GPR:$Rd, (rotr (bswap GPR:$Rm), (i32 16)))]>,
3820 Requires<[IsARM, HasV6]>;
3822 let AddedComplexity = 5 in
3823 def REVSH : AMiscA1I<0b01101111, 0b1011, (outs GPR:$Rd), (ins GPR:$Rm),
3824 IIC_iUNAr, "revsh", "\t$Rd, $Rm",
3825 [(set GPR:$Rd, (sra (bswap GPR:$Rm), (i32 16)))]>,
3826 Requires<[IsARM, HasV6]>;
3828 def : ARMV6Pat<(or (sra (shl GPR:$Rm, (i32 24)), (i32 16)),
3829 (and (srl GPR:$Rm, (i32 8)), 0xFF)),
3832 def PKHBT : APKHI<0b01101000, 0, (outs GPRnopc:$Rd),
3833 (ins GPRnopc:$Rn, GPRnopc:$Rm, pkh_lsl_amt:$sh),
3834 IIC_iALUsi, "pkhbt", "\t$Rd, $Rn, $Rm$sh",
3835 [(set GPRnopc:$Rd, (or (and GPRnopc:$Rn, 0xFFFF),
3836 (and (shl GPRnopc:$Rm, pkh_lsl_amt:$sh),
3838 Requires<[IsARM, HasV6]>;
3840 // Alternate cases for PKHBT where identities eliminate some nodes.
3841 def : ARMV6Pat<(or (and GPRnopc:$Rn, 0xFFFF), (and GPRnopc:$Rm, 0xFFFF0000)),
3842 (PKHBT GPRnopc:$Rn, GPRnopc:$Rm, 0)>;
3843 def : ARMV6Pat<(or (and GPRnopc:$Rn, 0xFFFF), (shl GPRnopc:$Rm, imm16_31:$sh)),
3844 (PKHBT GPRnopc:$Rn, GPRnopc:$Rm, imm16_31:$sh)>;
3846 // Note: Shifts of 1-15 bits will be transformed to srl instead of sra and
3847 // will match the pattern below.
3848 def PKHTB : APKHI<0b01101000, 1, (outs GPRnopc:$Rd),
3849 (ins GPRnopc:$Rn, GPRnopc:$Rm, pkh_asr_amt:$sh),
3850 IIC_iBITsi, "pkhtb", "\t$Rd, $Rn, $Rm$sh",
3851 [(set GPRnopc:$Rd, (or (and GPRnopc:$Rn, 0xFFFF0000),
3852 (and (sra GPRnopc:$Rm, pkh_asr_amt:$sh),
3854 Requires<[IsARM, HasV6]>;
3856 // Alternate cases for PKHTB where identities eliminate some nodes. Note that
3857 // a shift amount of 0 is *not legal* here, it is PKHBT instead.
3858 def : ARMV6Pat<(or (and GPRnopc:$src1, 0xFFFF0000),
3859 (srl GPRnopc:$src2, imm16_31:$sh)),
3860 (PKHTB GPRnopc:$src1, GPRnopc:$src2, imm16_31:$sh)>;
3861 def : ARMV6Pat<(or (and GPRnopc:$src1, 0xFFFF0000),
3862 (and (srl GPRnopc:$src2, imm1_15:$sh), 0xFFFF)),
3863 (PKHTB GPRnopc:$src1, GPRnopc:$src2, imm1_15:$sh)>;
3865 //===----------------------------------------------------------------------===//
3866 // Comparison Instructions...
3869 defm CMP : AI1_cmp_irs<0b1010, "cmp",
3870 IIC_iCMPi, IIC_iCMPr, IIC_iCMPsr,
3871 BinOpFrag<(ARMcmp node:$LHS, node:$RHS)>>;
3873 // ARMcmpZ can re-use the above instruction definitions.
3874 def : ARMPat<(ARMcmpZ GPR:$src, so_imm:$imm),
3875 (CMPri GPR:$src, so_imm:$imm)>;
3876 def : ARMPat<(ARMcmpZ GPR:$src, GPR:$rhs),
3877 (CMPrr GPR:$src, GPR:$rhs)>;
3878 def : ARMPat<(ARMcmpZ GPR:$src, so_reg_imm:$rhs),
3879 (CMPrsi GPR:$src, so_reg_imm:$rhs)>;
3880 def : ARMPat<(ARMcmpZ GPR:$src, so_reg_reg:$rhs),
3881 (CMPrsr GPR:$src, so_reg_reg:$rhs)>;
3883 // FIXME: We have to be careful when using the CMN instruction and comparison
3884 // with 0. One would expect these two pieces of code should give identical
3900 // However, the CMN gives the *opposite* result when r1 is 0. This is because
3901 // the carry flag is set in the CMP case but not in the CMN case. In short, the
3902 // CMP instruction doesn't perform a truncate of the (logical) NOT of 0 plus the
3903 // value of r0 and the carry bit (because the "carry bit" parameter to
3904 // AddWithCarry is defined as 1 in this case, the carry flag will always be set
3905 // when r0 >= 0). The CMN instruction doesn't perform a NOT of 0 so there is
3906 // never a "carry" when this AddWithCarry is performed (because the "carry bit"
3907 // parameter to AddWithCarry is defined as 0).
3909 // When x is 0 and unsigned:
3913 // ~x + 1 = 0x1 0000 0000
3914 // (-x = 0) != (0x1 0000 0000 = ~x + 1)
3916 // Therefore, we should disable CMN when comparing against zero, until we can
3917 // limit when the CMN instruction is used (when we know that the RHS is not 0 or
3918 // when it's a comparison which doesn't look at the 'carry' flag).
3920 // (See the ARM docs for the "AddWithCarry" pseudo-code.)
3922 // This is related to <rdar://problem/7569620>.
3924 //defm CMN : AI1_cmp_irs<0b1011, "cmn",
3925 // BinOpFrag<(ARMcmp node:$LHS,(ineg node:$RHS))>>;
3927 // Note that TST/TEQ don't set all the same flags that CMP does!
3928 defm TST : AI1_cmp_irs<0b1000, "tst",
3929 IIC_iTSTi, IIC_iTSTr, IIC_iTSTsr,
3930 BinOpFrag<(ARMcmpZ (and_su node:$LHS, node:$RHS), 0)>, 1>;
3931 defm TEQ : AI1_cmp_irs<0b1001, "teq",
3932 IIC_iTSTi, IIC_iTSTr, IIC_iTSTsr,
3933 BinOpFrag<(ARMcmpZ (xor_su node:$LHS, node:$RHS), 0)>, 1>;
3935 defm CMNz : AI1_cmp_irs<0b1011, "cmn",
3936 IIC_iCMPi, IIC_iCMPr, IIC_iCMPsr,
3937 BinOpFrag<(ARMcmpZ node:$LHS,(ineg node:$RHS))>>;
3939 //def : ARMPat<(ARMcmp GPR:$src, so_imm_neg:$imm),
3940 // (CMNri GPR:$src, so_imm_neg:$imm)>;
3942 def : ARMPat<(ARMcmpZ GPR:$src, so_imm_neg:$imm),
3943 (CMNzri GPR:$src, so_imm_neg:$imm)>;
3945 // Pseudo i64 compares for some floating point compares.
3946 let usesCustomInserter = 1, isBranch = 1, isTerminator = 1,
3948 def BCCi64 : PseudoInst<(outs),
3949 (ins i32imm:$cc, GPR:$lhs1, GPR:$lhs2, GPR:$rhs1, GPR:$rhs2, brtarget:$dst),
3951 [(ARMBcci64 imm:$cc, GPR:$lhs1, GPR:$lhs2, GPR:$rhs1, GPR:$rhs2, bb:$dst)]>;
3953 def BCCZi64 : PseudoInst<(outs),
3954 (ins i32imm:$cc, GPR:$lhs1, GPR:$lhs2, brtarget:$dst), IIC_Br,
3955 [(ARMBcci64 imm:$cc, GPR:$lhs1, GPR:$lhs2, 0, 0, bb:$dst)]>;
3956 } // usesCustomInserter
3959 // Conditional moves
3960 // FIXME: should be able to write a pattern for ARMcmov, but can't use
3961 // a two-value operand where a dag node expects two operands. :(
3962 let neverHasSideEffects = 1 in {
3963 def MOVCCr : ARMPseudoInst<(outs GPR:$Rd), (ins GPR:$false, GPR:$Rm, pred:$p),
3965 [/*(set GPR:$Rd, (ARMcmov GPR:$false, GPR:$Rm, imm:$cc, CCR:$ccr))*/]>,
3966 RegConstraint<"$false = $Rd">;
3967 def MOVCCsi : ARMPseudoInst<(outs GPR:$Rd),
3968 (ins GPR:$false, so_reg_imm:$shift, pred:$p),
3970 [/*(set GPR:$Rd, (ARMcmov GPR:$false, so_reg_imm:$shift,
3971 imm:$cc, CCR:$ccr))*/]>,
3972 RegConstraint<"$false = $Rd">;
3973 def MOVCCsr : ARMPseudoInst<(outs GPR:$Rd),
3974 (ins GPR:$false, so_reg_reg:$shift, pred:$p),
3976 [/*(set GPR:$Rd, (ARMcmov GPR:$false, so_reg_reg:$shift,
3977 imm:$cc, CCR:$ccr))*/]>,
3978 RegConstraint<"$false = $Rd">;
3981 let isMoveImm = 1 in
3982 def MOVCCi16 : ARMPseudoInst<(outs GPR:$Rd),
3983 (ins GPR:$false, imm0_65535_expr:$imm, pred:$p),
3986 RegConstraint<"$false = $Rd">, Requires<[IsARM, HasV6T2]>;
3988 let isMoveImm = 1 in
3989 def MOVCCi : ARMPseudoInst<(outs GPR:$Rd),
3990 (ins GPR:$false, so_imm:$imm, pred:$p),
3992 [/*(set GPR:$Rd, (ARMcmov GPR:$false, so_imm:$imm, imm:$cc, CCR:$ccr))*/]>,
3993 RegConstraint<"$false = $Rd">;
3995 // Two instruction predicate mov immediate.
3996 let isMoveImm = 1 in
3997 def MOVCCi32imm : ARMPseudoInst<(outs GPR:$Rd),
3998 (ins GPR:$false, i32imm:$src, pred:$p),
3999 8, IIC_iCMOVix2, []>, RegConstraint<"$false = $Rd">;
4001 let isMoveImm = 1 in
4002 def MVNCCi : ARMPseudoInst<(outs GPR:$Rd),
4003 (ins GPR:$false, so_imm:$imm, pred:$p),
4005 [/*(set GPR:$Rd, (ARMcmov GPR:$false, so_imm_not:$imm, imm:$cc, CCR:$ccr))*/]>,
4006 RegConstraint<"$false = $Rd">;
4007 } // neverHasSideEffects
4009 //===----------------------------------------------------------------------===//
4010 // Atomic operations intrinsics
4013 def MemBarrierOptOperand : AsmOperandClass {
4014 let Name = "MemBarrierOpt";
4015 let ParserMethod = "parseMemBarrierOptOperand";
4017 def memb_opt : Operand<i32> {
4018 let PrintMethod = "printMemBOption";
4019 let ParserMatchClass = MemBarrierOptOperand;
4020 let DecoderMethod = "DecodeMemBarrierOption";
4023 // memory barriers protect the atomic sequences
4024 let hasSideEffects = 1 in {
4025 def DMB : AInoP<(outs), (ins memb_opt:$opt), MiscFrm, NoItinerary,
4026 "dmb", "\t$opt", [(ARMMemBarrier (i32 imm:$opt))]>,
4027 Requires<[IsARM, HasDB]> {
4029 let Inst{31-4} = 0xf57ff05;
4030 let Inst{3-0} = opt;
4034 def DSB : AInoP<(outs), (ins memb_opt:$opt), MiscFrm, NoItinerary,
4035 "dsb", "\t$opt", []>,
4036 Requires<[IsARM, HasDB]> {
4038 let Inst{31-4} = 0xf57ff04;
4039 let Inst{3-0} = opt;
4042 // ISB has only full system option
4043 def ISB : AInoP<(outs), (ins memb_opt:$opt), MiscFrm, NoItinerary,
4044 "isb", "\t$opt", []>,
4045 Requires<[IsARM, HasDB]> {
4047 let Inst{31-4} = 0xf57ff06;
4048 let Inst{3-0} = opt;
4051 // Pseudo isntruction that combines movs + predicated rsbmi
4052 // to implement integer ABS
4053 let usesCustomInserter = 1, Defs = [CPSR] in {
4054 def ABS : ARMPseudoInst<
4055 (outs GPR:$dst), (ins GPR:$src),
4056 8, NoItinerary, []>;
4059 let usesCustomInserter = 1 in {
4060 let Defs = [CPSR] in {
4061 def ATOMIC_LOAD_ADD_I8 : PseudoInst<
4062 (outs GPR:$dst), (ins GPR:$ptr, GPR:$incr), NoItinerary,
4063 [(set GPR:$dst, (atomic_load_add_8 GPR:$ptr, GPR:$incr))]>;
4064 def ATOMIC_LOAD_SUB_I8 : PseudoInst<
4065 (outs GPR:$dst), (ins GPR:$ptr, GPR:$incr), NoItinerary,
4066 [(set GPR:$dst, (atomic_load_sub_8 GPR:$ptr, GPR:$incr))]>;
4067 def ATOMIC_LOAD_AND_I8 : PseudoInst<
4068 (outs GPR:$dst), (ins GPR:$ptr, GPR:$incr), NoItinerary,
4069 [(set GPR:$dst, (atomic_load_and_8 GPR:$ptr, GPR:$incr))]>;
4070 def ATOMIC_LOAD_OR_I8 : PseudoInst<
4071 (outs GPR:$dst), (ins GPR:$ptr, GPR:$incr), NoItinerary,
4072 [(set GPR:$dst, (atomic_load_or_8 GPR:$ptr, GPR:$incr))]>;
4073 def ATOMIC_LOAD_XOR_I8 : PseudoInst<
4074 (outs GPR:$dst), (ins GPR:$ptr, GPR:$incr), NoItinerary,
4075 [(set GPR:$dst, (atomic_load_xor_8 GPR:$ptr, GPR:$incr))]>;
4076 def ATOMIC_LOAD_NAND_I8 : PseudoInst<
4077 (outs GPR:$dst), (ins GPR:$ptr, GPR:$incr), NoItinerary,
4078 [(set GPR:$dst, (atomic_load_nand_8 GPR:$ptr, GPR:$incr))]>;
4079 def ATOMIC_LOAD_MIN_I8 : PseudoInst<
4080 (outs GPR:$dst), (ins GPR:$ptr, GPR:$val), NoItinerary,
4081 [(set GPR:$dst, (atomic_load_min_8 GPR:$ptr, GPR:$val))]>;
4082 def ATOMIC_LOAD_MAX_I8 : PseudoInst<
4083 (outs GPR:$dst), (ins GPR:$ptr, GPR:$val), NoItinerary,
4084 [(set GPR:$dst, (atomic_load_max_8 GPR:$ptr, GPR:$val))]>;
4085 def ATOMIC_LOAD_UMIN_I8 : PseudoInst<
4086 (outs GPR:$dst), (ins GPR:$ptr, GPR:$val), NoItinerary,
4087 [(set GPR:$dst, (atomic_load_min_8 GPR:$ptr, GPR:$val))]>;
4088 def ATOMIC_LOAD_UMAX_I8 : PseudoInst<
4089 (outs GPR:$dst), (ins GPR:$ptr, GPR:$val), NoItinerary,
4090 [(set GPR:$dst, (atomic_load_max_8 GPR:$ptr, GPR:$val))]>;
4091 def ATOMIC_LOAD_ADD_I16 : PseudoInst<
4092 (outs GPR:$dst), (ins GPR:$ptr, GPR:$incr), NoItinerary,
4093 [(set GPR:$dst, (atomic_load_add_16 GPR:$ptr, GPR:$incr))]>;
4094 def ATOMIC_LOAD_SUB_I16 : PseudoInst<
4095 (outs GPR:$dst), (ins GPR:$ptr, GPR:$incr), NoItinerary,
4096 [(set GPR:$dst, (atomic_load_sub_16 GPR:$ptr, GPR:$incr))]>;
4097 def ATOMIC_LOAD_AND_I16 : PseudoInst<
4098 (outs GPR:$dst), (ins GPR:$ptr, GPR:$incr), NoItinerary,
4099 [(set GPR:$dst, (atomic_load_and_16 GPR:$ptr, GPR:$incr))]>;
4100 def ATOMIC_LOAD_OR_I16 : PseudoInst<
4101 (outs GPR:$dst), (ins GPR:$ptr, GPR:$incr), NoItinerary,
4102 [(set GPR:$dst, (atomic_load_or_16 GPR:$ptr, GPR:$incr))]>;
4103 def ATOMIC_LOAD_XOR_I16 : PseudoInst<
4104 (outs GPR:$dst), (ins GPR:$ptr, GPR:$incr), NoItinerary,
4105 [(set GPR:$dst, (atomic_load_xor_16 GPR:$ptr, GPR:$incr))]>;
4106 def ATOMIC_LOAD_NAND_I16 : PseudoInst<
4107 (outs GPR:$dst), (ins GPR:$ptr, GPR:$incr), NoItinerary,
4108 [(set GPR:$dst, (atomic_load_nand_16 GPR:$ptr, GPR:$incr))]>;
4109 def ATOMIC_LOAD_MIN_I16 : PseudoInst<
4110 (outs GPR:$dst), (ins GPR:$ptr, GPR:$val), NoItinerary,
4111 [(set GPR:$dst, (atomic_load_min_16 GPR:$ptr, GPR:$val))]>;
4112 def ATOMIC_LOAD_MAX_I16 : PseudoInst<
4113 (outs GPR:$dst), (ins GPR:$ptr, GPR:$val), NoItinerary,
4114 [(set GPR:$dst, (atomic_load_max_16 GPR:$ptr, GPR:$val))]>;
4115 def ATOMIC_LOAD_UMIN_I16 : PseudoInst<
4116 (outs GPR:$dst), (ins GPR:$ptr, GPR:$val), NoItinerary,
4117 [(set GPR:$dst, (atomic_load_min_16 GPR:$ptr, GPR:$val))]>;
4118 def ATOMIC_LOAD_UMAX_I16 : PseudoInst<
4119 (outs GPR:$dst), (ins GPR:$ptr, GPR:$val), NoItinerary,
4120 [(set GPR:$dst, (atomic_load_max_16 GPR:$ptr, GPR:$val))]>;
4121 def ATOMIC_LOAD_ADD_I32 : PseudoInst<
4122 (outs GPR:$dst), (ins GPR:$ptr, GPR:$incr), NoItinerary,
4123 [(set GPR:$dst, (atomic_load_add_32 GPR:$ptr, GPR:$incr))]>;
4124 def ATOMIC_LOAD_SUB_I32 : PseudoInst<
4125 (outs GPR:$dst), (ins GPR:$ptr, GPR:$incr), NoItinerary,
4126 [(set GPR:$dst, (atomic_load_sub_32 GPR:$ptr, GPR:$incr))]>;
4127 def ATOMIC_LOAD_AND_I32 : PseudoInst<
4128 (outs GPR:$dst), (ins GPR:$ptr, GPR:$incr), NoItinerary,
4129 [(set GPR:$dst, (atomic_load_and_32 GPR:$ptr, GPR:$incr))]>;
4130 def ATOMIC_LOAD_OR_I32 : PseudoInst<
4131 (outs GPR:$dst), (ins GPR:$ptr, GPR:$incr), NoItinerary,
4132 [(set GPR:$dst, (atomic_load_or_32 GPR:$ptr, GPR:$incr))]>;
4133 def ATOMIC_LOAD_XOR_I32 : PseudoInst<
4134 (outs GPR:$dst), (ins GPR:$ptr, GPR:$incr), NoItinerary,
4135 [(set GPR:$dst, (atomic_load_xor_32 GPR:$ptr, GPR:$incr))]>;
4136 def ATOMIC_LOAD_NAND_I32 : PseudoInst<
4137 (outs GPR:$dst), (ins GPR:$ptr, GPR:$incr), NoItinerary,
4138 [(set GPR:$dst, (atomic_load_nand_32 GPR:$ptr, GPR:$incr))]>;
4139 def ATOMIC_LOAD_MIN_I32 : PseudoInst<
4140 (outs GPR:$dst), (ins GPR:$ptr, GPR:$val), NoItinerary,
4141 [(set GPR:$dst, (atomic_load_min_32 GPR:$ptr, GPR:$val))]>;
4142 def ATOMIC_LOAD_MAX_I32 : PseudoInst<
4143 (outs GPR:$dst), (ins GPR:$ptr, GPR:$val), NoItinerary,
4144 [(set GPR:$dst, (atomic_load_max_32 GPR:$ptr, GPR:$val))]>;
4145 def ATOMIC_LOAD_UMIN_I32 : PseudoInst<
4146 (outs GPR:$dst), (ins GPR:$ptr, GPR:$val), NoItinerary,
4147 [(set GPR:$dst, (atomic_load_min_32 GPR:$ptr, GPR:$val))]>;
4148 def ATOMIC_LOAD_UMAX_I32 : PseudoInst<
4149 (outs GPR:$dst), (ins GPR:$ptr, GPR:$val), NoItinerary,
4150 [(set GPR:$dst, (atomic_load_max_32 GPR:$ptr, GPR:$val))]>;
4152 def ATOMIC_SWAP_I8 : PseudoInst<
4153 (outs GPR:$dst), (ins GPR:$ptr, GPR:$new), NoItinerary,
4154 [(set GPR:$dst, (atomic_swap_8 GPR:$ptr, GPR:$new))]>;
4155 def ATOMIC_SWAP_I16 : PseudoInst<
4156 (outs GPR:$dst), (ins GPR:$ptr, GPR:$new), NoItinerary,
4157 [(set GPR:$dst, (atomic_swap_16 GPR:$ptr, GPR:$new))]>;
4158 def ATOMIC_SWAP_I32 : PseudoInst<
4159 (outs GPR:$dst), (ins GPR:$ptr, GPR:$new), NoItinerary,
4160 [(set GPR:$dst, (atomic_swap_32 GPR:$ptr, GPR:$new))]>;
4162 def ATOMIC_CMP_SWAP_I8 : PseudoInst<
4163 (outs GPR:$dst), (ins GPR:$ptr, GPR:$old, GPR:$new), NoItinerary,
4164 [(set GPR:$dst, (atomic_cmp_swap_8 GPR:$ptr, GPR:$old, GPR:$new))]>;
4165 def ATOMIC_CMP_SWAP_I16 : PseudoInst<
4166 (outs GPR:$dst), (ins GPR:$ptr, GPR:$old, GPR:$new), NoItinerary,
4167 [(set GPR:$dst, (atomic_cmp_swap_16 GPR:$ptr, GPR:$old, GPR:$new))]>;
4168 def ATOMIC_CMP_SWAP_I32 : PseudoInst<
4169 (outs GPR:$dst), (ins GPR:$ptr, GPR:$old, GPR:$new), NoItinerary,
4170 [(set GPR:$dst, (atomic_cmp_swap_32 GPR:$ptr, GPR:$old, GPR:$new))]>;
4174 let mayLoad = 1 in {
4175 def LDREXB : AIldrex<0b10, (outs GPR:$Rt), (ins addr_offset_none:$addr),
4177 "ldrexb", "\t$Rt, $addr", []>;
4178 def LDREXH : AIldrex<0b11, (outs GPR:$Rt), (ins addr_offset_none:$addr),
4179 NoItinerary, "ldrexh", "\t$Rt, $addr", []>;
4180 def LDREX : AIldrex<0b00, (outs GPR:$Rt), (ins addr_offset_none:$addr),
4181 NoItinerary, "ldrex", "\t$Rt, $addr", []>;
4182 let hasExtraDefRegAllocReq = 1 in
4183 def LDREXD: AIldrex<0b01, (outs GPR:$Rt, GPR:$Rt2),(ins addr_offset_none:$addr),
4184 NoItinerary, "ldrexd", "\t$Rt, $Rt2, $addr", []> {
4185 let DecoderMethod = "DecodeDoubleRegLoad";
4189 let mayStore = 1, Constraints = "@earlyclobber $Rd" in {
4190 def STREXB: AIstrex<0b10, (outs GPR:$Rd), (ins GPR:$Rt, addr_offset_none:$addr),
4191 NoItinerary, "strexb", "\t$Rd, $Rt, $addr", []>;
4192 def STREXH: AIstrex<0b11, (outs GPR:$Rd), (ins GPR:$Rt, addr_offset_none:$addr),
4193 NoItinerary, "strexh", "\t$Rd, $Rt, $addr", []>;
4194 def STREX : AIstrex<0b00, (outs GPR:$Rd), (ins GPR:$Rt, addr_offset_none:$addr),
4195 NoItinerary, "strex", "\t$Rd, $Rt, $addr", []>;
4198 let hasExtraSrcRegAllocReq = 1, Constraints = "@earlyclobber $Rd" in
4199 def STREXD : AIstrex<0b01, (outs GPR:$Rd),
4200 (ins GPR:$Rt, GPR:$Rt2, addr_offset_none:$addr),
4201 NoItinerary, "strexd", "\t$Rd, $Rt, $Rt2, $addr", []> {
4202 let DecoderMethod = "DecodeDoubleRegStore";
4205 def CLREX : AXI<(outs), (ins), MiscFrm, NoItinerary, "clrex", []>,
4206 Requires<[IsARM, HasV7]> {
4207 let Inst{31-0} = 0b11110101011111111111000000011111;
4210 // SWP/SWPB are deprecated in V6/V7.
4211 let mayLoad = 1, mayStore = 1 in {
4212 def SWP : AIswp<0, (outs GPR:$Rt), (ins GPR:$Rt2, addr_offset_none:$addr),
4214 def SWPB: AIswp<1, (outs GPR:$Rt), (ins GPR:$Rt2, addr_offset_none:$addr),
4218 //===----------------------------------------------------------------------===//
4219 // Coprocessor Instructions.
4222 def CDP : ABI<0b1110, (outs), (ins p_imm:$cop, imm0_15:$opc1,
4223 c_imm:$CRd, c_imm:$CRn, c_imm:$CRm, imm0_7:$opc2),
4224 NoItinerary, "cdp", "\t$cop, $opc1, $CRd, $CRn, $CRm, $opc2",
4225 [(int_arm_cdp imm:$cop, imm:$opc1, imm:$CRd, imm:$CRn,
4226 imm:$CRm, imm:$opc2)]> {
4234 let Inst{3-0} = CRm;
4236 let Inst{7-5} = opc2;
4237 let Inst{11-8} = cop;
4238 let Inst{15-12} = CRd;
4239 let Inst{19-16} = CRn;
4240 let Inst{23-20} = opc1;
4243 def CDP2 : ABXI<0b1110, (outs), (ins p_imm:$cop, imm0_15:$opc1,
4244 c_imm:$CRd, c_imm:$CRn, c_imm:$CRm, imm0_7:$opc2),
4245 NoItinerary, "cdp2\t$cop, $opc1, $CRd, $CRn, $CRm, $opc2",
4246 [(int_arm_cdp2 imm:$cop, imm:$opc1, imm:$CRd, imm:$CRn,
4247 imm:$CRm, imm:$opc2)]> {
4248 let Inst{31-28} = 0b1111;
4256 let Inst{3-0} = CRm;
4258 let Inst{7-5} = opc2;
4259 let Inst{11-8} = cop;
4260 let Inst{15-12} = CRd;
4261 let Inst{19-16} = CRn;
4262 let Inst{23-20} = opc1;
4265 class ACI<dag oops, dag iops, string opc, string asm,
4266 IndexMode im = IndexModeNone>
4267 : I<oops, iops, AddrModeNone, 4, im, BrFrm, NoItinerary,
4269 let Inst{27-25} = 0b110;
4271 class ACInoP<dag oops, dag iops, string opc, string asm,
4272 IndexMode im = IndexModeNone>
4273 : InoP<oops, iops, AddrModeNone, 4, im, BrFrm, NoItinerary,
4275 let Inst{31-28} = 0b1111;
4276 let Inst{27-25} = 0b110;
4278 multiclass LdStCop<bit load, bit Dbit, string asm> {
4279 def _OFFSET : ACI<(outs), (ins p_imm:$cop, c_imm:$CRd, addrmode5:$addr),
4280 asm, "\t$cop, $CRd, $addr"> {
4284 let Inst{24} = 1; // P = 1
4285 let Inst{23} = addr{8};
4286 let Inst{22} = Dbit;
4287 let Inst{21} = 0; // W = 0
4288 let Inst{20} = load;
4289 let Inst{19-16} = addr{12-9};
4290 let Inst{15-12} = CRd;
4291 let Inst{11-8} = cop;
4292 let Inst{7-0} = addr{7-0};
4293 let DecoderMethod = "DecodeCopMemInstruction";
4295 def _PRE : ACI<(outs), (ins p_imm:$cop, c_imm:$CRd, addrmode5:$addr),
4296 asm, "\t$cop, $CRd, $addr!", IndexModePre> {
4300 let Inst{24} = 1; // P = 1
4301 let Inst{23} = addr{8};
4302 let Inst{22} = Dbit;
4303 let Inst{21} = 1; // W = 1
4304 let Inst{20} = load;
4305 let Inst{19-16} = addr{12-9};
4306 let Inst{15-12} = CRd;
4307 let Inst{11-8} = cop;
4308 let Inst{7-0} = addr{7-0};
4309 let DecoderMethod = "DecodeCopMemInstruction";
4311 def _POST: ACI<(outs), (ins p_imm:$cop, c_imm:$CRd, addr_offset_none:$addr,
4312 postidx_imm8s4:$offset),
4313 asm, "\t$cop, $CRd, $addr, $offset", IndexModePost> {
4318 let Inst{24} = 0; // P = 0
4319 let Inst{23} = offset{8};
4320 let Inst{22} = Dbit;
4321 let Inst{21} = 1; // W = 1
4322 let Inst{20} = load;
4323 let Inst{19-16} = addr;
4324 let Inst{15-12} = CRd;
4325 let Inst{11-8} = cop;
4326 let Inst{7-0} = offset{7-0};
4327 let DecoderMethod = "DecodeCopMemInstruction";
4329 def _OPTION : ACI<(outs),
4330 (ins p_imm:$cop, c_imm:$CRd, addr_offset_none:$addr,
4331 coproc_option_imm:$option),
4332 asm, "\t$cop, $CRd, $addr, $option"> {
4337 let Inst{24} = 0; // P = 0
4338 let Inst{23} = 1; // U = 1
4339 let Inst{22} = Dbit;
4340 let Inst{21} = 0; // W = 0
4341 let Inst{20} = load;
4342 let Inst{19-16} = addr;
4343 let Inst{15-12} = CRd;
4344 let Inst{11-8} = cop;
4345 let Inst{7-0} = option;
4346 let DecoderMethod = "DecodeCopMemInstruction";
4349 multiclass LdSt2Cop<bit load, bit Dbit, string asm> {
4350 def _OFFSET : ACInoP<(outs), (ins p_imm:$cop, c_imm:$CRd, addrmode5:$addr),
4351 asm, "\t$cop, $CRd, $addr"> {
4355 let Inst{24} = 1; // P = 1
4356 let Inst{23} = addr{8};
4357 let Inst{22} = Dbit;
4358 let Inst{21} = 0; // W = 0
4359 let Inst{20} = load;
4360 let Inst{19-16} = addr{12-9};
4361 let Inst{15-12} = CRd;
4362 let Inst{11-8} = cop;
4363 let Inst{7-0} = addr{7-0};
4364 let DecoderMethod = "DecodeCopMemInstruction";
4366 def _PRE : ACInoP<(outs), (ins p_imm:$cop, c_imm:$CRd, addrmode5:$addr),
4367 asm, "\t$cop, $CRd, $addr!", IndexModePre> {
4371 let Inst{24} = 1; // P = 1
4372 let Inst{23} = addr{8};
4373 let Inst{22} = Dbit;
4374 let Inst{21} = 1; // W = 1
4375 let Inst{20} = load;
4376 let Inst{19-16} = addr{12-9};
4377 let Inst{15-12} = CRd;
4378 let Inst{11-8} = cop;
4379 let Inst{7-0} = addr{7-0};
4380 let DecoderMethod = "DecodeCopMemInstruction";
4382 def _POST: ACInoP<(outs), (ins p_imm:$cop, c_imm:$CRd, addr_offset_none:$addr,
4383 postidx_imm8s4:$offset),
4384 asm, "\t$cop, $CRd, $addr, $offset", IndexModePost> {
4389 let Inst{24} = 0; // P = 0
4390 let Inst{23} = offset{8};
4391 let Inst{22} = Dbit;
4392 let Inst{21} = 1; // W = 1
4393 let Inst{20} = load;
4394 let Inst{19-16} = addr;
4395 let Inst{15-12} = CRd;
4396 let Inst{11-8} = cop;
4397 let Inst{7-0} = offset{7-0};
4398 let DecoderMethod = "DecodeCopMemInstruction";
4400 def _OPTION : ACInoP<(outs),
4401 (ins p_imm:$cop, c_imm:$CRd, addr_offset_none:$addr,
4402 coproc_option_imm:$option),
4403 asm, "\t$cop, $CRd, $addr, $option"> {
4408 let Inst{24} = 0; // P = 0
4409 let Inst{23} = 1; // U = 1
4410 let Inst{22} = Dbit;
4411 let Inst{21} = 0; // W = 0
4412 let Inst{20} = load;
4413 let Inst{19-16} = addr;
4414 let Inst{15-12} = CRd;
4415 let Inst{11-8} = cop;
4416 let Inst{7-0} = option;
4417 let DecoderMethod = "DecodeCopMemInstruction";
4421 defm LDC : LdStCop <1, 0, "ldc">;
4422 defm LDCL : LdStCop <1, 1, "ldcl">;
4423 defm STC : LdStCop <0, 0, "stc">;
4424 defm STCL : LdStCop <0, 1, "stcl">;
4425 defm LDC2 : LdSt2Cop<1, 0, "ldc2">;
4426 defm LDC2L : LdSt2Cop<1, 1, "ldc2l">;
4427 defm STC2 : LdSt2Cop<0, 0, "stc2">;
4428 defm STC2L : LdSt2Cop<0, 1, "stc2l">;
4430 //===----------------------------------------------------------------------===//
4431 // Move between coprocessor and ARM core register.
4434 class MovRCopro<string opc, bit direction, dag oops, dag iops,
4436 : ABI<0b1110, oops, iops, NoItinerary, opc,
4437 "\t$cop, $opc1, $Rt, $CRn, $CRm, $opc2", pattern> {
4438 let Inst{20} = direction;
4448 let Inst{15-12} = Rt;
4449 let Inst{11-8} = cop;
4450 let Inst{23-21} = opc1;
4451 let Inst{7-5} = opc2;
4452 let Inst{3-0} = CRm;
4453 let Inst{19-16} = CRn;
4456 def MCR : MovRCopro<"mcr", 0 /* from ARM core register to coprocessor */,
4458 (ins p_imm:$cop, imm0_7:$opc1, GPR:$Rt, c_imm:$CRn,
4459 c_imm:$CRm, imm0_7:$opc2),
4460 [(int_arm_mcr imm:$cop, imm:$opc1, GPR:$Rt, imm:$CRn,
4461 imm:$CRm, imm:$opc2)]>;
4462 def MRC : MovRCopro<"mrc", 1 /* from coprocessor to ARM core register */,
4464 (ins p_imm:$cop, imm0_7:$opc1, c_imm:$CRn, c_imm:$CRm,
4467 def : ARMPat<(int_arm_mrc imm:$cop, imm:$opc1, imm:$CRn, imm:$CRm, imm:$opc2),
4468 (MRC imm:$cop, imm:$opc1, imm:$CRn, imm:$CRm, imm:$opc2)>;
4470 class MovRCopro2<string opc, bit direction, dag oops, dag iops,
4472 : ABXI<0b1110, oops, iops, NoItinerary,
4473 !strconcat(opc, "\t$cop, $opc1, $Rt, $CRn, $CRm, $opc2"), pattern> {
4474 let Inst{31-28} = 0b1111;
4475 let Inst{20} = direction;
4485 let Inst{15-12} = Rt;
4486 let Inst{11-8} = cop;
4487 let Inst{23-21} = opc1;
4488 let Inst{7-5} = opc2;
4489 let Inst{3-0} = CRm;
4490 let Inst{19-16} = CRn;
4493 def MCR2 : MovRCopro2<"mcr2", 0 /* from ARM core register to coprocessor */,
4495 (ins p_imm:$cop, imm0_7:$opc1, GPR:$Rt, c_imm:$CRn,
4496 c_imm:$CRm, imm0_7:$opc2),
4497 [(int_arm_mcr2 imm:$cop, imm:$opc1, GPR:$Rt, imm:$CRn,
4498 imm:$CRm, imm:$opc2)]>;
4499 def MRC2 : MovRCopro2<"mrc2", 1 /* from coprocessor to ARM core register */,
4501 (ins p_imm:$cop, imm0_7:$opc1, c_imm:$CRn, c_imm:$CRm,
4504 def : ARMV5TPat<(int_arm_mrc2 imm:$cop, imm:$opc1, imm:$CRn,
4505 imm:$CRm, imm:$opc2),
4506 (MRC2 imm:$cop, imm:$opc1, imm:$CRn, imm:$CRm, imm:$opc2)>;
4508 class MovRRCopro<string opc, bit direction, list<dag> pattern = []>
4509 : ABI<0b1100, (outs), (ins p_imm:$cop, imm0_15:$opc1,
4510 GPR:$Rt, GPR:$Rt2, c_imm:$CRm),
4511 NoItinerary, opc, "\t$cop, $opc1, $Rt, $Rt2, $CRm", pattern> {
4512 let Inst{23-21} = 0b010;
4513 let Inst{20} = direction;
4521 let Inst{15-12} = Rt;
4522 let Inst{19-16} = Rt2;
4523 let Inst{11-8} = cop;
4524 let Inst{7-4} = opc1;
4525 let Inst{3-0} = CRm;
4528 def MCRR : MovRRCopro<"mcrr", 0 /* from ARM core register to coprocessor */,
4529 [(int_arm_mcrr imm:$cop, imm:$opc1, GPR:$Rt, GPR:$Rt2,
4531 def MRRC : MovRRCopro<"mrrc", 1 /* from coprocessor to ARM core register */>;
4533 class MovRRCopro2<string opc, bit direction, list<dag> pattern = []>
4534 : ABXI<0b1100, (outs), (ins p_imm:$cop, imm0_15:$opc1,
4535 GPR:$Rt, GPR:$Rt2, c_imm:$CRm), NoItinerary,
4536 !strconcat(opc, "\t$cop, $opc1, $Rt, $Rt2, $CRm"), pattern> {
4537 let Inst{31-28} = 0b1111;
4538 let Inst{23-21} = 0b010;
4539 let Inst{20} = direction;
4547 let Inst{15-12} = Rt;
4548 let Inst{19-16} = Rt2;
4549 let Inst{11-8} = cop;
4550 let Inst{7-4} = opc1;
4551 let Inst{3-0} = CRm;
4554 def MCRR2 : MovRRCopro2<"mcrr2", 0 /* from ARM core register to coprocessor */,
4555 [(int_arm_mcrr2 imm:$cop, imm:$opc1, GPR:$Rt, GPR:$Rt2,
4557 def MRRC2 : MovRRCopro2<"mrrc2", 1 /* from coprocessor to ARM core register */>;
4559 //===----------------------------------------------------------------------===//
4560 // Move between special register and ARM core register
4563 // Move to ARM core register from Special Register
4564 def MRS : ABI<0b0001, (outs GPR:$Rd), (ins), NoItinerary,
4565 "mrs", "\t$Rd, apsr", []> {
4567 let Inst{23-16} = 0b00001111;
4568 let Inst{15-12} = Rd;
4569 let Inst{7-4} = 0b0000;
4572 def : InstAlias<"mrs${p} $Rd, cpsr", (MRS GPR:$Rd, pred:$p)>, Requires<[IsARM]>;
4574 def MRSsys : ABI<0b0001, (outs GPR:$Rd), (ins), NoItinerary,
4575 "mrs", "\t$Rd, spsr", []> {
4577 let Inst{23-16} = 0b01001111;
4578 let Inst{15-12} = Rd;
4579 let Inst{7-4} = 0b0000;
4582 // Move from ARM core register to Special Register
4584 // No need to have both system and application versions, the encodings are the
4585 // same and the assembly parser has no way to distinguish between them. The mask
4586 // operand contains the special register (R Bit) in bit 4 and bits 3-0 contains
4587 // the mask with the fields to be accessed in the special register.
4588 def MSR : ABI<0b0001, (outs), (ins msr_mask:$mask, GPR:$Rn), NoItinerary,
4589 "msr", "\t$mask, $Rn", []> {
4594 let Inst{22} = mask{4}; // R bit
4595 let Inst{21-20} = 0b10;
4596 let Inst{19-16} = mask{3-0};
4597 let Inst{15-12} = 0b1111;
4598 let Inst{11-4} = 0b00000000;
4602 def MSRi : ABI<0b0011, (outs), (ins msr_mask:$mask, so_imm:$a), NoItinerary,
4603 "msr", "\t$mask, $a", []> {
4608 let Inst{22} = mask{4}; // R bit
4609 let Inst{21-20} = 0b10;
4610 let Inst{19-16} = mask{3-0};
4611 let Inst{15-12} = 0b1111;
4615 //===----------------------------------------------------------------------===//
4619 // __aeabi_read_tp preserves the registers r1-r3.
4620 // This is a pseudo inst so that we can get the encoding right,
4621 // complete with fixup for the aeabi_read_tp function.
4623 Defs = [R0, R12, LR, CPSR], Uses = [SP] in {
4624 def TPsoft : PseudoInst<(outs), (ins), IIC_Br,
4625 [(set R0, ARMthread_pointer)]>;
4628 //===----------------------------------------------------------------------===//
4629 // SJLJ Exception handling intrinsics
4630 // eh_sjlj_setjmp() is an instruction sequence to store the return
4631 // address and save #0 in R0 for the non-longjmp case.
4632 // Since by its nature we may be coming from some other function to get
4633 // here, and we're using the stack frame for the containing function to
4634 // save/restore registers, we can't keep anything live in regs across
4635 // the eh_sjlj_setjmp(), else it will almost certainly have been tromped upon
4636 // when we get here from a longjmp(). We force everything out of registers
4637 // except for our own input by listing the relevant registers in Defs. By
4638 // doing so, we also cause the prologue/epilogue code to actively preserve
4639 // all of the callee-saved resgisters, which is exactly what we want.
4640 // A constant value is passed in $val, and we use the location as a scratch.
4642 // These are pseudo-instructions and are lowered to individual MC-insts, so
4643 // no encoding information is necessary.
4645 [ R0, R1, R2, R3, R4, R5, R6, R7, R8, R9, R10, R11, R12, LR, CPSR,
4646 QQQQ0, QQQQ1, QQQQ2, QQQQ3 ], hasSideEffects = 1, isBarrier = 1,
4647 usesCustomInserter = 1 in {
4648 def Int_eh_sjlj_setjmp : PseudoInst<(outs), (ins GPR:$src, GPR:$val),
4650 [(set R0, (ARMeh_sjlj_setjmp GPR:$src, GPR:$val))]>,
4651 Requires<[IsARM, HasVFP2]>;
4655 [ R0, R1, R2, R3, R4, R5, R6, R7, R8, R9, R10, R11, R12, LR, CPSR ],
4656 hasSideEffects = 1, isBarrier = 1 in {
4657 def Int_eh_sjlj_setjmp_nofp : PseudoInst<(outs), (ins GPR:$src, GPR:$val),
4659 [(set R0, (ARMeh_sjlj_setjmp GPR:$src, GPR:$val))]>,
4660 Requires<[IsARM, NoVFP]>;
4663 // FIXME: Non-Darwin version(s)
4664 let isBarrier = 1, hasSideEffects = 1, isTerminator = 1,
4665 Defs = [ R7, LR, SP ] in {
4666 def Int_eh_sjlj_longjmp : PseudoInst<(outs), (ins GPR:$src, GPR:$scratch),
4668 [(ARMeh_sjlj_longjmp GPR:$src, GPR:$scratch)]>,
4669 Requires<[IsARM, IsDarwin]>;
4672 // eh.sjlj.dispatchsetup pseudo-instruction.
4673 // This pseudo is used for ARM, Thumb1 and Thumb2. Any differences are
4674 // handled when the pseudo is expanded (which happens before any passes
4675 // that need the instruction size).
4676 let isBarrier = 1, hasSideEffects = 1 in
4677 def Int_eh_sjlj_dispatchsetup :
4678 PseudoInst<(outs), (ins GPR:$src), NoItinerary,
4679 [(ARMeh_sjlj_dispatchsetup GPR:$src)]>,
4680 Requires<[IsDarwin]>;
4682 //===----------------------------------------------------------------------===//
4683 // Non-Instruction Patterns
4686 // ARMv4 indirect branch using (MOVr PC, dst)
4687 let isBranch = 1, isTerminator = 1, isBarrier = 1, isIndirectBranch = 1 in
4688 def MOVPCRX : ARMPseudoExpand<(outs), (ins GPR:$dst),
4689 4, IIC_Br, [(brind GPR:$dst)],
4690 (MOVr PC, GPR:$dst, (ops 14, zero_reg), zero_reg)>,
4691 Requires<[IsARM, NoV4T]>;
4693 // Large immediate handling.
4695 // 32-bit immediate using two piece so_imms or movw + movt.
4696 // This is a single pseudo instruction, the benefit is that it can be remat'd
4697 // as a single unit instead of having to handle reg inputs.
4698 // FIXME: Remove this when we can do generalized remat.
4699 let isReMaterializable = 1, isMoveImm = 1 in
4700 def MOVi32imm : PseudoInst<(outs GPR:$dst), (ins i32imm:$src), IIC_iMOVix2,
4701 [(set GPR:$dst, (arm_i32imm:$src))]>,
4704 // Pseudo instruction that combines movw + movt + add pc (if PIC).
4705 // It also makes it possible to rematerialize the instructions.
4706 // FIXME: Remove this when we can do generalized remat and when machine licm
4707 // can properly the instructions.
4708 let isReMaterializable = 1 in {
4709 def MOV_ga_pcrel : PseudoInst<(outs GPR:$dst), (ins i32imm:$addr),
4711 [(set GPR:$dst, (ARMWrapperPIC tglobaladdr:$addr))]>,
4712 Requires<[IsARM, UseMovt]>;
4714 def MOV_ga_dyn : PseudoInst<(outs GPR:$dst), (ins i32imm:$addr),
4716 [(set GPR:$dst, (ARMWrapperDYN tglobaladdr:$addr))]>,
4717 Requires<[IsARM, UseMovt]>;
4719 let AddedComplexity = 10 in
4720 def MOV_ga_pcrel_ldr : PseudoInst<(outs GPR:$dst), (ins i32imm:$addr),
4722 [(set GPR:$dst, (load (ARMWrapperPIC tglobaladdr:$addr)))]>,
4723 Requires<[IsARM, UseMovt]>;
4724 } // isReMaterializable
4726 // ConstantPool, GlobalAddress, and JumpTable
4727 def : ARMPat<(ARMWrapper tglobaladdr :$dst), (LEApcrel tglobaladdr :$dst)>,
4728 Requires<[IsARM, DontUseMovt]>;
4729 def : ARMPat<(ARMWrapper tconstpool :$dst), (LEApcrel tconstpool :$dst)>;
4730 def : ARMPat<(ARMWrapper tglobaladdr :$dst), (MOVi32imm tglobaladdr :$dst)>,
4731 Requires<[IsARM, UseMovt]>;
4732 def : ARMPat<(ARMWrapperJT tjumptable:$dst, imm:$id),
4733 (LEApcrelJT tjumptable:$dst, imm:$id)>;
4735 // TODO: add,sub,and, 3-instr forms?
4738 def : ARMPat<(ARMtcret tcGPR:$dst),
4739 (TCRETURNri tcGPR:$dst)>, Requires<[IsDarwin]>;
4741 def : ARMPat<(ARMtcret (i32 tglobaladdr:$dst)),
4742 (TCRETURNdi texternalsym:$dst)>, Requires<[IsDarwin]>;
4744 def : ARMPat<(ARMtcret (i32 texternalsym:$dst)),
4745 (TCRETURNdi texternalsym:$dst)>, Requires<[IsDarwin]>;
4747 def : ARMPat<(ARMtcret tcGPR:$dst),
4748 (TCRETURNriND tcGPR:$dst)>, Requires<[IsNotDarwin]>;
4750 def : ARMPat<(ARMtcret (i32 tglobaladdr:$dst)),
4751 (TCRETURNdiND texternalsym:$dst)>, Requires<[IsNotDarwin]>;
4753 def : ARMPat<(ARMtcret (i32 texternalsym:$dst)),
4754 (TCRETURNdiND texternalsym:$dst)>, Requires<[IsNotDarwin]>;
4757 def : ARMPat<(ARMcall texternalsym:$func), (BL texternalsym:$func)>,
4758 Requires<[IsARM, IsNotDarwin]>;
4759 def : ARMPat<(ARMcall texternalsym:$func), (BLr9 texternalsym:$func)>,
4760 Requires<[IsARM, IsDarwin]>;
4762 // zextload i1 -> zextload i8
4763 def : ARMPat<(zextloadi1 addrmode_imm12:$addr), (LDRBi12 addrmode_imm12:$addr)>;
4764 def : ARMPat<(zextloadi1 ldst_so_reg:$addr), (LDRBrs ldst_so_reg:$addr)>;
4766 // extload -> zextload
4767 def : ARMPat<(extloadi1 addrmode_imm12:$addr), (LDRBi12 addrmode_imm12:$addr)>;
4768 def : ARMPat<(extloadi1 ldst_so_reg:$addr), (LDRBrs ldst_so_reg:$addr)>;
4769 def : ARMPat<(extloadi8 addrmode_imm12:$addr), (LDRBi12 addrmode_imm12:$addr)>;
4770 def : ARMPat<(extloadi8 ldst_so_reg:$addr), (LDRBrs ldst_so_reg:$addr)>;
4772 def : ARMPat<(extloadi16 addrmode3:$addr), (LDRH addrmode3:$addr)>;
4774 def : ARMPat<(extloadi8 addrmodepc:$addr), (PICLDRB addrmodepc:$addr)>;
4775 def : ARMPat<(extloadi16 addrmodepc:$addr), (PICLDRH addrmodepc:$addr)>;
4778 def : ARMV5TEPat<(mul (sra (shl GPR:$a, (i32 16)), (i32 16)),
4779 (sra (shl GPR:$b, (i32 16)), (i32 16))),
4780 (SMULBB GPR:$a, GPR:$b)>;
4781 def : ARMV5TEPat<(mul sext_16_node:$a, sext_16_node:$b),
4782 (SMULBB GPR:$a, GPR:$b)>;
4783 def : ARMV5TEPat<(mul (sra (shl GPR:$a, (i32 16)), (i32 16)),
4784 (sra GPR:$b, (i32 16))),
4785 (SMULBT GPR:$a, GPR:$b)>;
4786 def : ARMV5TEPat<(mul sext_16_node:$a, (sra GPR:$b, (i32 16))),
4787 (SMULBT GPR:$a, GPR:$b)>;
4788 def : ARMV5TEPat<(mul (sra GPR:$a, (i32 16)),
4789 (sra (shl GPR:$b, (i32 16)), (i32 16))),
4790 (SMULTB GPR:$a, GPR:$b)>;
4791 def : ARMV5TEPat<(mul (sra GPR:$a, (i32 16)), sext_16_node:$b),
4792 (SMULTB GPR:$a, GPR:$b)>;
4793 def : ARMV5TEPat<(sra (mul GPR:$a, (sra (shl GPR:$b, (i32 16)), (i32 16))),
4795 (SMULWB GPR:$a, GPR:$b)>;
4796 def : ARMV5TEPat<(sra (mul GPR:$a, sext_16_node:$b), (i32 16)),
4797 (SMULWB GPR:$a, GPR:$b)>;
4799 def : ARMV5TEPat<(add GPR:$acc,
4800 (mul (sra (shl GPR:$a, (i32 16)), (i32 16)),
4801 (sra (shl GPR:$b, (i32 16)), (i32 16)))),
4802 (SMLABB GPR:$a, GPR:$b, GPR:$acc)>;
4803 def : ARMV5TEPat<(add GPR:$acc,
4804 (mul sext_16_node:$a, sext_16_node:$b)),
4805 (SMLABB GPR:$a, GPR:$b, GPR:$acc)>;
4806 def : ARMV5TEPat<(add GPR:$acc,
4807 (mul (sra (shl GPR:$a, (i32 16)), (i32 16)),
4808 (sra GPR:$b, (i32 16)))),
4809 (SMLABT GPR:$a, GPR:$b, GPR:$acc)>;
4810 def : ARMV5TEPat<(add GPR:$acc,
4811 (mul sext_16_node:$a, (sra GPR:$b, (i32 16)))),
4812 (SMLABT GPR:$a, GPR:$b, GPR:$acc)>;
4813 def : ARMV5TEPat<(add GPR:$acc,
4814 (mul (sra GPR:$a, (i32 16)),
4815 (sra (shl GPR:$b, (i32 16)), (i32 16)))),
4816 (SMLATB GPR:$a, GPR:$b, GPR:$acc)>;
4817 def : ARMV5TEPat<(add GPR:$acc,
4818 (mul (sra GPR:$a, (i32 16)), sext_16_node:$b)),
4819 (SMLATB GPR:$a, GPR:$b, GPR:$acc)>;
4820 def : ARMV5TEPat<(add GPR:$acc,
4821 (sra (mul GPR:$a, (sra (shl GPR:$b, (i32 16)), (i32 16))),
4823 (SMLAWB GPR:$a, GPR:$b, GPR:$acc)>;
4824 def : ARMV5TEPat<(add GPR:$acc,
4825 (sra (mul GPR:$a, sext_16_node:$b), (i32 16))),
4826 (SMLAWB GPR:$a, GPR:$b, GPR:$acc)>;
4829 // Pre-v7 uses MCR for synchronization barriers.
4830 def : ARMPat<(ARMMemBarrierMCR GPR:$zero), (MCR 15, 0, GPR:$zero, 7, 10, 5)>,
4831 Requires<[IsARM, HasV6]>;
4833 // SXT/UXT with no rotate
4834 let AddedComplexity = 16 in {
4835 def : ARMV6Pat<(and GPR:$Src, 0x000000FF), (UXTB GPR:$Src, 0)>;
4836 def : ARMV6Pat<(and GPR:$Src, 0x0000FFFF), (UXTH GPR:$Src, 0)>;
4837 def : ARMV6Pat<(and GPR:$Src, 0x00FF00FF), (UXTB16 GPR:$Src, 0)>;
4838 def : ARMV6Pat<(add GPR:$Rn, (and GPR:$Rm, 0x00FF)),
4839 (UXTAB GPR:$Rn, GPR:$Rm, 0)>;
4840 def : ARMV6Pat<(add GPR:$Rn, (and GPR:$Rm, 0xFFFF)),
4841 (UXTAH GPR:$Rn, GPR:$Rm, 0)>;
4844 def : ARMV6Pat<(sext_inreg GPR:$Src, i8), (SXTB GPR:$Src, 0)>;
4845 def : ARMV6Pat<(sext_inreg GPR:$Src, i16), (SXTH GPR:$Src, 0)>;
4847 def : ARMV6Pat<(add GPR:$Rn, (sext_inreg GPRnopc:$Rm, i8)),
4848 (SXTAB GPR:$Rn, GPRnopc:$Rm, 0)>;
4849 def : ARMV6Pat<(add GPR:$Rn, (sext_inreg GPRnopc:$Rm, i16)),
4850 (SXTAH GPR:$Rn, GPRnopc:$Rm, 0)>;
4852 // Atomic load/store patterns
4853 def : ARMPat<(atomic_load_8 ldst_so_reg:$src),
4854 (LDRBrs ldst_so_reg:$src)>;
4855 def : ARMPat<(atomic_load_8 addrmode_imm12:$src),
4856 (LDRBi12 addrmode_imm12:$src)>;
4857 def : ARMPat<(atomic_load_16 addrmode3:$src),
4858 (LDRH addrmode3:$src)>;
4859 def : ARMPat<(atomic_load_32 ldst_so_reg:$src),
4860 (LDRrs ldst_so_reg:$src)>;
4861 def : ARMPat<(atomic_load_32 addrmode_imm12:$src),
4862 (LDRi12 addrmode_imm12:$src)>;
4863 def : ARMPat<(atomic_store_8 ldst_so_reg:$ptr, GPR:$val),
4864 (STRBrs GPR:$val, ldst_so_reg:$ptr)>;
4865 def : ARMPat<(atomic_store_8 addrmode_imm12:$ptr, GPR:$val),
4866 (STRBi12 GPR:$val, addrmode_imm12:$ptr)>;
4867 def : ARMPat<(atomic_store_16 addrmode3:$ptr, GPR:$val),
4868 (STRH GPR:$val, addrmode3:$ptr)>;
4869 def : ARMPat<(atomic_store_32 ldst_so_reg:$ptr, GPR:$val),
4870 (STRrs GPR:$val, ldst_so_reg:$ptr)>;
4871 def : ARMPat<(atomic_store_32 addrmode_imm12:$ptr, GPR:$val),
4872 (STRi12 GPR:$val, addrmode_imm12:$ptr)>;
4875 //===----------------------------------------------------------------------===//
4879 include "ARMInstrThumb.td"
4881 //===----------------------------------------------------------------------===//
4885 include "ARMInstrThumb2.td"
4887 //===----------------------------------------------------------------------===//
4888 // Floating Point Support
4891 include "ARMInstrVFP.td"
4893 //===----------------------------------------------------------------------===//
4894 // Advanced SIMD (NEON) Support
4897 include "ARMInstrNEON.td"
4899 //===----------------------------------------------------------------------===//
4900 // Assembler aliases
4904 def : InstAlias<"dmb", (DMB 0xf)>, Requires<[IsARM, HasDB]>;
4905 def : InstAlias<"dsb", (DSB 0xf)>, Requires<[IsARM, HasDB]>;
4906 def : InstAlias<"isb", (ISB 0xf)>, Requires<[IsARM, HasDB]>;
4908 // System instructions
4909 def : MnemonicAlias<"swi", "svc">;
4911 // Load / Store Multiple
4912 def : MnemonicAlias<"ldmfd", "ldm">;
4913 def : MnemonicAlias<"ldmia", "ldm">;
4914 def : MnemonicAlias<"ldmea", "ldmdb">;
4915 def : MnemonicAlias<"stmfd", "stmdb">;
4916 def : MnemonicAlias<"stmia", "stm">;
4917 def : MnemonicAlias<"stmea", "stm">;
4919 // PKHBT/PKHTB with default shift amount. PKHTB is equivalent to PKHBT when the
4920 // shift amount is zero (i.e., unspecified).
4921 def : InstAlias<"pkhbt${p} $Rd, $Rn, $Rm",
4922 (PKHBT GPRnopc:$Rd, GPRnopc:$Rn, GPRnopc:$Rm, 0, pred:$p)>,
4923 Requires<[IsARM, HasV6]>;
4924 def : InstAlias<"pkhtb${p} $Rd, $Rn, $Rm",
4925 (PKHBT GPRnopc:$Rd, GPRnopc:$Rn, GPRnopc:$Rm, 0, pred:$p)>,
4926 Requires<[IsARM, HasV6]>;
4928 // PUSH/POP aliases for STM/LDM
4929 def : ARMInstAlias<"push${p} $regs", (STMDB_UPD SP, pred:$p, reglist:$regs)>;
4930 def : ARMInstAlias<"pop${p} $regs", (LDMIA_UPD SP, pred:$p, reglist:$regs)>;
4932 // SSAT/USAT optional shift operand.
4933 def : ARMInstAlias<"ssat${p} $Rd, $sat_imm, $Rn",
4934 (SSAT GPRnopc:$Rd, imm1_32:$sat_imm, GPRnopc:$Rn, 0, pred:$p)>;
4935 def : ARMInstAlias<"usat${p} $Rd, $sat_imm, $Rn",
4936 (USAT GPRnopc:$Rd, imm0_31:$sat_imm, GPRnopc:$Rn, 0, pred:$p)>;
4939 // Extend instruction optional rotate operand.
4940 def : ARMInstAlias<"sxtab${p} $Rd, $Rn, $Rm",
4941 (SXTAB GPRnopc:$Rd, GPR:$Rn, GPRnopc:$Rm, 0, pred:$p)>;
4942 def : ARMInstAlias<"sxtah${p} $Rd, $Rn, $Rm",
4943 (SXTAH GPRnopc:$Rd, GPR:$Rn, GPRnopc:$Rm, 0, pred:$p)>;
4944 def : ARMInstAlias<"sxtab16${p} $Rd, $Rn, $Rm",
4945 (SXTAB16 GPRnopc:$Rd, GPR:$Rn, GPRnopc:$Rm, 0, pred:$p)>;
4946 def : ARMInstAlias<"sxtb${p} $Rd, $Rm",
4947 (SXTB GPRnopc:$Rd, GPRnopc:$Rm, 0, pred:$p)>;
4948 def : ARMInstAlias<"sxtb16${p} $Rd, $Rm",
4949 (SXTB16 GPRnopc:$Rd, GPRnopc:$Rm, 0, pred:$p)>;
4950 def : ARMInstAlias<"sxth${p} $Rd, $Rm",
4951 (SXTH GPRnopc:$Rd, GPRnopc:$Rm, 0, pred:$p)>;
4953 def : ARMInstAlias<"uxtab${p} $Rd, $Rn, $Rm",
4954 (UXTAB GPRnopc:$Rd, GPR:$Rn, GPRnopc:$Rm, 0, pred:$p)>;
4955 def : ARMInstAlias<"uxtah${p} $Rd, $Rn, $Rm",
4956 (UXTAH GPRnopc:$Rd, GPR:$Rn, GPRnopc:$Rm, 0, pred:$p)>;
4957 def : ARMInstAlias<"uxtab16${p} $Rd, $Rn, $Rm",
4958 (UXTAB16 GPRnopc:$Rd, GPR:$Rn, GPRnopc:$Rm, 0, pred:$p)>;
4959 def : ARMInstAlias<"uxtb${p} $Rd, $Rm",
4960 (UXTB GPRnopc:$Rd, GPRnopc:$Rm, 0, pred:$p)>;
4961 def : ARMInstAlias<"uxtb16${p} $Rd, $Rm",
4962 (UXTB16 GPRnopc:$Rd, GPRnopc:$Rm, 0, pred:$p)>;
4963 def : ARMInstAlias<"uxth${p} $Rd, $Rm",
4964 (UXTH GPRnopc:$Rd, GPRnopc:$Rm, 0, pred:$p)>;
4968 def : MnemonicAlias<"rfefa", "rfeda">;
4969 def : MnemonicAlias<"rfeea", "rfedb">;
4970 def : MnemonicAlias<"rfefd", "rfeia">;
4971 def : MnemonicAlias<"rfeed", "rfeib">;
4972 def : MnemonicAlias<"rfe", "rfeia">;
4975 def : MnemonicAlias<"srsfa", "srsda">;
4976 def : MnemonicAlias<"srsea", "srsdb">;
4977 def : MnemonicAlias<"srsfd", "srsia">;
4978 def : MnemonicAlias<"srsed", "srsib">;
4979 def : MnemonicAlias<"srs", "srsia">;
4982 def : MnemonicAlias<"qsubaddx", "qsax">;
4984 def : MnemonicAlias<"saddsubx", "sasx">;
4985 // SHASX == SHADDSUBX
4986 def : MnemonicAlias<"shaddsubx", "shasx">;
4987 // SHSAX == SHSUBADDX
4988 def : MnemonicAlias<"shsubaddx", "shsax">;
4990 def : MnemonicAlias<"ssubaddx", "ssax">;
4992 def : MnemonicAlias<"uaddsubx", "uasx">;
4993 // UHASX == UHADDSUBX
4994 def : MnemonicAlias<"uhaddsubx", "uhasx">;
4995 // UHSAX == UHSUBADDX
4996 def : MnemonicAlias<"uhsubaddx", "uhsax">;
4997 // UQASX == UQADDSUBX
4998 def : MnemonicAlias<"uqaddsubx", "uqasx">;
4999 // UQSAX == UQSUBADDX
5000 def : MnemonicAlias<"uqsubaddx", "uqsax">;
5002 def : MnemonicAlias<"usubaddx", "usax">;
5004 // "mov Rd, so_imm_not" can be handled via "mvn" in assembly, just like
5006 def : ARMInstAlias<"mov${s}${p} $Rd, $imm",
5007 (MVNi rGPR:$Rd, so_imm_not:$imm, pred:$p, cc_out:$s)>;
5009 // The shifter forms of the MOV instruction are aliased to the ASR, LSL,
5010 // LSR, ROR, and RRX instructions.
5011 // FIXME: We need C++ parser hooks to map the alias to the MOV
5012 // encoding. It seems we should be able to do that sort of thing
5013 // in tblgen, but it could get ugly.
5014 def ASRi : ARMAsmPseudo<"asr${s}${p} $Rd, $Rm, $imm",
5015 (ins GPR:$Rd, GPR:$Rm, imm0_32:$imm, pred:$p,
5017 def LSRi : ARMAsmPseudo<"lsr${s}${p} $Rd, $Rm, $imm",
5018 (ins GPR:$Rd, GPR:$Rm, imm0_32:$imm, pred:$p,
5020 def LSLi : ARMAsmPseudo<"lsl${s}${p} $Rd, $Rm, $imm",
5021 (ins GPR:$Rd, GPR:$Rm, imm0_31:$imm, pred:$p,
5023 def RORi : ARMAsmPseudo<"ror${s}${p} $Rd, $Rm, $imm",
5024 (ins GPR:$Rd, GPR:$Rm, imm0_31:$imm, pred:$p,