1 //===- ARMInstrInfo.td - Target Description for ARM Target -*- tablegen -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file describes the ARM instructions in TableGen format.
12 //===----------------------------------------------------------------------===//
14 //===----------------------------------------------------------------------===//
15 // ARM specific DAG Nodes.
19 def SDT_ARMCallSeqStart : SDCallSeqStart<[ SDTCisVT<0, i32> ]>;
20 def SDT_ARMCallSeqEnd : SDCallSeqEnd<[ SDTCisVT<0, i32>, SDTCisVT<1, i32> ]>;
22 def SDT_ARMSaveCallPC : SDTypeProfile<0, 1, []>;
24 def SDT_ARMcall : SDTypeProfile<0, -1, [SDTCisInt<0>]>;
26 def SDT_ARMCMov : SDTypeProfile<1, 3,
27 [SDTCisSameAs<0, 1>, SDTCisSameAs<0, 2>,
30 def SDT_ARMBrcond : SDTypeProfile<0, 2,
31 [SDTCisVT<0, OtherVT>, SDTCisVT<1, i32>]>;
33 def SDT_ARMBrJT : SDTypeProfile<0, 3,
34 [SDTCisPtrTy<0>, SDTCisVT<1, i32>,
37 def SDT_ARMBr2JT : SDTypeProfile<0, 4,
38 [SDTCisPtrTy<0>, SDTCisVT<1, i32>,
39 SDTCisVT<2, i32>, SDTCisVT<3, i32>]>;
41 def SDT_ARMCmp : SDTypeProfile<0, 2, [SDTCisSameAs<0, 1>]>;
43 def SDT_ARMPICAdd : SDTypeProfile<1, 2, [SDTCisSameAs<0, 1>,
44 SDTCisPtrTy<1>, SDTCisVT<2, i32>]>;
46 def SDT_ARMThreadPointer : SDTypeProfile<1, 0, [SDTCisPtrTy<0>]>;
47 def SDT_ARMEH_SJLJ_Setjmp : SDTypeProfile<1, 1, [SDTCisInt<0>, SDTCisPtrTy<1>]>;
50 def ARMWrapper : SDNode<"ARMISD::Wrapper", SDTIntUnaryOp>;
51 def ARMWrapperJT : SDNode<"ARMISD::WrapperJT", SDTIntBinOp>;
53 def ARMcallseq_start : SDNode<"ISD::CALLSEQ_START", SDT_ARMCallSeqStart,
54 [SDNPHasChain, SDNPOutFlag]>;
55 def ARMcallseq_end : SDNode<"ISD::CALLSEQ_END", SDT_ARMCallSeqEnd,
56 [SDNPHasChain, SDNPOptInFlag, SDNPOutFlag]>;
58 def ARMcall : SDNode<"ARMISD::CALL", SDT_ARMcall,
59 [SDNPHasChain, SDNPOptInFlag, SDNPOutFlag]>;
60 def ARMcall_pred : SDNode<"ARMISD::CALL_PRED", SDT_ARMcall,
61 [SDNPHasChain, SDNPOptInFlag, SDNPOutFlag]>;
62 def ARMcall_nolink : SDNode<"ARMISD::CALL_NOLINK", SDT_ARMcall,
63 [SDNPHasChain, SDNPOptInFlag, SDNPOutFlag]>;
65 def ARMretflag : SDNode<"ARMISD::RET_FLAG", SDTNone,
66 [SDNPHasChain, SDNPOptInFlag]>;
68 def ARMcmov : SDNode<"ARMISD::CMOV", SDT_ARMCMov,
70 def ARMcneg : SDNode<"ARMISD::CNEG", SDT_ARMCMov,
73 def ARMbrcond : SDNode<"ARMISD::BRCOND", SDT_ARMBrcond,
74 [SDNPHasChain, SDNPInFlag, SDNPOutFlag]>;
76 def ARMbrjt : SDNode<"ARMISD::BR_JT", SDT_ARMBrJT,
78 def ARMbr2jt : SDNode<"ARMISD::BR2_JT", SDT_ARMBr2JT,
81 def ARMcmp : SDNode<"ARMISD::CMP", SDT_ARMCmp,
84 def ARMcmpZ : SDNode<"ARMISD::CMPZ", SDT_ARMCmp,
85 [SDNPOutFlag,SDNPCommutative]>;
87 def ARMpic_add : SDNode<"ARMISD::PIC_ADD", SDT_ARMPICAdd>;
89 def ARMsrl_flag : SDNode<"ARMISD::SRL_FLAG", SDTIntUnaryOp, [SDNPOutFlag]>;
90 def ARMsra_flag : SDNode<"ARMISD::SRA_FLAG", SDTIntUnaryOp, [SDNPOutFlag]>;
91 def ARMrrx : SDNode<"ARMISD::RRX" , SDTIntUnaryOp, [SDNPInFlag ]>;
93 def ARMthread_pointer: SDNode<"ARMISD::THREAD_POINTER", SDT_ARMThreadPointer>;
94 def ARMeh_sjlj_setjmp: SDNode<"ARMISD::EH_SJLJ_SETJMP", SDT_ARMEH_SJLJ_Setjmp>;
96 //===----------------------------------------------------------------------===//
97 // ARM Instruction Predicate Definitions.
99 def HasV5T : Predicate<"Subtarget->hasV5TOps()">;
100 def HasV5TE : Predicate<"Subtarget->hasV5TEOps()">;
101 def HasV6 : Predicate<"Subtarget->hasV6Ops()">;
102 def HasV6T2 : Predicate<"Subtarget->hasV6T2Ops()">;
103 def NoV6T2 : Predicate<"!Subtarget->hasV6T2Ops()">;
104 def HasV7 : Predicate<"Subtarget->hasV7Ops()">;
105 def HasVFP2 : Predicate<"Subtarget->hasVFP2()">;
106 def HasVFP3 : Predicate<"Subtarget->hasVFP3()">;
107 def HasNEON : Predicate<"Subtarget->hasNEON()">;
108 def UseNEONForFP : Predicate<"Subtarget->useNEONForSinglePrecisionFP()">;
109 def DontUseNEONForFP : Predicate<"!Subtarget->useNEONForSinglePrecisionFP()">;
110 def IsThumb : Predicate<"Subtarget->isThumb()">;
111 def IsThumb1Only : Predicate<"Subtarget->isThumb1Only()">;
112 def IsThumb2 : Predicate<"Subtarget->isThumb2()">;
113 def IsARM : Predicate<"!Subtarget->isThumb()">;
114 def IsDarwin : Predicate<"Subtarget->isTargetDarwin()">;
115 def IsNotDarwin : Predicate<"!Subtarget->isTargetDarwin()">;
116 def CarryDefIsUnused : Predicate<"!N.getNode()->hasAnyUseOfValue(1)">;
117 def CarryDefIsUsed : Predicate<"N.getNode()->hasAnyUseOfValue(1)">;
119 //===----------------------------------------------------------------------===//
120 // ARM Flag Definitions.
122 class RegConstraint<string C> {
123 string Constraints = C;
126 //===----------------------------------------------------------------------===//
127 // ARM specific transformation functions and pattern fragments.
130 // so_imm_neg_XFORM - Return a so_imm value packed into the format described for
131 // so_imm_neg def below.
132 def so_imm_neg_XFORM : SDNodeXForm<imm, [{
133 return CurDAG->getTargetConstant(-(int)N->getZExtValue(), MVT::i32);
136 // so_imm_not_XFORM - Return a so_imm value packed into the format described for
137 // so_imm_not def below.
138 def so_imm_not_XFORM : SDNodeXForm<imm, [{
139 return CurDAG->getTargetConstant(~(int)N->getZExtValue(), MVT::i32);
142 // rot_imm predicate - True if the 32-bit immediate is equal to 8, 16, or 24.
143 def rot_imm : PatLeaf<(i32 imm), [{
144 int32_t v = (int32_t)N->getZExtValue();
145 return v == 8 || v == 16 || v == 24;
148 /// imm1_15 predicate - True if the 32-bit immediate is in the range [1,15].
149 def imm1_15 : PatLeaf<(i32 imm), [{
150 return (int32_t)N->getZExtValue() >= 1 && (int32_t)N->getZExtValue() < 16;
153 /// imm16_31 predicate - True if the 32-bit immediate is in the range [16,31].
154 def imm16_31 : PatLeaf<(i32 imm), [{
155 return (int32_t)N->getZExtValue() >= 16 && (int32_t)N->getZExtValue() < 32;
160 return ARM_AM::getSOImmVal(-(int)N->getZExtValue()) != -1;
161 }], so_imm_neg_XFORM>;
165 return ARM_AM::getSOImmVal(~(int)N->getZExtValue()) != -1;
166 }], so_imm_not_XFORM>;
168 // sext_16_node predicate - True if the SDNode is sign-extended 16 or more bits.
169 def sext_16_node : PatLeaf<(i32 GPR:$a), [{
170 return CurDAG->ComputeNumSignBits(SDValue(N,0)) >= 17;
173 /// bf_inv_mask_imm predicate - An AND mask to clear an arbitrary width bitfield
175 def bf_inv_mask_imm : Operand<i32>,
177 uint32_t v = (uint32_t)N->getZExtValue();
180 // there can be 1's on either or both "outsides", all the "inside"
182 unsigned int lsb = 0, msb = 31;
183 while (v & (1 << msb)) --msb;
184 while (v & (1 << lsb)) ++lsb;
185 for (unsigned int i = lsb; i <= msb; ++i) {
191 let PrintMethod = "printBitfieldInvMaskImmOperand";
194 /// Split a 32-bit immediate into two 16 bit parts.
195 def lo16 : SDNodeXForm<imm, [{
196 return CurDAG->getTargetConstant((uint32_t)N->getZExtValue() & 0xffff,
200 def hi16 : SDNodeXForm<imm, [{
201 return CurDAG->getTargetConstant((uint32_t)N->getZExtValue() >> 16, MVT::i32);
204 def lo16AllZero : PatLeaf<(i32 imm), [{
205 // Returns true if all low 16-bits are 0.
206 return (((uint32_t)N->getZExtValue()) & 0xFFFFUL) == 0;
209 /// imm0_65535 predicate - True if the 32-bit immediate is in the range
211 def imm0_65535 : PatLeaf<(i32 imm), [{
212 return (uint32_t)N->getZExtValue() < 65536;
215 class BinOpFrag<dag res> : PatFrag<(ops node:$LHS, node:$RHS), res>;
216 class UnOpFrag <dag res> : PatFrag<(ops node:$Src), res>;
218 //===----------------------------------------------------------------------===//
219 // Operand Definitions.
223 def brtarget : Operand<OtherVT>;
225 // A list of registers separated by comma. Used by load/store multiple.
226 def reglist : Operand<i32> {
227 let PrintMethod = "printRegisterList";
230 // An operand for the CONSTPOOL_ENTRY pseudo-instruction.
231 def cpinst_operand : Operand<i32> {
232 let PrintMethod = "printCPInstOperand";
235 def jtblock_operand : Operand<i32> {
236 let PrintMethod = "printJTBlockOperand";
238 def jt2block_operand : Operand<i32> {
239 let PrintMethod = "printJT2BlockOperand";
243 def pclabel : Operand<i32> {
244 let PrintMethod = "printPCLabel";
247 // shifter_operand operands: so_reg and so_imm.
248 def so_reg : Operand<i32>, // reg reg imm
249 ComplexPattern<i32, 3, "SelectShifterOperandReg",
250 [shl,srl,sra,rotr]> {
251 let PrintMethod = "printSORegOperand";
252 let MIOperandInfo = (ops GPR, GPR, i32imm);
255 // so_imm - Match a 32-bit shifter_operand immediate operand, which is an
256 // 8-bit immediate rotated by an arbitrary number of bits. so_imm values are
257 // represented in the imm field in the same 12-bit form that they are encoded
258 // into so_imm instructions: the 8-bit immediate is the least significant bits
259 // [bits 0-7], the 4-bit shift amount is the next 4 bits [bits 8-11].
260 def so_imm : Operand<i32>,
262 return ARM_AM::getSOImmVal(N->getZExtValue()) != -1;
264 let PrintMethod = "printSOImmOperand";
267 // Break so_imm's up into two pieces. This handles immediates with up to 16
268 // bits set in them. This uses so_imm2part to match and so_imm2part_[12] to
269 // get the first/second pieces.
270 def so_imm2part : Operand<i32>,
272 return ARM_AM::isSOImmTwoPartVal((unsigned)N->getZExtValue());
274 let PrintMethod = "printSOImm2PartOperand";
277 def so_imm2part_1 : SDNodeXForm<imm, [{
278 unsigned V = ARM_AM::getSOImmTwoPartFirst((unsigned)N->getZExtValue());
279 return CurDAG->getTargetConstant(V, MVT::i32);
282 def so_imm2part_2 : SDNodeXForm<imm, [{
283 unsigned V = ARM_AM::getSOImmTwoPartSecond((unsigned)N->getZExtValue());
284 return CurDAG->getTargetConstant(V, MVT::i32);
287 /// imm0_31 predicate - True if the 32-bit immediate is in the range [0,31].
288 def imm0_31 : Operand<i32>, PatLeaf<(imm), [{
289 return (int32_t)N->getZExtValue() < 32;
292 // Define ARM specific addressing modes.
294 // addrmode2 := reg +/- reg shop imm
295 // addrmode2 := reg +/- imm12
297 def addrmode2 : Operand<i32>,
298 ComplexPattern<i32, 3, "SelectAddrMode2", []> {
299 let PrintMethod = "printAddrMode2Operand";
300 let MIOperandInfo = (ops GPR:$base, GPR:$offsreg, i32imm:$offsimm);
303 def am2offset : Operand<i32>,
304 ComplexPattern<i32, 2, "SelectAddrMode2Offset", []> {
305 let PrintMethod = "printAddrMode2OffsetOperand";
306 let MIOperandInfo = (ops GPR, i32imm);
309 // addrmode3 := reg +/- reg
310 // addrmode3 := reg +/- imm8
312 def addrmode3 : Operand<i32>,
313 ComplexPattern<i32, 3, "SelectAddrMode3", []> {
314 let PrintMethod = "printAddrMode3Operand";
315 let MIOperandInfo = (ops GPR:$base, GPR:$offsreg, i32imm:$offsimm);
318 def am3offset : Operand<i32>,
319 ComplexPattern<i32, 2, "SelectAddrMode3Offset", []> {
320 let PrintMethod = "printAddrMode3OffsetOperand";
321 let MIOperandInfo = (ops GPR, i32imm);
324 // addrmode4 := reg, <mode|W>
326 def addrmode4 : Operand<i32>,
327 ComplexPattern<i32, 2, "SelectAddrMode4", []> {
328 let PrintMethod = "printAddrMode4Operand";
329 let MIOperandInfo = (ops GPR, i32imm);
332 // addrmode5 := reg +/- imm8*4
334 def addrmode5 : Operand<i32>,
335 ComplexPattern<i32, 2, "SelectAddrMode5", []> {
336 let PrintMethod = "printAddrMode5Operand";
337 let MIOperandInfo = (ops GPR, i32imm);
340 // addrmode6 := reg with optional writeback
342 def addrmode6 : Operand<i32>,
343 ComplexPattern<i32, 3, "SelectAddrMode6", []> {
344 let PrintMethod = "printAddrMode6Operand";
345 let MIOperandInfo = (ops GPR:$addr, GPR:$upd, i32imm);
348 // addrmodepc := pc + reg
350 def addrmodepc : Operand<i32>,
351 ComplexPattern<i32, 2, "SelectAddrModePC", []> {
352 let PrintMethod = "printAddrModePCOperand";
353 let MIOperandInfo = (ops GPR, i32imm);
356 def nohash_imm : Operand<i32> {
357 let PrintMethod = "printNoHashImmediate";
360 //===----------------------------------------------------------------------===//
362 include "ARMInstrFormats.td"
364 //===----------------------------------------------------------------------===//
365 // Multiclass helpers...
368 /// AsI1_bin_irs - Defines a set of (op r, {so_imm|r|so_reg}) patterns for a
369 /// binop that produces a value.
370 multiclass AsI1_bin_irs<bits<4> opcod, string opc, PatFrag opnode,
371 bit Commutable = 0> {
372 def ri : AsI1<opcod, (outs GPR:$dst), (ins GPR:$a, so_imm:$b), DPFrm,
373 IIC_iALUi, opc, "\t$dst, $a, $b",
374 [(set GPR:$dst, (opnode GPR:$a, so_imm:$b))]> {
377 def rr : AsI1<opcod, (outs GPR:$dst), (ins GPR:$a, GPR:$b), DPFrm,
378 IIC_iALUr, opc, "\t$dst, $a, $b",
379 [(set GPR:$dst, (opnode GPR:$a, GPR:$b))]> {
382 let isCommutable = Commutable;
384 def rs : AsI1<opcod, (outs GPR:$dst), (ins GPR:$a, so_reg:$b), DPSoRegFrm,
385 IIC_iALUsr, opc, "\t$dst, $a, $b",
386 [(set GPR:$dst, (opnode GPR:$a, so_reg:$b))]> {
393 /// AI1_bin_s_irs - Similar to AsI1_bin_irs except it sets the 's' bit so the
394 /// instruction modifies the CPSR register.
395 let Defs = [CPSR] in {
396 multiclass AI1_bin_s_irs<bits<4> opcod, string opc, PatFrag opnode,
397 bit Commutable = 0> {
398 def ri : AI1<opcod, (outs GPR:$dst), (ins GPR:$a, so_imm:$b), DPFrm,
399 IIC_iALUi, opc, "s\t$dst, $a, $b",
400 [(set GPR:$dst, (opnode GPR:$a, so_imm:$b))]> {
404 def rr : AI1<opcod, (outs GPR:$dst), (ins GPR:$a, GPR:$b), DPFrm,
405 IIC_iALUr, opc, "s\t$dst, $a, $b",
406 [(set GPR:$dst, (opnode GPR:$a, GPR:$b))]> {
407 let isCommutable = Commutable;
412 def rs : AI1<opcod, (outs GPR:$dst), (ins GPR:$a, so_reg:$b), DPSoRegFrm,
413 IIC_iALUsr, opc, "s\t$dst, $a, $b",
414 [(set GPR:$dst, (opnode GPR:$a, so_reg:$b))]> {
423 /// AI1_cmp_irs - Defines a set of (op r, {so_imm|r|so_reg}) cmp / test
424 /// patterns. Similar to AsI1_bin_irs except the instruction does not produce
425 /// a explicit result, only implicitly set CPSR.
426 let Defs = [CPSR] in {
427 multiclass AI1_cmp_irs<bits<4> opcod, string opc, PatFrag opnode,
428 bit Commutable = 0> {
429 def ri : AI1<opcod, (outs), (ins GPR:$a, so_imm:$b), DPFrm, IIC_iCMPi,
431 [(opnode GPR:$a, so_imm:$b)]> {
435 def rr : AI1<opcod, (outs), (ins GPR:$a, GPR:$b), DPFrm, IIC_iCMPr,
437 [(opnode GPR:$a, GPR:$b)]> {
441 let isCommutable = Commutable;
443 def rs : AI1<opcod, (outs), (ins GPR:$a, so_reg:$b), DPSoRegFrm, IIC_iCMPsr,
445 [(opnode GPR:$a, so_reg:$b)]> {
454 /// AI_unary_rrot - A unary operation with two forms: one whose operand is a
455 /// register and one whose operand is a register rotated by 8/16/24.
456 /// FIXME: Remove the 'r' variant. Its rot_imm is zero.
457 multiclass AI_unary_rrot<bits<8> opcod, string opc, PatFrag opnode> {
458 def r : AExtI<opcod, (outs GPR:$dst), (ins GPR:$src),
459 IIC_iUNAr, opc, "\t$dst, $src",
460 [(set GPR:$dst, (opnode GPR:$src))]>,
461 Requires<[IsARM, HasV6]> {
462 let Inst{11-10} = 0b00;
463 let Inst{19-16} = 0b1111;
465 def r_rot : AExtI<opcod, (outs GPR:$dst), (ins GPR:$src, i32imm:$rot),
466 IIC_iUNAsi, opc, "\t$dst, $src, ror $rot",
467 [(set GPR:$dst, (opnode (rotr GPR:$src, rot_imm:$rot)))]>,
468 Requires<[IsARM, HasV6]> {
469 let Inst{19-16} = 0b1111;
473 /// AI_bin_rrot - A binary operation with two forms: one whose operand is a
474 /// register and one whose operand is a register rotated by 8/16/24.
475 multiclass AI_bin_rrot<bits<8> opcod, string opc, PatFrag opnode> {
476 def rr : AExtI<opcod, (outs GPR:$dst), (ins GPR:$LHS, GPR:$RHS),
477 IIC_iALUr, opc, "\t$dst, $LHS, $RHS",
478 [(set GPR:$dst, (opnode GPR:$LHS, GPR:$RHS))]>,
479 Requires<[IsARM, HasV6]> {
480 let Inst{11-10} = 0b00;
482 def rr_rot : AExtI<opcod, (outs GPR:$dst), (ins GPR:$LHS, GPR:$RHS, i32imm:$rot),
483 IIC_iALUsi, opc, "\t$dst, $LHS, $RHS, ror $rot",
484 [(set GPR:$dst, (opnode GPR:$LHS,
485 (rotr GPR:$RHS, rot_imm:$rot)))]>,
486 Requires<[IsARM, HasV6]>;
489 /// AI1_adde_sube_irs - Define instructions and patterns for adde and sube.
490 let Uses = [CPSR] in {
491 multiclass AI1_adde_sube_irs<bits<4> opcod, string opc, PatFrag opnode,
492 bit Commutable = 0> {
493 def ri : AsI1<opcod, (outs GPR:$dst), (ins GPR:$a, so_imm:$b),
494 DPFrm, IIC_iALUi, opc, "\t$dst, $a, $b",
495 [(set GPR:$dst, (opnode GPR:$a, so_imm:$b))]>,
496 Requires<[IsARM, CarryDefIsUnused]> {
499 def rr : AsI1<opcod, (outs GPR:$dst), (ins GPR:$a, GPR:$b),
500 DPFrm, IIC_iALUr, opc, "\t$dst, $a, $b",
501 [(set GPR:$dst, (opnode GPR:$a, GPR:$b))]>,
502 Requires<[IsARM, CarryDefIsUnused]> {
503 let isCommutable = Commutable;
507 def rs : AsI1<opcod, (outs GPR:$dst), (ins GPR:$a, so_reg:$b),
508 DPSoRegFrm, IIC_iALUsr, opc, "\t$dst, $a, $b",
509 [(set GPR:$dst, (opnode GPR:$a, so_reg:$b))]>,
510 Requires<[IsARM, CarryDefIsUnused]> {
515 // Carry setting variants
516 def Sri : AXI1<opcod, (outs GPR:$dst), (ins GPR:$a, so_imm:$b),
517 DPFrm, IIC_iALUi, !strconcat(opc, "s\t$dst, $a, $b"),
518 [(set GPR:$dst, (opnode GPR:$a, so_imm:$b))]>,
519 Requires<[IsARM, CarryDefIsUsed]> {
524 def Srr : AXI1<opcod, (outs GPR:$dst), (ins GPR:$a, GPR:$b),
525 DPFrm, IIC_iALUr, !strconcat(opc, "s\t$dst, $a, $b"),
526 [(set GPR:$dst, (opnode GPR:$a, GPR:$b))]>,
527 Requires<[IsARM, CarryDefIsUsed]> {
533 def Srs : AXI1<opcod, (outs GPR:$dst), (ins GPR:$a, so_reg:$b),
534 DPSoRegFrm, IIC_iALUsr, !strconcat(opc, "s\t$dst, $a, $b"),
535 [(set GPR:$dst, (opnode GPR:$a, so_reg:$b))]>,
536 Requires<[IsARM, CarryDefIsUsed]> {
546 //===----------------------------------------------------------------------===//
548 //===----------------------------------------------------------------------===//
550 //===----------------------------------------------------------------------===//
551 // Miscellaneous Instructions.
554 /// CONSTPOOL_ENTRY - This instruction represents a floating constant pool in
555 /// the function. The first operand is the ID# for this instruction, the second
556 /// is the index into the MachineConstantPool that this is, the third is the
557 /// size in bytes of this constant pool entry.
558 let neverHasSideEffects = 1, isNotDuplicable = 1 in
559 def CONSTPOOL_ENTRY :
560 PseudoInst<(outs), (ins cpinst_operand:$instid, cpinst_operand:$cpidx,
561 i32imm:$size), NoItinerary,
562 "${instid:label} ${cpidx:cpentry}", []>;
564 let Defs = [SP], Uses = [SP] in {
566 PseudoInst<(outs), (ins i32imm:$amt1, i32imm:$amt2, pred:$p), NoItinerary,
567 "@ ADJCALLSTACKUP $amt1",
568 [(ARMcallseq_end timm:$amt1, timm:$amt2)]>;
570 def ADJCALLSTACKDOWN :
571 PseudoInst<(outs), (ins i32imm:$amt, pred:$p), NoItinerary,
572 "@ ADJCALLSTACKDOWN $amt",
573 [(ARMcallseq_start timm:$amt)]>;
577 PseudoInst<(outs), (ins i32imm:$line, i32imm:$col, i32imm:$file), NoItinerary,
578 ".loc $file, $line, $col",
579 [(dwarf_loc (i32 imm:$line), (i32 imm:$col), (i32 imm:$file))]>;
582 // Address computation and loads and stores in PIC mode.
583 let isNotDuplicable = 1 in {
584 def PICADD : AXI1<0b0100, (outs GPR:$dst), (ins GPR:$a, pclabel:$cp, pred:$p),
585 Pseudo, IIC_iALUr, "\n$cp:\n\tadd$p\t$dst, pc, $a",
586 [(set GPR:$dst, (ARMpic_add GPR:$a, imm:$cp))]>;
588 let AddedComplexity = 10 in {
589 let canFoldAsLoad = 1 in
590 def PICLDR : AXI2ldw<(outs GPR:$dst), (ins addrmodepc:$addr, pred:$p),
591 Pseudo, IIC_iLoadr, "\n${addr:label}:\n\tldr$p\t$dst, $addr",
592 [(set GPR:$dst, (load addrmodepc:$addr))]>;
594 def PICLDRH : AXI3ldh<(outs GPR:$dst), (ins addrmodepc:$addr, pred:$p),
595 Pseudo, IIC_iLoadr, "\n${addr:label}:\n\tldr${p}h\t$dst, $addr",
596 [(set GPR:$dst, (zextloadi16 addrmodepc:$addr))]>;
598 def PICLDRB : AXI2ldb<(outs GPR:$dst), (ins addrmodepc:$addr, pred:$p),
599 Pseudo, IIC_iLoadr, "\n${addr:label}:\n\tldr${p}b\t$dst, $addr",
600 [(set GPR:$dst, (zextloadi8 addrmodepc:$addr))]>;
602 def PICLDRSH : AXI3ldsh<(outs GPR:$dst), (ins addrmodepc:$addr, pred:$p),
603 Pseudo, IIC_iLoadr, "\n${addr:label}:\n\tldr${p}sh\t$dst, $addr",
604 [(set GPR:$dst, (sextloadi16 addrmodepc:$addr))]>;
606 def PICLDRSB : AXI3ldsb<(outs GPR:$dst), (ins addrmodepc:$addr, pred:$p),
607 Pseudo, IIC_iLoadr, "\n${addr:label}:\n\tldr${p}sb\t$dst, $addr",
608 [(set GPR:$dst, (sextloadi8 addrmodepc:$addr))]>;
610 let AddedComplexity = 10 in {
611 def PICSTR : AXI2stw<(outs), (ins GPR:$src, addrmodepc:$addr, pred:$p),
612 Pseudo, IIC_iStorer, "\n${addr:label}:\n\tstr$p\t$src, $addr",
613 [(store GPR:$src, addrmodepc:$addr)]>;
615 def PICSTRH : AXI3sth<(outs), (ins GPR:$src, addrmodepc:$addr, pred:$p),
616 Pseudo, IIC_iStorer, "\n${addr:label}:\n\tstr${p}h\t$src, $addr",
617 [(truncstorei16 GPR:$src, addrmodepc:$addr)]>;
619 def PICSTRB : AXI2stb<(outs), (ins GPR:$src, addrmodepc:$addr, pred:$p),
620 Pseudo, IIC_iStorer, "\n${addr:label}:\n\tstr${p}b\t$src, $addr",
621 [(truncstorei8 GPR:$src, addrmodepc:$addr)]>;
623 } // isNotDuplicable = 1
626 // LEApcrel - Load a pc-relative address into a register without offending the
628 def LEApcrel : AXI1<0x0, (outs GPR:$dst), (ins i32imm:$label, pred:$p),
630 !strconcat(!strconcat(".set ${:private}PCRELV${:uid}, ($label-(",
631 "${:private}PCRELL${:uid}+8))\n"),
632 !strconcat("${:private}PCRELL${:uid}:\n\t",
633 "add$p\t$dst, pc, #${:private}PCRELV${:uid}")),
636 def LEApcrelJT : AXI1<0x0, (outs GPR:$dst),
637 (ins i32imm:$label, nohash_imm:$id, pred:$p),
639 !strconcat(!strconcat(".set ${:private}PCRELV${:uid}, "
641 "${:private}PCRELL${:uid}+8))\n"),
642 !strconcat("${:private}PCRELL${:uid}:\n\t",
643 "add$p\t$dst, pc, #${:private}PCRELV${:uid}")),
648 //===----------------------------------------------------------------------===//
649 // Control Flow Instructions.
652 let isReturn = 1, isTerminator = 1, isBarrier = 1 in
653 def BX_RET : AI<(outs), (ins), BrMiscFrm, IIC_Br,
654 "bx", "\tlr", [(ARMretflag)]> {
655 let Inst{7-4} = 0b0001;
656 let Inst{19-8} = 0b111111111111;
657 let Inst{27-20} = 0b00010010;
661 let isBranch = 1, isTerminator = 1, isBarrier = 1, isIndirectBranch = 1 in {
662 def BRIND : AXI<(outs), (ins GPR:$dst), BrMiscFrm, IIC_Br, "bx\t$dst",
663 [(brind GPR:$dst)]> {
664 let Inst{7-4} = 0b0001;
665 let Inst{19-8} = 0b111111111111;
666 let Inst{27-20} = 0b00010010;
670 // FIXME: remove when we have a way to marking a MI with these properties.
671 // FIXME: Should pc be an implicit operand like PICADD, etc?
672 let isReturn = 1, isTerminator = 1, isBarrier = 1, mayLoad = 1,
673 hasExtraDefRegAllocReq = 1 in
674 def LDM_RET : AXI4ld<(outs),
675 (ins addrmode4:$addr, pred:$p, reglist:$wb, variable_ops),
676 LdStMulFrm, IIC_Br, "ldm${p}${addr:submode}\t$addr, $wb",
679 // On non-Darwin platforms R9 is callee-saved.
681 Defs = [R0, R1, R2, R3, R12, LR,
682 D0, D1, D2, D3, D4, D5, D6, D7,
683 D16, D17, D18, D19, D20, D21, D22, D23,
684 D24, D25, D26, D27, D28, D29, D30, D31, CPSR, FPSCR] in {
685 def BL : ABXI<0b1011, (outs), (ins i32imm:$func, variable_ops),
686 IIC_Br, "bl\t${func:call}",
687 [(ARMcall tglobaladdr:$func)]>,
688 Requires<[IsARM, IsNotDarwin]> {
689 let Inst{31-28} = 0b1110;
692 def BL_pred : ABI<0b1011, (outs), (ins i32imm:$func, variable_ops),
693 IIC_Br, "bl", "\t${func:call}",
694 [(ARMcall_pred tglobaladdr:$func)]>,
695 Requires<[IsARM, IsNotDarwin]>;
698 def BLX : AXI<(outs), (ins GPR:$func, variable_ops), BrMiscFrm,
699 IIC_Br, "blx\t$func",
700 [(ARMcall GPR:$func)]>,
701 Requires<[IsARM, HasV5T, IsNotDarwin]> {
702 let Inst{7-4} = 0b0011;
703 let Inst{19-8} = 0b111111111111;
704 let Inst{27-20} = 0b00010010;
708 def BX : ABXIx2<(outs), (ins GPR:$func, variable_ops),
709 IIC_Br, "mov\tlr, pc\n\tbx\t$func",
710 [(ARMcall_nolink GPR:$func)]>,
711 Requires<[IsARM, IsNotDarwin]> {
712 let Inst{7-4} = 0b0001;
713 let Inst{19-8} = 0b111111111111;
714 let Inst{27-20} = 0b00010010;
718 // On Darwin R9 is call-clobbered.
720 Defs = [R0, R1, R2, R3, R9, R12, LR,
721 D0, D1, D2, D3, D4, D5, D6, D7,
722 D16, D17, D18, D19, D20, D21, D22, D23,
723 D24, D25, D26, D27, D28, D29, D30, D31, CPSR, FPSCR] in {
724 def BLr9 : ABXI<0b1011, (outs), (ins i32imm:$func, variable_ops),
725 IIC_Br, "bl\t${func:call}",
726 [(ARMcall tglobaladdr:$func)]>, Requires<[IsARM, IsDarwin]> {
727 let Inst{31-28} = 0b1110;
730 def BLr9_pred : ABI<0b1011, (outs), (ins i32imm:$func, variable_ops),
731 IIC_Br, "bl", "\t${func:call}",
732 [(ARMcall_pred tglobaladdr:$func)]>,
733 Requires<[IsARM, IsDarwin]>;
736 def BLXr9 : AXI<(outs), (ins GPR:$func, variable_ops), BrMiscFrm,
737 IIC_Br, "blx\t$func",
738 [(ARMcall GPR:$func)]>, Requires<[IsARM, HasV5T, IsDarwin]> {
739 let Inst{7-4} = 0b0011;
740 let Inst{19-8} = 0b111111111111;
741 let Inst{27-20} = 0b00010010;
745 def BXr9 : ABXIx2<(outs), (ins GPR:$func, variable_ops),
746 IIC_Br, "mov\tlr, pc\n\tbx\t$func",
747 [(ARMcall_nolink GPR:$func)]>, Requires<[IsARM, IsDarwin]> {
748 let Inst{7-4} = 0b0001;
749 let Inst{19-8} = 0b111111111111;
750 let Inst{27-20} = 0b00010010;
754 let isBranch = 1, isTerminator = 1 in {
755 // B is "predicable" since it can be xformed into a Bcc.
756 let isBarrier = 1 in {
757 let isPredicable = 1 in
758 def B : ABXI<0b1010, (outs), (ins brtarget:$target), IIC_Br,
759 "b\t$target", [(br bb:$target)]>;
761 let isNotDuplicable = 1, isIndirectBranch = 1 in {
762 def BR_JTr : JTI<(outs), (ins GPR:$target, jtblock_operand:$jt, i32imm:$id),
763 IIC_Br, "mov\tpc, $target \n$jt",
764 [(ARMbrjt GPR:$target, tjumptable:$jt, imm:$id)]> {
765 let Inst{20} = 0; // S Bit
766 let Inst{24-21} = 0b1101;
767 let Inst{27-25} = 0b000;
769 def BR_JTm : JTI<(outs),
770 (ins addrmode2:$target, jtblock_operand:$jt, i32imm:$id),
771 IIC_Br, "ldr\tpc, $target \n$jt",
772 [(ARMbrjt (i32 (load addrmode2:$target)), tjumptable:$jt,
774 let Inst{20} = 1; // L bit
775 let Inst{21} = 0; // W bit
776 let Inst{22} = 0; // B bit
777 let Inst{24} = 1; // P bit
778 let Inst{27-25} = 0b011;
780 def BR_JTadd : JTI<(outs),
781 (ins GPR:$target, GPR:$idx, jtblock_operand:$jt, i32imm:$id),
782 IIC_Br, "add\tpc, $target, $idx \n$jt",
783 [(ARMbrjt (add GPR:$target, GPR:$idx), tjumptable:$jt,
785 let Inst{20} = 0; // S bit
786 let Inst{24-21} = 0b0100;
787 let Inst{27-25} = 0b000;
789 } // isNotDuplicable = 1, isIndirectBranch = 1
792 // FIXME: should be able to write a pattern for ARMBrcond, but can't use
793 // a two-value operand where a dag node expects two operands. :(
794 def Bcc : ABI<0b1010, (outs), (ins brtarget:$target),
795 IIC_Br, "b", "\t$target",
796 [/*(ARMbrcond bb:$target, imm:$cc, CCR:$ccr)*/]>;
799 //===----------------------------------------------------------------------===//
800 // Load / store Instructions.
804 let canFoldAsLoad = 1, isReMaterializable = 1 in
805 def LDR : AI2ldw<(outs GPR:$dst), (ins addrmode2:$addr), LdFrm, IIC_iLoadr,
806 "ldr", "\t$dst, $addr",
807 [(set GPR:$dst, (load addrmode2:$addr))]>;
809 // Special LDR for loads from non-pc-relative constpools.
810 let canFoldAsLoad = 1, mayLoad = 1, isReMaterializable = 1 in
811 def LDRcp : AI2ldw<(outs GPR:$dst), (ins addrmode2:$addr), LdFrm, IIC_iLoadr,
812 "ldr", "\t$dst, $addr", []>;
814 // Loads with zero extension
815 def LDRH : AI3ldh<(outs GPR:$dst), (ins addrmode3:$addr), LdMiscFrm,
816 IIC_iLoadr, "ldr", "h\t$dst, $addr",
817 [(set GPR:$dst, (zextloadi16 addrmode3:$addr))]>;
819 def LDRB : AI2ldb<(outs GPR:$dst), (ins addrmode2:$addr), LdFrm,
820 IIC_iLoadr, "ldr", "b\t$dst, $addr",
821 [(set GPR:$dst, (zextloadi8 addrmode2:$addr))]>;
823 // Loads with sign extension
824 def LDRSH : AI3ldsh<(outs GPR:$dst), (ins addrmode3:$addr), LdMiscFrm,
825 IIC_iLoadr, "ldr", "sh\t$dst, $addr",
826 [(set GPR:$dst, (sextloadi16 addrmode3:$addr))]>;
828 def LDRSB : AI3ldsb<(outs GPR:$dst), (ins addrmode3:$addr), LdMiscFrm,
829 IIC_iLoadr, "ldr", "sb\t$dst, $addr",
830 [(set GPR:$dst, (sextloadi8 addrmode3:$addr))]>;
832 let mayLoad = 1, hasExtraDefRegAllocReq = 1 in {
834 def LDRD : AI3ldd<(outs GPR:$dst1, GPR:$dst2), (ins addrmode3:$addr), LdMiscFrm,
835 IIC_iLoadr, "ldr", "d\t$dst1, $addr",
836 []>, Requires<[IsARM, HasV5TE]>;
839 def LDR_PRE : AI2ldwpr<(outs GPR:$dst, GPR:$base_wb),
840 (ins addrmode2:$addr), LdFrm, IIC_iLoadru,
841 "ldr", "\t$dst, $addr!", "$addr.base = $base_wb", []>;
843 def LDR_POST : AI2ldwpo<(outs GPR:$dst, GPR:$base_wb),
844 (ins GPR:$base, am2offset:$offset), LdFrm, IIC_iLoadru,
845 "ldr", "\t$dst, [$base], $offset", "$base = $base_wb", []>;
847 def LDRH_PRE : AI3ldhpr<(outs GPR:$dst, GPR:$base_wb),
848 (ins addrmode3:$addr), LdMiscFrm, IIC_iLoadru,
849 "ldr", "h\t$dst, $addr!", "$addr.base = $base_wb", []>;
851 def LDRH_POST : AI3ldhpo<(outs GPR:$dst, GPR:$base_wb),
852 (ins GPR:$base,am3offset:$offset), LdMiscFrm, IIC_iLoadru,
853 "ldr", "h\t$dst, [$base], $offset", "$base = $base_wb", []>;
855 def LDRB_PRE : AI2ldbpr<(outs GPR:$dst, GPR:$base_wb),
856 (ins addrmode2:$addr), LdFrm, IIC_iLoadru,
857 "ldr", "b\t$dst, $addr!", "$addr.base = $base_wb", []>;
859 def LDRB_POST : AI2ldbpo<(outs GPR:$dst, GPR:$base_wb),
860 (ins GPR:$base,am2offset:$offset), LdFrm, IIC_iLoadru,
861 "ldr", "b\t$dst, [$base], $offset", "$base = $base_wb", []>;
863 def LDRSH_PRE : AI3ldshpr<(outs GPR:$dst, GPR:$base_wb),
864 (ins addrmode3:$addr), LdMiscFrm, IIC_iLoadru,
865 "ldr", "sh\t$dst, $addr!", "$addr.base = $base_wb", []>;
867 def LDRSH_POST: AI3ldshpo<(outs GPR:$dst, GPR:$base_wb),
868 (ins GPR:$base,am3offset:$offset), LdMiscFrm, IIC_iLoadru,
869 "ldr", "sh\t$dst, [$base], $offset", "$base = $base_wb", []>;
871 def LDRSB_PRE : AI3ldsbpr<(outs GPR:$dst, GPR:$base_wb),
872 (ins addrmode3:$addr), LdMiscFrm, IIC_iLoadru,
873 "ldr", "sb\t$dst, $addr!", "$addr.base = $base_wb", []>;
875 def LDRSB_POST: AI3ldsbpo<(outs GPR:$dst, GPR:$base_wb),
876 (ins GPR:$base,am3offset:$offset), LdMiscFrm, IIC_iLoadru,
877 "ldr", "sb\t$dst, [$base], $offset", "$base = $base_wb", []>;
881 def STR : AI2stw<(outs), (ins GPR:$src, addrmode2:$addr), StFrm, IIC_iStorer,
882 "str", "\t$src, $addr",
883 [(store GPR:$src, addrmode2:$addr)]>;
885 // Stores with truncate
886 def STRH : AI3sth<(outs), (ins GPR:$src, addrmode3:$addr), StMiscFrm, IIC_iStorer,
887 "str", "h\t$src, $addr",
888 [(truncstorei16 GPR:$src, addrmode3:$addr)]>;
890 def STRB : AI2stb<(outs), (ins GPR:$src, addrmode2:$addr), StFrm, IIC_iStorer,
891 "str", "b\t$src, $addr",
892 [(truncstorei8 GPR:$src, addrmode2:$addr)]>;
895 let mayStore = 1, hasExtraSrcRegAllocReq = 1 in
896 def STRD : AI3std<(outs), (ins GPR:$src1, GPR:$src2, addrmode3:$addr),
897 StMiscFrm, IIC_iStorer,
898 "str", "d\t$src1, $addr", []>, Requires<[IsARM, HasV5TE]>;
901 def STR_PRE : AI2stwpr<(outs GPR:$base_wb),
902 (ins GPR:$src, GPR:$base, am2offset:$offset),
904 "str", "\t$src, [$base, $offset]!", "$base = $base_wb",
906 (pre_store GPR:$src, GPR:$base, am2offset:$offset))]>;
908 def STR_POST : AI2stwpo<(outs GPR:$base_wb),
909 (ins GPR:$src, GPR:$base,am2offset:$offset),
911 "str", "\t$src, [$base], $offset", "$base = $base_wb",
913 (post_store GPR:$src, GPR:$base, am2offset:$offset))]>;
915 def STRH_PRE : AI3sthpr<(outs GPR:$base_wb),
916 (ins GPR:$src, GPR:$base,am3offset:$offset),
917 StMiscFrm, IIC_iStoreru,
918 "str", "h\t$src, [$base, $offset]!", "$base = $base_wb",
920 (pre_truncsti16 GPR:$src, GPR:$base,am3offset:$offset))]>;
922 def STRH_POST: AI3sthpo<(outs GPR:$base_wb),
923 (ins GPR:$src, GPR:$base,am3offset:$offset),
924 StMiscFrm, IIC_iStoreru,
925 "str", "h\t$src, [$base], $offset", "$base = $base_wb",
926 [(set GPR:$base_wb, (post_truncsti16 GPR:$src,
927 GPR:$base, am3offset:$offset))]>;
929 def STRB_PRE : AI2stbpr<(outs GPR:$base_wb),
930 (ins GPR:$src, GPR:$base,am2offset:$offset),
932 "str", "b\t$src, [$base, $offset]!", "$base = $base_wb",
933 [(set GPR:$base_wb, (pre_truncsti8 GPR:$src,
934 GPR:$base, am2offset:$offset))]>;
936 def STRB_POST: AI2stbpo<(outs GPR:$base_wb),
937 (ins GPR:$src, GPR:$base,am2offset:$offset),
939 "str", "b\t$src, [$base], $offset", "$base = $base_wb",
940 [(set GPR:$base_wb, (post_truncsti8 GPR:$src,
941 GPR:$base, am2offset:$offset))]>;
943 //===----------------------------------------------------------------------===//
944 // Load / store multiple Instructions.
947 let mayLoad = 1, hasExtraDefRegAllocReq = 1 in
948 def LDM : AXI4ld<(outs),
949 (ins addrmode4:$addr, pred:$p, reglist:$wb, variable_ops),
950 LdStMulFrm, IIC_iLoadm, "ldm${p}${addr:submode}\t$addr, $wb",
953 let mayStore = 1, hasExtraSrcRegAllocReq = 1 in
954 def STM : AXI4st<(outs),
955 (ins addrmode4:$addr, pred:$p, reglist:$wb, variable_ops),
956 LdStMulFrm, IIC_iStorem, "stm${p}${addr:submode}\t$addr, $wb",
959 //===----------------------------------------------------------------------===//
960 // Move Instructions.
963 let neverHasSideEffects = 1 in
964 def MOVr : AsI1<0b1101, (outs GPR:$dst), (ins GPR:$src), DPFrm, IIC_iMOVr,
965 "mov", "\t$dst, $src", []>, UnaryDP {
970 def MOVs : AsI1<0b1101, (outs GPR:$dst), (ins so_reg:$src),
971 DPSoRegFrm, IIC_iMOVsr,
972 "mov", "\t$dst, $src", [(set GPR:$dst, so_reg:$src)]>, UnaryDP {
978 let isReMaterializable = 1, isAsCheapAsAMove = 1 in
979 def MOVi : AsI1<0b1101, (outs GPR:$dst), (ins so_imm:$src), DPFrm, IIC_iMOVi,
980 "mov", "\t$dst, $src", [(set GPR:$dst, so_imm:$src)]>, UnaryDP {
984 let isReMaterializable = 1, isAsCheapAsAMove = 1 in
985 def MOVi16 : AI1<0b1000, (outs GPR:$dst), (ins i32imm:$src),
987 "movw", "\t$dst, $src",
988 [(set GPR:$dst, imm0_65535:$src)]>,
989 Requires<[IsARM, HasV6T2]> {
994 let Constraints = "$src = $dst" in
995 def MOVTi16 : AI1<0b1010, (outs GPR:$dst), (ins GPR:$src, i32imm:$imm),
997 "movt", "\t$dst, $imm",
999 (or (and GPR:$src, 0xffff),
1000 lo16AllZero:$imm))]>, UnaryDP,
1001 Requires<[IsARM, HasV6T2]> {
1006 def : ARMPat<(or GPR:$src, 0xffff0000), (MOVTi16 GPR:$src, 0xffff)>,
1007 Requires<[IsARM, HasV6T2]>;
1009 let Uses = [CPSR] in
1010 def MOVrx : AsI1<0b1101, (outs GPR:$dst), (ins GPR:$src), Pseudo, IIC_iMOVsi,
1011 "mov", "\t$dst, $src, rrx",
1012 [(set GPR:$dst, (ARMrrx GPR:$src))]>, UnaryDP;
1014 // These aren't really mov instructions, but we have to define them this way
1015 // due to flag operands.
1017 let Defs = [CPSR] in {
1018 def MOVsrl_flag : AI1<0b1101, (outs GPR:$dst), (ins GPR:$src), Pseudo,
1019 IIC_iMOVsi, "mov", "s\t$dst, $src, lsr #1",
1020 [(set GPR:$dst, (ARMsrl_flag GPR:$src))]>, UnaryDP;
1021 def MOVsra_flag : AI1<0b1101, (outs GPR:$dst), (ins GPR:$src), Pseudo,
1022 IIC_iMOVsi, "mov", "s\t$dst, $src, asr #1",
1023 [(set GPR:$dst, (ARMsra_flag GPR:$src))]>, UnaryDP;
1026 //===----------------------------------------------------------------------===//
1027 // Extend Instructions.
1032 defm SXTB : AI_unary_rrot<0b01101010,
1033 "sxtb", UnOpFrag<(sext_inreg node:$Src, i8)>>;
1034 defm SXTH : AI_unary_rrot<0b01101011,
1035 "sxth", UnOpFrag<(sext_inreg node:$Src, i16)>>;
1037 defm SXTAB : AI_bin_rrot<0b01101010,
1038 "sxtab", BinOpFrag<(add node:$LHS, (sext_inreg node:$RHS, i8))>>;
1039 defm SXTAH : AI_bin_rrot<0b01101011,
1040 "sxtah", BinOpFrag<(add node:$LHS, (sext_inreg node:$RHS,i16))>>;
1042 // TODO: SXT(A){B|H}16
1046 let AddedComplexity = 16 in {
1047 defm UXTB : AI_unary_rrot<0b01101110,
1048 "uxtb" , UnOpFrag<(and node:$Src, 0x000000FF)>>;
1049 defm UXTH : AI_unary_rrot<0b01101111,
1050 "uxth" , UnOpFrag<(and node:$Src, 0x0000FFFF)>>;
1051 defm UXTB16 : AI_unary_rrot<0b01101100,
1052 "uxtb16", UnOpFrag<(and node:$Src, 0x00FF00FF)>>;
1054 def : ARMV6Pat<(and (shl GPR:$Src, (i32 8)), 0xFF00FF),
1055 (UXTB16r_rot GPR:$Src, 24)>;
1056 def : ARMV6Pat<(and (srl GPR:$Src, (i32 8)), 0xFF00FF),
1057 (UXTB16r_rot GPR:$Src, 8)>;
1059 defm UXTAB : AI_bin_rrot<0b01101110, "uxtab",
1060 BinOpFrag<(add node:$LHS, (and node:$RHS, 0x00FF))>>;
1061 defm UXTAH : AI_bin_rrot<0b01101111, "uxtah",
1062 BinOpFrag<(add node:$LHS, (and node:$RHS, 0xFFFF))>>;
1065 // This isn't safe in general, the add is two 16-bit units, not a 32-bit add.
1066 //defm UXTAB16 : xxx<"uxtab16", 0xff00ff>;
1068 // TODO: UXT(A){B|H}16
1070 def SBFX : I<(outs GPR:$dst),
1071 (ins GPR:$src, imm0_31:$lsb, imm0_31:$width),
1072 AddrMode1, Size4Bytes, IndexModeNone, DPFrm, IIC_iALUi,
1073 "sbfx", "\t$dst, $src, $lsb, $width", "", []>,
1074 Requires<[IsARM, HasV6T2]> {
1075 let Inst{27-21} = 0b0111101;
1076 let Inst{6-4} = 0b101;
1079 def UBFX : I<(outs GPR:$dst),
1080 (ins GPR:$src, imm0_31:$lsb, imm0_31:$width),
1081 AddrMode1, Size4Bytes, IndexModeNone, DPFrm, IIC_iALUi,
1082 "ubfx", "\t$dst, $src, $lsb, $width", "", []>,
1083 Requires<[IsARM, HasV6T2]> {
1084 let Inst{27-21} = 0b0111111;
1085 let Inst{6-4} = 0b101;
1088 //===----------------------------------------------------------------------===//
1089 // Arithmetic Instructions.
1092 defm ADD : AsI1_bin_irs<0b0100, "add",
1093 BinOpFrag<(add node:$LHS, node:$RHS)>, 1>;
1094 defm SUB : AsI1_bin_irs<0b0010, "sub",
1095 BinOpFrag<(sub node:$LHS, node:$RHS)>>;
1097 // ADD and SUB with 's' bit set.
1098 defm ADDS : AI1_bin_s_irs<0b0100, "add",
1099 BinOpFrag<(addc node:$LHS, node:$RHS)>>;
1100 defm SUBS : AI1_bin_s_irs<0b0010, "sub",
1101 BinOpFrag<(subc node:$LHS, node:$RHS)>>;
1103 defm ADC : AI1_adde_sube_irs<0b0101, "adc",
1104 BinOpFrag<(adde node:$LHS, node:$RHS)>, 1>;
1105 defm SBC : AI1_adde_sube_irs<0b0110, "sbc",
1106 BinOpFrag<(sube node:$LHS, node:$RHS)>>;
1108 // These don't define reg/reg forms, because they are handled above.
1109 def RSBri : AsI1<0b0011, (outs GPR:$dst), (ins GPR:$a, so_imm:$b), DPFrm,
1110 IIC_iALUi, "rsb", "\t$dst, $a, $b",
1111 [(set GPR:$dst, (sub so_imm:$b, GPR:$a))]> {
1115 def RSBrs : AsI1<0b0011, (outs GPR:$dst), (ins GPR:$a, so_reg:$b), DPSoRegFrm,
1116 IIC_iALUsr, "rsb", "\t$dst, $a, $b",
1117 [(set GPR:$dst, (sub so_reg:$b, GPR:$a))]> {
1123 // RSB with 's' bit set.
1124 let Defs = [CPSR] in {
1125 def RSBSri : AI1<0b0011, (outs GPR:$dst), (ins GPR:$a, so_imm:$b), DPFrm,
1126 IIC_iALUi, "rsb", "s\t$dst, $a, $b",
1127 [(set GPR:$dst, (subc so_imm:$b, GPR:$a))]> {
1131 def RSBSrs : AI1<0b0011, (outs GPR:$dst), (ins GPR:$a, so_reg:$b), DPSoRegFrm,
1132 IIC_iALUsr, "rsb", "s\t$dst, $a, $b",
1133 [(set GPR:$dst, (subc so_reg:$b, GPR:$a))]> {
1141 let Uses = [CPSR] in {
1142 def RSCri : AsI1<0b0111, (outs GPR:$dst), (ins GPR:$a, so_imm:$b),
1143 DPFrm, IIC_iALUi, "rsc", "\t$dst, $a, $b",
1144 [(set GPR:$dst, (sube so_imm:$b, GPR:$a))]>,
1145 Requires<[IsARM, CarryDefIsUnused]> {
1148 def RSCrs : AsI1<0b0111, (outs GPR:$dst), (ins GPR:$a, so_reg:$b),
1149 DPSoRegFrm, IIC_iALUsr, "rsc", "\t$dst, $a, $b",
1150 [(set GPR:$dst, (sube so_reg:$b, GPR:$a))]>,
1151 Requires<[IsARM, CarryDefIsUnused]> {
1158 // FIXME: Allow these to be predicated.
1159 let Defs = [CPSR], Uses = [CPSR] in {
1160 def RSCSri : AXI1<0b0111, (outs GPR:$dst), (ins GPR:$a, so_imm:$b),
1161 DPFrm, IIC_iALUi, "rscs\t$dst, $a, $b",
1162 [(set GPR:$dst, (sube so_imm:$b, GPR:$a))]>,
1163 Requires<[IsARM, CarryDefIsUnused]> {
1167 def RSCSrs : AXI1<0b0111, (outs GPR:$dst), (ins GPR:$a, so_reg:$b),
1168 DPSoRegFrm, IIC_iALUsr, "rscs\t$dst, $a, $b",
1169 [(set GPR:$dst, (sube so_reg:$b, GPR:$a))]>,
1170 Requires<[IsARM, CarryDefIsUnused]> {
1178 // (sub X, imm) gets canonicalized to (add X, -imm). Match this form.
1179 def : ARMPat<(add GPR:$src, so_imm_neg:$imm),
1180 (SUBri GPR:$src, so_imm_neg:$imm)>;
1182 //def : ARMPat<(addc GPR:$src, so_imm_neg:$imm),
1183 // (SUBSri GPR:$src, so_imm_neg:$imm)>;
1184 //def : ARMPat<(adde GPR:$src, so_imm_neg:$imm),
1185 // (SBCri GPR:$src, so_imm_neg:$imm)>;
1187 // Note: These are implemented in C++ code, because they have to generate
1188 // ADD/SUBrs instructions, which use a complex pattern that a xform function
1190 // (mul X, 2^n+1) -> (add (X << n), X)
1191 // (mul X, 2^n-1) -> (rsb X, (X << n))
1194 //===----------------------------------------------------------------------===//
1195 // Bitwise Instructions.
1198 defm AND : AsI1_bin_irs<0b0000, "and",
1199 BinOpFrag<(and node:$LHS, node:$RHS)>, 1>;
1200 defm ORR : AsI1_bin_irs<0b1100, "orr",
1201 BinOpFrag<(or node:$LHS, node:$RHS)>, 1>;
1202 defm EOR : AsI1_bin_irs<0b0001, "eor",
1203 BinOpFrag<(xor node:$LHS, node:$RHS)>, 1>;
1204 defm BIC : AsI1_bin_irs<0b1110, "bic",
1205 BinOpFrag<(and node:$LHS, (not node:$RHS))>>;
1207 def BFC : I<(outs GPR:$dst), (ins GPR:$src, bf_inv_mask_imm:$imm),
1208 AddrMode1, Size4Bytes, IndexModeNone, DPFrm, IIC_iUNAsi,
1209 "bfc", "\t$dst, $imm", "$src = $dst",
1210 [(set GPR:$dst, (and GPR:$src, bf_inv_mask_imm:$imm))]>,
1211 Requires<[IsARM, HasV6T2]> {
1212 let Inst{27-21} = 0b0111110;
1213 let Inst{6-0} = 0b0011111;
1216 def MVNr : AsI1<0b1111, (outs GPR:$dst), (ins GPR:$src), DPFrm, IIC_iMOVr,
1217 "mvn", "\t$dst, $src",
1218 [(set GPR:$dst, (not GPR:$src))]>, UnaryDP {
1221 def MVNs : AsI1<0b1111, (outs GPR:$dst), (ins so_reg:$src), DPSoRegFrm,
1222 IIC_iMOVsr, "mvn", "\t$dst, $src",
1223 [(set GPR:$dst, (not so_reg:$src))]>, UnaryDP {
1227 let isReMaterializable = 1, isAsCheapAsAMove = 1 in
1228 def MVNi : AsI1<0b1111, (outs GPR:$dst), (ins so_imm:$imm), DPFrm,
1229 IIC_iMOVi, "mvn", "\t$dst, $imm",
1230 [(set GPR:$dst, so_imm_not:$imm)]>,UnaryDP {
1234 def : ARMPat<(and GPR:$src, so_imm_not:$imm),
1235 (BICri GPR:$src, so_imm_not:$imm)>;
1237 //===----------------------------------------------------------------------===//
1238 // Multiply Instructions.
1241 let isCommutable = 1 in
1242 def MUL : AsMul1I<0b0000000, (outs GPR:$dst), (ins GPR:$a, GPR:$b),
1243 IIC_iMUL32, "mul", "\t$dst, $a, $b",
1244 [(set GPR:$dst, (mul GPR:$a, GPR:$b))]>;
1246 def MLA : AsMul1I<0b0000001, (outs GPR:$dst), (ins GPR:$a, GPR:$b, GPR:$c),
1247 IIC_iMAC32, "mla", "\t$dst, $a, $b, $c",
1248 [(set GPR:$dst, (add (mul GPR:$a, GPR:$b), GPR:$c))]>;
1250 def MLS : AMul1I<0b0000011, (outs GPR:$dst), (ins GPR:$a, GPR:$b, GPR:$c),
1251 IIC_iMAC32, "mls", "\t$dst, $a, $b, $c",
1252 [(set GPR:$dst, (sub GPR:$c, (mul GPR:$a, GPR:$b)))]>,
1253 Requires<[IsARM, HasV6T2]>;
1255 // Extra precision multiplies with low / high results
1256 let neverHasSideEffects = 1 in {
1257 let isCommutable = 1 in {
1258 def SMULL : AsMul1I<0b0000110, (outs GPR:$ldst, GPR:$hdst),
1259 (ins GPR:$a, GPR:$b), IIC_iMUL64,
1260 "smull", "\t$ldst, $hdst, $a, $b", []>;
1262 def UMULL : AsMul1I<0b0000100, (outs GPR:$ldst, GPR:$hdst),
1263 (ins GPR:$a, GPR:$b), IIC_iMUL64,
1264 "umull", "\t$ldst, $hdst, $a, $b", []>;
1267 // Multiply + accumulate
1268 def SMLAL : AsMul1I<0b0000111, (outs GPR:$ldst, GPR:$hdst),
1269 (ins GPR:$a, GPR:$b), IIC_iMAC64,
1270 "smlal", "\t$ldst, $hdst, $a, $b", []>;
1272 def UMLAL : AsMul1I<0b0000101, (outs GPR:$ldst, GPR:$hdst),
1273 (ins GPR:$a, GPR:$b), IIC_iMAC64,
1274 "umlal", "\t$ldst, $hdst, $a, $b", []>;
1276 def UMAAL : AMul1I <0b0000010, (outs GPR:$ldst, GPR:$hdst),
1277 (ins GPR:$a, GPR:$b), IIC_iMAC64,
1278 "umaal", "\t$ldst, $hdst, $a, $b", []>,
1279 Requires<[IsARM, HasV6]>;
1280 } // neverHasSideEffects
1282 // Most significant word multiply
1283 def SMMUL : AMul2I <0b0111010, (outs GPR:$dst), (ins GPR:$a, GPR:$b),
1284 IIC_iMUL32, "smmul", "\t$dst, $a, $b",
1285 [(set GPR:$dst, (mulhs GPR:$a, GPR:$b))]>,
1286 Requires<[IsARM, HasV6]> {
1287 let Inst{7-4} = 0b0001;
1288 let Inst{15-12} = 0b1111;
1291 def SMMLA : AMul2I <0b0111010, (outs GPR:$dst), (ins GPR:$a, GPR:$b, GPR:$c),
1292 IIC_iMAC32, "smmla", "\t$dst, $a, $b, $c",
1293 [(set GPR:$dst, (add (mulhs GPR:$a, GPR:$b), GPR:$c))]>,
1294 Requires<[IsARM, HasV6]> {
1295 let Inst{7-4} = 0b0001;
1299 def SMMLS : AMul2I <0b0111010, (outs GPR:$dst), (ins GPR:$a, GPR:$b, GPR:$c),
1300 IIC_iMAC32, "smmls", "\t$dst, $a, $b, $c",
1301 [(set GPR:$dst, (sub GPR:$c, (mulhs GPR:$a, GPR:$b)))]>,
1302 Requires<[IsARM, HasV6]> {
1303 let Inst{7-4} = 0b1101;
1306 multiclass AI_smul<string opc, PatFrag opnode> {
1307 def BB : AMulxyI<0b0001011, (outs GPR:$dst), (ins GPR:$a, GPR:$b),
1308 IIC_iMUL32, !strconcat(opc, "bb"), "\t$dst, $a, $b",
1309 [(set GPR:$dst, (opnode (sext_inreg GPR:$a, i16),
1310 (sext_inreg GPR:$b, i16)))]>,
1311 Requires<[IsARM, HasV5TE]> {
1316 def BT : AMulxyI<0b0001011, (outs GPR:$dst), (ins GPR:$a, GPR:$b),
1317 IIC_iMUL32, !strconcat(opc, "bt"), "\t$dst, $a, $b",
1318 [(set GPR:$dst, (opnode (sext_inreg GPR:$a, i16),
1319 (sra GPR:$b, (i32 16))))]>,
1320 Requires<[IsARM, HasV5TE]> {
1325 def TB : AMulxyI<0b0001011, (outs GPR:$dst), (ins GPR:$a, GPR:$b),
1326 IIC_iMUL32, !strconcat(opc, "tb"), "\t$dst, $a, $b",
1327 [(set GPR:$dst, (opnode (sra GPR:$a, (i32 16)),
1328 (sext_inreg GPR:$b, i16)))]>,
1329 Requires<[IsARM, HasV5TE]> {
1334 def TT : AMulxyI<0b0001011, (outs GPR:$dst), (ins GPR:$a, GPR:$b),
1335 IIC_iMUL32, !strconcat(opc, "tt"), "\t$dst, $a, $b",
1336 [(set GPR:$dst, (opnode (sra GPR:$a, (i32 16)),
1337 (sra GPR:$b, (i32 16))))]>,
1338 Requires<[IsARM, HasV5TE]> {
1343 def WB : AMulxyI<0b0001001, (outs GPR:$dst), (ins GPR:$a, GPR:$b),
1344 IIC_iMUL16, !strconcat(opc, "wb"), "\t$dst, $a, $b",
1345 [(set GPR:$dst, (sra (opnode GPR:$a,
1346 (sext_inreg GPR:$b, i16)), (i32 16)))]>,
1347 Requires<[IsARM, HasV5TE]> {
1352 def WT : AMulxyI<0b0001001, (outs GPR:$dst), (ins GPR:$a, GPR:$b),
1353 IIC_iMUL16, !strconcat(opc, "wt"), "\t$dst, $a, $b",
1354 [(set GPR:$dst, (sra (opnode GPR:$a,
1355 (sra GPR:$b, (i32 16))), (i32 16)))]>,
1356 Requires<[IsARM, HasV5TE]> {
1363 multiclass AI_smla<string opc, PatFrag opnode> {
1364 def BB : AMulxyI<0b0001000, (outs GPR:$dst), (ins GPR:$a, GPR:$b, GPR:$acc),
1365 IIC_iMAC16, !strconcat(opc, "bb"), "\t$dst, $a, $b, $acc",
1366 [(set GPR:$dst, (add GPR:$acc,
1367 (opnode (sext_inreg GPR:$a, i16),
1368 (sext_inreg GPR:$b, i16))))]>,
1369 Requires<[IsARM, HasV5TE]> {
1374 def BT : AMulxyI<0b0001000, (outs GPR:$dst), (ins GPR:$a, GPR:$b, GPR:$acc),
1375 IIC_iMAC16, !strconcat(opc, "bt"), "\t$dst, $a, $b, $acc",
1376 [(set GPR:$dst, (add GPR:$acc, (opnode (sext_inreg GPR:$a, i16),
1377 (sra GPR:$b, (i32 16)))))]>,
1378 Requires<[IsARM, HasV5TE]> {
1383 def TB : AMulxyI<0b0001000, (outs GPR:$dst), (ins GPR:$a, GPR:$b, GPR:$acc),
1384 IIC_iMAC16, !strconcat(opc, "tb"), "\t$dst, $a, $b, $acc",
1385 [(set GPR:$dst, (add GPR:$acc, (opnode (sra GPR:$a, (i32 16)),
1386 (sext_inreg GPR:$b, i16))))]>,
1387 Requires<[IsARM, HasV5TE]> {
1392 def TT : AMulxyI<0b0001000, (outs GPR:$dst), (ins GPR:$a, GPR:$b, GPR:$acc),
1393 IIC_iMAC16, !strconcat(opc, "tt"), "\t$dst, $a, $b, $acc",
1394 [(set GPR:$dst, (add GPR:$acc, (opnode (sra GPR:$a, (i32 16)),
1395 (sra GPR:$b, (i32 16)))))]>,
1396 Requires<[IsARM, HasV5TE]> {
1401 def WB : AMulxyI<0b0001001, (outs GPR:$dst), (ins GPR:$a, GPR:$b, GPR:$acc),
1402 IIC_iMAC16, !strconcat(opc, "wb"), "\t$dst, $a, $b, $acc",
1403 [(set GPR:$dst, (add GPR:$acc, (sra (opnode GPR:$a,
1404 (sext_inreg GPR:$b, i16)), (i32 16))))]>,
1405 Requires<[IsARM, HasV5TE]> {
1410 def WT : AMulxyI<0b0001001, (outs GPR:$dst), (ins GPR:$a, GPR:$b, GPR:$acc),
1411 IIC_iMAC16, !strconcat(opc, "wt"), "\t$dst, $a, $b, $acc",
1412 [(set GPR:$dst, (add GPR:$acc, (sra (opnode GPR:$a,
1413 (sra GPR:$b, (i32 16))), (i32 16))))]>,
1414 Requires<[IsARM, HasV5TE]> {
1420 defm SMUL : AI_smul<"smul", BinOpFrag<(mul node:$LHS, node:$RHS)>>;
1421 defm SMLA : AI_smla<"smla", BinOpFrag<(mul node:$LHS, node:$RHS)>>;
1423 // TODO: Halfword multiple accumulate long: SMLAL<x><y>
1424 // TODO: Dual halfword multiple: SMUAD, SMUSD, SMLAD, SMLSD, SMLALD, SMLSLD
1426 //===----------------------------------------------------------------------===//
1427 // Misc. Arithmetic Instructions.
1430 def CLZ : AMiscA1I<0b000010110, (outs GPR:$dst), (ins GPR:$src), IIC_iUNAr,
1431 "clz", "\t$dst, $src",
1432 [(set GPR:$dst, (ctlz GPR:$src))]>, Requires<[IsARM, HasV5T]> {
1433 let Inst{7-4} = 0b0001;
1434 let Inst{11-8} = 0b1111;
1435 let Inst{19-16} = 0b1111;
1438 def REV : AMiscA1I<0b01101011, (outs GPR:$dst), (ins GPR:$src), IIC_iUNAr,
1439 "rev", "\t$dst, $src",
1440 [(set GPR:$dst, (bswap GPR:$src))]>, Requires<[IsARM, HasV6]> {
1441 let Inst{7-4} = 0b0011;
1442 let Inst{11-8} = 0b1111;
1443 let Inst{19-16} = 0b1111;
1446 def REV16 : AMiscA1I<0b01101011, (outs GPR:$dst), (ins GPR:$src), IIC_iUNAr,
1447 "rev16", "\t$dst, $src",
1449 (or (and (srl GPR:$src, (i32 8)), 0xFF),
1450 (or (and (shl GPR:$src, (i32 8)), 0xFF00),
1451 (or (and (srl GPR:$src, (i32 8)), 0xFF0000),
1452 (and (shl GPR:$src, (i32 8)), 0xFF000000)))))]>,
1453 Requires<[IsARM, HasV6]> {
1454 let Inst{7-4} = 0b1011;
1455 let Inst{11-8} = 0b1111;
1456 let Inst{19-16} = 0b1111;
1459 def REVSH : AMiscA1I<0b01101111, (outs GPR:$dst), (ins GPR:$src), IIC_iUNAr,
1460 "revsh", "\t$dst, $src",
1463 (or (srl (and GPR:$src, 0xFF00), (i32 8)),
1464 (shl GPR:$src, (i32 8))), i16))]>,
1465 Requires<[IsARM, HasV6]> {
1466 let Inst{7-4} = 0b1011;
1467 let Inst{11-8} = 0b1111;
1468 let Inst{19-16} = 0b1111;
1471 def PKHBT : AMiscA1I<0b01101000, (outs GPR:$dst),
1472 (ins GPR:$src1, GPR:$src2, i32imm:$shamt),
1473 IIC_iALUsi, "pkhbt", "\t$dst, $src1, $src2, LSL $shamt",
1474 [(set GPR:$dst, (or (and GPR:$src1, 0xFFFF),
1475 (and (shl GPR:$src2, (i32 imm:$shamt)),
1477 Requires<[IsARM, HasV6]> {
1478 let Inst{6-4} = 0b001;
1481 // Alternate cases for PKHBT where identities eliminate some nodes.
1482 def : ARMV6Pat<(or (and GPR:$src1, 0xFFFF), (and GPR:$src2, 0xFFFF0000)),
1483 (PKHBT GPR:$src1, GPR:$src2, 0)>;
1484 def : ARMV6Pat<(or (and GPR:$src1, 0xFFFF), (shl GPR:$src2, imm16_31:$shamt)),
1485 (PKHBT GPR:$src1, GPR:$src2, imm16_31:$shamt)>;
1488 def PKHTB : AMiscA1I<0b01101000, (outs GPR:$dst),
1489 (ins GPR:$src1, GPR:$src2, i32imm:$shamt),
1490 IIC_iALUsi, "pkhtb", "\t$dst, $src1, $src2, ASR $shamt",
1491 [(set GPR:$dst, (or (and GPR:$src1, 0xFFFF0000),
1492 (and (sra GPR:$src2, imm16_31:$shamt),
1493 0xFFFF)))]>, Requires<[IsARM, HasV6]> {
1494 let Inst{6-4} = 0b101;
1497 // Alternate cases for PKHTB where identities eliminate some nodes. Note that
1498 // a shift amount of 0 is *not legal* here, it is PKHBT instead.
1499 def : ARMV6Pat<(or (and GPR:$src1, 0xFFFF0000), (srl GPR:$src2, (i32 16))),
1500 (PKHTB GPR:$src1, GPR:$src2, 16)>;
1501 def : ARMV6Pat<(or (and GPR:$src1, 0xFFFF0000),
1502 (and (srl GPR:$src2, imm1_15:$shamt), 0xFFFF)),
1503 (PKHTB GPR:$src1, GPR:$src2, imm1_15:$shamt)>;
1505 //===----------------------------------------------------------------------===//
1506 // Comparison Instructions...
1509 defm CMP : AI1_cmp_irs<0b1010, "cmp",
1510 BinOpFrag<(ARMcmp node:$LHS, node:$RHS)>>;
1511 defm CMN : AI1_cmp_irs<0b1011, "cmn",
1512 BinOpFrag<(ARMcmp node:$LHS,(ineg node:$RHS))>>;
1514 // Note that TST/TEQ don't set all the same flags that CMP does!
1515 defm TST : AI1_cmp_irs<0b1000, "tst",
1516 BinOpFrag<(ARMcmpZ (and node:$LHS, node:$RHS), 0)>, 1>;
1517 defm TEQ : AI1_cmp_irs<0b1001, "teq",
1518 BinOpFrag<(ARMcmpZ (xor node:$LHS, node:$RHS), 0)>, 1>;
1520 defm CMPz : AI1_cmp_irs<0b1010, "cmp",
1521 BinOpFrag<(ARMcmpZ node:$LHS, node:$RHS)>>;
1522 defm CMNz : AI1_cmp_irs<0b1011, "cmn",
1523 BinOpFrag<(ARMcmpZ node:$LHS,(ineg node:$RHS))>>;
1525 def : ARMPat<(ARMcmp GPR:$src, so_imm_neg:$imm),
1526 (CMNri GPR:$src, so_imm_neg:$imm)>;
1528 def : ARMPat<(ARMcmpZ GPR:$src, so_imm_neg:$imm),
1529 (CMNri GPR:$src, so_imm_neg:$imm)>;
1532 // Conditional moves
1533 // FIXME: should be able to write a pattern for ARMcmov, but can't use
1534 // a two-value operand where a dag node expects two operands. :(
1535 def MOVCCr : AI1<0b1101, (outs GPR:$dst), (ins GPR:$false, GPR:$true), DPFrm,
1536 IIC_iCMOVr, "mov", "\t$dst, $true",
1537 [/*(set GPR:$dst, (ARMcmov GPR:$false, GPR:$true, imm:$cc, CCR:$ccr))*/]>,
1538 RegConstraint<"$false = $dst">, UnaryDP {
1543 def MOVCCs : AI1<0b1101, (outs GPR:$dst),
1544 (ins GPR:$false, so_reg:$true), DPSoRegFrm, IIC_iCMOVsr,
1545 "mov", "\t$dst, $true",
1546 [/*(set GPR:$dst, (ARMcmov GPR:$false, so_reg:$true, imm:$cc, CCR:$ccr))*/]>,
1547 RegConstraint<"$false = $dst">, UnaryDP {
1553 def MOVCCi : AI1<0b1101, (outs GPR:$dst),
1554 (ins GPR:$false, so_imm:$true), DPFrm, IIC_iCMOVi,
1555 "mov", "\t$dst, $true",
1556 [/*(set GPR:$dst, (ARMcmov GPR:$false, so_imm:$true, imm:$cc, CCR:$ccr))*/]>,
1557 RegConstraint<"$false = $dst">, UnaryDP {
1562 //===----------------------------------------------------------------------===//
1566 // __aeabi_read_tp preserves the registers r1-r3.
1568 Defs = [R0, R12, LR, CPSR] in {
1569 def TPsoft : ABXI<0b1011, (outs), (ins), IIC_Br,
1570 "bl\t__aeabi_read_tp",
1571 [(set R0, ARMthread_pointer)]>;
1574 //===----------------------------------------------------------------------===//
1575 // SJLJ Exception handling intrinsics
1576 // eh_sjlj_setjmp() is an instruction sequence to store the return
1577 // address and save #0 in R0 for the non-longjmp case.
1578 // Since by its nature we may be coming from some other function to get
1579 // here, and we're using the stack frame for the containing function to
1580 // save/restore registers, we can't keep anything live in regs across
1581 // the eh_sjlj_setjmp(), else it will almost certainly have been tromped upon
1582 // when we get here from a longjmp(). We force everthing out of registers
1583 // except for our own input by listing the relevant registers in Defs. By
1584 // doing so, we also cause the prologue/epilogue code to actively preserve
1585 // all of the callee-saved resgisters, which is exactly what we want.
1587 [ R0, R1, R2, R3, R4, R5, R6, R7, R8, R9, R10, R11, R12, LR, D0,
1588 D1, D2, D3, D4, D5, D6, D7, D8, D9, D10, D11, D12, D13, D14, D15,
1589 D16, D17, D18, D19, D20, D21, D22, D23, D24, D25, D26, D27, D28, D29, D30,
1591 def Int_eh_sjlj_setjmp : XI<(outs), (ins GPR:$src),
1592 AddrModeNone, SizeSpecial, IndexModeNone,
1593 Pseudo, NoItinerary,
1594 "str\tsp, [$src, #+8] @ eh_setjmp begin\n\t"
1595 "add\tr12, pc, #8\n\t"
1596 "str\tr12, [$src, #+4]\n\t"
1598 "add\tpc, pc, #0\n\t"
1599 "mov\tr0, #1 @ eh_setjmp end", "",
1600 [(set R0, (ARMeh_sjlj_setjmp GPR:$src))]>;
1603 //===----------------------------------------------------------------------===//
1604 // Non-Instruction Patterns
1607 // ConstantPool, GlobalAddress, and JumpTable
1608 def : ARMPat<(ARMWrapper tglobaladdr :$dst), (LEApcrel tglobaladdr :$dst)>;
1609 def : ARMPat<(ARMWrapper tconstpool :$dst), (LEApcrel tconstpool :$dst)>;
1610 def : ARMPat<(ARMWrapper tblockaddress:$dst), (LEApcrel tblockaddress:$dst)>;
1611 def : ARMPat<(ARMWrapperJT tjumptable:$dst, imm:$id),
1612 (LEApcrelJT tjumptable:$dst, imm:$id)>;
1614 // Large immediate handling.
1616 // Two piece so_imms.
1617 let isReMaterializable = 1 in
1618 def MOVi2pieces : AI1x2<(outs GPR:$dst), (ins so_imm2part:$src),
1620 "mov", "\t$dst, $src",
1621 [(set GPR:$dst, so_imm2part:$src)]>,
1622 Requires<[IsARM, NoV6T2]>;
1624 def : ARMPat<(or GPR:$LHS, so_imm2part:$RHS),
1625 (ORRri (ORRri GPR:$LHS, (so_imm2part_1 imm:$RHS)),
1626 (so_imm2part_2 imm:$RHS))>;
1627 def : ARMPat<(xor GPR:$LHS, so_imm2part:$RHS),
1628 (EORri (EORri GPR:$LHS, (so_imm2part_1 imm:$RHS)),
1629 (so_imm2part_2 imm:$RHS))>;
1630 def : ARMPat<(add GPR:$LHS, so_imm2part:$RHS),
1631 (ADDri (ADDri GPR:$LHS, (so_imm2part_1 imm:$RHS)),
1632 (so_imm2part_2 imm:$RHS))>;
1633 def : ARMPat<(sub GPR:$LHS, so_imm2part:$RHS),
1634 (SUBri (SUBri GPR:$LHS, (so_imm2part_1 imm:$RHS)),
1635 (so_imm2part_2 imm:$RHS))>;
1637 // 32-bit immediate using movw + movt.
1638 // This is a single pseudo instruction, the benefit is that it can be remat'd
1639 // as a single unit instead of having to handle reg inputs.
1640 // FIXME: Remove this when we can do generalized remat.
1641 let isReMaterializable = 1 in
1642 def MOVi32imm : AI1x2<(outs GPR:$dst), (ins i32imm:$src), Pseudo, IIC_iMOVi,
1643 "movw", "\t$dst, ${src:lo16}\n\tmovt${p} $dst, ${src:hi16}",
1644 [(set GPR:$dst, (i32 imm:$src))]>,
1645 Requires<[IsARM, HasV6T2]>;
1647 // TODO: add,sub,and, 3-instr forms?
1651 def : ARMPat<(ARMcall texternalsym:$func), (BL texternalsym:$func)>,
1652 Requires<[IsARM, IsNotDarwin]>;
1653 def : ARMPat<(ARMcall texternalsym:$func), (BLr9 texternalsym:$func)>,
1654 Requires<[IsARM, IsDarwin]>;
1656 // zextload i1 -> zextload i8
1657 def : ARMPat<(zextloadi1 addrmode2:$addr), (LDRB addrmode2:$addr)>;
1659 // extload -> zextload
1660 def : ARMPat<(extloadi1 addrmode2:$addr), (LDRB addrmode2:$addr)>;
1661 def : ARMPat<(extloadi8 addrmode2:$addr), (LDRB addrmode2:$addr)>;
1662 def : ARMPat<(extloadi16 addrmode3:$addr), (LDRH addrmode3:$addr)>;
1664 def : ARMPat<(extloadi8 addrmodepc:$addr), (PICLDRB addrmodepc:$addr)>;
1665 def : ARMPat<(extloadi16 addrmodepc:$addr), (PICLDRH addrmodepc:$addr)>;
1668 def : ARMV5TEPat<(mul (sra (shl GPR:$a, (i32 16)), (i32 16)),
1669 (sra (shl GPR:$b, (i32 16)), (i32 16))),
1670 (SMULBB GPR:$a, GPR:$b)>;
1671 def : ARMV5TEPat<(mul sext_16_node:$a, sext_16_node:$b),
1672 (SMULBB GPR:$a, GPR:$b)>;
1673 def : ARMV5TEPat<(mul (sra (shl GPR:$a, (i32 16)), (i32 16)),
1674 (sra GPR:$b, (i32 16))),
1675 (SMULBT GPR:$a, GPR:$b)>;
1676 def : ARMV5TEPat<(mul sext_16_node:$a, (sra GPR:$b, (i32 16))),
1677 (SMULBT GPR:$a, GPR:$b)>;
1678 def : ARMV5TEPat<(mul (sra GPR:$a, (i32 16)),
1679 (sra (shl GPR:$b, (i32 16)), (i32 16))),
1680 (SMULTB GPR:$a, GPR:$b)>;
1681 def : ARMV5TEPat<(mul (sra GPR:$a, (i32 16)), sext_16_node:$b),
1682 (SMULTB GPR:$a, GPR:$b)>;
1683 def : ARMV5TEPat<(sra (mul GPR:$a, (sra (shl GPR:$b, (i32 16)), (i32 16))),
1685 (SMULWB GPR:$a, GPR:$b)>;
1686 def : ARMV5TEPat<(sra (mul GPR:$a, sext_16_node:$b), (i32 16)),
1687 (SMULWB GPR:$a, GPR:$b)>;
1689 def : ARMV5TEPat<(add GPR:$acc,
1690 (mul (sra (shl GPR:$a, (i32 16)), (i32 16)),
1691 (sra (shl GPR:$b, (i32 16)), (i32 16)))),
1692 (SMLABB GPR:$a, GPR:$b, GPR:$acc)>;
1693 def : ARMV5TEPat<(add GPR:$acc,
1694 (mul sext_16_node:$a, sext_16_node:$b)),
1695 (SMLABB GPR:$a, GPR:$b, GPR:$acc)>;
1696 def : ARMV5TEPat<(add GPR:$acc,
1697 (mul (sra (shl GPR:$a, (i32 16)), (i32 16)),
1698 (sra GPR:$b, (i32 16)))),
1699 (SMLABT GPR:$a, GPR:$b, GPR:$acc)>;
1700 def : ARMV5TEPat<(add GPR:$acc,
1701 (mul sext_16_node:$a, (sra GPR:$b, (i32 16)))),
1702 (SMLABT GPR:$a, GPR:$b, GPR:$acc)>;
1703 def : ARMV5TEPat<(add GPR:$acc,
1704 (mul (sra GPR:$a, (i32 16)),
1705 (sra (shl GPR:$b, (i32 16)), (i32 16)))),
1706 (SMLATB GPR:$a, GPR:$b, GPR:$acc)>;
1707 def : ARMV5TEPat<(add GPR:$acc,
1708 (mul (sra GPR:$a, (i32 16)), sext_16_node:$b)),
1709 (SMLATB GPR:$a, GPR:$b, GPR:$acc)>;
1710 def : ARMV5TEPat<(add GPR:$acc,
1711 (sra (mul GPR:$a, (sra (shl GPR:$b, (i32 16)), (i32 16))),
1713 (SMLAWB GPR:$a, GPR:$b, GPR:$acc)>;
1714 def : ARMV5TEPat<(add GPR:$acc,
1715 (sra (mul GPR:$a, sext_16_node:$b), (i32 16))),
1716 (SMLAWB GPR:$a, GPR:$b, GPR:$acc)>;
1718 //===----------------------------------------------------------------------===//
1722 include "ARMInstrThumb.td"
1724 //===----------------------------------------------------------------------===//
1728 include "ARMInstrThumb2.td"
1730 //===----------------------------------------------------------------------===//
1731 // Floating Point Support
1734 include "ARMInstrVFP.td"
1736 //===----------------------------------------------------------------------===//
1737 // Advanced SIMD (NEON) Support
1740 include "ARMInstrNEON.td"