1 //===- ARMInstrInfo.td - Target Description for ARM Target -*- tablegen -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file describes the ARM instructions in TableGen format.
12 //===----------------------------------------------------------------------===//
14 //===----------------------------------------------------------------------===//
15 // ARM specific DAG Nodes.
19 def SDT_ARMCallSeqStart : SDCallSeqStart<[ SDTCisVT<0, i32> ]>;
20 def SDT_ARMCallSeqEnd : SDCallSeqEnd<[ SDTCisVT<0, i32>, SDTCisVT<1, i32> ]>;
22 def SDT_ARMSaveCallPC : SDTypeProfile<0, 1, []>;
24 def SDT_ARMcall : SDTypeProfile<0, -1, [SDTCisPtrTy<0>]>;
26 def SDT_ARMCMov : SDTypeProfile<1, 3,
27 [SDTCisSameAs<0, 1>, SDTCisSameAs<0, 2>,
30 def SDT_ARMBrcond : SDTypeProfile<0, 2,
31 [SDTCisVT<0, OtherVT>, SDTCisVT<1, i32>]>;
33 def SDT_ARMBrJT : SDTypeProfile<0, 3,
34 [SDTCisPtrTy<0>, SDTCisVT<1, i32>,
37 def SDT_ARMBr2JT : SDTypeProfile<0, 4,
38 [SDTCisPtrTy<0>, SDTCisVT<1, i32>,
39 SDTCisVT<2, i32>, SDTCisVT<3, i32>]>;
41 def SDT_ARMBCC_i64 : SDTypeProfile<0, 6,
43 SDTCisVT<1, i32>, SDTCisVT<2, i32>,
44 SDTCisVT<3, i32>, SDTCisVT<4, i32>,
45 SDTCisVT<5, OtherVT>]>;
47 def SDT_ARMAnd : SDTypeProfile<1, 2,
48 [SDTCisVT<0, i32>, SDTCisVT<1, i32>,
51 def SDT_ARMCmp : SDTypeProfile<0, 2, [SDTCisSameAs<0, 1>]>;
53 def SDT_ARMPICAdd : SDTypeProfile<1, 2, [SDTCisSameAs<0, 1>,
54 SDTCisPtrTy<1>, SDTCisVT<2, i32>]>;
56 def SDT_ARMThreadPointer : SDTypeProfile<1, 0, [SDTCisPtrTy<0>]>;
57 def SDT_ARMEH_SJLJ_Setjmp : SDTypeProfile<1, 2, [SDTCisInt<0>, SDTCisPtrTy<1>,
59 def SDT_ARMEH_SJLJ_Longjmp: SDTypeProfile<0, 2, [SDTCisPtrTy<0>, SDTCisInt<1>]>;
61 def SDT_ARMEH_SJLJ_DispatchSetup: SDTypeProfile<0, 0, []>;
63 def SDT_ARMMEMBARRIER : SDTypeProfile<0, 1, [SDTCisInt<0>]>;
65 def SDT_ARMTCRET : SDTypeProfile<0, 1, [SDTCisPtrTy<0>]>;
67 def SDT_ARMBFI : SDTypeProfile<1, 3, [SDTCisVT<0, i32>, SDTCisVT<1, i32>,
68 SDTCisVT<2, i32>, SDTCisVT<3, i32>]>;
71 def ARMWrapper : SDNode<"ARMISD::Wrapper", SDTIntUnaryOp>;
72 def ARMWrapperDYN : SDNode<"ARMISD::WrapperDYN", SDTIntUnaryOp>;
73 def ARMWrapperPIC : SDNode<"ARMISD::WrapperPIC", SDTIntUnaryOp>;
74 def ARMWrapperJT : SDNode<"ARMISD::WrapperJT", SDTIntBinOp>;
76 def ARMcallseq_start : SDNode<"ISD::CALLSEQ_START", SDT_ARMCallSeqStart,
77 [SDNPHasChain, SDNPOutGlue]>;
78 def ARMcallseq_end : SDNode<"ISD::CALLSEQ_END", SDT_ARMCallSeqEnd,
79 [SDNPHasChain, SDNPOptInGlue, SDNPOutGlue]>;
81 def ARMcall : SDNode<"ARMISD::CALL", SDT_ARMcall,
82 [SDNPHasChain, SDNPOptInGlue, SDNPOutGlue,
84 def ARMcall_pred : SDNode<"ARMISD::CALL_PRED", SDT_ARMcall,
85 [SDNPHasChain, SDNPOptInGlue, SDNPOutGlue,
87 def ARMcall_nolink : SDNode<"ARMISD::CALL_NOLINK", SDT_ARMcall,
88 [SDNPHasChain, SDNPOptInGlue, SDNPOutGlue,
91 def ARMretflag : SDNode<"ARMISD::RET_FLAG", SDTNone,
92 [SDNPHasChain, SDNPOptInGlue]>;
94 def ARMcmov : SDNode<"ARMISD::CMOV", SDT_ARMCMov,
97 def ARMbrcond : SDNode<"ARMISD::BRCOND", SDT_ARMBrcond,
98 [SDNPHasChain, SDNPInGlue, SDNPOutGlue]>;
100 def ARMbrjt : SDNode<"ARMISD::BR_JT", SDT_ARMBrJT,
102 def ARMbr2jt : SDNode<"ARMISD::BR2_JT", SDT_ARMBr2JT,
105 def ARMBcci64 : SDNode<"ARMISD::BCC_i64", SDT_ARMBCC_i64,
108 def ARMcmp : SDNode<"ARMISD::CMP", SDT_ARMCmp,
111 def ARMcmpZ : SDNode<"ARMISD::CMPZ", SDT_ARMCmp,
112 [SDNPOutGlue, SDNPCommutative]>;
114 def ARMpic_add : SDNode<"ARMISD::PIC_ADD", SDT_ARMPICAdd>;
116 def ARMsrl_flag : SDNode<"ARMISD::SRL_FLAG", SDTIntUnaryOp, [SDNPOutGlue]>;
117 def ARMsra_flag : SDNode<"ARMISD::SRA_FLAG", SDTIntUnaryOp, [SDNPOutGlue]>;
118 def ARMrrx : SDNode<"ARMISD::RRX" , SDTIntUnaryOp, [SDNPInGlue ]>;
120 def ARMthread_pointer: SDNode<"ARMISD::THREAD_POINTER", SDT_ARMThreadPointer>;
121 def ARMeh_sjlj_setjmp: SDNode<"ARMISD::EH_SJLJ_SETJMP",
122 SDT_ARMEH_SJLJ_Setjmp, [SDNPHasChain]>;
123 def ARMeh_sjlj_longjmp: SDNode<"ARMISD::EH_SJLJ_LONGJMP",
124 SDT_ARMEH_SJLJ_Longjmp, [SDNPHasChain]>;
125 def ARMeh_sjlj_dispatchsetup: SDNode<"ARMISD::EH_SJLJ_DISPATCHSETUP",
126 SDT_ARMEH_SJLJ_DispatchSetup, [SDNPHasChain]>;
129 def ARMMemBarrier : SDNode<"ARMISD::MEMBARRIER", SDT_ARMMEMBARRIER,
131 def ARMMemBarrierMCR : SDNode<"ARMISD::MEMBARRIER_MCR", SDT_ARMMEMBARRIER,
133 def ARMPreload : SDNode<"ARMISD::PRELOAD", SDTPrefetch,
134 [SDNPHasChain, SDNPMayLoad, SDNPMayStore]>;
136 def ARMrbit : SDNode<"ARMISD::RBIT", SDTIntUnaryOp>;
138 def ARMtcret : SDNode<"ARMISD::TC_RETURN", SDT_ARMTCRET,
139 [SDNPHasChain, SDNPOptInGlue, SDNPVariadic]>;
142 def ARMbfi : SDNode<"ARMISD::BFI", SDT_ARMBFI>;
144 //===----------------------------------------------------------------------===//
145 // ARM Instruction Predicate Definitions.
147 def HasV4T : Predicate<"Subtarget->hasV4TOps()">, AssemblerPredicate;
148 def NoV4T : Predicate<"!Subtarget->hasV4TOps()">;
149 def HasV5T : Predicate<"Subtarget->hasV5TOps()">;
150 def HasV5TE : Predicate<"Subtarget->hasV5TEOps()">, AssemblerPredicate;
151 def HasV6 : Predicate<"Subtarget->hasV6Ops()">, AssemblerPredicate;
152 def NoV6 : Predicate<"!Subtarget->hasV6Ops()">;
153 def HasV6T2 : Predicate<"Subtarget->hasV6T2Ops()">, AssemblerPredicate;
154 def NoV6T2 : Predicate<"!Subtarget->hasV6T2Ops()">;
155 def HasV7 : Predicate<"Subtarget->hasV7Ops()">, AssemblerPredicate;
156 def NoVFP : Predicate<"!Subtarget->hasVFP2()">;
157 def HasVFP2 : Predicate<"Subtarget->hasVFP2()">, AssemblerPredicate;
158 def HasVFP3 : Predicate<"Subtarget->hasVFP3()">, AssemblerPredicate;
159 def HasNEON : Predicate<"Subtarget->hasNEON()">, AssemblerPredicate;
160 def HasFP16 : Predicate<"Subtarget->hasFP16()">, AssemblerPredicate;
161 def HasDivide : Predicate<"Subtarget->hasDivide()">, AssemblerPredicate;
162 def HasT2ExtractPack : Predicate<"Subtarget->hasT2ExtractPack()">,
164 def HasDB : Predicate<"Subtarget->hasDataBarrier()">,
166 def HasMP : Predicate<"Subtarget->hasMPExtension()">,
168 def UseNEONForFP : Predicate<"Subtarget->useNEONForSinglePrecisionFP()">;
169 def DontUseNEONForFP : Predicate<"!Subtarget->useNEONForSinglePrecisionFP()">;
170 def IsThumb : Predicate<"Subtarget->isThumb()">, AssemblerPredicate;
171 def IsThumb1Only : Predicate<"Subtarget->isThumb1Only()">;
172 def IsThumb2 : Predicate<"Subtarget->isThumb2()">, AssemblerPredicate;
173 def IsARM : Predicate<"!Subtarget->isThumb()">, AssemblerPredicate;
174 def IsDarwin : Predicate<"Subtarget->isTargetDarwin()">;
175 def IsNotDarwin : Predicate<"!Subtarget->isTargetDarwin()">;
177 // FIXME: Eventually this will be just "hasV6T2Ops".
178 def UseMovt : Predicate<"Subtarget->useMovt()">;
179 def DontUseMovt : Predicate<"!Subtarget->useMovt()">;
180 def UseFPVMLx : Predicate<"Subtarget->useFPVMLx()">;
182 //===----------------------------------------------------------------------===//
183 // ARM Flag Definitions.
185 class RegConstraint<string C> {
186 string Constraints = C;
189 //===----------------------------------------------------------------------===//
190 // ARM specific transformation functions and pattern fragments.
193 // so_imm_neg_XFORM - Return a so_imm value packed into the format described for
194 // so_imm_neg def below.
195 def so_imm_neg_XFORM : SDNodeXForm<imm, [{
196 return CurDAG->getTargetConstant(-(int)N->getZExtValue(), MVT::i32);
199 // so_imm_not_XFORM - Return a so_imm value packed into the format described for
200 // so_imm_not def below.
201 def so_imm_not_XFORM : SDNodeXForm<imm, [{
202 return CurDAG->getTargetConstant(~(int)N->getZExtValue(), MVT::i32);
205 /// imm1_15 predicate - True if the 32-bit immediate is in the range [1,15].
206 def imm1_15 : PatLeaf<(i32 imm), [{
207 return (int32_t)N->getZExtValue() >= 1 && (int32_t)N->getZExtValue() < 16;
210 /// imm16_31 predicate - True if the 32-bit immediate is in the range [16,31].
211 def imm16_31 : PatLeaf<(i32 imm), [{
212 return (int32_t)N->getZExtValue() >= 16 && (int32_t)N->getZExtValue() < 32;
217 return ARM_AM::getSOImmVal(-(uint32_t)N->getZExtValue()) != -1;
218 }], so_imm_neg_XFORM>;
222 return ARM_AM::getSOImmVal(~(uint32_t)N->getZExtValue()) != -1;
223 }], so_imm_not_XFORM>;
225 // sext_16_node predicate - True if the SDNode is sign-extended 16 or more bits.
226 def sext_16_node : PatLeaf<(i32 GPR:$a), [{
227 return CurDAG->ComputeNumSignBits(SDValue(N,0)) >= 17;
230 /// Split a 32-bit immediate into two 16 bit parts.
231 def hi16 : SDNodeXForm<imm, [{
232 return CurDAG->getTargetConstant((uint32_t)N->getZExtValue() >> 16, MVT::i32);
235 def lo16AllZero : PatLeaf<(i32 imm), [{
236 // Returns true if all low 16-bits are 0.
237 return (((uint32_t)N->getZExtValue()) & 0xFFFFUL) == 0;
240 /// imm0_65535 predicate - True if the 32-bit immediate is in the range
242 def imm0_65535 : PatLeaf<(i32 imm), [{
243 return (uint32_t)N->getZExtValue() < 65536;
246 class BinOpFrag<dag res> : PatFrag<(ops node:$LHS, node:$RHS), res>;
247 class UnOpFrag <dag res> : PatFrag<(ops node:$Src), res>;
249 /// adde and sube predicates - True based on whether the carry flag output
250 /// will be needed or not.
251 def adde_dead_carry :
252 PatFrag<(ops node:$LHS, node:$RHS), (adde node:$LHS, node:$RHS),
253 [{return !N->hasAnyUseOfValue(1);}]>;
254 def sube_dead_carry :
255 PatFrag<(ops node:$LHS, node:$RHS), (sube node:$LHS, node:$RHS),
256 [{return !N->hasAnyUseOfValue(1);}]>;
257 def adde_live_carry :
258 PatFrag<(ops node:$LHS, node:$RHS), (adde node:$LHS, node:$RHS),
259 [{return N->hasAnyUseOfValue(1);}]>;
260 def sube_live_carry :
261 PatFrag<(ops node:$LHS, node:$RHS), (sube node:$LHS, node:$RHS),
262 [{return N->hasAnyUseOfValue(1);}]>;
264 // An 'and' node with a single use.
265 def and_su : PatFrag<(ops node:$lhs, node:$rhs), (and node:$lhs, node:$rhs), [{
266 return N->hasOneUse();
269 // An 'xor' node with a single use.
270 def xor_su : PatFrag<(ops node:$lhs, node:$rhs), (xor node:$lhs, node:$rhs), [{
271 return N->hasOneUse();
274 // An 'fmul' node with a single use.
275 def fmul_su : PatFrag<(ops node:$lhs, node:$rhs), (fmul node:$lhs, node:$rhs),[{
276 return N->hasOneUse();
279 // An 'fadd' node which checks for single non-hazardous use.
280 def fadd_mlx : PatFrag<(ops node:$lhs, node:$rhs),(fadd node:$lhs, node:$rhs),[{
281 return hasNoVMLxHazardUse(N);
284 // An 'fsub' node which checks for single non-hazardous use.
285 def fsub_mlx : PatFrag<(ops node:$lhs, node:$rhs),(fsub node:$lhs, node:$rhs),[{
286 return hasNoVMLxHazardUse(N);
289 //===----------------------------------------------------------------------===//
290 // Operand Definitions.
294 // FIXME: rename brtarget to t2_brtarget
295 def brtarget : Operand<OtherVT> {
296 let EncoderMethod = "getBranchTargetOpValue";
299 // FIXME: get rid of this one?
300 def uncondbrtarget : Operand<OtherVT> {
301 let EncoderMethod = "getUnconditionalBranchTargetOpValue";
304 // Branch target for ARM. Handles conditional/unconditional
305 def br_target : Operand<OtherVT> {
306 let EncoderMethod = "getARMBranchTargetOpValue";
310 // FIXME: rename bltarget to t2_bl_target?
311 def bltarget : Operand<i32> {
312 // Encoded the same as branch targets.
313 let EncoderMethod = "getBranchTargetOpValue";
316 // Call target for ARM. Handles conditional/unconditional
317 // FIXME: rename bl_target to t2_bltarget?
318 def bl_target : Operand<i32> {
319 // Encoded the same as branch targets.
320 let EncoderMethod = "getARMBranchTargetOpValue";
324 // A list of registers separated by comma. Used by load/store multiple.
325 def RegListAsmOperand : AsmOperandClass {
326 let Name = "RegList";
327 let SuperClasses = [];
330 def DPRRegListAsmOperand : AsmOperandClass {
331 let Name = "DPRRegList";
332 let SuperClasses = [];
335 def SPRRegListAsmOperand : AsmOperandClass {
336 let Name = "SPRRegList";
337 let SuperClasses = [];
340 def reglist : Operand<i32> {
341 let EncoderMethod = "getRegisterListOpValue";
342 let ParserMatchClass = RegListAsmOperand;
343 let PrintMethod = "printRegisterList";
346 def dpr_reglist : Operand<i32> {
347 let EncoderMethod = "getRegisterListOpValue";
348 let ParserMatchClass = DPRRegListAsmOperand;
349 let PrintMethod = "printRegisterList";
352 def spr_reglist : Operand<i32> {
353 let EncoderMethod = "getRegisterListOpValue";
354 let ParserMatchClass = SPRRegListAsmOperand;
355 let PrintMethod = "printRegisterList";
358 // An operand for the CONSTPOOL_ENTRY pseudo-instruction.
359 def cpinst_operand : Operand<i32> {
360 let PrintMethod = "printCPInstOperand";
364 def pclabel : Operand<i32> {
365 let PrintMethod = "printPCLabel";
368 // ADR instruction labels.
369 def adrlabel : Operand<i32> {
370 let EncoderMethod = "getAdrLabelOpValue";
373 def neon_vcvt_imm32 : Operand<i32> {
374 let EncoderMethod = "getNEONVcvtImm32OpValue";
377 // rot_imm: An integer that encodes a rotate amount. Must be 8, 16, or 24.
378 def rot_imm : Operand<i32>, PatLeaf<(i32 imm), [{
379 int32_t v = (int32_t)N->getZExtValue();
380 return v == 8 || v == 16 || v == 24; }]> {
381 let EncoderMethod = "getRotImmOpValue";
384 def ShifterAsmOperand : AsmOperandClass {
385 let Name = "Shifter";
386 let SuperClasses = [];
389 // shift_imm: An integer that encodes a shift amount and the type of shift
390 // (currently either asr or lsl) using the same encoding used for the
391 // immediates in so_reg operands.
392 def shift_imm : Operand<i32> {
393 let PrintMethod = "printShiftImmOperand";
394 let ParserMatchClass = ShifterAsmOperand;
397 // shifter_operand operands: so_reg and so_imm.
398 def so_reg : Operand<i32>, // reg reg imm
399 ComplexPattern<i32, 3, "SelectShifterOperandReg",
400 [shl,srl,sra,rotr]> {
401 let EncoderMethod = "getSORegOpValue";
402 let PrintMethod = "printSORegOperand";
403 let MIOperandInfo = (ops GPR, GPR, shift_imm);
405 def shift_so_reg : Operand<i32>, // reg reg imm
406 ComplexPattern<i32, 3, "SelectShiftShifterOperandReg",
407 [shl,srl,sra,rotr]> {
408 let EncoderMethod = "getSORegOpValue";
409 let PrintMethod = "printSORegOperand";
410 let MIOperandInfo = (ops GPR, GPR, shift_imm);
413 // so_imm - Match a 32-bit shifter_operand immediate operand, which is an
414 // 8-bit immediate rotated by an arbitrary number of bits.
415 def so_imm : Operand<i32>, PatLeaf<(imm), [{ return Pred_so_imm(N); }]> {
416 let EncoderMethod = "getSOImmOpValue";
417 let PrintMethod = "printSOImmOperand";
420 // Break so_imm's up into two pieces. This handles immediates with up to 16
421 // bits set in them. This uses so_imm2part to match and so_imm2part_[12] to
422 // get the first/second pieces.
423 def so_imm2part : PatLeaf<(imm), [{
424 return ARM_AM::isSOImmTwoPartVal((unsigned)N->getZExtValue());
427 /// arm_i32imm - True for +V6T2, or true only if so_imm2part is true.
429 def arm_i32imm : PatLeaf<(imm), [{
430 if (Subtarget->hasV6T2Ops())
432 return ARM_AM::isSOImmTwoPartVal((unsigned)N->getZExtValue());
435 /// imm0_31 predicate - True if the 32-bit immediate is in the range [0,31].
436 def imm0_31 : Operand<i32>, PatLeaf<(imm), [{
437 return (int32_t)N->getZExtValue() < 32;
440 /// imm0_31_m1 - Matches and prints like imm0_31, but encodes as 'value - 1'.
441 def imm0_31_m1 : Operand<i32>, PatLeaf<(imm), [{
442 return (int32_t)N->getZExtValue() < 32;
444 let EncoderMethod = "getImmMinusOneOpValue";
447 // i32imm_hilo16 - For movt/movw - sets the MC Encoder method.
448 // The imm is split into imm{15-12}, imm{11-0}
450 def i32imm_hilo16 : Operand<i32> {
451 let EncoderMethod = "getHiLo16ImmOpValue";
454 /// bf_inv_mask_imm predicate - An AND mask to clear an arbitrary width bitfield
456 def bf_inv_mask_imm : Operand<i32>,
458 return ARM::isBitFieldInvertedMask(N->getZExtValue());
460 let EncoderMethod = "getBitfieldInvertedMaskOpValue";
461 let PrintMethod = "printBitfieldInvMaskImmOperand";
464 /// lsb_pos_imm - position of the lsb bit, used by BFI4p and t2BFI4p
465 def lsb_pos_imm : Operand<i32>, PatLeaf<(imm), [{
466 return isInt<5>(N->getSExtValue());
469 /// width_imm - number of bits to be copied, used by BFI4p and t2BFI4p
470 def width_imm : Operand<i32>, PatLeaf<(imm), [{
471 return N->getSExtValue() > 0 && N->getSExtValue() <= 32;
473 let EncoderMethod = "getMsbOpValue";
476 // Define ARM specific addressing modes.
478 def MemMode2AsmOperand : AsmOperandClass {
479 let Name = "MemMode2";
480 let SuperClasses = [];
481 let ParserMethod = "tryParseMemMode2Operand";
484 def MemMode3AsmOperand : AsmOperandClass {
485 let Name = "MemMode3";
486 let SuperClasses = [];
487 let ParserMethod = "tryParseMemMode3Operand";
490 // addrmode_imm12 := reg +/- imm12
492 def addrmode_imm12 : Operand<i32>,
493 ComplexPattern<i32, 2, "SelectAddrModeImm12", []> {
494 // 12-bit immediate operand. Note that instructions using this encode
495 // #0 and #-0 differently. We flag #-0 as the magic value INT32_MIN. All other
496 // immediate values are as normal.
498 let EncoderMethod = "getAddrModeImm12OpValue";
499 let PrintMethod = "printAddrModeImm12Operand";
500 let MIOperandInfo = (ops GPR:$base, i32imm:$offsimm);
502 // ldst_so_reg := reg +/- reg shop imm
504 def ldst_so_reg : Operand<i32>,
505 ComplexPattern<i32, 3, "SelectLdStSOReg", []> {
506 let EncoderMethod = "getLdStSORegOpValue";
507 // FIXME: Simplify the printer
508 let PrintMethod = "printAddrMode2Operand";
509 let MIOperandInfo = (ops GPR:$base, GPR:$offsreg, i32imm:$offsimm);
512 // addrmode2 := reg +/- imm12
513 // := reg +/- reg shop imm
515 def addrmode2 : Operand<i32>,
516 ComplexPattern<i32, 3, "SelectAddrMode2", []> {
517 let EncoderMethod = "getAddrMode2OpValue";
518 let PrintMethod = "printAddrMode2Operand";
519 let ParserMatchClass = MemMode2AsmOperand;
520 let MIOperandInfo = (ops GPR:$base, GPR:$offsreg, i32imm:$offsimm);
523 def am2offset : Operand<i32>,
524 ComplexPattern<i32, 2, "SelectAddrMode2Offset",
525 [], [SDNPWantRoot]> {
526 let EncoderMethod = "getAddrMode2OffsetOpValue";
527 let PrintMethod = "printAddrMode2OffsetOperand";
528 let MIOperandInfo = (ops GPR, i32imm);
531 // addrmode3 := reg +/- reg
532 // addrmode3 := reg +/- imm8
534 def addrmode3 : Operand<i32>,
535 ComplexPattern<i32, 3, "SelectAddrMode3", []> {
536 let EncoderMethod = "getAddrMode3OpValue";
537 let PrintMethod = "printAddrMode3Operand";
538 let ParserMatchClass = MemMode3AsmOperand;
539 let MIOperandInfo = (ops GPR:$base, GPR:$offsreg, i32imm:$offsimm);
542 def am3offset : Operand<i32>,
543 ComplexPattern<i32, 2, "SelectAddrMode3Offset",
544 [], [SDNPWantRoot]> {
545 let EncoderMethod = "getAddrMode3OffsetOpValue";
546 let PrintMethod = "printAddrMode3OffsetOperand";
547 let MIOperandInfo = (ops GPR, i32imm);
550 // ldstm_mode := {ia, ib, da, db}
552 def ldstm_mode : OptionalDefOperand<OtherVT, (ops i32), (ops (i32 1))> {
553 let EncoderMethod = "getLdStmModeOpValue";
554 let PrintMethod = "printLdStmModeOperand";
557 def MemMode5AsmOperand : AsmOperandClass {
558 let Name = "MemMode5";
559 let SuperClasses = [];
562 // addrmode5 := reg +/- imm8*4
564 def addrmode5 : Operand<i32>,
565 ComplexPattern<i32, 2, "SelectAddrMode5", []> {
566 let PrintMethod = "printAddrMode5Operand";
567 let MIOperandInfo = (ops GPR:$base, i32imm);
568 let ParserMatchClass = MemMode5AsmOperand;
569 let EncoderMethod = "getAddrMode5OpValue";
572 // addrmode6 := reg with optional alignment
574 def addrmode6 : Operand<i32>,
575 ComplexPattern<i32, 2, "SelectAddrMode6", [], [SDNPWantParent]>{
576 let PrintMethod = "printAddrMode6Operand";
577 let MIOperandInfo = (ops GPR:$addr, i32imm);
578 let EncoderMethod = "getAddrMode6AddressOpValue";
581 def am6offset : Operand<i32>,
582 ComplexPattern<i32, 1, "SelectAddrMode6Offset",
583 [], [SDNPWantRoot]> {
584 let PrintMethod = "printAddrMode6OffsetOperand";
585 let MIOperandInfo = (ops GPR);
586 let EncoderMethod = "getAddrMode6OffsetOpValue";
589 // Special version of addrmode6 to handle alignment encoding for VLD-dup
590 // instructions, specifically VLD4-dup.
591 def addrmode6dup : Operand<i32>,
592 ComplexPattern<i32, 2, "SelectAddrMode6", [], [SDNPWantParent]>{
593 let PrintMethod = "printAddrMode6Operand";
594 let MIOperandInfo = (ops GPR:$addr, i32imm);
595 let EncoderMethod = "getAddrMode6DupAddressOpValue";
598 // addrmodepc := pc + reg
600 def addrmodepc : Operand<i32>,
601 ComplexPattern<i32, 2, "SelectAddrModePC", []> {
602 let PrintMethod = "printAddrModePCOperand";
603 let MIOperandInfo = (ops GPR, i32imm);
606 def MemMode7AsmOperand : AsmOperandClass {
607 let Name = "MemMode7";
608 let SuperClasses = [];
612 // Used by load/store exclusive instructions. Useful to enable right assembly
613 // parsing and printing. Not used for any codegen matching.
615 def addrmode7 : Operand<i32> {
616 let PrintMethod = "printAddrMode7Operand";
617 let MIOperandInfo = (ops GPR);
618 let ParserMatchClass = MemMode7AsmOperand;
621 def nohash_imm : Operand<i32> {
622 let PrintMethod = "printNoHashImmediate";
625 def CoprocNumAsmOperand : AsmOperandClass {
626 let Name = "CoprocNum";
627 let SuperClasses = [];
628 let ParserMethod = "tryParseCoprocNumOperand";
631 def CoprocRegAsmOperand : AsmOperandClass {
632 let Name = "CoprocReg";
633 let SuperClasses = [];
634 let ParserMethod = "tryParseCoprocRegOperand";
637 def p_imm : Operand<i32> {
638 let PrintMethod = "printPImmediate";
639 let ParserMatchClass = CoprocNumAsmOperand;
642 def c_imm : Operand<i32> {
643 let PrintMethod = "printCImmediate";
644 let ParserMatchClass = CoprocRegAsmOperand;
647 //===----------------------------------------------------------------------===//
649 include "ARMInstrFormats.td"
651 //===----------------------------------------------------------------------===//
652 // Multiclass helpers...
655 /// AsI1_bin_irs - Defines a set of (op r, {so_imm|r|so_reg}) patterns for a
656 /// binop that produces a value.
657 multiclass AsI1_bin_irs<bits<4> opcod, string opc,
658 InstrItinClass iii, InstrItinClass iir, InstrItinClass iis,
659 PatFrag opnode, bit Commutable = 0> {
660 // The register-immediate version is re-materializable. This is useful
661 // in particular for taking the address of a local.
662 let isReMaterializable = 1 in {
663 def ri : AsI1<opcod, (outs GPR:$Rd), (ins GPR:$Rn, so_imm:$imm), DPFrm,
664 iii, opc, "\t$Rd, $Rn, $imm",
665 [(set GPR:$Rd, (opnode GPR:$Rn, so_imm:$imm))]> {
670 let Inst{19-16} = Rn;
671 let Inst{15-12} = Rd;
672 let Inst{11-0} = imm;
675 def rr : AsI1<opcod, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm), DPFrm,
676 iir, opc, "\t$Rd, $Rn, $Rm",
677 [(set GPR:$Rd, (opnode GPR:$Rn, GPR:$Rm))]> {
682 let isCommutable = Commutable;
683 let Inst{19-16} = Rn;
684 let Inst{15-12} = Rd;
685 let Inst{11-4} = 0b00000000;
688 def rs : AsI1<opcod, (outs GPR:$Rd), (ins GPR:$Rn, so_reg:$shift), DPSoRegFrm,
689 iis, opc, "\t$Rd, $Rn, $shift",
690 [(set GPR:$Rd, (opnode GPR:$Rn, so_reg:$shift))]> {
695 let Inst{19-16} = Rn;
696 let Inst{15-12} = Rd;
697 let Inst{11-0} = shift;
701 /// AI1_bin_s_irs - Similar to AsI1_bin_irs except it sets the 's' bit so the
702 /// instruction modifies the CPSR register.
703 let isCodeGenOnly = 1, Defs = [CPSR] in {
704 multiclass AI1_bin_s_irs<bits<4> opcod, string opc,
705 InstrItinClass iii, InstrItinClass iir, InstrItinClass iis,
706 PatFrag opnode, bit Commutable = 0> {
707 def ri : AI1<opcod, (outs GPR:$Rd), (ins GPR:$Rn, so_imm:$imm), DPFrm,
708 iii, opc, "\t$Rd, $Rn, $imm",
709 [(set GPR:$Rd, (opnode GPR:$Rn, so_imm:$imm))]> {
715 let Inst{19-16} = Rn;
716 let Inst{15-12} = Rd;
717 let Inst{11-0} = imm;
719 def rr : AI1<opcod, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm), DPFrm,
720 iir, opc, "\t$Rd, $Rn, $Rm",
721 [(set GPR:$Rd, (opnode GPR:$Rn, GPR:$Rm))]> {
725 let isCommutable = Commutable;
728 let Inst{19-16} = Rn;
729 let Inst{15-12} = Rd;
730 let Inst{11-4} = 0b00000000;
733 def rs : AI1<opcod, (outs GPR:$Rd), (ins GPR:$Rn, so_reg:$shift), DPSoRegFrm,
734 iis, opc, "\t$Rd, $Rn, $shift",
735 [(set GPR:$Rd, (opnode GPR:$Rn, so_reg:$shift))]> {
741 let Inst{19-16} = Rn;
742 let Inst{15-12} = Rd;
743 let Inst{11-0} = shift;
748 /// AI1_cmp_irs - Defines a set of (op r, {so_imm|r|so_reg}) cmp / test
749 /// patterns. Similar to AsI1_bin_irs except the instruction does not produce
750 /// a explicit result, only implicitly set CPSR.
751 let isCompare = 1, Defs = [CPSR] in {
752 multiclass AI1_cmp_irs<bits<4> opcod, string opc,
753 InstrItinClass iii, InstrItinClass iir, InstrItinClass iis,
754 PatFrag opnode, bit Commutable = 0> {
755 def ri : AI1<opcod, (outs), (ins GPR:$Rn, so_imm:$imm), DPFrm, iii,
757 [(opnode GPR:$Rn, so_imm:$imm)]> {
762 let Inst{19-16} = Rn;
763 let Inst{15-12} = 0b0000;
764 let Inst{11-0} = imm;
766 def rr : AI1<opcod, (outs), (ins GPR:$Rn, GPR:$Rm), DPFrm, iir,
768 [(opnode GPR:$Rn, GPR:$Rm)]> {
771 let isCommutable = Commutable;
774 let Inst{19-16} = Rn;
775 let Inst{15-12} = 0b0000;
776 let Inst{11-4} = 0b00000000;
779 def rs : AI1<opcod, (outs), (ins GPR:$Rn, so_reg:$shift), DPSoRegFrm, iis,
780 opc, "\t$Rn, $shift",
781 [(opnode GPR:$Rn, so_reg:$shift)]> {
786 let Inst{19-16} = Rn;
787 let Inst{15-12} = 0b0000;
788 let Inst{11-0} = shift;
793 /// AI_ext_rrot - A unary operation with two forms: one whose operand is a
794 /// register and one whose operand is a register rotated by 8/16/24.
795 /// FIXME: Remove the 'r' variant. Its rot_imm is zero.
796 multiclass AI_ext_rrot<bits<8> opcod, string opc, PatFrag opnode> {
797 def r : AExtI<opcod, (outs GPR:$Rd), (ins GPR:$Rm),
798 IIC_iEXTr, opc, "\t$Rd, $Rm",
799 [(set GPR:$Rd, (opnode GPR:$Rm))]>,
800 Requires<[IsARM, HasV6]> {
803 let Inst{19-16} = 0b1111;
804 let Inst{15-12} = Rd;
805 let Inst{11-10} = 0b00;
808 def r_rot : AExtI<opcod, (outs GPR:$Rd), (ins GPR:$Rm, rot_imm:$rot),
809 IIC_iEXTr, opc, "\t$Rd, $Rm, ror $rot",
810 [(set GPR:$Rd, (opnode (rotr GPR:$Rm, rot_imm:$rot)))]>,
811 Requires<[IsARM, HasV6]> {
815 let Inst{19-16} = 0b1111;
816 let Inst{15-12} = Rd;
817 let Inst{11-10} = rot;
822 multiclass AI_ext_rrot_np<bits<8> opcod, string opc> {
823 def r : AExtI<opcod, (outs GPR:$Rd), (ins GPR:$Rm),
824 IIC_iEXTr, opc, "\t$Rd, $Rm",
825 [/* For disassembly only; pattern left blank */]>,
826 Requires<[IsARM, HasV6]> {
827 let Inst{19-16} = 0b1111;
828 let Inst{11-10} = 0b00;
830 def r_rot : AExtI<opcod, (outs GPR:$Rd), (ins GPR:$Rm, rot_imm:$rot),
831 IIC_iEXTr, opc, "\t$Rd, $Rm, ror $rot",
832 [/* For disassembly only; pattern left blank */]>,
833 Requires<[IsARM, HasV6]> {
835 let Inst{19-16} = 0b1111;
836 let Inst{11-10} = rot;
840 /// AI_exta_rrot - A binary operation with two forms: one whose operand is a
841 /// register and one whose operand is a register rotated by 8/16/24.
842 multiclass AI_exta_rrot<bits<8> opcod, string opc, PatFrag opnode> {
843 def rr : AExtI<opcod, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm),
844 IIC_iEXTAr, opc, "\t$Rd, $Rn, $Rm",
845 [(set GPR:$Rd, (opnode GPR:$Rn, GPR:$Rm))]>,
846 Requires<[IsARM, HasV6]> {
850 let Inst{19-16} = Rn;
851 let Inst{15-12} = Rd;
852 let Inst{11-10} = 0b00;
853 let Inst{9-4} = 0b000111;
856 def rr_rot : AExtI<opcod, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm,
858 IIC_iEXTAr, opc, "\t$Rd, $Rn, $Rm, ror $rot",
859 [(set GPR:$Rd, (opnode GPR:$Rn,
860 (rotr GPR:$Rm, rot_imm:$rot)))]>,
861 Requires<[IsARM, HasV6]> {
866 let Inst{19-16} = Rn;
867 let Inst{15-12} = Rd;
868 let Inst{11-10} = rot;
869 let Inst{9-4} = 0b000111;
874 // For disassembly only.
875 multiclass AI_exta_rrot_np<bits<8> opcod, string opc> {
876 def rr : AExtI<opcod, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm),
877 IIC_iEXTAr, opc, "\t$Rd, $Rn, $Rm",
878 [/* For disassembly only; pattern left blank */]>,
879 Requires<[IsARM, HasV6]> {
880 let Inst{11-10} = 0b00;
882 def rr_rot : AExtI<opcod, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm,
884 IIC_iEXTAr, opc, "\t$Rd, $Rn, $Rm, ror $rot",
885 [/* For disassembly only; pattern left blank */]>,
886 Requires<[IsARM, HasV6]> {
889 let Inst{19-16} = Rn;
890 let Inst{11-10} = rot;
894 /// AI1_adde_sube_irs - Define instructions and patterns for adde and sube.
895 let Uses = [CPSR] in {
896 multiclass AI1_adde_sube_irs<bits<4> opcod, string opc, PatFrag opnode,
897 bit Commutable = 0> {
898 def ri : AsI1<opcod, (outs GPR:$Rd), (ins GPR:$Rn, so_imm:$imm),
899 DPFrm, IIC_iALUi, opc, "\t$Rd, $Rn, $imm",
900 [(set GPR:$Rd, (opnode GPR:$Rn, so_imm:$imm))]>,
906 let Inst{15-12} = Rd;
907 let Inst{19-16} = Rn;
908 let Inst{11-0} = imm;
910 def rr : AsI1<opcod, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm),
911 DPFrm, IIC_iALUr, opc, "\t$Rd, $Rn, $Rm",
912 [(set GPR:$Rd, (opnode GPR:$Rn, GPR:$Rm))]>,
917 let Inst{11-4} = 0b00000000;
919 let isCommutable = Commutable;
921 let Inst{15-12} = Rd;
922 let Inst{19-16} = Rn;
924 def rs : AsI1<opcod, (outs GPR:$Rd), (ins GPR:$Rn, so_reg:$shift),
925 DPSoRegFrm, IIC_iALUsr, opc, "\t$Rd, $Rn, $shift",
926 [(set GPR:$Rd, (opnode GPR:$Rn, so_reg:$shift))]>,
932 let Inst{11-0} = shift;
933 let Inst{15-12} = Rd;
934 let Inst{19-16} = Rn;
937 // Carry setting variants
938 let isCodeGenOnly = 1, Defs = [CPSR] in {
939 multiclass AI1_adde_sube_s_irs<PatFrag opnode, bit Commutable = 0> {
940 def Sri : ARMPseudoInst<(outs GPR:$Rd), (ins GPR:$Rn, so_imm:$imm),
941 Size4Bytes, IIC_iALUi,
942 [(set GPR:$Rd, (opnode GPR:$Rn, so_imm:$imm))]>,
944 def Srr : ARMPseudoInst<(outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm),
945 Size4Bytes, IIC_iALUr,
946 [(set GPR:$Rd, (opnode GPR:$Rn, GPR:$Rm))]>,
948 def Srs : ARMPseudoInst<(outs GPR:$Rd), (ins GPR:$Rn, so_reg:$shift),
949 Size4Bytes, IIC_iALUsr,
950 [(set GPR:$Rd, (opnode GPR:$Rn, so_reg:$shift))]>,
956 let canFoldAsLoad = 1, isReMaterializable = 1 in {
957 multiclass AI_ldr1<bit isByte, string opc, InstrItinClass iii,
958 InstrItinClass iir, PatFrag opnode> {
959 // Note: We use the complex addrmode_imm12 rather than just an input
960 // GPR and a constrained immediate so that we can use this to match
961 // frame index references and avoid matching constant pool references.
962 def i12: AI2ldst<0b010, 1, isByte, (outs GPR:$Rt), (ins addrmode_imm12:$addr),
963 AddrMode_i12, LdFrm, iii, opc, "\t$Rt, $addr",
964 [(set GPR:$Rt, (opnode addrmode_imm12:$addr))]> {
967 let Inst{23} = addr{12}; // U (add = ('U' == 1))
968 let Inst{19-16} = addr{16-13}; // Rn
969 let Inst{15-12} = Rt;
970 let Inst{11-0} = addr{11-0}; // imm12
972 def rs : AI2ldst<0b011, 1, isByte, (outs GPR:$Rt), (ins ldst_so_reg:$shift),
973 AddrModeNone, LdFrm, iir, opc, "\t$Rt, $shift",
974 [(set GPR:$Rt, (opnode ldst_so_reg:$shift))]> {
977 let shift{4} = 0; // Inst{4} = 0
978 let Inst{23} = shift{12}; // U (add = ('U' == 1))
979 let Inst{19-16} = shift{16-13}; // Rn
980 let Inst{15-12} = Rt;
981 let Inst{11-0} = shift{11-0};
986 multiclass AI_str1<bit isByte, string opc, InstrItinClass iii,
987 InstrItinClass iir, PatFrag opnode> {
988 // Note: We use the complex addrmode_imm12 rather than just an input
989 // GPR and a constrained immediate so that we can use this to match
990 // frame index references and avoid matching constant pool references.
991 def i12 : AI2ldst<0b010, 0, isByte, (outs),
992 (ins GPR:$Rt, addrmode_imm12:$addr),
993 AddrMode_i12, StFrm, iii, opc, "\t$Rt, $addr",
994 [(opnode GPR:$Rt, addrmode_imm12:$addr)]> {
997 let Inst{23} = addr{12}; // U (add = ('U' == 1))
998 let Inst{19-16} = addr{16-13}; // Rn
999 let Inst{15-12} = Rt;
1000 let Inst{11-0} = addr{11-0}; // imm12
1002 def rs : AI2ldst<0b011, 0, isByte, (outs), (ins GPR:$Rt, ldst_so_reg:$shift),
1003 AddrModeNone, StFrm, iir, opc, "\t$Rt, $shift",
1004 [(opnode GPR:$Rt, ldst_so_reg:$shift)]> {
1007 let shift{4} = 0; // Inst{4} = 0
1008 let Inst{23} = shift{12}; // U (add = ('U' == 1))
1009 let Inst{19-16} = shift{16-13}; // Rn
1010 let Inst{15-12} = Rt;
1011 let Inst{11-0} = shift{11-0};
1014 //===----------------------------------------------------------------------===//
1016 //===----------------------------------------------------------------------===//
1018 //===----------------------------------------------------------------------===//
1019 // Miscellaneous Instructions.
1022 /// CONSTPOOL_ENTRY - This instruction represents a floating constant pool in
1023 /// the function. The first operand is the ID# for this instruction, the second
1024 /// is the index into the MachineConstantPool that this is, the third is the
1025 /// size in bytes of this constant pool entry.
1026 let neverHasSideEffects = 1, isNotDuplicable = 1 in
1027 def CONSTPOOL_ENTRY :
1028 PseudoInst<(outs), (ins cpinst_operand:$instid, cpinst_operand:$cpidx,
1029 i32imm:$size), NoItinerary, []>;
1031 // FIXME: Marking these as hasSideEffects is necessary to prevent machine DCE
1032 // from removing one half of the matched pairs. That breaks PEI, which assumes
1033 // these will always be in pairs, and asserts if it finds otherwise. Better way?
1034 let Defs = [SP], Uses = [SP], hasSideEffects = 1 in {
1035 def ADJCALLSTACKUP :
1036 PseudoInst<(outs), (ins i32imm:$amt1, i32imm:$amt2, pred:$p), NoItinerary,
1037 [(ARMcallseq_end timm:$amt1, timm:$amt2)]>;
1039 def ADJCALLSTACKDOWN :
1040 PseudoInst<(outs), (ins i32imm:$amt, pred:$p), NoItinerary,
1041 [(ARMcallseq_start timm:$amt)]>;
1044 def NOP : AI<(outs), (ins), MiscFrm, NoItinerary, "nop", "",
1045 [/* For disassembly only; pattern left blank */]>,
1046 Requires<[IsARM, HasV6T2]> {
1047 let Inst{27-16} = 0b001100100000;
1048 let Inst{15-8} = 0b11110000;
1049 let Inst{7-0} = 0b00000000;
1052 def YIELD : AI<(outs), (ins), MiscFrm, NoItinerary, "yield", "",
1053 [/* For disassembly only; pattern left blank */]>,
1054 Requires<[IsARM, HasV6T2]> {
1055 let Inst{27-16} = 0b001100100000;
1056 let Inst{15-8} = 0b11110000;
1057 let Inst{7-0} = 0b00000001;
1060 def WFE : AI<(outs), (ins), MiscFrm, NoItinerary, "wfe", "",
1061 [/* For disassembly only; pattern left blank */]>,
1062 Requires<[IsARM, HasV6T2]> {
1063 let Inst{27-16} = 0b001100100000;
1064 let Inst{15-8} = 0b11110000;
1065 let Inst{7-0} = 0b00000010;
1068 def WFI : AI<(outs), (ins), MiscFrm, NoItinerary, "wfi", "",
1069 [/* For disassembly only; pattern left blank */]>,
1070 Requires<[IsARM, HasV6T2]> {
1071 let Inst{27-16} = 0b001100100000;
1072 let Inst{15-8} = 0b11110000;
1073 let Inst{7-0} = 0b00000011;
1076 def SEL : AI<(outs GPR:$dst), (ins GPR:$a, GPR:$b), DPFrm, NoItinerary, "sel",
1078 [/* For disassembly only; pattern left blank */]>,
1079 Requires<[IsARM, HasV6]> {
1084 let Inst{15-12} = Rd;
1085 let Inst{19-16} = Rn;
1086 let Inst{27-20} = 0b01101000;
1087 let Inst{7-4} = 0b1011;
1088 let Inst{11-8} = 0b1111;
1091 def SEV : AI<(outs), (ins), MiscFrm, NoItinerary, "sev", "",
1092 [/* For disassembly only; pattern left blank */]>,
1093 Requires<[IsARM, HasV6T2]> {
1094 let Inst{27-16} = 0b001100100000;
1095 let Inst{15-8} = 0b11110000;
1096 let Inst{7-0} = 0b00000100;
1099 // The i32imm operand $val can be used by a debugger to store more information
1100 // about the breakpoint.
1101 def BKPT : AI<(outs), (ins i32imm:$val), MiscFrm, NoItinerary, "bkpt", "\t$val",
1102 [/* For disassembly only; pattern left blank */]>,
1105 let Inst{3-0} = val{3-0};
1106 let Inst{19-8} = val{15-4};
1107 let Inst{27-20} = 0b00010010;
1108 let Inst{7-4} = 0b0111;
1111 // Change Processor State is a system instruction -- for disassembly and
1113 // FIXME: Since the asm parser has currently no clean way to handle optional
1114 // operands, create 3 versions of the same instruction. Once there's a clean
1115 // framework to represent optional operands, change this behavior.
1116 class CPS<dag iops, string asm_ops>
1117 : AXI<(outs), iops, MiscFrm, NoItinerary, !strconcat("cps", asm_ops),
1118 [/* For disassembly only; pattern left blank */]>, Requires<[IsARM]> {
1124 let Inst{31-28} = 0b1111;
1125 let Inst{27-20} = 0b00010000;
1126 let Inst{19-18} = imod;
1127 let Inst{17} = M; // Enabled if mode is set;
1129 let Inst{8-6} = iflags;
1131 let Inst{4-0} = mode;
1135 def CPS3p : CPS<(ins imod_op:$imod, iflags_op:$iflags, i32imm:$mode),
1136 "$imod\t$iflags, $mode">;
1137 let mode = 0, M = 0 in
1138 def CPS2p : CPS<(ins imod_op:$imod, iflags_op:$iflags), "$imod\t$iflags">;
1140 let imod = 0, iflags = 0, M = 1 in
1141 def CPS1p : CPS<(ins i32imm:$mode), "\t$mode">;
1143 // Preload signals the memory system of possible future data/instruction access.
1144 // These are for disassembly only.
1145 multiclass APreLoad<bits<1> read, bits<1> data, string opc> {
1147 def i12 : AXI<(outs), (ins addrmode_imm12:$addr), MiscFrm, IIC_Preload,
1148 !strconcat(opc, "\t$addr"),
1149 [(ARMPreload addrmode_imm12:$addr, (i32 read), (i32 data))]> {
1152 let Inst{31-26} = 0b111101;
1153 let Inst{25} = 0; // 0 for immediate form
1154 let Inst{24} = data;
1155 let Inst{23} = addr{12}; // U (add = ('U' == 1))
1156 let Inst{22} = read;
1157 let Inst{21-20} = 0b01;
1158 let Inst{19-16} = addr{16-13}; // Rn
1159 let Inst{15-12} = 0b1111;
1160 let Inst{11-0} = addr{11-0}; // imm12
1163 def rs : AXI<(outs), (ins ldst_so_reg:$shift), MiscFrm, IIC_Preload,
1164 !strconcat(opc, "\t$shift"),
1165 [(ARMPreload ldst_so_reg:$shift, (i32 read), (i32 data))]> {
1167 let Inst{31-26} = 0b111101;
1168 let Inst{25} = 1; // 1 for register form
1169 let Inst{24} = data;
1170 let Inst{23} = shift{12}; // U (add = ('U' == 1))
1171 let Inst{22} = read;
1172 let Inst{21-20} = 0b01;
1173 let Inst{19-16} = shift{16-13}; // Rn
1174 let Inst{15-12} = 0b1111;
1175 let Inst{11-0} = shift{11-0};
1179 defm PLD : APreLoad<1, 1, "pld">, Requires<[IsARM]>;
1180 defm PLDW : APreLoad<0, 1, "pldw">, Requires<[IsARM,HasV7,HasMP]>;
1181 defm PLI : APreLoad<1, 0, "pli">, Requires<[IsARM,HasV7]>;
1183 def SETEND : AXI<(outs),(ins setend_op:$end), MiscFrm, NoItinerary,
1185 [/* For disassembly only; pattern left blank */]>,
1188 let Inst{31-10} = 0b1111000100000001000000;
1193 def DBG : AI<(outs), (ins i32imm:$opt), MiscFrm, NoItinerary, "dbg", "\t$opt",
1194 [/* For disassembly only; pattern left blank */]>,
1195 Requires<[IsARM, HasV7]> {
1197 let Inst{27-4} = 0b001100100000111100001111;
1198 let Inst{3-0} = opt;
1201 // A5.4 Permanently UNDEFINED instructions.
1202 let isBarrier = 1, isTerminator = 1 in
1203 def TRAP : AXI<(outs), (ins), MiscFrm, NoItinerary,
1206 let Inst = 0xe7ffdefe;
1209 // Address computation and loads and stores in PIC mode.
1210 let isNotDuplicable = 1 in {
1211 def PICADD : ARMPseudoInst<(outs GPR:$dst), (ins GPR:$a, pclabel:$cp, pred:$p),
1212 Size4Bytes, IIC_iALUr,
1213 [(set GPR:$dst, (ARMpic_add GPR:$a, imm:$cp))]>;
1215 let AddedComplexity = 10 in {
1216 def PICLDR : ARMPseudoInst<(outs GPR:$dst), (ins addrmodepc:$addr, pred:$p),
1217 Size4Bytes, IIC_iLoad_r,
1218 [(set GPR:$dst, (load addrmodepc:$addr))]>;
1220 def PICLDRH : ARMPseudoInst<(outs GPR:$Rt), (ins addrmodepc:$addr, pred:$p),
1221 Size4Bytes, IIC_iLoad_bh_r,
1222 [(set GPR:$Rt, (zextloadi16 addrmodepc:$addr))]>;
1224 def PICLDRB : ARMPseudoInst<(outs GPR:$Rt), (ins addrmodepc:$addr, pred:$p),
1225 Size4Bytes, IIC_iLoad_bh_r,
1226 [(set GPR:$Rt, (zextloadi8 addrmodepc:$addr))]>;
1228 def PICLDRSH : ARMPseudoInst<(outs GPR:$Rt), (ins addrmodepc:$addr, pred:$p),
1229 Size4Bytes, IIC_iLoad_bh_r,
1230 [(set GPR:$Rt, (sextloadi16 addrmodepc:$addr))]>;
1232 def PICLDRSB : ARMPseudoInst<(outs GPR:$Rt), (ins addrmodepc:$addr, pred:$p),
1233 Size4Bytes, IIC_iLoad_bh_r,
1234 [(set GPR:$Rt, (sextloadi8 addrmodepc:$addr))]>;
1236 let AddedComplexity = 10 in {
1237 def PICSTR : ARMPseudoInst<(outs), (ins GPR:$src, addrmodepc:$addr, pred:$p),
1238 Size4Bytes, IIC_iStore_r, [(store GPR:$src, addrmodepc:$addr)]>;
1240 def PICSTRH : ARMPseudoInst<(outs), (ins GPR:$src, addrmodepc:$addr, pred:$p),
1241 Size4Bytes, IIC_iStore_bh_r, [(truncstorei16 GPR:$src,
1242 addrmodepc:$addr)]>;
1244 def PICSTRB : ARMPseudoInst<(outs), (ins GPR:$src, addrmodepc:$addr, pred:$p),
1245 Size4Bytes, IIC_iStore_bh_r, [(truncstorei8 GPR:$src, addrmodepc:$addr)]>;
1247 } // isNotDuplicable = 1
1250 // LEApcrel - Load a pc-relative address into a register without offending the
1252 let neverHasSideEffects = 1, isReMaterializable = 1 in
1253 // The 'adr' mnemonic encodes differently if the label is before or after
1254 // the instruction. The {24-21} opcode bits are set by the fixup, as we don't
1255 // know until then which form of the instruction will be used.
1256 def ADR : AI1<{0,?,?,0}, (outs GPR:$Rd), (ins adrlabel:$label),
1257 MiscFrm, IIC_iALUi, "adr", "\t$Rd, #$label", []> {
1260 let Inst{27-25} = 0b001;
1262 let Inst{19-16} = 0b1111;
1263 let Inst{15-12} = Rd;
1264 let Inst{11-0} = label;
1266 def LEApcrel : ARMPseudoInst<(outs GPR:$Rd), (ins i32imm:$label, pred:$p),
1267 Size4Bytes, IIC_iALUi, []>;
1269 def LEApcrelJT : ARMPseudoInst<(outs GPR:$Rd),
1270 (ins i32imm:$label, nohash_imm:$id, pred:$p),
1271 Size4Bytes, IIC_iALUi, []>;
1273 //===----------------------------------------------------------------------===//
1274 // Control Flow Instructions.
1277 let isReturn = 1, isTerminator = 1, isBarrier = 1 in {
1279 def BX_RET : AI<(outs), (ins), BrMiscFrm, IIC_Br,
1280 "bx", "\tlr", [(ARMretflag)]>,
1281 Requires<[IsARM, HasV4T]> {
1282 let Inst{27-0} = 0b0001001011111111111100011110;
1286 def MOVPCLR : AI<(outs), (ins), BrMiscFrm, IIC_Br,
1287 "mov", "\tpc, lr", [(ARMretflag)]>,
1288 Requires<[IsARM, NoV4T]> {
1289 let Inst{27-0} = 0b0001101000001111000000001110;
1293 // Indirect branches
1294 let isBranch = 1, isTerminator = 1, isBarrier = 1, isIndirectBranch = 1 in {
1296 def BX : AXI<(outs), (ins GPR:$dst), BrMiscFrm, IIC_Br, "bx\t$dst",
1297 [(brind GPR:$dst)]>,
1298 Requires<[IsARM, HasV4T]> {
1300 let Inst{31-4} = 0b1110000100101111111111110001;
1301 let Inst{3-0} = dst;
1305 // FIXME: We would really like to define this as a vanilla ARMPat like:
1306 // ARMPat<(brind GPR:$dst), (MOVr PC, GPR:$dst)>
1307 // With that, however, we can't set isBranch, isTerminator, etc..
1308 def MOVPCRX : ARMPseudoInst<(outs), (ins GPR:$dst),
1309 Size4Bytes, IIC_Br, [(brind GPR:$dst)]>,
1310 Requires<[IsARM, NoV4T]>;
1313 // All calls clobber the non-callee saved registers. SP is marked as
1314 // a use to prevent stack-pointer assignments that appear immediately
1315 // before calls from potentially appearing dead.
1317 // On non-Darwin platforms R9 is callee-saved.
1318 // FIXME: Do we really need a non-predicated version? If so, it should
1319 // at least be a pseudo instruction expanding to the predicated version
1320 // at MC lowering time.
1321 Defs = [R0, R1, R2, R3, R12, LR,
1322 D0, D1, D2, D3, D4, D5, D6, D7,
1323 D16, D17, D18, D19, D20, D21, D22, D23,
1324 D24, D25, D26, D27, D28, D29, D30, D31, CPSR, FPSCR],
1326 def BL : ABXI<0b1011, (outs), (ins bl_target:$func, variable_ops),
1327 IIC_Br, "bl\t$func",
1328 [(ARMcall tglobaladdr:$func)]>,
1329 Requires<[IsARM, IsNotDarwin]> {
1330 let Inst{31-28} = 0b1110;
1332 let Inst{23-0} = func;
1335 def BL_pred : ABI<0b1011, (outs), (ins bl_target:$func, variable_ops),
1336 IIC_Br, "bl", "\t$func",
1337 [(ARMcall_pred tglobaladdr:$func)]>,
1338 Requires<[IsARM, IsNotDarwin]> {
1340 let Inst{23-0} = func;
1344 def BLX : AXI<(outs), (ins GPR:$func, variable_ops), BrMiscFrm,
1345 IIC_Br, "blx\t$func",
1346 [(ARMcall GPR:$func)]>,
1347 Requires<[IsARM, HasV5T, IsNotDarwin]> {
1349 let Inst{31-4} = 0b1110000100101111111111110011;
1350 let Inst{3-0} = func;
1353 def BLX_pred : AI<(outs), (ins GPR:$func, variable_ops), BrMiscFrm,
1354 IIC_Br, "blx", "\t$func",
1355 [(ARMcall_pred GPR:$func)]>,
1356 Requires<[IsARM, HasV5T, IsNotDarwin]> {
1358 let Inst{27-4} = 0b000100101111111111110011;
1359 let Inst{3-0} = func;
1363 // Note: Restrict $func to the tGPR regclass to prevent it being in LR.
1364 def BX_CALL : ARMPseudoInst<(outs), (ins tGPR:$func, variable_ops),
1365 Size8Bytes, IIC_Br, [(ARMcall_nolink tGPR:$func)]>,
1366 Requires<[IsARM, HasV4T, IsNotDarwin]>;
1369 def BMOVPCRX_CALL : ARMPseudoInst<(outs), (ins tGPR:$func, variable_ops),
1370 Size8Bytes, IIC_Br, [(ARMcall_nolink tGPR:$func)]>,
1371 Requires<[IsARM, NoV4T, IsNotDarwin]>;
1375 // On Darwin R9 is call-clobbered.
1376 // R7 is marked as a use to prevent frame-pointer assignments from being
1377 // moved above / below calls.
1378 Defs = [R0, R1, R2, R3, R9, R12, LR,
1379 D0, D1, D2, D3, D4, D5, D6, D7,
1380 D16, D17, D18, D19, D20, D21, D22, D23,
1381 D24, D25, D26, D27, D28, D29, D30, D31, CPSR, FPSCR],
1382 Uses = [R7, SP] in {
1383 def BLr9 : ARMPseudoInst<(outs), (ins bltarget:$func, variable_ops),
1385 [(ARMcall tglobaladdr:$func)]>, Requires<[IsARM, IsDarwin]>;
1387 def BLr9_pred : ARMPseudoInst<(outs),
1388 (ins bltarget:$func, pred:$p, variable_ops),
1390 [(ARMcall_pred tglobaladdr:$func)]>,
1391 Requires<[IsARM, IsDarwin]>;
1394 def BLXr9 : ARMPseudoInst<(outs), (ins GPR:$func, variable_ops),
1396 [(ARMcall GPR:$func)]>, Requires<[IsARM, HasV5T, IsDarwin]>;
1398 def BLXr9_pred: ARMPseudoInst<(outs), (ins GPR:$func, pred:$p, variable_ops),
1400 [(ARMcall_pred GPR:$func)]>,
1401 Requires<[IsARM, HasV5T, IsDarwin]>;
1404 // Note: Restrict $func to the tGPR regclass to prevent it being in LR.
1405 def BXr9_CALL : ARMPseudoInst<(outs), (ins tGPR:$func, variable_ops),
1406 Size8Bytes, IIC_Br, [(ARMcall_nolink tGPR:$func)]>,
1407 Requires<[IsARM, HasV4T, IsDarwin]>;
1410 def BMOVPCRXr9_CALL : ARMPseudoInst<(outs), (ins tGPR:$func, variable_ops),
1411 Size8Bytes, IIC_Br, [(ARMcall_nolink tGPR:$func)]>,
1412 Requires<[IsARM, NoV4T, IsDarwin]>;
1417 // FIXME: The Thumb versions of these should live in ARMInstrThumb.td
1418 let isCall = 1, isTerminator = 1, isReturn = 1, isBarrier = 1 in {
1420 let Defs = [R0, R1, R2, R3, R9, R12,
1421 D0, D1, D2, D3, D4, D5, D6, D7,
1422 D16, D17, D18, D19, D20, D21, D22, D23, D24, D25, D26,
1423 D27, D28, D29, D30, D31, PC],
1425 def TCRETURNdi : PseudoInst<(outs), (ins i32imm:$dst, variable_ops),
1426 IIC_Br, []>, Requires<[IsDarwin]>;
1428 def TCRETURNri : PseudoInst<(outs), (ins tcGPR:$dst, variable_ops),
1429 IIC_Br, []>, Requires<[IsDarwin]>;
1431 def TAILJMPd : ARMPseudoInst<(outs), (ins brtarget:$dst, variable_ops),
1433 []>, Requires<[IsARM, IsDarwin]>;
1435 def tTAILJMPd: tPseudoInst<(outs), (ins brtarget:$dst, variable_ops),
1437 []>, Requires<[IsThumb, IsDarwin]>;
1439 def TAILJMPr : ARMPseudoInst<(outs), (ins tcGPR:$dst, variable_ops),
1441 []>, Requires<[IsARM, IsDarwin]>;
1443 def tTAILJMPr : tPseudoInst<(outs), (ins tcGPR:$dst, variable_ops),
1445 []>, Requires<[IsThumb, IsDarwin]>;
1448 // Non-Darwin versions (the difference is R9).
1449 let Defs = [R0, R1, R2, R3, R12,
1450 D0, D1, D2, D3, D4, D5, D6, D7,
1451 D16, D17, D18, D19, D20, D21, D22, D23, D24, D25, D26,
1452 D27, D28, D29, D30, D31, PC],
1454 def TCRETURNdiND : PseudoInst<(outs), (ins i32imm:$dst, variable_ops),
1455 IIC_Br, []>, Requires<[IsNotDarwin]>;
1457 def TCRETURNriND : PseudoInst<(outs), (ins tcGPR:$dst, variable_ops),
1458 IIC_Br, []>, Requires<[IsNotDarwin]>;
1460 def TAILJMPdND : ARMPseudoInst<(outs), (ins brtarget:$dst, variable_ops),
1462 []>, Requires<[IsARM, IsNotDarwin]>;
1464 def tTAILJMPdND : tPseudoInst<(outs), (ins brtarget:$dst, variable_ops),
1466 []>, Requires<[IsThumb, IsNotDarwin]>;
1468 def TAILJMPrND : ARMPseudoInst<(outs), (ins tcGPR:$dst, variable_ops),
1470 []>, Requires<[IsARM, IsNotDarwin]>;
1471 def tTAILJMPrND : tPseudoInst<(outs), (ins tcGPR:$dst, variable_ops),
1473 []>, Requires<[IsThumb, IsNotDarwin]>;
1477 let isBranch = 1, isTerminator = 1 in {
1478 // B is "predicable" since it's just a Bcc with an 'always' condition.
1479 let isBarrier = 1 in {
1480 let isPredicable = 1 in
1481 // FIXME: We shouldn't need this pseudo at all. Just using Bcc directly
1482 // should be sufficient.
1483 def B : ARMPseudoInst<(outs), (ins brtarget:$target), Size4Bytes, IIC_Br,
1486 let isNotDuplicable = 1, isIndirectBranch = 1 in {
1487 def BR_JTr : ARMPseudoInst<(outs),
1488 (ins GPR:$target, i32imm:$jt, i32imm:$id),
1489 SizeSpecial, IIC_Br,
1490 [(ARMbrjt GPR:$target, tjumptable:$jt, imm:$id)]>;
1491 // FIXME: This shouldn't use the generic "addrmode2," but rather be split
1492 // into i12 and rs suffixed versions.
1493 def BR_JTm : ARMPseudoInst<(outs),
1494 (ins addrmode2:$target, i32imm:$jt, i32imm:$id),
1495 SizeSpecial, IIC_Br,
1496 [(ARMbrjt (i32 (load addrmode2:$target)), tjumptable:$jt,
1498 def BR_JTadd : ARMPseudoInst<(outs),
1499 (ins GPR:$target, GPR:$idx, i32imm:$jt, i32imm:$id),
1500 SizeSpecial, IIC_Br,
1501 [(ARMbrjt (add GPR:$target, GPR:$idx), tjumptable:$jt,
1503 } // isNotDuplicable = 1, isIndirectBranch = 1
1506 // FIXME: should be able to write a pattern for ARMBrcond, but can't use
1507 // a two-value operand where a dag node expects two operands. :(
1508 def Bcc : ABI<0b1010, (outs), (ins br_target:$target),
1509 IIC_Br, "b", "\t$target",
1510 [/*(ARMbrcond bb:$target, imm:$cc, CCR:$ccr)*/]> {
1512 let Inst{23-0} = target;
1516 // BLX (immediate) -- for disassembly only
1517 def BLXi : AXI<(outs), (ins br_target:$target), BrMiscFrm, NoItinerary,
1518 "blx\t$target", [/* pattern left blank */]>,
1519 Requires<[IsARM, HasV5T]> {
1520 let Inst{31-25} = 0b1111101;
1522 let Inst{23-0} = target{24-1};
1523 let Inst{24} = target{0};
1526 // Branch and Exchange Jazelle -- for disassembly only
1527 def BXJ : ABI<0b0001, (outs), (ins GPR:$func), NoItinerary, "bxj", "\t$func",
1528 [/* For disassembly only; pattern left blank */]> {
1529 let Inst{23-20} = 0b0010;
1530 //let Inst{19-8} = 0xfff;
1531 let Inst{7-4} = 0b0010;
1534 // Secure Monitor Call is a system instruction -- for disassembly only
1535 def SMC : ABI<0b0001, (outs), (ins i32imm:$opt), NoItinerary, "smc", "\t$opt",
1536 [/* For disassembly only; pattern left blank */]> {
1538 let Inst{23-4} = 0b01100000000000000111;
1539 let Inst{3-0} = opt;
1542 // Supervisor Call (Software Interrupt) -- for disassembly only
1543 let isCall = 1, Uses = [SP] in {
1544 def SVC : ABI<0b1111, (outs), (ins i32imm:$svc), IIC_Br, "svc", "\t$svc",
1545 [/* For disassembly only; pattern left blank */]> {
1547 let Inst{23-0} = svc;
1550 def : MnemonicAlias<"swi", "svc">;
1552 // Store Return State is a system instruction -- for disassembly only
1553 let isCodeGenOnly = 1 in { // FIXME: This should not use submode!
1554 def SRSW : ABXI<{1,0,0,?}, (outs), (ins ldstm_mode:$amode, i32imm:$mode),
1555 NoItinerary, "srs${amode}\tsp!, $mode",
1556 [/* For disassembly only; pattern left blank */]> {
1557 let Inst{31-28} = 0b1111;
1558 let Inst{22-20} = 0b110; // W = 1
1559 let Inst{19-8} = 0xd05;
1560 let Inst{7-5} = 0b000;
1563 def SRS : ABXI<{1,0,0,?}, (outs), (ins ldstm_mode:$amode, i32imm:$mode),
1564 NoItinerary, "srs${amode}\tsp, $mode",
1565 [/* For disassembly only; pattern left blank */]> {
1566 let Inst{31-28} = 0b1111;
1567 let Inst{22-20} = 0b100; // W = 0
1568 let Inst{19-8} = 0xd05;
1569 let Inst{7-5} = 0b000;
1572 // Return From Exception is a system instruction -- for disassembly only
1573 def RFEW : ABXI<{1,0,0,?}, (outs), (ins ldstm_mode:$amode, GPR:$base),
1574 NoItinerary, "rfe${amode}\t$base!",
1575 [/* For disassembly only; pattern left blank */]> {
1576 let Inst{31-28} = 0b1111;
1577 let Inst{22-20} = 0b011; // W = 1
1578 let Inst{15-0} = 0x0a00;
1581 def RFE : ABXI<{1,0,0,?}, (outs), (ins ldstm_mode:$amode, GPR:$base),
1582 NoItinerary, "rfe${amode}\t$base",
1583 [/* For disassembly only; pattern left blank */]> {
1584 let Inst{31-28} = 0b1111;
1585 let Inst{22-20} = 0b001; // W = 0
1586 let Inst{15-0} = 0x0a00;
1588 } // isCodeGenOnly = 1
1590 //===----------------------------------------------------------------------===//
1591 // Load / store Instructions.
1597 defm LDR : AI_ldr1<0, "ldr", IIC_iLoad_r, IIC_iLoad_si,
1598 UnOpFrag<(load node:$Src)>>;
1599 defm LDRB : AI_ldr1<1, "ldrb", IIC_iLoad_bh_r, IIC_iLoad_bh_si,
1600 UnOpFrag<(zextloadi8 node:$Src)>>;
1601 defm STR : AI_str1<0, "str", IIC_iStore_r, IIC_iStore_si,
1602 BinOpFrag<(store node:$LHS, node:$RHS)>>;
1603 defm STRB : AI_str1<1, "strb", IIC_iStore_bh_r, IIC_iStore_bh_si,
1604 BinOpFrag<(truncstorei8 node:$LHS, node:$RHS)>>;
1606 // Special LDR for loads from non-pc-relative constpools.
1607 let canFoldAsLoad = 1, mayLoad = 1, neverHasSideEffects = 1,
1608 isReMaterializable = 1 in
1609 def LDRcp : AI2ldst<0b010, 1, 0, (outs GPR:$Rt), (ins addrmode_imm12:$addr),
1610 AddrMode_i12, LdFrm, IIC_iLoad_r, "ldr", "\t$Rt, $addr",
1614 let Inst{23} = addr{12}; // U (add = ('U' == 1))
1615 let Inst{19-16} = 0b1111;
1616 let Inst{15-12} = Rt;
1617 let Inst{11-0} = addr{11-0}; // imm12
1620 // Loads with zero extension
1621 def LDRH : AI3ld<0b1011, 1, (outs GPR:$Rt), (ins addrmode3:$addr), LdMiscFrm,
1622 IIC_iLoad_bh_r, "ldrh", "\t$Rt, $addr",
1623 [(set GPR:$Rt, (zextloadi16 addrmode3:$addr))]>;
1625 // Loads with sign extension
1626 def LDRSH : AI3ld<0b1111, 1, (outs GPR:$Rt), (ins addrmode3:$addr), LdMiscFrm,
1627 IIC_iLoad_bh_r, "ldrsh", "\t$Rt, $addr",
1628 [(set GPR:$Rt, (sextloadi16 addrmode3:$addr))]>;
1630 def LDRSB : AI3ld<0b1101, 1, (outs GPR:$Rt), (ins addrmode3:$addr), LdMiscFrm,
1631 IIC_iLoad_bh_r, "ldrsb", "\t$Rt, $addr",
1632 [(set GPR:$Rt, (sextloadi8 addrmode3:$addr))]>;
1634 let mayLoad = 1, neverHasSideEffects = 1 in {
1636 def LDRD : AI3ld<0b1101, 0, (outs GPR:$Rd, GPR:$dst2),
1637 (ins addrmode3:$addr), LdMiscFrm,
1638 IIC_iLoad_d_r, "ldrd", "\t$Rd, $dst2, $addr",
1639 []>, Requires<[IsARM, HasV5TE]>;
1643 multiclass AI2_ldridx<bit isByte, string opc, InstrItinClass itin> {
1644 def _PRE : AI2ldstidx<1, isByte, 1, (outs GPR:$Rt, GPR:$Rn_wb),
1645 (ins addrmode2:$addr), IndexModePre, LdFrm, itin,
1646 opc, "\t$Rt, $addr!", "$addr.base = $Rn_wb", []> {
1648 // {13} 1 == Rm, 0 == imm12
1652 let Inst{25} = addr{13};
1653 let Inst{23} = addr{12};
1654 let Inst{19-16} = addr{17-14};
1655 let Inst{11-0} = addr{11-0};
1656 let AsmMatchConverter = "CvtLdWriteBackRegAddrMode2";
1658 def _POST : AI2ldstidx<1, isByte, 0, (outs GPR:$Rt, GPR:$Rn_wb),
1659 (ins GPR:$Rn, am2offset:$offset),
1660 IndexModePost, LdFrm, itin,
1661 opc, "\t$Rt, [$Rn], $offset", "$Rn = $Rn_wb", []> {
1662 // {13} 1 == Rm, 0 == imm12
1667 let Inst{25} = offset{13};
1668 let Inst{23} = offset{12};
1669 let Inst{19-16} = Rn;
1670 let Inst{11-0} = offset{11-0};
1674 let mayLoad = 1, neverHasSideEffects = 1 in {
1675 defm LDR : AI2_ldridx<0, "ldr", IIC_iLoad_ru>;
1676 defm LDRB : AI2_ldridx<1, "ldrb", IIC_iLoad_bh_ru>;
1679 multiclass AI3_ldridx<bits<4> op, bit op20, string opc, InstrItinClass itin> {
1680 def _PRE : AI3ldstidx<op, op20, 1, 1, (outs GPR:$Rt, GPR:$Rn_wb),
1681 (ins addrmode3:$addr), IndexModePre,
1683 opc, "\t$Rt, $addr!", "$addr.base = $Rn_wb", []> {
1685 let Inst{23} = addr{8}; // U bit
1686 let Inst{22} = addr{13}; // 1 == imm8, 0 == Rm
1687 let Inst{19-16} = addr{12-9}; // Rn
1688 let Inst{11-8} = addr{7-4}; // imm7_4/zero
1689 let Inst{3-0} = addr{3-0}; // imm3_0/Rm
1691 def _POST : AI3ldstidx<op, op20, 1, 0, (outs GPR:$Rt, GPR:$Rn_wb),
1692 (ins GPR:$Rn, am3offset:$offset), IndexModePost,
1694 opc, "\t$Rt, [$Rn], $offset", "$Rn = $Rn_wb", []> {
1697 let Inst{23} = offset{8}; // U bit
1698 let Inst{22} = offset{9}; // 1 == imm8, 0 == Rm
1699 let Inst{19-16} = Rn;
1700 let Inst{11-8} = offset{7-4}; // imm7_4/zero
1701 let Inst{3-0} = offset{3-0}; // imm3_0/Rm
1705 let mayLoad = 1, neverHasSideEffects = 1 in {
1706 defm LDRH : AI3_ldridx<0b1011, 1, "ldrh", IIC_iLoad_bh_ru>;
1707 defm LDRSH : AI3_ldridx<0b1111, 1, "ldrsh", IIC_iLoad_bh_ru>;
1708 defm LDRSB : AI3_ldridx<0b1101, 1, "ldrsb", IIC_iLoad_bh_ru>;
1709 def LDRD_PRE : AI3ldstidx<0b1101, 0, 1, 1, (outs GPR:$Rt, GPR:$Rt2, GPR:$Rn_wb),
1710 (ins addrmode3:$addr), IndexModePre,
1711 LdMiscFrm, IIC_iLoad_d_ru,
1712 "ldrd", "\t$Rt, $Rt2, $addr!",
1713 "$addr.base = $Rn_wb", []> {
1715 let Inst{23} = addr{8}; // U bit
1716 let Inst{22} = addr{13}; // 1 == imm8, 0 == Rm
1717 let Inst{19-16} = addr{12-9}; // Rn
1718 let Inst{11-8} = addr{7-4}; // imm7_4/zero
1719 let Inst{3-0} = addr{3-0}; // imm3_0/Rm
1721 def LDRD_POST: AI3ldstidx<0b1101, 0, 1, 0, (outs GPR:$Rt, GPR:$Rt2, GPR:$Rn_wb),
1722 (ins GPR:$Rn, am3offset:$offset), IndexModePost,
1723 LdMiscFrm, IIC_iLoad_d_ru,
1724 "ldrd", "\t$Rt, $Rt2, [$Rn], $offset",
1725 "$Rn = $Rn_wb", []> {
1728 let Inst{23} = offset{8}; // U bit
1729 let Inst{22} = offset{9}; // 1 == imm8, 0 == Rm
1730 let Inst{19-16} = Rn;
1731 let Inst{11-8} = offset{7-4}; // imm7_4/zero
1732 let Inst{3-0} = offset{3-0}; // imm3_0/Rm
1734 } // mayLoad = 1, neverHasSideEffects = 1
1736 // LDRT, LDRBT, LDRSBT, LDRHT, LDRSHT are for disassembly only.
1737 let mayLoad = 1, neverHasSideEffects = 1 in {
1738 def LDRT : AI2ldstidx<1, 0, 0, (outs GPR:$Rt, GPR:$base_wb),
1739 (ins addrmode2:$addr), IndexModePost, LdFrm, IIC_iLoad_ru,
1740 "ldrt", "\t$Rt, $addr", "$addr.base = $base_wb", []> {
1742 // {13} 1 == Rm, 0 == imm12
1746 let Inst{25} = addr{13};
1747 let Inst{23} = addr{12};
1748 let Inst{21} = 1; // overwrite
1749 let Inst{19-16} = addr{17-14};
1750 let Inst{11-0} = addr{11-0};
1751 let AsmMatchConverter = "CvtLdWriteBackRegAddrMode2";
1753 def LDRBT : AI2ldstidx<1, 1, 0, (outs GPR:$Rt, GPR:$base_wb),
1754 (ins addrmode2:$addr), IndexModePost, LdFrm, IIC_iLoad_bh_ru,
1755 "ldrbt", "\t$Rt, $addr", "$addr.base = $base_wb", []> {
1757 // {13} 1 == Rm, 0 == imm12
1761 let Inst{25} = addr{13};
1762 let Inst{23} = addr{12};
1763 let Inst{21} = 1; // overwrite
1764 let Inst{19-16} = addr{17-14};
1765 let Inst{11-0} = addr{11-0};
1766 let AsmMatchConverter = "CvtLdWriteBackRegAddrMode2";
1768 def LDRSBT : AI3ldstidxT<0b1101, 1, 1, 0, (outs GPR:$Rt, GPR:$base_wb),
1769 (ins addrmode3:$addr), IndexModePost, LdMiscFrm, IIC_iLoad_bh_ru,
1770 "ldrsbt", "\t$Rt, $addr", "$addr.base = $base_wb", []> {
1771 let Inst{21} = 1; // overwrite
1773 def LDRHT : AI3ldstidxT<0b1011, 1, 1, 0, (outs GPR:$Rt, GPR:$base_wb),
1774 (ins addrmode3:$addr), IndexModePost, LdMiscFrm, IIC_iLoad_bh_ru,
1775 "ldrht", "\t$Rt, $addr", "$addr.base = $base_wb", []> {
1776 let Inst{21} = 1; // overwrite
1778 def LDRSHT : AI3ldstidxT<0b1111, 1, 1, 0, (outs GPR:$Rt, GPR:$base_wb),
1779 (ins addrmode3:$addr), IndexModePost, LdMiscFrm, IIC_iLoad_bh_ru,
1780 "ldrsht", "\t$Rt, $addr", "$addr.base = $base_wb", []> {
1781 let Inst{21} = 1; // overwrite
1787 // Stores with truncate
1788 def STRH : AI3str<0b1011, (outs), (ins GPR:$Rt, addrmode3:$addr), StMiscFrm,
1789 IIC_iStore_bh_r, "strh", "\t$Rt, $addr",
1790 [(truncstorei16 GPR:$Rt, addrmode3:$addr)]>;
1793 let mayStore = 1, neverHasSideEffects = 1, hasExtraSrcRegAllocReq = 1 in
1794 def STRD : AI3str<0b1111, (outs), (ins GPR:$Rt, GPR:$src2, addrmode3:$addr),
1795 StMiscFrm, IIC_iStore_d_r,
1796 "strd", "\t$Rt, $src2, $addr", []>, Requires<[IsARM, HasV5TE]>;
1799 def STR_PRE : AI2stridx<0, 1, (outs GPR:$Rn_wb),
1800 (ins GPR:$Rt, GPR:$Rn, am2offset:$offset),
1801 IndexModePre, StFrm, IIC_iStore_ru,
1802 "str", "\t$Rt, [$Rn, $offset]!", "$Rn = $Rn_wb",
1804 (pre_store GPR:$Rt, GPR:$Rn, am2offset:$offset))]>;
1806 def STR_POST : AI2stridx<0, 0, (outs GPR:$Rn_wb),
1807 (ins GPR:$Rt, GPR:$Rn, am2offset:$offset),
1808 IndexModePost, StFrm, IIC_iStore_ru,
1809 "str", "\t$Rt, [$Rn], $offset", "$Rn = $Rn_wb",
1811 (post_store GPR:$Rt, GPR:$Rn, am2offset:$offset))]>;
1813 def STRB_PRE : AI2stridx<1, 1, (outs GPR:$Rn_wb),
1814 (ins GPR:$Rt, GPR:$Rn, am2offset:$offset),
1815 IndexModePre, StFrm, IIC_iStore_bh_ru,
1816 "strb", "\t$Rt, [$Rn, $offset]!", "$Rn = $Rn_wb",
1817 [(set GPR:$Rn_wb, (pre_truncsti8 GPR:$Rt,
1818 GPR:$Rn, am2offset:$offset))]>;
1819 def STRB_POST: AI2stridx<1, 0, (outs GPR:$Rn_wb),
1820 (ins GPR:$Rt, GPR:$Rn, am2offset:$offset),
1821 IndexModePost, StFrm, IIC_iStore_bh_ru,
1822 "strb", "\t$Rt, [$Rn], $offset", "$Rn = $Rn_wb",
1823 [(set GPR:$Rn_wb, (post_truncsti8 GPR:$Rt,
1824 GPR:$Rn, am2offset:$offset))]>;
1826 def STRH_PRE : AI3stridx<0b1011, 0, 1, (outs GPR:$Rn_wb),
1827 (ins GPR:$Rt, GPR:$Rn, am3offset:$offset),
1828 IndexModePre, StMiscFrm, IIC_iStore_ru,
1829 "strh", "\t$Rt, [$Rn, $offset]!", "$Rn = $Rn_wb",
1831 (pre_truncsti16 GPR:$Rt, GPR:$Rn, am3offset:$offset))]>;
1833 def STRH_POST: AI3stridx<0b1011, 0, 0, (outs GPR:$Rn_wb),
1834 (ins GPR:$Rt, GPR:$Rn, am3offset:$offset),
1835 IndexModePost, StMiscFrm, IIC_iStore_bh_ru,
1836 "strh", "\t$Rt, [$Rn], $offset", "$Rn = $Rn_wb",
1837 [(set GPR:$Rn_wb, (post_truncsti16 GPR:$Rt,
1838 GPR:$Rn, am3offset:$offset))]>;
1840 // For disassembly only
1841 def STRD_PRE : AI3stdpr<(outs GPR:$base_wb),
1842 (ins GPR:$src1, GPR:$src2, GPR:$base, am3offset:$offset),
1843 StMiscFrm, IIC_iStore_d_ru,
1844 "strd", "\t$src1, $src2, [$base, $offset]!",
1845 "$base = $base_wb", []>;
1847 // For disassembly only
1848 def STRD_POST: AI3stdpo<(outs GPR:$base_wb),
1849 (ins GPR:$src1, GPR:$src2, GPR:$base, am3offset:$offset),
1850 StMiscFrm, IIC_iStore_d_ru,
1851 "strd", "\t$src1, $src2, [$base], $offset",
1852 "$base = $base_wb", []>;
1854 // STRT, STRBT, and STRHT are for disassembly only.
1856 def STRT : AI2stridxT<0, 0, (outs GPR:$Rn_wb), (ins GPR:$Rt, addrmode2:$addr),
1857 IndexModePost, StFrm, IIC_iStore_ru,
1858 "strt", "\t$Rt, $addr", "$addr.base = $Rn_wb",
1859 [/* For disassembly only; pattern left blank */]> {
1860 let Inst{21} = 1; // overwrite
1861 let AsmMatchConverter = "CvtStWriteBackRegAddrMode2";
1864 def STRBT : AI2stridxT<1, 0, (outs GPR:$Rn_wb), (ins GPR:$Rt, addrmode2:$addr),
1865 IndexModePost, StFrm, IIC_iStore_bh_ru,
1866 "strbt", "\t$Rt, $addr", "$addr.base = $Rn_wb",
1867 [/* For disassembly only; pattern left blank */]> {
1868 let Inst{21} = 1; // overwrite
1869 let AsmMatchConverter = "CvtStWriteBackRegAddrMode2";
1872 def STRHT: AI3sthpo<(outs GPR:$base_wb), (ins GPR:$Rt, addrmode3:$addr),
1873 StMiscFrm, IIC_iStore_bh_ru,
1874 "strht", "\t$Rt, $addr", "$addr.base = $base_wb",
1875 [/* For disassembly only; pattern left blank */]> {
1876 let Inst{21} = 1; // overwrite
1877 let AsmMatchConverter = "CvtStWriteBackRegAddrMode3";
1880 //===----------------------------------------------------------------------===//
1881 // Load / store multiple Instructions.
1884 multiclass arm_ldst_mult<string asm, bit L_bit, Format f,
1885 InstrItinClass itin, InstrItinClass itin_upd> {
1887 AXI4<(outs), (ins GPR:$Rn, pred:$p, reglist:$regs, variable_ops),
1888 IndexModeNone, f, itin,
1889 !strconcat(asm, "ia${p}\t$Rn, $regs"), "", []> {
1890 let Inst{24-23} = 0b01; // Increment After
1891 let Inst{21} = 0; // No writeback
1892 let Inst{20} = L_bit;
1895 AXI4<(outs GPR:$wb), (ins GPR:$Rn, pred:$p, reglist:$regs, variable_ops),
1896 IndexModeUpd, f, itin_upd,
1897 !strconcat(asm, "ia${p}\t$Rn!, $regs"), "$Rn = $wb", []> {
1898 let Inst{24-23} = 0b01; // Increment After
1899 let Inst{21} = 1; // Writeback
1900 let Inst{20} = L_bit;
1903 AXI4<(outs), (ins GPR:$Rn, pred:$p, reglist:$regs, variable_ops),
1904 IndexModeNone, f, itin,
1905 !strconcat(asm, "da${p}\t$Rn, $regs"), "", []> {
1906 let Inst{24-23} = 0b00; // Decrement After
1907 let Inst{21} = 0; // No writeback
1908 let Inst{20} = L_bit;
1911 AXI4<(outs GPR:$wb), (ins GPR:$Rn, pred:$p, reglist:$regs, variable_ops),
1912 IndexModeUpd, f, itin_upd,
1913 !strconcat(asm, "da${p}\t$Rn!, $regs"), "$Rn = $wb", []> {
1914 let Inst{24-23} = 0b00; // Decrement After
1915 let Inst{21} = 1; // Writeback
1916 let Inst{20} = L_bit;
1919 AXI4<(outs), (ins GPR:$Rn, pred:$p, reglist:$regs, variable_ops),
1920 IndexModeNone, f, itin,
1921 !strconcat(asm, "db${p}\t$Rn, $regs"), "", []> {
1922 let Inst{24-23} = 0b10; // Decrement Before
1923 let Inst{21} = 0; // No writeback
1924 let Inst{20} = L_bit;
1927 AXI4<(outs GPR:$wb), (ins GPR:$Rn, pred:$p, reglist:$regs, variable_ops),
1928 IndexModeUpd, f, itin_upd,
1929 !strconcat(asm, "db${p}\t$Rn!, $regs"), "$Rn = $wb", []> {
1930 let Inst{24-23} = 0b10; // Decrement Before
1931 let Inst{21} = 1; // Writeback
1932 let Inst{20} = L_bit;
1935 AXI4<(outs), (ins GPR:$Rn, pred:$p, reglist:$regs, variable_ops),
1936 IndexModeNone, f, itin,
1937 !strconcat(asm, "ib${p}\t$Rn, $regs"), "", []> {
1938 let Inst{24-23} = 0b11; // Increment Before
1939 let Inst{21} = 0; // No writeback
1940 let Inst{20} = L_bit;
1943 AXI4<(outs GPR:$wb), (ins GPR:$Rn, pred:$p, reglist:$regs, variable_ops),
1944 IndexModeUpd, f, itin_upd,
1945 !strconcat(asm, "ib${p}\t$Rn!, $regs"), "$Rn = $wb", []> {
1946 let Inst{24-23} = 0b11; // Increment Before
1947 let Inst{21} = 1; // Writeback
1948 let Inst{20} = L_bit;
1952 let neverHasSideEffects = 1 in {
1954 let mayLoad = 1, hasExtraDefRegAllocReq = 1 in
1955 defm LDM : arm_ldst_mult<"ldm", 1, LdStMulFrm, IIC_iLoad_m, IIC_iLoad_mu>;
1957 let mayStore = 1, hasExtraSrcRegAllocReq = 1 in
1958 defm STM : arm_ldst_mult<"stm", 0, LdStMulFrm, IIC_iStore_m, IIC_iStore_mu>;
1960 } // neverHasSideEffects
1962 // Load / Store Multiple Mnemonic Aliases
1963 def : MnemonicAlias<"ldm", "ldmia">;
1964 def : MnemonicAlias<"stm", "stmia">;
1966 // FIXME: remove when we have a way to marking a MI with these properties.
1967 // FIXME: Should pc be an implicit operand like PICADD, etc?
1968 let isReturn = 1, isTerminator = 1, isBarrier = 1, mayLoad = 1,
1969 hasExtraDefRegAllocReq = 1, isCodeGenOnly = 1 in
1970 def LDMIA_RET : ARMPseudoInst<(outs GPR:$wb), (ins GPR:$Rn, pred:$p,
1971 reglist:$regs, variable_ops),
1972 Size4Bytes, IIC_iLoad_mBr, []>,
1973 RegConstraint<"$Rn = $wb">;
1975 //===----------------------------------------------------------------------===//
1976 // Move Instructions.
1979 let neverHasSideEffects = 1 in
1980 def MOVr : AsI1<0b1101, (outs GPR:$Rd), (ins GPR:$Rm), DPFrm, IIC_iMOVr,
1981 "mov", "\t$Rd, $Rm", []>, UnaryDP {
1985 let Inst{19-16} = 0b0000;
1986 let Inst{11-4} = 0b00000000;
1989 let Inst{15-12} = Rd;
1992 // A version for the smaller set of tail call registers.
1993 let neverHasSideEffects = 1 in
1994 def MOVr_TC : AsI1<0b1101, (outs tcGPR:$Rd), (ins tcGPR:$Rm), DPFrm,
1995 IIC_iMOVr, "mov", "\t$Rd, $Rm", []>, UnaryDP {
1999 let Inst{11-4} = 0b00000000;
2002 let Inst{15-12} = Rd;
2005 def MOVs : AsI1<0b1101, (outs GPR:$Rd), (ins shift_so_reg:$src),
2006 DPSoRegFrm, IIC_iMOVsr,
2007 "mov", "\t$Rd, $src", [(set GPR:$Rd, shift_so_reg:$src)]>,
2011 let Inst{15-12} = Rd;
2012 let Inst{19-16} = 0b0000;
2013 let Inst{11-0} = src;
2017 let isReMaterializable = 1, isAsCheapAsAMove = 1, isMoveImm = 1 in
2018 def MOVi : AsI1<0b1101, (outs GPR:$Rd), (ins so_imm:$imm), DPFrm, IIC_iMOVi,
2019 "mov", "\t$Rd, $imm", [(set GPR:$Rd, so_imm:$imm)]>, UnaryDP {
2023 let Inst{15-12} = Rd;
2024 let Inst{19-16} = 0b0000;
2025 let Inst{11-0} = imm;
2028 let isReMaterializable = 1, isAsCheapAsAMove = 1, isMoveImm = 1 in
2029 def MOVi16 : AI1<0b1000, (outs GPR:$Rd), (ins i32imm_hilo16:$imm),
2031 "movw", "\t$Rd, $imm",
2032 [(set GPR:$Rd, imm0_65535:$imm)]>,
2033 Requires<[IsARM, HasV6T2]>, UnaryDP {
2036 let Inst{15-12} = Rd;
2037 let Inst{11-0} = imm{11-0};
2038 let Inst{19-16} = imm{15-12};
2043 def MOVi16_ga_pcrel : PseudoInst<(outs GPR:$Rd),
2044 (ins i32imm:$addr, pclabel:$id), IIC_iMOVi, []>;
2046 let Constraints = "$src = $Rd" in {
2047 def MOVTi16 : AI1<0b1010, (outs GPR:$Rd), (ins GPR:$src, i32imm_hilo16:$imm),
2049 "movt", "\t$Rd, $imm",
2051 (or (and GPR:$src, 0xffff),
2052 lo16AllZero:$imm))]>, UnaryDP,
2053 Requires<[IsARM, HasV6T2]> {
2056 let Inst{15-12} = Rd;
2057 let Inst{11-0} = imm{11-0};
2058 let Inst{19-16} = imm{15-12};
2063 def MOVTi16_ga_pcrel : PseudoInst<(outs GPR:$Rd),
2064 (ins GPR:$src, i32imm:$addr, pclabel:$id), IIC_iMOVi, []>;
2068 def : ARMPat<(or GPR:$src, 0xffff0000), (MOVTi16 GPR:$src, 0xffff)>,
2069 Requires<[IsARM, HasV6T2]>;
2071 let Uses = [CPSR] in
2072 def RRX: PseudoInst<(outs GPR:$Rd), (ins GPR:$Rm), IIC_iMOVsi,
2073 [(set GPR:$Rd, (ARMrrx GPR:$Rm))]>, UnaryDP,
2076 // These aren't really mov instructions, but we have to define them this way
2077 // due to flag operands.
2079 let Defs = [CPSR] in {
2080 def MOVsrl_flag : PseudoInst<(outs GPR:$dst), (ins GPR:$src), IIC_iMOVsi,
2081 [(set GPR:$dst, (ARMsrl_flag GPR:$src))]>, UnaryDP,
2083 def MOVsra_flag : PseudoInst<(outs GPR:$dst), (ins GPR:$src), IIC_iMOVsi,
2084 [(set GPR:$dst, (ARMsra_flag GPR:$src))]>, UnaryDP,
2088 //===----------------------------------------------------------------------===//
2089 // Extend Instructions.
2094 defm SXTB : AI_ext_rrot<0b01101010,
2095 "sxtb", UnOpFrag<(sext_inreg node:$Src, i8)>>;
2096 defm SXTH : AI_ext_rrot<0b01101011,
2097 "sxth", UnOpFrag<(sext_inreg node:$Src, i16)>>;
2099 defm SXTAB : AI_exta_rrot<0b01101010,
2100 "sxtab", BinOpFrag<(add node:$LHS, (sext_inreg node:$RHS, i8))>>;
2101 defm SXTAH : AI_exta_rrot<0b01101011,
2102 "sxtah", BinOpFrag<(add node:$LHS, (sext_inreg node:$RHS,i16))>>;
2104 // For disassembly only
2105 defm SXTB16 : AI_ext_rrot_np<0b01101000, "sxtb16">;
2107 // For disassembly only
2108 defm SXTAB16 : AI_exta_rrot_np<0b01101000, "sxtab16">;
2112 let AddedComplexity = 16 in {
2113 defm UXTB : AI_ext_rrot<0b01101110,
2114 "uxtb" , UnOpFrag<(and node:$Src, 0x000000FF)>>;
2115 defm UXTH : AI_ext_rrot<0b01101111,
2116 "uxth" , UnOpFrag<(and node:$Src, 0x0000FFFF)>>;
2117 defm UXTB16 : AI_ext_rrot<0b01101100,
2118 "uxtb16", UnOpFrag<(and node:$Src, 0x00FF00FF)>>;
2120 // FIXME: This pattern incorrectly assumes the shl operator is a rotate.
2121 // The transformation should probably be done as a combiner action
2122 // instead so we can include a check for masking back in the upper
2123 // eight bits of the source into the lower eight bits of the result.
2124 //def : ARMV6Pat<(and (shl GPR:$Src, (i32 8)), 0xFF00FF),
2125 // (UXTB16r_rot GPR:$Src, 24)>;
2126 def : ARMV6Pat<(and (srl GPR:$Src, (i32 8)), 0xFF00FF),
2127 (UXTB16r_rot GPR:$Src, 8)>;
2129 defm UXTAB : AI_exta_rrot<0b01101110, "uxtab",
2130 BinOpFrag<(add node:$LHS, (and node:$RHS, 0x00FF))>>;
2131 defm UXTAH : AI_exta_rrot<0b01101111, "uxtah",
2132 BinOpFrag<(add node:$LHS, (and node:$RHS, 0xFFFF))>>;
2135 // This isn't safe in general, the add is two 16-bit units, not a 32-bit add.
2136 // For disassembly only
2137 defm UXTAB16 : AI_exta_rrot_np<0b01101100, "uxtab16">;
2140 def SBFX : I<(outs GPR:$Rd),
2141 (ins GPR:$Rn, imm0_31:$lsb, imm0_31_m1:$width),
2142 AddrMode1, Size4Bytes, IndexModeNone, DPFrm, IIC_iUNAsi,
2143 "sbfx", "\t$Rd, $Rn, $lsb, $width", "", []>,
2144 Requires<[IsARM, HasV6T2]> {
2149 let Inst{27-21} = 0b0111101;
2150 let Inst{6-4} = 0b101;
2151 let Inst{20-16} = width;
2152 let Inst{15-12} = Rd;
2153 let Inst{11-7} = lsb;
2157 def UBFX : I<(outs GPR:$Rd),
2158 (ins GPR:$Rn, imm0_31:$lsb, imm0_31_m1:$width),
2159 AddrMode1, Size4Bytes, IndexModeNone, DPFrm, IIC_iUNAsi,
2160 "ubfx", "\t$Rd, $Rn, $lsb, $width", "", []>,
2161 Requires<[IsARM, HasV6T2]> {
2166 let Inst{27-21} = 0b0111111;
2167 let Inst{6-4} = 0b101;
2168 let Inst{20-16} = width;
2169 let Inst{15-12} = Rd;
2170 let Inst{11-7} = lsb;
2174 //===----------------------------------------------------------------------===//
2175 // Arithmetic Instructions.
2178 defm ADD : AsI1_bin_irs<0b0100, "add",
2179 IIC_iALUi, IIC_iALUr, IIC_iALUsr,
2180 BinOpFrag<(add node:$LHS, node:$RHS)>, 1>;
2181 defm SUB : AsI1_bin_irs<0b0010, "sub",
2182 IIC_iALUi, IIC_iALUr, IIC_iALUsr,
2183 BinOpFrag<(sub node:$LHS, node:$RHS)>>;
2185 // ADD and SUB with 's' bit set.
2186 defm ADDS : AI1_bin_s_irs<0b0100, "adds",
2187 IIC_iALUi, IIC_iALUr, IIC_iALUsr,
2188 BinOpFrag<(addc node:$LHS, node:$RHS)>, 1>;
2189 defm SUBS : AI1_bin_s_irs<0b0010, "subs",
2190 IIC_iALUi, IIC_iALUr, IIC_iALUsr,
2191 BinOpFrag<(subc node:$LHS, node:$RHS)>>;
2193 defm ADC : AI1_adde_sube_irs<0b0101, "adc",
2194 BinOpFrag<(adde_dead_carry node:$LHS, node:$RHS)>, 1>;
2195 defm SBC : AI1_adde_sube_irs<0b0110, "sbc",
2196 BinOpFrag<(sube_dead_carry node:$LHS, node:$RHS)>>;
2198 // ADC and SUBC with 's' bit set.
2199 let usesCustomInserter = 1 in {
2200 defm ADCS : AI1_adde_sube_s_irs<
2201 BinOpFrag<(adde_live_carry node:$LHS, node:$RHS)>, 1>;
2202 defm SBCS : AI1_adde_sube_s_irs<
2203 BinOpFrag<(sube_live_carry node:$LHS, node:$RHS) >>;
2206 def RSBri : AsI1<0b0011, (outs GPR:$Rd), (ins GPR:$Rn, so_imm:$imm), DPFrm,
2207 IIC_iALUi, "rsb", "\t$Rd, $Rn, $imm",
2208 [(set GPR:$Rd, (sub so_imm:$imm, GPR:$Rn))]> {
2213 let Inst{15-12} = Rd;
2214 let Inst{19-16} = Rn;
2215 let Inst{11-0} = imm;
2218 // The reg/reg form is only defined for the disassembler; for codegen it is
2219 // equivalent to SUBrr.
2220 def RSBrr : AsI1<0b0011, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm), DPFrm,
2221 IIC_iALUr, "rsb", "\t$Rd, $Rn, $Rm",
2222 [/* For disassembly only; pattern left blank */]> {
2226 let Inst{11-4} = 0b00000000;
2229 let Inst{15-12} = Rd;
2230 let Inst{19-16} = Rn;
2233 def RSBrs : AsI1<0b0011, (outs GPR:$Rd), (ins GPR:$Rn, so_reg:$shift),
2234 DPSoRegFrm, IIC_iALUsr, "rsb", "\t$Rd, $Rn, $shift",
2235 [(set GPR:$Rd, (sub so_reg:$shift, GPR:$Rn))]> {
2240 let Inst{11-0} = shift;
2241 let Inst{15-12} = Rd;
2242 let Inst{19-16} = Rn;
2245 // RSB with 's' bit set.
2246 let isCodeGenOnly = 1, Defs = [CPSR] in {
2247 def RSBSri : AI1<0b0011, (outs GPR:$Rd), (ins GPR:$Rn, so_imm:$imm), DPFrm,
2248 IIC_iALUi, "rsbs", "\t$Rd, $Rn, $imm",
2249 [(set GPR:$Rd, (subc so_imm:$imm, GPR:$Rn))]> {
2255 let Inst{15-12} = Rd;
2256 let Inst{19-16} = Rn;
2257 let Inst{11-0} = imm;
2259 def RSBSrr : AI1<0b0011, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm), DPFrm,
2260 IIC_iALUr, "rsbs", "\t$Rd, $Rn, $Rm",
2261 [/* For disassembly only; pattern left blank */]> {
2265 let Inst{11-4} = 0b00000000;
2269 let Inst{15-12} = Rd;
2270 let Inst{19-16} = Rn;
2272 def RSBSrs : AI1<0b0011, (outs GPR:$Rd), (ins GPR:$Rn, so_reg:$shift),
2273 DPSoRegFrm, IIC_iALUsr, "rsbs", "\t$Rd, $Rn, $shift",
2274 [(set GPR:$Rd, (subc so_reg:$shift, GPR:$Rn))]> {
2280 let Inst{11-0} = shift;
2281 let Inst{15-12} = Rd;
2282 let Inst{19-16} = Rn;
2286 let Uses = [CPSR] in {
2287 def RSCri : AsI1<0b0111, (outs GPR:$Rd), (ins GPR:$Rn, so_imm:$imm),
2288 DPFrm, IIC_iALUi, "rsc", "\t$Rd, $Rn, $imm",
2289 [(set GPR:$Rd, (sube_dead_carry so_imm:$imm, GPR:$Rn))]>,
2295 let Inst{15-12} = Rd;
2296 let Inst{19-16} = Rn;
2297 let Inst{11-0} = imm;
2299 // The reg/reg form is only defined for the disassembler; for codegen it is
2300 // equivalent to SUBrr.
2301 def RSCrr : AsI1<0b0111, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm),
2302 DPFrm, IIC_iALUr, "rsc", "\t$Rd, $Rn, $Rm",
2303 [/* For disassembly only; pattern left blank */]> {
2307 let Inst{11-4} = 0b00000000;
2310 let Inst{15-12} = Rd;
2311 let Inst{19-16} = Rn;
2313 def RSCrs : AsI1<0b0111, (outs GPR:$Rd), (ins GPR:$Rn, so_reg:$shift),
2314 DPSoRegFrm, IIC_iALUsr, "rsc", "\t$Rd, $Rn, $shift",
2315 [(set GPR:$Rd, (sube_dead_carry so_reg:$shift, GPR:$Rn))]>,
2321 let Inst{11-0} = shift;
2322 let Inst{15-12} = Rd;
2323 let Inst{19-16} = Rn;
2327 // FIXME: Allow these to be predicated.
2328 let isCodeGenOnly = 1, Defs = [CPSR], Uses = [CPSR] in {
2329 def RSCSri : AXI1<0b0111, (outs GPR:$Rd), (ins GPR:$Rn, so_imm:$imm),
2330 DPFrm, IIC_iALUi, "rscs\t$Rd, $Rn, $imm",
2331 [(set GPR:$Rd, (sube_dead_carry so_imm:$imm, GPR:$Rn))]>,
2338 let Inst{15-12} = Rd;
2339 let Inst{19-16} = Rn;
2340 let Inst{11-0} = imm;
2342 def RSCSrs : AXI1<0b0111, (outs GPR:$Rd), (ins GPR:$Rn, so_reg:$shift),
2343 DPSoRegFrm, IIC_iALUsr, "rscs\t$Rd, $Rn, $shift",
2344 [(set GPR:$Rd, (sube_dead_carry so_reg:$shift, GPR:$Rn))]>,
2351 let Inst{11-0} = shift;
2352 let Inst{15-12} = Rd;
2353 let Inst{19-16} = Rn;
2357 // (sub X, imm) gets canonicalized to (add X, -imm). Match this form.
2358 // The assume-no-carry-in form uses the negation of the input since add/sub
2359 // assume opposite meanings of the carry flag (i.e., carry == !borrow).
2360 // See the definition of AddWithCarry() in the ARM ARM A2.2.1 for the gory
2362 def : ARMPat<(add GPR:$src, so_imm_neg:$imm),
2363 (SUBri GPR:$src, so_imm_neg:$imm)>;
2364 def : ARMPat<(addc GPR:$src, so_imm_neg:$imm),
2365 (SUBSri GPR:$src, so_imm_neg:$imm)>;
2366 // The with-carry-in form matches bitwise not instead of the negation.
2367 // Effectively, the inverse interpretation of the carry flag already accounts
2368 // for part of the negation.
2369 def : ARMPat<(adde GPR:$src, so_imm_not:$imm),
2370 (SBCri GPR:$src, so_imm_not:$imm)>;
2372 // Note: These are implemented in C++ code, because they have to generate
2373 // ADD/SUBrs instructions, which use a complex pattern that a xform function
2375 // (mul X, 2^n+1) -> (add (X << n), X)
2376 // (mul X, 2^n-1) -> (rsb X, (X << n))
2378 // ARM Arithmetic Instruction -- for disassembly only
2379 // GPR:$dst = GPR:$a op GPR:$b
2380 class AAI<bits<8> op27_20, bits<8> op11_4, string opc,
2381 list<dag> pattern = [/* For disassembly only; pattern left blank */],
2382 dag iops = (ins GPR:$Rn, GPR:$Rm), string asm = "\t$Rd, $Rn, $Rm">
2383 : AI<(outs GPR:$Rd), iops, DPFrm, IIC_iALUr, opc, asm, pattern> {
2387 let Inst{27-20} = op27_20;
2388 let Inst{11-4} = op11_4;
2389 let Inst{19-16} = Rn;
2390 let Inst{15-12} = Rd;
2394 // Saturating add/subtract -- for disassembly only
2396 def QADD : AAI<0b00010000, 0b00000101, "qadd",
2397 [(set GPR:$Rd, (int_arm_qadd GPR:$Rm, GPR:$Rn))],
2398 (ins GPR:$Rm, GPR:$Rn), "\t$Rd, $Rm, $Rn">;
2399 def QSUB : AAI<0b00010010, 0b00000101, "qsub",
2400 [(set GPR:$Rd, (int_arm_qsub GPR:$Rm, GPR:$Rn))],
2401 (ins GPR:$Rm, GPR:$Rn), "\t$Rd, $Rm, $Rn">;
2402 def QDADD : AAI<0b00010100, 0b00000101, "qdadd", [], (ins GPR:$Rm, GPR:$Rn),
2404 def QDSUB : AAI<0b00010110, 0b00000101, "qdsub", [], (ins GPR:$Rm, GPR:$Rn),
2407 def QADD16 : AAI<0b01100010, 0b11110001, "qadd16">;
2408 def QADD8 : AAI<0b01100010, 0b11111001, "qadd8">;
2409 def QASX : AAI<0b01100010, 0b11110011, "qasx">;
2410 def QSAX : AAI<0b01100010, 0b11110101, "qsax">;
2411 def QSUB16 : AAI<0b01100010, 0b11110111, "qsub16">;
2412 def QSUB8 : AAI<0b01100010, 0b11111111, "qsub8">;
2413 def UQADD16 : AAI<0b01100110, 0b11110001, "uqadd16">;
2414 def UQADD8 : AAI<0b01100110, 0b11111001, "uqadd8">;
2415 def UQASX : AAI<0b01100110, 0b11110011, "uqasx">;
2416 def UQSAX : AAI<0b01100110, 0b11110101, "uqsax">;
2417 def UQSUB16 : AAI<0b01100110, 0b11110111, "uqsub16">;
2418 def UQSUB8 : AAI<0b01100110, 0b11111111, "uqsub8">;
2420 // Signed/Unsigned add/subtract -- for disassembly only
2422 def SASX : AAI<0b01100001, 0b11110011, "sasx">;
2423 def SADD16 : AAI<0b01100001, 0b11110001, "sadd16">;
2424 def SADD8 : AAI<0b01100001, 0b11111001, "sadd8">;
2425 def SSAX : AAI<0b01100001, 0b11110101, "ssax">;
2426 def SSUB16 : AAI<0b01100001, 0b11110111, "ssub16">;
2427 def SSUB8 : AAI<0b01100001, 0b11111111, "ssub8">;
2428 def UASX : AAI<0b01100101, 0b11110011, "uasx">;
2429 def UADD16 : AAI<0b01100101, 0b11110001, "uadd16">;
2430 def UADD8 : AAI<0b01100101, 0b11111001, "uadd8">;
2431 def USAX : AAI<0b01100101, 0b11110101, "usax">;
2432 def USUB16 : AAI<0b01100101, 0b11110111, "usub16">;
2433 def USUB8 : AAI<0b01100101, 0b11111111, "usub8">;
2435 // Signed/Unsigned halving add/subtract -- for disassembly only
2437 def SHASX : AAI<0b01100011, 0b11110011, "shasx">;
2438 def SHADD16 : AAI<0b01100011, 0b11110001, "shadd16">;
2439 def SHADD8 : AAI<0b01100011, 0b11111001, "shadd8">;
2440 def SHSAX : AAI<0b01100011, 0b11110101, "shsax">;
2441 def SHSUB16 : AAI<0b01100011, 0b11110111, "shsub16">;
2442 def SHSUB8 : AAI<0b01100011, 0b11111111, "shsub8">;
2443 def UHASX : AAI<0b01100111, 0b11110011, "uhasx">;
2444 def UHADD16 : AAI<0b01100111, 0b11110001, "uhadd16">;
2445 def UHADD8 : AAI<0b01100111, 0b11111001, "uhadd8">;
2446 def UHSAX : AAI<0b01100111, 0b11110101, "uhsax">;
2447 def UHSUB16 : AAI<0b01100111, 0b11110111, "uhsub16">;
2448 def UHSUB8 : AAI<0b01100111, 0b11111111, "uhsub8">;
2450 // Unsigned Sum of Absolute Differences [and Accumulate] -- for disassembly only
2452 def USAD8 : AI<(outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm),
2453 MulFrm /* for convenience */, NoItinerary, "usad8",
2454 "\t$Rd, $Rn, $Rm", []>,
2455 Requires<[IsARM, HasV6]> {
2459 let Inst{27-20} = 0b01111000;
2460 let Inst{15-12} = 0b1111;
2461 let Inst{7-4} = 0b0001;
2462 let Inst{19-16} = Rd;
2463 let Inst{11-8} = Rm;
2466 def USADA8 : AI<(outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm, GPR:$Ra),
2467 MulFrm /* for convenience */, NoItinerary, "usada8",
2468 "\t$Rd, $Rn, $Rm, $Ra", []>,
2469 Requires<[IsARM, HasV6]> {
2474 let Inst{27-20} = 0b01111000;
2475 let Inst{7-4} = 0b0001;
2476 let Inst{19-16} = Rd;
2477 let Inst{15-12} = Ra;
2478 let Inst{11-8} = Rm;
2482 // Signed/Unsigned saturate -- for disassembly only
2484 def SSAT : AI<(outs GPR:$Rd), (ins i32imm:$sat_imm, GPR:$a, shift_imm:$sh),
2485 SatFrm, NoItinerary, "ssat", "\t$Rd, $sat_imm, $a$sh",
2486 [/* For disassembly only; pattern left blank */]> {
2491 let Inst{27-21} = 0b0110101;
2492 let Inst{5-4} = 0b01;
2493 let Inst{20-16} = sat_imm;
2494 let Inst{15-12} = Rd;
2495 let Inst{11-7} = sh{7-3};
2496 let Inst{6} = sh{0};
2500 def SSAT16 : AI<(outs GPR:$Rd), (ins i32imm:$sat_imm, GPR:$Rn), SatFrm,
2501 NoItinerary, "ssat16", "\t$Rd, $sat_imm, $Rn",
2502 [/* For disassembly only; pattern left blank */]> {
2506 let Inst{27-20} = 0b01101010;
2507 let Inst{11-4} = 0b11110011;
2508 let Inst{15-12} = Rd;
2509 let Inst{19-16} = sat_imm;
2513 def USAT : AI<(outs GPR:$Rd), (ins i32imm:$sat_imm, GPR:$a, shift_imm:$sh),
2514 SatFrm, NoItinerary, "usat", "\t$Rd, $sat_imm, $a$sh",
2515 [/* For disassembly only; pattern left blank */]> {
2520 let Inst{27-21} = 0b0110111;
2521 let Inst{5-4} = 0b01;
2522 let Inst{15-12} = Rd;
2523 let Inst{11-7} = sh{7-3};
2524 let Inst{6} = sh{0};
2525 let Inst{20-16} = sat_imm;
2529 def USAT16 : AI<(outs GPR:$Rd), (ins i32imm:$sat_imm, GPR:$a), SatFrm,
2530 NoItinerary, "usat16", "\t$Rd, $sat_imm, $a",
2531 [/* For disassembly only; pattern left blank */]> {
2535 let Inst{27-20} = 0b01101110;
2536 let Inst{11-4} = 0b11110011;
2537 let Inst{15-12} = Rd;
2538 let Inst{19-16} = sat_imm;
2542 def : ARMV6Pat<(int_arm_ssat GPR:$a, imm:$pos), (SSAT imm:$pos, GPR:$a, 0)>;
2543 def : ARMV6Pat<(int_arm_usat GPR:$a, imm:$pos), (USAT imm:$pos, GPR:$a, 0)>;
2545 //===----------------------------------------------------------------------===//
2546 // Bitwise Instructions.
2549 defm AND : AsI1_bin_irs<0b0000, "and",
2550 IIC_iBITi, IIC_iBITr, IIC_iBITsr,
2551 BinOpFrag<(and node:$LHS, node:$RHS)>, 1>;
2552 defm ORR : AsI1_bin_irs<0b1100, "orr",
2553 IIC_iBITi, IIC_iBITr, IIC_iBITsr,
2554 BinOpFrag<(or node:$LHS, node:$RHS)>, 1>;
2555 defm EOR : AsI1_bin_irs<0b0001, "eor",
2556 IIC_iBITi, IIC_iBITr, IIC_iBITsr,
2557 BinOpFrag<(xor node:$LHS, node:$RHS)>, 1>;
2558 defm BIC : AsI1_bin_irs<0b1110, "bic",
2559 IIC_iBITi, IIC_iBITr, IIC_iBITsr,
2560 BinOpFrag<(and node:$LHS, (not node:$RHS))>>;
2562 def BFC : I<(outs GPR:$Rd), (ins GPR:$src, bf_inv_mask_imm:$imm),
2563 AddrMode1, Size4Bytes, IndexModeNone, DPFrm, IIC_iUNAsi,
2564 "bfc", "\t$Rd, $imm", "$src = $Rd",
2565 [(set GPR:$Rd, (and GPR:$src, bf_inv_mask_imm:$imm))]>,
2566 Requires<[IsARM, HasV6T2]> {
2569 let Inst{27-21} = 0b0111110;
2570 let Inst{6-0} = 0b0011111;
2571 let Inst{15-12} = Rd;
2572 let Inst{11-7} = imm{4-0}; // lsb
2573 let Inst{20-16} = imm{9-5}; // width
2576 // A8.6.18 BFI - Bitfield insert (Encoding A1)
2577 def BFI : I<(outs GPR:$Rd), (ins GPR:$src, GPR:$Rn, bf_inv_mask_imm:$imm),
2578 AddrMode1, Size4Bytes, IndexModeNone, DPFrm, IIC_iUNAsi,
2579 "bfi", "\t$Rd, $Rn, $imm", "$src = $Rd",
2580 [(set GPR:$Rd, (ARMbfi GPR:$src, GPR:$Rn,
2581 bf_inv_mask_imm:$imm))]>,
2582 Requires<[IsARM, HasV6T2]> {
2586 let Inst{27-21} = 0b0111110;
2587 let Inst{6-4} = 0b001; // Rn: Inst{3-0} != 15
2588 let Inst{15-12} = Rd;
2589 let Inst{11-7} = imm{4-0}; // lsb
2590 let Inst{20-16} = imm{9-5}; // width
2594 // GNU as only supports this form of bfi (w/ 4 arguments)
2595 let isAsmParserOnly = 1 in
2596 def BFI4p : I<(outs GPR:$Rd), (ins GPR:$src, GPR:$Rn,
2597 lsb_pos_imm:$lsb, width_imm:$width),
2598 AddrMode1, Size4Bytes, IndexModeNone, DPFrm, IIC_iUNAsi,
2599 "bfi", "\t$Rd, $Rn, $lsb, $width", "$src = $Rd",
2600 []>, Requires<[IsARM, HasV6T2]> {
2605 let Inst{27-21} = 0b0111110;
2606 let Inst{6-4} = 0b001; // Rn: Inst{3-0} != 15
2607 let Inst{15-12} = Rd;
2608 let Inst{11-7} = lsb;
2609 let Inst{20-16} = width; // Custom encoder => lsb+width-1
2613 def MVNr : AsI1<0b1111, (outs GPR:$Rd), (ins GPR:$Rm), DPFrm, IIC_iMVNr,
2614 "mvn", "\t$Rd, $Rm",
2615 [(set GPR:$Rd, (not GPR:$Rm))]>, UnaryDP {
2619 let Inst{19-16} = 0b0000;
2620 let Inst{11-4} = 0b00000000;
2621 let Inst{15-12} = Rd;
2624 def MVNs : AsI1<0b1111, (outs GPR:$Rd), (ins so_reg:$shift), DPSoRegFrm,
2625 IIC_iMVNsr, "mvn", "\t$Rd, $shift",
2626 [(set GPR:$Rd, (not so_reg:$shift))]>, UnaryDP {
2630 let Inst{19-16} = 0b0000;
2631 let Inst{15-12} = Rd;
2632 let Inst{11-0} = shift;
2634 let isReMaterializable = 1, isAsCheapAsAMove = 1, isMoveImm = 1 in
2635 def MVNi : AsI1<0b1111, (outs GPR:$Rd), (ins so_imm:$imm), DPFrm,
2636 IIC_iMVNi, "mvn", "\t$Rd, $imm",
2637 [(set GPR:$Rd, so_imm_not:$imm)]>,UnaryDP {
2641 let Inst{19-16} = 0b0000;
2642 let Inst{15-12} = Rd;
2643 let Inst{11-0} = imm;
2646 def : ARMPat<(and GPR:$src, so_imm_not:$imm),
2647 (BICri GPR:$src, so_imm_not:$imm)>;
2649 //===----------------------------------------------------------------------===//
2650 // Multiply Instructions.
2652 class AsMul1I32<bits<7> opcod, dag oops, dag iops, InstrItinClass itin,
2653 string opc, string asm, list<dag> pattern>
2654 : AsMul1I<opcod, oops, iops, itin, opc, asm, pattern> {
2658 let Inst{19-16} = Rd;
2659 let Inst{11-8} = Rm;
2662 class AsMul1I64<bits<7> opcod, dag oops, dag iops, InstrItinClass itin,
2663 string opc, string asm, list<dag> pattern>
2664 : AsMul1I<opcod, oops, iops, itin, opc, asm, pattern> {
2669 let Inst{19-16} = RdHi;
2670 let Inst{15-12} = RdLo;
2671 let Inst{11-8} = Rm;
2675 let isCommutable = 1 in {
2676 let Constraints = "@earlyclobber $Rd" in
2677 def MULv5: ARMPseudoInst<(outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm,
2678 pred:$p, cc_out:$s),
2679 Size4Bytes, IIC_iMUL32,
2680 [(set GPR:$Rd, (mul GPR:$Rn, GPR:$Rm))]>,
2681 Requires<[IsARM, NoV6]>;
2683 def MUL : AsMul1I32<0b0000000, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm),
2684 IIC_iMUL32, "mul", "\t$Rd, $Rn, $Rm",
2685 [(set GPR:$Rd, (mul GPR:$Rn, GPR:$Rm))]>,
2686 Requires<[IsARM, HasV6]> {
2687 let Inst{15-12} = 0b0000;
2691 let Constraints = "@earlyclobber $Rd" in
2692 def MLAv5: ARMPseudoInst<(outs GPR:$Rd),
2693 (ins GPR:$Rn, GPR:$Rm, GPR:$Ra, pred:$p, cc_out:$s),
2694 Size4Bytes, IIC_iMAC32,
2695 [(set GPR:$Rd, (add (mul GPR:$Rn, GPR:$Rm), GPR:$Ra))]>,
2696 Requires<[IsARM, NoV6]> {
2698 let Inst{15-12} = Ra;
2700 def MLA : AsMul1I32<0b0000001, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm, GPR:$Ra),
2701 IIC_iMAC32, "mla", "\t$Rd, $Rn, $Rm, $Ra",
2702 [(set GPR:$Rd, (add (mul GPR:$Rn, GPR:$Rm), GPR:$Ra))]>,
2703 Requires<[IsARM, HasV6]> {
2705 let Inst{15-12} = Ra;
2708 def MLS : AMul1I<0b0000011, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm, GPR:$Ra),
2709 IIC_iMAC32, "mls", "\t$Rd, $Rn, $Rm, $Ra",
2710 [(set GPR:$Rd, (sub GPR:$Ra, (mul GPR:$Rn, GPR:$Rm)))]>,
2711 Requires<[IsARM, HasV6T2]> {
2716 let Inst{19-16} = Rd;
2717 let Inst{15-12} = Ra;
2718 let Inst{11-8} = Rm;
2722 // Extra precision multiplies with low / high results
2724 let neverHasSideEffects = 1 in {
2725 let isCommutable = 1 in {
2726 let Constraints = "@earlyclobber $RdLo,@earlyclobber $RdHi" in {
2727 def SMULLv5 : ARMPseudoInst<(outs GPR:$RdLo, GPR:$RdHi),
2728 (ins GPR:$Rn, GPR:$Rm, pred:$p, cc_out:$s),
2729 Size4Bytes, IIC_iMUL64, []>,
2730 Requires<[IsARM, NoV6]>;
2732 def UMULLv5 : ARMPseudoInst<(outs GPR:$RdLo, GPR:$RdHi),
2733 (ins GPR:$Rn, GPR:$Rm, pred:$p, cc_out:$s),
2734 Size4Bytes, IIC_iMUL64, []>,
2735 Requires<[IsARM, NoV6]>;
2738 def SMULL : AsMul1I64<0b0000110, (outs GPR:$RdLo, GPR:$RdHi),
2739 (ins GPR:$Rn, GPR:$Rm), IIC_iMUL64,
2740 "smull", "\t$RdLo, $RdHi, $Rn, $Rm", []>,
2741 Requires<[IsARM, HasV6]>;
2743 def UMULL : AsMul1I64<0b0000100, (outs GPR:$RdLo, GPR:$RdHi),
2744 (ins GPR:$Rn, GPR:$Rm), IIC_iMUL64,
2745 "umull", "\t$RdLo, $RdHi, $Rn, $Rm", []>,
2746 Requires<[IsARM, HasV6]>;
2749 // Multiply + accumulate
2750 let Constraints = "@earlyclobber $RdLo,@earlyclobber $RdHi" in {
2751 def SMLALv5 : ARMPseudoInst<(outs GPR:$RdLo, GPR:$RdHi),
2752 (ins GPR:$Rn, GPR:$Rm, pred:$p, cc_out:$s),
2753 Size4Bytes, IIC_iMAC64, []>,
2754 Requires<[IsARM, NoV6]>;
2755 def UMLALv5 : ARMPseudoInst<(outs GPR:$RdLo, GPR:$RdHi),
2756 (ins GPR:$Rn, GPR:$Rm, pred:$p, cc_out:$s),
2757 Size4Bytes, IIC_iMAC64, []>,
2758 Requires<[IsARM, NoV6]>;
2759 def UMAALv5 : ARMPseudoInst<(outs GPR:$RdLo, GPR:$RdHi),
2760 (ins GPR:$Rn, GPR:$Rm, pred:$p, cc_out:$s),
2761 Size4Bytes, IIC_iMAC64, []>,
2762 Requires<[IsARM, NoV6]>;
2766 def SMLAL : AsMul1I64<0b0000111, (outs GPR:$RdLo, GPR:$RdHi),
2767 (ins GPR:$Rn, GPR:$Rm), IIC_iMAC64,
2768 "smlal", "\t$RdLo, $RdHi, $Rn, $Rm", []>,
2769 Requires<[IsARM, HasV6]>;
2770 def UMLAL : AsMul1I64<0b0000101, (outs GPR:$RdLo, GPR:$RdHi),
2771 (ins GPR:$Rn, GPR:$Rm), IIC_iMAC64,
2772 "umlal", "\t$RdLo, $RdHi, $Rn, $Rm", []>,
2773 Requires<[IsARM, HasV6]>;
2775 def UMAAL : AMul1I <0b0000010, (outs GPR:$RdLo, GPR:$RdHi),
2776 (ins GPR:$Rn, GPR:$Rm), IIC_iMAC64,
2777 "umaal", "\t$RdLo, $RdHi, $Rn, $Rm", []>,
2778 Requires<[IsARM, HasV6]> {
2783 let Inst{19-16} = RdLo;
2784 let Inst{15-12} = RdHi;
2785 let Inst{11-8} = Rm;
2788 } // neverHasSideEffects
2790 // Most significant word multiply
2791 def SMMUL : AMul2I <0b0111010, 0b0001, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm),
2792 IIC_iMUL32, "smmul", "\t$Rd, $Rn, $Rm",
2793 [(set GPR:$Rd, (mulhs GPR:$Rn, GPR:$Rm))]>,
2794 Requires<[IsARM, HasV6]> {
2795 let Inst{15-12} = 0b1111;
2798 def SMMULR : AMul2I <0b0111010, 0b0011, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm),
2799 IIC_iMUL32, "smmulr", "\t$Rd, $Rn, $Rm",
2800 [/* For disassembly only; pattern left blank */]>,
2801 Requires<[IsARM, HasV6]> {
2802 let Inst{15-12} = 0b1111;
2805 def SMMLA : AMul2Ia <0b0111010, 0b0001, (outs GPR:$Rd),
2806 (ins GPR:$Rn, GPR:$Rm, GPR:$Ra),
2807 IIC_iMAC32, "smmla", "\t$Rd, $Rn, $Rm, $Ra",
2808 [(set GPR:$Rd, (add (mulhs GPR:$Rn, GPR:$Rm), GPR:$Ra))]>,
2809 Requires<[IsARM, HasV6]>;
2811 def SMMLAR : AMul2Ia <0b0111010, 0b0011, (outs GPR:$Rd),
2812 (ins GPR:$Rn, GPR:$Rm, GPR:$Ra),
2813 IIC_iMAC32, "smmlar", "\t$Rd, $Rn, $Rm, $Ra",
2814 [/* For disassembly only; pattern left blank */]>,
2815 Requires<[IsARM, HasV6]>;
2817 def SMMLS : AMul2Ia <0b0111010, 0b1101, (outs GPR:$Rd),
2818 (ins GPR:$Rn, GPR:$Rm, GPR:$Ra),
2819 IIC_iMAC32, "smmls", "\t$Rd, $Rn, $Rm, $Ra",
2820 [(set GPR:$Rd, (sub GPR:$Ra, (mulhs GPR:$Rn, GPR:$Rm)))]>,
2821 Requires<[IsARM, HasV6]>;
2823 def SMMLSR : AMul2Ia <0b0111010, 0b1111, (outs GPR:$Rd),
2824 (ins GPR:$Rn, GPR:$Rm, GPR:$Ra),
2825 IIC_iMAC32, "smmlsr", "\t$Rd, $Rn, $Rm, $Ra",
2826 [/* For disassembly only; pattern left blank */]>,
2827 Requires<[IsARM, HasV6]>;
2829 multiclass AI_smul<string opc, PatFrag opnode> {
2830 def BB : AMulxyI<0b0001011, 0b00, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm),
2831 IIC_iMUL16, !strconcat(opc, "bb"), "\t$Rd, $Rn, $Rm",
2832 [(set GPR:$Rd, (opnode (sext_inreg GPR:$Rn, i16),
2833 (sext_inreg GPR:$Rm, i16)))]>,
2834 Requires<[IsARM, HasV5TE]>;
2836 def BT : AMulxyI<0b0001011, 0b10, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm),
2837 IIC_iMUL16, !strconcat(opc, "bt"), "\t$Rd, $Rn, $Rm",
2838 [(set GPR:$Rd, (opnode (sext_inreg GPR:$Rn, i16),
2839 (sra GPR:$Rm, (i32 16))))]>,
2840 Requires<[IsARM, HasV5TE]>;
2842 def TB : AMulxyI<0b0001011, 0b01, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm),
2843 IIC_iMUL16, !strconcat(opc, "tb"), "\t$Rd, $Rn, $Rm",
2844 [(set GPR:$Rd, (opnode (sra GPR:$Rn, (i32 16)),
2845 (sext_inreg GPR:$Rm, i16)))]>,
2846 Requires<[IsARM, HasV5TE]>;
2848 def TT : AMulxyI<0b0001011, 0b11, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm),
2849 IIC_iMUL16, !strconcat(opc, "tt"), "\t$Rd, $Rn, $Rm",
2850 [(set GPR:$Rd, (opnode (sra GPR:$Rn, (i32 16)),
2851 (sra GPR:$Rm, (i32 16))))]>,
2852 Requires<[IsARM, HasV5TE]>;
2854 def WB : AMulxyI<0b0001001, 0b01, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm),
2855 IIC_iMUL16, !strconcat(opc, "wb"), "\t$Rd, $Rn, $Rm",
2856 [(set GPR:$Rd, (sra (opnode GPR:$Rn,
2857 (sext_inreg GPR:$Rm, i16)), (i32 16)))]>,
2858 Requires<[IsARM, HasV5TE]>;
2860 def WT : AMulxyI<0b0001001, 0b11, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm),
2861 IIC_iMUL16, !strconcat(opc, "wt"), "\t$Rd, $Rn, $Rm",
2862 [(set GPR:$Rd, (sra (opnode GPR:$Rn,
2863 (sra GPR:$Rm, (i32 16))), (i32 16)))]>,
2864 Requires<[IsARM, HasV5TE]>;
2868 multiclass AI_smla<string opc, PatFrag opnode> {
2869 def BB : AMulxyIa<0b0001000, 0b00, (outs GPR:$Rd),
2870 (ins GPR:$Rn, GPR:$Rm, GPR:$Ra),
2871 IIC_iMAC16, !strconcat(opc, "bb"), "\t$Rd, $Rn, $Rm, $Ra",
2872 [(set GPR:$Rd, (add GPR:$Ra,
2873 (opnode (sext_inreg GPR:$Rn, i16),
2874 (sext_inreg GPR:$Rm, i16))))]>,
2875 Requires<[IsARM, HasV5TE]>;
2877 def BT : AMulxyIa<0b0001000, 0b10, (outs GPR:$Rd),
2878 (ins GPR:$Rn, GPR:$Rm, GPR:$Ra),
2879 IIC_iMAC16, !strconcat(opc, "bt"), "\t$Rd, $Rn, $Rm, $Ra",
2880 [(set GPR:$Rd, (add GPR:$Ra, (opnode (sext_inreg GPR:$Rn, i16),
2881 (sra GPR:$Rm, (i32 16)))))]>,
2882 Requires<[IsARM, HasV5TE]>;
2884 def TB : AMulxyIa<0b0001000, 0b01, (outs GPR:$Rd),
2885 (ins GPR:$Rn, GPR:$Rm, GPR:$Ra),
2886 IIC_iMAC16, !strconcat(opc, "tb"), "\t$Rd, $Rn, $Rm, $Ra",
2887 [(set GPR:$Rd, (add GPR:$Ra, (opnode (sra GPR:$Rn, (i32 16)),
2888 (sext_inreg GPR:$Rm, i16))))]>,
2889 Requires<[IsARM, HasV5TE]>;
2891 def TT : AMulxyIa<0b0001000, 0b11, (outs GPR:$Rd),
2892 (ins GPR:$Rn, GPR:$Rm, GPR:$Ra),
2893 IIC_iMAC16, !strconcat(opc, "tt"), "\t$Rd, $Rn, $Rm, $Ra",
2894 [(set GPR:$Rd, (add GPR:$Ra, (opnode (sra GPR:$Rn, (i32 16)),
2895 (sra GPR:$Rm, (i32 16)))))]>,
2896 Requires<[IsARM, HasV5TE]>;
2898 def WB : AMulxyIa<0b0001001, 0b00, (outs GPR:$Rd),
2899 (ins GPR:$Rn, GPR:$Rm, GPR:$Ra),
2900 IIC_iMAC16, !strconcat(opc, "wb"), "\t$Rd, $Rn, $Rm, $Ra",
2901 [(set GPR:$Rd, (add GPR:$Ra, (sra (opnode GPR:$Rn,
2902 (sext_inreg GPR:$Rm, i16)), (i32 16))))]>,
2903 Requires<[IsARM, HasV5TE]>;
2905 def WT : AMulxyIa<0b0001001, 0b10, (outs GPR:$Rd),
2906 (ins GPR:$Rn, GPR:$Rm, GPR:$Ra),
2907 IIC_iMAC16, !strconcat(opc, "wt"), "\t$Rd, $Rn, $Rm, $Ra",
2908 [(set GPR:$Rd, (add GPR:$Ra, (sra (opnode GPR:$Rn,
2909 (sra GPR:$Rm, (i32 16))), (i32 16))))]>,
2910 Requires<[IsARM, HasV5TE]>;
2913 defm SMUL : AI_smul<"smul", BinOpFrag<(mul node:$LHS, node:$RHS)>>;
2914 defm SMLA : AI_smla<"smla", BinOpFrag<(mul node:$LHS, node:$RHS)>>;
2916 // Halfword multiply accumulate long: SMLAL<x><y> -- for disassembly only
2917 def SMLALBB : AMulxyI64<0b0001010, 0b00, (outs GPR:$RdLo, GPR:$RdHi),
2918 (ins GPR:$Rn, GPR:$Rm),
2919 IIC_iMAC64, "smlalbb", "\t$RdLo, $RdHi, $Rn, $Rm",
2920 [/* For disassembly only; pattern left blank */]>,
2921 Requires<[IsARM, HasV5TE]>;
2923 def SMLALBT : AMulxyI64<0b0001010, 0b10, (outs GPR:$RdLo, GPR:$RdHi),
2924 (ins GPR:$Rn, GPR:$Rm),
2925 IIC_iMAC64, "smlalbt", "\t$RdLo, $RdHi, $Rn, $Rm",
2926 [/* For disassembly only; pattern left blank */]>,
2927 Requires<[IsARM, HasV5TE]>;
2929 def SMLALTB : AMulxyI64<0b0001010, 0b01, (outs GPR:$RdLo, GPR:$RdHi),
2930 (ins GPR:$Rn, GPR:$Rm),
2931 IIC_iMAC64, "smlaltb", "\t$RdLo, $RdHi, $Rn, $Rm",
2932 [/* For disassembly only; pattern left blank */]>,
2933 Requires<[IsARM, HasV5TE]>;
2935 def SMLALTT : AMulxyI64<0b0001010, 0b11, (outs GPR:$RdLo, GPR:$RdHi),
2936 (ins GPR:$Rn, GPR:$Rm),
2937 IIC_iMAC64, "smlaltt", "\t$RdLo, $RdHi, $Rn, $Rm",
2938 [/* For disassembly only; pattern left blank */]>,
2939 Requires<[IsARM, HasV5TE]>;
2941 // Helper class for AI_smld -- for disassembly only
2942 class AMulDualIbase<bit long, bit sub, bit swap, dag oops, dag iops,
2943 InstrItinClass itin, string opc, string asm>
2944 : AI<oops, iops, MulFrm, itin, opc, asm, []>, Requires<[IsARM, HasV6]> {
2951 let Inst{21-20} = 0b00;
2952 let Inst{22} = long;
2953 let Inst{27-23} = 0b01110;
2954 let Inst{11-8} = Rm;
2957 class AMulDualI<bit long, bit sub, bit swap, dag oops, dag iops,
2958 InstrItinClass itin, string opc, string asm>
2959 : AMulDualIbase<long, sub, swap, oops, iops, itin, opc, asm> {
2961 let Inst{15-12} = 0b1111;
2962 let Inst{19-16} = Rd;
2964 class AMulDualIa<bit long, bit sub, bit swap, dag oops, dag iops,
2965 InstrItinClass itin, string opc, string asm>
2966 : AMulDualIbase<long, sub, swap, oops, iops, itin, opc, asm> {
2968 let Inst{15-12} = Ra;
2970 class AMulDualI64<bit long, bit sub, bit swap, dag oops, dag iops,
2971 InstrItinClass itin, string opc, string asm>
2972 : AMulDualIbase<long, sub, swap, oops, iops, itin, opc, asm> {
2975 let Inst{19-16} = RdHi;
2976 let Inst{15-12} = RdLo;
2979 multiclass AI_smld<bit sub, string opc> {
2981 def D : AMulDualIa<0, sub, 0, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm, GPR:$Ra),
2982 NoItinerary, !strconcat(opc, "d"), "\t$Rd, $Rn, $Rm, $Ra">;
2984 def DX: AMulDualIa<0, sub, 1, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm, GPR:$Ra),
2985 NoItinerary, !strconcat(opc, "dx"), "\t$Rd, $Rn, $Rm, $Ra">;
2987 def LD: AMulDualI64<1, sub, 0, (outs GPR:$RdLo,GPR:$RdHi),
2988 (ins GPR:$Rn, GPR:$Rm), NoItinerary,
2989 !strconcat(opc, "ld"), "\t$RdLo, $RdHi, $Rn, $Rm">;
2991 def LDX : AMulDualI64<1, sub, 1, (outs GPR:$RdLo,GPR:$RdHi),
2992 (ins GPR:$Rn, GPR:$Rm), NoItinerary,
2993 !strconcat(opc, "ldx"),"\t$RdLo, $RdHi, $Rn, $Rm">;
2997 defm SMLA : AI_smld<0, "smla">;
2998 defm SMLS : AI_smld<1, "smls">;
3000 multiclass AI_sdml<bit sub, string opc> {
3002 def D : AMulDualI<0, sub, 0, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm),
3003 NoItinerary, !strconcat(opc, "d"), "\t$Rd, $Rn, $Rm">;
3004 def DX : AMulDualI<0, sub, 1, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm),
3005 NoItinerary, !strconcat(opc, "dx"), "\t$Rd, $Rn, $Rm">;
3008 defm SMUA : AI_sdml<0, "smua">;
3009 defm SMUS : AI_sdml<1, "smus">;
3011 //===----------------------------------------------------------------------===//
3012 // Misc. Arithmetic Instructions.
3015 def CLZ : AMiscA1I<0b000010110, 0b0001, (outs GPR:$Rd), (ins GPR:$Rm),
3016 IIC_iUNAr, "clz", "\t$Rd, $Rm",
3017 [(set GPR:$Rd, (ctlz GPR:$Rm))]>, Requires<[IsARM, HasV5T]>;
3019 def RBIT : AMiscA1I<0b01101111, 0b0011, (outs GPR:$Rd), (ins GPR:$Rm),
3020 IIC_iUNAr, "rbit", "\t$Rd, $Rm",
3021 [(set GPR:$Rd, (ARMrbit GPR:$Rm))]>,
3022 Requires<[IsARM, HasV6T2]>;
3024 def REV : AMiscA1I<0b01101011, 0b0011, (outs GPR:$Rd), (ins GPR:$Rm),
3025 IIC_iUNAr, "rev", "\t$Rd, $Rm",
3026 [(set GPR:$Rd, (bswap GPR:$Rm))]>, Requires<[IsARM, HasV6]>;
3028 def REV16 : AMiscA1I<0b01101011, 0b1011, (outs GPR:$Rd), (ins GPR:$Rm),
3029 IIC_iUNAr, "rev16", "\t$Rd, $Rm",
3031 (or (and (srl GPR:$Rm, (i32 8)), 0xFF),
3032 (or (and (shl GPR:$Rm, (i32 8)), 0xFF00),
3033 (or (and (srl GPR:$Rm, (i32 8)), 0xFF0000),
3034 (and (shl GPR:$Rm, (i32 8)), 0xFF000000)))))]>,
3035 Requires<[IsARM, HasV6]>;
3037 def REVSH : AMiscA1I<0b01101111, 0b1011, (outs GPR:$Rd), (ins GPR:$Rm),
3038 IIC_iUNAr, "revsh", "\t$Rd, $Rm",
3041 (or (srl GPR:$Rm, (i32 8)),
3042 (shl GPR:$Rm, (i32 8))), i16))]>,
3043 Requires<[IsARM, HasV6]>;
3045 def : ARMV6Pat<(sext_inreg (or (srl (and GPR:$Rm, 0xFF00), (i32 8)),
3046 (shl GPR:$Rm, (i32 8))), i16),
3049 // Need the AddedComplexity or else MOVs + REV would be chosen.
3050 let AddedComplexity = 5 in
3051 def : ARMV6Pat<(sra (bswap GPR:$Rm), (i32 16)), (REVSH GPR:$Rm)>;
3053 def lsl_shift_imm : SDNodeXForm<imm, [{
3054 unsigned Sh = ARM_AM::getSORegOpc(ARM_AM::lsl, N->getZExtValue());
3055 return CurDAG->getTargetConstant(Sh, MVT::i32);
3058 def lsl_amt : PatLeaf<(i32 imm), [{
3059 return (N->getZExtValue() < 32);
3062 def PKHBT : APKHI<0b01101000, 0, (outs GPR:$Rd),
3063 (ins GPR:$Rn, GPR:$Rm, shift_imm:$sh),
3064 IIC_iALUsi, "pkhbt", "\t$Rd, $Rn, $Rm$sh",
3065 [(set GPR:$Rd, (or (and GPR:$Rn, 0xFFFF),
3066 (and (shl GPR:$Rm, lsl_amt:$sh),
3068 Requires<[IsARM, HasV6]>;
3070 // Alternate cases for PKHBT where identities eliminate some nodes.
3071 def : ARMV6Pat<(or (and GPR:$Rn, 0xFFFF), (and GPR:$Rm, 0xFFFF0000)),
3072 (PKHBT GPR:$Rn, GPR:$Rm, 0)>;
3073 def : ARMV6Pat<(or (and GPR:$Rn, 0xFFFF), (shl GPR:$Rm, imm16_31:$sh)),
3074 (PKHBT GPR:$Rn, GPR:$Rm, (lsl_shift_imm imm16_31:$sh))>;
3076 def asr_shift_imm : SDNodeXForm<imm, [{
3077 unsigned Sh = ARM_AM::getSORegOpc(ARM_AM::asr, N->getZExtValue());
3078 return CurDAG->getTargetConstant(Sh, MVT::i32);
3081 def asr_amt : PatLeaf<(i32 imm), [{
3082 return (N->getZExtValue() <= 32);
3085 // Note: Shifts of 1-15 bits will be transformed to srl instead of sra and
3086 // will match the pattern below.
3087 def PKHTB : APKHI<0b01101000, 1, (outs GPR:$Rd),
3088 (ins GPR:$Rn, GPR:$Rm, shift_imm:$sh),
3089 IIC_iBITsi, "pkhtb", "\t$Rd, $Rn, $Rm$sh",
3090 [(set GPR:$Rd, (or (and GPR:$Rn, 0xFFFF0000),
3091 (and (sra GPR:$Rm, asr_amt:$sh),
3093 Requires<[IsARM, HasV6]>;
3095 // Alternate cases for PKHTB where identities eliminate some nodes. Note that
3096 // a shift amount of 0 is *not legal* here, it is PKHBT instead.
3097 def : ARMV6Pat<(or (and GPR:$src1, 0xFFFF0000), (srl GPR:$src2, imm16_31:$sh)),
3098 (PKHTB GPR:$src1, GPR:$src2, (asr_shift_imm imm16_31:$sh))>;
3099 def : ARMV6Pat<(or (and GPR:$src1, 0xFFFF0000),
3100 (and (srl GPR:$src2, imm1_15:$sh), 0xFFFF)),
3101 (PKHTB GPR:$src1, GPR:$src2, (asr_shift_imm imm1_15:$sh))>;
3103 //===----------------------------------------------------------------------===//
3104 // Comparison Instructions...
3107 defm CMP : AI1_cmp_irs<0b1010, "cmp",
3108 IIC_iCMPi, IIC_iCMPr, IIC_iCMPsr,
3109 BinOpFrag<(ARMcmp node:$LHS, node:$RHS)>>;
3111 // ARMcmpZ can re-use the above instruction definitions.
3112 def : ARMPat<(ARMcmpZ GPR:$src, so_imm:$imm),
3113 (CMPri GPR:$src, so_imm:$imm)>;
3114 def : ARMPat<(ARMcmpZ GPR:$src, GPR:$rhs),
3115 (CMPrr GPR:$src, GPR:$rhs)>;
3116 def : ARMPat<(ARMcmpZ GPR:$src, so_reg:$rhs),
3117 (CMPrs GPR:$src, so_reg:$rhs)>;
3119 // FIXME: We have to be careful when using the CMN instruction and comparison
3120 // with 0. One would expect these two pieces of code should give identical
3136 // However, the CMN gives the *opposite* result when r1 is 0. This is because
3137 // the carry flag is set in the CMP case but not in the CMN case. In short, the
3138 // CMP instruction doesn't perform a truncate of the (logical) NOT of 0 plus the
3139 // value of r0 and the carry bit (because the "carry bit" parameter to
3140 // AddWithCarry is defined as 1 in this case, the carry flag will always be set
3141 // when r0 >= 0). The CMN instruction doesn't perform a NOT of 0 so there is
3142 // never a "carry" when this AddWithCarry is performed (because the "carry bit"
3143 // parameter to AddWithCarry is defined as 0).
3145 // When x is 0 and unsigned:
3149 // ~x + 1 = 0x1 0000 0000
3150 // (-x = 0) != (0x1 0000 0000 = ~x + 1)
3152 // Therefore, we should disable CMN when comparing against zero, until we can
3153 // limit when the CMN instruction is used (when we know that the RHS is not 0 or
3154 // when it's a comparison which doesn't look at the 'carry' flag).
3156 // (See the ARM docs for the "AddWithCarry" pseudo-code.)
3158 // This is related to <rdar://problem/7569620>.
3160 //defm CMN : AI1_cmp_irs<0b1011, "cmn",
3161 // BinOpFrag<(ARMcmp node:$LHS,(ineg node:$RHS))>>;
3163 // Note that TST/TEQ don't set all the same flags that CMP does!
3164 defm TST : AI1_cmp_irs<0b1000, "tst",
3165 IIC_iTSTi, IIC_iTSTr, IIC_iTSTsr,
3166 BinOpFrag<(ARMcmpZ (and_su node:$LHS, node:$RHS), 0)>, 1>;
3167 defm TEQ : AI1_cmp_irs<0b1001, "teq",
3168 IIC_iTSTi, IIC_iTSTr, IIC_iTSTsr,
3169 BinOpFrag<(ARMcmpZ (xor_su node:$LHS, node:$RHS), 0)>, 1>;
3171 defm CMNz : AI1_cmp_irs<0b1011, "cmn",
3172 IIC_iCMPi, IIC_iCMPr, IIC_iCMPsr,
3173 BinOpFrag<(ARMcmpZ node:$LHS,(ineg node:$RHS))>>;
3175 //def : ARMPat<(ARMcmp GPR:$src, so_imm_neg:$imm),
3176 // (CMNri GPR:$src, so_imm_neg:$imm)>;
3178 def : ARMPat<(ARMcmpZ GPR:$src, so_imm_neg:$imm),
3179 (CMNzri GPR:$src, so_imm_neg:$imm)>;
3181 // Pseudo i64 compares for some floating point compares.
3182 let usesCustomInserter = 1, isBranch = 1, isTerminator = 1,
3184 def BCCi64 : PseudoInst<(outs),
3185 (ins i32imm:$cc, GPR:$lhs1, GPR:$lhs2, GPR:$rhs1, GPR:$rhs2, brtarget:$dst),
3187 [(ARMBcci64 imm:$cc, GPR:$lhs1, GPR:$lhs2, GPR:$rhs1, GPR:$rhs2, bb:$dst)]>;
3189 def BCCZi64 : PseudoInst<(outs),
3190 (ins i32imm:$cc, GPR:$lhs1, GPR:$lhs2, brtarget:$dst), IIC_Br,
3191 [(ARMBcci64 imm:$cc, GPR:$lhs1, GPR:$lhs2, 0, 0, bb:$dst)]>;
3192 } // usesCustomInserter
3195 // Conditional moves
3196 // FIXME: should be able to write a pattern for ARMcmov, but can't use
3197 // a two-value operand where a dag node expects two operands. :(
3198 let neverHasSideEffects = 1 in {
3199 def MOVCCr : ARMPseudoInst<(outs GPR:$Rd), (ins GPR:$false, GPR:$Rm, pred:$p),
3200 Size4Bytes, IIC_iCMOVr,
3201 [/*(set GPR:$Rd, (ARMcmov GPR:$false, GPR:$Rm, imm:$cc, CCR:$ccr))*/]>,
3202 RegConstraint<"$false = $Rd">;
3203 def MOVCCs : ARMPseudoInst<(outs GPR:$Rd),
3204 (ins GPR:$false, so_reg:$shift, pred:$p),
3205 Size4Bytes, IIC_iCMOVsr,
3206 [/*(set GPR:$Rd, (ARMcmov GPR:$false, so_reg:$shift, imm:$cc, CCR:$ccr))*/]>,
3207 RegConstraint<"$false = $Rd">;
3209 let isMoveImm = 1 in
3210 def MOVCCi16 : ARMPseudoInst<(outs GPR:$Rd),
3211 (ins GPR:$false, i32imm_hilo16:$imm, pred:$p),
3212 Size4Bytes, IIC_iMOVi,
3214 RegConstraint<"$false = $Rd">, Requires<[IsARM, HasV6T2]>;
3216 let isMoveImm = 1 in
3217 def MOVCCi : ARMPseudoInst<(outs GPR:$Rd),
3218 (ins GPR:$false, so_imm:$imm, pred:$p),
3219 Size4Bytes, IIC_iCMOVi,
3220 [/*(set GPR:$Rd, (ARMcmov GPR:$false, so_imm:$imm, imm:$cc, CCR:$ccr))*/]>,
3221 RegConstraint<"$false = $Rd">;
3223 // Two instruction predicate mov immediate.
3224 let isMoveImm = 1 in
3225 def MOVCCi32imm : ARMPseudoInst<(outs GPR:$Rd),
3226 (ins GPR:$false, i32imm:$src, pred:$p),
3227 Size8Bytes, IIC_iCMOVix2, []>, RegConstraint<"$false = $Rd">;
3229 let isMoveImm = 1 in
3230 def MVNCCi : ARMPseudoInst<(outs GPR:$Rd),
3231 (ins GPR:$false, so_imm:$imm, pred:$p),
3232 Size4Bytes, IIC_iCMOVi,
3233 [/*(set GPR:$Rd, (ARMcmov GPR:$false, so_imm_not:$imm, imm:$cc, CCR:$ccr))*/]>,
3234 RegConstraint<"$false = $Rd">;
3235 } // neverHasSideEffects
3237 //===----------------------------------------------------------------------===//
3238 // Atomic operations intrinsics
3241 def memb_opt : Operand<i32> {
3242 let PrintMethod = "printMemBOption";
3243 let ParserMatchClass = MemBarrierOptOperand;
3246 // memory barriers protect the atomic sequences
3247 let hasSideEffects = 1 in {
3248 def DMB : AInoP<(outs), (ins memb_opt:$opt), MiscFrm, NoItinerary,
3249 "dmb", "\t$opt", [(ARMMemBarrier (i32 imm:$opt))]>,
3250 Requires<[IsARM, HasDB]> {
3252 let Inst{31-4} = 0xf57ff05;
3253 let Inst{3-0} = opt;
3257 def DSB : AInoP<(outs), (ins memb_opt:$opt), MiscFrm, NoItinerary,
3259 [/* For disassembly only; pattern left blank */]>,
3260 Requires<[IsARM, HasDB]> {
3262 let Inst{31-4} = 0xf57ff04;
3263 let Inst{3-0} = opt;
3266 // ISB has only full system option -- for disassembly only
3267 def ISB : AInoP<(outs), (ins), MiscFrm, NoItinerary, "isb", "", []>,
3268 Requires<[IsARM, HasDB]> {
3269 let Inst{31-4} = 0xf57ff06;
3270 let Inst{3-0} = 0b1111;
3273 let usesCustomInserter = 1 in {
3274 let Uses = [CPSR] in {
3275 def ATOMIC_LOAD_ADD_I8 : PseudoInst<
3276 (outs GPR:$dst), (ins GPR:$ptr, GPR:$incr), NoItinerary,
3277 [(set GPR:$dst, (atomic_load_add_8 GPR:$ptr, GPR:$incr))]>;
3278 def ATOMIC_LOAD_SUB_I8 : PseudoInst<
3279 (outs GPR:$dst), (ins GPR:$ptr, GPR:$incr), NoItinerary,
3280 [(set GPR:$dst, (atomic_load_sub_8 GPR:$ptr, GPR:$incr))]>;
3281 def ATOMIC_LOAD_AND_I8 : PseudoInst<
3282 (outs GPR:$dst), (ins GPR:$ptr, GPR:$incr), NoItinerary,
3283 [(set GPR:$dst, (atomic_load_and_8 GPR:$ptr, GPR:$incr))]>;
3284 def ATOMIC_LOAD_OR_I8 : PseudoInst<
3285 (outs GPR:$dst), (ins GPR:$ptr, GPR:$incr), NoItinerary,
3286 [(set GPR:$dst, (atomic_load_or_8 GPR:$ptr, GPR:$incr))]>;
3287 def ATOMIC_LOAD_XOR_I8 : PseudoInst<
3288 (outs GPR:$dst), (ins GPR:$ptr, GPR:$incr), NoItinerary,
3289 [(set GPR:$dst, (atomic_load_xor_8 GPR:$ptr, GPR:$incr))]>;
3290 def ATOMIC_LOAD_NAND_I8 : PseudoInst<
3291 (outs GPR:$dst), (ins GPR:$ptr, GPR:$incr), NoItinerary,
3292 [(set GPR:$dst, (atomic_load_nand_8 GPR:$ptr, GPR:$incr))]>;
3293 def ATOMIC_LOAD_ADD_I16 : PseudoInst<
3294 (outs GPR:$dst), (ins GPR:$ptr, GPR:$incr), NoItinerary,
3295 [(set GPR:$dst, (atomic_load_add_16 GPR:$ptr, GPR:$incr))]>;
3296 def ATOMIC_LOAD_SUB_I16 : PseudoInst<
3297 (outs GPR:$dst), (ins GPR:$ptr, GPR:$incr), NoItinerary,
3298 [(set GPR:$dst, (atomic_load_sub_16 GPR:$ptr, GPR:$incr))]>;
3299 def ATOMIC_LOAD_AND_I16 : PseudoInst<
3300 (outs GPR:$dst), (ins GPR:$ptr, GPR:$incr), NoItinerary,
3301 [(set GPR:$dst, (atomic_load_and_16 GPR:$ptr, GPR:$incr))]>;
3302 def ATOMIC_LOAD_OR_I16 : PseudoInst<
3303 (outs GPR:$dst), (ins GPR:$ptr, GPR:$incr), NoItinerary,
3304 [(set GPR:$dst, (atomic_load_or_16 GPR:$ptr, GPR:$incr))]>;
3305 def ATOMIC_LOAD_XOR_I16 : PseudoInst<
3306 (outs GPR:$dst), (ins GPR:$ptr, GPR:$incr), NoItinerary,
3307 [(set GPR:$dst, (atomic_load_xor_16 GPR:$ptr, GPR:$incr))]>;
3308 def ATOMIC_LOAD_NAND_I16 : PseudoInst<
3309 (outs GPR:$dst), (ins GPR:$ptr, GPR:$incr), NoItinerary,
3310 [(set GPR:$dst, (atomic_load_nand_16 GPR:$ptr, GPR:$incr))]>;
3311 def ATOMIC_LOAD_ADD_I32 : PseudoInst<
3312 (outs GPR:$dst), (ins GPR:$ptr, GPR:$incr), NoItinerary,
3313 [(set GPR:$dst, (atomic_load_add_32 GPR:$ptr, GPR:$incr))]>;
3314 def ATOMIC_LOAD_SUB_I32 : PseudoInst<
3315 (outs GPR:$dst), (ins GPR:$ptr, GPR:$incr), NoItinerary,
3316 [(set GPR:$dst, (atomic_load_sub_32 GPR:$ptr, GPR:$incr))]>;
3317 def ATOMIC_LOAD_AND_I32 : PseudoInst<
3318 (outs GPR:$dst), (ins GPR:$ptr, GPR:$incr), NoItinerary,
3319 [(set GPR:$dst, (atomic_load_and_32 GPR:$ptr, GPR:$incr))]>;
3320 def ATOMIC_LOAD_OR_I32 : PseudoInst<
3321 (outs GPR:$dst), (ins GPR:$ptr, GPR:$incr), NoItinerary,
3322 [(set GPR:$dst, (atomic_load_or_32 GPR:$ptr, GPR:$incr))]>;
3323 def ATOMIC_LOAD_XOR_I32 : PseudoInst<
3324 (outs GPR:$dst), (ins GPR:$ptr, GPR:$incr), NoItinerary,
3325 [(set GPR:$dst, (atomic_load_xor_32 GPR:$ptr, GPR:$incr))]>;
3326 def ATOMIC_LOAD_NAND_I32 : PseudoInst<
3327 (outs GPR:$dst), (ins GPR:$ptr, GPR:$incr), NoItinerary,
3328 [(set GPR:$dst, (atomic_load_nand_32 GPR:$ptr, GPR:$incr))]>;
3330 def ATOMIC_SWAP_I8 : PseudoInst<
3331 (outs GPR:$dst), (ins GPR:$ptr, GPR:$new), NoItinerary,
3332 [(set GPR:$dst, (atomic_swap_8 GPR:$ptr, GPR:$new))]>;
3333 def ATOMIC_SWAP_I16 : PseudoInst<
3334 (outs GPR:$dst), (ins GPR:$ptr, GPR:$new), NoItinerary,
3335 [(set GPR:$dst, (atomic_swap_16 GPR:$ptr, GPR:$new))]>;
3336 def ATOMIC_SWAP_I32 : PseudoInst<
3337 (outs GPR:$dst), (ins GPR:$ptr, GPR:$new), NoItinerary,
3338 [(set GPR:$dst, (atomic_swap_32 GPR:$ptr, GPR:$new))]>;
3340 def ATOMIC_CMP_SWAP_I8 : PseudoInst<
3341 (outs GPR:$dst), (ins GPR:$ptr, GPR:$old, GPR:$new), NoItinerary,
3342 [(set GPR:$dst, (atomic_cmp_swap_8 GPR:$ptr, GPR:$old, GPR:$new))]>;
3343 def ATOMIC_CMP_SWAP_I16 : PseudoInst<
3344 (outs GPR:$dst), (ins GPR:$ptr, GPR:$old, GPR:$new), NoItinerary,
3345 [(set GPR:$dst, (atomic_cmp_swap_16 GPR:$ptr, GPR:$old, GPR:$new))]>;
3346 def ATOMIC_CMP_SWAP_I32 : PseudoInst<
3347 (outs GPR:$dst), (ins GPR:$ptr, GPR:$old, GPR:$new), NoItinerary,
3348 [(set GPR:$dst, (atomic_cmp_swap_32 GPR:$ptr, GPR:$old, GPR:$new))]>;
3352 let mayLoad = 1 in {
3353 def LDREXB : AIldrex<0b10, (outs GPR:$Rt), (ins addrmode7:$addr), NoItinerary,
3354 "ldrexb", "\t$Rt, $addr", []>;
3355 def LDREXH : AIldrex<0b11, (outs GPR:$Rt), (ins addrmode7:$addr), NoItinerary,
3356 "ldrexh", "\t$Rt, $addr", []>;
3357 def LDREX : AIldrex<0b00, (outs GPR:$Rt), (ins addrmode7:$addr), NoItinerary,
3358 "ldrex", "\t$Rt, $addr", []>;
3359 def LDREXD : AIldrex<0b01, (outs GPR:$Rt, GPR:$Rt2), (ins addrmode7:$addr),
3360 NoItinerary, "ldrexd", "\t$Rt, $Rt2, $addr", []>;
3363 let mayStore = 1, Constraints = "@earlyclobber $Rd" in {
3364 def STREXB : AIstrex<0b10, (outs GPR:$Rd), (ins GPR:$Rt, addrmode7:$addr),
3365 NoItinerary, "strexb", "\t$Rd, $Rt, $addr", []>;
3366 def STREXH : AIstrex<0b11, (outs GPR:$Rd), (ins GPR:$Rt, addrmode7:$addr),
3367 NoItinerary, "strexh", "\t$Rd, $Rt, $addr", []>;
3368 def STREX : AIstrex<0b00, (outs GPR:$Rd), (ins GPR:$Rt, addrmode7:$addr),
3369 NoItinerary, "strex", "\t$Rd, $Rt, $addr", []>;
3370 def STREXD : AIstrex<0b01, (outs GPR:$Rd),
3371 (ins GPR:$Rt, GPR:$Rt2, addrmode7:$addr),
3372 NoItinerary, "strexd", "\t$Rd, $Rt, $Rt2, $addr", []>;
3375 // Clear-Exclusive is for disassembly only.
3376 def CLREX : AXI<(outs), (ins), MiscFrm, NoItinerary, "clrex",
3377 [/* For disassembly only; pattern left blank */]>,
3378 Requires<[IsARM, HasV7]> {
3379 let Inst{31-0} = 0b11110101011111111111000000011111;
3382 // SWP/SWPB are deprecated in V6/V7 and for disassembly only.
3383 let mayLoad = 1 in {
3384 def SWP : AIswp<0, (outs GPR:$Rt), (ins GPR:$Rt2, GPR:$Rn), "swp",
3385 [/* For disassembly only; pattern left blank */]>;
3386 def SWPB : AIswp<1, (outs GPR:$Rt), (ins GPR:$Rt2, GPR:$Rn), "swpb",
3387 [/* For disassembly only; pattern left blank */]>;
3390 //===----------------------------------------------------------------------===//
3391 // Coprocessor Instructions.
3394 def CDP : ABI<0b1110, (outs), (ins p_imm:$cop, i32imm:$opc1,
3395 c_imm:$CRd, c_imm:$CRn, c_imm:$CRm, i32imm:$opc2),
3396 NoItinerary, "cdp", "\t$cop, $opc1, $CRd, $CRn, $CRm, $opc2",
3397 [/* For disassembly only; pattern left blank */]> {
3405 let Inst{3-0} = CRm;
3407 let Inst{7-5} = opc2;
3408 let Inst{11-8} = cop;
3409 let Inst{15-12} = CRd;
3410 let Inst{19-16} = CRn;
3411 let Inst{23-20} = opc1;
3414 def CDP2 : ABXI<0b1110, (outs), (ins p_imm:$cop, i32imm:$opc1,
3415 c_imm:$CRd, c_imm:$CRn, c_imm:$CRm, i32imm:$opc2),
3416 NoItinerary, "cdp2\t$cop, $opc1, $CRd, $CRn, $CRm, $opc2",
3417 [/* For disassembly only; pattern left blank */]> {
3418 let Inst{31-28} = 0b1111;
3426 let Inst{3-0} = CRm;
3428 let Inst{7-5} = opc2;
3429 let Inst{11-8} = cop;
3430 let Inst{15-12} = CRd;
3431 let Inst{19-16} = CRn;
3432 let Inst{23-20} = opc1;
3435 class ACI<dag oops, dag iops, string opc, string asm,
3436 IndexMode im = IndexModeNone>
3437 : InoP<oops, iops, AddrModeNone, Size4Bytes, im, BrFrm, NoItinerary,
3438 opc, asm, "", [/* For disassembly only; pattern left blank */]> {
3439 let Inst{27-25} = 0b110;
3442 multiclass LdStCop<bits<4> op31_28, bit load, dag ops, string opc, string cond>{
3444 def _OFFSET : ACI<(outs),
3445 !con((ins nohash_imm:$cop, nohash_imm:$CRd, addrmode2:$addr), ops),
3446 !strconcat(opc, cond), "\tp$cop, cr$CRd, $addr"> {
3447 let Inst{31-28} = op31_28;
3448 let Inst{24} = 1; // P = 1
3449 let Inst{21} = 0; // W = 0
3450 let Inst{22} = 0; // D = 0
3451 let Inst{20} = load;
3454 def _PRE : ACI<(outs),
3455 !con((ins nohash_imm:$cop, nohash_imm:$CRd, addrmode2:$addr), ops),
3456 !strconcat(opc, cond), "\tp$cop, cr$CRd, $addr!", IndexModePre> {
3457 let Inst{31-28} = op31_28;
3458 let Inst{24} = 1; // P = 1
3459 let Inst{21} = 1; // W = 1
3460 let Inst{22} = 0; // D = 0
3461 let Inst{20} = load;
3464 def _POST : ACI<(outs),
3465 !con((ins nohash_imm:$cop, nohash_imm:$CRd, addrmode2:$addr), ops),
3466 !strconcat(opc, cond), "\tp$cop, cr$CRd, $addr", IndexModePost> {
3467 let Inst{31-28} = op31_28;
3468 let Inst{24} = 0; // P = 0
3469 let Inst{21} = 1; // W = 1
3470 let Inst{22} = 0; // D = 0
3471 let Inst{20} = load;
3474 def _OPTION : ACI<(outs),
3475 !con((ins nohash_imm:$cop,nohash_imm:$CRd,GPR:$base, nohash_imm:$option),
3477 !strconcat(opc, cond), "\tp$cop, cr$CRd, [$base], \\{$option\\}"> {
3478 let Inst{31-28} = op31_28;
3479 let Inst{24} = 0; // P = 0
3480 let Inst{23} = 1; // U = 1
3481 let Inst{21} = 0; // W = 0
3482 let Inst{22} = 0; // D = 0
3483 let Inst{20} = load;
3486 def L_OFFSET : ACI<(outs),
3487 !con((ins nohash_imm:$cop, nohash_imm:$CRd, addrmode2:$addr), ops),
3488 !strconcat(!strconcat(opc, "l"), cond), "\tp$cop, cr$CRd, $addr"> {
3489 let Inst{31-28} = op31_28;
3490 let Inst{24} = 1; // P = 1
3491 let Inst{21} = 0; // W = 0
3492 let Inst{22} = 1; // D = 1
3493 let Inst{20} = load;
3496 def L_PRE : ACI<(outs),
3497 !con((ins nohash_imm:$cop, nohash_imm:$CRd, addrmode2:$addr), ops),
3498 !strconcat(!strconcat(opc, "l"), cond), "\tp$cop, cr$CRd, $addr!",
3500 let Inst{31-28} = op31_28;
3501 let Inst{24} = 1; // P = 1
3502 let Inst{21} = 1; // W = 1
3503 let Inst{22} = 1; // D = 1
3504 let Inst{20} = load;
3507 def L_POST : ACI<(outs),
3508 !con((ins nohash_imm:$cop, nohash_imm:$CRd, addrmode2:$addr), ops),
3509 !strconcat(!strconcat(opc, "l"), cond), "\tp$cop, cr$CRd, $addr",
3511 let Inst{31-28} = op31_28;
3512 let Inst{24} = 0; // P = 0
3513 let Inst{21} = 1; // W = 1
3514 let Inst{22} = 1; // D = 1
3515 let Inst{20} = load;
3518 def L_OPTION : ACI<(outs),
3519 !con((ins nohash_imm:$cop, nohash_imm:$CRd,GPR:$base,nohash_imm:$option),
3521 !strconcat(!strconcat(opc, "l"), cond),
3522 "\tp$cop, cr$CRd, [$base], \\{$option\\}"> {
3523 let Inst{31-28} = op31_28;
3524 let Inst{24} = 0; // P = 0
3525 let Inst{23} = 1; // U = 1
3526 let Inst{21} = 0; // W = 0
3527 let Inst{22} = 1; // D = 1
3528 let Inst{20} = load;
3532 defm LDC : LdStCop<{?,?,?,?}, 1, (ins pred:$p), "ldc", "${p}">;
3533 defm LDC2 : LdStCop<0b1111, 1, (ins), "ldc2", "">;
3534 defm STC : LdStCop<{?,?,?,?}, 0, (ins pred:$p), "stc", "${p}">;
3535 defm STC2 : LdStCop<0b1111, 0, (ins), "stc2", "">;
3537 //===----------------------------------------------------------------------===//
3538 // Move between coprocessor and ARM core register -- for disassembly only
3541 class MovRCopro<string opc, bit direction, dag oops, dag iops>
3542 : ABI<0b1110, oops, iops, NoItinerary, opc,
3543 "\t$cop, $opc1, $Rt, $CRn, $CRm, $opc2",
3544 [/* For disassembly only; pattern left blank */]> {
3545 let Inst{20} = direction;
3555 let Inst{15-12} = Rt;
3556 let Inst{11-8} = cop;
3557 let Inst{23-21} = opc1;
3558 let Inst{7-5} = opc2;
3559 let Inst{3-0} = CRm;
3560 let Inst{19-16} = CRn;
3563 def MCR : MovRCopro<"mcr", 0 /* from ARM core register to coprocessor */,
3564 (outs), (ins p_imm:$cop, i32imm:$opc1,
3565 GPR:$Rt, c_imm:$CRn, c_imm:$CRm,
3567 def MRC : MovRCopro<"mrc", 1 /* from coprocessor to ARM core register */,
3568 (outs GPR:$Rt), (ins p_imm:$cop, i32imm:$opc1,
3569 c_imm:$CRn, c_imm:$CRm, i32imm:$opc2)>;
3571 class MovRCopro2<string opc, bit direction, dag oops, dag iops>
3572 : ABXI<0b1110, oops, iops, NoItinerary,
3573 !strconcat(opc, "\t$cop, $opc1, $Rt, $CRn, $CRm, $opc2"),
3574 [/* For disassembly only; pattern left blank */]> {
3575 let Inst{31-28} = 0b1111;
3576 let Inst{20} = direction;
3586 let Inst{15-12} = Rt;
3587 let Inst{11-8} = cop;
3588 let Inst{23-21} = opc1;
3589 let Inst{7-5} = opc2;
3590 let Inst{3-0} = CRm;
3591 let Inst{19-16} = CRn;
3594 def MCR2 : MovRCopro2<"mcr2", 0 /* from ARM core register to coprocessor */,
3595 (outs), (ins p_imm:$cop, i32imm:$opc1,
3596 GPR:$Rt, c_imm:$CRn, c_imm:$CRm,
3598 def MRC2 : MovRCopro2<"mrc2", 1 /* from coprocessor to ARM core register */,
3599 (outs GPR:$Rt), (ins p_imm:$cop, i32imm:$opc1,
3600 c_imm:$CRn, c_imm:$CRm,
3603 class MovRRCopro<string opc, bit direction>
3604 : ABI<0b1100, (outs), (ins p_imm:$cop, i32imm:$opc1,
3605 GPR:$Rt, GPR:$Rt2, c_imm:$CRm),
3606 NoItinerary, opc, "\t$cop, $opc1, $Rt, $Rt2, $CRm",
3607 [/* For disassembly only; pattern left blank */]> {
3608 let Inst{23-21} = 0b010;
3609 let Inst{20} = direction;
3617 let Inst{15-12} = Rt;
3618 let Inst{19-16} = Rt2;
3619 let Inst{11-8} = cop;
3620 let Inst{7-4} = opc1;
3621 let Inst{3-0} = CRm;
3624 def MCRR : MovRRCopro<"mcrr", 0 /* from ARM core register to coprocessor */>;
3625 def MRRC : MovRRCopro<"mrrc", 1 /* from coprocessor to ARM core register */>;
3627 class MovRRCopro2<string opc, bit direction>
3628 : ABXI<0b1100, (outs), (ins p_imm:$cop, i32imm:$opc1,
3629 GPR:$Rt, GPR:$Rt2, c_imm:$CRm),
3630 NoItinerary, !strconcat(opc, "\t$cop, $opc1, $Rt, $Rt2, $CRm"),
3631 [/* For disassembly only; pattern left blank */]> {
3632 let Inst{31-28} = 0b1111;
3633 let Inst{23-21} = 0b010;
3634 let Inst{20} = direction;
3642 let Inst{15-12} = Rt;
3643 let Inst{19-16} = Rt2;
3644 let Inst{11-8} = cop;
3645 let Inst{7-4} = opc1;
3646 let Inst{3-0} = CRm;
3649 def MCRR2 : MovRRCopro2<"mcrr2", 0 /* from ARM core register to coprocessor */>;
3650 def MRRC2 : MovRRCopro2<"mrrc2", 1 /* from coprocessor to ARM core register */>;
3652 //===----------------------------------------------------------------------===//
3653 // Move between special register and ARM core register -- for disassembly only
3656 // Move to ARM core register from Special Register
3657 def MRS : ABI<0b0001, (outs GPR:$Rd), (ins), NoItinerary, "mrs", "\t$Rd, cpsr",
3658 [/* For disassembly only; pattern left blank */]> {
3660 let Inst{23-16} = 0b00001111;
3661 let Inst{15-12} = Rd;
3662 let Inst{7-4} = 0b0000;
3665 def MRSsys : ABI<0b0001, (outs GPR:$Rd), (ins), NoItinerary,"mrs","\t$Rd, spsr",
3666 [/* For disassembly only; pattern left blank */]> {
3668 let Inst{23-16} = 0b01001111;
3669 let Inst{15-12} = Rd;
3670 let Inst{7-4} = 0b0000;
3673 // Move from ARM core register to Special Register
3675 // No need to have both system and application versions, the encodings are the
3676 // same and the assembly parser has no way to distinguish between them. The mask
3677 // operand contains the special register (R Bit) in bit 4 and bits 3-0 contains
3678 // the mask with the fields to be accessed in the special register.
3679 def MSR : ABI<0b0001, (outs), (ins msr_mask:$mask, GPR:$Rn), NoItinerary,
3680 "msr", "\t$mask, $Rn",
3681 [/* For disassembly only; pattern left blank */]> {
3686 let Inst{22} = mask{4}; // R bit
3687 let Inst{21-20} = 0b10;
3688 let Inst{19-16} = mask{3-0};
3689 let Inst{15-12} = 0b1111;
3690 let Inst{11-4} = 0b00000000;
3694 def MSRi : ABI<0b0011, (outs), (ins msr_mask:$mask, so_imm:$a), NoItinerary,
3695 "msr", "\t$mask, $a",
3696 [/* For disassembly only; pattern left blank */]> {
3701 let Inst{22} = mask{4}; // R bit
3702 let Inst{21-20} = 0b10;
3703 let Inst{19-16} = mask{3-0};
3704 let Inst{15-12} = 0b1111;
3708 //===----------------------------------------------------------------------===//
3712 // __aeabi_read_tp preserves the registers r1-r3.
3713 // This is a pseudo inst so that we can get the encoding right,
3714 // complete with fixup for the aeabi_read_tp function.
3716 Defs = [R0, R12, LR, CPSR], Uses = [SP] in {
3717 def TPsoft : PseudoInst<(outs), (ins), IIC_Br,
3718 [(set R0, ARMthread_pointer)]>;
3721 //===----------------------------------------------------------------------===//
3722 // SJLJ Exception handling intrinsics
3723 // eh_sjlj_setjmp() is an instruction sequence to store the return
3724 // address and save #0 in R0 for the non-longjmp case.
3725 // Since by its nature we may be coming from some other function to get
3726 // here, and we're using the stack frame for the containing function to
3727 // save/restore registers, we can't keep anything live in regs across
3728 // the eh_sjlj_setjmp(), else it will almost certainly have been tromped upon
3729 // when we get here from a longjmp(). We force everthing out of registers
3730 // except for our own input by listing the relevant registers in Defs. By
3731 // doing so, we also cause the prologue/epilogue code to actively preserve
3732 // all of the callee-saved resgisters, which is exactly what we want.
3733 // A constant value is passed in $val, and we use the location as a scratch.
3735 // These are pseudo-instructions and are lowered to individual MC-insts, so
3736 // no encoding information is necessary.
3738 [ R0, R1, R2, R3, R4, R5, R6, R7, R8, R9, R10, R11, R12, LR, D0,
3739 D1, D2, D3, D4, D5, D6, D7, D8, D9, D10, D11, D12, D13, D14, D15,
3740 D16, D17, D18, D19, D20, D21, D22, D23, D24, D25, D26, D27, D28, D29, D30,
3741 D31 ], hasSideEffects = 1, isBarrier = 1 in {
3742 def Int_eh_sjlj_setjmp : PseudoInst<(outs), (ins GPR:$src, GPR:$val),
3744 [(set R0, (ARMeh_sjlj_setjmp GPR:$src, GPR:$val))]>,
3745 Requires<[IsARM, HasVFP2]>;
3749 [ R0, R1, R2, R3, R4, R5, R6, R7, R8, R9, R10, R11, R12, LR ],
3750 hasSideEffects = 1, isBarrier = 1 in {
3751 def Int_eh_sjlj_setjmp_nofp : PseudoInst<(outs), (ins GPR:$src, GPR:$val),
3753 [(set R0, (ARMeh_sjlj_setjmp GPR:$src, GPR:$val))]>,
3754 Requires<[IsARM, NoVFP]>;
3757 // FIXME: Non-Darwin version(s)
3758 let isBarrier = 1, hasSideEffects = 1, isTerminator = 1,
3759 Defs = [ R7, LR, SP ] in {
3760 def Int_eh_sjlj_longjmp : PseudoInst<(outs), (ins GPR:$src, GPR:$scratch),
3762 [(ARMeh_sjlj_longjmp GPR:$src, GPR:$scratch)]>,
3763 Requires<[IsARM, IsDarwin]>;
3766 // eh.sjlj.dispatchsetup pseudo-instruction.
3767 // This pseudo is used for ARM, Thumb1 and Thumb2. Any differences are
3768 // handled when the pseudo is expanded (which happens before any passes
3769 // that need the instruction size).
3770 let isBarrier = 1, hasSideEffects = 1 in
3771 def Int_eh_sjlj_dispatchsetup :
3772 PseudoInst<(outs), (ins), NoItinerary,
3773 [(ARMeh_sjlj_dispatchsetup)]>,
3774 Requires<[IsDarwin]>;
3776 //===----------------------------------------------------------------------===//
3777 // Non-Instruction Patterns
3780 // Large immediate handling.
3782 // 32-bit immediate using two piece so_imms or movw + movt.
3783 // This is a single pseudo instruction, the benefit is that it can be remat'd
3784 // as a single unit instead of having to handle reg inputs.
3785 // FIXME: Remove this when we can do generalized remat.
3786 let isReMaterializable = 1, isMoveImm = 1 in
3787 def MOVi32imm : PseudoInst<(outs GPR:$dst), (ins i32imm:$src), IIC_iMOVix2,
3788 [(set GPR:$dst, (arm_i32imm:$src))]>,
3791 // Pseudo instruction that combines movw + movt + add pc (if PIC).
3792 // It also makes it possible to rematerialize the instructions.
3793 // FIXME: Remove this when we can do generalized remat and when machine licm
3794 // can properly the instructions.
3795 let isReMaterializable = 1 in {
3796 def MOV_ga_pcrel : PseudoInst<(outs GPR:$dst), (ins i32imm:$addr),
3798 [(set GPR:$dst, (ARMWrapperPIC tglobaladdr:$addr))]>,
3799 Requires<[IsARM, UseMovt]>;
3801 def MOV_ga_dyn : PseudoInst<(outs GPR:$dst), (ins i32imm:$addr),
3803 [(set GPR:$dst, (ARMWrapperDYN tglobaladdr:$addr))]>,
3804 Requires<[IsARM, UseMovt]>;
3806 let AddedComplexity = 10 in
3807 def MOV_ga_pcrel_ldr : PseudoInst<(outs GPR:$dst), (ins i32imm:$addr),
3809 [(set GPR:$dst, (load (ARMWrapperPIC tglobaladdr:$addr)))]>,
3810 Requires<[IsARM, UseMovt]>;
3811 } // isReMaterializable
3813 // ConstantPool, GlobalAddress, and JumpTable
3814 def : ARMPat<(ARMWrapper tglobaladdr :$dst), (LEApcrel tglobaladdr :$dst)>,
3815 Requires<[IsARM, DontUseMovt]>;
3816 def : ARMPat<(ARMWrapper tconstpool :$dst), (LEApcrel tconstpool :$dst)>;
3817 def : ARMPat<(ARMWrapper tglobaladdr :$dst), (MOVi32imm tglobaladdr :$dst)>,
3818 Requires<[IsARM, UseMovt]>;
3819 def : ARMPat<(ARMWrapperJT tjumptable:$dst, imm:$id),
3820 (LEApcrelJT tjumptable:$dst, imm:$id)>;
3822 // TODO: add,sub,and, 3-instr forms?
3825 def : ARMPat<(ARMtcret tcGPR:$dst),
3826 (TCRETURNri tcGPR:$dst)>, Requires<[IsDarwin]>;
3828 def : ARMPat<(ARMtcret (i32 tglobaladdr:$dst)),
3829 (TCRETURNdi texternalsym:$dst)>, Requires<[IsDarwin]>;
3831 def : ARMPat<(ARMtcret (i32 texternalsym:$dst)),
3832 (TCRETURNdi texternalsym:$dst)>, Requires<[IsDarwin]>;
3834 def : ARMPat<(ARMtcret tcGPR:$dst),
3835 (TCRETURNriND tcGPR:$dst)>, Requires<[IsNotDarwin]>;
3837 def : ARMPat<(ARMtcret (i32 tglobaladdr:$dst)),
3838 (TCRETURNdiND texternalsym:$dst)>, Requires<[IsNotDarwin]>;
3840 def : ARMPat<(ARMtcret (i32 texternalsym:$dst)),
3841 (TCRETURNdiND texternalsym:$dst)>, Requires<[IsNotDarwin]>;
3844 def : ARMPat<(ARMcall texternalsym:$func), (BL texternalsym:$func)>,
3845 Requires<[IsARM, IsNotDarwin]>;
3846 def : ARMPat<(ARMcall texternalsym:$func), (BLr9 texternalsym:$func)>,
3847 Requires<[IsARM, IsDarwin]>;
3849 // zextload i1 -> zextload i8
3850 def : ARMPat<(zextloadi1 addrmode_imm12:$addr), (LDRBi12 addrmode_imm12:$addr)>;
3851 def : ARMPat<(zextloadi1 ldst_so_reg:$addr), (LDRBrs ldst_so_reg:$addr)>;
3853 // extload -> zextload
3854 def : ARMPat<(extloadi1 addrmode_imm12:$addr), (LDRBi12 addrmode_imm12:$addr)>;
3855 def : ARMPat<(extloadi1 ldst_so_reg:$addr), (LDRBrs ldst_so_reg:$addr)>;
3856 def : ARMPat<(extloadi8 addrmode_imm12:$addr), (LDRBi12 addrmode_imm12:$addr)>;
3857 def : ARMPat<(extloadi8 ldst_so_reg:$addr), (LDRBrs ldst_so_reg:$addr)>;
3859 def : ARMPat<(extloadi16 addrmode3:$addr), (LDRH addrmode3:$addr)>;
3861 def : ARMPat<(extloadi8 addrmodepc:$addr), (PICLDRB addrmodepc:$addr)>;
3862 def : ARMPat<(extloadi16 addrmodepc:$addr), (PICLDRH addrmodepc:$addr)>;
3865 def : ARMV5TEPat<(mul (sra (shl GPR:$a, (i32 16)), (i32 16)),
3866 (sra (shl GPR:$b, (i32 16)), (i32 16))),
3867 (SMULBB GPR:$a, GPR:$b)>;
3868 def : ARMV5TEPat<(mul sext_16_node:$a, sext_16_node:$b),
3869 (SMULBB GPR:$a, GPR:$b)>;
3870 def : ARMV5TEPat<(mul (sra (shl GPR:$a, (i32 16)), (i32 16)),
3871 (sra GPR:$b, (i32 16))),
3872 (SMULBT GPR:$a, GPR:$b)>;
3873 def : ARMV5TEPat<(mul sext_16_node:$a, (sra GPR:$b, (i32 16))),
3874 (SMULBT GPR:$a, GPR:$b)>;
3875 def : ARMV5TEPat<(mul (sra GPR:$a, (i32 16)),
3876 (sra (shl GPR:$b, (i32 16)), (i32 16))),
3877 (SMULTB GPR:$a, GPR:$b)>;
3878 def : ARMV5TEPat<(mul (sra GPR:$a, (i32 16)), sext_16_node:$b),
3879 (SMULTB GPR:$a, GPR:$b)>;
3880 def : ARMV5TEPat<(sra (mul GPR:$a, (sra (shl GPR:$b, (i32 16)), (i32 16))),
3882 (SMULWB GPR:$a, GPR:$b)>;
3883 def : ARMV5TEPat<(sra (mul GPR:$a, sext_16_node:$b), (i32 16)),
3884 (SMULWB GPR:$a, GPR:$b)>;
3886 def : ARMV5TEPat<(add GPR:$acc,
3887 (mul (sra (shl GPR:$a, (i32 16)), (i32 16)),
3888 (sra (shl GPR:$b, (i32 16)), (i32 16)))),
3889 (SMLABB GPR:$a, GPR:$b, GPR:$acc)>;
3890 def : ARMV5TEPat<(add GPR:$acc,
3891 (mul sext_16_node:$a, sext_16_node:$b)),
3892 (SMLABB GPR:$a, GPR:$b, GPR:$acc)>;
3893 def : ARMV5TEPat<(add GPR:$acc,
3894 (mul (sra (shl GPR:$a, (i32 16)), (i32 16)),
3895 (sra GPR:$b, (i32 16)))),
3896 (SMLABT GPR:$a, GPR:$b, GPR:$acc)>;
3897 def : ARMV5TEPat<(add GPR:$acc,
3898 (mul sext_16_node:$a, (sra GPR:$b, (i32 16)))),
3899 (SMLABT GPR:$a, GPR:$b, GPR:$acc)>;
3900 def : ARMV5TEPat<(add GPR:$acc,
3901 (mul (sra GPR:$a, (i32 16)),
3902 (sra (shl GPR:$b, (i32 16)), (i32 16)))),
3903 (SMLATB GPR:$a, GPR:$b, GPR:$acc)>;
3904 def : ARMV5TEPat<(add GPR:$acc,
3905 (mul (sra GPR:$a, (i32 16)), sext_16_node:$b)),
3906 (SMLATB GPR:$a, GPR:$b, GPR:$acc)>;
3907 def : ARMV5TEPat<(add GPR:$acc,
3908 (sra (mul GPR:$a, (sra (shl GPR:$b, (i32 16)), (i32 16))),
3910 (SMLAWB GPR:$a, GPR:$b, GPR:$acc)>;
3911 def : ARMV5TEPat<(add GPR:$acc,
3912 (sra (mul GPR:$a, sext_16_node:$b), (i32 16))),
3913 (SMLAWB GPR:$a, GPR:$b, GPR:$acc)>;
3916 // Pre-v7 uses MCR for synchronization barriers.
3917 def : ARMPat<(ARMMemBarrierMCR GPR:$zero), (MCR 15, 0, GPR:$zero, 7, 10, 5)>,
3918 Requires<[IsARM, HasV6]>;
3921 //===----------------------------------------------------------------------===//
3925 include "ARMInstrThumb.td"
3927 //===----------------------------------------------------------------------===//
3931 include "ARMInstrThumb2.td"
3933 //===----------------------------------------------------------------------===//
3934 // Floating Point Support
3937 include "ARMInstrVFP.td"
3939 //===----------------------------------------------------------------------===//
3940 // Advanced SIMD (NEON) Support
3943 include "ARMInstrNEON.td"