1 //===- ARMInstrInfo.td - Target Description for ARM Target -*- tablegen -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file describes the ARM instructions in TableGen format.
12 //===----------------------------------------------------------------------===//
14 //===----------------------------------------------------------------------===//
15 // ARM specific DAG Nodes.
19 def SDT_ARMCallSeqStart : SDCallSeqStart<[ SDTCisVT<0, i32> ]>;
20 def SDT_ARMCallSeqEnd : SDCallSeqEnd<[ SDTCisVT<0, i32>, SDTCisVT<1, i32> ]>;
21 def SDT_ARMStructByVal : SDTypeProfile<0, 4,
22 [SDTCisVT<0, i32>, SDTCisVT<1, i32>,
23 SDTCisVT<2, i32>, SDTCisVT<3, i32>]>;
25 def SDT_ARMSaveCallPC : SDTypeProfile<0, 1, []>;
27 def SDT_ARMcall : SDTypeProfile<0, -1, [SDTCisPtrTy<0>]>;
29 def SDT_ARMCMov : SDTypeProfile<1, 3,
30 [SDTCisSameAs<0, 1>, SDTCisSameAs<0, 2>,
33 def SDT_ARMBrcond : SDTypeProfile<0, 2,
34 [SDTCisVT<0, OtherVT>, SDTCisVT<1, i32>]>;
36 def SDT_ARMBrJT : SDTypeProfile<0, 3,
37 [SDTCisPtrTy<0>, SDTCisVT<1, i32>,
40 def SDT_ARMBr2JT : SDTypeProfile<0, 4,
41 [SDTCisPtrTy<0>, SDTCisVT<1, i32>,
42 SDTCisVT<2, i32>, SDTCisVT<3, i32>]>;
44 def SDT_ARMBCC_i64 : SDTypeProfile<0, 6,
46 SDTCisVT<1, i32>, SDTCisVT<2, i32>,
47 SDTCisVT<3, i32>, SDTCisVT<4, i32>,
48 SDTCisVT<5, OtherVT>]>;
50 def SDT_ARMAnd : SDTypeProfile<1, 2,
51 [SDTCisVT<0, i32>, SDTCisVT<1, i32>,
54 def SDT_ARMCmp : SDTypeProfile<0, 2, [SDTCisSameAs<0, 1>]>;
56 def SDT_ARMPICAdd : SDTypeProfile<1, 2, [SDTCisSameAs<0, 1>,
57 SDTCisPtrTy<1>, SDTCisVT<2, i32>]>;
59 def SDT_ARMThreadPointer : SDTypeProfile<1, 0, [SDTCisPtrTy<0>]>;
60 def SDT_ARMEH_SJLJ_Setjmp : SDTypeProfile<1, 2, [SDTCisInt<0>, SDTCisPtrTy<1>,
62 def SDT_ARMEH_SJLJ_Longjmp: SDTypeProfile<0, 2, [SDTCisPtrTy<0>, SDTCisInt<1>]>;
64 def SDT_ARMMEMBARRIER : SDTypeProfile<0, 1, [SDTCisInt<0>]>;
66 def SDT_ARMPREFETCH : SDTypeProfile<0, 3, [SDTCisPtrTy<0>, SDTCisSameAs<1, 2>,
69 def SDT_ARMTCRET : SDTypeProfile<0, 1, [SDTCisPtrTy<0>]>;
71 def SDT_ARMBFI : SDTypeProfile<1, 3, [SDTCisVT<0, i32>, SDTCisVT<1, i32>,
72 SDTCisVT<2, i32>, SDTCisVT<3, i32>]>;
74 def SDTBinaryArithWithFlags : SDTypeProfile<2, 2,
77 SDTCisInt<0>, SDTCisVT<1, i32>]>;
79 // SDTBinaryArithWithFlagsInOut - RES1, CPSR = op LHS, RHS, CPSR
80 def SDTBinaryArithWithFlagsInOut : SDTypeProfile<2, 3,
87 def ARMWrapper : SDNode<"ARMISD::Wrapper", SDTIntUnaryOp>;
88 def ARMWrapperDYN : SDNode<"ARMISD::WrapperDYN", SDTIntUnaryOp>;
89 def ARMWrapperPIC : SDNode<"ARMISD::WrapperPIC", SDTIntUnaryOp>;
90 def ARMWrapperJT : SDNode<"ARMISD::WrapperJT", SDTIntBinOp>;
92 def ARMcallseq_start : SDNode<"ISD::CALLSEQ_START", SDT_ARMCallSeqStart,
93 [SDNPHasChain, SDNPOutGlue]>;
94 def ARMcallseq_end : SDNode<"ISD::CALLSEQ_END", SDT_ARMCallSeqEnd,
95 [SDNPHasChain, SDNPOptInGlue, SDNPOutGlue]>;
96 def ARMcopystructbyval : SDNode<"ARMISD::COPY_STRUCT_BYVAL" ,
98 [SDNPHasChain, SDNPInGlue, SDNPOutGlue,
99 SDNPMayStore, SDNPMayLoad]>;
101 def ARMcall : SDNode<"ARMISD::CALL", SDT_ARMcall,
102 [SDNPHasChain, SDNPOptInGlue, SDNPOutGlue,
104 def ARMcall_pred : SDNode<"ARMISD::CALL_PRED", SDT_ARMcall,
105 [SDNPHasChain, SDNPOptInGlue, SDNPOutGlue,
107 def ARMcall_nolink : SDNode<"ARMISD::CALL_NOLINK", SDT_ARMcall,
108 [SDNPHasChain, SDNPOptInGlue, SDNPOutGlue,
111 def ARMretflag : SDNode<"ARMISD::RET_FLAG", SDTNone,
112 [SDNPHasChain, SDNPOptInGlue]>;
114 def ARMcmov : SDNode<"ARMISD::CMOV", SDT_ARMCMov,
117 def ARMbrcond : SDNode<"ARMISD::BRCOND", SDT_ARMBrcond,
118 [SDNPHasChain, SDNPInGlue, SDNPOutGlue]>;
120 def ARMbrjt : SDNode<"ARMISD::BR_JT", SDT_ARMBrJT,
122 def ARMbr2jt : SDNode<"ARMISD::BR2_JT", SDT_ARMBr2JT,
125 def ARMBcci64 : SDNode<"ARMISD::BCC_i64", SDT_ARMBCC_i64,
128 def ARMcmp : SDNode<"ARMISD::CMP", SDT_ARMCmp,
131 def ARMcmn : SDNode<"ARMISD::CMN", SDT_ARMCmp,
134 def ARMcmpZ : SDNode<"ARMISD::CMPZ", SDT_ARMCmp,
135 [SDNPOutGlue, SDNPCommutative]>;
137 def ARMpic_add : SDNode<"ARMISD::PIC_ADD", SDT_ARMPICAdd>;
139 def ARMsrl_flag : SDNode<"ARMISD::SRL_FLAG", SDTIntUnaryOp, [SDNPOutGlue]>;
140 def ARMsra_flag : SDNode<"ARMISD::SRA_FLAG", SDTIntUnaryOp, [SDNPOutGlue]>;
141 def ARMrrx : SDNode<"ARMISD::RRX" , SDTIntUnaryOp, [SDNPInGlue ]>;
143 def ARMaddc : SDNode<"ARMISD::ADDC", SDTBinaryArithWithFlags,
145 def ARMsubc : SDNode<"ARMISD::SUBC", SDTBinaryArithWithFlags>;
146 def ARMadde : SDNode<"ARMISD::ADDE", SDTBinaryArithWithFlagsInOut>;
147 def ARMsube : SDNode<"ARMISD::SUBE", SDTBinaryArithWithFlagsInOut>;
149 def ARMthread_pointer: SDNode<"ARMISD::THREAD_POINTER", SDT_ARMThreadPointer>;
150 def ARMeh_sjlj_setjmp: SDNode<"ARMISD::EH_SJLJ_SETJMP",
151 SDT_ARMEH_SJLJ_Setjmp, [SDNPHasChain]>;
152 def ARMeh_sjlj_longjmp: SDNode<"ARMISD::EH_SJLJ_LONGJMP",
153 SDT_ARMEH_SJLJ_Longjmp, [SDNPHasChain]>;
155 def ARMMemBarrier : SDNode<"ARMISD::MEMBARRIER", SDT_ARMMEMBARRIER,
157 def ARMMemBarrierMCR : SDNode<"ARMISD::MEMBARRIER_MCR", SDT_ARMMEMBARRIER,
159 def ARMPreload : SDNode<"ARMISD::PRELOAD", SDT_ARMPREFETCH,
160 [SDNPHasChain, SDNPMayLoad, SDNPMayStore]>;
162 def ARMrbit : SDNode<"ARMISD::RBIT", SDTIntUnaryOp>;
164 def ARMtcret : SDNode<"ARMISD::TC_RETURN", SDT_ARMTCRET,
165 [SDNPHasChain, SDNPOptInGlue, SDNPVariadic]>;
168 def ARMbfi : SDNode<"ARMISD::BFI", SDT_ARMBFI>;
170 //===----------------------------------------------------------------------===//
171 // ARM Instruction Predicate Definitions.
173 def HasV4T : Predicate<"Subtarget->hasV4TOps()">,
174 AssemblerPredicate<"HasV4TOps", "armv4t">;
175 def NoV4T : Predicate<"!Subtarget->hasV4TOps()">;
176 def HasV5T : Predicate<"Subtarget->hasV5TOps()">;
177 def HasV5TE : Predicate<"Subtarget->hasV5TEOps()">,
178 AssemblerPredicate<"HasV5TEOps", "armv5te">;
179 def HasV6 : Predicate<"Subtarget->hasV6Ops()">,
180 AssemblerPredicate<"HasV6Ops", "armv6">;
181 def NoV6 : Predicate<"!Subtarget->hasV6Ops()">;
182 def HasV6T2 : Predicate<"Subtarget->hasV6T2Ops()">,
183 AssemblerPredicate<"HasV6T2Ops", "armv6t2">;
184 def NoV6T2 : Predicate<"!Subtarget->hasV6T2Ops()">;
185 def HasV7 : Predicate<"Subtarget->hasV7Ops()">,
186 AssemblerPredicate<"HasV7Ops", "armv7">;
187 def NoVFP : Predicate<"!Subtarget->hasVFP2()">;
188 def HasVFP2 : Predicate<"Subtarget->hasVFP2()">,
189 AssemblerPredicate<"FeatureVFP2", "VFP2">;
190 def HasVFP3 : Predicate<"Subtarget->hasVFP3()">,
191 AssemblerPredicate<"FeatureVFP3", "VFP3">;
192 def HasVFP4 : Predicate<"Subtarget->hasVFP4()">,
193 AssemblerPredicate<"FeatureVFP4", "VFP4">;
194 def HasNEON : Predicate<"Subtarget->hasNEON()">,
195 AssemblerPredicate<"FeatureNEON", "NEON">;
196 def HasFP16 : Predicate<"Subtarget->hasFP16()">,
197 AssemblerPredicate<"FeatureFP16","half-float">;
198 def HasDivide : Predicate<"Subtarget->hasDivide()">,
199 AssemblerPredicate<"FeatureHWDiv", "divide">;
200 def HasT2ExtractPack : Predicate<"Subtarget->hasT2ExtractPack()">,
201 AssemblerPredicate<"FeatureT2XtPk",
203 def HasThumb2DSP : Predicate<"Subtarget->hasThumb2DSP()">,
204 AssemblerPredicate<"FeatureDSPThumb2",
206 def HasDB : Predicate<"Subtarget->hasDataBarrier()">,
207 AssemblerPredicate<"FeatureDB",
209 def HasMP : Predicate<"Subtarget->hasMPExtension()">,
210 AssemblerPredicate<"FeatureMP",
212 def UseNEONForFP : Predicate<"Subtarget->useNEONForSinglePrecisionFP()">;
213 def DontUseNEONForFP : Predicate<"!Subtarget->useNEONForSinglePrecisionFP()">;
214 def IsThumb : Predicate<"Subtarget->isThumb()">,
215 AssemblerPredicate<"ModeThumb", "thumb">;
216 def IsThumb1Only : Predicate<"Subtarget->isThumb1Only()">;
217 def IsThumb2 : Predicate<"Subtarget->isThumb2()">,
218 AssemblerPredicate<"ModeThumb,FeatureThumb2",
220 def IsMClass : Predicate<"Subtarget->isMClass()">,
221 AssemblerPredicate<"FeatureMClass", "armv7m">;
222 def IsARClass : Predicate<"!Subtarget->isMClass()">,
223 AssemblerPredicate<"!FeatureMClass",
225 def IsARM : Predicate<"!Subtarget->isThumb()">,
226 AssemblerPredicate<"!ModeThumb", "arm-mode">;
227 def IsIOS : Predicate<"Subtarget->isTargetIOS()">;
228 def IsNotIOS : Predicate<"!Subtarget->isTargetIOS()">;
229 def IsNaCl : Predicate<"Subtarget->isTargetNaCl()">;
231 // FIXME: Eventually this will be just "hasV6T2Ops".
232 def UseMovt : Predicate<"Subtarget->useMovt()">;
233 def DontUseMovt : Predicate<"!Subtarget->useMovt()">;
234 def UseFPVMLx : Predicate<"Subtarget->useFPVMLx()">;
236 // Prefer fused MAC for fp mul + add over fp VMLA / VMLS if they are available.
237 // But only select them if more precision in FP computation is allowed.
238 // Do not use them for Darwin platforms.
239 def UseFusedMAC : Predicate<"(TM.Options.AllowFPOpFusion =="
240 " FPOpFusion::Fast) && "
241 "!Subtarget->isTargetDarwin()">;
242 def DontUseFusedMAC : Predicate<"!Subtarget->hasVFP4() || "
243 "Subtarget->isTargetDarwin()">;
245 //===----------------------------------------------------------------------===//
246 // ARM Flag Definitions.
248 class RegConstraint<string C> {
249 string Constraints = C;
252 //===----------------------------------------------------------------------===//
253 // ARM specific transformation functions and pattern fragments.
256 // imm_neg_XFORM - Return a imm value packed into the format described for
257 // imm_neg defs below.
258 def imm_neg_XFORM : SDNodeXForm<imm, [{
259 return CurDAG->getTargetConstant(-(int)N->getZExtValue(), MVT::i32);
262 // so_imm_not_XFORM - Return a so_imm value packed into the format described for
263 // so_imm_not def below.
264 def so_imm_not_XFORM : SDNodeXForm<imm, [{
265 return CurDAG->getTargetConstant(~(int)N->getZExtValue(), MVT::i32);
268 /// imm16_31 predicate - True if the 32-bit immediate is in the range [16,31].
269 def imm16_31 : ImmLeaf<i32, [{
270 return (int32_t)Imm >= 16 && (int32_t)Imm < 32;
273 def so_imm_neg_asmoperand : AsmOperandClass { let Name = "ARMSOImmNeg"; }
274 def so_imm_neg : Operand<i32>, PatLeaf<(imm), [{
275 int64_t Value = -(int)N->getZExtValue();
276 return Value && ARM_AM::getSOImmVal(Value) != -1;
278 let ParserMatchClass = so_imm_neg_asmoperand;
281 // Note: this pattern doesn't require an encoder method and such, as it's
282 // only used on aliases (Pat<> and InstAlias<>). The actual encoding
283 // is handled by the destination instructions, which use so_imm.
284 def so_imm_not_asmoperand : AsmOperandClass { let Name = "ARMSOImmNot"; }
285 def so_imm_not : Operand<i32>, PatLeaf<(imm), [{
286 return ARM_AM::getSOImmVal(~(uint32_t)N->getZExtValue()) != -1;
287 }], so_imm_not_XFORM> {
288 let ParserMatchClass = so_imm_not_asmoperand;
291 // sext_16_node predicate - True if the SDNode is sign-extended 16 or more bits.
292 def sext_16_node : PatLeaf<(i32 GPR:$a), [{
293 return CurDAG->ComputeNumSignBits(SDValue(N,0)) >= 17;
296 /// Split a 32-bit immediate into two 16 bit parts.
297 def hi16 : SDNodeXForm<imm, [{
298 return CurDAG->getTargetConstant((uint32_t)N->getZExtValue() >> 16, MVT::i32);
301 def lo16AllZero : PatLeaf<(i32 imm), [{
302 // Returns true if all low 16-bits are 0.
303 return (((uint32_t)N->getZExtValue()) & 0xFFFFUL) == 0;
306 class BinOpWithFlagFrag<dag res> :
307 PatFrag<(ops node:$LHS, node:$RHS, node:$FLAG), res>;
308 class BinOpFrag<dag res> : PatFrag<(ops node:$LHS, node:$RHS), res>;
309 class UnOpFrag <dag res> : PatFrag<(ops node:$Src), res>;
311 // An 'and' node with a single use.
312 def and_su : PatFrag<(ops node:$lhs, node:$rhs), (and node:$lhs, node:$rhs), [{
313 return N->hasOneUse();
316 // An 'xor' node with a single use.
317 def xor_su : PatFrag<(ops node:$lhs, node:$rhs), (xor node:$lhs, node:$rhs), [{
318 return N->hasOneUse();
321 // An 'fmul' node with a single use.
322 def fmul_su : PatFrag<(ops node:$lhs, node:$rhs), (fmul node:$lhs, node:$rhs),[{
323 return N->hasOneUse();
326 // An 'fadd' node which checks for single non-hazardous use.
327 def fadd_mlx : PatFrag<(ops node:$lhs, node:$rhs),(fadd node:$lhs, node:$rhs),[{
328 return hasNoVMLxHazardUse(N);
331 // An 'fsub' node which checks for single non-hazardous use.
332 def fsub_mlx : PatFrag<(ops node:$lhs, node:$rhs),(fsub node:$lhs, node:$rhs),[{
333 return hasNoVMLxHazardUse(N);
336 //===----------------------------------------------------------------------===//
337 // Operand Definitions.
340 // Immediate operands with a shared generic asm render method.
341 class ImmAsmOperand : AsmOperandClass { let RenderMethod = "addImmOperands"; }
344 // FIXME: rename brtarget to t2_brtarget
345 def brtarget : Operand<OtherVT> {
346 let EncoderMethod = "getBranchTargetOpValue";
347 let OperandType = "OPERAND_PCREL";
348 let DecoderMethod = "DecodeT2BROperand";
351 // FIXME: get rid of this one?
352 def uncondbrtarget : Operand<OtherVT> {
353 let EncoderMethod = "getUnconditionalBranchTargetOpValue";
354 let OperandType = "OPERAND_PCREL";
357 // Branch target for ARM. Handles conditional/unconditional
358 def br_target : Operand<OtherVT> {
359 let EncoderMethod = "getARMBranchTargetOpValue";
360 let OperandType = "OPERAND_PCREL";
364 // FIXME: rename bltarget to t2_bl_target?
365 def bltarget : Operand<i32> {
366 // Encoded the same as branch targets.
367 let EncoderMethod = "getBranchTargetOpValue";
368 let OperandType = "OPERAND_PCREL";
371 // Call target for ARM. Handles conditional/unconditional
372 // FIXME: rename bl_target to t2_bltarget?
373 def bl_target : Operand<i32> {
374 let EncoderMethod = "getARMBLTargetOpValue";
375 let OperandType = "OPERAND_PCREL";
378 def blx_target : Operand<i32> {
379 let EncoderMethod = "getARMBLXTargetOpValue";
380 let OperandType = "OPERAND_PCREL";
383 // A list of registers separated by comma. Used by load/store multiple.
384 def RegListAsmOperand : AsmOperandClass { let Name = "RegList"; }
385 def reglist : Operand<i32> {
386 let EncoderMethod = "getRegisterListOpValue";
387 let ParserMatchClass = RegListAsmOperand;
388 let PrintMethod = "printRegisterList";
389 let DecoderMethod = "DecodeRegListOperand";
392 def DPRRegListAsmOperand : AsmOperandClass { let Name = "DPRRegList"; }
393 def dpr_reglist : Operand<i32> {
394 let EncoderMethod = "getRegisterListOpValue";
395 let ParserMatchClass = DPRRegListAsmOperand;
396 let PrintMethod = "printRegisterList";
397 let DecoderMethod = "DecodeDPRRegListOperand";
400 def SPRRegListAsmOperand : AsmOperandClass { let Name = "SPRRegList"; }
401 def spr_reglist : Operand<i32> {
402 let EncoderMethod = "getRegisterListOpValue";
403 let ParserMatchClass = SPRRegListAsmOperand;
404 let PrintMethod = "printRegisterList";
405 let DecoderMethod = "DecodeSPRRegListOperand";
408 // An operand for the CONSTPOOL_ENTRY pseudo-instruction.
409 def cpinst_operand : Operand<i32> {
410 let PrintMethod = "printCPInstOperand";
414 def pclabel : Operand<i32> {
415 let PrintMethod = "printPCLabel";
418 // ADR instruction labels.
419 def adrlabel : Operand<i32> {
420 let EncoderMethod = "getAdrLabelOpValue";
423 def neon_vcvt_imm32 : Operand<i32> {
424 let EncoderMethod = "getNEONVcvtImm32OpValue";
425 let DecoderMethod = "DecodeVCVTImmOperand";
428 // rot_imm: An integer that encodes a rotate amount. Must be 8, 16, or 24.
429 def rot_imm_XFORM: SDNodeXForm<imm, [{
430 switch (N->getZExtValue()){
432 case 0: return CurDAG->getTargetConstant(0, MVT::i32);
433 case 8: return CurDAG->getTargetConstant(1, MVT::i32);
434 case 16: return CurDAG->getTargetConstant(2, MVT::i32);
435 case 24: return CurDAG->getTargetConstant(3, MVT::i32);
438 def RotImmAsmOperand : AsmOperandClass {
440 let ParserMethod = "parseRotImm";
442 def rot_imm : Operand<i32>, PatLeaf<(i32 imm), [{
443 int32_t v = N->getZExtValue();
444 return v == 8 || v == 16 || v == 24; }],
446 let PrintMethod = "printRotImmOperand";
447 let ParserMatchClass = RotImmAsmOperand;
450 // shift_imm: An integer that encodes a shift amount and the type of shift
451 // (asr or lsl). The 6-bit immediate encodes as:
454 // {4-0} imm5 shift amount.
455 // asr #32 encoded as imm5 == 0.
456 def ShifterImmAsmOperand : AsmOperandClass {
457 let Name = "ShifterImm";
458 let ParserMethod = "parseShifterImm";
460 def shift_imm : Operand<i32> {
461 let PrintMethod = "printShiftImmOperand";
462 let ParserMatchClass = ShifterImmAsmOperand;
465 // shifter_operand operands: so_reg_reg, so_reg_imm, and so_imm.
466 def ShiftedRegAsmOperand : AsmOperandClass { let Name = "RegShiftedReg"; }
467 def so_reg_reg : Operand<i32>, // reg reg imm
468 ComplexPattern<i32, 3, "SelectRegShifterOperand",
469 [shl, srl, sra, rotr]> {
470 let EncoderMethod = "getSORegRegOpValue";
471 let PrintMethod = "printSORegRegOperand";
472 let DecoderMethod = "DecodeSORegRegOperand";
473 let ParserMatchClass = ShiftedRegAsmOperand;
474 let MIOperandInfo = (ops GPRnopc, GPRnopc, i32imm);
477 def ShiftedImmAsmOperand : AsmOperandClass { let Name = "RegShiftedImm"; }
478 def so_reg_imm : Operand<i32>, // reg imm
479 ComplexPattern<i32, 2, "SelectImmShifterOperand",
480 [shl, srl, sra, rotr]> {
481 let EncoderMethod = "getSORegImmOpValue";
482 let PrintMethod = "printSORegImmOperand";
483 let DecoderMethod = "DecodeSORegImmOperand";
484 let ParserMatchClass = ShiftedImmAsmOperand;
485 let MIOperandInfo = (ops GPR, i32imm);
488 // FIXME: Does this need to be distinct from so_reg?
489 def shift_so_reg_reg : Operand<i32>, // reg reg imm
490 ComplexPattern<i32, 3, "SelectShiftRegShifterOperand",
491 [shl,srl,sra,rotr]> {
492 let EncoderMethod = "getSORegRegOpValue";
493 let PrintMethod = "printSORegRegOperand";
494 let DecoderMethod = "DecodeSORegRegOperand";
495 let ParserMatchClass = ShiftedRegAsmOperand;
496 let MIOperandInfo = (ops GPR, GPR, i32imm);
499 // FIXME: Does this need to be distinct from so_reg?
500 def shift_so_reg_imm : Operand<i32>, // reg reg imm
501 ComplexPattern<i32, 2, "SelectShiftImmShifterOperand",
502 [shl,srl,sra,rotr]> {
503 let EncoderMethod = "getSORegImmOpValue";
504 let PrintMethod = "printSORegImmOperand";
505 let DecoderMethod = "DecodeSORegImmOperand";
506 let ParserMatchClass = ShiftedImmAsmOperand;
507 let MIOperandInfo = (ops GPR, i32imm);
511 // so_imm - Match a 32-bit shifter_operand immediate operand, which is an
512 // 8-bit immediate rotated by an arbitrary number of bits.
513 def SOImmAsmOperand: ImmAsmOperand { let Name = "ARMSOImm"; }
514 def so_imm : Operand<i32>, ImmLeaf<i32, [{
515 return ARM_AM::getSOImmVal(Imm) != -1;
517 let EncoderMethod = "getSOImmOpValue";
518 let ParserMatchClass = SOImmAsmOperand;
519 let DecoderMethod = "DecodeSOImmOperand";
522 // Break so_imm's up into two pieces. This handles immediates with up to 16
523 // bits set in them. This uses so_imm2part to match and so_imm2part_[12] to
524 // get the first/second pieces.
525 def so_imm2part : PatLeaf<(imm), [{
526 return ARM_AM::isSOImmTwoPartVal((unsigned)N->getZExtValue());
529 /// arm_i32imm - True for +V6T2, or true only if so_imm2part is true.
531 def arm_i32imm : PatLeaf<(imm), [{
532 if (Subtarget->hasV6T2Ops())
534 return ARM_AM::isSOImmTwoPartVal((unsigned)N->getZExtValue());
537 /// imm0_1 predicate - Immediate in the range [0,1].
538 def Imm0_1AsmOperand: ImmAsmOperand { let Name = "Imm0_1"; }
539 def imm0_1 : Operand<i32> { let ParserMatchClass = Imm0_1AsmOperand; }
541 /// imm0_3 predicate - Immediate in the range [0,3].
542 def Imm0_3AsmOperand: ImmAsmOperand { let Name = "Imm0_3"; }
543 def imm0_3 : Operand<i32> { let ParserMatchClass = Imm0_3AsmOperand; }
545 /// imm0_7 predicate - Immediate in the range [0,7].
546 def Imm0_7AsmOperand: ImmAsmOperand { let Name = "Imm0_7"; }
547 def imm0_7 : Operand<i32>, ImmLeaf<i32, [{
548 return Imm >= 0 && Imm < 8;
550 let ParserMatchClass = Imm0_7AsmOperand;
553 /// imm8 predicate - Immediate is exactly 8.
554 def Imm8AsmOperand: ImmAsmOperand { let Name = "Imm8"; }
555 def imm8 : Operand<i32>, ImmLeaf<i32, [{ return Imm == 8; }]> {
556 let ParserMatchClass = Imm8AsmOperand;
559 /// imm16 predicate - Immediate is exactly 16.
560 def Imm16AsmOperand: ImmAsmOperand { let Name = "Imm16"; }
561 def imm16 : Operand<i32>, ImmLeaf<i32, [{ return Imm == 16; }]> {
562 let ParserMatchClass = Imm16AsmOperand;
565 /// imm32 predicate - Immediate is exactly 32.
566 def Imm32AsmOperand: ImmAsmOperand { let Name = "Imm32"; }
567 def imm32 : Operand<i32>, ImmLeaf<i32, [{ return Imm == 32; }]> {
568 let ParserMatchClass = Imm32AsmOperand;
571 /// imm1_7 predicate - Immediate in the range [1,7].
572 def Imm1_7AsmOperand: ImmAsmOperand { let Name = "Imm1_7"; }
573 def imm1_7 : Operand<i32>, ImmLeaf<i32, [{ return Imm > 0 && Imm < 8; }]> {
574 let ParserMatchClass = Imm1_7AsmOperand;
577 /// imm1_15 predicate - Immediate in the range [1,15].
578 def Imm1_15AsmOperand: ImmAsmOperand { let Name = "Imm1_15"; }
579 def imm1_15 : Operand<i32>, ImmLeaf<i32, [{ return Imm > 0 && Imm < 16; }]> {
580 let ParserMatchClass = Imm1_15AsmOperand;
583 /// imm1_31 predicate - Immediate in the range [1,31].
584 def Imm1_31AsmOperand: ImmAsmOperand { let Name = "Imm1_31"; }
585 def imm1_31 : Operand<i32>, ImmLeaf<i32, [{ return Imm > 0 && Imm < 32; }]> {
586 let ParserMatchClass = Imm1_31AsmOperand;
589 /// imm0_15 predicate - Immediate in the range [0,15].
590 def Imm0_15AsmOperand: ImmAsmOperand {
591 let Name = "Imm0_15";
592 let DiagnosticType = "ImmRange0_15";
594 def imm0_15 : Operand<i32>, ImmLeaf<i32, [{
595 return Imm >= 0 && Imm < 16;
597 let ParserMatchClass = Imm0_15AsmOperand;
600 /// imm0_31 predicate - True if the 32-bit immediate is in the range [0,31].
601 def Imm0_31AsmOperand: ImmAsmOperand { let Name = "Imm0_31"; }
602 def imm0_31 : Operand<i32>, ImmLeaf<i32, [{
603 return Imm >= 0 && Imm < 32;
605 let ParserMatchClass = Imm0_31AsmOperand;
608 /// imm0_32 predicate - True if the 32-bit immediate is in the range [0,32].
609 def Imm0_32AsmOperand: ImmAsmOperand { let Name = "Imm0_32"; }
610 def imm0_32 : Operand<i32>, ImmLeaf<i32, [{
611 return Imm >= 0 && Imm < 32;
613 let ParserMatchClass = Imm0_32AsmOperand;
616 /// imm0_63 predicate - True if the 32-bit immediate is in the range [0,63].
617 def Imm0_63AsmOperand: ImmAsmOperand { let Name = "Imm0_63"; }
618 def imm0_63 : Operand<i32>, ImmLeaf<i32, [{
619 return Imm >= 0 && Imm < 64;
621 let ParserMatchClass = Imm0_63AsmOperand;
624 /// imm0_255 predicate - Immediate in the range [0,255].
625 def Imm0_255AsmOperand : ImmAsmOperand { let Name = "Imm0_255"; }
626 def imm0_255 : Operand<i32>, ImmLeaf<i32, [{ return Imm >= 0 && Imm < 256; }]> {
627 let ParserMatchClass = Imm0_255AsmOperand;
630 /// imm0_65535 - An immediate is in the range [0.65535].
631 def Imm0_65535AsmOperand: ImmAsmOperand { let Name = "Imm0_65535"; }
632 def imm0_65535 : Operand<i32>, ImmLeaf<i32, [{
633 return Imm >= 0 && Imm < 65536;
635 let ParserMatchClass = Imm0_65535AsmOperand;
638 // imm0_65535_neg - An immediate whose negative value is in the range [0.65535].
639 def imm0_65535_neg : Operand<i32>, ImmLeaf<i32, [{
640 return -Imm >= 0 && -Imm < 65536;
643 // imm0_65535_expr - For movt/movw - 16-bit immediate that can also reference
644 // a relocatable expression.
646 // FIXME: This really needs a Thumb version separate from the ARM version.
647 // While the range is the same, and can thus use the same match class,
648 // the encoding is different so it should have a different encoder method.
649 def Imm0_65535ExprAsmOperand: ImmAsmOperand { let Name = "Imm0_65535Expr"; }
650 def imm0_65535_expr : Operand<i32> {
651 let EncoderMethod = "getHiLo16ImmOpValue";
652 let ParserMatchClass = Imm0_65535ExprAsmOperand;
655 /// imm24b - True if the 32-bit immediate is encodable in 24 bits.
656 def Imm24bitAsmOperand: ImmAsmOperand { let Name = "Imm24bit"; }
657 def imm24b : Operand<i32>, ImmLeaf<i32, [{
658 return Imm >= 0 && Imm <= 0xffffff;
660 let ParserMatchClass = Imm24bitAsmOperand;
664 /// bf_inv_mask_imm predicate - An AND mask to clear an arbitrary width bitfield
666 def BitfieldAsmOperand : AsmOperandClass {
667 let Name = "Bitfield";
668 let ParserMethod = "parseBitfield";
671 def bf_inv_mask_imm : Operand<i32>,
673 return ARM::isBitFieldInvertedMask(N->getZExtValue());
675 let EncoderMethod = "getBitfieldInvertedMaskOpValue";
676 let PrintMethod = "printBitfieldInvMaskImmOperand";
677 let DecoderMethod = "DecodeBitfieldMaskOperand";
678 let ParserMatchClass = BitfieldAsmOperand;
681 def imm1_32_XFORM: SDNodeXForm<imm, [{
682 return CurDAG->getTargetConstant((int)N->getZExtValue() - 1, MVT::i32);
684 def Imm1_32AsmOperand: AsmOperandClass { let Name = "Imm1_32"; }
685 def imm1_32 : Operand<i32>, PatLeaf<(imm), [{
686 uint64_t Imm = N->getZExtValue();
687 return Imm > 0 && Imm <= 32;
690 let PrintMethod = "printImmPlusOneOperand";
691 let ParserMatchClass = Imm1_32AsmOperand;
694 def imm1_16_XFORM: SDNodeXForm<imm, [{
695 return CurDAG->getTargetConstant((int)N->getZExtValue() - 1, MVT::i32);
697 def Imm1_16AsmOperand: AsmOperandClass { let Name = "Imm1_16"; }
698 def imm1_16 : Operand<i32>, PatLeaf<(imm), [{ return Imm > 0 && Imm <= 16; }],
700 let PrintMethod = "printImmPlusOneOperand";
701 let ParserMatchClass = Imm1_16AsmOperand;
704 // Define ARM specific addressing modes.
705 // addrmode_imm12 := reg +/- imm12
707 def MemImm12OffsetAsmOperand : AsmOperandClass { let Name = "MemImm12Offset"; }
708 def addrmode_imm12 : Operand<i32>,
709 ComplexPattern<i32, 2, "SelectAddrModeImm12", []> {
710 // 12-bit immediate operand. Note that instructions using this encode
711 // #0 and #-0 differently. We flag #-0 as the magic value INT32_MIN. All other
712 // immediate values are as normal.
714 let EncoderMethod = "getAddrModeImm12OpValue";
715 let PrintMethod = "printAddrModeImm12Operand";
716 let DecoderMethod = "DecodeAddrModeImm12Operand";
717 let ParserMatchClass = MemImm12OffsetAsmOperand;
718 let MIOperandInfo = (ops GPR:$base, i32imm:$offsimm);
720 // ldst_so_reg := reg +/- reg shop imm
722 def MemRegOffsetAsmOperand : AsmOperandClass { let Name = "MemRegOffset"; }
723 def ldst_so_reg : Operand<i32>,
724 ComplexPattern<i32, 3, "SelectLdStSOReg", []> {
725 let EncoderMethod = "getLdStSORegOpValue";
726 // FIXME: Simplify the printer
727 let PrintMethod = "printAddrMode2Operand";
728 let DecoderMethod = "DecodeSORegMemOperand";
729 let ParserMatchClass = MemRegOffsetAsmOperand;
730 let MIOperandInfo = (ops GPR:$base, GPRnopc:$offsreg, i32imm:$shift);
733 // postidx_imm8 := +/- [0,255]
736 // {8} 1 is imm8 is non-negative. 0 otherwise.
737 // {7-0} [0,255] imm8 value.
738 def PostIdxImm8AsmOperand : AsmOperandClass { let Name = "PostIdxImm8"; }
739 def postidx_imm8 : Operand<i32> {
740 let PrintMethod = "printPostIdxImm8Operand";
741 let ParserMatchClass = PostIdxImm8AsmOperand;
742 let MIOperandInfo = (ops i32imm);
745 // postidx_imm8s4 := +/- [0,1020]
748 // {8} 1 is imm8 is non-negative. 0 otherwise.
749 // {7-0} [0,255] imm8 value, scaled by 4.
750 def PostIdxImm8s4AsmOperand : AsmOperandClass { let Name = "PostIdxImm8s4"; }
751 def postidx_imm8s4 : Operand<i32> {
752 let PrintMethod = "printPostIdxImm8s4Operand";
753 let ParserMatchClass = PostIdxImm8s4AsmOperand;
754 let MIOperandInfo = (ops i32imm);
758 // postidx_reg := +/- reg
760 def PostIdxRegAsmOperand : AsmOperandClass {
761 let Name = "PostIdxReg";
762 let ParserMethod = "parsePostIdxReg";
764 def postidx_reg : Operand<i32> {
765 let EncoderMethod = "getPostIdxRegOpValue";
766 let DecoderMethod = "DecodePostIdxReg";
767 let PrintMethod = "printPostIdxRegOperand";
768 let ParserMatchClass = PostIdxRegAsmOperand;
769 let MIOperandInfo = (ops GPRnopc, i32imm);
773 // addrmode2 := reg +/- imm12
774 // := reg +/- reg shop imm
776 // FIXME: addrmode2 should be refactored the rest of the way to always
777 // use explicit imm vs. reg versions above (addrmode_imm12 and ldst_so_reg).
778 def AddrMode2AsmOperand : AsmOperandClass { let Name = "AddrMode2"; }
779 def addrmode2 : Operand<i32>,
780 ComplexPattern<i32, 3, "SelectAddrMode2", []> {
781 let EncoderMethod = "getAddrMode2OpValue";
782 let PrintMethod = "printAddrMode2Operand";
783 let ParserMatchClass = AddrMode2AsmOperand;
784 let MIOperandInfo = (ops GPR:$base, GPR:$offsreg, i32imm:$offsimm);
787 def PostIdxRegShiftedAsmOperand : AsmOperandClass {
788 let Name = "PostIdxRegShifted";
789 let ParserMethod = "parsePostIdxReg";
791 def am2offset_reg : Operand<i32>,
792 ComplexPattern<i32, 2, "SelectAddrMode2OffsetReg",
793 [], [SDNPWantRoot]> {
794 let EncoderMethod = "getAddrMode2OffsetOpValue";
795 let PrintMethod = "printAddrMode2OffsetOperand";
796 // When using this for assembly, it's always as a post-index offset.
797 let ParserMatchClass = PostIdxRegShiftedAsmOperand;
798 let MIOperandInfo = (ops GPRnopc, i32imm);
801 // FIXME: am2offset_imm should only need the immediate, not the GPR. Having
802 // the GPR is purely vestigal at this point.
803 def AM2OffsetImmAsmOperand : AsmOperandClass { let Name = "AM2OffsetImm"; }
804 def am2offset_imm : Operand<i32>,
805 ComplexPattern<i32, 2, "SelectAddrMode2OffsetImm",
806 [], [SDNPWantRoot]> {
807 let EncoderMethod = "getAddrMode2OffsetOpValue";
808 let PrintMethod = "printAddrMode2OffsetOperand";
809 let ParserMatchClass = AM2OffsetImmAsmOperand;
810 let MIOperandInfo = (ops GPRnopc, i32imm);
814 // addrmode3 := reg +/- reg
815 // addrmode3 := reg +/- imm8
817 // FIXME: split into imm vs. reg versions.
818 def AddrMode3AsmOperand : AsmOperandClass { let Name = "AddrMode3"; }
819 def addrmode3 : Operand<i32>,
820 ComplexPattern<i32, 3, "SelectAddrMode3", []> {
821 let EncoderMethod = "getAddrMode3OpValue";
822 let PrintMethod = "printAddrMode3Operand";
823 let ParserMatchClass = AddrMode3AsmOperand;
824 let MIOperandInfo = (ops GPR:$base, GPR:$offsreg, i32imm:$offsimm);
827 // FIXME: split into imm vs. reg versions.
828 // FIXME: parser method to handle +/- register.
829 def AM3OffsetAsmOperand : AsmOperandClass {
830 let Name = "AM3Offset";
831 let ParserMethod = "parseAM3Offset";
833 def am3offset : Operand<i32>,
834 ComplexPattern<i32, 2, "SelectAddrMode3Offset",
835 [], [SDNPWantRoot]> {
836 let EncoderMethod = "getAddrMode3OffsetOpValue";
837 let PrintMethod = "printAddrMode3OffsetOperand";
838 let ParserMatchClass = AM3OffsetAsmOperand;
839 let MIOperandInfo = (ops GPR, i32imm);
842 // ldstm_mode := {ia, ib, da, db}
844 def ldstm_mode : OptionalDefOperand<OtherVT, (ops i32), (ops (i32 1))> {
845 let EncoderMethod = "getLdStmModeOpValue";
846 let PrintMethod = "printLdStmModeOperand";
849 // addrmode5 := reg +/- imm8*4
851 def AddrMode5AsmOperand : AsmOperandClass { let Name = "AddrMode5"; }
852 def addrmode5 : Operand<i32>,
853 ComplexPattern<i32, 2, "SelectAddrMode5", []> {
854 let PrintMethod = "printAddrMode5Operand";
855 let EncoderMethod = "getAddrMode5OpValue";
856 let DecoderMethod = "DecodeAddrMode5Operand";
857 let ParserMatchClass = AddrMode5AsmOperand;
858 let MIOperandInfo = (ops GPR:$base, i32imm);
861 // addrmode6 := reg with optional alignment
863 def AddrMode6AsmOperand : AsmOperandClass { let Name = "AlignedMemory"; }
864 def addrmode6 : Operand<i32>,
865 ComplexPattern<i32, 2, "SelectAddrMode6", [], [SDNPWantParent]>{
866 let PrintMethod = "printAddrMode6Operand";
867 let MIOperandInfo = (ops GPR:$addr, i32imm:$align);
868 let EncoderMethod = "getAddrMode6AddressOpValue";
869 let DecoderMethod = "DecodeAddrMode6Operand";
870 let ParserMatchClass = AddrMode6AsmOperand;
873 def am6offset : Operand<i32>,
874 ComplexPattern<i32, 1, "SelectAddrMode6Offset",
875 [], [SDNPWantRoot]> {
876 let PrintMethod = "printAddrMode6OffsetOperand";
877 let MIOperandInfo = (ops GPR);
878 let EncoderMethod = "getAddrMode6OffsetOpValue";
879 let DecoderMethod = "DecodeGPRRegisterClass";
882 // Special version of addrmode6 to handle alignment encoding for VST1/VLD1
883 // (single element from one lane) for size 32.
884 def addrmode6oneL32 : Operand<i32>,
885 ComplexPattern<i32, 2, "SelectAddrMode6", [], [SDNPWantParent]>{
886 let PrintMethod = "printAddrMode6Operand";
887 let MIOperandInfo = (ops GPR:$addr, i32imm);
888 let EncoderMethod = "getAddrMode6OneLane32AddressOpValue";
891 // Special version of addrmode6 to handle alignment encoding for VLD-dup
892 // instructions, specifically VLD4-dup.
893 def addrmode6dup : Operand<i32>,
894 ComplexPattern<i32, 2, "SelectAddrMode6", [], [SDNPWantParent]>{
895 let PrintMethod = "printAddrMode6Operand";
896 let MIOperandInfo = (ops GPR:$addr, i32imm);
897 let EncoderMethod = "getAddrMode6DupAddressOpValue";
898 // FIXME: This is close, but not quite right. The alignment specifier is
900 let ParserMatchClass = AddrMode6AsmOperand;
903 // addrmodepc := pc + reg
905 def addrmodepc : Operand<i32>,
906 ComplexPattern<i32, 2, "SelectAddrModePC", []> {
907 let PrintMethod = "printAddrModePCOperand";
908 let MIOperandInfo = (ops GPR, i32imm);
911 // addr_offset_none := reg
913 def MemNoOffsetAsmOperand : AsmOperandClass { let Name = "MemNoOffset"; }
914 def addr_offset_none : Operand<i32>,
915 ComplexPattern<i32, 1, "SelectAddrOffsetNone", []> {
916 let PrintMethod = "printAddrMode7Operand";
917 let DecoderMethod = "DecodeAddrMode7Operand";
918 let ParserMatchClass = MemNoOffsetAsmOperand;
919 let MIOperandInfo = (ops GPR:$base);
922 def nohash_imm : Operand<i32> {
923 let PrintMethod = "printNoHashImmediate";
926 def CoprocNumAsmOperand : AsmOperandClass {
927 let Name = "CoprocNum";
928 let ParserMethod = "parseCoprocNumOperand";
930 def p_imm : Operand<i32> {
931 let PrintMethod = "printPImmediate";
932 let ParserMatchClass = CoprocNumAsmOperand;
933 let DecoderMethod = "DecodeCoprocessor";
936 def pf_imm : Operand<i32> {
937 let PrintMethod = "printPImmediate";
938 let ParserMatchClass = CoprocNumAsmOperand;
941 def CoprocRegAsmOperand : AsmOperandClass {
942 let Name = "CoprocReg";
943 let ParserMethod = "parseCoprocRegOperand";
945 def c_imm : Operand<i32> {
946 let PrintMethod = "printCImmediate";
947 let ParserMatchClass = CoprocRegAsmOperand;
949 def CoprocOptionAsmOperand : AsmOperandClass {
950 let Name = "CoprocOption";
951 let ParserMethod = "parseCoprocOptionOperand";
953 def coproc_option_imm : Operand<i32> {
954 let PrintMethod = "printCoprocOptionImm";
955 let ParserMatchClass = CoprocOptionAsmOperand;
958 //===----------------------------------------------------------------------===//
960 include "ARMInstrFormats.td"
962 //===----------------------------------------------------------------------===//
963 // Multiclass helpers...
966 /// AsI1_bin_irs - Defines a set of (op r, {so_imm|r|so_reg}) patterns for a
967 /// binop that produces a value.
968 let TwoOperandAliasConstraint = "$Rn = $Rd" in
969 multiclass AsI1_bin_irs<bits<4> opcod, string opc,
970 InstrItinClass iii, InstrItinClass iir, InstrItinClass iis,
971 PatFrag opnode, string baseOpc, bit Commutable = 0> {
972 // The register-immediate version is re-materializable. This is useful
973 // in particular for taking the address of a local.
974 let isReMaterializable = 1 in {
975 def ri : AsI1<opcod, (outs GPR:$Rd), (ins GPR:$Rn, so_imm:$imm), DPFrm,
976 iii, opc, "\t$Rd, $Rn, $imm",
977 [(set GPR:$Rd, (opnode GPR:$Rn, so_imm:$imm))]> {
982 let Inst{19-16} = Rn;
983 let Inst{15-12} = Rd;
984 let Inst{11-0} = imm;
987 def rr : AsI1<opcod, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm), DPFrm,
988 iir, opc, "\t$Rd, $Rn, $Rm",
989 [(set GPR:$Rd, (opnode GPR:$Rn, GPR:$Rm))]> {
994 let isCommutable = Commutable;
995 let Inst{19-16} = Rn;
996 let Inst{15-12} = Rd;
997 let Inst{11-4} = 0b00000000;
1001 def rsi : AsI1<opcod, (outs GPR:$Rd),
1002 (ins GPR:$Rn, so_reg_imm:$shift), DPSoRegImmFrm,
1003 iis, opc, "\t$Rd, $Rn, $shift",
1004 [(set GPR:$Rd, (opnode GPR:$Rn, so_reg_imm:$shift))]> {
1009 let Inst{19-16} = Rn;
1010 let Inst{15-12} = Rd;
1011 let Inst{11-5} = shift{11-5};
1013 let Inst{3-0} = shift{3-0};
1016 def rsr : AsI1<opcod, (outs GPR:$Rd),
1017 (ins GPR:$Rn, so_reg_reg:$shift), DPSoRegRegFrm,
1018 iis, opc, "\t$Rd, $Rn, $shift",
1019 [(set GPR:$Rd, (opnode GPR:$Rn, so_reg_reg:$shift))]> {
1024 let Inst{19-16} = Rn;
1025 let Inst{15-12} = Rd;
1026 let Inst{11-8} = shift{11-8};
1028 let Inst{6-5} = shift{6-5};
1030 let Inst{3-0} = shift{3-0};
1034 /// AsI1_rbin_irs - Same as AsI1_bin_irs except the order of operands are
1035 /// reversed. The 'rr' form is only defined for the disassembler; for codegen
1036 /// it is equivalent to the AsI1_bin_irs counterpart.
1037 let TwoOperandAliasConstraint = "$Rn = $Rd" in
1038 multiclass AsI1_rbin_irs<bits<4> opcod, string opc,
1039 InstrItinClass iii, InstrItinClass iir, InstrItinClass iis,
1040 PatFrag opnode, string baseOpc, bit Commutable = 0> {
1041 // The register-immediate version is re-materializable. This is useful
1042 // in particular for taking the address of a local.
1043 let isReMaterializable = 1 in {
1044 def ri : AsI1<opcod, (outs GPR:$Rd), (ins GPR:$Rn, so_imm:$imm), DPFrm,
1045 iii, opc, "\t$Rd, $Rn, $imm",
1046 [(set GPR:$Rd, (opnode so_imm:$imm, GPR:$Rn))]> {
1051 let Inst{19-16} = Rn;
1052 let Inst{15-12} = Rd;
1053 let Inst{11-0} = imm;
1056 def rr : AsI1<opcod, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm), DPFrm,
1057 iir, opc, "\t$Rd, $Rn, $Rm",
1058 [/* pattern left blank */]> {
1062 let Inst{11-4} = 0b00000000;
1065 let Inst{15-12} = Rd;
1066 let Inst{19-16} = Rn;
1069 def rsi : AsI1<opcod, (outs GPR:$Rd),
1070 (ins GPR:$Rn, so_reg_imm:$shift), DPSoRegImmFrm,
1071 iis, opc, "\t$Rd, $Rn, $shift",
1072 [(set GPR:$Rd, (opnode so_reg_imm:$shift, GPR:$Rn))]> {
1077 let Inst{19-16} = Rn;
1078 let Inst{15-12} = Rd;
1079 let Inst{11-5} = shift{11-5};
1081 let Inst{3-0} = shift{3-0};
1084 def rsr : AsI1<opcod, (outs GPR:$Rd),
1085 (ins GPR:$Rn, so_reg_reg:$shift), DPSoRegRegFrm,
1086 iis, opc, "\t$Rd, $Rn, $shift",
1087 [(set GPR:$Rd, (opnode so_reg_reg:$shift, GPR:$Rn))]> {
1092 let Inst{19-16} = Rn;
1093 let Inst{15-12} = Rd;
1094 let Inst{11-8} = shift{11-8};
1096 let Inst{6-5} = shift{6-5};
1098 let Inst{3-0} = shift{3-0};
1102 /// AsI1_bin_s_irs - Same as AsI1_bin_irs except it sets the 's' bit by default.
1104 /// These opcodes will be converted to the real non-S opcodes by
1105 /// AdjustInstrPostInstrSelection after giving them an optional CPSR operand.
1106 let hasPostISelHook = 1, Defs = [CPSR] in {
1107 multiclass AsI1_bin_s_irs<InstrItinClass iii, InstrItinClass iir,
1108 InstrItinClass iis, PatFrag opnode,
1109 bit Commutable = 0> {
1110 def ri : ARMPseudoInst<(outs GPR:$Rd), (ins GPR:$Rn, so_imm:$imm, pred:$p),
1112 [(set GPR:$Rd, CPSR, (opnode GPR:$Rn, so_imm:$imm))]>;
1114 def rr : ARMPseudoInst<(outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm, pred:$p),
1116 [(set GPR:$Rd, CPSR, (opnode GPR:$Rn, GPR:$Rm))]> {
1117 let isCommutable = Commutable;
1119 def rsi : ARMPseudoInst<(outs GPR:$Rd),
1120 (ins GPR:$Rn, so_reg_imm:$shift, pred:$p),
1122 [(set GPR:$Rd, CPSR, (opnode GPR:$Rn,
1123 so_reg_imm:$shift))]>;
1125 def rsr : ARMPseudoInst<(outs GPR:$Rd),
1126 (ins GPR:$Rn, so_reg_reg:$shift, pred:$p),
1128 [(set GPR:$Rd, CPSR, (opnode GPR:$Rn,
1129 so_reg_reg:$shift))]>;
1133 /// AsI1_rbin_s_is - Same as AsI1_bin_s_irs, except selection DAG
1134 /// operands are reversed.
1135 let hasPostISelHook = 1, Defs = [CPSR] in {
1136 multiclass AsI1_rbin_s_is<InstrItinClass iii, InstrItinClass iir,
1137 InstrItinClass iis, PatFrag opnode,
1138 bit Commutable = 0> {
1139 def ri : ARMPseudoInst<(outs GPR:$Rd), (ins GPR:$Rn, so_imm:$imm, pred:$p),
1141 [(set GPR:$Rd, CPSR, (opnode so_imm:$imm, GPR:$Rn))]>;
1143 def rsi : ARMPseudoInst<(outs GPR:$Rd),
1144 (ins GPR:$Rn, so_reg_imm:$shift, pred:$p),
1146 [(set GPR:$Rd, CPSR, (opnode so_reg_imm:$shift,
1149 def rsr : ARMPseudoInst<(outs GPR:$Rd),
1150 (ins GPR:$Rn, so_reg_reg:$shift, pred:$p),
1152 [(set GPR:$Rd, CPSR, (opnode so_reg_reg:$shift,
1157 /// AI1_cmp_irs - Defines a set of (op r, {so_imm|r|so_reg}) cmp / test
1158 /// patterns. Similar to AsI1_bin_irs except the instruction does not produce
1159 /// a explicit result, only implicitly set CPSR.
1160 let isCompare = 1, Defs = [CPSR] in {
1161 multiclass AI1_cmp_irs<bits<4> opcod, string opc,
1162 InstrItinClass iii, InstrItinClass iir, InstrItinClass iis,
1163 PatFrag opnode, bit Commutable = 0> {
1164 def ri : AI1<opcod, (outs), (ins GPR:$Rn, so_imm:$imm), DPFrm, iii,
1166 [(opnode GPR:$Rn, so_imm:$imm)]> {
1171 let Inst{19-16} = Rn;
1172 let Inst{15-12} = 0b0000;
1173 let Inst{11-0} = imm;
1175 let Unpredictable{15-12} = 0b1111;
1177 def rr : AI1<opcod, (outs), (ins GPR:$Rn, GPR:$Rm), DPFrm, iir,
1179 [(opnode GPR:$Rn, GPR:$Rm)]> {
1182 let isCommutable = Commutable;
1185 let Inst{19-16} = Rn;
1186 let Inst{15-12} = 0b0000;
1187 let Inst{11-4} = 0b00000000;
1190 let Unpredictable{15-12} = 0b1111;
1192 def rsi : AI1<opcod, (outs),
1193 (ins GPR:$Rn, so_reg_imm:$shift), DPSoRegImmFrm, iis,
1194 opc, "\t$Rn, $shift",
1195 [(opnode GPR:$Rn, so_reg_imm:$shift)]> {
1200 let Inst{19-16} = Rn;
1201 let Inst{15-12} = 0b0000;
1202 let Inst{11-5} = shift{11-5};
1204 let Inst{3-0} = shift{3-0};
1206 let Unpredictable{15-12} = 0b1111;
1208 def rsr : AI1<opcod, (outs),
1209 (ins GPRnopc:$Rn, so_reg_reg:$shift), DPSoRegRegFrm, iis,
1210 opc, "\t$Rn, $shift",
1211 [(opnode GPRnopc:$Rn, so_reg_reg:$shift)]> {
1216 let Inst{19-16} = Rn;
1217 let Inst{15-12} = 0b0000;
1218 let Inst{11-8} = shift{11-8};
1220 let Inst{6-5} = shift{6-5};
1222 let Inst{3-0} = shift{3-0};
1224 let Unpredictable{15-12} = 0b1111;
1230 /// AI_ext_rrot - A unary operation with two forms: one whose operand is a
1231 /// register and one whose operand is a register rotated by 8/16/24.
1232 /// FIXME: Remove the 'r' variant. Its rot_imm is zero.
1233 class AI_ext_rrot<bits<8> opcod, string opc, PatFrag opnode>
1234 : AExtI<opcod, (outs GPRnopc:$Rd), (ins GPRnopc:$Rm, rot_imm:$rot),
1235 IIC_iEXTr, opc, "\t$Rd, $Rm$rot",
1236 [(set GPRnopc:$Rd, (opnode (rotr GPRnopc:$Rm, rot_imm:$rot)))]>,
1237 Requires<[IsARM, HasV6]> {
1241 let Inst{19-16} = 0b1111;
1242 let Inst{15-12} = Rd;
1243 let Inst{11-10} = rot;
1247 class AI_ext_rrot_np<bits<8> opcod, string opc>
1248 : AExtI<opcod, (outs GPRnopc:$Rd), (ins GPRnopc:$Rm, rot_imm:$rot),
1249 IIC_iEXTr, opc, "\t$Rd, $Rm$rot", []>,
1250 Requires<[IsARM, HasV6]> {
1252 let Inst{19-16} = 0b1111;
1253 let Inst{11-10} = rot;
1256 /// AI_exta_rrot - A binary operation with two forms: one whose operand is a
1257 /// register and one whose operand is a register rotated by 8/16/24.
1258 class AI_exta_rrot<bits<8> opcod, string opc, PatFrag opnode>
1259 : AExtI<opcod, (outs GPRnopc:$Rd), (ins GPR:$Rn, GPRnopc:$Rm, rot_imm:$rot),
1260 IIC_iEXTAr, opc, "\t$Rd, $Rn, $Rm$rot",
1261 [(set GPRnopc:$Rd, (opnode GPR:$Rn,
1262 (rotr GPRnopc:$Rm, rot_imm:$rot)))]>,
1263 Requires<[IsARM, HasV6]> {
1268 let Inst{19-16} = Rn;
1269 let Inst{15-12} = Rd;
1270 let Inst{11-10} = rot;
1271 let Inst{9-4} = 0b000111;
1275 class AI_exta_rrot_np<bits<8> opcod, string opc>
1276 : AExtI<opcod, (outs GPRnopc:$Rd), (ins GPR:$Rn, GPRnopc:$Rm, rot_imm:$rot),
1277 IIC_iEXTAr, opc, "\t$Rd, $Rn, $Rm$rot", []>,
1278 Requires<[IsARM, HasV6]> {
1281 let Inst{19-16} = Rn;
1282 let Inst{11-10} = rot;
1285 /// AI1_adde_sube_irs - Define instructions and patterns for adde and sube.
1286 let TwoOperandAliasConstraint = "$Rn = $Rd" in
1287 multiclass AI1_adde_sube_irs<bits<4> opcod, string opc, PatFrag opnode,
1288 string baseOpc, bit Commutable = 0> {
1289 let hasPostISelHook = 1, Defs = [CPSR], Uses = [CPSR] in {
1290 def ri : AsI1<opcod, (outs GPR:$Rd), (ins GPR:$Rn, so_imm:$imm),
1291 DPFrm, IIC_iALUi, opc, "\t$Rd, $Rn, $imm",
1292 [(set GPR:$Rd, CPSR, (opnode GPR:$Rn, so_imm:$imm, CPSR))]>,
1298 let Inst{15-12} = Rd;
1299 let Inst{19-16} = Rn;
1300 let Inst{11-0} = imm;
1302 def rr : AsI1<opcod, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm),
1303 DPFrm, IIC_iALUr, opc, "\t$Rd, $Rn, $Rm",
1304 [(set GPR:$Rd, CPSR, (opnode GPR:$Rn, GPR:$Rm, CPSR))]>,
1309 let Inst{11-4} = 0b00000000;
1311 let isCommutable = Commutable;
1313 let Inst{15-12} = Rd;
1314 let Inst{19-16} = Rn;
1316 def rsi : AsI1<opcod, (outs GPR:$Rd),
1317 (ins GPR:$Rn, so_reg_imm:$shift),
1318 DPSoRegImmFrm, IIC_iALUsr, opc, "\t$Rd, $Rn, $shift",
1319 [(set GPR:$Rd, CPSR, (opnode GPR:$Rn, so_reg_imm:$shift, CPSR))]>,
1325 let Inst{19-16} = Rn;
1326 let Inst{15-12} = Rd;
1327 let Inst{11-5} = shift{11-5};
1329 let Inst{3-0} = shift{3-0};
1331 def rsr : AsI1<opcod, (outs GPRnopc:$Rd),
1332 (ins GPRnopc:$Rn, so_reg_reg:$shift),
1333 DPSoRegRegFrm, IIC_iALUsr, opc, "\t$Rd, $Rn, $shift",
1334 [(set GPRnopc:$Rd, CPSR,
1335 (opnode GPRnopc:$Rn, so_reg_reg:$shift, CPSR))]>,
1341 let Inst{19-16} = Rn;
1342 let Inst{15-12} = Rd;
1343 let Inst{11-8} = shift{11-8};
1345 let Inst{6-5} = shift{6-5};
1347 let Inst{3-0} = shift{3-0};
1352 /// AI1_rsc_irs - Define instructions and patterns for rsc
1353 let TwoOperandAliasConstraint = "$Rn = $Rd" in
1354 multiclass AI1_rsc_irs<bits<4> opcod, string opc, PatFrag opnode,
1356 let hasPostISelHook = 1, Defs = [CPSR], Uses = [CPSR] in {
1357 def ri : AsI1<opcod, (outs GPR:$Rd), (ins GPR:$Rn, so_imm:$imm),
1358 DPFrm, IIC_iALUi, opc, "\t$Rd, $Rn, $imm",
1359 [(set GPR:$Rd, CPSR, (opnode so_imm:$imm, GPR:$Rn, CPSR))]>,
1365 let Inst{15-12} = Rd;
1366 let Inst{19-16} = Rn;
1367 let Inst{11-0} = imm;
1369 def rr : AsI1<opcod, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm),
1370 DPFrm, IIC_iALUr, opc, "\t$Rd, $Rn, $Rm",
1371 [/* pattern left blank */]> {
1375 let Inst{11-4} = 0b00000000;
1378 let Inst{15-12} = Rd;
1379 let Inst{19-16} = Rn;
1381 def rsi : AsI1<opcod, (outs GPR:$Rd), (ins GPR:$Rn, so_reg_imm:$shift),
1382 DPSoRegImmFrm, IIC_iALUsr, opc, "\t$Rd, $Rn, $shift",
1383 [(set GPR:$Rd, CPSR, (opnode so_reg_imm:$shift, GPR:$Rn, CPSR))]>,
1389 let Inst{19-16} = Rn;
1390 let Inst{15-12} = Rd;
1391 let Inst{11-5} = shift{11-5};
1393 let Inst{3-0} = shift{3-0};
1395 def rsr : AsI1<opcod, (outs GPR:$Rd), (ins GPR:$Rn, so_reg_reg:$shift),
1396 DPSoRegRegFrm, IIC_iALUsr, opc, "\t$Rd, $Rn, $shift",
1397 [(set GPR:$Rd, CPSR, (opnode so_reg_reg:$shift, GPR:$Rn, CPSR))]>,
1403 let Inst{19-16} = Rn;
1404 let Inst{15-12} = Rd;
1405 let Inst{11-8} = shift{11-8};
1407 let Inst{6-5} = shift{6-5};
1409 let Inst{3-0} = shift{3-0};
1414 let canFoldAsLoad = 1, isReMaterializable = 1 in {
1415 multiclass AI_ldr1<bit isByte, string opc, InstrItinClass iii,
1416 InstrItinClass iir, PatFrag opnode> {
1417 // Note: We use the complex addrmode_imm12 rather than just an input
1418 // GPR and a constrained immediate so that we can use this to match
1419 // frame index references and avoid matching constant pool references.
1420 def i12: AI2ldst<0b010, 1, isByte, (outs GPR:$Rt), (ins addrmode_imm12:$addr),
1421 AddrMode_i12, LdFrm, iii, opc, "\t$Rt, $addr",
1422 [(set GPR:$Rt, (opnode addrmode_imm12:$addr))]> {
1425 let Inst{23} = addr{12}; // U (add = ('U' == 1))
1426 let Inst{19-16} = addr{16-13}; // Rn
1427 let Inst{15-12} = Rt;
1428 let Inst{11-0} = addr{11-0}; // imm12
1430 def rs : AI2ldst<0b011, 1, isByte, (outs GPR:$Rt), (ins ldst_so_reg:$shift),
1431 AddrModeNone, LdFrm, iir, opc, "\t$Rt, $shift",
1432 [(set GPR:$Rt, (opnode ldst_so_reg:$shift))]> {
1435 let shift{4} = 0; // Inst{4} = 0
1436 let Inst{23} = shift{12}; // U (add = ('U' == 1))
1437 let Inst{19-16} = shift{16-13}; // Rn
1438 let Inst{15-12} = Rt;
1439 let Inst{11-0} = shift{11-0};
1444 let canFoldAsLoad = 1, isReMaterializable = 1 in {
1445 multiclass AI_ldr1nopc<bit isByte, string opc, InstrItinClass iii,
1446 InstrItinClass iir, PatFrag opnode> {
1447 // Note: We use the complex addrmode_imm12 rather than just an input
1448 // GPR and a constrained immediate so that we can use this to match
1449 // frame index references and avoid matching constant pool references.
1450 def i12: AI2ldst<0b010, 1, isByte, (outs GPRnopc:$Rt),
1451 (ins addrmode_imm12:$addr),
1452 AddrMode_i12, LdFrm, iii, opc, "\t$Rt, $addr",
1453 [(set GPRnopc:$Rt, (opnode addrmode_imm12:$addr))]> {
1456 let Inst{23} = addr{12}; // U (add = ('U' == 1))
1457 let Inst{19-16} = addr{16-13}; // Rn
1458 let Inst{15-12} = Rt;
1459 let Inst{11-0} = addr{11-0}; // imm12
1461 def rs : AI2ldst<0b011, 1, isByte, (outs GPRnopc:$Rt),
1462 (ins ldst_so_reg:$shift),
1463 AddrModeNone, LdFrm, iir, opc, "\t$Rt, $shift",
1464 [(set GPRnopc:$Rt, (opnode ldst_so_reg:$shift))]> {
1467 let shift{4} = 0; // Inst{4} = 0
1468 let Inst{23} = shift{12}; // U (add = ('U' == 1))
1469 let Inst{19-16} = shift{16-13}; // Rn
1470 let Inst{15-12} = Rt;
1471 let Inst{11-0} = shift{11-0};
1477 multiclass AI_str1<bit isByte, string opc, InstrItinClass iii,
1478 InstrItinClass iir, PatFrag opnode> {
1479 // Note: We use the complex addrmode_imm12 rather than just an input
1480 // GPR and a constrained immediate so that we can use this to match
1481 // frame index references and avoid matching constant pool references.
1482 def i12 : AI2ldst<0b010, 0, isByte, (outs),
1483 (ins GPR:$Rt, addrmode_imm12:$addr),
1484 AddrMode_i12, StFrm, iii, opc, "\t$Rt, $addr",
1485 [(opnode GPR:$Rt, addrmode_imm12:$addr)]> {
1488 let Inst{23} = addr{12}; // U (add = ('U' == 1))
1489 let Inst{19-16} = addr{16-13}; // Rn
1490 let Inst{15-12} = Rt;
1491 let Inst{11-0} = addr{11-0}; // imm12
1493 def rs : AI2ldst<0b011, 0, isByte, (outs), (ins GPR:$Rt, ldst_so_reg:$shift),
1494 AddrModeNone, StFrm, iir, opc, "\t$Rt, $shift",
1495 [(opnode GPR:$Rt, ldst_so_reg:$shift)]> {
1498 let shift{4} = 0; // Inst{4} = 0
1499 let Inst{23} = shift{12}; // U (add = ('U' == 1))
1500 let Inst{19-16} = shift{16-13}; // Rn
1501 let Inst{15-12} = Rt;
1502 let Inst{11-0} = shift{11-0};
1506 multiclass AI_str1nopc<bit isByte, string opc, InstrItinClass iii,
1507 InstrItinClass iir, PatFrag opnode> {
1508 // Note: We use the complex addrmode_imm12 rather than just an input
1509 // GPR and a constrained immediate so that we can use this to match
1510 // frame index references and avoid matching constant pool references.
1511 def i12 : AI2ldst<0b010, 0, isByte, (outs),
1512 (ins GPRnopc:$Rt, addrmode_imm12:$addr),
1513 AddrMode_i12, StFrm, iii, opc, "\t$Rt, $addr",
1514 [(opnode GPRnopc:$Rt, addrmode_imm12:$addr)]> {
1517 let Inst{23} = addr{12}; // U (add = ('U' == 1))
1518 let Inst{19-16} = addr{16-13}; // Rn
1519 let Inst{15-12} = Rt;
1520 let Inst{11-0} = addr{11-0}; // imm12
1522 def rs : AI2ldst<0b011, 0, isByte, (outs),
1523 (ins GPRnopc:$Rt, ldst_so_reg:$shift),
1524 AddrModeNone, StFrm, iir, opc, "\t$Rt, $shift",
1525 [(opnode GPRnopc:$Rt, ldst_so_reg:$shift)]> {
1528 let shift{4} = 0; // Inst{4} = 0
1529 let Inst{23} = shift{12}; // U (add = ('U' == 1))
1530 let Inst{19-16} = shift{16-13}; // Rn
1531 let Inst{15-12} = Rt;
1532 let Inst{11-0} = shift{11-0};
1537 //===----------------------------------------------------------------------===//
1539 //===----------------------------------------------------------------------===//
1541 //===----------------------------------------------------------------------===//
1542 // Miscellaneous Instructions.
1545 /// CONSTPOOL_ENTRY - This instruction represents a floating constant pool in
1546 /// the function. The first operand is the ID# for this instruction, the second
1547 /// is the index into the MachineConstantPool that this is, the third is the
1548 /// size in bytes of this constant pool entry.
1549 let neverHasSideEffects = 1, isNotDuplicable = 1 in
1550 def CONSTPOOL_ENTRY :
1551 PseudoInst<(outs), (ins cpinst_operand:$instid, cpinst_operand:$cpidx,
1552 i32imm:$size), NoItinerary, []>;
1554 // FIXME: Marking these as hasSideEffects is necessary to prevent machine DCE
1555 // from removing one half of the matched pairs. That breaks PEI, which assumes
1556 // these will always be in pairs, and asserts if it finds otherwise. Better way?
1557 let Defs = [SP], Uses = [SP], hasSideEffects = 1 in {
1558 def ADJCALLSTACKUP :
1559 PseudoInst<(outs), (ins i32imm:$amt1, i32imm:$amt2, pred:$p), NoItinerary,
1560 [(ARMcallseq_end timm:$amt1, timm:$amt2)]>;
1562 def ADJCALLSTACKDOWN :
1563 PseudoInst<(outs), (ins i32imm:$amt, pred:$p), NoItinerary,
1564 [(ARMcallseq_start timm:$amt)]>;
1567 // Atomic pseudo-insts which will be lowered to ldrexd/strexd loops.
1568 // (These pseudos use a hand-written selection code).
1569 let usesCustomInserter = 1, Defs = [CPSR], mayLoad = 1, mayStore = 1 in {
1570 def ATOMOR6432 : PseudoInst<(outs GPR:$dst1, GPR:$dst2),
1571 (ins GPR:$addr, GPR:$src1, GPR:$src2),
1573 def ATOMXOR6432 : PseudoInst<(outs GPR:$dst1, GPR:$dst2),
1574 (ins GPR:$addr, GPR:$src1, GPR:$src2),
1576 def ATOMADD6432 : PseudoInst<(outs GPR:$dst1, GPR:$dst2),
1577 (ins GPR:$addr, GPR:$src1, GPR:$src2),
1579 def ATOMSUB6432 : PseudoInst<(outs GPR:$dst1, GPR:$dst2),
1580 (ins GPR:$addr, GPR:$src1, GPR:$src2),
1582 def ATOMNAND6432 : PseudoInst<(outs GPR:$dst1, GPR:$dst2),
1583 (ins GPR:$addr, GPR:$src1, GPR:$src2),
1585 def ATOMAND6432 : PseudoInst<(outs GPR:$dst1, GPR:$dst2),
1586 (ins GPR:$addr, GPR:$src1, GPR:$src2),
1588 def ATOMSWAP6432 : PseudoInst<(outs GPR:$dst1, GPR:$dst2),
1589 (ins GPR:$addr, GPR:$src1, GPR:$src2),
1591 def ATOMCMPXCHG6432 : PseudoInst<(outs GPR:$dst1, GPR:$dst2),
1592 (ins GPR:$addr, GPR:$cmp1, GPR:$cmp2,
1593 GPR:$set1, GPR:$set2),
1597 def HINT : AI<(outs), (ins imm0_255:$imm), MiscFrm, NoItinerary,
1598 "hint", "\t$imm", []>, Requires<[IsARM, HasV6]> {
1600 let Inst{27-8} = 0b00110010000011110000;
1601 let Inst{7-0} = imm;
1604 def : InstAlias<"nop$p", (HINT 0, pred:$p)>, Requires<[IsARM, HasV6T2]>;
1605 def : InstAlias<"yield$p", (HINT 1, pred:$p)>, Requires<[IsARM, HasV6T2]>;
1606 def : InstAlias<"wfe$p", (HINT 2, pred:$p)>, Requires<[IsARM, HasV6T2]>;
1607 def : InstAlias<"wfi$p", (HINT 3, pred:$p)>, Requires<[IsARM, HasV6T2]>;
1608 def : InstAlias<"sev$p", (HINT 4, pred:$p)>, Requires<[IsARM, HasV6T2]>;
1610 def SEL : AI<(outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm), DPFrm, NoItinerary, "sel",
1611 "\t$Rd, $Rn, $Rm", []>, Requires<[IsARM, HasV6]> {
1616 let Inst{15-12} = Rd;
1617 let Inst{19-16} = Rn;
1618 let Inst{27-20} = 0b01101000;
1619 let Inst{7-4} = 0b1011;
1620 let Inst{11-8} = 0b1111;
1621 let Unpredictable{11-8} = 0b1111;
1624 // The 16-bit operand $val can be used by a debugger to store more information
1625 // about the breakpoint.
1626 def BKPT : AI<(outs), (ins imm0_65535:$val), MiscFrm, NoItinerary,
1627 "bkpt", "\t$val", []>, Requires<[IsARM]> {
1629 let Inst{3-0} = val{3-0};
1630 let Inst{19-8} = val{15-4};
1631 let Inst{27-20} = 0b00010010;
1632 let Inst{7-4} = 0b0111;
1635 // Change Processor State
1636 // FIXME: We should use InstAlias to handle the optional operands.
1637 class CPS<dag iops, string asm_ops>
1638 : AXI<(outs), iops, MiscFrm, NoItinerary, !strconcat("cps", asm_ops),
1639 []>, Requires<[IsARM]> {
1645 let Inst{31-28} = 0b1111;
1646 let Inst{27-20} = 0b00010000;
1647 let Inst{19-18} = imod;
1648 let Inst{17} = M; // Enabled if mode is set;
1649 let Inst{16-9} = 0b00000000;
1650 let Inst{8-6} = iflags;
1652 let Inst{4-0} = mode;
1655 let DecoderMethod = "DecodeCPSInstruction" in {
1657 def CPS3p : CPS<(ins imod_op:$imod, iflags_op:$iflags, imm0_31:$mode),
1658 "$imod\t$iflags, $mode">;
1659 let mode = 0, M = 0 in
1660 def CPS2p : CPS<(ins imod_op:$imod, iflags_op:$iflags), "$imod\t$iflags">;
1662 let imod = 0, iflags = 0, M = 1 in
1663 def CPS1p : CPS<(ins imm0_31:$mode), "\t$mode">;
1666 // Preload signals the memory system of possible future data/instruction access.
1667 multiclass APreLoad<bits<1> read, bits<1> data, string opc> {
1669 def i12 : AXI<(outs), (ins addrmode_imm12:$addr), MiscFrm, IIC_Preload,
1670 !strconcat(opc, "\t$addr"),
1671 [(ARMPreload addrmode_imm12:$addr, (i32 read), (i32 data))]> {
1674 let Inst{31-26} = 0b111101;
1675 let Inst{25} = 0; // 0 for immediate form
1676 let Inst{24} = data;
1677 let Inst{23} = addr{12}; // U (add = ('U' == 1))
1678 let Inst{22} = read;
1679 let Inst{21-20} = 0b01;
1680 let Inst{19-16} = addr{16-13}; // Rn
1681 let Inst{15-12} = 0b1111;
1682 let Inst{11-0} = addr{11-0}; // imm12
1685 def rs : AXI<(outs), (ins ldst_so_reg:$shift), MiscFrm, IIC_Preload,
1686 !strconcat(opc, "\t$shift"),
1687 [(ARMPreload ldst_so_reg:$shift, (i32 read), (i32 data))]> {
1689 let Inst{31-26} = 0b111101;
1690 let Inst{25} = 1; // 1 for register form
1691 let Inst{24} = data;
1692 let Inst{23} = shift{12}; // U (add = ('U' == 1))
1693 let Inst{22} = read;
1694 let Inst{21-20} = 0b01;
1695 let Inst{19-16} = shift{16-13}; // Rn
1696 let Inst{15-12} = 0b1111;
1697 let Inst{11-0} = shift{11-0};
1702 defm PLD : APreLoad<1, 1, "pld">, Requires<[IsARM]>;
1703 defm PLDW : APreLoad<0, 1, "pldw">, Requires<[IsARM,HasV7,HasMP]>;
1704 defm PLI : APreLoad<1, 0, "pli">, Requires<[IsARM,HasV7]>;
1706 def SETEND : AXI<(outs), (ins setend_op:$end), MiscFrm, NoItinerary,
1707 "setend\t$end", []>, Requires<[IsARM]> {
1709 let Inst{31-10} = 0b1111000100000001000000;
1714 def DBG : AI<(outs), (ins imm0_15:$opt), MiscFrm, NoItinerary, "dbg", "\t$opt",
1715 []>, Requires<[IsARM, HasV7]> {
1717 let Inst{27-4} = 0b001100100000111100001111;
1718 let Inst{3-0} = opt;
1721 // A5.4 Permanently UNDEFINED instructions.
1722 let isBarrier = 1, isTerminator = 1 in
1723 def TRAP : AXI<(outs), (ins), MiscFrm, NoItinerary,
1726 let Inst = 0xe7ffdefe;
1729 // Address computation and loads and stores in PIC mode.
1730 let isNotDuplicable = 1 in {
1731 def PICADD : ARMPseudoInst<(outs GPR:$dst), (ins GPR:$a, pclabel:$cp, pred:$p),
1733 [(set GPR:$dst, (ARMpic_add GPR:$a, imm:$cp))]>;
1735 let AddedComplexity = 10 in {
1736 def PICLDR : ARMPseudoInst<(outs GPR:$dst), (ins addrmodepc:$addr, pred:$p),
1738 [(set GPR:$dst, (load addrmodepc:$addr))]>;
1740 def PICLDRH : ARMPseudoInst<(outs GPR:$Rt), (ins addrmodepc:$addr, pred:$p),
1742 [(set GPR:$Rt, (zextloadi16 addrmodepc:$addr))]>;
1744 def PICLDRB : ARMPseudoInst<(outs GPR:$Rt), (ins addrmodepc:$addr, pred:$p),
1746 [(set GPR:$Rt, (zextloadi8 addrmodepc:$addr))]>;
1748 def PICLDRSH : ARMPseudoInst<(outs GPR:$Rt), (ins addrmodepc:$addr, pred:$p),
1750 [(set GPR:$Rt, (sextloadi16 addrmodepc:$addr))]>;
1752 def PICLDRSB : ARMPseudoInst<(outs GPR:$Rt), (ins addrmodepc:$addr, pred:$p),
1754 [(set GPR:$Rt, (sextloadi8 addrmodepc:$addr))]>;
1756 let AddedComplexity = 10 in {
1757 def PICSTR : ARMPseudoInst<(outs), (ins GPR:$src, addrmodepc:$addr, pred:$p),
1758 4, IIC_iStore_r, [(store GPR:$src, addrmodepc:$addr)]>;
1760 def PICSTRH : ARMPseudoInst<(outs), (ins GPR:$src, addrmodepc:$addr, pred:$p),
1761 4, IIC_iStore_bh_r, [(truncstorei16 GPR:$src,
1762 addrmodepc:$addr)]>;
1764 def PICSTRB : ARMPseudoInst<(outs), (ins GPR:$src, addrmodepc:$addr, pred:$p),
1765 4, IIC_iStore_bh_r, [(truncstorei8 GPR:$src, addrmodepc:$addr)]>;
1767 } // isNotDuplicable = 1
1770 // LEApcrel - Load a pc-relative address into a register without offending the
1772 let neverHasSideEffects = 1, isReMaterializable = 1 in
1773 // The 'adr' mnemonic encodes differently if the label is before or after
1774 // the instruction. The {24-21} opcode bits are set by the fixup, as we don't
1775 // know until then which form of the instruction will be used.
1776 def ADR : AI1<{0,?,?,0}, (outs GPR:$Rd), (ins adrlabel:$label),
1777 MiscFrm, IIC_iALUi, "adr", "\t$Rd, $label", []> {
1780 let Inst{27-25} = 0b001;
1782 let Inst{23-22} = label{13-12};
1785 let Inst{19-16} = 0b1111;
1786 let Inst{15-12} = Rd;
1787 let Inst{11-0} = label{11-0};
1789 def LEApcrel : ARMPseudoInst<(outs GPR:$Rd), (ins i32imm:$label, pred:$p),
1792 def LEApcrelJT : ARMPseudoInst<(outs GPR:$Rd),
1793 (ins i32imm:$label, nohash_imm:$id, pred:$p),
1796 //===----------------------------------------------------------------------===//
1797 // Control Flow Instructions.
1800 let isReturn = 1, isTerminator = 1, isBarrier = 1 in {
1802 def BX_RET : AI<(outs), (ins), BrMiscFrm, IIC_Br,
1803 "bx", "\tlr", [(ARMretflag)]>,
1804 Requires<[IsARM, HasV4T]> {
1805 let Inst{27-0} = 0b0001001011111111111100011110;
1809 def MOVPCLR : AI<(outs), (ins), BrMiscFrm, IIC_Br,
1810 "mov", "\tpc, lr", [(ARMretflag)]>,
1811 Requires<[IsARM, NoV4T]> {
1812 let Inst{27-0} = 0b0001101000001111000000001110;
1816 // Indirect branches
1817 let isBranch = 1, isTerminator = 1, isBarrier = 1, isIndirectBranch = 1 in {
1819 def BX : AXI<(outs), (ins GPR:$dst), BrMiscFrm, IIC_Br, "bx\t$dst",
1820 [(brind GPR:$dst)]>,
1821 Requires<[IsARM, HasV4T]> {
1823 let Inst{31-4} = 0b1110000100101111111111110001;
1824 let Inst{3-0} = dst;
1827 def BX_pred : AI<(outs), (ins GPR:$dst), BrMiscFrm, IIC_Br,
1828 "bx", "\t$dst", [/* pattern left blank */]>,
1829 Requires<[IsARM, HasV4T]> {
1831 let Inst{27-4} = 0b000100101111111111110001;
1832 let Inst{3-0} = dst;
1836 // SP is marked as a use to prevent stack-pointer assignments that appear
1837 // immediately before calls from potentially appearing dead.
1839 // FIXME: Do we really need a non-predicated version? If so, it should
1840 // at least be a pseudo instruction expanding to the predicated version
1841 // at MC lowering time.
1842 Defs = [LR], Uses = [SP] in {
1843 def BL : ABXI<0b1011, (outs), (ins bl_target:$func, variable_ops),
1844 IIC_Br, "bl\t$func",
1845 [(ARMcall tglobaladdr:$func)]>,
1847 let Inst{31-28} = 0b1110;
1849 let Inst{23-0} = func;
1850 let DecoderMethod = "DecodeBranchImmInstruction";
1853 def BL_pred : ABI<0b1011, (outs), (ins bl_target:$func, variable_ops),
1854 IIC_Br, "bl", "\t$func",
1855 [(ARMcall_pred tglobaladdr:$func)]>,
1858 let Inst{23-0} = func;
1859 let DecoderMethod = "DecodeBranchImmInstruction";
1863 def BLX : AXI<(outs), (ins GPR:$func, variable_ops), BrMiscFrm,
1864 IIC_Br, "blx\t$func",
1865 [(ARMcall GPR:$func)]>,
1866 Requires<[IsARM, HasV5T]> {
1868 let Inst{31-4} = 0b1110000100101111111111110011;
1869 let Inst{3-0} = func;
1872 def BLX_pred : AI<(outs), (ins GPR:$func, variable_ops), BrMiscFrm,
1873 IIC_Br, "blx", "\t$func",
1874 [(ARMcall_pred GPR:$func)]>,
1875 Requires<[IsARM, HasV5T]> {
1877 let Inst{27-4} = 0b000100101111111111110011;
1878 let Inst{3-0} = func;
1882 // Note: Restrict $func to the tGPR regclass to prevent it being in LR.
1883 def BX_CALL : ARMPseudoInst<(outs), (ins tGPR:$func, variable_ops),
1884 8, IIC_Br, [(ARMcall_nolink tGPR:$func)]>,
1885 Requires<[IsARM, HasV4T]>;
1888 def BMOVPCRX_CALL : ARMPseudoInst<(outs), (ins tGPR:$func, variable_ops),
1889 8, IIC_Br, [(ARMcall_nolink tGPR:$func)]>,
1890 Requires<[IsARM, NoV4T]>;
1892 // mov lr, pc; b if callee is marked noreturn to avoid confusing the
1893 // return stack predictor.
1894 def BMOVPCB_CALL : ARMPseudoInst<(outs),
1895 (ins bl_target:$func, variable_ops),
1896 8, IIC_Br, [(ARMcall_nolink tglobaladdr:$func)]>,
1900 let isBranch = 1, isTerminator = 1 in {
1901 // FIXME: should be able to write a pattern for ARMBrcond, but can't use
1902 // a two-value operand where a dag node expects two operands. :(
1903 def Bcc : ABI<0b1010, (outs), (ins br_target:$target),
1904 IIC_Br, "b", "\t$target",
1905 [/*(ARMbrcond bb:$target, imm:$cc, CCR:$ccr)*/]> {
1907 let Inst{23-0} = target;
1908 let DecoderMethod = "DecodeBranchImmInstruction";
1911 let isBarrier = 1 in {
1912 // B is "predicable" since it's just a Bcc with an 'always' condition.
1913 let isPredicable = 1 in
1914 // FIXME: We shouldn't need this pseudo at all. Just using Bcc directly
1915 // should be sufficient.
1916 // FIXME: Is B really a Barrier? That doesn't seem right.
1917 def B : ARMPseudoExpand<(outs), (ins br_target:$target), 4, IIC_Br,
1918 [(br bb:$target)], (Bcc br_target:$target, (ops 14, zero_reg))>;
1920 let isNotDuplicable = 1, isIndirectBranch = 1 in {
1921 def BR_JTr : ARMPseudoInst<(outs),
1922 (ins GPR:$target, i32imm:$jt, i32imm:$id),
1924 [(ARMbrjt GPR:$target, tjumptable:$jt, imm:$id)]>;
1925 // FIXME: This shouldn't use the generic "addrmode2," but rather be split
1926 // into i12 and rs suffixed versions.
1927 def BR_JTm : ARMPseudoInst<(outs),
1928 (ins addrmode2:$target, i32imm:$jt, i32imm:$id),
1930 [(ARMbrjt (i32 (load addrmode2:$target)), tjumptable:$jt,
1932 def BR_JTadd : ARMPseudoInst<(outs),
1933 (ins GPR:$target, GPR:$idx, i32imm:$jt, i32imm:$id),
1935 [(ARMbrjt (add GPR:$target, GPR:$idx), tjumptable:$jt,
1937 } // isNotDuplicable = 1, isIndirectBranch = 1
1943 def BLXi : AXI<(outs), (ins blx_target:$target), BrMiscFrm, NoItinerary,
1944 "blx\t$target", []>,
1945 Requires<[IsARM, HasV5T]> {
1946 let Inst{31-25} = 0b1111101;
1948 let Inst{23-0} = target{24-1};
1949 let Inst{24} = target{0};
1952 // Branch and Exchange Jazelle
1953 def BXJ : ABI<0b0001, (outs), (ins GPR:$func), NoItinerary, "bxj", "\t$func",
1954 [/* pattern left blank */]> {
1956 let Inst{23-20} = 0b0010;
1957 let Inst{19-8} = 0xfff;
1958 let Inst{7-4} = 0b0010;
1959 let Inst{3-0} = func;
1964 let isCall = 1, isTerminator = 1, isReturn = 1, isBarrier = 1, Uses = [SP] in {
1965 def TCRETURNdi : PseudoInst<(outs), (ins i32imm:$dst, variable_ops),
1968 def TCRETURNri : PseudoInst<(outs), (ins tcGPR:$dst, variable_ops),
1971 def TAILJMPd : ARMPseudoExpand<(outs), (ins br_target:$dst, variable_ops),
1973 (Bcc br_target:$dst, (ops 14, zero_reg))>,
1976 def TAILJMPr : ARMPseudoExpand<(outs), (ins tcGPR:$dst, variable_ops),
1982 // Secure Monitor Call is a system instruction.
1983 def SMC : ABI<0b0001, (outs), (ins imm0_15:$opt), NoItinerary, "smc", "\t$opt",
1986 let Inst{23-4} = 0b01100000000000000111;
1987 let Inst{3-0} = opt;
1990 // Supervisor Call (Software Interrupt)
1991 let isCall = 1, Uses = [SP] in {
1992 def SVC : ABI<0b1111, (outs), (ins imm24b:$svc), IIC_Br, "svc", "\t$svc", []> {
1994 let Inst{23-0} = svc;
1998 // Store Return State
1999 class SRSI<bit wb, string asm>
2000 : XI<(outs), (ins imm0_31:$mode), AddrModeNone, 4, IndexModeNone, BrFrm,
2001 NoItinerary, asm, "", []> {
2003 let Inst{31-28} = 0b1111;
2004 let Inst{27-25} = 0b100;
2008 let Inst{19-16} = 0b1101; // SP
2009 let Inst{15-5} = 0b00000101000;
2010 let Inst{4-0} = mode;
2013 def SRSDA : SRSI<0, "srsda\tsp, $mode"> {
2014 let Inst{24-23} = 0;
2016 def SRSDA_UPD : SRSI<1, "srsda\tsp!, $mode"> {
2017 let Inst{24-23} = 0;
2019 def SRSDB : SRSI<0, "srsdb\tsp, $mode"> {
2020 let Inst{24-23} = 0b10;
2022 def SRSDB_UPD : SRSI<1, "srsdb\tsp!, $mode"> {
2023 let Inst{24-23} = 0b10;
2025 def SRSIA : SRSI<0, "srsia\tsp, $mode"> {
2026 let Inst{24-23} = 0b01;
2028 def SRSIA_UPD : SRSI<1, "srsia\tsp!, $mode"> {
2029 let Inst{24-23} = 0b01;
2031 def SRSIB : SRSI<0, "srsib\tsp, $mode"> {
2032 let Inst{24-23} = 0b11;
2034 def SRSIB_UPD : SRSI<1, "srsib\tsp!, $mode"> {
2035 let Inst{24-23} = 0b11;
2038 // Return From Exception
2039 class RFEI<bit wb, string asm>
2040 : XI<(outs), (ins GPR:$Rn), AddrModeNone, 4, IndexModeNone, BrFrm,
2041 NoItinerary, asm, "", []> {
2043 let Inst{31-28} = 0b1111;
2044 let Inst{27-25} = 0b100;
2048 let Inst{19-16} = Rn;
2049 let Inst{15-0} = 0xa00;
2052 def RFEDA : RFEI<0, "rfeda\t$Rn"> {
2053 let Inst{24-23} = 0;
2055 def RFEDA_UPD : RFEI<1, "rfeda\t$Rn!"> {
2056 let Inst{24-23} = 0;
2058 def RFEDB : RFEI<0, "rfedb\t$Rn"> {
2059 let Inst{24-23} = 0b10;
2061 def RFEDB_UPD : RFEI<1, "rfedb\t$Rn!"> {
2062 let Inst{24-23} = 0b10;
2064 def RFEIA : RFEI<0, "rfeia\t$Rn"> {
2065 let Inst{24-23} = 0b01;
2067 def RFEIA_UPD : RFEI<1, "rfeia\t$Rn!"> {
2068 let Inst{24-23} = 0b01;
2070 def RFEIB : RFEI<0, "rfeib\t$Rn"> {
2071 let Inst{24-23} = 0b11;
2073 def RFEIB_UPD : RFEI<1, "rfeib\t$Rn!"> {
2074 let Inst{24-23} = 0b11;
2077 //===----------------------------------------------------------------------===//
2078 // Load / Store Instructions.
2084 defm LDR : AI_ldr1<0, "ldr", IIC_iLoad_r, IIC_iLoad_si,
2085 UnOpFrag<(load node:$Src)>>;
2086 defm LDRB : AI_ldr1nopc<1, "ldrb", IIC_iLoad_bh_r, IIC_iLoad_bh_si,
2087 UnOpFrag<(zextloadi8 node:$Src)>>;
2088 defm STR : AI_str1<0, "str", IIC_iStore_r, IIC_iStore_si,
2089 BinOpFrag<(store node:$LHS, node:$RHS)>>;
2090 defm STRB : AI_str1nopc<1, "strb", IIC_iStore_bh_r, IIC_iStore_bh_si,
2091 BinOpFrag<(truncstorei8 node:$LHS, node:$RHS)>>;
2093 // Special LDR for loads from non-pc-relative constpools.
2094 let canFoldAsLoad = 1, mayLoad = 1, neverHasSideEffects = 1,
2095 isReMaterializable = 1, isCodeGenOnly = 1 in
2096 def LDRcp : AI2ldst<0b010, 1, 0, (outs GPR:$Rt), (ins addrmode_imm12:$addr),
2097 AddrMode_i12, LdFrm, IIC_iLoad_r, "ldr", "\t$Rt, $addr",
2101 let Inst{23} = addr{12}; // U (add = ('U' == 1))
2102 let Inst{19-16} = 0b1111;
2103 let Inst{15-12} = Rt;
2104 let Inst{11-0} = addr{11-0}; // imm12
2107 // Loads with zero extension
2108 def LDRH : AI3ld<0b1011, 1, (outs GPR:$Rt), (ins addrmode3:$addr), LdMiscFrm,
2109 IIC_iLoad_bh_r, "ldrh", "\t$Rt, $addr",
2110 [(set GPR:$Rt, (zextloadi16 addrmode3:$addr))]>;
2112 // Loads with sign extension
2113 def LDRSH : AI3ld<0b1111, 1, (outs GPR:$Rt), (ins addrmode3:$addr), LdMiscFrm,
2114 IIC_iLoad_bh_r, "ldrsh", "\t$Rt, $addr",
2115 [(set GPR:$Rt, (sextloadi16 addrmode3:$addr))]>;
2117 def LDRSB : AI3ld<0b1101, 1, (outs GPR:$Rt), (ins addrmode3:$addr), LdMiscFrm,
2118 IIC_iLoad_bh_r, "ldrsb", "\t$Rt, $addr",
2119 [(set GPR:$Rt, (sextloadi8 addrmode3:$addr))]>;
2121 let mayLoad = 1, neverHasSideEffects = 1, hasExtraDefRegAllocReq = 1 in {
2123 def LDRD : AI3ld<0b1101, 0, (outs GPR:$Rd, GPR:$dst2),
2124 (ins addrmode3:$addr), LdMiscFrm,
2125 IIC_iLoad_d_r, "ldrd", "\t$Rd, $dst2, $addr",
2126 []>, Requires<[IsARM, HasV5TE]>;
2130 multiclass AI2_ldridx<bit isByte, string opc,
2131 InstrItinClass iii, InstrItinClass iir> {
2132 def _PRE_IMM : AI2ldstidx<1, isByte, 1, (outs GPR:$Rt, GPR:$Rn_wb),
2133 (ins addrmode_imm12:$addr), IndexModePre, LdFrm, iii,
2134 opc, "\t$Rt, $addr!", "$addr.base = $Rn_wb", []> {
2137 let Inst{23} = addr{12};
2138 let Inst{19-16} = addr{16-13};
2139 let Inst{11-0} = addr{11-0};
2140 let DecoderMethod = "DecodeLDRPreImm";
2141 let AsmMatchConverter = "cvtLdWriteBackRegAddrModeImm12";
2144 def _PRE_REG : AI2ldstidx<1, isByte, 1, (outs GPR:$Rt, GPR:$Rn_wb),
2145 (ins ldst_so_reg:$addr), IndexModePre, LdFrm, iir,
2146 opc, "\t$Rt, $addr!", "$addr.base = $Rn_wb", []> {
2149 let Inst{23} = addr{12};
2150 let Inst{19-16} = addr{16-13};
2151 let Inst{11-0} = addr{11-0};
2153 let DecoderMethod = "DecodeLDRPreReg";
2154 let AsmMatchConverter = "cvtLdWriteBackRegAddrMode2";
2157 def _POST_REG : AI2ldstidx<1, isByte, 0, (outs GPR:$Rt, GPR:$Rn_wb),
2158 (ins addr_offset_none:$addr, am2offset_reg:$offset),
2159 IndexModePost, LdFrm, iir,
2160 opc, "\t$Rt, $addr, $offset",
2161 "$addr.base = $Rn_wb", []> {
2167 let Inst{23} = offset{12};
2168 let Inst{19-16} = addr;
2169 let Inst{11-0} = offset{11-0};
2171 let DecoderMethod = "DecodeAddrMode2IdxInstruction";
2174 def _POST_IMM : AI2ldstidx<1, isByte, 0, (outs GPR:$Rt, GPR:$Rn_wb),
2175 (ins addr_offset_none:$addr, am2offset_imm:$offset),
2176 IndexModePost, LdFrm, iii,
2177 opc, "\t$Rt, $addr, $offset",
2178 "$addr.base = $Rn_wb", []> {
2184 let Inst{23} = offset{12};
2185 let Inst{19-16} = addr;
2186 let Inst{11-0} = offset{11-0};
2188 let DecoderMethod = "DecodeAddrMode2IdxInstruction";
2193 let mayLoad = 1, neverHasSideEffects = 1 in {
2194 // FIXME: for LDR_PRE_REG etc. the itineray should be either IIC_iLoad_ru or
2195 // IIC_iLoad_siu depending on whether it the offset register is shifted.
2196 defm LDR : AI2_ldridx<0, "ldr", IIC_iLoad_iu, IIC_iLoad_ru>;
2197 defm LDRB : AI2_ldridx<1, "ldrb", IIC_iLoad_bh_iu, IIC_iLoad_bh_ru>;
2200 multiclass AI3_ldridx<bits<4> op, string opc, InstrItinClass itin> {
2201 def _PRE : AI3ldstidx<op, 1, 1, (outs GPR:$Rt, GPR:$Rn_wb),
2202 (ins addrmode3:$addr), IndexModePre,
2204 opc, "\t$Rt, $addr!", "$addr.base = $Rn_wb", []> {
2206 let Inst{23} = addr{8}; // U bit
2207 let Inst{22} = addr{13}; // 1 == imm8, 0 == Rm
2208 let Inst{19-16} = addr{12-9}; // Rn
2209 let Inst{11-8} = addr{7-4}; // imm7_4/zero
2210 let Inst{3-0} = addr{3-0}; // imm3_0/Rm
2211 let AsmMatchConverter = "cvtLdWriteBackRegAddrMode3";
2212 let DecoderMethod = "DecodeAddrMode3Instruction";
2214 def _POST : AI3ldstidx<op, 1, 0, (outs GPR:$Rt, GPR:$Rn_wb),
2215 (ins addr_offset_none:$addr, am3offset:$offset),
2216 IndexModePost, LdMiscFrm, itin,
2217 opc, "\t$Rt, $addr, $offset", "$addr.base = $Rn_wb",
2221 let Inst{23} = offset{8}; // U bit
2222 let Inst{22} = offset{9}; // 1 == imm8, 0 == Rm
2223 let Inst{19-16} = addr;
2224 let Inst{11-8} = offset{7-4}; // imm7_4/zero
2225 let Inst{3-0} = offset{3-0}; // imm3_0/Rm
2226 let DecoderMethod = "DecodeAddrMode3Instruction";
2230 let mayLoad = 1, neverHasSideEffects = 1 in {
2231 defm LDRH : AI3_ldridx<0b1011, "ldrh", IIC_iLoad_bh_ru>;
2232 defm LDRSH : AI3_ldridx<0b1111, "ldrsh", IIC_iLoad_bh_ru>;
2233 defm LDRSB : AI3_ldridx<0b1101, "ldrsb", IIC_iLoad_bh_ru>;
2234 let hasExtraDefRegAllocReq = 1 in {
2235 def LDRD_PRE : AI3ldstidx<0b1101, 0, 1, (outs GPR:$Rt, GPR:$Rt2, GPR:$Rn_wb),
2236 (ins addrmode3:$addr), IndexModePre,
2237 LdMiscFrm, IIC_iLoad_d_ru,
2238 "ldrd", "\t$Rt, $Rt2, $addr!",
2239 "$addr.base = $Rn_wb", []> {
2241 let Inst{23} = addr{8}; // U bit
2242 let Inst{22} = addr{13}; // 1 == imm8, 0 == Rm
2243 let Inst{19-16} = addr{12-9}; // Rn
2244 let Inst{11-8} = addr{7-4}; // imm7_4/zero
2245 let Inst{3-0} = addr{3-0}; // imm3_0/Rm
2246 let DecoderMethod = "DecodeAddrMode3Instruction";
2247 let AsmMatchConverter = "cvtLdrdPre";
2249 def LDRD_POST: AI3ldstidx<0b1101, 0, 0, (outs GPR:$Rt, GPR:$Rt2, GPR:$Rn_wb),
2250 (ins addr_offset_none:$addr, am3offset:$offset),
2251 IndexModePost, LdMiscFrm, IIC_iLoad_d_ru,
2252 "ldrd", "\t$Rt, $Rt2, $addr, $offset",
2253 "$addr.base = $Rn_wb", []> {
2256 let Inst{23} = offset{8}; // U bit
2257 let Inst{22} = offset{9}; // 1 == imm8, 0 == Rm
2258 let Inst{19-16} = addr;
2259 let Inst{11-8} = offset{7-4}; // imm7_4/zero
2260 let Inst{3-0} = offset{3-0}; // imm3_0/Rm
2261 let DecoderMethod = "DecodeAddrMode3Instruction";
2263 } // hasExtraDefRegAllocReq = 1
2264 } // mayLoad = 1, neverHasSideEffects = 1
2266 // LDRT, LDRBT, LDRSBT, LDRHT, LDRSHT.
2267 let mayLoad = 1, neverHasSideEffects = 1 in {
2268 def LDRT_POST_REG : AI2ldstidx<1, 0, 0, (outs GPR:$Rt, GPR:$Rn_wb),
2269 (ins addr_offset_none:$addr, am2offset_reg:$offset),
2270 IndexModePost, LdFrm, IIC_iLoad_ru,
2271 "ldrt", "\t$Rt, $addr, $offset",
2272 "$addr.base = $Rn_wb", []> {
2278 let Inst{23} = offset{12};
2279 let Inst{21} = 1; // overwrite
2280 let Inst{19-16} = addr;
2281 let Inst{11-5} = offset{11-5};
2283 let Inst{3-0} = offset{3-0};
2284 let DecoderMethod = "DecodeAddrMode2IdxInstruction";
2287 def LDRT_POST_IMM : AI2ldstidx<1, 0, 0, (outs GPR:$Rt, GPR:$Rn_wb),
2288 (ins addr_offset_none:$addr, am2offset_imm:$offset),
2289 IndexModePost, LdFrm, IIC_iLoad_ru,
2290 "ldrt", "\t$Rt, $addr, $offset",
2291 "$addr.base = $Rn_wb", []> {
2297 let Inst{23} = offset{12};
2298 let Inst{21} = 1; // overwrite
2299 let Inst{19-16} = addr;
2300 let Inst{11-0} = offset{11-0};
2301 let DecoderMethod = "DecodeAddrMode2IdxInstruction";
2304 def LDRBT_POST_REG : AI2ldstidx<1, 1, 0, (outs GPR:$Rt, GPR:$Rn_wb),
2305 (ins addr_offset_none:$addr, am2offset_reg:$offset),
2306 IndexModePost, LdFrm, IIC_iLoad_bh_ru,
2307 "ldrbt", "\t$Rt, $addr, $offset",
2308 "$addr.base = $Rn_wb", []> {
2314 let Inst{23} = offset{12};
2315 let Inst{21} = 1; // overwrite
2316 let Inst{19-16} = addr;
2317 let Inst{11-5} = offset{11-5};
2319 let Inst{3-0} = offset{3-0};
2320 let DecoderMethod = "DecodeAddrMode2IdxInstruction";
2323 def LDRBT_POST_IMM : AI2ldstidx<1, 1, 0, (outs GPR:$Rt, GPR:$Rn_wb),
2324 (ins addr_offset_none:$addr, am2offset_imm:$offset),
2325 IndexModePost, LdFrm, IIC_iLoad_bh_ru,
2326 "ldrbt", "\t$Rt, $addr, $offset",
2327 "$addr.base = $Rn_wb", []> {
2333 let Inst{23} = offset{12};
2334 let Inst{21} = 1; // overwrite
2335 let Inst{19-16} = addr;
2336 let Inst{11-0} = offset{11-0};
2337 let DecoderMethod = "DecodeAddrMode2IdxInstruction";
2340 multiclass AI3ldrT<bits<4> op, string opc> {
2341 def i : AI3ldstidxT<op, 1, (outs GPR:$Rt, GPR:$base_wb),
2342 (ins addr_offset_none:$addr, postidx_imm8:$offset),
2343 IndexModePost, LdMiscFrm, IIC_iLoad_bh_ru, opc,
2344 "\t$Rt, $addr, $offset", "$addr.base = $base_wb", []> {
2346 let Inst{23} = offset{8};
2348 let Inst{11-8} = offset{7-4};
2349 let Inst{3-0} = offset{3-0};
2350 let AsmMatchConverter = "cvtLdExtTWriteBackImm";
2352 def r : AI3ldstidxT<op, 1, (outs GPRnopc:$Rt, GPRnopc:$base_wb),
2353 (ins addr_offset_none:$addr, postidx_reg:$Rm),
2354 IndexModePost, LdMiscFrm, IIC_iLoad_bh_ru, opc,
2355 "\t$Rt, $addr, $Rm", "$addr.base = $base_wb", []> {
2357 let Inst{23} = Rm{4};
2360 let Unpredictable{11-8} = 0b1111;
2361 let Inst{3-0} = Rm{3-0};
2362 let AsmMatchConverter = "cvtLdExtTWriteBackReg";
2363 let DecoderMethod = "DecodeLDR";
2367 defm LDRSBT : AI3ldrT<0b1101, "ldrsbt">;
2368 defm LDRHT : AI3ldrT<0b1011, "ldrht">;
2369 defm LDRSHT : AI3ldrT<0b1111, "ldrsht">;
2374 // Stores with truncate
2375 def STRH : AI3str<0b1011, (outs), (ins GPR:$Rt, addrmode3:$addr), StMiscFrm,
2376 IIC_iStore_bh_r, "strh", "\t$Rt, $addr",
2377 [(truncstorei16 GPR:$Rt, addrmode3:$addr)]>;
2380 let mayStore = 1, neverHasSideEffects = 1, hasExtraSrcRegAllocReq = 1 in
2381 def STRD : AI3str<0b1111, (outs), (ins GPR:$Rt, GPR:$src2, addrmode3:$addr),
2382 StMiscFrm, IIC_iStore_d_r,
2383 "strd", "\t$Rt, $src2, $addr", []>,
2384 Requires<[IsARM, HasV5TE]> {
2389 multiclass AI2_stridx<bit isByte, string opc,
2390 InstrItinClass iii, InstrItinClass iir> {
2391 def _PRE_IMM : AI2ldstidx<0, isByte, 1, (outs GPR:$Rn_wb),
2392 (ins GPR:$Rt, addrmode_imm12:$addr), IndexModePre,
2394 opc, "\t$Rt, $addr!", "$addr.base = $Rn_wb", []> {
2397 let Inst{23} = addr{12}; // U (add = ('U' == 1))
2398 let Inst{19-16} = addr{16-13}; // Rn
2399 let Inst{11-0} = addr{11-0}; // imm12
2400 let AsmMatchConverter = "cvtStWriteBackRegAddrModeImm12";
2401 let DecoderMethod = "DecodeSTRPreImm";
2404 def _PRE_REG : AI2ldstidx<0, isByte, 1, (outs GPR:$Rn_wb),
2405 (ins GPR:$Rt, ldst_so_reg:$addr),
2406 IndexModePre, StFrm, iir,
2407 opc, "\t$Rt, $addr!", "$addr.base = $Rn_wb", []> {
2410 let Inst{23} = addr{12}; // U (add = ('U' == 1))
2411 let Inst{19-16} = addr{16-13}; // Rn
2412 let Inst{11-0} = addr{11-0};
2413 let Inst{4} = 0; // Inst{4} = 0
2414 let AsmMatchConverter = "cvtStWriteBackRegAddrMode2";
2415 let DecoderMethod = "DecodeSTRPreReg";
2417 def _POST_REG : AI2ldstidx<0, isByte, 0, (outs GPR:$Rn_wb),
2418 (ins GPR:$Rt, addr_offset_none:$addr, am2offset_reg:$offset),
2419 IndexModePost, StFrm, iir,
2420 opc, "\t$Rt, $addr, $offset",
2421 "$addr.base = $Rn_wb", []> {
2427 let Inst{23} = offset{12};
2428 let Inst{19-16} = addr;
2429 let Inst{11-0} = offset{11-0};
2432 let DecoderMethod = "DecodeAddrMode2IdxInstruction";
2435 def _POST_IMM : AI2ldstidx<0, isByte, 0, (outs GPR:$Rn_wb),
2436 (ins GPR:$Rt, addr_offset_none:$addr, am2offset_imm:$offset),
2437 IndexModePost, StFrm, iii,
2438 opc, "\t$Rt, $addr, $offset",
2439 "$addr.base = $Rn_wb", []> {
2445 let Inst{23} = offset{12};
2446 let Inst{19-16} = addr;
2447 let Inst{11-0} = offset{11-0};
2449 let DecoderMethod = "DecodeAddrMode2IdxInstruction";
2453 let mayStore = 1, neverHasSideEffects = 1 in {
2454 // FIXME: for STR_PRE_REG etc. the itineray should be either IIC_iStore_ru or
2455 // IIC_iStore_siu depending on whether it the offset register is shifted.
2456 defm STR : AI2_stridx<0, "str", IIC_iStore_iu, IIC_iStore_ru>;
2457 defm STRB : AI2_stridx<1, "strb", IIC_iStore_bh_iu, IIC_iStore_bh_ru>;
2460 def : ARMPat<(post_store GPR:$Rt, addr_offset_none:$addr,
2461 am2offset_reg:$offset),
2462 (STR_POST_REG GPR:$Rt, addr_offset_none:$addr,
2463 am2offset_reg:$offset)>;
2464 def : ARMPat<(post_store GPR:$Rt, addr_offset_none:$addr,
2465 am2offset_imm:$offset),
2466 (STR_POST_IMM GPR:$Rt, addr_offset_none:$addr,
2467 am2offset_imm:$offset)>;
2468 def : ARMPat<(post_truncsti8 GPR:$Rt, addr_offset_none:$addr,
2469 am2offset_reg:$offset),
2470 (STRB_POST_REG GPR:$Rt, addr_offset_none:$addr,
2471 am2offset_reg:$offset)>;
2472 def : ARMPat<(post_truncsti8 GPR:$Rt, addr_offset_none:$addr,
2473 am2offset_imm:$offset),
2474 (STRB_POST_IMM GPR:$Rt, addr_offset_none:$addr,
2475 am2offset_imm:$offset)>;
2477 // Pseudo-instructions for pattern matching the pre-indexed stores. We can't
2478 // put the patterns on the instruction definitions directly as ISel wants
2479 // the address base and offset to be separate operands, not a single
2480 // complex operand like we represent the instructions themselves. The
2481 // pseudos map between the two.
2482 let usesCustomInserter = 1,
2483 Constraints = "$Rn = $Rn_wb,@earlyclobber $Rn_wb" in {
2484 def STRi_preidx: ARMPseudoInst<(outs GPR:$Rn_wb),
2485 (ins GPR:$Rt, GPR:$Rn, am2offset_imm:$offset, pred:$p),
2488 (pre_store GPR:$Rt, GPR:$Rn, am2offset_imm:$offset))]>;
2489 def STRr_preidx: ARMPseudoInst<(outs GPR:$Rn_wb),
2490 (ins GPR:$Rt, GPR:$Rn, am2offset_reg:$offset, pred:$p),
2493 (pre_store GPR:$Rt, GPR:$Rn, am2offset_reg:$offset))]>;
2494 def STRBi_preidx: ARMPseudoInst<(outs GPR:$Rn_wb),
2495 (ins GPR:$Rt, GPR:$Rn, am2offset_imm:$offset, pred:$p),
2498 (pre_truncsti8 GPR:$Rt, GPR:$Rn, am2offset_imm:$offset))]>;
2499 def STRBr_preidx: ARMPseudoInst<(outs GPR:$Rn_wb),
2500 (ins GPR:$Rt, GPR:$Rn, am2offset_reg:$offset, pred:$p),
2503 (pre_truncsti8 GPR:$Rt, GPR:$Rn, am2offset_reg:$offset))]>;
2504 def STRH_preidx: ARMPseudoInst<(outs GPR:$Rn_wb),
2505 (ins GPR:$Rt, GPR:$Rn, am3offset:$offset, pred:$p),
2508 (pre_truncsti16 GPR:$Rt, GPR:$Rn, am3offset:$offset))]>;
2513 def STRH_PRE : AI3ldstidx<0b1011, 0, 1, (outs GPR:$Rn_wb),
2514 (ins GPR:$Rt, addrmode3:$addr), IndexModePre,
2515 StMiscFrm, IIC_iStore_bh_ru,
2516 "strh", "\t$Rt, $addr!", "$addr.base = $Rn_wb", []> {
2518 let Inst{23} = addr{8}; // U bit
2519 let Inst{22} = addr{13}; // 1 == imm8, 0 == Rm
2520 let Inst{19-16} = addr{12-9}; // Rn
2521 let Inst{11-8} = addr{7-4}; // imm7_4/zero
2522 let Inst{3-0} = addr{3-0}; // imm3_0/Rm
2523 let AsmMatchConverter = "cvtStWriteBackRegAddrMode3";
2524 let DecoderMethod = "DecodeAddrMode3Instruction";
2527 def STRH_POST : AI3ldstidx<0b1011, 0, 0, (outs GPR:$Rn_wb),
2528 (ins GPR:$Rt, addr_offset_none:$addr, am3offset:$offset),
2529 IndexModePost, StMiscFrm, IIC_iStore_bh_ru,
2530 "strh", "\t$Rt, $addr, $offset", "$addr.base = $Rn_wb",
2531 [(set GPR:$Rn_wb, (post_truncsti16 GPR:$Rt,
2532 addr_offset_none:$addr,
2533 am3offset:$offset))]> {
2536 let Inst{23} = offset{8}; // U bit
2537 let Inst{22} = offset{9}; // 1 == imm8, 0 == Rm
2538 let Inst{19-16} = addr;
2539 let Inst{11-8} = offset{7-4}; // imm7_4/zero
2540 let Inst{3-0} = offset{3-0}; // imm3_0/Rm
2541 let DecoderMethod = "DecodeAddrMode3Instruction";
2544 let mayStore = 1, neverHasSideEffects = 1, hasExtraSrcRegAllocReq = 1 in {
2545 def STRD_PRE : AI3ldstidx<0b1111, 0, 1, (outs GPR:$Rn_wb),
2546 (ins GPR:$Rt, GPR:$Rt2, addrmode3:$addr),
2547 IndexModePre, StMiscFrm, IIC_iStore_d_ru,
2548 "strd", "\t$Rt, $Rt2, $addr!",
2549 "$addr.base = $Rn_wb", []> {
2551 let Inst{23} = addr{8}; // U bit
2552 let Inst{22} = addr{13}; // 1 == imm8, 0 == Rm
2553 let Inst{19-16} = addr{12-9}; // Rn
2554 let Inst{11-8} = addr{7-4}; // imm7_4/zero
2555 let Inst{3-0} = addr{3-0}; // imm3_0/Rm
2556 let DecoderMethod = "DecodeAddrMode3Instruction";
2557 let AsmMatchConverter = "cvtStrdPre";
2560 def STRD_POST: AI3ldstidx<0b1111, 0, 0, (outs GPR:$Rn_wb),
2561 (ins GPR:$Rt, GPR:$Rt2, addr_offset_none:$addr,
2563 IndexModePost, StMiscFrm, IIC_iStore_d_ru,
2564 "strd", "\t$Rt, $Rt2, $addr, $offset",
2565 "$addr.base = $Rn_wb", []> {
2568 let Inst{23} = offset{8}; // U bit
2569 let Inst{22} = offset{9}; // 1 == imm8, 0 == Rm
2570 let Inst{19-16} = addr;
2571 let Inst{11-8} = offset{7-4}; // imm7_4/zero
2572 let Inst{3-0} = offset{3-0}; // imm3_0/Rm
2573 let DecoderMethod = "DecodeAddrMode3Instruction";
2575 } // mayStore = 1, neverHasSideEffects = 1, hasExtraSrcRegAllocReq = 1
2577 // STRT, STRBT, and STRHT
2579 def STRBT_POST_REG : AI2ldstidx<0, 1, 0, (outs GPR:$Rn_wb),
2580 (ins GPR:$Rt, addr_offset_none:$addr, am2offset_reg:$offset),
2581 IndexModePost, StFrm, IIC_iStore_bh_ru,
2582 "strbt", "\t$Rt, $addr, $offset",
2583 "$addr.base = $Rn_wb", []> {
2589 let Inst{23} = offset{12};
2590 let Inst{21} = 1; // overwrite
2591 let Inst{19-16} = addr;
2592 let Inst{11-5} = offset{11-5};
2594 let Inst{3-0} = offset{3-0};
2595 let DecoderMethod = "DecodeAddrMode2IdxInstruction";
2598 def STRBT_POST_IMM : AI2ldstidx<0, 1, 0, (outs GPR:$Rn_wb),
2599 (ins GPR:$Rt, addr_offset_none:$addr, am2offset_imm:$offset),
2600 IndexModePost, StFrm, IIC_iStore_bh_ru,
2601 "strbt", "\t$Rt, $addr, $offset",
2602 "$addr.base = $Rn_wb", []> {
2608 let Inst{23} = offset{12};
2609 let Inst{21} = 1; // overwrite
2610 let Inst{19-16} = addr;
2611 let Inst{11-0} = offset{11-0};
2612 let DecoderMethod = "DecodeAddrMode2IdxInstruction";
2615 let mayStore = 1, neverHasSideEffects = 1 in {
2616 def STRT_POST_REG : AI2ldstidx<0, 0, 0, (outs GPR:$Rn_wb),
2617 (ins GPR:$Rt, addr_offset_none:$addr, am2offset_reg:$offset),
2618 IndexModePost, StFrm, IIC_iStore_ru,
2619 "strt", "\t$Rt, $addr, $offset",
2620 "$addr.base = $Rn_wb", []> {
2626 let Inst{23} = offset{12};
2627 let Inst{21} = 1; // overwrite
2628 let Inst{19-16} = addr;
2629 let Inst{11-5} = offset{11-5};
2631 let Inst{3-0} = offset{3-0};
2632 let DecoderMethod = "DecodeAddrMode2IdxInstruction";
2635 def STRT_POST_IMM : AI2ldstidx<0, 0, 0, (outs GPR:$Rn_wb),
2636 (ins GPR:$Rt, addr_offset_none:$addr, am2offset_imm:$offset),
2637 IndexModePost, StFrm, IIC_iStore_ru,
2638 "strt", "\t$Rt, $addr, $offset",
2639 "$addr.base = $Rn_wb", []> {
2645 let Inst{23} = offset{12};
2646 let Inst{21} = 1; // overwrite
2647 let Inst{19-16} = addr;
2648 let Inst{11-0} = offset{11-0};
2649 let DecoderMethod = "DecodeAddrMode2IdxInstruction";
2654 multiclass AI3strT<bits<4> op, string opc> {
2655 def i : AI3ldstidxT<op, 0, (outs GPR:$base_wb),
2656 (ins GPR:$Rt, addr_offset_none:$addr, postidx_imm8:$offset),
2657 IndexModePost, StMiscFrm, IIC_iStore_bh_ru, opc,
2658 "\t$Rt, $addr, $offset", "$addr.base = $base_wb", []> {
2660 let Inst{23} = offset{8};
2662 let Inst{11-8} = offset{7-4};
2663 let Inst{3-0} = offset{3-0};
2664 let AsmMatchConverter = "cvtStExtTWriteBackImm";
2666 def r : AI3ldstidxT<op, 0, (outs GPR:$base_wb),
2667 (ins GPR:$Rt, addr_offset_none:$addr, postidx_reg:$Rm),
2668 IndexModePost, StMiscFrm, IIC_iStore_bh_ru, opc,
2669 "\t$Rt, $addr, $Rm", "$addr.base = $base_wb", []> {
2671 let Inst{23} = Rm{4};
2674 let Inst{3-0} = Rm{3-0};
2675 let AsmMatchConverter = "cvtStExtTWriteBackReg";
2680 defm STRHT : AI3strT<0b1011, "strht">;
2683 //===----------------------------------------------------------------------===//
2684 // Load / store multiple Instructions.
2687 multiclass arm_ldst_mult<string asm, string sfx, bit L_bit, bit P_bit, Format f,
2688 InstrItinClass itin, InstrItinClass itin_upd> {
2689 // IA is the default, so no need for an explicit suffix on the
2690 // mnemonic here. Without it is the canonical spelling.
2692 AXI4<(outs), (ins GPR:$Rn, pred:$p, reglist:$regs, variable_ops),
2693 IndexModeNone, f, itin,
2694 !strconcat(asm, "${p}\t$Rn, $regs", sfx), "", []> {
2695 let Inst{24-23} = 0b01; // Increment After
2696 let Inst{22} = P_bit;
2697 let Inst{21} = 0; // No writeback
2698 let Inst{20} = L_bit;
2701 AXI4<(outs GPR:$wb), (ins GPR:$Rn, pred:$p, reglist:$regs, variable_ops),
2702 IndexModeUpd, f, itin_upd,
2703 !strconcat(asm, "${p}\t$Rn!, $regs", sfx), "$Rn = $wb", []> {
2704 let Inst{24-23} = 0b01; // Increment After
2705 let Inst{22} = P_bit;
2706 let Inst{21} = 1; // Writeback
2707 let Inst{20} = L_bit;
2709 let DecoderMethod = "DecodeMemMultipleWritebackInstruction";
2712 AXI4<(outs), (ins GPR:$Rn, pred:$p, reglist:$regs, variable_ops),
2713 IndexModeNone, f, itin,
2714 !strconcat(asm, "da${p}\t$Rn, $regs", sfx), "", []> {
2715 let Inst{24-23} = 0b00; // Decrement After
2716 let Inst{22} = P_bit;
2717 let Inst{21} = 0; // No writeback
2718 let Inst{20} = L_bit;
2721 AXI4<(outs GPR:$wb), (ins GPR:$Rn, pred:$p, reglist:$regs, variable_ops),
2722 IndexModeUpd, f, itin_upd,
2723 !strconcat(asm, "da${p}\t$Rn!, $regs", sfx), "$Rn = $wb", []> {
2724 let Inst{24-23} = 0b00; // Decrement After
2725 let Inst{22} = P_bit;
2726 let Inst{21} = 1; // Writeback
2727 let Inst{20} = L_bit;
2729 let DecoderMethod = "DecodeMemMultipleWritebackInstruction";
2732 AXI4<(outs), (ins GPR:$Rn, pred:$p, reglist:$regs, variable_ops),
2733 IndexModeNone, f, itin,
2734 !strconcat(asm, "db${p}\t$Rn, $regs", sfx), "", []> {
2735 let Inst{24-23} = 0b10; // Decrement Before
2736 let Inst{22} = P_bit;
2737 let Inst{21} = 0; // No writeback
2738 let Inst{20} = L_bit;
2741 AXI4<(outs GPR:$wb), (ins GPR:$Rn, pred:$p, reglist:$regs, variable_ops),
2742 IndexModeUpd, f, itin_upd,
2743 !strconcat(asm, "db${p}\t$Rn!, $regs", sfx), "$Rn = $wb", []> {
2744 let Inst{24-23} = 0b10; // Decrement Before
2745 let Inst{22} = P_bit;
2746 let Inst{21} = 1; // Writeback
2747 let Inst{20} = L_bit;
2749 let DecoderMethod = "DecodeMemMultipleWritebackInstruction";
2752 AXI4<(outs), (ins GPR:$Rn, pred:$p, reglist:$regs, variable_ops),
2753 IndexModeNone, f, itin,
2754 !strconcat(asm, "ib${p}\t$Rn, $regs", sfx), "", []> {
2755 let Inst{24-23} = 0b11; // Increment Before
2756 let Inst{22} = P_bit;
2757 let Inst{21} = 0; // No writeback
2758 let Inst{20} = L_bit;
2761 AXI4<(outs GPR:$wb), (ins GPR:$Rn, pred:$p, reglist:$regs, variable_ops),
2762 IndexModeUpd, f, itin_upd,
2763 !strconcat(asm, "ib${p}\t$Rn!, $regs", sfx), "$Rn = $wb", []> {
2764 let Inst{24-23} = 0b11; // Increment Before
2765 let Inst{22} = P_bit;
2766 let Inst{21} = 1; // Writeback
2767 let Inst{20} = L_bit;
2769 let DecoderMethod = "DecodeMemMultipleWritebackInstruction";
2773 let neverHasSideEffects = 1 in {
2775 let mayLoad = 1, hasExtraDefRegAllocReq = 1 in
2776 defm LDM : arm_ldst_mult<"ldm", "", 1, 0, LdStMulFrm, IIC_iLoad_m,
2779 let mayStore = 1, hasExtraSrcRegAllocReq = 1 in
2780 defm STM : arm_ldst_mult<"stm", "", 0, 0, LdStMulFrm, IIC_iStore_m,
2783 } // neverHasSideEffects
2785 // FIXME: remove when we have a way to marking a MI with these properties.
2786 // FIXME: Should pc be an implicit operand like PICADD, etc?
2787 let isReturn = 1, isTerminator = 1, isBarrier = 1, mayLoad = 1,
2788 hasExtraDefRegAllocReq = 1, isCodeGenOnly = 1 in
2789 def LDMIA_RET : ARMPseudoExpand<(outs GPR:$wb), (ins GPR:$Rn, pred:$p,
2790 reglist:$regs, variable_ops),
2791 4, IIC_iLoad_mBr, [],
2792 (LDMIA_UPD GPR:$wb, GPR:$Rn, pred:$p, reglist:$regs)>,
2793 RegConstraint<"$Rn = $wb">;
2795 let mayLoad = 1, hasExtraDefRegAllocReq = 1 in
2796 defm sysLDM : arm_ldst_mult<"ldm", " ^", 1, 1, LdStMulFrm, IIC_iLoad_m,
2799 let mayStore = 1, hasExtraSrcRegAllocReq = 1 in
2800 defm sysSTM : arm_ldst_mult<"stm", " ^", 0, 1, LdStMulFrm, IIC_iStore_m,
2805 //===----------------------------------------------------------------------===//
2806 // Move Instructions.
2809 let neverHasSideEffects = 1 in
2810 def MOVr : AsI1<0b1101, (outs GPR:$Rd), (ins GPR:$Rm), DPFrm, IIC_iMOVr,
2811 "mov", "\t$Rd, $Rm", []>, UnaryDP {
2815 let Inst{19-16} = 0b0000;
2816 let Inst{11-4} = 0b00000000;
2819 let Inst{15-12} = Rd;
2822 def : ARMInstAlias<"movs${p} $Rd, $Rm",
2823 (MOVr GPR:$Rd, GPR:$Rm, pred:$p, CPSR)>;
2825 // A version for the smaller set of tail call registers.
2826 let neverHasSideEffects = 1 in
2827 def MOVr_TC : AsI1<0b1101, (outs tcGPR:$Rd), (ins tcGPR:$Rm), DPFrm,
2828 IIC_iMOVr, "mov", "\t$Rd, $Rm", []>, UnaryDP {
2832 let Inst{11-4} = 0b00000000;
2835 let Inst{15-12} = Rd;
2838 def MOVsr : AsI1<0b1101, (outs GPRnopc:$Rd), (ins shift_so_reg_reg:$src),
2839 DPSoRegRegFrm, IIC_iMOVsr,
2840 "mov", "\t$Rd, $src",
2841 [(set GPRnopc:$Rd, shift_so_reg_reg:$src)]>, UnaryDP {
2844 let Inst{15-12} = Rd;
2845 let Inst{19-16} = 0b0000;
2846 let Inst{11-8} = src{11-8};
2848 let Inst{6-5} = src{6-5};
2850 let Inst{3-0} = src{3-0};
2854 def MOVsi : AsI1<0b1101, (outs GPR:$Rd), (ins shift_so_reg_imm:$src),
2855 DPSoRegImmFrm, IIC_iMOVsr,
2856 "mov", "\t$Rd, $src", [(set GPR:$Rd, shift_so_reg_imm:$src)]>,
2860 let Inst{15-12} = Rd;
2861 let Inst{19-16} = 0b0000;
2862 let Inst{11-5} = src{11-5};
2864 let Inst{3-0} = src{3-0};
2868 let isReMaterializable = 1, isAsCheapAsAMove = 1, isMoveImm = 1 in
2869 def MOVi : AsI1<0b1101, (outs GPR:$Rd), (ins so_imm:$imm), DPFrm, IIC_iMOVi,
2870 "mov", "\t$Rd, $imm", [(set GPR:$Rd, so_imm:$imm)]>, UnaryDP {
2874 let Inst{15-12} = Rd;
2875 let Inst{19-16} = 0b0000;
2876 let Inst{11-0} = imm;
2879 let isReMaterializable = 1, isAsCheapAsAMove = 1, isMoveImm = 1 in
2880 def MOVi16 : AI1<0b1000, (outs GPR:$Rd), (ins imm0_65535_expr:$imm),
2882 "movw", "\t$Rd, $imm",
2883 [(set GPR:$Rd, imm0_65535:$imm)]>,
2884 Requires<[IsARM, HasV6T2]>, UnaryDP {
2887 let Inst{15-12} = Rd;
2888 let Inst{11-0} = imm{11-0};
2889 let Inst{19-16} = imm{15-12};
2892 let DecoderMethod = "DecodeArmMOVTWInstruction";
2895 def : InstAlias<"mov${p} $Rd, $imm",
2896 (MOVi16 GPR:$Rd, imm0_65535_expr:$imm, pred:$p)>,
2899 def MOVi16_ga_pcrel : PseudoInst<(outs GPR:$Rd),
2900 (ins i32imm:$addr, pclabel:$id), IIC_iMOVi, []>;
2902 let Constraints = "$src = $Rd" in {
2903 def MOVTi16 : AI1<0b1010, (outs GPRnopc:$Rd),
2904 (ins GPR:$src, imm0_65535_expr:$imm),
2906 "movt", "\t$Rd, $imm",
2908 (or (and GPR:$src, 0xffff),
2909 lo16AllZero:$imm))]>, UnaryDP,
2910 Requires<[IsARM, HasV6T2]> {
2913 let Inst{15-12} = Rd;
2914 let Inst{11-0} = imm{11-0};
2915 let Inst{19-16} = imm{15-12};
2918 let DecoderMethod = "DecodeArmMOVTWInstruction";
2921 def MOVTi16_ga_pcrel : PseudoInst<(outs GPR:$Rd),
2922 (ins GPR:$src, i32imm:$addr, pclabel:$id), IIC_iMOVi, []>;
2926 def : ARMPat<(or GPR:$src, 0xffff0000), (MOVTi16 GPR:$src, 0xffff)>,
2927 Requires<[IsARM, HasV6T2]>;
2929 let Uses = [CPSR] in
2930 def RRX: PseudoInst<(outs GPR:$Rd), (ins GPR:$Rm), IIC_iMOVsi,
2931 [(set GPR:$Rd, (ARMrrx GPR:$Rm))]>, UnaryDP,
2934 // These aren't really mov instructions, but we have to define them this way
2935 // due to flag operands.
2937 let Defs = [CPSR] in {
2938 def MOVsrl_flag : PseudoInst<(outs GPR:$dst), (ins GPR:$src), IIC_iMOVsi,
2939 [(set GPR:$dst, (ARMsrl_flag GPR:$src))]>, UnaryDP,
2941 def MOVsra_flag : PseudoInst<(outs GPR:$dst), (ins GPR:$src), IIC_iMOVsi,
2942 [(set GPR:$dst, (ARMsra_flag GPR:$src))]>, UnaryDP,
2946 //===----------------------------------------------------------------------===//
2947 // Extend Instructions.
2952 def SXTB : AI_ext_rrot<0b01101010,
2953 "sxtb", UnOpFrag<(sext_inreg node:$Src, i8)>>;
2954 def SXTH : AI_ext_rrot<0b01101011,
2955 "sxth", UnOpFrag<(sext_inreg node:$Src, i16)>>;
2957 def SXTAB : AI_exta_rrot<0b01101010,
2958 "sxtab", BinOpFrag<(add node:$LHS, (sext_inreg node:$RHS, i8))>>;
2959 def SXTAH : AI_exta_rrot<0b01101011,
2960 "sxtah", BinOpFrag<(add node:$LHS, (sext_inreg node:$RHS,i16))>>;
2962 def SXTB16 : AI_ext_rrot_np<0b01101000, "sxtb16">;
2964 def SXTAB16 : AI_exta_rrot_np<0b01101000, "sxtab16">;
2968 let AddedComplexity = 16 in {
2969 def UXTB : AI_ext_rrot<0b01101110,
2970 "uxtb" , UnOpFrag<(and node:$Src, 0x000000FF)>>;
2971 def UXTH : AI_ext_rrot<0b01101111,
2972 "uxth" , UnOpFrag<(and node:$Src, 0x0000FFFF)>>;
2973 def UXTB16 : AI_ext_rrot<0b01101100,
2974 "uxtb16", UnOpFrag<(and node:$Src, 0x00FF00FF)>>;
2976 // FIXME: This pattern incorrectly assumes the shl operator is a rotate.
2977 // The transformation should probably be done as a combiner action
2978 // instead so we can include a check for masking back in the upper
2979 // eight bits of the source into the lower eight bits of the result.
2980 //def : ARMV6Pat<(and (shl GPR:$Src, (i32 8)), 0xFF00FF),
2981 // (UXTB16r_rot GPR:$Src, 3)>;
2982 def : ARMV6Pat<(and (srl GPR:$Src, (i32 8)), 0xFF00FF),
2983 (UXTB16 GPR:$Src, 1)>;
2985 def UXTAB : AI_exta_rrot<0b01101110, "uxtab",
2986 BinOpFrag<(add node:$LHS, (and node:$RHS, 0x00FF))>>;
2987 def UXTAH : AI_exta_rrot<0b01101111, "uxtah",
2988 BinOpFrag<(add node:$LHS, (and node:$RHS, 0xFFFF))>>;
2991 // This isn't safe in general, the add is two 16-bit units, not a 32-bit add.
2992 def UXTAB16 : AI_exta_rrot_np<0b01101100, "uxtab16">;
2995 def SBFX : I<(outs GPRnopc:$Rd),
2996 (ins GPRnopc:$Rn, imm0_31:$lsb, imm1_32:$width),
2997 AddrMode1, 4, IndexModeNone, DPFrm, IIC_iUNAsi,
2998 "sbfx", "\t$Rd, $Rn, $lsb, $width", "", []>,
2999 Requires<[IsARM, HasV6T2]> {
3004 let Inst{27-21} = 0b0111101;
3005 let Inst{6-4} = 0b101;
3006 let Inst{20-16} = width;
3007 let Inst{15-12} = Rd;
3008 let Inst{11-7} = lsb;
3012 def UBFX : I<(outs GPR:$Rd),
3013 (ins GPR:$Rn, imm0_31:$lsb, imm1_32:$width),
3014 AddrMode1, 4, IndexModeNone, DPFrm, IIC_iUNAsi,
3015 "ubfx", "\t$Rd, $Rn, $lsb, $width", "", []>,
3016 Requires<[IsARM, HasV6T2]> {
3021 let Inst{27-21} = 0b0111111;
3022 let Inst{6-4} = 0b101;
3023 let Inst{20-16} = width;
3024 let Inst{15-12} = Rd;
3025 let Inst{11-7} = lsb;
3029 //===----------------------------------------------------------------------===//
3030 // Arithmetic Instructions.
3033 defm ADD : AsI1_bin_irs<0b0100, "add",
3034 IIC_iALUi, IIC_iALUr, IIC_iALUsr,
3035 BinOpFrag<(add node:$LHS, node:$RHS)>, "ADD", 1>;
3036 defm SUB : AsI1_bin_irs<0b0010, "sub",
3037 IIC_iALUi, IIC_iALUr, IIC_iALUsr,
3038 BinOpFrag<(sub node:$LHS, node:$RHS)>, "SUB">;
3040 // ADD and SUB with 's' bit set.
3042 // Currently, ADDS/SUBS are pseudo opcodes that exist only in the
3043 // selection DAG. They are "lowered" to real ADD/SUB opcodes by
3044 // AdjustInstrPostInstrSelection where we determine whether or not to
3045 // set the "s" bit based on CPSR liveness.
3047 // FIXME: Eliminate ADDS/SUBS pseudo opcodes after adding tablegen
3048 // support for an optional CPSR definition that corresponds to the DAG
3049 // node's second value. We can then eliminate the implicit def of CPSR.
3050 defm ADDS : AsI1_bin_s_irs<IIC_iALUi, IIC_iALUr, IIC_iALUsr,
3051 BinOpFrag<(ARMaddc node:$LHS, node:$RHS)>, 1>;
3052 defm SUBS : AsI1_bin_s_irs<IIC_iALUi, IIC_iALUr, IIC_iALUsr,
3053 BinOpFrag<(ARMsubc node:$LHS, node:$RHS)>>;
3055 defm ADC : AI1_adde_sube_irs<0b0101, "adc",
3056 BinOpWithFlagFrag<(ARMadde node:$LHS, node:$RHS, node:$FLAG)>,
3058 defm SBC : AI1_adde_sube_irs<0b0110, "sbc",
3059 BinOpWithFlagFrag<(ARMsube node:$LHS, node:$RHS, node:$FLAG)>,
3062 defm RSB : AsI1_rbin_irs <0b0011, "rsb",
3063 IIC_iALUi, IIC_iALUr, IIC_iALUsr,
3064 BinOpFrag<(sub node:$LHS, node:$RHS)>, "RSB">;
3066 // FIXME: Eliminate them if we can write def : Pat patterns which defines
3067 // CPSR and the implicit def of CPSR is not needed.
3068 defm RSBS : AsI1_rbin_s_is<IIC_iALUi, IIC_iALUr, IIC_iALUsr,
3069 BinOpFrag<(ARMsubc node:$LHS, node:$RHS)>>;
3071 defm RSC : AI1_rsc_irs<0b0111, "rsc",
3072 BinOpWithFlagFrag<(ARMsube node:$LHS, node:$RHS, node:$FLAG)>,
3075 // (sub X, imm) gets canonicalized to (add X, -imm). Match this form.
3076 // The assume-no-carry-in form uses the negation of the input since add/sub
3077 // assume opposite meanings of the carry flag (i.e., carry == !borrow).
3078 // See the definition of AddWithCarry() in the ARM ARM A2.2.1 for the gory
3080 def : ARMPat<(add GPR:$src, so_imm_neg:$imm),
3081 (SUBri GPR:$src, so_imm_neg:$imm)>;
3082 def : ARMPat<(ARMaddc GPR:$src, so_imm_neg:$imm),
3083 (SUBSri GPR:$src, so_imm_neg:$imm)>;
3085 def : ARMPat<(add GPR:$src, imm0_65535_neg:$imm),
3086 (SUBrr GPR:$src, (MOVi16 (imm_neg_XFORM imm:$imm)))>;
3087 def : ARMPat<(ARMaddc GPR:$src, imm0_65535_neg:$imm),
3088 (SUBSrr GPR:$src, (MOVi16 (imm_neg_XFORM imm:$imm)))>;
3090 // The with-carry-in form matches bitwise not instead of the negation.
3091 // Effectively, the inverse interpretation of the carry flag already accounts
3092 // for part of the negation.
3093 def : ARMPat<(ARMadde GPR:$src, so_imm_not:$imm, CPSR),
3094 (SBCri GPR:$src, so_imm_not:$imm)>;
3096 // Note: These are implemented in C++ code, because they have to generate
3097 // ADD/SUBrs instructions, which use a complex pattern that a xform function
3099 // (mul X, 2^n+1) -> (add (X << n), X)
3100 // (mul X, 2^n-1) -> (rsb X, (X << n))
3102 // ARM Arithmetic Instruction
3103 // GPR:$dst = GPR:$a op GPR:$b
3104 class AAI<bits<8> op27_20, bits<8> op11_4, string opc,
3105 list<dag> pattern = [],
3106 dag iops = (ins GPRnopc:$Rn, GPRnopc:$Rm),
3107 string asm = "\t$Rd, $Rn, $Rm">
3108 : AI<(outs GPRnopc:$Rd), iops, DPFrm, IIC_iALUr, opc, asm, pattern> {
3112 let Inst{27-20} = op27_20;
3113 let Inst{11-4} = op11_4;
3114 let Inst{19-16} = Rn;
3115 let Inst{15-12} = Rd;
3118 let Unpredictable{11-8} = 0b1111;
3121 // Saturating add/subtract
3123 def QADD : AAI<0b00010000, 0b00000101, "qadd",
3124 [(set GPRnopc:$Rd, (int_arm_qadd GPRnopc:$Rm, GPRnopc:$Rn))],
3125 (ins GPRnopc:$Rm, GPRnopc:$Rn), "\t$Rd, $Rm, $Rn">;
3126 def QSUB : AAI<0b00010010, 0b00000101, "qsub",
3127 [(set GPRnopc:$Rd, (int_arm_qsub GPRnopc:$Rm, GPRnopc:$Rn))],
3128 (ins GPRnopc:$Rm, GPRnopc:$Rn), "\t$Rd, $Rm, $Rn">;
3129 def QDADD : AAI<0b00010100, 0b00000101, "qdadd", [],
3130 (ins GPRnopc:$Rm, GPRnopc:$Rn),
3132 def QDSUB : AAI<0b00010110, 0b00000101, "qdsub", [],
3133 (ins GPRnopc:$Rm, GPRnopc:$Rn),
3136 def QADD16 : AAI<0b01100010, 0b11110001, "qadd16">;
3137 def QADD8 : AAI<0b01100010, 0b11111001, "qadd8">;
3138 def QASX : AAI<0b01100010, 0b11110011, "qasx">;
3139 def QSAX : AAI<0b01100010, 0b11110101, "qsax">;
3140 def QSUB16 : AAI<0b01100010, 0b11110111, "qsub16">;
3141 def QSUB8 : AAI<0b01100010, 0b11111111, "qsub8">;
3142 def UQADD16 : AAI<0b01100110, 0b11110001, "uqadd16">;
3143 def UQADD8 : AAI<0b01100110, 0b11111001, "uqadd8">;
3144 def UQASX : AAI<0b01100110, 0b11110011, "uqasx">;
3145 def UQSAX : AAI<0b01100110, 0b11110101, "uqsax">;
3146 def UQSUB16 : AAI<0b01100110, 0b11110111, "uqsub16">;
3147 def UQSUB8 : AAI<0b01100110, 0b11111111, "uqsub8">;
3149 // Signed/Unsigned add/subtract
3151 def SASX : AAI<0b01100001, 0b11110011, "sasx">;
3152 def SADD16 : AAI<0b01100001, 0b11110001, "sadd16">;
3153 def SADD8 : AAI<0b01100001, 0b11111001, "sadd8">;
3154 def SSAX : AAI<0b01100001, 0b11110101, "ssax">;
3155 def SSUB16 : AAI<0b01100001, 0b11110111, "ssub16">;
3156 def SSUB8 : AAI<0b01100001, 0b11111111, "ssub8">;
3157 def UASX : AAI<0b01100101, 0b11110011, "uasx">;
3158 def UADD16 : AAI<0b01100101, 0b11110001, "uadd16">;
3159 def UADD8 : AAI<0b01100101, 0b11111001, "uadd8">;
3160 def USAX : AAI<0b01100101, 0b11110101, "usax">;
3161 def USUB16 : AAI<0b01100101, 0b11110111, "usub16">;
3162 def USUB8 : AAI<0b01100101, 0b11111111, "usub8">;
3164 // Signed/Unsigned halving add/subtract
3166 def SHASX : AAI<0b01100011, 0b11110011, "shasx">;
3167 def SHADD16 : AAI<0b01100011, 0b11110001, "shadd16">;
3168 def SHADD8 : AAI<0b01100011, 0b11111001, "shadd8">;
3169 def SHSAX : AAI<0b01100011, 0b11110101, "shsax">;
3170 def SHSUB16 : AAI<0b01100011, 0b11110111, "shsub16">;
3171 def SHSUB8 : AAI<0b01100011, 0b11111111, "shsub8">;
3172 def UHASX : AAI<0b01100111, 0b11110011, "uhasx">;
3173 def UHADD16 : AAI<0b01100111, 0b11110001, "uhadd16">;
3174 def UHADD8 : AAI<0b01100111, 0b11111001, "uhadd8">;
3175 def UHSAX : AAI<0b01100111, 0b11110101, "uhsax">;
3176 def UHSUB16 : AAI<0b01100111, 0b11110111, "uhsub16">;
3177 def UHSUB8 : AAI<0b01100111, 0b11111111, "uhsub8">;
3179 // Unsigned Sum of Absolute Differences [and Accumulate].
3181 def USAD8 : AI<(outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm),
3182 MulFrm /* for convenience */, NoItinerary, "usad8",
3183 "\t$Rd, $Rn, $Rm", []>,
3184 Requires<[IsARM, HasV6]> {
3188 let Inst{27-20} = 0b01111000;
3189 let Inst{15-12} = 0b1111;
3190 let Inst{7-4} = 0b0001;
3191 let Inst{19-16} = Rd;
3192 let Inst{11-8} = Rm;
3195 def USADA8 : AI<(outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm, GPR:$Ra),
3196 MulFrm /* for convenience */, NoItinerary, "usada8",
3197 "\t$Rd, $Rn, $Rm, $Ra", []>,
3198 Requires<[IsARM, HasV6]> {
3203 let Inst{27-20} = 0b01111000;
3204 let Inst{7-4} = 0b0001;
3205 let Inst{19-16} = Rd;
3206 let Inst{15-12} = Ra;
3207 let Inst{11-8} = Rm;
3211 // Signed/Unsigned saturate
3213 def SSAT : AI<(outs GPRnopc:$Rd),
3214 (ins imm1_32:$sat_imm, GPRnopc:$Rn, shift_imm:$sh),
3215 SatFrm, NoItinerary, "ssat", "\t$Rd, $sat_imm, $Rn$sh", []> {
3220 let Inst{27-21} = 0b0110101;
3221 let Inst{5-4} = 0b01;
3222 let Inst{20-16} = sat_imm;
3223 let Inst{15-12} = Rd;
3224 let Inst{11-7} = sh{4-0};
3225 let Inst{6} = sh{5};
3229 def SSAT16 : AI<(outs GPRnopc:$Rd),
3230 (ins imm1_16:$sat_imm, GPRnopc:$Rn), SatFrm,
3231 NoItinerary, "ssat16", "\t$Rd, $sat_imm, $Rn", []> {
3235 let Inst{27-20} = 0b01101010;
3236 let Inst{11-4} = 0b11110011;
3237 let Inst{15-12} = Rd;
3238 let Inst{19-16} = sat_imm;
3242 def USAT : AI<(outs GPRnopc:$Rd),
3243 (ins imm0_31:$sat_imm, GPRnopc:$Rn, shift_imm:$sh),
3244 SatFrm, NoItinerary, "usat", "\t$Rd, $sat_imm, $Rn$sh", []> {
3249 let Inst{27-21} = 0b0110111;
3250 let Inst{5-4} = 0b01;
3251 let Inst{15-12} = Rd;
3252 let Inst{11-7} = sh{4-0};
3253 let Inst{6} = sh{5};
3254 let Inst{20-16} = sat_imm;
3258 def USAT16 : AI<(outs GPRnopc:$Rd),
3259 (ins imm0_15:$sat_imm, GPRnopc:$Rn), SatFrm,
3260 NoItinerary, "usat16", "\t$Rd, $sat_imm, $Rn", []> {
3264 let Inst{27-20} = 0b01101110;
3265 let Inst{11-4} = 0b11110011;
3266 let Inst{15-12} = Rd;
3267 let Inst{19-16} = sat_imm;
3271 def : ARMV6Pat<(int_arm_ssat GPRnopc:$a, imm:$pos),
3272 (SSAT imm:$pos, GPRnopc:$a, 0)>;
3273 def : ARMV6Pat<(int_arm_usat GPRnopc:$a, imm:$pos),
3274 (USAT imm:$pos, GPRnopc:$a, 0)>;
3276 //===----------------------------------------------------------------------===//
3277 // Bitwise Instructions.
3280 defm AND : AsI1_bin_irs<0b0000, "and",
3281 IIC_iBITi, IIC_iBITr, IIC_iBITsr,
3282 BinOpFrag<(and node:$LHS, node:$RHS)>, "AND", 1>;
3283 defm ORR : AsI1_bin_irs<0b1100, "orr",
3284 IIC_iBITi, IIC_iBITr, IIC_iBITsr,
3285 BinOpFrag<(or node:$LHS, node:$RHS)>, "ORR", 1>;
3286 defm EOR : AsI1_bin_irs<0b0001, "eor",
3287 IIC_iBITi, IIC_iBITr, IIC_iBITsr,
3288 BinOpFrag<(xor node:$LHS, node:$RHS)>, "EOR", 1>;
3289 defm BIC : AsI1_bin_irs<0b1110, "bic",
3290 IIC_iBITi, IIC_iBITr, IIC_iBITsr,
3291 BinOpFrag<(and node:$LHS, (not node:$RHS))>, "BIC">;
3293 // FIXME: bf_inv_mask_imm should be two operands, the lsb and the msb, just
3294 // like in the actual instruction encoding. The complexity of mapping the mask
3295 // to the lsb/msb pair should be handled by ISel, not encapsulated in the
3296 // instruction description.
3297 def BFC : I<(outs GPR:$Rd), (ins GPR:$src, bf_inv_mask_imm:$imm),
3298 AddrMode1, 4, IndexModeNone, DPFrm, IIC_iUNAsi,
3299 "bfc", "\t$Rd, $imm", "$src = $Rd",
3300 [(set GPR:$Rd, (and GPR:$src, bf_inv_mask_imm:$imm))]>,
3301 Requires<[IsARM, HasV6T2]> {
3304 let Inst{27-21} = 0b0111110;
3305 let Inst{6-0} = 0b0011111;
3306 let Inst{15-12} = Rd;
3307 let Inst{11-7} = imm{4-0}; // lsb
3308 let Inst{20-16} = imm{9-5}; // msb
3311 // A8.6.18 BFI - Bitfield insert (Encoding A1)
3312 def BFI:I<(outs GPRnopc:$Rd), (ins GPRnopc:$src, GPR:$Rn, bf_inv_mask_imm:$imm),
3313 AddrMode1, 4, IndexModeNone, DPFrm, IIC_iUNAsi,
3314 "bfi", "\t$Rd, $Rn, $imm", "$src = $Rd",
3315 [(set GPRnopc:$Rd, (ARMbfi GPRnopc:$src, GPR:$Rn,
3316 bf_inv_mask_imm:$imm))]>,
3317 Requires<[IsARM, HasV6T2]> {
3321 let Inst{27-21} = 0b0111110;
3322 let Inst{6-4} = 0b001; // Rn: Inst{3-0} != 15
3323 let Inst{15-12} = Rd;
3324 let Inst{11-7} = imm{4-0}; // lsb
3325 let Inst{20-16} = imm{9-5}; // width
3329 def MVNr : AsI1<0b1111, (outs GPR:$Rd), (ins GPR:$Rm), DPFrm, IIC_iMVNr,
3330 "mvn", "\t$Rd, $Rm",
3331 [(set GPR:$Rd, (not GPR:$Rm))]>, UnaryDP {
3335 let Inst{19-16} = 0b0000;
3336 let Inst{11-4} = 0b00000000;
3337 let Inst{15-12} = Rd;
3340 def MVNsi : AsI1<0b1111, (outs GPR:$Rd), (ins so_reg_imm:$shift),
3341 DPSoRegImmFrm, IIC_iMVNsr, "mvn", "\t$Rd, $shift",
3342 [(set GPR:$Rd, (not so_reg_imm:$shift))]>, UnaryDP {
3346 let Inst{19-16} = 0b0000;
3347 let Inst{15-12} = Rd;
3348 let Inst{11-5} = shift{11-5};
3350 let Inst{3-0} = shift{3-0};
3352 def MVNsr : AsI1<0b1111, (outs GPR:$Rd), (ins so_reg_reg:$shift),
3353 DPSoRegRegFrm, IIC_iMVNsr, "mvn", "\t$Rd, $shift",
3354 [(set GPR:$Rd, (not so_reg_reg:$shift))]>, UnaryDP {
3358 let Inst{19-16} = 0b0000;
3359 let Inst{15-12} = Rd;
3360 let Inst{11-8} = shift{11-8};
3362 let Inst{6-5} = shift{6-5};
3364 let Inst{3-0} = shift{3-0};
3366 let isReMaterializable = 1, isAsCheapAsAMove = 1, isMoveImm = 1 in
3367 def MVNi : AsI1<0b1111, (outs GPR:$Rd), (ins so_imm:$imm), DPFrm,
3368 IIC_iMVNi, "mvn", "\t$Rd, $imm",
3369 [(set GPR:$Rd, so_imm_not:$imm)]>,UnaryDP {
3373 let Inst{19-16} = 0b0000;
3374 let Inst{15-12} = Rd;
3375 let Inst{11-0} = imm;
3378 def : ARMPat<(and GPR:$src, so_imm_not:$imm),
3379 (BICri GPR:$src, so_imm_not:$imm)>;
3381 //===----------------------------------------------------------------------===//
3382 // Multiply Instructions.
3384 class AsMul1I32<bits<7> opcod, dag oops, dag iops, InstrItinClass itin,
3385 string opc, string asm, list<dag> pattern>
3386 : AsMul1I<opcod, oops, iops, itin, opc, asm, pattern> {
3390 let Inst{19-16} = Rd;
3391 let Inst{11-8} = Rm;
3394 class AsMul1I64<bits<7> opcod, dag oops, dag iops, InstrItinClass itin,
3395 string opc, string asm, list<dag> pattern>
3396 : AsMul1I<opcod, oops, iops, itin, opc, asm, pattern> {
3401 let Inst{19-16} = RdHi;
3402 let Inst{15-12} = RdLo;
3403 let Inst{11-8} = Rm;
3407 // FIXME: The v5 pseudos are only necessary for the additional Constraint
3408 // property. Remove them when it's possible to add those properties
3409 // on an individual MachineInstr, not just an instruction description.
3410 let isCommutable = 1, TwoOperandAliasConstraint = "$Rn = $Rd" in {
3411 def MUL : AsMul1I32<0b0000000, (outs GPRnopc:$Rd),
3412 (ins GPRnopc:$Rn, GPRnopc:$Rm),
3413 IIC_iMUL32, "mul", "\t$Rd, $Rn, $Rm",
3414 [(set GPRnopc:$Rd, (mul GPRnopc:$Rn, GPRnopc:$Rm))]>,
3415 Requires<[IsARM, HasV6]> {
3416 let Inst{15-12} = 0b0000;
3417 let Unpredictable{15-12} = 0b1111;
3420 let Constraints = "@earlyclobber $Rd" in
3421 def MULv5: ARMPseudoExpand<(outs GPRnopc:$Rd), (ins GPRnopc:$Rn, GPRnopc:$Rm,
3422 pred:$p, cc_out:$s),
3424 [(set GPRnopc:$Rd, (mul GPRnopc:$Rn, GPRnopc:$Rm))],
3425 (MUL GPRnopc:$Rd, GPRnopc:$Rn, GPRnopc:$Rm, pred:$p, cc_out:$s)>,
3426 Requires<[IsARM, NoV6]>;
3429 def MLA : AsMul1I32<0b0000001, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm, GPR:$Ra),
3430 IIC_iMAC32, "mla", "\t$Rd, $Rn, $Rm, $Ra",
3431 [(set GPR:$Rd, (add (mul GPR:$Rn, GPR:$Rm), GPR:$Ra))]>,
3432 Requires<[IsARM, HasV6]> {
3434 let Inst{15-12} = Ra;
3437 let Constraints = "@earlyclobber $Rd" in
3438 def MLAv5: ARMPseudoExpand<(outs GPR:$Rd),
3439 (ins GPR:$Rn, GPR:$Rm, GPR:$Ra, pred:$p, cc_out:$s),
3441 [(set GPR:$Rd, (add (mul GPR:$Rn, GPR:$Rm), GPR:$Ra))],
3442 (MLA GPR:$Rd, GPR:$Rn, GPR:$Rm, GPR:$Ra, pred:$p, cc_out:$s)>,
3443 Requires<[IsARM, NoV6]>;
3445 def MLS : AMul1I<0b0000011, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm, GPR:$Ra),
3446 IIC_iMAC32, "mls", "\t$Rd, $Rn, $Rm, $Ra",
3447 [(set GPR:$Rd, (sub GPR:$Ra, (mul GPR:$Rn, GPR:$Rm)))]>,
3448 Requires<[IsARM, HasV6T2]> {
3453 let Inst{19-16} = Rd;
3454 let Inst{15-12} = Ra;
3455 let Inst{11-8} = Rm;
3459 // Extra precision multiplies with low / high results
3460 let neverHasSideEffects = 1 in {
3461 let isCommutable = 1 in {
3462 def SMULL : AsMul1I64<0b0000110, (outs GPR:$RdLo, GPR:$RdHi),
3463 (ins GPR:$Rn, GPR:$Rm), IIC_iMUL64,
3464 "smull", "\t$RdLo, $RdHi, $Rn, $Rm", []>,
3465 Requires<[IsARM, HasV6]>;
3467 def UMULL : AsMul1I64<0b0000100, (outs GPR:$RdLo, GPR:$RdHi),
3468 (ins GPR:$Rn, GPR:$Rm), IIC_iMUL64,
3469 "umull", "\t$RdLo, $RdHi, $Rn, $Rm", []>,
3470 Requires<[IsARM, HasV6]>;
3472 let Constraints = "@earlyclobber $RdLo,@earlyclobber $RdHi" in {
3473 def SMULLv5 : ARMPseudoExpand<(outs GPR:$RdLo, GPR:$RdHi),
3474 (ins GPR:$Rn, GPR:$Rm, pred:$p, cc_out:$s),
3476 (SMULL GPR:$RdLo, GPR:$RdHi, GPR:$Rn, GPR:$Rm, pred:$p, cc_out:$s)>,
3477 Requires<[IsARM, NoV6]>;
3479 def UMULLv5 : ARMPseudoExpand<(outs GPR:$RdLo, GPR:$RdHi),
3480 (ins GPR:$Rn, GPR:$Rm, pred:$p, cc_out:$s),
3482 (UMULL GPR:$RdLo, GPR:$RdHi, GPR:$Rn, GPR:$Rm, pred:$p, cc_out:$s)>,
3483 Requires<[IsARM, NoV6]>;
3487 // Multiply + accumulate
3488 def SMLAL : AsMul1I64<0b0000111, (outs GPR:$RdLo, GPR:$RdHi),
3489 (ins GPR:$Rn, GPR:$Rm), IIC_iMAC64,
3490 "smlal", "\t$RdLo, $RdHi, $Rn, $Rm", []>,
3491 Requires<[IsARM, HasV6]>;
3492 def UMLAL : AsMul1I64<0b0000101, (outs GPR:$RdLo, GPR:$RdHi),
3493 (ins GPR:$Rn, GPR:$Rm), IIC_iMAC64,
3494 "umlal", "\t$RdLo, $RdHi, $Rn, $Rm", []>,
3495 Requires<[IsARM, HasV6]>;
3497 def UMAAL : AMul1I <0b0000010, (outs GPR:$RdLo, GPR:$RdHi),
3498 (ins GPR:$Rn, GPR:$Rm), IIC_iMAC64,
3499 "umaal", "\t$RdLo, $RdHi, $Rn, $Rm", []>,
3500 Requires<[IsARM, HasV6]> {
3505 let Inst{19-16} = RdHi;
3506 let Inst{15-12} = RdLo;
3507 let Inst{11-8} = Rm;
3511 let Constraints = "@earlyclobber $RdLo,@earlyclobber $RdHi" in {
3512 def SMLALv5 : ARMPseudoExpand<(outs GPR:$RdLo, GPR:$RdHi),
3513 (ins GPR:$Rn, GPR:$Rm, pred:$p, cc_out:$s),
3515 (SMLAL GPR:$RdLo, GPR:$RdHi, GPR:$Rn, GPR:$Rm, pred:$p, cc_out:$s)>,
3516 Requires<[IsARM, NoV6]>;
3517 def UMLALv5 : ARMPseudoExpand<(outs GPR:$RdLo, GPR:$RdHi),
3518 (ins GPR:$Rn, GPR:$Rm, pred:$p, cc_out:$s),
3520 (UMLAL GPR:$RdLo, GPR:$RdHi, GPR:$Rn, GPR:$Rm, pred:$p, cc_out:$s)>,
3521 Requires<[IsARM, NoV6]>;
3522 def UMAALv5 : ARMPseudoExpand<(outs GPR:$RdLo, GPR:$RdHi),
3523 (ins GPR:$Rn, GPR:$Rm, pred:$p),
3525 (UMAAL GPR:$RdLo, GPR:$RdHi, GPR:$Rn, GPR:$Rm, pred:$p)>,
3526 Requires<[IsARM, NoV6]>;
3529 } // neverHasSideEffects
3531 // Most significant word multiply
3532 def SMMUL : AMul2I <0b0111010, 0b0001, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm),
3533 IIC_iMUL32, "smmul", "\t$Rd, $Rn, $Rm",
3534 [(set GPR:$Rd, (mulhs GPR:$Rn, GPR:$Rm))]>,
3535 Requires<[IsARM, HasV6]> {
3536 let Inst{15-12} = 0b1111;
3539 def SMMULR : AMul2I <0b0111010, 0b0011, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm),
3540 IIC_iMUL32, "smmulr", "\t$Rd, $Rn, $Rm", []>,
3541 Requires<[IsARM, HasV6]> {
3542 let Inst{15-12} = 0b1111;
3545 def SMMLA : AMul2Ia <0b0111010, 0b0001, (outs GPR:$Rd),
3546 (ins GPR:$Rn, GPR:$Rm, GPR:$Ra),
3547 IIC_iMAC32, "smmla", "\t$Rd, $Rn, $Rm, $Ra",
3548 [(set GPR:$Rd, (add (mulhs GPR:$Rn, GPR:$Rm), GPR:$Ra))]>,
3549 Requires<[IsARM, HasV6]>;
3551 def SMMLAR : AMul2Ia <0b0111010, 0b0011, (outs GPR:$Rd),
3552 (ins GPR:$Rn, GPR:$Rm, GPR:$Ra),
3553 IIC_iMAC32, "smmlar", "\t$Rd, $Rn, $Rm, $Ra", []>,
3554 Requires<[IsARM, HasV6]>;
3556 def SMMLS : AMul2Ia <0b0111010, 0b1101, (outs GPR:$Rd),
3557 (ins GPR:$Rn, GPR:$Rm, GPR:$Ra),
3558 IIC_iMAC32, "smmls", "\t$Rd, $Rn, $Rm, $Ra", []>,
3559 Requires<[IsARM, HasV6]>;
3561 def SMMLSR : AMul2Ia <0b0111010, 0b1111, (outs GPR:$Rd),
3562 (ins GPR:$Rn, GPR:$Rm, GPR:$Ra),
3563 IIC_iMAC32, "smmlsr", "\t$Rd, $Rn, $Rm, $Ra", []>,
3564 Requires<[IsARM, HasV6]>;
3566 multiclass AI_smul<string opc, PatFrag opnode> {
3567 def BB : AMulxyI<0b0001011, 0b00, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm),
3568 IIC_iMUL16, !strconcat(opc, "bb"), "\t$Rd, $Rn, $Rm",
3569 [(set GPR:$Rd, (opnode (sext_inreg GPR:$Rn, i16),
3570 (sext_inreg GPR:$Rm, i16)))]>,
3571 Requires<[IsARM, HasV5TE]>;
3573 def BT : AMulxyI<0b0001011, 0b10, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm),
3574 IIC_iMUL16, !strconcat(opc, "bt"), "\t$Rd, $Rn, $Rm",
3575 [(set GPR:$Rd, (opnode (sext_inreg GPR:$Rn, i16),
3576 (sra GPR:$Rm, (i32 16))))]>,
3577 Requires<[IsARM, HasV5TE]>;
3579 def TB : AMulxyI<0b0001011, 0b01, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm),
3580 IIC_iMUL16, !strconcat(opc, "tb"), "\t$Rd, $Rn, $Rm",
3581 [(set GPR:$Rd, (opnode (sra GPR:$Rn, (i32 16)),
3582 (sext_inreg GPR:$Rm, i16)))]>,
3583 Requires<[IsARM, HasV5TE]>;
3585 def TT : AMulxyI<0b0001011, 0b11, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm),
3586 IIC_iMUL16, !strconcat(opc, "tt"), "\t$Rd, $Rn, $Rm",
3587 [(set GPR:$Rd, (opnode (sra GPR:$Rn, (i32 16)),
3588 (sra GPR:$Rm, (i32 16))))]>,
3589 Requires<[IsARM, HasV5TE]>;
3591 def WB : AMulxyI<0b0001001, 0b01, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm),
3592 IIC_iMUL16, !strconcat(opc, "wb"), "\t$Rd, $Rn, $Rm",
3593 [(set GPR:$Rd, (sra (opnode GPR:$Rn,
3594 (sext_inreg GPR:$Rm, i16)), (i32 16)))]>,
3595 Requires<[IsARM, HasV5TE]>;
3597 def WT : AMulxyI<0b0001001, 0b11, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm),
3598 IIC_iMUL16, !strconcat(opc, "wt"), "\t$Rd, $Rn, $Rm",
3599 [(set GPR:$Rd, (sra (opnode GPR:$Rn,
3600 (sra GPR:$Rm, (i32 16))), (i32 16)))]>,
3601 Requires<[IsARM, HasV5TE]>;
3605 multiclass AI_smla<string opc, PatFrag opnode> {
3606 let DecoderMethod = "DecodeSMLAInstruction" in {
3607 def BB : AMulxyIa<0b0001000, 0b00, (outs GPRnopc:$Rd),
3608 (ins GPRnopc:$Rn, GPRnopc:$Rm, GPR:$Ra),
3609 IIC_iMAC16, !strconcat(opc, "bb"), "\t$Rd, $Rn, $Rm, $Ra",
3610 [(set GPRnopc:$Rd, (add GPR:$Ra,
3611 (opnode (sext_inreg GPRnopc:$Rn, i16),
3612 (sext_inreg GPRnopc:$Rm, i16))))]>,
3613 Requires<[IsARM, HasV5TE]>;
3615 def BT : AMulxyIa<0b0001000, 0b10, (outs GPRnopc:$Rd),
3616 (ins GPRnopc:$Rn, GPRnopc:$Rm, GPR:$Ra),
3617 IIC_iMAC16, !strconcat(opc, "bt"), "\t$Rd, $Rn, $Rm, $Ra",
3619 (add GPR:$Ra, (opnode (sext_inreg GPRnopc:$Rn, i16),
3620 (sra GPRnopc:$Rm, (i32 16)))))]>,
3621 Requires<[IsARM, HasV5TE]>;
3623 def TB : AMulxyIa<0b0001000, 0b01, (outs GPRnopc:$Rd),
3624 (ins GPRnopc:$Rn, GPRnopc:$Rm, GPR:$Ra),
3625 IIC_iMAC16, !strconcat(opc, "tb"), "\t$Rd, $Rn, $Rm, $Ra",
3627 (add GPR:$Ra, (opnode (sra GPRnopc:$Rn, (i32 16)),
3628 (sext_inreg GPRnopc:$Rm, i16))))]>,
3629 Requires<[IsARM, HasV5TE]>;
3631 def TT : AMulxyIa<0b0001000, 0b11, (outs GPRnopc:$Rd),
3632 (ins GPRnopc:$Rn, GPRnopc:$Rm, GPR:$Ra),
3633 IIC_iMAC16, !strconcat(opc, "tt"), "\t$Rd, $Rn, $Rm, $Ra",
3635 (add GPR:$Ra, (opnode (sra GPRnopc:$Rn, (i32 16)),
3636 (sra GPRnopc:$Rm, (i32 16)))))]>,
3637 Requires<[IsARM, HasV5TE]>;
3639 def WB : AMulxyIa<0b0001001, 0b00, (outs GPRnopc:$Rd),
3640 (ins GPRnopc:$Rn, GPRnopc:$Rm, GPR:$Ra),
3641 IIC_iMAC16, !strconcat(opc, "wb"), "\t$Rd, $Rn, $Rm, $Ra",
3643 (add GPR:$Ra, (sra (opnode GPRnopc:$Rn,
3644 (sext_inreg GPRnopc:$Rm, i16)), (i32 16))))]>,
3645 Requires<[IsARM, HasV5TE]>;
3647 def WT : AMulxyIa<0b0001001, 0b10, (outs GPRnopc:$Rd),
3648 (ins GPRnopc:$Rn, GPRnopc:$Rm, GPR:$Ra),
3649 IIC_iMAC16, !strconcat(opc, "wt"), "\t$Rd, $Rn, $Rm, $Ra",
3651 (add GPR:$Ra, (sra (opnode GPRnopc:$Rn,
3652 (sra GPRnopc:$Rm, (i32 16))), (i32 16))))]>,
3653 Requires<[IsARM, HasV5TE]>;
3657 defm SMUL : AI_smul<"smul", BinOpFrag<(mul node:$LHS, node:$RHS)>>;
3658 defm SMLA : AI_smla<"smla", BinOpFrag<(mul node:$LHS, node:$RHS)>>;
3660 // Halfword multiply accumulate long: SMLAL<x><y>.
3661 def SMLALBB : AMulxyI64<0b0001010, 0b00, (outs GPRnopc:$RdLo, GPRnopc:$RdHi),
3662 (ins GPRnopc:$Rn, GPRnopc:$Rm),
3663 IIC_iMAC64, "smlalbb", "\t$RdLo, $RdHi, $Rn, $Rm", []>,
3664 Requires<[IsARM, HasV5TE]>;
3666 def SMLALBT : AMulxyI64<0b0001010, 0b10, (outs GPRnopc:$RdLo, GPRnopc:$RdHi),
3667 (ins GPRnopc:$Rn, GPRnopc:$Rm),
3668 IIC_iMAC64, "smlalbt", "\t$RdLo, $RdHi, $Rn, $Rm", []>,
3669 Requires<[IsARM, HasV5TE]>;
3671 def SMLALTB : AMulxyI64<0b0001010, 0b01, (outs GPRnopc:$RdLo, GPRnopc:$RdHi),
3672 (ins GPRnopc:$Rn, GPRnopc:$Rm),
3673 IIC_iMAC64, "smlaltb", "\t$RdLo, $RdHi, $Rn, $Rm", []>,
3674 Requires<[IsARM, HasV5TE]>;
3676 def SMLALTT : AMulxyI64<0b0001010, 0b11, (outs GPRnopc:$RdLo, GPRnopc:$RdHi),
3677 (ins GPRnopc:$Rn, GPRnopc:$Rm),
3678 IIC_iMAC64, "smlaltt", "\t$RdLo, $RdHi, $Rn, $Rm", []>,
3679 Requires<[IsARM, HasV5TE]>;
3681 // Helper class for AI_smld.
3682 class AMulDualIbase<bit long, bit sub, bit swap, dag oops, dag iops,
3683 InstrItinClass itin, string opc, string asm>
3684 : AI<oops, iops, MulFrm, itin, opc, asm, []>, Requires<[IsARM, HasV6]> {
3687 let Inst{27-23} = 0b01110;
3688 let Inst{22} = long;
3689 let Inst{21-20} = 0b00;
3690 let Inst{11-8} = Rm;
3697 class AMulDualI<bit long, bit sub, bit swap, dag oops, dag iops,
3698 InstrItinClass itin, string opc, string asm>
3699 : AMulDualIbase<long, sub, swap, oops, iops, itin, opc, asm> {
3701 let Inst{15-12} = 0b1111;
3702 let Inst{19-16} = Rd;
3704 class AMulDualIa<bit long, bit sub, bit swap, dag oops, dag iops,
3705 InstrItinClass itin, string opc, string asm>
3706 : AMulDualIbase<long, sub, swap, oops, iops, itin, opc, asm> {
3709 let Inst{19-16} = Rd;
3710 let Inst{15-12} = Ra;
3712 class AMulDualI64<bit long, bit sub, bit swap, dag oops, dag iops,
3713 InstrItinClass itin, string opc, string asm>
3714 : AMulDualIbase<long, sub, swap, oops, iops, itin, opc, asm> {
3717 let Inst{19-16} = RdHi;
3718 let Inst{15-12} = RdLo;
3721 multiclass AI_smld<bit sub, string opc> {
3723 def D : AMulDualIa<0, sub, 0, (outs GPRnopc:$Rd),
3724 (ins GPRnopc:$Rn, GPRnopc:$Rm, GPR:$Ra),
3725 NoItinerary, !strconcat(opc, "d"), "\t$Rd, $Rn, $Rm, $Ra">;
3727 def DX: AMulDualIa<0, sub, 1, (outs GPRnopc:$Rd),
3728 (ins GPRnopc:$Rn, GPRnopc:$Rm, GPR:$Ra),
3729 NoItinerary, !strconcat(opc, "dx"), "\t$Rd, $Rn, $Rm, $Ra">;
3731 def LD: AMulDualI64<1, sub, 0, (outs GPRnopc:$RdLo, GPRnopc:$RdHi),
3732 (ins GPRnopc:$Rn, GPRnopc:$Rm), NoItinerary,
3733 !strconcat(opc, "ld"), "\t$RdLo, $RdHi, $Rn, $Rm">;
3735 def LDX : AMulDualI64<1, sub, 1, (outs GPRnopc:$RdLo, GPRnopc:$RdHi),
3736 (ins GPRnopc:$Rn, GPRnopc:$Rm), NoItinerary,
3737 !strconcat(opc, "ldx"),"\t$RdLo, $RdHi, $Rn, $Rm">;
3741 defm SMLA : AI_smld<0, "smla">;
3742 defm SMLS : AI_smld<1, "smls">;
3744 multiclass AI_sdml<bit sub, string opc> {
3746 def D:AMulDualI<0, sub, 0, (outs GPRnopc:$Rd), (ins GPRnopc:$Rn, GPRnopc:$Rm),
3747 NoItinerary, !strconcat(opc, "d"), "\t$Rd, $Rn, $Rm">;
3748 def DX:AMulDualI<0, sub, 1, (outs GPRnopc:$Rd),(ins GPRnopc:$Rn, GPRnopc:$Rm),
3749 NoItinerary, !strconcat(opc, "dx"), "\t$Rd, $Rn, $Rm">;
3752 defm SMUA : AI_sdml<0, "smua">;
3753 defm SMUS : AI_sdml<1, "smus">;
3755 //===----------------------------------------------------------------------===//
3756 // Misc. Arithmetic Instructions.
3759 def CLZ : AMiscA1I<0b000010110, 0b0001, (outs GPR:$Rd), (ins GPR:$Rm),
3760 IIC_iUNAr, "clz", "\t$Rd, $Rm",
3761 [(set GPR:$Rd, (ctlz GPR:$Rm))]>, Requires<[IsARM, HasV5T]>;
3763 def RBIT : AMiscA1I<0b01101111, 0b0011, (outs GPR:$Rd), (ins GPR:$Rm),
3764 IIC_iUNAr, "rbit", "\t$Rd, $Rm",
3765 [(set GPR:$Rd, (ARMrbit GPR:$Rm))]>,
3766 Requires<[IsARM, HasV6T2]>;
3768 def REV : AMiscA1I<0b01101011, 0b0011, (outs GPR:$Rd), (ins GPR:$Rm),
3769 IIC_iUNAr, "rev", "\t$Rd, $Rm",
3770 [(set GPR:$Rd, (bswap GPR:$Rm))]>, Requires<[IsARM, HasV6]>;
3772 let AddedComplexity = 5 in
3773 def REV16 : AMiscA1I<0b01101011, 0b1011, (outs GPR:$Rd), (ins GPR:$Rm),
3774 IIC_iUNAr, "rev16", "\t$Rd, $Rm",
3775 [(set GPR:$Rd, (rotr (bswap GPR:$Rm), (i32 16)))]>,
3776 Requires<[IsARM, HasV6]>;
3778 let AddedComplexity = 5 in
3779 def REVSH : AMiscA1I<0b01101111, 0b1011, (outs GPR:$Rd), (ins GPR:$Rm),
3780 IIC_iUNAr, "revsh", "\t$Rd, $Rm",
3781 [(set GPR:$Rd, (sra (bswap GPR:$Rm), (i32 16)))]>,
3782 Requires<[IsARM, HasV6]>;
3784 def : ARMV6Pat<(or (sra (shl GPR:$Rm, (i32 24)), (i32 16)),
3785 (and (srl GPR:$Rm, (i32 8)), 0xFF)),
3788 def PKHBT : APKHI<0b01101000, 0, (outs GPRnopc:$Rd),
3789 (ins GPRnopc:$Rn, GPRnopc:$Rm, pkh_lsl_amt:$sh),
3790 IIC_iALUsi, "pkhbt", "\t$Rd, $Rn, $Rm$sh",
3791 [(set GPRnopc:$Rd, (or (and GPRnopc:$Rn, 0xFFFF),
3792 (and (shl GPRnopc:$Rm, pkh_lsl_amt:$sh),
3794 Requires<[IsARM, HasV6]>;
3796 // Alternate cases for PKHBT where identities eliminate some nodes.
3797 def : ARMV6Pat<(or (and GPRnopc:$Rn, 0xFFFF), (and GPRnopc:$Rm, 0xFFFF0000)),
3798 (PKHBT GPRnopc:$Rn, GPRnopc:$Rm, 0)>;
3799 def : ARMV6Pat<(or (and GPRnopc:$Rn, 0xFFFF), (shl GPRnopc:$Rm, imm16_31:$sh)),
3800 (PKHBT GPRnopc:$Rn, GPRnopc:$Rm, imm16_31:$sh)>;
3802 // Note: Shifts of 1-15 bits will be transformed to srl instead of sra and
3803 // will match the pattern below.
3804 def PKHTB : APKHI<0b01101000, 1, (outs GPRnopc:$Rd),
3805 (ins GPRnopc:$Rn, GPRnopc:$Rm, pkh_asr_amt:$sh),
3806 IIC_iBITsi, "pkhtb", "\t$Rd, $Rn, $Rm$sh",
3807 [(set GPRnopc:$Rd, (or (and GPRnopc:$Rn, 0xFFFF0000),
3808 (and (sra GPRnopc:$Rm, pkh_asr_amt:$sh),
3810 Requires<[IsARM, HasV6]>;
3812 // Alternate cases for PKHTB where identities eliminate some nodes. Note that
3813 // a shift amount of 0 is *not legal* here, it is PKHBT instead.
3814 def : ARMV6Pat<(or (and GPRnopc:$src1, 0xFFFF0000),
3815 (srl GPRnopc:$src2, imm16_31:$sh)),
3816 (PKHTB GPRnopc:$src1, GPRnopc:$src2, imm16_31:$sh)>;
3817 def : ARMV6Pat<(or (and GPRnopc:$src1, 0xFFFF0000),
3818 (and (srl GPRnopc:$src2, imm1_15:$sh), 0xFFFF)),
3819 (PKHTB GPRnopc:$src1, GPRnopc:$src2, imm1_15:$sh)>;
3821 //===----------------------------------------------------------------------===//
3822 // Comparison Instructions...
3825 defm CMP : AI1_cmp_irs<0b1010, "cmp",
3826 IIC_iCMPi, IIC_iCMPr, IIC_iCMPsr,
3827 BinOpFrag<(ARMcmp node:$LHS, node:$RHS)>>;
3829 // ARMcmpZ can re-use the above instruction definitions.
3830 def : ARMPat<(ARMcmpZ GPR:$src, so_imm:$imm),
3831 (CMPri GPR:$src, so_imm:$imm)>;
3832 def : ARMPat<(ARMcmpZ GPR:$src, GPR:$rhs),
3833 (CMPrr GPR:$src, GPR:$rhs)>;
3834 def : ARMPat<(ARMcmpZ GPR:$src, so_reg_imm:$rhs),
3835 (CMPrsi GPR:$src, so_reg_imm:$rhs)>;
3836 def : ARMPat<(ARMcmpZ GPR:$src, so_reg_reg:$rhs),
3837 (CMPrsr GPR:$src, so_reg_reg:$rhs)>;
3839 // CMN register-integer
3840 let isCompare = 1, Defs = [CPSR] in {
3841 def CMNri : AI1<0b1011, (outs), (ins GPR:$Rn, so_imm:$imm), DPFrm, IIC_iCMPi,
3842 "cmn", "\t$Rn, $imm",
3843 [(ARMcmn GPR:$Rn, so_imm:$imm)]> {
3848 let Inst{19-16} = Rn;
3849 let Inst{15-12} = 0b0000;
3850 let Inst{11-0} = imm;
3852 let Unpredictable{15-12} = 0b1111;
3855 // CMN register-register/shift
3856 def CMNzrr : AI1<0b1011, (outs), (ins GPR:$Rn, GPR:$Rm), DPFrm, IIC_iCMPr,
3857 "cmn", "\t$Rn, $Rm",
3858 [(BinOpFrag<(ARMcmpZ node:$LHS,(ineg node:$RHS))>
3859 GPR:$Rn, GPR:$Rm)]> {
3862 let isCommutable = 1;
3865 let Inst{19-16} = Rn;
3866 let Inst{15-12} = 0b0000;
3867 let Inst{11-4} = 0b00000000;
3870 let Unpredictable{15-12} = 0b1111;
3873 def CMNzrsi : AI1<0b1011, (outs),
3874 (ins GPR:$Rn, so_reg_imm:$shift), DPSoRegImmFrm, IIC_iCMPsr,
3875 "cmn", "\t$Rn, $shift",
3876 [(BinOpFrag<(ARMcmpZ node:$LHS,(ineg node:$RHS))>
3877 GPR:$Rn, so_reg_imm:$shift)]> {
3882 let Inst{19-16} = Rn;
3883 let Inst{15-12} = 0b0000;
3884 let Inst{11-5} = shift{11-5};
3886 let Inst{3-0} = shift{3-0};
3888 let Unpredictable{15-12} = 0b1111;
3891 def CMNzrsr : AI1<0b1011, (outs),
3892 (ins GPRnopc:$Rn, so_reg_reg:$shift), DPSoRegRegFrm, IIC_iCMPsr,
3893 "cmn", "\t$Rn, $shift",
3894 [(BinOpFrag<(ARMcmpZ node:$LHS,(ineg node:$RHS))>
3895 GPRnopc:$Rn, so_reg_reg:$shift)]> {
3900 let Inst{19-16} = Rn;
3901 let Inst{15-12} = 0b0000;
3902 let Inst{11-8} = shift{11-8};
3904 let Inst{6-5} = shift{6-5};
3906 let Inst{3-0} = shift{3-0};
3908 let Unpredictable{15-12} = 0b1111;
3913 def : ARMPat<(ARMcmp GPR:$src, so_imm_neg:$imm),
3914 (CMNri GPR:$src, so_imm_neg:$imm)>;
3916 def : ARMPat<(ARMcmpZ GPR:$src, so_imm_neg:$imm),
3917 (CMNri GPR:$src, so_imm_neg:$imm)>;
3919 // Note that TST/TEQ don't set all the same flags that CMP does!
3920 defm TST : AI1_cmp_irs<0b1000, "tst",
3921 IIC_iTSTi, IIC_iTSTr, IIC_iTSTsr,
3922 BinOpFrag<(ARMcmpZ (and_su node:$LHS, node:$RHS), 0)>, 1>;
3923 defm TEQ : AI1_cmp_irs<0b1001, "teq",
3924 IIC_iTSTi, IIC_iTSTr, IIC_iTSTsr,
3925 BinOpFrag<(ARMcmpZ (xor_su node:$LHS, node:$RHS), 0)>, 1>;
3927 // Pseudo i64 compares for some floating point compares.
3928 let usesCustomInserter = 1, isBranch = 1, isTerminator = 1,
3930 def BCCi64 : PseudoInst<(outs),
3931 (ins i32imm:$cc, GPR:$lhs1, GPR:$lhs2, GPR:$rhs1, GPR:$rhs2, brtarget:$dst),
3933 [(ARMBcci64 imm:$cc, GPR:$lhs1, GPR:$lhs2, GPR:$rhs1, GPR:$rhs2, bb:$dst)]>;
3935 def BCCZi64 : PseudoInst<(outs),
3936 (ins i32imm:$cc, GPR:$lhs1, GPR:$lhs2, brtarget:$dst), IIC_Br,
3937 [(ARMBcci64 imm:$cc, GPR:$lhs1, GPR:$lhs2, 0, 0, bb:$dst)]>;
3938 } // usesCustomInserter
3941 // Conditional moves
3942 // FIXME: should be able to write a pattern for ARMcmov, but can't use
3943 // a two-value operand where a dag node expects two operands. :(
3944 let neverHasSideEffects = 1 in {
3946 let isCommutable = 1 in
3947 def MOVCCr : ARMPseudoInst<(outs GPR:$Rd), (ins GPR:$false, GPR:$Rm, pred:$p),
3949 [/*(set GPR:$Rd, (ARMcmov GPR:$false, GPR:$Rm, imm:$cc, CCR:$ccr))*/]>,
3950 RegConstraint<"$false = $Rd">;
3952 def MOVCCsi : ARMPseudoInst<(outs GPR:$Rd),
3953 (ins GPR:$false, so_reg_imm:$shift, pred:$p),
3955 [/*(set GPR:$Rd, (ARMcmov GPR:$false, so_reg_imm:$shift,
3956 imm:$cc, CCR:$ccr))*/]>,
3957 RegConstraint<"$false = $Rd">;
3958 def MOVCCsr : ARMPseudoInst<(outs GPR:$Rd),
3959 (ins GPR:$false, so_reg_reg:$shift, pred:$p),
3961 [/*(set GPR:$Rd, (ARMcmov GPR:$false, so_reg_reg:$shift,
3962 imm:$cc, CCR:$ccr))*/]>,
3963 RegConstraint<"$false = $Rd">;
3966 let isMoveImm = 1 in
3967 def MOVCCi16 : ARMPseudoInst<(outs GPR:$Rd),
3968 (ins GPR:$false, imm0_65535_expr:$imm, pred:$p),
3971 RegConstraint<"$false = $Rd">, Requires<[IsARM, HasV6T2]>;
3973 let isMoveImm = 1 in
3974 def MOVCCi : ARMPseudoInst<(outs GPR:$Rd),
3975 (ins GPR:$false, so_imm:$imm, pred:$p),
3977 [/*(set GPR:$Rd, (ARMcmov GPR:$false, so_imm:$imm, imm:$cc, CCR:$ccr))*/]>,
3978 RegConstraint<"$false = $Rd">;
3980 // Two instruction predicate mov immediate.
3981 let isMoveImm = 1 in
3982 def MOVCCi32imm : ARMPseudoInst<(outs GPR:$Rd),
3983 (ins GPR:$false, i32imm:$src, pred:$p),
3984 8, IIC_iCMOVix2, []>, RegConstraint<"$false = $Rd">;
3986 let isMoveImm = 1 in
3987 def MVNCCi : ARMPseudoInst<(outs GPR:$Rd),
3988 (ins GPR:$false, so_imm:$imm, pred:$p),
3990 [/*(set GPR:$Rd, (ARMcmov GPR:$false, so_imm_not:$imm, imm:$cc, CCR:$ccr))*/]>,
3991 RegConstraint<"$false = $Rd">;
3993 // Conditional instructions
3994 multiclass AsI1_bincc_irs<Instruction iri, Instruction irr, Instruction irsi,
3996 InstrItinClass iii, InstrItinClass iir,
3997 InstrItinClass iis> {
3998 def ri : ARMPseudoExpand<(outs GPR:$Rd),
3999 (ins GPR:$Rn, so_imm:$imm, pred:$p, cc_out:$s),
4001 (iri GPR:$Rd, GPR:$Rn, so_imm:$imm, pred:$p, cc_out:$s)>,
4002 RegConstraint<"$Rn = $Rd">;
4003 def rr : ARMPseudoExpand<(outs GPR:$Rd),
4004 (ins GPR:$Rn, GPR:$Rm, pred:$p, cc_out:$s),
4006 (irr GPR:$Rd, GPR:$Rn, GPR:$Rm, pred:$p, cc_out:$s)>,
4007 RegConstraint<"$Rn = $Rd">;
4008 def rsi : ARMPseudoExpand<(outs GPR:$Rd),
4009 (ins GPR:$Rn, so_reg_imm:$shift, pred:$p, cc_out:$s),
4011 (irsi GPR:$Rd, GPR:$Rn, so_reg_imm:$shift, pred:$p, cc_out:$s)>,
4012 RegConstraint<"$Rn = $Rd">;
4013 def rsr : ARMPseudoExpand<(outs GPRnopc:$Rd),
4014 (ins GPRnopc:$Rn, so_reg_reg:$shift, pred:$p, cc_out:$s),
4016 (irsr GPR:$Rd, GPR:$Rn, so_reg_reg:$shift, pred:$p, cc_out:$s)>,
4017 RegConstraint<"$Rn = $Rd">;
4020 defm ANDCC : AsI1_bincc_irs<ANDri, ANDrr, ANDrsi, ANDrsr,
4021 IIC_iBITi, IIC_iBITr, IIC_iBITsr>;
4022 defm ORRCC : AsI1_bincc_irs<ORRri, ORRrr, ORRrsi, ORRrsr,
4023 IIC_iBITi, IIC_iBITr, IIC_iBITsr>;
4024 defm EORCC : AsI1_bincc_irs<EORri, EORrr, EORrsi, EORrsr,
4025 IIC_iBITi, IIC_iBITr, IIC_iBITsr>;
4027 } // neverHasSideEffects
4030 //===----------------------------------------------------------------------===//
4031 // Atomic operations intrinsics
4034 def MemBarrierOptOperand : AsmOperandClass {
4035 let Name = "MemBarrierOpt";
4036 let ParserMethod = "parseMemBarrierOptOperand";
4038 def memb_opt : Operand<i32> {
4039 let PrintMethod = "printMemBOption";
4040 let ParserMatchClass = MemBarrierOptOperand;
4041 let DecoderMethod = "DecodeMemBarrierOption";
4044 // memory barriers protect the atomic sequences
4045 let hasSideEffects = 1 in {
4046 def DMB : AInoP<(outs), (ins memb_opt:$opt), MiscFrm, NoItinerary,
4047 "dmb", "\t$opt", [(ARMMemBarrier (i32 imm:$opt))]>,
4048 Requires<[IsARM, HasDB]> {
4050 let Inst{31-4} = 0xf57ff05;
4051 let Inst{3-0} = opt;
4055 def DSB : AInoP<(outs), (ins memb_opt:$opt), MiscFrm, NoItinerary,
4056 "dsb", "\t$opt", []>,
4057 Requires<[IsARM, HasDB]> {
4059 let Inst{31-4} = 0xf57ff04;
4060 let Inst{3-0} = opt;
4063 // ISB has only full system option
4064 def ISB : AInoP<(outs), (ins memb_opt:$opt), MiscFrm, NoItinerary,
4065 "isb", "\t$opt", []>,
4066 Requires<[IsARM, HasDB]> {
4068 let Inst{31-4} = 0xf57ff06;
4069 let Inst{3-0} = opt;
4072 // Pseudo instruction that combines movs + predicated rsbmi
4073 // to implement integer ABS
4074 let usesCustomInserter = 1, Defs = [CPSR] in {
4075 def ABS : ARMPseudoInst<
4076 (outs GPR:$dst), (ins GPR:$src),
4077 8, NoItinerary, []>;
4080 let usesCustomInserter = 1 in {
4081 let Defs = [CPSR] in {
4082 def ATOMIC_LOAD_ADD_I8 : PseudoInst<
4083 (outs GPR:$dst), (ins GPR:$ptr, GPR:$incr), NoItinerary,
4084 [(set GPR:$dst, (atomic_load_add_8 GPR:$ptr, GPR:$incr))]>;
4085 def ATOMIC_LOAD_SUB_I8 : PseudoInst<
4086 (outs GPR:$dst), (ins GPR:$ptr, GPR:$incr), NoItinerary,
4087 [(set GPR:$dst, (atomic_load_sub_8 GPR:$ptr, GPR:$incr))]>;
4088 def ATOMIC_LOAD_AND_I8 : PseudoInst<
4089 (outs GPR:$dst), (ins GPR:$ptr, GPR:$incr), NoItinerary,
4090 [(set GPR:$dst, (atomic_load_and_8 GPR:$ptr, GPR:$incr))]>;
4091 def ATOMIC_LOAD_OR_I8 : PseudoInst<
4092 (outs GPR:$dst), (ins GPR:$ptr, GPR:$incr), NoItinerary,
4093 [(set GPR:$dst, (atomic_load_or_8 GPR:$ptr, GPR:$incr))]>;
4094 def ATOMIC_LOAD_XOR_I8 : PseudoInst<
4095 (outs GPR:$dst), (ins GPR:$ptr, GPR:$incr), NoItinerary,
4096 [(set GPR:$dst, (atomic_load_xor_8 GPR:$ptr, GPR:$incr))]>;
4097 def ATOMIC_LOAD_NAND_I8 : PseudoInst<
4098 (outs GPR:$dst), (ins GPR:$ptr, GPR:$incr), NoItinerary,
4099 [(set GPR:$dst, (atomic_load_nand_8 GPR:$ptr, GPR:$incr))]>;
4100 def ATOMIC_LOAD_MIN_I8 : PseudoInst<
4101 (outs GPR:$dst), (ins GPR:$ptr, GPR:$val), NoItinerary,
4102 [(set GPR:$dst, (atomic_load_min_8 GPR:$ptr, GPR:$val))]>;
4103 def ATOMIC_LOAD_MAX_I8 : PseudoInst<
4104 (outs GPR:$dst), (ins GPR:$ptr, GPR:$val), NoItinerary,
4105 [(set GPR:$dst, (atomic_load_max_8 GPR:$ptr, GPR:$val))]>;
4106 def ATOMIC_LOAD_UMIN_I8 : PseudoInst<
4107 (outs GPR:$dst), (ins GPR:$ptr, GPR:$val), NoItinerary,
4108 [(set GPR:$dst, (atomic_load_umin_8 GPR:$ptr, GPR:$val))]>;
4109 def ATOMIC_LOAD_UMAX_I8 : PseudoInst<
4110 (outs GPR:$dst), (ins GPR:$ptr, GPR:$val), NoItinerary,
4111 [(set GPR:$dst, (atomic_load_umax_8 GPR:$ptr, GPR:$val))]>;
4112 def ATOMIC_LOAD_ADD_I16 : PseudoInst<
4113 (outs GPR:$dst), (ins GPR:$ptr, GPR:$incr), NoItinerary,
4114 [(set GPR:$dst, (atomic_load_add_16 GPR:$ptr, GPR:$incr))]>;
4115 def ATOMIC_LOAD_SUB_I16 : PseudoInst<
4116 (outs GPR:$dst), (ins GPR:$ptr, GPR:$incr), NoItinerary,
4117 [(set GPR:$dst, (atomic_load_sub_16 GPR:$ptr, GPR:$incr))]>;
4118 def ATOMIC_LOAD_AND_I16 : PseudoInst<
4119 (outs GPR:$dst), (ins GPR:$ptr, GPR:$incr), NoItinerary,
4120 [(set GPR:$dst, (atomic_load_and_16 GPR:$ptr, GPR:$incr))]>;
4121 def ATOMIC_LOAD_OR_I16 : PseudoInst<
4122 (outs GPR:$dst), (ins GPR:$ptr, GPR:$incr), NoItinerary,
4123 [(set GPR:$dst, (atomic_load_or_16 GPR:$ptr, GPR:$incr))]>;
4124 def ATOMIC_LOAD_XOR_I16 : PseudoInst<
4125 (outs GPR:$dst), (ins GPR:$ptr, GPR:$incr), NoItinerary,
4126 [(set GPR:$dst, (atomic_load_xor_16 GPR:$ptr, GPR:$incr))]>;
4127 def ATOMIC_LOAD_NAND_I16 : PseudoInst<
4128 (outs GPR:$dst), (ins GPR:$ptr, GPR:$incr), NoItinerary,
4129 [(set GPR:$dst, (atomic_load_nand_16 GPR:$ptr, GPR:$incr))]>;
4130 def ATOMIC_LOAD_MIN_I16 : PseudoInst<
4131 (outs GPR:$dst), (ins GPR:$ptr, GPR:$val), NoItinerary,
4132 [(set GPR:$dst, (atomic_load_min_16 GPR:$ptr, GPR:$val))]>;
4133 def ATOMIC_LOAD_MAX_I16 : PseudoInst<
4134 (outs GPR:$dst), (ins GPR:$ptr, GPR:$val), NoItinerary,
4135 [(set GPR:$dst, (atomic_load_max_16 GPR:$ptr, GPR:$val))]>;
4136 def ATOMIC_LOAD_UMIN_I16 : PseudoInst<
4137 (outs GPR:$dst), (ins GPR:$ptr, GPR:$val), NoItinerary,
4138 [(set GPR:$dst, (atomic_load_umin_16 GPR:$ptr, GPR:$val))]>;
4139 def ATOMIC_LOAD_UMAX_I16 : PseudoInst<
4140 (outs GPR:$dst), (ins GPR:$ptr, GPR:$val), NoItinerary,
4141 [(set GPR:$dst, (atomic_load_umax_16 GPR:$ptr, GPR:$val))]>;
4142 def ATOMIC_LOAD_ADD_I32 : PseudoInst<
4143 (outs GPR:$dst), (ins GPR:$ptr, GPR:$incr), NoItinerary,
4144 [(set GPR:$dst, (atomic_load_add_32 GPR:$ptr, GPR:$incr))]>;
4145 def ATOMIC_LOAD_SUB_I32 : PseudoInst<
4146 (outs GPR:$dst), (ins GPR:$ptr, GPR:$incr), NoItinerary,
4147 [(set GPR:$dst, (atomic_load_sub_32 GPR:$ptr, GPR:$incr))]>;
4148 def ATOMIC_LOAD_AND_I32 : PseudoInst<
4149 (outs GPR:$dst), (ins GPR:$ptr, GPR:$incr), NoItinerary,
4150 [(set GPR:$dst, (atomic_load_and_32 GPR:$ptr, GPR:$incr))]>;
4151 def ATOMIC_LOAD_OR_I32 : PseudoInst<
4152 (outs GPR:$dst), (ins GPR:$ptr, GPR:$incr), NoItinerary,
4153 [(set GPR:$dst, (atomic_load_or_32 GPR:$ptr, GPR:$incr))]>;
4154 def ATOMIC_LOAD_XOR_I32 : PseudoInst<
4155 (outs GPR:$dst), (ins GPR:$ptr, GPR:$incr), NoItinerary,
4156 [(set GPR:$dst, (atomic_load_xor_32 GPR:$ptr, GPR:$incr))]>;
4157 def ATOMIC_LOAD_NAND_I32 : PseudoInst<
4158 (outs GPR:$dst), (ins GPR:$ptr, GPR:$incr), NoItinerary,
4159 [(set GPR:$dst, (atomic_load_nand_32 GPR:$ptr, GPR:$incr))]>;
4160 def ATOMIC_LOAD_MIN_I32 : PseudoInst<
4161 (outs GPR:$dst), (ins GPR:$ptr, GPR:$val), NoItinerary,
4162 [(set GPR:$dst, (atomic_load_min_32 GPR:$ptr, GPR:$val))]>;
4163 def ATOMIC_LOAD_MAX_I32 : PseudoInst<
4164 (outs GPR:$dst), (ins GPR:$ptr, GPR:$val), NoItinerary,
4165 [(set GPR:$dst, (atomic_load_max_32 GPR:$ptr, GPR:$val))]>;
4166 def ATOMIC_LOAD_UMIN_I32 : PseudoInst<
4167 (outs GPR:$dst), (ins GPR:$ptr, GPR:$val), NoItinerary,
4168 [(set GPR:$dst, (atomic_load_umin_32 GPR:$ptr, GPR:$val))]>;
4169 def ATOMIC_LOAD_UMAX_I32 : PseudoInst<
4170 (outs GPR:$dst), (ins GPR:$ptr, GPR:$val), NoItinerary,
4171 [(set GPR:$dst, (atomic_load_umax_32 GPR:$ptr, GPR:$val))]>;
4173 def ATOMIC_SWAP_I8 : PseudoInst<
4174 (outs GPR:$dst), (ins GPR:$ptr, GPR:$new), NoItinerary,
4175 [(set GPR:$dst, (atomic_swap_8 GPR:$ptr, GPR:$new))]>;
4176 def ATOMIC_SWAP_I16 : PseudoInst<
4177 (outs GPR:$dst), (ins GPR:$ptr, GPR:$new), NoItinerary,
4178 [(set GPR:$dst, (atomic_swap_16 GPR:$ptr, GPR:$new))]>;
4179 def ATOMIC_SWAP_I32 : PseudoInst<
4180 (outs GPR:$dst), (ins GPR:$ptr, GPR:$new), NoItinerary,
4181 [(set GPR:$dst, (atomic_swap_32 GPR:$ptr, GPR:$new))]>;
4183 def ATOMIC_CMP_SWAP_I8 : PseudoInst<
4184 (outs GPR:$dst), (ins GPR:$ptr, GPR:$old, GPR:$new), NoItinerary,
4185 [(set GPR:$dst, (atomic_cmp_swap_8 GPR:$ptr, GPR:$old, GPR:$new))]>;
4186 def ATOMIC_CMP_SWAP_I16 : PseudoInst<
4187 (outs GPR:$dst), (ins GPR:$ptr, GPR:$old, GPR:$new), NoItinerary,
4188 [(set GPR:$dst, (atomic_cmp_swap_16 GPR:$ptr, GPR:$old, GPR:$new))]>;
4189 def ATOMIC_CMP_SWAP_I32 : PseudoInst<
4190 (outs GPR:$dst), (ins GPR:$ptr, GPR:$old, GPR:$new), NoItinerary,
4191 [(set GPR:$dst, (atomic_cmp_swap_32 GPR:$ptr, GPR:$old, GPR:$new))]>;
4195 let usesCustomInserter = 1 in {
4196 def COPY_STRUCT_BYVAL_I32 : PseudoInst<
4197 (outs), (ins GPR:$dst, GPR:$src, i32imm:$size, i32imm:$alignment),
4199 [(ARMcopystructbyval GPR:$dst, GPR:$src, imm:$size, imm:$alignment)]>;
4202 let mayLoad = 1 in {
4203 def LDREXB : AIldrex<0b10, (outs GPR:$Rt), (ins addr_offset_none:$addr),
4205 "ldrexb", "\t$Rt, $addr", []>;
4206 def LDREXH : AIldrex<0b11, (outs GPR:$Rt), (ins addr_offset_none:$addr),
4207 NoItinerary, "ldrexh", "\t$Rt, $addr", []>;
4208 def LDREX : AIldrex<0b00, (outs GPR:$Rt), (ins addr_offset_none:$addr),
4209 NoItinerary, "ldrex", "\t$Rt, $addr", []>;
4210 let hasExtraDefRegAllocReq = 1 in
4211 def LDREXD: AIldrex<0b01, (outs GPR:$Rt, GPR:$Rt2),(ins addr_offset_none:$addr),
4212 NoItinerary, "ldrexd", "\t$Rt, $Rt2, $addr", []> {
4213 let DecoderMethod = "DecodeDoubleRegLoad";
4217 let mayStore = 1, Constraints = "@earlyclobber $Rd" in {
4218 def STREXB: AIstrex<0b10, (outs GPR:$Rd), (ins GPR:$Rt, addr_offset_none:$addr),
4219 NoItinerary, "strexb", "\t$Rd, $Rt, $addr", []>;
4220 def STREXH: AIstrex<0b11, (outs GPR:$Rd), (ins GPR:$Rt, addr_offset_none:$addr),
4221 NoItinerary, "strexh", "\t$Rd, $Rt, $addr", []>;
4222 def STREX : AIstrex<0b00, (outs GPR:$Rd), (ins GPR:$Rt, addr_offset_none:$addr),
4223 NoItinerary, "strex", "\t$Rd, $Rt, $addr", []>;
4224 let hasExtraSrcRegAllocReq = 1 in
4225 def STREXD : AIstrex<0b01, (outs GPR:$Rd),
4226 (ins GPR:$Rt, GPR:$Rt2, addr_offset_none:$addr),
4227 NoItinerary, "strexd", "\t$Rd, $Rt, $Rt2, $addr", []> {
4228 let DecoderMethod = "DecodeDoubleRegStore";
4233 def CLREX : AXI<(outs), (ins), MiscFrm, NoItinerary, "clrex", []>,
4234 Requires<[IsARM, HasV7]> {
4235 let Inst{31-0} = 0b11110101011111111111000000011111;
4238 // SWP/SWPB are deprecated in V6/V7.
4239 let mayLoad = 1, mayStore = 1 in {
4240 def SWP : AIswp<0, (outs GPRnopc:$Rt),
4241 (ins GPRnopc:$Rt2, addr_offset_none:$addr), "swp", []>;
4242 def SWPB: AIswp<1, (outs GPRnopc:$Rt),
4243 (ins GPRnopc:$Rt2, addr_offset_none:$addr), "swpb", []>;
4246 //===----------------------------------------------------------------------===//
4247 // Coprocessor Instructions.
4250 def CDP : ABI<0b1110, (outs), (ins p_imm:$cop, imm0_15:$opc1,
4251 c_imm:$CRd, c_imm:$CRn, c_imm:$CRm, imm0_7:$opc2),
4252 NoItinerary, "cdp", "\t$cop, $opc1, $CRd, $CRn, $CRm, $opc2",
4253 [(int_arm_cdp imm:$cop, imm:$opc1, imm:$CRd, imm:$CRn,
4254 imm:$CRm, imm:$opc2)]> {
4262 let Inst{3-0} = CRm;
4264 let Inst{7-5} = opc2;
4265 let Inst{11-8} = cop;
4266 let Inst{15-12} = CRd;
4267 let Inst{19-16} = CRn;
4268 let Inst{23-20} = opc1;
4271 def CDP2 : ABXI<0b1110, (outs), (ins pf_imm:$cop, imm0_15:$opc1,
4272 c_imm:$CRd, c_imm:$CRn, c_imm:$CRm, imm0_7:$opc2),
4273 NoItinerary, "cdp2\t$cop, $opc1, $CRd, $CRn, $CRm, $opc2",
4274 [(int_arm_cdp2 imm:$cop, imm:$opc1, imm:$CRd, imm:$CRn,
4275 imm:$CRm, imm:$opc2)]> {
4276 let Inst{31-28} = 0b1111;
4284 let Inst{3-0} = CRm;
4286 let Inst{7-5} = opc2;
4287 let Inst{11-8} = cop;
4288 let Inst{15-12} = CRd;
4289 let Inst{19-16} = CRn;
4290 let Inst{23-20} = opc1;
4293 class ACI<dag oops, dag iops, string opc, string asm,
4294 IndexMode im = IndexModeNone>
4295 : I<oops, iops, AddrModeNone, 4, im, BrFrm, NoItinerary,
4297 let Inst{27-25} = 0b110;
4299 class ACInoP<dag oops, dag iops, string opc, string asm,
4300 IndexMode im = IndexModeNone>
4301 : InoP<oops, iops, AddrModeNone, 4, im, BrFrm, NoItinerary,
4303 let Inst{31-28} = 0b1111;
4304 let Inst{27-25} = 0b110;
4306 multiclass LdStCop<bit load, bit Dbit, string asm> {
4307 def _OFFSET : ACI<(outs), (ins p_imm:$cop, c_imm:$CRd, addrmode5:$addr),
4308 asm, "\t$cop, $CRd, $addr"> {
4312 let Inst{24} = 1; // P = 1
4313 let Inst{23} = addr{8};
4314 let Inst{22} = Dbit;
4315 let Inst{21} = 0; // W = 0
4316 let Inst{20} = load;
4317 let Inst{19-16} = addr{12-9};
4318 let Inst{15-12} = CRd;
4319 let Inst{11-8} = cop;
4320 let Inst{7-0} = addr{7-0};
4321 let DecoderMethod = "DecodeCopMemInstruction";
4323 def _PRE : ACI<(outs), (ins p_imm:$cop, c_imm:$CRd, addrmode5:$addr),
4324 asm, "\t$cop, $CRd, $addr!", IndexModePre> {
4328 let Inst{24} = 1; // P = 1
4329 let Inst{23} = addr{8};
4330 let Inst{22} = Dbit;
4331 let Inst{21} = 1; // W = 1
4332 let Inst{20} = load;
4333 let Inst{19-16} = addr{12-9};
4334 let Inst{15-12} = CRd;
4335 let Inst{11-8} = cop;
4336 let Inst{7-0} = addr{7-0};
4337 let DecoderMethod = "DecodeCopMemInstruction";
4339 def _POST: ACI<(outs), (ins p_imm:$cop, c_imm:$CRd, addr_offset_none:$addr,
4340 postidx_imm8s4:$offset),
4341 asm, "\t$cop, $CRd, $addr, $offset", IndexModePost> {
4346 let Inst{24} = 0; // P = 0
4347 let Inst{23} = offset{8};
4348 let Inst{22} = Dbit;
4349 let Inst{21} = 1; // W = 1
4350 let Inst{20} = load;
4351 let Inst{19-16} = addr;
4352 let Inst{15-12} = CRd;
4353 let Inst{11-8} = cop;
4354 let Inst{7-0} = offset{7-0};
4355 let DecoderMethod = "DecodeCopMemInstruction";
4357 def _OPTION : ACI<(outs),
4358 (ins p_imm:$cop, c_imm:$CRd, addr_offset_none:$addr,
4359 coproc_option_imm:$option),
4360 asm, "\t$cop, $CRd, $addr, $option"> {
4365 let Inst{24} = 0; // P = 0
4366 let Inst{23} = 1; // U = 1
4367 let Inst{22} = Dbit;
4368 let Inst{21} = 0; // W = 0
4369 let Inst{20} = load;
4370 let Inst{19-16} = addr;
4371 let Inst{15-12} = CRd;
4372 let Inst{11-8} = cop;
4373 let Inst{7-0} = option;
4374 let DecoderMethod = "DecodeCopMemInstruction";
4377 multiclass LdSt2Cop<bit load, bit Dbit, string asm> {
4378 def _OFFSET : ACInoP<(outs), (ins p_imm:$cop, c_imm:$CRd, addrmode5:$addr),
4379 asm, "\t$cop, $CRd, $addr"> {
4383 let Inst{24} = 1; // P = 1
4384 let Inst{23} = addr{8};
4385 let Inst{22} = Dbit;
4386 let Inst{21} = 0; // W = 0
4387 let Inst{20} = load;
4388 let Inst{19-16} = addr{12-9};
4389 let Inst{15-12} = CRd;
4390 let Inst{11-8} = cop;
4391 let Inst{7-0} = addr{7-0};
4392 let DecoderMethod = "DecodeCopMemInstruction";
4394 def _PRE : ACInoP<(outs), (ins p_imm:$cop, c_imm:$CRd, addrmode5:$addr),
4395 asm, "\t$cop, $CRd, $addr!", IndexModePre> {
4399 let Inst{24} = 1; // P = 1
4400 let Inst{23} = addr{8};
4401 let Inst{22} = Dbit;
4402 let Inst{21} = 1; // W = 1
4403 let Inst{20} = load;
4404 let Inst{19-16} = addr{12-9};
4405 let Inst{15-12} = CRd;
4406 let Inst{11-8} = cop;
4407 let Inst{7-0} = addr{7-0};
4408 let DecoderMethod = "DecodeCopMemInstruction";
4410 def _POST: ACInoP<(outs), (ins p_imm:$cop, c_imm:$CRd, addr_offset_none:$addr,
4411 postidx_imm8s4:$offset),
4412 asm, "\t$cop, $CRd, $addr, $offset", IndexModePost> {
4417 let Inst{24} = 0; // P = 0
4418 let Inst{23} = offset{8};
4419 let Inst{22} = Dbit;
4420 let Inst{21} = 1; // W = 1
4421 let Inst{20} = load;
4422 let Inst{19-16} = addr;
4423 let Inst{15-12} = CRd;
4424 let Inst{11-8} = cop;
4425 let Inst{7-0} = offset{7-0};
4426 let DecoderMethod = "DecodeCopMemInstruction";
4428 def _OPTION : ACInoP<(outs),
4429 (ins p_imm:$cop, c_imm:$CRd, addr_offset_none:$addr,
4430 coproc_option_imm:$option),
4431 asm, "\t$cop, $CRd, $addr, $option"> {
4436 let Inst{24} = 0; // P = 0
4437 let Inst{23} = 1; // U = 1
4438 let Inst{22} = Dbit;
4439 let Inst{21} = 0; // W = 0
4440 let Inst{20} = load;
4441 let Inst{19-16} = addr;
4442 let Inst{15-12} = CRd;
4443 let Inst{11-8} = cop;
4444 let Inst{7-0} = option;
4445 let DecoderMethod = "DecodeCopMemInstruction";
4449 defm LDC : LdStCop <1, 0, "ldc">;
4450 defm LDCL : LdStCop <1, 1, "ldcl">;
4451 defm STC : LdStCop <0, 0, "stc">;
4452 defm STCL : LdStCop <0, 1, "stcl">;
4453 defm LDC2 : LdSt2Cop<1, 0, "ldc2">;
4454 defm LDC2L : LdSt2Cop<1, 1, "ldc2l">;
4455 defm STC2 : LdSt2Cop<0, 0, "stc2">;
4456 defm STC2L : LdSt2Cop<0, 1, "stc2l">;
4458 //===----------------------------------------------------------------------===//
4459 // Move between coprocessor and ARM core register.
4462 class MovRCopro<string opc, bit direction, dag oops, dag iops,
4464 : ABI<0b1110, oops, iops, NoItinerary, opc,
4465 "\t$cop, $opc1, $Rt, $CRn, $CRm, $opc2", pattern> {
4466 let Inst{20} = direction;
4476 let Inst{15-12} = Rt;
4477 let Inst{11-8} = cop;
4478 let Inst{23-21} = opc1;
4479 let Inst{7-5} = opc2;
4480 let Inst{3-0} = CRm;
4481 let Inst{19-16} = CRn;
4484 def MCR : MovRCopro<"mcr", 0 /* from ARM core register to coprocessor */,
4486 (ins p_imm:$cop, imm0_7:$opc1, GPR:$Rt, c_imm:$CRn,
4487 c_imm:$CRm, imm0_7:$opc2),
4488 [(int_arm_mcr imm:$cop, imm:$opc1, GPR:$Rt, imm:$CRn,
4489 imm:$CRm, imm:$opc2)]>;
4490 def : ARMInstAlias<"mcr${p} $cop, $opc1, $Rt, $CRn, $CRm",
4491 (MCR p_imm:$cop, imm0_7:$opc1, GPR:$Rt, c_imm:$CRn,
4492 c_imm:$CRm, 0, pred:$p)>;
4493 def MRC : MovRCopro<"mrc", 1 /* from coprocessor to ARM core register */,
4495 (ins p_imm:$cop, imm0_7:$opc1, c_imm:$CRn, c_imm:$CRm,
4497 def : ARMInstAlias<"mrc${p} $cop, $opc1, $Rt, $CRn, $CRm",
4498 (MRC GPR:$Rt, p_imm:$cop, imm0_7:$opc1, c_imm:$CRn,
4499 c_imm:$CRm, 0, pred:$p)>;
4501 def : ARMPat<(int_arm_mrc imm:$cop, imm:$opc1, imm:$CRn, imm:$CRm, imm:$opc2),
4502 (MRC imm:$cop, imm:$opc1, imm:$CRn, imm:$CRm, imm:$opc2)>;
4504 class MovRCopro2<string opc, bit direction, dag oops, dag iops,
4506 : ABXI<0b1110, oops, iops, NoItinerary,
4507 !strconcat(opc, "\t$cop, $opc1, $Rt, $CRn, $CRm, $opc2"), pattern> {
4508 let Inst{31-28} = 0b1111;
4509 let Inst{20} = direction;
4519 let Inst{15-12} = Rt;
4520 let Inst{11-8} = cop;
4521 let Inst{23-21} = opc1;
4522 let Inst{7-5} = opc2;
4523 let Inst{3-0} = CRm;
4524 let Inst{19-16} = CRn;
4527 def MCR2 : MovRCopro2<"mcr2", 0 /* from ARM core register to coprocessor */,
4529 (ins p_imm:$cop, imm0_7:$opc1, GPR:$Rt, c_imm:$CRn,
4530 c_imm:$CRm, imm0_7:$opc2),
4531 [(int_arm_mcr2 imm:$cop, imm:$opc1, GPR:$Rt, imm:$CRn,
4532 imm:$CRm, imm:$opc2)]>;
4533 def : ARMInstAlias<"mcr2$ $cop, $opc1, $Rt, $CRn, $CRm",
4534 (MCR2 p_imm:$cop, imm0_7:$opc1, GPR:$Rt, c_imm:$CRn,
4536 def MRC2 : MovRCopro2<"mrc2", 1 /* from coprocessor to ARM core register */,
4538 (ins p_imm:$cop, imm0_7:$opc1, c_imm:$CRn, c_imm:$CRm,
4540 def : ARMInstAlias<"mrc2$ $cop, $opc1, $Rt, $CRn, $CRm",
4541 (MRC2 GPR:$Rt, p_imm:$cop, imm0_7:$opc1, c_imm:$CRn,
4544 def : ARMV5TPat<(int_arm_mrc2 imm:$cop, imm:$opc1, imm:$CRn,
4545 imm:$CRm, imm:$opc2),
4546 (MRC2 imm:$cop, imm:$opc1, imm:$CRn, imm:$CRm, imm:$opc2)>;
4548 class MovRRCopro<string opc, bit direction, list<dag> pattern = []>
4549 : ABI<0b1100, (outs), (ins p_imm:$cop, imm0_15:$opc1,
4550 GPRnopc:$Rt, GPRnopc:$Rt2, c_imm:$CRm),
4551 NoItinerary, opc, "\t$cop, $opc1, $Rt, $Rt2, $CRm", pattern> {
4552 let Inst{23-21} = 0b010;
4553 let Inst{20} = direction;
4561 let Inst{15-12} = Rt;
4562 let Inst{19-16} = Rt2;
4563 let Inst{11-8} = cop;
4564 let Inst{7-4} = opc1;
4565 let Inst{3-0} = CRm;
4568 def MCRR : MovRRCopro<"mcrr", 0 /* from ARM core register to coprocessor */,
4569 [(int_arm_mcrr imm:$cop, imm:$opc1, GPRnopc:$Rt,
4570 GPRnopc:$Rt2, imm:$CRm)]>;
4571 def MRRC : MovRRCopro<"mrrc", 1 /* from coprocessor to ARM core register */>;
4573 class MovRRCopro2<string opc, bit direction, list<dag> pattern = []>
4574 : ABXI<0b1100, (outs), (ins p_imm:$cop, imm0_15:$opc1,
4575 GPRnopc:$Rt, GPRnopc:$Rt2, c_imm:$CRm), NoItinerary,
4576 !strconcat(opc, "\t$cop, $opc1, $Rt, $Rt2, $CRm"), pattern> {
4577 let Inst{31-28} = 0b1111;
4578 let Inst{23-21} = 0b010;
4579 let Inst{20} = direction;
4587 let Inst{15-12} = Rt;
4588 let Inst{19-16} = Rt2;
4589 let Inst{11-8} = cop;
4590 let Inst{7-4} = opc1;
4591 let Inst{3-0} = CRm;
4593 let DecoderMethod = "DecodeMRRC2";
4596 def MCRR2 : MovRRCopro2<"mcrr2", 0 /* from ARM core register to coprocessor */,
4597 [(int_arm_mcrr2 imm:$cop, imm:$opc1, GPRnopc:$Rt,
4598 GPRnopc:$Rt2, imm:$CRm)]>;
4599 def MRRC2 : MovRRCopro2<"mrrc2", 1 /* from coprocessor to ARM core register */>;
4601 //===----------------------------------------------------------------------===//
4602 // Move between special register and ARM core register
4605 // Move to ARM core register from Special Register
4606 def MRS : ABI<0b0001, (outs GPRnopc:$Rd), (ins), NoItinerary,
4607 "mrs", "\t$Rd, apsr", []> {
4609 let Inst{23-16} = 0b00001111;
4610 let Unpredictable{19-17} = 0b111;
4612 let Inst{15-12} = Rd;
4614 let Inst{11-0} = 0b000000000000;
4615 let Unpredictable{11-0} = 0b110100001111;
4618 def : InstAlias<"mrs${p} $Rd, cpsr", (MRS GPRnopc:$Rd, pred:$p)>,
4621 // The MRSsys instruction is the MRS instruction from the ARM ARM,
4622 // section B9.3.9, with the R bit set to 1.
4623 def MRSsys : ABI<0b0001, (outs GPRnopc:$Rd), (ins), NoItinerary,
4624 "mrs", "\t$Rd, spsr", []> {
4626 let Inst{23-16} = 0b01001111;
4627 let Unpredictable{19-16} = 0b1111;
4629 let Inst{15-12} = Rd;
4631 let Inst{11-0} = 0b000000000000;
4632 let Unpredictable{11-0} = 0b110100001111;
4635 // Move from ARM core register to Special Register
4637 // No need to have both system and application versions, the encodings are the
4638 // same and the assembly parser has no way to distinguish between them. The mask
4639 // operand contains the special register (R Bit) in bit 4 and bits 3-0 contains
4640 // the mask with the fields to be accessed in the special register.
4641 def MSR : ABI<0b0001, (outs), (ins msr_mask:$mask, GPR:$Rn), NoItinerary,
4642 "msr", "\t$mask, $Rn", []> {
4647 let Inst{22} = mask{4}; // R bit
4648 let Inst{21-20} = 0b10;
4649 let Inst{19-16} = mask{3-0};
4650 let Inst{15-12} = 0b1111;
4651 let Inst{11-4} = 0b00000000;
4655 def MSRi : ABI<0b0011, (outs), (ins msr_mask:$mask, so_imm:$a), NoItinerary,
4656 "msr", "\t$mask, $a", []> {
4661 let Inst{22} = mask{4}; // R bit
4662 let Inst{21-20} = 0b10;
4663 let Inst{19-16} = mask{3-0};
4664 let Inst{15-12} = 0b1111;
4668 //===----------------------------------------------------------------------===//
4672 // __aeabi_read_tp preserves the registers r1-r3.
4673 // This is a pseudo inst so that we can get the encoding right,
4674 // complete with fixup for the aeabi_read_tp function.
4676 Defs = [R0, R12, LR, CPSR], Uses = [SP] in {
4677 def TPsoft : PseudoInst<(outs), (ins), IIC_Br,
4678 [(set R0, ARMthread_pointer)]>;
4681 //===----------------------------------------------------------------------===//
4682 // SJLJ Exception handling intrinsics
4683 // eh_sjlj_setjmp() is an instruction sequence to store the return
4684 // address and save #0 in R0 for the non-longjmp case.
4685 // Since by its nature we may be coming from some other function to get
4686 // here, and we're using the stack frame for the containing function to
4687 // save/restore registers, we can't keep anything live in regs across
4688 // the eh_sjlj_setjmp(), else it will almost certainly have been tromped upon
4689 // when we get here from a longjmp(). We force everything out of registers
4690 // except for our own input by listing the relevant registers in Defs. By
4691 // doing so, we also cause the prologue/epilogue code to actively preserve
4692 // all of the callee-saved resgisters, which is exactly what we want.
4693 // A constant value is passed in $val, and we use the location as a scratch.
4695 // These are pseudo-instructions and are lowered to individual MC-insts, so
4696 // no encoding information is necessary.
4698 [ R0, R1, R2, R3, R4, R5, R6, R7, R8, R9, R10, R11, R12, LR, CPSR,
4699 Q0, Q1, Q2, Q3, Q4, Q5, Q6, Q7, Q8, Q9, Q10, Q11, Q12, Q13, Q14, Q15 ],
4700 hasSideEffects = 1, isBarrier = 1, usesCustomInserter = 1 in {
4701 def Int_eh_sjlj_setjmp : PseudoInst<(outs), (ins GPR:$src, GPR:$val),
4703 [(set R0, (ARMeh_sjlj_setjmp GPR:$src, GPR:$val))]>,
4704 Requires<[IsARM, HasVFP2]>;
4708 [ R0, R1, R2, R3, R4, R5, R6, R7, R8, R9, R10, R11, R12, LR, CPSR ],
4709 hasSideEffects = 1, isBarrier = 1, usesCustomInserter = 1 in {
4710 def Int_eh_sjlj_setjmp_nofp : PseudoInst<(outs), (ins GPR:$src, GPR:$val),
4712 [(set R0, (ARMeh_sjlj_setjmp GPR:$src, GPR:$val))]>,
4713 Requires<[IsARM, NoVFP]>;
4716 // FIXME: Non-IOS version(s)
4717 let isBarrier = 1, hasSideEffects = 1, isTerminator = 1,
4718 Defs = [ R7, LR, SP ] in {
4719 def Int_eh_sjlj_longjmp : PseudoInst<(outs), (ins GPR:$src, GPR:$scratch),
4721 [(ARMeh_sjlj_longjmp GPR:$src, GPR:$scratch)]>,
4722 Requires<[IsARM, IsIOS]>;
4725 // eh.sjlj.dispatchsetup pseudo-instructions.
4726 // These pseudos are used for both ARM and Thumb2. Any differences are
4727 // handled when the pseudo is expanded (which happens before any passes
4728 // that need the instruction size).
4730 [ R0, R1, R2, R3, R4, R5, R6, R7, R8, R9, R10, R11, R12, LR, CPSR,
4731 Q0, Q1, Q2, Q3, Q4, Q5, Q6, Q7, Q8, Q9, Q10, Q11, Q12, Q13, Q14, Q15 ],
4733 def Int_eh_sjlj_dispatchsetup : PseudoInst<(outs), (ins), NoItinerary, []>;
4736 [ R0, R1, R2, R3, R4, R5, R6, R7, R8, R9, R10, R11, R12, LR, CPSR ],
4738 def Int_eh_sjlj_dispatchsetup_nofp : PseudoInst<(outs), (ins), NoItinerary, []>;
4741 //===----------------------------------------------------------------------===//
4742 // Non-Instruction Patterns
4745 // ARMv4 indirect branch using (MOVr PC, dst)
4746 let isBranch = 1, isTerminator = 1, isBarrier = 1, isIndirectBranch = 1 in
4747 def MOVPCRX : ARMPseudoExpand<(outs), (ins GPR:$dst),
4748 4, IIC_Br, [(brind GPR:$dst)],
4749 (MOVr PC, GPR:$dst, (ops 14, zero_reg), zero_reg)>,
4750 Requires<[IsARM, NoV4T]>;
4752 // Large immediate handling.
4754 // 32-bit immediate using two piece so_imms or movw + movt.
4755 // This is a single pseudo instruction, the benefit is that it can be remat'd
4756 // as a single unit instead of having to handle reg inputs.
4757 // FIXME: Remove this when we can do generalized remat.
4758 let isReMaterializable = 1, isMoveImm = 1 in
4759 def MOVi32imm : PseudoInst<(outs GPR:$dst), (ins i32imm:$src), IIC_iMOVix2,
4760 [(set GPR:$dst, (arm_i32imm:$src))]>,
4763 // Pseudo instruction that combines movw + movt + add pc (if PIC).
4764 // It also makes it possible to rematerialize the instructions.
4765 // FIXME: Remove this when we can do generalized remat and when machine licm
4766 // can properly the instructions.
4767 let isReMaterializable = 1 in {
4768 def MOV_ga_pcrel : PseudoInst<(outs GPR:$dst), (ins i32imm:$addr),
4770 [(set GPR:$dst, (ARMWrapperPIC tglobaladdr:$addr))]>,
4771 Requires<[IsARM, UseMovt]>;
4773 def MOV_ga_dyn : PseudoInst<(outs GPR:$dst), (ins i32imm:$addr),
4775 [(set GPR:$dst, (ARMWrapperDYN tglobaladdr:$addr))]>,
4776 Requires<[IsARM, UseMovt]>;
4778 let AddedComplexity = 10 in
4779 def MOV_ga_pcrel_ldr : PseudoInst<(outs GPR:$dst), (ins i32imm:$addr),
4781 [(set GPR:$dst, (load (ARMWrapperPIC tglobaladdr:$addr)))]>,
4782 Requires<[IsARM, UseMovt]>;
4783 } // isReMaterializable
4785 // ConstantPool, GlobalAddress, and JumpTable
4786 def : ARMPat<(ARMWrapper tglobaladdr :$dst), (LEApcrel tglobaladdr :$dst)>,
4787 Requires<[IsARM, DontUseMovt]>;
4788 def : ARMPat<(ARMWrapper tconstpool :$dst), (LEApcrel tconstpool :$dst)>;
4789 def : ARMPat<(ARMWrapper tglobaladdr :$dst), (MOVi32imm tglobaladdr :$dst)>,
4790 Requires<[IsARM, UseMovt]>;
4791 def : ARMPat<(ARMWrapperJT tjumptable:$dst, imm:$id),
4792 (LEApcrelJT tjumptable:$dst, imm:$id)>;
4794 // TODO: add,sub,and, 3-instr forms?
4796 // Tail calls. These patterns also apply to Thumb mode.
4797 def : Pat<(ARMtcret tcGPR:$dst), (TCRETURNri tcGPR:$dst)>;
4798 def : Pat<(ARMtcret (i32 tglobaladdr:$dst)), (TCRETURNdi texternalsym:$dst)>;
4799 def : Pat<(ARMtcret (i32 texternalsym:$dst)), (TCRETURNdi texternalsym:$dst)>;
4802 def : ARMPat<(ARMcall texternalsym:$func), (BL texternalsym:$func)>;
4803 def : ARMPat<(ARMcall_nolink texternalsym:$func),
4804 (BMOVPCB_CALL texternalsym:$func)>;
4806 // zextload i1 -> zextload i8
4807 def : ARMPat<(zextloadi1 addrmode_imm12:$addr), (LDRBi12 addrmode_imm12:$addr)>;
4808 def : ARMPat<(zextloadi1 ldst_so_reg:$addr), (LDRBrs ldst_so_reg:$addr)>;
4810 // extload -> zextload
4811 def : ARMPat<(extloadi1 addrmode_imm12:$addr), (LDRBi12 addrmode_imm12:$addr)>;
4812 def : ARMPat<(extloadi1 ldst_so_reg:$addr), (LDRBrs ldst_so_reg:$addr)>;
4813 def : ARMPat<(extloadi8 addrmode_imm12:$addr), (LDRBi12 addrmode_imm12:$addr)>;
4814 def : ARMPat<(extloadi8 ldst_so_reg:$addr), (LDRBrs ldst_so_reg:$addr)>;
4816 def : ARMPat<(extloadi16 addrmode3:$addr), (LDRH addrmode3:$addr)>;
4818 def : ARMPat<(extloadi8 addrmodepc:$addr), (PICLDRB addrmodepc:$addr)>;
4819 def : ARMPat<(extloadi16 addrmodepc:$addr), (PICLDRH addrmodepc:$addr)>;
4822 def : ARMV5TEPat<(mul (sra (shl GPR:$a, (i32 16)), (i32 16)),
4823 (sra (shl GPR:$b, (i32 16)), (i32 16))),
4824 (SMULBB GPR:$a, GPR:$b)>;
4825 def : ARMV5TEPat<(mul sext_16_node:$a, sext_16_node:$b),
4826 (SMULBB GPR:$a, GPR:$b)>;
4827 def : ARMV5TEPat<(mul (sra (shl GPR:$a, (i32 16)), (i32 16)),
4828 (sra GPR:$b, (i32 16))),
4829 (SMULBT GPR:$a, GPR:$b)>;
4830 def : ARMV5TEPat<(mul sext_16_node:$a, (sra GPR:$b, (i32 16))),
4831 (SMULBT GPR:$a, GPR:$b)>;
4832 def : ARMV5TEPat<(mul (sra GPR:$a, (i32 16)),
4833 (sra (shl GPR:$b, (i32 16)), (i32 16))),
4834 (SMULTB GPR:$a, GPR:$b)>;
4835 def : ARMV5TEPat<(mul (sra GPR:$a, (i32 16)), sext_16_node:$b),
4836 (SMULTB GPR:$a, GPR:$b)>;
4837 def : ARMV5TEPat<(sra (mul GPR:$a, (sra (shl GPR:$b, (i32 16)), (i32 16))),
4839 (SMULWB GPR:$a, GPR:$b)>;
4840 def : ARMV5TEPat<(sra (mul GPR:$a, sext_16_node:$b), (i32 16)),
4841 (SMULWB GPR:$a, GPR:$b)>;
4843 def : ARMV5TEPat<(add GPR:$acc,
4844 (mul (sra (shl GPR:$a, (i32 16)), (i32 16)),
4845 (sra (shl GPR:$b, (i32 16)), (i32 16)))),
4846 (SMLABB GPR:$a, GPR:$b, GPR:$acc)>;
4847 def : ARMV5TEPat<(add GPR:$acc,
4848 (mul sext_16_node:$a, sext_16_node:$b)),
4849 (SMLABB GPR:$a, GPR:$b, GPR:$acc)>;
4850 def : ARMV5TEPat<(add GPR:$acc,
4851 (mul (sra (shl GPR:$a, (i32 16)), (i32 16)),
4852 (sra GPR:$b, (i32 16)))),
4853 (SMLABT GPR:$a, GPR:$b, GPR:$acc)>;
4854 def : ARMV5TEPat<(add GPR:$acc,
4855 (mul sext_16_node:$a, (sra GPR:$b, (i32 16)))),
4856 (SMLABT GPR:$a, GPR:$b, GPR:$acc)>;
4857 def : ARMV5TEPat<(add GPR:$acc,
4858 (mul (sra GPR:$a, (i32 16)),
4859 (sra (shl GPR:$b, (i32 16)), (i32 16)))),
4860 (SMLATB GPR:$a, GPR:$b, GPR:$acc)>;
4861 def : ARMV5TEPat<(add GPR:$acc,
4862 (mul (sra GPR:$a, (i32 16)), sext_16_node:$b)),
4863 (SMLATB GPR:$a, GPR:$b, GPR:$acc)>;
4864 def : ARMV5TEPat<(add GPR:$acc,
4865 (sra (mul GPR:$a, (sra (shl GPR:$b, (i32 16)), (i32 16))),
4867 (SMLAWB GPR:$a, GPR:$b, GPR:$acc)>;
4868 def : ARMV5TEPat<(add GPR:$acc,
4869 (sra (mul GPR:$a, sext_16_node:$b), (i32 16))),
4870 (SMLAWB GPR:$a, GPR:$b, GPR:$acc)>;
4873 // Pre-v7 uses MCR for synchronization barriers.
4874 def : ARMPat<(ARMMemBarrierMCR GPR:$zero), (MCR 15, 0, GPR:$zero, 7, 10, 5)>,
4875 Requires<[IsARM, HasV6]>;
4877 // SXT/UXT with no rotate
4878 let AddedComplexity = 16 in {
4879 def : ARMV6Pat<(and GPR:$Src, 0x000000FF), (UXTB GPR:$Src, 0)>;
4880 def : ARMV6Pat<(and GPR:$Src, 0x0000FFFF), (UXTH GPR:$Src, 0)>;
4881 def : ARMV6Pat<(and GPR:$Src, 0x00FF00FF), (UXTB16 GPR:$Src, 0)>;
4882 def : ARMV6Pat<(add GPR:$Rn, (and GPR:$Rm, 0x00FF)),
4883 (UXTAB GPR:$Rn, GPR:$Rm, 0)>;
4884 def : ARMV6Pat<(add GPR:$Rn, (and GPR:$Rm, 0xFFFF)),
4885 (UXTAH GPR:$Rn, GPR:$Rm, 0)>;
4888 def : ARMV6Pat<(sext_inreg GPR:$Src, i8), (SXTB GPR:$Src, 0)>;
4889 def : ARMV6Pat<(sext_inreg GPR:$Src, i16), (SXTH GPR:$Src, 0)>;
4891 def : ARMV6Pat<(add GPR:$Rn, (sext_inreg GPRnopc:$Rm, i8)),
4892 (SXTAB GPR:$Rn, GPRnopc:$Rm, 0)>;
4893 def : ARMV6Pat<(add GPR:$Rn, (sext_inreg GPRnopc:$Rm, i16)),
4894 (SXTAH GPR:$Rn, GPRnopc:$Rm, 0)>;
4896 // Atomic load/store patterns
4897 def : ARMPat<(atomic_load_8 ldst_so_reg:$src),
4898 (LDRBrs ldst_so_reg:$src)>;
4899 def : ARMPat<(atomic_load_8 addrmode_imm12:$src),
4900 (LDRBi12 addrmode_imm12:$src)>;
4901 def : ARMPat<(atomic_load_16 addrmode3:$src),
4902 (LDRH addrmode3:$src)>;
4903 def : ARMPat<(atomic_load_32 ldst_so_reg:$src),
4904 (LDRrs ldst_so_reg:$src)>;
4905 def : ARMPat<(atomic_load_32 addrmode_imm12:$src),
4906 (LDRi12 addrmode_imm12:$src)>;
4907 def : ARMPat<(atomic_store_8 ldst_so_reg:$ptr, GPR:$val),
4908 (STRBrs GPR:$val, ldst_so_reg:$ptr)>;
4909 def : ARMPat<(atomic_store_8 addrmode_imm12:$ptr, GPR:$val),
4910 (STRBi12 GPR:$val, addrmode_imm12:$ptr)>;
4911 def : ARMPat<(atomic_store_16 addrmode3:$ptr, GPR:$val),
4912 (STRH GPR:$val, addrmode3:$ptr)>;
4913 def : ARMPat<(atomic_store_32 ldst_so_reg:$ptr, GPR:$val),
4914 (STRrs GPR:$val, ldst_so_reg:$ptr)>;
4915 def : ARMPat<(atomic_store_32 addrmode_imm12:$ptr, GPR:$val),
4916 (STRi12 GPR:$val, addrmode_imm12:$ptr)>;
4919 //===----------------------------------------------------------------------===//
4923 include "ARMInstrThumb.td"
4925 //===----------------------------------------------------------------------===//
4929 include "ARMInstrThumb2.td"
4931 //===----------------------------------------------------------------------===//
4932 // Floating Point Support
4935 include "ARMInstrVFP.td"
4937 //===----------------------------------------------------------------------===//
4938 // Advanced SIMD (NEON) Support
4941 include "ARMInstrNEON.td"
4943 //===----------------------------------------------------------------------===//
4944 // Assembler aliases
4948 def : InstAlias<"dmb", (DMB 0xf)>, Requires<[IsARM, HasDB]>;
4949 def : InstAlias<"dsb", (DSB 0xf)>, Requires<[IsARM, HasDB]>;
4950 def : InstAlias<"isb", (ISB 0xf)>, Requires<[IsARM, HasDB]>;
4952 // System instructions
4953 def : MnemonicAlias<"swi", "svc">;
4955 // Load / Store Multiple
4956 def : MnemonicAlias<"ldmfd", "ldm">;
4957 def : MnemonicAlias<"ldmia", "ldm">;
4958 def : MnemonicAlias<"ldmea", "ldmdb">;
4959 def : MnemonicAlias<"stmfd", "stmdb">;
4960 def : MnemonicAlias<"stmia", "stm">;
4961 def : MnemonicAlias<"stmea", "stm">;
4963 // PKHBT/PKHTB with default shift amount. PKHTB is equivalent to PKHBT when the
4964 // shift amount is zero (i.e., unspecified).
4965 def : InstAlias<"pkhbt${p} $Rd, $Rn, $Rm",
4966 (PKHBT GPRnopc:$Rd, GPRnopc:$Rn, GPRnopc:$Rm, 0, pred:$p)>,
4967 Requires<[IsARM, HasV6]>;
4968 def : InstAlias<"pkhtb${p} $Rd, $Rn, $Rm",
4969 (PKHBT GPRnopc:$Rd, GPRnopc:$Rn, GPRnopc:$Rm, 0, pred:$p)>,
4970 Requires<[IsARM, HasV6]>;
4972 // PUSH/POP aliases for STM/LDM
4973 def : ARMInstAlias<"push${p} $regs", (STMDB_UPD SP, pred:$p, reglist:$regs)>;
4974 def : ARMInstAlias<"pop${p} $regs", (LDMIA_UPD SP, pred:$p, reglist:$regs)>;
4976 // SSAT/USAT optional shift operand.
4977 def : ARMInstAlias<"ssat${p} $Rd, $sat_imm, $Rn",
4978 (SSAT GPRnopc:$Rd, imm1_32:$sat_imm, GPRnopc:$Rn, 0, pred:$p)>;
4979 def : ARMInstAlias<"usat${p} $Rd, $sat_imm, $Rn",
4980 (USAT GPRnopc:$Rd, imm0_31:$sat_imm, GPRnopc:$Rn, 0, pred:$p)>;
4983 // Extend instruction optional rotate operand.
4984 def : ARMInstAlias<"sxtab${p} $Rd, $Rn, $Rm",
4985 (SXTAB GPRnopc:$Rd, GPR:$Rn, GPRnopc:$Rm, 0, pred:$p)>;
4986 def : ARMInstAlias<"sxtah${p} $Rd, $Rn, $Rm",
4987 (SXTAH GPRnopc:$Rd, GPR:$Rn, GPRnopc:$Rm, 0, pred:$p)>;
4988 def : ARMInstAlias<"sxtab16${p} $Rd, $Rn, $Rm",
4989 (SXTAB16 GPRnopc:$Rd, GPR:$Rn, GPRnopc:$Rm, 0, pred:$p)>;
4990 def : ARMInstAlias<"sxtb${p} $Rd, $Rm",
4991 (SXTB GPRnopc:$Rd, GPRnopc:$Rm, 0, pred:$p)>;
4992 def : ARMInstAlias<"sxtb16${p} $Rd, $Rm",
4993 (SXTB16 GPRnopc:$Rd, GPRnopc:$Rm, 0, pred:$p)>;
4994 def : ARMInstAlias<"sxth${p} $Rd, $Rm",
4995 (SXTH GPRnopc:$Rd, GPRnopc:$Rm, 0, pred:$p)>;
4997 def : ARMInstAlias<"uxtab${p} $Rd, $Rn, $Rm",
4998 (UXTAB GPRnopc:$Rd, GPR:$Rn, GPRnopc:$Rm, 0, pred:$p)>;
4999 def : ARMInstAlias<"uxtah${p} $Rd, $Rn, $Rm",
5000 (UXTAH GPRnopc:$Rd, GPR:$Rn, GPRnopc:$Rm, 0, pred:$p)>;
5001 def : ARMInstAlias<"uxtab16${p} $Rd, $Rn, $Rm",
5002 (UXTAB16 GPRnopc:$Rd, GPR:$Rn, GPRnopc:$Rm, 0, pred:$p)>;
5003 def : ARMInstAlias<"uxtb${p} $Rd, $Rm",
5004 (UXTB GPRnopc:$Rd, GPRnopc:$Rm, 0, pred:$p)>;
5005 def : ARMInstAlias<"uxtb16${p} $Rd, $Rm",
5006 (UXTB16 GPRnopc:$Rd, GPRnopc:$Rm, 0, pred:$p)>;
5007 def : ARMInstAlias<"uxth${p} $Rd, $Rm",
5008 (UXTH GPRnopc:$Rd, GPRnopc:$Rm, 0, pred:$p)>;
5012 def : MnemonicAlias<"rfefa", "rfeda">;
5013 def : MnemonicAlias<"rfeea", "rfedb">;
5014 def : MnemonicAlias<"rfefd", "rfeia">;
5015 def : MnemonicAlias<"rfeed", "rfeib">;
5016 def : MnemonicAlias<"rfe", "rfeia">;
5019 def : MnemonicAlias<"srsfa", "srsda">;
5020 def : MnemonicAlias<"srsea", "srsdb">;
5021 def : MnemonicAlias<"srsfd", "srsia">;
5022 def : MnemonicAlias<"srsed", "srsib">;
5023 def : MnemonicAlias<"srs", "srsia">;
5026 def : MnemonicAlias<"qsubaddx", "qsax">;
5028 def : MnemonicAlias<"saddsubx", "sasx">;
5029 // SHASX == SHADDSUBX
5030 def : MnemonicAlias<"shaddsubx", "shasx">;
5031 // SHSAX == SHSUBADDX
5032 def : MnemonicAlias<"shsubaddx", "shsax">;
5034 def : MnemonicAlias<"ssubaddx", "ssax">;
5036 def : MnemonicAlias<"uaddsubx", "uasx">;
5037 // UHASX == UHADDSUBX
5038 def : MnemonicAlias<"uhaddsubx", "uhasx">;
5039 // UHSAX == UHSUBADDX
5040 def : MnemonicAlias<"uhsubaddx", "uhsax">;
5041 // UQASX == UQADDSUBX
5042 def : MnemonicAlias<"uqaddsubx", "uqasx">;
5043 // UQSAX == UQSUBADDX
5044 def : MnemonicAlias<"uqsubaddx", "uqsax">;
5046 def : MnemonicAlias<"usubaddx", "usax">;
5048 // "mov Rd, so_imm_not" can be handled via "mvn" in assembly, just like
5050 def : ARMInstAlias<"mov${s}${p} $Rd, $imm",
5051 (MVNi rGPR:$Rd, so_imm_not:$imm, pred:$p, cc_out:$s)>;
5052 def : ARMInstAlias<"mvn${s}${p} $Rd, $imm",
5053 (MOVi rGPR:$Rd, so_imm_not:$imm, pred:$p, cc_out:$s)>;
5054 // Same for AND <--> BIC
5055 def : ARMInstAlias<"bic${s}${p} $Rd, $Rn, $imm",
5056 (ANDri rGPR:$Rd, rGPR:$Rn, so_imm_not:$imm,
5057 pred:$p, cc_out:$s)>;
5058 def : ARMInstAlias<"bic${s}${p} $Rdn, $imm",
5059 (ANDri rGPR:$Rdn, rGPR:$Rdn, so_imm_not:$imm,
5060 pred:$p, cc_out:$s)>;
5061 def : ARMInstAlias<"and${s}${p} $Rd, $Rn, $imm",
5062 (BICri rGPR:$Rd, rGPR:$Rn, so_imm_not:$imm,
5063 pred:$p, cc_out:$s)>;
5064 def : ARMInstAlias<"and${s}${p} $Rdn, $imm",
5065 (BICri rGPR:$Rdn, rGPR:$Rdn, so_imm_not:$imm,
5066 pred:$p, cc_out:$s)>;
5068 // Likewise, "add Rd, so_imm_neg" -> sub
5069 def : ARMInstAlias<"add${s}${p} $Rd, $Rn, $imm",
5070 (SUBri GPR:$Rd, GPR:$Rn, so_imm_neg:$imm, pred:$p, cc_out:$s)>;
5071 def : ARMInstAlias<"add${s}${p} $Rd, $imm",
5072 (SUBri GPR:$Rd, GPR:$Rd, so_imm_neg:$imm, pred:$p, cc_out:$s)>;
5073 // Same for CMP <--> CMN via so_imm_neg
5074 def : ARMInstAlias<"cmp${p} $Rd, $imm",
5075 (CMNri rGPR:$Rd, so_imm_neg:$imm, pred:$p)>;
5076 def : ARMInstAlias<"cmn${p} $Rd, $imm",
5077 (CMPri rGPR:$Rd, so_imm_neg:$imm, pred:$p)>;
5079 // The shifter forms of the MOV instruction are aliased to the ASR, LSL,
5080 // LSR, ROR, and RRX instructions.
5081 // FIXME: We need C++ parser hooks to map the alias to the MOV
5082 // encoding. It seems we should be able to do that sort of thing
5083 // in tblgen, but it could get ugly.
5084 let TwoOperandAliasConstraint = "$Rm = $Rd" in {
5085 def ASRi : ARMAsmPseudo<"asr${s}${p} $Rd, $Rm, $imm",
5086 (ins GPR:$Rd, GPR:$Rm, imm0_32:$imm, pred:$p,
5088 def LSRi : ARMAsmPseudo<"lsr${s}${p} $Rd, $Rm, $imm",
5089 (ins GPR:$Rd, GPR:$Rm, imm0_32:$imm, pred:$p,
5091 def LSLi : ARMAsmPseudo<"lsl${s}${p} $Rd, $Rm, $imm",
5092 (ins GPR:$Rd, GPR:$Rm, imm0_31:$imm, pred:$p,
5094 def RORi : ARMAsmPseudo<"ror${s}${p} $Rd, $Rm, $imm",
5095 (ins GPR:$Rd, GPR:$Rm, imm0_31:$imm, pred:$p,
5098 def RRXi : ARMAsmPseudo<"rrx${s}${p} $Rd, $Rm",
5099 (ins GPRnopc:$Rd, GPRnopc:$Rm, pred:$p, cc_out:$s)>;
5100 let TwoOperandAliasConstraint = "$Rn = $Rd" in {
5101 def ASRr : ARMAsmPseudo<"asr${s}${p} $Rd, $Rn, $Rm",
5102 (ins GPRnopc:$Rd, GPRnopc:$Rn, GPRnopc:$Rm, pred:$p,
5104 def LSRr : ARMAsmPseudo<"lsr${s}${p} $Rd, $Rn, $Rm",
5105 (ins GPRnopc:$Rd, GPRnopc:$Rn, GPRnopc:$Rm, pred:$p,
5107 def LSLr : ARMAsmPseudo<"lsl${s}${p} $Rd, $Rn, $Rm",
5108 (ins GPRnopc:$Rd, GPRnopc:$Rn, GPRnopc:$Rm, pred:$p,
5110 def RORr : ARMAsmPseudo<"ror${s}${p} $Rd, $Rn, $Rm",
5111 (ins GPRnopc:$Rd, GPRnopc:$Rn, GPRnopc:$Rm, pred:$p,
5115 // "neg" is and alias for "rsb rd, rn, #0"
5116 def : ARMInstAlias<"neg${s}${p} $Rd, $Rm",
5117 (RSBri GPR:$Rd, GPR:$Rm, 0, pred:$p, cc_out:$s)>;
5119 // Pre-v6, 'mov r0, r0' was used as a NOP encoding.
5120 def : InstAlias<"nop${p}", (MOVr R0, R0, pred:$p, zero_reg)>,
5121 Requires<[IsARM, NoV6]>;
5123 // UMULL/SMULL are available on all arches, but the instruction definitions
5124 // need difference constraints pre-v6. Use these aliases for the assembly
5125 // parsing on pre-v6.
5126 def : InstAlias<"smull${s}${p} $RdLo, $RdHi, $Rn, $Rm",
5127 (SMULL GPR:$RdLo, GPR:$RdHi, GPR:$Rn, GPR:$Rm, pred:$p, cc_out:$s)>,
5128 Requires<[IsARM, NoV6]>;
5129 def : InstAlias<"umull${s}${p} $RdLo, $RdHi, $Rn, $Rm",
5130 (UMULL GPR:$RdLo, GPR:$RdHi, GPR:$Rn, GPR:$Rm, pred:$p, cc_out:$s)>,
5131 Requires<[IsARM, NoV6]>;
5133 // 'it' blocks in ARM mode just validate the predicates. The IT itself
5135 def ITasm : ARMAsmPseudo<"it$mask $cc", (ins it_pred:$cc, it_mask:$mask)>;