1 //===- ARMInstrInfo.td - Target Description for ARM Target ----------------===//
3 // The LLVM Compiler Infrastructure
5 // This file was developed by the "Instituto Nokia de Tecnologia" and
6 // is distributed under the University of Illinois Open Source
7 // License. See LICENSE.TXT for details.
9 //===----------------------------------------------------------------------===//
11 // This file describes the ARM instructions in TableGen format.
13 //===----------------------------------------------------------------------===//
16 def op_addr_mode1 : Operand<iPTR> {
17 let PrintMethod = "printAddrMode1";
18 let NumMIOperands = 3;
19 let MIOperandInfo = (ops ptr_rc, ptr_rc, i32imm);
22 def op_addr_mode5 : Operand<iPTR> {
23 let PrintMethod = "printAddrMode5";
24 let NumMIOperands = 2;
25 let MIOperandInfo = (ops ptr_rc, i32imm);
28 def memri : Operand<iPTR> {
29 let PrintMethod = "printMemRegImm";
30 let NumMIOperands = 2;
31 let MIOperandInfo = (ops i32imm, ptr_rc);
34 // Define ARM specific addressing mode.
35 //Addressing Mode 1: data processing operands
36 def addr_mode1 : ComplexPattern<iPTR, 3, "SelectAddrMode1", [imm, sra, shl, srl],
39 //Addressing Mode 5: VFP load/store
40 def addr_mode5 : ComplexPattern<iPTR, 2, "SelectAddrMode5", [], []>;
42 //register plus/minus 12 bit offset
43 def iaddr : ComplexPattern<iPTR, 2, "SelectAddrRegImm", [frameindex], []>;
44 //register plus scaled register
45 //def raddr : ComplexPattern<iPTR, 2, "SelectAddrRegReg", [], []>;
47 //===----------------------------------------------------------------------===//
48 // Instruction Class Templates
49 //===----------------------------------------------------------------------===//
50 class InstARM<dag ops, string asmstr, list<dag> pattern> : Instruction {
51 let Namespace = "ARM";
53 dag OperandList = ops;
54 let AsmString = asmstr;
55 let Pattern = pattern;
58 class IntBinOp<string OpcStr, SDNode OpNode> :
59 InstARM<(ops IntRegs:$dst, IntRegs:$a, IntRegs:$b),
60 !strconcat(OpcStr, " $dst, $a, $b"),
61 [(set IntRegs:$dst, (OpNode IntRegs:$a, IntRegs:$b))]>;
63 class FPBinOp<string OpcStr, SDNode OpNode> :
64 InstARM<(ops FPRegs:$dst, FPRegs:$a, FPRegs:$b),
65 !strconcat(OpcStr, " $dst, $a, $b"),
66 [(set FPRegs:$dst, (OpNode FPRegs:$a, FPRegs:$b))]>;
68 class DFPBinOp<string OpcStr, SDNode OpNode> :
69 InstARM<(ops DFPRegs:$dst, DFPRegs:$a, DFPRegs:$b),
70 !strconcat(OpcStr, " $dst, $a, $b"),
71 [(set DFPRegs:$dst, (OpNode DFPRegs:$a, DFPRegs:$b))]>;
73 class FPUnaryOp<string OpcStr, SDNode OpNode> :
74 InstARM<(ops FPRegs:$dst, FPRegs:$src),
75 !strconcat(OpcStr, " $dst, $src"),
76 [(set FPRegs:$dst, (OpNode FPRegs:$src))]>;
78 class DFPUnaryOp<string OpcStr, SDNode OpNode> :
79 InstARM<(ops DFPRegs:$dst, DFPRegs:$src),
80 !strconcat(OpcStr, " $dst, $src"),
81 [(set DFPRegs:$dst, (OpNode DFPRegs:$src))]>;
83 class Addr1BinOp<string OpcStr, SDNode OpNode> :
84 InstARM<(ops IntRegs:$dst, IntRegs:$a, op_addr_mode1:$b),
85 !strconcat(OpcStr, " $dst, $a, $b"),
86 [(set IntRegs:$dst, (OpNode IntRegs:$a, addr_mode1:$b))]>;
88 //===----------------------------------------------------------------------===//
90 //===----------------------------------------------------------------------===//
92 def brtarget : Operand<OtherVT>;
94 // Operand for printing out a condition code.
95 let PrintMethod = "printCCOperand" in
96 def CCOp : Operand<i32>;
98 def SDT_ARMCallSeq : SDTypeProfile<0, 1, [ SDTCisVT<0, i32> ]>;
99 def callseq_start : SDNode<"ISD::CALLSEQ_START", SDT_ARMCallSeq,
100 [SDNPHasChain, SDNPOutFlag]>;
101 def callseq_end : SDNode<"ISD::CALLSEQ_END", SDT_ARMCallSeq,
102 [SDNPHasChain, SDNPOutFlag]>;
104 def SDT_ARMcall : SDTypeProfile<0, -1, [SDTCisInt<0>]>;
105 def ARMcall : SDNode<"ARMISD::CALL", SDT_ARMcall,
106 [SDNPHasChain, SDNPOptInFlag, SDNPOutFlag]>;
107 def retflag : SDNode<"ARMISD::RET_FLAG", SDTRet,
108 [SDNPHasChain, SDNPOptInFlag]>;
110 def SDTarmselect : SDTypeProfile<1, 3, [SDTCisSameAs<0, 1>, SDTCisSameAs<0, 2>, SDTCisInt<0>, SDTCisVT<2, i32>]>;
111 def armselect : SDNode<"ARMISD::SELECT", SDTarmselect, [SDNPInFlag, SDNPOutFlag]>;
113 def SDTarmfmstat : SDTypeProfile<0, 0, []>;
114 def armfmstat : SDNode<"ARMISD::FMSTAT", SDTarmfmstat, [SDNPInFlag, SDNPOutFlag]>;
116 def SDTarmbr : SDTypeProfile<0, 2, [SDTCisVT<0, OtherVT>, SDTCisVT<1, i32>]>;
117 def armbr : SDNode<"ARMISD::BR", SDTarmbr, [SDNPHasChain, SDNPInFlag]>;
119 def SDTVoidBinOp : SDTypeProfile<0, 2, [SDTCisSameAs<0, 1>]>;
120 def armcmp : SDNode<"ARMISD::CMP", SDTVoidBinOp, [SDNPOutFlag]>;
122 def armfsitos : SDNode<"ARMISD::FSITOS", SDTUnaryOp>;
123 def armftosis : SDNode<"ARMISD::FTOSIS", SDTUnaryOp>;
124 def armfsitod : SDNode<"ARMISD::FSITOD", SDTUnaryOp>;
125 def armftosid : SDNode<"ARMISD::FTOSID", SDTUnaryOp>;
126 def armfuitos : SDNode<"ARMISD::FUITOS", SDTUnaryOp>;
127 def armftouis : SDNode<"ARMISD::FTOUIS", SDTUnaryOp>;
128 def armfuitod : SDNode<"ARMISD::FUITOD", SDTUnaryOp>;
129 def armftouid : SDNode<"ARMISD::FTOUID", SDTUnaryOp>;
131 def SDTarmfmrrd : SDTypeProfile<0, 3, [SDTCisInt<0>, SDTCisInt<1>, SDTCisFP<2>]>;
132 def armfmrrd : SDNode<"ARMISD::FMRRD", SDTarmfmrrd,
133 [SDNPHasChain, SDNPOptInFlag, SDNPOutFlag]>;
135 def SDTarmfmdrr : SDTypeProfile<1, 2, [SDTCisFP<0>, SDTCisInt<1>, SDTCisInt<2>]>;
136 def armfmdrr : SDNode<"ARMISD::FMDRR", SDTarmfmdrr, []>;
138 def ADJCALLSTACKUP : InstARM<(ops i32imm:$amt),
139 "!ADJCALLSTACKUP $amt",
140 [(callseq_end imm:$amt)]>, Imp<[R13],[R13]>;
142 def ADJCALLSTACKDOWN : InstARM<(ops i32imm:$amt),
143 "!ADJCALLSTACKDOWN $amt",
144 [(callseq_start imm:$amt)]>, Imp<[R13],[R13]>;
146 def IMPLICIT_DEF_Int : InstARM<(ops IntRegs:$dst),
147 "@IMPLICIT_DEF $dst",
148 [(set IntRegs:$dst, (undef))]>;
149 def IMPLICIT_DEF_FP : InstARM<(ops FPRegs:$dst), "@IMPLICIT_DEF $dst",
150 [(set FPRegs:$dst, (undef))]>;
151 def IMPLICIT_DEF_DFP : InstARM<(ops DFPRegs:$dst), "@IMPLICIT_DEF $dst",
152 [(set DFPRegs:$dst, (undef))]>;
154 let isReturn = 1 in {
155 def bx: InstARM<(ops), "bx r14", [(retflag)]>;
158 let noResults = 1, Defs = [R0, R1, R2, R3, R14] in {
159 def bl: InstARM<(ops i32imm:$func, variable_ops), "bl $func", []>;
160 def blx : InstARM<(ops IntRegs:$func, variable_ops), "blx $func", [(ARMcall IntRegs:$func)]>;
163 def ldr : InstARM<(ops IntRegs:$dst, memri:$addr),
165 [(set IntRegs:$dst, (load iaddr:$addr))]>;
167 def LDRB : InstARM<(ops IntRegs:$dst, IntRegs:$addr),
168 "ldrb $dst, [$addr]",
169 [(set IntRegs:$dst, (zextloadi8 IntRegs:$addr))]>;
171 def LDRSB : InstARM<(ops IntRegs:$dst, IntRegs:$addr),
172 "ldrsb $dst, [$addr]",
173 [(set IntRegs:$dst, (sextloadi8 IntRegs:$addr))]>;
175 def LDRH : InstARM<(ops IntRegs:$dst, IntRegs:$addr),
176 "ldrh $dst, [$addr]",
177 [(set IntRegs:$dst, (zextloadi16 IntRegs:$addr))]>;
179 def LDRSH : InstARM<(ops IntRegs:$dst, IntRegs:$addr),
180 "ldrsh $dst, [$addr]",
181 [(set IntRegs:$dst, (sextloadi16 IntRegs:$addr))]>;
183 def str : InstARM<(ops IntRegs:$src, memri:$addr),
185 [(store IntRegs:$src, iaddr:$addr)]>;
187 def STRB : InstARM<(ops IntRegs:$src, IntRegs:$addr),
188 "strb $src, [$addr]",
189 [(truncstorei8 IntRegs:$src, IntRegs:$addr)]>;
191 def STRH : InstARM<(ops IntRegs:$src, IntRegs:$addr),
192 "strh $src, [$addr]",
193 [(truncstorei16 IntRegs:$src, IntRegs:$addr)]>;
195 def MOV : InstARM<(ops IntRegs:$dst, op_addr_mode1:$src),
196 "mov $dst, $src", [(set IntRegs:$dst, addr_mode1:$src)]>;
198 def ADD : Addr1BinOp<"add", add>;
199 def ADCS : Addr1BinOp<"adcs", adde>;
200 def ADDS : Addr1BinOp<"adds", addc>;
202 // "LEA" forms of add
203 def lea_addri : InstARM<(ops IntRegs:$dst, memri:$addr),
204 "add $dst, ${addr:arith}",
205 [(set IntRegs:$dst, iaddr:$addr)]>;
208 def SUB : Addr1BinOp<"sub", sub>;
209 def SBCS : Addr1BinOp<"sbcs", sube>;
210 def SUBS : Addr1BinOp<"subs", subc>;
211 def AND : Addr1BinOp<"and", and>;
212 def EOR : Addr1BinOp<"eor", xor>;
213 def ORR : Addr1BinOp<"orr", or>;
215 let isTwoAddress = 1 in {
216 def movcond : InstARM<(ops IntRegs:$dst, IntRegs:$false,
217 op_addr_mode1:$true, CCOp:$cc),
218 "mov$cc $dst, $true",
219 [(set IntRegs:$dst, (armselect addr_mode1:$true,
220 IntRegs:$false, imm:$cc))]>;
223 def MUL : IntBinOp<"mul", mul>;
226 def SMULL : IntBinOp<"smull r12,", mulhs>;
227 def UMULL : IntBinOp<"umull r12,", mulhu>;
230 let isTerminator = 1, isBranch = 1 in {
231 def bcond : InstARM<(ops brtarget:$dst, CCOp:$cc),
233 [(armbr bb:$dst, imm:$cc)]>;
235 def b : InstARM<(ops brtarget:$dst),
240 def cmp : InstARM<(ops IntRegs:$a, op_addr_mode1:$b),
242 [(armcmp IntRegs:$a, addr_mode1:$b)]>;
244 // Floating Point Compare
245 def fcmps : InstARM<(ops FPRegs:$a, FPRegs:$b),
247 [(armcmp FPRegs:$a, FPRegs:$b)]>;
249 def fcmpd : InstARM<(ops DFPRegs:$a, DFPRegs:$b),
251 [(armcmp DFPRegs:$a, DFPRegs:$b)]>;
253 // Floating Point Copy
254 def FCPYS : InstARM<(ops FPRegs:$dst, FPRegs:$src), "fcpys $dst, $src", []>;
256 def FCPYD : InstARM<(ops DFPRegs:$dst, DFPRegs:$src), "fcpyd $dst, $src", []>;
258 // Floating Point Conversion
259 // We use bitconvert for moving the data between the register classes.
260 // The format conversion is done with ARM specific nodes
262 def FMSR : InstARM<(ops FPRegs:$dst, IntRegs:$src),
263 "fmsr $dst, $src", [(set FPRegs:$dst, (bitconvert IntRegs:$src))]>;
265 def FMRS : InstARM<(ops IntRegs:$dst, FPRegs:$src),
266 "fmrs $dst, $src", [(set IntRegs:$dst, (bitconvert FPRegs:$src))]>;
268 def FMRRD : InstARM<(ops IntRegs:$i0, IntRegs:$i1, DFPRegs:$src),
269 "fmrrd $i0, $i1, $src", [(armfmrrd IntRegs:$i0, IntRegs:$i1, DFPRegs:$src)]>;
271 def FMDRR : InstARM<(ops DFPRegs:$dst, IntRegs:$i0, IntRegs:$i1),
272 "fmdrr $dst, $i0, $i1", [(set DFPRegs:$dst, (armfmdrr IntRegs:$i0, IntRegs:$i1))]>;
274 def FSITOS : InstARM<(ops FPRegs:$dst, FPRegs:$src),
275 "fsitos $dst, $src", [(set FPRegs:$dst, (armfsitos FPRegs:$src))]>;
277 def FTOSIS : InstARM<(ops FPRegs:$dst, FPRegs:$src),
278 "ftosis $dst, $src", [(set FPRegs:$dst, (armftosis FPRegs:$src))]>;
280 def FSITOD : InstARM<(ops DFPRegs:$dst, FPRegs:$src),
281 "fsitod $dst, $src", [(set DFPRegs:$dst, (armfsitod FPRegs:$src))]>;
283 def FTOSID : InstARM<(ops FPRegs:$dst, DFPRegs:$src),
284 "ftosid $dst, $src", [(set FPRegs:$dst, (armftosid DFPRegs:$src))]>;
286 def FUITOS : InstARM<(ops FPRegs:$dst, FPRegs:$src),
287 "fuitos $dst, $src", [(set FPRegs:$dst, (armfuitos FPRegs:$src))]>;
289 def FTOUIS : InstARM<(ops FPRegs:$dst, FPRegs:$src),
290 "ftouis $dst, $src", [(set FPRegs:$dst, (armftouis FPRegs:$src))]>;
292 def FUITOD : InstARM<(ops DFPRegs:$dst, FPRegs:$src),
293 "fuitod $dst, $src", [(set DFPRegs:$dst, (armfuitod FPRegs:$src))]>;
295 def FTOUID : InstARM<(ops FPRegs:$dst, DFPRegs:$src),
296 "ftouid $dst, $src", [(set FPRegs:$dst, (armftouid DFPRegs:$src))]>;
298 def FCVTDS : InstARM<(ops DFPRegs:$dst, FPRegs:$src),
299 "fcvtds $dst, $src", [(set DFPRegs:$dst, (fextend FPRegs:$src))]>;
301 def FCVTSD : InstARM<(ops FPRegs:$dst, DFPRegs:$src),
302 "fcvtsd $dst, $src", [(set FPRegs:$dst, (fround DFPRegs:$src))]>;
304 def FMSTAT : InstARM<(ops ), "fmstat", [(armfmstat)]>;
306 // Floating Point Arithmetic
307 def FADDS : FPBinOp<"fadds", fadd>;
308 def FADDD : DFPBinOp<"faddd", fadd>;
309 def FSUBS : FPBinOp<"fsubs", fsub>;
310 def FSUBD : DFPBinOp<"fsubd", fsub>;
312 def FNEGS : FPUnaryOp<"fnegs", fneg>;
313 def FNEGD : DFPUnaryOp<"fnegd", fneg>;
314 def FABSS : FPUnaryOp<"fabss", fabs>;
315 def FABSD : DFPUnaryOp<"fabsd", fabs>;
317 def FMULS : FPBinOp<"fmuls", fmul>;
318 def FMULD : DFPBinOp<"fmuld", fmul>;
319 def FDIVS : FPBinOp<"fdivs", fdiv>;
320 def FDIVD : DFPBinOp<"fdivd", fdiv>;
322 // Floating Point Load
323 def FLDS : InstARM<(ops FPRegs:$dst, op_addr_mode5:$addr),
325 [(set FPRegs:$dst, (load addr_mode5:$addr))]>;
327 def FLDD : InstARM<(ops DFPRegs:$dst, op_addr_mode5:$addr),
329 [(set DFPRegs:$dst, (load addr_mode5:$addr))]>;
331 // Floating Point Store
332 def FSTS : InstARM<(ops FPRegs:$src, op_addr_mode5:$addr),
334 [(store FPRegs:$src, addr_mode5:$addr)]>;
336 def FSTD : InstARM<(ops DFPRegs:$src, op_addr_mode5:$addr),
338 [(store DFPRegs:$src, addr_mode5:$addr)]>;
340 def : Pat<(ARMcall tglobaladdr:$dst),
341 (bl tglobaladdr:$dst)>;
343 def : Pat<(ARMcall texternalsym:$dst),
344 (bl texternalsym:$dst)>;
346 def : Pat<(extloadi8 IntRegs:$addr),
347 (LDRB IntRegs:$addr)>;
348 def : Pat<(extloadi16 IntRegs:$addr),
349 (LDRH IntRegs:$addr)>;