1 //===- ARMInstrInfo.td - Target Description for ARM Target -*- tablegen -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file describes the ARM instructions in TableGen format.
12 //===----------------------------------------------------------------------===//
14 //===----------------------------------------------------------------------===//
15 // ARM specific DAG Nodes.
19 def SDT_ARMCallSeqStart : SDCallSeqStart<[ SDTCisVT<0, i32> ]>;
20 def SDT_ARMCallSeqEnd : SDCallSeqEnd<[ SDTCisVT<0, i32>, SDTCisVT<1, i32> ]>;
21 def SDT_ARMStructByVal : SDTypeProfile<0, 4,
22 [SDTCisVT<0, i32>, SDTCisVT<1, i32>,
23 SDTCisVT<2, i32>, SDTCisVT<3, i32>]>;
25 def SDT_ARMSaveCallPC : SDTypeProfile<0, 1, []>;
27 def SDT_ARMcall : SDTypeProfile<0, -1, [SDTCisPtrTy<0>]>;
29 def SDT_ARMCMov : SDTypeProfile<1, 3,
30 [SDTCisSameAs<0, 1>, SDTCisSameAs<0, 2>,
33 def SDT_ARMBrcond : SDTypeProfile<0, 2,
34 [SDTCisVT<0, OtherVT>, SDTCisVT<1, i32>]>;
36 def SDT_ARMBrJT : SDTypeProfile<0, 3,
37 [SDTCisPtrTy<0>, SDTCisVT<1, i32>,
40 def SDT_ARMBr2JT : SDTypeProfile<0, 4,
41 [SDTCisPtrTy<0>, SDTCisVT<1, i32>,
42 SDTCisVT<2, i32>, SDTCisVT<3, i32>]>;
44 def SDT_ARMBCC_i64 : SDTypeProfile<0, 6,
46 SDTCisVT<1, i32>, SDTCisVT<2, i32>,
47 SDTCisVT<3, i32>, SDTCisVT<4, i32>,
48 SDTCisVT<5, OtherVT>]>;
50 def SDT_ARMAnd : SDTypeProfile<1, 2,
51 [SDTCisVT<0, i32>, SDTCisVT<1, i32>,
54 def SDT_ARMCmp : SDTypeProfile<0, 2, [SDTCisSameAs<0, 1>]>;
56 def SDT_ARMPICAdd : SDTypeProfile<1, 2, [SDTCisSameAs<0, 1>,
57 SDTCisPtrTy<1>, SDTCisVT<2, i32>]>;
59 def SDT_ARMThreadPointer : SDTypeProfile<1, 0, [SDTCisPtrTy<0>]>;
60 def SDT_ARMEH_SJLJ_Setjmp : SDTypeProfile<1, 2, [SDTCisInt<0>, SDTCisPtrTy<1>,
62 def SDT_ARMEH_SJLJ_Longjmp: SDTypeProfile<0, 2, [SDTCisPtrTy<0>, SDTCisInt<1>]>;
64 def SDT_ARMMEMBARRIER : SDTypeProfile<0, 1, [SDTCisInt<0>]>;
66 def SDT_ARMPREFETCH : SDTypeProfile<0, 3, [SDTCisPtrTy<0>, SDTCisSameAs<1, 2>,
69 def SDT_ARMTCRET : SDTypeProfile<0, 1, [SDTCisPtrTy<0>]>;
71 def SDT_ARMBFI : SDTypeProfile<1, 3, [SDTCisVT<0, i32>, SDTCisVT<1, i32>,
72 SDTCisVT<2, i32>, SDTCisVT<3, i32>]>;
74 def SDT_ARMVMAXNM : SDTypeProfile<1, 2, [SDTCisFP<0>, SDTCisFP<1>, SDTCisFP<2>]>;
75 def SDT_ARMVMINNM : SDTypeProfile<1, 2, [SDTCisFP<0>, SDTCisFP<1>, SDTCisFP<2>]>;
77 def SDTBinaryArithWithFlags : SDTypeProfile<2, 2,
80 SDTCisInt<0>, SDTCisVT<1, i32>]>;
82 // SDTBinaryArithWithFlagsInOut - RES1, CPSR = op LHS, RHS, CPSR
83 def SDTBinaryArithWithFlagsInOut : SDTypeProfile<2, 3,
90 def SDT_ARM64bitmlal : SDTypeProfile<2,4, [ SDTCisVT<0, i32>, SDTCisVT<1, i32>,
91 SDTCisVT<2, i32>, SDTCisVT<3, i32>,
92 SDTCisVT<4, i32>, SDTCisVT<5, i32> ] >;
93 def ARMUmlal : SDNode<"ARMISD::UMLAL", SDT_ARM64bitmlal>;
94 def ARMSmlal : SDNode<"ARMISD::SMLAL", SDT_ARM64bitmlal>;
97 def ARMWrapper : SDNode<"ARMISD::Wrapper", SDTIntUnaryOp>;
98 def ARMWrapperPIC : SDNode<"ARMISD::WrapperPIC", SDTIntUnaryOp>;
99 def ARMWrapperJT : SDNode<"ARMISD::WrapperJT", SDTIntBinOp>;
101 def ARMcallseq_start : SDNode<"ISD::CALLSEQ_START", SDT_ARMCallSeqStart,
102 [SDNPHasChain, SDNPSideEffect, SDNPOutGlue]>;
103 def ARMcallseq_end : SDNode<"ISD::CALLSEQ_END", SDT_ARMCallSeqEnd,
104 [SDNPHasChain, SDNPSideEffect,
105 SDNPOptInGlue, SDNPOutGlue]>;
106 def ARMcopystructbyval : SDNode<"ARMISD::COPY_STRUCT_BYVAL" ,
108 [SDNPHasChain, SDNPInGlue, SDNPOutGlue,
109 SDNPMayStore, SDNPMayLoad]>;
111 def ARMcall : SDNode<"ARMISD::CALL", SDT_ARMcall,
112 [SDNPHasChain, SDNPOptInGlue, SDNPOutGlue,
114 def ARMcall_pred : SDNode<"ARMISD::CALL_PRED", SDT_ARMcall,
115 [SDNPHasChain, SDNPOptInGlue, SDNPOutGlue,
117 def ARMcall_nolink : SDNode<"ARMISD::CALL_NOLINK", SDT_ARMcall,
118 [SDNPHasChain, SDNPOptInGlue, SDNPOutGlue,
121 def ARMretflag : SDNode<"ARMISD::RET_FLAG", SDTNone,
122 [SDNPHasChain, SDNPOptInGlue, SDNPVariadic]>;
123 def ARMintretflag : SDNode<"ARMISD::INTRET_FLAG", SDT_ARMcall,
124 [SDNPHasChain, SDNPOptInGlue, SDNPVariadic]>;
125 def ARMcmov : SDNode<"ARMISD::CMOV", SDT_ARMCMov,
128 def ARMbrcond : SDNode<"ARMISD::BRCOND", SDT_ARMBrcond,
129 [SDNPHasChain, SDNPInGlue, SDNPOutGlue]>;
131 def ARMbrjt : SDNode<"ARMISD::BR_JT", SDT_ARMBrJT,
133 def ARMbr2jt : SDNode<"ARMISD::BR2_JT", SDT_ARMBr2JT,
136 def ARMBcci64 : SDNode<"ARMISD::BCC_i64", SDT_ARMBCC_i64,
139 def ARMcmp : SDNode<"ARMISD::CMP", SDT_ARMCmp,
142 def ARMcmn : SDNode<"ARMISD::CMN", SDT_ARMCmp,
145 def ARMcmpZ : SDNode<"ARMISD::CMPZ", SDT_ARMCmp,
146 [SDNPOutGlue, SDNPCommutative]>;
148 def ARMpic_add : SDNode<"ARMISD::PIC_ADD", SDT_ARMPICAdd>;
150 def ARMsrl_flag : SDNode<"ARMISD::SRL_FLAG", SDTIntUnaryOp, [SDNPOutGlue]>;
151 def ARMsra_flag : SDNode<"ARMISD::SRA_FLAG", SDTIntUnaryOp, [SDNPOutGlue]>;
152 def ARMrrx : SDNode<"ARMISD::RRX" , SDTIntUnaryOp, [SDNPInGlue ]>;
154 def ARMaddc : SDNode<"ARMISD::ADDC", SDTBinaryArithWithFlags,
156 def ARMsubc : SDNode<"ARMISD::SUBC", SDTBinaryArithWithFlags>;
157 def ARMadde : SDNode<"ARMISD::ADDE", SDTBinaryArithWithFlagsInOut>;
158 def ARMsube : SDNode<"ARMISD::SUBE", SDTBinaryArithWithFlagsInOut>;
160 def ARMthread_pointer: SDNode<"ARMISD::THREAD_POINTER", SDT_ARMThreadPointer>;
161 def ARMeh_sjlj_setjmp: SDNode<"ARMISD::EH_SJLJ_SETJMP",
162 SDT_ARMEH_SJLJ_Setjmp,
163 [SDNPHasChain, SDNPSideEffect]>;
164 def ARMeh_sjlj_longjmp: SDNode<"ARMISD::EH_SJLJ_LONGJMP",
165 SDT_ARMEH_SJLJ_Longjmp,
166 [SDNPHasChain, SDNPSideEffect]>;
168 def ARMMemBarrierMCR : SDNode<"ARMISD::MEMBARRIER_MCR", SDT_ARMMEMBARRIER,
169 [SDNPHasChain, SDNPSideEffect]>;
170 def ARMPreload : SDNode<"ARMISD::PRELOAD", SDT_ARMPREFETCH,
171 [SDNPHasChain, SDNPMayLoad, SDNPMayStore]>;
173 def ARMrbit : SDNode<"ARMISD::RBIT", SDTIntUnaryOp>;
175 def ARMtcret : SDNode<"ARMISD::TC_RETURN", SDT_ARMTCRET,
176 [SDNPHasChain, SDNPOptInGlue, SDNPVariadic]>;
178 def ARMbfi : SDNode<"ARMISD::BFI", SDT_ARMBFI>;
180 def ARMvmaxnm : SDNode<"ARMISD::VMAXNM", SDT_ARMVMAXNM, []>;
181 def ARMvminnm : SDNode<"ARMISD::VMINNM", SDT_ARMVMINNM, []>;
183 //===----------------------------------------------------------------------===//
184 // ARM Instruction Predicate Definitions.
186 def HasV4T : Predicate<"Subtarget->hasV4TOps()">,
187 AssemblerPredicate<"HasV4TOps", "armv4t">;
188 def NoV4T : Predicate<"!Subtarget->hasV4TOps()">;
189 def HasV5T : Predicate<"Subtarget->hasV5TOps()">,
190 AssemblerPredicate<"HasV5TOps", "armv5t">;
191 def HasV5TE : Predicate<"Subtarget->hasV5TEOps()">,
192 AssemblerPredicate<"HasV5TEOps", "armv5te">;
193 def HasV6 : Predicate<"Subtarget->hasV6Ops()">,
194 AssemblerPredicate<"HasV6Ops", "armv6">;
195 def NoV6 : Predicate<"!Subtarget->hasV6Ops()">;
196 def HasV6M : Predicate<"Subtarget->hasV6MOps()">,
197 AssemblerPredicate<"HasV6MOps",
198 "armv6m or armv6t2">;
199 def HasV6T2 : Predicate<"Subtarget->hasV6T2Ops()">,
200 AssemblerPredicate<"HasV6T2Ops", "armv6t2">;
201 def NoV6T2 : Predicate<"!Subtarget->hasV6T2Ops()">;
202 def HasV7 : Predicate<"Subtarget->hasV7Ops()">,
203 AssemblerPredicate<"HasV7Ops", "armv7">;
204 def HasV8 : Predicate<"Subtarget->hasV8Ops()">,
205 AssemblerPredicate<"HasV8Ops", "armv8">;
206 def PreV8 : Predicate<"!Subtarget->hasV8Ops()">,
207 AssemblerPredicate<"!HasV8Ops", "armv7 or earlier">;
208 def NoVFP : Predicate<"!Subtarget->hasVFP2()">;
209 def HasVFP2 : Predicate<"Subtarget->hasVFP2()">,
210 AssemblerPredicate<"FeatureVFP2", "VFP2">;
211 def HasVFP3 : Predicate<"Subtarget->hasVFP3()">,
212 AssemblerPredicate<"FeatureVFP3", "VFP3">;
213 def HasVFP4 : Predicate<"Subtarget->hasVFP4()">,
214 AssemblerPredicate<"FeatureVFP4", "VFP4">;
215 def HasDPVFP : Predicate<"!Subtarget->isFPOnlySP()">,
216 AssemblerPredicate<"!FeatureVFPOnlySP",
217 "double precision VFP">;
218 def HasFPARMv8 : Predicate<"Subtarget->hasFPARMv8()">,
219 AssemblerPredicate<"FeatureFPARMv8", "FPARMv8">;
220 def HasNEON : Predicate<"Subtarget->hasNEON()">,
221 AssemblerPredicate<"FeatureNEON", "NEON">;
222 def HasCrypto : Predicate<"Subtarget->hasCrypto()">,
223 AssemblerPredicate<"FeatureCrypto", "crypto">;
224 def HasCRC : Predicate<"Subtarget->hasCRC()">,
225 AssemblerPredicate<"FeatureCRC", "crc">;
226 def HasFP16 : Predicate<"Subtarget->hasFP16()">,
227 AssemblerPredicate<"FeatureFP16","half-float">;
228 def HasDivide : Predicate<"Subtarget->hasDivide()">,
229 AssemblerPredicate<"FeatureHWDiv", "divide in THUMB">;
230 def HasDivideInARM : Predicate<"Subtarget->hasDivideInARMMode()">,
231 AssemblerPredicate<"FeatureHWDivARM", "divide in ARM">;
232 def HasT2ExtractPack : Predicate<"Subtarget->hasT2ExtractPack()">,
233 AssemblerPredicate<"FeatureT2XtPk",
235 def HasThumb2DSP : Predicate<"Subtarget->hasThumb2DSP()">,
236 AssemblerPredicate<"FeatureDSPThumb2",
238 def HasDB : Predicate<"Subtarget->hasDataBarrier()">,
239 AssemblerPredicate<"FeatureDB",
241 def HasMP : Predicate<"Subtarget->hasMPExtension()">,
242 AssemblerPredicate<"FeatureMP",
244 def HasVirtualization: Predicate<"false">,
245 AssemblerPredicate<"FeatureVirtualization",
246 "virtualization-extensions">;
247 def HasTrustZone : Predicate<"Subtarget->hasTrustZone()">,
248 AssemblerPredicate<"FeatureTrustZone",
250 def HasZCZ : Predicate<"Subtarget->hasZeroCycleZeroing()">;
251 def UseNEONForFP : Predicate<"Subtarget->useNEONForSinglePrecisionFP()">;
252 def DontUseNEONForFP : Predicate<"!Subtarget->useNEONForSinglePrecisionFP()">;
253 def IsThumb : Predicate<"Subtarget->isThumb()">,
254 AssemblerPredicate<"ModeThumb", "thumb">;
255 def IsThumb1Only : Predicate<"Subtarget->isThumb1Only()">;
256 def IsThumb2 : Predicate<"Subtarget->isThumb2()">,
257 AssemblerPredicate<"ModeThumb,FeatureThumb2",
259 def IsMClass : Predicate<"Subtarget->isMClass()">,
260 AssemblerPredicate<"FeatureMClass", "armv*m">;
261 def IsNotMClass : Predicate<"!Subtarget->isMClass()">,
262 AssemblerPredicate<"!FeatureMClass",
264 def IsARM : Predicate<"!Subtarget->isThumb()">,
265 AssemblerPredicate<"!ModeThumb", "arm-mode">;
266 def IsIOS : Predicate<"Subtarget->isTargetIOS()">;
267 def IsNotIOS : Predicate<"!Subtarget->isTargetIOS()">;
268 def IsMachO : Predicate<"Subtarget->isTargetMachO()">;
269 def IsNotMachO : Predicate<"!Subtarget->isTargetMachO()">;
270 def IsNaCl : Predicate<"Subtarget->isTargetNaCl()">;
271 def UseNaClTrap : Predicate<"Subtarget->useNaClTrap()">,
272 AssemblerPredicate<"FeatureNaClTrap", "NaCl">;
273 def DontUseNaClTrap : Predicate<"!Subtarget->useNaClTrap()">;
275 // FIXME: Eventually this will be just "hasV6T2Ops".
276 def UseMovt : Predicate<"Subtarget->useMovt(*MF)">;
277 def DontUseMovt : Predicate<"!Subtarget->useMovt(*MF)">;
278 def UseFPVMLx : Predicate<"Subtarget->useFPVMLx()">;
279 def UseMulOps : Predicate<"Subtarget->useMulOps()">;
281 // Prefer fused MAC for fp mul + add over fp VMLA / VMLS if they are available.
282 // But only select them if more precision in FP computation is allowed.
283 // Do not use them for Darwin platforms.
284 def UseFusedMAC : Predicate<"(TM.Options.AllowFPOpFusion =="
285 " FPOpFusion::Fast && "
286 " Subtarget->hasVFP4()) && "
287 "!Subtarget->isTargetDarwin()">;
288 def DontUseFusedMAC : Predicate<"!(TM.Options.AllowFPOpFusion =="
289 " FPOpFusion::Fast &&"
290 " Subtarget->hasVFP4()) || "
291 "Subtarget->isTargetDarwin()">;
293 // VGETLNi32 is microcoded on Swift - prefer VMOV.
294 def HasFastVGETLNi32 : Predicate<"!Subtarget->isSwift()">;
295 def HasSlowVGETLNi32 : Predicate<"Subtarget->isSwift()">;
297 // VDUP.32 is microcoded on Swift - prefer VMOV.
298 def HasFastVDUP32 : Predicate<"!Subtarget->isSwift()">;
299 def HasSlowVDUP32 : Predicate<"Subtarget->isSwift()">;
301 // Cortex-A9 prefers VMOVSR to VMOVDRR even when using NEON for scalar FP, as
302 // this allows more effective execution domain optimization. See
303 // setExecutionDomain().
304 def UseVMOVSR : Predicate<"Subtarget->isCortexA9() || !Subtarget->useNEONForSinglePrecisionFP()">;
305 def DontUseVMOVSR : Predicate<"!Subtarget->isCortexA9() && Subtarget->useNEONForSinglePrecisionFP()">;
307 def IsLE : Predicate<"getTargetLowering()->isLittleEndian()">;
308 def IsBE : Predicate<"getTargetLowering()->isBigEndian()">;
310 //===----------------------------------------------------------------------===//
311 // ARM Flag Definitions.
313 class RegConstraint<string C> {
314 string Constraints = C;
317 //===----------------------------------------------------------------------===//
318 // ARM specific transformation functions and pattern fragments.
321 // imm_neg_XFORM - Return the negation of an i32 immediate value.
322 def imm_neg_XFORM : SDNodeXForm<imm, [{
323 return CurDAG->getTargetConstant(-(int)N->getZExtValue(), MVT::i32);
326 // imm_not_XFORM - Return the complement of a i32 immediate value.
327 def imm_not_XFORM : SDNodeXForm<imm, [{
328 return CurDAG->getTargetConstant(~(int)N->getZExtValue(), MVT::i32);
331 /// imm16_31 predicate - True if the 32-bit immediate is in the range [16,31].
332 def imm16_31 : ImmLeaf<i32, [{
333 return (int32_t)Imm >= 16 && (int32_t)Imm < 32;
336 def so_imm_neg_asmoperand : AsmOperandClass { let Name = "ARMSOImmNeg"; }
337 def so_imm_neg : Operand<i32>, PatLeaf<(imm), [{
338 unsigned Value = -(unsigned)N->getZExtValue();
339 return Value && ARM_AM::getSOImmVal(Value) != -1;
341 let ParserMatchClass = so_imm_neg_asmoperand;
344 // Note: this pattern doesn't require an encoder method and such, as it's
345 // only used on aliases (Pat<> and InstAlias<>). The actual encoding
346 // is handled by the destination instructions, which use so_imm.
347 def so_imm_not_asmoperand : AsmOperandClass { let Name = "ARMSOImmNot"; }
348 def so_imm_not : Operand<i32>, PatLeaf<(imm), [{
349 return ARM_AM::getSOImmVal(~(uint32_t)N->getZExtValue()) != -1;
351 let ParserMatchClass = so_imm_not_asmoperand;
354 // sext_16_node predicate - True if the SDNode is sign-extended 16 or more bits.
355 def sext_16_node : PatLeaf<(i32 GPR:$a), [{
356 return CurDAG->ComputeNumSignBits(SDValue(N,0)) >= 17;
359 /// Split a 32-bit immediate into two 16 bit parts.
360 def hi16 : SDNodeXForm<imm, [{
361 return CurDAG->getTargetConstant((uint32_t)N->getZExtValue() >> 16, MVT::i32);
364 def lo16AllZero : PatLeaf<(i32 imm), [{
365 // Returns true if all low 16-bits are 0.
366 return (((uint32_t)N->getZExtValue()) & 0xFFFFUL) == 0;
369 class BinOpWithFlagFrag<dag res> :
370 PatFrag<(ops node:$LHS, node:$RHS, node:$FLAG), res>;
371 class BinOpFrag<dag res> : PatFrag<(ops node:$LHS, node:$RHS), res>;
372 class UnOpFrag <dag res> : PatFrag<(ops node:$Src), res>;
374 // An 'and' node with a single use.
375 def and_su : PatFrag<(ops node:$lhs, node:$rhs), (and node:$lhs, node:$rhs), [{
376 return N->hasOneUse();
379 // An 'xor' node with a single use.
380 def xor_su : PatFrag<(ops node:$lhs, node:$rhs), (xor node:$lhs, node:$rhs), [{
381 return N->hasOneUse();
384 // An 'fmul' node with a single use.
385 def fmul_su : PatFrag<(ops node:$lhs, node:$rhs), (fmul node:$lhs, node:$rhs),[{
386 return N->hasOneUse();
389 // An 'fadd' node which checks for single non-hazardous use.
390 def fadd_mlx : PatFrag<(ops node:$lhs, node:$rhs),(fadd node:$lhs, node:$rhs),[{
391 return hasNoVMLxHazardUse(N);
394 // An 'fsub' node which checks for single non-hazardous use.
395 def fsub_mlx : PatFrag<(ops node:$lhs, node:$rhs),(fsub node:$lhs, node:$rhs),[{
396 return hasNoVMLxHazardUse(N);
399 //===----------------------------------------------------------------------===//
400 // Operand Definitions.
403 // Immediate operands with a shared generic asm render method.
404 class ImmAsmOperand : AsmOperandClass { let RenderMethod = "addImmOperands"; }
407 // FIXME: rename brtarget to t2_brtarget
408 def brtarget : Operand<OtherVT> {
409 let EncoderMethod = "getBranchTargetOpValue";
410 let OperandType = "OPERAND_PCREL";
411 let DecoderMethod = "DecodeT2BROperand";
414 // FIXME: get rid of this one?
415 def uncondbrtarget : Operand<OtherVT> {
416 let EncoderMethod = "getUnconditionalBranchTargetOpValue";
417 let OperandType = "OPERAND_PCREL";
420 // Branch target for ARM. Handles conditional/unconditional
421 def br_target : Operand<OtherVT> {
422 let EncoderMethod = "getARMBranchTargetOpValue";
423 let OperandType = "OPERAND_PCREL";
427 // FIXME: rename bltarget to t2_bl_target?
428 def bltarget : Operand<i32> {
429 // Encoded the same as branch targets.
430 let EncoderMethod = "getBranchTargetOpValue";
431 let OperandType = "OPERAND_PCREL";
434 // Call target for ARM. Handles conditional/unconditional
435 // FIXME: rename bl_target to t2_bltarget?
436 def bl_target : Operand<i32> {
437 let EncoderMethod = "getARMBLTargetOpValue";
438 let OperandType = "OPERAND_PCREL";
441 def blx_target : Operand<i32> {
442 let EncoderMethod = "getARMBLXTargetOpValue";
443 let OperandType = "OPERAND_PCREL";
446 // A list of registers separated by comma. Used by load/store multiple.
447 def RegListAsmOperand : AsmOperandClass { let Name = "RegList"; }
448 def reglist : Operand<i32> {
449 let EncoderMethod = "getRegisterListOpValue";
450 let ParserMatchClass = RegListAsmOperand;
451 let PrintMethod = "printRegisterList";
452 let DecoderMethod = "DecodeRegListOperand";
455 def GPRPairOp : RegisterOperand<GPRPair, "printGPRPairOperand">;
457 def DPRRegListAsmOperand : AsmOperandClass { let Name = "DPRRegList"; }
458 def dpr_reglist : Operand<i32> {
459 let EncoderMethod = "getRegisterListOpValue";
460 let ParserMatchClass = DPRRegListAsmOperand;
461 let PrintMethod = "printRegisterList";
462 let DecoderMethod = "DecodeDPRRegListOperand";
465 def SPRRegListAsmOperand : AsmOperandClass { let Name = "SPRRegList"; }
466 def spr_reglist : Operand<i32> {
467 let EncoderMethod = "getRegisterListOpValue";
468 let ParserMatchClass = SPRRegListAsmOperand;
469 let PrintMethod = "printRegisterList";
470 let DecoderMethod = "DecodeSPRRegListOperand";
473 // An operand for the CONSTPOOL_ENTRY pseudo-instruction.
474 def cpinst_operand : Operand<i32> {
475 let PrintMethod = "printCPInstOperand";
479 def pclabel : Operand<i32> {
480 let PrintMethod = "printPCLabel";
483 // ADR instruction labels.
484 def AdrLabelAsmOperand : AsmOperandClass { let Name = "AdrLabel"; }
485 def adrlabel : Operand<i32> {
486 let EncoderMethod = "getAdrLabelOpValue";
487 let ParserMatchClass = AdrLabelAsmOperand;
488 let PrintMethod = "printAdrLabelOperand<0>";
491 def neon_vcvt_imm32 : Operand<i32> {
492 let EncoderMethod = "getNEONVcvtImm32OpValue";
493 let DecoderMethod = "DecodeVCVTImmOperand";
496 // rot_imm: An integer that encodes a rotate amount. Must be 8, 16, or 24.
497 def rot_imm_XFORM: SDNodeXForm<imm, [{
498 switch (N->getZExtValue()){
499 default: llvm_unreachable(nullptr);
500 case 0: return CurDAG->getTargetConstant(0, MVT::i32);
501 case 8: return CurDAG->getTargetConstant(1, MVT::i32);
502 case 16: return CurDAG->getTargetConstant(2, MVT::i32);
503 case 24: return CurDAG->getTargetConstant(3, MVT::i32);
506 def RotImmAsmOperand : AsmOperandClass {
508 let ParserMethod = "parseRotImm";
510 def rot_imm : Operand<i32>, PatLeaf<(i32 imm), [{
511 int32_t v = N->getZExtValue();
512 return v == 8 || v == 16 || v == 24; }],
514 let PrintMethod = "printRotImmOperand";
515 let ParserMatchClass = RotImmAsmOperand;
518 // shift_imm: An integer that encodes a shift amount and the type of shift
519 // (asr or lsl). The 6-bit immediate encodes as:
522 // {4-0} imm5 shift amount.
523 // asr #32 encoded as imm5 == 0.
524 def ShifterImmAsmOperand : AsmOperandClass {
525 let Name = "ShifterImm";
526 let ParserMethod = "parseShifterImm";
528 def shift_imm : Operand<i32> {
529 let PrintMethod = "printShiftImmOperand";
530 let ParserMatchClass = ShifterImmAsmOperand;
533 // shifter_operand operands: so_reg_reg, so_reg_imm, and so_imm.
534 def ShiftedRegAsmOperand : AsmOperandClass { let Name = "RegShiftedReg"; }
535 def so_reg_reg : Operand<i32>, // reg reg imm
536 ComplexPattern<i32, 3, "SelectRegShifterOperand",
537 [shl, srl, sra, rotr]> {
538 let EncoderMethod = "getSORegRegOpValue";
539 let PrintMethod = "printSORegRegOperand";
540 let DecoderMethod = "DecodeSORegRegOperand";
541 let ParserMatchClass = ShiftedRegAsmOperand;
542 let MIOperandInfo = (ops GPRnopc, GPRnopc, i32imm);
545 def ShiftedImmAsmOperand : AsmOperandClass { let Name = "RegShiftedImm"; }
546 def so_reg_imm : Operand<i32>, // reg imm
547 ComplexPattern<i32, 2, "SelectImmShifterOperand",
548 [shl, srl, sra, rotr]> {
549 let EncoderMethod = "getSORegImmOpValue";
550 let PrintMethod = "printSORegImmOperand";
551 let DecoderMethod = "DecodeSORegImmOperand";
552 let ParserMatchClass = ShiftedImmAsmOperand;
553 let MIOperandInfo = (ops GPR, i32imm);
556 // FIXME: Does this need to be distinct from so_reg?
557 def shift_so_reg_reg : Operand<i32>, // reg reg imm
558 ComplexPattern<i32, 3, "SelectShiftRegShifterOperand",
559 [shl,srl,sra,rotr]> {
560 let EncoderMethod = "getSORegRegOpValue";
561 let PrintMethod = "printSORegRegOperand";
562 let DecoderMethod = "DecodeSORegRegOperand";
563 let ParserMatchClass = ShiftedRegAsmOperand;
564 let MIOperandInfo = (ops GPR, GPR, i32imm);
567 // FIXME: Does this need to be distinct from so_reg?
568 def shift_so_reg_imm : Operand<i32>, // reg reg imm
569 ComplexPattern<i32, 2, "SelectShiftImmShifterOperand",
570 [shl,srl,sra,rotr]> {
571 let EncoderMethod = "getSORegImmOpValue";
572 let PrintMethod = "printSORegImmOperand";
573 let DecoderMethod = "DecodeSORegImmOperand";
574 let ParserMatchClass = ShiftedImmAsmOperand;
575 let MIOperandInfo = (ops GPR, i32imm);
579 // so_imm - Match a 32-bit shifter_operand immediate operand, which is an
580 // 8-bit immediate rotated by an arbitrary number of bits.
581 def SOImmAsmOperand: ImmAsmOperand { let Name = "ARMSOImm"; }
582 def so_imm : Operand<i32>, ImmLeaf<i32, [{
583 return ARM_AM::getSOImmVal(Imm) != -1;
585 let EncoderMethod = "getSOImmOpValue";
586 let ParserMatchClass = SOImmAsmOperand;
587 let DecoderMethod = "DecodeSOImmOperand";
590 // Break so_imm's up into two pieces. This handles immediates with up to 16
591 // bits set in them. This uses so_imm2part to match and so_imm2part_[12] to
592 // get the first/second pieces.
593 def so_imm2part : PatLeaf<(imm), [{
594 return ARM_AM::isSOImmTwoPartVal((unsigned)N->getZExtValue());
597 /// arm_i32imm - True for +V6T2, or true only if so_imm2part is true.
599 def arm_i32imm : PatLeaf<(imm), [{
600 if (Subtarget->useMovt(*MF))
602 return ARM_AM::isSOImmTwoPartVal((unsigned)N->getZExtValue());
605 /// imm0_1 predicate - Immediate in the range [0,1].
606 def Imm0_1AsmOperand: ImmAsmOperand { let Name = "Imm0_1"; }
607 def imm0_1 : Operand<i32> { let ParserMatchClass = Imm0_1AsmOperand; }
609 /// imm0_3 predicate - Immediate in the range [0,3].
610 def Imm0_3AsmOperand: ImmAsmOperand { let Name = "Imm0_3"; }
611 def imm0_3 : Operand<i32> { let ParserMatchClass = Imm0_3AsmOperand; }
613 /// imm0_7 predicate - Immediate in the range [0,7].
614 def Imm0_7AsmOperand: ImmAsmOperand { let Name = "Imm0_7"; }
615 def imm0_7 : Operand<i32>, ImmLeaf<i32, [{
616 return Imm >= 0 && Imm < 8;
618 let ParserMatchClass = Imm0_7AsmOperand;
621 /// imm8 predicate - Immediate is exactly 8.
622 def Imm8AsmOperand: ImmAsmOperand { let Name = "Imm8"; }
623 def imm8 : Operand<i32>, ImmLeaf<i32, [{ return Imm == 8; }]> {
624 let ParserMatchClass = Imm8AsmOperand;
627 /// imm16 predicate - Immediate is exactly 16.
628 def Imm16AsmOperand: ImmAsmOperand { let Name = "Imm16"; }
629 def imm16 : Operand<i32>, ImmLeaf<i32, [{ return Imm == 16; }]> {
630 let ParserMatchClass = Imm16AsmOperand;
633 /// imm32 predicate - Immediate is exactly 32.
634 def Imm32AsmOperand: ImmAsmOperand { let Name = "Imm32"; }
635 def imm32 : Operand<i32>, ImmLeaf<i32, [{ return Imm == 32; }]> {
636 let ParserMatchClass = Imm32AsmOperand;
639 def imm8_or_16 : ImmLeaf<i32, [{ return Imm == 8 || Imm == 16;}]>;
641 /// imm1_7 predicate - Immediate in the range [1,7].
642 def Imm1_7AsmOperand: ImmAsmOperand { let Name = "Imm1_7"; }
643 def imm1_7 : Operand<i32>, ImmLeaf<i32, [{ return Imm > 0 && Imm < 8; }]> {
644 let ParserMatchClass = Imm1_7AsmOperand;
647 /// imm1_15 predicate - Immediate in the range [1,15].
648 def Imm1_15AsmOperand: ImmAsmOperand { let Name = "Imm1_15"; }
649 def imm1_15 : Operand<i32>, ImmLeaf<i32, [{ return Imm > 0 && Imm < 16; }]> {
650 let ParserMatchClass = Imm1_15AsmOperand;
653 /// imm1_31 predicate - Immediate in the range [1,31].
654 def Imm1_31AsmOperand: ImmAsmOperand { let Name = "Imm1_31"; }
655 def imm1_31 : Operand<i32>, ImmLeaf<i32, [{ return Imm > 0 && Imm < 32; }]> {
656 let ParserMatchClass = Imm1_31AsmOperand;
659 /// imm0_15 predicate - Immediate in the range [0,15].
660 def Imm0_15AsmOperand: ImmAsmOperand {
661 let Name = "Imm0_15";
662 let DiagnosticType = "ImmRange0_15";
664 def imm0_15 : Operand<i32>, ImmLeaf<i32, [{
665 return Imm >= 0 && Imm < 16;
667 let ParserMatchClass = Imm0_15AsmOperand;
670 /// imm0_31 predicate - True if the 32-bit immediate is in the range [0,31].
671 def Imm0_31AsmOperand: ImmAsmOperand { let Name = "Imm0_31"; }
672 def imm0_31 : Operand<i32>, ImmLeaf<i32, [{
673 return Imm >= 0 && Imm < 32;
675 let ParserMatchClass = Imm0_31AsmOperand;
678 /// imm0_32 predicate - True if the 32-bit immediate is in the range [0,32].
679 def Imm0_32AsmOperand: ImmAsmOperand { let Name = "Imm0_32"; }
680 def imm0_32 : Operand<i32>, ImmLeaf<i32, [{
681 return Imm >= 0 && Imm < 32;
683 let ParserMatchClass = Imm0_32AsmOperand;
686 /// imm0_63 predicate - True if the 32-bit immediate is in the range [0,63].
687 def Imm0_63AsmOperand: ImmAsmOperand { let Name = "Imm0_63"; }
688 def imm0_63 : Operand<i32>, ImmLeaf<i32, [{
689 return Imm >= 0 && Imm < 64;
691 let ParserMatchClass = Imm0_63AsmOperand;
694 /// imm0_239 predicate - Immediate in the range [0,239].
695 def Imm0_239AsmOperand : ImmAsmOperand {
696 let Name = "Imm0_239";
697 let DiagnosticType = "ImmRange0_239";
699 def imm0_239 : Operand<i32>, ImmLeaf<i32, [{ return Imm >= 0 && Imm < 240; }]> {
700 let ParserMatchClass = Imm0_239AsmOperand;
703 /// imm0_255 predicate - Immediate in the range [0,255].
704 def Imm0_255AsmOperand : ImmAsmOperand { let Name = "Imm0_255"; }
705 def imm0_255 : Operand<i32>, ImmLeaf<i32, [{ return Imm >= 0 && Imm < 256; }]> {
706 let ParserMatchClass = Imm0_255AsmOperand;
709 /// imm0_65535 - An immediate is in the range [0.65535].
710 def Imm0_65535AsmOperand: ImmAsmOperand { let Name = "Imm0_65535"; }
711 def imm0_65535 : Operand<i32>, ImmLeaf<i32, [{
712 return Imm >= 0 && Imm < 65536;
714 let ParserMatchClass = Imm0_65535AsmOperand;
717 // imm0_65535_neg - An immediate whose negative value is in the range [0.65535].
718 def imm0_65535_neg : Operand<i32>, ImmLeaf<i32, [{
719 return -Imm >= 0 && -Imm < 65536;
722 // imm0_65535_expr - For movt/movw - 16-bit immediate that can also reference
723 // a relocatable expression.
725 // FIXME: This really needs a Thumb version separate from the ARM version.
726 // While the range is the same, and can thus use the same match class,
727 // the encoding is different so it should have a different encoder method.
728 def Imm0_65535ExprAsmOperand: ImmAsmOperand { let Name = "Imm0_65535Expr"; }
729 def imm0_65535_expr : Operand<i32> {
730 let EncoderMethod = "getHiLo16ImmOpValue";
731 let ParserMatchClass = Imm0_65535ExprAsmOperand;
734 def Imm256_65535ExprAsmOperand: ImmAsmOperand { let Name = "Imm256_65535Expr"; }
735 def imm256_65535_expr : Operand<i32> {
736 let ParserMatchClass = Imm256_65535ExprAsmOperand;
739 /// imm24b - True if the 32-bit immediate is encodable in 24 bits.
740 def Imm24bitAsmOperand: ImmAsmOperand { let Name = "Imm24bit"; }
741 def imm24b : Operand<i32>, ImmLeaf<i32, [{
742 return Imm >= 0 && Imm <= 0xffffff;
744 let ParserMatchClass = Imm24bitAsmOperand;
748 /// bf_inv_mask_imm predicate - An AND mask to clear an arbitrary width bitfield
750 def BitfieldAsmOperand : AsmOperandClass {
751 let Name = "Bitfield";
752 let ParserMethod = "parseBitfield";
755 def bf_inv_mask_imm : Operand<i32>,
757 return ARM::isBitFieldInvertedMask(N->getZExtValue());
759 let EncoderMethod = "getBitfieldInvertedMaskOpValue";
760 let PrintMethod = "printBitfieldInvMaskImmOperand";
761 let DecoderMethod = "DecodeBitfieldMaskOperand";
762 let ParserMatchClass = BitfieldAsmOperand;
765 def imm1_32_XFORM: SDNodeXForm<imm, [{
766 return CurDAG->getTargetConstant((int)N->getZExtValue() - 1, MVT::i32);
768 def Imm1_32AsmOperand: AsmOperandClass { let Name = "Imm1_32"; }
769 def imm1_32 : Operand<i32>, PatLeaf<(imm), [{
770 uint64_t Imm = N->getZExtValue();
771 return Imm > 0 && Imm <= 32;
774 let PrintMethod = "printImmPlusOneOperand";
775 let ParserMatchClass = Imm1_32AsmOperand;
778 def imm1_16_XFORM: SDNodeXForm<imm, [{
779 return CurDAG->getTargetConstant((int)N->getZExtValue() - 1, MVT::i32);
781 def Imm1_16AsmOperand: AsmOperandClass { let Name = "Imm1_16"; }
782 def imm1_16 : Operand<i32>, PatLeaf<(imm), [{ return Imm > 0 && Imm <= 16; }],
784 let PrintMethod = "printImmPlusOneOperand";
785 let ParserMatchClass = Imm1_16AsmOperand;
788 // Define ARM specific addressing modes.
789 // addrmode_imm12 := reg +/- imm12
791 def MemImm12OffsetAsmOperand : AsmOperandClass { let Name = "MemImm12Offset"; }
792 class AddrMode_Imm12 : Operand<i32>,
793 ComplexPattern<i32, 2, "SelectAddrModeImm12", []> {
794 // 12-bit immediate operand. Note that instructions using this encode
795 // #0 and #-0 differently. We flag #-0 as the magic value INT32_MIN. All other
796 // immediate values are as normal.
798 let EncoderMethod = "getAddrModeImm12OpValue";
799 let DecoderMethod = "DecodeAddrModeImm12Operand";
800 let ParserMatchClass = MemImm12OffsetAsmOperand;
801 let MIOperandInfo = (ops GPR:$base, i32imm:$offsimm);
804 def addrmode_imm12 : AddrMode_Imm12 {
805 let PrintMethod = "printAddrModeImm12Operand<false>";
808 def addrmode_imm12_pre : AddrMode_Imm12 {
809 let PrintMethod = "printAddrModeImm12Operand<true>";
812 // ldst_so_reg := reg +/- reg shop imm
814 def MemRegOffsetAsmOperand : AsmOperandClass { let Name = "MemRegOffset"; }
815 def ldst_so_reg : Operand<i32>,
816 ComplexPattern<i32, 3, "SelectLdStSOReg", []> {
817 let EncoderMethod = "getLdStSORegOpValue";
818 // FIXME: Simplify the printer
819 let PrintMethod = "printAddrMode2Operand";
820 let DecoderMethod = "DecodeSORegMemOperand";
821 let ParserMatchClass = MemRegOffsetAsmOperand;
822 let MIOperandInfo = (ops GPR:$base, GPRnopc:$offsreg, i32imm:$shift);
825 // postidx_imm8 := +/- [0,255]
828 // {8} 1 is imm8 is non-negative. 0 otherwise.
829 // {7-0} [0,255] imm8 value.
830 def PostIdxImm8AsmOperand : AsmOperandClass { let Name = "PostIdxImm8"; }
831 def postidx_imm8 : Operand<i32> {
832 let PrintMethod = "printPostIdxImm8Operand";
833 let ParserMatchClass = PostIdxImm8AsmOperand;
834 let MIOperandInfo = (ops i32imm);
837 // postidx_imm8s4 := +/- [0,1020]
840 // {8} 1 is imm8 is non-negative. 0 otherwise.
841 // {7-0} [0,255] imm8 value, scaled by 4.
842 def PostIdxImm8s4AsmOperand : AsmOperandClass { let Name = "PostIdxImm8s4"; }
843 def postidx_imm8s4 : Operand<i32> {
844 let PrintMethod = "printPostIdxImm8s4Operand";
845 let ParserMatchClass = PostIdxImm8s4AsmOperand;
846 let MIOperandInfo = (ops i32imm);
850 // postidx_reg := +/- reg
852 def PostIdxRegAsmOperand : AsmOperandClass {
853 let Name = "PostIdxReg";
854 let ParserMethod = "parsePostIdxReg";
856 def postidx_reg : Operand<i32> {
857 let EncoderMethod = "getPostIdxRegOpValue";
858 let DecoderMethod = "DecodePostIdxReg";
859 let PrintMethod = "printPostIdxRegOperand";
860 let ParserMatchClass = PostIdxRegAsmOperand;
861 let MIOperandInfo = (ops GPRnopc, i32imm);
865 // addrmode2 := reg +/- imm12
866 // := reg +/- reg shop imm
868 // FIXME: addrmode2 should be refactored the rest of the way to always
869 // use explicit imm vs. reg versions above (addrmode_imm12 and ldst_so_reg).
870 def AddrMode2AsmOperand : AsmOperandClass { let Name = "AddrMode2"; }
871 def addrmode2 : Operand<i32>,
872 ComplexPattern<i32, 3, "SelectAddrMode2", []> {
873 let EncoderMethod = "getAddrMode2OpValue";
874 let PrintMethod = "printAddrMode2Operand";
875 let ParserMatchClass = AddrMode2AsmOperand;
876 let MIOperandInfo = (ops GPR:$base, GPR:$offsreg, i32imm:$offsimm);
879 def PostIdxRegShiftedAsmOperand : AsmOperandClass {
880 let Name = "PostIdxRegShifted";
881 let ParserMethod = "parsePostIdxReg";
883 def am2offset_reg : Operand<i32>,
884 ComplexPattern<i32, 2, "SelectAddrMode2OffsetReg",
885 [], [SDNPWantRoot]> {
886 let EncoderMethod = "getAddrMode2OffsetOpValue";
887 let PrintMethod = "printAddrMode2OffsetOperand";
888 // When using this for assembly, it's always as a post-index offset.
889 let ParserMatchClass = PostIdxRegShiftedAsmOperand;
890 let MIOperandInfo = (ops GPRnopc, i32imm);
893 // FIXME: am2offset_imm should only need the immediate, not the GPR. Having
894 // the GPR is purely vestigal at this point.
895 def AM2OffsetImmAsmOperand : AsmOperandClass { let Name = "AM2OffsetImm"; }
896 def am2offset_imm : Operand<i32>,
897 ComplexPattern<i32, 2, "SelectAddrMode2OffsetImm",
898 [], [SDNPWantRoot]> {
899 let EncoderMethod = "getAddrMode2OffsetOpValue";
900 let PrintMethod = "printAddrMode2OffsetOperand";
901 let ParserMatchClass = AM2OffsetImmAsmOperand;
902 let MIOperandInfo = (ops GPRnopc, i32imm);
906 // addrmode3 := reg +/- reg
907 // addrmode3 := reg +/- imm8
909 // FIXME: split into imm vs. reg versions.
910 def AddrMode3AsmOperand : AsmOperandClass { let Name = "AddrMode3"; }
911 class AddrMode3 : Operand<i32>,
912 ComplexPattern<i32, 3, "SelectAddrMode3", []> {
913 let EncoderMethod = "getAddrMode3OpValue";
914 let ParserMatchClass = AddrMode3AsmOperand;
915 let MIOperandInfo = (ops GPR:$base, GPR:$offsreg, i32imm:$offsimm);
918 def addrmode3 : AddrMode3
920 let PrintMethod = "printAddrMode3Operand<false>";
923 def addrmode3_pre : AddrMode3
925 let PrintMethod = "printAddrMode3Operand<true>";
928 // FIXME: split into imm vs. reg versions.
929 // FIXME: parser method to handle +/- register.
930 def AM3OffsetAsmOperand : AsmOperandClass {
931 let Name = "AM3Offset";
932 let ParserMethod = "parseAM3Offset";
934 def am3offset : Operand<i32>,
935 ComplexPattern<i32, 2, "SelectAddrMode3Offset",
936 [], [SDNPWantRoot]> {
937 let EncoderMethod = "getAddrMode3OffsetOpValue";
938 let PrintMethod = "printAddrMode3OffsetOperand";
939 let ParserMatchClass = AM3OffsetAsmOperand;
940 let MIOperandInfo = (ops GPR, i32imm);
943 // ldstm_mode := {ia, ib, da, db}
945 def ldstm_mode : OptionalDefOperand<OtherVT, (ops i32), (ops (i32 1))> {
946 let EncoderMethod = "getLdStmModeOpValue";
947 let PrintMethod = "printLdStmModeOperand";
950 // addrmode5 := reg +/- imm8*4
952 def AddrMode5AsmOperand : AsmOperandClass { let Name = "AddrMode5"; }
953 class AddrMode5 : Operand<i32>,
954 ComplexPattern<i32, 2, "SelectAddrMode5", []> {
955 let EncoderMethod = "getAddrMode5OpValue";
956 let DecoderMethod = "DecodeAddrMode5Operand";
957 let ParserMatchClass = AddrMode5AsmOperand;
958 let MIOperandInfo = (ops GPR:$base, i32imm);
961 def addrmode5 : AddrMode5 {
962 let PrintMethod = "printAddrMode5Operand<false>";
965 def addrmode5_pre : AddrMode5 {
966 let PrintMethod = "printAddrMode5Operand<true>";
969 // addrmode6 := reg with optional alignment
971 def AddrMode6AsmOperand : AsmOperandClass { let Name = "AlignedMemory"; }
972 def addrmode6 : Operand<i32>,
973 ComplexPattern<i32, 2, "SelectAddrMode6", [], [SDNPWantParent]>{
974 let PrintMethod = "printAddrMode6Operand";
975 let MIOperandInfo = (ops GPR:$addr, i32imm:$align);
976 let EncoderMethod = "getAddrMode6AddressOpValue";
977 let DecoderMethod = "DecodeAddrMode6Operand";
978 let ParserMatchClass = AddrMode6AsmOperand;
981 def am6offset : Operand<i32>,
982 ComplexPattern<i32, 1, "SelectAddrMode6Offset",
983 [], [SDNPWantRoot]> {
984 let PrintMethod = "printAddrMode6OffsetOperand";
985 let MIOperandInfo = (ops GPR);
986 let EncoderMethod = "getAddrMode6OffsetOpValue";
987 let DecoderMethod = "DecodeGPRRegisterClass";
990 // Special version of addrmode6 to handle alignment encoding for VST1/VLD1
991 // (single element from one lane) for size 32.
992 def addrmode6oneL32 : Operand<i32>,
993 ComplexPattern<i32, 2, "SelectAddrMode6", [], [SDNPWantParent]>{
994 let PrintMethod = "printAddrMode6Operand";
995 let MIOperandInfo = (ops GPR:$addr, i32imm);
996 let EncoderMethod = "getAddrMode6OneLane32AddressOpValue";
999 // Base class for addrmode6 with specific alignment restrictions.
1000 class AddrMode6Align : Operand<i32>,
1001 ComplexPattern<i32, 2, "SelectAddrMode6", [], [SDNPWantParent]>{
1002 let PrintMethod = "printAddrMode6Operand";
1003 let MIOperandInfo = (ops GPR:$addr, i32imm:$align);
1004 let EncoderMethod = "getAddrMode6AddressOpValue";
1005 let DecoderMethod = "DecodeAddrMode6Operand";
1008 // Special version of addrmode6 to handle no allowed alignment encoding for
1009 // VLD/VST instructions and checking the alignment is not specified.
1010 def AddrMode6AlignNoneAsmOperand : AsmOperandClass {
1011 let Name = "AlignedMemoryNone";
1012 let DiagnosticType = "AlignedMemoryRequiresNone";
1014 def addrmode6alignNone : AddrMode6Align {
1015 // The alignment specifier can only be omitted.
1016 let ParserMatchClass = AddrMode6AlignNoneAsmOperand;
1019 // Special version of addrmode6 to handle 16-bit alignment encoding for
1020 // VLD/VST instructions and checking the alignment value.
1021 def AddrMode6Align16AsmOperand : AsmOperandClass {
1022 let Name = "AlignedMemory16";
1023 let DiagnosticType = "AlignedMemoryRequires16";
1025 def addrmode6align16 : AddrMode6Align {
1026 // The alignment specifier can only be 16 or omitted.
1027 let ParserMatchClass = AddrMode6Align16AsmOperand;
1030 // Special version of addrmode6 to handle 32-bit alignment encoding for
1031 // VLD/VST instructions and checking the alignment value.
1032 def AddrMode6Align32AsmOperand : AsmOperandClass {
1033 let Name = "AlignedMemory32";
1034 let DiagnosticType = "AlignedMemoryRequires32";
1036 def addrmode6align32 : AddrMode6Align {
1037 // The alignment specifier can only be 32 or omitted.
1038 let ParserMatchClass = AddrMode6Align32AsmOperand;
1041 // Special version of addrmode6 to handle 64-bit alignment encoding for
1042 // VLD/VST instructions and checking the alignment value.
1043 def AddrMode6Align64AsmOperand : AsmOperandClass {
1044 let Name = "AlignedMemory64";
1045 let DiagnosticType = "AlignedMemoryRequires64";
1047 def addrmode6align64 : AddrMode6Align {
1048 // The alignment specifier can only be 64 or omitted.
1049 let ParserMatchClass = AddrMode6Align64AsmOperand;
1052 // Special version of addrmode6 to handle 64-bit or 128-bit alignment encoding
1053 // for VLD/VST instructions and checking the alignment value.
1054 def AddrMode6Align64or128AsmOperand : AsmOperandClass {
1055 let Name = "AlignedMemory64or128";
1056 let DiagnosticType = "AlignedMemoryRequires64or128";
1058 def addrmode6align64or128 : AddrMode6Align {
1059 // The alignment specifier can only be 64, 128 or omitted.
1060 let ParserMatchClass = AddrMode6Align64or128AsmOperand;
1063 // Special version of addrmode6 to handle 64-bit, 128-bit or 256-bit alignment
1064 // encoding for VLD/VST instructions and checking the alignment value.
1065 def AddrMode6Align64or128or256AsmOperand : AsmOperandClass {
1066 let Name = "AlignedMemory64or128or256";
1067 let DiagnosticType = "AlignedMemoryRequires64or128or256";
1069 def addrmode6align64or128or256 : AddrMode6Align {
1070 // The alignment specifier can only be 64, 128, 256 or omitted.
1071 let ParserMatchClass = AddrMode6Align64or128or256AsmOperand;
1074 // Special version of addrmode6 to handle alignment encoding for VLD-dup
1075 // instructions, specifically VLD4-dup.
1076 def addrmode6dup : Operand<i32>,
1077 ComplexPattern<i32, 2, "SelectAddrMode6", [], [SDNPWantParent]>{
1078 let PrintMethod = "printAddrMode6Operand";
1079 let MIOperandInfo = (ops GPR:$addr, i32imm);
1080 let EncoderMethod = "getAddrMode6DupAddressOpValue";
1081 // FIXME: This is close, but not quite right. The alignment specifier is
1083 let ParserMatchClass = AddrMode6AsmOperand;
1086 // Base class for addrmode6dup with specific alignment restrictions.
1087 class AddrMode6DupAlign : Operand<i32>,
1088 ComplexPattern<i32, 2, "SelectAddrMode6", [], [SDNPWantParent]>{
1089 let PrintMethod = "printAddrMode6Operand";
1090 let MIOperandInfo = (ops GPR:$addr, i32imm);
1091 let EncoderMethod = "getAddrMode6DupAddressOpValue";
1094 // Special version of addrmode6 to handle no allowed alignment encoding for
1095 // VLD-dup instruction and checking the alignment is not specified.
1096 def AddrMode6dupAlignNoneAsmOperand : AsmOperandClass {
1097 let Name = "DupAlignedMemoryNone";
1098 let DiagnosticType = "DupAlignedMemoryRequiresNone";
1100 def addrmode6dupalignNone : AddrMode6DupAlign {
1101 // The alignment specifier can only be omitted.
1102 let ParserMatchClass = AddrMode6dupAlignNoneAsmOperand;
1105 // Special version of addrmode6 to handle 16-bit alignment encoding for VLD-dup
1106 // instruction and checking the alignment value.
1107 def AddrMode6dupAlign16AsmOperand : AsmOperandClass {
1108 let Name = "DupAlignedMemory16";
1109 let DiagnosticType = "DupAlignedMemoryRequires16";
1111 def addrmode6dupalign16 : AddrMode6DupAlign {
1112 // The alignment specifier can only be 16 or omitted.
1113 let ParserMatchClass = AddrMode6dupAlign16AsmOperand;
1116 // Special version of addrmode6 to handle 32-bit alignment encoding for VLD-dup
1117 // instruction and checking the alignment value.
1118 def AddrMode6dupAlign32AsmOperand : AsmOperandClass {
1119 let Name = "DupAlignedMemory32";
1120 let DiagnosticType = "DupAlignedMemoryRequires32";
1122 def addrmode6dupalign32 : AddrMode6DupAlign {
1123 // The alignment specifier can only be 32 or omitted.
1124 let ParserMatchClass = AddrMode6dupAlign32AsmOperand;
1127 // Special version of addrmode6 to handle 64-bit alignment encoding for VLD
1128 // instructions and checking the alignment value.
1129 def AddrMode6dupAlign64AsmOperand : AsmOperandClass {
1130 let Name = "DupAlignedMemory64";
1131 let DiagnosticType = "DupAlignedMemoryRequires64";
1133 def addrmode6dupalign64 : AddrMode6DupAlign {
1134 // The alignment specifier can only be 64 or omitted.
1135 let ParserMatchClass = AddrMode6dupAlign64AsmOperand;
1138 // Special version of addrmode6 to handle 64-bit or 128-bit alignment encoding
1139 // for VLD instructions and checking the alignment value.
1140 def AddrMode6dupAlign64or128AsmOperand : AsmOperandClass {
1141 let Name = "DupAlignedMemory64or128";
1142 let DiagnosticType = "DupAlignedMemoryRequires64or128";
1144 def addrmode6dupalign64or128 : AddrMode6DupAlign {
1145 // The alignment specifier can only be 64, 128 or omitted.
1146 let ParserMatchClass = AddrMode6dupAlign64or128AsmOperand;
1149 // addrmodepc := pc + reg
1151 def addrmodepc : Operand<i32>,
1152 ComplexPattern<i32, 2, "SelectAddrModePC", []> {
1153 let PrintMethod = "printAddrModePCOperand";
1154 let MIOperandInfo = (ops GPR, i32imm);
1157 // addr_offset_none := reg
1159 def MemNoOffsetAsmOperand : AsmOperandClass { let Name = "MemNoOffset"; }
1160 def addr_offset_none : Operand<i32>,
1161 ComplexPattern<i32, 1, "SelectAddrOffsetNone", []> {
1162 let PrintMethod = "printAddrMode7Operand";
1163 let DecoderMethod = "DecodeAddrMode7Operand";
1164 let ParserMatchClass = MemNoOffsetAsmOperand;
1165 let MIOperandInfo = (ops GPR:$base);
1168 def nohash_imm : Operand<i32> {
1169 let PrintMethod = "printNoHashImmediate";
1172 def CoprocNumAsmOperand : AsmOperandClass {
1173 let Name = "CoprocNum";
1174 let ParserMethod = "parseCoprocNumOperand";
1176 def p_imm : Operand<i32> {
1177 let PrintMethod = "printPImmediate";
1178 let ParserMatchClass = CoprocNumAsmOperand;
1179 let DecoderMethod = "DecodeCoprocessor";
1182 def CoprocRegAsmOperand : AsmOperandClass {
1183 let Name = "CoprocReg";
1184 let ParserMethod = "parseCoprocRegOperand";
1186 def c_imm : Operand<i32> {
1187 let PrintMethod = "printCImmediate";
1188 let ParserMatchClass = CoprocRegAsmOperand;
1190 def CoprocOptionAsmOperand : AsmOperandClass {
1191 let Name = "CoprocOption";
1192 let ParserMethod = "parseCoprocOptionOperand";
1194 def coproc_option_imm : Operand<i32> {
1195 let PrintMethod = "printCoprocOptionImm";
1196 let ParserMatchClass = CoprocOptionAsmOperand;
1199 //===----------------------------------------------------------------------===//
1201 include "ARMInstrFormats.td"
1203 //===----------------------------------------------------------------------===//
1204 // Multiclass helpers...
1207 /// AsI1_bin_irs - Defines a set of (op r, {so_imm|r|so_reg}) patterns for a
1208 /// binop that produces a value.
1209 let TwoOperandAliasConstraint = "$Rn = $Rd" in
1210 multiclass AsI1_bin_irs<bits<4> opcod, string opc,
1211 InstrItinClass iii, InstrItinClass iir, InstrItinClass iis,
1212 PatFrag opnode, bit Commutable = 0> {
1213 // The register-immediate version is re-materializable. This is useful
1214 // in particular for taking the address of a local.
1215 let isReMaterializable = 1 in {
1216 def ri : AsI1<opcod, (outs GPR:$Rd), (ins GPR:$Rn, so_imm:$imm), DPFrm,
1217 iii, opc, "\t$Rd, $Rn, $imm",
1218 [(set GPR:$Rd, (opnode GPR:$Rn, so_imm:$imm))]>,
1219 Sched<[WriteALU, ReadALU]> {
1224 let Inst{19-16} = Rn;
1225 let Inst{15-12} = Rd;
1226 let Inst{11-0} = imm;
1229 def rr : AsI1<opcod, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm), DPFrm,
1230 iir, opc, "\t$Rd, $Rn, $Rm",
1231 [(set GPR:$Rd, (opnode GPR:$Rn, GPR:$Rm))]>,
1232 Sched<[WriteALU, ReadALU, ReadALU]> {
1237 let isCommutable = Commutable;
1238 let Inst{19-16} = Rn;
1239 let Inst{15-12} = Rd;
1240 let Inst{11-4} = 0b00000000;
1244 def rsi : AsI1<opcod, (outs GPR:$Rd),
1245 (ins GPR:$Rn, so_reg_imm:$shift), DPSoRegImmFrm,
1246 iis, opc, "\t$Rd, $Rn, $shift",
1247 [(set GPR:$Rd, (opnode GPR:$Rn, so_reg_imm:$shift))]>,
1248 Sched<[WriteALUsi, ReadALU]> {
1253 let Inst{19-16} = Rn;
1254 let Inst{15-12} = Rd;
1255 let Inst{11-5} = shift{11-5};
1257 let Inst{3-0} = shift{3-0};
1260 def rsr : AsI1<opcod, (outs GPR:$Rd),
1261 (ins GPR:$Rn, so_reg_reg:$shift), DPSoRegRegFrm,
1262 iis, opc, "\t$Rd, $Rn, $shift",
1263 [(set GPR:$Rd, (opnode GPR:$Rn, so_reg_reg:$shift))]>,
1264 Sched<[WriteALUsr, ReadALUsr]> {
1269 let Inst{19-16} = Rn;
1270 let Inst{15-12} = Rd;
1271 let Inst{11-8} = shift{11-8};
1273 let Inst{6-5} = shift{6-5};
1275 let Inst{3-0} = shift{3-0};
1279 /// AsI1_rbin_irs - Same as AsI1_bin_irs except the order of operands are
1280 /// reversed. The 'rr' form is only defined for the disassembler; for codegen
1281 /// it is equivalent to the AsI1_bin_irs counterpart.
1282 let TwoOperandAliasConstraint = "$Rn = $Rd" in
1283 multiclass AsI1_rbin_irs<bits<4> opcod, string opc,
1284 InstrItinClass iii, InstrItinClass iir, InstrItinClass iis,
1285 PatFrag opnode, bit Commutable = 0> {
1286 // The register-immediate version is re-materializable. This is useful
1287 // in particular for taking the address of a local.
1288 let isReMaterializable = 1 in {
1289 def ri : AsI1<opcod, (outs GPR:$Rd), (ins GPR:$Rn, so_imm:$imm), DPFrm,
1290 iii, opc, "\t$Rd, $Rn, $imm",
1291 [(set GPR:$Rd, (opnode so_imm:$imm, GPR:$Rn))]>,
1292 Sched<[WriteALU, ReadALU]> {
1297 let Inst{19-16} = Rn;
1298 let Inst{15-12} = Rd;
1299 let Inst{11-0} = imm;
1302 def rr : AsI1<opcod, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm), DPFrm,
1303 iir, opc, "\t$Rd, $Rn, $Rm",
1304 [/* pattern left blank */]>,
1305 Sched<[WriteALU, ReadALU, ReadALU]> {
1309 let Inst{11-4} = 0b00000000;
1312 let Inst{15-12} = Rd;
1313 let Inst{19-16} = Rn;
1316 def rsi : AsI1<opcod, (outs GPR:$Rd),
1317 (ins GPR:$Rn, so_reg_imm:$shift), DPSoRegImmFrm,
1318 iis, opc, "\t$Rd, $Rn, $shift",
1319 [(set GPR:$Rd, (opnode so_reg_imm:$shift, GPR:$Rn))]>,
1320 Sched<[WriteALUsi, ReadALU]> {
1325 let Inst{19-16} = Rn;
1326 let Inst{15-12} = Rd;
1327 let Inst{11-5} = shift{11-5};
1329 let Inst{3-0} = shift{3-0};
1332 def rsr : AsI1<opcod, (outs GPR:$Rd),
1333 (ins GPR:$Rn, so_reg_reg:$shift), DPSoRegRegFrm,
1334 iis, opc, "\t$Rd, $Rn, $shift",
1335 [(set GPR:$Rd, (opnode so_reg_reg:$shift, GPR:$Rn))]>,
1336 Sched<[WriteALUsr, ReadALUsr]> {
1341 let Inst{19-16} = Rn;
1342 let Inst{15-12} = Rd;
1343 let Inst{11-8} = shift{11-8};
1345 let Inst{6-5} = shift{6-5};
1347 let Inst{3-0} = shift{3-0};
1351 /// AsI1_bin_s_irs - Same as AsI1_bin_irs except it sets the 's' bit by default.
1353 /// These opcodes will be converted to the real non-S opcodes by
1354 /// AdjustInstrPostInstrSelection after giving them an optional CPSR operand.
1355 let hasPostISelHook = 1, Defs = [CPSR] in {
1356 multiclass AsI1_bin_s_irs<InstrItinClass iii, InstrItinClass iir,
1357 InstrItinClass iis, PatFrag opnode,
1358 bit Commutable = 0> {
1359 def ri : ARMPseudoInst<(outs GPR:$Rd), (ins GPR:$Rn, so_imm:$imm, pred:$p),
1361 [(set GPR:$Rd, CPSR, (opnode GPR:$Rn, so_imm:$imm))]>,
1362 Sched<[WriteALU, ReadALU]>;
1364 def rr : ARMPseudoInst<(outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm, pred:$p),
1366 [(set GPR:$Rd, CPSR, (opnode GPR:$Rn, GPR:$Rm))]>,
1367 Sched<[WriteALU, ReadALU, ReadALU]> {
1368 let isCommutable = Commutable;
1370 def rsi : ARMPseudoInst<(outs GPR:$Rd),
1371 (ins GPR:$Rn, so_reg_imm:$shift, pred:$p),
1373 [(set GPR:$Rd, CPSR, (opnode GPR:$Rn,
1374 so_reg_imm:$shift))]>,
1375 Sched<[WriteALUsi, ReadALU]>;
1377 def rsr : ARMPseudoInst<(outs GPR:$Rd),
1378 (ins GPR:$Rn, so_reg_reg:$shift, pred:$p),
1380 [(set GPR:$Rd, CPSR, (opnode GPR:$Rn,
1381 so_reg_reg:$shift))]>,
1382 Sched<[WriteALUSsr, ReadALUsr]>;
1386 /// AsI1_rbin_s_is - Same as AsI1_bin_s_irs, except selection DAG
1387 /// operands are reversed.
1388 let hasPostISelHook = 1, Defs = [CPSR] in {
1389 multiclass AsI1_rbin_s_is<InstrItinClass iii, InstrItinClass iir,
1390 InstrItinClass iis, PatFrag opnode,
1391 bit Commutable = 0> {
1392 def ri : ARMPseudoInst<(outs GPR:$Rd), (ins GPR:$Rn, so_imm:$imm, pred:$p),
1394 [(set GPR:$Rd, CPSR, (opnode so_imm:$imm, GPR:$Rn))]>,
1395 Sched<[WriteALU, ReadALU]>;
1397 def rsi : ARMPseudoInst<(outs GPR:$Rd),
1398 (ins GPR:$Rn, so_reg_imm:$shift, pred:$p),
1400 [(set GPR:$Rd, CPSR, (opnode so_reg_imm:$shift,
1402 Sched<[WriteALUsi, ReadALU]>;
1404 def rsr : ARMPseudoInst<(outs GPR:$Rd),
1405 (ins GPR:$Rn, so_reg_reg:$shift, pred:$p),
1407 [(set GPR:$Rd, CPSR, (opnode so_reg_reg:$shift,
1409 Sched<[WriteALUSsr, ReadALUsr]>;
1413 /// AI1_cmp_irs - Defines a set of (op r, {so_imm|r|so_reg}) cmp / test
1414 /// patterns. Similar to AsI1_bin_irs except the instruction does not produce
1415 /// a explicit result, only implicitly set CPSR.
1416 let isCompare = 1, Defs = [CPSR] in {
1417 multiclass AI1_cmp_irs<bits<4> opcod, string opc,
1418 InstrItinClass iii, InstrItinClass iir, InstrItinClass iis,
1419 PatFrag opnode, bit Commutable = 0> {
1420 def ri : AI1<opcod, (outs), (ins GPR:$Rn, so_imm:$imm), DPFrm, iii,
1422 [(opnode GPR:$Rn, so_imm:$imm)]>,
1423 Sched<[WriteCMP, ReadALU]> {
1428 let Inst{19-16} = Rn;
1429 let Inst{15-12} = 0b0000;
1430 let Inst{11-0} = imm;
1432 let Unpredictable{15-12} = 0b1111;
1434 def rr : AI1<opcod, (outs), (ins GPR:$Rn, GPR:$Rm), DPFrm, iir,
1436 [(opnode GPR:$Rn, GPR:$Rm)]>,
1437 Sched<[WriteCMP, ReadALU, ReadALU]> {
1440 let isCommutable = Commutable;
1443 let Inst{19-16} = Rn;
1444 let Inst{15-12} = 0b0000;
1445 let Inst{11-4} = 0b00000000;
1448 let Unpredictable{15-12} = 0b1111;
1450 def rsi : AI1<opcod, (outs),
1451 (ins GPR:$Rn, so_reg_imm:$shift), DPSoRegImmFrm, iis,
1452 opc, "\t$Rn, $shift",
1453 [(opnode GPR:$Rn, so_reg_imm:$shift)]>,
1454 Sched<[WriteCMPsi, ReadALU]> {
1459 let Inst{19-16} = Rn;
1460 let Inst{15-12} = 0b0000;
1461 let Inst{11-5} = shift{11-5};
1463 let Inst{3-0} = shift{3-0};
1465 let Unpredictable{15-12} = 0b1111;
1467 def rsr : AI1<opcod, (outs),
1468 (ins GPRnopc:$Rn, so_reg_reg:$shift), DPSoRegRegFrm, iis,
1469 opc, "\t$Rn, $shift",
1470 [(opnode GPRnopc:$Rn, so_reg_reg:$shift)]>,
1471 Sched<[WriteCMPsr, ReadALU]> {
1476 let Inst{19-16} = Rn;
1477 let Inst{15-12} = 0b0000;
1478 let Inst{11-8} = shift{11-8};
1480 let Inst{6-5} = shift{6-5};
1482 let Inst{3-0} = shift{3-0};
1484 let Unpredictable{15-12} = 0b1111;
1490 /// AI_ext_rrot - A unary operation with two forms: one whose operand is a
1491 /// register and one whose operand is a register rotated by 8/16/24.
1492 /// FIXME: Remove the 'r' variant. Its rot_imm is zero.
1493 class AI_ext_rrot<bits<8> opcod, string opc, PatFrag opnode>
1494 : AExtI<opcod, (outs GPRnopc:$Rd), (ins GPRnopc:$Rm, rot_imm:$rot),
1495 IIC_iEXTr, opc, "\t$Rd, $Rm$rot",
1496 [(set GPRnopc:$Rd, (opnode (rotr GPRnopc:$Rm, rot_imm:$rot)))]>,
1497 Requires<[IsARM, HasV6]>, Sched<[WriteALUsi]> {
1501 let Inst{19-16} = 0b1111;
1502 let Inst{15-12} = Rd;
1503 let Inst{11-10} = rot;
1507 class AI_ext_rrot_np<bits<8> opcod, string opc>
1508 : AExtI<opcod, (outs GPRnopc:$Rd), (ins GPRnopc:$Rm, rot_imm:$rot),
1509 IIC_iEXTr, opc, "\t$Rd, $Rm$rot", []>,
1510 Requires<[IsARM, HasV6]>, Sched<[WriteALUsi]> {
1512 let Inst{19-16} = 0b1111;
1513 let Inst{11-10} = rot;
1516 /// AI_exta_rrot - A binary operation with two forms: one whose operand is a
1517 /// register and one whose operand is a register rotated by 8/16/24.
1518 class AI_exta_rrot<bits<8> opcod, string opc, PatFrag opnode>
1519 : AExtI<opcod, (outs GPRnopc:$Rd), (ins GPR:$Rn, GPRnopc:$Rm, rot_imm:$rot),
1520 IIC_iEXTAr, opc, "\t$Rd, $Rn, $Rm$rot",
1521 [(set GPRnopc:$Rd, (opnode GPR:$Rn,
1522 (rotr GPRnopc:$Rm, rot_imm:$rot)))]>,
1523 Requires<[IsARM, HasV6]>, Sched<[WriteALUsr]> {
1528 let Inst{19-16} = Rn;
1529 let Inst{15-12} = Rd;
1530 let Inst{11-10} = rot;
1531 let Inst{9-4} = 0b000111;
1535 class AI_exta_rrot_np<bits<8> opcod, string opc>
1536 : AExtI<opcod, (outs GPRnopc:$Rd), (ins GPR:$Rn, GPRnopc:$Rm, rot_imm:$rot),
1537 IIC_iEXTAr, opc, "\t$Rd, $Rn, $Rm$rot", []>,
1538 Requires<[IsARM, HasV6]>, Sched<[WriteALUsr]> {
1541 let Inst{19-16} = Rn;
1542 let Inst{11-10} = rot;
1545 /// AI1_adde_sube_irs - Define instructions and patterns for adde and sube.
1546 let TwoOperandAliasConstraint = "$Rn = $Rd" in
1547 multiclass AI1_adde_sube_irs<bits<4> opcod, string opc, PatFrag opnode,
1548 bit Commutable = 0> {
1549 let hasPostISelHook = 1, Defs = [CPSR], Uses = [CPSR] in {
1550 def ri : AsI1<opcod, (outs GPR:$Rd), (ins GPR:$Rn, so_imm:$imm),
1551 DPFrm, IIC_iALUi, opc, "\t$Rd, $Rn, $imm",
1552 [(set GPR:$Rd, CPSR, (opnode GPR:$Rn, so_imm:$imm, CPSR))]>,
1554 Sched<[WriteALU, ReadALU]> {
1559 let Inst{15-12} = Rd;
1560 let Inst{19-16} = Rn;
1561 let Inst{11-0} = imm;
1563 def rr : AsI1<opcod, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm),
1564 DPFrm, IIC_iALUr, opc, "\t$Rd, $Rn, $Rm",
1565 [(set GPR:$Rd, CPSR, (opnode GPR:$Rn, GPR:$Rm, CPSR))]>,
1567 Sched<[WriteALU, ReadALU, ReadALU]> {
1571 let Inst{11-4} = 0b00000000;
1573 let isCommutable = Commutable;
1575 let Inst{15-12} = Rd;
1576 let Inst{19-16} = Rn;
1578 def rsi : AsI1<opcod, (outs GPR:$Rd),
1579 (ins GPR:$Rn, so_reg_imm:$shift),
1580 DPSoRegImmFrm, IIC_iALUsr, opc, "\t$Rd, $Rn, $shift",
1581 [(set GPR:$Rd, CPSR, (opnode GPR:$Rn, so_reg_imm:$shift, CPSR))]>,
1583 Sched<[WriteALUsi, ReadALU]> {
1588 let Inst{19-16} = Rn;
1589 let Inst{15-12} = Rd;
1590 let Inst{11-5} = shift{11-5};
1592 let Inst{3-0} = shift{3-0};
1594 def rsr : AsI1<opcod, (outs GPRnopc:$Rd),
1595 (ins GPRnopc:$Rn, so_reg_reg:$shift),
1596 DPSoRegRegFrm, IIC_iALUsr, opc, "\t$Rd, $Rn, $shift",
1597 [(set GPRnopc:$Rd, CPSR,
1598 (opnode GPRnopc:$Rn, so_reg_reg:$shift, CPSR))]>,
1600 Sched<[WriteALUsr, ReadALUsr]> {
1605 let Inst{19-16} = Rn;
1606 let Inst{15-12} = Rd;
1607 let Inst{11-8} = shift{11-8};
1609 let Inst{6-5} = shift{6-5};
1611 let Inst{3-0} = shift{3-0};
1616 /// AI1_rsc_irs - Define instructions and patterns for rsc
1617 let TwoOperandAliasConstraint = "$Rn = $Rd" in
1618 multiclass AI1_rsc_irs<bits<4> opcod, string opc, PatFrag opnode> {
1619 let hasPostISelHook = 1, Defs = [CPSR], Uses = [CPSR] in {
1620 def ri : AsI1<opcod, (outs GPR:$Rd), (ins GPR:$Rn, so_imm:$imm),
1621 DPFrm, IIC_iALUi, opc, "\t$Rd, $Rn, $imm",
1622 [(set GPR:$Rd, CPSR, (opnode so_imm:$imm, GPR:$Rn, CPSR))]>,
1624 Sched<[WriteALU, ReadALU]> {
1629 let Inst{15-12} = Rd;
1630 let Inst{19-16} = Rn;
1631 let Inst{11-0} = imm;
1633 def rr : AsI1<opcod, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm),
1634 DPFrm, IIC_iALUr, opc, "\t$Rd, $Rn, $Rm",
1635 [/* pattern left blank */]>,
1636 Sched<[WriteALU, ReadALU, ReadALU]> {
1640 let Inst{11-4} = 0b00000000;
1643 let Inst{15-12} = Rd;
1644 let Inst{19-16} = Rn;
1646 def rsi : AsI1<opcod, (outs GPR:$Rd), (ins GPR:$Rn, so_reg_imm:$shift),
1647 DPSoRegImmFrm, IIC_iALUsr, opc, "\t$Rd, $Rn, $shift",
1648 [(set GPR:$Rd, CPSR, (opnode so_reg_imm:$shift, GPR:$Rn, CPSR))]>,
1650 Sched<[WriteALUsi, ReadALU]> {
1655 let Inst{19-16} = Rn;
1656 let Inst{15-12} = Rd;
1657 let Inst{11-5} = shift{11-5};
1659 let Inst{3-0} = shift{3-0};
1661 def rsr : AsI1<opcod, (outs GPR:$Rd), (ins GPR:$Rn, so_reg_reg:$shift),
1662 DPSoRegRegFrm, IIC_iALUsr, opc, "\t$Rd, $Rn, $shift",
1663 [(set GPR:$Rd, CPSR, (opnode so_reg_reg:$shift, GPR:$Rn, CPSR))]>,
1665 Sched<[WriteALUsr, ReadALUsr]> {
1670 let Inst{19-16} = Rn;
1671 let Inst{15-12} = Rd;
1672 let Inst{11-8} = shift{11-8};
1674 let Inst{6-5} = shift{6-5};
1676 let Inst{3-0} = shift{3-0};
1681 let canFoldAsLoad = 1, isReMaterializable = 1 in {
1682 multiclass AI_ldr1<bit isByte, string opc, InstrItinClass iii,
1683 InstrItinClass iir, PatFrag opnode> {
1684 // Note: We use the complex addrmode_imm12 rather than just an input
1685 // GPR and a constrained immediate so that we can use this to match
1686 // frame index references and avoid matching constant pool references.
1687 def i12: AI2ldst<0b010, 1, isByte, (outs GPR:$Rt), (ins addrmode_imm12:$addr),
1688 AddrMode_i12, LdFrm, iii, opc, "\t$Rt, $addr",
1689 [(set GPR:$Rt, (opnode addrmode_imm12:$addr))]> {
1692 let Inst{23} = addr{12}; // U (add = ('U' == 1))
1693 let Inst{19-16} = addr{16-13}; // Rn
1694 let Inst{15-12} = Rt;
1695 let Inst{11-0} = addr{11-0}; // imm12
1697 def rs : AI2ldst<0b011, 1, isByte, (outs GPR:$Rt), (ins ldst_so_reg:$shift),
1698 AddrModeNone, LdFrm, iir, opc, "\t$Rt, $shift",
1699 [(set GPR:$Rt, (opnode ldst_so_reg:$shift))]> {
1702 let shift{4} = 0; // Inst{4} = 0
1703 let Inst{23} = shift{12}; // U (add = ('U' == 1))
1704 let Inst{19-16} = shift{16-13}; // Rn
1705 let Inst{15-12} = Rt;
1706 let Inst{11-0} = shift{11-0};
1711 let canFoldAsLoad = 1, isReMaterializable = 1 in {
1712 multiclass AI_ldr1nopc<bit isByte, string opc, InstrItinClass iii,
1713 InstrItinClass iir, PatFrag opnode> {
1714 // Note: We use the complex addrmode_imm12 rather than just an input
1715 // GPR and a constrained immediate so that we can use this to match
1716 // frame index references and avoid matching constant pool references.
1717 def i12: AI2ldst<0b010, 1, isByte, (outs GPRnopc:$Rt),
1718 (ins addrmode_imm12:$addr),
1719 AddrMode_i12, LdFrm, iii, opc, "\t$Rt, $addr",
1720 [(set GPRnopc:$Rt, (opnode addrmode_imm12:$addr))]> {
1723 let Inst{23} = addr{12}; // U (add = ('U' == 1))
1724 let Inst{19-16} = addr{16-13}; // Rn
1725 let Inst{15-12} = Rt;
1726 let Inst{11-0} = addr{11-0}; // imm12
1728 def rs : AI2ldst<0b011, 1, isByte, (outs GPRnopc:$Rt),
1729 (ins ldst_so_reg:$shift),
1730 AddrModeNone, LdFrm, iir, opc, "\t$Rt, $shift",
1731 [(set GPRnopc:$Rt, (opnode ldst_so_reg:$shift))]> {
1734 let shift{4} = 0; // Inst{4} = 0
1735 let Inst{23} = shift{12}; // U (add = ('U' == 1))
1736 let Inst{19-16} = shift{16-13}; // Rn
1737 let Inst{15-12} = Rt;
1738 let Inst{11-0} = shift{11-0};
1744 multiclass AI_str1<bit isByte, string opc, InstrItinClass iii,
1745 InstrItinClass iir, PatFrag opnode> {
1746 // Note: We use the complex addrmode_imm12 rather than just an input
1747 // GPR and a constrained immediate so that we can use this to match
1748 // frame index references and avoid matching constant pool references.
1749 def i12 : AI2ldst<0b010, 0, isByte, (outs),
1750 (ins GPR:$Rt, addrmode_imm12:$addr),
1751 AddrMode_i12, StFrm, iii, opc, "\t$Rt, $addr",
1752 [(opnode GPR:$Rt, addrmode_imm12:$addr)]> {
1755 let Inst{23} = addr{12}; // U (add = ('U' == 1))
1756 let Inst{19-16} = addr{16-13}; // Rn
1757 let Inst{15-12} = Rt;
1758 let Inst{11-0} = addr{11-0}; // imm12
1760 def rs : AI2ldst<0b011, 0, isByte, (outs), (ins GPR:$Rt, ldst_so_reg:$shift),
1761 AddrModeNone, StFrm, iir, opc, "\t$Rt, $shift",
1762 [(opnode GPR:$Rt, ldst_so_reg:$shift)]> {
1765 let shift{4} = 0; // Inst{4} = 0
1766 let Inst{23} = shift{12}; // U (add = ('U' == 1))
1767 let Inst{19-16} = shift{16-13}; // Rn
1768 let Inst{15-12} = Rt;
1769 let Inst{11-0} = shift{11-0};
1773 multiclass AI_str1nopc<bit isByte, string opc, InstrItinClass iii,
1774 InstrItinClass iir, PatFrag opnode> {
1775 // Note: We use the complex addrmode_imm12 rather than just an input
1776 // GPR and a constrained immediate so that we can use this to match
1777 // frame index references and avoid matching constant pool references.
1778 def i12 : AI2ldst<0b010, 0, isByte, (outs),
1779 (ins GPRnopc:$Rt, addrmode_imm12:$addr),
1780 AddrMode_i12, StFrm, iii, opc, "\t$Rt, $addr",
1781 [(opnode GPRnopc:$Rt, addrmode_imm12:$addr)]> {
1784 let Inst{23} = addr{12}; // U (add = ('U' == 1))
1785 let Inst{19-16} = addr{16-13}; // Rn
1786 let Inst{15-12} = Rt;
1787 let Inst{11-0} = addr{11-0}; // imm12
1789 def rs : AI2ldst<0b011, 0, isByte, (outs),
1790 (ins GPRnopc:$Rt, ldst_so_reg:$shift),
1791 AddrModeNone, StFrm, iir, opc, "\t$Rt, $shift",
1792 [(opnode GPRnopc:$Rt, ldst_so_reg:$shift)]> {
1795 let shift{4} = 0; // Inst{4} = 0
1796 let Inst{23} = shift{12}; // U (add = ('U' == 1))
1797 let Inst{19-16} = shift{16-13}; // Rn
1798 let Inst{15-12} = Rt;
1799 let Inst{11-0} = shift{11-0};
1804 //===----------------------------------------------------------------------===//
1806 //===----------------------------------------------------------------------===//
1808 //===----------------------------------------------------------------------===//
1809 // Miscellaneous Instructions.
1812 /// CONSTPOOL_ENTRY - This instruction represents a floating constant pool in
1813 /// the function. The first operand is the ID# for this instruction, the second
1814 /// is the index into the MachineConstantPool that this is, the third is the
1815 /// size in bytes of this constant pool entry.
1816 let neverHasSideEffects = 1, isNotDuplicable = 1 in
1817 def CONSTPOOL_ENTRY :
1818 PseudoInst<(outs), (ins cpinst_operand:$instid, cpinst_operand:$cpidx,
1819 i32imm:$size), NoItinerary, []>;
1821 // FIXME: Marking these as hasSideEffects is necessary to prevent machine DCE
1822 // from removing one half of the matched pairs. That breaks PEI, which assumes
1823 // these will always be in pairs, and asserts if it finds otherwise. Better way?
1824 let Defs = [SP], Uses = [SP], hasSideEffects = 1 in {
1825 def ADJCALLSTACKUP :
1826 PseudoInst<(outs), (ins i32imm:$amt1, i32imm:$amt2, pred:$p), NoItinerary,
1827 [(ARMcallseq_end timm:$amt1, timm:$amt2)]>;
1829 def ADJCALLSTACKDOWN :
1830 PseudoInst<(outs), (ins i32imm:$amt, pred:$p), NoItinerary,
1831 [(ARMcallseq_start timm:$amt)]>;
1834 def HINT : AI<(outs), (ins imm0_239:$imm), MiscFrm, NoItinerary,
1835 "hint", "\t$imm", [(int_arm_hint imm0_239:$imm)]>,
1836 Requires<[IsARM, HasV6]> {
1838 let Inst{27-8} = 0b00110010000011110000;
1839 let Inst{7-0} = imm;
1842 def : InstAlias<"nop$p", (HINT 0, pred:$p)>, Requires<[IsARM, HasV6T2]>;
1843 def : InstAlias<"yield$p", (HINT 1, pred:$p)>, Requires<[IsARM, HasV6T2]>;
1844 def : InstAlias<"wfe$p", (HINT 2, pred:$p)>, Requires<[IsARM, HasV6T2]>;
1845 def : InstAlias<"wfi$p", (HINT 3, pred:$p)>, Requires<[IsARM, HasV6T2]>;
1846 def : InstAlias<"sev$p", (HINT 4, pred:$p)>, Requires<[IsARM, HasV6T2]>;
1847 def : InstAlias<"sevl$p", (HINT 5, pred:$p)>, Requires<[IsARM, HasV8]>;
1849 def SEL : AI<(outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm), DPFrm, NoItinerary, "sel",
1850 "\t$Rd, $Rn, $Rm", []>, Requires<[IsARM, HasV6]> {
1855 let Inst{15-12} = Rd;
1856 let Inst{19-16} = Rn;
1857 let Inst{27-20} = 0b01101000;
1858 let Inst{7-4} = 0b1011;
1859 let Inst{11-8} = 0b1111;
1860 let Unpredictable{11-8} = 0b1111;
1863 // The 16-bit operand $val can be used by a debugger to store more information
1864 // about the breakpoint.
1865 def BKPT : AInoP<(outs), (ins imm0_65535:$val), MiscFrm, NoItinerary,
1866 "bkpt", "\t$val", []>, Requires<[IsARM]> {
1868 let Inst{3-0} = val{3-0};
1869 let Inst{19-8} = val{15-4};
1870 let Inst{27-20} = 0b00010010;
1871 let Inst{31-28} = 0xe; // AL
1872 let Inst{7-4} = 0b0111;
1874 // default immediate for breakpoint mnemonic
1875 def : InstAlias<"bkpt", (BKPT 0)>, Requires<[IsARM]>;
1877 def HLT : AInoP<(outs), (ins imm0_65535:$val), MiscFrm, NoItinerary,
1878 "hlt", "\t$val", []>, Requires<[IsARM, HasV8]> {
1880 let Inst{3-0} = val{3-0};
1881 let Inst{19-8} = val{15-4};
1882 let Inst{27-20} = 0b00010000;
1883 let Inst{31-28} = 0xe; // AL
1884 let Inst{7-4} = 0b0111;
1887 // Change Processor State
1888 // FIXME: We should use InstAlias to handle the optional operands.
1889 class CPS<dag iops, string asm_ops>
1890 : AXI<(outs), iops, MiscFrm, NoItinerary, !strconcat("cps", asm_ops),
1891 []>, Requires<[IsARM]> {
1897 let Inst{31-28} = 0b1111;
1898 let Inst{27-20} = 0b00010000;
1899 let Inst{19-18} = imod;
1900 let Inst{17} = M; // Enabled if mode is set;
1901 let Inst{16-9} = 0b00000000;
1902 let Inst{8-6} = iflags;
1904 let Inst{4-0} = mode;
1907 let DecoderMethod = "DecodeCPSInstruction" in {
1909 def CPS3p : CPS<(ins imod_op:$imod, iflags_op:$iflags, imm0_31:$mode),
1910 "$imod\t$iflags, $mode">;
1911 let mode = 0, M = 0 in
1912 def CPS2p : CPS<(ins imod_op:$imod, iflags_op:$iflags), "$imod\t$iflags">;
1914 let imod = 0, iflags = 0, M = 1 in
1915 def CPS1p : CPS<(ins imm0_31:$mode), "\t$mode">;
1918 // Preload signals the memory system of possible future data/instruction access.
1919 multiclass APreLoad<bits<1> read, bits<1> data, string opc> {
1921 def i12 : AXIM<(outs), (ins addrmode_imm12:$addr), AddrMode_i12, MiscFrm,
1922 IIC_Preload, !strconcat(opc, "\t$addr"),
1923 [(ARMPreload addrmode_imm12:$addr, (i32 read), (i32 data))]>,
1924 Sched<[WritePreLd]> {
1927 let Inst{31-26} = 0b111101;
1928 let Inst{25} = 0; // 0 for immediate form
1929 let Inst{24} = data;
1930 let Inst{23} = addr{12}; // U (add = ('U' == 1))
1931 let Inst{22} = read;
1932 let Inst{21-20} = 0b01;
1933 let Inst{19-16} = addr{16-13}; // Rn
1934 let Inst{15-12} = 0b1111;
1935 let Inst{11-0} = addr{11-0}; // imm12
1938 def rs : AXI<(outs), (ins ldst_so_reg:$shift), MiscFrm, IIC_Preload,
1939 !strconcat(opc, "\t$shift"),
1940 [(ARMPreload ldst_so_reg:$shift, (i32 read), (i32 data))]>,
1941 Sched<[WritePreLd]> {
1943 let Inst{31-26} = 0b111101;
1944 let Inst{25} = 1; // 1 for register form
1945 let Inst{24} = data;
1946 let Inst{23} = shift{12}; // U (add = ('U' == 1))
1947 let Inst{22} = read;
1948 let Inst{21-20} = 0b01;
1949 let Inst{19-16} = shift{16-13}; // Rn
1950 let Inst{15-12} = 0b1111;
1951 let Inst{11-0} = shift{11-0};
1956 defm PLD : APreLoad<1, 1, "pld">, Requires<[IsARM]>;
1957 defm PLDW : APreLoad<0, 1, "pldw">, Requires<[IsARM,HasV7,HasMP]>;
1958 defm PLI : APreLoad<1, 0, "pli">, Requires<[IsARM,HasV7]>;
1960 def SETEND : AXI<(outs), (ins setend_op:$end), MiscFrm, NoItinerary,
1961 "setend\t$end", []>, Requires<[IsARM]>, Deprecated<HasV8Ops> {
1963 let Inst{31-10} = 0b1111000100000001000000;
1968 def DBG : AI<(outs), (ins imm0_15:$opt), MiscFrm, NoItinerary, "dbg", "\t$opt",
1969 []>, Requires<[IsARM, HasV7]> {
1971 let Inst{27-4} = 0b001100100000111100001111;
1972 let Inst{3-0} = opt;
1975 // A8.8.247 UDF - Undefined (Encoding A1)
1976 def UDF : AInoP<(outs), (ins imm0_65535:$imm16), MiscFrm, NoItinerary,
1977 "udf", "\t$imm16", [(int_arm_undefined imm0_65535:$imm16)]> {
1979 let Inst{31-28} = 0b1110; // AL
1980 let Inst{27-25} = 0b011;
1981 let Inst{24-20} = 0b11111;
1982 let Inst{19-8} = imm16{15-4};
1983 let Inst{7-4} = 0b1111;
1984 let Inst{3-0} = imm16{3-0};
1988 * A5.4 Permanently UNDEFINED instructions.
1990 * For most targets use UDF #65006, for which the OS will generate SIGTRAP.
1991 * Other UDF encodings generate SIGILL.
1993 * NaCl's OS instead chooses an ARM UDF encoding that's also a UDF in Thumb.
1995 * 1110 0111 1111 iiii iiii iiii 1111 iiii
1997 * 1101 1110 iiii iiii
1998 * It uses the following encoding:
1999 * 1110 0111 1111 1110 1101 1110 1111 0000
2000 * - In ARM: UDF #60896;
2001 * - In Thumb: UDF #254 followed by a branch-to-self.
2003 let isBarrier = 1, isTerminator = 1 in
2004 def TRAPNaCl : AXI<(outs), (ins), MiscFrm, NoItinerary,
2006 Requires<[IsARM,UseNaClTrap]> {
2007 let Inst = 0xe7fedef0;
2009 let isBarrier = 1, isTerminator = 1 in
2010 def TRAP : AXI<(outs), (ins), MiscFrm, NoItinerary,
2012 Requires<[IsARM,DontUseNaClTrap]> {
2013 let Inst = 0xe7ffdefe;
2016 // Address computation and loads and stores in PIC mode.
2017 let isNotDuplicable = 1 in {
2018 def PICADD : ARMPseudoInst<(outs GPR:$dst), (ins GPR:$a, pclabel:$cp, pred:$p),
2020 [(set GPR:$dst, (ARMpic_add GPR:$a, imm:$cp))]>,
2021 Sched<[WriteALU, ReadALU]>;
2023 let AddedComplexity = 10 in {
2024 def PICLDR : ARMPseudoInst<(outs GPR:$dst), (ins addrmodepc:$addr, pred:$p),
2026 [(set GPR:$dst, (load addrmodepc:$addr))]>;
2028 def PICLDRH : ARMPseudoInst<(outs GPR:$Rt), (ins addrmodepc:$addr, pred:$p),
2030 [(set GPR:$Rt, (zextloadi16 addrmodepc:$addr))]>;
2032 def PICLDRB : ARMPseudoInst<(outs GPR:$Rt), (ins addrmodepc:$addr, pred:$p),
2034 [(set GPR:$Rt, (zextloadi8 addrmodepc:$addr))]>;
2036 def PICLDRSH : ARMPseudoInst<(outs GPR:$Rt), (ins addrmodepc:$addr, pred:$p),
2038 [(set GPR:$Rt, (sextloadi16 addrmodepc:$addr))]>;
2040 def PICLDRSB : ARMPseudoInst<(outs GPR:$Rt), (ins addrmodepc:$addr, pred:$p),
2042 [(set GPR:$Rt, (sextloadi8 addrmodepc:$addr))]>;
2044 let AddedComplexity = 10 in {
2045 def PICSTR : ARMPseudoInst<(outs), (ins GPR:$src, addrmodepc:$addr, pred:$p),
2046 4, IIC_iStore_r, [(store GPR:$src, addrmodepc:$addr)]>;
2048 def PICSTRH : ARMPseudoInst<(outs), (ins GPR:$src, addrmodepc:$addr, pred:$p),
2049 4, IIC_iStore_bh_r, [(truncstorei16 GPR:$src,
2050 addrmodepc:$addr)]>;
2052 def PICSTRB : ARMPseudoInst<(outs), (ins GPR:$src, addrmodepc:$addr, pred:$p),
2053 4, IIC_iStore_bh_r, [(truncstorei8 GPR:$src, addrmodepc:$addr)]>;
2055 } // isNotDuplicable = 1
2058 // LEApcrel - Load a pc-relative address into a register without offending the
2060 let neverHasSideEffects = 1, isReMaterializable = 1 in
2061 // The 'adr' mnemonic encodes differently if the label is before or after
2062 // the instruction. The {24-21} opcode bits are set by the fixup, as we don't
2063 // know until then which form of the instruction will be used.
2064 def ADR : AI1<{0,?,?,0}, (outs GPR:$Rd), (ins adrlabel:$label),
2065 MiscFrm, IIC_iALUi, "adr", "\t$Rd, $label", []>,
2066 Sched<[WriteALU, ReadALU]> {
2069 let Inst{27-25} = 0b001;
2071 let Inst{23-22} = label{13-12};
2074 let Inst{19-16} = 0b1111;
2075 let Inst{15-12} = Rd;
2076 let Inst{11-0} = label{11-0};
2079 let hasSideEffects = 1 in {
2080 def LEApcrel : ARMPseudoInst<(outs GPR:$Rd), (ins i32imm:$label, pred:$p),
2081 4, IIC_iALUi, []>, Sched<[WriteALU, ReadALU]>;
2083 def LEApcrelJT : ARMPseudoInst<(outs GPR:$Rd),
2084 (ins i32imm:$label, nohash_imm:$id, pred:$p),
2085 4, IIC_iALUi, []>, Sched<[WriteALU, ReadALU]>;
2088 //===----------------------------------------------------------------------===//
2089 // Control Flow Instructions.
2092 let isReturn = 1, isTerminator = 1, isBarrier = 1 in {
2094 def BX_RET : AI<(outs), (ins), BrMiscFrm, IIC_Br,
2095 "bx", "\tlr", [(ARMretflag)]>,
2096 Requires<[IsARM, HasV4T]>, Sched<[WriteBr]> {
2097 let Inst{27-0} = 0b0001001011111111111100011110;
2101 def MOVPCLR : AI<(outs), (ins), BrMiscFrm, IIC_Br,
2102 "mov", "\tpc, lr", [(ARMretflag)]>,
2103 Requires<[IsARM, NoV4T]>, Sched<[WriteBr]> {
2104 let Inst{27-0} = 0b0001101000001111000000001110;
2107 // Exception return: N.b. doesn't set CPSR as far as we're concerned (it sets
2108 // the user-space one).
2109 def SUBS_PC_LR : ARMPseudoInst<(outs), (ins i32imm:$offset, pred:$p),
2111 [(ARMintretflag imm:$offset)]>;
2114 // Indirect branches
2115 let isBranch = 1, isTerminator = 1, isBarrier = 1, isIndirectBranch = 1 in {
2117 def BX : AXI<(outs), (ins GPR:$dst), BrMiscFrm, IIC_Br, "bx\t$dst",
2118 [(brind GPR:$dst)]>,
2119 Requires<[IsARM, HasV4T]>, Sched<[WriteBr]> {
2121 let Inst{31-4} = 0b1110000100101111111111110001;
2122 let Inst{3-0} = dst;
2125 def BX_pred : AI<(outs), (ins GPR:$dst), BrMiscFrm, IIC_Br,
2126 "bx", "\t$dst", [/* pattern left blank */]>,
2127 Requires<[IsARM, HasV4T]>, Sched<[WriteBr]> {
2129 let Inst{27-4} = 0b000100101111111111110001;
2130 let Inst{3-0} = dst;
2134 // SP is marked as a use to prevent stack-pointer assignments that appear
2135 // immediately before calls from potentially appearing dead.
2137 // FIXME: Do we really need a non-predicated version? If so, it should
2138 // at least be a pseudo instruction expanding to the predicated version
2139 // at MC lowering time.
2140 Defs = [LR], Uses = [SP] in {
2141 def BL : ABXI<0b1011, (outs), (ins bl_target:$func),
2142 IIC_Br, "bl\t$func",
2143 [(ARMcall tglobaladdr:$func)]>,
2144 Requires<[IsARM]>, Sched<[WriteBrL]> {
2145 let Inst{31-28} = 0b1110;
2147 let Inst{23-0} = func;
2148 let DecoderMethod = "DecodeBranchImmInstruction";
2151 def BL_pred : ABI<0b1011, (outs), (ins bl_target:$func),
2152 IIC_Br, "bl", "\t$func",
2153 [(ARMcall_pred tglobaladdr:$func)]>,
2154 Requires<[IsARM]>, Sched<[WriteBrL]> {
2156 let Inst{23-0} = func;
2157 let DecoderMethod = "DecodeBranchImmInstruction";
2161 def BLX : AXI<(outs), (ins GPR:$func), BrMiscFrm,
2162 IIC_Br, "blx\t$func",
2163 [(ARMcall GPR:$func)]>,
2164 Requires<[IsARM, HasV5T]>, Sched<[WriteBrL]> {
2166 let Inst{31-4} = 0b1110000100101111111111110011;
2167 let Inst{3-0} = func;
2170 def BLX_pred : AI<(outs), (ins GPR:$func), BrMiscFrm,
2171 IIC_Br, "blx", "\t$func",
2172 [(ARMcall_pred GPR:$func)]>,
2173 Requires<[IsARM, HasV5T]>, Sched<[WriteBrL]> {
2175 let Inst{27-4} = 0b000100101111111111110011;
2176 let Inst{3-0} = func;
2180 // Note: Restrict $func to the tGPR regclass to prevent it being in LR.
2181 def BX_CALL : ARMPseudoInst<(outs), (ins tGPR:$func),
2182 8, IIC_Br, [(ARMcall_nolink tGPR:$func)]>,
2183 Requires<[IsARM, HasV4T]>, Sched<[WriteBr]>;
2186 def BMOVPCRX_CALL : ARMPseudoInst<(outs), (ins tGPR:$func),
2187 8, IIC_Br, [(ARMcall_nolink tGPR:$func)]>,
2188 Requires<[IsARM, NoV4T]>, Sched<[WriteBr]>;
2190 // mov lr, pc; b if callee is marked noreturn to avoid confusing the
2191 // return stack predictor.
2192 def BMOVPCB_CALL : ARMPseudoInst<(outs), (ins bl_target:$func),
2193 8, IIC_Br, [(ARMcall_nolink tglobaladdr:$func)]>,
2194 Requires<[IsARM]>, Sched<[WriteBr]>;
2197 let isBranch = 1, isTerminator = 1 in {
2198 // FIXME: should be able to write a pattern for ARMBrcond, but can't use
2199 // a two-value operand where a dag node expects two operands. :(
2200 def Bcc : ABI<0b1010, (outs), (ins br_target:$target),
2201 IIC_Br, "b", "\t$target",
2202 [/*(ARMbrcond bb:$target, imm:$cc, CCR:$ccr)*/]>,
2205 let Inst{23-0} = target;
2206 let DecoderMethod = "DecodeBranchImmInstruction";
2209 let isBarrier = 1 in {
2210 // B is "predicable" since it's just a Bcc with an 'always' condition.
2211 let isPredicable = 1 in
2212 // FIXME: We shouldn't need this pseudo at all. Just using Bcc directly
2213 // should be sufficient.
2214 // FIXME: Is B really a Barrier? That doesn't seem right.
2215 def B : ARMPseudoExpand<(outs), (ins br_target:$target), 4, IIC_Br,
2216 [(br bb:$target)], (Bcc br_target:$target, (ops 14, zero_reg))>,
2219 let isNotDuplicable = 1, isIndirectBranch = 1 in {
2220 def BR_JTr : ARMPseudoInst<(outs),
2221 (ins GPR:$target, i32imm:$jt, i32imm:$id),
2223 [(ARMbrjt GPR:$target, tjumptable:$jt, imm:$id)]>,
2225 // FIXME: This shouldn't use the generic "addrmode2," but rather be split
2226 // into i12 and rs suffixed versions.
2227 def BR_JTm : ARMPseudoInst<(outs),
2228 (ins addrmode2:$target, i32imm:$jt, i32imm:$id),
2230 [(ARMbrjt (i32 (load addrmode2:$target)), tjumptable:$jt,
2231 imm:$id)]>, Sched<[WriteBrTbl]>;
2232 def BR_JTadd : ARMPseudoInst<(outs),
2233 (ins GPR:$target, GPR:$idx, i32imm:$jt, i32imm:$id),
2235 [(ARMbrjt (add GPR:$target, GPR:$idx), tjumptable:$jt,
2236 imm:$id)]>, Sched<[WriteBrTbl]>;
2237 } // isNotDuplicable = 1, isIndirectBranch = 1
2243 def BLXi : AXI<(outs), (ins blx_target:$target), BrMiscFrm, NoItinerary,
2244 "blx\t$target", []>,
2245 Requires<[IsARM, HasV5T]>, Sched<[WriteBrL]> {
2246 let Inst{31-25} = 0b1111101;
2248 let Inst{23-0} = target{24-1};
2249 let Inst{24} = target{0};
2252 // Branch and Exchange Jazelle
2253 def BXJ : ABI<0b0001, (outs), (ins GPR:$func), NoItinerary, "bxj", "\t$func",
2254 [/* pattern left blank */]>, Sched<[WriteBr]> {
2256 let Inst{23-20} = 0b0010;
2257 let Inst{19-8} = 0xfff;
2258 let Inst{7-4} = 0b0010;
2259 let Inst{3-0} = func;
2264 let isCall = 1, isTerminator = 1, isReturn = 1, isBarrier = 1, Uses = [SP] in {
2265 def TCRETURNdi : PseudoInst<(outs), (ins i32imm:$dst), IIC_Br, []>,
2268 def TCRETURNri : PseudoInst<(outs), (ins tcGPR:$dst), IIC_Br, []>,
2271 def TAILJMPd : ARMPseudoExpand<(outs), (ins br_target:$dst),
2273 (Bcc br_target:$dst, (ops 14, zero_reg))>,
2274 Requires<[IsARM]>, Sched<[WriteBr]>;
2276 def TAILJMPr : ARMPseudoExpand<(outs), (ins tcGPR:$dst),
2278 (BX GPR:$dst)>, Sched<[WriteBr]>,
2282 // Secure Monitor Call is a system instruction.
2283 def SMC : ABI<0b0001, (outs), (ins imm0_15:$opt), NoItinerary, "smc", "\t$opt",
2284 []>, Requires<[IsARM, HasTrustZone]> {
2286 let Inst{23-4} = 0b01100000000000000111;
2287 let Inst{3-0} = opt;
2290 // Supervisor Call (Software Interrupt)
2291 let isCall = 1, Uses = [SP] in {
2292 def SVC : ABI<0b1111, (outs), (ins imm24b:$svc), IIC_Br, "svc", "\t$svc", []>,
2295 let Inst{23-0} = svc;
2299 // Store Return State
2300 class SRSI<bit wb, string asm>
2301 : XI<(outs), (ins imm0_31:$mode), AddrModeNone, 4, IndexModeNone, BrFrm,
2302 NoItinerary, asm, "", []> {
2304 let Inst{31-28} = 0b1111;
2305 let Inst{27-25} = 0b100;
2309 let Inst{19-16} = 0b1101; // SP
2310 let Inst{15-5} = 0b00000101000;
2311 let Inst{4-0} = mode;
2314 def SRSDA : SRSI<0, "srsda\tsp, $mode"> {
2315 let Inst{24-23} = 0;
2317 def SRSDA_UPD : SRSI<1, "srsda\tsp!, $mode"> {
2318 let Inst{24-23} = 0;
2320 def SRSDB : SRSI<0, "srsdb\tsp, $mode"> {
2321 let Inst{24-23} = 0b10;
2323 def SRSDB_UPD : SRSI<1, "srsdb\tsp!, $mode"> {
2324 let Inst{24-23} = 0b10;
2326 def SRSIA : SRSI<0, "srsia\tsp, $mode"> {
2327 let Inst{24-23} = 0b01;
2329 def SRSIA_UPD : SRSI<1, "srsia\tsp!, $mode"> {
2330 let Inst{24-23} = 0b01;
2332 def SRSIB : SRSI<0, "srsib\tsp, $mode"> {
2333 let Inst{24-23} = 0b11;
2335 def SRSIB_UPD : SRSI<1, "srsib\tsp!, $mode"> {
2336 let Inst{24-23} = 0b11;
2339 def : ARMInstAlias<"srsda $mode", (SRSDA imm0_31:$mode)>;
2340 def : ARMInstAlias<"srsda $mode!", (SRSDA_UPD imm0_31:$mode)>;
2342 def : ARMInstAlias<"srsdb $mode", (SRSDB imm0_31:$mode)>;
2343 def : ARMInstAlias<"srsdb $mode!", (SRSDB_UPD imm0_31:$mode)>;
2345 def : ARMInstAlias<"srsia $mode", (SRSIA imm0_31:$mode)>;
2346 def : ARMInstAlias<"srsia $mode!", (SRSIA_UPD imm0_31:$mode)>;
2348 def : ARMInstAlias<"srsib $mode", (SRSIB imm0_31:$mode)>;
2349 def : ARMInstAlias<"srsib $mode!", (SRSIB_UPD imm0_31:$mode)>;
2351 // Return From Exception
2352 class RFEI<bit wb, string asm>
2353 : XI<(outs), (ins GPR:$Rn), AddrModeNone, 4, IndexModeNone, BrFrm,
2354 NoItinerary, asm, "", []> {
2356 let Inst{31-28} = 0b1111;
2357 let Inst{27-25} = 0b100;
2361 let Inst{19-16} = Rn;
2362 let Inst{15-0} = 0xa00;
2365 def RFEDA : RFEI<0, "rfeda\t$Rn"> {
2366 let Inst{24-23} = 0;
2368 def RFEDA_UPD : RFEI<1, "rfeda\t$Rn!"> {
2369 let Inst{24-23} = 0;
2371 def RFEDB : RFEI<0, "rfedb\t$Rn"> {
2372 let Inst{24-23} = 0b10;
2374 def RFEDB_UPD : RFEI<1, "rfedb\t$Rn!"> {
2375 let Inst{24-23} = 0b10;
2377 def RFEIA : RFEI<0, "rfeia\t$Rn"> {
2378 let Inst{24-23} = 0b01;
2380 def RFEIA_UPD : RFEI<1, "rfeia\t$Rn!"> {
2381 let Inst{24-23} = 0b01;
2383 def RFEIB : RFEI<0, "rfeib\t$Rn"> {
2384 let Inst{24-23} = 0b11;
2386 def RFEIB_UPD : RFEI<1, "rfeib\t$Rn!"> {
2387 let Inst{24-23} = 0b11;
2390 //===----------------------------------------------------------------------===//
2391 // Load / Store Instructions.
2397 defm LDR : AI_ldr1<0, "ldr", IIC_iLoad_r, IIC_iLoad_si,
2398 UnOpFrag<(load node:$Src)>>;
2399 defm LDRB : AI_ldr1nopc<1, "ldrb", IIC_iLoad_bh_r, IIC_iLoad_bh_si,
2400 UnOpFrag<(zextloadi8 node:$Src)>>;
2401 defm STR : AI_str1<0, "str", IIC_iStore_r, IIC_iStore_si,
2402 BinOpFrag<(store node:$LHS, node:$RHS)>>;
2403 defm STRB : AI_str1nopc<1, "strb", IIC_iStore_bh_r, IIC_iStore_bh_si,
2404 BinOpFrag<(truncstorei8 node:$LHS, node:$RHS)>>;
2406 // Special LDR for loads from non-pc-relative constpools.
2407 let canFoldAsLoad = 1, mayLoad = 1, neverHasSideEffects = 1,
2408 isReMaterializable = 1, isCodeGenOnly = 1 in
2409 def LDRcp : AI2ldst<0b010, 1, 0, (outs GPR:$Rt), (ins addrmode_imm12:$addr),
2410 AddrMode_i12, LdFrm, IIC_iLoad_r, "ldr", "\t$Rt, $addr",
2414 let Inst{23} = addr{12}; // U (add = ('U' == 1))
2415 let Inst{19-16} = 0b1111;
2416 let Inst{15-12} = Rt;
2417 let Inst{11-0} = addr{11-0}; // imm12
2420 // Loads with zero extension
2421 def LDRH : AI3ld<0b1011, 1, (outs GPR:$Rt), (ins addrmode3:$addr), LdMiscFrm,
2422 IIC_iLoad_bh_r, "ldrh", "\t$Rt, $addr",
2423 [(set GPR:$Rt, (zextloadi16 addrmode3:$addr))]>;
2425 // Loads with sign extension
2426 def LDRSH : AI3ld<0b1111, 1, (outs GPR:$Rt), (ins addrmode3:$addr), LdMiscFrm,
2427 IIC_iLoad_bh_r, "ldrsh", "\t$Rt, $addr",
2428 [(set GPR:$Rt, (sextloadi16 addrmode3:$addr))]>;
2430 def LDRSB : AI3ld<0b1101, 1, (outs GPR:$Rt), (ins addrmode3:$addr), LdMiscFrm,
2431 IIC_iLoad_bh_r, "ldrsb", "\t$Rt, $addr",
2432 [(set GPR:$Rt, (sextloadi8 addrmode3:$addr))]>;
2434 let mayLoad = 1, neverHasSideEffects = 1, hasExtraDefRegAllocReq = 1 in {
2436 def LDRD : AI3ld<0b1101, 0, (outs GPR:$Rt, GPR:$Rt2), (ins addrmode3:$addr),
2437 LdMiscFrm, IIC_iLoad_d_r, "ldrd", "\t$Rt, $Rt2, $addr", []>,
2438 Requires<[IsARM, HasV5TE]>;
2441 def LDA : AIldracq<0b00, (outs GPR:$Rt), (ins addr_offset_none:$addr),
2442 NoItinerary, "lda", "\t$Rt, $addr", []>;
2443 def LDAB : AIldracq<0b10, (outs GPR:$Rt), (ins addr_offset_none:$addr),
2444 NoItinerary, "ldab", "\t$Rt, $addr", []>;
2445 def LDAH : AIldracq<0b11, (outs GPR:$Rt), (ins addr_offset_none:$addr),
2446 NoItinerary, "ldah", "\t$Rt, $addr", []>;
2449 multiclass AI2_ldridx<bit isByte, string opc,
2450 InstrItinClass iii, InstrItinClass iir> {
2451 def _PRE_IMM : AI2ldstidx<1, isByte, 1, (outs GPR:$Rt, GPR:$Rn_wb),
2452 (ins addrmode_imm12_pre:$addr), IndexModePre, LdFrm, iii,
2453 opc, "\t$Rt, $addr!", "$addr.base = $Rn_wb", []> {
2456 let Inst{23} = addr{12};
2457 let Inst{19-16} = addr{16-13};
2458 let Inst{11-0} = addr{11-0};
2459 let DecoderMethod = "DecodeLDRPreImm";
2462 def _PRE_REG : AI2ldstidx<1, isByte, 1, (outs GPR:$Rt, GPR:$Rn_wb),
2463 (ins ldst_so_reg:$addr), IndexModePre, LdFrm, iir,
2464 opc, "\t$Rt, $addr!", "$addr.base = $Rn_wb", []> {
2467 let Inst{23} = addr{12};
2468 let Inst{19-16} = addr{16-13};
2469 let Inst{11-0} = addr{11-0};
2471 let DecoderMethod = "DecodeLDRPreReg";
2474 def _POST_REG : AI2ldstidx<1, isByte, 0, (outs GPR:$Rt, GPR:$Rn_wb),
2475 (ins addr_offset_none:$addr, am2offset_reg:$offset),
2476 IndexModePost, LdFrm, iir,
2477 opc, "\t$Rt, $addr, $offset",
2478 "$addr.base = $Rn_wb", []> {
2484 let Inst{23} = offset{12};
2485 let Inst{19-16} = addr;
2486 let Inst{11-0} = offset{11-0};
2489 let DecoderMethod = "DecodeAddrMode2IdxInstruction";
2492 def _POST_IMM : AI2ldstidx<1, isByte, 0, (outs GPR:$Rt, GPR:$Rn_wb),
2493 (ins addr_offset_none:$addr, am2offset_imm:$offset),
2494 IndexModePost, LdFrm, iii,
2495 opc, "\t$Rt, $addr, $offset",
2496 "$addr.base = $Rn_wb", []> {
2502 let Inst{23} = offset{12};
2503 let Inst{19-16} = addr;
2504 let Inst{11-0} = offset{11-0};
2506 let DecoderMethod = "DecodeAddrMode2IdxInstruction";
2511 let mayLoad = 1, neverHasSideEffects = 1 in {
2512 // FIXME: for LDR_PRE_REG etc. the itineray should be either IIC_iLoad_ru or
2513 // IIC_iLoad_siu depending on whether it the offset register is shifted.
2514 defm LDR : AI2_ldridx<0, "ldr", IIC_iLoad_iu, IIC_iLoad_ru>;
2515 defm LDRB : AI2_ldridx<1, "ldrb", IIC_iLoad_bh_iu, IIC_iLoad_bh_ru>;
2518 multiclass AI3_ldridx<bits<4> op, string opc, InstrItinClass itin> {
2519 def _PRE : AI3ldstidx<op, 1, 1, (outs GPR:$Rt, GPR:$Rn_wb),
2520 (ins addrmode3_pre:$addr), IndexModePre,
2522 opc, "\t$Rt, $addr!", "$addr.base = $Rn_wb", []> {
2524 let Inst{23} = addr{8}; // U bit
2525 let Inst{22} = addr{13}; // 1 == imm8, 0 == Rm
2526 let Inst{19-16} = addr{12-9}; // Rn
2527 let Inst{11-8} = addr{7-4}; // imm7_4/zero
2528 let Inst{3-0} = addr{3-0}; // imm3_0/Rm
2529 let DecoderMethod = "DecodeAddrMode3Instruction";
2531 def _POST : AI3ldstidx<op, 1, 0, (outs GPR:$Rt, GPR:$Rn_wb),
2532 (ins addr_offset_none:$addr, am3offset:$offset),
2533 IndexModePost, LdMiscFrm, itin,
2534 opc, "\t$Rt, $addr, $offset", "$addr.base = $Rn_wb",
2538 let Inst{23} = offset{8}; // U bit
2539 let Inst{22} = offset{9}; // 1 == imm8, 0 == Rm
2540 let Inst{19-16} = addr;
2541 let Inst{11-8} = offset{7-4}; // imm7_4/zero
2542 let Inst{3-0} = offset{3-0}; // imm3_0/Rm
2543 let DecoderMethod = "DecodeAddrMode3Instruction";
2547 let mayLoad = 1, neverHasSideEffects = 1 in {
2548 defm LDRH : AI3_ldridx<0b1011, "ldrh", IIC_iLoad_bh_ru>;
2549 defm LDRSH : AI3_ldridx<0b1111, "ldrsh", IIC_iLoad_bh_ru>;
2550 defm LDRSB : AI3_ldridx<0b1101, "ldrsb", IIC_iLoad_bh_ru>;
2551 let hasExtraDefRegAllocReq = 1 in {
2552 def LDRD_PRE : AI3ldstidx<0b1101, 0, 1, (outs GPR:$Rt, GPR:$Rt2, GPR:$Rn_wb),
2553 (ins addrmode3_pre:$addr), IndexModePre,
2554 LdMiscFrm, IIC_iLoad_d_ru,
2555 "ldrd", "\t$Rt, $Rt2, $addr!",
2556 "$addr.base = $Rn_wb", []> {
2558 let Inst{23} = addr{8}; // U bit
2559 let Inst{22} = addr{13}; // 1 == imm8, 0 == Rm
2560 let Inst{19-16} = addr{12-9}; // Rn
2561 let Inst{11-8} = addr{7-4}; // imm7_4/zero
2562 let Inst{3-0} = addr{3-0}; // imm3_0/Rm
2563 let DecoderMethod = "DecodeAddrMode3Instruction";
2565 def LDRD_POST: AI3ldstidx<0b1101, 0, 0, (outs GPR:$Rt, GPR:$Rt2, GPR:$Rn_wb),
2566 (ins addr_offset_none:$addr, am3offset:$offset),
2567 IndexModePost, LdMiscFrm, IIC_iLoad_d_ru,
2568 "ldrd", "\t$Rt, $Rt2, $addr, $offset",
2569 "$addr.base = $Rn_wb", []> {
2572 let Inst{23} = offset{8}; // U bit
2573 let Inst{22} = offset{9}; // 1 == imm8, 0 == Rm
2574 let Inst{19-16} = addr;
2575 let Inst{11-8} = offset{7-4}; // imm7_4/zero
2576 let Inst{3-0} = offset{3-0}; // imm3_0/Rm
2577 let DecoderMethod = "DecodeAddrMode3Instruction";
2579 } // hasExtraDefRegAllocReq = 1
2580 } // mayLoad = 1, neverHasSideEffects = 1
2582 // LDRT, LDRBT, LDRSBT, LDRHT, LDRSHT.
2583 let mayLoad = 1, neverHasSideEffects = 1 in {
2584 def LDRT_POST_REG : AI2ldstidx<1, 0, 0, (outs GPR:$Rt, GPR:$Rn_wb),
2585 (ins addr_offset_none:$addr, am2offset_reg:$offset),
2586 IndexModePost, LdFrm, IIC_iLoad_ru,
2587 "ldrt", "\t$Rt, $addr, $offset",
2588 "$addr.base = $Rn_wb", []> {
2594 let Inst{23} = offset{12};
2595 let Inst{21} = 1; // overwrite
2596 let Inst{19-16} = addr;
2597 let Inst{11-5} = offset{11-5};
2599 let Inst{3-0} = offset{3-0};
2600 let DecoderMethod = "DecodeAddrMode2IdxInstruction";
2604 : AI2ldstidx<1, 0, 0, (outs GPR:$Rt, GPR:$Rn_wb),
2605 (ins addr_offset_none:$addr, am2offset_imm:$offset),
2606 IndexModePost, LdFrm, IIC_iLoad_ru,
2607 "ldrt", "\t$Rt, $addr, $offset", "$addr.base = $Rn_wb", []> {
2613 let Inst{23} = offset{12};
2614 let Inst{21} = 1; // overwrite
2615 let Inst{19-16} = addr;
2616 let Inst{11-0} = offset{11-0};
2617 let DecoderMethod = "DecodeAddrMode2IdxInstruction";
2620 def LDRBT_POST_REG : AI2ldstidx<1, 1, 0, (outs GPR:$Rt, GPR:$Rn_wb),
2621 (ins addr_offset_none:$addr, am2offset_reg:$offset),
2622 IndexModePost, LdFrm, IIC_iLoad_bh_ru,
2623 "ldrbt", "\t$Rt, $addr, $offset",
2624 "$addr.base = $Rn_wb", []> {
2630 let Inst{23} = offset{12};
2631 let Inst{21} = 1; // overwrite
2632 let Inst{19-16} = addr;
2633 let Inst{11-5} = offset{11-5};
2635 let Inst{3-0} = offset{3-0};
2636 let DecoderMethod = "DecodeAddrMode2IdxInstruction";
2640 : AI2ldstidx<1, 1, 0, (outs GPR:$Rt, GPR:$Rn_wb),
2641 (ins addr_offset_none:$addr, am2offset_imm:$offset),
2642 IndexModePost, LdFrm, IIC_iLoad_bh_ru,
2643 "ldrbt", "\t$Rt, $addr, $offset", "$addr.base = $Rn_wb", []> {
2649 let Inst{23} = offset{12};
2650 let Inst{21} = 1; // overwrite
2651 let Inst{19-16} = addr;
2652 let Inst{11-0} = offset{11-0};
2653 let DecoderMethod = "DecodeAddrMode2IdxInstruction";
2656 multiclass AI3ldrT<bits<4> op, string opc> {
2657 def i : AI3ldstidxT<op, 1, (outs GPR:$Rt, GPR:$base_wb),
2658 (ins addr_offset_none:$addr, postidx_imm8:$offset),
2659 IndexModePost, LdMiscFrm, IIC_iLoad_bh_ru, opc,
2660 "\t$Rt, $addr, $offset", "$addr.base = $base_wb", []> {
2662 let Inst{23} = offset{8};
2664 let Inst{11-8} = offset{7-4};
2665 let Inst{3-0} = offset{3-0};
2667 def r : AI3ldstidxT<op, 1, (outs GPRnopc:$Rt, GPRnopc:$base_wb),
2668 (ins addr_offset_none:$addr, postidx_reg:$Rm),
2669 IndexModePost, LdMiscFrm, IIC_iLoad_bh_ru, opc,
2670 "\t$Rt, $addr, $Rm", "$addr.base = $base_wb", []> {
2672 let Inst{23} = Rm{4};
2675 let Unpredictable{11-8} = 0b1111;
2676 let Inst{3-0} = Rm{3-0};
2677 let DecoderMethod = "DecodeLDR";
2681 defm LDRSBT : AI3ldrT<0b1101, "ldrsbt">;
2682 defm LDRHT : AI3ldrT<0b1011, "ldrht">;
2683 defm LDRSHT : AI3ldrT<0b1111, "ldrsht">;
2687 : ARMAsmPseudo<"ldrt${q} $Rt, $addr", (ins addr_offset_none:$addr, pred:$q),
2691 : ARMAsmPseudo<"ldrbt${q} $Rt, $addr", (ins addr_offset_none:$addr, pred:$q),
2696 // Stores with truncate
2697 def STRH : AI3str<0b1011, (outs), (ins GPR:$Rt, addrmode3:$addr), StMiscFrm,
2698 IIC_iStore_bh_r, "strh", "\t$Rt, $addr",
2699 [(truncstorei16 GPR:$Rt, addrmode3:$addr)]>;
2702 let mayStore = 1, neverHasSideEffects = 1, hasExtraSrcRegAllocReq = 1 in {
2703 def STRD : AI3str<0b1111, (outs), (ins GPR:$Rt, GPR:$Rt2, addrmode3:$addr),
2704 StMiscFrm, IIC_iStore_d_r, "strd", "\t$Rt, $Rt2, $addr", []>,
2705 Requires<[IsARM, HasV5TE]> {
2711 multiclass AI2_stridx<bit isByte, string opc,
2712 InstrItinClass iii, InstrItinClass iir> {
2713 def _PRE_IMM : AI2ldstidx<0, isByte, 1, (outs GPR:$Rn_wb),
2714 (ins GPR:$Rt, addrmode_imm12_pre:$addr), IndexModePre,
2716 opc, "\t$Rt, $addr!",
2717 "$addr.base = $Rn_wb,@earlyclobber $Rn_wb", []> {
2720 let Inst{23} = addr{12}; // U (add = ('U' == 1))
2721 let Inst{19-16} = addr{16-13}; // Rn
2722 let Inst{11-0} = addr{11-0}; // imm12
2723 let DecoderMethod = "DecodeSTRPreImm";
2726 def _PRE_REG : AI2ldstidx<0, isByte, 1, (outs GPR:$Rn_wb),
2727 (ins GPR:$Rt, ldst_so_reg:$addr),
2728 IndexModePre, StFrm, iir,
2729 opc, "\t$Rt, $addr!",
2730 "$addr.base = $Rn_wb,@earlyclobber $Rn_wb", []> {
2733 let Inst{23} = addr{12}; // U (add = ('U' == 1))
2734 let Inst{19-16} = addr{16-13}; // Rn
2735 let Inst{11-0} = addr{11-0};
2736 let Inst{4} = 0; // Inst{4} = 0
2737 let DecoderMethod = "DecodeSTRPreReg";
2739 def _POST_REG : AI2ldstidx<0, isByte, 0, (outs GPR:$Rn_wb),
2740 (ins GPR:$Rt, addr_offset_none:$addr, am2offset_reg:$offset),
2741 IndexModePost, StFrm, iir,
2742 opc, "\t$Rt, $addr, $offset",
2743 "$addr.base = $Rn_wb,@earlyclobber $Rn_wb", []> {
2749 let Inst{23} = offset{12};
2750 let Inst{19-16} = addr;
2751 let Inst{11-0} = offset{11-0};
2754 let DecoderMethod = "DecodeAddrMode2IdxInstruction";
2757 def _POST_IMM : AI2ldstidx<0, isByte, 0, (outs GPR:$Rn_wb),
2758 (ins GPR:$Rt, addr_offset_none:$addr, am2offset_imm:$offset),
2759 IndexModePost, StFrm, iii,
2760 opc, "\t$Rt, $addr, $offset",
2761 "$addr.base = $Rn_wb,@earlyclobber $Rn_wb", []> {
2767 let Inst{23} = offset{12};
2768 let Inst{19-16} = addr;
2769 let Inst{11-0} = offset{11-0};
2771 let DecoderMethod = "DecodeAddrMode2IdxInstruction";
2775 let mayStore = 1, neverHasSideEffects = 1 in {
2776 // FIXME: for STR_PRE_REG etc. the itineray should be either IIC_iStore_ru or
2777 // IIC_iStore_siu depending on whether it the offset register is shifted.
2778 defm STR : AI2_stridx<0, "str", IIC_iStore_iu, IIC_iStore_ru>;
2779 defm STRB : AI2_stridx<1, "strb", IIC_iStore_bh_iu, IIC_iStore_bh_ru>;
2782 def : ARMPat<(post_store GPR:$Rt, addr_offset_none:$addr,
2783 am2offset_reg:$offset),
2784 (STR_POST_REG GPR:$Rt, addr_offset_none:$addr,
2785 am2offset_reg:$offset)>;
2786 def : ARMPat<(post_store GPR:$Rt, addr_offset_none:$addr,
2787 am2offset_imm:$offset),
2788 (STR_POST_IMM GPR:$Rt, addr_offset_none:$addr,
2789 am2offset_imm:$offset)>;
2790 def : ARMPat<(post_truncsti8 GPR:$Rt, addr_offset_none:$addr,
2791 am2offset_reg:$offset),
2792 (STRB_POST_REG GPR:$Rt, addr_offset_none:$addr,
2793 am2offset_reg:$offset)>;
2794 def : ARMPat<(post_truncsti8 GPR:$Rt, addr_offset_none:$addr,
2795 am2offset_imm:$offset),
2796 (STRB_POST_IMM GPR:$Rt, addr_offset_none:$addr,
2797 am2offset_imm:$offset)>;
2799 // Pseudo-instructions for pattern matching the pre-indexed stores. We can't
2800 // put the patterns on the instruction definitions directly as ISel wants
2801 // the address base and offset to be separate operands, not a single
2802 // complex operand like we represent the instructions themselves. The
2803 // pseudos map between the two.
2804 let usesCustomInserter = 1,
2805 Constraints = "$Rn = $Rn_wb,@earlyclobber $Rn_wb" in {
2806 def STRi_preidx: ARMPseudoInst<(outs GPR:$Rn_wb),
2807 (ins GPR:$Rt, GPR:$Rn, am2offset_imm:$offset, pred:$p),
2810 (pre_store GPR:$Rt, GPR:$Rn, am2offset_imm:$offset))]>;
2811 def STRr_preidx: ARMPseudoInst<(outs GPR:$Rn_wb),
2812 (ins GPR:$Rt, GPR:$Rn, am2offset_reg:$offset, pred:$p),
2815 (pre_store GPR:$Rt, GPR:$Rn, am2offset_reg:$offset))]>;
2816 def STRBi_preidx: ARMPseudoInst<(outs GPR:$Rn_wb),
2817 (ins GPR:$Rt, GPR:$Rn, am2offset_imm:$offset, pred:$p),
2820 (pre_truncsti8 GPR:$Rt, GPR:$Rn, am2offset_imm:$offset))]>;
2821 def STRBr_preidx: ARMPseudoInst<(outs GPR:$Rn_wb),
2822 (ins GPR:$Rt, GPR:$Rn, am2offset_reg:$offset, pred:$p),
2825 (pre_truncsti8 GPR:$Rt, GPR:$Rn, am2offset_reg:$offset))]>;
2826 def STRH_preidx: ARMPseudoInst<(outs GPR:$Rn_wb),
2827 (ins GPR:$Rt, GPR:$Rn, am3offset:$offset, pred:$p),
2830 (pre_truncsti16 GPR:$Rt, GPR:$Rn, am3offset:$offset))]>;
2835 def STRH_PRE : AI3ldstidx<0b1011, 0, 1, (outs GPR:$Rn_wb),
2836 (ins GPR:$Rt, addrmode3_pre:$addr), IndexModePre,
2837 StMiscFrm, IIC_iStore_bh_ru,
2838 "strh", "\t$Rt, $addr!",
2839 "$addr.base = $Rn_wb,@earlyclobber $Rn_wb", []> {
2841 let Inst{23} = addr{8}; // U bit
2842 let Inst{22} = addr{13}; // 1 == imm8, 0 == Rm
2843 let Inst{19-16} = addr{12-9}; // Rn
2844 let Inst{11-8} = addr{7-4}; // imm7_4/zero
2845 let Inst{3-0} = addr{3-0}; // imm3_0/Rm
2846 let DecoderMethod = "DecodeAddrMode3Instruction";
2849 def STRH_POST : AI3ldstidx<0b1011, 0, 0, (outs GPR:$Rn_wb),
2850 (ins GPR:$Rt, addr_offset_none:$addr, am3offset:$offset),
2851 IndexModePost, StMiscFrm, IIC_iStore_bh_ru,
2852 "strh", "\t$Rt, $addr, $offset",
2853 "$addr.base = $Rn_wb,@earlyclobber $Rn_wb",
2854 [(set GPR:$Rn_wb, (post_truncsti16 GPR:$Rt,
2855 addr_offset_none:$addr,
2856 am3offset:$offset))]> {
2859 let Inst{23} = offset{8}; // U bit
2860 let Inst{22} = offset{9}; // 1 == imm8, 0 == Rm
2861 let Inst{19-16} = addr;
2862 let Inst{11-8} = offset{7-4}; // imm7_4/zero
2863 let Inst{3-0} = offset{3-0}; // imm3_0/Rm
2864 let DecoderMethod = "DecodeAddrMode3Instruction";
2867 let mayStore = 1, neverHasSideEffects = 1, hasExtraSrcRegAllocReq = 1 in {
2868 def STRD_PRE : AI3ldstidx<0b1111, 0, 1, (outs GPR:$Rn_wb),
2869 (ins GPR:$Rt, GPR:$Rt2, addrmode3_pre:$addr),
2870 IndexModePre, StMiscFrm, IIC_iStore_d_ru,
2871 "strd", "\t$Rt, $Rt2, $addr!",
2872 "$addr.base = $Rn_wb", []> {
2874 let Inst{23} = addr{8}; // U bit
2875 let Inst{22} = addr{13}; // 1 == imm8, 0 == Rm
2876 let Inst{19-16} = addr{12-9}; // Rn
2877 let Inst{11-8} = addr{7-4}; // imm7_4/zero
2878 let Inst{3-0} = addr{3-0}; // imm3_0/Rm
2879 let DecoderMethod = "DecodeAddrMode3Instruction";
2882 def STRD_POST: AI3ldstidx<0b1111, 0, 0, (outs GPR:$Rn_wb),
2883 (ins GPR:$Rt, GPR:$Rt2, addr_offset_none:$addr,
2885 IndexModePost, StMiscFrm, IIC_iStore_d_ru,
2886 "strd", "\t$Rt, $Rt2, $addr, $offset",
2887 "$addr.base = $Rn_wb", []> {
2890 let Inst{23} = offset{8}; // U bit
2891 let Inst{22} = offset{9}; // 1 == imm8, 0 == Rm
2892 let Inst{19-16} = addr;
2893 let Inst{11-8} = offset{7-4}; // imm7_4/zero
2894 let Inst{3-0} = offset{3-0}; // imm3_0/Rm
2895 let DecoderMethod = "DecodeAddrMode3Instruction";
2897 } // mayStore = 1, neverHasSideEffects = 1, hasExtraSrcRegAllocReq = 1
2899 // STRT, STRBT, and STRHT
2901 def STRBT_POST_REG : AI2ldstidx<0, 1, 0, (outs GPR:$Rn_wb),
2902 (ins GPR:$Rt, addr_offset_none:$addr, am2offset_reg:$offset),
2903 IndexModePost, StFrm, IIC_iStore_bh_ru,
2904 "strbt", "\t$Rt, $addr, $offset",
2905 "$addr.base = $Rn_wb", []> {
2911 let Inst{23} = offset{12};
2912 let Inst{21} = 1; // overwrite
2913 let Inst{19-16} = addr;
2914 let Inst{11-5} = offset{11-5};
2916 let Inst{3-0} = offset{3-0};
2917 let DecoderMethod = "DecodeAddrMode2IdxInstruction";
2921 : AI2ldstidx<0, 1, 0, (outs GPR:$Rn_wb),
2922 (ins GPR:$Rt, addr_offset_none:$addr, am2offset_imm:$offset),
2923 IndexModePost, StFrm, IIC_iStore_bh_ru,
2924 "strbt", "\t$Rt, $addr, $offset", "$addr.base = $Rn_wb", []> {
2930 let Inst{23} = offset{12};
2931 let Inst{21} = 1; // overwrite
2932 let Inst{19-16} = addr;
2933 let Inst{11-0} = offset{11-0};
2934 let DecoderMethod = "DecodeAddrMode2IdxInstruction";
2938 : ARMAsmPseudo<"strbt${q} $Rt, $addr",
2939 (ins GPR:$Rt, addr_offset_none:$addr, pred:$q)>;
2941 let mayStore = 1, neverHasSideEffects = 1 in {
2942 def STRT_POST_REG : AI2ldstidx<0, 0, 0, (outs GPR:$Rn_wb),
2943 (ins GPR:$Rt, addr_offset_none:$addr, am2offset_reg:$offset),
2944 IndexModePost, StFrm, IIC_iStore_ru,
2945 "strt", "\t$Rt, $addr, $offset",
2946 "$addr.base = $Rn_wb", []> {
2952 let Inst{23} = offset{12};
2953 let Inst{21} = 1; // overwrite
2954 let Inst{19-16} = addr;
2955 let Inst{11-5} = offset{11-5};
2957 let Inst{3-0} = offset{3-0};
2958 let DecoderMethod = "DecodeAddrMode2IdxInstruction";
2962 : AI2ldstidx<0, 0, 0, (outs GPR:$Rn_wb),
2963 (ins GPR:$Rt, addr_offset_none:$addr, am2offset_imm:$offset),
2964 IndexModePost, StFrm, IIC_iStore_ru,
2965 "strt", "\t$Rt, $addr, $offset", "$addr.base = $Rn_wb", []> {
2971 let Inst{23} = offset{12};
2972 let Inst{21} = 1; // overwrite
2973 let Inst{19-16} = addr;
2974 let Inst{11-0} = offset{11-0};
2975 let DecoderMethod = "DecodeAddrMode2IdxInstruction";
2980 : ARMAsmPseudo<"strt${q} $Rt, $addr",
2981 (ins GPR:$Rt, addr_offset_none:$addr, pred:$q)>;
2983 multiclass AI3strT<bits<4> op, string opc> {
2984 def i : AI3ldstidxT<op, 0, (outs GPR:$base_wb),
2985 (ins GPR:$Rt, addr_offset_none:$addr, postidx_imm8:$offset),
2986 IndexModePost, StMiscFrm, IIC_iStore_bh_ru, opc,
2987 "\t$Rt, $addr, $offset", "$addr.base = $base_wb", []> {
2989 let Inst{23} = offset{8};
2991 let Inst{11-8} = offset{7-4};
2992 let Inst{3-0} = offset{3-0};
2994 def r : AI3ldstidxT<op, 0, (outs GPR:$base_wb),
2995 (ins GPR:$Rt, addr_offset_none:$addr, postidx_reg:$Rm),
2996 IndexModePost, StMiscFrm, IIC_iStore_bh_ru, opc,
2997 "\t$Rt, $addr, $Rm", "$addr.base = $base_wb", []> {
2999 let Inst{23} = Rm{4};
3002 let Inst{3-0} = Rm{3-0};
3007 defm STRHT : AI3strT<0b1011, "strht">;
3009 def STL : AIstrrel<0b00, (outs), (ins GPR:$Rt, addr_offset_none:$addr),
3010 NoItinerary, "stl", "\t$Rt, $addr", []>;
3011 def STLB : AIstrrel<0b10, (outs), (ins GPR:$Rt, addr_offset_none:$addr),
3012 NoItinerary, "stlb", "\t$Rt, $addr", []>;
3013 def STLH : AIstrrel<0b11, (outs), (ins GPR:$Rt, addr_offset_none:$addr),
3014 NoItinerary, "stlh", "\t$Rt, $addr", []>;
3016 //===----------------------------------------------------------------------===//
3017 // Load / store multiple Instructions.
3020 multiclass arm_ldst_mult<string asm, string sfx, bit L_bit, bit P_bit, Format f,
3021 InstrItinClass itin, InstrItinClass itin_upd> {
3022 // IA is the default, so no need for an explicit suffix on the
3023 // mnemonic here. Without it is the canonical spelling.
3025 AXI4<(outs), (ins GPR:$Rn, pred:$p, reglist:$regs, variable_ops),
3026 IndexModeNone, f, itin,
3027 !strconcat(asm, "${p}\t$Rn, $regs", sfx), "", []> {
3028 let Inst{24-23} = 0b01; // Increment After
3029 let Inst{22} = P_bit;
3030 let Inst{21} = 0; // No writeback
3031 let Inst{20} = L_bit;
3034 AXI4<(outs GPR:$wb), (ins GPR:$Rn, pred:$p, reglist:$regs, variable_ops),
3035 IndexModeUpd, f, itin_upd,
3036 !strconcat(asm, "${p}\t$Rn!, $regs", sfx), "$Rn = $wb", []> {
3037 let Inst{24-23} = 0b01; // Increment After
3038 let Inst{22} = P_bit;
3039 let Inst{21} = 1; // Writeback
3040 let Inst{20} = L_bit;
3042 let DecoderMethod = "DecodeMemMultipleWritebackInstruction";
3045 AXI4<(outs), (ins GPR:$Rn, pred:$p, reglist:$regs, variable_ops),
3046 IndexModeNone, f, itin,
3047 !strconcat(asm, "da${p}\t$Rn, $regs", sfx), "", []> {
3048 let Inst{24-23} = 0b00; // Decrement After
3049 let Inst{22} = P_bit;
3050 let Inst{21} = 0; // No writeback
3051 let Inst{20} = L_bit;
3054 AXI4<(outs GPR:$wb), (ins GPR:$Rn, pred:$p, reglist:$regs, variable_ops),
3055 IndexModeUpd, f, itin_upd,
3056 !strconcat(asm, "da${p}\t$Rn!, $regs", sfx), "$Rn = $wb", []> {
3057 let Inst{24-23} = 0b00; // Decrement After
3058 let Inst{22} = P_bit;
3059 let Inst{21} = 1; // Writeback
3060 let Inst{20} = L_bit;
3062 let DecoderMethod = "DecodeMemMultipleWritebackInstruction";
3065 AXI4<(outs), (ins GPR:$Rn, pred:$p, reglist:$regs, variable_ops),
3066 IndexModeNone, f, itin,
3067 !strconcat(asm, "db${p}\t$Rn, $regs", sfx), "", []> {
3068 let Inst{24-23} = 0b10; // Decrement Before
3069 let Inst{22} = P_bit;
3070 let Inst{21} = 0; // No writeback
3071 let Inst{20} = L_bit;
3074 AXI4<(outs GPR:$wb), (ins GPR:$Rn, pred:$p, reglist:$regs, variable_ops),
3075 IndexModeUpd, f, itin_upd,
3076 !strconcat(asm, "db${p}\t$Rn!, $regs", sfx), "$Rn = $wb", []> {
3077 let Inst{24-23} = 0b10; // Decrement Before
3078 let Inst{22} = P_bit;
3079 let Inst{21} = 1; // Writeback
3080 let Inst{20} = L_bit;
3082 let DecoderMethod = "DecodeMemMultipleWritebackInstruction";
3085 AXI4<(outs), (ins GPR:$Rn, pred:$p, reglist:$regs, variable_ops),
3086 IndexModeNone, f, itin,
3087 !strconcat(asm, "ib${p}\t$Rn, $regs", sfx), "", []> {
3088 let Inst{24-23} = 0b11; // Increment Before
3089 let Inst{22} = P_bit;
3090 let Inst{21} = 0; // No writeback
3091 let Inst{20} = L_bit;
3094 AXI4<(outs GPR:$wb), (ins GPR:$Rn, pred:$p, reglist:$regs, variable_ops),
3095 IndexModeUpd, f, itin_upd,
3096 !strconcat(asm, "ib${p}\t$Rn!, $regs", sfx), "$Rn = $wb", []> {
3097 let Inst{24-23} = 0b11; // Increment Before
3098 let Inst{22} = P_bit;
3099 let Inst{21} = 1; // Writeback
3100 let Inst{20} = L_bit;
3102 let DecoderMethod = "DecodeMemMultipleWritebackInstruction";
3106 let neverHasSideEffects = 1 in {
3108 let mayLoad = 1, hasExtraDefRegAllocReq = 1 in
3109 defm LDM : arm_ldst_mult<"ldm", "", 1, 0, LdStMulFrm, IIC_iLoad_m,
3112 let mayStore = 1, hasExtraSrcRegAllocReq = 1 in
3113 defm STM : arm_ldst_mult<"stm", "", 0, 0, LdStMulFrm, IIC_iStore_m,
3116 } // neverHasSideEffects
3118 // FIXME: remove when we have a way to marking a MI with these properties.
3119 // FIXME: Should pc be an implicit operand like PICADD, etc?
3120 let isReturn = 1, isTerminator = 1, isBarrier = 1, mayLoad = 1,
3121 hasExtraDefRegAllocReq = 1, isCodeGenOnly = 1 in
3122 def LDMIA_RET : ARMPseudoExpand<(outs GPR:$wb), (ins GPR:$Rn, pred:$p,
3123 reglist:$regs, variable_ops),
3124 4, IIC_iLoad_mBr, [],
3125 (LDMIA_UPD GPR:$wb, GPR:$Rn, pred:$p, reglist:$regs)>,
3126 RegConstraint<"$Rn = $wb">;
3128 let mayLoad = 1, hasExtraDefRegAllocReq = 1 in
3129 defm sysLDM : arm_ldst_mult<"ldm", " ^", 1, 1, LdStMulFrm, IIC_iLoad_m,
3132 let mayStore = 1, hasExtraSrcRegAllocReq = 1 in
3133 defm sysSTM : arm_ldst_mult<"stm", " ^", 0, 1, LdStMulFrm, IIC_iStore_m,
3138 //===----------------------------------------------------------------------===//
3139 // Move Instructions.
3142 let neverHasSideEffects = 1 in
3143 def MOVr : AsI1<0b1101, (outs GPR:$Rd), (ins GPR:$Rm), DPFrm, IIC_iMOVr,
3144 "mov", "\t$Rd, $Rm", []>, UnaryDP, Sched<[WriteALU]> {
3148 let Inst{19-16} = 0b0000;
3149 let Inst{11-4} = 0b00000000;
3152 let Inst{15-12} = Rd;
3155 // A version for the smaller set of tail call registers.
3156 let neverHasSideEffects = 1 in
3157 def MOVr_TC : AsI1<0b1101, (outs tcGPR:$Rd), (ins tcGPR:$Rm), DPFrm,
3158 IIC_iMOVr, "mov", "\t$Rd, $Rm", []>, UnaryDP, Sched<[WriteALU]> {
3162 let Inst{11-4} = 0b00000000;
3165 let Inst{15-12} = Rd;
3168 def MOVsr : AsI1<0b1101, (outs GPRnopc:$Rd), (ins shift_so_reg_reg:$src),
3169 DPSoRegRegFrm, IIC_iMOVsr,
3170 "mov", "\t$Rd, $src",
3171 [(set GPRnopc:$Rd, shift_so_reg_reg:$src)]>, UnaryDP,
3175 let Inst{15-12} = Rd;
3176 let Inst{19-16} = 0b0000;
3177 let Inst{11-8} = src{11-8};
3179 let Inst{6-5} = src{6-5};
3181 let Inst{3-0} = src{3-0};
3185 def MOVsi : AsI1<0b1101, (outs GPR:$Rd), (ins shift_so_reg_imm:$src),
3186 DPSoRegImmFrm, IIC_iMOVsr,
3187 "mov", "\t$Rd, $src", [(set GPR:$Rd, shift_so_reg_imm:$src)]>,
3188 UnaryDP, Sched<[WriteALU]> {
3191 let Inst{15-12} = Rd;
3192 let Inst{19-16} = 0b0000;
3193 let Inst{11-5} = src{11-5};
3195 let Inst{3-0} = src{3-0};
3199 let isReMaterializable = 1, isAsCheapAsAMove = 1, isMoveImm = 1 in
3200 def MOVi : AsI1<0b1101, (outs GPR:$Rd), (ins so_imm:$imm), DPFrm, IIC_iMOVi,
3201 "mov", "\t$Rd, $imm", [(set GPR:$Rd, so_imm:$imm)]>, UnaryDP,
3206 let Inst{15-12} = Rd;
3207 let Inst{19-16} = 0b0000;
3208 let Inst{11-0} = imm;
3211 let isReMaterializable = 1, isAsCheapAsAMove = 1, isMoveImm = 1 in
3212 def MOVi16 : AI1<0b1000, (outs GPR:$Rd), (ins imm0_65535_expr:$imm),
3214 "movw", "\t$Rd, $imm",
3215 [(set GPR:$Rd, imm0_65535:$imm)]>,
3216 Requires<[IsARM, HasV6T2]>, UnaryDP, Sched<[WriteALU]> {
3219 let Inst{15-12} = Rd;
3220 let Inst{11-0} = imm{11-0};
3221 let Inst{19-16} = imm{15-12};
3224 let DecoderMethod = "DecodeArmMOVTWInstruction";
3227 def : InstAlias<"mov${p} $Rd, $imm",
3228 (MOVi16 GPR:$Rd, imm0_65535_expr:$imm, pred:$p)>,
3231 def MOVi16_ga_pcrel : PseudoInst<(outs GPR:$Rd),
3232 (ins i32imm:$addr, pclabel:$id), IIC_iMOVi, []>,
3235 let Constraints = "$src = $Rd" in {
3236 def MOVTi16 : AI1<0b1010, (outs GPRnopc:$Rd),
3237 (ins GPR:$src, imm0_65535_expr:$imm),
3239 "movt", "\t$Rd, $imm",
3241 (or (and GPR:$src, 0xffff),
3242 lo16AllZero:$imm))]>, UnaryDP,
3243 Requires<[IsARM, HasV6T2]>, Sched<[WriteALU]> {
3246 let Inst{15-12} = Rd;
3247 let Inst{11-0} = imm{11-0};
3248 let Inst{19-16} = imm{15-12};
3251 let DecoderMethod = "DecodeArmMOVTWInstruction";
3254 def MOVTi16_ga_pcrel : PseudoInst<(outs GPR:$Rd),
3255 (ins GPR:$src, i32imm:$addr, pclabel:$id), IIC_iMOVi, []>,
3260 def : ARMPat<(or GPR:$src, 0xffff0000), (MOVTi16 GPR:$src, 0xffff)>,
3261 Requires<[IsARM, HasV6T2]>;
3263 let Uses = [CPSR] in
3264 def RRX: PseudoInst<(outs GPR:$Rd), (ins GPR:$Rm), IIC_iMOVsi,
3265 [(set GPR:$Rd, (ARMrrx GPR:$Rm))]>, UnaryDP,
3266 Requires<[IsARM]>, Sched<[WriteALU]>;
3268 // These aren't really mov instructions, but we have to define them this way
3269 // due to flag operands.
3271 let Defs = [CPSR] in {
3272 def MOVsrl_flag : PseudoInst<(outs GPR:$dst), (ins GPR:$src), IIC_iMOVsi,
3273 [(set GPR:$dst, (ARMsrl_flag GPR:$src))]>, UnaryDP,
3274 Sched<[WriteALU]>, Requires<[IsARM]>;
3275 def MOVsra_flag : PseudoInst<(outs GPR:$dst), (ins GPR:$src), IIC_iMOVsi,
3276 [(set GPR:$dst, (ARMsra_flag GPR:$src))]>, UnaryDP,
3277 Sched<[WriteALU]>, Requires<[IsARM]>;
3280 //===----------------------------------------------------------------------===//
3281 // Extend Instructions.
3286 def SXTB : AI_ext_rrot<0b01101010,
3287 "sxtb", UnOpFrag<(sext_inreg node:$Src, i8)>>;
3288 def SXTH : AI_ext_rrot<0b01101011,
3289 "sxth", UnOpFrag<(sext_inreg node:$Src, i16)>>;
3291 def SXTAB : AI_exta_rrot<0b01101010,
3292 "sxtab", BinOpFrag<(add node:$LHS, (sext_inreg node:$RHS, i8))>>;
3293 def SXTAH : AI_exta_rrot<0b01101011,
3294 "sxtah", BinOpFrag<(add node:$LHS, (sext_inreg node:$RHS,i16))>>;
3296 def SXTB16 : AI_ext_rrot_np<0b01101000, "sxtb16">;
3298 def SXTAB16 : AI_exta_rrot_np<0b01101000, "sxtab16">;
3302 let AddedComplexity = 16 in {
3303 def UXTB : AI_ext_rrot<0b01101110,
3304 "uxtb" , UnOpFrag<(and node:$Src, 0x000000FF)>>;
3305 def UXTH : AI_ext_rrot<0b01101111,
3306 "uxth" , UnOpFrag<(and node:$Src, 0x0000FFFF)>>;
3307 def UXTB16 : AI_ext_rrot<0b01101100,
3308 "uxtb16", UnOpFrag<(and node:$Src, 0x00FF00FF)>>;
3310 // FIXME: This pattern incorrectly assumes the shl operator is a rotate.
3311 // The transformation should probably be done as a combiner action
3312 // instead so we can include a check for masking back in the upper
3313 // eight bits of the source into the lower eight bits of the result.
3314 //def : ARMV6Pat<(and (shl GPR:$Src, (i32 8)), 0xFF00FF),
3315 // (UXTB16r_rot GPR:$Src, 3)>;
3316 def : ARMV6Pat<(and (srl GPR:$Src, (i32 8)), 0xFF00FF),
3317 (UXTB16 GPR:$Src, 1)>;
3319 def UXTAB : AI_exta_rrot<0b01101110, "uxtab",
3320 BinOpFrag<(add node:$LHS, (and node:$RHS, 0x00FF))>>;
3321 def UXTAH : AI_exta_rrot<0b01101111, "uxtah",
3322 BinOpFrag<(add node:$LHS, (and node:$RHS, 0xFFFF))>>;
3325 // This isn't safe in general, the add is two 16-bit units, not a 32-bit add.
3326 def UXTAB16 : AI_exta_rrot_np<0b01101100, "uxtab16">;
3329 def SBFX : I<(outs GPRnopc:$Rd),
3330 (ins GPRnopc:$Rn, imm0_31:$lsb, imm1_32:$width),
3331 AddrMode1, 4, IndexModeNone, DPFrm, IIC_iUNAsi,
3332 "sbfx", "\t$Rd, $Rn, $lsb, $width", "", []>,
3333 Requires<[IsARM, HasV6T2]> {
3338 let Inst{27-21} = 0b0111101;
3339 let Inst{6-4} = 0b101;
3340 let Inst{20-16} = width;
3341 let Inst{15-12} = Rd;
3342 let Inst{11-7} = lsb;
3346 def UBFX : I<(outs GPRnopc:$Rd),
3347 (ins GPRnopc:$Rn, imm0_31:$lsb, imm1_32:$width),
3348 AddrMode1, 4, IndexModeNone, DPFrm, IIC_iUNAsi,
3349 "ubfx", "\t$Rd, $Rn, $lsb, $width", "", []>,
3350 Requires<[IsARM, HasV6T2]> {
3355 let Inst{27-21} = 0b0111111;
3356 let Inst{6-4} = 0b101;
3357 let Inst{20-16} = width;
3358 let Inst{15-12} = Rd;
3359 let Inst{11-7} = lsb;
3363 //===----------------------------------------------------------------------===//
3364 // Arithmetic Instructions.
3367 defm ADD : AsI1_bin_irs<0b0100, "add",
3368 IIC_iALUi, IIC_iALUr, IIC_iALUsr,
3369 BinOpFrag<(add node:$LHS, node:$RHS)>, 1>;
3370 defm SUB : AsI1_bin_irs<0b0010, "sub",
3371 IIC_iALUi, IIC_iALUr, IIC_iALUsr,
3372 BinOpFrag<(sub node:$LHS, node:$RHS)>>;
3374 // ADD and SUB with 's' bit set.
3376 // Currently, ADDS/SUBS are pseudo opcodes that exist only in the
3377 // selection DAG. They are "lowered" to real ADD/SUB opcodes by
3378 // AdjustInstrPostInstrSelection where we determine whether or not to
3379 // set the "s" bit based on CPSR liveness.
3381 // FIXME: Eliminate ADDS/SUBS pseudo opcodes after adding tablegen
3382 // support for an optional CPSR definition that corresponds to the DAG
3383 // node's second value. We can then eliminate the implicit def of CPSR.
3384 defm ADDS : AsI1_bin_s_irs<IIC_iALUi, IIC_iALUr, IIC_iALUsr,
3385 BinOpFrag<(ARMaddc node:$LHS, node:$RHS)>, 1>;
3386 defm SUBS : AsI1_bin_s_irs<IIC_iALUi, IIC_iALUr, IIC_iALUsr,
3387 BinOpFrag<(ARMsubc node:$LHS, node:$RHS)>>;
3389 defm ADC : AI1_adde_sube_irs<0b0101, "adc",
3390 BinOpWithFlagFrag<(ARMadde node:$LHS, node:$RHS, node:$FLAG)>, 1>;
3391 defm SBC : AI1_adde_sube_irs<0b0110, "sbc",
3392 BinOpWithFlagFrag<(ARMsube node:$LHS, node:$RHS, node:$FLAG)>>;
3394 defm RSB : AsI1_rbin_irs<0b0011, "rsb",
3395 IIC_iALUi, IIC_iALUr, IIC_iALUsr,
3396 BinOpFrag<(sub node:$LHS, node:$RHS)>>;
3398 // FIXME: Eliminate them if we can write def : Pat patterns which defines
3399 // CPSR and the implicit def of CPSR is not needed.
3400 defm RSBS : AsI1_rbin_s_is<IIC_iALUi, IIC_iALUr, IIC_iALUsr,
3401 BinOpFrag<(ARMsubc node:$LHS, node:$RHS)>>;
3403 defm RSC : AI1_rsc_irs<0b0111, "rsc",
3404 BinOpWithFlagFrag<(ARMsube node:$LHS, node:$RHS, node:$FLAG)>>;
3406 // (sub X, imm) gets canonicalized to (add X, -imm). Match this form.
3407 // The assume-no-carry-in form uses the negation of the input since add/sub
3408 // assume opposite meanings of the carry flag (i.e., carry == !borrow).
3409 // See the definition of AddWithCarry() in the ARM ARM A2.2.1 for the gory
3411 def : ARMPat<(add GPR:$src, so_imm_neg:$imm),
3412 (SUBri GPR:$src, so_imm_neg:$imm)>;
3413 def : ARMPat<(ARMaddc GPR:$src, so_imm_neg:$imm),
3414 (SUBSri GPR:$src, so_imm_neg:$imm)>;
3416 def : ARMPat<(add GPR:$src, imm0_65535_neg:$imm),
3417 (SUBrr GPR:$src, (MOVi16 (imm_neg_XFORM imm:$imm)))>,
3418 Requires<[IsARM, HasV6T2]>;
3419 def : ARMPat<(ARMaddc GPR:$src, imm0_65535_neg:$imm),
3420 (SUBSrr GPR:$src, (MOVi16 (imm_neg_XFORM imm:$imm)))>,
3421 Requires<[IsARM, HasV6T2]>;
3423 // The with-carry-in form matches bitwise not instead of the negation.
3424 // Effectively, the inverse interpretation of the carry flag already accounts
3425 // for part of the negation.
3426 def : ARMPat<(ARMadde GPR:$src, so_imm_not:$imm, CPSR),
3427 (SBCri GPR:$src, so_imm_not:$imm)>;
3428 def : ARMPat<(ARMadde GPR:$src, imm0_65535_neg:$imm, CPSR),
3429 (SBCrr GPR:$src, (MOVi16 (imm_not_XFORM imm:$imm)))>;
3431 // Note: These are implemented in C++ code, because they have to generate
3432 // ADD/SUBrs instructions, which use a complex pattern that a xform function
3434 // (mul X, 2^n+1) -> (add (X << n), X)
3435 // (mul X, 2^n-1) -> (rsb X, (X << n))
3437 // ARM Arithmetic Instruction
3438 // GPR:$dst = GPR:$a op GPR:$b
3439 class AAI<bits<8> op27_20, bits<8> op11_4, string opc,
3440 list<dag> pattern = [],
3441 dag iops = (ins GPRnopc:$Rn, GPRnopc:$Rm),
3442 string asm = "\t$Rd, $Rn, $Rm">
3443 : AI<(outs GPRnopc:$Rd), iops, DPFrm, IIC_iALUr, opc, asm, pattern>,
3444 Sched<[WriteALU, ReadALU, ReadALU]> {
3448 let Inst{27-20} = op27_20;
3449 let Inst{11-4} = op11_4;
3450 let Inst{19-16} = Rn;
3451 let Inst{15-12} = Rd;
3454 let Unpredictable{11-8} = 0b1111;
3457 // Saturating add/subtract
3459 let DecoderMethod = "DecodeQADDInstruction" in
3460 def QADD : AAI<0b00010000, 0b00000101, "qadd",
3461 [(set GPRnopc:$Rd, (int_arm_qadd GPRnopc:$Rm, GPRnopc:$Rn))],
3462 (ins GPRnopc:$Rm, GPRnopc:$Rn), "\t$Rd, $Rm, $Rn">;
3464 def QSUB : AAI<0b00010010, 0b00000101, "qsub",
3465 [(set GPRnopc:$Rd, (int_arm_qsub GPRnopc:$Rm, GPRnopc:$Rn))],
3466 (ins GPRnopc:$Rm, GPRnopc:$Rn), "\t$Rd, $Rm, $Rn">;
3467 def QDADD : AAI<0b00010100, 0b00000101, "qdadd", [],
3468 (ins GPRnopc:$Rm, GPRnopc:$Rn),
3470 def QDSUB : AAI<0b00010110, 0b00000101, "qdsub", [],
3471 (ins GPRnopc:$Rm, GPRnopc:$Rn),
3474 def QADD16 : AAI<0b01100010, 0b11110001, "qadd16">;
3475 def QADD8 : AAI<0b01100010, 0b11111001, "qadd8">;
3476 def QASX : AAI<0b01100010, 0b11110011, "qasx">;
3477 def QSAX : AAI<0b01100010, 0b11110101, "qsax">;
3478 def QSUB16 : AAI<0b01100010, 0b11110111, "qsub16">;
3479 def QSUB8 : AAI<0b01100010, 0b11111111, "qsub8">;
3480 def UQADD16 : AAI<0b01100110, 0b11110001, "uqadd16">;
3481 def UQADD8 : AAI<0b01100110, 0b11111001, "uqadd8">;
3482 def UQASX : AAI<0b01100110, 0b11110011, "uqasx">;
3483 def UQSAX : AAI<0b01100110, 0b11110101, "uqsax">;
3484 def UQSUB16 : AAI<0b01100110, 0b11110111, "uqsub16">;
3485 def UQSUB8 : AAI<0b01100110, 0b11111111, "uqsub8">;
3487 // Signed/Unsigned add/subtract
3489 def SASX : AAI<0b01100001, 0b11110011, "sasx">;
3490 def SADD16 : AAI<0b01100001, 0b11110001, "sadd16">;
3491 def SADD8 : AAI<0b01100001, 0b11111001, "sadd8">;
3492 def SSAX : AAI<0b01100001, 0b11110101, "ssax">;
3493 def SSUB16 : AAI<0b01100001, 0b11110111, "ssub16">;
3494 def SSUB8 : AAI<0b01100001, 0b11111111, "ssub8">;
3495 def UASX : AAI<0b01100101, 0b11110011, "uasx">;
3496 def UADD16 : AAI<0b01100101, 0b11110001, "uadd16">;
3497 def UADD8 : AAI<0b01100101, 0b11111001, "uadd8">;
3498 def USAX : AAI<0b01100101, 0b11110101, "usax">;
3499 def USUB16 : AAI<0b01100101, 0b11110111, "usub16">;
3500 def USUB8 : AAI<0b01100101, 0b11111111, "usub8">;
3502 // Signed/Unsigned halving add/subtract
3504 def SHASX : AAI<0b01100011, 0b11110011, "shasx">;
3505 def SHADD16 : AAI<0b01100011, 0b11110001, "shadd16">;
3506 def SHADD8 : AAI<0b01100011, 0b11111001, "shadd8">;
3507 def SHSAX : AAI<0b01100011, 0b11110101, "shsax">;
3508 def SHSUB16 : AAI<0b01100011, 0b11110111, "shsub16">;
3509 def SHSUB8 : AAI<0b01100011, 0b11111111, "shsub8">;
3510 def UHASX : AAI<0b01100111, 0b11110011, "uhasx">;
3511 def UHADD16 : AAI<0b01100111, 0b11110001, "uhadd16">;
3512 def UHADD8 : AAI<0b01100111, 0b11111001, "uhadd8">;
3513 def UHSAX : AAI<0b01100111, 0b11110101, "uhsax">;
3514 def UHSUB16 : AAI<0b01100111, 0b11110111, "uhsub16">;
3515 def UHSUB8 : AAI<0b01100111, 0b11111111, "uhsub8">;
3517 // Unsigned Sum of Absolute Differences [and Accumulate].
3519 def USAD8 : AI<(outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm),
3520 MulFrm /* for convenience */, NoItinerary, "usad8",
3521 "\t$Rd, $Rn, $Rm", []>,
3522 Requires<[IsARM, HasV6]>, Sched<[WriteALU, ReadALU, ReadALU]> {
3526 let Inst{27-20} = 0b01111000;
3527 let Inst{15-12} = 0b1111;
3528 let Inst{7-4} = 0b0001;
3529 let Inst{19-16} = Rd;
3530 let Inst{11-8} = Rm;
3533 def USADA8 : AI<(outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm, GPR:$Ra),
3534 MulFrm /* for convenience */, NoItinerary, "usada8",
3535 "\t$Rd, $Rn, $Rm, $Ra", []>,
3536 Requires<[IsARM, HasV6]>, Sched<[WriteALU, ReadALU, ReadALU]>{
3541 let Inst{27-20} = 0b01111000;
3542 let Inst{7-4} = 0b0001;
3543 let Inst{19-16} = Rd;
3544 let Inst{15-12} = Ra;
3545 let Inst{11-8} = Rm;
3549 // Signed/Unsigned saturate
3551 def SSAT : AI<(outs GPRnopc:$Rd),
3552 (ins imm1_32:$sat_imm, GPRnopc:$Rn, shift_imm:$sh),
3553 SatFrm, NoItinerary, "ssat", "\t$Rd, $sat_imm, $Rn$sh", []> {
3558 let Inst{27-21} = 0b0110101;
3559 let Inst{5-4} = 0b01;
3560 let Inst{20-16} = sat_imm;
3561 let Inst{15-12} = Rd;
3562 let Inst{11-7} = sh{4-0};
3563 let Inst{6} = sh{5};
3567 def SSAT16 : AI<(outs GPRnopc:$Rd),
3568 (ins imm1_16:$sat_imm, GPRnopc:$Rn), SatFrm,
3569 NoItinerary, "ssat16", "\t$Rd, $sat_imm, $Rn", []> {
3573 let Inst{27-20} = 0b01101010;
3574 let Inst{11-4} = 0b11110011;
3575 let Inst{15-12} = Rd;
3576 let Inst{19-16} = sat_imm;
3580 def USAT : AI<(outs GPRnopc:$Rd),
3581 (ins imm0_31:$sat_imm, GPRnopc:$Rn, shift_imm:$sh),
3582 SatFrm, NoItinerary, "usat", "\t$Rd, $sat_imm, $Rn$sh", []> {
3587 let Inst{27-21} = 0b0110111;
3588 let Inst{5-4} = 0b01;
3589 let Inst{15-12} = Rd;
3590 let Inst{11-7} = sh{4-0};
3591 let Inst{6} = sh{5};
3592 let Inst{20-16} = sat_imm;
3596 def USAT16 : AI<(outs GPRnopc:$Rd),
3597 (ins imm0_15:$sat_imm, GPRnopc:$Rn), SatFrm,
3598 NoItinerary, "usat16", "\t$Rd, $sat_imm, $Rn", []> {
3602 let Inst{27-20} = 0b01101110;
3603 let Inst{11-4} = 0b11110011;
3604 let Inst{15-12} = Rd;
3605 let Inst{19-16} = sat_imm;
3609 def : ARMV6Pat<(int_arm_ssat GPRnopc:$a, imm:$pos),
3610 (SSAT imm:$pos, GPRnopc:$a, 0)>;
3611 def : ARMV6Pat<(int_arm_usat GPRnopc:$a, imm:$pos),
3612 (USAT imm:$pos, GPRnopc:$a, 0)>;
3614 //===----------------------------------------------------------------------===//
3615 // Bitwise Instructions.
3618 defm AND : AsI1_bin_irs<0b0000, "and",
3619 IIC_iBITi, IIC_iBITr, IIC_iBITsr,
3620 BinOpFrag<(and node:$LHS, node:$RHS)>, 1>;
3621 defm ORR : AsI1_bin_irs<0b1100, "orr",
3622 IIC_iBITi, IIC_iBITr, IIC_iBITsr,
3623 BinOpFrag<(or node:$LHS, node:$RHS)>, 1>;
3624 defm EOR : AsI1_bin_irs<0b0001, "eor",
3625 IIC_iBITi, IIC_iBITr, IIC_iBITsr,
3626 BinOpFrag<(xor node:$LHS, node:$RHS)>, 1>;
3627 defm BIC : AsI1_bin_irs<0b1110, "bic",
3628 IIC_iBITi, IIC_iBITr, IIC_iBITsr,
3629 BinOpFrag<(and node:$LHS, (not node:$RHS))>>;
3631 // FIXME: bf_inv_mask_imm should be two operands, the lsb and the msb, just
3632 // like in the actual instruction encoding. The complexity of mapping the mask
3633 // to the lsb/msb pair should be handled by ISel, not encapsulated in the
3634 // instruction description.
3635 def BFC : I<(outs GPR:$Rd), (ins GPR:$src, bf_inv_mask_imm:$imm),
3636 AddrMode1, 4, IndexModeNone, DPFrm, IIC_iUNAsi,
3637 "bfc", "\t$Rd, $imm", "$src = $Rd",
3638 [(set GPR:$Rd, (and GPR:$src, bf_inv_mask_imm:$imm))]>,
3639 Requires<[IsARM, HasV6T2]> {
3642 let Inst{27-21} = 0b0111110;
3643 let Inst{6-0} = 0b0011111;
3644 let Inst{15-12} = Rd;
3645 let Inst{11-7} = imm{4-0}; // lsb
3646 let Inst{20-16} = imm{9-5}; // msb
3649 // A8.6.18 BFI - Bitfield insert (Encoding A1)
3650 def BFI:I<(outs GPRnopc:$Rd), (ins GPRnopc:$src, GPR:$Rn, bf_inv_mask_imm:$imm),
3651 AddrMode1, 4, IndexModeNone, DPFrm, IIC_iUNAsi,
3652 "bfi", "\t$Rd, $Rn, $imm", "$src = $Rd",
3653 [(set GPRnopc:$Rd, (ARMbfi GPRnopc:$src, GPR:$Rn,
3654 bf_inv_mask_imm:$imm))]>,
3655 Requires<[IsARM, HasV6T2]> {
3659 let Inst{27-21} = 0b0111110;
3660 let Inst{6-4} = 0b001; // Rn: Inst{3-0} != 15
3661 let Inst{15-12} = Rd;
3662 let Inst{11-7} = imm{4-0}; // lsb
3663 let Inst{20-16} = imm{9-5}; // width
3667 def MVNr : AsI1<0b1111, (outs GPR:$Rd), (ins GPR:$Rm), DPFrm, IIC_iMVNr,
3668 "mvn", "\t$Rd, $Rm",
3669 [(set GPR:$Rd, (not GPR:$Rm))]>, UnaryDP, Sched<[WriteALU]> {
3673 let Inst{19-16} = 0b0000;
3674 let Inst{11-4} = 0b00000000;
3675 let Inst{15-12} = Rd;
3678 def MVNsi : AsI1<0b1111, (outs GPR:$Rd), (ins so_reg_imm:$shift),
3679 DPSoRegImmFrm, IIC_iMVNsr, "mvn", "\t$Rd, $shift",
3680 [(set GPR:$Rd, (not so_reg_imm:$shift))]>, UnaryDP,
3685 let Inst{19-16} = 0b0000;
3686 let Inst{15-12} = Rd;
3687 let Inst{11-5} = shift{11-5};
3689 let Inst{3-0} = shift{3-0};
3691 def MVNsr : AsI1<0b1111, (outs GPR:$Rd), (ins so_reg_reg:$shift),
3692 DPSoRegRegFrm, IIC_iMVNsr, "mvn", "\t$Rd, $shift",
3693 [(set GPR:$Rd, (not so_reg_reg:$shift))]>, UnaryDP,
3698 let Inst{19-16} = 0b0000;
3699 let Inst{15-12} = Rd;
3700 let Inst{11-8} = shift{11-8};
3702 let Inst{6-5} = shift{6-5};
3704 let Inst{3-0} = shift{3-0};
3706 let isReMaterializable = 1, isAsCheapAsAMove = 1, isMoveImm = 1 in
3707 def MVNi : AsI1<0b1111, (outs GPR:$Rd), (ins so_imm:$imm), DPFrm,
3708 IIC_iMVNi, "mvn", "\t$Rd, $imm",
3709 [(set GPR:$Rd, so_imm_not:$imm)]>,UnaryDP, Sched<[WriteALU]> {
3713 let Inst{19-16} = 0b0000;
3714 let Inst{15-12} = Rd;
3715 let Inst{11-0} = imm;
3718 def : ARMPat<(and GPR:$src, so_imm_not:$imm),
3719 (BICri GPR:$src, so_imm_not:$imm)>;
3721 //===----------------------------------------------------------------------===//
3722 // Multiply Instructions.
3724 class AsMul1I32<bits<7> opcod, dag oops, dag iops, InstrItinClass itin,
3725 string opc, string asm, list<dag> pattern>
3726 : AsMul1I<opcod, oops, iops, itin, opc, asm, pattern> {
3730 let Inst{19-16} = Rd;
3731 let Inst{11-8} = Rm;
3734 class AsMul1I64<bits<7> opcod, dag oops, dag iops, InstrItinClass itin,
3735 string opc, string asm, list<dag> pattern>
3736 : AsMul1I<opcod, oops, iops, itin, opc, asm, pattern> {
3741 let Inst{19-16} = RdHi;
3742 let Inst{15-12} = RdLo;
3743 let Inst{11-8} = Rm;
3746 class AsMla1I64<bits<7> opcod, dag oops, dag iops, InstrItinClass itin,
3747 string opc, string asm, list<dag> pattern>
3748 : AsMul1I<opcod, oops, iops, itin, opc, asm, pattern> {
3753 let Inst{19-16} = RdHi;
3754 let Inst{15-12} = RdLo;
3755 let Inst{11-8} = Rm;
3759 // FIXME: The v5 pseudos are only necessary for the additional Constraint
3760 // property. Remove them when it's possible to add those properties
3761 // on an individual MachineInstr, not just an instruction description.
3762 let isCommutable = 1, TwoOperandAliasConstraint = "$Rn = $Rd" in {
3763 def MUL : AsMul1I32<0b0000000, (outs GPRnopc:$Rd),
3764 (ins GPRnopc:$Rn, GPRnopc:$Rm),
3765 IIC_iMUL32, "mul", "\t$Rd, $Rn, $Rm",
3766 [(set GPRnopc:$Rd, (mul GPRnopc:$Rn, GPRnopc:$Rm))]>,
3767 Requires<[IsARM, HasV6]> {
3768 let Inst{15-12} = 0b0000;
3769 let Unpredictable{15-12} = 0b1111;
3772 let Constraints = "@earlyclobber $Rd" in
3773 def MULv5: ARMPseudoExpand<(outs GPRnopc:$Rd), (ins GPRnopc:$Rn, GPRnopc:$Rm,
3774 pred:$p, cc_out:$s),
3776 [(set GPRnopc:$Rd, (mul GPRnopc:$Rn, GPRnopc:$Rm))],
3777 (MUL GPRnopc:$Rd, GPRnopc:$Rn, GPRnopc:$Rm, pred:$p, cc_out:$s)>,
3778 Requires<[IsARM, NoV6, UseMulOps]>;
3781 def MLA : AsMul1I32<0b0000001, (outs GPRnopc:$Rd),
3782 (ins GPRnopc:$Rn, GPRnopc:$Rm, GPRnopc:$Ra),
3783 IIC_iMAC32, "mla", "\t$Rd, $Rn, $Rm, $Ra",
3784 [(set GPRnopc:$Rd, (add (mul GPRnopc:$Rn, GPRnopc:$Rm), GPRnopc:$Ra))]>,
3785 Requires<[IsARM, HasV6, UseMulOps]> {
3787 let Inst{15-12} = Ra;
3790 let Constraints = "@earlyclobber $Rd" in
3791 def MLAv5: ARMPseudoExpand<(outs GPRnopc:$Rd),
3792 (ins GPRnopc:$Rn, GPRnopc:$Rm, GPRnopc:$Ra,
3793 pred:$p, cc_out:$s), 4, IIC_iMAC32,
3794 [(set GPRnopc:$Rd, (add (mul GPRnopc:$Rn, GPRnopc:$Rm), GPRnopc:$Ra))],
3795 (MLA GPRnopc:$Rd, GPRnopc:$Rn, GPRnopc:$Rm, GPRnopc:$Ra, pred:$p, cc_out:$s)>,
3796 Requires<[IsARM, NoV6]>;
3798 def MLS : AMul1I<0b0000011, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm, GPR:$Ra),
3799 IIC_iMAC32, "mls", "\t$Rd, $Rn, $Rm, $Ra",
3800 [(set GPR:$Rd, (sub GPR:$Ra, (mul GPR:$Rn, GPR:$Rm)))]>,
3801 Requires<[IsARM, HasV6T2, UseMulOps]> {
3806 let Inst{19-16} = Rd;
3807 let Inst{15-12} = Ra;
3808 let Inst{11-8} = Rm;
3812 // Extra precision multiplies with low / high results
3813 let neverHasSideEffects = 1 in {
3814 let isCommutable = 1 in {
3815 def SMULL : AsMul1I64<0b0000110, (outs GPR:$RdLo, GPR:$RdHi),
3816 (ins GPR:$Rn, GPR:$Rm), IIC_iMUL64,
3817 "smull", "\t$RdLo, $RdHi, $Rn, $Rm", []>,
3818 Requires<[IsARM, HasV6]>;
3820 def UMULL : AsMul1I64<0b0000100, (outs GPR:$RdLo, GPR:$RdHi),
3821 (ins GPR:$Rn, GPR:$Rm), IIC_iMUL64,
3822 "umull", "\t$RdLo, $RdHi, $Rn, $Rm", []>,
3823 Requires<[IsARM, HasV6]>;
3825 let Constraints = "@earlyclobber $RdLo,@earlyclobber $RdHi" in {
3826 def SMULLv5 : ARMPseudoExpand<(outs GPR:$RdLo, GPR:$RdHi),
3827 (ins GPR:$Rn, GPR:$Rm, pred:$p, cc_out:$s),
3829 (SMULL GPR:$RdLo, GPR:$RdHi, GPR:$Rn, GPR:$Rm, pred:$p, cc_out:$s)>,
3830 Requires<[IsARM, NoV6]>;
3832 def UMULLv5 : ARMPseudoExpand<(outs GPR:$RdLo, GPR:$RdHi),
3833 (ins GPR:$Rn, GPR:$Rm, pred:$p, cc_out:$s),
3835 (UMULL GPR:$RdLo, GPR:$RdHi, GPR:$Rn, GPR:$Rm, pred:$p, cc_out:$s)>,
3836 Requires<[IsARM, NoV6]>;
3840 // Multiply + accumulate
3841 def SMLAL : AsMla1I64<0b0000111, (outs GPR:$RdLo, GPR:$RdHi),
3842 (ins GPR:$Rn, GPR:$Rm, GPR:$RLo, GPR:$RHi), IIC_iMAC64,
3843 "smlal", "\t$RdLo, $RdHi, $Rn, $Rm", []>,
3844 RegConstraint<"$RLo = $RdLo, $RHi = $RdHi">, Requires<[IsARM, HasV6]>;
3845 def UMLAL : AsMla1I64<0b0000101, (outs GPR:$RdLo, GPR:$RdHi),
3846 (ins GPR:$Rn, GPR:$Rm, GPR:$RLo, GPR:$RHi), IIC_iMAC64,
3847 "umlal", "\t$RdLo, $RdHi, $Rn, $Rm", []>,
3848 RegConstraint<"$RLo = $RdLo, $RHi = $RdHi">, Requires<[IsARM, HasV6]>;
3850 def UMAAL : AMul1I <0b0000010, (outs GPR:$RdLo, GPR:$RdHi),
3851 (ins GPR:$Rn, GPR:$Rm), IIC_iMAC64,
3852 "umaal", "\t$RdLo, $RdHi, $Rn, $Rm", []>,
3853 Requires<[IsARM, HasV6]> {
3858 let Inst{19-16} = RdHi;
3859 let Inst{15-12} = RdLo;
3860 let Inst{11-8} = Rm;
3865 "@earlyclobber $RdLo,@earlyclobber $RdHi,$RLo = $RdLo,$RHi = $RdHi" in {
3866 def SMLALv5 : ARMPseudoExpand<(outs GPR:$RdLo, GPR:$RdHi),
3867 (ins GPR:$Rn, GPR:$Rm, GPR:$RLo, GPR:$RHi, pred:$p, cc_out:$s),
3869 (SMLAL GPR:$RdLo, GPR:$RdHi, GPR:$Rn, GPR:$Rm, GPR:$RLo, GPR:$RHi,
3870 pred:$p, cc_out:$s)>,
3871 Requires<[IsARM, NoV6]>;
3872 def UMLALv5 : ARMPseudoExpand<(outs GPR:$RdLo, GPR:$RdHi),
3873 (ins GPR:$Rn, GPR:$Rm, GPR:$RLo, GPR:$RHi, pred:$p, cc_out:$s),
3875 (UMLAL GPR:$RdLo, GPR:$RdHi, GPR:$Rn, GPR:$Rm, GPR:$RLo, GPR:$RHi,
3876 pred:$p, cc_out:$s)>,
3877 Requires<[IsARM, NoV6]>;
3880 } // neverHasSideEffects
3882 // Most significant word multiply
3883 def SMMUL : AMul2I <0b0111010, 0b0001, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm),
3884 IIC_iMUL32, "smmul", "\t$Rd, $Rn, $Rm",
3885 [(set GPR:$Rd, (mulhs GPR:$Rn, GPR:$Rm))]>,
3886 Requires<[IsARM, HasV6]> {
3887 let Inst{15-12} = 0b1111;
3890 def SMMULR : AMul2I <0b0111010, 0b0011, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm),
3891 IIC_iMUL32, "smmulr", "\t$Rd, $Rn, $Rm", []>,
3892 Requires<[IsARM, HasV6]> {
3893 let Inst{15-12} = 0b1111;
3896 def SMMLA : AMul2Ia <0b0111010, 0b0001, (outs GPR:$Rd),
3897 (ins GPR:$Rn, GPR:$Rm, GPR:$Ra),
3898 IIC_iMAC32, "smmla", "\t$Rd, $Rn, $Rm, $Ra",
3899 [(set GPR:$Rd, (add (mulhs GPR:$Rn, GPR:$Rm), GPR:$Ra))]>,
3900 Requires<[IsARM, HasV6, UseMulOps]>;
3902 def SMMLAR : AMul2Ia <0b0111010, 0b0011, (outs GPR:$Rd),
3903 (ins GPR:$Rn, GPR:$Rm, GPR:$Ra),
3904 IIC_iMAC32, "smmlar", "\t$Rd, $Rn, $Rm, $Ra", []>,
3905 Requires<[IsARM, HasV6]>;
3907 def SMMLS : AMul2Ia <0b0111010, 0b1101, (outs GPR:$Rd),
3908 (ins GPR:$Rn, GPR:$Rm, GPR:$Ra),
3909 IIC_iMAC32, "smmls", "\t$Rd, $Rn, $Rm, $Ra", []>,
3910 Requires<[IsARM, HasV6, UseMulOps]>;
3912 def SMMLSR : AMul2Ia <0b0111010, 0b1111, (outs GPR:$Rd),
3913 (ins GPR:$Rn, GPR:$Rm, GPR:$Ra),
3914 IIC_iMAC32, "smmlsr", "\t$Rd, $Rn, $Rm, $Ra", []>,
3915 Requires<[IsARM, HasV6]>;
3917 multiclass AI_smul<string opc, PatFrag opnode> {
3918 def BB : AMulxyI<0b0001011, 0b00, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm),
3919 IIC_iMUL16, !strconcat(opc, "bb"), "\t$Rd, $Rn, $Rm",
3920 [(set GPR:$Rd, (opnode (sext_inreg GPR:$Rn, i16),
3921 (sext_inreg GPR:$Rm, i16)))]>,
3922 Requires<[IsARM, HasV5TE]>;
3924 def BT : AMulxyI<0b0001011, 0b10, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm),
3925 IIC_iMUL16, !strconcat(opc, "bt"), "\t$Rd, $Rn, $Rm",
3926 [(set GPR:$Rd, (opnode (sext_inreg GPR:$Rn, i16),
3927 (sra GPR:$Rm, (i32 16))))]>,
3928 Requires<[IsARM, HasV5TE]>;
3930 def TB : AMulxyI<0b0001011, 0b01, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm),
3931 IIC_iMUL16, !strconcat(opc, "tb"), "\t$Rd, $Rn, $Rm",
3932 [(set GPR:$Rd, (opnode (sra GPR:$Rn, (i32 16)),
3933 (sext_inreg GPR:$Rm, i16)))]>,
3934 Requires<[IsARM, HasV5TE]>;
3936 def TT : AMulxyI<0b0001011, 0b11, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm),
3937 IIC_iMUL16, !strconcat(opc, "tt"), "\t$Rd, $Rn, $Rm",
3938 [(set GPR:$Rd, (opnode (sra GPR:$Rn, (i32 16)),
3939 (sra GPR:$Rm, (i32 16))))]>,
3940 Requires<[IsARM, HasV5TE]>;
3942 def WB : AMulxyI<0b0001001, 0b01, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm),
3943 IIC_iMUL16, !strconcat(opc, "wb"), "\t$Rd, $Rn, $Rm",
3944 [(set GPR:$Rd, (sra (opnode GPR:$Rn,
3945 (sext_inreg GPR:$Rm, i16)), (i32 16)))]>,
3946 Requires<[IsARM, HasV5TE]>;
3948 def WT : AMulxyI<0b0001001, 0b11, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm),
3949 IIC_iMUL16, !strconcat(opc, "wt"), "\t$Rd, $Rn, $Rm",
3950 [(set GPR:$Rd, (sra (opnode GPR:$Rn,
3951 (sra GPR:$Rm, (i32 16))), (i32 16)))]>,
3952 Requires<[IsARM, HasV5TE]>;
3956 multiclass AI_smla<string opc, PatFrag opnode> {
3957 let DecoderMethod = "DecodeSMLAInstruction" in {
3958 def BB : AMulxyIa<0b0001000, 0b00, (outs GPRnopc:$Rd),
3959 (ins GPRnopc:$Rn, GPRnopc:$Rm, GPR:$Ra),
3960 IIC_iMAC16, !strconcat(opc, "bb"), "\t$Rd, $Rn, $Rm, $Ra",
3961 [(set GPRnopc:$Rd, (add GPR:$Ra,
3962 (opnode (sext_inreg GPRnopc:$Rn, i16),
3963 (sext_inreg GPRnopc:$Rm, i16))))]>,
3964 Requires<[IsARM, HasV5TE, UseMulOps]>;
3966 def BT : AMulxyIa<0b0001000, 0b10, (outs GPRnopc:$Rd),
3967 (ins GPRnopc:$Rn, GPRnopc:$Rm, GPR:$Ra),
3968 IIC_iMAC16, !strconcat(opc, "bt"), "\t$Rd, $Rn, $Rm, $Ra",
3970 (add GPR:$Ra, (opnode (sext_inreg GPRnopc:$Rn, i16),
3971 (sra GPRnopc:$Rm, (i32 16)))))]>,
3972 Requires<[IsARM, HasV5TE, UseMulOps]>;
3974 def TB : AMulxyIa<0b0001000, 0b01, (outs GPRnopc:$Rd),
3975 (ins GPRnopc:$Rn, GPRnopc:$Rm, GPR:$Ra),
3976 IIC_iMAC16, !strconcat(opc, "tb"), "\t$Rd, $Rn, $Rm, $Ra",
3978 (add GPR:$Ra, (opnode (sra GPRnopc:$Rn, (i32 16)),
3979 (sext_inreg GPRnopc:$Rm, i16))))]>,
3980 Requires<[IsARM, HasV5TE, UseMulOps]>;
3982 def TT : AMulxyIa<0b0001000, 0b11, (outs GPRnopc:$Rd),
3983 (ins GPRnopc:$Rn, GPRnopc:$Rm, GPR:$Ra),
3984 IIC_iMAC16, !strconcat(opc, "tt"), "\t$Rd, $Rn, $Rm, $Ra",
3986 (add GPR:$Ra, (opnode (sra GPRnopc:$Rn, (i32 16)),
3987 (sra GPRnopc:$Rm, (i32 16)))))]>,
3988 Requires<[IsARM, HasV5TE, UseMulOps]>;
3990 def WB : AMulxyIa<0b0001001, 0b00, (outs GPRnopc:$Rd),
3991 (ins GPRnopc:$Rn, GPRnopc:$Rm, GPR:$Ra),
3992 IIC_iMAC16, !strconcat(opc, "wb"), "\t$Rd, $Rn, $Rm, $Ra",
3994 (add GPR:$Ra, (sra (opnode GPRnopc:$Rn,
3995 (sext_inreg GPRnopc:$Rm, i16)), (i32 16))))]>,
3996 Requires<[IsARM, HasV5TE, UseMulOps]>;
3998 def WT : AMulxyIa<0b0001001, 0b10, (outs GPRnopc:$Rd),
3999 (ins GPRnopc:$Rn, GPRnopc:$Rm, GPR:$Ra),
4000 IIC_iMAC16, !strconcat(opc, "wt"), "\t$Rd, $Rn, $Rm, $Ra",
4002 (add GPR:$Ra, (sra (opnode GPRnopc:$Rn,
4003 (sra GPRnopc:$Rm, (i32 16))), (i32 16))))]>,
4004 Requires<[IsARM, HasV5TE, UseMulOps]>;
4008 defm SMUL : AI_smul<"smul", BinOpFrag<(mul node:$LHS, node:$RHS)>>;
4009 defm SMLA : AI_smla<"smla", BinOpFrag<(mul node:$LHS, node:$RHS)>>;
4011 // Halfword multiply accumulate long: SMLAL<x><y>.
4012 def SMLALBB : AMulxyI64<0b0001010, 0b00, (outs GPRnopc:$RdLo, GPRnopc:$RdHi),
4013 (ins GPRnopc:$Rn, GPRnopc:$Rm),
4014 IIC_iMAC64, "smlalbb", "\t$RdLo, $RdHi, $Rn, $Rm", []>,
4015 Requires<[IsARM, HasV5TE]>;
4017 def SMLALBT : AMulxyI64<0b0001010, 0b10, (outs GPRnopc:$RdLo, GPRnopc:$RdHi),
4018 (ins GPRnopc:$Rn, GPRnopc:$Rm),
4019 IIC_iMAC64, "smlalbt", "\t$RdLo, $RdHi, $Rn, $Rm", []>,
4020 Requires<[IsARM, HasV5TE]>;
4022 def SMLALTB : AMulxyI64<0b0001010, 0b01, (outs GPRnopc:$RdLo, GPRnopc:$RdHi),
4023 (ins GPRnopc:$Rn, GPRnopc:$Rm),
4024 IIC_iMAC64, "smlaltb", "\t$RdLo, $RdHi, $Rn, $Rm", []>,
4025 Requires<[IsARM, HasV5TE]>;
4027 def SMLALTT : AMulxyI64<0b0001010, 0b11, (outs GPRnopc:$RdLo, GPRnopc:$RdHi),
4028 (ins GPRnopc:$Rn, GPRnopc:$Rm),
4029 IIC_iMAC64, "smlaltt", "\t$RdLo, $RdHi, $Rn, $Rm", []>,
4030 Requires<[IsARM, HasV5TE]>;
4032 // Helper class for AI_smld.
4033 class AMulDualIbase<bit long, bit sub, bit swap, dag oops, dag iops,
4034 InstrItinClass itin, string opc, string asm>
4035 : AI<oops, iops, MulFrm, itin, opc, asm, []>, Requires<[IsARM, HasV6]> {
4038 let Inst{27-23} = 0b01110;
4039 let Inst{22} = long;
4040 let Inst{21-20} = 0b00;
4041 let Inst{11-8} = Rm;
4048 class AMulDualI<bit long, bit sub, bit swap, dag oops, dag iops,
4049 InstrItinClass itin, string opc, string asm>
4050 : AMulDualIbase<long, sub, swap, oops, iops, itin, opc, asm> {
4052 let Inst{15-12} = 0b1111;
4053 let Inst{19-16} = Rd;
4055 class AMulDualIa<bit long, bit sub, bit swap, dag oops, dag iops,
4056 InstrItinClass itin, string opc, string asm>
4057 : AMulDualIbase<long, sub, swap, oops, iops, itin, opc, asm> {
4060 let Inst{19-16} = Rd;
4061 let Inst{15-12} = Ra;
4063 class AMulDualI64<bit long, bit sub, bit swap, dag oops, dag iops,
4064 InstrItinClass itin, string opc, string asm>
4065 : AMulDualIbase<long, sub, swap, oops, iops, itin, opc, asm> {
4068 let Inst{19-16} = RdHi;
4069 let Inst{15-12} = RdLo;
4072 multiclass AI_smld<bit sub, string opc> {
4074 def D : AMulDualIa<0, sub, 0, (outs GPRnopc:$Rd),
4075 (ins GPRnopc:$Rn, GPRnopc:$Rm, GPR:$Ra),
4076 NoItinerary, !strconcat(opc, "d"), "\t$Rd, $Rn, $Rm, $Ra">;
4078 def DX: AMulDualIa<0, sub, 1, (outs GPRnopc:$Rd),
4079 (ins GPRnopc:$Rn, GPRnopc:$Rm, GPR:$Ra),
4080 NoItinerary, !strconcat(opc, "dx"), "\t$Rd, $Rn, $Rm, $Ra">;
4082 def LD: AMulDualI64<1, sub, 0, (outs GPRnopc:$RdLo, GPRnopc:$RdHi),
4083 (ins GPRnopc:$Rn, GPRnopc:$Rm), NoItinerary,
4084 !strconcat(opc, "ld"), "\t$RdLo, $RdHi, $Rn, $Rm">;
4086 def LDX : AMulDualI64<1, sub, 1, (outs GPRnopc:$RdLo, GPRnopc:$RdHi),
4087 (ins GPRnopc:$Rn, GPRnopc:$Rm), NoItinerary,
4088 !strconcat(opc, "ldx"),"\t$RdLo, $RdHi, $Rn, $Rm">;
4092 defm SMLA : AI_smld<0, "smla">;
4093 defm SMLS : AI_smld<1, "smls">;
4095 multiclass AI_sdml<bit sub, string opc> {
4097 def D:AMulDualI<0, sub, 0, (outs GPRnopc:$Rd), (ins GPRnopc:$Rn, GPRnopc:$Rm),
4098 NoItinerary, !strconcat(opc, "d"), "\t$Rd, $Rn, $Rm">;
4099 def DX:AMulDualI<0, sub, 1, (outs GPRnopc:$Rd),(ins GPRnopc:$Rn, GPRnopc:$Rm),
4100 NoItinerary, !strconcat(opc, "dx"), "\t$Rd, $Rn, $Rm">;
4103 defm SMUA : AI_sdml<0, "smua">;
4104 defm SMUS : AI_sdml<1, "smus">;
4106 //===----------------------------------------------------------------------===//
4107 // Division Instructions (ARMv7-A with virtualization extension)
4109 def SDIV : ADivA1I<0b001, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm), IIC_iDIV,
4110 "sdiv", "\t$Rd, $Rn, $Rm",
4111 [(set GPR:$Rd, (sdiv GPR:$Rn, GPR:$Rm))]>,
4112 Requires<[IsARM, HasDivideInARM]>;
4114 def UDIV : ADivA1I<0b011, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm), IIC_iDIV,
4115 "udiv", "\t$Rd, $Rn, $Rm",
4116 [(set GPR:$Rd, (udiv GPR:$Rn, GPR:$Rm))]>,
4117 Requires<[IsARM, HasDivideInARM]>;
4119 //===----------------------------------------------------------------------===//
4120 // Misc. Arithmetic Instructions.
4123 def CLZ : AMiscA1I<0b00010110, 0b0001, (outs GPR:$Rd), (ins GPR:$Rm),
4124 IIC_iUNAr, "clz", "\t$Rd, $Rm",
4125 [(set GPR:$Rd, (ctlz GPR:$Rm))]>, Requires<[IsARM, HasV5T]>,
4128 def RBIT : AMiscA1I<0b01101111, 0b0011, (outs GPR:$Rd), (ins GPR:$Rm),
4129 IIC_iUNAr, "rbit", "\t$Rd, $Rm",
4130 [(set GPR:$Rd, (ARMrbit GPR:$Rm))]>,
4131 Requires<[IsARM, HasV6T2]>,
4134 def REV : AMiscA1I<0b01101011, 0b0011, (outs GPR:$Rd), (ins GPR:$Rm),
4135 IIC_iUNAr, "rev", "\t$Rd, $Rm",
4136 [(set GPR:$Rd, (bswap GPR:$Rm))]>, Requires<[IsARM, HasV6]>,
4139 let AddedComplexity = 5 in
4140 def REV16 : AMiscA1I<0b01101011, 0b1011, (outs GPR:$Rd), (ins GPR:$Rm),
4141 IIC_iUNAr, "rev16", "\t$Rd, $Rm",
4142 [(set GPR:$Rd, (rotr (bswap GPR:$Rm), (i32 16)))]>,
4143 Requires<[IsARM, HasV6]>,
4146 def : ARMV6Pat<(srl (bswap (extloadi16 addrmode3:$addr)), (i32 16)),
4147 (REV16 (LDRH addrmode3:$addr))>;
4148 def : ARMV6Pat<(truncstorei16 (srl (bswap GPR:$Rn), (i32 16)), addrmode3:$addr),
4149 (STRH (REV16 GPR:$Rn), addrmode3:$addr)>;
4151 let AddedComplexity = 5 in
4152 def REVSH : AMiscA1I<0b01101111, 0b1011, (outs GPR:$Rd), (ins GPR:$Rm),
4153 IIC_iUNAr, "revsh", "\t$Rd, $Rm",
4154 [(set GPR:$Rd, (sra (bswap GPR:$Rm), (i32 16)))]>,
4155 Requires<[IsARM, HasV6]>,
4158 def : ARMV6Pat<(or (sra (shl GPR:$Rm, (i32 24)), (i32 16)),
4159 (and (srl GPR:$Rm, (i32 8)), 0xFF)),
4162 def PKHBT : APKHI<0b01101000, 0, (outs GPRnopc:$Rd),
4163 (ins GPRnopc:$Rn, GPRnopc:$Rm, pkh_lsl_amt:$sh),
4164 IIC_iALUsi, "pkhbt", "\t$Rd, $Rn, $Rm$sh",
4165 [(set GPRnopc:$Rd, (or (and GPRnopc:$Rn, 0xFFFF),
4166 (and (shl GPRnopc:$Rm, pkh_lsl_amt:$sh),
4168 Requires<[IsARM, HasV6]>,
4169 Sched<[WriteALUsi, ReadALU]>;
4171 // Alternate cases for PKHBT where identities eliminate some nodes.
4172 def : ARMV6Pat<(or (and GPRnopc:$Rn, 0xFFFF), (and GPRnopc:$Rm, 0xFFFF0000)),
4173 (PKHBT GPRnopc:$Rn, GPRnopc:$Rm, 0)>;
4174 def : ARMV6Pat<(or (and GPRnopc:$Rn, 0xFFFF), (shl GPRnopc:$Rm, imm16_31:$sh)),
4175 (PKHBT GPRnopc:$Rn, GPRnopc:$Rm, imm16_31:$sh)>;
4177 // Note: Shifts of 1-15 bits will be transformed to srl instead of sra and
4178 // will match the pattern below.
4179 def PKHTB : APKHI<0b01101000, 1, (outs GPRnopc:$Rd),
4180 (ins GPRnopc:$Rn, GPRnopc:$Rm, pkh_asr_amt:$sh),
4181 IIC_iBITsi, "pkhtb", "\t$Rd, $Rn, $Rm$sh",
4182 [(set GPRnopc:$Rd, (or (and GPRnopc:$Rn, 0xFFFF0000),
4183 (and (sra GPRnopc:$Rm, pkh_asr_amt:$sh),
4185 Requires<[IsARM, HasV6]>,
4186 Sched<[WriteALUsi, ReadALU]>;
4188 // Alternate cases for PKHTB where identities eliminate some nodes. Note that
4189 // a shift amount of 0 is *not legal* here, it is PKHBT instead.
4190 // We also can not replace a srl (17..31) by an arithmetic shift we would use in
4191 // pkhtb src1, src2, asr (17..31).
4192 def : ARMV6Pat<(or (and GPRnopc:$src1, 0xFFFF0000),
4193 (srl GPRnopc:$src2, imm16:$sh)),
4194 (PKHTB GPRnopc:$src1, GPRnopc:$src2, imm16:$sh)>;
4195 def : ARMV6Pat<(or (and GPRnopc:$src1, 0xFFFF0000),
4196 (sra GPRnopc:$src2, imm16_31:$sh)),
4197 (PKHTB GPRnopc:$src1, GPRnopc:$src2, imm16_31:$sh)>;
4198 def : ARMV6Pat<(or (and GPRnopc:$src1, 0xFFFF0000),
4199 (and (srl GPRnopc:$src2, imm1_15:$sh), 0xFFFF)),
4200 (PKHTB GPRnopc:$src1, GPRnopc:$src2, imm1_15:$sh)>;
4202 //===----------------------------------------------------------------------===//
4206 // + CRC32{B,H,W} 0x04C11DB7
4207 // + CRC32C{B,H,W} 0x1EDC6F41
4210 class AI_crc32<bit C, bits<2> sz, string suffix, SDPatternOperator builtin>
4211 : AInoP<(outs GPRnopc:$Rd), (ins GPRnopc:$Rn, GPRnopc:$Rm), MiscFrm, NoItinerary,
4212 !strconcat("crc32", suffix), "\t$Rd, $Rn, $Rm",
4213 [(set GPRnopc:$Rd, (builtin GPRnopc:$Rn, GPRnopc:$Rm))]>,
4214 Requires<[IsARM, HasV8, HasCRC]> {
4219 let Inst{31-28} = 0b1110;
4220 let Inst{27-23} = 0b00010;
4221 let Inst{22-21} = sz;
4223 let Inst{19-16} = Rn;
4224 let Inst{15-12} = Rd;
4225 let Inst{11-10} = 0b00;
4228 let Inst{7-4} = 0b0100;
4231 let Unpredictable{11-8} = 0b1101;
4234 def CRC32B : AI_crc32<0, 0b00, "b", int_arm_crc32b>;
4235 def CRC32CB : AI_crc32<1, 0b00, "cb", int_arm_crc32cb>;
4236 def CRC32H : AI_crc32<0, 0b01, "h", int_arm_crc32h>;
4237 def CRC32CH : AI_crc32<1, 0b01, "ch", int_arm_crc32ch>;
4238 def CRC32W : AI_crc32<0, 0b10, "w", int_arm_crc32w>;
4239 def CRC32CW : AI_crc32<1, 0b10, "cw", int_arm_crc32cw>;
4241 //===----------------------------------------------------------------------===//
4242 // Comparison Instructions...
4245 defm CMP : AI1_cmp_irs<0b1010, "cmp",
4246 IIC_iCMPi, IIC_iCMPr, IIC_iCMPsr,
4247 BinOpFrag<(ARMcmp node:$LHS, node:$RHS)>>;
4249 // ARMcmpZ can re-use the above instruction definitions.
4250 def : ARMPat<(ARMcmpZ GPR:$src, so_imm:$imm),
4251 (CMPri GPR:$src, so_imm:$imm)>;
4252 def : ARMPat<(ARMcmpZ GPR:$src, GPR:$rhs),
4253 (CMPrr GPR:$src, GPR:$rhs)>;
4254 def : ARMPat<(ARMcmpZ GPR:$src, so_reg_imm:$rhs),
4255 (CMPrsi GPR:$src, so_reg_imm:$rhs)>;
4256 def : ARMPat<(ARMcmpZ GPR:$src, so_reg_reg:$rhs),
4257 (CMPrsr GPR:$src, so_reg_reg:$rhs)>;
4259 // CMN register-integer
4260 let isCompare = 1, Defs = [CPSR] in {
4261 def CMNri : AI1<0b1011, (outs), (ins GPR:$Rn, so_imm:$imm), DPFrm, IIC_iCMPi,
4262 "cmn", "\t$Rn, $imm",
4263 [(ARMcmn GPR:$Rn, so_imm:$imm)]>,
4264 Sched<[WriteCMP, ReadALU]> {
4269 let Inst{19-16} = Rn;
4270 let Inst{15-12} = 0b0000;
4271 let Inst{11-0} = imm;
4273 let Unpredictable{15-12} = 0b1111;
4276 // CMN register-register/shift
4277 def CMNzrr : AI1<0b1011, (outs), (ins GPR:$Rn, GPR:$Rm), DPFrm, IIC_iCMPr,
4278 "cmn", "\t$Rn, $Rm",
4279 [(BinOpFrag<(ARMcmpZ node:$LHS,(ineg node:$RHS))>
4280 GPR:$Rn, GPR:$Rm)]>, Sched<[WriteCMP, ReadALU, ReadALU]> {
4283 let isCommutable = 1;
4286 let Inst{19-16} = Rn;
4287 let Inst{15-12} = 0b0000;
4288 let Inst{11-4} = 0b00000000;
4291 let Unpredictable{15-12} = 0b1111;
4294 def CMNzrsi : AI1<0b1011, (outs),
4295 (ins GPR:$Rn, so_reg_imm:$shift), DPSoRegImmFrm, IIC_iCMPsr,
4296 "cmn", "\t$Rn, $shift",
4297 [(BinOpFrag<(ARMcmpZ node:$LHS,(ineg node:$RHS))>
4298 GPR:$Rn, so_reg_imm:$shift)]>,
4299 Sched<[WriteCMPsi, ReadALU]> {
4304 let Inst{19-16} = Rn;
4305 let Inst{15-12} = 0b0000;
4306 let Inst{11-5} = shift{11-5};
4308 let Inst{3-0} = shift{3-0};
4310 let Unpredictable{15-12} = 0b1111;
4313 def CMNzrsr : AI1<0b1011, (outs),
4314 (ins GPRnopc:$Rn, so_reg_reg:$shift), DPSoRegRegFrm, IIC_iCMPsr,
4315 "cmn", "\t$Rn, $shift",
4316 [(BinOpFrag<(ARMcmpZ node:$LHS,(ineg node:$RHS))>
4317 GPRnopc:$Rn, so_reg_reg:$shift)]>,
4318 Sched<[WriteCMPsr, ReadALU]> {
4323 let Inst{19-16} = Rn;
4324 let Inst{15-12} = 0b0000;
4325 let Inst{11-8} = shift{11-8};
4327 let Inst{6-5} = shift{6-5};
4329 let Inst{3-0} = shift{3-0};
4331 let Unpredictable{15-12} = 0b1111;
4336 def : ARMPat<(ARMcmp GPR:$src, so_imm_neg:$imm),
4337 (CMNri GPR:$src, so_imm_neg:$imm)>;
4339 def : ARMPat<(ARMcmpZ GPR:$src, so_imm_neg:$imm),
4340 (CMNri GPR:$src, so_imm_neg:$imm)>;
4342 // Note that TST/TEQ don't set all the same flags that CMP does!
4343 defm TST : AI1_cmp_irs<0b1000, "tst",
4344 IIC_iTSTi, IIC_iTSTr, IIC_iTSTsr,
4345 BinOpFrag<(ARMcmpZ (and_su node:$LHS, node:$RHS), 0)>, 1>;
4346 defm TEQ : AI1_cmp_irs<0b1001, "teq",
4347 IIC_iTSTi, IIC_iTSTr, IIC_iTSTsr,
4348 BinOpFrag<(ARMcmpZ (xor_su node:$LHS, node:$RHS), 0)>, 1>;
4350 // Pseudo i64 compares for some floating point compares.
4351 let usesCustomInserter = 1, isBranch = 1, isTerminator = 1,
4353 def BCCi64 : PseudoInst<(outs),
4354 (ins i32imm:$cc, GPR:$lhs1, GPR:$lhs2, GPR:$rhs1, GPR:$rhs2, brtarget:$dst),
4356 [(ARMBcci64 imm:$cc, GPR:$lhs1, GPR:$lhs2, GPR:$rhs1, GPR:$rhs2, bb:$dst)]>,
4359 def BCCZi64 : PseudoInst<(outs),
4360 (ins i32imm:$cc, GPR:$lhs1, GPR:$lhs2, brtarget:$dst), IIC_Br,
4361 [(ARMBcci64 imm:$cc, GPR:$lhs1, GPR:$lhs2, 0, 0, bb:$dst)]>,
4363 } // usesCustomInserter
4366 // Conditional moves
4367 let neverHasSideEffects = 1 in {
4369 let isCommutable = 1, isSelect = 1 in
4370 def MOVCCr : ARMPseudoInst<(outs GPR:$Rd),
4371 (ins GPR:$false, GPR:$Rm, cmovpred:$p),
4373 [(set GPR:$Rd, (ARMcmov GPR:$false, GPR:$Rm,
4375 RegConstraint<"$false = $Rd">, Sched<[WriteALU]>;
4377 def MOVCCsi : ARMPseudoInst<(outs GPR:$Rd),
4378 (ins GPR:$false, so_reg_imm:$shift, cmovpred:$p),
4381 (ARMcmov GPR:$false, so_reg_imm:$shift,
4383 RegConstraint<"$false = $Rd">, Sched<[WriteALU]>;
4384 def MOVCCsr : ARMPseudoInst<(outs GPR:$Rd),
4385 (ins GPR:$false, so_reg_reg:$shift, cmovpred:$p),
4387 [(set GPR:$Rd, (ARMcmov GPR:$false, so_reg_reg:$shift,
4389 RegConstraint<"$false = $Rd">, Sched<[WriteALU]>;
4392 let isMoveImm = 1 in
4394 : ARMPseudoInst<(outs GPR:$Rd),
4395 (ins GPR:$false, imm0_65535_expr:$imm, cmovpred:$p),
4397 [(set GPR:$Rd, (ARMcmov GPR:$false, imm0_65535:$imm,
4399 RegConstraint<"$false = $Rd">, Requires<[IsARM, HasV6T2]>,
4402 let isMoveImm = 1 in
4403 def MOVCCi : ARMPseudoInst<(outs GPR:$Rd),
4404 (ins GPR:$false, so_imm:$imm, cmovpred:$p),
4406 [(set GPR:$Rd, (ARMcmov GPR:$false, so_imm:$imm,
4408 RegConstraint<"$false = $Rd">, Sched<[WriteALU]>;
4410 // Two instruction predicate mov immediate.
4411 let isMoveImm = 1 in
4413 : ARMPseudoInst<(outs GPR:$Rd),
4414 (ins GPR:$false, i32imm:$src, cmovpred:$p),
4416 [(set GPR:$Rd, (ARMcmov GPR:$false, imm:$src,
4418 RegConstraint<"$false = $Rd">, Requires<[IsARM, HasV6T2]>;
4420 let isMoveImm = 1 in
4421 def MVNCCi : ARMPseudoInst<(outs GPR:$Rd),
4422 (ins GPR:$false, so_imm:$imm, cmovpred:$p),
4424 [(set GPR:$Rd, (ARMcmov GPR:$false, so_imm_not:$imm,
4426 RegConstraint<"$false = $Rd">, Sched<[WriteALU]>;
4428 } // neverHasSideEffects
4431 //===----------------------------------------------------------------------===//
4432 // Atomic operations intrinsics
4435 def MemBarrierOptOperand : AsmOperandClass {
4436 let Name = "MemBarrierOpt";
4437 let ParserMethod = "parseMemBarrierOptOperand";
4439 def memb_opt : Operand<i32> {
4440 let PrintMethod = "printMemBOption";
4441 let ParserMatchClass = MemBarrierOptOperand;
4442 let DecoderMethod = "DecodeMemBarrierOption";
4445 def InstSyncBarrierOptOperand : AsmOperandClass {
4446 let Name = "InstSyncBarrierOpt";
4447 let ParserMethod = "parseInstSyncBarrierOptOperand";
4449 def instsyncb_opt : Operand<i32> {
4450 let PrintMethod = "printInstSyncBOption";
4451 let ParserMatchClass = InstSyncBarrierOptOperand;
4452 let DecoderMethod = "DecodeInstSyncBarrierOption";
4455 // Memory barriers protect the atomic sequences
4456 let hasSideEffects = 1 in {
4457 def DMB : AInoP<(outs), (ins memb_opt:$opt), MiscFrm, NoItinerary,
4458 "dmb", "\t$opt", [(int_arm_dmb (i32 imm0_15:$opt))]>,
4459 Requires<[IsARM, HasDB]> {
4461 let Inst{31-4} = 0xf57ff05;
4462 let Inst{3-0} = opt;
4465 def DSB : AInoP<(outs), (ins memb_opt:$opt), MiscFrm, NoItinerary,
4466 "dsb", "\t$opt", [(int_arm_dsb (i32 imm0_15:$opt))]>,
4467 Requires<[IsARM, HasDB]> {
4469 let Inst{31-4} = 0xf57ff04;
4470 let Inst{3-0} = opt;
4473 // ISB has only full system option
4474 def ISB : AInoP<(outs), (ins instsyncb_opt:$opt), MiscFrm, NoItinerary,
4475 "isb", "\t$opt", [(int_arm_isb (i32 imm0_15:$opt))]>,
4476 Requires<[IsARM, HasDB]> {
4478 let Inst{31-4} = 0xf57ff06;
4479 let Inst{3-0} = opt;
4483 let usesCustomInserter = 1, Defs = [CPSR] in {
4485 // Pseudo instruction that combines movs + predicated rsbmi
4486 // to implement integer ABS
4487 def ABS : ARMPseudoInst<(outs GPR:$dst), (ins GPR:$src), 8, NoItinerary, []>;
4490 let usesCustomInserter = 1 in {
4491 def COPY_STRUCT_BYVAL_I32 : PseudoInst<
4492 (outs), (ins GPR:$dst, GPR:$src, i32imm:$size, i32imm:$alignment),
4494 [(ARMcopystructbyval GPR:$dst, GPR:$src, imm:$size, imm:$alignment)]>;
4497 def ldrex_1 : PatFrag<(ops node:$ptr), (int_arm_ldrex node:$ptr), [{
4498 return cast<MemIntrinsicSDNode>(N)->getMemoryVT() == MVT::i8;
4501 def ldrex_2 : PatFrag<(ops node:$ptr), (int_arm_ldrex node:$ptr), [{
4502 return cast<MemIntrinsicSDNode>(N)->getMemoryVT() == MVT::i16;
4505 def ldrex_4 : PatFrag<(ops node:$ptr), (int_arm_ldrex node:$ptr), [{
4506 return cast<MemIntrinsicSDNode>(N)->getMemoryVT() == MVT::i32;
4509 def strex_1 : PatFrag<(ops node:$val, node:$ptr),
4510 (int_arm_strex node:$val, node:$ptr), [{
4511 return cast<MemIntrinsicSDNode>(N)->getMemoryVT() == MVT::i8;
4514 def strex_2 : PatFrag<(ops node:$val, node:$ptr),
4515 (int_arm_strex node:$val, node:$ptr), [{
4516 return cast<MemIntrinsicSDNode>(N)->getMemoryVT() == MVT::i16;
4519 def strex_4 : PatFrag<(ops node:$val, node:$ptr),
4520 (int_arm_strex node:$val, node:$ptr), [{
4521 return cast<MemIntrinsicSDNode>(N)->getMemoryVT() == MVT::i32;
4524 def ldaex_1 : PatFrag<(ops node:$ptr), (int_arm_ldaex node:$ptr), [{
4525 return cast<MemIntrinsicSDNode>(N)->getMemoryVT() == MVT::i8;
4528 def ldaex_2 : PatFrag<(ops node:$ptr), (int_arm_ldaex node:$ptr), [{
4529 return cast<MemIntrinsicSDNode>(N)->getMemoryVT() == MVT::i16;
4532 def ldaex_4 : PatFrag<(ops node:$ptr), (int_arm_ldaex node:$ptr), [{
4533 return cast<MemIntrinsicSDNode>(N)->getMemoryVT() == MVT::i32;
4536 def stlex_1 : PatFrag<(ops node:$val, node:$ptr),
4537 (int_arm_stlex node:$val, node:$ptr), [{
4538 return cast<MemIntrinsicSDNode>(N)->getMemoryVT() == MVT::i8;
4541 def stlex_2 : PatFrag<(ops node:$val, node:$ptr),
4542 (int_arm_stlex node:$val, node:$ptr), [{
4543 return cast<MemIntrinsicSDNode>(N)->getMemoryVT() == MVT::i16;
4546 def stlex_4 : PatFrag<(ops node:$val, node:$ptr),
4547 (int_arm_stlex node:$val, node:$ptr), [{
4548 return cast<MemIntrinsicSDNode>(N)->getMemoryVT() == MVT::i32;
4551 let mayLoad = 1 in {
4552 def LDREXB : AIldrex<0b10, (outs GPR:$Rt), (ins addr_offset_none:$addr),
4553 NoItinerary, "ldrexb", "\t$Rt, $addr",
4554 [(set GPR:$Rt, (ldrex_1 addr_offset_none:$addr))]>;
4555 def LDREXH : AIldrex<0b11, (outs GPR:$Rt), (ins addr_offset_none:$addr),
4556 NoItinerary, "ldrexh", "\t$Rt, $addr",
4557 [(set GPR:$Rt, (ldrex_2 addr_offset_none:$addr))]>;
4558 def LDREX : AIldrex<0b00, (outs GPR:$Rt), (ins addr_offset_none:$addr),
4559 NoItinerary, "ldrex", "\t$Rt, $addr",
4560 [(set GPR:$Rt, (ldrex_4 addr_offset_none:$addr))]>;
4561 let hasExtraDefRegAllocReq = 1 in
4562 def LDREXD : AIldrex<0b01, (outs GPRPairOp:$Rt),(ins addr_offset_none:$addr),
4563 NoItinerary, "ldrexd", "\t$Rt, $addr", []> {
4564 let DecoderMethod = "DecodeDoubleRegLoad";
4567 def LDAEXB : AIldaex<0b10, (outs GPR:$Rt), (ins addr_offset_none:$addr),
4568 NoItinerary, "ldaexb", "\t$Rt, $addr",
4569 [(set GPR:$Rt, (ldaex_1 addr_offset_none:$addr))]>;
4570 def LDAEXH : AIldaex<0b11, (outs GPR:$Rt), (ins addr_offset_none:$addr),
4571 NoItinerary, "ldaexh", "\t$Rt, $addr",
4572 [(set GPR:$Rt, (ldaex_2 addr_offset_none:$addr))]>;
4573 def LDAEX : AIldaex<0b00, (outs GPR:$Rt), (ins addr_offset_none:$addr),
4574 NoItinerary, "ldaex", "\t$Rt, $addr",
4575 [(set GPR:$Rt, (ldaex_4 addr_offset_none:$addr))]>;
4576 let hasExtraDefRegAllocReq = 1 in
4577 def LDAEXD : AIldaex<0b01, (outs GPRPairOp:$Rt),(ins addr_offset_none:$addr),
4578 NoItinerary, "ldaexd", "\t$Rt, $addr", []> {
4579 let DecoderMethod = "DecodeDoubleRegLoad";
4583 let mayStore = 1, Constraints = "@earlyclobber $Rd" in {
4584 def STREXB: AIstrex<0b10, (outs GPR:$Rd), (ins GPR:$Rt, addr_offset_none:$addr),
4585 NoItinerary, "strexb", "\t$Rd, $Rt, $addr",
4586 [(set GPR:$Rd, (strex_1 GPR:$Rt,
4587 addr_offset_none:$addr))]>;
4588 def STREXH: AIstrex<0b11, (outs GPR:$Rd), (ins GPR:$Rt, addr_offset_none:$addr),
4589 NoItinerary, "strexh", "\t$Rd, $Rt, $addr",
4590 [(set GPR:$Rd, (strex_2 GPR:$Rt,
4591 addr_offset_none:$addr))]>;
4592 def STREX : AIstrex<0b00, (outs GPR:$Rd), (ins GPR:$Rt, addr_offset_none:$addr),
4593 NoItinerary, "strex", "\t$Rd, $Rt, $addr",
4594 [(set GPR:$Rd, (strex_4 GPR:$Rt,
4595 addr_offset_none:$addr))]>;
4596 let hasExtraSrcRegAllocReq = 1 in
4597 def STREXD : AIstrex<0b01, (outs GPR:$Rd),
4598 (ins GPRPairOp:$Rt, addr_offset_none:$addr),
4599 NoItinerary, "strexd", "\t$Rd, $Rt, $addr", []> {
4600 let DecoderMethod = "DecodeDoubleRegStore";
4602 def STLEXB: AIstlex<0b10, (outs GPR:$Rd), (ins GPR:$Rt, addr_offset_none:$addr),
4603 NoItinerary, "stlexb", "\t$Rd, $Rt, $addr",
4605 (stlex_1 GPR:$Rt, addr_offset_none:$addr))]>;
4606 def STLEXH: AIstlex<0b11, (outs GPR:$Rd), (ins GPR:$Rt, addr_offset_none:$addr),
4607 NoItinerary, "stlexh", "\t$Rd, $Rt, $addr",
4609 (stlex_2 GPR:$Rt, addr_offset_none:$addr))]>;
4610 def STLEX : AIstlex<0b00, (outs GPR:$Rd), (ins GPR:$Rt, addr_offset_none:$addr),
4611 NoItinerary, "stlex", "\t$Rd, $Rt, $addr",
4613 (stlex_4 GPR:$Rt, addr_offset_none:$addr))]>;
4614 let hasExtraSrcRegAllocReq = 1 in
4615 def STLEXD : AIstlex<0b01, (outs GPR:$Rd),
4616 (ins GPRPairOp:$Rt, addr_offset_none:$addr),
4617 NoItinerary, "stlexd", "\t$Rd, $Rt, $addr", []> {
4618 let DecoderMethod = "DecodeDoubleRegStore";
4622 def CLREX : AXI<(outs), (ins), MiscFrm, NoItinerary, "clrex",
4624 Requires<[IsARM, HasV7]> {
4625 let Inst{31-0} = 0b11110101011111111111000000011111;
4628 def : ARMPat<(strex_1 (and GPR:$Rt, 0xff), addr_offset_none:$addr),
4629 (STREXB GPR:$Rt, addr_offset_none:$addr)>;
4630 def : ARMPat<(strex_2 (and GPR:$Rt, 0xffff), addr_offset_none:$addr),
4631 (STREXH GPR:$Rt, addr_offset_none:$addr)>;
4633 def : ARMPat<(stlex_1 (and GPR:$Rt, 0xff), addr_offset_none:$addr),
4634 (STLEXB GPR:$Rt, addr_offset_none:$addr)>;
4635 def : ARMPat<(stlex_2 (and GPR:$Rt, 0xffff), addr_offset_none:$addr),
4636 (STLEXH GPR:$Rt, addr_offset_none:$addr)>;
4638 class acquiring_load<PatFrag base>
4639 : PatFrag<(ops node:$ptr), (base node:$ptr), [{
4640 AtomicOrdering Ordering = cast<AtomicSDNode>(N)->getOrdering();
4641 return isAtLeastAcquire(Ordering);
4644 def atomic_load_acquire_8 : acquiring_load<atomic_load_8>;
4645 def atomic_load_acquire_16 : acquiring_load<atomic_load_16>;
4646 def atomic_load_acquire_32 : acquiring_load<atomic_load_32>;
4648 class releasing_store<PatFrag base>
4649 : PatFrag<(ops node:$ptr, node:$val), (base node:$ptr, node:$val), [{
4650 AtomicOrdering Ordering = cast<AtomicSDNode>(N)->getOrdering();
4651 return isAtLeastRelease(Ordering);
4654 def atomic_store_release_8 : releasing_store<atomic_store_8>;
4655 def atomic_store_release_16 : releasing_store<atomic_store_16>;
4656 def atomic_store_release_32 : releasing_store<atomic_store_32>;
4658 let AddedComplexity = 8 in {
4659 def : ARMPat<(atomic_load_acquire_8 addr_offset_none:$addr), (LDAB addr_offset_none:$addr)>;
4660 def : ARMPat<(atomic_load_acquire_16 addr_offset_none:$addr), (LDAH addr_offset_none:$addr)>;
4661 def : ARMPat<(atomic_load_acquire_32 addr_offset_none:$addr), (LDA addr_offset_none:$addr)>;
4662 def : ARMPat<(atomic_store_release_8 addr_offset_none:$addr, GPR:$val), (STLB GPR:$val, addr_offset_none:$addr)>;
4663 def : ARMPat<(atomic_store_release_16 addr_offset_none:$addr, GPR:$val), (STLH GPR:$val, addr_offset_none:$addr)>;
4664 def : ARMPat<(atomic_store_release_32 addr_offset_none:$addr, GPR:$val), (STL GPR:$val, addr_offset_none:$addr)>;
4667 // SWP/SWPB are deprecated in V6/V7.
4668 let mayLoad = 1, mayStore = 1 in {
4669 def SWP : AIswp<0, (outs GPRnopc:$Rt),
4670 (ins GPRnopc:$Rt2, addr_offset_none:$addr), "swp", []>,
4672 def SWPB: AIswp<1, (outs GPRnopc:$Rt),
4673 (ins GPRnopc:$Rt2, addr_offset_none:$addr), "swpb", []>,
4677 //===----------------------------------------------------------------------===//
4678 // Coprocessor Instructions.
4681 def CDP : ABI<0b1110, (outs), (ins p_imm:$cop, imm0_15:$opc1,
4682 c_imm:$CRd, c_imm:$CRn, c_imm:$CRm, imm0_7:$opc2),
4683 NoItinerary, "cdp", "\t$cop, $opc1, $CRd, $CRn, $CRm, $opc2",
4684 [(int_arm_cdp imm:$cop, imm:$opc1, imm:$CRd, imm:$CRn,
4685 imm:$CRm, imm:$opc2)]>,
4694 let Inst{3-0} = CRm;
4696 let Inst{7-5} = opc2;
4697 let Inst{11-8} = cop;
4698 let Inst{15-12} = CRd;
4699 let Inst{19-16} = CRn;
4700 let Inst{23-20} = opc1;
4703 def CDP2 : ABXI<0b1110, (outs), (ins p_imm:$cop, imm0_15:$opc1,
4704 c_imm:$CRd, c_imm:$CRn, c_imm:$CRm, imm0_7:$opc2),
4705 NoItinerary, "cdp2\t$cop, $opc1, $CRd, $CRn, $CRm, $opc2",
4706 [(int_arm_cdp2 imm:$cop, imm:$opc1, imm:$CRd, imm:$CRn,
4707 imm:$CRm, imm:$opc2)]>,
4709 let Inst{31-28} = 0b1111;
4717 let Inst{3-0} = CRm;
4719 let Inst{7-5} = opc2;
4720 let Inst{11-8} = cop;
4721 let Inst{15-12} = CRd;
4722 let Inst{19-16} = CRn;
4723 let Inst{23-20} = opc1;
4726 class ACI<dag oops, dag iops, string opc, string asm,
4727 IndexMode im = IndexModeNone>
4728 : I<oops, iops, AddrModeNone, 4, im, BrFrm, NoItinerary,
4730 let Inst{27-25} = 0b110;
4732 class ACInoP<dag oops, dag iops, string opc, string asm,
4733 IndexMode im = IndexModeNone>
4734 : InoP<oops, iops, AddrModeNone, 4, im, BrFrm, NoItinerary,
4736 let Inst{31-28} = 0b1111;
4737 let Inst{27-25} = 0b110;
4739 multiclass LdStCop<bit load, bit Dbit, string asm> {
4740 def _OFFSET : ACI<(outs), (ins p_imm:$cop, c_imm:$CRd, addrmode5:$addr),
4741 asm, "\t$cop, $CRd, $addr"> {
4745 let Inst{24} = 1; // P = 1
4746 let Inst{23} = addr{8};
4747 let Inst{22} = Dbit;
4748 let Inst{21} = 0; // W = 0
4749 let Inst{20} = load;
4750 let Inst{19-16} = addr{12-9};
4751 let Inst{15-12} = CRd;
4752 let Inst{11-8} = cop;
4753 let Inst{7-0} = addr{7-0};
4754 let DecoderMethod = "DecodeCopMemInstruction";
4756 def _PRE : ACI<(outs), (ins p_imm:$cop, c_imm:$CRd, addrmode5_pre:$addr),
4757 asm, "\t$cop, $CRd, $addr!", IndexModePre> {
4761 let Inst{24} = 1; // P = 1
4762 let Inst{23} = addr{8};
4763 let Inst{22} = Dbit;
4764 let Inst{21} = 1; // W = 1
4765 let Inst{20} = load;
4766 let Inst{19-16} = addr{12-9};
4767 let Inst{15-12} = CRd;
4768 let Inst{11-8} = cop;
4769 let Inst{7-0} = addr{7-0};
4770 let DecoderMethod = "DecodeCopMemInstruction";
4772 def _POST: ACI<(outs), (ins p_imm:$cop, c_imm:$CRd, addr_offset_none:$addr,
4773 postidx_imm8s4:$offset),
4774 asm, "\t$cop, $CRd, $addr, $offset", IndexModePost> {
4779 let Inst{24} = 0; // P = 0
4780 let Inst{23} = offset{8};
4781 let Inst{22} = Dbit;
4782 let Inst{21} = 1; // W = 1
4783 let Inst{20} = load;
4784 let Inst{19-16} = addr;
4785 let Inst{15-12} = CRd;
4786 let Inst{11-8} = cop;
4787 let Inst{7-0} = offset{7-0};
4788 let DecoderMethod = "DecodeCopMemInstruction";
4790 def _OPTION : ACI<(outs),
4791 (ins p_imm:$cop, c_imm:$CRd, addr_offset_none:$addr,
4792 coproc_option_imm:$option),
4793 asm, "\t$cop, $CRd, $addr, $option"> {
4798 let Inst{24} = 0; // P = 0
4799 let Inst{23} = 1; // U = 1
4800 let Inst{22} = Dbit;
4801 let Inst{21} = 0; // W = 0
4802 let Inst{20} = load;
4803 let Inst{19-16} = addr;
4804 let Inst{15-12} = CRd;
4805 let Inst{11-8} = cop;
4806 let Inst{7-0} = option;
4807 let DecoderMethod = "DecodeCopMemInstruction";
4810 multiclass LdSt2Cop<bit load, bit Dbit, string asm> {
4811 def _OFFSET : ACInoP<(outs), (ins p_imm:$cop, c_imm:$CRd, addrmode5:$addr),
4812 asm, "\t$cop, $CRd, $addr"> {
4816 let Inst{24} = 1; // P = 1
4817 let Inst{23} = addr{8};
4818 let Inst{22} = Dbit;
4819 let Inst{21} = 0; // W = 0
4820 let Inst{20} = load;
4821 let Inst{19-16} = addr{12-9};
4822 let Inst{15-12} = CRd;
4823 let Inst{11-8} = cop;
4824 let Inst{7-0} = addr{7-0};
4825 let DecoderMethod = "DecodeCopMemInstruction";
4827 def _PRE : ACInoP<(outs), (ins p_imm:$cop, c_imm:$CRd, addrmode5_pre:$addr),
4828 asm, "\t$cop, $CRd, $addr!", IndexModePre> {
4832 let Inst{24} = 1; // P = 1
4833 let Inst{23} = addr{8};
4834 let Inst{22} = Dbit;
4835 let Inst{21} = 1; // W = 1
4836 let Inst{20} = load;
4837 let Inst{19-16} = addr{12-9};
4838 let Inst{15-12} = CRd;
4839 let Inst{11-8} = cop;
4840 let Inst{7-0} = addr{7-0};
4841 let DecoderMethod = "DecodeCopMemInstruction";
4843 def _POST: ACInoP<(outs), (ins p_imm:$cop, c_imm:$CRd, addr_offset_none:$addr,
4844 postidx_imm8s4:$offset),
4845 asm, "\t$cop, $CRd, $addr, $offset", IndexModePost> {
4850 let Inst{24} = 0; // P = 0
4851 let Inst{23} = offset{8};
4852 let Inst{22} = Dbit;
4853 let Inst{21} = 1; // W = 1
4854 let Inst{20} = load;
4855 let Inst{19-16} = addr;
4856 let Inst{15-12} = CRd;
4857 let Inst{11-8} = cop;
4858 let Inst{7-0} = offset{7-0};
4859 let DecoderMethod = "DecodeCopMemInstruction";
4861 def _OPTION : ACInoP<(outs),
4862 (ins p_imm:$cop, c_imm:$CRd, addr_offset_none:$addr,
4863 coproc_option_imm:$option),
4864 asm, "\t$cop, $CRd, $addr, $option"> {
4869 let Inst{24} = 0; // P = 0
4870 let Inst{23} = 1; // U = 1
4871 let Inst{22} = Dbit;
4872 let Inst{21} = 0; // W = 0
4873 let Inst{20} = load;
4874 let Inst{19-16} = addr;
4875 let Inst{15-12} = CRd;
4876 let Inst{11-8} = cop;
4877 let Inst{7-0} = option;
4878 let DecoderMethod = "DecodeCopMemInstruction";
4882 defm LDC : LdStCop <1, 0, "ldc">;
4883 defm LDCL : LdStCop <1, 1, "ldcl">;
4884 defm STC : LdStCop <0, 0, "stc">;
4885 defm STCL : LdStCop <0, 1, "stcl">;
4886 defm LDC2 : LdSt2Cop<1, 0, "ldc2">, Requires<[PreV8]>;
4887 defm LDC2L : LdSt2Cop<1, 1, "ldc2l">, Requires<[PreV8]>;
4888 defm STC2 : LdSt2Cop<0, 0, "stc2">, Requires<[PreV8]>;
4889 defm STC2L : LdSt2Cop<0, 1, "stc2l">, Requires<[PreV8]>;
4891 //===----------------------------------------------------------------------===//
4892 // Move between coprocessor and ARM core register.
4895 class MovRCopro<string opc, bit direction, dag oops, dag iops,
4897 : ABI<0b1110, oops, iops, NoItinerary, opc,
4898 "\t$cop, $opc1, $Rt, $CRn, $CRm, $opc2", pattern> {
4899 let Inst{20} = direction;
4909 let Inst{15-12} = Rt;
4910 let Inst{11-8} = cop;
4911 let Inst{23-21} = opc1;
4912 let Inst{7-5} = opc2;
4913 let Inst{3-0} = CRm;
4914 let Inst{19-16} = CRn;
4917 def MCR : MovRCopro<"mcr", 0 /* from ARM core register to coprocessor */,
4919 (ins p_imm:$cop, imm0_7:$opc1, GPR:$Rt, c_imm:$CRn,
4920 c_imm:$CRm, imm0_7:$opc2),
4921 [(int_arm_mcr imm:$cop, imm:$opc1, GPR:$Rt, imm:$CRn,
4922 imm:$CRm, imm:$opc2)]>,
4923 ComplexDeprecationPredicate<"MCR">;
4924 def : ARMInstAlias<"mcr${p} $cop, $opc1, $Rt, $CRn, $CRm",
4925 (MCR p_imm:$cop, imm0_7:$opc1, GPR:$Rt, c_imm:$CRn,
4926 c_imm:$CRm, 0, pred:$p)>;
4927 def MRC : MovRCopro<"mrc", 1 /* from coprocessor to ARM core register */,
4928 (outs GPRwithAPSR:$Rt),
4929 (ins p_imm:$cop, imm0_7:$opc1, c_imm:$CRn, c_imm:$CRm,
4931 def : ARMInstAlias<"mrc${p} $cop, $opc1, $Rt, $CRn, $CRm",
4932 (MRC GPRwithAPSR:$Rt, p_imm:$cop, imm0_7:$opc1, c_imm:$CRn,
4933 c_imm:$CRm, 0, pred:$p)>;
4935 def : ARMPat<(int_arm_mrc imm:$cop, imm:$opc1, imm:$CRn, imm:$CRm, imm:$opc2),
4936 (MRC imm:$cop, imm:$opc1, imm:$CRn, imm:$CRm, imm:$opc2)>;
4938 class MovRCopro2<string opc, bit direction, dag oops, dag iops,
4940 : ABXI<0b1110, oops, iops, NoItinerary,
4941 !strconcat(opc, "\t$cop, $opc1, $Rt, $CRn, $CRm, $opc2"), pattern> {
4942 let Inst{31-24} = 0b11111110;
4943 let Inst{20} = direction;
4953 let Inst{15-12} = Rt;
4954 let Inst{11-8} = cop;
4955 let Inst{23-21} = opc1;
4956 let Inst{7-5} = opc2;
4957 let Inst{3-0} = CRm;
4958 let Inst{19-16} = CRn;
4961 def MCR2 : MovRCopro2<"mcr2", 0 /* from ARM core register to coprocessor */,
4963 (ins p_imm:$cop, imm0_7:$opc1, GPR:$Rt, c_imm:$CRn,
4964 c_imm:$CRm, imm0_7:$opc2),
4965 [(int_arm_mcr2 imm:$cop, imm:$opc1, GPR:$Rt, imm:$CRn,
4966 imm:$CRm, imm:$opc2)]>,
4968 def : ARMInstAlias<"mcr2 $cop, $opc1, $Rt, $CRn, $CRm",
4969 (MCR2 p_imm:$cop, imm0_7:$opc1, GPR:$Rt, c_imm:$CRn,
4971 def MRC2 : MovRCopro2<"mrc2", 1 /* from coprocessor to ARM core register */,
4972 (outs GPRwithAPSR:$Rt),
4973 (ins p_imm:$cop, imm0_7:$opc1, c_imm:$CRn, c_imm:$CRm,
4976 def : ARMInstAlias<"mrc2 $cop, $opc1, $Rt, $CRn, $CRm",
4977 (MRC2 GPRwithAPSR:$Rt, p_imm:$cop, imm0_7:$opc1, c_imm:$CRn,
4980 def : ARMV5TPat<(int_arm_mrc2 imm:$cop, imm:$opc1, imm:$CRn,
4981 imm:$CRm, imm:$opc2),
4982 (MRC2 imm:$cop, imm:$opc1, imm:$CRn, imm:$CRm, imm:$opc2)>;
4984 class MovRRCopro<string opc, bit direction, list<dag> pattern = []>
4985 : ABI<0b1100, (outs), (ins p_imm:$cop, imm0_15:$opc1,
4986 GPRnopc:$Rt, GPRnopc:$Rt2, c_imm:$CRm),
4987 NoItinerary, opc, "\t$cop, $opc1, $Rt, $Rt2, $CRm", pattern> {
4988 let Inst{23-21} = 0b010;
4989 let Inst{20} = direction;
4997 let Inst{15-12} = Rt;
4998 let Inst{19-16} = Rt2;
4999 let Inst{11-8} = cop;
5000 let Inst{7-4} = opc1;
5001 let Inst{3-0} = CRm;
5004 def MCRR : MovRRCopro<"mcrr", 0 /* from ARM core register to coprocessor */,
5005 [(int_arm_mcrr imm:$cop, imm:$opc1, GPRnopc:$Rt,
5006 GPRnopc:$Rt2, imm:$CRm)]>;
5007 def MRRC : MovRRCopro<"mrrc", 1 /* from coprocessor to ARM core register */>;
5009 class MovRRCopro2<string opc, bit direction, list<dag> pattern = []>
5010 : ABXI<0b1100, (outs), (ins p_imm:$cop, imm0_15:$opc1,
5011 GPRnopc:$Rt, GPRnopc:$Rt2, c_imm:$CRm), NoItinerary,
5012 !strconcat(opc, "\t$cop, $opc1, $Rt, $Rt2, $CRm"), pattern>,
5014 let Inst{31-28} = 0b1111;
5015 let Inst{23-21} = 0b010;
5016 let Inst{20} = direction;
5024 let Inst{15-12} = Rt;
5025 let Inst{19-16} = Rt2;
5026 let Inst{11-8} = cop;
5027 let Inst{7-4} = opc1;
5028 let Inst{3-0} = CRm;
5030 let DecoderMethod = "DecodeMRRC2";
5033 def MCRR2 : MovRRCopro2<"mcrr2", 0 /* from ARM core register to coprocessor */,
5034 [(int_arm_mcrr2 imm:$cop, imm:$opc1, GPRnopc:$Rt,
5035 GPRnopc:$Rt2, imm:$CRm)]>;
5036 def MRRC2 : MovRRCopro2<"mrrc2", 1 /* from coprocessor to ARM core register */>;
5038 //===----------------------------------------------------------------------===//
5039 // Move between special register and ARM core register
5042 // Move to ARM core register from Special Register
5043 def MRS : ABI<0b0001, (outs GPRnopc:$Rd), (ins), NoItinerary,
5044 "mrs", "\t$Rd, apsr", []> {
5046 let Inst{23-16} = 0b00001111;
5047 let Unpredictable{19-17} = 0b111;
5049 let Inst{15-12} = Rd;
5051 let Inst{11-0} = 0b000000000000;
5052 let Unpredictable{11-0} = 0b110100001111;
5055 def : InstAlias<"mrs${p} $Rd, cpsr", (MRS GPRnopc:$Rd, pred:$p)>,
5058 // The MRSsys instruction is the MRS instruction from the ARM ARM,
5059 // section B9.3.9, with the R bit set to 1.
5060 def MRSsys : ABI<0b0001, (outs GPRnopc:$Rd), (ins), NoItinerary,
5061 "mrs", "\t$Rd, spsr", []> {
5063 let Inst{23-16} = 0b01001111;
5064 let Unpredictable{19-16} = 0b1111;
5066 let Inst{15-12} = Rd;
5068 let Inst{11-0} = 0b000000000000;
5069 let Unpredictable{11-0} = 0b110100001111;
5072 // However, the MRS (banked register) system instruction (ARMv7VE) *does* have a
5073 // separate encoding (distinguished by bit 5.
5074 def MRSbanked : ABI<0b0001, (outs GPRnopc:$Rd), (ins banked_reg:$banked),
5075 NoItinerary, "mrs", "\t$Rd, $banked", []>,
5076 Requires<[IsARM, HasVirtualization]> {
5081 let Inst{22} = banked{5}; // R bit
5082 let Inst{21-20} = 0b10;
5083 let Inst{19-16} = banked{3-0};
5084 let Inst{15-12} = Rd;
5085 let Inst{11-9} = 0b001;
5086 let Inst{8} = banked{4};
5087 let Inst{7-0} = 0b00000000;
5090 // Move from ARM core register to Special Register
5092 // No need to have both system and application versions of MSR (immediate) or
5093 // MSR (register), the encodings are the same and the assembly parser has no way
5094 // to distinguish between them. The mask operand contains the special register
5095 // (R Bit) in bit 4 and bits 3-0 contains the mask with the fields to be
5096 // accessed in the special register.
5097 def MSR : ABI<0b0001, (outs), (ins msr_mask:$mask, GPR:$Rn), NoItinerary,
5098 "msr", "\t$mask, $Rn", []> {
5103 let Inst{22} = mask{4}; // R bit
5104 let Inst{21-20} = 0b10;
5105 let Inst{19-16} = mask{3-0};
5106 let Inst{15-12} = 0b1111;
5107 let Inst{11-4} = 0b00000000;
5111 def MSRi : ABI<0b0011, (outs), (ins msr_mask:$mask, so_imm:$a), NoItinerary,
5112 "msr", "\t$mask, $a", []> {
5117 let Inst{22} = mask{4}; // R bit
5118 let Inst{21-20} = 0b10;
5119 let Inst{19-16} = mask{3-0};
5120 let Inst{15-12} = 0b1111;
5124 // However, the MSR (banked register) system instruction (ARMv7VE) *does* have a
5125 // separate encoding (distinguished by bit 5.
5126 def MSRbanked : ABI<0b0001, (outs), (ins banked_reg:$banked, GPRnopc:$Rn),
5127 NoItinerary, "msr", "\t$banked, $Rn", []>,
5128 Requires<[IsARM, HasVirtualization]> {
5133 let Inst{22} = banked{5}; // R bit
5134 let Inst{21-20} = 0b10;
5135 let Inst{19-16} = banked{3-0};
5136 let Inst{15-12} = 0b1111;
5137 let Inst{11-9} = 0b001;
5138 let Inst{8} = banked{4};
5139 let Inst{7-4} = 0b0000;
5143 // Dynamic stack allocation yields a _chkstk for Windows targets. These calls
5144 // are needed to probe the stack when allocating more than
5145 // 4k bytes in one go. Touching the stack at 4K increments is necessary to
5146 // ensure that the guard pages used by the OS virtual memory manager are
5147 // allocated in correct sequence.
5148 // The main point of having separate instruction are extra unmodelled effects
5149 // (compared to ordinary calls) like stack pointer change.
5151 def win__chkstk : SDNode<"ARMISD::WIN__CHKSTK", SDTNone,
5152 [SDNPHasChain, SDNPSideEffect]>;
5153 let usesCustomInserter = 1, Uses = [R4], Defs = [R4, SP] in
5154 def WIN__CHKSTK : PseudoInst<(outs), (ins), NoItinerary, [(win__chkstk)]>;
5156 //===----------------------------------------------------------------------===//
5160 // __aeabi_read_tp preserves the registers r1-r3.
5161 // This is a pseudo inst so that we can get the encoding right,
5162 // complete with fixup for the aeabi_read_tp function.
5163 // TPsoft is valid for ARM mode only, in case of Thumb mode a tTPsoft pattern
5164 // is defined in "ARMInstrThumb.td".
5166 Defs = [R0, R12, LR, CPSR], Uses = [SP] in {
5167 def TPsoft : ARMPseudoInst<(outs), (ins), 4, IIC_Br,
5168 [(set R0, ARMthread_pointer)]>, Sched<[WriteBr]>;
5171 //===----------------------------------------------------------------------===//
5172 // SJLJ Exception handling intrinsics
5173 // eh_sjlj_setjmp() is an instruction sequence to store the return
5174 // address and save #0 in R0 for the non-longjmp case.
5175 // Since by its nature we may be coming from some other function to get
5176 // here, and we're using the stack frame for the containing function to
5177 // save/restore registers, we can't keep anything live in regs across
5178 // the eh_sjlj_setjmp(), else it will almost certainly have been tromped upon
5179 // when we get here from a longjmp(). We force everything out of registers
5180 // except for our own input by listing the relevant registers in Defs. By
5181 // doing so, we also cause the prologue/epilogue code to actively preserve
5182 // all of the callee-saved resgisters, which is exactly what we want.
5183 // A constant value is passed in $val, and we use the location as a scratch.
5185 // These are pseudo-instructions and are lowered to individual MC-insts, so
5186 // no encoding information is necessary.
5188 [ R0, R1, R2, R3, R4, R5, R6, R7, R8, R9, R10, R11, R12, LR, CPSR,
5189 Q0, Q1, Q2, Q3, Q4, Q5, Q6, Q7, Q8, Q9, Q10, Q11, Q12, Q13, Q14, Q15 ],
5190 hasSideEffects = 1, isBarrier = 1, usesCustomInserter = 1 in {
5191 def Int_eh_sjlj_setjmp : PseudoInst<(outs), (ins GPR:$src, GPR:$val),
5193 [(set R0, (ARMeh_sjlj_setjmp GPR:$src, GPR:$val))]>,
5194 Requires<[IsARM, HasVFP2]>;
5198 [ R0, R1, R2, R3, R4, R5, R6, R7, R8, R9, R10, R11, R12, LR, CPSR ],
5199 hasSideEffects = 1, isBarrier = 1, usesCustomInserter = 1 in {
5200 def Int_eh_sjlj_setjmp_nofp : PseudoInst<(outs), (ins GPR:$src, GPR:$val),
5202 [(set R0, (ARMeh_sjlj_setjmp GPR:$src, GPR:$val))]>,
5203 Requires<[IsARM, NoVFP]>;
5206 // FIXME: Non-IOS version(s)
5207 let isBarrier = 1, hasSideEffects = 1, isTerminator = 1,
5208 Defs = [ R7, LR, SP ] in {
5209 def Int_eh_sjlj_longjmp : PseudoInst<(outs), (ins GPR:$src, GPR:$scratch),
5211 [(ARMeh_sjlj_longjmp GPR:$src, GPR:$scratch)]>,
5212 Requires<[IsARM, IsIOS]>;
5215 // eh.sjlj.dispatchsetup pseudo-instruction.
5216 // This pseudo is used for both ARM and Thumb. Any differences are handled when
5217 // the pseudo is expanded (which happens before any passes that need the
5218 // instruction size).
5219 let isBarrier = 1 in
5220 def Int_eh_sjlj_dispatchsetup : PseudoInst<(outs), (ins), NoItinerary, []>;
5223 //===----------------------------------------------------------------------===//
5224 // Non-Instruction Patterns
5227 // ARMv4 indirect branch using (MOVr PC, dst)
5228 let isBranch = 1, isTerminator = 1, isBarrier = 1, isIndirectBranch = 1 in
5229 def MOVPCRX : ARMPseudoExpand<(outs), (ins GPR:$dst),
5230 4, IIC_Br, [(brind GPR:$dst)],
5231 (MOVr PC, GPR:$dst, (ops 14, zero_reg), zero_reg)>,
5232 Requires<[IsARM, NoV4T]>, Sched<[WriteBr]>;
5234 // Large immediate handling.
5236 // 32-bit immediate using two piece so_imms or movw + movt.
5237 // This is a single pseudo instruction, the benefit is that it can be remat'd
5238 // as a single unit instead of having to handle reg inputs.
5239 // FIXME: Remove this when we can do generalized remat.
5240 let isReMaterializable = 1, isMoveImm = 1 in
5241 def MOVi32imm : PseudoInst<(outs GPR:$dst), (ins i32imm:$src), IIC_iMOVix2,
5242 [(set GPR:$dst, (arm_i32imm:$src))]>,
5245 def LDRLIT_ga_abs : PseudoInst<(outs GPR:$dst), (ins i32imm:$src), IIC_iLoad_i,
5246 [(set GPR:$dst, (ARMWrapper tglobaladdr:$src))]>,
5247 Requires<[IsARM, DontUseMovt]>;
5249 // Pseudo instruction that combines movw + movt + add pc (if PIC).
5250 // It also makes it possible to rematerialize the instructions.
5251 // FIXME: Remove this when we can do generalized remat and when machine licm
5252 // can properly the instructions.
5253 let isReMaterializable = 1 in {
5254 def MOV_ga_pcrel : PseudoInst<(outs GPR:$dst), (ins i32imm:$addr),
5256 [(set GPR:$dst, (ARMWrapperPIC tglobaladdr:$addr))]>,
5257 Requires<[IsARM, UseMovt]>;
5259 def LDRLIT_ga_pcrel : PseudoInst<(outs GPR:$dst), (ins i32imm:$addr),
5262 (ARMWrapperPIC tglobaladdr:$addr))]>,
5263 Requires<[IsARM, DontUseMovt]>;
5265 def LDRLIT_ga_pcrel_ldr : PseudoInst<(outs GPR:$dst), (ins i32imm:$addr),
5268 (load (ARMWrapperPIC tglobaladdr:$addr)))]>,
5269 Requires<[IsARM, DontUseMovt]>;
5271 let AddedComplexity = 10 in
5272 def MOV_ga_pcrel_ldr : PseudoInst<(outs GPR:$dst), (ins i32imm:$addr),
5274 [(set GPR:$dst, (load (ARMWrapperPIC tglobaladdr:$addr)))]>,
5275 Requires<[IsARM, UseMovt]>;
5276 } // isReMaterializable
5278 // ConstantPool, GlobalAddress, and JumpTable
5279 def : ARMPat<(ARMWrapper tconstpool :$dst), (LEApcrel tconstpool :$dst)>;
5280 def : ARMPat<(ARMWrapper tglobaladdr :$dst), (MOVi32imm tglobaladdr :$dst)>,
5281 Requires<[IsARM, UseMovt]>;
5282 def : ARMPat<(ARMWrapperJT tjumptable:$dst, imm:$id),
5283 (LEApcrelJT tjumptable:$dst, imm:$id)>;
5285 // TODO: add,sub,and, 3-instr forms?
5287 // Tail calls. These patterns also apply to Thumb mode.
5288 def : Pat<(ARMtcret tcGPR:$dst), (TCRETURNri tcGPR:$dst)>;
5289 def : Pat<(ARMtcret (i32 tglobaladdr:$dst)), (TCRETURNdi texternalsym:$dst)>;
5290 def : Pat<(ARMtcret (i32 texternalsym:$dst)), (TCRETURNdi texternalsym:$dst)>;
5293 def : ARMPat<(ARMcall texternalsym:$func), (BL texternalsym:$func)>;
5294 def : ARMPat<(ARMcall_nolink texternalsym:$func),
5295 (BMOVPCB_CALL texternalsym:$func)>;
5297 // zextload i1 -> zextload i8
5298 def : ARMPat<(zextloadi1 addrmode_imm12:$addr), (LDRBi12 addrmode_imm12:$addr)>;
5299 def : ARMPat<(zextloadi1 ldst_so_reg:$addr), (LDRBrs ldst_so_reg:$addr)>;
5301 // extload -> zextload
5302 def : ARMPat<(extloadi1 addrmode_imm12:$addr), (LDRBi12 addrmode_imm12:$addr)>;
5303 def : ARMPat<(extloadi1 ldst_so_reg:$addr), (LDRBrs ldst_so_reg:$addr)>;
5304 def : ARMPat<(extloadi8 addrmode_imm12:$addr), (LDRBi12 addrmode_imm12:$addr)>;
5305 def : ARMPat<(extloadi8 ldst_so_reg:$addr), (LDRBrs ldst_so_reg:$addr)>;
5307 def : ARMPat<(extloadi16 addrmode3:$addr), (LDRH addrmode3:$addr)>;
5309 def : ARMPat<(extloadi8 addrmodepc:$addr), (PICLDRB addrmodepc:$addr)>;
5310 def : ARMPat<(extloadi16 addrmodepc:$addr), (PICLDRH addrmodepc:$addr)>;
5313 def : ARMV5TEPat<(mul (sra (shl GPR:$a, (i32 16)), (i32 16)),
5314 (sra (shl GPR:$b, (i32 16)), (i32 16))),
5315 (SMULBB GPR:$a, GPR:$b)>;
5316 def : ARMV5TEPat<(mul sext_16_node:$a, sext_16_node:$b),
5317 (SMULBB GPR:$a, GPR:$b)>;
5318 def : ARMV5TEPat<(mul (sra (shl GPR:$a, (i32 16)), (i32 16)),
5319 (sra GPR:$b, (i32 16))),
5320 (SMULBT GPR:$a, GPR:$b)>;
5321 def : ARMV5TEPat<(mul sext_16_node:$a, (sra GPR:$b, (i32 16))),
5322 (SMULBT GPR:$a, GPR:$b)>;
5323 def : ARMV5TEPat<(mul (sra GPR:$a, (i32 16)),
5324 (sra (shl GPR:$b, (i32 16)), (i32 16))),
5325 (SMULTB GPR:$a, GPR:$b)>;
5326 def : ARMV5TEPat<(mul (sra GPR:$a, (i32 16)), sext_16_node:$b),
5327 (SMULTB GPR:$a, GPR:$b)>;
5328 def : ARMV5TEPat<(sra (mul GPR:$a, (sra (shl GPR:$b, (i32 16)), (i32 16))),
5330 (SMULWB GPR:$a, GPR:$b)>;
5331 def : ARMV5TEPat<(sra (mul GPR:$a, sext_16_node:$b), (i32 16)),
5332 (SMULWB GPR:$a, GPR:$b)>;
5334 def : ARMV5MOPat<(add GPR:$acc,
5335 (mul (sra (shl GPR:$a, (i32 16)), (i32 16)),
5336 (sra (shl GPR:$b, (i32 16)), (i32 16)))),
5337 (SMLABB GPR:$a, GPR:$b, GPR:$acc)>;
5338 def : ARMV5MOPat<(add GPR:$acc,
5339 (mul sext_16_node:$a, sext_16_node:$b)),
5340 (SMLABB GPR:$a, GPR:$b, GPR:$acc)>;
5341 def : ARMV5MOPat<(add GPR:$acc,
5342 (mul (sra (shl GPR:$a, (i32 16)), (i32 16)),
5343 (sra GPR:$b, (i32 16)))),
5344 (SMLABT GPR:$a, GPR:$b, GPR:$acc)>;
5345 def : ARMV5MOPat<(add GPR:$acc,
5346 (mul sext_16_node:$a, (sra GPR:$b, (i32 16)))),
5347 (SMLABT GPR:$a, GPR:$b, GPR:$acc)>;
5348 def : ARMV5MOPat<(add GPR:$acc,
5349 (mul (sra GPR:$a, (i32 16)),
5350 (sra (shl GPR:$b, (i32 16)), (i32 16)))),
5351 (SMLATB GPR:$a, GPR:$b, GPR:$acc)>;
5352 def : ARMV5MOPat<(add GPR:$acc,
5353 (mul (sra GPR:$a, (i32 16)), sext_16_node:$b)),
5354 (SMLATB GPR:$a, GPR:$b, GPR:$acc)>;
5355 def : ARMV5MOPat<(add GPR:$acc,
5356 (sra (mul GPR:$a, (sra (shl GPR:$b, (i32 16)), (i32 16))),
5358 (SMLAWB GPR:$a, GPR:$b, GPR:$acc)>;
5359 def : ARMV5MOPat<(add GPR:$acc,
5360 (sra (mul GPR:$a, sext_16_node:$b), (i32 16))),
5361 (SMLAWB GPR:$a, GPR:$b, GPR:$acc)>;
5364 // Pre-v7 uses MCR for synchronization barriers.
5365 def : ARMPat<(ARMMemBarrierMCR GPR:$zero), (MCR 15, 0, GPR:$zero, 7, 10, 5)>,
5366 Requires<[IsARM, HasV6]>;
5368 // SXT/UXT with no rotate
5369 let AddedComplexity = 16 in {
5370 def : ARMV6Pat<(and GPR:$Src, 0x000000FF), (UXTB GPR:$Src, 0)>;
5371 def : ARMV6Pat<(and GPR:$Src, 0x0000FFFF), (UXTH GPR:$Src, 0)>;
5372 def : ARMV6Pat<(and GPR:$Src, 0x00FF00FF), (UXTB16 GPR:$Src, 0)>;
5373 def : ARMV6Pat<(add GPR:$Rn, (and GPR:$Rm, 0x00FF)),
5374 (UXTAB GPR:$Rn, GPR:$Rm, 0)>;
5375 def : ARMV6Pat<(add GPR:$Rn, (and GPR:$Rm, 0xFFFF)),
5376 (UXTAH GPR:$Rn, GPR:$Rm, 0)>;
5379 def : ARMV6Pat<(sext_inreg GPR:$Src, i8), (SXTB GPR:$Src, 0)>;
5380 def : ARMV6Pat<(sext_inreg GPR:$Src, i16), (SXTH GPR:$Src, 0)>;
5382 def : ARMV6Pat<(add GPR:$Rn, (sext_inreg GPRnopc:$Rm, i8)),
5383 (SXTAB GPR:$Rn, GPRnopc:$Rm, 0)>;
5384 def : ARMV6Pat<(add GPR:$Rn, (sext_inreg GPRnopc:$Rm, i16)),
5385 (SXTAH GPR:$Rn, GPRnopc:$Rm, 0)>;
5387 // Atomic load/store patterns
5388 def : ARMPat<(atomic_load_8 ldst_so_reg:$src),
5389 (LDRBrs ldst_so_reg:$src)>;
5390 def : ARMPat<(atomic_load_8 addrmode_imm12:$src),
5391 (LDRBi12 addrmode_imm12:$src)>;
5392 def : ARMPat<(atomic_load_16 addrmode3:$src),
5393 (LDRH addrmode3:$src)>;
5394 def : ARMPat<(atomic_load_32 ldst_so_reg:$src),
5395 (LDRrs ldst_so_reg:$src)>;
5396 def : ARMPat<(atomic_load_32 addrmode_imm12:$src),
5397 (LDRi12 addrmode_imm12:$src)>;
5398 def : ARMPat<(atomic_store_8 ldst_so_reg:$ptr, GPR:$val),
5399 (STRBrs GPR:$val, ldst_so_reg:$ptr)>;
5400 def : ARMPat<(atomic_store_8 addrmode_imm12:$ptr, GPR:$val),
5401 (STRBi12 GPR:$val, addrmode_imm12:$ptr)>;
5402 def : ARMPat<(atomic_store_16 addrmode3:$ptr, GPR:$val),
5403 (STRH GPR:$val, addrmode3:$ptr)>;
5404 def : ARMPat<(atomic_store_32 ldst_so_reg:$ptr, GPR:$val),
5405 (STRrs GPR:$val, ldst_so_reg:$ptr)>;
5406 def : ARMPat<(atomic_store_32 addrmode_imm12:$ptr, GPR:$val),
5407 (STRi12 GPR:$val, addrmode_imm12:$ptr)>;
5410 //===----------------------------------------------------------------------===//
5414 include "ARMInstrThumb.td"
5416 //===----------------------------------------------------------------------===//
5420 include "ARMInstrThumb2.td"
5422 //===----------------------------------------------------------------------===//
5423 // Floating Point Support
5426 include "ARMInstrVFP.td"
5428 //===----------------------------------------------------------------------===//
5429 // Advanced SIMD (NEON) Support
5432 include "ARMInstrNEON.td"
5434 //===----------------------------------------------------------------------===//
5435 // Assembler aliases
5439 def : InstAlias<"dmb", (DMB 0xf)>, Requires<[IsARM, HasDB]>;
5440 def : InstAlias<"dsb", (DSB 0xf)>, Requires<[IsARM, HasDB]>;
5441 def : InstAlias<"isb", (ISB 0xf)>, Requires<[IsARM, HasDB]>;
5443 // System instructions
5444 def : MnemonicAlias<"swi", "svc">;
5446 // Load / Store Multiple
5447 def : MnemonicAlias<"ldmfd", "ldm">;
5448 def : MnemonicAlias<"ldmia", "ldm">;
5449 def : MnemonicAlias<"ldmea", "ldmdb">;
5450 def : MnemonicAlias<"stmfd", "stmdb">;
5451 def : MnemonicAlias<"stmia", "stm">;
5452 def : MnemonicAlias<"stmea", "stm">;
5454 // PKHBT/PKHTB with default shift amount. PKHTB is equivalent to PKHBT when the
5455 // shift amount is zero (i.e., unspecified).
5456 def : InstAlias<"pkhbt${p} $Rd, $Rn, $Rm",
5457 (PKHBT GPRnopc:$Rd, GPRnopc:$Rn, GPRnopc:$Rm, 0, pred:$p)>,
5458 Requires<[IsARM, HasV6]>;
5459 def : InstAlias<"pkhtb${p} $Rd, $Rn, $Rm",
5460 (PKHBT GPRnopc:$Rd, GPRnopc:$Rn, GPRnopc:$Rm, 0, pred:$p)>,
5461 Requires<[IsARM, HasV6]>;
5463 // PUSH/POP aliases for STM/LDM
5464 def : ARMInstAlias<"push${p} $regs", (STMDB_UPD SP, pred:$p, reglist:$regs)>;
5465 def : ARMInstAlias<"pop${p} $regs", (LDMIA_UPD SP, pred:$p, reglist:$regs)>;
5467 // SSAT/USAT optional shift operand.
5468 def : ARMInstAlias<"ssat${p} $Rd, $sat_imm, $Rn",
5469 (SSAT GPRnopc:$Rd, imm1_32:$sat_imm, GPRnopc:$Rn, 0, pred:$p)>;
5470 def : ARMInstAlias<"usat${p} $Rd, $sat_imm, $Rn",
5471 (USAT GPRnopc:$Rd, imm0_31:$sat_imm, GPRnopc:$Rn, 0, pred:$p)>;
5474 // Extend instruction optional rotate operand.
5475 def : ARMInstAlias<"sxtab${p} $Rd, $Rn, $Rm",
5476 (SXTAB GPRnopc:$Rd, GPR:$Rn, GPRnopc:$Rm, 0, pred:$p)>;
5477 def : ARMInstAlias<"sxtah${p} $Rd, $Rn, $Rm",
5478 (SXTAH GPRnopc:$Rd, GPR:$Rn, GPRnopc:$Rm, 0, pred:$p)>;
5479 def : ARMInstAlias<"sxtab16${p} $Rd, $Rn, $Rm",
5480 (SXTAB16 GPRnopc:$Rd, GPR:$Rn, GPRnopc:$Rm, 0, pred:$p)>;
5481 def : ARMInstAlias<"sxtb${p} $Rd, $Rm",
5482 (SXTB GPRnopc:$Rd, GPRnopc:$Rm, 0, pred:$p)>;
5483 def : ARMInstAlias<"sxtb16${p} $Rd, $Rm",
5484 (SXTB16 GPRnopc:$Rd, GPRnopc:$Rm, 0, pred:$p)>;
5485 def : ARMInstAlias<"sxth${p} $Rd, $Rm",
5486 (SXTH GPRnopc:$Rd, GPRnopc:$Rm, 0, pred:$p)>;
5488 def : ARMInstAlias<"uxtab${p} $Rd, $Rn, $Rm",
5489 (UXTAB GPRnopc:$Rd, GPR:$Rn, GPRnopc:$Rm, 0, pred:$p)>;
5490 def : ARMInstAlias<"uxtah${p} $Rd, $Rn, $Rm",
5491 (UXTAH GPRnopc:$Rd, GPR:$Rn, GPRnopc:$Rm, 0, pred:$p)>;
5492 def : ARMInstAlias<"uxtab16${p} $Rd, $Rn, $Rm",
5493 (UXTAB16 GPRnopc:$Rd, GPR:$Rn, GPRnopc:$Rm, 0, pred:$p)>;
5494 def : ARMInstAlias<"uxtb${p} $Rd, $Rm",
5495 (UXTB GPRnopc:$Rd, GPRnopc:$Rm, 0, pred:$p)>;
5496 def : ARMInstAlias<"uxtb16${p} $Rd, $Rm",
5497 (UXTB16 GPRnopc:$Rd, GPRnopc:$Rm, 0, pred:$p)>;
5498 def : ARMInstAlias<"uxth${p} $Rd, $Rm",
5499 (UXTH GPRnopc:$Rd, GPRnopc:$Rm, 0, pred:$p)>;
5503 def : MnemonicAlias<"rfefa", "rfeda">;
5504 def : MnemonicAlias<"rfeea", "rfedb">;
5505 def : MnemonicAlias<"rfefd", "rfeia">;
5506 def : MnemonicAlias<"rfeed", "rfeib">;
5507 def : MnemonicAlias<"rfe", "rfeia">;
5510 def : MnemonicAlias<"srsfa", "srsib">;
5511 def : MnemonicAlias<"srsea", "srsia">;
5512 def : MnemonicAlias<"srsfd", "srsdb">;
5513 def : MnemonicAlias<"srsed", "srsda">;
5514 def : MnemonicAlias<"srs", "srsia">;
5517 def : MnemonicAlias<"qsubaddx", "qsax">;
5519 def : MnemonicAlias<"saddsubx", "sasx">;
5520 // SHASX == SHADDSUBX
5521 def : MnemonicAlias<"shaddsubx", "shasx">;
5522 // SHSAX == SHSUBADDX
5523 def : MnemonicAlias<"shsubaddx", "shsax">;
5525 def : MnemonicAlias<"ssubaddx", "ssax">;
5527 def : MnemonicAlias<"uaddsubx", "uasx">;
5528 // UHASX == UHADDSUBX
5529 def : MnemonicAlias<"uhaddsubx", "uhasx">;
5530 // UHSAX == UHSUBADDX
5531 def : MnemonicAlias<"uhsubaddx", "uhsax">;
5532 // UQASX == UQADDSUBX
5533 def : MnemonicAlias<"uqaddsubx", "uqasx">;
5534 // UQSAX == UQSUBADDX
5535 def : MnemonicAlias<"uqsubaddx", "uqsax">;
5537 def : MnemonicAlias<"usubaddx", "usax">;
5539 // "mov Rd, so_imm_not" can be handled via "mvn" in assembly, just like
5541 def : ARMInstAlias<"mov${s}${p} $Rd, $imm",
5542 (MVNi rGPR:$Rd, so_imm_not:$imm, pred:$p, cc_out:$s)>;
5543 def : ARMInstAlias<"mvn${s}${p} $Rd, $imm",
5544 (MOVi rGPR:$Rd, so_imm_not:$imm, pred:$p, cc_out:$s)>;
5545 // Same for AND <--> BIC
5546 def : ARMInstAlias<"bic${s}${p} $Rd, $Rn, $imm",
5547 (ANDri rGPR:$Rd, rGPR:$Rn, so_imm_not:$imm,
5548 pred:$p, cc_out:$s)>;
5549 def : ARMInstAlias<"bic${s}${p} $Rdn, $imm",
5550 (ANDri rGPR:$Rdn, rGPR:$Rdn, so_imm_not:$imm,
5551 pred:$p, cc_out:$s)>;
5552 def : ARMInstAlias<"and${s}${p} $Rd, $Rn, $imm",
5553 (BICri rGPR:$Rd, rGPR:$Rn, so_imm_not:$imm,
5554 pred:$p, cc_out:$s)>;
5555 def : ARMInstAlias<"and${s}${p} $Rdn, $imm",
5556 (BICri rGPR:$Rdn, rGPR:$Rdn, so_imm_not:$imm,
5557 pred:$p, cc_out:$s)>;
5559 // Likewise, "add Rd, so_imm_neg" -> sub
5560 def : ARMInstAlias<"add${s}${p} $Rd, $Rn, $imm",
5561 (SUBri GPR:$Rd, GPR:$Rn, so_imm_neg:$imm, pred:$p, cc_out:$s)>;
5562 def : ARMInstAlias<"add${s}${p} $Rd, $imm",
5563 (SUBri GPR:$Rd, GPR:$Rd, so_imm_neg:$imm, pred:$p, cc_out:$s)>;
5564 // Same for CMP <--> CMN via so_imm_neg
5565 def : ARMInstAlias<"cmp${p} $Rd, $imm",
5566 (CMNri rGPR:$Rd, so_imm_neg:$imm, pred:$p)>;
5567 def : ARMInstAlias<"cmn${p} $Rd, $imm",
5568 (CMPri rGPR:$Rd, so_imm_neg:$imm, pred:$p)>;
5570 // The shifter forms of the MOV instruction are aliased to the ASR, LSL,
5571 // LSR, ROR, and RRX instructions.
5572 // FIXME: We need C++ parser hooks to map the alias to the MOV
5573 // encoding. It seems we should be able to do that sort of thing
5574 // in tblgen, but it could get ugly.
5575 let TwoOperandAliasConstraint = "$Rm = $Rd" in {
5576 def ASRi : ARMAsmPseudo<"asr${s}${p} $Rd, $Rm, $imm",
5577 (ins GPR:$Rd, GPR:$Rm, imm0_32:$imm, pred:$p,
5579 def LSRi : ARMAsmPseudo<"lsr${s}${p} $Rd, $Rm, $imm",
5580 (ins GPR:$Rd, GPR:$Rm, imm0_32:$imm, pred:$p,
5582 def LSLi : ARMAsmPseudo<"lsl${s}${p} $Rd, $Rm, $imm",
5583 (ins GPR:$Rd, GPR:$Rm, imm0_31:$imm, pred:$p,
5585 def RORi : ARMAsmPseudo<"ror${s}${p} $Rd, $Rm, $imm",
5586 (ins GPR:$Rd, GPR:$Rm, imm0_31:$imm, pred:$p,
5589 def RRXi : ARMAsmPseudo<"rrx${s}${p} $Rd, $Rm",
5590 (ins GPR:$Rd, GPR:$Rm, pred:$p, cc_out:$s)>;
5591 let TwoOperandAliasConstraint = "$Rn = $Rd" in {
5592 def ASRr : ARMAsmPseudo<"asr${s}${p} $Rd, $Rn, $Rm",
5593 (ins GPRnopc:$Rd, GPRnopc:$Rn, GPRnopc:$Rm, pred:$p,
5595 def LSRr : ARMAsmPseudo<"lsr${s}${p} $Rd, $Rn, $Rm",
5596 (ins GPRnopc:$Rd, GPRnopc:$Rn, GPRnopc:$Rm, pred:$p,
5598 def LSLr : ARMAsmPseudo<"lsl${s}${p} $Rd, $Rn, $Rm",
5599 (ins GPRnopc:$Rd, GPRnopc:$Rn, GPRnopc:$Rm, pred:$p,
5601 def RORr : ARMAsmPseudo<"ror${s}${p} $Rd, $Rn, $Rm",
5602 (ins GPRnopc:$Rd, GPRnopc:$Rn, GPRnopc:$Rm, pred:$p,
5606 // "neg" is and alias for "rsb rd, rn, #0"
5607 def : ARMInstAlias<"neg${s}${p} $Rd, $Rm",
5608 (RSBri GPR:$Rd, GPR:$Rm, 0, pred:$p, cc_out:$s)>;
5610 // Pre-v6, 'mov r0, r0' was used as a NOP encoding.
5611 def : InstAlias<"nop${p}", (MOVr R0, R0, pred:$p, zero_reg)>,
5612 Requires<[IsARM, NoV6]>;
5614 // MUL/UMLAL/SMLAL/UMULL/SMULL are available on all arches, but
5615 // the instruction definitions need difference constraints pre-v6.
5616 // Use these aliases for the assembly parsing on pre-v6.
5617 def : InstAlias<"mul${s}${p} $Rd, $Rn, $Rm",
5618 (MUL GPRnopc:$Rd, GPRnopc:$Rn, GPRnopc:$Rm, pred:$p, cc_out:$s)>,
5619 Requires<[IsARM, NoV6]>;
5620 def : InstAlias<"mla${s}${p} $Rd, $Rn, $Rm, $Ra",
5621 (MLA GPRnopc:$Rd, GPRnopc:$Rn, GPRnopc:$Rm, GPRnopc:$Ra,
5622 pred:$p, cc_out:$s)>,
5623 Requires<[IsARM, NoV6]>;
5624 def : InstAlias<"smlal${s}${p} $RdLo, $RdHi, $Rn, $Rm",
5625 (SMLAL GPR:$RdLo, GPR:$RdHi, GPR:$Rn, GPR:$Rm, pred:$p, cc_out:$s)>,
5626 Requires<[IsARM, NoV6]>;
5627 def : InstAlias<"umlal${s}${p} $RdLo, $RdHi, $Rn, $Rm",
5628 (UMLAL GPR:$RdLo, GPR:$RdHi, GPR:$Rn, GPR:$Rm, pred:$p, cc_out:$s)>,
5629 Requires<[IsARM, NoV6]>;
5630 def : InstAlias<"smull${s}${p} $RdLo, $RdHi, $Rn, $Rm",
5631 (SMULL GPR:$RdLo, GPR:$RdHi, GPR:$Rn, GPR:$Rm, pred:$p, cc_out:$s)>,
5632 Requires<[IsARM, NoV6]>;
5633 def : InstAlias<"umull${s}${p} $RdLo, $RdHi, $Rn, $Rm",
5634 (UMULL GPR:$RdLo, GPR:$RdHi, GPR:$Rn, GPR:$Rm, pred:$p, cc_out:$s)>,
5635 Requires<[IsARM, NoV6]>;
5637 // 'it' blocks in ARM mode just validate the predicates. The IT itself
5639 def ITasm : ARMAsmPseudo<"it$mask $cc", (ins it_pred:$cc, it_mask:$mask)>,
5640 ComplexDeprecationPredicate<"IT">;