1 //===- ARMInstrInfo.td - Target Description for ARM Target ----------------===//
3 // The LLVM Compiler Infrastructure
5 // This file was developed by the "Instituto Nokia de Tecnologia" and
6 // is distributed under the University of Illinois Open Source
7 // License. See LICENSE.TXT for details.
9 //===----------------------------------------------------------------------===//
11 // This file describes the ARM instructions in TableGen format.
13 //===----------------------------------------------------------------------===//
16 def op_addr_mode1 : Operand<iPTR> {
17 let PrintMethod = "printAddrMode1";
18 let MIOperandInfo = (ops ptr_rc, ptr_rc, i32imm);
21 def op_addr_mode2 : Operand<iPTR> {
22 let PrintMethod = "printAddrMode2";
23 let MIOperandInfo = (ops ptr_rc, i32imm);
26 def op_addr_mode5 : Operand<iPTR> {
27 let PrintMethod = "printAddrMode5";
28 let MIOperandInfo = (ops ptr_rc, i32imm);
31 // Define ARM specific addressing mode.
32 //Addressing Mode 1: data processing operands
33 def addr_mode1 : ComplexPattern<iPTR, 3, "SelectAddrMode1", [imm, sra, shl, srl],
36 //Addressing Mode 2: Load and Store Word or Unsigned Byte
37 def addr_mode2 : ComplexPattern<iPTR, 2, "SelectAddrMode2", [], []>;
39 //Addressing Mode 5: VFP load/store
40 def addr_mode5 : ComplexPattern<iPTR, 2, "SelectAddrMode5", [], []>;
42 //===----------------------------------------------------------------------===//
43 // Instruction Class Templates
44 //===----------------------------------------------------------------------===//
45 class InstARM<dag ops, string asmstr, list<dag> pattern> : Instruction {
46 let Namespace = "ARM";
48 dag OperandList = ops;
49 let AsmString = asmstr;
50 let Pattern = pattern;
53 class IntBinOp<string OpcStr, SDNode OpNode> :
54 InstARM<(ops IntRegs:$dst, IntRegs:$a, IntRegs:$b),
55 !strconcat(OpcStr, " $dst, $a, $b"),
56 [(set IntRegs:$dst, (OpNode IntRegs:$a, IntRegs:$b))]>;
58 class FPBinOp<string OpcStr, SDNode OpNode> :
59 InstARM<(ops FPRegs:$dst, FPRegs:$a, FPRegs:$b),
60 !strconcat(OpcStr, " $dst, $a, $b"),
61 [(set FPRegs:$dst, (OpNode FPRegs:$a, FPRegs:$b))]>;
63 class DFPBinOp<string OpcStr, SDNode OpNode> :
64 InstARM<(ops DFPRegs:$dst, DFPRegs:$a, DFPRegs:$b),
65 !strconcat(OpcStr, " $dst, $a, $b"),
66 [(set DFPRegs:$dst, (OpNode DFPRegs:$a, DFPRegs:$b))]>;
68 class FPUnaryOp<string OpcStr, SDNode OpNode> :
69 InstARM<(ops FPRegs:$dst, FPRegs:$src),
70 !strconcat(OpcStr, " $dst, $src"),
71 [(set FPRegs:$dst, (OpNode FPRegs:$src))]>;
73 class DFPUnaryOp<string OpcStr, SDNode OpNode> :
74 InstARM<(ops DFPRegs:$dst, DFPRegs:$src),
75 !strconcat(OpcStr, " $dst, $src"),
76 [(set DFPRegs:$dst, (OpNode DFPRegs:$src))]>;
78 class Addr1BinOp<string OpcStr, SDNode OpNode> :
79 InstARM<(ops IntRegs:$dst, IntRegs:$a, op_addr_mode1:$b),
80 !strconcat(OpcStr, " $dst, $a, $b"),
81 [(set IntRegs:$dst, (OpNode IntRegs:$a, addr_mode1:$b))]>;
83 //===----------------------------------------------------------------------===//
85 //===----------------------------------------------------------------------===//
87 def brtarget : Operand<OtherVT>;
89 // Operand for printing out a condition code.
90 let PrintMethod = "printCCOperand" in
91 def CCOp : Operand<i32>;
93 def SDT_ARMCallSeq : SDTypeProfile<0, 1, [ SDTCisVT<0, i32> ]>;
94 def callseq_start : SDNode<"ISD::CALLSEQ_START", SDT_ARMCallSeq,
95 [SDNPHasChain, SDNPOutFlag]>;
96 def callseq_end : SDNode<"ISD::CALLSEQ_END", SDT_ARMCallSeq,
97 [SDNPHasChain, SDNPOutFlag]>;
99 def SDT_ARMcall : SDTypeProfile<0, -1, [SDTCisInt<0>]>;
100 def ARMcall : SDNode<"ARMISD::CALL", SDT_ARMcall,
101 [SDNPHasChain, SDNPOptInFlag, SDNPOutFlag]>;
102 def retflag : SDNode<"ARMISD::RET_FLAG", SDTRet,
103 [SDNPHasChain, SDNPOptInFlag]>;
105 def SDTarmselect : SDTypeProfile<1, 3, [SDTCisSameAs<0, 1>, SDTCisSameAs<0, 2>, SDTCisInt<0>, SDTCisVT<2, i32>]>;
106 def armselect : SDNode<"ARMISD::SELECT", SDTarmselect, [SDNPInFlag, SDNPOutFlag]>;
108 def SDTarmfmstat : SDTypeProfile<0, 0, []>;
109 def armfmstat : SDNode<"ARMISD::FMSTAT", SDTarmfmstat, [SDNPInFlag, SDNPOutFlag]>;
111 def SDTarmbr : SDTypeProfile<0, 2, [SDTCisVT<0, OtherVT>, SDTCisVT<1, i32>]>;
112 def armbr : SDNode<"ARMISD::BR", SDTarmbr, [SDNPHasChain, SDNPInFlag]>;
114 def SDTVoidBinOp : SDTypeProfile<0, 2, [SDTCisSameAs<0, 1>]>;
115 def armcmp : SDNode<"ARMISD::CMP", SDTVoidBinOp, [SDNPOutFlag]>;
117 def armfsitos : SDNode<"ARMISD::FSITOS", SDTUnaryOp>;
118 def armftosis : SDNode<"ARMISD::FTOSIS", SDTUnaryOp>;
119 def armfsitod : SDNode<"ARMISD::FSITOD", SDTUnaryOp>;
120 def armftosid : SDNode<"ARMISD::FTOSID", SDTUnaryOp>;
121 def armfuitos : SDNode<"ARMISD::FUITOS", SDTUnaryOp>;
122 def armftouis : SDNode<"ARMISD::FTOUIS", SDTUnaryOp>;
123 def armfuitod : SDNode<"ARMISD::FUITOD", SDTUnaryOp>;
124 def armftouid : SDNode<"ARMISD::FTOUID", SDTUnaryOp>;
126 def SDTarmfmrrd : SDTypeProfile<0, 3, [SDTCisInt<0>, SDTCisInt<1>, SDTCisFP<2>]>;
127 def armfmrrd : SDNode<"ARMISD::FMRRD", SDTarmfmrrd,
128 [SDNPHasChain, SDNPOptInFlag, SDNPOutFlag]>;
130 def SDTarmfmdrr : SDTypeProfile<1, 2, [SDTCisFP<0>, SDTCisInt<1>, SDTCisInt<2>]>;
131 def armfmdrr : SDNode<"ARMISD::FMDRR", SDTarmfmdrr, []>;
133 def ADJCALLSTACKUP : InstARM<(ops i32imm:$amt),
134 "!ADJCALLSTACKUP $amt",
135 [(callseq_end imm:$amt)]>, Imp<[R13],[R13]>;
137 def ADJCALLSTACKDOWN : InstARM<(ops i32imm:$amt),
138 "!ADJCALLSTACKDOWN $amt",
139 [(callseq_start imm:$amt)]>, Imp<[R13],[R13]>;
141 def IMPLICIT_DEF_Int : InstARM<(ops IntRegs:$dst),
142 "@IMPLICIT_DEF $dst",
143 [(set IntRegs:$dst, (undef))]>;
144 def IMPLICIT_DEF_FP : InstARM<(ops FPRegs:$dst), "@IMPLICIT_DEF $dst",
145 [(set FPRegs:$dst, (undef))]>;
146 def IMPLICIT_DEF_DFP : InstARM<(ops DFPRegs:$dst), "@IMPLICIT_DEF $dst",
147 [(set DFPRegs:$dst, (undef))]>;
149 let isReturn = 1 in {
150 def bx: InstARM<(ops), "bx r14", [(retflag)]>;
153 let noResults = 1, Defs = [R0, R1, R2, R3, R14] in {
154 def bl: InstARM<(ops i32imm:$func, variable_ops), "bl $func", []>;
155 def blx : InstARM<(ops IntRegs:$func, variable_ops), "blx $func", [(ARMcall IntRegs:$func)]>;
158 def LDR : InstARM<(ops IntRegs:$dst, op_addr_mode2:$addr),
160 [(set IntRegs:$dst, (load addr_mode2:$addr))]>;
162 def LDRB : InstARM<(ops IntRegs:$dst, IntRegs:$addr),
163 "ldrb $dst, [$addr]",
164 [(set IntRegs:$dst, (zextloadi8 IntRegs:$addr))]>;
166 def LDRSB : InstARM<(ops IntRegs:$dst, IntRegs:$addr),
167 "ldrsb $dst, [$addr]",
168 [(set IntRegs:$dst, (sextloadi8 IntRegs:$addr))]>;
170 def LDRH : InstARM<(ops IntRegs:$dst, IntRegs:$addr),
171 "ldrh $dst, [$addr]",
172 [(set IntRegs:$dst, (zextloadi16 IntRegs:$addr))]>;
174 def LDRSH : InstARM<(ops IntRegs:$dst, IntRegs:$addr),
175 "ldrsh $dst, [$addr]",
176 [(set IntRegs:$dst, (sextloadi16 IntRegs:$addr))]>;
178 def STR : InstARM<(ops IntRegs:$src, op_addr_mode2:$addr),
180 [(store IntRegs:$src, addr_mode2:$addr)]>;
182 def STRB : InstARM<(ops IntRegs:$src, IntRegs:$addr),
183 "strb $src, [$addr]",
184 [(truncstorei8 IntRegs:$src, IntRegs:$addr)]>;
186 def STRH : InstARM<(ops IntRegs:$src, IntRegs:$addr),
187 "strh $src, [$addr]",
188 [(truncstorei16 IntRegs:$src, IntRegs:$addr)]>;
190 def MOV : InstARM<(ops IntRegs:$dst, op_addr_mode1:$src),
191 "mov $dst, $src", [(set IntRegs:$dst, addr_mode1:$src)]>;
193 def ADD : Addr1BinOp<"add", add>;
194 def ADCS : Addr1BinOp<"adcs", adde>;
195 def ADDS : Addr1BinOp<"adds", addc>;
196 def SUB : Addr1BinOp<"sub", sub>;
197 def SBCS : Addr1BinOp<"sbcs", sube>;
198 def SUBS : Addr1BinOp<"subs", subc>;
199 def AND : Addr1BinOp<"and", and>;
200 def EOR : Addr1BinOp<"eor", xor>;
201 def ORR : Addr1BinOp<"orr", or>;
203 let isTwoAddress = 1 in {
204 def movcond : InstARM<(ops IntRegs:$dst, IntRegs:$false,
205 op_addr_mode1:$true, CCOp:$cc),
206 "mov$cc $dst, $true",
207 [(set IntRegs:$dst, (armselect addr_mode1:$true,
208 IntRegs:$false, imm:$cc))]>;
211 def MUL : IntBinOp<"mul", mul>;
214 def SMULL : IntBinOp<"smull r12,", mulhs>;
215 def UMULL : IntBinOp<"umull r12,", mulhu>;
218 let isTerminator = 1, isBranch = 1 in {
219 def bcond : InstARM<(ops brtarget:$dst, CCOp:$cc),
221 [(armbr bb:$dst, imm:$cc)]>;
223 def b : InstARM<(ops brtarget:$dst),
228 def cmp : InstARM<(ops IntRegs:$a, op_addr_mode1:$b),
230 [(armcmp IntRegs:$a, addr_mode1:$b)]>;
232 // Floating Point Compare
233 def fcmps : InstARM<(ops FPRegs:$a, FPRegs:$b),
235 [(armcmp FPRegs:$a, FPRegs:$b)]>;
237 def fcmpd : InstARM<(ops DFPRegs:$a, DFPRegs:$b),
239 [(armcmp DFPRegs:$a, DFPRegs:$b)]>;
241 // Floating Point Copy
242 def FCPYS : InstARM<(ops FPRegs:$dst, FPRegs:$src), "fcpys $dst, $src", []>;
244 def FCPYD : InstARM<(ops DFPRegs:$dst, DFPRegs:$src), "fcpyd $dst, $src", []>;
246 // Floating Point Conversion
247 // We use bitconvert for moving the data between the register classes.
248 // The format conversion is done with ARM specific nodes
250 def FMSR : InstARM<(ops FPRegs:$dst, IntRegs:$src),
251 "fmsr $dst, $src", [(set FPRegs:$dst, (bitconvert IntRegs:$src))]>;
253 def FMRS : InstARM<(ops IntRegs:$dst, FPRegs:$src),
254 "fmrs $dst, $src", [(set IntRegs:$dst, (bitconvert FPRegs:$src))]>;
256 def FMRRD : InstARM<(ops IntRegs:$i0, IntRegs:$i1, DFPRegs:$src),
257 "fmrrd $i0, $i1, $src", [(armfmrrd IntRegs:$i0, IntRegs:$i1, DFPRegs:$src)]>;
259 def FMDRR : InstARM<(ops DFPRegs:$dst, IntRegs:$i0, IntRegs:$i1),
260 "fmdrr $dst, $i0, $i1", [(set DFPRegs:$dst, (armfmdrr IntRegs:$i0, IntRegs:$i1))]>;
262 def FSITOS : InstARM<(ops FPRegs:$dst, FPRegs:$src),
263 "fsitos $dst, $src", [(set FPRegs:$dst, (armfsitos FPRegs:$src))]>;
265 def FTOSIS : InstARM<(ops FPRegs:$dst, FPRegs:$src),
266 "ftosis $dst, $src", [(set FPRegs:$dst, (armftosis FPRegs:$src))]>;
268 def FSITOD : InstARM<(ops DFPRegs:$dst, FPRegs:$src),
269 "fsitod $dst, $src", [(set DFPRegs:$dst, (armfsitod FPRegs:$src))]>;
271 def FTOSID : InstARM<(ops FPRegs:$dst, DFPRegs:$src),
272 "ftosid $dst, $src", [(set FPRegs:$dst, (armftosid DFPRegs:$src))]>;
274 def FUITOS : InstARM<(ops FPRegs:$dst, FPRegs:$src),
275 "fuitos $dst, $src", [(set FPRegs:$dst, (armfuitos FPRegs:$src))]>;
277 def FTOUIS : InstARM<(ops FPRegs:$dst, FPRegs:$src),
278 "ftouis $dst, $src", [(set FPRegs:$dst, (armftouis FPRegs:$src))]>;
280 def FUITOD : InstARM<(ops DFPRegs:$dst, FPRegs:$src),
281 "fuitod $dst, $src", [(set DFPRegs:$dst, (armfuitod FPRegs:$src))]>;
283 def FTOUID : InstARM<(ops FPRegs:$dst, DFPRegs:$src),
284 "ftouid $dst, $src", [(set FPRegs:$dst, (armftouid DFPRegs:$src))]>;
286 def FCVTDS : InstARM<(ops DFPRegs:$dst, FPRegs:$src),
287 "fcvtds $dst, $src", [(set DFPRegs:$dst, (fextend FPRegs:$src))]>;
289 def FCVTSD : InstARM<(ops FPRegs:$dst, DFPRegs:$src),
290 "fcvtsd $dst, $src", [(set FPRegs:$dst, (fround DFPRegs:$src))]>;
292 def FMSTAT : InstARM<(ops ), "fmstat", [(armfmstat)]>;
294 // Floating Point Arithmetic
295 def FADDS : FPBinOp<"fadds", fadd>;
296 def FADDD : DFPBinOp<"faddd", fadd>;
297 def FSUBS : FPBinOp<"fsubs", fsub>;
298 def FSUBD : DFPBinOp<"fsubd", fsub>;
300 def FNEGS : FPUnaryOp<"fnegs", fneg>;
301 def FNEGD : DFPUnaryOp<"fnegd", fneg>;
302 def FABSS : FPUnaryOp<"fabss", fabs>;
303 def FABSD : DFPUnaryOp<"fabsd", fabs>;
305 def FMULS : FPBinOp<"fmuls", fmul>;
306 def FMULD : DFPBinOp<"fmuld", fmul>;
307 def FDIVS : FPBinOp<"fdivs", fdiv>;
308 def FDIVD : DFPBinOp<"fdivd", fdiv>;
310 // Floating Point Load
311 def FLDS : InstARM<(ops FPRegs:$dst, op_addr_mode5:$addr),
313 [(set FPRegs:$dst, (load addr_mode5:$addr))]>;
315 def FLDD : InstARM<(ops DFPRegs:$dst, op_addr_mode5:$addr),
317 [(set DFPRegs:$dst, (load addr_mode5:$addr))]>;
319 // Floating Point Store
320 def FSTS : InstARM<(ops FPRegs:$src, op_addr_mode5:$addr),
322 [(store FPRegs:$src, addr_mode5:$addr)]>;
324 def FSTD : InstARM<(ops DFPRegs:$src, op_addr_mode5:$addr),
326 [(store DFPRegs:$src, addr_mode5:$addr)]>;
328 def : Pat<(ARMcall tglobaladdr:$dst),
329 (bl tglobaladdr:$dst)>;
331 def : Pat<(ARMcall texternalsym:$dst),
332 (bl texternalsym:$dst)>;
334 def : Pat<(extloadi8 IntRegs:$addr),
335 (LDRB IntRegs:$addr)>;
336 def : Pat<(extloadi16 IntRegs:$addr),
337 (LDRH IntRegs:$addr)>;
339 // zextload bool -> zextload byte
340 def : Pat<(i32 (zextloadi1 IntRegs:$addr)), (LDRB IntRegs:$addr)>;
341 def : Pat<(i32 (zextloadi1 IntRegs:$addr)), (LDRB IntRegs:$addr)>;
343 // truncstore bool -> truncstore byte.
344 def : Pat<(truncstorei1 IntRegs:$src, IntRegs:$addr),
345 (STRB IntRegs:$addr, IntRegs:$src)>;
346 def : Pat<(truncstorei1 IntRegs:$src, IntRegs:$addr),
347 (STRB IntRegs:$addr, IntRegs:$src)>;