1 //===- ARMInstrInfo.td - Target Description for ARM Target -*- tablegen -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file describes the ARM instructions in TableGen format.
12 //===----------------------------------------------------------------------===//
14 //===----------------------------------------------------------------------===//
15 // ARM specific DAG Nodes.
19 def SDT_ARMCallSeqStart : SDCallSeqStart<[ SDTCisVT<0, i32> ]>;
20 def SDT_ARMCallSeqEnd : SDCallSeqEnd<[ SDTCisVT<0, i32>, SDTCisVT<1, i32> ]>;
22 def SDT_ARMSaveCallPC : SDTypeProfile<0, 1, []>;
24 def SDT_ARMcall : SDTypeProfile<0, -1, [SDTCisPtrTy<0>]>;
26 def SDT_ARMCMov : SDTypeProfile<1, 3,
27 [SDTCisSameAs<0, 1>, SDTCisSameAs<0, 2>,
30 def SDT_ARMBrcond : SDTypeProfile<0, 2,
31 [SDTCisVT<0, OtherVT>, SDTCisVT<1, i32>]>;
33 def SDT_ARMBrJT : SDTypeProfile<0, 3,
34 [SDTCisPtrTy<0>, SDTCisVT<1, i32>,
37 def SDT_ARMBr2JT : SDTypeProfile<0, 4,
38 [SDTCisPtrTy<0>, SDTCisVT<1, i32>,
39 SDTCisVT<2, i32>, SDTCisVT<3, i32>]>;
41 def SDT_ARMBCC_i64 : SDTypeProfile<0, 6,
43 SDTCisVT<1, i32>, SDTCisVT<2, i32>,
44 SDTCisVT<3, i32>, SDTCisVT<4, i32>,
45 SDTCisVT<5, OtherVT>]>;
47 def SDT_ARMAnd : SDTypeProfile<1, 2,
48 [SDTCisVT<0, i32>, SDTCisVT<1, i32>,
51 def SDT_ARMCmp : SDTypeProfile<0, 2, [SDTCisSameAs<0, 1>]>;
53 def SDT_ARMPICAdd : SDTypeProfile<1, 2, [SDTCisSameAs<0, 1>,
54 SDTCisPtrTy<1>, SDTCisVT<2, i32>]>;
56 def SDT_ARMThreadPointer : SDTypeProfile<1, 0, [SDTCisPtrTy<0>]>;
57 def SDT_ARMEH_SJLJ_Setjmp : SDTypeProfile<1, 2, [SDTCisInt<0>, SDTCisPtrTy<1>,
59 def SDT_ARMEH_SJLJ_Longjmp: SDTypeProfile<0, 2, [SDTCisPtrTy<0>, SDTCisInt<1>]>;
61 def SDT_ARMEH_SJLJ_DispatchSetup: SDTypeProfile<0, 1, [SDTCisPtrTy<0>]>;
63 def SDT_ARMMEMBARRIER : SDTypeProfile<0, 1, [SDTCisInt<0>]>;
65 def SDT_ARMTCRET : SDTypeProfile<0, 1, [SDTCisPtrTy<0>]>;
67 def SDT_ARMBFI : SDTypeProfile<1, 3, [SDTCisVT<0, i32>, SDTCisVT<1, i32>,
68 SDTCisVT<2, i32>, SDTCisVT<3, i32>]>;
71 def ARMWrapper : SDNode<"ARMISD::Wrapper", SDTIntUnaryOp>;
72 def ARMWrapperJT : SDNode<"ARMISD::WrapperJT", SDTIntBinOp>;
74 def ARMcallseq_start : SDNode<"ISD::CALLSEQ_START", SDT_ARMCallSeqStart,
75 [SDNPHasChain, SDNPOutFlag]>;
76 def ARMcallseq_end : SDNode<"ISD::CALLSEQ_END", SDT_ARMCallSeqEnd,
77 [SDNPHasChain, SDNPOptInFlag, SDNPOutFlag]>;
79 def ARMcall : SDNode<"ARMISD::CALL", SDT_ARMcall,
80 [SDNPHasChain, SDNPOptInFlag, SDNPOutFlag,
82 def ARMcall_pred : SDNode<"ARMISD::CALL_PRED", SDT_ARMcall,
83 [SDNPHasChain, SDNPOptInFlag, SDNPOutFlag,
85 def ARMcall_nolink : SDNode<"ARMISD::CALL_NOLINK", SDT_ARMcall,
86 [SDNPHasChain, SDNPOptInFlag, SDNPOutFlag,
89 def ARMretflag : SDNode<"ARMISD::RET_FLAG", SDTNone,
90 [SDNPHasChain, SDNPOptInFlag]>;
92 def ARMcmov : SDNode<"ARMISD::CMOV", SDT_ARMCMov,
94 def ARMcneg : SDNode<"ARMISD::CNEG", SDT_ARMCMov,
97 def ARMbrcond : SDNode<"ARMISD::BRCOND", SDT_ARMBrcond,
98 [SDNPHasChain, SDNPInFlag, SDNPOutFlag]>;
100 def ARMbrjt : SDNode<"ARMISD::BR_JT", SDT_ARMBrJT,
102 def ARMbr2jt : SDNode<"ARMISD::BR2_JT", SDT_ARMBr2JT,
105 def ARMBcci64 : SDNode<"ARMISD::BCC_i64", SDT_ARMBCC_i64,
108 def ARMcmp : SDNode<"ARMISD::CMP", SDT_ARMCmp,
111 def ARMcmpZ : SDNode<"ARMISD::CMPZ", SDT_ARMCmp,
112 [SDNPOutFlag, SDNPCommutative]>;
114 def ARMpic_add : SDNode<"ARMISD::PIC_ADD", SDT_ARMPICAdd>;
116 def ARMsrl_flag : SDNode<"ARMISD::SRL_FLAG", SDTIntUnaryOp, [SDNPOutFlag]>;
117 def ARMsra_flag : SDNode<"ARMISD::SRA_FLAG", SDTIntUnaryOp, [SDNPOutFlag]>;
118 def ARMrrx : SDNode<"ARMISD::RRX" , SDTIntUnaryOp, [SDNPInFlag ]>;
120 def ARMthread_pointer: SDNode<"ARMISD::THREAD_POINTER", SDT_ARMThreadPointer>;
121 def ARMeh_sjlj_setjmp: SDNode<"ARMISD::EH_SJLJ_SETJMP",
122 SDT_ARMEH_SJLJ_Setjmp, [SDNPHasChain]>;
123 def ARMeh_sjlj_longjmp: SDNode<"ARMISD::EH_SJLJ_LONGJMP",
124 SDT_ARMEH_SJLJ_Longjmp, [SDNPHasChain]>;
125 def ARMeh_sjlj_dispatchsetup: SDNode<"ARMISD::EH_SJLJ_DISPATCHSETUP",
126 SDT_ARMEH_SJLJ_DispatchSetup, [SDNPHasChain]>;
129 def ARMMemBarrier : SDNode<"ARMISD::MEMBARRIER", SDT_ARMMEMBARRIER,
131 def ARMMemBarrierMCR : SDNode<"ARMISD::MEMBARRIER_MCR", SDT_ARMMEMBARRIER,
133 def ARMPreload : SDNode<"ARMISD::PRELOAD", SDTPrefetch,
134 [SDNPHasChain, SDNPMayLoad, SDNPMayStore]>;
136 def ARMrbit : SDNode<"ARMISD::RBIT", SDTIntUnaryOp>;
138 def ARMtcret : SDNode<"ARMISD::TC_RETURN", SDT_ARMTCRET,
139 [SDNPHasChain, SDNPOptInFlag, SDNPVariadic]>;
142 def ARMbfi : SDNode<"ARMISD::BFI", SDT_ARMBFI>;
144 //===----------------------------------------------------------------------===//
145 // ARM Instruction Predicate Definitions.
147 def HasV4T : Predicate<"Subtarget->hasV4TOps()">, AssemblerPredicate;
148 def NoV4T : Predicate<"!Subtarget->hasV4TOps()">;
149 def HasV5T : Predicate<"Subtarget->hasV5TOps()">;
150 def HasV5TE : Predicate<"Subtarget->hasV5TEOps()">, AssemblerPredicate;
151 def HasV6 : Predicate<"Subtarget->hasV6Ops()">, AssemblerPredicate;
152 def HasV6T2 : Predicate<"Subtarget->hasV6T2Ops()">, AssemblerPredicate;
153 def NoV6T2 : Predicate<"!Subtarget->hasV6T2Ops()">;
154 def HasV7 : Predicate<"Subtarget->hasV7Ops()">, AssemblerPredicate;
155 def NoVFP : Predicate<"!Subtarget->hasVFP2()">;
156 def HasVFP2 : Predicate<"Subtarget->hasVFP2()">, AssemblerPredicate;
157 def HasVFP3 : Predicate<"Subtarget->hasVFP3()">, AssemblerPredicate;
158 def HasNEON : Predicate<"Subtarget->hasNEON()">, AssemblerPredicate;
159 def HasDivide : Predicate<"Subtarget->hasDivide()">, AssemblerPredicate;
160 def HasT2ExtractPack : Predicate<"Subtarget->hasT2ExtractPack()">,
162 def HasDB : Predicate<"Subtarget->hasDataBarrier()">,
164 def HasMP : Predicate<"Subtarget->hasMPExtension()">,
166 def UseNEONForFP : Predicate<"Subtarget->useNEONForSinglePrecisionFP()">;
167 def DontUseNEONForFP : Predicate<"!Subtarget->useNEONForSinglePrecisionFP()">;
168 def IsThumb : Predicate<"Subtarget->isThumb()">, AssemblerPredicate;
169 def IsThumb1Only : Predicate<"Subtarget->isThumb1Only()">;
170 def IsThumb2 : Predicate<"Subtarget->isThumb2()">, AssemblerPredicate;
171 def IsARM : Predicate<"!Subtarget->isThumb()">, AssemblerPredicate;
172 def IsDarwin : Predicate<"Subtarget->isTargetDarwin()">;
173 def IsNotDarwin : Predicate<"!Subtarget->isTargetDarwin()">;
175 // FIXME: Eventually this will be just "hasV6T2Ops".
176 def UseMovt : Predicate<"Subtarget->useMovt()">;
177 def DontUseMovt : Predicate<"!Subtarget->useMovt()">;
178 def UseFPVMLx : Predicate<"Subtarget->useFPVMLx()">;
180 //===----------------------------------------------------------------------===//
181 // ARM Flag Definitions.
183 class RegConstraint<string C> {
184 string Constraints = C;
187 //===----------------------------------------------------------------------===//
188 // ARM specific transformation functions and pattern fragments.
191 // so_imm_neg_XFORM - Return a so_imm value packed into the format described for
192 // so_imm_neg def below.
193 def so_imm_neg_XFORM : SDNodeXForm<imm, [{
194 return CurDAG->getTargetConstant(-(int)N->getZExtValue(), MVT::i32);
197 // so_imm_not_XFORM - Return a so_imm value packed into the format described for
198 // so_imm_not def below.
199 def so_imm_not_XFORM : SDNodeXForm<imm, [{
200 return CurDAG->getTargetConstant(~(int)N->getZExtValue(), MVT::i32);
203 /// imm1_15 predicate - True if the 32-bit immediate is in the range [1,15].
204 def imm1_15 : PatLeaf<(i32 imm), [{
205 return (int32_t)N->getZExtValue() >= 1 && (int32_t)N->getZExtValue() < 16;
208 /// imm16_31 predicate - True if the 32-bit immediate is in the range [16,31].
209 def imm16_31 : PatLeaf<(i32 imm), [{
210 return (int32_t)N->getZExtValue() >= 16 && (int32_t)N->getZExtValue() < 32;
215 return ARM_AM::getSOImmVal(-(uint32_t)N->getZExtValue()) != -1;
216 }], so_imm_neg_XFORM>;
220 return ARM_AM::getSOImmVal(~(uint32_t)N->getZExtValue()) != -1;
221 }], so_imm_not_XFORM>;
223 // sext_16_node predicate - True if the SDNode is sign-extended 16 or more bits.
224 def sext_16_node : PatLeaf<(i32 GPR:$a), [{
225 return CurDAG->ComputeNumSignBits(SDValue(N,0)) >= 17;
228 /// Split a 32-bit immediate into two 16 bit parts.
229 def hi16 : SDNodeXForm<imm, [{
230 return CurDAG->getTargetConstant((uint32_t)N->getZExtValue() >> 16, MVT::i32);
233 def lo16AllZero : PatLeaf<(i32 imm), [{
234 // Returns true if all low 16-bits are 0.
235 return (((uint32_t)N->getZExtValue()) & 0xFFFFUL) == 0;
238 /// imm0_65535 predicate - True if the 32-bit immediate is in the range
240 def imm0_65535 : PatLeaf<(i32 imm), [{
241 return (uint32_t)N->getZExtValue() < 65536;
244 class BinOpFrag<dag res> : PatFrag<(ops node:$LHS, node:$RHS), res>;
245 class UnOpFrag <dag res> : PatFrag<(ops node:$Src), res>;
247 /// adde and sube predicates - True based on whether the carry flag output
248 /// will be needed or not.
249 def adde_dead_carry :
250 PatFrag<(ops node:$LHS, node:$RHS), (adde node:$LHS, node:$RHS),
251 [{return !N->hasAnyUseOfValue(1);}]>;
252 def sube_dead_carry :
253 PatFrag<(ops node:$LHS, node:$RHS), (sube node:$LHS, node:$RHS),
254 [{return !N->hasAnyUseOfValue(1);}]>;
255 def adde_live_carry :
256 PatFrag<(ops node:$LHS, node:$RHS), (adde node:$LHS, node:$RHS),
257 [{return N->hasAnyUseOfValue(1);}]>;
258 def sube_live_carry :
259 PatFrag<(ops node:$LHS, node:$RHS), (sube node:$LHS, node:$RHS),
260 [{return N->hasAnyUseOfValue(1);}]>;
262 // An 'and' node with a single use.
263 def and_su : PatFrag<(ops node:$lhs, node:$rhs), (and node:$lhs, node:$rhs), [{
264 return N->hasOneUse();
267 // An 'xor' node with a single use.
268 def xor_su : PatFrag<(ops node:$lhs, node:$rhs), (xor node:$lhs, node:$rhs), [{
269 return N->hasOneUse();
272 // An 'fmul' node with a single use.
273 def fmul_su : PatFrag<(ops node:$lhs, node:$rhs), (fmul node:$lhs, node:$rhs),[{
274 return N->hasOneUse();
277 // An 'fadd' node which checks for single non-hazardous use.
278 def fadd_mlx : PatFrag<(ops node:$lhs, node:$rhs),(fadd node:$lhs, node:$rhs),[{
279 return hasNoVMLxHazardUse(N);
282 // An 'fsub' node which checks for single non-hazardous use.
283 def fsub_mlx : PatFrag<(ops node:$lhs, node:$rhs),(fsub node:$lhs, node:$rhs),[{
284 return hasNoVMLxHazardUse(N);
287 //===----------------------------------------------------------------------===//
288 // Operand Definitions.
292 def brtarget : Operand<OtherVT> {
293 let EncoderMethod = "getBranchTargetOpValue";
297 def bltarget : Operand<i32> {
298 // Encoded the same as branch targets.
299 let EncoderMethod = "getBranchTargetOpValue";
302 // A list of registers separated by comma. Used by load/store multiple.
303 def RegListAsmOperand : AsmOperandClass {
304 let Name = "RegList";
305 let SuperClasses = [];
308 def DPRRegListAsmOperand : AsmOperandClass {
309 let Name = "DPRRegList";
310 let SuperClasses = [];
313 def SPRRegListAsmOperand : AsmOperandClass {
314 let Name = "SPRRegList";
315 let SuperClasses = [];
318 def reglist : Operand<i32> {
319 let EncoderMethod = "getRegisterListOpValue";
320 let ParserMatchClass = RegListAsmOperand;
321 let PrintMethod = "printRegisterList";
324 def dpr_reglist : Operand<i32> {
325 let EncoderMethod = "getRegisterListOpValue";
326 let ParserMatchClass = DPRRegListAsmOperand;
327 let PrintMethod = "printRegisterList";
330 def spr_reglist : Operand<i32> {
331 let EncoderMethod = "getRegisterListOpValue";
332 let ParserMatchClass = SPRRegListAsmOperand;
333 let PrintMethod = "printRegisterList";
336 // An operand for the CONSTPOOL_ENTRY pseudo-instruction.
337 def cpinst_operand : Operand<i32> {
338 let PrintMethod = "printCPInstOperand";
342 def pclabel : Operand<i32> {
343 let PrintMethod = "printPCLabel";
346 // ADR instruction labels.
347 def adrlabel : Operand<i32> {
348 let EncoderMethod = "getAdrLabelOpValue";
351 def neon_vcvt_imm32 : Operand<i32> {
352 let EncoderMethod = "getNEONVcvtImm32OpValue";
355 // rot_imm: An integer that encodes a rotate amount. Must be 8, 16, or 24.
356 def rot_imm : Operand<i32>, PatLeaf<(i32 imm), [{
357 int32_t v = (int32_t)N->getZExtValue();
358 return v == 8 || v == 16 || v == 24; }]> {
359 let EncoderMethod = "getRotImmOpValue";
362 // shift_imm: An integer that encodes a shift amount and the type of shift
363 // (currently either asr or lsl) using the same encoding used for the
364 // immediates in so_reg operands.
365 def shift_imm : Operand<i32> {
366 let PrintMethod = "printShiftImmOperand";
369 // shifter_operand operands: so_reg and so_imm.
370 def so_reg : Operand<i32>, // reg reg imm
371 ComplexPattern<i32, 3, "SelectShifterOperandReg",
372 [shl,srl,sra,rotr]> {
373 let EncoderMethod = "getSORegOpValue";
374 let PrintMethod = "printSORegOperand";
375 let MIOperandInfo = (ops GPR, GPR, i32imm);
377 def shift_so_reg : Operand<i32>, // reg reg imm
378 ComplexPattern<i32, 3, "SelectShiftShifterOperandReg",
379 [shl,srl,sra,rotr]> {
380 let EncoderMethod = "getSORegOpValue";
381 let PrintMethod = "printSORegOperand";
382 let MIOperandInfo = (ops GPR, GPR, i32imm);
385 // so_imm - Match a 32-bit shifter_operand immediate operand, which is an
386 // 8-bit immediate rotated by an arbitrary number of bits. so_imm values are
387 // represented in the imm field in the same 12-bit form that they are encoded
388 // into so_imm instructions: the 8-bit immediate is the least significant bits
389 // [bits 0-7], the 4-bit shift amount is the next 4 bits [bits 8-11].
390 def so_imm : Operand<i32>, PatLeaf<(imm), [{ return Pred_so_imm(N); }]> {
391 let EncoderMethod = "getSOImmOpValue";
392 let PrintMethod = "printSOImmOperand";
395 // Break so_imm's up into two pieces. This handles immediates with up to 16
396 // bits set in them. This uses so_imm2part to match and so_imm2part_[12] to
397 // get the first/second pieces.
398 def so_imm2part : PatLeaf<(imm), [{
399 return ARM_AM::isSOImmTwoPartVal((unsigned)N->getZExtValue());
402 /// arm_i32imm - True for +V6T2, or true only if so_imm2part is true.
404 def arm_i32imm : PatLeaf<(imm), [{
405 if (Subtarget->hasV6T2Ops())
407 return ARM_AM::isSOImmTwoPartVal((unsigned)N->getZExtValue());
410 def so_imm2part_1 : SDNodeXForm<imm, [{
411 unsigned V = ARM_AM::getSOImmTwoPartFirst((unsigned)N->getZExtValue());
412 return CurDAG->getTargetConstant(V, MVT::i32);
415 def so_imm2part_2 : SDNodeXForm<imm, [{
416 unsigned V = ARM_AM::getSOImmTwoPartSecond((unsigned)N->getZExtValue());
417 return CurDAG->getTargetConstant(V, MVT::i32);
420 def so_neg_imm2part : Operand<i32>, PatLeaf<(imm), [{
421 return ARM_AM::isSOImmTwoPartVal(-(int)N->getZExtValue());
423 let PrintMethod = "printSOImm2PartOperand";
426 def so_neg_imm2part_1 : SDNodeXForm<imm, [{
427 unsigned V = ARM_AM::getSOImmTwoPartFirst(-(int)N->getZExtValue());
428 return CurDAG->getTargetConstant(V, MVT::i32);
431 def so_neg_imm2part_2 : SDNodeXForm<imm, [{
432 unsigned V = ARM_AM::getSOImmTwoPartSecond(-(int)N->getZExtValue());
433 return CurDAG->getTargetConstant(V, MVT::i32);
436 /// imm0_31 predicate - True if the 32-bit immediate is in the range [0,31].
437 def imm0_31 : Operand<i32>, PatLeaf<(imm), [{
438 return (int32_t)N->getZExtValue() < 32;
441 /// imm0_31_m1 - Matches and prints like imm0_31, but encodes as 'value - 1'.
442 def imm0_31_m1 : Operand<i32>, PatLeaf<(imm), [{
443 return (int32_t)N->getZExtValue() < 32;
445 let EncoderMethod = "getImmMinusOneOpValue";
448 // For movt/movw - sets the MC Encoder method.
449 // The imm is split into imm{15-12}, imm{11-0}
451 def movt_imm : Operand<i32> {
452 let EncoderMethod = "getMovtImmOpValue";
455 /// bf_inv_mask_imm predicate - An AND mask to clear an arbitrary width bitfield
457 def bf_inv_mask_imm : Operand<i32>,
459 return ARM::isBitFieldInvertedMask(N->getZExtValue());
461 let EncoderMethod = "getBitfieldInvertedMaskOpValue";
462 let PrintMethod = "printBitfieldInvMaskImmOperand";
465 // Define ARM specific addressing modes.
468 // addrmode_imm12 := reg +/- imm12
470 def addrmode_imm12 : Operand<i32>,
471 ComplexPattern<i32, 2, "SelectAddrModeImm12", []> {
472 // 12-bit immediate operand. Note that instructions using this encode
473 // #0 and #-0 differently. We flag #-0 as the magic value INT32_MIN. All other
474 // immediate values are as normal.
476 let EncoderMethod = "getAddrModeImm12OpValue";
477 let PrintMethod = "printAddrModeImm12Operand";
478 let MIOperandInfo = (ops GPR:$base, i32imm:$offsimm);
480 // ldst_so_reg := reg +/- reg shop imm
482 def ldst_so_reg : Operand<i32>,
483 ComplexPattern<i32, 3, "SelectLdStSOReg", []> {
484 let EncoderMethod = "getLdStSORegOpValue";
485 // FIXME: Simplify the printer
486 let PrintMethod = "printAddrMode2Operand";
487 let MIOperandInfo = (ops GPR:$base, GPR:$offsreg, i32imm:$offsimm);
490 // addrmode2 := reg +/- imm12
491 // := reg +/- reg shop imm
493 def addrmode2 : Operand<i32>,
494 ComplexPattern<i32, 3, "SelectAddrMode2", []> {
495 let EncoderMethod = "getAddrMode2OpValue";
496 let PrintMethod = "printAddrMode2Operand";
497 let MIOperandInfo = (ops GPR:$base, GPR:$offsreg, i32imm:$offsimm);
500 def am2offset : Operand<i32>,
501 ComplexPattern<i32, 2, "SelectAddrMode2Offset",
502 [], [SDNPWantRoot]> {
503 let EncoderMethod = "getAddrMode2OffsetOpValue";
504 let PrintMethod = "printAddrMode2OffsetOperand";
505 let MIOperandInfo = (ops GPR, i32imm);
508 // addrmode3 := reg +/- reg
509 // addrmode3 := reg +/- imm8
511 def addrmode3 : Operand<i32>,
512 ComplexPattern<i32, 3, "SelectAddrMode3", []> {
513 let EncoderMethod = "getAddrMode3OpValue";
514 let PrintMethod = "printAddrMode3Operand";
515 let MIOperandInfo = (ops GPR:$base, GPR:$offsreg, i32imm:$offsimm);
518 def am3offset : Operand<i32>,
519 ComplexPattern<i32, 2, "SelectAddrMode3Offset",
520 [], [SDNPWantRoot]> {
521 let EncoderMethod = "getAddrMode3OffsetOpValue";
522 let PrintMethod = "printAddrMode3OffsetOperand";
523 let MIOperandInfo = (ops GPR, i32imm);
526 // ldstm_mode := {ia, ib, da, db}
528 def ldstm_mode : OptionalDefOperand<OtherVT, (ops i32), (ops (i32 1))> {
529 let EncoderMethod = "getLdStmModeOpValue";
530 let PrintMethod = "printLdStmModeOperand";
533 def MemMode5AsmOperand : AsmOperandClass {
534 let Name = "MemMode5";
535 let SuperClasses = [];
538 // addrmode5 := reg +/- imm8*4
540 def addrmode5 : Operand<i32>,
541 ComplexPattern<i32, 2, "SelectAddrMode5", []> {
542 let PrintMethod = "printAddrMode5Operand";
543 let MIOperandInfo = (ops GPR:$base, i32imm);
544 let ParserMatchClass = MemMode5AsmOperand;
545 let EncoderMethod = "getAddrMode5OpValue";
548 // addrmode6 := reg with optional writeback
550 def addrmode6 : Operand<i32>,
551 ComplexPattern<i32, 2, "SelectAddrMode6", [], [SDNPWantParent]>{
552 let PrintMethod = "printAddrMode6Operand";
553 let MIOperandInfo = (ops GPR:$addr, i32imm);
554 let EncoderMethod = "getAddrMode6AddressOpValue";
557 def am6offset : Operand<i32> {
558 let PrintMethod = "printAddrMode6OffsetOperand";
559 let MIOperandInfo = (ops GPR);
560 let EncoderMethod = "getAddrMode6OffsetOpValue";
563 // Special version of addrmode6 to handle alignment encoding for VLD-dup
564 // instructions, specifically VLD4-dup.
565 def addrmode6dup : Operand<i32>,
566 ComplexPattern<i32, 2, "SelectAddrMode6", [], [SDNPWantParent]>{
567 let PrintMethod = "printAddrMode6Operand";
568 let MIOperandInfo = (ops GPR:$addr, i32imm);
569 let EncoderMethod = "getAddrMode6DupAddressOpValue";
572 // addrmodepc := pc + reg
574 def addrmodepc : Operand<i32>,
575 ComplexPattern<i32, 2, "SelectAddrModePC", []> {
576 let PrintMethod = "printAddrModePCOperand";
577 let MIOperandInfo = (ops GPR, i32imm);
580 def nohash_imm : Operand<i32> {
581 let PrintMethod = "printNoHashImmediate";
584 //===----------------------------------------------------------------------===//
586 include "ARMInstrFormats.td"
588 //===----------------------------------------------------------------------===//
589 // Multiclass helpers...
592 /// AsI1_bin_irs - Defines a set of (op r, {so_imm|r|so_reg}) patterns for a
593 /// binop that produces a value.
594 multiclass AsI1_bin_irs<bits<4> opcod, string opc,
595 InstrItinClass iii, InstrItinClass iir, InstrItinClass iis,
596 PatFrag opnode, bit Commutable = 0> {
597 // The register-immediate version is re-materializable. This is useful
598 // in particular for taking the address of a local.
599 let isReMaterializable = 1 in {
600 def ri : AsI1<opcod, (outs GPR:$Rd), (ins GPR:$Rn, so_imm:$imm), DPFrm,
601 iii, opc, "\t$Rd, $Rn, $imm",
602 [(set GPR:$Rd, (opnode GPR:$Rn, so_imm:$imm))]> {
607 let Inst{19-16} = Rn;
608 let Inst{15-12} = Rd;
609 let Inst{11-0} = imm;
612 def rr : AsI1<opcod, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm), DPFrm,
613 iir, opc, "\t$Rd, $Rn, $Rm",
614 [(set GPR:$Rd, (opnode GPR:$Rn, GPR:$Rm))]> {
619 let isCommutable = Commutable;
620 let Inst{19-16} = Rn;
621 let Inst{15-12} = Rd;
622 let Inst{11-4} = 0b00000000;
625 def rs : AsI1<opcod, (outs GPR:$Rd), (ins GPR:$Rn, so_reg:$shift), DPSoRegFrm,
626 iis, opc, "\t$Rd, $Rn, $shift",
627 [(set GPR:$Rd, (opnode GPR:$Rn, so_reg:$shift))]> {
632 let Inst{19-16} = Rn;
633 let Inst{15-12} = Rd;
634 let Inst{11-0} = shift;
638 /// AI1_bin_s_irs - Similar to AsI1_bin_irs except it sets the 's' bit so the
639 /// instruction modifies the CPSR register.
640 let Defs = [CPSR] in {
641 multiclass AI1_bin_s_irs<bits<4> opcod, string opc,
642 InstrItinClass iii, InstrItinClass iir, InstrItinClass iis,
643 PatFrag opnode, bit Commutable = 0> {
644 def ri : AI1<opcod, (outs GPR:$Rd), (ins GPR:$Rn, so_imm:$imm), DPFrm,
645 iii, opc, "\t$Rd, $Rn, $imm",
646 [(set GPR:$Rd, (opnode GPR:$Rn, so_imm:$imm))]> {
652 let Inst{19-16} = Rn;
653 let Inst{15-12} = Rd;
654 let Inst{11-0} = imm;
656 def rr : AI1<opcod, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm), DPFrm,
657 iir, opc, "\t$Rd, $Rn, $Rm",
658 [(set GPR:$Rd, (opnode GPR:$Rn, GPR:$Rm))]> {
662 let isCommutable = Commutable;
665 let Inst{19-16} = Rn;
666 let Inst{15-12} = Rd;
667 let Inst{11-4} = 0b00000000;
670 def rs : AI1<opcod, (outs GPR:$Rd), (ins GPR:$Rn, so_reg:$shift), DPSoRegFrm,
671 iis, opc, "\t$Rd, $Rn, $shift",
672 [(set GPR:$Rd, (opnode GPR:$Rn, so_reg:$shift))]> {
678 let Inst{19-16} = Rn;
679 let Inst{15-12} = Rd;
680 let Inst{11-0} = shift;
685 /// AI1_cmp_irs - Defines a set of (op r, {so_imm|r|so_reg}) cmp / test
686 /// patterns. Similar to AsI1_bin_irs except the instruction does not produce
687 /// a explicit result, only implicitly set CPSR.
688 let isCompare = 1, Defs = [CPSR] in {
689 multiclass AI1_cmp_irs<bits<4> opcod, string opc,
690 InstrItinClass iii, InstrItinClass iir, InstrItinClass iis,
691 PatFrag opnode, bit Commutable = 0> {
692 def ri : AI1<opcod, (outs), (ins GPR:$Rn, so_imm:$imm), DPFrm, iii,
694 [(opnode GPR:$Rn, so_imm:$imm)]> {
699 let Inst{19-16} = Rn;
700 let Inst{15-12} = 0b0000;
701 let Inst{11-0} = imm;
703 def rr : AI1<opcod, (outs), (ins GPR:$Rn, GPR:$Rm), DPFrm, iir,
705 [(opnode GPR:$Rn, GPR:$Rm)]> {
708 let isCommutable = Commutable;
711 let Inst{19-16} = Rn;
712 let Inst{15-12} = 0b0000;
713 let Inst{11-4} = 0b00000000;
716 def rs : AI1<opcod, (outs), (ins GPR:$Rn, so_reg:$shift), DPSoRegFrm, iis,
717 opc, "\t$Rn, $shift",
718 [(opnode GPR:$Rn, so_reg:$shift)]> {
723 let Inst{19-16} = Rn;
724 let Inst{15-12} = 0b0000;
725 let Inst{11-0} = shift;
730 /// AI_ext_rrot - A unary operation with two forms: one whose operand is a
731 /// register and one whose operand is a register rotated by 8/16/24.
732 /// FIXME: Remove the 'r' variant. Its rot_imm is zero.
733 multiclass AI_ext_rrot<bits<8> opcod, string opc, PatFrag opnode> {
734 def r : AExtI<opcod, (outs GPR:$Rd), (ins GPR:$Rm),
735 IIC_iEXTr, opc, "\t$Rd, $Rm",
736 [(set GPR:$Rd, (opnode GPR:$Rm))]>,
737 Requires<[IsARM, HasV6]> {
740 let Inst{19-16} = 0b1111;
741 let Inst{15-12} = Rd;
742 let Inst{11-10} = 0b00;
745 def r_rot : AExtI<opcod, (outs GPR:$Rd), (ins GPR:$Rm, rot_imm:$rot),
746 IIC_iEXTr, opc, "\t$Rd, $Rm, ror $rot",
747 [(set GPR:$Rd, (opnode (rotr GPR:$Rm, rot_imm:$rot)))]>,
748 Requires<[IsARM, HasV6]> {
752 let Inst{19-16} = 0b1111;
753 let Inst{15-12} = Rd;
754 let Inst{11-10} = rot;
759 multiclass AI_ext_rrot_np<bits<8> opcod, string opc> {
760 def r : AExtI<opcod, (outs GPR:$Rd), (ins GPR:$Rm),
761 IIC_iEXTr, opc, "\t$Rd, $Rm",
762 [/* For disassembly only; pattern left blank */]>,
763 Requires<[IsARM, HasV6]> {
764 let Inst{19-16} = 0b1111;
765 let Inst{11-10} = 0b00;
767 def r_rot : AExtI<opcod, (outs GPR:$Rd), (ins GPR:$Rm, rot_imm:$rot),
768 IIC_iEXTr, opc, "\t$Rd, $Rm, ror $rot",
769 [/* For disassembly only; pattern left blank */]>,
770 Requires<[IsARM, HasV6]> {
772 let Inst{19-16} = 0b1111;
773 let Inst{11-10} = rot;
777 /// AI_exta_rrot - A binary operation with two forms: one whose operand is a
778 /// register and one whose operand is a register rotated by 8/16/24.
779 multiclass AI_exta_rrot<bits<8> opcod, string opc, PatFrag opnode> {
780 def rr : AExtI<opcod, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm),
781 IIC_iEXTAr, opc, "\t$Rd, $Rn, $Rm",
782 [(set GPR:$Rd, (opnode GPR:$Rn, GPR:$Rm))]>,
783 Requires<[IsARM, HasV6]> {
787 let Inst{19-16} = Rn;
788 let Inst{15-12} = Rd;
789 let Inst{11-10} = 0b00;
790 let Inst{9-4} = 0b000111;
793 def rr_rot : AExtI<opcod, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm,
795 IIC_iEXTAr, opc, "\t$Rd, $Rn, $Rm, ror $rot",
796 [(set GPR:$Rd, (opnode GPR:$Rn,
797 (rotr GPR:$Rm, rot_imm:$rot)))]>,
798 Requires<[IsARM, HasV6]> {
803 let Inst{19-16} = Rn;
804 let Inst{15-12} = Rd;
805 let Inst{11-10} = rot;
806 let Inst{9-4} = 0b000111;
811 // For disassembly only.
812 multiclass AI_exta_rrot_np<bits<8> opcod, string opc> {
813 def rr : AExtI<opcod, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm),
814 IIC_iEXTAr, opc, "\t$Rd, $Rn, $Rm",
815 [/* For disassembly only; pattern left blank */]>,
816 Requires<[IsARM, HasV6]> {
817 let Inst{11-10} = 0b00;
819 def rr_rot : AExtI<opcod, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm,
821 IIC_iEXTAr, opc, "\t$Rd, $Rn, $Rm, ror $rot",
822 [/* For disassembly only; pattern left blank */]>,
823 Requires<[IsARM, HasV6]> {
826 let Inst{19-16} = Rn;
827 let Inst{11-10} = rot;
831 /// AI1_adde_sube_irs - Define instructions and patterns for adde and sube.
832 let Uses = [CPSR] in {
833 multiclass AI1_adde_sube_irs<bits<4> opcod, string opc, PatFrag opnode,
834 bit Commutable = 0> {
835 def ri : AsI1<opcod, (outs GPR:$Rd), (ins GPR:$Rn, so_imm:$imm),
836 DPFrm, IIC_iALUi, opc, "\t$Rd, $Rn, $imm",
837 [(set GPR:$Rd, (opnode GPR:$Rn, so_imm:$imm))]>,
843 let Inst{15-12} = Rd;
844 let Inst{19-16} = Rn;
845 let Inst{11-0} = imm;
847 def rr : AsI1<opcod, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm),
848 DPFrm, IIC_iALUr, opc, "\t$Rd, $Rn, $Rm",
849 [(set GPR:$Rd, (opnode GPR:$Rn, GPR:$Rm))]>,
854 let Inst{11-4} = 0b00000000;
856 let isCommutable = Commutable;
858 let Inst{15-12} = Rd;
859 let Inst{19-16} = Rn;
861 def rs : AsI1<opcod, (outs GPR:$Rd), (ins GPR:$Rn, so_reg:$shift),
862 DPSoRegFrm, IIC_iALUsr, opc, "\t$Rd, $Rn, $shift",
863 [(set GPR:$Rd, (opnode GPR:$Rn, so_reg:$shift))]>,
869 let Inst{11-0} = shift;
870 let Inst{15-12} = Rd;
871 let Inst{19-16} = Rn;
874 // Carry setting variants
875 let Defs = [CPSR] in {
876 multiclass AI1_adde_sube_s_irs<bits<4> opcod, string opc, PatFrag opnode,
877 bit Commutable = 0> {
878 def Sri : AXI1<opcod, (outs GPR:$Rd), (ins GPR:$Rn, so_imm:$imm),
879 DPFrm, IIC_iALUi, !strconcat(opc, "\t$Rd, $Rn, $imm"),
880 [(set GPR:$Rd, (opnode GPR:$Rn, so_imm:$imm))]>,
885 let Inst{15-12} = Rd;
886 let Inst{19-16} = Rn;
887 let Inst{11-0} = imm;
891 def Srr : AXI1<opcod, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm),
892 DPFrm, IIC_iALUr, !strconcat(opc, "\t$Rd, $Rn, $Rm"),
893 [(set GPR:$Rd, (opnode GPR:$Rn, GPR:$Rm))]>,
898 let Inst{11-4} = 0b00000000;
899 let isCommutable = Commutable;
901 let Inst{15-12} = Rd;
902 let Inst{19-16} = Rn;
906 def Srs : AXI1<opcod, (outs GPR:$Rd), (ins GPR:$Rn, so_reg:$shift),
907 DPSoRegFrm, IIC_iALUsr, !strconcat(opc, "\t$Rd, $Rn, $shift"),
908 [(set GPR:$Rd, (opnode GPR:$Rn, so_reg:$shift))]>,
913 let Inst{11-0} = shift;
914 let Inst{15-12} = Rd;
915 let Inst{19-16} = Rn;
923 let canFoldAsLoad = 1, isReMaterializable = 1 in {
924 multiclass AI_ldr1<bit isByte, string opc, InstrItinClass iii,
925 InstrItinClass iir, PatFrag opnode> {
926 // Note: We use the complex addrmode_imm12 rather than just an input
927 // GPR and a constrained immediate so that we can use this to match
928 // frame index references and avoid matching constant pool references.
929 def i12: AI2ldst<0b010, 1, isByte, (outs GPR:$Rt), (ins addrmode_imm12:$addr),
930 AddrMode_i12, LdFrm, iii, opc, "\t$Rt, $addr",
931 [(set GPR:$Rt, (opnode addrmode_imm12:$addr))]> {
934 let Inst{23} = addr{12}; // U (add = ('U' == 1))
935 let Inst{19-16} = addr{16-13}; // Rn
936 let Inst{15-12} = Rt;
937 let Inst{11-0} = addr{11-0}; // imm12
939 def rs : AI2ldst<0b011, 1, isByte, (outs GPR:$Rt), (ins ldst_so_reg:$shift),
940 AddrModeNone, LdFrm, iir, opc, "\t$Rt, $shift",
941 [(set GPR:$Rt, (opnode ldst_so_reg:$shift))]> {
944 let Inst{23} = shift{12}; // U (add = ('U' == 1))
945 let Inst{19-16} = shift{16-13}; // Rn
946 let Inst{15-12} = Rt;
947 let Inst{11-0} = shift{11-0};
952 multiclass AI_str1<bit isByte, string opc, InstrItinClass iii,
953 InstrItinClass iir, PatFrag opnode> {
954 // Note: We use the complex addrmode_imm12 rather than just an input
955 // GPR and a constrained immediate so that we can use this to match
956 // frame index references and avoid matching constant pool references.
957 def i12 : AI2ldst<0b010, 0, isByte, (outs),
958 (ins GPR:$Rt, addrmode_imm12:$addr),
959 AddrMode_i12, StFrm, iii, opc, "\t$Rt, $addr",
960 [(opnode GPR:$Rt, addrmode_imm12:$addr)]> {
963 let Inst{23} = addr{12}; // U (add = ('U' == 1))
964 let Inst{19-16} = addr{16-13}; // Rn
965 let Inst{15-12} = Rt;
966 let Inst{11-0} = addr{11-0}; // imm12
968 def rs : AI2ldst<0b011, 0, isByte, (outs), (ins GPR:$Rt, ldst_so_reg:$shift),
969 AddrModeNone, StFrm, iir, opc, "\t$Rt, $shift",
970 [(opnode GPR:$Rt, ldst_so_reg:$shift)]> {
973 let Inst{23} = shift{12}; // U (add = ('U' == 1))
974 let Inst{19-16} = shift{16-13}; // Rn
975 let Inst{15-12} = Rt;
976 let Inst{11-0} = shift{11-0};
979 //===----------------------------------------------------------------------===//
981 //===----------------------------------------------------------------------===//
983 //===----------------------------------------------------------------------===//
984 // Miscellaneous Instructions.
987 /// CONSTPOOL_ENTRY - This instruction represents a floating constant pool in
988 /// the function. The first operand is the ID# for this instruction, the second
989 /// is the index into the MachineConstantPool that this is, the third is the
990 /// size in bytes of this constant pool entry.
991 let neverHasSideEffects = 1, isNotDuplicable = 1 in
992 def CONSTPOOL_ENTRY :
993 PseudoInst<(outs), (ins cpinst_operand:$instid, cpinst_operand:$cpidx,
994 i32imm:$size), NoItinerary, []>;
996 // FIXME: Marking these as hasSideEffects is necessary to prevent machine DCE
997 // from removing one half of the matched pairs. That breaks PEI, which assumes
998 // these will always be in pairs, and asserts if it finds otherwise. Better way?
999 let Defs = [SP], Uses = [SP], hasSideEffects = 1 in {
1000 def ADJCALLSTACKUP :
1001 PseudoInst<(outs), (ins i32imm:$amt1, i32imm:$amt2, pred:$p), NoItinerary,
1002 [(ARMcallseq_end timm:$amt1, timm:$amt2)]>;
1004 def ADJCALLSTACKDOWN :
1005 PseudoInst<(outs), (ins i32imm:$amt, pred:$p), NoItinerary,
1006 [(ARMcallseq_start timm:$amt)]>;
1009 def NOP : AI<(outs), (ins), MiscFrm, NoItinerary, "nop", "",
1010 [/* For disassembly only; pattern left blank */]>,
1011 Requires<[IsARM, HasV6T2]> {
1012 let Inst{27-16} = 0b001100100000;
1013 let Inst{15-8} = 0b11110000;
1014 let Inst{7-0} = 0b00000000;
1017 def YIELD : AI<(outs), (ins), MiscFrm, NoItinerary, "yield", "",
1018 [/* For disassembly only; pattern left blank */]>,
1019 Requires<[IsARM, HasV6T2]> {
1020 let Inst{27-16} = 0b001100100000;
1021 let Inst{15-8} = 0b11110000;
1022 let Inst{7-0} = 0b00000001;
1025 def WFE : AI<(outs), (ins), MiscFrm, NoItinerary, "wfe", "",
1026 [/* For disassembly only; pattern left blank */]>,
1027 Requires<[IsARM, HasV6T2]> {
1028 let Inst{27-16} = 0b001100100000;
1029 let Inst{15-8} = 0b11110000;
1030 let Inst{7-0} = 0b00000010;
1033 def WFI : AI<(outs), (ins), MiscFrm, NoItinerary, "wfi", "",
1034 [/* For disassembly only; pattern left blank */]>,
1035 Requires<[IsARM, HasV6T2]> {
1036 let Inst{27-16} = 0b001100100000;
1037 let Inst{15-8} = 0b11110000;
1038 let Inst{7-0} = 0b00000011;
1041 def SEL : AI<(outs GPR:$dst), (ins GPR:$a, GPR:$b), DPFrm, NoItinerary, "sel",
1043 [/* For disassembly only; pattern left blank */]>,
1044 Requires<[IsARM, HasV6]> {
1049 let Inst{15-12} = Rd;
1050 let Inst{19-16} = Rn;
1051 let Inst{27-20} = 0b01101000;
1052 let Inst{7-4} = 0b1011;
1053 let Inst{11-8} = 0b1111;
1056 def SEV : AI<(outs), (ins), MiscFrm, NoItinerary, "sev", "",
1057 [/* For disassembly only; pattern left blank */]>,
1058 Requires<[IsARM, HasV6T2]> {
1059 let Inst{27-16} = 0b001100100000;
1060 let Inst{15-8} = 0b11110000;
1061 let Inst{7-0} = 0b00000100;
1064 // The i32imm operand $val can be used by a debugger to store more information
1065 // about the breakpoint.
1066 def BKPT : AI<(outs), (ins i32imm:$val), MiscFrm, NoItinerary, "bkpt", "\t$val",
1067 [/* For disassembly only; pattern left blank */]>,
1070 let Inst{3-0} = val{3-0};
1071 let Inst{19-8} = val{15-4};
1072 let Inst{27-20} = 0b00010010;
1073 let Inst{7-4} = 0b0111;
1076 // Change Processor State is a system instruction -- for disassembly only.
1077 // The singleton $opt operand contains the following information:
1078 // opt{4-0} = mode from Inst{4-0}
1079 // opt{5} = changemode from Inst{17}
1080 // opt{8-6} = AIF from Inst{8-6}
1081 // opt{10-9} = imod from Inst{19-18} with 0b10 as enable and 0b11 as disable
1082 // FIXME: Integrated assembler will need these split out.
1083 def CPS : AXI<(outs), (ins cps_opt:$opt), MiscFrm, NoItinerary, "cps$opt",
1084 [/* For disassembly only; pattern left blank */]>,
1086 let Inst{31-28} = 0b1111;
1087 let Inst{27-20} = 0b00010000;
1092 // Preload signals the memory system of possible future data/instruction access.
1093 // These are for disassembly only.
1094 multiclass APreLoad<bits<1> read, bits<1> data, string opc> {
1096 def i12 : AXI<(outs), (ins addrmode_imm12:$addr), MiscFrm, IIC_Preload,
1097 !strconcat(opc, "\t$addr"),
1098 [(ARMPreload addrmode_imm12:$addr, (i32 read), (i32 data))]> {
1101 let Inst{31-26} = 0b111101;
1102 let Inst{25} = 0; // 0 for immediate form
1103 let Inst{24} = data;
1104 let Inst{23} = addr{12}; // U (add = ('U' == 1))
1105 let Inst{22} = read;
1106 let Inst{21-20} = 0b01;
1107 let Inst{19-16} = addr{16-13}; // Rn
1108 let Inst{15-12} = Rt;
1109 let Inst{11-0} = addr{11-0}; // imm12
1112 def rs : AXI<(outs), (ins ldst_so_reg:$shift), MiscFrm, IIC_Preload,
1113 !strconcat(opc, "\t$shift"),
1114 [(ARMPreload ldst_so_reg:$shift, (i32 read), (i32 data))]> {
1117 let Inst{31-26} = 0b111101;
1118 let Inst{25} = 1; // 1 for register form
1119 let Inst{24} = data;
1120 let Inst{23} = shift{12}; // U (add = ('U' == 1))
1121 let Inst{22} = read;
1122 let Inst{21-20} = 0b01;
1123 let Inst{19-16} = shift{16-13}; // Rn
1124 let Inst{11-0} = shift{11-0};
1128 defm PLD : APreLoad<1, 1, "pld">, Requires<[IsARM]>;
1129 defm PLDW : APreLoad<0, 1, "pldw">, Requires<[IsARM,HasV7,HasMP]>;
1130 defm PLI : APreLoad<1, 0, "pli">, Requires<[IsARM,HasV7]>;
1132 def SETEND : AXI<(outs),(ins setend_op:$end), MiscFrm, NoItinerary,
1134 [/* For disassembly only; pattern left blank */]>,
1137 let Inst{31-10} = 0b1111000100000001000000;
1142 def DBG : AI<(outs), (ins i32imm:$opt), MiscFrm, NoItinerary, "dbg", "\t$opt",
1143 [/* For disassembly only; pattern left blank */]>,
1144 Requires<[IsARM, HasV7]> {
1146 let Inst{27-4} = 0b001100100000111100001111;
1147 let Inst{3-0} = opt;
1150 // A5.4 Permanently UNDEFINED instructions.
1151 let isBarrier = 1, isTerminator = 1 in
1152 def TRAP : AXI<(outs), (ins), MiscFrm, NoItinerary,
1155 let Inst = 0xe7ffdefe;
1158 // Address computation and loads and stores in PIC mode.
1159 let isNotDuplicable = 1 in {
1160 def PICADD : ARMPseudoInst<(outs GPR:$dst), (ins GPR:$a, pclabel:$cp, pred:$p),
1161 Size4Bytes, IIC_iALUr,
1162 [(set GPR:$dst, (ARMpic_add GPR:$a, imm:$cp))]>;
1164 let AddedComplexity = 10 in {
1165 def PICLDR : ARMPseudoInst<(outs GPR:$dst), (ins addrmodepc:$addr, pred:$p),
1166 Size4Bytes, IIC_iLoad_r,
1167 [(set GPR:$dst, (load addrmodepc:$addr))]>;
1169 def PICLDRH : ARMPseudoInst<(outs GPR:$Rt), (ins addrmodepc:$addr, pred:$p),
1170 Size4Bytes, IIC_iLoad_bh_r,
1171 [(set GPR:$Rt, (zextloadi16 addrmodepc:$addr))]>;
1173 def PICLDRB : ARMPseudoInst<(outs GPR:$Rt), (ins addrmodepc:$addr, pred:$p),
1174 Size4Bytes, IIC_iLoad_bh_r,
1175 [(set GPR:$Rt, (zextloadi8 addrmodepc:$addr))]>;
1177 def PICLDRSH : ARMPseudoInst<(outs GPR:$Rt), (ins addrmodepc:$addr, pred:$p),
1178 Size4Bytes, IIC_iLoad_bh_r,
1179 [(set GPR:$Rt, (sextloadi16 addrmodepc:$addr))]>;
1181 def PICLDRSB : ARMPseudoInst<(outs GPR:$Rt), (ins addrmodepc:$addr, pred:$p),
1182 Size4Bytes, IIC_iLoad_bh_r,
1183 [(set GPR:$Rt, (sextloadi8 addrmodepc:$addr))]>;
1185 let AddedComplexity = 10 in {
1186 def PICSTR : ARMPseudoInst<(outs), (ins GPR:$src, addrmodepc:$addr, pred:$p),
1187 Size4Bytes, IIC_iStore_r, [(store GPR:$src, addrmodepc:$addr)]>;
1189 def PICSTRH : ARMPseudoInst<(outs), (ins GPR:$src, addrmodepc:$addr, pred:$p),
1190 Size4Bytes, IIC_iStore_bh_r, [(truncstorei16 GPR:$src, addrmodepc:$addr)]>;
1192 def PICSTRB : ARMPseudoInst<(outs), (ins GPR:$src, addrmodepc:$addr, pred:$p),
1193 Size4Bytes, IIC_iStore_bh_r, [(truncstorei8 GPR:$src, addrmodepc:$addr)]>;
1195 } // isNotDuplicable = 1
1198 // LEApcrel - Load a pc-relative address into a register without offending the
1200 let neverHasSideEffects = 1, isReMaterializable = 1 in
1201 // The 'adr' mnemonic encodes differently if the label is before or after
1202 // the instruction. The {24-21} opcode bits are set by the fixup, as we don't
1203 // know until then which form of the instruction will be used.
1204 def ADR : AI1<0, (outs GPR:$Rd), (ins adrlabel:$label),
1205 MiscFrm, IIC_iALUi, "adr", "\t$Rd, #$label", []> {
1208 let Inst{27-25} = 0b001;
1210 let Inst{19-16} = 0b1111;
1211 let Inst{15-12} = Rd;
1212 let Inst{11-0} = label;
1214 def LEApcrel : ARMPseudoInst<(outs GPR:$Rd), (ins i32imm:$label, pred:$p),
1215 Size4Bytes, IIC_iALUi, []>;
1217 def LEApcrelJT : ARMPseudoInst<(outs GPR:$Rd),
1218 (ins i32imm:$label, nohash_imm:$id, pred:$p),
1219 Size4Bytes, IIC_iALUi, []>;
1221 //===----------------------------------------------------------------------===//
1222 // Control Flow Instructions.
1225 let isReturn = 1, isTerminator = 1, isBarrier = 1 in {
1227 def BX_RET : AI<(outs), (ins), BrMiscFrm, IIC_Br,
1228 "bx", "\tlr", [(ARMretflag)]>,
1229 Requires<[IsARM, HasV4T]> {
1230 let Inst{27-0} = 0b0001001011111111111100011110;
1234 def MOVPCLR : AI<(outs), (ins), BrMiscFrm, IIC_Br,
1235 "mov", "\tpc, lr", [(ARMretflag)]>,
1236 Requires<[IsARM, NoV4T]> {
1237 let Inst{27-0} = 0b0001101000001111000000001110;
1241 // Indirect branches
1242 let isBranch = 1, isTerminator = 1, isBarrier = 1, isIndirectBranch = 1 in {
1244 def BX : AXI<(outs), (ins GPR:$dst), BrMiscFrm, IIC_Br, "bx\t$dst",
1245 [(brind GPR:$dst)]>,
1246 Requires<[IsARM, HasV4T]> {
1248 let Inst{31-4} = 0b1110000100101111111111110001;
1249 let Inst{3-0} = dst;
1253 // FIXME: We would really like to define this as a vanilla ARMPat like:
1254 // ARMPat<(brind GPR:$dst), (MOVr PC, GPR:$dst)>
1255 // With that, however, we can't set isBranch, isTerminator, etc..
1256 def MOVPCRX : ARMPseudoInst<(outs), (ins GPR:$dst),
1257 Size4Bytes, IIC_Br, [(brind GPR:$dst)]>,
1258 Requires<[IsARM, NoV4T]>;
1261 // All calls clobber the non-callee saved registers. SP is marked as
1262 // a use to prevent stack-pointer assignments that appear immediately
1263 // before calls from potentially appearing dead.
1265 // On non-Darwin platforms R9 is callee-saved.
1266 Defs = [R0, R1, R2, R3, R12, LR,
1267 D0, D1, D2, D3, D4, D5, D6, D7,
1268 D16, D17, D18, D19, D20, D21, D22, D23,
1269 D24, D25, D26, D27, D28, D29, D30, D31, CPSR, FPSCR],
1271 def BL : ABXI<0b1011, (outs), (ins bltarget:$func, variable_ops),
1272 IIC_Br, "bl\t$func",
1273 [(ARMcall tglobaladdr:$func)]>,
1274 Requires<[IsARM, IsNotDarwin]> {
1275 let Inst{31-28} = 0b1110;
1277 let Inst{23-0} = func;
1280 def BL_pred : ABI<0b1011, (outs), (ins bltarget:$func, variable_ops),
1281 IIC_Br, "bl", "\t$func",
1282 [(ARMcall_pred tglobaladdr:$func)]>,
1283 Requires<[IsARM, IsNotDarwin]> {
1285 let Inst{23-0} = func;
1289 def BLX : AXI<(outs), (ins GPR:$func, variable_ops), BrMiscFrm,
1290 IIC_Br, "blx\t$func",
1291 [(ARMcall GPR:$func)]>,
1292 Requires<[IsARM, HasV5T, IsNotDarwin]> {
1294 let Inst{31-4} = 0b1110000100101111111111110011;
1295 let Inst{3-0} = func;
1299 // Note: Restrict $func to the tGPR regclass to prevent it being in LR.
1300 def BX_CALL : ARMPseudoInst<(outs), (ins tGPR:$func, variable_ops),
1301 Size8Bytes, IIC_Br, [(ARMcall_nolink tGPR:$func)]>,
1302 Requires<[IsARM, HasV4T, IsNotDarwin]>;
1305 def BMOVPCRX_CALL : ARMPseudoInst<(outs), (ins tGPR:$func, variable_ops),
1306 Size8Bytes, IIC_Br, [(ARMcall_nolink tGPR:$func)]>,
1307 Requires<[IsARM, NoV4T, IsNotDarwin]>;
1311 // On Darwin R9 is call-clobbered.
1312 // R7 is marked as a use to prevent frame-pointer assignments from being
1313 // moved above / below calls.
1314 Defs = [R0, R1, R2, R3, R9, R12, LR,
1315 D0, D1, D2, D3, D4, D5, D6, D7,
1316 D16, D17, D18, D19, D20, D21, D22, D23,
1317 D24, D25, D26, D27, D28, D29, D30, D31, CPSR, FPSCR],
1318 Uses = [R7, SP] in {
1319 def BLr9 : ABXI<0b1011, (outs), (ins bltarget:$func, variable_ops),
1320 IIC_Br, "bl\t$func",
1321 [(ARMcall tglobaladdr:$func)]>, Requires<[IsARM, IsDarwin]> {
1322 let Inst{31-28} = 0b1110;
1324 let Inst{23-0} = func;
1327 def BLr9_pred : ABI<0b1011, (outs), (ins bltarget:$func, variable_ops),
1328 IIC_Br, "bl", "\t$func",
1329 [(ARMcall_pred tglobaladdr:$func)]>,
1330 Requires<[IsARM, IsDarwin]> {
1332 let Inst{23-0} = func;
1336 def BLXr9 : AXI<(outs), (ins GPR:$func, variable_ops), BrMiscFrm,
1337 IIC_Br, "blx\t$func",
1338 [(ARMcall GPR:$func)]>, Requires<[IsARM, HasV5T, IsDarwin]> {
1340 let Inst{31-4} = 0b1110000100101111111111110011;
1341 let Inst{3-0} = func;
1345 // Note: Restrict $func to the tGPR regclass to prevent it being in LR.
1346 def BXr9_CALL : ARMPseudoInst<(outs), (ins tGPR:$func, variable_ops),
1347 Size8Bytes, IIC_Br, [(ARMcall_nolink tGPR:$func)]>,
1348 Requires<[IsARM, HasV4T, IsDarwin]>;
1351 def BMOVPCRXr9_CALL : ARMPseudoInst<(outs), (ins tGPR:$func, variable_ops),
1352 Size8Bytes, IIC_Br, [(ARMcall_nolink tGPR:$func)]>,
1353 Requires<[IsARM, NoV4T, IsDarwin]>;
1358 // FIXME: These should probably be xformed into the non-TC versions of the
1359 // instructions as part of MC lowering.
1360 // FIXME: These seem to be used for both Thumb and ARM instruction selection.
1361 // Thumb should have its own version since the instruction is actually
1362 // different, even though the mnemonic is the same.
1363 let isCall = 1, isTerminator = 1, isReturn = 1, isBarrier = 1 in {
1365 let Defs = [R0, R1, R2, R3, R9, R12,
1366 D0, D1, D2, D3, D4, D5, D6, D7,
1367 D16, D17, D18, D19, D20, D21, D22, D23, D24, D25, D26,
1368 D27, D28, D29, D30, D31, PC],
1370 def TCRETURNdi : PseudoInst<(outs), (ins i32imm:$dst, variable_ops),
1371 IIC_Br, []>, Requires<[IsDarwin]>;
1373 def TCRETURNri : PseudoInst<(outs), (ins tcGPR:$dst, variable_ops),
1374 IIC_Br, []>, Requires<[IsDarwin]>;
1376 def TAILJMPd : ABXI<0b1010, (outs), (ins brtarget:$dst, variable_ops),
1377 IIC_Br, "b\t$dst @ TAILCALL",
1378 []>, Requires<[IsARM, IsDarwin]>;
1380 def TAILJMPdt: ABXI<0b1010, (outs), (ins brtarget:$dst, variable_ops),
1381 IIC_Br, "b.w\t$dst @ TAILCALL",
1382 []>, Requires<[IsThumb, IsDarwin]>;
1384 def TAILJMPr : AXI<(outs), (ins tcGPR:$dst, variable_ops),
1385 BrMiscFrm, IIC_Br, "bx\t$dst @ TAILCALL",
1386 []>, Requires<[IsDarwin]> {
1388 let Inst{31-4} = 0b1110000100101111111111110001;
1389 let Inst{3-0} = dst;
1393 // Non-Darwin versions (the difference is R9).
1394 let Defs = [R0, R1, R2, R3, R12,
1395 D0, D1, D2, D3, D4, D5, D6, D7,
1396 D16, D17, D18, D19, D20, D21, D22, D23, D24, D25, D26,
1397 D27, D28, D29, D30, D31, PC],
1399 def TCRETURNdiND : PseudoInst<(outs), (ins i32imm:$dst, variable_ops),
1400 IIC_Br, []>, Requires<[IsNotDarwin]>;
1402 def TCRETURNriND : PseudoInst<(outs), (ins tcGPR:$dst, variable_ops),
1403 IIC_Br, []>, Requires<[IsNotDarwin]>;
1405 def TAILJMPdND : ABXI<0b1010, (outs), (ins brtarget:$dst, variable_ops),
1406 IIC_Br, "b\t$dst @ TAILCALL",
1407 []>, Requires<[IsARM, IsNotDarwin]>;
1409 def TAILJMPdNDt : ABXI<0b1010, (outs), (ins brtarget:$dst, variable_ops),
1410 IIC_Br, "b.w\t$dst @ TAILCALL",
1411 []>, Requires<[IsThumb, IsNotDarwin]>;
1413 def TAILJMPrND : AXI<(outs), (ins tcGPR:$dst, variable_ops),
1414 BrMiscFrm, IIC_Br, "bx\t$dst @ TAILCALL",
1415 []>, Requires<[IsNotDarwin]> {
1417 let Inst{31-4} = 0b1110000100101111111111110001;
1418 let Inst{3-0} = dst;
1423 let isBranch = 1, isTerminator = 1 in {
1424 // B is "predicable" since it can be xformed into a Bcc.
1425 let isBarrier = 1 in {
1426 let isPredicable = 1 in
1427 def B : ABXI<0b1010, (outs), (ins brtarget:$target), IIC_Br,
1428 "b\t$target", [(br bb:$target)]> {
1430 let Inst{31-28} = 0b1110;
1431 let Inst{23-0} = target;
1434 let isNotDuplicable = 1, isIndirectBranch = 1 in {
1435 def BR_JTr : ARMPseudoInst<(outs),
1436 (ins GPR:$target, i32imm:$jt, i32imm:$id),
1437 SizeSpecial, IIC_Br,
1438 [(ARMbrjt GPR:$target, tjumptable:$jt, imm:$id)]>;
1439 // FIXME: This shouldn't use the generic "addrmode2," but rather be split
1440 // into i12 and rs suffixed versions.
1441 def BR_JTm : ARMPseudoInst<(outs),
1442 (ins addrmode2:$target, i32imm:$jt, i32imm:$id),
1443 SizeSpecial, IIC_Br,
1444 [(ARMbrjt (i32 (load addrmode2:$target)), tjumptable:$jt,
1446 def BR_JTadd : ARMPseudoInst<(outs),
1447 (ins GPR:$target, GPR:$idx, i32imm:$jt, i32imm:$id),
1448 SizeSpecial, IIC_Br,
1449 [(ARMbrjt (add GPR:$target, GPR:$idx), tjumptable:$jt,
1451 } // isNotDuplicable = 1, isIndirectBranch = 1
1454 // FIXME: should be able to write a pattern for ARMBrcond, but can't use
1455 // a two-value operand where a dag node expects two operands. :(
1456 def Bcc : ABI<0b1010, (outs), (ins brtarget:$target),
1457 IIC_Br, "b", "\t$target",
1458 [/*(ARMbrcond bb:$target, imm:$cc, CCR:$ccr)*/]> {
1460 let Inst{23-0} = target;
1464 // Branch and Exchange Jazelle -- for disassembly only
1465 def BXJ : ABI<0b0001, (outs), (ins GPR:$func), NoItinerary, "bxj", "\t$func",
1466 [/* For disassembly only; pattern left blank */]> {
1467 let Inst{23-20} = 0b0010;
1468 //let Inst{19-8} = 0xfff;
1469 let Inst{7-4} = 0b0010;
1472 // Secure Monitor Call is a system instruction -- for disassembly only
1473 def SMC : ABI<0b0001, (outs), (ins i32imm:$opt), NoItinerary, "smc", "\t$opt",
1474 [/* For disassembly only; pattern left blank */]> {
1476 let Inst{23-4} = 0b01100000000000000111;
1477 let Inst{3-0} = opt;
1480 // Supervisor Call (Software Interrupt) -- for disassembly only
1481 let isCall = 1, Uses = [SP] in {
1482 def SVC : ABI<0b1111, (outs), (ins i32imm:$svc), IIC_Br, "svc", "\t$svc",
1483 [/* For disassembly only; pattern left blank */]> {
1485 let Inst{23-0} = svc;
1489 // Store Return State is a system instruction -- for disassembly only
1490 let isCodeGenOnly = 1 in { // FIXME: This should not use submode!
1491 def SRSW : ABXI<{1,0,0,?}, (outs), (ins ldstm_mode:$amode, i32imm:$mode),
1492 NoItinerary, "srs${amode}\tsp!, $mode",
1493 [/* For disassembly only; pattern left blank */]> {
1494 let Inst{31-28} = 0b1111;
1495 let Inst{22-20} = 0b110; // W = 1
1498 def SRS : ABXI<{1,0,0,?}, (outs), (ins ldstm_mode:$amode, i32imm:$mode),
1499 NoItinerary, "srs${amode}\tsp, $mode",
1500 [/* For disassembly only; pattern left blank */]> {
1501 let Inst{31-28} = 0b1111;
1502 let Inst{22-20} = 0b100; // W = 0
1505 // Return From Exception is a system instruction -- for disassembly only
1506 def RFEW : ABXI<{1,0,0,?}, (outs), (ins ldstm_mode:$amode, GPR:$base),
1507 NoItinerary, "rfe${amode}\t$base!",
1508 [/* For disassembly only; pattern left blank */]> {
1509 let Inst{31-28} = 0b1111;
1510 let Inst{22-20} = 0b011; // W = 1
1513 def RFE : ABXI<{1,0,0,?}, (outs), (ins ldstm_mode:$amode, GPR:$base),
1514 NoItinerary, "rfe${amode}\t$base",
1515 [/* For disassembly only; pattern left blank */]> {
1516 let Inst{31-28} = 0b1111;
1517 let Inst{22-20} = 0b001; // W = 0
1519 } // isCodeGenOnly = 1
1521 //===----------------------------------------------------------------------===//
1522 // Load / store Instructions.
1528 defm LDR : AI_ldr1<0, "ldr", IIC_iLoad_r, IIC_iLoad_si,
1529 UnOpFrag<(load node:$Src)>>;
1530 defm LDRB : AI_ldr1<1, "ldrb", IIC_iLoad_bh_r, IIC_iLoad_bh_si,
1531 UnOpFrag<(zextloadi8 node:$Src)>>;
1532 defm STR : AI_str1<0, "str", IIC_iStore_r, IIC_iStore_si,
1533 BinOpFrag<(store node:$LHS, node:$RHS)>>;
1534 defm STRB : AI_str1<1, "strb", IIC_iStore_bh_r, IIC_iStore_bh_si,
1535 BinOpFrag<(truncstorei8 node:$LHS, node:$RHS)>>;
1537 // Special LDR for loads from non-pc-relative constpools.
1538 let canFoldAsLoad = 1, mayLoad = 1, neverHasSideEffects = 1,
1539 isReMaterializable = 1 in
1540 def LDRcp : AI2ldst<0b010, 1, 0, (outs GPR:$Rt), (ins addrmode_imm12:$addr),
1541 AddrMode_i12, LdFrm, IIC_iLoad_r, "ldr", "\t$Rt, $addr",
1545 let Inst{23} = addr{12}; // U (add = ('U' == 1))
1546 let Inst{19-16} = 0b1111;
1547 let Inst{15-12} = Rt;
1548 let Inst{11-0} = addr{11-0}; // imm12
1551 // Loads with zero extension
1552 def LDRH : AI3ld<0b1011, 1, (outs GPR:$Rt), (ins addrmode3:$addr), LdMiscFrm,
1553 IIC_iLoad_bh_r, "ldrh", "\t$Rt, $addr",
1554 [(set GPR:$Rt, (zextloadi16 addrmode3:$addr))]>;
1556 // Loads with sign extension
1557 def LDRSH : AI3ld<0b1111, 1, (outs GPR:$Rt), (ins addrmode3:$addr), LdMiscFrm,
1558 IIC_iLoad_bh_r, "ldrsh", "\t$Rt, $addr",
1559 [(set GPR:$Rt, (sextloadi16 addrmode3:$addr))]>;
1561 def LDRSB : AI3ld<0b1101, 1, (outs GPR:$Rt), (ins addrmode3:$addr), LdMiscFrm,
1562 IIC_iLoad_bh_r, "ldrsb", "\t$Rt, $addr",
1563 [(set GPR:$Rt, (sextloadi8 addrmode3:$addr))]>;
1565 let mayLoad = 1, neverHasSideEffects = 1, hasExtraDefRegAllocReq = 1,
1566 isCodeGenOnly = 1 in { // $dst2 doesn't exist in asmstring?
1567 // FIXME: $dst2 isn't in the asm string as it's implied by $Rd (dst2 = Rd+1)
1568 // how to represent that such that tblgen is happy and we don't
1569 // mark this codegen only?
1571 def LDRD : AI3ld<0b1101, 0, (outs GPR:$Rd, GPR:$dst2),
1572 (ins addrmode3:$addr), LdMiscFrm,
1573 IIC_iLoad_d_r, "ldrd", "\t$Rd, $addr",
1574 []>, Requires<[IsARM, HasV5TE]>;
1578 multiclass AI2_ldridx<bit isByte, string opc, InstrItinClass itin> {
1579 def _PRE : AI2ldstidx<1, isByte, 1, (outs GPR:$Rt, GPR:$Rn_wb),
1580 (ins addrmode2:$addr), IndexModePre, LdFrm, itin,
1581 opc, "\t$Rt, $addr!", "$addr.base = $Rn_wb", []> {
1583 // {13} 1 == Rm, 0 == imm12
1587 let Inst{25} = addr{13};
1588 let Inst{23} = addr{12};
1589 let Inst{19-16} = addr{17-14};
1590 let Inst{11-0} = addr{11-0};
1592 def _POST : AI2ldstidx<1, isByte, 0, (outs GPR:$Rt, GPR:$Rn_wb),
1593 (ins GPR:$Rn, am2offset:$offset),
1594 IndexModePost, LdFrm, itin,
1595 opc, "\t$Rt, [$Rn], $offset", "$Rn = $Rn_wb", []> {
1596 // {13} 1 == Rm, 0 == imm12
1601 let Inst{25} = offset{13};
1602 let Inst{23} = offset{12};
1603 let Inst{19-16} = Rn;
1604 let Inst{11-0} = offset{11-0};
1608 let mayLoad = 1, neverHasSideEffects = 1 in {
1609 defm LDR : AI2_ldridx<0, "ldr", IIC_iLoad_ru>;
1610 defm LDRB : AI2_ldridx<1, "ldrb", IIC_iLoad_bh_ru>;
1613 multiclass AI3_ldridx<bits<4> op, bit op20, string opc, InstrItinClass itin> {
1614 def _PRE : AI3ldstidx<op, op20, 1, 1, (outs GPR:$Rt, GPR:$Rn_wb),
1615 (ins addrmode3:$addr), IndexModePre,
1617 opc, "\t$Rt, $addr!", "$addr.base = $Rn_wb", []> {
1619 let Inst{23} = addr{8}; // U bit
1620 let Inst{22} = addr{13}; // 1 == imm8, 0 == Rm
1621 let Inst{19-16} = addr{12-9}; // Rn
1622 let Inst{11-8} = addr{7-4}; // imm7_4/zero
1623 let Inst{3-0} = addr{3-0}; // imm3_0/Rm
1625 def _POST : AI3ldstidx<op, op20, 1, 0, (outs GPR:$Rt, GPR:$Rn_wb),
1626 (ins GPR:$Rn, am3offset:$offset), IndexModePost,
1628 opc, "\t$Rt, [$Rn], $offset", "$Rn = $Rn_wb", []> {
1631 let Inst{23} = offset{8}; // U bit
1632 let Inst{22} = offset{9}; // 1 == imm8, 0 == Rm
1633 let Inst{19-16} = Rn;
1634 let Inst{11-8} = offset{7-4}; // imm7_4/zero
1635 let Inst{3-0} = offset{3-0}; // imm3_0/Rm
1639 let mayLoad = 1, neverHasSideEffects = 1 in {
1640 defm LDRH : AI3_ldridx<0b1011, 1, "ldrh", IIC_iLoad_bh_ru>;
1641 defm LDRSH : AI3_ldridx<0b1111, 1, "ldrsh", IIC_iLoad_bh_ru>;
1642 defm LDRSB : AI3_ldridx<0b1101, 1, "ldrsb", IIC_iLoad_bh_ru>;
1643 let hasExtraDefRegAllocReq = 1, isCodeGenOnly = 1 in
1644 defm LDRD : AI3_ldridx<0b1101, 0, "ldrd", IIC_iLoad_d_ru>;
1645 } // mayLoad = 1, neverHasSideEffects = 1
1647 // LDRT, LDRBT, LDRSBT, LDRHT, LDRSHT are for disassembly only.
1648 let mayLoad = 1, neverHasSideEffects = 1 in {
1649 def LDRT : AI2ldstidx<1, 0, 0, (outs GPR:$dst, GPR:$base_wb),
1650 (ins GPR:$base, am2offset:$offset), IndexModeNone,
1651 LdFrm, IIC_iLoad_ru,
1652 "ldrt", "\t$dst, [$base], $offset", "$base = $base_wb", []> {
1653 let Inst{21} = 1; // overwrite
1655 def LDRBT : AI2ldstidx<1, 1, 0, (outs GPR:$dst, GPR:$base_wb),
1656 (ins GPR:$base, am2offset:$offset), IndexModeNone,
1657 LdFrm, IIC_iLoad_bh_ru,
1658 "ldrbt", "\t$dst, [$base], $offset", "$base = $base_wb", []> {
1659 let Inst{21} = 1; // overwrite
1661 def LDRSBT : AI3ldstidx<0b1101, 1, 1, 0, (outs GPR:$dst, GPR:$base_wb),
1662 (ins GPR:$base, am3offset:$offset), IndexModePost,
1663 LdMiscFrm, IIC_iLoad_bh_ru,
1664 "ldrsbt", "\t$dst, [$base], $offset", "$base = $base_wb", []> {
1665 let Inst{21} = 1; // overwrite
1667 def LDRHT : AI3ldstidx<0b1011, 1, 1, 0, (outs GPR:$dst, GPR:$base_wb),
1668 (ins GPR:$base, am3offset:$offset), IndexModePost,
1669 LdMiscFrm, IIC_iLoad_bh_ru,
1670 "ldrht", "\t$dst, [$base], $offset", "$base = $base_wb", []> {
1671 let Inst{21} = 1; // overwrite
1673 def LDRSHT : AI3ldstidx<0b1111, 1, 1, 0, (outs GPR:$dst, GPR:$base_wb),
1674 (ins GPR:$base, am3offset:$offset), IndexModePost,
1675 LdMiscFrm, IIC_iLoad_bh_ru,
1676 "ldrsht", "\t$dst, [$base], $offset", "$base = $base_wb", []> {
1677 let Inst{21} = 1; // overwrite
1683 // Stores with truncate
1684 def STRH : AI3str<0b1011, (outs), (ins GPR:$Rt, addrmode3:$addr), StMiscFrm,
1685 IIC_iStore_bh_r, "strh", "\t$Rt, $addr",
1686 [(truncstorei16 GPR:$Rt, addrmode3:$addr)]>;
1689 let mayStore = 1, neverHasSideEffects = 1, hasExtraSrcRegAllocReq = 1,
1690 isCodeGenOnly = 1 in // $src2 doesn't exist in asm string
1691 def STRD : AI3str<0b1111, (outs), (ins GPR:$src1, GPR:$src2, addrmode3:$addr),
1692 StMiscFrm, IIC_iStore_d_r,
1693 "strd", "\t$src1, $addr", []>, Requires<[IsARM, HasV5TE]>;
1696 def STR_PRE : AI2stridx<0, 1, (outs GPR:$Rn_wb),
1697 (ins GPR:$Rt, GPR:$Rn, am2offset:$offset),
1698 IndexModePre, StFrm, IIC_iStore_ru,
1699 "str", "\t$Rt, [$Rn, $offset]!", "$Rn = $Rn_wb",
1701 (pre_store GPR:$Rt, GPR:$Rn, am2offset:$offset))]>;
1703 def STR_POST : AI2stridx<0, 0, (outs GPR:$Rn_wb),
1704 (ins GPR:$Rt, GPR:$Rn, am2offset:$offset),
1705 IndexModePost, StFrm, IIC_iStore_ru,
1706 "str", "\t$Rt, [$Rn], $offset", "$Rn = $Rn_wb",
1708 (post_store GPR:$Rt, GPR:$Rn, am2offset:$offset))]>;
1710 def STRB_PRE : AI2stridx<1, 1, (outs GPR:$Rn_wb),
1711 (ins GPR:$Rt, GPR:$Rn, am2offset:$offset),
1712 IndexModePre, StFrm, IIC_iStore_bh_ru,
1713 "strb", "\t$Rt, [$Rn, $offset]!", "$Rn = $Rn_wb",
1714 [(set GPR:$Rn_wb, (pre_truncsti8 GPR:$Rt,
1715 GPR:$Rn, am2offset:$offset))]>;
1716 def STRB_POST: AI2stridx<1, 0, (outs GPR:$Rn_wb),
1717 (ins GPR:$Rt, GPR:$Rn, am2offset:$offset),
1718 IndexModePost, StFrm, IIC_iStore_bh_ru,
1719 "strb", "\t$Rt, [$Rn], $offset", "$Rn = $Rn_wb",
1720 [(set GPR:$Rn_wb, (post_truncsti8 GPR:$Rt,
1721 GPR:$Rn, am2offset:$offset))]>;
1723 def STRH_PRE : AI3stridx<0b1011, 0, 1, (outs GPR:$Rn_wb),
1724 (ins GPR:$Rt, GPR:$Rn, am3offset:$offset),
1725 IndexModePre, StMiscFrm, IIC_iStore_ru,
1726 "strh", "\t$Rt, [$Rn, $offset]!", "$Rn = $Rn_wb",
1728 (pre_truncsti16 GPR:$Rt, GPR:$Rn, am3offset:$offset))]>;
1730 def STRH_POST: AI3stridx<0b1011, 0, 0, (outs GPR:$Rn_wb),
1731 (ins GPR:$Rt, GPR:$Rn, am3offset:$offset),
1732 IndexModePost, StMiscFrm, IIC_iStore_bh_ru,
1733 "strh", "\t$Rt, [$Rn], $offset", "$Rn = $Rn_wb",
1734 [(set GPR:$Rn_wb, (post_truncsti16 GPR:$Rt,
1735 GPR:$Rn, am3offset:$offset))]>;
1737 // For disassembly only
1738 def STRD_PRE : AI3stdpr<(outs GPR:$base_wb),
1739 (ins GPR:$src1, GPR:$src2, GPR:$base, am3offset:$offset),
1740 StMiscFrm, IIC_iStore_d_ru,
1741 "strd", "\t$src1, $src2, [$base, $offset]!",
1742 "$base = $base_wb", []>;
1744 // For disassembly only
1745 def STRD_POST: AI3stdpo<(outs GPR:$base_wb),
1746 (ins GPR:$src1, GPR:$src2, GPR:$base, am3offset:$offset),
1747 StMiscFrm, IIC_iStore_d_ru,
1748 "strd", "\t$src1, $src2, [$base], $offset",
1749 "$base = $base_wb", []>;
1751 // STRT, STRBT, and STRHT are for disassembly only.
1753 def STRT : AI2stridx<0, 0, (outs GPR:$Rn_wb),
1754 (ins GPR:$Rt, GPR:$Rn,am2offset:$offset),
1755 IndexModeNone, StFrm, IIC_iStore_ru,
1756 "strt", "\t$Rt, [$Rn], $offset", "$Rn = $Rn_wb",
1757 [/* For disassembly only; pattern left blank */]> {
1758 let Inst{21} = 1; // overwrite
1761 def STRBT : AI2stridx<1, 0, (outs GPR:$Rn_wb),
1762 (ins GPR:$Rt, GPR:$Rn, am2offset:$offset),
1763 IndexModeNone, StFrm, IIC_iStore_bh_ru,
1764 "strbt", "\t$Rt, [$Rn], $offset", "$Rn = $Rn_wb",
1765 [/* For disassembly only; pattern left blank */]> {
1766 let Inst{21} = 1; // overwrite
1769 def STRHT: AI3sthpo<(outs GPR:$base_wb),
1770 (ins GPR:$src, GPR:$base,am3offset:$offset),
1771 StMiscFrm, IIC_iStore_bh_ru,
1772 "strht", "\t$src, [$base], $offset", "$base = $base_wb",
1773 [/* For disassembly only; pattern left blank */]> {
1774 let Inst{21} = 1; // overwrite
1777 //===----------------------------------------------------------------------===//
1778 // Load / store multiple Instructions.
1781 multiclass arm_ldst_mult<string asm, bit L_bit, Format f,
1782 InstrItinClass itin, InstrItinClass itin_upd> {
1784 AXI4<(outs), (ins GPR:$Rn, pred:$p, reglist:$regs, variable_ops),
1785 IndexModeNone, f, itin,
1786 !strconcat(asm, "ia${p}\t$Rn, $regs"), "", []> {
1787 let Inst{24-23} = 0b01; // Increment After
1788 let Inst{21} = 0; // No writeback
1789 let Inst{20} = L_bit;
1792 AXI4<(outs GPR:$wb), (ins GPR:$Rn, pred:$p, reglist:$regs, variable_ops),
1793 IndexModeUpd, f, itin_upd,
1794 !strconcat(asm, "ia${p}\t$Rn!, $regs"), "$Rn = $wb", []> {
1795 let Inst{24-23} = 0b01; // Increment After
1796 let Inst{21} = 1; // Writeback
1797 let Inst{20} = L_bit;
1800 AXI4<(outs), (ins GPR:$Rn, pred:$p, reglist:$regs, variable_ops),
1801 IndexModeNone, f, itin,
1802 !strconcat(asm, "da${p}\t$Rn, $regs"), "", []> {
1803 let Inst{24-23} = 0b00; // Decrement After
1804 let Inst{21} = 0; // No writeback
1805 let Inst{20} = L_bit;
1808 AXI4<(outs GPR:$wb), (ins GPR:$Rn, pred:$p, reglist:$regs, variable_ops),
1809 IndexModeUpd, f, itin_upd,
1810 !strconcat(asm, "da${p}\t$Rn!, $regs"), "$Rn = $wb", []> {
1811 let Inst{24-23} = 0b00; // Decrement After
1812 let Inst{21} = 1; // Writeback
1813 let Inst{20} = L_bit;
1816 AXI4<(outs), (ins GPR:$Rn, pred:$p, reglist:$regs, variable_ops),
1817 IndexModeNone, f, itin,
1818 !strconcat(asm, "db${p}\t$Rn, $regs"), "", []> {
1819 let Inst{24-23} = 0b10; // Decrement Before
1820 let Inst{21} = 0; // No writeback
1821 let Inst{20} = L_bit;
1824 AXI4<(outs GPR:$wb), (ins GPR:$Rn, pred:$p, reglist:$regs, variable_ops),
1825 IndexModeUpd, f, itin_upd,
1826 !strconcat(asm, "db${p}\t$Rn!, $regs"), "$Rn = $wb", []> {
1827 let Inst{24-23} = 0b10; // Decrement Before
1828 let Inst{21} = 1; // Writeback
1829 let Inst{20} = L_bit;
1832 AXI4<(outs), (ins GPR:$Rn, pred:$p, reglist:$regs, variable_ops),
1833 IndexModeNone, f, itin,
1834 !strconcat(asm, "ib${p}\t$Rn, $regs"), "", []> {
1835 let Inst{24-23} = 0b11; // Increment Before
1836 let Inst{21} = 0; // No writeback
1837 let Inst{20} = L_bit;
1840 AXI4<(outs GPR:$wb), (ins GPR:$Rn, pred:$p, reglist:$regs, variable_ops),
1841 IndexModeUpd, f, itin_upd,
1842 !strconcat(asm, "ib${p}\t$Rn!, $regs"), "$Rn = $wb", []> {
1843 let Inst{24-23} = 0b11; // Increment Before
1844 let Inst{21} = 1; // Writeback
1845 let Inst{20} = L_bit;
1849 let neverHasSideEffects = 1 in {
1851 let mayLoad = 1, hasExtraDefRegAllocReq = 1 in
1852 defm LDM : arm_ldst_mult<"ldm", 1, LdStMulFrm, IIC_iLoad_m, IIC_iLoad_mu>;
1854 let mayStore = 1, hasExtraSrcRegAllocReq = 1 in
1855 defm STM : arm_ldst_mult<"stm", 0, LdStMulFrm, IIC_iStore_m, IIC_iStore_mu>;
1857 } // neverHasSideEffects
1859 // Load / Store Multiple Mnemnoic Aliases
1860 def : MnemonicAlias<"ldm", "ldmia">;
1861 def : MnemonicAlias<"stm", "stmia">;
1863 // FIXME: remove when we have a way to marking a MI with these properties.
1864 // FIXME: Should pc be an implicit operand like PICADD, etc?
1865 let isReturn = 1, isTerminator = 1, isBarrier = 1, mayLoad = 1,
1866 hasExtraDefRegAllocReq = 1, isCodeGenOnly = 1 in
1867 // FIXME: Should be a pseudo-instruction.
1868 def LDMIA_RET : AXI4<(outs GPR:$wb), (ins GPR:$Rn, pred:$p,
1869 reglist:$regs, variable_ops),
1870 IndexModeUpd, LdStMulFrm, IIC_iLoad_mBr,
1871 "ldmia${p}\t$Rn!, $regs",
1873 let Inst{24-23} = 0b01; // Increment After
1874 let Inst{21} = 1; // Writeback
1875 let Inst{20} = 1; // Load
1878 //===----------------------------------------------------------------------===//
1879 // Move Instructions.
1882 let neverHasSideEffects = 1 in
1883 def MOVr : AsI1<0b1101, (outs GPR:$Rd), (ins GPR:$Rm), DPFrm, IIC_iMOVr,
1884 "mov", "\t$Rd, $Rm", []>, UnaryDP {
1888 let Inst{11-4} = 0b00000000;
1891 let Inst{15-12} = Rd;
1894 // A version for the smaller set of tail call registers.
1895 let neverHasSideEffects = 1 in
1896 def MOVr_TC : AsI1<0b1101, (outs tcGPR:$Rd), (ins tcGPR:$Rm), DPFrm,
1897 IIC_iMOVr, "mov", "\t$Rd, $Rm", []>, UnaryDP {
1901 let Inst{11-4} = 0b00000000;
1904 let Inst{15-12} = Rd;
1907 def MOVs : AsI1<0b1101, (outs GPR:$Rd), (ins shift_so_reg:$src),
1908 DPSoRegFrm, IIC_iMOVsr,
1909 "mov", "\t$Rd, $src", [(set GPR:$Rd, shift_so_reg:$src)]>,
1913 let Inst{15-12} = Rd;
1914 let Inst{11-0} = src;
1918 let isReMaterializable = 1, isAsCheapAsAMove = 1, isMoveImm = 1 in
1919 def MOVi : AsI1<0b1101, (outs GPR:$Rd), (ins so_imm:$imm), DPFrm, IIC_iMOVi,
1920 "mov", "\t$Rd, $imm", [(set GPR:$Rd, so_imm:$imm)]>, UnaryDP {
1924 let Inst{15-12} = Rd;
1925 let Inst{19-16} = 0b0000;
1926 let Inst{11-0} = imm;
1929 let isReMaterializable = 1, isAsCheapAsAMove = 1, isMoveImm = 1 in
1930 def MOVi16 : AI1<0b1000, (outs GPR:$Rd), (ins movt_imm:$imm),
1932 "movw", "\t$Rd, $imm",
1933 [(set GPR:$Rd, imm0_65535:$imm)]>,
1934 Requires<[IsARM, HasV6T2]>, UnaryDP {
1937 let Inst{15-12} = Rd;
1938 let Inst{11-0} = imm{11-0};
1939 let Inst{19-16} = imm{15-12};
1944 let Constraints = "$src = $Rd" in
1945 def MOVTi16 : AI1<0b1010, (outs GPR:$Rd), (ins GPR:$src, movt_imm:$imm),
1947 "movt", "\t$Rd, $imm",
1949 (or (and GPR:$src, 0xffff),
1950 lo16AllZero:$imm))]>, UnaryDP,
1951 Requires<[IsARM, HasV6T2]> {
1954 let Inst{15-12} = Rd;
1955 let Inst{11-0} = imm{11-0};
1956 let Inst{19-16} = imm{15-12};
1961 def : ARMPat<(or GPR:$src, 0xffff0000), (MOVTi16 GPR:$src, 0xffff)>,
1962 Requires<[IsARM, HasV6T2]>;
1964 let Uses = [CPSR] in
1965 def RRX: PseudoInst<(outs GPR:$Rd), (ins GPR:$Rm), IIC_iMOVsi,
1966 [(set GPR:$Rd, (ARMrrx GPR:$Rm))]>, UnaryDP,
1969 // These aren't really mov instructions, but we have to define them this way
1970 // due to flag operands.
1972 let Defs = [CPSR] in {
1973 def MOVsrl_flag : PseudoInst<(outs GPR:$dst), (ins GPR:$src), IIC_iMOVsi,
1974 [(set GPR:$dst, (ARMsrl_flag GPR:$src))]>, UnaryDP,
1976 def MOVsra_flag : PseudoInst<(outs GPR:$dst), (ins GPR:$src), IIC_iMOVsi,
1977 [(set GPR:$dst, (ARMsra_flag GPR:$src))]>, UnaryDP,
1981 //===----------------------------------------------------------------------===//
1982 // Extend Instructions.
1987 defm SXTB : AI_ext_rrot<0b01101010,
1988 "sxtb", UnOpFrag<(sext_inreg node:$Src, i8)>>;
1989 defm SXTH : AI_ext_rrot<0b01101011,
1990 "sxth", UnOpFrag<(sext_inreg node:$Src, i16)>>;
1992 defm SXTAB : AI_exta_rrot<0b01101010,
1993 "sxtab", BinOpFrag<(add node:$LHS, (sext_inreg node:$RHS, i8))>>;
1994 defm SXTAH : AI_exta_rrot<0b01101011,
1995 "sxtah", BinOpFrag<(add node:$LHS, (sext_inreg node:$RHS,i16))>>;
1997 // For disassembly only
1998 defm SXTB16 : AI_ext_rrot_np<0b01101000, "sxtb16">;
2000 // For disassembly only
2001 defm SXTAB16 : AI_exta_rrot_np<0b01101000, "sxtab16">;
2005 let AddedComplexity = 16 in {
2006 defm UXTB : AI_ext_rrot<0b01101110,
2007 "uxtb" , UnOpFrag<(and node:$Src, 0x000000FF)>>;
2008 defm UXTH : AI_ext_rrot<0b01101111,
2009 "uxth" , UnOpFrag<(and node:$Src, 0x0000FFFF)>>;
2010 defm UXTB16 : AI_ext_rrot<0b01101100,
2011 "uxtb16", UnOpFrag<(and node:$Src, 0x00FF00FF)>>;
2013 // FIXME: This pattern incorrectly assumes the shl operator is a rotate.
2014 // The transformation should probably be done as a combiner action
2015 // instead so we can include a check for masking back in the upper
2016 // eight bits of the source into the lower eight bits of the result.
2017 //def : ARMV6Pat<(and (shl GPR:$Src, (i32 8)), 0xFF00FF),
2018 // (UXTB16r_rot GPR:$Src, 24)>;
2019 def : ARMV6Pat<(and (srl GPR:$Src, (i32 8)), 0xFF00FF),
2020 (UXTB16r_rot GPR:$Src, 8)>;
2022 defm UXTAB : AI_exta_rrot<0b01101110, "uxtab",
2023 BinOpFrag<(add node:$LHS, (and node:$RHS, 0x00FF))>>;
2024 defm UXTAH : AI_exta_rrot<0b01101111, "uxtah",
2025 BinOpFrag<(add node:$LHS, (and node:$RHS, 0xFFFF))>>;
2028 // This isn't safe in general, the add is two 16-bit units, not a 32-bit add.
2029 // For disassembly only
2030 defm UXTAB16 : AI_exta_rrot_np<0b01101100, "uxtab16">;
2033 def SBFX : I<(outs GPR:$Rd),
2034 (ins GPR:$Rn, imm0_31:$lsb, imm0_31_m1:$width),
2035 AddrMode1, Size4Bytes, IndexModeNone, DPFrm, IIC_iUNAsi,
2036 "sbfx", "\t$Rd, $Rn, $lsb, $width", "", []>,
2037 Requires<[IsARM, HasV6T2]> {
2042 let Inst{27-21} = 0b0111101;
2043 let Inst{6-4} = 0b101;
2044 let Inst{20-16} = width;
2045 let Inst{15-12} = Rd;
2046 let Inst{11-7} = lsb;
2050 def UBFX : I<(outs GPR:$Rd),
2051 (ins GPR:$Rn, imm0_31:$lsb, imm0_31_m1:$width),
2052 AddrMode1, Size4Bytes, IndexModeNone, DPFrm, IIC_iUNAsi,
2053 "ubfx", "\t$Rd, $Rn, $lsb, $width", "", []>,
2054 Requires<[IsARM, HasV6T2]> {
2059 let Inst{27-21} = 0b0111111;
2060 let Inst{6-4} = 0b101;
2061 let Inst{20-16} = width;
2062 let Inst{15-12} = Rd;
2063 let Inst{11-7} = lsb;
2067 //===----------------------------------------------------------------------===//
2068 // Arithmetic Instructions.
2071 defm ADD : AsI1_bin_irs<0b0100, "add",
2072 IIC_iALUi, IIC_iALUr, IIC_iALUsr,
2073 BinOpFrag<(add node:$LHS, node:$RHS)>, 1>;
2074 defm SUB : AsI1_bin_irs<0b0010, "sub",
2075 IIC_iALUi, IIC_iALUr, IIC_iALUsr,
2076 BinOpFrag<(sub node:$LHS, node:$RHS)>>;
2078 // ADD and SUB with 's' bit set.
2079 defm ADDS : AI1_bin_s_irs<0b0100, "adds",
2080 IIC_iALUi, IIC_iALUr, IIC_iALUsr,
2081 BinOpFrag<(addc node:$LHS, node:$RHS)>, 1>;
2082 defm SUBS : AI1_bin_s_irs<0b0010, "subs",
2083 IIC_iALUi, IIC_iALUr, IIC_iALUsr,
2084 BinOpFrag<(subc node:$LHS, node:$RHS)>>;
2086 defm ADC : AI1_adde_sube_irs<0b0101, "adc",
2087 BinOpFrag<(adde_dead_carry node:$LHS, node:$RHS)>, 1>;
2088 defm SBC : AI1_adde_sube_irs<0b0110, "sbc",
2089 BinOpFrag<(sube_dead_carry node:$LHS, node:$RHS)>>;
2090 defm ADCS : AI1_adde_sube_s_irs<0b0101, "adcs",
2091 BinOpFrag<(adde_live_carry node:$LHS, node:$RHS)>, 1>;
2092 defm SBCS : AI1_adde_sube_s_irs<0b0110, "sbcs",
2093 BinOpFrag<(sube_live_carry node:$LHS, node:$RHS) >>;
2095 def RSBri : AsI1<0b0011, (outs GPR:$Rd), (ins GPR:$Rn, so_imm:$imm), DPFrm,
2096 IIC_iALUi, "rsb", "\t$Rd, $Rn, $imm",
2097 [(set GPR:$Rd, (sub so_imm:$imm, GPR:$Rn))]> {
2102 let Inst{15-12} = Rd;
2103 let Inst{19-16} = Rn;
2104 let Inst{11-0} = imm;
2107 // The reg/reg form is only defined for the disassembler; for codegen it is
2108 // equivalent to SUBrr.
2109 def RSBrr : AsI1<0b0011, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm), DPFrm,
2110 IIC_iALUr, "rsb", "\t$Rd, $Rn, $Rm",
2111 [/* For disassembly only; pattern left blank */]> {
2115 let Inst{11-4} = 0b00000000;
2118 let Inst{15-12} = Rd;
2119 let Inst{19-16} = Rn;
2122 def RSBrs : AsI1<0b0011, (outs GPR:$Rd), (ins GPR:$Rn, so_reg:$shift),
2123 DPSoRegFrm, IIC_iALUsr, "rsb", "\t$Rd, $Rn, $shift",
2124 [(set GPR:$Rd, (sub so_reg:$shift, GPR:$Rn))]> {
2129 let Inst{11-0} = shift;
2130 let Inst{15-12} = Rd;
2131 let Inst{19-16} = Rn;
2134 // RSB with 's' bit set.
2135 let Defs = [CPSR] in {
2136 def RSBSri : AI1<0b0011, (outs GPR:$Rd), (ins GPR:$Rn, so_imm:$imm), DPFrm,
2137 IIC_iALUi, "rsbs", "\t$Rd, $Rn, $imm",
2138 [(set GPR:$Rd, (subc so_imm:$imm, GPR:$Rn))]> {
2144 let Inst{15-12} = Rd;
2145 let Inst{19-16} = Rn;
2146 let Inst{11-0} = imm;
2148 def RSBSrs : AI1<0b0011, (outs GPR:$Rd), (ins GPR:$Rn, so_reg:$shift),
2149 DPSoRegFrm, IIC_iALUsr, "rsbs", "\t$Rd, $Rn, $shift",
2150 [(set GPR:$Rd, (subc so_reg:$shift, GPR:$Rn))]> {
2156 let Inst{11-0} = shift;
2157 let Inst{15-12} = Rd;
2158 let Inst{19-16} = Rn;
2162 let Uses = [CPSR] in {
2163 def RSCri : AsI1<0b0111, (outs GPR:$Rd), (ins GPR:$Rn, so_imm:$imm),
2164 DPFrm, IIC_iALUi, "rsc", "\t$Rd, $Rn, $imm",
2165 [(set GPR:$Rd, (sube_dead_carry so_imm:$imm, GPR:$Rn))]>,
2171 let Inst{15-12} = Rd;
2172 let Inst{19-16} = Rn;
2173 let Inst{11-0} = imm;
2175 // The reg/reg form is only defined for the disassembler; for codegen it is
2176 // equivalent to SUBrr.
2177 def RSCrr : AsI1<0b0111, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm),
2178 DPFrm, IIC_iALUr, "rsc", "\t$Rd, $Rn, $Rm",
2179 [/* For disassembly only; pattern left blank */]> {
2183 let Inst{11-4} = 0b00000000;
2186 let Inst{15-12} = Rd;
2187 let Inst{19-16} = Rn;
2189 def RSCrs : AsI1<0b0111, (outs GPR:$Rd), (ins GPR:$Rn, so_reg:$shift),
2190 DPSoRegFrm, IIC_iALUsr, "rsc", "\t$Rd, $Rn, $shift",
2191 [(set GPR:$Rd, (sube_dead_carry so_reg:$shift, GPR:$Rn))]>,
2197 let Inst{11-0} = shift;
2198 let Inst{15-12} = Rd;
2199 let Inst{19-16} = Rn;
2203 // FIXME: Allow these to be predicated.
2204 let Defs = [CPSR], Uses = [CPSR] in {
2205 def RSCSri : AXI1<0b0111, (outs GPR:$Rd), (ins GPR:$Rn, so_imm:$imm),
2206 DPFrm, IIC_iALUi, "rscs\t$Rd, $Rn, $imm",
2207 [(set GPR:$Rd, (sube_dead_carry so_imm:$imm, GPR:$Rn))]>,
2214 let Inst{15-12} = Rd;
2215 let Inst{19-16} = Rn;
2216 let Inst{11-0} = imm;
2218 def RSCSrs : AXI1<0b0111, (outs GPR:$Rd), (ins GPR:$Rn, so_reg:$shift),
2219 DPSoRegFrm, IIC_iALUsr, "rscs\t$Rd, $Rn, $shift",
2220 [(set GPR:$Rd, (sube_dead_carry so_reg:$shift, GPR:$Rn))]>,
2227 let Inst{11-0} = shift;
2228 let Inst{15-12} = Rd;
2229 let Inst{19-16} = Rn;
2233 // (sub X, imm) gets canonicalized to (add X, -imm). Match this form.
2234 // The assume-no-carry-in form uses the negation of the input since add/sub
2235 // assume opposite meanings of the carry flag (i.e., carry == !borrow).
2236 // See the definition of AddWithCarry() in the ARM ARM A2.2.1 for the gory
2238 def : ARMPat<(add GPR:$src, so_imm_neg:$imm),
2239 (SUBri GPR:$src, so_imm_neg:$imm)>;
2240 def : ARMPat<(addc GPR:$src, so_imm_neg:$imm),
2241 (SUBSri GPR:$src, so_imm_neg:$imm)>;
2242 // The with-carry-in form matches bitwise not instead of the negation.
2243 // Effectively, the inverse interpretation of the carry flag already accounts
2244 // for part of the negation.
2245 def : ARMPat<(adde GPR:$src, so_imm_not:$imm),
2246 (SBCri GPR:$src, so_imm_not:$imm)>;
2248 // Note: These are implemented in C++ code, because they have to generate
2249 // ADD/SUBrs instructions, which use a complex pattern that a xform function
2251 // (mul X, 2^n+1) -> (add (X << n), X)
2252 // (mul X, 2^n-1) -> (rsb X, (X << n))
2254 // ARM Arithmetic Instruction -- for disassembly only
2255 // GPR:$dst = GPR:$a op GPR:$b
2256 class AAI<bits<8> op27_20, bits<8> op11_4, string opc,
2257 list<dag> pattern = [/* For disassembly only; pattern left blank */]>
2258 : AI<(outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm), DPFrm, IIC_iALUr,
2259 opc, "\t$Rd, $Rn, $Rm", pattern> {
2263 let Inst{27-20} = op27_20;
2264 let Inst{11-4} = op11_4;
2265 let Inst{19-16} = Rn;
2266 let Inst{15-12} = Rd;
2270 // Saturating add/subtract -- for disassembly only
2272 def QADD : AAI<0b00010000, 0b00000101, "qadd",
2273 [(set GPR:$Rd, (int_arm_qadd GPR:$Rn, GPR:$Rm))]>;
2274 def QSUB : AAI<0b00010010, 0b00000101, "qsub",
2275 [(set GPR:$Rd, (int_arm_qsub GPR:$Rn, GPR:$Rm))]>;
2276 def QDADD : AAI<0b00010100, 0b00000101, "qdadd">;
2277 def QDSUB : AAI<0b00010110, 0b00000101, "qdsub">;
2279 def QADD16 : AAI<0b01100010, 0b11110001, "qadd16">;
2280 def QADD8 : AAI<0b01100010, 0b11111001, "qadd8">;
2281 def QASX : AAI<0b01100010, 0b11110011, "qasx">;
2282 def QSAX : AAI<0b01100010, 0b11110101, "qsax">;
2283 def QSUB16 : AAI<0b01100010, 0b11110111, "qsub16">;
2284 def QSUB8 : AAI<0b01100010, 0b11111111, "qsub8">;
2285 def UQADD16 : AAI<0b01100110, 0b11110001, "uqadd16">;
2286 def UQADD8 : AAI<0b01100110, 0b11111001, "uqadd8">;
2287 def UQASX : AAI<0b01100110, 0b11110011, "uqasx">;
2288 def UQSAX : AAI<0b01100110, 0b11110101, "uqsax">;
2289 def UQSUB16 : AAI<0b01100110, 0b11110111, "uqsub16">;
2290 def UQSUB8 : AAI<0b01100110, 0b11111111, "uqsub8">;
2292 // Signed/Unsigned add/subtract -- for disassembly only
2294 def SASX : AAI<0b01100001, 0b11110011, "sasx">;
2295 def SADD16 : AAI<0b01100001, 0b11110001, "sadd16">;
2296 def SADD8 : AAI<0b01100001, 0b11111001, "sadd8">;
2297 def SSAX : AAI<0b01100001, 0b11110101, "ssax">;
2298 def SSUB16 : AAI<0b01100001, 0b11110111, "ssub16">;
2299 def SSUB8 : AAI<0b01100001, 0b11111111, "ssub8">;
2300 def UASX : AAI<0b01100101, 0b11110011, "uasx">;
2301 def UADD16 : AAI<0b01100101, 0b11110001, "uadd16">;
2302 def UADD8 : AAI<0b01100101, 0b11111001, "uadd8">;
2303 def USAX : AAI<0b01100101, 0b11110101, "usax">;
2304 def USUB16 : AAI<0b01100101, 0b11110111, "usub16">;
2305 def USUB8 : AAI<0b01100101, 0b11111111, "usub8">;
2307 // Signed/Unsigned halving add/subtract -- for disassembly only
2309 def SHASX : AAI<0b01100011, 0b11110011, "shasx">;
2310 def SHADD16 : AAI<0b01100011, 0b11110001, "shadd16">;
2311 def SHADD8 : AAI<0b01100011, 0b11111001, "shadd8">;
2312 def SHSAX : AAI<0b01100011, 0b11110101, "shsax">;
2313 def SHSUB16 : AAI<0b01100011, 0b11110111, "shsub16">;
2314 def SHSUB8 : AAI<0b01100011, 0b11111111, "shsub8">;
2315 def UHASX : AAI<0b01100111, 0b11110011, "uhasx">;
2316 def UHADD16 : AAI<0b01100111, 0b11110001, "uhadd16">;
2317 def UHADD8 : AAI<0b01100111, 0b11111001, "uhadd8">;
2318 def UHSAX : AAI<0b01100111, 0b11110101, "uhsax">;
2319 def UHSUB16 : AAI<0b01100111, 0b11110111, "uhsub16">;
2320 def UHSUB8 : AAI<0b01100111, 0b11111111, "uhsub8">;
2322 // Unsigned Sum of Absolute Differences [and Accumulate] -- for disassembly only
2324 def USAD8 : AI<(outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm),
2325 MulFrm /* for convenience */, NoItinerary, "usad8",
2326 "\t$Rd, $Rn, $Rm", []>,
2327 Requires<[IsARM, HasV6]> {
2331 let Inst{27-20} = 0b01111000;
2332 let Inst{15-12} = 0b1111;
2333 let Inst{7-4} = 0b0001;
2334 let Inst{19-16} = Rd;
2335 let Inst{11-8} = Rm;
2338 def USADA8 : AI<(outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm, GPR:$Ra),
2339 MulFrm /* for convenience */, NoItinerary, "usada8",
2340 "\t$Rd, $Rn, $Rm, $Ra", []>,
2341 Requires<[IsARM, HasV6]> {
2346 let Inst{27-20} = 0b01111000;
2347 let Inst{7-4} = 0b0001;
2348 let Inst{19-16} = Rd;
2349 let Inst{15-12} = Ra;
2350 let Inst{11-8} = Rm;
2354 // Signed/Unsigned saturate -- for disassembly only
2356 def SSAT : AI<(outs GPR:$Rd), (ins i32imm:$sat_imm, GPR:$a, shift_imm:$sh),
2357 SatFrm, NoItinerary, "ssat", "\t$Rd, $sat_imm, $a$sh",
2358 [/* For disassembly only; pattern left blank */]> {
2363 let Inst{27-21} = 0b0110101;
2364 let Inst{5-4} = 0b01;
2365 let Inst{20-16} = sat_imm;
2366 let Inst{15-12} = Rd;
2367 let Inst{11-7} = sh{7-3};
2368 let Inst{6} = sh{0};
2372 def SSAT16 : AI<(outs GPR:$Rd), (ins i32imm:$sat_imm, GPR:$Rn), SatFrm,
2373 NoItinerary, "ssat16", "\t$Rd, $sat_imm, $Rn",
2374 [/* For disassembly only; pattern left blank */]> {
2378 let Inst{27-20} = 0b01101010;
2379 let Inst{11-4} = 0b11110011;
2380 let Inst{15-12} = Rd;
2381 let Inst{19-16} = sat_imm;
2385 def USAT : AI<(outs GPR:$Rd), (ins i32imm:$sat_imm, GPR:$a, shift_imm:$sh),
2386 SatFrm, NoItinerary, "usat", "\t$Rd, $sat_imm, $a$sh",
2387 [/* For disassembly only; pattern left blank */]> {
2392 let Inst{27-21} = 0b0110111;
2393 let Inst{5-4} = 0b01;
2394 let Inst{15-12} = Rd;
2395 let Inst{11-7} = sh{7-3};
2396 let Inst{6} = sh{0};
2397 let Inst{20-16} = sat_imm;
2401 def USAT16 : AI<(outs GPR:$Rd), (ins i32imm:$sat_imm, GPR:$a), SatFrm,
2402 NoItinerary, "usat16", "\t$Rd, $sat_imm, $a",
2403 [/* For disassembly only; pattern left blank */]> {
2407 let Inst{27-20} = 0b01101110;
2408 let Inst{11-4} = 0b11110011;
2409 let Inst{15-12} = Rd;
2410 let Inst{19-16} = sat_imm;
2414 def : ARMV6Pat<(int_arm_ssat GPR:$a, imm:$pos), (SSAT imm:$pos, GPR:$a, 0)>;
2415 def : ARMV6Pat<(int_arm_usat GPR:$a, imm:$pos), (USAT imm:$pos, GPR:$a, 0)>;
2417 //===----------------------------------------------------------------------===//
2418 // Bitwise Instructions.
2421 defm AND : AsI1_bin_irs<0b0000, "and",
2422 IIC_iBITi, IIC_iBITr, IIC_iBITsr,
2423 BinOpFrag<(and node:$LHS, node:$RHS)>, 1>;
2424 defm ORR : AsI1_bin_irs<0b1100, "orr",
2425 IIC_iBITi, IIC_iBITr, IIC_iBITsr,
2426 BinOpFrag<(or node:$LHS, node:$RHS)>, 1>;
2427 defm EOR : AsI1_bin_irs<0b0001, "eor",
2428 IIC_iBITi, IIC_iBITr, IIC_iBITsr,
2429 BinOpFrag<(xor node:$LHS, node:$RHS)>, 1>;
2430 defm BIC : AsI1_bin_irs<0b1110, "bic",
2431 IIC_iBITi, IIC_iBITr, IIC_iBITsr,
2432 BinOpFrag<(and node:$LHS, (not node:$RHS))>>;
2434 def BFC : I<(outs GPR:$Rd), (ins GPR:$src, bf_inv_mask_imm:$imm),
2435 AddrMode1, Size4Bytes, IndexModeNone, DPFrm, IIC_iUNAsi,
2436 "bfc", "\t$Rd, $imm", "$src = $Rd",
2437 [(set GPR:$Rd, (and GPR:$src, bf_inv_mask_imm:$imm))]>,
2438 Requires<[IsARM, HasV6T2]> {
2441 let Inst{27-21} = 0b0111110;
2442 let Inst{6-0} = 0b0011111;
2443 let Inst{15-12} = Rd;
2444 let Inst{11-7} = imm{4-0}; // lsb
2445 let Inst{20-16} = imm{9-5}; // width
2448 // A8.6.18 BFI - Bitfield insert (Encoding A1)
2449 def BFI : I<(outs GPR:$Rd), (ins GPR:$src, GPR:$Rn, bf_inv_mask_imm:$imm),
2450 AddrMode1, Size4Bytes, IndexModeNone, DPFrm, IIC_iUNAsi,
2451 "bfi", "\t$Rd, $Rn, $imm", "$src = $Rd",
2452 [(set GPR:$Rd, (ARMbfi GPR:$src, GPR:$Rn,
2453 bf_inv_mask_imm:$imm))]>,
2454 Requires<[IsARM, HasV6T2]> {
2458 let Inst{27-21} = 0b0111110;
2459 let Inst{6-4} = 0b001; // Rn: Inst{3-0} != 15
2460 let Inst{15-12} = Rd;
2461 let Inst{11-7} = imm{4-0}; // lsb
2462 let Inst{20-16} = imm{9-5}; // width
2466 def MVNr : AsI1<0b1111, (outs GPR:$Rd), (ins GPR:$Rm), DPFrm, IIC_iMVNr,
2467 "mvn", "\t$Rd, $Rm",
2468 [(set GPR:$Rd, (not GPR:$Rm))]>, UnaryDP {
2472 let Inst{19-16} = 0b0000;
2473 let Inst{11-4} = 0b00000000;
2474 let Inst{15-12} = Rd;
2477 def MVNs : AsI1<0b1111, (outs GPR:$Rd), (ins so_reg:$shift), DPSoRegFrm,
2478 IIC_iMVNsr, "mvn", "\t$Rd, $shift",
2479 [(set GPR:$Rd, (not so_reg:$shift))]>, UnaryDP {
2483 let Inst{19-16} = 0b0000;
2484 let Inst{15-12} = Rd;
2485 let Inst{11-0} = shift;
2487 let isReMaterializable = 1, isAsCheapAsAMove = 1, isMoveImm = 1 in
2488 def MVNi : AsI1<0b1111, (outs GPR:$Rd), (ins so_imm:$imm), DPFrm,
2489 IIC_iMVNi, "mvn", "\t$Rd, $imm",
2490 [(set GPR:$Rd, so_imm_not:$imm)]>,UnaryDP {
2494 let Inst{19-16} = 0b0000;
2495 let Inst{15-12} = Rd;
2496 let Inst{11-0} = imm;
2499 def : ARMPat<(and GPR:$src, so_imm_not:$imm),
2500 (BICri GPR:$src, so_imm_not:$imm)>;
2502 //===----------------------------------------------------------------------===//
2503 // Multiply Instructions.
2505 class AsMul1I32<bits<7> opcod, dag oops, dag iops, InstrItinClass itin,
2506 string opc, string asm, list<dag> pattern>
2507 : AsMul1I<opcod, oops, iops, itin, opc, asm, pattern> {
2511 let Inst{19-16} = Rd;
2512 let Inst{11-8} = Rm;
2515 class AsMul1I64<bits<7> opcod, dag oops, dag iops, InstrItinClass itin,
2516 string opc, string asm, list<dag> pattern>
2517 : AsMul1I<opcod, oops, iops, itin, opc, asm, pattern> {
2522 let Inst{19-16} = RdHi;
2523 let Inst{15-12} = RdLo;
2524 let Inst{11-8} = Rm;
2528 let isCommutable = 1 in
2529 def MUL : AsMul1I32<0b0000000, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm),
2530 IIC_iMUL32, "mul", "\t$Rd, $Rn, $Rm",
2531 [(set GPR:$Rd, (mul GPR:$Rn, GPR:$Rm))]>;
2533 def MLA : AsMul1I32<0b0000001, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm, GPR:$Ra),
2534 IIC_iMAC32, "mla", "\t$Rd, $Rn, $Rm, $Ra",
2535 [(set GPR:$Rd, (add (mul GPR:$Rn, GPR:$Rm), GPR:$Ra))]> {
2537 let Inst{15-12} = Ra;
2540 def MLS : AMul1I<0b0000011, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm, GPR:$Ra),
2541 IIC_iMAC32, "mls", "\t$Rd, $Rn, $Rm, $Ra",
2542 [(set GPR:$Rd, (sub GPR:$Ra, (mul GPR:$Rn, GPR:$Rm)))]>,
2543 Requires<[IsARM, HasV6T2]> {
2548 let Inst{19-16} = Rd;
2549 let Inst{15-12} = Ra;
2550 let Inst{11-8} = Rm;
2554 // Extra precision multiplies with low / high results
2556 let neverHasSideEffects = 1 in {
2557 let isCommutable = 1 in {
2558 def SMULL : AsMul1I64<0b0000110, (outs GPR:$RdLo, GPR:$RdHi),
2559 (ins GPR:$Rn, GPR:$Rm), IIC_iMUL64,
2560 "smull", "\t$RdLo, $RdHi, $Rn, $Rm", []>;
2562 def UMULL : AsMul1I64<0b0000100, (outs GPR:$RdLo, GPR:$RdHi),
2563 (ins GPR:$Rn, GPR:$Rm), IIC_iMUL64,
2564 "umull", "\t$RdLo, $RdHi, $Rn, $Rm", []>;
2567 // Multiply + accumulate
2568 def SMLAL : AsMul1I64<0b0000111, (outs GPR:$RdLo, GPR:$RdHi),
2569 (ins GPR:$Rn, GPR:$Rm), IIC_iMAC64,
2570 "smlal", "\t$RdLo, $RdHi, $Rn, $Rm", []>;
2572 def UMLAL : AsMul1I64<0b0000101, (outs GPR:$RdLo, GPR:$RdHi),
2573 (ins GPR:$Rn, GPR:$Rm), IIC_iMAC64,
2574 "umlal", "\t$RdLo, $RdHi, $Rn, $Rm", []>;
2576 def UMAAL : AMul1I <0b0000010, (outs GPR:$RdLo, GPR:$RdHi),
2577 (ins GPR:$Rn, GPR:$Rm), IIC_iMAC64,
2578 "umaal", "\t$RdLo, $RdHi, $Rn, $Rm", []>,
2579 Requires<[IsARM, HasV6]> {
2584 let Inst{19-16} = RdLo;
2585 let Inst{15-12} = RdHi;
2586 let Inst{11-8} = Rm;
2589 } // neverHasSideEffects
2591 // Most significant word multiply
2592 def SMMUL : AMul2I <0b0111010, 0b0001, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm),
2593 IIC_iMUL32, "smmul", "\t$Rd, $Rn, $Rm",
2594 [(set GPR:$Rd, (mulhs GPR:$Rn, GPR:$Rm))]>,
2595 Requires<[IsARM, HasV6]> {
2596 let Inst{15-12} = 0b1111;
2599 def SMMULR : AMul2I <0b0111010, 0b0011, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm),
2600 IIC_iMUL32, "smmulr", "\t$Rd, $Rn, $Rm",
2601 [/* For disassembly only; pattern left blank */]>,
2602 Requires<[IsARM, HasV6]> {
2603 let Inst{15-12} = 0b1111;
2606 def SMMLA : AMul2Ia <0b0111010, 0b0001, (outs GPR:$Rd),
2607 (ins GPR:$Rn, GPR:$Rm, GPR:$Ra),
2608 IIC_iMAC32, "smmla", "\t$Rd, $Rn, $Rm, $Ra",
2609 [(set GPR:$Rd, (add (mulhs GPR:$Rn, GPR:$Rm), GPR:$Ra))]>,
2610 Requires<[IsARM, HasV6]>;
2612 def SMMLAR : AMul2Ia <0b0111010, 0b0011, (outs GPR:$Rd),
2613 (ins GPR:$Rn, GPR:$Rm, GPR:$Ra),
2614 IIC_iMAC32, "smmlar", "\t$Rd, $Rn, $Rm, $Ra",
2615 [/* For disassembly only; pattern left blank */]>,
2616 Requires<[IsARM, HasV6]>;
2618 def SMMLS : AMul2Ia <0b0111010, 0b1101, (outs GPR:$Rd),
2619 (ins GPR:$Rn, GPR:$Rm, GPR:$Ra),
2620 IIC_iMAC32, "smmls", "\t$Rd, $Rn, $Rm, $Ra",
2621 [(set GPR:$Rd, (sub GPR:$Ra, (mulhs GPR:$Rn, GPR:$Rm)))]>,
2622 Requires<[IsARM, HasV6]>;
2624 def SMMLSR : AMul2Ia <0b0111010, 0b1111, (outs GPR:$Rd),
2625 (ins GPR:$Rn, GPR:$Rm, GPR:$Ra),
2626 IIC_iMAC32, "smmlsr", "\t$Rd, $Rn, $Rm, $Ra",
2627 [/* For disassembly only; pattern left blank */]>,
2628 Requires<[IsARM, HasV6]>;
2630 multiclass AI_smul<string opc, PatFrag opnode> {
2631 def BB : AMulxyI<0b0001011, 0b00, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm),
2632 IIC_iMUL16, !strconcat(opc, "bb"), "\t$Rd, $Rn, $Rm",
2633 [(set GPR:$Rd, (opnode (sext_inreg GPR:$Rn, i16),
2634 (sext_inreg GPR:$Rm, i16)))]>,
2635 Requires<[IsARM, HasV5TE]>;
2637 def BT : AMulxyI<0b0001011, 0b10, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm),
2638 IIC_iMUL16, !strconcat(opc, "bt"), "\t$Rd, $Rn, $Rm",
2639 [(set GPR:$Rd, (opnode (sext_inreg GPR:$Rn, i16),
2640 (sra GPR:$Rm, (i32 16))))]>,
2641 Requires<[IsARM, HasV5TE]>;
2643 def TB : AMulxyI<0b0001011, 0b01, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm),
2644 IIC_iMUL16, !strconcat(opc, "tb"), "\t$Rd, $Rn, $Rm",
2645 [(set GPR:$Rd, (opnode (sra GPR:$Rn, (i32 16)),
2646 (sext_inreg GPR:$Rm, i16)))]>,
2647 Requires<[IsARM, HasV5TE]>;
2649 def TT : AMulxyI<0b0001011, 0b11, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm),
2650 IIC_iMUL16, !strconcat(opc, "tt"), "\t$Rd, $Rn, $Rm",
2651 [(set GPR:$Rd, (opnode (sra GPR:$Rn, (i32 16)),
2652 (sra GPR:$Rm, (i32 16))))]>,
2653 Requires<[IsARM, HasV5TE]>;
2655 def WB : AMulxyI<0b0001001, 0b01, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm),
2656 IIC_iMUL16, !strconcat(opc, "wb"), "\t$Rd, $Rn, $Rm",
2657 [(set GPR:$Rd, (sra (opnode GPR:$Rn,
2658 (sext_inreg GPR:$Rm, i16)), (i32 16)))]>,
2659 Requires<[IsARM, HasV5TE]>;
2661 def WT : AMulxyI<0b0001001, 0b11, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm),
2662 IIC_iMUL16, !strconcat(opc, "wt"), "\t$Rd, $Rn, $Rm",
2663 [(set GPR:$Rd, (sra (opnode GPR:$Rn,
2664 (sra GPR:$Rm, (i32 16))), (i32 16)))]>,
2665 Requires<[IsARM, HasV5TE]>;
2669 multiclass AI_smla<string opc, PatFrag opnode> {
2670 def BB : AMulxyIa<0b0001000, 0b00, (outs GPR:$Rd),
2671 (ins GPR:$Rn, GPR:$Rm, GPR:$Ra),
2672 IIC_iMAC16, !strconcat(opc, "bb"), "\t$Rd, $Rn, $Rm, $Ra",
2673 [(set GPR:$Rd, (add GPR:$Ra,
2674 (opnode (sext_inreg GPR:$Rn, i16),
2675 (sext_inreg GPR:$Rm, i16))))]>,
2676 Requires<[IsARM, HasV5TE]>;
2678 def BT : AMulxyIa<0b0001000, 0b10, (outs GPR:$Rd),
2679 (ins GPR:$Rn, GPR:$Rm, GPR:$Ra),
2680 IIC_iMAC16, !strconcat(opc, "bt"), "\t$Rd, $Rn, $Rm, $Ra",
2681 [(set GPR:$Rd, (add GPR:$Ra, (opnode (sext_inreg GPR:$Rn, i16),
2682 (sra GPR:$Rm, (i32 16)))))]>,
2683 Requires<[IsARM, HasV5TE]>;
2685 def TB : AMulxyIa<0b0001000, 0b01, (outs GPR:$Rd),
2686 (ins GPR:$Rn, GPR:$Rm, GPR:$Ra),
2687 IIC_iMAC16, !strconcat(opc, "tb"), "\t$Rd, $Rn, $Rm, $Ra",
2688 [(set GPR:$Rd, (add GPR:$Ra, (opnode (sra GPR:$Rn, (i32 16)),
2689 (sext_inreg GPR:$Rm, i16))))]>,
2690 Requires<[IsARM, HasV5TE]>;
2692 def TT : AMulxyIa<0b0001000, 0b11, (outs GPR:$Rd),
2693 (ins GPR:$Rn, GPR:$Rm, GPR:$Ra),
2694 IIC_iMAC16, !strconcat(opc, "tt"), "\t$Rd, $Rn, $Rm, $Ra",
2695 [(set GPR:$Rd, (add GPR:$Ra, (opnode (sra GPR:$Rn, (i32 16)),
2696 (sra GPR:$Rm, (i32 16)))))]>,
2697 Requires<[IsARM, HasV5TE]>;
2699 def WB : AMulxyIa<0b0001001, 0b00, (outs GPR:$Rd),
2700 (ins GPR:$Rn, GPR:$Rm, GPR:$Ra),
2701 IIC_iMAC16, !strconcat(opc, "wb"), "\t$Rd, $Rn, $Rm, $Ra",
2702 [(set GPR:$Rd, (add GPR:$Ra, (sra (opnode GPR:$Rn,
2703 (sext_inreg GPR:$Rm, i16)), (i32 16))))]>,
2704 Requires<[IsARM, HasV5TE]>;
2706 def WT : AMulxyIa<0b0001001, 0b10, (outs GPR:$Rd),
2707 (ins GPR:$Rn, GPR:$Rm, GPR:$Ra),
2708 IIC_iMAC16, !strconcat(opc, "wt"), "\t$Rd, $Rn, $Rm, $Ra",
2709 [(set GPR:$Rd, (add GPR:$Ra, (sra (opnode GPR:$Rn,
2710 (sra GPR:$Rm, (i32 16))), (i32 16))))]>,
2711 Requires<[IsARM, HasV5TE]>;
2714 defm SMUL : AI_smul<"smul", BinOpFrag<(mul node:$LHS, node:$RHS)>>;
2715 defm SMLA : AI_smla<"smla", BinOpFrag<(mul node:$LHS, node:$RHS)>>;
2717 // Halfword multiply accumulate long: SMLAL<x><y> -- for disassembly only
2718 def SMLALBB : AMulxyI64<0b0001010, 0b00, (outs GPR:$RdLo, GPR:$RdHi),
2719 (ins GPR:$Rn, GPR:$Rm),
2720 IIC_iMAC64, "smlalbb", "\t$RdLo, $RdHi, $Rn, $Rm",
2721 [/* For disassembly only; pattern left blank */]>,
2722 Requires<[IsARM, HasV5TE]>;
2724 def SMLALBT : AMulxyI64<0b0001010, 0b10, (outs GPR:$RdLo, GPR:$RdHi),
2725 (ins GPR:$Rn, GPR:$Rm),
2726 IIC_iMAC64, "smlalbt", "\t$RdLo, $RdHi, $Rn, $Rm",
2727 [/* For disassembly only; pattern left blank */]>,
2728 Requires<[IsARM, HasV5TE]>;
2730 def SMLALTB : AMulxyI64<0b0001010, 0b01, (outs GPR:$RdLo, GPR:$RdHi),
2731 (ins GPR:$Rn, GPR:$Rm),
2732 IIC_iMAC64, "smlaltb", "\t$RdLo, $RdHi, $Rn, $Rm",
2733 [/* For disassembly only; pattern left blank */]>,
2734 Requires<[IsARM, HasV5TE]>;
2736 def SMLALTT : AMulxyI64<0b0001010, 0b11, (outs GPR:$RdLo, GPR:$RdHi),
2737 (ins GPR:$Rn, GPR:$Rm),
2738 IIC_iMAC64, "smlaltt", "\t$RdLo, $RdHi, $Rn, $Rm",
2739 [/* For disassembly only; pattern left blank */]>,
2740 Requires<[IsARM, HasV5TE]>;
2742 // Helper class for AI_smld -- for disassembly only
2743 class AMulDualIbase<bit long, bit sub, bit swap, dag oops, dag iops,
2744 InstrItinClass itin, string opc, string asm>
2745 : AI<oops, iops, MulFrm, itin, opc, asm, []>, Requires<[IsARM, HasV6]> {
2752 let Inst{21-20} = 0b00;
2753 let Inst{22} = long;
2754 let Inst{27-23} = 0b01110;
2755 let Inst{11-8} = Rm;
2758 class AMulDualI<bit long, bit sub, bit swap, dag oops, dag iops,
2759 InstrItinClass itin, string opc, string asm>
2760 : AMulDualIbase<long, sub, swap, oops, iops, itin, opc, asm> {
2762 let Inst{15-12} = 0b1111;
2763 let Inst{19-16} = Rd;
2765 class AMulDualIa<bit long, bit sub, bit swap, dag oops, dag iops,
2766 InstrItinClass itin, string opc, string asm>
2767 : AMulDualIbase<long, sub, swap, oops, iops, itin, opc, asm> {
2769 let Inst{15-12} = Ra;
2771 class AMulDualI64<bit long, bit sub, bit swap, dag oops, dag iops,
2772 InstrItinClass itin, string opc, string asm>
2773 : AMulDualIbase<long, sub, swap, oops, iops, itin, opc, asm> {
2776 let Inst{19-16} = RdHi;
2777 let Inst{15-12} = RdLo;
2780 multiclass AI_smld<bit sub, string opc> {
2782 def D : AMulDualIa<0, sub, 0, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm, GPR:$Ra),
2783 NoItinerary, !strconcat(opc, "d"), "\t$Rd, $Rn, $Rm, $Ra">;
2785 def DX: AMulDualIa<0, sub, 1, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm, GPR:$Ra),
2786 NoItinerary, !strconcat(opc, "dx"), "\t$Rd, $Rn, $Rm, $Ra">;
2788 def LD: AMulDualI64<1, sub, 0, (outs GPR:$RdLo,GPR:$RdHi),
2789 (ins GPR:$Rn, GPR:$Rm), NoItinerary,
2790 !strconcat(opc, "ld"), "\t$RdLo, $RdHi, $Rn, $Rm">;
2792 def LDX : AMulDualI64<1, sub, 1, (outs GPR:$RdLo,GPR:$RdHi),
2793 (ins GPR:$Rn, GPR:$Rm), NoItinerary,
2794 !strconcat(opc, "ldx"),"\t$RdLo, $RdHi, $Rn, $Rm">;
2798 defm SMLA : AI_smld<0, "smla">;
2799 defm SMLS : AI_smld<1, "smls">;
2801 multiclass AI_sdml<bit sub, string opc> {
2803 def D : AMulDualI<0, sub, 0, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm),
2804 NoItinerary, !strconcat(opc, "d"), "\t$Rd, $Rn, $Rm">;
2805 def DX : AMulDualI<0, sub, 1, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm),
2806 NoItinerary, !strconcat(opc, "dx"), "\t$Rd, $Rn, $Rm">;
2809 defm SMUA : AI_sdml<0, "smua">;
2810 defm SMUS : AI_sdml<1, "smus">;
2812 //===----------------------------------------------------------------------===//
2813 // Misc. Arithmetic Instructions.
2816 def CLZ : AMiscA1I<0b000010110, 0b0001, (outs GPR:$Rd), (ins GPR:$Rm),
2817 IIC_iUNAr, "clz", "\t$Rd, $Rm",
2818 [(set GPR:$Rd, (ctlz GPR:$Rm))]>, Requires<[IsARM, HasV5T]>;
2820 def RBIT : AMiscA1I<0b01101111, 0b0011, (outs GPR:$Rd), (ins GPR:$Rm),
2821 IIC_iUNAr, "rbit", "\t$Rd, $Rm",
2822 [(set GPR:$Rd, (ARMrbit GPR:$Rm))]>,
2823 Requires<[IsARM, HasV6T2]>;
2825 def REV : AMiscA1I<0b01101011, 0b0011, (outs GPR:$Rd), (ins GPR:$Rm),
2826 IIC_iUNAr, "rev", "\t$Rd, $Rm",
2827 [(set GPR:$Rd, (bswap GPR:$Rm))]>, Requires<[IsARM, HasV6]>;
2829 def REV16 : AMiscA1I<0b01101011, 0b1011, (outs GPR:$Rd), (ins GPR:$Rm),
2830 IIC_iUNAr, "rev16", "\t$Rd, $Rm",
2832 (or (and (srl GPR:$Rm, (i32 8)), 0xFF),
2833 (or (and (shl GPR:$Rm, (i32 8)), 0xFF00),
2834 (or (and (srl GPR:$Rm, (i32 8)), 0xFF0000),
2835 (and (shl GPR:$Rm, (i32 8)), 0xFF000000)))))]>,
2836 Requires<[IsARM, HasV6]>;
2838 def REVSH : AMiscA1I<0b01101111, 0b1011, (outs GPR:$Rd), (ins GPR:$Rm),
2839 IIC_iUNAr, "revsh", "\t$Rd, $Rm",
2842 (or (srl (and GPR:$Rm, 0xFF00), (i32 8)),
2843 (shl GPR:$Rm, (i32 8))), i16))]>,
2844 Requires<[IsARM, HasV6]>;
2846 def lsl_shift_imm : SDNodeXForm<imm, [{
2847 unsigned Sh = ARM_AM::getSORegOpc(ARM_AM::lsl, N->getZExtValue());
2848 return CurDAG->getTargetConstant(Sh, MVT::i32);
2851 def lsl_amt : PatLeaf<(i32 imm), [{
2852 return (N->getZExtValue() < 32);
2855 def PKHBT : APKHI<0b01101000, 0, (outs GPR:$Rd),
2856 (ins GPR:$Rn, GPR:$Rm, shift_imm:$sh),
2857 IIC_iALUsi, "pkhbt", "\t$Rd, $Rn, $Rm$sh",
2858 [(set GPR:$Rd, (or (and GPR:$Rn, 0xFFFF),
2859 (and (shl GPR:$Rm, lsl_amt:$sh),
2861 Requires<[IsARM, HasV6]>;
2863 // Alternate cases for PKHBT where identities eliminate some nodes.
2864 def : ARMV6Pat<(or (and GPR:$Rn, 0xFFFF), (and GPR:$Rm, 0xFFFF0000)),
2865 (PKHBT GPR:$Rn, GPR:$Rm, 0)>;
2866 def : ARMV6Pat<(or (and GPR:$Rn, 0xFFFF), (shl GPR:$Rm, imm16_31:$sh)),
2867 (PKHBT GPR:$Rn, GPR:$Rm, (lsl_shift_imm imm16_31:$sh))>;
2869 def asr_shift_imm : SDNodeXForm<imm, [{
2870 unsigned Sh = ARM_AM::getSORegOpc(ARM_AM::asr, N->getZExtValue());
2871 return CurDAG->getTargetConstant(Sh, MVT::i32);
2874 def asr_amt : PatLeaf<(i32 imm), [{
2875 return (N->getZExtValue() <= 32);
2878 // Note: Shifts of 1-15 bits will be transformed to srl instead of sra and
2879 // will match the pattern below.
2880 def PKHTB : APKHI<0b01101000, 1, (outs GPR:$Rd),
2881 (ins GPR:$Rn, GPR:$Rm, shift_imm:$sh),
2882 IIC_iBITsi, "pkhtb", "\t$Rd, $Rn, $Rm$sh",
2883 [(set GPR:$Rd, (or (and GPR:$Rn, 0xFFFF0000),
2884 (and (sra GPR:$Rm, asr_amt:$sh),
2886 Requires<[IsARM, HasV6]>;
2888 // Alternate cases for PKHTB where identities eliminate some nodes. Note that
2889 // a shift amount of 0 is *not legal* here, it is PKHBT instead.
2890 def : ARMV6Pat<(or (and GPR:$src1, 0xFFFF0000), (srl GPR:$src2, imm16_31:$sh)),
2891 (PKHTB GPR:$src1, GPR:$src2, (asr_shift_imm imm16_31:$sh))>;
2892 def : ARMV6Pat<(or (and GPR:$src1, 0xFFFF0000),
2893 (and (srl GPR:$src2, imm1_15:$sh), 0xFFFF)),
2894 (PKHTB GPR:$src1, GPR:$src2, (asr_shift_imm imm1_15:$sh))>;
2896 //===----------------------------------------------------------------------===//
2897 // Comparison Instructions...
2900 defm CMP : AI1_cmp_irs<0b1010, "cmp",
2901 IIC_iCMPi, IIC_iCMPr, IIC_iCMPsr,
2902 BinOpFrag<(ARMcmp node:$LHS, node:$RHS)>>;
2904 // ARMcmpZ can re-use the above instruction definitions.
2905 def : ARMPat<(ARMcmpZ GPR:$src, so_imm:$imm),
2906 (CMPri GPR:$src, so_imm:$imm)>;
2907 def : ARMPat<(ARMcmpZ GPR:$src, GPR:$rhs),
2908 (CMPrr GPR:$src, GPR:$rhs)>;
2909 def : ARMPat<(ARMcmpZ GPR:$src, so_reg:$rhs),
2910 (CMPrs GPR:$src, so_reg:$rhs)>;
2912 // FIXME: We have to be careful when using the CMN instruction and comparison
2913 // with 0. One would expect these two pieces of code should give identical
2929 // However, the CMN gives the *opposite* result when r1 is 0. This is because
2930 // the carry flag is set in the CMP case but not in the CMN case. In short, the
2931 // CMP instruction doesn't perform a truncate of the (logical) NOT of 0 plus the
2932 // value of r0 and the carry bit (because the "carry bit" parameter to
2933 // AddWithCarry is defined as 1 in this case, the carry flag will always be set
2934 // when r0 >= 0). The CMN instruction doesn't perform a NOT of 0 so there is
2935 // never a "carry" when this AddWithCarry is performed (because the "carry bit"
2936 // parameter to AddWithCarry is defined as 0).
2938 // When x is 0 and unsigned:
2942 // ~x + 1 = 0x1 0000 0000
2943 // (-x = 0) != (0x1 0000 0000 = ~x + 1)
2945 // Therefore, we should disable CMN when comparing against zero, until we can
2946 // limit when the CMN instruction is used (when we know that the RHS is not 0 or
2947 // when it's a comparison which doesn't look at the 'carry' flag).
2949 // (See the ARM docs for the "AddWithCarry" pseudo-code.)
2951 // This is related to <rdar://problem/7569620>.
2953 //defm CMN : AI1_cmp_irs<0b1011, "cmn",
2954 // BinOpFrag<(ARMcmp node:$LHS,(ineg node:$RHS))>>;
2956 // Note that TST/TEQ don't set all the same flags that CMP does!
2957 defm TST : AI1_cmp_irs<0b1000, "tst",
2958 IIC_iTSTi, IIC_iTSTr, IIC_iTSTsr,
2959 BinOpFrag<(ARMcmpZ (and_su node:$LHS, node:$RHS), 0)>, 1>;
2960 defm TEQ : AI1_cmp_irs<0b1001, "teq",
2961 IIC_iTSTi, IIC_iTSTr, IIC_iTSTsr,
2962 BinOpFrag<(ARMcmpZ (xor_su node:$LHS, node:$RHS), 0)>, 1>;
2964 defm CMNz : AI1_cmp_irs<0b1011, "cmn",
2965 IIC_iCMPi, IIC_iCMPr, IIC_iCMPsr,
2966 BinOpFrag<(ARMcmpZ node:$LHS,(ineg node:$RHS))>>;
2968 //def : ARMPat<(ARMcmp GPR:$src, so_imm_neg:$imm),
2969 // (CMNri GPR:$src, so_imm_neg:$imm)>;
2971 def : ARMPat<(ARMcmpZ GPR:$src, so_imm_neg:$imm),
2972 (CMNzri GPR:$src, so_imm_neg:$imm)>;
2974 // Pseudo i64 compares for some floating point compares.
2975 let usesCustomInserter = 1, isBranch = 1, isTerminator = 1,
2977 def BCCi64 : PseudoInst<(outs),
2978 (ins i32imm:$cc, GPR:$lhs1, GPR:$lhs2, GPR:$rhs1, GPR:$rhs2, brtarget:$dst),
2980 [(ARMBcci64 imm:$cc, GPR:$lhs1, GPR:$lhs2, GPR:$rhs1, GPR:$rhs2, bb:$dst)]>;
2982 def BCCZi64 : PseudoInst<(outs),
2983 (ins i32imm:$cc, GPR:$lhs1, GPR:$lhs2, brtarget:$dst), IIC_Br,
2984 [(ARMBcci64 imm:$cc, GPR:$lhs1, GPR:$lhs2, 0, 0, bb:$dst)]>;
2985 } // usesCustomInserter
2988 // Conditional moves
2989 // FIXME: should be able to write a pattern for ARMcmov, but can't use
2990 // a two-value operand where a dag node expects two operands. :(
2991 // FIXME: These should all be pseudo-instructions that get expanded to
2992 // the normal MOV instructions. That would fix the dependency on
2993 // special casing them in tblgen.
2994 let neverHasSideEffects = 1 in {
2995 def MOVCCr : AI1<0b1101, (outs GPR:$Rd), (ins GPR:$false, GPR:$Rm), DPFrm,
2996 IIC_iCMOVr, "mov", "\t$Rd, $Rm",
2997 [/*(set GPR:$Rd, (ARMcmov GPR:$false, GPR:$Rm, imm:$cc, CCR:$ccr))*/]>,
2998 RegConstraint<"$false = $Rd">, UnaryDP {
3003 let Inst{15-12} = Rd;
3004 let Inst{11-4} = 0b00000000;
3008 def MOVCCs : AI1<0b1101, (outs GPR:$Rd),
3009 (ins GPR:$false, so_reg:$shift), DPSoRegFrm, IIC_iCMOVsr,
3010 "mov", "\t$Rd, $shift",
3011 [/*(set GPR:$Rd, (ARMcmov GPR:$false, so_reg:$shift, imm:$cc, CCR:$ccr))*/]>,
3012 RegConstraint<"$false = $Rd">, UnaryDP {
3017 let Inst{19-16} = 0;
3018 let Inst{15-12} = Rd;
3019 let Inst{11-0} = shift;
3022 let isMoveImm = 1 in
3023 def MOVCCi16 : AI1<0b1000, (outs GPR:$Rd), (ins GPR:$false, movt_imm:$imm),
3025 "movw", "\t$Rd, $imm",
3027 RegConstraint<"$false = $Rd">, Requires<[IsARM, HasV6T2]>,
3033 let Inst{19-16} = imm{15-12};
3034 let Inst{15-12} = Rd;
3035 let Inst{11-0} = imm{11-0};
3038 let isMoveImm = 1 in
3039 def MOVCCi : AI1<0b1101, (outs GPR:$Rd),
3040 (ins GPR:$false, so_imm:$imm), DPFrm, IIC_iCMOVi,
3041 "mov", "\t$Rd, $imm",
3042 [/*(set GPR:$Rd, (ARMcmov GPR:$false, so_imm:$imm, imm:$cc, CCR:$ccr))*/]>,
3043 RegConstraint<"$false = $Rd">, UnaryDP {
3048 let Inst{19-16} = 0b0000;
3049 let Inst{15-12} = Rd;
3050 let Inst{11-0} = imm;
3053 // Two instruction predicate mov immediate.
3054 let isMoveImm = 1 in
3055 def MOVCCi32imm : PseudoInst<(outs GPR:$Rd),
3056 (ins GPR:$false, i32imm:$src, pred:$p),
3057 IIC_iCMOVix2, []>, RegConstraint<"$false = $Rd">;
3059 let isMoveImm = 1 in
3060 def MVNCCi : AI1<0b1111, (outs GPR:$Rd),
3061 (ins GPR:$false, so_imm:$imm), DPFrm, IIC_iCMOVi,
3062 "mvn", "\t$Rd, $imm",
3063 [/*(set GPR:$Rd, (ARMcmov GPR:$false, so_imm_not:$imm, imm:$cc, CCR:$ccr))*/]>,
3064 RegConstraint<"$false = $Rd">, UnaryDP {
3069 let Inst{19-16} = 0b0000;
3070 let Inst{15-12} = Rd;
3071 let Inst{11-0} = imm;
3073 } // neverHasSideEffects
3075 //===----------------------------------------------------------------------===//
3076 // Atomic operations intrinsics
3079 def memb_opt : Operand<i32> {
3080 let PrintMethod = "printMemBOption";
3083 // memory barriers protect the atomic sequences
3084 let hasSideEffects = 1 in {
3085 def DMB : AInoP<(outs), (ins memb_opt:$opt), MiscFrm, NoItinerary,
3086 "dmb", "\t$opt", [(ARMMemBarrier (i32 imm:$opt))]>,
3087 Requires<[IsARM, HasDB]> {
3089 let Inst{31-4} = 0xf57ff05;
3090 let Inst{3-0} = opt;
3093 def DMB_MCR : AInoP<(outs), (ins GPR:$zero), MiscFrm, NoItinerary,
3094 "mcr", "\tp15, 0, $zero, c7, c10, 5",
3095 [(ARMMemBarrierMCR GPR:$zero)]>,
3096 Requires<[IsARM, HasV6]> {
3097 // FIXME: add encoding
3101 def DSB : AInoP<(outs), (ins memb_opt:$opt), MiscFrm, NoItinerary,
3103 [/* For disassembly only; pattern left blank */]>,
3104 Requires<[IsARM, HasDB]> {
3106 let Inst{31-4} = 0xf57ff04;
3107 let Inst{3-0} = opt;
3110 // ISB has only full system option -- for disassembly only
3111 def ISB : AInoP<(outs), (ins), MiscFrm, NoItinerary, "isb", "", []>,
3112 Requires<[IsARM, HasDB]> {
3113 let Inst{31-4} = 0xf57ff06;
3114 let Inst{3-0} = 0b1111;
3117 let usesCustomInserter = 1 in {
3118 let Uses = [CPSR] in {
3119 def ATOMIC_LOAD_ADD_I8 : PseudoInst<
3120 (outs GPR:$dst), (ins GPR:$ptr, GPR:$incr), NoItinerary,
3121 [(set GPR:$dst, (atomic_load_add_8 GPR:$ptr, GPR:$incr))]>;
3122 def ATOMIC_LOAD_SUB_I8 : PseudoInst<
3123 (outs GPR:$dst), (ins GPR:$ptr, GPR:$incr), NoItinerary,
3124 [(set GPR:$dst, (atomic_load_sub_8 GPR:$ptr, GPR:$incr))]>;
3125 def ATOMIC_LOAD_AND_I8 : PseudoInst<
3126 (outs GPR:$dst), (ins GPR:$ptr, GPR:$incr), NoItinerary,
3127 [(set GPR:$dst, (atomic_load_and_8 GPR:$ptr, GPR:$incr))]>;
3128 def ATOMIC_LOAD_OR_I8 : PseudoInst<
3129 (outs GPR:$dst), (ins GPR:$ptr, GPR:$incr), NoItinerary,
3130 [(set GPR:$dst, (atomic_load_or_8 GPR:$ptr, GPR:$incr))]>;
3131 def ATOMIC_LOAD_XOR_I8 : PseudoInst<
3132 (outs GPR:$dst), (ins GPR:$ptr, GPR:$incr), NoItinerary,
3133 [(set GPR:$dst, (atomic_load_xor_8 GPR:$ptr, GPR:$incr))]>;
3134 def ATOMIC_LOAD_NAND_I8 : PseudoInst<
3135 (outs GPR:$dst), (ins GPR:$ptr, GPR:$incr), NoItinerary,
3136 [(set GPR:$dst, (atomic_load_nand_8 GPR:$ptr, GPR:$incr))]>;
3137 def ATOMIC_LOAD_ADD_I16 : PseudoInst<
3138 (outs GPR:$dst), (ins GPR:$ptr, GPR:$incr), NoItinerary,
3139 [(set GPR:$dst, (atomic_load_add_16 GPR:$ptr, GPR:$incr))]>;
3140 def ATOMIC_LOAD_SUB_I16 : PseudoInst<
3141 (outs GPR:$dst), (ins GPR:$ptr, GPR:$incr), NoItinerary,
3142 [(set GPR:$dst, (atomic_load_sub_16 GPR:$ptr, GPR:$incr))]>;
3143 def ATOMIC_LOAD_AND_I16 : PseudoInst<
3144 (outs GPR:$dst), (ins GPR:$ptr, GPR:$incr), NoItinerary,
3145 [(set GPR:$dst, (atomic_load_and_16 GPR:$ptr, GPR:$incr))]>;
3146 def ATOMIC_LOAD_OR_I16 : PseudoInst<
3147 (outs GPR:$dst), (ins GPR:$ptr, GPR:$incr), NoItinerary,
3148 [(set GPR:$dst, (atomic_load_or_16 GPR:$ptr, GPR:$incr))]>;
3149 def ATOMIC_LOAD_XOR_I16 : PseudoInst<
3150 (outs GPR:$dst), (ins GPR:$ptr, GPR:$incr), NoItinerary,
3151 [(set GPR:$dst, (atomic_load_xor_16 GPR:$ptr, GPR:$incr))]>;
3152 def ATOMIC_LOAD_NAND_I16 : PseudoInst<
3153 (outs GPR:$dst), (ins GPR:$ptr, GPR:$incr), NoItinerary,
3154 [(set GPR:$dst, (atomic_load_nand_16 GPR:$ptr, GPR:$incr))]>;
3155 def ATOMIC_LOAD_ADD_I32 : PseudoInst<
3156 (outs GPR:$dst), (ins GPR:$ptr, GPR:$incr), NoItinerary,
3157 [(set GPR:$dst, (atomic_load_add_32 GPR:$ptr, GPR:$incr))]>;
3158 def ATOMIC_LOAD_SUB_I32 : PseudoInst<
3159 (outs GPR:$dst), (ins GPR:$ptr, GPR:$incr), NoItinerary,
3160 [(set GPR:$dst, (atomic_load_sub_32 GPR:$ptr, GPR:$incr))]>;
3161 def ATOMIC_LOAD_AND_I32 : PseudoInst<
3162 (outs GPR:$dst), (ins GPR:$ptr, GPR:$incr), NoItinerary,
3163 [(set GPR:$dst, (atomic_load_and_32 GPR:$ptr, GPR:$incr))]>;
3164 def ATOMIC_LOAD_OR_I32 : PseudoInst<
3165 (outs GPR:$dst), (ins GPR:$ptr, GPR:$incr), NoItinerary,
3166 [(set GPR:$dst, (atomic_load_or_32 GPR:$ptr, GPR:$incr))]>;
3167 def ATOMIC_LOAD_XOR_I32 : PseudoInst<
3168 (outs GPR:$dst), (ins GPR:$ptr, GPR:$incr), NoItinerary,
3169 [(set GPR:$dst, (atomic_load_xor_32 GPR:$ptr, GPR:$incr))]>;
3170 def ATOMIC_LOAD_NAND_I32 : PseudoInst<
3171 (outs GPR:$dst), (ins GPR:$ptr, GPR:$incr), NoItinerary,
3172 [(set GPR:$dst, (atomic_load_nand_32 GPR:$ptr, GPR:$incr))]>;
3174 def ATOMIC_SWAP_I8 : PseudoInst<
3175 (outs GPR:$dst), (ins GPR:$ptr, GPR:$new), NoItinerary,
3176 [(set GPR:$dst, (atomic_swap_8 GPR:$ptr, GPR:$new))]>;
3177 def ATOMIC_SWAP_I16 : PseudoInst<
3178 (outs GPR:$dst), (ins GPR:$ptr, GPR:$new), NoItinerary,
3179 [(set GPR:$dst, (atomic_swap_16 GPR:$ptr, GPR:$new))]>;
3180 def ATOMIC_SWAP_I32 : PseudoInst<
3181 (outs GPR:$dst), (ins GPR:$ptr, GPR:$new), NoItinerary,
3182 [(set GPR:$dst, (atomic_swap_32 GPR:$ptr, GPR:$new))]>;
3184 def ATOMIC_CMP_SWAP_I8 : PseudoInst<
3185 (outs GPR:$dst), (ins GPR:$ptr, GPR:$old, GPR:$new), NoItinerary,
3186 [(set GPR:$dst, (atomic_cmp_swap_8 GPR:$ptr, GPR:$old, GPR:$new))]>;
3187 def ATOMIC_CMP_SWAP_I16 : PseudoInst<
3188 (outs GPR:$dst), (ins GPR:$ptr, GPR:$old, GPR:$new), NoItinerary,
3189 [(set GPR:$dst, (atomic_cmp_swap_16 GPR:$ptr, GPR:$old, GPR:$new))]>;
3190 def ATOMIC_CMP_SWAP_I32 : PseudoInst<
3191 (outs GPR:$dst), (ins GPR:$ptr, GPR:$old, GPR:$new), NoItinerary,
3192 [(set GPR:$dst, (atomic_cmp_swap_32 GPR:$ptr, GPR:$old, GPR:$new))]>;
3196 let mayLoad = 1 in {
3197 def LDREXB : AIldrex<0b10, (outs GPR:$Rt), (ins GPR:$Rn), NoItinerary,
3198 "ldrexb", "\t$Rt, [$Rn]",
3200 def LDREXH : AIldrex<0b11, (outs GPR:$Rt), (ins GPR:$Rn), NoItinerary,
3201 "ldrexh", "\t$Rt, [$Rn]",
3203 def LDREX : AIldrex<0b00, (outs GPR:$Rt), (ins GPR:$Rn), NoItinerary,
3204 "ldrex", "\t$Rt, [$Rn]",
3206 def LDREXD : AIldrex<0b01, (outs GPR:$Rt, GPR:$Rt2), (ins GPR:$Rn),
3208 "ldrexd", "\t$Rt, $Rt2, [$Rn]",
3212 let mayStore = 1, Constraints = "@earlyclobber $Rd" in {
3213 def STREXB : AIstrex<0b10, (outs GPR:$Rd), (ins GPR:$src, GPR:$Rn),
3215 "strexb", "\t$Rd, $src, [$Rn]",
3217 def STREXH : AIstrex<0b11, (outs GPR:$Rd), (ins GPR:$Rt, GPR:$Rn),
3219 "strexh", "\t$Rd, $Rt, [$Rn]",
3221 def STREX : AIstrex<0b00, (outs GPR:$Rd), (ins GPR:$Rt, GPR:$Rn),
3223 "strex", "\t$Rd, $Rt, [$Rn]",
3225 def STREXD : AIstrex<0b01, (outs GPR:$Rd),
3226 (ins GPR:$Rt, GPR:$Rt2, GPR:$Rn),
3228 "strexd", "\t$Rd, $Rt, $Rt2, [$Rn]",
3232 // Clear-Exclusive is for disassembly only.
3233 def CLREX : AXI<(outs), (ins), MiscFrm, NoItinerary, "clrex",
3234 [/* For disassembly only; pattern left blank */]>,
3235 Requires<[IsARM, HasV7]> {
3236 let Inst{31-0} = 0b11110101011111111111000000011111;
3239 // SWP/SWPB are deprecated in V6/V7 and for disassembly only.
3240 let mayLoad = 1 in {
3241 def SWP : AIswp<0, (outs GPR:$Rt), (ins GPR:$Rt2, GPR:$Rn), "swp",
3242 [/* For disassembly only; pattern left blank */]>;
3243 def SWPB : AIswp<1, (outs GPR:$Rt), (ins GPR:$Rt2, GPR:$Rn), "swpb",
3244 [/* For disassembly only; pattern left blank */]>;
3247 //===----------------------------------------------------------------------===//
3251 // __aeabi_read_tp preserves the registers r1-r3.
3252 // This is a pseudo inst so that we can get the encoding right,
3253 // complete with fixup for the aeabi_read_tp function.
3255 Defs = [R0, R12, LR, CPSR], Uses = [SP] in {
3256 def TPsoft : PseudoInst<(outs), (ins), IIC_Br,
3257 [(set R0, ARMthread_pointer)]>;
3260 //===----------------------------------------------------------------------===//
3261 // SJLJ Exception handling intrinsics
3262 // eh_sjlj_setjmp() is an instruction sequence to store the return
3263 // address and save #0 in R0 for the non-longjmp case.
3264 // Since by its nature we may be coming from some other function to get
3265 // here, and we're using the stack frame for the containing function to
3266 // save/restore registers, we can't keep anything live in regs across
3267 // the eh_sjlj_setjmp(), else it will almost certainly have been tromped upon
3268 // when we get here from a longjmp(). We force everthing out of registers
3269 // except for our own input by listing the relevant registers in Defs. By
3270 // doing so, we also cause the prologue/epilogue code to actively preserve
3271 // all of the callee-saved resgisters, which is exactly what we want.
3272 // A constant value is passed in $val, and we use the location as a scratch.
3274 // These are pseudo-instructions and are lowered to individual MC-insts, so
3275 // no encoding information is necessary.
3277 [ R0, R1, R2, R3, R4, R5, R6, R7, R8, R9, R10, R11, R12, LR, D0,
3278 D1, D2, D3, D4, D5, D6, D7, D8, D9, D10, D11, D12, D13, D14, D15,
3279 D16, D17, D18, D19, D20, D21, D22, D23, D24, D25, D26, D27, D28, D29, D30,
3280 D31 ], hasSideEffects = 1, isBarrier = 1 in {
3281 def Int_eh_sjlj_setjmp : PseudoInst<(outs), (ins GPR:$src, GPR:$val),
3283 [(set R0, (ARMeh_sjlj_setjmp GPR:$src, GPR:$val))]>,
3284 Requires<[IsARM, HasVFP2]>;
3288 [ R0, R1, R2, R3, R4, R5, R6, R7, R8, R9, R10, R11, R12, LR ],
3289 hasSideEffects = 1, isBarrier = 1 in {
3290 def Int_eh_sjlj_setjmp_nofp : PseudoInst<(outs), (ins GPR:$src, GPR:$val),
3292 [(set R0, (ARMeh_sjlj_setjmp GPR:$src, GPR:$val))]>,
3293 Requires<[IsARM, NoVFP]>;
3296 // FIXME: Non-Darwin version(s)
3297 let isBarrier = 1, hasSideEffects = 1, isTerminator = 1,
3298 Defs = [ R7, LR, SP ] in {
3299 def Int_eh_sjlj_longjmp : PseudoInst<(outs), (ins GPR:$src, GPR:$scratch),
3301 [(ARMeh_sjlj_longjmp GPR:$src, GPR:$scratch)]>,
3302 Requires<[IsARM, IsDarwin]>;
3305 // eh.sjlj.dispatchsetup pseudo-instruction.
3306 // This pseudo is used for ARM, Thumb1 and Thumb2. Any differences are
3307 // handled when the pseudo is expanded (which happens before any passes
3308 // that need the instruction size).
3309 let isBarrier = 1, hasSideEffects = 1 in
3310 def Int_eh_sjlj_dispatchsetup :
3311 PseudoInst<(outs), (ins GPR:$src), NoItinerary,
3312 [(ARMeh_sjlj_dispatchsetup GPR:$src)]>,
3313 Requires<[IsDarwin]>;
3315 //===----------------------------------------------------------------------===//
3316 // Non-Instruction Patterns
3319 // Large immediate handling.
3321 // 32-bit immediate using two piece so_imms or movw + movt.
3322 // This is a single pseudo instruction, the benefit is that it can be remat'd
3323 // as a single unit instead of having to handle reg inputs.
3324 // FIXME: Remove this when we can do generalized remat.
3325 let isReMaterializable = 1, isMoveImm = 1 in
3326 def MOVi32imm : PseudoInst<(outs GPR:$dst), (ins i32imm:$src), IIC_iMOVix2,
3327 [(set GPR:$dst, (arm_i32imm:$src))]>,
3330 // ConstantPool, GlobalAddress, and JumpTable
3331 def : ARMPat<(ARMWrapper tglobaladdr :$dst), (LEApcrel tglobaladdr :$dst)>,
3332 Requires<[IsARM, DontUseMovt]>;
3333 def : ARMPat<(ARMWrapper tconstpool :$dst), (LEApcrel tconstpool :$dst)>;
3334 def : ARMPat<(ARMWrapper tglobaladdr :$dst), (MOVi32imm tglobaladdr :$dst)>,
3335 Requires<[IsARM, UseMovt]>;
3336 def : ARMPat<(ARMWrapperJT tjumptable:$dst, imm:$id),
3337 (LEApcrelJT tjumptable:$dst, imm:$id)>;
3339 // TODO: add,sub,and, 3-instr forms?
3342 def : ARMPat<(ARMtcret tcGPR:$dst),
3343 (TCRETURNri tcGPR:$dst)>, Requires<[IsDarwin]>;
3345 def : ARMPat<(ARMtcret (i32 tglobaladdr:$dst)),
3346 (TCRETURNdi texternalsym:$dst)>, Requires<[IsDarwin]>;
3348 def : ARMPat<(ARMtcret (i32 texternalsym:$dst)),
3349 (TCRETURNdi texternalsym:$dst)>, Requires<[IsDarwin]>;
3351 def : ARMPat<(ARMtcret tcGPR:$dst),
3352 (TCRETURNriND tcGPR:$dst)>, Requires<[IsNotDarwin]>;
3354 def : ARMPat<(ARMtcret (i32 tglobaladdr:$dst)),
3355 (TCRETURNdiND texternalsym:$dst)>, Requires<[IsNotDarwin]>;
3357 def : ARMPat<(ARMtcret (i32 texternalsym:$dst)),
3358 (TCRETURNdiND texternalsym:$dst)>, Requires<[IsNotDarwin]>;
3361 def : ARMPat<(ARMcall texternalsym:$func), (BL texternalsym:$func)>,
3362 Requires<[IsARM, IsNotDarwin]>;
3363 def : ARMPat<(ARMcall texternalsym:$func), (BLr9 texternalsym:$func)>,
3364 Requires<[IsARM, IsDarwin]>;
3366 // zextload i1 -> zextload i8
3367 def : ARMPat<(zextloadi1 addrmode_imm12:$addr), (LDRBi12 addrmode_imm12:$addr)>;
3368 def : ARMPat<(zextloadi1 ldst_so_reg:$addr), (LDRBrs ldst_so_reg:$addr)>;
3370 // extload -> zextload
3371 def : ARMPat<(extloadi1 addrmode_imm12:$addr), (LDRBi12 addrmode_imm12:$addr)>;
3372 def : ARMPat<(extloadi1 ldst_so_reg:$addr), (LDRBrs ldst_so_reg:$addr)>;
3373 def : ARMPat<(extloadi8 addrmode_imm12:$addr), (LDRBi12 addrmode_imm12:$addr)>;
3374 def : ARMPat<(extloadi8 ldst_so_reg:$addr), (LDRBrs ldst_so_reg:$addr)>;
3376 def : ARMPat<(extloadi16 addrmode3:$addr), (LDRH addrmode3:$addr)>;
3378 def : ARMPat<(extloadi8 addrmodepc:$addr), (PICLDRB addrmodepc:$addr)>;
3379 def : ARMPat<(extloadi16 addrmodepc:$addr), (PICLDRH addrmodepc:$addr)>;
3382 def : ARMV5TEPat<(mul (sra (shl GPR:$a, (i32 16)), (i32 16)),
3383 (sra (shl GPR:$b, (i32 16)), (i32 16))),
3384 (SMULBB GPR:$a, GPR:$b)>;
3385 def : ARMV5TEPat<(mul sext_16_node:$a, sext_16_node:$b),
3386 (SMULBB GPR:$a, GPR:$b)>;
3387 def : ARMV5TEPat<(mul (sra (shl GPR:$a, (i32 16)), (i32 16)),
3388 (sra GPR:$b, (i32 16))),
3389 (SMULBT GPR:$a, GPR:$b)>;
3390 def : ARMV5TEPat<(mul sext_16_node:$a, (sra GPR:$b, (i32 16))),
3391 (SMULBT GPR:$a, GPR:$b)>;
3392 def : ARMV5TEPat<(mul (sra GPR:$a, (i32 16)),
3393 (sra (shl GPR:$b, (i32 16)), (i32 16))),
3394 (SMULTB GPR:$a, GPR:$b)>;
3395 def : ARMV5TEPat<(mul (sra GPR:$a, (i32 16)), sext_16_node:$b),
3396 (SMULTB GPR:$a, GPR:$b)>;
3397 def : ARMV5TEPat<(sra (mul GPR:$a, (sra (shl GPR:$b, (i32 16)), (i32 16))),
3399 (SMULWB GPR:$a, GPR:$b)>;
3400 def : ARMV5TEPat<(sra (mul GPR:$a, sext_16_node:$b), (i32 16)),
3401 (SMULWB GPR:$a, GPR:$b)>;
3403 def : ARMV5TEPat<(add GPR:$acc,
3404 (mul (sra (shl GPR:$a, (i32 16)), (i32 16)),
3405 (sra (shl GPR:$b, (i32 16)), (i32 16)))),
3406 (SMLABB GPR:$a, GPR:$b, GPR:$acc)>;
3407 def : ARMV5TEPat<(add GPR:$acc,
3408 (mul sext_16_node:$a, sext_16_node:$b)),
3409 (SMLABB GPR:$a, GPR:$b, GPR:$acc)>;
3410 def : ARMV5TEPat<(add GPR:$acc,
3411 (mul (sra (shl GPR:$a, (i32 16)), (i32 16)),
3412 (sra GPR:$b, (i32 16)))),
3413 (SMLABT GPR:$a, GPR:$b, GPR:$acc)>;
3414 def : ARMV5TEPat<(add GPR:$acc,
3415 (mul sext_16_node:$a, (sra GPR:$b, (i32 16)))),
3416 (SMLABT GPR:$a, GPR:$b, GPR:$acc)>;
3417 def : ARMV5TEPat<(add GPR:$acc,
3418 (mul (sra GPR:$a, (i32 16)),
3419 (sra (shl GPR:$b, (i32 16)), (i32 16)))),
3420 (SMLATB GPR:$a, GPR:$b, GPR:$acc)>;
3421 def : ARMV5TEPat<(add GPR:$acc,
3422 (mul (sra GPR:$a, (i32 16)), sext_16_node:$b)),
3423 (SMLATB GPR:$a, GPR:$b, GPR:$acc)>;
3424 def : ARMV5TEPat<(add GPR:$acc,
3425 (sra (mul GPR:$a, (sra (shl GPR:$b, (i32 16)), (i32 16))),
3427 (SMLAWB GPR:$a, GPR:$b, GPR:$acc)>;
3428 def : ARMV5TEPat<(add GPR:$acc,
3429 (sra (mul GPR:$a, sext_16_node:$b), (i32 16))),
3430 (SMLAWB GPR:$a, GPR:$b, GPR:$acc)>;
3432 //===----------------------------------------------------------------------===//
3436 include "ARMInstrThumb.td"
3438 //===----------------------------------------------------------------------===//
3442 include "ARMInstrThumb2.td"
3444 //===----------------------------------------------------------------------===//
3445 // Floating Point Support
3448 include "ARMInstrVFP.td"
3450 //===----------------------------------------------------------------------===//
3451 // Advanced SIMD (NEON) Support
3454 include "ARMInstrNEON.td"
3456 //===----------------------------------------------------------------------===//
3457 // Coprocessor Instructions. For disassembly only.
3460 def CDP : ABI<0b1110, (outs), (ins nohash_imm:$cop, i32imm:$opc1,
3461 nohash_imm:$CRd, nohash_imm:$CRn, nohash_imm:$CRm, i32imm:$opc2),
3462 NoItinerary, "cdp", "\tp$cop, $opc1, cr$CRd, cr$CRn, cr$CRm, $opc2",
3463 [/* For disassembly only; pattern left blank */]> {
3467 def CDP2 : ABXI<0b1110, (outs), (ins nohash_imm:$cop, i32imm:$opc1,
3468 nohash_imm:$CRd, nohash_imm:$CRn, nohash_imm:$CRm, i32imm:$opc2),
3469 NoItinerary, "cdp2\tp$cop, $opc1, cr$CRd, cr$CRn, cr$CRm, $opc2",
3470 [/* For disassembly only; pattern left blank */]> {
3471 let Inst{31-28} = 0b1111;
3475 class ACI<dag oops, dag iops, string opc, string asm>
3476 : I<oops, iops, AddrModeNone, Size4Bytes, IndexModeNone, BrFrm, NoItinerary,
3477 opc, asm, "", [/* For disassembly only; pattern left blank */]> {
3478 let Inst{27-25} = 0b110;
3481 multiclass LdStCop<bits<4> op31_28, bit load, string opc> {
3483 def _OFFSET : ACI<(outs),
3484 (ins nohash_imm:$cop, nohash_imm:$CRd, addrmode2:$addr),
3485 opc, "\tp$cop, cr$CRd, $addr"> {
3486 let Inst{31-28} = op31_28;
3487 let Inst{24} = 1; // P = 1
3488 let Inst{21} = 0; // W = 0
3489 let Inst{22} = 0; // D = 0
3490 let Inst{20} = load;
3493 def _PRE : ACI<(outs),
3494 (ins nohash_imm:$cop, nohash_imm:$CRd, addrmode2:$addr),
3495 opc, "\tp$cop, cr$CRd, $addr!"> {
3496 let Inst{31-28} = op31_28;
3497 let Inst{24} = 1; // P = 1
3498 let Inst{21} = 1; // W = 1
3499 let Inst{22} = 0; // D = 0
3500 let Inst{20} = load;
3503 def _POST : ACI<(outs),
3504 (ins nohash_imm:$cop, nohash_imm:$CRd, GPR:$base, am2offset:$offset),
3505 opc, "\tp$cop, cr$CRd, [$base], $offset"> {
3506 let Inst{31-28} = op31_28;
3507 let Inst{24} = 0; // P = 0
3508 let Inst{21} = 1; // W = 1
3509 let Inst{22} = 0; // D = 0
3510 let Inst{20} = load;
3513 def _OPTION : ACI<(outs),
3514 (ins nohash_imm:$cop, nohash_imm:$CRd, GPR:$base, i32imm:$option),
3515 opc, "\tp$cop, cr$CRd, [$base], $option"> {
3516 let Inst{31-28} = op31_28;
3517 let Inst{24} = 0; // P = 0
3518 let Inst{23} = 1; // U = 1
3519 let Inst{21} = 0; // W = 0
3520 let Inst{22} = 0; // D = 0
3521 let Inst{20} = load;
3524 def L_OFFSET : ACI<(outs),
3525 (ins nohash_imm:$cop, nohash_imm:$CRd, addrmode2:$addr),
3526 !strconcat(opc, "l"), "\tp$cop, cr$CRd, $addr"> {
3527 let Inst{31-28} = op31_28;
3528 let Inst{24} = 1; // P = 1
3529 let Inst{21} = 0; // W = 0
3530 let Inst{22} = 1; // D = 1
3531 let Inst{20} = load;
3534 def L_PRE : ACI<(outs),
3535 (ins nohash_imm:$cop, nohash_imm:$CRd, addrmode2:$addr),
3536 !strconcat(opc, "l"), "\tp$cop, cr$CRd, $addr!"> {
3537 let Inst{31-28} = op31_28;
3538 let Inst{24} = 1; // P = 1
3539 let Inst{21} = 1; // W = 1
3540 let Inst{22} = 1; // D = 1
3541 let Inst{20} = load;
3544 def L_POST : ACI<(outs),
3545 (ins nohash_imm:$cop, nohash_imm:$CRd, GPR:$base, am2offset:$offset),
3546 !strconcat(opc, "l"), "\tp$cop, cr$CRd, [$base], $offset"> {
3547 let Inst{31-28} = op31_28;
3548 let Inst{24} = 0; // P = 0
3549 let Inst{21} = 1; // W = 1
3550 let Inst{22} = 1; // D = 1
3551 let Inst{20} = load;
3554 def L_OPTION : ACI<(outs),
3555 (ins nohash_imm:$cop, nohash_imm:$CRd, GPR:$base, nohash_imm:$option),
3556 !strconcat(opc, "l"), "\tp$cop, cr$CRd, [$base], $option"> {
3557 let Inst{31-28} = op31_28;
3558 let Inst{24} = 0; // P = 0
3559 let Inst{23} = 1; // U = 1
3560 let Inst{21} = 0; // W = 0
3561 let Inst{22} = 1; // D = 1
3562 let Inst{20} = load;
3566 defm LDC : LdStCop<{?,?,?,?}, 1, "ldc">;
3567 defm LDC2 : LdStCop<0b1111, 1, "ldc2">;
3568 defm STC : LdStCop<{?,?,?,?}, 0, "stc">;
3569 defm STC2 : LdStCop<0b1111, 0, "stc2">;
3571 def MCR : ABI<0b1110, (outs), (ins nohash_imm:$cop, i32imm:$opc1,
3572 GPR:$Rt, nohash_imm:$CRn, nohash_imm:$CRm, i32imm:$opc2),
3573 NoItinerary, "mcr", "\tp$cop, $opc1, $Rt, cr$CRn, cr$CRm, $opc2",
3574 [/* For disassembly only; pattern left blank */]> {
3579 def MCR2 : ABXI<0b1110, (outs), (ins nohash_imm:$cop, i32imm:$opc1,
3580 GPR:$Rt, nohash_imm:$CRn, nohash_imm:$CRm, i32imm:$opc2),
3581 NoItinerary, "mcr2\tp$cop, $opc1, $Rt, cr$CRn, cr$CRm, $opc2",
3582 [/* For disassembly only; pattern left blank */]> {
3583 let Inst{31-28} = 0b1111;
3588 def MRC : ABI<0b1110, (outs), (ins nohash_imm:$cop, i32imm:$opc1,
3589 GPR:$Rt, nohash_imm:$CRn, nohash_imm:$CRm, i32imm:$opc2),
3590 NoItinerary, "mrc", "\tp$cop, $opc1, $Rt, cr$CRn, cr$CRm, $opc2",
3591 [/* For disassembly only; pattern left blank */]> {
3596 def MRC2 : ABXI<0b1110, (outs), (ins nohash_imm:$cop, i32imm:$opc1,
3597 GPR:$Rt, nohash_imm:$CRn, nohash_imm:$CRm, i32imm:$opc2),
3598 NoItinerary, "mrc2\tp$cop, $opc1, $Rt, cr$CRn, cr$CRm, $opc2",
3599 [/* For disassembly only; pattern left blank */]> {
3600 let Inst{31-28} = 0b1111;
3605 def MCRR : ABI<0b1100, (outs), (ins nohash_imm:$cop, i32imm:$opc,
3606 GPR:$Rt, GPR:$Rt2, nohash_imm:$CRm),
3607 NoItinerary, "mcrr", "\tp$cop, $opc, $Rt, $Rt2, cr$CRm",
3608 [/* For disassembly only; pattern left blank */]> {
3609 let Inst{23-20} = 0b0100;
3612 def MCRR2 : ABXI<0b1100, (outs), (ins nohash_imm:$cop, i32imm:$opc,
3613 GPR:$Rt, GPR:$Rt2, nohash_imm:$CRm),
3614 NoItinerary, "mcrr2\tp$cop, $opc, $Rt, $Rt2, cr$CRm",
3615 [/* For disassembly only; pattern left blank */]> {
3616 let Inst{31-28} = 0b1111;
3617 let Inst{23-20} = 0b0100;
3620 def MRRC : ABI<0b1100, (outs), (ins nohash_imm:$cop, i32imm:$opc,
3621 GPR:$Rt, GPR:$Rt2, nohash_imm:$CRm),
3622 NoItinerary, "mrrc", "\tp$cop, $opc, $Rt, $Rt2, cr$CRm",
3623 [/* For disassembly only; pattern left blank */]> {
3624 let Inst{23-20} = 0b0101;
3627 def MRRC2 : ABXI<0b1100, (outs), (ins nohash_imm:$cop, i32imm:$opc,
3628 GPR:$Rt, GPR:$Rt2, nohash_imm:$CRm),
3629 NoItinerary, "mrrc2\tp$cop, $opc, $Rt, $Rt2, cr$CRm",
3630 [/* For disassembly only; pattern left blank */]> {
3631 let Inst{31-28} = 0b1111;
3632 let Inst{23-20} = 0b0101;
3635 //===----------------------------------------------------------------------===//
3636 // Move between special register and ARM core register -- for disassembly only
3639 def MRS : ABI<0b0001,(outs GPR:$dst),(ins), NoItinerary, "mrs", "\t$dst, cpsr",
3640 [/* For disassembly only; pattern left blank */]> {
3641 let Inst{23-20} = 0b0000;
3642 let Inst{7-4} = 0b0000;
3645 def MRSsys : ABI<0b0001,(outs GPR:$dst),(ins), NoItinerary,"mrs","\t$dst, spsr",
3646 [/* For disassembly only; pattern left blank */]> {
3647 let Inst{23-20} = 0b0100;
3648 let Inst{7-4} = 0b0000;
3651 def MSR : ABI<0b0001, (outs), (ins GPR:$src, msr_mask:$mask), NoItinerary,
3652 "msr", "\tcpsr$mask, $src",
3653 [/* For disassembly only; pattern left blank */]> {
3654 let Inst{23-20} = 0b0010;
3655 let Inst{7-4} = 0b0000;
3658 def MSRi : ABI<0b0011, (outs), (ins so_imm:$a, msr_mask:$mask), NoItinerary,
3659 "msr", "\tcpsr$mask, $a",
3660 [/* For disassembly only; pattern left blank */]> {
3661 let Inst{23-20} = 0b0010;
3662 let Inst{7-4} = 0b0000;
3665 def MSRsys : ABI<0b0001, (outs), (ins GPR:$src, msr_mask:$mask), NoItinerary,
3666 "msr", "\tspsr$mask, $src",
3667 [/* For disassembly only; pattern left blank */]> {
3668 let Inst{23-20} = 0b0110;
3669 let Inst{7-4} = 0b0000;
3672 def MSRsysi : ABI<0b0011, (outs), (ins so_imm:$a, msr_mask:$mask), NoItinerary,
3673 "msr", "\tspsr$mask, $a",
3674 [/* For disassembly only; pattern left blank */]> {
3675 let Inst{23-20} = 0b0110;
3676 let Inst{7-4} = 0b0000;