1 //===- ARMInstrInfo.td - Target Description for ARM Target ----------------===//
3 // The LLVM Compiler Infrastructure
5 // This file was developed by the "Instituto Nokia de Tecnologia" and
6 // is distributed under the University of Illinois Open Source
7 // License. See LICENSE.TXT for details.
9 //===----------------------------------------------------------------------===//
11 // This file describes the ARM instructions in TableGen format.
13 //===----------------------------------------------------------------------===//
16 def op_addr_mode1 : Operand<iPTR> {
17 let PrintMethod = "printAddrMode1";
18 let NumMIOperands = 3;
19 let MIOperandInfo = (ops ptr_rc, ptr_rc, i32imm);
22 def memri : Operand<iPTR> {
23 let PrintMethod = "printMemRegImm";
24 let NumMIOperands = 2;
25 let MIOperandInfo = (ops i32imm, ptr_rc);
28 // Define ARM specific addressing mode.
29 //Addressing Mode 1: data processing operands
30 def addr_mode1 : ComplexPattern<iPTR, 3, "SelectAddrMode1", [imm, sra, shl, srl],
33 //register plus/minus 12 bit offset
34 def iaddr : ComplexPattern<iPTR, 2, "SelectAddrRegImm", [frameindex], []>;
35 //register plus scaled register
36 //def raddr : ComplexPattern<iPTR, 2, "SelectAddrRegReg", [], []>;
38 //===----------------------------------------------------------------------===//
40 //===----------------------------------------------------------------------===//
42 class InstARM<dag ops, string asmstr, list<dag> pattern> : Instruction {
43 let Namespace = "ARM";
45 dag OperandList = ops;
46 let AsmString = asmstr;
47 let Pattern = pattern;
50 def brtarget : Operand<OtherVT>;
52 // Operand for printing out a condition code.
53 let PrintMethod = "printCCOperand" in
54 def CCOp : Operand<i32>;
56 def SDT_ARMCallSeq : SDTypeProfile<0, 1, [ SDTCisVT<0, i32> ]>;
57 def callseq_start : SDNode<"ISD::CALLSEQ_START", SDT_ARMCallSeq,
58 [SDNPHasChain, SDNPOutFlag]>;
59 def callseq_end : SDNode<"ISD::CALLSEQ_END", SDT_ARMCallSeq,
60 [SDNPHasChain, SDNPOutFlag]>;
62 def SDT_ARMcall : SDTypeProfile<0, -1, [SDTCisInt<0>]>;
63 def ARMcall : SDNode<"ARMISD::CALL", SDT_ARMcall,
64 [SDNPHasChain, SDNPOptInFlag, SDNPOutFlag]>;
65 def retflag : SDNode<"ARMISD::RET_FLAG", SDTRet,
66 [SDNPHasChain, SDNPOptInFlag]>;
68 def SDTarmselect : SDTypeProfile<1, 3, [SDTCisSameAs<0, 1>, SDTCisSameAs<0, 2>, SDTCisInt<0>, SDTCisVT<2, i32>]>;
69 def armselect : SDNode<"ARMISD::SELECT", SDTarmselect, [SDNPInFlag, SDNPOutFlag]>;
71 def SDTarmfmstat : SDTypeProfile<0, 0, []>;
72 def armfmstat : SDNode<"ARMISD::FMSTAT", SDTarmfmstat, [SDNPInFlag, SDNPOutFlag]>;
74 def SDTarmbr : SDTypeProfile<0, 2, [SDTCisVT<0, OtherVT>, SDTCisVT<1, i32>]>;
75 def armbr : SDNode<"ARMISD::BR", SDTarmbr, [SDNPHasChain, SDNPInFlag]>;
77 def SDTVoidBinOp : SDTypeProfile<0, 2, [SDTCisSameAs<0, 1>]>;
78 def armcmp : SDNode<"ARMISD::CMP", SDTVoidBinOp, [SDNPOutFlag]>;
79 def armcmpe : SDNode<"ARMISD::CMPE", SDTVoidBinOp, [SDNPOutFlag]>;
81 def armfsitos : SDNode<"ARMISD::FSITOS", SDTUnaryOp>;
82 def armftosis : SDNode<"ARMISD::FTOSIS", SDTUnaryOp>;
83 def armfsitod : SDNode<"ARMISD::FSITOD", SDTUnaryOp>;
84 def armftosid : SDNode<"ARMISD::FTOSID", SDTUnaryOp>;
85 def armfuitos : SDNode<"ARMISD::FUITOS", SDTUnaryOp>;
86 def armftouis : SDNode<"ARMISD::FTOUIS", SDTUnaryOp>;
87 def armfuitod : SDNode<"ARMISD::FUITOD", SDTUnaryOp>;
88 def armftouid : SDNode<"ARMISD::FTOUID", SDTUnaryOp>;
90 def SDTarmfmrrd : SDTypeProfile<0, 3, [SDTCisInt<0>, SDTCisInt<1>, SDTCisFP<2>]>;
91 def armfmrrd : SDNode<"ARMISD::FMRRD", SDTarmfmrrd,
92 [SDNPHasChain, SDNPOptInFlag, SDNPOutFlag]>;
94 def SDTarmfmdrr : SDTypeProfile<1, 2, [SDTCisFP<0>, SDTCisInt<1>, SDTCisInt<2>]>;
95 def armfmdrr : SDNode<"ARMISD::FMDRR", SDTarmfmdrr, []>;
97 def ADJCALLSTACKUP : InstARM<(ops i32imm:$amt),
98 "!ADJCALLSTACKUP $amt",
99 [(callseq_end imm:$amt)]>, Imp<[R13],[R13]>;
101 def ADJCALLSTACKDOWN : InstARM<(ops i32imm:$amt),
102 "!ADJCALLSTACKDOWN $amt",
103 [(callseq_start imm:$amt)]>, Imp<[R13],[R13]>;
105 let isReturn = 1 in {
106 def bx: InstARM<(ops), "bx r14", [(retflag)]>;
109 let Defs = [R0, R1, R2, R3, R14] in {
110 def bl: InstARM<(ops i32imm:$func, variable_ops), "bl $func", [(ARMcall tglobaladdr:$func)]>;
113 def ldr : InstARM<(ops IntRegs:$dst, memri:$addr),
115 [(set IntRegs:$dst, (load iaddr:$addr))]>;
117 def str : InstARM<(ops IntRegs:$src, memri:$addr),
119 [(store IntRegs:$src, iaddr:$addr)]>;
121 def MOV : InstARM<(ops IntRegs:$dst, op_addr_mode1:$src),
122 "mov $dst, $src", [(set IntRegs:$dst, addr_mode1:$src)]>;
124 def ADD : InstARM<(ops IntRegs:$dst, IntRegs:$a, op_addr_mode1:$b),
126 [(set IntRegs:$dst, (add IntRegs:$a, addr_mode1:$b))]>;
128 def ADCS : InstARM<(ops IntRegs:$dst, IntRegs:$a, op_addr_mode1:$b),
130 [(set IntRegs:$dst, (adde IntRegs:$a, addr_mode1:$b))]>;
132 def ADDS : InstARM<(ops IntRegs:$dst, IntRegs:$a, op_addr_mode1:$b),
134 [(set IntRegs:$dst, (addc IntRegs:$a, addr_mode1:$b))]>;
136 // "LEA" forms of add
137 def lea_addri : InstARM<(ops IntRegs:$dst, memri:$addr),
138 "add $dst, ${addr:arith}",
139 [(set IntRegs:$dst, iaddr:$addr)]>;
142 def SUB : InstARM<(ops IntRegs:$dst, IntRegs:$a, op_addr_mode1:$b),
144 [(set IntRegs:$dst, (sub IntRegs:$a, addr_mode1:$b))]>;
146 def SBCS : InstARM<(ops IntRegs:$dst, IntRegs:$a, op_addr_mode1:$b),
148 [(set IntRegs:$dst, (sube IntRegs:$a, addr_mode1:$b))]>;
150 def SUBS : InstARM<(ops IntRegs:$dst, IntRegs:$a, op_addr_mode1:$b),
152 [(set IntRegs:$dst, (subc IntRegs:$a, addr_mode1:$b))]>;
154 def AND : InstARM<(ops IntRegs:$dst, IntRegs:$a, op_addr_mode1:$b),
156 [(set IntRegs:$dst, (and IntRegs:$a, addr_mode1:$b))]>;
158 def EOR : InstARM<(ops IntRegs:$dst, IntRegs:$a, op_addr_mode1:$b),
160 [(set IntRegs:$dst, (xor IntRegs:$a, addr_mode1:$b))]>;
162 def ORR : InstARM<(ops IntRegs:$dst, IntRegs:$a, op_addr_mode1:$b),
164 [(set IntRegs:$dst, (or IntRegs:$a, addr_mode1:$b))]>;
166 let isTwoAddress = 1 in {
167 def movcond : InstARM<(ops IntRegs:$dst, IntRegs:$false,
168 op_addr_mode1:$true, CCOp:$cc),
169 "mov$cc $dst, $true",
170 [(set IntRegs:$dst, (armselect addr_mode1:$true,
171 IntRegs:$false, imm:$cc))]>;
174 def MUL : InstARM<(ops IntRegs:$dst, IntRegs:$a, IntRegs:$b),
176 [(set IntRegs:$dst, (mul IntRegs:$a, IntRegs:$b))]>;
178 def bcond : InstARM<(ops brtarget:$dst, CCOp:$cc),
180 [(armbr bb:$dst, imm:$cc)]>;
182 def b : InstARM<(ops brtarget:$dst),
186 def cmp : InstARM<(ops IntRegs:$a, op_addr_mode1:$b),
188 [(armcmp IntRegs:$a, addr_mode1:$b)]>;
190 // Floating Point Compare
191 def fcmps : InstARM<(ops FPRegs:$a, FPRegs:$b),
193 [(armcmp FPRegs:$a, FPRegs:$b)]>;
195 def fcmpes : InstARM<(ops FPRegs:$a, FPRegs:$b),
197 [(armcmpe FPRegs:$a, FPRegs:$b)]>;
199 def fcmped : InstARM<(ops DFPRegs:$a, DFPRegs:$b),
201 [(armcmpe DFPRegs:$a, DFPRegs:$b)]>;
203 def fcmpd : InstARM<(ops DFPRegs:$a, DFPRegs:$b),
205 [(armcmp DFPRegs:$a, DFPRegs:$b)]>;
207 // Floating Point Conversion
208 // We use bitconvert for moving the data between the register classes.
209 // The format conversion is done with ARM specific nodes
211 def FMSR : InstARM<(ops FPRegs:$dst, IntRegs:$src),
212 "fmsr $dst, $src", [(set FPRegs:$dst, (bitconvert IntRegs:$src))]>;
214 def FMRS : InstARM<(ops IntRegs:$dst, FPRegs:$src),
215 "fmrs $dst, $src", [(set IntRegs:$dst, (bitconvert FPRegs:$src))]>;
217 def FMRRD : InstARM<(ops IntRegs:$i0, IntRegs:$i1, DFPRegs:$src),
218 "fmrrd $i0, $i1, $src", [(armfmrrd IntRegs:$i0, IntRegs:$i1, DFPRegs:$src)]>;
220 def FMDRR : InstARM<(ops DFPRegs:$dst, IntRegs:$i0, IntRegs:$i1),
221 "fmdrr $dst, $i0, $i1", [(set DFPRegs:$dst, (armfmdrr IntRegs:$i0, IntRegs:$i1))]>;
223 def FSITOS : InstARM<(ops FPRegs:$dst, FPRegs:$src),
224 "fsitos $dst, $src", [(set FPRegs:$dst, (armfsitos FPRegs:$src))]>;
226 def FTOSIS : InstARM<(ops FPRegs:$dst, FPRegs:$src),
227 "ftosis $dst, $src", [(set FPRegs:$dst, (armftosis FPRegs:$src))]>;
229 def FSITOD : InstARM<(ops DFPRegs:$dst, FPRegs:$src),
230 "fsitod $dst, $src", [(set DFPRegs:$dst, (armfsitod FPRegs:$src))]>;
232 def FTOSID : InstARM<(ops FPRegs:$dst, DFPRegs:$src),
233 "ftosid $dst, $src", [(set FPRegs:$dst, (armftosid DFPRegs:$src))]>;
235 def FUITOS : InstARM<(ops FPRegs:$dst, FPRegs:$src),
236 "fuitos $dst, $src", [(set FPRegs:$dst, (armfuitos FPRegs:$src))]>;
238 def FTOUIS : InstARM<(ops FPRegs:$dst, FPRegs:$src),
239 "ftouis $dst, $src", [(set FPRegs:$dst, (armftouis FPRegs:$src))]>;
241 def FUITOD : InstARM<(ops DFPRegs:$dst, FPRegs:$src),
242 "fuitod $dst, $src", [(set DFPRegs:$dst, (armfuitod FPRegs:$src))]>;
244 def FTOUID : InstARM<(ops FPRegs:$dst, DFPRegs:$src),
245 "ftouid $dst, $src", [(set FPRegs:$dst, (armftouid DFPRegs:$src))]>;
247 def FCVTDS : InstARM<(ops DFPRegs:$dst, FPRegs:$src),
248 "fcvtds $dst, $src", [(set DFPRegs:$dst, (fextend FPRegs:$src))]>;
250 def FCVTSD : InstARM<(ops FPRegs:$dst, DFPRegs:$src),
251 "fcvtsd $dst, $src", [(set FPRegs:$dst, (fround DFPRegs:$src))]>;
253 def FMSTAT : InstARM<(ops ), "fmstat", [(armfmstat)]>;
255 // Floating Point Arithmetic
256 def FADDS : InstARM<(ops FPRegs:$dst, FPRegs:$a, FPRegs:$b),
257 "fadds $dst, $a, $b",
258 [(set FPRegs:$dst, (fadd FPRegs:$a, FPRegs:$b))]>;
260 def FADDD : InstARM<(ops DFPRegs:$dst, DFPRegs:$a, DFPRegs:$b),
261 "faddd $dst, $a, $b",
262 [(set DFPRegs:$dst, (fadd DFPRegs:$a, DFPRegs:$b))]>;
264 def FSUBS : InstARM<(ops FPRegs:$dst, FPRegs:$a, FPRegs:$b),
265 "fsubs $dst, $a, $b",
266 [(set FPRegs:$dst, (fsub FPRegs:$a, FPRegs:$b))]>;
268 def FSUBD : InstARM<(ops DFPRegs:$dst, DFPRegs:$a, DFPRegs:$b),
269 "fsubd $dst, $a, $b",
270 [(set DFPRegs:$dst, (fsub DFPRegs:$a, DFPRegs:$b))]>;
272 def FNEGS : InstARM<(ops FPRegs:$dst, FPRegs:$src),
274 [(set FPRegs:$dst, (fneg FPRegs:$src))]>;
276 def FNEGD : InstARM<(ops DFPRegs:$dst, DFPRegs:$src),
278 [(set DFPRegs:$dst, (fneg DFPRegs:$src))]>;
280 def FMULS : InstARM<(ops FPRegs:$dst, FPRegs:$a, FPRegs:$b),
281 "fmuls $dst, $a, $b",
282 [(set FPRegs:$dst, (fmul FPRegs:$a, FPRegs:$b))]>;
284 def FMULD : InstARM<(ops DFPRegs:$dst, DFPRegs:$a, DFPRegs:$b),
285 "fmuld $dst, $a, $b",
286 [(set DFPRegs:$dst, (fmul DFPRegs:$a, DFPRegs:$b))]>;
289 // Floating Point Load
290 def FLDS : InstARM<(ops FPRegs:$dst, IntRegs:$addr),
292 [(set FPRegs:$dst, (load IntRegs:$addr))]>;
294 def FLDD : InstARM<(ops DFPRegs:$dst, IntRegs:$addr),
296 [(set DFPRegs:$dst, (load IntRegs:$addr))]>;