1 //===- ARMInstrInfo.td - Target Description for ARM Target -*- tablegen -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file describes the ARM instructions in TableGen format.
12 //===----------------------------------------------------------------------===//
14 //===----------------------------------------------------------------------===//
15 // ARM specific DAG Nodes.
19 def SDT_ARMCallSeqStart : SDCallSeqStart<[ SDTCisVT<0, i32> ]>;
20 def SDT_ARMCallSeqEnd : SDCallSeqEnd<[ SDTCisVT<0, i32>, SDTCisVT<1, i32> ]>;
22 def SDT_ARMSaveCallPC : SDTypeProfile<0, 1, []>;
24 def SDT_ARMcall : SDTypeProfile<0, -1, [SDTCisPtrTy<0>]>;
26 def SDT_ARMCMov : SDTypeProfile<1, 3,
27 [SDTCisSameAs<0, 1>, SDTCisSameAs<0, 2>,
30 def SDT_ARMBrcond : SDTypeProfile<0, 2,
31 [SDTCisVT<0, OtherVT>, SDTCisVT<1, i32>]>;
33 def SDT_ARMBrJT : SDTypeProfile<0, 3,
34 [SDTCisPtrTy<0>, SDTCisVT<1, i32>,
37 def SDT_ARMBr2JT : SDTypeProfile<0, 4,
38 [SDTCisPtrTy<0>, SDTCisVT<1, i32>,
39 SDTCisVT<2, i32>, SDTCisVT<3, i32>]>;
41 def SDT_ARMBCC_i64 : SDTypeProfile<0, 6,
43 SDTCisVT<1, i32>, SDTCisVT<2, i32>,
44 SDTCisVT<3, i32>, SDTCisVT<4, i32>,
45 SDTCisVT<5, OtherVT>]>;
47 def SDT_ARMAnd : SDTypeProfile<1, 2,
48 [SDTCisVT<0, i32>, SDTCisVT<1, i32>,
51 def SDT_ARMCmp : SDTypeProfile<0, 2, [SDTCisSameAs<0, 1>]>;
53 def SDT_ARMPICAdd : SDTypeProfile<1, 2, [SDTCisSameAs<0, 1>,
54 SDTCisPtrTy<1>, SDTCisVT<2, i32>]>;
56 def SDT_ARMThreadPointer : SDTypeProfile<1, 0, [SDTCisPtrTy<0>]>;
57 def SDT_ARMEH_SJLJ_Setjmp : SDTypeProfile<1, 2, [SDTCisInt<0>, SDTCisPtrTy<1>,
59 def SDT_ARMEH_SJLJ_Longjmp: SDTypeProfile<0, 2, [SDTCisPtrTy<0>, SDTCisInt<1>]>;
61 def SDT_ARMMEMBARRIER : SDTypeProfile<0, 1, [SDTCisInt<0>]>;
63 def SDT_ARMPREFETCH : SDTypeProfile<0, 3, [SDTCisPtrTy<0>, SDTCisSameAs<1, 2>,
66 def SDT_ARMTCRET : SDTypeProfile<0, 1, [SDTCisPtrTy<0>]>;
68 def SDT_ARMBFI : SDTypeProfile<1, 3, [SDTCisVT<0, i32>, SDTCisVT<1, i32>,
69 SDTCisVT<2, i32>, SDTCisVT<3, i32>]>;
71 def SDTBinaryArithWithFlags : SDTypeProfile<2, 2,
74 SDTCisInt<0>, SDTCisVT<1, i32>]>;
76 // SDTBinaryArithWithFlagsInOut - RES1, CPSR = op LHS, RHS, CPSR
77 def SDTBinaryArithWithFlagsInOut : SDTypeProfile<2, 3,
84 def ARMWrapper : SDNode<"ARMISD::Wrapper", SDTIntUnaryOp>;
85 def ARMWrapperDYN : SDNode<"ARMISD::WrapperDYN", SDTIntUnaryOp>;
86 def ARMWrapperPIC : SDNode<"ARMISD::WrapperPIC", SDTIntUnaryOp>;
87 def ARMWrapperJT : SDNode<"ARMISD::WrapperJT", SDTIntBinOp>;
89 def ARMcallseq_start : SDNode<"ISD::CALLSEQ_START", SDT_ARMCallSeqStart,
90 [SDNPHasChain, SDNPOutGlue]>;
91 def ARMcallseq_end : SDNode<"ISD::CALLSEQ_END", SDT_ARMCallSeqEnd,
92 [SDNPHasChain, SDNPOptInGlue, SDNPOutGlue]>;
94 def ARMcall : SDNode<"ARMISD::CALL", SDT_ARMcall,
95 [SDNPHasChain, SDNPOptInGlue, SDNPOutGlue,
97 def ARMcall_pred : SDNode<"ARMISD::CALL_PRED", SDT_ARMcall,
98 [SDNPHasChain, SDNPOptInGlue, SDNPOutGlue,
100 def ARMcall_nolink : SDNode<"ARMISD::CALL_NOLINK", SDT_ARMcall,
101 [SDNPHasChain, SDNPOptInGlue, SDNPOutGlue,
104 def ARMretflag : SDNode<"ARMISD::RET_FLAG", SDTNone,
105 [SDNPHasChain, SDNPOptInGlue]>;
107 def ARMcmov : SDNode<"ARMISD::CMOV", SDT_ARMCMov,
110 def ARMbrcond : SDNode<"ARMISD::BRCOND", SDT_ARMBrcond,
111 [SDNPHasChain, SDNPInGlue, SDNPOutGlue]>;
113 def ARMbrjt : SDNode<"ARMISD::BR_JT", SDT_ARMBrJT,
115 def ARMbr2jt : SDNode<"ARMISD::BR2_JT", SDT_ARMBr2JT,
118 def ARMBcci64 : SDNode<"ARMISD::BCC_i64", SDT_ARMBCC_i64,
121 def ARMcmp : SDNode<"ARMISD::CMP", SDT_ARMCmp,
124 def ARMcmpZ : SDNode<"ARMISD::CMPZ", SDT_ARMCmp,
125 [SDNPOutGlue, SDNPCommutative]>;
127 def ARMpic_add : SDNode<"ARMISD::PIC_ADD", SDT_ARMPICAdd>;
129 def ARMsrl_flag : SDNode<"ARMISD::SRL_FLAG", SDTIntUnaryOp, [SDNPOutGlue]>;
130 def ARMsra_flag : SDNode<"ARMISD::SRA_FLAG", SDTIntUnaryOp, [SDNPOutGlue]>;
131 def ARMrrx : SDNode<"ARMISD::RRX" , SDTIntUnaryOp, [SDNPInGlue ]>;
133 def ARMaddc : SDNode<"ARMISD::ADDC", SDTBinaryArithWithFlags,
135 def ARMsubc : SDNode<"ARMISD::SUBC", SDTBinaryArithWithFlags>;
136 def ARMadde : SDNode<"ARMISD::ADDE", SDTBinaryArithWithFlagsInOut>;
137 def ARMsube : SDNode<"ARMISD::SUBE", SDTBinaryArithWithFlagsInOut>;
139 def ARMthread_pointer: SDNode<"ARMISD::THREAD_POINTER", SDT_ARMThreadPointer>;
140 def ARMeh_sjlj_setjmp: SDNode<"ARMISD::EH_SJLJ_SETJMP",
141 SDT_ARMEH_SJLJ_Setjmp, [SDNPHasChain]>;
142 def ARMeh_sjlj_longjmp: SDNode<"ARMISD::EH_SJLJ_LONGJMP",
143 SDT_ARMEH_SJLJ_Longjmp, [SDNPHasChain]>;
145 def ARMMemBarrier : SDNode<"ARMISD::MEMBARRIER", SDT_ARMMEMBARRIER,
147 def ARMMemBarrierMCR : SDNode<"ARMISD::MEMBARRIER_MCR", SDT_ARMMEMBARRIER,
149 def ARMPreload : SDNode<"ARMISD::PRELOAD", SDT_ARMPREFETCH,
150 [SDNPHasChain, SDNPMayLoad, SDNPMayStore]>;
152 def ARMrbit : SDNode<"ARMISD::RBIT", SDTIntUnaryOp>;
154 def ARMtcret : SDNode<"ARMISD::TC_RETURN", SDT_ARMTCRET,
155 [SDNPHasChain, SDNPOptInGlue, SDNPVariadic]>;
158 def ARMbfi : SDNode<"ARMISD::BFI", SDT_ARMBFI>;
160 //===----------------------------------------------------------------------===//
161 // ARM Instruction Predicate Definitions.
163 def HasV4T : Predicate<"Subtarget->hasV4TOps()">,
164 AssemblerPredicate<"HasV4TOps">;
165 def NoV4T : Predicate<"!Subtarget->hasV4TOps()">;
166 def HasV5T : Predicate<"Subtarget->hasV5TOps()">;
167 def HasV5TE : Predicate<"Subtarget->hasV5TEOps()">,
168 AssemblerPredicate<"HasV5TEOps">;
169 def HasV6 : Predicate<"Subtarget->hasV6Ops()">,
170 AssemblerPredicate<"HasV6Ops">;
171 def NoV6 : Predicate<"!Subtarget->hasV6Ops()">;
172 def HasV6T2 : Predicate<"Subtarget->hasV6T2Ops()">,
173 AssemblerPredicate<"HasV6T2Ops">;
174 def NoV6T2 : Predicate<"!Subtarget->hasV6T2Ops()">;
175 def HasV7 : Predicate<"Subtarget->hasV7Ops()">,
176 AssemblerPredicate<"HasV7Ops">;
177 def NoVFP : Predicate<"!Subtarget->hasVFP2()">;
178 def HasVFP2 : Predicate<"Subtarget->hasVFP2()">,
179 AssemblerPredicate<"FeatureVFP2">;
180 def HasVFP3 : Predicate<"Subtarget->hasVFP3()">,
181 AssemblerPredicate<"FeatureVFP3">;
182 def HasVFP4 : Predicate<"Subtarget->hasVFP4()">,
183 AssemblerPredicate<"FeatureVFP4">;
184 def NoVFP4 : Predicate<"!Subtarget->hasVFP4()">;
185 def HasNEON : Predicate<"Subtarget->hasNEON()">,
186 AssemblerPredicate<"FeatureNEON">;
187 def HasNEON2 : Predicate<"Subtarget->hasNEON2()">,
188 AssemblerPredicate<"FeatureNEON2">;
189 def NoNEON2 : Predicate<"!Subtarget->hasNEON2()">;
190 def HasFP16 : Predicate<"Subtarget->hasFP16()">,
191 AssemblerPredicate<"FeatureFP16">;
192 def HasDivide : Predicate<"Subtarget->hasDivide()">,
193 AssemblerPredicate<"FeatureHWDiv">;
194 def HasT2ExtractPack : Predicate<"Subtarget->hasT2ExtractPack()">,
195 AssemblerPredicate<"FeatureT2XtPk">;
196 def HasThumb2DSP : Predicate<"Subtarget->hasThumb2DSP()">,
197 AssemblerPredicate<"FeatureDSPThumb2">;
198 def HasDB : Predicate<"Subtarget->hasDataBarrier()">,
199 AssemblerPredicate<"FeatureDB">;
200 def HasMP : Predicate<"Subtarget->hasMPExtension()">,
201 AssemblerPredicate<"FeatureMP">;
202 def UseNEONForFP : Predicate<"Subtarget->useNEONForSinglePrecisionFP()">;
203 def DontUseNEONForFP : Predicate<"!Subtarget->useNEONForSinglePrecisionFP()">;
204 def IsThumb : Predicate<"Subtarget->isThumb()">,
205 AssemblerPredicate<"ModeThumb">;
206 def IsThumb1Only : Predicate<"Subtarget->isThumb1Only()">;
207 def IsThumb2 : Predicate<"Subtarget->isThumb2()">,
208 AssemblerPredicate<"ModeThumb,FeatureThumb2">;
209 def IsMClass : Predicate<"Subtarget->isMClass()">,
210 AssemblerPredicate<"FeatureMClass">;
211 def IsARClass : Predicate<"!Subtarget->isMClass()">,
212 AssemblerPredicate<"!FeatureMClass">;
213 def IsARM : Predicate<"!Subtarget->isThumb()">,
214 AssemblerPredicate<"!ModeThumb">;
215 def IsIOS : Predicate<"Subtarget->isTargetIOS()">;
216 def IsNotIOS : Predicate<"!Subtarget->isTargetIOS()">;
217 def IsNaCl : Predicate<"Subtarget->isTargetNaCl()">;
219 // FIXME: Eventually this will be just "hasV6T2Ops".
220 def UseMovt : Predicate<"Subtarget->useMovt()">;
221 def DontUseMovt : Predicate<"!Subtarget->useMovt()">;
222 def UseFPVMLx : Predicate<"Subtarget->useFPVMLx()">;
224 //===----------------------------------------------------------------------===//
225 // ARM Flag Definitions.
227 class RegConstraint<string C> {
228 string Constraints = C;
231 //===----------------------------------------------------------------------===//
232 // ARM specific transformation functions and pattern fragments.
235 // so_imm_neg_XFORM - Return a so_imm value packed into the format described for
236 // so_imm_neg def below.
237 def so_imm_neg_XFORM : SDNodeXForm<imm, [{
238 return CurDAG->getTargetConstant(-(int)N->getZExtValue(), MVT::i32);
241 // so_imm_not_XFORM - Return a so_imm value packed into the format described for
242 // so_imm_not def below.
243 def so_imm_not_XFORM : SDNodeXForm<imm, [{
244 return CurDAG->getTargetConstant(~(int)N->getZExtValue(), MVT::i32);
247 /// imm16_31 predicate - True if the 32-bit immediate is in the range [16,31].
248 def imm16_31 : ImmLeaf<i32, [{
249 return (int32_t)Imm >= 16 && (int32_t)Imm < 32;
252 def so_imm_neg_asmoperand : AsmOperandClass { let Name = "ARMSOImmNeg"; }
253 def so_imm_neg : Operand<i32>, PatLeaf<(imm), [{
254 return ARM_AM::getSOImmVal(-(uint32_t)N->getZExtValue()) != -1;
255 }], so_imm_neg_XFORM> {
256 let ParserMatchClass = so_imm_neg_asmoperand;
259 // Note: this pattern doesn't require an encoder method and such, as it's
260 // only used on aliases (Pat<> and InstAlias<>). The actual encoding
261 // is handled by the destination instructions, which use so_imm.
262 def so_imm_not_asmoperand : AsmOperandClass { let Name = "ARMSOImmNot"; }
263 def so_imm_not : Operand<i32>, PatLeaf<(imm), [{
264 return ARM_AM::getSOImmVal(~(uint32_t)N->getZExtValue()) != -1;
265 }], so_imm_not_XFORM> {
266 let ParserMatchClass = so_imm_not_asmoperand;
269 // sext_16_node predicate - True if the SDNode is sign-extended 16 or more bits.
270 def sext_16_node : PatLeaf<(i32 GPR:$a), [{
271 return CurDAG->ComputeNumSignBits(SDValue(N,0)) >= 17;
274 /// Split a 32-bit immediate into two 16 bit parts.
275 def hi16 : SDNodeXForm<imm, [{
276 return CurDAG->getTargetConstant((uint32_t)N->getZExtValue() >> 16, MVT::i32);
279 def lo16AllZero : PatLeaf<(i32 imm), [{
280 // Returns true if all low 16-bits are 0.
281 return (((uint32_t)N->getZExtValue()) & 0xFFFFUL) == 0;
284 class BinOpWithFlagFrag<dag res> :
285 PatFrag<(ops node:$LHS, node:$RHS, node:$FLAG), res>;
286 class BinOpFrag<dag res> : PatFrag<(ops node:$LHS, node:$RHS), res>;
287 class UnOpFrag <dag res> : PatFrag<(ops node:$Src), res>;
289 // An 'and' node with a single use.
290 def and_su : PatFrag<(ops node:$lhs, node:$rhs), (and node:$lhs, node:$rhs), [{
291 return N->hasOneUse();
294 // An 'xor' node with a single use.
295 def xor_su : PatFrag<(ops node:$lhs, node:$rhs), (xor node:$lhs, node:$rhs), [{
296 return N->hasOneUse();
299 // An 'fmul' node with a single use.
300 def fmul_su : PatFrag<(ops node:$lhs, node:$rhs), (fmul node:$lhs, node:$rhs),[{
301 return N->hasOneUse();
304 // An 'fadd' node which checks for single non-hazardous use.
305 def fadd_mlx : PatFrag<(ops node:$lhs, node:$rhs),(fadd node:$lhs, node:$rhs),[{
306 return hasNoVMLxHazardUse(N);
309 // An 'fsub' node which checks for single non-hazardous use.
310 def fsub_mlx : PatFrag<(ops node:$lhs, node:$rhs),(fsub node:$lhs, node:$rhs),[{
311 return hasNoVMLxHazardUse(N);
314 //===----------------------------------------------------------------------===//
315 // Operand Definitions.
318 // Immediate operands with a shared generic asm render method.
319 class ImmAsmOperand : AsmOperandClass { let RenderMethod = "addImmOperands"; }
322 // FIXME: rename brtarget to t2_brtarget
323 def brtarget : Operand<OtherVT> {
324 let EncoderMethod = "getBranchTargetOpValue";
325 let OperandType = "OPERAND_PCREL";
326 let DecoderMethod = "DecodeT2BROperand";
329 // FIXME: get rid of this one?
330 def uncondbrtarget : Operand<OtherVT> {
331 let EncoderMethod = "getUnconditionalBranchTargetOpValue";
332 let OperandType = "OPERAND_PCREL";
335 // Branch target for ARM. Handles conditional/unconditional
336 def br_target : Operand<OtherVT> {
337 let EncoderMethod = "getARMBranchTargetOpValue";
338 let OperandType = "OPERAND_PCREL";
342 // FIXME: rename bltarget to t2_bl_target?
343 def bltarget : Operand<i32> {
344 // Encoded the same as branch targets.
345 let EncoderMethod = "getBranchTargetOpValue";
346 let OperandType = "OPERAND_PCREL";
349 // Call target for ARM. Handles conditional/unconditional
350 // FIXME: rename bl_target to t2_bltarget?
351 def bl_target : Operand<i32> {
352 let EncoderMethod = "getARMBLTargetOpValue";
353 let OperandType = "OPERAND_PCREL";
356 def blx_target : Operand<i32> {
357 let EncoderMethod = "getARMBLXTargetOpValue";
358 let OperandType = "OPERAND_PCREL";
361 // A list of registers separated by comma. Used by load/store multiple.
362 def RegListAsmOperand : AsmOperandClass { let Name = "RegList"; }
363 def reglist : Operand<i32> {
364 let EncoderMethod = "getRegisterListOpValue";
365 let ParserMatchClass = RegListAsmOperand;
366 let PrintMethod = "printRegisterList";
367 let DecoderMethod = "DecodeRegListOperand";
370 def DPRRegListAsmOperand : AsmOperandClass { let Name = "DPRRegList"; }
371 def dpr_reglist : Operand<i32> {
372 let EncoderMethod = "getRegisterListOpValue";
373 let ParserMatchClass = DPRRegListAsmOperand;
374 let PrintMethod = "printRegisterList";
375 let DecoderMethod = "DecodeDPRRegListOperand";
378 def SPRRegListAsmOperand : AsmOperandClass { let Name = "SPRRegList"; }
379 def spr_reglist : Operand<i32> {
380 let EncoderMethod = "getRegisterListOpValue";
381 let ParserMatchClass = SPRRegListAsmOperand;
382 let PrintMethod = "printRegisterList";
383 let DecoderMethod = "DecodeSPRRegListOperand";
386 // An operand for the CONSTPOOL_ENTRY pseudo-instruction.
387 def cpinst_operand : Operand<i32> {
388 let PrintMethod = "printCPInstOperand";
392 def pclabel : Operand<i32> {
393 let PrintMethod = "printPCLabel";
396 // ADR instruction labels.
397 def adrlabel : Operand<i32> {
398 let EncoderMethod = "getAdrLabelOpValue";
401 def neon_vcvt_imm32 : Operand<i32> {
402 let EncoderMethod = "getNEONVcvtImm32OpValue";
403 let DecoderMethod = "DecodeVCVTImmOperand";
406 // rot_imm: An integer that encodes a rotate amount. Must be 8, 16, or 24.
407 def rot_imm_XFORM: SDNodeXForm<imm, [{
408 switch (N->getZExtValue()){
410 case 0: return CurDAG->getTargetConstant(0, MVT::i32);
411 case 8: return CurDAG->getTargetConstant(1, MVT::i32);
412 case 16: return CurDAG->getTargetConstant(2, MVT::i32);
413 case 24: return CurDAG->getTargetConstant(3, MVT::i32);
416 def RotImmAsmOperand : AsmOperandClass {
418 let ParserMethod = "parseRotImm";
420 def rot_imm : Operand<i32>, PatLeaf<(i32 imm), [{
421 int32_t v = N->getZExtValue();
422 return v == 8 || v == 16 || v == 24; }],
424 let PrintMethod = "printRotImmOperand";
425 let ParserMatchClass = RotImmAsmOperand;
428 // shift_imm: An integer that encodes a shift amount and the type of shift
429 // (asr or lsl). The 6-bit immediate encodes as:
432 // {4-0} imm5 shift amount.
433 // asr #32 encoded as imm5 == 0.
434 def ShifterImmAsmOperand : AsmOperandClass {
435 let Name = "ShifterImm";
436 let ParserMethod = "parseShifterImm";
438 def shift_imm : Operand<i32> {
439 let PrintMethod = "printShiftImmOperand";
440 let ParserMatchClass = ShifterImmAsmOperand;
443 // shifter_operand operands: so_reg_reg, so_reg_imm, and so_imm.
444 def ShiftedRegAsmOperand : AsmOperandClass { let Name = "RegShiftedReg"; }
445 def so_reg_reg : Operand<i32>, // reg reg imm
446 ComplexPattern<i32, 3, "SelectRegShifterOperand",
447 [shl, srl, sra, rotr]> {
448 let EncoderMethod = "getSORegRegOpValue";
449 let PrintMethod = "printSORegRegOperand";
450 let DecoderMethod = "DecodeSORegRegOperand";
451 let ParserMatchClass = ShiftedRegAsmOperand;
452 let MIOperandInfo = (ops GPRnopc, GPRnopc, i32imm);
455 def ShiftedImmAsmOperand : AsmOperandClass { let Name = "RegShiftedImm"; }
456 def so_reg_imm : Operand<i32>, // reg imm
457 ComplexPattern<i32, 2, "SelectImmShifterOperand",
458 [shl, srl, sra, rotr]> {
459 let EncoderMethod = "getSORegImmOpValue";
460 let PrintMethod = "printSORegImmOperand";
461 let DecoderMethod = "DecodeSORegImmOperand";
462 let ParserMatchClass = ShiftedImmAsmOperand;
463 let MIOperandInfo = (ops GPR, i32imm);
466 // FIXME: Does this need to be distinct from so_reg?
467 def shift_so_reg_reg : Operand<i32>, // reg reg imm
468 ComplexPattern<i32, 3, "SelectShiftRegShifterOperand",
469 [shl,srl,sra,rotr]> {
470 let EncoderMethod = "getSORegRegOpValue";
471 let PrintMethod = "printSORegRegOperand";
472 let DecoderMethod = "DecodeSORegRegOperand";
473 let ParserMatchClass = ShiftedRegAsmOperand;
474 let MIOperandInfo = (ops GPR, GPR, i32imm);
477 // FIXME: Does this need to be distinct from so_reg?
478 def shift_so_reg_imm : Operand<i32>, // reg reg imm
479 ComplexPattern<i32, 2, "SelectShiftImmShifterOperand",
480 [shl,srl,sra,rotr]> {
481 let EncoderMethod = "getSORegImmOpValue";
482 let PrintMethod = "printSORegImmOperand";
483 let DecoderMethod = "DecodeSORegImmOperand";
484 let ParserMatchClass = ShiftedImmAsmOperand;
485 let MIOperandInfo = (ops GPR, i32imm);
489 // so_imm - Match a 32-bit shifter_operand immediate operand, which is an
490 // 8-bit immediate rotated by an arbitrary number of bits.
491 def SOImmAsmOperand: ImmAsmOperand { let Name = "ARMSOImm"; }
492 def so_imm : Operand<i32>, ImmLeaf<i32, [{
493 return ARM_AM::getSOImmVal(Imm) != -1;
495 let EncoderMethod = "getSOImmOpValue";
496 let ParserMatchClass = SOImmAsmOperand;
497 let DecoderMethod = "DecodeSOImmOperand";
500 // Break so_imm's up into two pieces. This handles immediates with up to 16
501 // bits set in them. This uses so_imm2part to match and so_imm2part_[12] to
502 // get the first/second pieces.
503 def so_imm2part : PatLeaf<(imm), [{
504 return ARM_AM::isSOImmTwoPartVal((unsigned)N->getZExtValue());
507 /// arm_i32imm - True for +V6T2, or true only if so_imm2part is true.
509 def arm_i32imm : PatLeaf<(imm), [{
510 if (Subtarget->hasV6T2Ops())
512 return ARM_AM::isSOImmTwoPartVal((unsigned)N->getZExtValue());
515 /// imm0_1 predicate - Immediate in the range [0,1].
516 def Imm0_1AsmOperand: ImmAsmOperand { let Name = "Imm0_1"; }
517 def imm0_1 : Operand<i32> { let ParserMatchClass = Imm0_1AsmOperand; }
519 /// imm0_3 predicate - Immediate in the range [0,3].
520 def Imm0_3AsmOperand: ImmAsmOperand { let Name = "Imm0_3"; }
521 def imm0_3 : Operand<i32> { let ParserMatchClass = Imm0_3AsmOperand; }
523 /// imm0_7 predicate - Immediate in the range [0,7].
524 def Imm0_7AsmOperand: ImmAsmOperand { let Name = "Imm0_7"; }
525 def imm0_7 : Operand<i32>, ImmLeaf<i32, [{
526 return Imm >= 0 && Imm < 8;
528 let ParserMatchClass = Imm0_7AsmOperand;
531 /// imm8 predicate - Immediate is exactly 8.
532 def Imm8AsmOperand: ImmAsmOperand { let Name = "Imm8"; }
533 def imm8 : Operand<i32>, ImmLeaf<i32, [{ return Imm == 8; }]> {
534 let ParserMatchClass = Imm8AsmOperand;
537 /// imm16 predicate - Immediate is exactly 16.
538 def Imm16AsmOperand: ImmAsmOperand { let Name = "Imm16"; }
539 def imm16 : Operand<i32>, ImmLeaf<i32, [{ return Imm == 16; }]> {
540 let ParserMatchClass = Imm16AsmOperand;
543 /// imm32 predicate - Immediate is exactly 32.
544 def Imm32AsmOperand: ImmAsmOperand { let Name = "Imm32"; }
545 def imm32 : Operand<i32>, ImmLeaf<i32, [{ return Imm == 32; }]> {
546 let ParserMatchClass = Imm32AsmOperand;
549 /// imm1_7 predicate - Immediate in the range [1,7].
550 def Imm1_7AsmOperand: ImmAsmOperand { let Name = "Imm1_7"; }
551 def imm1_7 : Operand<i32>, ImmLeaf<i32, [{ return Imm > 0 && Imm < 8; }]> {
552 let ParserMatchClass = Imm1_7AsmOperand;
555 /// imm1_15 predicate - Immediate in the range [1,15].
556 def Imm1_15AsmOperand: ImmAsmOperand { let Name = "Imm1_15"; }
557 def imm1_15 : Operand<i32>, ImmLeaf<i32, [{ return Imm > 0 && Imm < 16; }]> {
558 let ParserMatchClass = Imm1_15AsmOperand;
561 /// imm1_31 predicate - Immediate in the range [1,31].
562 def Imm1_31AsmOperand: ImmAsmOperand { let Name = "Imm1_31"; }
563 def imm1_31 : Operand<i32>, ImmLeaf<i32, [{ return Imm > 0 && Imm < 32; }]> {
564 let ParserMatchClass = Imm1_31AsmOperand;
567 /// imm0_15 predicate - Immediate in the range [0,15].
568 def Imm0_15AsmOperand: ImmAsmOperand { let Name = "Imm0_15"; }
569 def imm0_15 : Operand<i32>, ImmLeaf<i32, [{
570 return Imm >= 0 && Imm < 16;
572 let ParserMatchClass = Imm0_15AsmOperand;
575 /// imm0_31 predicate - True if the 32-bit immediate is in the range [0,31].
576 def Imm0_31AsmOperand: ImmAsmOperand { let Name = "Imm0_31"; }
577 def imm0_31 : Operand<i32>, ImmLeaf<i32, [{
578 return Imm >= 0 && Imm < 32;
580 let ParserMatchClass = Imm0_31AsmOperand;
583 /// imm0_32 predicate - True if the 32-bit immediate is in the range [0,32].
584 def Imm0_32AsmOperand: ImmAsmOperand { let Name = "Imm0_32"; }
585 def imm0_32 : Operand<i32>, ImmLeaf<i32, [{
586 return Imm >= 0 && Imm < 32;
588 let ParserMatchClass = Imm0_32AsmOperand;
591 /// imm0_63 predicate - True if the 32-bit immediate is in the range [0,63].
592 def Imm0_63AsmOperand: ImmAsmOperand { let Name = "Imm0_63"; }
593 def imm0_63 : Operand<i32>, ImmLeaf<i32, [{
594 return Imm >= 0 && Imm < 64;
596 let ParserMatchClass = Imm0_63AsmOperand;
599 /// imm0_255 predicate - Immediate in the range [0,255].
600 def Imm0_255AsmOperand : ImmAsmOperand { let Name = "Imm0_255"; }
601 def imm0_255 : Operand<i32>, ImmLeaf<i32, [{ return Imm >= 0 && Imm < 256; }]> {
602 let ParserMatchClass = Imm0_255AsmOperand;
605 /// imm0_65535 - An immediate is in the range [0.65535].
606 def Imm0_65535AsmOperand: ImmAsmOperand { let Name = "Imm0_65535"; }
607 def imm0_65535 : Operand<i32>, ImmLeaf<i32, [{
608 return Imm >= 0 && Imm < 65536;
610 let ParserMatchClass = Imm0_65535AsmOperand;
613 // imm0_65535_expr - For movt/movw - 16-bit immediate that can also reference
614 // a relocatable expression.
616 // FIXME: This really needs a Thumb version separate from the ARM version.
617 // While the range is the same, and can thus use the same match class,
618 // the encoding is different so it should have a different encoder method.
619 def Imm0_65535ExprAsmOperand: ImmAsmOperand { let Name = "Imm0_65535Expr"; }
620 def imm0_65535_expr : Operand<i32> {
621 let EncoderMethod = "getHiLo16ImmOpValue";
622 let ParserMatchClass = Imm0_65535ExprAsmOperand;
625 /// imm24b - True if the 32-bit immediate is encodable in 24 bits.
626 def Imm24bitAsmOperand: ImmAsmOperand { let Name = "Imm24bit"; }
627 def imm24b : Operand<i32>, ImmLeaf<i32, [{
628 return Imm >= 0 && Imm <= 0xffffff;
630 let ParserMatchClass = Imm24bitAsmOperand;
634 /// bf_inv_mask_imm predicate - An AND mask to clear an arbitrary width bitfield
636 def BitfieldAsmOperand : AsmOperandClass {
637 let Name = "Bitfield";
638 let ParserMethod = "parseBitfield";
640 def bf_inv_mask_imm : Operand<i32>,
642 return ARM::isBitFieldInvertedMask(N->getZExtValue());
644 let EncoderMethod = "getBitfieldInvertedMaskOpValue";
645 let PrintMethod = "printBitfieldInvMaskImmOperand";
646 let DecoderMethod = "DecodeBitfieldMaskOperand";
647 let ParserMatchClass = BitfieldAsmOperand;
650 def imm1_32_XFORM: SDNodeXForm<imm, [{
651 return CurDAG->getTargetConstant((int)N->getZExtValue() - 1, MVT::i32);
653 def Imm1_32AsmOperand: AsmOperandClass { let Name = "Imm1_32"; }
654 def imm1_32 : Operand<i32>, PatLeaf<(imm), [{
655 uint64_t Imm = N->getZExtValue();
656 return Imm > 0 && Imm <= 32;
659 let PrintMethod = "printImmPlusOneOperand";
660 let ParserMatchClass = Imm1_32AsmOperand;
663 def imm1_16_XFORM: SDNodeXForm<imm, [{
664 return CurDAG->getTargetConstant((int)N->getZExtValue() - 1, MVT::i32);
666 def Imm1_16AsmOperand: AsmOperandClass { let Name = "Imm1_16"; }
667 def imm1_16 : Operand<i32>, PatLeaf<(imm), [{ return Imm > 0 && Imm <= 16; }],
669 let PrintMethod = "printImmPlusOneOperand";
670 let ParserMatchClass = Imm1_16AsmOperand;
673 // Define ARM specific addressing modes.
674 // addrmode_imm12 := reg +/- imm12
676 def MemImm12OffsetAsmOperand : AsmOperandClass { let Name = "MemImm12Offset"; }
677 def addrmode_imm12 : Operand<i32>,
678 ComplexPattern<i32, 2, "SelectAddrModeImm12", []> {
679 // 12-bit immediate operand. Note that instructions using this encode
680 // #0 and #-0 differently. We flag #-0 as the magic value INT32_MIN. All other
681 // immediate values are as normal.
683 let EncoderMethod = "getAddrModeImm12OpValue";
684 let PrintMethod = "printAddrModeImm12Operand";
685 let DecoderMethod = "DecodeAddrModeImm12Operand";
686 let ParserMatchClass = MemImm12OffsetAsmOperand;
687 let MIOperandInfo = (ops GPR:$base, i32imm:$offsimm);
689 // ldst_so_reg := reg +/- reg shop imm
691 def MemRegOffsetAsmOperand : AsmOperandClass { let Name = "MemRegOffset"; }
692 def ldst_so_reg : Operand<i32>,
693 ComplexPattern<i32, 3, "SelectLdStSOReg", []> {
694 let EncoderMethod = "getLdStSORegOpValue";
695 // FIXME: Simplify the printer
696 let PrintMethod = "printAddrMode2Operand";
697 let DecoderMethod = "DecodeSORegMemOperand";
698 let ParserMatchClass = MemRegOffsetAsmOperand;
699 let MIOperandInfo = (ops GPR:$base, GPRnopc:$offsreg, i32imm:$shift);
702 // postidx_imm8 := +/- [0,255]
705 // {8} 1 is imm8 is non-negative. 0 otherwise.
706 // {7-0} [0,255] imm8 value.
707 def PostIdxImm8AsmOperand : AsmOperandClass { let Name = "PostIdxImm8"; }
708 def postidx_imm8 : Operand<i32> {
709 let PrintMethod = "printPostIdxImm8Operand";
710 let ParserMatchClass = PostIdxImm8AsmOperand;
711 let MIOperandInfo = (ops i32imm);
714 // postidx_imm8s4 := +/- [0,1020]
717 // {8} 1 is imm8 is non-negative. 0 otherwise.
718 // {7-0} [0,255] imm8 value, scaled by 4.
719 def PostIdxImm8s4AsmOperand : AsmOperandClass { let Name = "PostIdxImm8s4"; }
720 def postidx_imm8s4 : Operand<i32> {
721 let PrintMethod = "printPostIdxImm8s4Operand";
722 let ParserMatchClass = PostIdxImm8s4AsmOperand;
723 let MIOperandInfo = (ops i32imm);
727 // postidx_reg := +/- reg
729 def PostIdxRegAsmOperand : AsmOperandClass {
730 let Name = "PostIdxReg";
731 let ParserMethod = "parsePostIdxReg";
733 def postidx_reg : Operand<i32> {
734 let EncoderMethod = "getPostIdxRegOpValue";
735 let DecoderMethod = "DecodePostIdxReg";
736 let PrintMethod = "printPostIdxRegOperand";
737 let ParserMatchClass = PostIdxRegAsmOperand;
738 let MIOperandInfo = (ops GPR, i32imm);
742 // addrmode2 := reg +/- imm12
743 // := reg +/- reg shop imm
745 // FIXME: addrmode2 should be refactored the rest of the way to always
746 // use explicit imm vs. reg versions above (addrmode_imm12 and ldst_so_reg).
747 def AddrMode2AsmOperand : AsmOperandClass { let Name = "AddrMode2"; }
748 def addrmode2 : Operand<i32>,
749 ComplexPattern<i32, 3, "SelectAddrMode2", []> {
750 let EncoderMethod = "getAddrMode2OpValue";
751 let PrintMethod = "printAddrMode2Operand";
752 let ParserMatchClass = AddrMode2AsmOperand;
753 let MIOperandInfo = (ops GPR:$base, GPR:$offsreg, i32imm:$offsimm);
756 def PostIdxRegShiftedAsmOperand : AsmOperandClass {
757 let Name = "PostIdxRegShifted";
758 let ParserMethod = "parsePostIdxReg";
760 def am2offset_reg : Operand<i32>,
761 ComplexPattern<i32, 2, "SelectAddrMode2OffsetReg",
762 [], [SDNPWantRoot]> {
763 let EncoderMethod = "getAddrMode2OffsetOpValue";
764 let PrintMethod = "printAddrMode2OffsetOperand";
765 // When using this for assembly, it's always as a post-index offset.
766 let ParserMatchClass = PostIdxRegShiftedAsmOperand;
767 let MIOperandInfo = (ops GPRnopc, i32imm);
770 // FIXME: am2offset_imm should only need the immediate, not the GPR. Having
771 // the GPR is purely vestigal at this point.
772 def AM2OffsetImmAsmOperand : AsmOperandClass { let Name = "AM2OffsetImm"; }
773 def am2offset_imm : Operand<i32>,
774 ComplexPattern<i32, 2, "SelectAddrMode2OffsetImm",
775 [], [SDNPWantRoot]> {
776 let EncoderMethod = "getAddrMode2OffsetOpValue";
777 let PrintMethod = "printAddrMode2OffsetOperand";
778 let ParserMatchClass = AM2OffsetImmAsmOperand;
779 let MIOperandInfo = (ops GPRnopc, i32imm);
783 // addrmode3 := reg +/- reg
784 // addrmode3 := reg +/- imm8
786 // FIXME: split into imm vs. reg versions.
787 def AddrMode3AsmOperand : AsmOperandClass { let Name = "AddrMode3"; }
788 def addrmode3 : Operand<i32>,
789 ComplexPattern<i32, 3, "SelectAddrMode3", []> {
790 let EncoderMethod = "getAddrMode3OpValue";
791 let PrintMethod = "printAddrMode3Operand";
792 let ParserMatchClass = AddrMode3AsmOperand;
793 let MIOperandInfo = (ops GPR:$base, GPR:$offsreg, i32imm:$offsimm);
796 // FIXME: split into imm vs. reg versions.
797 // FIXME: parser method to handle +/- register.
798 def AM3OffsetAsmOperand : AsmOperandClass {
799 let Name = "AM3Offset";
800 let ParserMethod = "parseAM3Offset";
802 def am3offset : Operand<i32>,
803 ComplexPattern<i32, 2, "SelectAddrMode3Offset",
804 [], [SDNPWantRoot]> {
805 let EncoderMethod = "getAddrMode3OffsetOpValue";
806 let PrintMethod = "printAddrMode3OffsetOperand";
807 let ParserMatchClass = AM3OffsetAsmOperand;
808 let MIOperandInfo = (ops GPR, i32imm);
811 // ldstm_mode := {ia, ib, da, db}
813 def ldstm_mode : OptionalDefOperand<OtherVT, (ops i32), (ops (i32 1))> {
814 let EncoderMethod = "getLdStmModeOpValue";
815 let PrintMethod = "printLdStmModeOperand";
818 // addrmode5 := reg +/- imm8*4
820 def AddrMode5AsmOperand : AsmOperandClass { let Name = "AddrMode5"; }
821 def addrmode5 : Operand<i32>,
822 ComplexPattern<i32, 2, "SelectAddrMode5", []> {
823 let PrintMethod = "printAddrMode5Operand";
824 let EncoderMethod = "getAddrMode5OpValue";
825 let DecoderMethod = "DecodeAddrMode5Operand";
826 let ParserMatchClass = AddrMode5AsmOperand;
827 let MIOperandInfo = (ops GPR:$base, i32imm);
830 // addrmode6 := reg with optional alignment
832 def AddrMode6AsmOperand : AsmOperandClass { let Name = "AlignedMemory"; }
833 def addrmode6 : Operand<i32>,
834 ComplexPattern<i32, 2, "SelectAddrMode6", [], [SDNPWantParent]>{
835 let PrintMethod = "printAddrMode6Operand";
836 let MIOperandInfo = (ops GPR:$addr, i32imm:$align);
837 let EncoderMethod = "getAddrMode6AddressOpValue";
838 let DecoderMethod = "DecodeAddrMode6Operand";
839 let ParserMatchClass = AddrMode6AsmOperand;
842 def am6offset : Operand<i32>,
843 ComplexPattern<i32, 1, "SelectAddrMode6Offset",
844 [], [SDNPWantRoot]> {
845 let PrintMethod = "printAddrMode6OffsetOperand";
846 let MIOperandInfo = (ops GPR);
847 let EncoderMethod = "getAddrMode6OffsetOpValue";
848 let DecoderMethod = "DecodeGPRRegisterClass";
851 // Special version of addrmode6 to handle alignment encoding for VST1/VLD1
852 // (single element from one lane) for size 32.
853 def addrmode6oneL32 : Operand<i32>,
854 ComplexPattern<i32, 2, "SelectAddrMode6", [], [SDNPWantParent]>{
855 let PrintMethod = "printAddrMode6Operand";
856 let MIOperandInfo = (ops GPR:$addr, i32imm);
857 let EncoderMethod = "getAddrMode6OneLane32AddressOpValue";
860 // Special version of addrmode6 to handle alignment encoding for VLD-dup
861 // instructions, specifically VLD4-dup.
862 def addrmode6dup : Operand<i32>,
863 ComplexPattern<i32, 2, "SelectAddrMode6", [], [SDNPWantParent]>{
864 let PrintMethod = "printAddrMode6Operand";
865 let MIOperandInfo = (ops GPR:$addr, i32imm);
866 let EncoderMethod = "getAddrMode6DupAddressOpValue";
867 // FIXME: This is close, but not quite right. The alignment specifier is
869 let ParserMatchClass = AddrMode6AsmOperand;
872 // addrmodepc := pc + reg
874 def addrmodepc : Operand<i32>,
875 ComplexPattern<i32, 2, "SelectAddrModePC", []> {
876 let PrintMethod = "printAddrModePCOperand";
877 let MIOperandInfo = (ops GPR, i32imm);
880 // addr_offset_none := reg
882 def MemNoOffsetAsmOperand : AsmOperandClass { let Name = "MemNoOffset"; }
883 def addr_offset_none : Operand<i32>,
884 ComplexPattern<i32, 1, "SelectAddrOffsetNone", []> {
885 let PrintMethod = "printAddrMode7Operand";
886 let DecoderMethod = "DecodeAddrMode7Operand";
887 let ParserMatchClass = MemNoOffsetAsmOperand;
888 let MIOperandInfo = (ops GPR:$base);
891 def nohash_imm : Operand<i32> {
892 let PrintMethod = "printNoHashImmediate";
895 def CoprocNumAsmOperand : AsmOperandClass {
896 let Name = "CoprocNum";
897 let ParserMethod = "parseCoprocNumOperand";
899 def p_imm : Operand<i32> {
900 let PrintMethod = "printPImmediate";
901 let ParserMatchClass = CoprocNumAsmOperand;
902 let DecoderMethod = "DecodeCoprocessor";
905 def CoprocRegAsmOperand : AsmOperandClass {
906 let Name = "CoprocReg";
907 let ParserMethod = "parseCoprocRegOperand";
909 def c_imm : Operand<i32> {
910 let PrintMethod = "printCImmediate";
911 let ParserMatchClass = CoprocRegAsmOperand;
913 def CoprocOptionAsmOperand : AsmOperandClass {
914 let Name = "CoprocOption";
915 let ParserMethod = "parseCoprocOptionOperand";
917 def coproc_option_imm : Operand<i32> {
918 let PrintMethod = "printCoprocOptionImm";
919 let ParserMatchClass = CoprocOptionAsmOperand;
922 //===----------------------------------------------------------------------===//
924 include "ARMInstrFormats.td"
926 //===----------------------------------------------------------------------===//
927 // Multiclass helpers...
930 /// AsI1_bin_irs - Defines a set of (op r, {so_imm|r|so_reg}) patterns for a
931 /// binop that produces a value.
932 multiclass AsI1_bin_irs<bits<4> opcod, string opc,
933 InstrItinClass iii, InstrItinClass iir, InstrItinClass iis,
934 PatFrag opnode, string baseOpc, bit Commutable = 0> {
935 // The register-immediate version is re-materializable. This is useful
936 // in particular for taking the address of a local.
937 let isReMaterializable = 1 in {
938 def ri : AsI1<opcod, (outs GPR:$Rd), (ins GPR:$Rn, so_imm:$imm), DPFrm,
939 iii, opc, "\t$Rd, $Rn, $imm",
940 [(set GPR:$Rd, (opnode GPR:$Rn, so_imm:$imm))]> {
945 let Inst{19-16} = Rn;
946 let Inst{15-12} = Rd;
947 let Inst{11-0} = imm;
950 def rr : AsI1<opcod, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm), DPFrm,
951 iir, opc, "\t$Rd, $Rn, $Rm",
952 [(set GPR:$Rd, (opnode GPR:$Rn, GPR:$Rm))]> {
957 let isCommutable = Commutable;
958 let Inst{19-16} = Rn;
959 let Inst{15-12} = Rd;
960 let Inst{11-4} = 0b00000000;
964 def rsi : AsI1<opcod, (outs GPR:$Rd),
965 (ins GPR:$Rn, so_reg_imm:$shift), DPSoRegImmFrm,
966 iis, opc, "\t$Rd, $Rn, $shift",
967 [(set GPR:$Rd, (opnode GPR:$Rn, so_reg_imm:$shift))]> {
972 let Inst{19-16} = Rn;
973 let Inst{15-12} = Rd;
974 let Inst{11-5} = shift{11-5};
976 let Inst{3-0} = shift{3-0};
979 def rsr : AsI1<opcod, (outs GPR:$Rd),
980 (ins GPR:$Rn, so_reg_reg:$shift), DPSoRegRegFrm,
981 iis, opc, "\t$Rd, $Rn, $shift",
982 [(set GPR:$Rd, (opnode GPR:$Rn, so_reg_reg:$shift))]> {
987 let Inst{19-16} = Rn;
988 let Inst{15-12} = Rd;
989 let Inst{11-8} = shift{11-8};
991 let Inst{6-5} = shift{6-5};
993 let Inst{3-0} = shift{3-0};
996 // Assembly aliases for optional destination operand when it's the same
997 // as the source operand.
998 def : InstAlias<!strconcat(opc, "${s}${p} $Rdn, $imm"),
999 (!cast<Instruction>(!strconcat(baseOpc, "ri")) GPR:$Rdn, GPR:$Rdn,
1000 so_imm:$imm, pred:$p,
1003 def : InstAlias<!strconcat(opc, "${s}${p} $Rdn, $Rm"),
1004 (!cast<Instruction>(!strconcat(baseOpc, "rr")) GPR:$Rdn, GPR:$Rdn,
1008 def : InstAlias<!strconcat(opc, "${s}${p} $Rdn, $shift"),
1009 (!cast<Instruction>(!strconcat(baseOpc, "rsi")) GPR:$Rdn, GPR:$Rdn,
1010 so_reg_imm:$shift, pred:$p,
1013 def : InstAlias<!strconcat(opc, "${s}${p} $Rdn, $shift"),
1014 (!cast<Instruction>(!strconcat(baseOpc, "rsr")) GPR:$Rdn, GPR:$Rdn,
1015 so_reg_reg:$shift, pred:$p,
1021 /// AsI1_rbin_irs - Same as AsI1_bin_irs except the order of operands are
1022 /// reversed. The 'rr' form is only defined for the disassembler; for codegen
1023 /// it is equivalent to the AsI1_bin_irs counterpart.
1024 multiclass AsI1_rbin_irs<bits<4> opcod, string opc,
1025 InstrItinClass iii, InstrItinClass iir, InstrItinClass iis,
1026 PatFrag opnode, string baseOpc, bit Commutable = 0> {
1027 // The register-immediate version is re-materializable. This is useful
1028 // in particular for taking the address of a local.
1029 let isReMaterializable = 1 in {
1030 def ri : AsI1<opcod, (outs GPR:$Rd), (ins GPR:$Rn, so_imm:$imm), DPFrm,
1031 iii, opc, "\t$Rd, $Rn, $imm",
1032 [(set GPR:$Rd, (opnode so_imm:$imm, GPR:$Rn))]> {
1037 let Inst{19-16} = Rn;
1038 let Inst{15-12} = Rd;
1039 let Inst{11-0} = imm;
1042 def rr : AsI1<opcod, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm), DPFrm,
1043 iir, opc, "\t$Rd, $Rn, $Rm",
1044 [/* pattern left blank */]> {
1048 let Inst{11-4} = 0b00000000;
1051 let Inst{15-12} = Rd;
1052 let Inst{19-16} = Rn;
1055 def rsi : AsI1<opcod, (outs GPR:$Rd),
1056 (ins GPR:$Rn, so_reg_imm:$shift), DPSoRegImmFrm,
1057 iis, opc, "\t$Rd, $Rn, $shift",
1058 [(set GPR:$Rd, (opnode so_reg_imm:$shift, GPR:$Rn))]> {
1063 let Inst{19-16} = Rn;
1064 let Inst{15-12} = Rd;
1065 let Inst{11-5} = shift{11-5};
1067 let Inst{3-0} = shift{3-0};
1070 def rsr : AsI1<opcod, (outs GPR:$Rd),
1071 (ins GPR:$Rn, so_reg_reg:$shift), DPSoRegRegFrm,
1072 iis, opc, "\t$Rd, $Rn, $shift",
1073 [(set GPR:$Rd, (opnode so_reg_reg:$shift, GPR:$Rn))]> {
1078 let Inst{19-16} = Rn;
1079 let Inst{15-12} = Rd;
1080 let Inst{11-8} = shift{11-8};
1082 let Inst{6-5} = shift{6-5};
1084 let Inst{3-0} = shift{3-0};
1087 // Assembly aliases for optional destination operand when it's the same
1088 // as the source operand.
1089 def : InstAlias<!strconcat(opc, "${s}${p} $Rdn, $imm"),
1090 (!cast<Instruction>(!strconcat(baseOpc, "ri")) GPR:$Rdn, GPR:$Rdn,
1091 so_imm:$imm, pred:$p,
1094 def : InstAlias<!strconcat(opc, "${s}${p} $Rdn, $Rm"),
1095 (!cast<Instruction>(!strconcat(baseOpc, "rr")) GPR:$Rdn, GPR:$Rdn,
1099 def : InstAlias<!strconcat(opc, "${s}${p} $Rdn, $shift"),
1100 (!cast<Instruction>(!strconcat(baseOpc, "rsi")) GPR:$Rdn, GPR:$Rdn,
1101 so_reg_imm:$shift, pred:$p,
1104 def : InstAlias<!strconcat(opc, "${s}${p} $Rdn, $shift"),
1105 (!cast<Instruction>(!strconcat(baseOpc, "rsr")) GPR:$Rdn, GPR:$Rdn,
1106 so_reg_reg:$shift, pred:$p,
1112 /// AsI1_bin_s_irs - Same as AsI1_bin_irs except it sets the 's' bit by default.
1114 /// These opcodes will be converted to the real non-S opcodes by
1115 /// AdjustInstrPostInstrSelection after giving them an optional CPSR operand.
1116 let hasPostISelHook = 1, Defs = [CPSR] in {
1117 multiclass AsI1_bin_s_irs<InstrItinClass iii, InstrItinClass iir,
1118 InstrItinClass iis, PatFrag opnode,
1119 bit Commutable = 0> {
1120 def ri : ARMPseudoInst<(outs GPR:$Rd), (ins GPR:$Rn, so_imm:$imm, pred:$p),
1122 [(set GPR:$Rd, CPSR, (opnode GPR:$Rn, so_imm:$imm))]>;
1124 def rr : ARMPseudoInst<(outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm, pred:$p),
1126 [(set GPR:$Rd, CPSR, (opnode GPR:$Rn, GPR:$Rm))]> {
1127 let isCommutable = Commutable;
1129 def rsi : ARMPseudoInst<(outs GPR:$Rd),
1130 (ins GPR:$Rn, so_reg_imm:$shift, pred:$p),
1132 [(set GPR:$Rd, CPSR, (opnode GPR:$Rn,
1133 so_reg_imm:$shift))]>;
1135 def rsr : ARMPseudoInst<(outs GPR:$Rd),
1136 (ins GPR:$Rn, so_reg_reg:$shift, pred:$p),
1138 [(set GPR:$Rd, CPSR, (opnode GPR:$Rn,
1139 so_reg_reg:$shift))]>;
1143 /// AsI1_rbin_s_is - Same as AsI1_bin_s_irs, except selection DAG
1144 /// operands are reversed.
1145 let hasPostISelHook = 1, Defs = [CPSR] in {
1146 multiclass AsI1_rbin_s_is<InstrItinClass iii, InstrItinClass iir,
1147 InstrItinClass iis, PatFrag opnode,
1148 bit Commutable = 0> {
1149 def ri : ARMPseudoInst<(outs GPR:$Rd), (ins GPR:$Rn, so_imm:$imm, pred:$p),
1151 [(set GPR:$Rd, CPSR, (opnode so_imm:$imm, GPR:$Rn))]>;
1153 def rsi : ARMPseudoInst<(outs GPR:$Rd),
1154 (ins GPR:$Rn, so_reg_imm:$shift, pred:$p),
1156 [(set GPR:$Rd, CPSR, (opnode so_reg_imm:$shift,
1159 def rsr : ARMPseudoInst<(outs GPR:$Rd),
1160 (ins GPR:$Rn, so_reg_reg:$shift, pred:$p),
1162 [(set GPR:$Rd, CPSR, (opnode so_reg_reg:$shift,
1167 /// AI1_cmp_irs - Defines a set of (op r, {so_imm|r|so_reg}) cmp / test
1168 /// patterns. Similar to AsI1_bin_irs except the instruction does not produce
1169 /// a explicit result, only implicitly set CPSR.
1170 let isCompare = 1, Defs = [CPSR] in {
1171 multiclass AI1_cmp_irs<bits<4> opcod, string opc,
1172 InstrItinClass iii, InstrItinClass iir, InstrItinClass iis,
1173 PatFrag opnode, bit Commutable = 0> {
1174 def ri : AI1<opcod, (outs), (ins GPR:$Rn, so_imm:$imm), DPFrm, iii,
1176 [(opnode GPR:$Rn, so_imm:$imm)]> {
1181 let Inst{19-16} = Rn;
1182 let Inst{15-12} = 0b0000;
1183 let Inst{11-0} = imm;
1185 def rr : AI1<opcod, (outs), (ins GPR:$Rn, GPR:$Rm), DPFrm, iir,
1187 [(opnode GPR:$Rn, GPR:$Rm)]> {
1190 let isCommutable = Commutable;
1193 let Inst{19-16} = Rn;
1194 let Inst{15-12} = 0b0000;
1195 let Inst{11-4} = 0b00000000;
1198 def rsi : AI1<opcod, (outs),
1199 (ins GPR:$Rn, so_reg_imm:$shift), DPSoRegImmFrm, iis,
1200 opc, "\t$Rn, $shift",
1201 [(opnode GPR:$Rn, so_reg_imm:$shift)]> {
1206 let Inst{19-16} = Rn;
1207 let Inst{15-12} = 0b0000;
1208 let Inst{11-5} = shift{11-5};
1210 let Inst{3-0} = shift{3-0};
1212 def rsr : AI1<opcod, (outs),
1213 (ins GPR:$Rn, so_reg_reg:$shift), DPSoRegRegFrm, iis,
1214 opc, "\t$Rn, $shift",
1215 [(opnode GPR:$Rn, so_reg_reg:$shift)]> {
1220 let Inst{19-16} = Rn;
1221 let Inst{15-12} = 0b0000;
1222 let Inst{11-8} = shift{11-8};
1224 let Inst{6-5} = shift{6-5};
1226 let Inst{3-0} = shift{3-0};
1232 /// AI_ext_rrot - A unary operation with two forms: one whose operand is a
1233 /// register and one whose operand is a register rotated by 8/16/24.
1234 /// FIXME: Remove the 'r' variant. Its rot_imm is zero.
1235 class AI_ext_rrot<bits<8> opcod, string opc, PatFrag opnode>
1236 : AExtI<opcod, (outs GPRnopc:$Rd), (ins GPRnopc:$Rm, rot_imm:$rot),
1237 IIC_iEXTr, opc, "\t$Rd, $Rm$rot",
1238 [(set GPRnopc:$Rd, (opnode (rotr GPRnopc:$Rm, rot_imm:$rot)))]>,
1239 Requires<[IsARM, HasV6]> {
1243 let Inst{19-16} = 0b1111;
1244 let Inst{15-12} = Rd;
1245 let Inst{11-10} = rot;
1249 class AI_ext_rrot_np<bits<8> opcod, string opc>
1250 : AExtI<opcod, (outs GPRnopc:$Rd), (ins GPRnopc:$Rm, rot_imm:$rot),
1251 IIC_iEXTr, opc, "\t$Rd, $Rm$rot", []>,
1252 Requires<[IsARM, HasV6]> {
1254 let Inst{19-16} = 0b1111;
1255 let Inst{11-10} = rot;
1258 /// AI_exta_rrot - A binary operation with two forms: one whose operand is a
1259 /// register and one whose operand is a register rotated by 8/16/24.
1260 class AI_exta_rrot<bits<8> opcod, string opc, PatFrag opnode>
1261 : AExtI<opcod, (outs GPRnopc:$Rd), (ins GPR:$Rn, GPRnopc:$Rm, rot_imm:$rot),
1262 IIC_iEXTAr, opc, "\t$Rd, $Rn, $Rm$rot",
1263 [(set GPRnopc:$Rd, (opnode GPR:$Rn,
1264 (rotr GPRnopc:$Rm, rot_imm:$rot)))]>,
1265 Requires<[IsARM, HasV6]> {
1270 let Inst{19-16} = Rn;
1271 let Inst{15-12} = Rd;
1272 let Inst{11-10} = rot;
1273 let Inst{9-4} = 0b000111;
1277 class AI_exta_rrot_np<bits<8> opcod, string opc>
1278 : AExtI<opcod, (outs GPRnopc:$Rd), (ins GPR:$Rn, GPRnopc:$Rm, rot_imm:$rot),
1279 IIC_iEXTAr, opc, "\t$Rd, $Rn, $Rm$rot", []>,
1280 Requires<[IsARM, HasV6]> {
1283 let Inst{19-16} = Rn;
1284 let Inst{11-10} = rot;
1287 /// AI1_adde_sube_irs - Define instructions and patterns for adde and sube.
1288 multiclass AI1_adde_sube_irs<bits<4> opcod, string opc, PatFrag opnode,
1289 string baseOpc, bit Commutable = 0> {
1290 let hasPostISelHook = 1, Defs = [CPSR], Uses = [CPSR] in {
1291 def ri : AsI1<opcod, (outs GPR:$Rd), (ins GPR:$Rn, so_imm:$imm),
1292 DPFrm, IIC_iALUi, opc, "\t$Rd, $Rn, $imm",
1293 [(set GPR:$Rd, CPSR, (opnode GPR:$Rn, so_imm:$imm, CPSR))]>,
1299 let Inst{15-12} = Rd;
1300 let Inst{19-16} = Rn;
1301 let Inst{11-0} = imm;
1303 def rr : AsI1<opcod, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm),
1304 DPFrm, IIC_iALUr, opc, "\t$Rd, $Rn, $Rm",
1305 [(set GPR:$Rd, CPSR, (opnode GPR:$Rn, GPR:$Rm, CPSR))]>,
1310 let Inst{11-4} = 0b00000000;
1312 let isCommutable = Commutable;
1314 let Inst{15-12} = Rd;
1315 let Inst{19-16} = Rn;
1317 def rsi : AsI1<opcod, (outs GPR:$Rd),
1318 (ins GPR:$Rn, so_reg_imm:$shift),
1319 DPSoRegImmFrm, IIC_iALUsr, opc, "\t$Rd, $Rn, $shift",
1320 [(set GPR:$Rd, CPSR, (opnode GPR:$Rn, so_reg_imm:$shift, CPSR))]>,
1326 let Inst{19-16} = Rn;
1327 let Inst{15-12} = Rd;
1328 let Inst{11-5} = shift{11-5};
1330 let Inst{3-0} = shift{3-0};
1332 def rsr : AsI1<opcod, (outs GPR:$Rd),
1333 (ins GPR:$Rn, so_reg_reg:$shift),
1334 DPSoRegRegFrm, IIC_iALUsr, opc, "\t$Rd, $Rn, $shift",
1335 [(set GPR:$Rd, CPSR, (opnode GPR:$Rn, so_reg_reg:$shift, CPSR))]>,
1341 let Inst{19-16} = Rn;
1342 let Inst{15-12} = Rd;
1343 let Inst{11-8} = shift{11-8};
1345 let Inst{6-5} = shift{6-5};
1347 let Inst{3-0} = shift{3-0};
1351 // Assembly aliases for optional destination operand when it's the same
1352 // as the source operand.
1353 def : InstAlias<!strconcat(opc, "${s}${p} $Rdn, $imm"),
1354 (!cast<Instruction>(!strconcat(baseOpc, "ri")) GPR:$Rdn, GPR:$Rdn,
1355 so_imm:$imm, pred:$p,
1358 def : InstAlias<!strconcat(opc, "${s}${p} $Rdn, $Rm"),
1359 (!cast<Instruction>(!strconcat(baseOpc, "rr")) GPR:$Rdn, GPR:$Rdn,
1363 def : InstAlias<!strconcat(opc, "${s}${p} $Rdn, $shift"),
1364 (!cast<Instruction>(!strconcat(baseOpc, "rsi")) GPR:$Rdn, GPR:$Rdn,
1365 so_reg_imm:$shift, pred:$p,
1368 def : InstAlias<!strconcat(opc, "${s}${p} $Rdn, $shift"),
1369 (!cast<Instruction>(!strconcat(baseOpc, "rsr")) GPR:$Rdn, GPR:$Rdn,
1370 so_reg_reg:$shift, pred:$p,
1375 /// AI1_rsc_irs - Define instructions and patterns for rsc
1376 multiclass AI1_rsc_irs<bits<4> opcod, string opc, PatFrag opnode,
1378 let hasPostISelHook = 1, Defs = [CPSR], Uses = [CPSR] in {
1379 def ri : AsI1<opcod, (outs GPR:$Rd), (ins GPR:$Rn, so_imm:$imm),
1380 DPFrm, IIC_iALUi, opc, "\t$Rd, $Rn, $imm",
1381 [(set GPR:$Rd, CPSR, (opnode so_imm:$imm, GPR:$Rn, CPSR))]>,
1387 let Inst{15-12} = Rd;
1388 let Inst{19-16} = Rn;
1389 let Inst{11-0} = imm;
1391 def rr : AsI1<opcod, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm),
1392 DPFrm, IIC_iALUr, opc, "\t$Rd, $Rn, $Rm",
1393 [/* pattern left blank */]> {
1397 let Inst{11-4} = 0b00000000;
1400 let Inst{15-12} = Rd;
1401 let Inst{19-16} = Rn;
1403 def rsi : AsI1<opcod, (outs GPR:$Rd), (ins GPR:$Rn, so_reg_imm:$shift),
1404 DPSoRegImmFrm, IIC_iALUsr, opc, "\t$Rd, $Rn, $shift",
1405 [(set GPR:$Rd, CPSR, (opnode so_reg_imm:$shift, GPR:$Rn, CPSR))]>,
1411 let Inst{19-16} = Rn;
1412 let Inst{15-12} = Rd;
1413 let Inst{11-5} = shift{11-5};
1415 let Inst{3-0} = shift{3-0};
1417 def rsr : AsI1<opcod, (outs GPR:$Rd), (ins GPR:$Rn, so_reg_reg:$shift),
1418 DPSoRegRegFrm, IIC_iALUsr, opc, "\t$Rd, $Rn, $shift",
1419 [(set GPR:$Rd, CPSR, (opnode so_reg_reg:$shift, GPR:$Rn, CPSR))]>,
1425 let Inst{19-16} = Rn;
1426 let Inst{15-12} = Rd;
1427 let Inst{11-8} = shift{11-8};
1429 let Inst{6-5} = shift{6-5};
1431 let Inst{3-0} = shift{3-0};
1435 // Assembly aliases for optional destination operand when it's the same
1436 // as the source operand.
1437 def : InstAlias<!strconcat(opc, "${s}${p} $Rdn, $imm"),
1438 (!cast<Instruction>(!strconcat(baseOpc, "ri")) GPR:$Rdn, GPR:$Rdn,
1439 so_imm:$imm, pred:$p,
1442 def : InstAlias<!strconcat(opc, "${s}${p} $Rdn, $Rm"),
1443 (!cast<Instruction>(!strconcat(baseOpc, "rr")) GPR:$Rdn, GPR:$Rdn,
1447 def : InstAlias<!strconcat(opc, "${s}${p} $Rdn, $shift"),
1448 (!cast<Instruction>(!strconcat(baseOpc, "rsi")) GPR:$Rdn, GPR:$Rdn,
1449 so_reg_imm:$shift, pred:$p,
1452 def : InstAlias<!strconcat(opc, "${s}${p} $Rdn, $shift"),
1453 (!cast<Instruction>(!strconcat(baseOpc, "rsr")) GPR:$Rdn, GPR:$Rdn,
1454 so_reg_reg:$shift, pred:$p,
1459 let canFoldAsLoad = 1, isReMaterializable = 1 in {
1460 multiclass AI_ldr1<bit isByte, string opc, InstrItinClass iii,
1461 InstrItinClass iir, PatFrag opnode> {
1462 // Note: We use the complex addrmode_imm12 rather than just an input
1463 // GPR and a constrained immediate so that we can use this to match
1464 // frame index references and avoid matching constant pool references.
1465 def i12: AI2ldst<0b010, 1, isByte, (outs GPR:$Rt), (ins addrmode_imm12:$addr),
1466 AddrMode_i12, LdFrm, iii, opc, "\t$Rt, $addr",
1467 [(set GPR:$Rt, (opnode addrmode_imm12:$addr))]> {
1470 let Inst{23} = addr{12}; // U (add = ('U' == 1))
1471 let Inst{19-16} = addr{16-13}; // Rn
1472 let Inst{15-12} = Rt;
1473 let Inst{11-0} = addr{11-0}; // imm12
1475 def rs : AI2ldst<0b011, 1, isByte, (outs GPR:$Rt), (ins ldst_so_reg:$shift),
1476 AddrModeNone, LdFrm, iir, opc, "\t$Rt, $shift",
1477 [(set GPR:$Rt, (opnode ldst_so_reg:$shift))]> {
1480 let shift{4} = 0; // Inst{4} = 0
1481 let Inst{23} = shift{12}; // U (add = ('U' == 1))
1482 let Inst{19-16} = shift{16-13}; // Rn
1483 let Inst{15-12} = Rt;
1484 let Inst{11-0} = shift{11-0};
1489 let canFoldAsLoad = 1, isReMaterializable = 1 in {
1490 multiclass AI_ldr1nopc<bit isByte, string opc, InstrItinClass iii,
1491 InstrItinClass iir, PatFrag opnode> {
1492 // Note: We use the complex addrmode_imm12 rather than just an input
1493 // GPR and a constrained immediate so that we can use this to match
1494 // frame index references and avoid matching constant pool references.
1495 def i12: AI2ldst<0b010, 1, isByte, (outs GPRnopc:$Rt), (ins addrmode_imm12:$addr),
1496 AddrMode_i12, LdFrm, iii, opc, "\t$Rt, $addr",
1497 [(set GPRnopc:$Rt, (opnode addrmode_imm12:$addr))]> {
1500 let Inst{23} = addr{12}; // U (add = ('U' == 1))
1501 let Inst{19-16} = addr{16-13}; // Rn
1502 let Inst{15-12} = Rt;
1503 let Inst{11-0} = addr{11-0}; // imm12
1505 def rs : AI2ldst<0b011, 1, isByte, (outs GPRnopc:$Rt), (ins ldst_so_reg:$shift),
1506 AddrModeNone, LdFrm, iir, opc, "\t$Rt, $shift",
1507 [(set GPRnopc:$Rt, (opnode ldst_so_reg:$shift))]> {
1510 let shift{4} = 0; // Inst{4} = 0
1511 let Inst{23} = shift{12}; // U (add = ('U' == 1))
1512 let Inst{19-16} = shift{16-13}; // Rn
1513 let Inst{15-12} = Rt;
1514 let Inst{11-0} = shift{11-0};
1520 multiclass AI_str1<bit isByte, string opc, InstrItinClass iii,
1521 InstrItinClass iir, PatFrag opnode> {
1522 // Note: We use the complex addrmode_imm12 rather than just an input
1523 // GPR and a constrained immediate so that we can use this to match
1524 // frame index references and avoid matching constant pool references.
1525 def i12 : AI2ldst<0b010, 0, isByte, (outs),
1526 (ins GPR:$Rt, addrmode_imm12:$addr),
1527 AddrMode_i12, StFrm, iii, opc, "\t$Rt, $addr",
1528 [(opnode GPR:$Rt, addrmode_imm12:$addr)]> {
1531 let Inst{23} = addr{12}; // U (add = ('U' == 1))
1532 let Inst{19-16} = addr{16-13}; // Rn
1533 let Inst{15-12} = Rt;
1534 let Inst{11-0} = addr{11-0}; // imm12
1536 def rs : AI2ldst<0b011, 0, isByte, (outs), (ins GPR:$Rt, ldst_so_reg:$shift),
1537 AddrModeNone, StFrm, iir, opc, "\t$Rt, $shift",
1538 [(opnode GPR:$Rt, ldst_so_reg:$shift)]> {
1541 let shift{4} = 0; // Inst{4} = 0
1542 let Inst{23} = shift{12}; // U (add = ('U' == 1))
1543 let Inst{19-16} = shift{16-13}; // Rn
1544 let Inst{15-12} = Rt;
1545 let Inst{11-0} = shift{11-0};
1549 multiclass AI_str1nopc<bit isByte, string opc, InstrItinClass iii,
1550 InstrItinClass iir, PatFrag opnode> {
1551 // Note: We use the complex addrmode_imm12 rather than just an input
1552 // GPR and a constrained immediate so that we can use this to match
1553 // frame index references and avoid matching constant pool references.
1554 def i12 : AI2ldst<0b010, 0, isByte, (outs),
1555 (ins GPRnopc:$Rt, addrmode_imm12:$addr),
1556 AddrMode_i12, StFrm, iii, opc, "\t$Rt, $addr",
1557 [(opnode GPRnopc:$Rt, addrmode_imm12:$addr)]> {
1560 let Inst{23} = addr{12}; // U (add = ('U' == 1))
1561 let Inst{19-16} = addr{16-13}; // Rn
1562 let Inst{15-12} = Rt;
1563 let Inst{11-0} = addr{11-0}; // imm12
1565 def rs : AI2ldst<0b011, 0, isByte, (outs), (ins GPRnopc:$Rt, ldst_so_reg:$shift),
1566 AddrModeNone, StFrm, iir, opc, "\t$Rt, $shift",
1567 [(opnode GPRnopc:$Rt, ldst_so_reg:$shift)]> {
1570 let shift{4} = 0; // Inst{4} = 0
1571 let Inst{23} = shift{12}; // U (add = ('U' == 1))
1572 let Inst{19-16} = shift{16-13}; // Rn
1573 let Inst{15-12} = Rt;
1574 let Inst{11-0} = shift{11-0};
1579 //===----------------------------------------------------------------------===//
1581 //===----------------------------------------------------------------------===//
1583 //===----------------------------------------------------------------------===//
1584 // Miscellaneous Instructions.
1587 /// CONSTPOOL_ENTRY - This instruction represents a floating constant pool in
1588 /// the function. The first operand is the ID# for this instruction, the second
1589 /// is the index into the MachineConstantPool that this is, the third is the
1590 /// size in bytes of this constant pool entry.
1591 let neverHasSideEffects = 1, isNotDuplicable = 1 in
1592 def CONSTPOOL_ENTRY :
1593 PseudoInst<(outs), (ins cpinst_operand:$instid, cpinst_operand:$cpidx,
1594 i32imm:$size), NoItinerary, []>;
1596 // FIXME: Marking these as hasSideEffects is necessary to prevent machine DCE
1597 // from removing one half of the matched pairs. That breaks PEI, which assumes
1598 // these will always be in pairs, and asserts if it finds otherwise. Better way?
1599 let Defs = [SP], Uses = [SP], hasSideEffects = 1 in {
1600 def ADJCALLSTACKUP :
1601 PseudoInst<(outs), (ins i32imm:$amt1, i32imm:$amt2, pred:$p), NoItinerary,
1602 [(ARMcallseq_end timm:$amt1, timm:$amt2)]>;
1604 def ADJCALLSTACKDOWN :
1605 PseudoInst<(outs), (ins i32imm:$amt, pred:$p), NoItinerary,
1606 [(ARMcallseq_start timm:$amt)]>;
1609 // Atomic pseudo-insts which will be lowered to ldrexd/strexd loops.
1610 // (These pseudos use a hand-written selection code).
1611 let usesCustomInserter = 1, Defs = [CPSR], mayLoad = 1, mayStore = 1 in {
1612 def ATOMOR6432 : PseudoInst<(outs GPR:$dst1, GPR:$dst2),
1613 (ins GPR:$addr, GPR:$src1, GPR:$src2),
1615 def ATOMXOR6432 : PseudoInst<(outs GPR:$dst1, GPR:$dst2),
1616 (ins GPR:$addr, GPR:$src1, GPR:$src2),
1618 def ATOMADD6432 : PseudoInst<(outs GPR:$dst1, GPR:$dst2),
1619 (ins GPR:$addr, GPR:$src1, GPR:$src2),
1621 def ATOMSUB6432 : PseudoInst<(outs GPR:$dst1, GPR:$dst2),
1622 (ins GPR:$addr, GPR:$src1, GPR:$src2),
1624 def ATOMNAND6432 : PseudoInst<(outs GPR:$dst1, GPR:$dst2),
1625 (ins GPR:$addr, GPR:$src1, GPR:$src2),
1627 def ATOMAND6432 : PseudoInst<(outs GPR:$dst1, GPR:$dst2),
1628 (ins GPR:$addr, GPR:$src1, GPR:$src2),
1630 def ATOMSWAP6432 : PseudoInst<(outs GPR:$dst1, GPR:$dst2),
1631 (ins GPR:$addr, GPR:$src1, GPR:$src2),
1633 def ATOMCMPXCHG6432 : PseudoInst<(outs GPR:$dst1, GPR:$dst2),
1634 (ins GPR:$addr, GPR:$cmp1, GPR:$cmp2,
1635 GPR:$set1, GPR:$set2),
1639 def NOP : AI<(outs), (ins), MiscFrm, NoItinerary, "nop", "", []>,
1640 Requires<[IsARM, HasV6T2]> {
1641 let Inst{27-16} = 0b001100100000;
1642 let Inst{15-8} = 0b11110000;
1643 let Inst{7-0} = 0b00000000;
1646 def YIELD : AI<(outs), (ins), MiscFrm, NoItinerary, "yield", "", []>,
1647 Requires<[IsARM, HasV6T2]> {
1648 let Inst{27-16} = 0b001100100000;
1649 let Inst{15-8} = 0b11110000;
1650 let Inst{7-0} = 0b00000001;
1653 def WFE : AI<(outs), (ins), MiscFrm, NoItinerary, "wfe", "", []>,
1654 Requires<[IsARM, HasV6T2]> {
1655 let Inst{27-16} = 0b001100100000;
1656 let Inst{15-8} = 0b11110000;
1657 let Inst{7-0} = 0b00000010;
1660 def WFI : AI<(outs), (ins), MiscFrm, NoItinerary, "wfi", "", []>,
1661 Requires<[IsARM, HasV6T2]> {
1662 let Inst{27-16} = 0b001100100000;
1663 let Inst{15-8} = 0b11110000;
1664 let Inst{7-0} = 0b00000011;
1667 def SEL : AI<(outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm), DPFrm, NoItinerary, "sel",
1668 "\t$Rd, $Rn, $Rm", []>, Requires<[IsARM, HasV6]> {
1673 let Inst{15-12} = Rd;
1674 let Inst{19-16} = Rn;
1675 let Inst{27-20} = 0b01101000;
1676 let Inst{7-4} = 0b1011;
1677 let Inst{11-8} = 0b1111;
1680 def SEV : AI<(outs), (ins), MiscFrm, NoItinerary, "sev", "",
1681 []>, Requires<[IsARM, HasV6T2]> {
1682 let Inst{27-16} = 0b001100100000;
1683 let Inst{15-8} = 0b11110000;
1684 let Inst{7-0} = 0b00000100;
1687 // The i32imm operand $val can be used by a debugger to store more information
1688 // about the breakpoint.
1689 def BKPT : AI<(outs), (ins imm0_65535:$val), MiscFrm, NoItinerary,
1690 "bkpt", "\t$val", []>, Requires<[IsARM]> {
1692 let Inst{3-0} = val{3-0};
1693 let Inst{19-8} = val{15-4};
1694 let Inst{27-20} = 0b00010010;
1695 let Inst{7-4} = 0b0111;
1698 // Change Processor State
1699 // FIXME: We should use InstAlias to handle the optional operands.
1700 class CPS<dag iops, string asm_ops>
1701 : AXI<(outs), iops, MiscFrm, NoItinerary, !strconcat("cps", asm_ops),
1702 []>, Requires<[IsARM]> {
1708 let Inst{31-28} = 0b1111;
1709 let Inst{27-20} = 0b00010000;
1710 let Inst{19-18} = imod;
1711 let Inst{17} = M; // Enabled if mode is set;
1712 let Inst{16-9} = 0b00000000;
1713 let Inst{8-6} = iflags;
1715 let Inst{4-0} = mode;
1718 let DecoderMethod = "DecodeCPSInstruction" in {
1720 def CPS3p : CPS<(ins imod_op:$imod, iflags_op:$iflags, imm0_31:$mode),
1721 "$imod\t$iflags, $mode">;
1722 let mode = 0, M = 0 in
1723 def CPS2p : CPS<(ins imod_op:$imod, iflags_op:$iflags), "$imod\t$iflags">;
1725 let imod = 0, iflags = 0, M = 1 in
1726 def CPS1p : CPS<(ins imm0_31:$mode), "\t$mode">;
1729 // Preload signals the memory system of possible future data/instruction access.
1730 multiclass APreLoad<bits<1> read, bits<1> data, string opc> {
1732 def i12 : AXI<(outs), (ins addrmode_imm12:$addr), MiscFrm, IIC_Preload,
1733 !strconcat(opc, "\t$addr"),
1734 [(ARMPreload addrmode_imm12:$addr, (i32 read), (i32 data))]> {
1737 let Inst{31-26} = 0b111101;
1738 let Inst{25} = 0; // 0 for immediate form
1739 let Inst{24} = data;
1740 let Inst{23} = addr{12}; // U (add = ('U' == 1))
1741 let Inst{22} = read;
1742 let Inst{21-20} = 0b01;
1743 let Inst{19-16} = addr{16-13}; // Rn
1744 let Inst{15-12} = 0b1111;
1745 let Inst{11-0} = addr{11-0}; // imm12
1748 def rs : AXI<(outs), (ins ldst_so_reg:$shift), MiscFrm, IIC_Preload,
1749 !strconcat(opc, "\t$shift"),
1750 [(ARMPreload ldst_so_reg:$shift, (i32 read), (i32 data))]> {
1752 let Inst{31-26} = 0b111101;
1753 let Inst{25} = 1; // 1 for register form
1754 let Inst{24} = data;
1755 let Inst{23} = shift{12}; // U (add = ('U' == 1))
1756 let Inst{22} = read;
1757 let Inst{21-20} = 0b01;
1758 let Inst{19-16} = shift{16-13}; // Rn
1759 let Inst{15-12} = 0b1111;
1760 let Inst{11-0} = shift{11-0};
1765 defm PLD : APreLoad<1, 1, "pld">, Requires<[IsARM]>;
1766 defm PLDW : APreLoad<0, 1, "pldw">, Requires<[IsARM,HasV7,HasMP]>;
1767 defm PLI : APreLoad<1, 0, "pli">, Requires<[IsARM,HasV7]>;
1769 def SETEND : AXI<(outs), (ins setend_op:$end), MiscFrm, NoItinerary,
1770 "setend\t$end", []>, Requires<[IsARM]> {
1772 let Inst{31-10} = 0b1111000100000001000000;
1777 def DBG : AI<(outs), (ins imm0_15:$opt), MiscFrm, NoItinerary, "dbg", "\t$opt",
1778 []>, Requires<[IsARM, HasV7]> {
1780 let Inst{27-4} = 0b001100100000111100001111;
1781 let Inst{3-0} = opt;
1784 // A5.4 Permanently UNDEFINED instructions.
1785 let isBarrier = 1, isTerminator = 1 in
1786 def TRAP : AXI<(outs), (ins), MiscFrm, NoItinerary,
1789 let Inst = 0xe7ffdefe;
1792 // Address computation and loads and stores in PIC mode.
1793 let isNotDuplicable = 1 in {
1794 def PICADD : ARMPseudoInst<(outs GPR:$dst), (ins GPR:$a, pclabel:$cp, pred:$p),
1796 [(set GPR:$dst, (ARMpic_add GPR:$a, imm:$cp))]>;
1798 let AddedComplexity = 10 in {
1799 def PICLDR : ARMPseudoInst<(outs GPR:$dst), (ins addrmodepc:$addr, pred:$p),
1801 [(set GPR:$dst, (load addrmodepc:$addr))]>;
1803 def PICLDRH : ARMPseudoInst<(outs GPR:$Rt), (ins addrmodepc:$addr, pred:$p),
1805 [(set GPR:$Rt, (zextloadi16 addrmodepc:$addr))]>;
1807 def PICLDRB : ARMPseudoInst<(outs GPR:$Rt), (ins addrmodepc:$addr, pred:$p),
1809 [(set GPR:$Rt, (zextloadi8 addrmodepc:$addr))]>;
1811 def PICLDRSH : ARMPseudoInst<(outs GPR:$Rt), (ins addrmodepc:$addr, pred:$p),
1813 [(set GPR:$Rt, (sextloadi16 addrmodepc:$addr))]>;
1815 def PICLDRSB : ARMPseudoInst<(outs GPR:$Rt), (ins addrmodepc:$addr, pred:$p),
1817 [(set GPR:$Rt, (sextloadi8 addrmodepc:$addr))]>;
1819 let AddedComplexity = 10 in {
1820 def PICSTR : ARMPseudoInst<(outs), (ins GPR:$src, addrmodepc:$addr, pred:$p),
1821 4, IIC_iStore_r, [(store GPR:$src, addrmodepc:$addr)]>;
1823 def PICSTRH : ARMPseudoInst<(outs), (ins GPR:$src, addrmodepc:$addr, pred:$p),
1824 4, IIC_iStore_bh_r, [(truncstorei16 GPR:$src,
1825 addrmodepc:$addr)]>;
1827 def PICSTRB : ARMPseudoInst<(outs), (ins GPR:$src, addrmodepc:$addr, pred:$p),
1828 4, IIC_iStore_bh_r, [(truncstorei8 GPR:$src, addrmodepc:$addr)]>;
1830 } // isNotDuplicable = 1
1833 // LEApcrel - Load a pc-relative address into a register without offending the
1835 let neverHasSideEffects = 1, isReMaterializable = 1 in
1836 // The 'adr' mnemonic encodes differently if the label is before or after
1837 // the instruction. The {24-21} opcode bits are set by the fixup, as we don't
1838 // know until then which form of the instruction will be used.
1839 def ADR : AI1<{0,?,?,0}, (outs GPR:$Rd), (ins adrlabel:$label),
1840 MiscFrm, IIC_iALUi, "adr", "\t$Rd, $label", []> {
1843 let Inst{27-25} = 0b001;
1845 let Inst{23-22} = label{13-12};
1848 let Inst{19-16} = 0b1111;
1849 let Inst{15-12} = Rd;
1850 let Inst{11-0} = label{11-0};
1852 def LEApcrel : ARMPseudoInst<(outs GPR:$Rd), (ins i32imm:$label, pred:$p),
1855 def LEApcrelJT : ARMPseudoInst<(outs GPR:$Rd),
1856 (ins i32imm:$label, nohash_imm:$id, pred:$p),
1859 //===----------------------------------------------------------------------===//
1860 // Control Flow Instructions.
1863 let isReturn = 1, isTerminator = 1, isBarrier = 1 in {
1865 def BX_RET : AI<(outs), (ins), BrMiscFrm, IIC_Br,
1866 "bx", "\tlr", [(ARMretflag)]>,
1867 Requires<[IsARM, HasV4T]> {
1868 let Inst{27-0} = 0b0001001011111111111100011110;
1872 def MOVPCLR : AI<(outs), (ins), BrMiscFrm, IIC_Br,
1873 "mov", "\tpc, lr", [(ARMretflag)]>,
1874 Requires<[IsARM, NoV4T]> {
1875 let Inst{27-0} = 0b0001101000001111000000001110;
1879 // Indirect branches
1880 let isBranch = 1, isTerminator = 1, isBarrier = 1, isIndirectBranch = 1 in {
1882 def BX : AXI<(outs), (ins GPR:$dst), BrMiscFrm, IIC_Br, "bx\t$dst",
1883 [(brind GPR:$dst)]>,
1884 Requires<[IsARM, HasV4T]> {
1886 let Inst{31-4} = 0b1110000100101111111111110001;
1887 let Inst{3-0} = dst;
1890 def BX_pred : AI<(outs), (ins GPR:$dst), BrMiscFrm, IIC_Br,
1891 "bx", "\t$dst", [/* pattern left blank */]>,
1892 Requires<[IsARM, HasV4T]> {
1894 let Inst{27-4} = 0b000100101111111111110001;
1895 let Inst{3-0} = dst;
1899 // SP is marked as a use to prevent stack-pointer assignments that appear
1900 // immediately before calls from potentially appearing dead.
1902 // FIXME: Do we really need a non-predicated version? If so, it should
1903 // at least be a pseudo instruction expanding to the predicated version
1904 // at MC lowering time.
1905 Defs = [LR], Uses = [SP] in {
1906 def BL : ABXI<0b1011, (outs), (ins bl_target:$func, variable_ops),
1907 IIC_Br, "bl\t$func",
1908 [(ARMcall tglobaladdr:$func)]>,
1909 Requires<[IsARM, IsNotIOS]> {
1910 let Inst{31-28} = 0b1110;
1912 let Inst{23-0} = func;
1913 let DecoderMethod = "DecodeBranchImmInstruction";
1916 def BL_pred : ABI<0b1011, (outs), (ins bl_target:$func, variable_ops),
1917 IIC_Br, "bl", "\t$func",
1918 [(ARMcall_pred tglobaladdr:$func)]>,
1919 Requires<[IsARM, IsNotIOS]> {
1921 let Inst{23-0} = func;
1922 let DecoderMethod = "DecodeBranchImmInstruction";
1926 def BLX : AXI<(outs), (ins GPR:$func, variable_ops), BrMiscFrm,
1927 IIC_Br, "blx\t$func",
1928 [(ARMcall GPR:$func)]>,
1929 Requires<[IsARM, HasV5T, IsNotIOS]> {
1931 let Inst{31-4} = 0b1110000100101111111111110011;
1932 let Inst{3-0} = func;
1935 def BLX_pred : AI<(outs), (ins GPR:$func, variable_ops), BrMiscFrm,
1936 IIC_Br, "blx", "\t$func",
1937 [(ARMcall_pred GPR:$func)]>,
1938 Requires<[IsARM, HasV5T, IsNotIOS]> {
1940 let Inst{27-4} = 0b000100101111111111110011;
1941 let Inst{3-0} = func;
1945 // Note: Restrict $func to the tGPR regclass to prevent it being in LR.
1946 def BX_CALL : ARMPseudoInst<(outs), (ins tGPR:$func, variable_ops),
1947 8, IIC_Br, [(ARMcall_nolink tGPR:$func)]>,
1948 Requires<[IsARM, HasV4T, IsNotIOS]>;
1951 def BMOVPCRX_CALL : ARMPseudoInst<(outs), (ins tGPR:$func, variable_ops),
1952 8, IIC_Br, [(ARMcall_nolink tGPR:$func)]>,
1953 Requires<[IsARM, NoV4T, IsNotIOS]>;
1955 // mov lr, pc; b if callee is marked noreturn to avoid confusing the
1956 // return stack predictor.
1957 def BMOVPCB_CALL : ARMPseudoInst<(outs),
1958 (ins bl_target:$func, variable_ops),
1959 8, IIC_Br, [(ARMcall_nolink tglobaladdr:$func)]>,
1960 Requires<[IsARM, IsNotIOS]>;
1964 // On IOS R9 is call-clobbered.
1965 // R7 is marked as a use to prevent frame-pointer assignments from being
1966 // moved above / below calls.
1967 Defs = [LR], Uses = [R7, SP] in {
1968 def BLr9 : ARMPseudoExpand<(outs), (ins bl_target:$func, variable_ops),
1970 [(ARMcall tglobaladdr:$func)], (BL bl_target:$func)>,
1971 Requires<[IsARM, IsIOS]>;
1973 def BLr9_pred : ARMPseudoExpand<(outs),
1974 (ins bl_target:$func, pred:$p, variable_ops),
1976 [(ARMcall_pred tglobaladdr:$func)],
1977 (BL_pred bl_target:$func, pred:$p)>,
1978 Requires<[IsARM, IsIOS]>;
1981 def BLXr9 : ARMPseudoExpand<(outs), (ins GPR:$func, variable_ops),
1983 [(ARMcall GPR:$func)],
1985 Requires<[IsARM, HasV5T, IsIOS]>;
1987 def BLXr9_pred: ARMPseudoExpand<(outs), (ins GPR:$func, pred:$p,variable_ops),
1989 [(ARMcall_pred GPR:$func)],
1990 (BLX_pred GPR:$func, pred:$p)>,
1991 Requires<[IsARM, HasV5T, IsIOS]>;
1994 // Note: Restrict $func to the tGPR regclass to prevent it being in LR.
1995 def BXr9_CALL : ARMPseudoInst<(outs), (ins tGPR:$func, variable_ops),
1996 8, IIC_Br, [(ARMcall_nolink tGPR:$func)]>,
1997 Requires<[IsARM, HasV4T, IsIOS]>;
2000 def BMOVPCRXr9_CALL : ARMPseudoInst<(outs), (ins tGPR:$func, variable_ops),
2001 8, IIC_Br, [(ARMcall_nolink tGPR:$func)]>,
2002 Requires<[IsARM, NoV4T, IsIOS]>;
2004 // mov lr, pc; b if callee is marked noreturn to avoid confusing the
2005 // return stack predictor.
2006 def BMOVPCBr9_CALL : ARMPseudoInst<(outs),(ins bl_target:$func, variable_ops),
2007 8, IIC_Br, [(ARMcall_nolink tglobaladdr:$func)]>,
2008 Requires<[IsARM, IsIOS]>;
2011 let isBranch = 1, isTerminator = 1 in {
2012 // FIXME: should be able to write a pattern for ARMBrcond, but can't use
2013 // a two-value operand where a dag node expects two operands. :(
2014 def Bcc : ABI<0b1010, (outs), (ins br_target:$target),
2015 IIC_Br, "b", "\t$target",
2016 [/*(ARMbrcond bb:$target, imm:$cc, CCR:$ccr)*/]> {
2018 let Inst{23-0} = target;
2019 let DecoderMethod = "DecodeBranchImmInstruction";
2022 let isBarrier = 1 in {
2023 // B is "predicable" since it's just a Bcc with an 'always' condition.
2024 let isPredicable = 1 in
2025 // FIXME: We shouldn't need this pseudo at all. Just using Bcc directly
2026 // should be sufficient.
2027 // FIXME: Is B really a Barrier? That doesn't seem right.
2028 def B : ARMPseudoExpand<(outs), (ins br_target:$target), 4, IIC_Br,
2029 [(br bb:$target)], (Bcc br_target:$target, (ops 14, zero_reg))>;
2031 let isNotDuplicable = 1, isIndirectBranch = 1 in {
2032 def BR_JTr : ARMPseudoInst<(outs),
2033 (ins GPR:$target, i32imm:$jt, i32imm:$id),
2035 [(ARMbrjt GPR:$target, tjumptable:$jt, imm:$id)]>;
2036 // FIXME: This shouldn't use the generic "addrmode2," but rather be split
2037 // into i12 and rs suffixed versions.
2038 def BR_JTm : ARMPseudoInst<(outs),
2039 (ins addrmode2:$target, i32imm:$jt, i32imm:$id),
2041 [(ARMbrjt (i32 (load addrmode2:$target)), tjumptable:$jt,
2043 def BR_JTadd : ARMPseudoInst<(outs),
2044 (ins GPR:$target, GPR:$idx, i32imm:$jt, i32imm:$id),
2046 [(ARMbrjt (add GPR:$target, GPR:$idx), tjumptable:$jt,
2048 } // isNotDuplicable = 1, isIndirectBranch = 1
2054 def BLXi : AXI<(outs), (ins blx_target:$target), BrMiscFrm, NoItinerary,
2055 "blx\t$target", []>,
2056 Requires<[IsARM, HasV5T]> {
2057 let Inst{31-25} = 0b1111101;
2059 let Inst{23-0} = target{24-1};
2060 let Inst{24} = target{0};
2063 // Branch and Exchange Jazelle
2064 def BXJ : ABI<0b0001, (outs), (ins GPR:$func), NoItinerary, "bxj", "\t$func",
2065 [/* pattern left blank */]> {
2067 let Inst{23-20} = 0b0010;
2068 let Inst{19-8} = 0xfff;
2069 let Inst{7-4} = 0b0010;
2070 let Inst{3-0} = func;
2075 let isCall = 1, isTerminator = 1, isReturn = 1, isBarrier = 1 in {
2077 let Uses = [SP] in {
2078 def TCRETURNdi : PseudoInst<(outs), (ins i32imm:$dst, variable_ops),
2079 IIC_Br, []>, Requires<[IsIOS]>;
2081 def TCRETURNri : PseudoInst<(outs), (ins tcGPR:$dst, variable_ops),
2082 IIC_Br, []>, Requires<[IsIOS]>;
2084 def TAILJMPd : ARMPseudoExpand<(outs), (ins br_target:$dst, variable_ops),
2086 (Bcc br_target:$dst, (ops 14, zero_reg))>,
2087 Requires<[IsARM, IsIOS]>;
2089 def TAILJMPr : ARMPseudoExpand<(outs), (ins tcGPR:$dst, variable_ops),
2092 Requires<[IsARM, IsIOS]>;
2096 // Non-IOS versions (the difference is R9).
2097 let Uses = [SP] in {
2098 def TCRETURNdiND : PseudoInst<(outs), (ins i32imm:$dst, variable_ops),
2099 IIC_Br, []>, Requires<[IsNotIOS]>;
2101 def TCRETURNriND : PseudoInst<(outs), (ins tcGPR:$dst, variable_ops),
2102 IIC_Br, []>, Requires<[IsNotIOS]>;
2104 def TAILJMPdND : ARMPseudoExpand<(outs), (ins brtarget:$dst, variable_ops),
2106 (Bcc br_target:$dst, (ops 14, zero_reg))>,
2107 Requires<[IsARM, IsNotIOS]>;
2109 def TAILJMPrND : ARMPseudoExpand<(outs), (ins tcGPR:$dst, variable_ops),
2112 Requires<[IsARM, IsNotIOS]>;
2116 // Secure Monitor Call is a system instruction.
2117 def SMC : ABI<0b0001, (outs), (ins imm0_15:$opt), NoItinerary, "smc", "\t$opt",
2120 let Inst{23-4} = 0b01100000000000000111;
2121 let Inst{3-0} = opt;
2124 // Supervisor Call (Software Interrupt)
2125 let isCall = 1, Uses = [SP] in {
2126 def SVC : ABI<0b1111, (outs), (ins imm24b:$svc), IIC_Br, "svc", "\t$svc", []> {
2128 let Inst{23-0} = svc;
2132 // Store Return State
2133 class SRSI<bit wb, string asm>
2134 : XI<(outs), (ins imm0_31:$mode), AddrModeNone, 4, IndexModeNone, BrFrm,
2135 NoItinerary, asm, "", []> {
2137 let Inst{31-28} = 0b1111;
2138 let Inst{27-25} = 0b100;
2142 let Inst{19-16} = 0b1101; // SP
2143 let Inst{15-5} = 0b00000101000;
2144 let Inst{4-0} = mode;
2147 def SRSDA : SRSI<0, "srsda\tsp, $mode"> {
2148 let Inst{24-23} = 0;
2150 def SRSDA_UPD : SRSI<1, "srsda\tsp!, $mode"> {
2151 let Inst{24-23} = 0;
2153 def SRSDB : SRSI<0, "srsdb\tsp, $mode"> {
2154 let Inst{24-23} = 0b10;
2156 def SRSDB_UPD : SRSI<1, "srsdb\tsp!, $mode"> {
2157 let Inst{24-23} = 0b10;
2159 def SRSIA : SRSI<0, "srsia\tsp, $mode"> {
2160 let Inst{24-23} = 0b01;
2162 def SRSIA_UPD : SRSI<1, "srsia\tsp!, $mode"> {
2163 let Inst{24-23} = 0b01;
2165 def SRSIB : SRSI<0, "srsib\tsp, $mode"> {
2166 let Inst{24-23} = 0b11;
2168 def SRSIB_UPD : SRSI<1, "srsib\tsp!, $mode"> {
2169 let Inst{24-23} = 0b11;
2172 // Return From Exception
2173 class RFEI<bit wb, string asm>
2174 : XI<(outs), (ins GPR:$Rn), AddrModeNone, 4, IndexModeNone, BrFrm,
2175 NoItinerary, asm, "", []> {
2177 let Inst{31-28} = 0b1111;
2178 let Inst{27-25} = 0b100;
2182 let Inst{19-16} = Rn;
2183 let Inst{15-0} = 0xa00;
2186 def RFEDA : RFEI<0, "rfeda\t$Rn"> {
2187 let Inst{24-23} = 0;
2189 def RFEDA_UPD : RFEI<1, "rfeda\t$Rn!"> {
2190 let Inst{24-23} = 0;
2192 def RFEDB : RFEI<0, "rfedb\t$Rn"> {
2193 let Inst{24-23} = 0b10;
2195 def RFEDB_UPD : RFEI<1, "rfedb\t$Rn!"> {
2196 let Inst{24-23} = 0b10;
2198 def RFEIA : RFEI<0, "rfeia\t$Rn"> {
2199 let Inst{24-23} = 0b01;
2201 def RFEIA_UPD : RFEI<1, "rfeia\t$Rn!"> {
2202 let Inst{24-23} = 0b01;
2204 def RFEIB : RFEI<0, "rfeib\t$Rn"> {
2205 let Inst{24-23} = 0b11;
2207 def RFEIB_UPD : RFEI<1, "rfeib\t$Rn!"> {
2208 let Inst{24-23} = 0b11;
2211 //===----------------------------------------------------------------------===//
2212 // Load / Store Instructions.
2218 defm LDR : AI_ldr1<0, "ldr", IIC_iLoad_r, IIC_iLoad_si,
2219 UnOpFrag<(load node:$Src)>>;
2220 defm LDRB : AI_ldr1nopc<1, "ldrb", IIC_iLoad_bh_r, IIC_iLoad_bh_si,
2221 UnOpFrag<(zextloadi8 node:$Src)>>;
2222 defm STR : AI_str1<0, "str", IIC_iStore_r, IIC_iStore_si,
2223 BinOpFrag<(store node:$LHS, node:$RHS)>>;
2224 defm STRB : AI_str1nopc<1, "strb", IIC_iStore_bh_r, IIC_iStore_bh_si,
2225 BinOpFrag<(truncstorei8 node:$LHS, node:$RHS)>>;
2227 // Special LDR for loads from non-pc-relative constpools.
2228 let canFoldAsLoad = 1, mayLoad = 1, neverHasSideEffects = 1,
2229 isReMaterializable = 1, isCodeGenOnly = 1 in
2230 def LDRcp : AI2ldst<0b010, 1, 0, (outs GPR:$Rt), (ins addrmode_imm12:$addr),
2231 AddrMode_i12, LdFrm, IIC_iLoad_r, "ldr", "\t$Rt, $addr",
2235 let Inst{23} = addr{12}; // U (add = ('U' == 1))
2236 let Inst{19-16} = 0b1111;
2237 let Inst{15-12} = Rt;
2238 let Inst{11-0} = addr{11-0}; // imm12
2241 // Loads with zero extension
2242 def LDRH : AI3ld<0b1011, 1, (outs GPR:$Rt), (ins addrmode3:$addr), LdMiscFrm,
2243 IIC_iLoad_bh_r, "ldrh", "\t$Rt, $addr",
2244 [(set GPR:$Rt, (zextloadi16 addrmode3:$addr))]>;
2246 // Loads with sign extension
2247 def LDRSH : AI3ld<0b1111, 1, (outs GPR:$Rt), (ins addrmode3:$addr), LdMiscFrm,
2248 IIC_iLoad_bh_r, "ldrsh", "\t$Rt, $addr",
2249 [(set GPR:$Rt, (sextloadi16 addrmode3:$addr))]>;
2251 def LDRSB : AI3ld<0b1101, 1, (outs GPR:$Rt), (ins addrmode3:$addr), LdMiscFrm,
2252 IIC_iLoad_bh_r, "ldrsb", "\t$Rt, $addr",
2253 [(set GPR:$Rt, (sextloadi8 addrmode3:$addr))]>;
2255 let mayLoad = 1, neverHasSideEffects = 1, hasExtraDefRegAllocReq = 1 in {
2257 def LDRD : AI3ld<0b1101, 0, (outs GPR:$Rd, GPR:$dst2),
2258 (ins addrmode3:$addr), LdMiscFrm,
2259 IIC_iLoad_d_r, "ldrd", "\t$Rd, $dst2, $addr",
2260 []>, Requires<[IsARM, HasV5TE]>;
2264 multiclass AI2_ldridx<bit isByte, string opc,
2265 InstrItinClass iii, InstrItinClass iir> {
2266 def _PRE_IMM : AI2ldstidx<1, isByte, 1, (outs GPR:$Rt, GPR:$Rn_wb),
2267 (ins addrmode_imm12:$addr), IndexModePre, LdFrm, iii,
2268 opc, "\t$Rt, $addr!", "$addr.base = $Rn_wb", []> {
2271 let Inst{23} = addr{12};
2272 let Inst{19-16} = addr{16-13};
2273 let Inst{11-0} = addr{11-0};
2274 let DecoderMethod = "DecodeLDRPreImm";
2275 let AsmMatchConverter = "cvtLdWriteBackRegAddrModeImm12";
2278 def _PRE_REG : AI2ldstidx<1, isByte, 1, (outs GPR:$Rt, GPR:$Rn_wb),
2279 (ins ldst_so_reg:$addr), IndexModePre, LdFrm, iir,
2280 opc, "\t$Rt, $addr!", "$addr.base = $Rn_wb", []> {
2283 let Inst{23} = addr{12};
2284 let Inst{19-16} = addr{16-13};
2285 let Inst{11-0} = addr{11-0};
2287 let DecoderMethod = "DecodeLDRPreReg";
2288 let AsmMatchConverter = "cvtLdWriteBackRegAddrMode2";
2291 def _POST_REG : AI2ldstidx<1, isByte, 0, (outs GPR:$Rt, GPR:$Rn_wb),
2292 (ins addr_offset_none:$addr, am2offset_reg:$offset),
2293 IndexModePost, LdFrm, iir,
2294 opc, "\t$Rt, $addr, $offset",
2295 "$addr.base = $Rn_wb", []> {
2301 let Inst{23} = offset{12};
2302 let Inst{19-16} = addr;
2303 let Inst{11-0} = offset{11-0};
2305 let DecoderMethod = "DecodeAddrMode2IdxInstruction";
2308 def _POST_IMM : AI2ldstidx<1, isByte, 0, (outs GPR:$Rt, GPR:$Rn_wb),
2309 (ins addr_offset_none:$addr, am2offset_imm:$offset),
2310 IndexModePost, LdFrm, iii,
2311 opc, "\t$Rt, $addr, $offset",
2312 "$addr.base = $Rn_wb", []> {
2318 let Inst{23} = offset{12};
2319 let Inst{19-16} = addr;
2320 let Inst{11-0} = offset{11-0};
2322 let DecoderMethod = "DecodeAddrMode2IdxInstruction";
2327 let mayLoad = 1, neverHasSideEffects = 1 in {
2328 // FIXME: for LDR_PRE_REG etc. the itineray should be either IIC_iLoad_ru or
2329 // IIC_iLoad_siu depending on whether it the offset register is shifted.
2330 defm LDR : AI2_ldridx<0, "ldr", IIC_iLoad_iu, IIC_iLoad_ru>;
2331 defm LDRB : AI2_ldridx<1, "ldrb", IIC_iLoad_bh_iu, IIC_iLoad_bh_ru>;
2334 multiclass AI3_ldridx<bits<4> op, string opc, InstrItinClass itin> {
2335 def _PRE : AI3ldstidx<op, 1, 1, (outs GPR:$Rt, GPR:$Rn_wb),
2336 (ins addrmode3:$addr), IndexModePre,
2338 opc, "\t$Rt, $addr!", "$addr.base = $Rn_wb", []> {
2340 let Inst{23} = addr{8}; // U bit
2341 let Inst{22} = addr{13}; // 1 == imm8, 0 == Rm
2342 let Inst{19-16} = addr{12-9}; // Rn
2343 let Inst{11-8} = addr{7-4}; // imm7_4/zero
2344 let Inst{3-0} = addr{3-0}; // imm3_0/Rm
2345 let AsmMatchConverter = "cvtLdWriteBackRegAddrMode3";
2346 let DecoderMethod = "DecodeAddrMode3Instruction";
2348 def _POST : AI3ldstidx<op, 1, 0, (outs GPR:$Rt, GPR:$Rn_wb),
2349 (ins addr_offset_none:$addr, am3offset:$offset),
2350 IndexModePost, LdMiscFrm, itin,
2351 opc, "\t$Rt, $addr, $offset", "$addr.base = $Rn_wb",
2355 let Inst{23} = offset{8}; // U bit
2356 let Inst{22} = offset{9}; // 1 == imm8, 0 == Rm
2357 let Inst{19-16} = addr;
2358 let Inst{11-8} = offset{7-4}; // imm7_4/zero
2359 let Inst{3-0} = offset{3-0}; // imm3_0/Rm
2360 let DecoderMethod = "DecodeAddrMode3Instruction";
2364 let mayLoad = 1, neverHasSideEffects = 1 in {
2365 defm LDRH : AI3_ldridx<0b1011, "ldrh", IIC_iLoad_bh_ru>;
2366 defm LDRSH : AI3_ldridx<0b1111, "ldrsh", IIC_iLoad_bh_ru>;
2367 defm LDRSB : AI3_ldridx<0b1101, "ldrsb", IIC_iLoad_bh_ru>;
2368 let hasExtraDefRegAllocReq = 1 in {
2369 def LDRD_PRE : AI3ldstidx<0b1101, 0, 1, (outs GPR:$Rt, GPR:$Rt2, GPR:$Rn_wb),
2370 (ins addrmode3:$addr), IndexModePre,
2371 LdMiscFrm, IIC_iLoad_d_ru,
2372 "ldrd", "\t$Rt, $Rt2, $addr!",
2373 "$addr.base = $Rn_wb", []> {
2375 let Inst{23} = addr{8}; // U bit
2376 let Inst{22} = addr{13}; // 1 == imm8, 0 == Rm
2377 let Inst{19-16} = addr{12-9}; // Rn
2378 let Inst{11-8} = addr{7-4}; // imm7_4/zero
2379 let Inst{3-0} = addr{3-0}; // imm3_0/Rm
2380 let DecoderMethod = "DecodeAddrMode3Instruction";
2381 let AsmMatchConverter = "cvtLdrdPre";
2383 def LDRD_POST: AI3ldstidx<0b1101, 0, 0, (outs GPR:$Rt, GPR:$Rt2, GPR:$Rn_wb),
2384 (ins addr_offset_none:$addr, am3offset:$offset),
2385 IndexModePost, LdMiscFrm, IIC_iLoad_d_ru,
2386 "ldrd", "\t$Rt, $Rt2, $addr, $offset",
2387 "$addr.base = $Rn_wb", []> {
2390 let Inst{23} = offset{8}; // U bit
2391 let Inst{22} = offset{9}; // 1 == imm8, 0 == Rm
2392 let Inst{19-16} = addr;
2393 let Inst{11-8} = offset{7-4}; // imm7_4/zero
2394 let Inst{3-0} = offset{3-0}; // imm3_0/Rm
2395 let DecoderMethod = "DecodeAddrMode3Instruction";
2397 } // hasExtraDefRegAllocReq = 1
2398 } // mayLoad = 1, neverHasSideEffects = 1
2400 // LDRT, LDRBT, LDRSBT, LDRHT, LDRSHT.
2401 let mayLoad = 1, neverHasSideEffects = 1 in {
2402 def LDRT_POST_REG : AI2ldstidx<1, 0, 0, (outs GPR:$Rt, GPR:$Rn_wb),
2403 (ins addr_offset_none:$addr, am2offset_reg:$offset),
2404 IndexModePost, LdFrm, IIC_iLoad_ru,
2405 "ldrt", "\t$Rt, $addr, $offset",
2406 "$addr.base = $Rn_wb", []> {
2412 let Inst{23} = offset{12};
2413 let Inst{21} = 1; // overwrite
2414 let Inst{19-16} = addr;
2415 let Inst{11-5} = offset{11-5};
2417 let Inst{3-0} = offset{3-0};
2418 let DecoderMethod = "DecodeAddrMode2IdxInstruction";
2421 def LDRT_POST_IMM : AI2ldstidx<1, 0, 0, (outs GPR:$Rt, GPR:$Rn_wb),
2422 (ins addr_offset_none:$addr, am2offset_imm:$offset),
2423 IndexModePost, LdFrm, IIC_iLoad_ru,
2424 "ldrt", "\t$Rt, $addr, $offset",
2425 "$addr.base = $Rn_wb", []> {
2431 let Inst{23} = offset{12};
2432 let Inst{21} = 1; // overwrite
2433 let Inst{19-16} = addr;
2434 let Inst{11-0} = offset{11-0};
2435 let DecoderMethod = "DecodeAddrMode2IdxInstruction";
2438 def LDRBT_POST_REG : AI2ldstidx<1, 1, 0, (outs GPR:$Rt, GPR:$Rn_wb),
2439 (ins addr_offset_none:$addr, am2offset_reg:$offset),
2440 IndexModePost, LdFrm, IIC_iLoad_bh_ru,
2441 "ldrbt", "\t$Rt, $addr, $offset",
2442 "$addr.base = $Rn_wb", []> {
2448 let Inst{23} = offset{12};
2449 let Inst{21} = 1; // overwrite
2450 let Inst{19-16} = addr;
2451 let Inst{11-5} = offset{11-5};
2453 let Inst{3-0} = offset{3-0};
2454 let DecoderMethod = "DecodeAddrMode2IdxInstruction";
2457 def LDRBT_POST_IMM : AI2ldstidx<1, 1, 0, (outs GPR:$Rt, GPR:$Rn_wb),
2458 (ins addr_offset_none:$addr, am2offset_imm:$offset),
2459 IndexModePost, LdFrm, IIC_iLoad_bh_ru,
2460 "ldrbt", "\t$Rt, $addr, $offset",
2461 "$addr.base = $Rn_wb", []> {
2467 let Inst{23} = offset{12};
2468 let Inst{21} = 1; // overwrite
2469 let Inst{19-16} = addr;
2470 let Inst{11-0} = offset{11-0};
2471 let DecoderMethod = "DecodeAddrMode2IdxInstruction";
2474 multiclass AI3ldrT<bits<4> op, string opc> {
2475 def i : AI3ldstidxT<op, 1, (outs GPR:$Rt, GPR:$base_wb),
2476 (ins addr_offset_none:$addr, postidx_imm8:$offset),
2477 IndexModePost, LdMiscFrm, IIC_iLoad_bh_ru, opc,
2478 "\t$Rt, $addr, $offset", "$addr.base = $base_wb", []> {
2480 let Inst{23} = offset{8};
2482 let Inst{11-8} = offset{7-4};
2483 let Inst{3-0} = offset{3-0};
2484 let AsmMatchConverter = "cvtLdExtTWriteBackImm";
2486 def r : AI3ldstidxT<op, 1, (outs GPR:$Rt, GPR:$base_wb),
2487 (ins addr_offset_none:$addr, postidx_reg:$Rm),
2488 IndexModePost, LdMiscFrm, IIC_iLoad_bh_ru, opc,
2489 "\t$Rt, $addr, $Rm", "$addr.base = $base_wb", []> {
2491 let Inst{23} = Rm{4};
2494 let Inst{3-0} = Rm{3-0};
2495 let AsmMatchConverter = "cvtLdExtTWriteBackReg";
2499 defm LDRSBT : AI3ldrT<0b1101, "ldrsbt">;
2500 defm LDRHT : AI3ldrT<0b1011, "ldrht">;
2501 defm LDRSHT : AI3ldrT<0b1111, "ldrsht">;
2506 // Stores with truncate
2507 def STRH : AI3str<0b1011, (outs), (ins GPR:$Rt, addrmode3:$addr), StMiscFrm,
2508 IIC_iStore_bh_r, "strh", "\t$Rt, $addr",
2509 [(truncstorei16 GPR:$Rt, addrmode3:$addr)]>;
2512 let mayStore = 1, neverHasSideEffects = 1, hasExtraSrcRegAllocReq = 1 in
2513 def STRD : AI3str<0b1111, (outs), (ins GPR:$Rt, GPR:$src2, addrmode3:$addr),
2514 StMiscFrm, IIC_iStore_d_r,
2515 "strd", "\t$Rt, $src2, $addr", []>,
2516 Requires<[IsARM, HasV5TE]> {
2521 multiclass AI2_stridx<bit isByte, string opc,
2522 InstrItinClass iii, InstrItinClass iir> {
2523 def _PRE_IMM : AI2ldstidx<0, isByte, 1, (outs GPR:$Rn_wb),
2524 (ins GPR:$Rt, addrmode_imm12:$addr), IndexModePre,
2526 opc, "\t$Rt, $addr!", "$addr.base = $Rn_wb", []> {
2529 let Inst{23} = addr{12}; // U (add = ('U' == 1))
2530 let Inst{19-16} = addr{16-13}; // Rn
2531 let Inst{11-0} = addr{11-0}; // imm12
2532 let AsmMatchConverter = "cvtStWriteBackRegAddrModeImm12";
2533 let DecoderMethod = "DecodeSTRPreImm";
2536 def _PRE_REG : AI2ldstidx<0, isByte, 1, (outs GPR:$Rn_wb),
2537 (ins GPR:$Rt, ldst_so_reg:$addr),
2538 IndexModePre, StFrm, iir,
2539 opc, "\t$Rt, $addr!", "$addr.base = $Rn_wb", []> {
2542 let Inst{23} = addr{12}; // U (add = ('U' == 1))
2543 let Inst{19-16} = addr{16-13}; // Rn
2544 let Inst{11-0} = addr{11-0};
2545 let Inst{4} = 0; // Inst{4} = 0
2546 let AsmMatchConverter = "cvtStWriteBackRegAddrMode2";
2547 let DecoderMethod = "DecodeSTRPreReg";
2549 def _POST_REG : AI2ldstidx<0, isByte, 0, (outs GPR:$Rn_wb),
2550 (ins GPR:$Rt, addr_offset_none:$addr, am2offset_reg:$offset),
2551 IndexModePost, StFrm, iir,
2552 opc, "\t$Rt, $addr, $offset",
2553 "$addr.base = $Rn_wb", []> {
2559 let Inst{23} = offset{12};
2560 let Inst{19-16} = addr;
2561 let Inst{11-0} = offset{11-0};
2563 let DecoderMethod = "DecodeAddrMode2IdxInstruction";
2566 def _POST_IMM : AI2ldstidx<0, isByte, 0, (outs GPR:$Rn_wb),
2567 (ins GPR:$Rt, addr_offset_none:$addr, am2offset_imm:$offset),
2568 IndexModePost, StFrm, iii,
2569 opc, "\t$Rt, $addr, $offset",
2570 "$addr.base = $Rn_wb", []> {
2576 let Inst{23} = offset{12};
2577 let Inst{19-16} = addr;
2578 let Inst{11-0} = offset{11-0};
2580 let DecoderMethod = "DecodeAddrMode2IdxInstruction";
2584 let mayStore = 1, neverHasSideEffects = 1 in {
2585 // FIXME: for STR_PRE_REG etc. the itineray should be either IIC_iStore_ru or
2586 // IIC_iStore_siu depending on whether it the offset register is shifted.
2587 defm STR : AI2_stridx<0, "str", IIC_iStore_iu, IIC_iStore_ru>;
2588 defm STRB : AI2_stridx<1, "strb", IIC_iStore_bh_iu, IIC_iStore_bh_ru>;
2591 def : ARMPat<(post_store GPR:$Rt, addr_offset_none:$addr,
2592 am2offset_reg:$offset),
2593 (STR_POST_REG GPR:$Rt, addr_offset_none:$addr,
2594 am2offset_reg:$offset)>;
2595 def : ARMPat<(post_store GPR:$Rt, addr_offset_none:$addr,
2596 am2offset_imm:$offset),
2597 (STR_POST_IMM GPR:$Rt, addr_offset_none:$addr,
2598 am2offset_imm:$offset)>;
2599 def : ARMPat<(post_truncsti8 GPR:$Rt, addr_offset_none:$addr,
2600 am2offset_reg:$offset),
2601 (STRB_POST_REG GPR:$Rt, addr_offset_none:$addr,
2602 am2offset_reg:$offset)>;
2603 def : ARMPat<(post_truncsti8 GPR:$Rt, addr_offset_none:$addr,
2604 am2offset_imm:$offset),
2605 (STRB_POST_IMM GPR:$Rt, addr_offset_none:$addr,
2606 am2offset_imm:$offset)>;
2608 // Pseudo-instructions for pattern matching the pre-indexed stores. We can't
2609 // put the patterns on the instruction definitions directly as ISel wants
2610 // the address base and offset to be separate operands, not a single
2611 // complex operand like we represent the instructions themselves. The
2612 // pseudos map between the two.
2613 let usesCustomInserter = 1,
2614 Constraints = "$Rn = $Rn_wb,@earlyclobber $Rn_wb" in {
2615 def STRi_preidx: ARMPseudoInst<(outs GPR:$Rn_wb),
2616 (ins GPR:$Rt, GPR:$Rn, am2offset_imm:$offset, pred:$p),
2619 (pre_store GPR:$Rt, GPR:$Rn, am2offset_imm:$offset))]>;
2620 def STRr_preidx: ARMPseudoInst<(outs GPR:$Rn_wb),
2621 (ins GPR:$Rt, GPR:$Rn, am2offset_reg:$offset, pred:$p),
2624 (pre_store GPR:$Rt, GPR:$Rn, am2offset_reg:$offset))]>;
2625 def STRBi_preidx: ARMPseudoInst<(outs GPR:$Rn_wb),
2626 (ins GPR:$Rt, GPR:$Rn, am2offset_imm:$offset, pred:$p),
2629 (pre_truncsti8 GPR:$Rt, GPR:$Rn, am2offset_imm:$offset))]>;
2630 def STRBr_preidx: ARMPseudoInst<(outs GPR:$Rn_wb),
2631 (ins GPR:$Rt, GPR:$Rn, am2offset_reg:$offset, pred:$p),
2634 (pre_truncsti8 GPR:$Rt, GPR:$Rn, am2offset_reg:$offset))]>;
2635 def STRH_preidx: ARMPseudoInst<(outs GPR:$Rn_wb),
2636 (ins GPR:$Rt, GPR:$Rn, am3offset:$offset, pred:$p),
2639 (pre_truncsti16 GPR:$Rt, GPR:$Rn, am3offset:$offset))]>;
2644 def STRH_PRE : AI3ldstidx<0b1011, 0, 1, (outs GPR:$Rn_wb),
2645 (ins GPR:$Rt, addrmode3:$addr), IndexModePre,
2646 StMiscFrm, IIC_iStore_bh_ru,
2647 "strh", "\t$Rt, $addr!", "$addr.base = $Rn_wb", []> {
2649 let Inst{23} = addr{8}; // U bit
2650 let Inst{22} = addr{13}; // 1 == imm8, 0 == Rm
2651 let Inst{19-16} = addr{12-9}; // Rn
2652 let Inst{11-8} = addr{7-4}; // imm7_4/zero
2653 let Inst{3-0} = addr{3-0}; // imm3_0/Rm
2654 let AsmMatchConverter = "cvtStWriteBackRegAddrMode3";
2655 let DecoderMethod = "DecodeAddrMode3Instruction";
2658 def STRH_POST : AI3ldstidx<0b1011, 0, 0, (outs GPR:$Rn_wb),
2659 (ins GPR:$Rt, addr_offset_none:$addr, am3offset:$offset),
2660 IndexModePost, StMiscFrm, IIC_iStore_bh_ru,
2661 "strh", "\t$Rt, $addr, $offset", "$addr.base = $Rn_wb",
2662 [(set GPR:$Rn_wb, (post_truncsti16 GPR:$Rt,
2663 addr_offset_none:$addr,
2664 am3offset:$offset))]> {
2667 let Inst{23} = offset{8}; // U bit
2668 let Inst{22} = offset{9}; // 1 == imm8, 0 == Rm
2669 let Inst{19-16} = addr;
2670 let Inst{11-8} = offset{7-4}; // imm7_4/zero
2671 let Inst{3-0} = offset{3-0}; // imm3_0/Rm
2672 let DecoderMethod = "DecodeAddrMode3Instruction";
2675 let mayStore = 1, neverHasSideEffects = 1, hasExtraSrcRegAllocReq = 1 in {
2676 def STRD_PRE : AI3ldstidx<0b1111, 0, 1, (outs GPR:$Rn_wb),
2677 (ins GPR:$Rt, GPR:$Rt2, addrmode3:$addr),
2678 IndexModePre, StMiscFrm, IIC_iStore_d_ru,
2679 "strd", "\t$Rt, $Rt2, $addr!",
2680 "$addr.base = $Rn_wb", []> {
2682 let Inst{23} = addr{8}; // U bit
2683 let Inst{22} = addr{13}; // 1 == imm8, 0 == Rm
2684 let Inst{19-16} = addr{12-9}; // Rn
2685 let Inst{11-8} = addr{7-4}; // imm7_4/zero
2686 let Inst{3-0} = addr{3-0}; // imm3_0/Rm
2687 let DecoderMethod = "DecodeAddrMode3Instruction";
2688 let AsmMatchConverter = "cvtStrdPre";
2691 def STRD_POST: AI3ldstidx<0b1111, 0, 0, (outs GPR:$Rn_wb),
2692 (ins GPR:$Rt, GPR:$Rt2, addr_offset_none:$addr,
2694 IndexModePost, StMiscFrm, IIC_iStore_d_ru,
2695 "strd", "\t$Rt, $Rt2, $addr, $offset",
2696 "$addr.base = $Rn_wb", []> {
2699 let Inst{23} = offset{8}; // U bit
2700 let Inst{22} = offset{9}; // 1 == imm8, 0 == Rm
2701 let Inst{19-16} = addr;
2702 let Inst{11-8} = offset{7-4}; // imm7_4/zero
2703 let Inst{3-0} = offset{3-0}; // imm3_0/Rm
2704 let DecoderMethod = "DecodeAddrMode3Instruction";
2706 } // mayStore = 1, neverHasSideEffects = 1, hasExtraSrcRegAllocReq = 1
2708 // STRT, STRBT, and STRHT
2710 def STRBT_POST_REG : AI2ldstidx<0, 1, 0, (outs GPR:$Rn_wb),
2711 (ins GPR:$Rt, addr_offset_none:$addr, am2offset_reg:$offset),
2712 IndexModePost, StFrm, IIC_iStore_bh_ru,
2713 "strbt", "\t$Rt, $addr, $offset",
2714 "$addr.base = $Rn_wb", []> {
2720 let Inst{23} = offset{12};
2721 let Inst{21} = 1; // overwrite
2722 let Inst{19-16} = addr;
2723 let Inst{11-5} = offset{11-5};
2725 let Inst{3-0} = offset{3-0};
2726 let DecoderMethod = "DecodeAddrMode2IdxInstruction";
2729 def STRBT_POST_IMM : AI2ldstidx<0, 1, 0, (outs GPR:$Rn_wb),
2730 (ins GPR:$Rt, addr_offset_none:$addr, am2offset_imm:$offset),
2731 IndexModePost, StFrm, IIC_iStore_bh_ru,
2732 "strbt", "\t$Rt, $addr, $offset",
2733 "$addr.base = $Rn_wb", []> {
2739 let Inst{23} = offset{12};
2740 let Inst{21} = 1; // overwrite
2741 let Inst{19-16} = addr;
2742 let Inst{11-0} = offset{11-0};
2743 let DecoderMethod = "DecodeAddrMode2IdxInstruction";
2746 let mayStore = 1, neverHasSideEffects = 1 in {
2747 def STRT_POST_REG : AI2ldstidx<0, 0, 0, (outs GPR:$Rn_wb),
2748 (ins GPR:$Rt, addr_offset_none:$addr, am2offset_reg:$offset),
2749 IndexModePost, StFrm, IIC_iStore_ru,
2750 "strt", "\t$Rt, $addr, $offset",
2751 "$addr.base = $Rn_wb", []> {
2757 let Inst{23} = offset{12};
2758 let Inst{21} = 1; // overwrite
2759 let Inst{19-16} = addr;
2760 let Inst{11-5} = offset{11-5};
2762 let Inst{3-0} = offset{3-0};
2763 let DecoderMethod = "DecodeAddrMode2IdxInstruction";
2766 def STRT_POST_IMM : AI2ldstidx<0, 0, 0, (outs GPR:$Rn_wb),
2767 (ins GPR:$Rt, addr_offset_none:$addr, am2offset_imm:$offset),
2768 IndexModePost, StFrm, IIC_iStore_ru,
2769 "strt", "\t$Rt, $addr, $offset",
2770 "$addr.base = $Rn_wb", []> {
2776 let Inst{23} = offset{12};
2777 let Inst{21} = 1; // overwrite
2778 let Inst{19-16} = addr;
2779 let Inst{11-0} = offset{11-0};
2780 let DecoderMethod = "DecodeAddrMode2IdxInstruction";
2785 multiclass AI3strT<bits<4> op, string opc> {
2786 def i : AI3ldstidxT<op, 0, (outs GPR:$base_wb),
2787 (ins GPR:$Rt, addr_offset_none:$addr, postidx_imm8:$offset),
2788 IndexModePost, StMiscFrm, IIC_iStore_bh_ru, opc,
2789 "\t$Rt, $addr, $offset", "$addr.base = $base_wb", []> {
2791 let Inst{23} = offset{8};
2793 let Inst{11-8} = offset{7-4};
2794 let Inst{3-0} = offset{3-0};
2795 let AsmMatchConverter = "cvtStExtTWriteBackImm";
2797 def r : AI3ldstidxT<op, 0, (outs GPR:$base_wb),
2798 (ins GPR:$Rt, addr_offset_none:$addr, postidx_reg:$Rm),
2799 IndexModePost, StMiscFrm, IIC_iStore_bh_ru, opc,
2800 "\t$Rt, $addr, $Rm", "$addr.base = $base_wb", []> {
2802 let Inst{23} = Rm{4};
2805 let Inst{3-0} = Rm{3-0};
2806 let AsmMatchConverter = "cvtStExtTWriteBackReg";
2811 defm STRHT : AI3strT<0b1011, "strht">;
2814 //===----------------------------------------------------------------------===//
2815 // Load / store multiple Instructions.
2818 multiclass arm_ldst_mult<string asm, string sfx, bit L_bit, bit P_bit, Format f,
2819 InstrItinClass itin, InstrItinClass itin_upd> {
2820 // IA is the default, so no need for an explicit suffix on the
2821 // mnemonic here. Without it is the cannonical spelling.
2823 AXI4<(outs), (ins GPR:$Rn, pred:$p, reglist:$regs, variable_ops),
2824 IndexModeNone, f, itin,
2825 !strconcat(asm, "${p}\t$Rn, $regs", sfx), "", []> {
2826 let Inst{24-23} = 0b01; // Increment After
2827 let Inst{22} = P_bit;
2828 let Inst{21} = 0; // No writeback
2829 let Inst{20} = L_bit;
2832 AXI4<(outs GPR:$wb), (ins GPR:$Rn, pred:$p, reglist:$regs, variable_ops),
2833 IndexModeUpd, f, itin_upd,
2834 !strconcat(asm, "${p}\t$Rn!, $regs", sfx), "$Rn = $wb", []> {
2835 let Inst{24-23} = 0b01; // Increment After
2836 let Inst{22} = P_bit;
2837 let Inst{21} = 1; // Writeback
2838 let Inst{20} = L_bit;
2840 let DecoderMethod = "DecodeMemMultipleWritebackInstruction";
2843 AXI4<(outs), (ins GPR:$Rn, pred:$p, reglist:$regs, variable_ops),
2844 IndexModeNone, f, itin,
2845 !strconcat(asm, "da${p}\t$Rn, $regs", sfx), "", []> {
2846 let Inst{24-23} = 0b00; // Decrement After
2847 let Inst{22} = P_bit;
2848 let Inst{21} = 0; // No writeback
2849 let Inst{20} = L_bit;
2852 AXI4<(outs GPR:$wb), (ins GPR:$Rn, pred:$p, reglist:$regs, variable_ops),
2853 IndexModeUpd, f, itin_upd,
2854 !strconcat(asm, "da${p}\t$Rn!, $regs", sfx), "$Rn = $wb", []> {
2855 let Inst{24-23} = 0b00; // Decrement After
2856 let Inst{22} = P_bit;
2857 let Inst{21} = 1; // Writeback
2858 let Inst{20} = L_bit;
2860 let DecoderMethod = "DecodeMemMultipleWritebackInstruction";
2863 AXI4<(outs), (ins GPR:$Rn, pred:$p, reglist:$regs, variable_ops),
2864 IndexModeNone, f, itin,
2865 !strconcat(asm, "db${p}\t$Rn, $regs", sfx), "", []> {
2866 let Inst{24-23} = 0b10; // Decrement Before
2867 let Inst{22} = P_bit;
2868 let Inst{21} = 0; // No writeback
2869 let Inst{20} = L_bit;
2872 AXI4<(outs GPR:$wb), (ins GPR:$Rn, pred:$p, reglist:$regs, variable_ops),
2873 IndexModeUpd, f, itin_upd,
2874 !strconcat(asm, "db${p}\t$Rn!, $regs", sfx), "$Rn = $wb", []> {
2875 let Inst{24-23} = 0b10; // Decrement Before
2876 let Inst{22} = P_bit;
2877 let Inst{21} = 1; // Writeback
2878 let Inst{20} = L_bit;
2880 let DecoderMethod = "DecodeMemMultipleWritebackInstruction";
2883 AXI4<(outs), (ins GPR:$Rn, pred:$p, reglist:$regs, variable_ops),
2884 IndexModeNone, f, itin,
2885 !strconcat(asm, "ib${p}\t$Rn, $regs", sfx), "", []> {
2886 let Inst{24-23} = 0b11; // Increment Before
2887 let Inst{22} = P_bit;
2888 let Inst{21} = 0; // No writeback
2889 let Inst{20} = L_bit;
2892 AXI4<(outs GPR:$wb), (ins GPR:$Rn, pred:$p, reglist:$regs, variable_ops),
2893 IndexModeUpd, f, itin_upd,
2894 !strconcat(asm, "ib${p}\t$Rn!, $regs", sfx), "$Rn = $wb", []> {
2895 let Inst{24-23} = 0b11; // Increment Before
2896 let Inst{22} = P_bit;
2897 let Inst{21} = 1; // Writeback
2898 let Inst{20} = L_bit;
2900 let DecoderMethod = "DecodeMemMultipleWritebackInstruction";
2904 let neverHasSideEffects = 1 in {
2906 let mayLoad = 1, hasExtraDefRegAllocReq = 1 in
2907 defm LDM : arm_ldst_mult<"ldm", "", 1, 0, LdStMulFrm, IIC_iLoad_m,
2910 let mayStore = 1, hasExtraSrcRegAllocReq = 1 in
2911 defm STM : arm_ldst_mult<"stm", "", 0, 0, LdStMulFrm, IIC_iStore_m,
2914 } // neverHasSideEffects
2916 // FIXME: remove when we have a way to marking a MI with these properties.
2917 // FIXME: Should pc be an implicit operand like PICADD, etc?
2918 let isReturn = 1, isTerminator = 1, isBarrier = 1, mayLoad = 1,
2919 hasExtraDefRegAllocReq = 1, isCodeGenOnly = 1 in
2920 def LDMIA_RET : ARMPseudoExpand<(outs GPR:$wb), (ins GPR:$Rn, pred:$p,
2921 reglist:$regs, variable_ops),
2922 4, IIC_iLoad_mBr, [],
2923 (LDMIA_UPD GPR:$wb, GPR:$Rn, pred:$p, reglist:$regs)>,
2924 RegConstraint<"$Rn = $wb">;
2926 let mayLoad = 1, hasExtraDefRegAllocReq = 1 in
2927 defm sysLDM : arm_ldst_mult<"ldm", " ^", 1, 1, LdStMulFrm, IIC_iLoad_m,
2930 let mayStore = 1, hasExtraSrcRegAllocReq = 1 in
2931 defm sysSTM : arm_ldst_mult<"stm", " ^", 0, 1, LdStMulFrm, IIC_iStore_m,
2936 //===----------------------------------------------------------------------===//
2937 // Move Instructions.
2940 let neverHasSideEffects = 1 in
2941 def MOVr : AsI1<0b1101, (outs GPR:$Rd), (ins GPR:$Rm), DPFrm, IIC_iMOVr,
2942 "mov", "\t$Rd, $Rm", []>, UnaryDP {
2946 let Inst{19-16} = 0b0000;
2947 let Inst{11-4} = 0b00000000;
2950 let Inst{15-12} = Rd;
2953 def : ARMInstAlias<"movs${p} $Rd, $Rm",
2954 (MOVr GPR:$Rd, GPR:$Rm, pred:$p, CPSR)>;
2956 // A version for the smaller set of tail call registers.
2957 let neverHasSideEffects = 1 in
2958 def MOVr_TC : AsI1<0b1101, (outs tcGPR:$Rd), (ins tcGPR:$Rm), DPFrm,
2959 IIC_iMOVr, "mov", "\t$Rd, $Rm", []>, UnaryDP {
2963 let Inst{11-4} = 0b00000000;
2966 let Inst{15-12} = Rd;
2969 def MOVsr : AsI1<0b1101, (outs GPRnopc:$Rd), (ins shift_so_reg_reg:$src),
2970 DPSoRegRegFrm, IIC_iMOVsr,
2971 "mov", "\t$Rd, $src",
2972 [(set GPRnopc:$Rd, shift_so_reg_reg:$src)]>, UnaryDP {
2975 let Inst{15-12} = Rd;
2976 let Inst{19-16} = 0b0000;
2977 let Inst{11-8} = src{11-8};
2979 let Inst{6-5} = src{6-5};
2981 let Inst{3-0} = src{3-0};
2985 def MOVsi : AsI1<0b1101, (outs GPR:$Rd), (ins shift_so_reg_imm:$src),
2986 DPSoRegImmFrm, IIC_iMOVsr,
2987 "mov", "\t$Rd, $src", [(set GPR:$Rd, shift_so_reg_imm:$src)]>,
2991 let Inst{15-12} = Rd;
2992 let Inst{19-16} = 0b0000;
2993 let Inst{11-5} = src{11-5};
2995 let Inst{3-0} = src{3-0};
2999 let isReMaterializable = 1, isAsCheapAsAMove = 1, isMoveImm = 1 in
3000 def MOVi : AsI1<0b1101, (outs GPR:$Rd), (ins so_imm:$imm), DPFrm, IIC_iMOVi,
3001 "mov", "\t$Rd, $imm", [(set GPR:$Rd, so_imm:$imm)]>, UnaryDP {
3005 let Inst{15-12} = Rd;
3006 let Inst{19-16} = 0b0000;
3007 let Inst{11-0} = imm;
3010 let isReMaterializable = 1, isAsCheapAsAMove = 1, isMoveImm = 1 in
3011 def MOVi16 : AI1<0b1000, (outs GPR:$Rd), (ins imm0_65535_expr:$imm),
3013 "movw", "\t$Rd, $imm",
3014 [(set GPR:$Rd, imm0_65535:$imm)]>,
3015 Requires<[IsARM, HasV6T2]>, UnaryDP {
3018 let Inst{15-12} = Rd;
3019 let Inst{11-0} = imm{11-0};
3020 let Inst{19-16} = imm{15-12};
3023 let DecoderMethod = "DecodeArmMOVTWInstruction";
3026 def : InstAlias<"mov${p} $Rd, $imm",
3027 (MOVi16 GPR:$Rd, imm0_65535_expr:$imm, pred:$p)>,
3030 def MOVi16_ga_pcrel : PseudoInst<(outs GPR:$Rd),
3031 (ins i32imm:$addr, pclabel:$id), IIC_iMOVi, []>;
3033 let Constraints = "$src = $Rd" in {
3034 def MOVTi16 : AI1<0b1010, (outs GPRnopc:$Rd),
3035 (ins GPR:$src, imm0_65535_expr:$imm),
3037 "movt", "\t$Rd, $imm",
3039 (or (and GPR:$src, 0xffff),
3040 lo16AllZero:$imm))]>, UnaryDP,
3041 Requires<[IsARM, HasV6T2]> {
3044 let Inst{15-12} = Rd;
3045 let Inst{11-0} = imm{11-0};
3046 let Inst{19-16} = imm{15-12};
3049 let DecoderMethod = "DecodeArmMOVTWInstruction";
3052 def MOVTi16_ga_pcrel : PseudoInst<(outs GPR:$Rd),
3053 (ins GPR:$src, i32imm:$addr, pclabel:$id), IIC_iMOVi, []>;
3057 def : ARMPat<(or GPR:$src, 0xffff0000), (MOVTi16 GPR:$src, 0xffff)>,
3058 Requires<[IsARM, HasV6T2]>;
3060 let Uses = [CPSR] in
3061 def RRX: PseudoInst<(outs GPR:$Rd), (ins GPR:$Rm), IIC_iMOVsi,
3062 [(set GPR:$Rd, (ARMrrx GPR:$Rm))]>, UnaryDP,
3065 // These aren't really mov instructions, but we have to define them this way
3066 // due to flag operands.
3068 let Defs = [CPSR] in {
3069 def MOVsrl_flag : PseudoInst<(outs GPR:$dst), (ins GPR:$src), IIC_iMOVsi,
3070 [(set GPR:$dst, (ARMsrl_flag GPR:$src))]>, UnaryDP,
3072 def MOVsra_flag : PseudoInst<(outs GPR:$dst), (ins GPR:$src), IIC_iMOVsi,
3073 [(set GPR:$dst, (ARMsra_flag GPR:$src))]>, UnaryDP,
3077 //===----------------------------------------------------------------------===//
3078 // Extend Instructions.
3083 def SXTB : AI_ext_rrot<0b01101010,
3084 "sxtb", UnOpFrag<(sext_inreg node:$Src, i8)>>;
3085 def SXTH : AI_ext_rrot<0b01101011,
3086 "sxth", UnOpFrag<(sext_inreg node:$Src, i16)>>;
3088 def SXTAB : AI_exta_rrot<0b01101010,
3089 "sxtab", BinOpFrag<(add node:$LHS, (sext_inreg node:$RHS, i8))>>;
3090 def SXTAH : AI_exta_rrot<0b01101011,
3091 "sxtah", BinOpFrag<(add node:$LHS, (sext_inreg node:$RHS,i16))>>;
3093 def SXTB16 : AI_ext_rrot_np<0b01101000, "sxtb16">;
3095 def SXTAB16 : AI_exta_rrot_np<0b01101000, "sxtab16">;
3099 let AddedComplexity = 16 in {
3100 def UXTB : AI_ext_rrot<0b01101110,
3101 "uxtb" , UnOpFrag<(and node:$Src, 0x000000FF)>>;
3102 def UXTH : AI_ext_rrot<0b01101111,
3103 "uxth" , UnOpFrag<(and node:$Src, 0x0000FFFF)>>;
3104 def UXTB16 : AI_ext_rrot<0b01101100,
3105 "uxtb16", UnOpFrag<(and node:$Src, 0x00FF00FF)>>;
3107 // FIXME: This pattern incorrectly assumes the shl operator is a rotate.
3108 // The transformation should probably be done as a combiner action
3109 // instead so we can include a check for masking back in the upper
3110 // eight bits of the source into the lower eight bits of the result.
3111 //def : ARMV6Pat<(and (shl GPR:$Src, (i32 8)), 0xFF00FF),
3112 // (UXTB16r_rot GPR:$Src, 3)>;
3113 def : ARMV6Pat<(and (srl GPR:$Src, (i32 8)), 0xFF00FF),
3114 (UXTB16 GPR:$Src, 1)>;
3116 def UXTAB : AI_exta_rrot<0b01101110, "uxtab",
3117 BinOpFrag<(add node:$LHS, (and node:$RHS, 0x00FF))>>;
3118 def UXTAH : AI_exta_rrot<0b01101111, "uxtah",
3119 BinOpFrag<(add node:$LHS, (and node:$RHS, 0xFFFF))>>;
3122 // This isn't safe in general, the add is two 16-bit units, not a 32-bit add.
3123 def UXTAB16 : AI_exta_rrot_np<0b01101100, "uxtab16">;
3126 def SBFX : I<(outs GPRnopc:$Rd),
3127 (ins GPRnopc:$Rn, imm0_31:$lsb, imm1_32:$width),
3128 AddrMode1, 4, IndexModeNone, DPFrm, IIC_iUNAsi,
3129 "sbfx", "\t$Rd, $Rn, $lsb, $width", "", []>,
3130 Requires<[IsARM, HasV6T2]> {
3135 let Inst{27-21} = 0b0111101;
3136 let Inst{6-4} = 0b101;
3137 let Inst{20-16} = width;
3138 let Inst{15-12} = Rd;
3139 let Inst{11-7} = lsb;
3143 def UBFX : I<(outs GPR:$Rd),
3144 (ins GPR:$Rn, imm0_31:$lsb, imm1_32:$width),
3145 AddrMode1, 4, IndexModeNone, DPFrm, IIC_iUNAsi,
3146 "ubfx", "\t$Rd, $Rn, $lsb, $width", "", []>,
3147 Requires<[IsARM, HasV6T2]> {
3152 let Inst{27-21} = 0b0111111;
3153 let Inst{6-4} = 0b101;
3154 let Inst{20-16} = width;
3155 let Inst{15-12} = Rd;
3156 let Inst{11-7} = lsb;
3160 //===----------------------------------------------------------------------===//
3161 // Arithmetic Instructions.
3164 defm ADD : AsI1_bin_irs<0b0100, "add",
3165 IIC_iALUi, IIC_iALUr, IIC_iALUsr,
3166 BinOpFrag<(add node:$LHS, node:$RHS)>, "ADD", 1>;
3167 defm SUB : AsI1_bin_irs<0b0010, "sub",
3168 IIC_iALUi, IIC_iALUr, IIC_iALUsr,
3169 BinOpFrag<(sub node:$LHS, node:$RHS)>, "SUB">;
3171 // ADD and SUB with 's' bit set.
3173 // Currently, ADDS/SUBS are pseudo opcodes that exist only in the
3174 // selection DAG. They are "lowered" to real ADD/SUB opcodes by
3175 // AdjustInstrPostInstrSelection where we determine whether or not to
3176 // set the "s" bit based on CPSR liveness.
3178 // FIXME: Eliminate ADDS/SUBS pseudo opcodes after adding tablegen
3179 // support for an optional CPSR definition that corresponds to the DAG
3180 // node's second value. We can then eliminate the implicit def of CPSR.
3181 defm ADDS : AsI1_bin_s_irs<IIC_iALUi, IIC_iALUr, IIC_iALUsr,
3182 BinOpFrag<(ARMaddc node:$LHS, node:$RHS)>, 1>;
3183 defm SUBS : AsI1_bin_s_irs<IIC_iALUi, IIC_iALUr, IIC_iALUsr,
3184 BinOpFrag<(ARMsubc node:$LHS, node:$RHS)>>;
3186 defm ADC : AI1_adde_sube_irs<0b0101, "adc",
3187 BinOpWithFlagFrag<(ARMadde node:$LHS, node:$RHS, node:$FLAG)>,
3189 defm SBC : AI1_adde_sube_irs<0b0110, "sbc",
3190 BinOpWithFlagFrag<(ARMsube node:$LHS, node:$RHS, node:$FLAG)>,
3193 defm RSB : AsI1_rbin_irs <0b0011, "rsb",
3194 IIC_iALUi, IIC_iALUr, IIC_iALUsr,
3195 BinOpFrag<(sub node:$LHS, node:$RHS)>, "RSB">;
3197 // FIXME: Eliminate them if we can write def : Pat patterns which defines
3198 // CPSR and the implicit def of CPSR is not needed.
3199 defm RSBS : AsI1_rbin_s_is<IIC_iALUi, IIC_iALUr, IIC_iALUsr,
3200 BinOpFrag<(ARMsubc node:$LHS, node:$RHS)>>;
3202 defm RSC : AI1_rsc_irs<0b0111, "rsc",
3203 BinOpWithFlagFrag<(ARMsube node:$LHS, node:$RHS, node:$FLAG)>,
3206 // (sub X, imm) gets canonicalized to (add X, -imm). Match this form.
3207 // The assume-no-carry-in form uses the negation of the input since add/sub
3208 // assume opposite meanings of the carry flag (i.e., carry == !borrow).
3209 // See the definition of AddWithCarry() in the ARM ARM A2.2.1 for the gory
3211 def : ARMPat<(add GPR:$src, so_imm_neg:$imm),
3212 (SUBri GPR:$src, so_imm_neg:$imm)>;
3213 def : ARMPat<(ARMaddc GPR:$src, so_imm_neg:$imm),
3214 (SUBSri GPR:$src, so_imm_neg:$imm)>;
3216 // The with-carry-in form matches bitwise not instead of the negation.
3217 // Effectively, the inverse interpretation of the carry flag already accounts
3218 // for part of the negation.
3219 def : ARMPat<(ARMadde GPR:$src, so_imm_not:$imm, CPSR),
3220 (SBCri GPR:$src, so_imm_not:$imm)>;
3222 // Note: These are implemented in C++ code, because they have to generate
3223 // ADD/SUBrs instructions, which use a complex pattern that a xform function
3225 // (mul X, 2^n+1) -> (add (X << n), X)
3226 // (mul X, 2^n-1) -> (rsb X, (X << n))
3228 // ARM Arithmetic Instruction
3229 // GPR:$dst = GPR:$a op GPR:$b
3230 class AAI<bits<8> op27_20, bits<8> op11_4, string opc,
3231 list<dag> pattern = [],
3232 dag iops = (ins GPRnopc:$Rn, GPRnopc:$Rm),
3233 string asm = "\t$Rd, $Rn, $Rm">
3234 : AI<(outs GPRnopc:$Rd), iops, DPFrm, IIC_iALUr, opc, asm, pattern> {
3238 let Inst{27-20} = op27_20;
3239 let Inst{11-4} = op11_4;
3240 let Inst{19-16} = Rn;
3241 let Inst{15-12} = Rd;
3245 // Saturating add/subtract
3247 def QADD : AAI<0b00010000, 0b00000101, "qadd",
3248 [(set GPRnopc:$Rd, (int_arm_qadd GPRnopc:$Rm, GPRnopc:$Rn))],
3249 (ins GPRnopc:$Rm, GPRnopc:$Rn), "\t$Rd, $Rm, $Rn">;
3250 def QSUB : AAI<0b00010010, 0b00000101, "qsub",
3251 [(set GPRnopc:$Rd, (int_arm_qsub GPRnopc:$Rm, GPRnopc:$Rn))],
3252 (ins GPRnopc:$Rm, GPRnopc:$Rn), "\t$Rd, $Rm, $Rn">;
3253 def QDADD : AAI<0b00010100, 0b00000101, "qdadd", [],
3254 (ins GPRnopc:$Rm, GPRnopc:$Rn),
3256 def QDSUB : AAI<0b00010110, 0b00000101, "qdsub", [],
3257 (ins GPRnopc:$Rm, GPRnopc:$Rn),
3260 def QADD16 : AAI<0b01100010, 0b11110001, "qadd16">;
3261 def QADD8 : AAI<0b01100010, 0b11111001, "qadd8">;
3262 def QASX : AAI<0b01100010, 0b11110011, "qasx">;
3263 def QSAX : AAI<0b01100010, 0b11110101, "qsax">;
3264 def QSUB16 : AAI<0b01100010, 0b11110111, "qsub16">;
3265 def QSUB8 : AAI<0b01100010, 0b11111111, "qsub8">;
3266 def UQADD16 : AAI<0b01100110, 0b11110001, "uqadd16">;
3267 def UQADD8 : AAI<0b01100110, 0b11111001, "uqadd8">;
3268 def UQASX : AAI<0b01100110, 0b11110011, "uqasx">;
3269 def UQSAX : AAI<0b01100110, 0b11110101, "uqsax">;
3270 def UQSUB16 : AAI<0b01100110, 0b11110111, "uqsub16">;
3271 def UQSUB8 : AAI<0b01100110, 0b11111111, "uqsub8">;
3273 // Signed/Unsigned add/subtract
3275 def SASX : AAI<0b01100001, 0b11110011, "sasx">;
3276 def SADD16 : AAI<0b01100001, 0b11110001, "sadd16">;
3277 def SADD8 : AAI<0b01100001, 0b11111001, "sadd8">;
3278 def SSAX : AAI<0b01100001, 0b11110101, "ssax">;
3279 def SSUB16 : AAI<0b01100001, 0b11110111, "ssub16">;
3280 def SSUB8 : AAI<0b01100001, 0b11111111, "ssub8">;
3281 def UASX : AAI<0b01100101, 0b11110011, "uasx">;
3282 def UADD16 : AAI<0b01100101, 0b11110001, "uadd16">;
3283 def UADD8 : AAI<0b01100101, 0b11111001, "uadd8">;
3284 def USAX : AAI<0b01100101, 0b11110101, "usax">;
3285 def USUB16 : AAI<0b01100101, 0b11110111, "usub16">;
3286 def USUB8 : AAI<0b01100101, 0b11111111, "usub8">;
3288 // Signed/Unsigned halving add/subtract
3290 def SHASX : AAI<0b01100011, 0b11110011, "shasx">;
3291 def SHADD16 : AAI<0b01100011, 0b11110001, "shadd16">;
3292 def SHADD8 : AAI<0b01100011, 0b11111001, "shadd8">;
3293 def SHSAX : AAI<0b01100011, 0b11110101, "shsax">;
3294 def SHSUB16 : AAI<0b01100011, 0b11110111, "shsub16">;
3295 def SHSUB8 : AAI<0b01100011, 0b11111111, "shsub8">;
3296 def UHASX : AAI<0b01100111, 0b11110011, "uhasx">;
3297 def UHADD16 : AAI<0b01100111, 0b11110001, "uhadd16">;
3298 def UHADD8 : AAI<0b01100111, 0b11111001, "uhadd8">;
3299 def UHSAX : AAI<0b01100111, 0b11110101, "uhsax">;
3300 def UHSUB16 : AAI<0b01100111, 0b11110111, "uhsub16">;
3301 def UHSUB8 : AAI<0b01100111, 0b11111111, "uhsub8">;
3303 // Unsigned Sum of Absolute Differences [and Accumulate].
3305 def USAD8 : AI<(outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm),
3306 MulFrm /* for convenience */, NoItinerary, "usad8",
3307 "\t$Rd, $Rn, $Rm", []>,
3308 Requires<[IsARM, HasV6]> {
3312 let Inst{27-20} = 0b01111000;
3313 let Inst{15-12} = 0b1111;
3314 let Inst{7-4} = 0b0001;
3315 let Inst{19-16} = Rd;
3316 let Inst{11-8} = Rm;
3319 def USADA8 : AI<(outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm, GPR:$Ra),
3320 MulFrm /* for convenience */, NoItinerary, "usada8",
3321 "\t$Rd, $Rn, $Rm, $Ra", []>,
3322 Requires<[IsARM, HasV6]> {
3327 let Inst{27-20} = 0b01111000;
3328 let Inst{7-4} = 0b0001;
3329 let Inst{19-16} = Rd;
3330 let Inst{15-12} = Ra;
3331 let Inst{11-8} = Rm;
3335 // Signed/Unsigned saturate
3337 def SSAT : AI<(outs GPRnopc:$Rd),
3338 (ins imm1_32:$sat_imm, GPRnopc:$Rn, shift_imm:$sh),
3339 SatFrm, NoItinerary, "ssat", "\t$Rd, $sat_imm, $Rn$sh", []> {
3344 let Inst{27-21} = 0b0110101;
3345 let Inst{5-4} = 0b01;
3346 let Inst{20-16} = sat_imm;
3347 let Inst{15-12} = Rd;
3348 let Inst{11-7} = sh{4-0};
3349 let Inst{6} = sh{5};
3353 def SSAT16 : AI<(outs GPRnopc:$Rd),
3354 (ins imm1_16:$sat_imm, GPRnopc:$Rn), SatFrm,
3355 NoItinerary, "ssat16", "\t$Rd, $sat_imm, $Rn", []> {
3359 let Inst{27-20} = 0b01101010;
3360 let Inst{11-4} = 0b11110011;
3361 let Inst{15-12} = Rd;
3362 let Inst{19-16} = sat_imm;
3366 def USAT : AI<(outs GPRnopc:$Rd),
3367 (ins imm0_31:$sat_imm, GPRnopc:$Rn, shift_imm:$sh),
3368 SatFrm, NoItinerary, "usat", "\t$Rd, $sat_imm, $Rn$sh", []> {
3373 let Inst{27-21} = 0b0110111;
3374 let Inst{5-4} = 0b01;
3375 let Inst{15-12} = Rd;
3376 let Inst{11-7} = sh{4-0};
3377 let Inst{6} = sh{5};
3378 let Inst{20-16} = sat_imm;
3382 def USAT16 : AI<(outs GPRnopc:$Rd),
3383 (ins imm0_15:$sat_imm, GPRnopc:$Rn), SatFrm,
3384 NoItinerary, "usat16", "\t$Rd, $sat_imm, $Rn", []> {
3388 let Inst{27-20} = 0b01101110;
3389 let Inst{11-4} = 0b11110011;
3390 let Inst{15-12} = Rd;
3391 let Inst{19-16} = sat_imm;
3395 def : ARMV6Pat<(int_arm_ssat GPRnopc:$a, imm:$pos),
3396 (SSAT imm:$pos, GPRnopc:$a, 0)>;
3397 def : ARMV6Pat<(int_arm_usat GPRnopc:$a, imm:$pos),
3398 (USAT imm:$pos, GPRnopc:$a, 0)>;
3400 //===----------------------------------------------------------------------===//
3401 // Bitwise Instructions.
3404 defm AND : AsI1_bin_irs<0b0000, "and",
3405 IIC_iBITi, IIC_iBITr, IIC_iBITsr,
3406 BinOpFrag<(and node:$LHS, node:$RHS)>, "AND", 1>;
3407 defm ORR : AsI1_bin_irs<0b1100, "orr",
3408 IIC_iBITi, IIC_iBITr, IIC_iBITsr,
3409 BinOpFrag<(or node:$LHS, node:$RHS)>, "ORR", 1>;
3410 defm EOR : AsI1_bin_irs<0b0001, "eor",
3411 IIC_iBITi, IIC_iBITr, IIC_iBITsr,
3412 BinOpFrag<(xor node:$LHS, node:$RHS)>, "EOR", 1>;
3413 defm BIC : AsI1_bin_irs<0b1110, "bic",
3414 IIC_iBITi, IIC_iBITr, IIC_iBITsr,
3415 BinOpFrag<(and node:$LHS, (not node:$RHS))>, "BIC">;
3417 // FIXME: bf_inv_mask_imm should be two operands, the lsb and the msb, just
3418 // like in the actual instruction encoding. The complexity of mapping the mask
3419 // to the lsb/msb pair should be handled by ISel, not encapsulated in the
3420 // instruction description.
3421 def BFC : I<(outs GPR:$Rd), (ins GPR:$src, bf_inv_mask_imm:$imm),
3422 AddrMode1, 4, IndexModeNone, DPFrm, IIC_iUNAsi,
3423 "bfc", "\t$Rd, $imm", "$src = $Rd",
3424 [(set GPR:$Rd, (and GPR:$src, bf_inv_mask_imm:$imm))]>,
3425 Requires<[IsARM, HasV6T2]> {
3428 let Inst{27-21} = 0b0111110;
3429 let Inst{6-0} = 0b0011111;
3430 let Inst{15-12} = Rd;
3431 let Inst{11-7} = imm{4-0}; // lsb
3432 let Inst{20-16} = imm{9-5}; // msb
3435 // A8.6.18 BFI - Bitfield insert (Encoding A1)
3436 def BFI:I<(outs GPRnopc:$Rd), (ins GPRnopc:$src, GPR:$Rn, bf_inv_mask_imm:$imm),
3437 AddrMode1, 4, IndexModeNone, DPFrm, IIC_iUNAsi,
3438 "bfi", "\t$Rd, $Rn, $imm", "$src = $Rd",
3439 [(set GPRnopc:$Rd, (ARMbfi GPRnopc:$src, GPR:$Rn,
3440 bf_inv_mask_imm:$imm))]>,
3441 Requires<[IsARM, HasV6T2]> {
3445 let Inst{27-21} = 0b0111110;
3446 let Inst{6-4} = 0b001; // Rn: Inst{3-0} != 15
3447 let Inst{15-12} = Rd;
3448 let Inst{11-7} = imm{4-0}; // lsb
3449 let Inst{20-16} = imm{9-5}; // width
3453 def MVNr : AsI1<0b1111, (outs GPR:$Rd), (ins GPR:$Rm), DPFrm, IIC_iMVNr,
3454 "mvn", "\t$Rd, $Rm",
3455 [(set GPR:$Rd, (not GPR:$Rm))]>, UnaryDP {
3459 let Inst{19-16} = 0b0000;
3460 let Inst{11-4} = 0b00000000;
3461 let Inst{15-12} = Rd;
3464 def MVNsi : AsI1<0b1111, (outs GPR:$Rd), (ins so_reg_imm:$shift),
3465 DPSoRegImmFrm, IIC_iMVNsr, "mvn", "\t$Rd, $shift",
3466 [(set GPR:$Rd, (not so_reg_imm:$shift))]>, UnaryDP {
3470 let Inst{19-16} = 0b0000;
3471 let Inst{15-12} = Rd;
3472 let Inst{11-5} = shift{11-5};
3474 let Inst{3-0} = shift{3-0};
3476 def MVNsr : AsI1<0b1111, (outs GPR:$Rd), (ins so_reg_reg:$shift),
3477 DPSoRegRegFrm, IIC_iMVNsr, "mvn", "\t$Rd, $shift",
3478 [(set GPR:$Rd, (not so_reg_reg:$shift))]>, UnaryDP {
3482 let Inst{19-16} = 0b0000;
3483 let Inst{15-12} = Rd;
3484 let Inst{11-8} = shift{11-8};
3486 let Inst{6-5} = shift{6-5};
3488 let Inst{3-0} = shift{3-0};
3490 let isReMaterializable = 1, isAsCheapAsAMove = 1, isMoveImm = 1 in
3491 def MVNi : AsI1<0b1111, (outs GPR:$Rd), (ins so_imm:$imm), DPFrm,
3492 IIC_iMVNi, "mvn", "\t$Rd, $imm",
3493 [(set GPR:$Rd, so_imm_not:$imm)]>,UnaryDP {
3497 let Inst{19-16} = 0b0000;
3498 let Inst{15-12} = Rd;
3499 let Inst{11-0} = imm;
3502 def : ARMPat<(and GPR:$src, so_imm_not:$imm),
3503 (BICri GPR:$src, so_imm_not:$imm)>;
3505 //===----------------------------------------------------------------------===//
3506 // Multiply Instructions.
3508 class AsMul1I32<bits<7> opcod, dag oops, dag iops, InstrItinClass itin,
3509 string opc, string asm, list<dag> pattern>
3510 : AsMul1I<opcod, oops, iops, itin, opc, asm, pattern> {
3514 let Inst{19-16} = Rd;
3515 let Inst{11-8} = Rm;
3518 class AsMul1I64<bits<7> opcod, dag oops, dag iops, InstrItinClass itin,
3519 string opc, string asm, list<dag> pattern>
3520 : AsMul1I<opcod, oops, iops, itin, opc, asm, pattern> {
3525 let Inst{19-16} = RdHi;
3526 let Inst{15-12} = RdLo;
3527 let Inst{11-8} = Rm;
3531 // FIXME: The v5 pseudos are only necessary for the additional Constraint
3532 // property. Remove them when it's possible to add those properties
3533 // on an individual MachineInstr, not just an instuction description.
3534 let isCommutable = 1 in {
3535 def MUL : AsMul1I32<0b0000000, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm),
3536 IIC_iMUL32, "mul", "\t$Rd, $Rn, $Rm",
3537 [(set GPR:$Rd, (mul GPR:$Rn, GPR:$Rm))]>,
3538 Requires<[IsARM, HasV6]> {
3539 let Inst{15-12} = 0b0000;
3542 let Constraints = "@earlyclobber $Rd" in
3543 def MULv5: ARMPseudoExpand<(outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm,
3544 pred:$p, cc_out:$s),
3546 [(set GPR:$Rd, (mul GPR:$Rn, GPR:$Rm))],
3547 (MUL GPR:$Rd, GPR:$Rn, GPR:$Rm, pred:$p, cc_out:$s)>,
3548 Requires<[IsARM, NoV6]>;
3551 def MLA : AsMul1I32<0b0000001, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm, GPR:$Ra),
3552 IIC_iMAC32, "mla", "\t$Rd, $Rn, $Rm, $Ra",
3553 [(set GPR:$Rd, (add (mul GPR:$Rn, GPR:$Rm), GPR:$Ra))]>,
3554 Requires<[IsARM, HasV6]> {
3556 let Inst{15-12} = Ra;
3559 let Constraints = "@earlyclobber $Rd" in
3560 def MLAv5: ARMPseudoExpand<(outs GPR:$Rd),
3561 (ins GPR:$Rn, GPR:$Rm, GPR:$Ra, pred:$p, cc_out:$s),
3563 [(set GPR:$Rd, (add (mul GPR:$Rn, GPR:$Rm), GPR:$Ra))],
3564 (MLA GPR:$Rd, GPR:$Rn, GPR:$Rm, GPR:$Ra, pred:$p, cc_out:$s)>,
3565 Requires<[IsARM, NoV6]>;
3567 def MLS : AMul1I<0b0000011, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm, GPR:$Ra),
3568 IIC_iMAC32, "mls", "\t$Rd, $Rn, $Rm, $Ra",
3569 [(set GPR:$Rd, (sub GPR:$Ra, (mul GPR:$Rn, GPR:$Rm)))]>,
3570 Requires<[IsARM, HasV6T2]> {
3575 let Inst{19-16} = Rd;
3576 let Inst{15-12} = Ra;
3577 let Inst{11-8} = Rm;
3581 // Extra precision multiplies with low / high results
3582 let neverHasSideEffects = 1 in {
3583 let isCommutable = 1 in {
3584 def SMULL : AsMul1I64<0b0000110, (outs GPR:$RdLo, GPR:$RdHi),
3585 (ins GPR:$Rn, GPR:$Rm), IIC_iMUL64,
3586 "smull", "\t$RdLo, $RdHi, $Rn, $Rm", []>,
3587 Requires<[IsARM, HasV6]>;
3589 def UMULL : AsMul1I64<0b0000100, (outs GPR:$RdLo, GPR:$RdHi),
3590 (ins GPR:$Rn, GPR:$Rm), IIC_iMUL64,
3591 "umull", "\t$RdLo, $RdHi, $Rn, $Rm", []>,
3592 Requires<[IsARM, HasV6]>;
3594 let Constraints = "@earlyclobber $RdLo,@earlyclobber $RdHi" in {
3595 def SMULLv5 : ARMPseudoExpand<(outs GPR:$RdLo, GPR:$RdHi),
3596 (ins GPR:$Rn, GPR:$Rm, pred:$p, cc_out:$s),
3598 (SMULL GPR:$RdLo, GPR:$RdHi, GPR:$Rn, GPR:$Rm, pred:$p, cc_out:$s)>,
3599 Requires<[IsARM, NoV6]>;
3601 def UMULLv5 : ARMPseudoExpand<(outs GPR:$RdLo, GPR:$RdHi),
3602 (ins GPR:$Rn, GPR:$Rm, pred:$p, cc_out:$s),
3604 (UMULL GPR:$RdLo, GPR:$RdHi, GPR:$Rn, GPR:$Rm, pred:$p, cc_out:$s)>,
3605 Requires<[IsARM, NoV6]>;
3609 // Multiply + accumulate
3610 def SMLAL : AsMul1I64<0b0000111, (outs GPR:$RdLo, GPR:$RdHi),
3611 (ins GPR:$Rn, GPR:$Rm), IIC_iMAC64,
3612 "smlal", "\t$RdLo, $RdHi, $Rn, $Rm", []>,
3613 Requires<[IsARM, HasV6]>;
3614 def UMLAL : AsMul1I64<0b0000101, (outs GPR:$RdLo, GPR:$RdHi),
3615 (ins GPR:$Rn, GPR:$Rm), IIC_iMAC64,
3616 "umlal", "\t$RdLo, $RdHi, $Rn, $Rm", []>,
3617 Requires<[IsARM, HasV6]>;
3619 def UMAAL : AMul1I <0b0000010, (outs GPR:$RdLo, GPR:$RdHi),
3620 (ins GPR:$Rn, GPR:$Rm), IIC_iMAC64,
3621 "umaal", "\t$RdLo, $RdHi, $Rn, $Rm", []>,
3622 Requires<[IsARM, HasV6]> {
3627 let Inst{19-16} = RdHi;
3628 let Inst{15-12} = RdLo;
3629 let Inst{11-8} = Rm;
3633 let Constraints = "@earlyclobber $RdLo,@earlyclobber $RdHi" in {
3634 def SMLALv5 : ARMPseudoExpand<(outs GPR:$RdLo, GPR:$RdHi),
3635 (ins GPR:$Rn, GPR:$Rm, pred:$p, cc_out:$s),
3637 (SMLAL GPR:$RdLo, GPR:$RdHi, GPR:$Rn, GPR:$Rm, pred:$p, cc_out:$s)>,
3638 Requires<[IsARM, NoV6]>;
3639 def UMLALv5 : ARMPseudoExpand<(outs GPR:$RdLo, GPR:$RdHi),
3640 (ins GPR:$Rn, GPR:$Rm, pred:$p, cc_out:$s),
3642 (UMLAL GPR:$RdLo, GPR:$RdHi, GPR:$Rn, GPR:$Rm, pred:$p, cc_out:$s)>,
3643 Requires<[IsARM, NoV6]>;
3644 def UMAALv5 : ARMPseudoExpand<(outs GPR:$RdLo, GPR:$RdHi),
3645 (ins GPR:$Rn, GPR:$Rm, pred:$p),
3647 (UMAAL GPR:$RdLo, GPR:$RdHi, GPR:$Rn, GPR:$Rm, pred:$p)>,
3648 Requires<[IsARM, NoV6]>;
3651 } // neverHasSideEffects
3653 // Most significant word multiply
3654 def SMMUL : AMul2I <0b0111010, 0b0001, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm),
3655 IIC_iMUL32, "smmul", "\t$Rd, $Rn, $Rm",
3656 [(set GPR:$Rd, (mulhs GPR:$Rn, GPR:$Rm))]>,
3657 Requires<[IsARM, HasV6]> {
3658 let Inst{15-12} = 0b1111;
3661 def SMMULR : AMul2I <0b0111010, 0b0011, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm),
3662 IIC_iMUL32, "smmulr", "\t$Rd, $Rn, $Rm", []>,
3663 Requires<[IsARM, HasV6]> {
3664 let Inst{15-12} = 0b1111;
3667 def SMMLA : AMul2Ia <0b0111010, 0b0001, (outs GPR:$Rd),
3668 (ins GPR:$Rn, GPR:$Rm, GPR:$Ra),
3669 IIC_iMAC32, "smmla", "\t$Rd, $Rn, $Rm, $Ra",
3670 [(set GPR:$Rd, (add (mulhs GPR:$Rn, GPR:$Rm), GPR:$Ra))]>,
3671 Requires<[IsARM, HasV6]>;
3673 def SMMLAR : AMul2Ia <0b0111010, 0b0011, (outs GPR:$Rd),
3674 (ins GPR:$Rn, GPR:$Rm, GPR:$Ra),
3675 IIC_iMAC32, "smmlar", "\t$Rd, $Rn, $Rm, $Ra", []>,
3676 Requires<[IsARM, HasV6]>;
3678 def SMMLS : AMul2Ia <0b0111010, 0b1101, (outs GPR:$Rd),
3679 (ins GPR:$Rn, GPR:$Rm, GPR:$Ra),
3680 IIC_iMAC32, "smmls", "\t$Rd, $Rn, $Rm, $Ra",
3681 [(set GPR:$Rd, (sub GPR:$Ra, (mulhs GPR:$Rn, GPR:$Rm)))]>,
3682 Requires<[IsARM, HasV6]>;
3684 def SMMLSR : AMul2Ia <0b0111010, 0b1111, (outs GPR:$Rd),
3685 (ins GPR:$Rn, GPR:$Rm, GPR:$Ra),
3686 IIC_iMAC32, "smmlsr", "\t$Rd, $Rn, $Rm, $Ra", []>,
3687 Requires<[IsARM, HasV6]>;
3689 multiclass AI_smul<string opc, PatFrag opnode> {
3690 def BB : AMulxyI<0b0001011, 0b00, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm),
3691 IIC_iMUL16, !strconcat(opc, "bb"), "\t$Rd, $Rn, $Rm",
3692 [(set GPR:$Rd, (opnode (sext_inreg GPR:$Rn, i16),
3693 (sext_inreg GPR:$Rm, i16)))]>,
3694 Requires<[IsARM, HasV5TE]>;
3696 def BT : AMulxyI<0b0001011, 0b10, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm),
3697 IIC_iMUL16, !strconcat(opc, "bt"), "\t$Rd, $Rn, $Rm",
3698 [(set GPR:$Rd, (opnode (sext_inreg GPR:$Rn, i16),
3699 (sra GPR:$Rm, (i32 16))))]>,
3700 Requires<[IsARM, HasV5TE]>;
3702 def TB : AMulxyI<0b0001011, 0b01, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm),
3703 IIC_iMUL16, !strconcat(opc, "tb"), "\t$Rd, $Rn, $Rm",
3704 [(set GPR:$Rd, (opnode (sra GPR:$Rn, (i32 16)),
3705 (sext_inreg GPR:$Rm, i16)))]>,
3706 Requires<[IsARM, HasV5TE]>;
3708 def TT : AMulxyI<0b0001011, 0b11, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm),
3709 IIC_iMUL16, !strconcat(opc, "tt"), "\t$Rd, $Rn, $Rm",
3710 [(set GPR:$Rd, (opnode (sra GPR:$Rn, (i32 16)),
3711 (sra GPR:$Rm, (i32 16))))]>,
3712 Requires<[IsARM, HasV5TE]>;
3714 def WB : AMulxyI<0b0001001, 0b01, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm),
3715 IIC_iMUL16, !strconcat(opc, "wb"), "\t$Rd, $Rn, $Rm",
3716 [(set GPR:$Rd, (sra (opnode GPR:$Rn,
3717 (sext_inreg GPR:$Rm, i16)), (i32 16)))]>,
3718 Requires<[IsARM, HasV5TE]>;
3720 def WT : AMulxyI<0b0001001, 0b11, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm),
3721 IIC_iMUL16, !strconcat(opc, "wt"), "\t$Rd, $Rn, $Rm",
3722 [(set GPR:$Rd, (sra (opnode GPR:$Rn,
3723 (sra GPR:$Rm, (i32 16))), (i32 16)))]>,
3724 Requires<[IsARM, HasV5TE]>;
3728 multiclass AI_smla<string opc, PatFrag opnode> {
3729 let DecoderMethod = "DecodeSMLAInstruction" in {
3730 def BB : AMulxyIa<0b0001000, 0b00, (outs GPRnopc:$Rd),
3731 (ins GPRnopc:$Rn, GPRnopc:$Rm, GPR:$Ra),
3732 IIC_iMAC16, !strconcat(opc, "bb"), "\t$Rd, $Rn, $Rm, $Ra",
3733 [(set GPRnopc:$Rd, (add GPR:$Ra,
3734 (opnode (sext_inreg GPRnopc:$Rn, i16),
3735 (sext_inreg GPRnopc:$Rm, i16))))]>,
3736 Requires<[IsARM, HasV5TE]>;
3738 def BT : AMulxyIa<0b0001000, 0b10, (outs GPRnopc:$Rd),
3739 (ins GPRnopc:$Rn, GPRnopc:$Rm, GPR:$Ra),
3740 IIC_iMAC16, !strconcat(opc, "bt"), "\t$Rd, $Rn, $Rm, $Ra",
3742 (add GPR:$Ra, (opnode (sext_inreg GPRnopc:$Rn, i16),
3743 (sra GPRnopc:$Rm, (i32 16)))))]>,
3744 Requires<[IsARM, HasV5TE]>;
3746 def TB : AMulxyIa<0b0001000, 0b01, (outs GPRnopc:$Rd),
3747 (ins GPRnopc:$Rn, GPRnopc:$Rm, GPR:$Ra),
3748 IIC_iMAC16, !strconcat(opc, "tb"), "\t$Rd, $Rn, $Rm, $Ra",
3750 (add GPR:$Ra, (opnode (sra GPRnopc:$Rn, (i32 16)),
3751 (sext_inreg GPRnopc:$Rm, i16))))]>,
3752 Requires<[IsARM, HasV5TE]>;
3754 def TT : AMulxyIa<0b0001000, 0b11, (outs GPRnopc:$Rd),
3755 (ins GPRnopc:$Rn, GPRnopc:$Rm, GPR:$Ra),
3756 IIC_iMAC16, !strconcat(opc, "tt"), "\t$Rd, $Rn, $Rm, $Ra",
3758 (add GPR:$Ra, (opnode (sra GPRnopc:$Rn, (i32 16)),
3759 (sra GPRnopc:$Rm, (i32 16)))))]>,
3760 Requires<[IsARM, HasV5TE]>;
3762 def WB : AMulxyIa<0b0001001, 0b00, (outs GPRnopc:$Rd),
3763 (ins GPRnopc:$Rn, GPRnopc:$Rm, GPR:$Ra),
3764 IIC_iMAC16, !strconcat(opc, "wb"), "\t$Rd, $Rn, $Rm, $Ra",
3766 (add GPR:$Ra, (sra (opnode GPRnopc:$Rn,
3767 (sext_inreg GPRnopc:$Rm, i16)), (i32 16))))]>,
3768 Requires<[IsARM, HasV5TE]>;
3770 def WT : AMulxyIa<0b0001001, 0b10, (outs GPRnopc:$Rd),
3771 (ins GPRnopc:$Rn, GPRnopc:$Rm, GPR:$Ra),
3772 IIC_iMAC16, !strconcat(opc, "wt"), "\t$Rd, $Rn, $Rm, $Ra",
3774 (add GPR:$Ra, (sra (opnode GPRnopc:$Rn,
3775 (sra GPRnopc:$Rm, (i32 16))), (i32 16))))]>,
3776 Requires<[IsARM, HasV5TE]>;
3780 defm SMUL : AI_smul<"smul", BinOpFrag<(mul node:$LHS, node:$RHS)>>;
3781 defm SMLA : AI_smla<"smla", BinOpFrag<(mul node:$LHS, node:$RHS)>>;
3783 // Halfword multiply accumulate long: SMLAL<x><y>.
3784 def SMLALBB : AMulxyI64<0b0001010, 0b00, (outs GPRnopc:$RdLo, GPRnopc:$RdHi),
3785 (ins GPRnopc:$Rn, GPRnopc:$Rm),
3786 IIC_iMAC64, "smlalbb", "\t$RdLo, $RdHi, $Rn, $Rm", []>,
3787 Requires<[IsARM, HasV5TE]>;
3789 def SMLALBT : AMulxyI64<0b0001010, 0b10, (outs GPRnopc:$RdLo, GPRnopc:$RdHi),
3790 (ins GPRnopc:$Rn, GPRnopc:$Rm),
3791 IIC_iMAC64, "smlalbt", "\t$RdLo, $RdHi, $Rn, $Rm", []>,
3792 Requires<[IsARM, HasV5TE]>;
3794 def SMLALTB : AMulxyI64<0b0001010, 0b01, (outs GPRnopc:$RdLo, GPRnopc:$RdHi),
3795 (ins GPRnopc:$Rn, GPRnopc:$Rm),
3796 IIC_iMAC64, "smlaltb", "\t$RdLo, $RdHi, $Rn, $Rm", []>,
3797 Requires<[IsARM, HasV5TE]>;
3799 def SMLALTT : AMulxyI64<0b0001010, 0b11, (outs GPRnopc:$RdLo, GPRnopc:$RdHi),
3800 (ins GPRnopc:$Rn, GPRnopc:$Rm),
3801 IIC_iMAC64, "smlaltt", "\t$RdLo, $RdHi, $Rn, $Rm", []>,
3802 Requires<[IsARM, HasV5TE]>;
3804 // Helper class for AI_smld.
3805 class AMulDualIbase<bit long, bit sub, bit swap, dag oops, dag iops,
3806 InstrItinClass itin, string opc, string asm>
3807 : AI<oops, iops, MulFrm, itin, opc, asm, []>, Requires<[IsARM, HasV6]> {
3810 let Inst{27-23} = 0b01110;
3811 let Inst{22} = long;
3812 let Inst{21-20} = 0b00;
3813 let Inst{11-8} = Rm;
3820 class AMulDualI<bit long, bit sub, bit swap, dag oops, dag iops,
3821 InstrItinClass itin, string opc, string asm>
3822 : AMulDualIbase<long, sub, swap, oops, iops, itin, opc, asm> {
3824 let Inst{15-12} = 0b1111;
3825 let Inst{19-16} = Rd;
3827 class AMulDualIa<bit long, bit sub, bit swap, dag oops, dag iops,
3828 InstrItinClass itin, string opc, string asm>
3829 : AMulDualIbase<long, sub, swap, oops, iops, itin, opc, asm> {
3832 let Inst{19-16} = Rd;
3833 let Inst{15-12} = Ra;
3835 class AMulDualI64<bit long, bit sub, bit swap, dag oops, dag iops,
3836 InstrItinClass itin, string opc, string asm>
3837 : AMulDualIbase<long, sub, swap, oops, iops, itin, opc, asm> {
3840 let Inst{19-16} = RdHi;
3841 let Inst{15-12} = RdLo;
3844 multiclass AI_smld<bit sub, string opc> {
3846 def D : AMulDualIa<0, sub, 0, (outs GPRnopc:$Rd),
3847 (ins GPRnopc:$Rn, GPRnopc:$Rm, GPR:$Ra),
3848 NoItinerary, !strconcat(opc, "d"), "\t$Rd, $Rn, $Rm, $Ra">;
3850 def DX: AMulDualIa<0, sub, 1, (outs GPRnopc:$Rd),
3851 (ins GPRnopc:$Rn, GPRnopc:$Rm, GPR:$Ra),
3852 NoItinerary, !strconcat(opc, "dx"), "\t$Rd, $Rn, $Rm, $Ra">;
3854 def LD: AMulDualI64<1, sub, 0, (outs GPRnopc:$RdLo, GPRnopc:$RdHi),
3855 (ins GPRnopc:$Rn, GPRnopc:$Rm), NoItinerary,
3856 !strconcat(opc, "ld"), "\t$RdLo, $RdHi, $Rn, $Rm">;
3858 def LDX : AMulDualI64<1, sub, 1, (outs GPRnopc:$RdLo, GPRnopc:$RdHi),
3859 (ins GPRnopc:$Rn, GPRnopc:$Rm), NoItinerary,
3860 !strconcat(opc, "ldx"),"\t$RdLo, $RdHi, $Rn, $Rm">;
3864 defm SMLA : AI_smld<0, "smla">;
3865 defm SMLS : AI_smld<1, "smls">;
3867 multiclass AI_sdml<bit sub, string opc> {
3869 def D:AMulDualI<0, sub, 0, (outs GPRnopc:$Rd), (ins GPRnopc:$Rn, GPRnopc:$Rm),
3870 NoItinerary, !strconcat(opc, "d"), "\t$Rd, $Rn, $Rm">;
3871 def DX:AMulDualI<0, sub, 1, (outs GPRnopc:$Rd),(ins GPRnopc:$Rn, GPRnopc:$Rm),
3872 NoItinerary, !strconcat(opc, "dx"), "\t$Rd, $Rn, $Rm">;
3875 defm SMUA : AI_sdml<0, "smua">;
3876 defm SMUS : AI_sdml<1, "smus">;
3878 //===----------------------------------------------------------------------===//
3879 // Misc. Arithmetic Instructions.
3882 def CLZ : AMiscA1I<0b000010110, 0b0001, (outs GPR:$Rd), (ins GPR:$Rm),
3883 IIC_iUNAr, "clz", "\t$Rd, $Rm",
3884 [(set GPR:$Rd, (ctlz GPR:$Rm))]>, Requires<[IsARM, HasV5T]>;
3886 def RBIT : AMiscA1I<0b01101111, 0b0011, (outs GPR:$Rd), (ins GPR:$Rm),
3887 IIC_iUNAr, "rbit", "\t$Rd, $Rm",
3888 [(set GPR:$Rd, (ARMrbit GPR:$Rm))]>,
3889 Requires<[IsARM, HasV6T2]>;
3891 def REV : AMiscA1I<0b01101011, 0b0011, (outs GPR:$Rd), (ins GPR:$Rm),
3892 IIC_iUNAr, "rev", "\t$Rd, $Rm",
3893 [(set GPR:$Rd, (bswap GPR:$Rm))]>, Requires<[IsARM, HasV6]>;
3895 let AddedComplexity = 5 in
3896 def REV16 : AMiscA1I<0b01101011, 0b1011, (outs GPR:$Rd), (ins GPR:$Rm),
3897 IIC_iUNAr, "rev16", "\t$Rd, $Rm",
3898 [(set GPR:$Rd, (rotr (bswap GPR:$Rm), (i32 16)))]>,
3899 Requires<[IsARM, HasV6]>;
3901 let AddedComplexity = 5 in
3902 def REVSH : AMiscA1I<0b01101111, 0b1011, (outs GPR:$Rd), (ins GPR:$Rm),
3903 IIC_iUNAr, "revsh", "\t$Rd, $Rm",
3904 [(set GPR:$Rd, (sra (bswap GPR:$Rm), (i32 16)))]>,
3905 Requires<[IsARM, HasV6]>;
3907 def : ARMV6Pat<(or (sra (shl GPR:$Rm, (i32 24)), (i32 16)),
3908 (and (srl GPR:$Rm, (i32 8)), 0xFF)),
3911 def PKHBT : APKHI<0b01101000, 0, (outs GPRnopc:$Rd),
3912 (ins GPRnopc:$Rn, GPRnopc:$Rm, pkh_lsl_amt:$sh),
3913 IIC_iALUsi, "pkhbt", "\t$Rd, $Rn, $Rm$sh",
3914 [(set GPRnopc:$Rd, (or (and GPRnopc:$Rn, 0xFFFF),
3915 (and (shl GPRnopc:$Rm, pkh_lsl_amt:$sh),
3917 Requires<[IsARM, HasV6]>;
3919 // Alternate cases for PKHBT where identities eliminate some nodes.
3920 def : ARMV6Pat<(or (and GPRnopc:$Rn, 0xFFFF), (and GPRnopc:$Rm, 0xFFFF0000)),
3921 (PKHBT GPRnopc:$Rn, GPRnopc:$Rm, 0)>;
3922 def : ARMV6Pat<(or (and GPRnopc:$Rn, 0xFFFF), (shl GPRnopc:$Rm, imm16_31:$sh)),
3923 (PKHBT GPRnopc:$Rn, GPRnopc:$Rm, imm16_31:$sh)>;
3925 // Note: Shifts of 1-15 bits will be transformed to srl instead of sra and
3926 // will match the pattern below.
3927 def PKHTB : APKHI<0b01101000, 1, (outs GPRnopc:$Rd),
3928 (ins GPRnopc:$Rn, GPRnopc:$Rm, pkh_asr_amt:$sh),
3929 IIC_iBITsi, "pkhtb", "\t$Rd, $Rn, $Rm$sh",
3930 [(set GPRnopc:$Rd, (or (and GPRnopc:$Rn, 0xFFFF0000),
3931 (and (sra GPRnopc:$Rm, pkh_asr_amt:$sh),
3933 Requires<[IsARM, HasV6]>;
3935 // Alternate cases for PKHTB where identities eliminate some nodes. Note that
3936 // a shift amount of 0 is *not legal* here, it is PKHBT instead.
3937 def : ARMV6Pat<(or (and GPRnopc:$src1, 0xFFFF0000),
3938 (srl GPRnopc:$src2, imm16_31:$sh)),
3939 (PKHTB GPRnopc:$src1, GPRnopc:$src2, imm16_31:$sh)>;
3940 def : ARMV6Pat<(or (and GPRnopc:$src1, 0xFFFF0000),
3941 (and (srl GPRnopc:$src2, imm1_15:$sh), 0xFFFF)),
3942 (PKHTB GPRnopc:$src1, GPRnopc:$src2, imm1_15:$sh)>;
3944 //===----------------------------------------------------------------------===//
3945 // Comparison Instructions...
3948 defm CMP : AI1_cmp_irs<0b1010, "cmp",
3949 IIC_iCMPi, IIC_iCMPr, IIC_iCMPsr,
3950 BinOpFrag<(ARMcmp node:$LHS, node:$RHS)>>;
3952 // ARMcmpZ can re-use the above instruction definitions.
3953 def : ARMPat<(ARMcmpZ GPR:$src, so_imm:$imm),
3954 (CMPri GPR:$src, so_imm:$imm)>;
3955 def : ARMPat<(ARMcmpZ GPR:$src, GPR:$rhs),
3956 (CMPrr GPR:$src, GPR:$rhs)>;
3957 def : ARMPat<(ARMcmpZ GPR:$src, so_reg_imm:$rhs),
3958 (CMPrsi GPR:$src, so_reg_imm:$rhs)>;
3959 def : ARMPat<(ARMcmpZ GPR:$src, so_reg_reg:$rhs),
3960 (CMPrsr GPR:$src, so_reg_reg:$rhs)>;
3962 // FIXME: We have to be careful when using the CMN instruction and comparison
3963 // with 0. One would expect these two pieces of code should give identical
3979 // However, the CMN gives the *opposite* result when r1 is 0. This is because
3980 // the carry flag is set in the CMP case but not in the CMN case. In short, the
3981 // CMP instruction doesn't perform a truncate of the (logical) NOT of 0 plus the
3982 // value of r0 and the carry bit (because the "carry bit" parameter to
3983 // AddWithCarry is defined as 1 in this case, the carry flag will always be set
3984 // when r0 >= 0). The CMN instruction doesn't perform a NOT of 0 so there is
3985 // never a "carry" when this AddWithCarry is performed (because the "carry bit"
3986 // parameter to AddWithCarry is defined as 0).
3988 // When x is 0 and unsigned:
3992 // ~x + 1 = 0x1 0000 0000
3993 // (-x = 0) != (0x1 0000 0000 = ~x + 1)
3995 // Therefore, we should disable CMN when comparing against zero, until we can
3996 // limit when the CMN instruction is used (when we know that the RHS is not 0 or
3997 // when it's a comparison which doesn't look at the 'carry' flag).
3999 // (See the ARM docs for the "AddWithCarry" pseudo-code.)
4001 // This is related to <rdar://problem/7569620>.
4003 //defm CMN : AI1_cmp_irs<0b1011, "cmn",
4004 // BinOpFrag<(ARMcmp node:$LHS,(ineg node:$RHS))>>;
4006 // Note that TST/TEQ don't set all the same flags that CMP does!
4007 defm TST : AI1_cmp_irs<0b1000, "tst",
4008 IIC_iTSTi, IIC_iTSTr, IIC_iTSTsr,
4009 BinOpFrag<(ARMcmpZ (and_su node:$LHS, node:$RHS), 0)>, 1>;
4010 defm TEQ : AI1_cmp_irs<0b1001, "teq",
4011 IIC_iTSTi, IIC_iTSTr, IIC_iTSTsr,
4012 BinOpFrag<(ARMcmpZ (xor_su node:$LHS, node:$RHS), 0)>, 1>;
4014 defm CMNz : AI1_cmp_irs<0b1011, "cmn",
4015 IIC_iCMPi, IIC_iCMPr, IIC_iCMPsr,
4016 BinOpFrag<(ARMcmpZ node:$LHS,(ineg node:$RHS))>>;
4018 //def : ARMPat<(ARMcmp GPR:$src, so_imm_neg:$imm),
4019 // (CMNri GPR:$src, so_imm_neg:$imm)>;
4021 def : ARMPat<(ARMcmpZ GPR:$src, so_imm_neg:$imm),
4022 (CMNzri GPR:$src, so_imm_neg:$imm)>;
4024 // Pseudo i64 compares for some floating point compares.
4025 let usesCustomInserter = 1, isBranch = 1, isTerminator = 1,
4027 def BCCi64 : PseudoInst<(outs),
4028 (ins i32imm:$cc, GPR:$lhs1, GPR:$lhs2, GPR:$rhs1, GPR:$rhs2, brtarget:$dst),
4030 [(ARMBcci64 imm:$cc, GPR:$lhs1, GPR:$lhs2, GPR:$rhs1, GPR:$rhs2, bb:$dst)]>;
4032 def BCCZi64 : PseudoInst<(outs),
4033 (ins i32imm:$cc, GPR:$lhs1, GPR:$lhs2, brtarget:$dst), IIC_Br,
4034 [(ARMBcci64 imm:$cc, GPR:$lhs1, GPR:$lhs2, 0, 0, bb:$dst)]>;
4035 } // usesCustomInserter
4038 // Conditional moves
4039 // FIXME: should be able to write a pattern for ARMcmov, but can't use
4040 // a two-value operand where a dag node expects two operands. :(
4041 let neverHasSideEffects = 1 in {
4042 def MOVCCr : ARMPseudoInst<(outs GPR:$Rd), (ins GPR:$false, GPR:$Rm, pred:$p),
4044 [/*(set GPR:$Rd, (ARMcmov GPR:$false, GPR:$Rm, imm:$cc, CCR:$ccr))*/]>,
4045 RegConstraint<"$false = $Rd">;
4046 def MOVCCsi : ARMPseudoInst<(outs GPR:$Rd),
4047 (ins GPR:$false, so_reg_imm:$shift, pred:$p),
4049 [/*(set GPR:$Rd, (ARMcmov GPR:$false, so_reg_imm:$shift,
4050 imm:$cc, CCR:$ccr))*/]>,
4051 RegConstraint<"$false = $Rd">;
4052 def MOVCCsr : ARMPseudoInst<(outs GPR:$Rd),
4053 (ins GPR:$false, so_reg_reg:$shift, pred:$p),
4055 [/*(set GPR:$Rd, (ARMcmov GPR:$false, so_reg_reg:$shift,
4056 imm:$cc, CCR:$ccr))*/]>,
4057 RegConstraint<"$false = $Rd">;
4060 let isMoveImm = 1 in
4061 def MOVCCi16 : ARMPseudoInst<(outs GPR:$Rd),
4062 (ins GPR:$false, imm0_65535_expr:$imm, pred:$p),
4065 RegConstraint<"$false = $Rd">, Requires<[IsARM, HasV6T2]>;
4067 let isMoveImm = 1 in
4068 def MOVCCi : ARMPseudoInst<(outs GPR:$Rd),
4069 (ins GPR:$false, so_imm:$imm, pred:$p),
4071 [/*(set GPR:$Rd, (ARMcmov GPR:$false, so_imm:$imm, imm:$cc, CCR:$ccr))*/]>,
4072 RegConstraint<"$false = $Rd">;
4074 // Two instruction predicate mov immediate.
4075 let isMoveImm = 1 in
4076 def MOVCCi32imm : ARMPseudoInst<(outs GPR:$Rd),
4077 (ins GPR:$false, i32imm:$src, pred:$p),
4078 8, IIC_iCMOVix2, []>, RegConstraint<"$false = $Rd">;
4080 let isMoveImm = 1 in
4081 def MVNCCi : ARMPseudoInst<(outs GPR:$Rd),
4082 (ins GPR:$false, so_imm:$imm, pred:$p),
4084 [/*(set GPR:$Rd, (ARMcmov GPR:$false, so_imm_not:$imm, imm:$cc, CCR:$ccr))*/]>,
4085 RegConstraint<"$false = $Rd">;
4087 let isCodeGenOnly = 1 in {
4088 // Conditional instructions
4089 multiclass AsI1_bincc_irs<bits<4> opcod, string opc,
4090 InstrItinClass iii, InstrItinClass iir, InstrItinClass iis> {
4091 def ri : AsI1<opcod, (outs GPR:$Rd), (ins GPR:$Rn, so_imm:$imm), DPFrm,
4092 iii, opc, "\t$Rd, $Rn, $imm", []>,
4093 RegConstraint<"$Rn = $Rd"> {
4098 let Inst{19-16} = Rn;
4099 let Inst{15-12} = Rd;
4100 let Inst{11-0} = imm;
4102 def rr : AsI1<opcod, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm), DPFrm,
4103 iir, opc, "\t$Rd, $Rn, $Rm", []>,
4104 RegConstraint<"$Rn = $Rd"> {
4109 let Inst{19-16} = Rn;
4110 let Inst{15-12} = Rd;
4111 let Inst{11-4} = 0b00000000;
4115 def rsi : AsI1<opcod, (outs GPR:$Rd),
4116 (ins GPR:$Rn, so_reg_imm:$shift), DPSoRegImmFrm,
4117 iis, opc, "\t$Rd, $Rn, $shift", []>,
4118 RegConstraint<"$Rn = $Rd"> {
4123 let Inst{19-16} = Rn;
4124 let Inst{15-12} = Rd;
4125 let Inst{11-5} = shift{11-5};
4127 let Inst{3-0} = shift{3-0};
4130 def rsr : AsI1<opcod, (outs GPR:$Rd),
4131 (ins GPR:$Rn, so_reg_reg:$shift), DPSoRegRegFrm,
4132 iis, opc, "\t$Rd, $Rn, $shift", []>,
4133 RegConstraint<"$Rn = $Rd"> {
4138 let Inst{19-16} = Rn;
4139 let Inst{15-12} = Rd;
4140 let Inst{11-8} = shift{11-8};
4142 let Inst{6-5} = shift{6-5};
4144 let Inst{3-0} = shift{3-0};
4148 defm ANDCC : AsI1_bincc_irs<0b0000, "and", IIC_iBITi, IIC_iBITr, IIC_iBITsr>;
4149 defm ORRCC : AsI1_bincc_irs<0b1100, "orr", IIC_iBITi, IIC_iBITr, IIC_iBITsr>;
4150 defm EORCC : AsI1_bincc_irs<0b0001, "eor", IIC_iBITi, IIC_iBITr, IIC_iBITsr>;
4153 } // neverHasSideEffects
4155 //===----------------------------------------------------------------------===//
4156 // Atomic operations intrinsics
4159 def MemBarrierOptOperand : AsmOperandClass {
4160 let Name = "MemBarrierOpt";
4161 let ParserMethod = "parseMemBarrierOptOperand";
4163 def memb_opt : Operand<i32> {
4164 let PrintMethod = "printMemBOption";
4165 let ParserMatchClass = MemBarrierOptOperand;
4166 let DecoderMethod = "DecodeMemBarrierOption";
4169 // memory barriers protect the atomic sequences
4170 let hasSideEffects = 1 in {
4171 def DMB : AInoP<(outs), (ins memb_opt:$opt), MiscFrm, NoItinerary,
4172 "dmb", "\t$opt", [(ARMMemBarrier (i32 imm:$opt))]>,
4173 Requires<[IsARM, HasDB]> {
4175 let Inst{31-4} = 0xf57ff05;
4176 let Inst{3-0} = opt;
4180 def DSB : AInoP<(outs), (ins memb_opt:$opt), MiscFrm, NoItinerary,
4181 "dsb", "\t$opt", []>,
4182 Requires<[IsARM, HasDB]> {
4184 let Inst{31-4} = 0xf57ff04;
4185 let Inst{3-0} = opt;
4188 // ISB has only full system option
4189 def ISB : AInoP<(outs), (ins memb_opt:$opt), MiscFrm, NoItinerary,
4190 "isb", "\t$opt", []>,
4191 Requires<[IsARM, HasDB]> {
4193 let Inst{31-4} = 0xf57ff06;
4194 let Inst{3-0} = opt;
4197 // Pseudo isntruction that combines movs + predicated rsbmi
4198 // to implement integer ABS
4199 let usesCustomInserter = 1, Defs = [CPSR] in {
4200 def ABS : ARMPseudoInst<
4201 (outs GPR:$dst), (ins GPR:$src),
4202 8, NoItinerary, []>;
4205 let usesCustomInserter = 1 in {
4206 let Defs = [CPSR] in {
4207 def ATOMIC_LOAD_ADD_I8 : PseudoInst<
4208 (outs GPR:$dst), (ins GPR:$ptr, GPR:$incr), NoItinerary,
4209 [(set GPR:$dst, (atomic_load_add_8 GPR:$ptr, GPR:$incr))]>;
4210 def ATOMIC_LOAD_SUB_I8 : PseudoInst<
4211 (outs GPR:$dst), (ins GPR:$ptr, GPR:$incr), NoItinerary,
4212 [(set GPR:$dst, (atomic_load_sub_8 GPR:$ptr, GPR:$incr))]>;
4213 def ATOMIC_LOAD_AND_I8 : PseudoInst<
4214 (outs GPR:$dst), (ins GPR:$ptr, GPR:$incr), NoItinerary,
4215 [(set GPR:$dst, (atomic_load_and_8 GPR:$ptr, GPR:$incr))]>;
4216 def ATOMIC_LOAD_OR_I8 : PseudoInst<
4217 (outs GPR:$dst), (ins GPR:$ptr, GPR:$incr), NoItinerary,
4218 [(set GPR:$dst, (atomic_load_or_8 GPR:$ptr, GPR:$incr))]>;
4219 def ATOMIC_LOAD_XOR_I8 : PseudoInst<
4220 (outs GPR:$dst), (ins GPR:$ptr, GPR:$incr), NoItinerary,
4221 [(set GPR:$dst, (atomic_load_xor_8 GPR:$ptr, GPR:$incr))]>;
4222 def ATOMIC_LOAD_NAND_I8 : PseudoInst<
4223 (outs GPR:$dst), (ins GPR:$ptr, GPR:$incr), NoItinerary,
4224 [(set GPR:$dst, (atomic_load_nand_8 GPR:$ptr, GPR:$incr))]>;
4225 def ATOMIC_LOAD_MIN_I8 : PseudoInst<
4226 (outs GPR:$dst), (ins GPR:$ptr, GPR:$val), NoItinerary,
4227 [(set GPR:$dst, (atomic_load_min_8 GPR:$ptr, GPR:$val))]>;
4228 def ATOMIC_LOAD_MAX_I8 : PseudoInst<
4229 (outs GPR:$dst), (ins GPR:$ptr, GPR:$val), NoItinerary,
4230 [(set GPR:$dst, (atomic_load_max_8 GPR:$ptr, GPR:$val))]>;
4231 def ATOMIC_LOAD_UMIN_I8 : PseudoInst<
4232 (outs GPR:$dst), (ins GPR:$ptr, GPR:$val), NoItinerary,
4233 [(set GPR:$dst, (atomic_load_umin_8 GPR:$ptr, GPR:$val))]>;
4234 def ATOMIC_LOAD_UMAX_I8 : PseudoInst<
4235 (outs GPR:$dst), (ins GPR:$ptr, GPR:$val), NoItinerary,
4236 [(set GPR:$dst, (atomic_load_umax_8 GPR:$ptr, GPR:$val))]>;
4237 def ATOMIC_LOAD_ADD_I16 : PseudoInst<
4238 (outs GPR:$dst), (ins GPR:$ptr, GPR:$incr), NoItinerary,
4239 [(set GPR:$dst, (atomic_load_add_16 GPR:$ptr, GPR:$incr))]>;
4240 def ATOMIC_LOAD_SUB_I16 : PseudoInst<
4241 (outs GPR:$dst), (ins GPR:$ptr, GPR:$incr), NoItinerary,
4242 [(set GPR:$dst, (atomic_load_sub_16 GPR:$ptr, GPR:$incr))]>;
4243 def ATOMIC_LOAD_AND_I16 : PseudoInst<
4244 (outs GPR:$dst), (ins GPR:$ptr, GPR:$incr), NoItinerary,
4245 [(set GPR:$dst, (atomic_load_and_16 GPR:$ptr, GPR:$incr))]>;
4246 def ATOMIC_LOAD_OR_I16 : PseudoInst<
4247 (outs GPR:$dst), (ins GPR:$ptr, GPR:$incr), NoItinerary,
4248 [(set GPR:$dst, (atomic_load_or_16 GPR:$ptr, GPR:$incr))]>;
4249 def ATOMIC_LOAD_XOR_I16 : PseudoInst<
4250 (outs GPR:$dst), (ins GPR:$ptr, GPR:$incr), NoItinerary,
4251 [(set GPR:$dst, (atomic_load_xor_16 GPR:$ptr, GPR:$incr))]>;
4252 def ATOMIC_LOAD_NAND_I16 : PseudoInst<
4253 (outs GPR:$dst), (ins GPR:$ptr, GPR:$incr), NoItinerary,
4254 [(set GPR:$dst, (atomic_load_nand_16 GPR:$ptr, GPR:$incr))]>;
4255 def ATOMIC_LOAD_MIN_I16 : PseudoInst<
4256 (outs GPR:$dst), (ins GPR:$ptr, GPR:$val), NoItinerary,
4257 [(set GPR:$dst, (atomic_load_min_16 GPR:$ptr, GPR:$val))]>;
4258 def ATOMIC_LOAD_MAX_I16 : PseudoInst<
4259 (outs GPR:$dst), (ins GPR:$ptr, GPR:$val), NoItinerary,
4260 [(set GPR:$dst, (atomic_load_max_16 GPR:$ptr, GPR:$val))]>;
4261 def ATOMIC_LOAD_UMIN_I16 : PseudoInst<
4262 (outs GPR:$dst), (ins GPR:$ptr, GPR:$val), NoItinerary,
4263 [(set GPR:$dst, (atomic_load_umin_16 GPR:$ptr, GPR:$val))]>;
4264 def ATOMIC_LOAD_UMAX_I16 : PseudoInst<
4265 (outs GPR:$dst), (ins GPR:$ptr, GPR:$val), NoItinerary,
4266 [(set GPR:$dst, (atomic_load_umax_16 GPR:$ptr, GPR:$val))]>;
4267 def ATOMIC_LOAD_ADD_I32 : PseudoInst<
4268 (outs GPR:$dst), (ins GPR:$ptr, GPR:$incr), NoItinerary,
4269 [(set GPR:$dst, (atomic_load_add_32 GPR:$ptr, GPR:$incr))]>;
4270 def ATOMIC_LOAD_SUB_I32 : PseudoInst<
4271 (outs GPR:$dst), (ins GPR:$ptr, GPR:$incr), NoItinerary,
4272 [(set GPR:$dst, (atomic_load_sub_32 GPR:$ptr, GPR:$incr))]>;
4273 def ATOMIC_LOAD_AND_I32 : PseudoInst<
4274 (outs GPR:$dst), (ins GPR:$ptr, GPR:$incr), NoItinerary,
4275 [(set GPR:$dst, (atomic_load_and_32 GPR:$ptr, GPR:$incr))]>;
4276 def ATOMIC_LOAD_OR_I32 : PseudoInst<
4277 (outs GPR:$dst), (ins GPR:$ptr, GPR:$incr), NoItinerary,
4278 [(set GPR:$dst, (atomic_load_or_32 GPR:$ptr, GPR:$incr))]>;
4279 def ATOMIC_LOAD_XOR_I32 : PseudoInst<
4280 (outs GPR:$dst), (ins GPR:$ptr, GPR:$incr), NoItinerary,
4281 [(set GPR:$dst, (atomic_load_xor_32 GPR:$ptr, GPR:$incr))]>;
4282 def ATOMIC_LOAD_NAND_I32 : PseudoInst<
4283 (outs GPR:$dst), (ins GPR:$ptr, GPR:$incr), NoItinerary,
4284 [(set GPR:$dst, (atomic_load_nand_32 GPR:$ptr, GPR:$incr))]>;
4285 def ATOMIC_LOAD_MIN_I32 : PseudoInst<
4286 (outs GPR:$dst), (ins GPR:$ptr, GPR:$val), NoItinerary,
4287 [(set GPR:$dst, (atomic_load_min_32 GPR:$ptr, GPR:$val))]>;
4288 def ATOMIC_LOAD_MAX_I32 : PseudoInst<
4289 (outs GPR:$dst), (ins GPR:$ptr, GPR:$val), NoItinerary,
4290 [(set GPR:$dst, (atomic_load_max_32 GPR:$ptr, GPR:$val))]>;
4291 def ATOMIC_LOAD_UMIN_I32 : PseudoInst<
4292 (outs GPR:$dst), (ins GPR:$ptr, GPR:$val), NoItinerary,
4293 [(set GPR:$dst, (atomic_load_umin_32 GPR:$ptr, GPR:$val))]>;
4294 def ATOMIC_LOAD_UMAX_I32 : PseudoInst<
4295 (outs GPR:$dst), (ins GPR:$ptr, GPR:$val), NoItinerary,
4296 [(set GPR:$dst, (atomic_load_umax_32 GPR:$ptr, GPR:$val))]>;
4298 def ATOMIC_SWAP_I8 : PseudoInst<
4299 (outs GPR:$dst), (ins GPR:$ptr, GPR:$new), NoItinerary,
4300 [(set GPR:$dst, (atomic_swap_8 GPR:$ptr, GPR:$new))]>;
4301 def ATOMIC_SWAP_I16 : PseudoInst<
4302 (outs GPR:$dst), (ins GPR:$ptr, GPR:$new), NoItinerary,
4303 [(set GPR:$dst, (atomic_swap_16 GPR:$ptr, GPR:$new))]>;
4304 def ATOMIC_SWAP_I32 : PseudoInst<
4305 (outs GPR:$dst), (ins GPR:$ptr, GPR:$new), NoItinerary,
4306 [(set GPR:$dst, (atomic_swap_32 GPR:$ptr, GPR:$new))]>;
4308 def ATOMIC_CMP_SWAP_I8 : PseudoInst<
4309 (outs GPR:$dst), (ins GPR:$ptr, GPR:$old, GPR:$new), NoItinerary,
4310 [(set GPR:$dst, (atomic_cmp_swap_8 GPR:$ptr, GPR:$old, GPR:$new))]>;
4311 def ATOMIC_CMP_SWAP_I16 : PseudoInst<
4312 (outs GPR:$dst), (ins GPR:$ptr, GPR:$old, GPR:$new), NoItinerary,
4313 [(set GPR:$dst, (atomic_cmp_swap_16 GPR:$ptr, GPR:$old, GPR:$new))]>;
4314 def ATOMIC_CMP_SWAP_I32 : PseudoInst<
4315 (outs GPR:$dst), (ins GPR:$ptr, GPR:$old, GPR:$new), NoItinerary,
4316 [(set GPR:$dst, (atomic_cmp_swap_32 GPR:$ptr, GPR:$old, GPR:$new))]>;
4320 let mayLoad = 1 in {
4321 def LDREXB : AIldrex<0b10, (outs GPR:$Rt), (ins addr_offset_none:$addr),
4323 "ldrexb", "\t$Rt, $addr", []>;
4324 def LDREXH : AIldrex<0b11, (outs GPR:$Rt), (ins addr_offset_none:$addr),
4325 NoItinerary, "ldrexh", "\t$Rt, $addr", []>;
4326 def LDREX : AIldrex<0b00, (outs GPR:$Rt), (ins addr_offset_none:$addr),
4327 NoItinerary, "ldrex", "\t$Rt, $addr", []>;
4328 let hasExtraDefRegAllocReq = 1 in
4329 def LDREXD: AIldrex<0b01, (outs GPR:$Rt, GPR:$Rt2),(ins addr_offset_none:$addr),
4330 NoItinerary, "ldrexd", "\t$Rt, $Rt2, $addr", []> {
4331 let DecoderMethod = "DecodeDoubleRegLoad";
4335 let mayStore = 1, Constraints = "@earlyclobber $Rd" in {
4336 def STREXB: AIstrex<0b10, (outs GPR:$Rd), (ins GPR:$Rt, addr_offset_none:$addr),
4337 NoItinerary, "strexb", "\t$Rd, $Rt, $addr", []>;
4338 def STREXH: AIstrex<0b11, (outs GPR:$Rd), (ins GPR:$Rt, addr_offset_none:$addr),
4339 NoItinerary, "strexh", "\t$Rd, $Rt, $addr", []>;
4340 def STREX : AIstrex<0b00, (outs GPR:$Rd), (ins GPR:$Rt, addr_offset_none:$addr),
4341 NoItinerary, "strex", "\t$Rd, $Rt, $addr", []>;
4342 let hasExtraSrcRegAllocReq = 1 in
4343 def STREXD : AIstrex<0b01, (outs GPR:$Rd),
4344 (ins GPR:$Rt, GPR:$Rt2, addr_offset_none:$addr),
4345 NoItinerary, "strexd", "\t$Rd, $Rt, $Rt2, $addr", []> {
4346 let DecoderMethod = "DecodeDoubleRegStore";
4351 def CLREX : AXI<(outs), (ins), MiscFrm, NoItinerary, "clrex", []>,
4352 Requires<[IsARM, HasV7]> {
4353 let Inst{31-0} = 0b11110101011111111111000000011111;
4356 // SWP/SWPB are deprecated in V6/V7.
4357 let mayLoad = 1, mayStore = 1 in {
4358 def SWP : AIswp<0, (outs GPR:$Rt), (ins GPR:$Rt2, addr_offset_none:$addr),
4360 def SWPB: AIswp<1, (outs GPR:$Rt), (ins GPR:$Rt2, addr_offset_none:$addr),
4364 //===----------------------------------------------------------------------===//
4365 // Coprocessor Instructions.
4368 def CDP : ABI<0b1110, (outs), (ins p_imm:$cop, imm0_15:$opc1,
4369 c_imm:$CRd, c_imm:$CRn, c_imm:$CRm, imm0_7:$opc2),
4370 NoItinerary, "cdp", "\t$cop, $opc1, $CRd, $CRn, $CRm, $opc2",
4371 [(int_arm_cdp imm:$cop, imm:$opc1, imm:$CRd, imm:$CRn,
4372 imm:$CRm, imm:$opc2)]> {
4380 let Inst{3-0} = CRm;
4382 let Inst{7-5} = opc2;
4383 let Inst{11-8} = cop;
4384 let Inst{15-12} = CRd;
4385 let Inst{19-16} = CRn;
4386 let Inst{23-20} = opc1;
4389 def CDP2 : ABXI<0b1110, (outs), (ins p_imm:$cop, imm0_15:$opc1,
4390 c_imm:$CRd, c_imm:$CRn, c_imm:$CRm, imm0_7:$opc2),
4391 NoItinerary, "cdp2\t$cop, $opc1, $CRd, $CRn, $CRm, $opc2",
4392 [(int_arm_cdp2 imm:$cop, imm:$opc1, imm:$CRd, imm:$CRn,
4393 imm:$CRm, imm:$opc2)]> {
4394 let Inst{31-28} = 0b1111;
4402 let Inst{3-0} = CRm;
4404 let Inst{7-5} = opc2;
4405 let Inst{11-8} = cop;
4406 let Inst{15-12} = CRd;
4407 let Inst{19-16} = CRn;
4408 let Inst{23-20} = opc1;
4411 class ACI<dag oops, dag iops, string opc, string asm,
4412 IndexMode im = IndexModeNone>
4413 : I<oops, iops, AddrModeNone, 4, im, BrFrm, NoItinerary,
4415 let Inst{27-25} = 0b110;
4417 class ACInoP<dag oops, dag iops, string opc, string asm,
4418 IndexMode im = IndexModeNone>
4419 : InoP<oops, iops, AddrModeNone, 4, im, BrFrm, NoItinerary,
4421 let Inst{31-28} = 0b1111;
4422 let Inst{27-25} = 0b110;
4424 multiclass LdStCop<bit load, bit Dbit, string asm> {
4425 def _OFFSET : ACI<(outs), (ins p_imm:$cop, c_imm:$CRd, addrmode5:$addr),
4426 asm, "\t$cop, $CRd, $addr"> {
4430 let Inst{24} = 1; // P = 1
4431 let Inst{23} = addr{8};
4432 let Inst{22} = Dbit;
4433 let Inst{21} = 0; // W = 0
4434 let Inst{20} = load;
4435 let Inst{19-16} = addr{12-9};
4436 let Inst{15-12} = CRd;
4437 let Inst{11-8} = cop;
4438 let Inst{7-0} = addr{7-0};
4439 let DecoderMethod = "DecodeCopMemInstruction";
4441 def _PRE : ACI<(outs), (ins p_imm:$cop, c_imm:$CRd, addrmode5:$addr),
4442 asm, "\t$cop, $CRd, $addr!", IndexModePre> {
4446 let Inst{24} = 1; // P = 1
4447 let Inst{23} = addr{8};
4448 let Inst{22} = Dbit;
4449 let Inst{21} = 1; // W = 1
4450 let Inst{20} = load;
4451 let Inst{19-16} = addr{12-9};
4452 let Inst{15-12} = CRd;
4453 let Inst{11-8} = cop;
4454 let Inst{7-0} = addr{7-0};
4455 let DecoderMethod = "DecodeCopMemInstruction";
4457 def _POST: ACI<(outs), (ins p_imm:$cop, c_imm:$CRd, addr_offset_none:$addr,
4458 postidx_imm8s4:$offset),
4459 asm, "\t$cop, $CRd, $addr, $offset", IndexModePost> {
4464 let Inst{24} = 0; // P = 0
4465 let Inst{23} = offset{8};
4466 let Inst{22} = Dbit;
4467 let Inst{21} = 1; // W = 1
4468 let Inst{20} = load;
4469 let Inst{19-16} = addr;
4470 let Inst{15-12} = CRd;
4471 let Inst{11-8} = cop;
4472 let Inst{7-0} = offset{7-0};
4473 let DecoderMethod = "DecodeCopMemInstruction";
4475 def _OPTION : ACI<(outs),
4476 (ins p_imm:$cop, c_imm:$CRd, addr_offset_none:$addr,
4477 coproc_option_imm:$option),
4478 asm, "\t$cop, $CRd, $addr, $option"> {
4483 let Inst{24} = 0; // P = 0
4484 let Inst{23} = 1; // U = 1
4485 let Inst{22} = Dbit;
4486 let Inst{21} = 0; // W = 0
4487 let Inst{20} = load;
4488 let Inst{19-16} = addr;
4489 let Inst{15-12} = CRd;
4490 let Inst{11-8} = cop;
4491 let Inst{7-0} = option;
4492 let DecoderMethod = "DecodeCopMemInstruction";
4495 multiclass LdSt2Cop<bit load, bit Dbit, string asm> {
4496 def _OFFSET : ACInoP<(outs), (ins p_imm:$cop, c_imm:$CRd, addrmode5:$addr),
4497 asm, "\t$cop, $CRd, $addr"> {
4501 let Inst{24} = 1; // P = 1
4502 let Inst{23} = addr{8};
4503 let Inst{22} = Dbit;
4504 let Inst{21} = 0; // W = 0
4505 let Inst{20} = load;
4506 let Inst{19-16} = addr{12-9};
4507 let Inst{15-12} = CRd;
4508 let Inst{11-8} = cop;
4509 let Inst{7-0} = addr{7-0};
4510 let DecoderMethod = "DecodeCopMemInstruction";
4512 def _PRE : ACInoP<(outs), (ins p_imm:$cop, c_imm:$CRd, addrmode5:$addr),
4513 asm, "\t$cop, $CRd, $addr!", IndexModePre> {
4517 let Inst{24} = 1; // P = 1
4518 let Inst{23} = addr{8};
4519 let Inst{22} = Dbit;
4520 let Inst{21} = 1; // W = 1
4521 let Inst{20} = load;
4522 let Inst{19-16} = addr{12-9};
4523 let Inst{15-12} = CRd;
4524 let Inst{11-8} = cop;
4525 let Inst{7-0} = addr{7-0};
4526 let DecoderMethod = "DecodeCopMemInstruction";
4528 def _POST: ACInoP<(outs), (ins p_imm:$cop, c_imm:$CRd, addr_offset_none:$addr,
4529 postidx_imm8s4:$offset),
4530 asm, "\t$cop, $CRd, $addr, $offset", IndexModePost> {
4535 let Inst{24} = 0; // P = 0
4536 let Inst{23} = offset{8};
4537 let Inst{22} = Dbit;
4538 let Inst{21} = 1; // W = 1
4539 let Inst{20} = load;
4540 let Inst{19-16} = addr;
4541 let Inst{15-12} = CRd;
4542 let Inst{11-8} = cop;
4543 let Inst{7-0} = offset{7-0};
4544 let DecoderMethod = "DecodeCopMemInstruction";
4546 def _OPTION : ACInoP<(outs),
4547 (ins p_imm:$cop, c_imm:$CRd, addr_offset_none:$addr,
4548 coproc_option_imm:$option),
4549 asm, "\t$cop, $CRd, $addr, $option"> {
4554 let Inst{24} = 0; // P = 0
4555 let Inst{23} = 1; // U = 1
4556 let Inst{22} = Dbit;
4557 let Inst{21} = 0; // W = 0
4558 let Inst{20} = load;
4559 let Inst{19-16} = addr;
4560 let Inst{15-12} = CRd;
4561 let Inst{11-8} = cop;
4562 let Inst{7-0} = option;
4563 let DecoderMethod = "DecodeCopMemInstruction";
4567 defm LDC : LdStCop <1, 0, "ldc">;
4568 defm LDCL : LdStCop <1, 1, "ldcl">;
4569 defm STC : LdStCop <0, 0, "stc">;
4570 defm STCL : LdStCop <0, 1, "stcl">;
4571 defm LDC2 : LdSt2Cop<1, 0, "ldc2">;
4572 defm LDC2L : LdSt2Cop<1, 1, "ldc2l">;
4573 defm STC2 : LdSt2Cop<0, 0, "stc2">;
4574 defm STC2L : LdSt2Cop<0, 1, "stc2l">;
4576 //===----------------------------------------------------------------------===//
4577 // Move between coprocessor and ARM core register.
4580 class MovRCopro<string opc, bit direction, dag oops, dag iops,
4582 : ABI<0b1110, oops, iops, NoItinerary, opc,
4583 "\t$cop, $opc1, $Rt, $CRn, $CRm, $opc2", pattern> {
4584 let Inst{20} = direction;
4594 let Inst{15-12} = Rt;
4595 let Inst{11-8} = cop;
4596 let Inst{23-21} = opc1;
4597 let Inst{7-5} = opc2;
4598 let Inst{3-0} = CRm;
4599 let Inst{19-16} = CRn;
4602 def MCR : MovRCopro<"mcr", 0 /* from ARM core register to coprocessor */,
4604 (ins p_imm:$cop, imm0_7:$opc1, GPR:$Rt, c_imm:$CRn,
4605 c_imm:$CRm, imm0_7:$opc2),
4606 [(int_arm_mcr imm:$cop, imm:$opc1, GPR:$Rt, imm:$CRn,
4607 imm:$CRm, imm:$opc2)]>;
4608 def MRC : MovRCopro<"mrc", 1 /* from coprocessor to ARM core register */,
4610 (ins p_imm:$cop, imm0_7:$opc1, c_imm:$CRn, c_imm:$CRm,
4613 def : ARMPat<(int_arm_mrc imm:$cop, imm:$opc1, imm:$CRn, imm:$CRm, imm:$opc2),
4614 (MRC imm:$cop, imm:$opc1, imm:$CRn, imm:$CRm, imm:$opc2)>;
4616 class MovRCopro2<string opc, bit direction, dag oops, dag iops,
4618 : ABXI<0b1110, oops, iops, NoItinerary,
4619 !strconcat(opc, "\t$cop, $opc1, $Rt, $CRn, $CRm, $opc2"), pattern> {
4620 let Inst{31-28} = 0b1111;
4621 let Inst{20} = direction;
4631 let Inst{15-12} = Rt;
4632 let Inst{11-8} = cop;
4633 let Inst{23-21} = opc1;
4634 let Inst{7-5} = opc2;
4635 let Inst{3-0} = CRm;
4636 let Inst{19-16} = CRn;
4639 def MCR2 : MovRCopro2<"mcr2", 0 /* from ARM core register to coprocessor */,
4641 (ins p_imm:$cop, imm0_7:$opc1, GPR:$Rt, c_imm:$CRn,
4642 c_imm:$CRm, imm0_7:$opc2),
4643 [(int_arm_mcr2 imm:$cop, imm:$opc1, GPR:$Rt, imm:$CRn,
4644 imm:$CRm, imm:$opc2)]>;
4645 def MRC2 : MovRCopro2<"mrc2", 1 /* from coprocessor to ARM core register */,
4647 (ins p_imm:$cop, imm0_7:$opc1, c_imm:$CRn, c_imm:$CRm,
4650 def : ARMV5TPat<(int_arm_mrc2 imm:$cop, imm:$opc1, imm:$CRn,
4651 imm:$CRm, imm:$opc2),
4652 (MRC2 imm:$cop, imm:$opc1, imm:$CRn, imm:$CRm, imm:$opc2)>;
4654 class MovRRCopro<string opc, bit direction, list<dag> pattern = []>
4655 : ABI<0b1100, (outs), (ins p_imm:$cop, imm0_15:$opc1,
4656 GPR:$Rt, GPR:$Rt2, c_imm:$CRm),
4657 NoItinerary, opc, "\t$cop, $opc1, $Rt, $Rt2, $CRm", pattern> {
4658 let Inst{23-21} = 0b010;
4659 let Inst{20} = direction;
4667 let Inst{15-12} = Rt;
4668 let Inst{19-16} = Rt2;
4669 let Inst{11-8} = cop;
4670 let Inst{7-4} = opc1;
4671 let Inst{3-0} = CRm;
4674 def MCRR : MovRRCopro<"mcrr", 0 /* from ARM core register to coprocessor */,
4675 [(int_arm_mcrr imm:$cop, imm:$opc1, GPR:$Rt, GPR:$Rt2,
4677 def MRRC : MovRRCopro<"mrrc", 1 /* from coprocessor to ARM core register */>;
4679 class MovRRCopro2<string opc, bit direction, list<dag> pattern = []>
4680 : ABXI<0b1100, (outs), (ins p_imm:$cop, imm0_15:$opc1,
4681 GPR:$Rt, GPR:$Rt2, c_imm:$CRm), NoItinerary,
4682 !strconcat(opc, "\t$cop, $opc1, $Rt, $Rt2, $CRm"), pattern> {
4683 let Inst{31-28} = 0b1111;
4684 let Inst{23-21} = 0b010;
4685 let Inst{20} = direction;
4693 let Inst{15-12} = Rt;
4694 let Inst{19-16} = Rt2;
4695 let Inst{11-8} = cop;
4696 let Inst{7-4} = opc1;
4697 let Inst{3-0} = CRm;
4700 def MCRR2 : MovRRCopro2<"mcrr2", 0 /* from ARM core register to coprocessor */,
4701 [(int_arm_mcrr2 imm:$cop, imm:$opc1, GPR:$Rt, GPR:$Rt2,
4703 def MRRC2 : MovRRCopro2<"mrrc2", 1 /* from coprocessor to ARM core register */>;
4705 //===----------------------------------------------------------------------===//
4706 // Move between special register and ARM core register
4709 // Move to ARM core register from Special Register
4710 def MRS : ABI<0b0001, (outs GPR:$Rd), (ins), NoItinerary,
4711 "mrs", "\t$Rd, apsr", []> {
4713 let Inst{23-16} = 0b00001111;
4714 let Inst{15-12} = Rd;
4715 let Inst{7-4} = 0b0000;
4718 def : InstAlias<"mrs${p} $Rd, cpsr", (MRS GPR:$Rd, pred:$p)>, Requires<[IsARM]>;
4720 def MRSsys : ABI<0b0001, (outs GPR:$Rd), (ins), NoItinerary,
4721 "mrs", "\t$Rd, spsr", []> {
4723 let Inst{23-16} = 0b01001111;
4724 let Inst{15-12} = Rd;
4725 let Inst{7-4} = 0b0000;
4728 // Move from ARM core register to Special Register
4730 // No need to have both system and application versions, the encodings are the
4731 // same and the assembly parser has no way to distinguish between them. The mask
4732 // operand contains the special register (R Bit) in bit 4 and bits 3-0 contains
4733 // the mask with the fields to be accessed in the special register.
4734 def MSR : ABI<0b0001, (outs), (ins msr_mask:$mask, GPR:$Rn), NoItinerary,
4735 "msr", "\t$mask, $Rn", []> {
4740 let Inst{22} = mask{4}; // R bit
4741 let Inst{21-20} = 0b10;
4742 let Inst{19-16} = mask{3-0};
4743 let Inst{15-12} = 0b1111;
4744 let Inst{11-4} = 0b00000000;
4748 def MSRi : ABI<0b0011, (outs), (ins msr_mask:$mask, so_imm:$a), NoItinerary,
4749 "msr", "\t$mask, $a", []> {
4754 let Inst{22} = mask{4}; // R bit
4755 let Inst{21-20} = 0b10;
4756 let Inst{19-16} = mask{3-0};
4757 let Inst{15-12} = 0b1111;
4761 //===----------------------------------------------------------------------===//
4765 // __aeabi_read_tp preserves the registers r1-r3.
4766 // This is a pseudo inst so that we can get the encoding right,
4767 // complete with fixup for the aeabi_read_tp function.
4769 Defs = [R0, R12, LR, CPSR], Uses = [SP] in {
4770 def TPsoft : PseudoInst<(outs), (ins), IIC_Br,
4771 [(set R0, ARMthread_pointer)]>;
4774 //===----------------------------------------------------------------------===//
4775 // SJLJ Exception handling intrinsics
4776 // eh_sjlj_setjmp() is an instruction sequence to store the return
4777 // address and save #0 in R0 for the non-longjmp case.
4778 // Since by its nature we may be coming from some other function to get
4779 // here, and we're using the stack frame for the containing function to
4780 // save/restore registers, we can't keep anything live in regs across
4781 // the eh_sjlj_setjmp(), else it will almost certainly have been tromped upon
4782 // when we get here from a longjmp(). We force everything out of registers
4783 // except for our own input by listing the relevant registers in Defs. By
4784 // doing so, we also cause the prologue/epilogue code to actively preserve
4785 // all of the callee-saved resgisters, which is exactly what we want.
4786 // A constant value is passed in $val, and we use the location as a scratch.
4788 // These are pseudo-instructions and are lowered to individual MC-insts, so
4789 // no encoding information is necessary.
4791 [ R0, R1, R2, R3, R4, R5, R6, R7, R8, R9, R10, R11, R12, LR, CPSR,
4792 Q0, Q1, Q2, Q3, Q4, Q5, Q6, Q7, Q8, Q9, Q10, Q11, Q12, Q13, Q14, Q15 ],
4793 hasSideEffects = 1, isBarrier = 1, usesCustomInserter = 1 in {
4794 def Int_eh_sjlj_setjmp : PseudoInst<(outs), (ins GPR:$src, GPR:$val),
4796 [(set R0, (ARMeh_sjlj_setjmp GPR:$src, GPR:$val))]>,
4797 Requires<[IsARM, HasVFP2]>;
4801 [ R0, R1, R2, R3, R4, R5, R6, R7, R8, R9, R10, R11, R12, LR, CPSR ],
4802 hasSideEffects = 1, isBarrier = 1, usesCustomInserter = 1 in {
4803 def Int_eh_sjlj_setjmp_nofp : PseudoInst<(outs), (ins GPR:$src, GPR:$val),
4805 [(set R0, (ARMeh_sjlj_setjmp GPR:$src, GPR:$val))]>,
4806 Requires<[IsARM, NoVFP]>;
4809 // FIXME: Non-IOS version(s)
4810 let isBarrier = 1, hasSideEffects = 1, isTerminator = 1,
4811 Defs = [ R7, LR, SP ] in {
4812 def Int_eh_sjlj_longjmp : PseudoInst<(outs), (ins GPR:$src, GPR:$scratch),
4814 [(ARMeh_sjlj_longjmp GPR:$src, GPR:$scratch)]>,
4815 Requires<[IsARM, IsIOS]>;
4818 // eh.sjlj.dispatchsetup pseudo-instructions.
4819 // These pseudos are used for both ARM and Thumb2. Any differences are
4820 // handled when the pseudo is expanded (which happens before any passes
4821 // that need the instruction size).
4823 [ R0, R1, R2, R3, R4, R5, R6, R7, R8, R9, R10, R11, R12, LR, CPSR,
4824 Q0, Q1, Q2, Q3, Q4, Q5, Q6, Q7, Q8, Q9, Q10, Q11, Q12, Q13, Q14, Q15 ],
4826 def Int_eh_sjlj_dispatchsetup : PseudoInst<(outs), (ins), NoItinerary, []>;
4829 [ R0, R1, R2, R3, R4, R5, R6, R7, R8, R9, R10, R11, R12, LR, CPSR ],
4831 def Int_eh_sjlj_dispatchsetup_nofp : PseudoInst<(outs), (ins), NoItinerary, []>;
4834 //===----------------------------------------------------------------------===//
4835 // Non-Instruction Patterns
4838 // ARMv4 indirect branch using (MOVr PC, dst)
4839 let isBranch = 1, isTerminator = 1, isBarrier = 1, isIndirectBranch = 1 in
4840 def MOVPCRX : ARMPseudoExpand<(outs), (ins GPR:$dst),
4841 4, IIC_Br, [(brind GPR:$dst)],
4842 (MOVr PC, GPR:$dst, (ops 14, zero_reg), zero_reg)>,
4843 Requires<[IsARM, NoV4T]>;
4845 // Large immediate handling.
4847 // 32-bit immediate using two piece so_imms or movw + movt.
4848 // This is a single pseudo instruction, the benefit is that it can be remat'd
4849 // as a single unit instead of having to handle reg inputs.
4850 // FIXME: Remove this when we can do generalized remat.
4851 let isReMaterializable = 1, isMoveImm = 1 in
4852 def MOVi32imm : PseudoInst<(outs GPR:$dst), (ins i32imm:$src), IIC_iMOVix2,
4853 [(set GPR:$dst, (arm_i32imm:$src))]>,
4856 // Pseudo instruction that combines movw + movt + add pc (if PIC).
4857 // It also makes it possible to rematerialize the instructions.
4858 // FIXME: Remove this when we can do generalized remat and when machine licm
4859 // can properly the instructions.
4860 let isReMaterializable = 1 in {
4861 def MOV_ga_pcrel : PseudoInst<(outs GPR:$dst), (ins i32imm:$addr),
4863 [(set GPR:$dst, (ARMWrapperPIC tglobaladdr:$addr))]>,
4864 Requires<[IsARM, UseMovt]>;
4866 def MOV_ga_dyn : PseudoInst<(outs GPR:$dst), (ins i32imm:$addr),
4868 [(set GPR:$dst, (ARMWrapperDYN tglobaladdr:$addr))]>,
4869 Requires<[IsARM, UseMovt]>;
4871 let AddedComplexity = 10 in
4872 def MOV_ga_pcrel_ldr : PseudoInst<(outs GPR:$dst), (ins i32imm:$addr),
4874 [(set GPR:$dst, (load (ARMWrapperPIC tglobaladdr:$addr)))]>,
4875 Requires<[IsARM, UseMovt]>;
4876 } // isReMaterializable
4878 // ConstantPool, GlobalAddress, and JumpTable
4879 def : ARMPat<(ARMWrapper tglobaladdr :$dst), (LEApcrel tglobaladdr :$dst)>,
4880 Requires<[IsARM, DontUseMovt]>;
4881 def : ARMPat<(ARMWrapper tconstpool :$dst), (LEApcrel tconstpool :$dst)>;
4882 def : ARMPat<(ARMWrapper tglobaladdr :$dst), (MOVi32imm tglobaladdr :$dst)>,
4883 Requires<[IsARM, UseMovt]>;
4884 def : ARMPat<(ARMWrapperJT tjumptable:$dst, imm:$id),
4885 (LEApcrelJT tjumptable:$dst, imm:$id)>;
4887 // TODO: add,sub,and, 3-instr forms?
4890 def : ARMPat<(ARMtcret tcGPR:$dst),
4891 (TCRETURNri tcGPR:$dst)>, Requires<[IsIOS]>;
4893 def : ARMPat<(ARMtcret (i32 tglobaladdr:$dst)),
4894 (TCRETURNdi texternalsym:$dst)>, Requires<[IsIOS]>;
4896 def : ARMPat<(ARMtcret (i32 texternalsym:$dst)),
4897 (TCRETURNdi texternalsym:$dst)>, Requires<[IsIOS]>;
4899 def : ARMPat<(ARMtcret tcGPR:$dst),
4900 (TCRETURNriND tcGPR:$dst)>, Requires<[IsNotIOS]>;
4902 def : ARMPat<(ARMtcret (i32 tglobaladdr:$dst)),
4903 (TCRETURNdiND texternalsym:$dst)>, Requires<[IsNotIOS]>;
4905 def : ARMPat<(ARMtcret (i32 texternalsym:$dst)),
4906 (TCRETURNdiND texternalsym:$dst)>, Requires<[IsNotIOS]>;
4909 def : ARMPat<(ARMcall texternalsym:$func), (BL texternalsym:$func)>,
4910 Requires<[IsARM, IsNotIOS]>;
4911 def : ARMPat<(ARMcall texternalsym:$func), (BLr9 texternalsym:$func)>,
4912 Requires<[IsARM, IsIOS]>;
4913 def : ARMPat<(ARMcall_nolink texternalsym:$func),
4914 (BMOVPCB_CALL texternalsym:$func)>,
4915 Requires<[IsARM, IsNotIOS]>;
4916 def : ARMPat<(ARMcall_nolink texternalsym:$func),
4917 (BMOVPCBr9_CALL texternalsym:$func)>,
4918 Requires<[IsARM, IsIOS]>;
4920 // zextload i1 -> zextload i8
4921 def : ARMPat<(zextloadi1 addrmode_imm12:$addr), (LDRBi12 addrmode_imm12:$addr)>;
4922 def : ARMPat<(zextloadi1 ldst_so_reg:$addr), (LDRBrs ldst_so_reg:$addr)>;
4924 // extload -> zextload
4925 def : ARMPat<(extloadi1 addrmode_imm12:$addr), (LDRBi12 addrmode_imm12:$addr)>;
4926 def : ARMPat<(extloadi1 ldst_so_reg:$addr), (LDRBrs ldst_so_reg:$addr)>;
4927 def : ARMPat<(extloadi8 addrmode_imm12:$addr), (LDRBi12 addrmode_imm12:$addr)>;
4928 def : ARMPat<(extloadi8 ldst_so_reg:$addr), (LDRBrs ldst_so_reg:$addr)>;
4930 def : ARMPat<(extloadi16 addrmode3:$addr), (LDRH addrmode3:$addr)>;
4932 def : ARMPat<(extloadi8 addrmodepc:$addr), (PICLDRB addrmodepc:$addr)>;
4933 def : ARMPat<(extloadi16 addrmodepc:$addr), (PICLDRH addrmodepc:$addr)>;
4936 def : ARMV5TEPat<(mul (sra (shl GPR:$a, (i32 16)), (i32 16)),
4937 (sra (shl GPR:$b, (i32 16)), (i32 16))),
4938 (SMULBB GPR:$a, GPR:$b)>;
4939 def : ARMV5TEPat<(mul sext_16_node:$a, sext_16_node:$b),
4940 (SMULBB GPR:$a, GPR:$b)>;
4941 def : ARMV5TEPat<(mul (sra (shl GPR:$a, (i32 16)), (i32 16)),
4942 (sra GPR:$b, (i32 16))),
4943 (SMULBT GPR:$a, GPR:$b)>;
4944 def : ARMV5TEPat<(mul sext_16_node:$a, (sra GPR:$b, (i32 16))),
4945 (SMULBT GPR:$a, GPR:$b)>;
4946 def : ARMV5TEPat<(mul (sra GPR:$a, (i32 16)),
4947 (sra (shl GPR:$b, (i32 16)), (i32 16))),
4948 (SMULTB GPR:$a, GPR:$b)>;
4949 def : ARMV5TEPat<(mul (sra GPR:$a, (i32 16)), sext_16_node:$b),
4950 (SMULTB GPR:$a, GPR:$b)>;
4951 def : ARMV5TEPat<(sra (mul GPR:$a, (sra (shl GPR:$b, (i32 16)), (i32 16))),
4953 (SMULWB GPR:$a, GPR:$b)>;
4954 def : ARMV5TEPat<(sra (mul GPR:$a, sext_16_node:$b), (i32 16)),
4955 (SMULWB GPR:$a, GPR:$b)>;
4957 def : ARMV5TEPat<(add GPR:$acc,
4958 (mul (sra (shl GPR:$a, (i32 16)), (i32 16)),
4959 (sra (shl GPR:$b, (i32 16)), (i32 16)))),
4960 (SMLABB GPR:$a, GPR:$b, GPR:$acc)>;
4961 def : ARMV5TEPat<(add GPR:$acc,
4962 (mul sext_16_node:$a, sext_16_node:$b)),
4963 (SMLABB GPR:$a, GPR:$b, GPR:$acc)>;
4964 def : ARMV5TEPat<(add GPR:$acc,
4965 (mul (sra (shl GPR:$a, (i32 16)), (i32 16)),
4966 (sra GPR:$b, (i32 16)))),
4967 (SMLABT GPR:$a, GPR:$b, GPR:$acc)>;
4968 def : ARMV5TEPat<(add GPR:$acc,
4969 (mul sext_16_node:$a, (sra GPR:$b, (i32 16)))),
4970 (SMLABT GPR:$a, GPR:$b, GPR:$acc)>;
4971 def : ARMV5TEPat<(add GPR:$acc,
4972 (mul (sra GPR:$a, (i32 16)),
4973 (sra (shl GPR:$b, (i32 16)), (i32 16)))),
4974 (SMLATB GPR:$a, GPR:$b, GPR:$acc)>;
4975 def : ARMV5TEPat<(add GPR:$acc,
4976 (mul (sra GPR:$a, (i32 16)), sext_16_node:$b)),
4977 (SMLATB GPR:$a, GPR:$b, GPR:$acc)>;
4978 def : ARMV5TEPat<(add GPR:$acc,
4979 (sra (mul GPR:$a, (sra (shl GPR:$b, (i32 16)), (i32 16))),
4981 (SMLAWB GPR:$a, GPR:$b, GPR:$acc)>;
4982 def : ARMV5TEPat<(add GPR:$acc,
4983 (sra (mul GPR:$a, sext_16_node:$b), (i32 16))),
4984 (SMLAWB GPR:$a, GPR:$b, GPR:$acc)>;
4987 // Pre-v7 uses MCR for synchronization barriers.
4988 def : ARMPat<(ARMMemBarrierMCR GPR:$zero), (MCR 15, 0, GPR:$zero, 7, 10, 5)>,
4989 Requires<[IsARM, HasV6]>;
4991 // SXT/UXT with no rotate
4992 let AddedComplexity = 16 in {
4993 def : ARMV6Pat<(and GPR:$Src, 0x000000FF), (UXTB GPR:$Src, 0)>;
4994 def : ARMV6Pat<(and GPR:$Src, 0x0000FFFF), (UXTH GPR:$Src, 0)>;
4995 def : ARMV6Pat<(and GPR:$Src, 0x00FF00FF), (UXTB16 GPR:$Src, 0)>;
4996 def : ARMV6Pat<(add GPR:$Rn, (and GPR:$Rm, 0x00FF)),
4997 (UXTAB GPR:$Rn, GPR:$Rm, 0)>;
4998 def : ARMV6Pat<(add GPR:$Rn, (and GPR:$Rm, 0xFFFF)),
4999 (UXTAH GPR:$Rn, GPR:$Rm, 0)>;
5002 def : ARMV6Pat<(sext_inreg GPR:$Src, i8), (SXTB GPR:$Src, 0)>;
5003 def : ARMV6Pat<(sext_inreg GPR:$Src, i16), (SXTH GPR:$Src, 0)>;
5005 def : ARMV6Pat<(add GPR:$Rn, (sext_inreg GPRnopc:$Rm, i8)),
5006 (SXTAB GPR:$Rn, GPRnopc:$Rm, 0)>;
5007 def : ARMV6Pat<(add GPR:$Rn, (sext_inreg GPRnopc:$Rm, i16)),
5008 (SXTAH GPR:$Rn, GPRnopc:$Rm, 0)>;
5010 // Atomic load/store patterns
5011 def : ARMPat<(atomic_load_8 ldst_so_reg:$src),
5012 (LDRBrs ldst_so_reg:$src)>;
5013 def : ARMPat<(atomic_load_8 addrmode_imm12:$src),
5014 (LDRBi12 addrmode_imm12:$src)>;
5015 def : ARMPat<(atomic_load_16 addrmode3:$src),
5016 (LDRH addrmode3:$src)>;
5017 def : ARMPat<(atomic_load_32 ldst_so_reg:$src),
5018 (LDRrs ldst_so_reg:$src)>;
5019 def : ARMPat<(atomic_load_32 addrmode_imm12:$src),
5020 (LDRi12 addrmode_imm12:$src)>;
5021 def : ARMPat<(atomic_store_8 ldst_so_reg:$ptr, GPR:$val),
5022 (STRBrs GPR:$val, ldst_so_reg:$ptr)>;
5023 def : ARMPat<(atomic_store_8 addrmode_imm12:$ptr, GPR:$val),
5024 (STRBi12 GPR:$val, addrmode_imm12:$ptr)>;
5025 def : ARMPat<(atomic_store_16 addrmode3:$ptr, GPR:$val),
5026 (STRH GPR:$val, addrmode3:$ptr)>;
5027 def : ARMPat<(atomic_store_32 ldst_so_reg:$ptr, GPR:$val),
5028 (STRrs GPR:$val, ldst_so_reg:$ptr)>;
5029 def : ARMPat<(atomic_store_32 addrmode_imm12:$ptr, GPR:$val),
5030 (STRi12 GPR:$val, addrmode_imm12:$ptr)>;
5033 //===----------------------------------------------------------------------===//
5037 include "ARMInstrThumb.td"
5039 //===----------------------------------------------------------------------===//
5043 include "ARMInstrThumb2.td"
5045 //===----------------------------------------------------------------------===//
5046 // Floating Point Support
5049 include "ARMInstrVFP.td"
5051 //===----------------------------------------------------------------------===//
5052 // Advanced SIMD (NEON) Support
5055 include "ARMInstrNEON.td"
5057 //===----------------------------------------------------------------------===//
5058 // Assembler aliases
5062 def : InstAlias<"dmb", (DMB 0xf)>, Requires<[IsARM, HasDB]>;
5063 def : InstAlias<"dsb", (DSB 0xf)>, Requires<[IsARM, HasDB]>;
5064 def : InstAlias<"isb", (ISB 0xf)>, Requires<[IsARM, HasDB]>;
5066 // System instructions
5067 def : MnemonicAlias<"swi", "svc">;
5069 // Load / Store Multiple
5070 def : MnemonicAlias<"ldmfd", "ldm">;
5071 def : MnemonicAlias<"ldmia", "ldm">;
5072 def : MnemonicAlias<"ldmea", "ldmdb">;
5073 def : MnemonicAlias<"stmfd", "stmdb">;
5074 def : MnemonicAlias<"stmia", "stm">;
5075 def : MnemonicAlias<"stmea", "stm">;
5077 // PKHBT/PKHTB with default shift amount. PKHTB is equivalent to PKHBT when the
5078 // shift amount is zero (i.e., unspecified).
5079 def : InstAlias<"pkhbt${p} $Rd, $Rn, $Rm",
5080 (PKHBT GPRnopc:$Rd, GPRnopc:$Rn, GPRnopc:$Rm, 0, pred:$p)>,
5081 Requires<[IsARM, HasV6]>;
5082 def : InstAlias<"pkhtb${p} $Rd, $Rn, $Rm",
5083 (PKHBT GPRnopc:$Rd, GPRnopc:$Rn, GPRnopc:$Rm, 0, pred:$p)>,
5084 Requires<[IsARM, HasV6]>;
5086 // PUSH/POP aliases for STM/LDM
5087 def : ARMInstAlias<"push${p} $regs", (STMDB_UPD SP, pred:$p, reglist:$regs)>;
5088 def : ARMInstAlias<"pop${p} $regs", (LDMIA_UPD SP, pred:$p, reglist:$regs)>;
5090 // SSAT/USAT optional shift operand.
5091 def : ARMInstAlias<"ssat${p} $Rd, $sat_imm, $Rn",
5092 (SSAT GPRnopc:$Rd, imm1_32:$sat_imm, GPRnopc:$Rn, 0, pred:$p)>;
5093 def : ARMInstAlias<"usat${p} $Rd, $sat_imm, $Rn",
5094 (USAT GPRnopc:$Rd, imm0_31:$sat_imm, GPRnopc:$Rn, 0, pred:$p)>;
5097 // Extend instruction optional rotate operand.
5098 def : ARMInstAlias<"sxtab${p} $Rd, $Rn, $Rm",
5099 (SXTAB GPRnopc:$Rd, GPR:$Rn, GPRnopc:$Rm, 0, pred:$p)>;
5100 def : ARMInstAlias<"sxtah${p} $Rd, $Rn, $Rm",
5101 (SXTAH GPRnopc:$Rd, GPR:$Rn, GPRnopc:$Rm, 0, pred:$p)>;
5102 def : ARMInstAlias<"sxtab16${p} $Rd, $Rn, $Rm",
5103 (SXTAB16 GPRnopc:$Rd, GPR:$Rn, GPRnopc:$Rm, 0, pred:$p)>;
5104 def : ARMInstAlias<"sxtb${p} $Rd, $Rm",
5105 (SXTB GPRnopc:$Rd, GPRnopc:$Rm, 0, pred:$p)>;
5106 def : ARMInstAlias<"sxtb16${p} $Rd, $Rm",
5107 (SXTB16 GPRnopc:$Rd, GPRnopc:$Rm, 0, pred:$p)>;
5108 def : ARMInstAlias<"sxth${p} $Rd, $Rm",
5109 (SXTH GPRnopc:$Rd, GPRnopc:$Rm, 0, pred:$p)>;
5111 def : ARMInstAlias<"uxtab${p} $Rd, $Rn, $Rm",
5112 (UXTAB GPRnopc:$Rd, GPR:$Rn, GPRnopc:$Rm, 0, pred:$p)>;
5113 def : ARMInstAlias<"uxtah${p} $Rd, $Rn, $Rm",
5114 (UXTAH GPRnopc:$Rd, GPR:$Rn, GPRnopc:$Rm, 0, pred:$p)>;
5115 def : ARMInstAlias<"uxtab16${p} $Rd, $Rn, $Rm",
5116 (UXTAB16 GPRnopc:$Rd, GPR:$Rn, GPRnopc:$Rm, 0, pred:$p)>;
5117 def : ARMInstAlias<"uxtb${p} $Rd, $Rm",
5118 (UXTB GPRnopc:$Rd, GPRnopc:$Rm, 0, pred:$p)>;
5119 def : ARMInstAlias<"uxtb16${p} $Rd, $Rm",
5120 (UXTB16 GPRnopc:$Rd, GPRnopc:$Rm, 0, pred:$p)>;
5121 def : ARMInstAlias<"uxth${p} $Rd, $Rm",
5122 (UXTH GPRnopc:$Rd, GPRnopc:$Rm, 0, pred:$p)>;
5126 def : MnemonicAlias<"rfefa", "rfeda">;
5127 def : MnemonicAlias<"rfeea", "rfedb">;
5128 def : MnemonicAlias<"rfefd", "rfeia">;
5129 def : MnemonicAlias<"rfeed", "rfeib">;
5130 def : MnemonicAlias<"rfe", "rfeia">;
5133 def : MnemonicAlias<"srsfa", "srsda">;
5134 def : MnemonicAlias<"srsea", "srsdb">;
5135 def : MnemonicAlias<"srsfd", "srsia">;
5136 def : MnemonicAlias<"srsed", "srsib">;
5137 def : MnemonicAlias<"srs", "srsia">;
5140 def : MnemonicAlias<"qsubaddx", "qsax">;
5142 def : MnemonicAlias<"saddsubx", "sasx">;
5143 // SHASX == SHADDSUBX
5144 def : MnemonicAlias<"shaddsubx", "shasx">;
5145 // SHSAX == SHSUBADDX
5146 def : MnemonicAlias<"shsubaddx", "shsax">;
5148 def : MnemonicAlias<"ssubaddx", "ssax">;
5150 def : MnemonicAlias<"uaddsubx", "uasx">;
5151 // UHASX == UHADDSUBX
5152 def : MnemonicAlias<"uhaddsubx", "uhasx">;
5153 // UHSAX == UHSUBADDX
5154 def : MnemonicAlias<"uhsubaddx", "uhsax">;
5155 // UQASX == UQADDSUBX
5156 def : MnemonicAlias<"uqaddsubx", "uqasx">;
5157 // UQSAX == UQSUBADDX
5158 def : MnemonicAlias<"uqsubaddx", "uqsax">;
5160 def : MnemonicAlias<"usubaddx", "usax">;
5162 // "mov Rd, so_imm_not" can be handled via "mvn" in assembly, just like
5164 def : ARMInstAlias<"mov${s}${p} $Rd, $imm",
5165 (MVNi rGPR:$Rd, so_imm_not:$imm, pred:$p, cc_out:$s)>;
5166 def : ARMInstAlias<"mvn${s}${p} $Rd, $imm",
5167 (MOVi rGPR:$Rd, so_imm_not:$imm, pred:$p, cc_out:$s)>;
5168 // Same for AND <--> BIC
5169 def : ARMInstAlias<"bic${s}${p} $Rd, $Rn, $imm",
5170 (ANDri rGPR:$Rd, rGPR:$Rn, so_imm_not:$imm,
5171 pred:$p, cc_out:$s)>;
5172 def : ARMInstAlias<"bic${s}${p} $Rdn, $imm",
5173 (ANDri rGPR:$Rdn, rGPR:$Rdn, so_imm_not:$imm,
5174 pred:$p, cc_out:$s)>;
5175 def : ARMInstAlias<"and${s}${p} $Rd, $Rn, $imm",
5176 (BICri rGPR:$Rd, rGPR:$Rn, so_imm_not:$imm,
5177 pred:$p, cc_out:$s)>;
5178 def : ARMInstAlias<"and${s}${p} $Rdn, $imm",
5179 (BICri rGPR:$Rdn, rGPR:$Rdn, so_imm_not:$imm,
5180 pred:$p, cc_out:$s)>;
5182 // Likewise, "add Rd, so_imm_neg" -> sub
5183 def : ARMInstAlias<"add${s}${p} $Rd, $Rn, $imm",
5184 (SUBri GPR:$Rd, GPR:$Rn, so_imm_neg:$imm, pred:$p, cc_out:$s)>;
5185 def : ARMInstAlias<"add${s}${p} $Rd, $imm",
5186 (SUBri GPR:$Rd, GPR:$Rd, so_imm_neg:$imm, pred:$p, cc_out:$s)>;
5187 // Same for CMP <--> CMN via so_imm_neg
5188 def : ARMInstAlias<"cmp${p} $Rd, $imm",
5189 (CMNzri rGPR:$Rd, so_imm_neg:$imm, pred:$p)>;
5190 def : ARMInstAlias<"cmn${p} $Rd, $imm",
5191 (CMPri rGPR:$Rd, so_imm_neg:$imm, pred:$p)>;
5193 // The shifter forms of the MOV instruction are aliased to the ASR, LSL,
5194 // LSR, ROR, and RRX instructions.
5195 // FIXME: We need C++ parser hooks to map the alias to the MOV
5196 // encoding. It seems we should be able to do that sort of thing
5197 // in tblgen, but it could get ugly.
5198 def ASRi : ARMAsmPseudo<"asr${s}${p} $Rd, $Rm, $imm",
5199 (ins GPR:$Rd, GPR:$Rm, imm0_32:$imm, pred:$p,
5201 def LSRi : ARMAsmPseudo<"lsr${s}${p} $Rd, $Rm, $imm",
5202 (ins GPR:$Rd, GPR:$Rm, imm0_32:$imm, pred:$p,
5204 def LSLi : ARMAsmPseudo<"lsl${s}${p} $Rd, $Rm, $imm",
5205 (ins GPR:$Rd, GPR:$Rm, imm0_31:$imm, pred:$p,
5207 def RORi : ARMAsmPseudo<"ror${s}${p} $Rd, $Rm, $imm",
5208 (ins GPR:$Rd, GPR:$Rm, imm0_31:$imm, pred:$p,
5210 def RRXi : ARMAsmPseudo<"rrx${s}${p} $Rd, $Rm",
5211 (ins GPRnopc:$Rd, GPRnopc:$Rm, pred:$p, cc_out:$s)>;
5212 def ASRr : ARMAsmPseudo<"asr${s}${p} $Rd, $Rn, $Rm",
5213 (ins GPRnopc:$Rd, GPRnopc:$Rn, GPRnopc:$Rm, pred:$p,
5215 def LSRr : ARMAsmPseudo<"lsr${s}${p} $Rd, $Rn, $Rm",
5216 (ins GPRnopc:$Rd, GPRnopc:$Rn, GPRnopc:$Rm, pred:$p,
5218 def LSLr : ARMAsmPseudo<"lsl${s}${p} $Rd, $Rn, $Rm",
5219 (ins GPRnopc:$Rd, GPRnopc:$Rn, GPRnopc:$Rm, pred:$p,
5221 def RORr : ARMAsmPseudo<"ror${s}${p} $Rd, $Rn, $Rm",
5222 (ins GPRnopc:$Rd, GPRnopc:$Rn, GPRnopc:$Rm, pred:$p,
5224 // shifter instructions also support a two-operand form.
5225 def : ARMInstAlias<"asr${s}${p} $Rm, $imm",
5226 (ASRi GPR:$Rm, GPR:$Rm, imm0_32:$imm, pred:$p, cc_out:$s)>;
5227 def : ARMInstAlias<"lsr${s}${p} $Rm, $imm",
5228 (LSRi GPR:$Rm, GPR:$Rm, imm0_32:$imm, pred:$p, cc_out:$s)>;
5229 def : ARMInstAlias<"lsl${s}${p} $Rm, $imm",
5230 (LSLi GPR:$Rm, GPR:$Rm, imm0_31:$imm, pred:$p, cc_out:$s)>;
5231 def : ARMInstAlias<"ror${s}${p} $Rm, $imm",
5232 (RORi GPR:$Rm, GPR:$Rm, imm0_31:$imm, pred:$p, cc_out:$s)>;
5233 def : ARMInstAlias<"asr${s}${p} $Rn, $Rm",
5234 (ASRr GPRnopc:$Rn, GPRnopc:$Rn, GPRnopc:$Rm, pred:$p,
5236 def : ARMInstAlias<"lsr${s}${p} $Rn, $Rm",
5237 (LSRr GPRnopc:$Rn, GPRnopc:$Rn, GPRnopc:$Rm, pred:$p,
5239 def : ARMInstAlias<"lsl${s}${p} $Rn, $Rm",
5240 (LSLr GPRnopc:$Rn, GPRnopc:$Rn, GPRnopc:$Rm, pred:$p,
5242 def : ARMInstAlias<"ror${s}${p} $Rn, $Rm",
5243 (RORr GPRnopc:$Rn, GPRnopc:$Rn, GPRnopc:$Rm, pred:$p,
5247 // 'mul' instruction can be specified with only two operands.
5248 def : ARMInstAlias<"mul${s}${p} $Rn, $Rm",
5249 (MUL rGPR:$Rn, rGPR:$Rm, rGPR:$Rn, pred:$p, cc_out:$s)>;
5251 // "neg" is and alias for "rsb rd, rn, #0"
5252 def : ARMInstAlias<"neg${s}${p} $Rd, $Rm",
5253 (RSBri GPR:$Rd, GPR:$Rm, 0, pred:$p, cc_out:$s)>;
5255 // Pre-v6, 'mov r0, r0' was used as a NOP encoding.
5256 def : InstAlias<"nop${p}", (MOVr R0, R0, pred:$p, zero_reg)>,
5257 Requires<[IsARM, NoV6]>;
5259 // 'it' blocks in ARM mode just validate the predicates. The IT itself
5261 def ITasm : ARMAsmPseudo<"it$mask $cc", (ins it_pred:$cc, it_mask:$mask)>;