1 //===- ARMInstrInfo.td - Target Description for ARM Target -*- tablegen -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file describes the ARM instructions in TableGen format.
12 //===----------------------------------------------------------------------===//
14 //===----------------------------------------------------------------------===//
15 // ARM specific DAG Nodes.
19 def SDT_ARMCallSeqStart : SDCallSeqStart<[ SDTCisVT<0, i32> ]>;
20 def SDT_ARMCallSeqEnd : SDCallSeqEnd<[ SDTCisVT<0, i32>, SDTCisVT<1, i32> ]>;
22 def SDT_ARMSaveCallPC : SDTypeProfile<0, 1, []>;
24 def SDT_ARMcall : SDTypeProfile<0, -1, [SDTCisInt<0>]>;
26 def SDT_ARMCMov : SDTypeProfile<1, 3,
27 [SDTCisSameAs<0, 1>, SDTCisSameAs<0, 2>,
30 def SDT_ARMBrcond : SDTypeProfile<0, 2,
31 [SDTCisVT<0, OtherVT>, SDTCisVT<1, i32>]>;
33 def SDT_ARMBrJT : SDTypeProfile<0, 3,
34 [SDTCisPtrTy<0>, SDTCisVT<1, i32>,
37 def SDT_ARMCmp : SDTypeProfile<0, 2, [SDTCisSameAs<0, 1>]>;
39 def SDT_ARMPICAdd : SDTypeProfile<1, 2, [SDTCisSameAs<0, 1>,
40 SDTCisPtrTy<1>, SDTCisVT<2, i32>]>;
42 def SDT_ARMThreadPointer : SDTypeProfile<1, 0, [SDTCisPtrTy<0>]>;
43 def SDT_ARMEH_SJLJ_Setjmp : SDTypeProfile<1, 1, [SDTCisInt<0>, SDTCisPtrTy<1>]>;
46 def ARMWrapper : SDNode<"ARMISD::Wrapper", SDTIntUnaryOp>;
47 def ARMWrapperJT : SDNode<"ARMISD::WrapperJT", SDTIntBinOp>;
49 def ARMcallseq_start : SDNode<"ISD::CALLSEQ_START", SDT_ARMCallSeqStart,
50 [SDNPHasChain, SDNPOutFlag]>;
51 def ARMcallseq_end : SDNode<"ISD::CALLSEQ_END", SDT_ARMCallSeqEnd,
52 [SDNPHasChain, SDNPOptInFlag, SDNPOutFlag]>;
54 def ARMcall : SDNode<"ARMISD::CALL", SDT_ARMcall,
55 [SDNPHasChain, SDNPOptInFlag, SDNPOutFlag]>;
56 def ARMcall_pred : SDNode<"ARMISD::CALL_PRED", SDT_ARMcall,
57 [SDNPHasChain, SDNPOptInFlag, SDNPOutFlag]>;
58 def ARMcall_nolink : SDNode<"ARMISD::CALL_NOLINK", SDT_ARMcall,
59 [SDNPHasChain, SDNPOptInFlag, SDNPOutFlag]>;
61 def ARMretflag : SDNode<"ARMISD::RET_FLAG", SDTNone,
62 [SDNPHasChain, SDNPOptInFlag]>;
64 def ARMcmov : SDNode<"ARMISD::CMOV", SDT_ARMCMov,
66 def ARMcneg : SDNode<"ARMISD::CNEG", SDT_ARMCMov,
69 def ARMbrcond : SDNode<"ARMISD::BRCOND", SDT_ARMBrcond,
70 [SDNPHasChain, SDNPInFlag, SDNPOutFlag]>;
72 def ARMbrjt : SDNode<"ARMISD::BR_JT", SDT_ARMBrJT,
75 def ARMcmp : SDNode<"ARMISD::CMP", SDT_ARMCmp,
78 def ARMcmpNZ : SDNode<"ARMISD::CMPNZ", SDT_ARMCmp,
81 def ARMpic_add : SDNode<"ARMISD::PIC_ADD", SDT_ARMPICAdd>;
83 def ARMsrl_flag : SDNode<"ARMISD::SRL_FLAG", SDTIntUnaryOp, [SDNPOutFlag]>;
84 def ARMsra_flag : SDNode<"ARMISD::SRA_FLAG", SDTIntUnaryOp, [SDNPOutFlag]>;
85 def ARMrrx : SDNode<"ARMISD::RRX" , SDTIntUnaryOp, [SDNPInFlag ]>;
87 def ARMthread_pointer: SDNode<"ARMISD::THREAD_POINTER", SDT_ARMThreadPointer>;
88 def ARMeh_sjlj_setjmp: SDNode<"ARMISD::EH_SJLJ_SETJMP", SDT_ARMEH_SJLJ_Setjmp>;
90 //===----------------------------------------------------------------------===//
91 // ARM Instruction Predicate Definitions.
93 def HasV5T : Predicate<"Subtarget->hasV5TOps()">;
94 def HasV5TE : Predicate<"Subtarget->hasV5TEOps()">;
95 def HasV6 : Predicate<"Subtarget->hasV6Ops()">;
96 def HasV7 : Predicate<"Subtarget->hasV7Ops()">;
97 def HasVFP2 : Predicate<"Subtarget->hasVFP2()">;
98 def HasVFP3 : Predicate<"Subtarget->hasVFP3()">;
99 def HasNEON : Predicate<"Subtarget->hasNEON()">;
100 def IsThumb : Predicate<"Subtarget->isThumb()">;
101 def IsThumb1Only : Predicate<"Subtarget->isThumb1Only()">;
102 def HasThumb2 : Predicate<"Subtarget->hasThumb2()">;
103 def IsARM : Predicate<"!Subtarget->isThumb()">;
104 def IsDarwin : Predicate<"Subtarget->isTargetDarwin()">;
105 def IsNotDarwin : Predicate<"!Subtarget->isTargetDarwin()">;
106 def CarryDefIsUnused : Predicate<"!N.getNode()->hasAnyUseOfValue(1)">;
107 def CarryDefIsUsed : Predicate<"N.getNode()->hasAnyUseOfValue(1)">;
109 //===----------------------------------------------------------------------===//
110 // ARM Flag Definitions.
112 class RegConstraint<string C> {
113 string Constraints = C;
116 //===----------------------------------------------------------------------===//
117 // ARM specific transformation functions and pattern fragments.
120 // so_imm_XFORM - Return a so_imm value packed into the format described for
122 def so_imm_XFORM : SDNodeXForm<imm, [{
123 return CurDAG->getTargetConstant(ARM_AM::getSOImmVal(N->getZExtValue()),
127 // so_imm_neg_XFORM - Return a so_imm value packed into the format described for
128 // so_imm_neg def below.
129 def so_imm_neg_XFORM : SDNodeXForm<imm, [{
130 return CurDAG->getTargetConstant(ARM_AM::getSOImmVal(-(int)N->getZExtValue()),
134 // so_imm_not_XFORM - Return a so_imm value packed into the format described for
135 // so_imm_not def below.
136 def so_imm_not_XFORM : SDNodeXForm<imm, [{
137 return CurDAG->getTargetConstant(ARM_AM::getSOImmVal(~(int)N->getZExtValue()),
141 // rot_imm predicate - True if the 32-bit immediate is equal to 8, 16, or 24.
142 def rot_imm : PatLeaf<(i32 imm), [{
143 int32_t v = (int32_t)N->getZExtValue();
144 return v == 8 || v == 16 || v == 24;
147 /// imm1_15 predicate - True if the 32-bit immediate is in the range [1,15].
148 def imm1_15 : PatLeaf<(i32 imm), [{
149 return (int32_t)N->getZExtValue() >= 1 && (int32_t)N->getZExtValue() < 16;
152 /// imm16_31 predicate - True if the 32-bit immediate is in the range [16,31].
153 def imm16_31 : PatLeaf<(i32 imm), [{
154 return (int32_t)N->getZExtValue() >= 16 && (int32_t)N->getZExtValue() < 32;
159 return ARM_AM::getSOImmVal(-(int)N->getZExtValue()) != -1;
160 }], so_imm_neg_XFORM>;
164 return ARM_AM::getSOImmVal(~(int)N->getZExtValue()) != -1;
165 }], so_imm_not_XFORM>;
167 // sext_16_node predicate - True if the SDNode is sign-extended 16 or more bits.
168 def sext_16_node : PatLeaf<(i32 GPR:$a), [{
169 return CurDAG->ComputeNumSignBits(SDValue(N,0)) >= 17;
172 class BinOpFrag<dag res> : PatFrag<(ops node:$LHS, node:$RHS), res>;
173 class UnOpFrag <dag res> : PatFrag<(ops node:$Src), res>;
175 //===----------------------------------------------------------------------===//
176 // Operand Definitions.
180 def brtarget : Operand<OtherVT>;
182 // A list of registers separated by comma. Used by load/store multiple.
183 def reglist : Operand<i32> {
184 let PrintMethod = "printRegisterList";
187 // An operand for the CONSTPOOL_ENTRY pseudo-instruction.
188 def cpinst_operand : Operand<i32> {
189 let PrintMethod = "printCPInstOperand";
192 def jtblock_operand : Operand<i32> {
193 let PrintMethod = "printJTBlockOperand";
197 def pclabel : Operand<i32> {
198 let PrintMethod = "printPCLabel";
201 // shifter_operand operands: so_reg and so_imm.
202 def so_reg : Operand<i32>, // reg reg imm
203 ComplexPattern<i32, 3, "SelectShifterOperandReg",
204 [shl,srl,sra,rotr]> {
205 let PrintMethod = "printSORegOperand";
206 let MIOperandInfo = (ops GPR, GPR, i32imm);
209 // so_imm - Match a 32-bit shifter_operand immediate operand, which is an
210 // 8-bit immediate rotated by an arbitrary number of bits. so_imm values are
211 // represented in the imm field in the same 12-bit form that they are encoded
212 // into so_imm instructions: the 8-bit immediate is the least significant bits
213 // [bits 0-7], the 4-bit shift amount is the next 4 bits [bits 8-11].
214 def so_imm : Operand<i32>,
216 [{ return ARM_AM::getSOImmVal(N->getZExtValue()) != -1; }],
218 let PrintMethod = "printSOImmOperand";
221 // Break so_imm's up into two pieces. This handles immediates with up to 16
222 // bits set in them. This uses so_imm2part to match and so_imm2part_[12] to
223 // get the first/second pieces.
224 def so_imm2part : Operand<i32>,
226 return ARM_AM::isSOImmTwoPartVal((unsigned)N->getZExtValue());
228 let PrintMethod = "printSOImm2PartOperand";
231 def so_imm2part_1 : SDNodeXForm<imm, [{
232 unsigned V = ARM_AM::getSOImmTwoPartFirst((unsigned)N->getZExtValue());
233 return CurDAG->getTargetConstant(ARM_AM::getSOImmVal(V), MVT::i32);
236 def so_imm2part_2 : SDNodeXForm<imm, [{
237 unsigned V = ARM_AM::getSOImmTwoPartSecond((unsigned)N->getZExtValue());
238 return CurDAG->getTargetConstant(ARM_AM::getSOImmVal(V), MVT::i32);
242 // Define ARM specific addressing modes.
244 // addrmode2 := reg +/- reg shop imm
245 // addrmode2 := reg +/- imm12
247 def addrmode2 : Operand<i32>,
248 ComplexPattern<i32, 3, "SelectAddrMode2", []> {
249 let PrintMethod = "printAddrMode2Operand";
250 let MIOperandInfo = (ops GPR:$base, GPR:$offsreg, i32imm:$offsimm);
253 def am2offset : Operand<i32>,
254 ComplexPattern<i32, 2, "SelectAddrMode2Offset", []> {
255 let PrintMethod = "printAddrMode2OffsetOperand";
256 let MIOperandInfo = (ops GPR, i32imm);
259 // addrmode3 := reg +/- reg
260 // addrmode3 := reg +/- imm8
262 def addrmode3 : Operand<i32>,
263 ComplexPattern<i32, 3, "SelectAddrMode3", []> {
264 let PrintMethod = "printAddrMode3Operand";
265 let MIOperandInfo = (ops GPR:$base, GPR:$offsreg, i32imm:$offsimm);
268 def am3offset : Operand<i32>,
269 ComplexPattern<i32, 2, "SelectAddrMode3Offset", []> {
270 let PrintMethod = "printAddrMode3OffsetOperand";
271 let MIOperandInfo = (ops GPR, i32imm);
274 // addrmode4 := reg, <mode|W>
276 def addrmode4 : Operand<i32>,
277 ComplexPattern<i32, 2, "", []> {
278 let PrintMethod = "printAddrMode4Operand";
279 let MIOperandInfo = (ops GPR, i32imm);
282 // addrmode5 := reg +/- imm8*4
284 def addrmode5 : Operand<i32>,
285 ComplexPattern<i32, 2, "SelectAddrMode5", []> {
286 let PrintMethod = "printAddrMode5Operand";
287 let MIOperandInfo = (ops GPR, i32imm);
290 // addrmodepc := pc + reg
292 def addrmodepc : Operand<i32>,
293 ComplexPattern<i32, 2, "SelectAddrModePC", []> {
294 let PrintMethod = "printAddrModePCOperand";
295 let MIOperandInfo = (ops GPR, i32imm);
298 // ARM Predicate operand. Default to 14 = always (AL). Second part is CC
299 // register whose default is 0 (no register).
300 def pred : PredicateOperand<OtherVT, (ops i32imm, CCR),
301 (ops (i32 14), (i32 zero_reg))> {
302 let PrintMethod = "printPredicateOperand";
305 // Conditional code result for instructions whose 's' bit is set, e.g. subs.
307 def cc_out : OptionalDefOperand<OtherVT, (ops CCR), (ops (i32 zero_reg))> {
308 let PrintMethod = "printSBitModifierOperand";
311 //===----------------------------------------------------------------------===//
313 include "ARMInstrFormats.td"
315 //===----------------------------------------------------------------------===//
316 // Multiclass helpers...
319 /// AsI1_bin_irs - Defines a set of (op r, {so_imm|r|so_reg}) patterns for a
320 /// binop that produces a value.
321 multiclass AsI1_bin_irs<bits<4> opcod, string opc, PatFrag opnode,
322 bit Commutable = 0> {
323 def ri : AsI1<opcod, (outs GPR:$dst), (ins GPR:$a, so_imm:$b), DPFrm,
324 opc, " $dst, $a, $b",
325 [(set GPR:$dst, (opnode GPR:$a, so_imm:$b))]>;
326 def rr : AsI1<opcod, (outs GPR:$dst), (ins GPR:$a, GPR:$b), DPFrm,
327 opc, " $dst, $a, $b",
328 [(set GPR:$dst, (opnode GPR:$a, GPR:$b))]> {
329 let isCommutable = Commutable;
331 def rs : AsI1<opcod, (outs GPR:$dst), (ins GPR:$a, so_reg:$b), DPSoRegFrm,
332 opc, " $dst, $a, $b",
333 [(set GPR:$dst, (opnode GPR:$a, so_reg:$b))]>;
336 /// AI1_bin_s_irs - Similar to AsI1_bin_irs except it sets the 's' bit so the
337 /// instruction modifies the CSPR register.
338 let Defs = [CPSR] in {
339 multiclass AI1_bin_s_irs<bits<4> opcod, string opc, PatFrag opnode,
340 bit Commutable = 0> {
341 def ri : AI1<opcod, (outs GPR:$dst), (ins GPR:$a, so_imm:$b), DPFrm,
342 opc, "s $dst, $a, $b",
343 [(set GPR:$dst, (opnode GPR:$a, so_imm:$b))]>;
344 def rr : AI1<opcod, (outs GPR:$dst), (ins GPR:$a, GPR:$b), DPFrm,
345 opc, "s $dst, $a, $b",
346 [(set GPR:$dst, (opnode GPR:$a, GPR:$b))]> {
347 let isCommutable = Commutable;
349 def rs : AI1<opcod, (outs GPR:$dst), (ins GPR:$a, so_reg:$b), DPSoRegFrm,
350 opc, "s $dst, $a, $b",
351 [(set GPR:$dst, (opnode GPR:$a, so_reg:$b))]>;
355 /// AI1_cmp_irs - Defines a set of (op r, {so_imm|r|so_reg}) cmp / test
356 /// patterns. Similar to AsI1_bin_irs except the instruction does not produce
357 /// a explicit result, only implicitly set CPSR.
358 let Defs = [CPSR] in {
359 multiclass AI1_cmp_irs<bits<4> opcod, string opc, PatFrag opnode,
360 bit Commutable = 0> {
361 def ri : AI1<opcod, (outs), (ins GPR:$a, so_imm:$b), DPFrm,
363 [(opnode GPR:$a, so_imm:$b)]>;
364 def rr : AI1<opcod, (outs), (ins GPR:$a, GPR:$b), DPFrm,
366 [(opnode GPR:$a, GPR:$b)]> {
367 let isCommutable = Commutable;
369 def rs : AI1<opcod, (outs), (ins GPR:$a, so_reg:$b), DPSoRegFrm,
371 [(opnode GPR:$a, so_reg:$b)]>;
375 /// AI_unary_rrot - A unary operation with two forms: one whose operand is a
376 /// register and one whose operand is a register rotated by 8/16/24.
377 /// FIXME: Remove the 'r' variant. Its rot_imm is zero.
378 multiclass AI_unary_rrot<bits<8> opcod, string opc, PatFrag opnode> {
379 def r : AExtI<opcod, (outs GPR:$dst), (ins GPR:$Src),
381 [(set GPR:$dst, (opnode GPR:$Src))]>,
382 Requires<[IsARM, HasV6]> {
383 let Inst{19-16} = 0b1111;
385 def r_rot : AExtI<opcod, (outs GPR:$dst), (ins GPR:$Src, i32imm:$rot),
386 opc, " $dst, $Src, ror $rot",
387 [(set GPR:$dst, (opnode (rotr GPR:$Src, rot_imm:$rot)))]>,
388 Requires<[IsARM, HasV6]> {
389 let Inst{19-16} = 0b1111;
393 /// AI_bin_rrot - A binary operation with two forms: one whose operand is a
394 /// register and one whose operand is a register rotated by 8/16/24.
395 multiclass AI_bin_rrot<bits<8> opcod, string opc, PatFrag opnode> {
396 def rr : AExtI<opcod, (outs GPR:$dst), (ins GPR:$LHS, GPR:$RHS),
397 opc, " $dst, $LHS, $RHS",
398 [(set GPR:$dst, (opnode GPR:$LHS, GPR:$RHS))]>,
399 Requires<[IsARM, HasV6]>;
400 def rr_rot : AExtI<opcod, (outs GPR:$dst), (ins GPR:$LHS, GPR:$RHS, i32imm:$rot),
401 opc, " $dst, $LHS, $RHS, ror $rot",
402 [(set GPR:$dst, (opnode GPR:$LHS,
403 (rotr GPR:$RHS, rot_imm:$rot)))]>,
404 Requires<[IsARM, HasV6]>;
407 /// AI1_adde_sube_irs - Define instructions and patterns for adde and sube.
408 let Uses = [CPSR] in {
409 multiclass AI1_adde_sube_irs<bits<4> opcod, string opc, PatFrag opnode,
410 bit Commutable = 0> {
411 def ri : AsI1<opcod, (outs GPR:$dst), (ins GPR:$a, so_imm:$b),
412 DPFrm, opc, " $dst, $a, $b",
413 [(set GPR:$dst, (opnode GPR:$a, so_imm:$b))]>,
414 Requires<[IsARM, CarryDefIsUnused]>;
415 def rr : AsI1<opcod, (outs GPR:$dst), (ins GPR:$a, GPR:$b),
416 DPFrm, opc, " $dst, $a, $b",
417 [(set GPR:$dst, (opnode GPR:$a, GPR:$b))]>,
418 Requires<[IsARM, CarryDefIsUnused]> {
419 let isCommutable = Commutable;
421 def rs : AsI1<opcod, (outs GPR:$dst), (ins GPR:$a, so_reg:$b),
422 DPSoRegFrm, opc, " $dst, $a, $b",
423 [(set GPR:$dst, (opnode GPR:$a, so_reg:$b))]>,
424 Requires<[IsARM, CarryDefIsUnused]>;
425 // Carry setting variants
426 def Sri : AXI1<opcod, (outs GPR:$dst), (ins GPR:$a, so_imm:$b),
427 DPFrm, !strconcat(opc, "s $dst, $a, $b"),
428 [(set GPR:$dst, (opnode GPR:$a, so_imm:$b))]>,
429 Requires<[IsARM, CarryDefIsUsed]> {
432 def Srr : AXI1<opcod, (outs GPR:$dst), (ins GPR:$a, GPR:$b),
433 DPFrm, !strconcat(opc, "s $dst, $a, $b"),
434 [(set GPR:$dst, (opnode GPR:$a, GPR:$b))]>,
435 Requires<[IsARM, CarryDefIsUsed]> {
438 def Srs : AXI1<opcod, (outs GPR:$dst), (ins GPR:$a, so_reg:$b),
439 DPSoRegFrm, !strconcat(opc, "s $dst, $a, $b"),
440 [(set GPR:$dst, (opnode GPR:$a, so_reg:$b))]>,
441 Requires<[IsARM, CarryDefIsUsed]> {
447 //===----------------------------------------------------------------------===//
449 //===----------------------------------------------------------------------===//
451 //===----------------------------------------------------------------------===//
452 // Miscellaneous Instructions.
455 /// CONSTPOOL_ENTRY - This instruction represents a floating constant pool in
456 /// the function. The first operand is the ID# for this instruction, the second
457 /// is the index into the MachineConstantPool that this is, the third is the
458 /// size in bytes of this constant pool entry.
459 let neverHasSideEffects = 1, isNotDuplicable = 1 in
460 def CONSTPOOL_ENTRY :
461 PseudoInst<(outs), (ins cpinst_operand:$instid, cpinst_operand:$cpidx,
463 "${instid:label} ${cpidx:cpentry}", []>;
465 let Defs = [SP], Uses = [SP] in {
467 PseudoInst<(outs), (ins i32imm:$amt1, i32imm:$amt2, pred:$p),
468 "@ ADJCALLSTACKUP $amt1",
469 [(ARMcallseq_end timm:$amt1, timm:$amt2)]>;
471 def ADJCALLSTACKDOWN :
472 PseudoInst<(outs), (ins i32imm:$amt, pred:$p),
473 "@ ADJCALLSTACKDOWN $amt",
474 [(ARMcallseq_start timm:$amt)]>;
478 PseudoInst<(outs), (ins i32imm:$line, i32imm:$col, i32imm:$file),
479 ".loc $file, $line, $col",
480 [(dwarf_loc (i32 imm:$line), (i32 imm:$col), (i32 imm:$file))]>;
483 // Address computation and loads and stores in PIC mode.
484 let isNotDuplicable = 1 in {
485 def PICADD : AXI1<0b0100, (outs GPR:$dst), (ins GPR:$a, pclabel:$cp, pred:$p),
486 Pseudo, "$cp:\n\tadd$p $dst, pc, $a",
487 [(set GPR:$dst, (ARMpic_add GPR:$a, imm:$cp))]>;
489 let AddedComplexity = 10 in {
490 let canFoldAsLoad = 1 in
491 def PICLDR : AXI2ldw<(outs GPR:$dst), (ins addrmodepc:$addr, pred:$p),
492 Pseudo, "${addr:label}:\n\tldr$p $dst, $addr",
493 [(set GPR:$dst, (load addrmodepc:$addr))]>;
495 def PICLDRH : AXI3ldh<(outs GPR:$dst), (ins addrmodepc:$addr, pred:$p),
496 Pseudo, "${addr:label}:\n\tldr${p}h $dst, $addr",
497 [(set GPR:$dst, (zextloadi16 addrmodepc:$addr))]>;
499 def PICLDRB : AXI2ldb<(outs GPR:$dst), (ins addrmodepc:$addr, pred:$p),
500 Pseudo, "${addr:label}:\n\tldr${p}b $dst, $addr",
501 [(set GPR:$dst, (zextloadi8 addrmodepc:$addr))]>;
503 def PICLDRSH : AXI3ldsh<(outs GPR:$dst), (ins addrmodepc:$addr, pred:$p),
504 Pseudo, "${addr:label}:\n\tldr${p}sh $dst, $addr",
505 [(set GPR:$dst, (sextloadi16 addrmodepc:$addr))]>;
507 def PICLDRSB : AXI3ldsb<(outs GPR:$dst), (ins addrmodepc:$addr, pred:$p),
508 Pseudo, "${addr:label}:\n\tldr${p}sb $dst, $addr",
509 [(set GPR:$dst, (sextloadi8 addrmodepc:$addr))]>;
511 let AddedComplexity = 10 in {
512 def PICSTR : AXI2stw<(outs), (ins GPR:$src, addrmodepc:$addr, pred:$p),
513 Pseudo, "${addr:label}:\n\tstr$p $src, $addr",
514 [(store GPR:$src, addrmodepc:$addr)]>;
516 def PICSTRH : AXI3sth<(outs), (ins GPR:$src, addrmodepc:$addr, pred:$p),
517 Pseudo, "${addr:label}:\n\tstr${p}h $src, $addr",
518 [(truncstorei16 GPR:$src, addrmodepc:$addr)]>;
520 def PICSTRB : AXI2stb<(outs), (ins GPR:$src, addrmodepc:$addr, pred:$p),
521 Pseudo, "${addr:label}:\n\tstr${p}b $src, $addr",
522 [(truncstorei8 GPR:$src, addrmodepc:$addr)]>;
524 } // isNotDuplicable = 1
527 // LEApcrel - Load a pc-relative address into a register without offending the
529 def LEApcrel : AXI1<0x0, (outs GPR:$dst), (ins i32imm:$label, pred:$p), Pseudo,
530 !strconcat(!strconcat(".set PCRELV${:uid}, ($label-(",
531 "${:private}PCRELL${:uid}+8))\n"),
532 !strconcat("${:private}PCRELL${:uid}:\n\t",
533 "add$p $dst, pc, #PCRELV${:uid}")),
536 def LEApcrelJT : AXI1<0x0, (outs GPR:$dst),
537 (ins i32imm:$label, i32imm:$id, pred:$p),
539 !strconcat(!strconcat(".set PCRELV${:uid}, (${label}_${id:no_hash}-(",
540 "${:private}PCRELL${:uid}+8))\n"),
541 !strconcat("${:private}PCRELL${:uid}:\n\t",
542 "add$p $dst, pc, #PCRELV${:uid}")),
545 //===----------------------------------------------------------------------===//
546 // Control Flow Instructions.
549 let isReturn = 1, isTerminator = 1 in
550 def BX_RET : AI<(outs), (ins), BrMiscFrm, "bx", " lr", [(ARMretflag)]> {
551 let Inst{7-4} = 0b0001;
552 let Inst{19-8} = 0b111111111111;
553 let Inst{27-20} = 0b00010010;
556 // FIXME: remove when we have a way to marking a MI with these properties.
557 // FIXME: $dst1 should be a def. But the extra ops must be in the end of the
559 // FIXME: Should pc be an implicit operand like PICADD, etc?
560 let isReturn = 1, isTerminator = 1 in
561 def LDM_RET : AXI4ld<(outs),
562 (ins addrmode4:$addr, pred:$p, reglist:$dst1, variable_ops),
563 LdStMulFrm, "ldm${p}${addr:submode} $addr, $dst1",
566 // On non-Darwin platforms R9 is callee-saved.
567 let isCall = 1, Itinerary = IIC_Br,
568 Defs = [R0, R1, R2, R3, R12, LR,
569 D0, D1, D2, D3, D4, D5, D6, D7, CPSR] in {
570 def BL : ABXI<0b1011, (outs), (ins i32imm:$func, variable_ops),
572 [(ARMcall tglobaladdr:$func)]>, Requires<[IsNotDarwin]>;
574 def BL_pred : ABI<0b1011, (outs), (ins i32imm:$func, variable_ops),
575 "bl", " ${func:call}",
576 [(ARMcall_pred tglobaladdr:$func)]>, Requires<[IsNotDarwin]>;
579 def BLX : AXI<(outs), (ins GPR:$func, variable_ops), BrMiscFrm,
581 [(ARMcall GPR:$func)]>, Requires<[IsARM, HasV5T, IsNotDarwin]> {
582 let Inst{7-4} = 0b0011;
583 let Inst{19-8} = 0b111111111111;
584 let Inst{27-20} = 0b00010010;
589 def BX : ABXIx2<(outs), (ins GPR:$func, variable_ops),
590 "mov lr, pc\n\tbx $func",
591 [(ARMcall_nolink GPR:$func)]>, Requires<[IsNotDarwin]>;
595 // On Darwin R9 is call-clobbered.
596 let isCall = 1, Itinerary = IIC_Br,
597 Defs = [R0, R1, R2, R3, R9, R12, LR,
598 D0, D1, D2, D3, D4, D5, D6, D7, CPSR] in {
599 def BLr9 : ABXI<0b1011, (outs), (ins i32imm:$func, variable_ops),
601 [(ARMcall tglobaladdr:$func)]>, Requires<[IsDarwin]>;
603 def BLr9_pred : ABI<0b1011, (outs), (ins i32imm:$func, variable_ops),
604 "bl", " ${func:call}",
605 [(ARMcall_pred tglobaladdr:$func)]>, Requires<[IsDarwin]>;
608 def BLXr9 : AXI<(outs), (ins GPR:$func, variable_ops), BrMiscFrm,
610 [(ARMcall GPR:$func)]>, Requires<[IsARM, HasV5T, IsDarwin]> {
611 let Inst{7-4} = 0b0011;
612 let Inst{19-8} = 0b111111111111;
613 let Inst{27-20} = 0b00010010;
618 def BXr9 : ABXIx2<(outs), (ins GPR:$func, variable_ops),
619 "mov lr, pc\n\tbx $func",
620 [(ARMcall_nolink GPR:$func)]>, Requires<[IsDarwin]>;
624 let isBranch = 1, isTerminator = 1, Itinerary = IIC_Br in {
625 // B is "predicable" since it can be xformed into a Bcc.
626 let isBarrier = 1 in {
627 let isPredicable = 1 in
628 def B : ABXI<0b1010, (outs), (ins brtarget:$target), "b $target",
631 let isNotDuplicable = 1, isIndirectBranch = 1 in {
632 def BR_JTr : JTI<(outs), (ins GPR:$target, jtblock_operand:$jt, i32imm:$id),
633 "mov pc, $target \n$jt",
634 [(ARMbrjt GPR:$target, tjumptable:$jt, imm:$id)]> {
635 let Inst{20} = 0; // S Bit
636 let Inst{24-21} = 0b1101;
637 let Inst{27-26} = {0,0};
639 def BR_JTm : JTI<(outs),
640 (ins addrmode2:$target, jtblock_operand:$jt, i32imm:$id),
641 "ldr pc, $target \n$jt",
642 [(ARMbrjt (i32 (load addrmode2:$target)), tjumptable:$jt,
644 let Inst{20} = 1; // L bit
645 let Inst{21} = 0; // W bit
646 let Inst{22} = 0; // B bit
647 let Inst{24} = 1; // P bit
648 let Inst{27-26} = {0,1};
650 def BR_JTadd : JTI<(outs),
651 (ins GPR:$target, GPR:$idx, jtblock_operand:$jt, i32imm:$id),
652 "add pc, $target, $idx \n$jt",
653 [(ARMbrjt (add GPR:$target, GPR:$idx), tjumptable:$jt,
655 let Inst{20} = 0; // S bit
656 let Inst{24-21} = 0b0100;
657 let Inst{27-26} = {0,0};
659 } // isNotDuplicable = 1, isIndirectBranch = 1
662 // FIXME: should be able to write a pattern for ARMBrcond, but can't use
663 // a two-value operand where a dag node expects two operands. :(
664 def Bcc : ABI<0b1010, (outs), (ins brtarget:$target),
666 [/*(ARMbrcond bb:$target, imm:$cc, CCR:$ccr)*/]>;
669 //===----------------------------------------------------------------------===//
670 // Load / store Instructions.
674 let canFoldAsLoad = 1 in
675 def LDR : AI2ldw<(outs GPR:$dst), (ins addrmode2:$addr), LdFrm,
676 "ldr", " $dst, $addr",
677 [(set GPR:$dst, (load addrmode2:$addr))]>;
679 // Special LDR for loads from non-pc-relative constpools.
680 let canFoldAsLoad = 1, mayLoad = 1, isReMaterializable = 1 in
681 def LDRcp : AI2ldw<(outs GPR:$dst), (ins addrmode2:$addr), LdFrm,
682 "ldr", " $dst, $addr", []>;
684 // Loads with zero extension
685 def LDRH : AI3ldh<(outs GPR:$dst), (ins addrmode3:$addr), LdMiscFrm,
686 "ldr", "h $dst, $addr",
687 [(set GPR:$dst, (zextloadi16 addrmode3:$addr))]>;
689 def LDRB : AI2ldb<(outs GPR:$dst), (ins addrmode2:$addr), LdFrm,
690 "ldr", "b $dst, $addr",
691 [(set GPR:$dst, (zextloadi8 addrmode2:$addr))]>;
693 // Loads with sign extension
694 def LDRSH : AI3ldsh<(outs GPR:$dst), (ins addrmode3:$addr), LdMiscFrm,
695 "ldr", "sh $dst, $addr",
696 [(set GPR:$dst, (sextloadi16 addrmode3:$addr))]>;
698 def LDRSB : AI3ldsb<(outs GPR:$dst), (ins addrmode3:$addr), LdMiscFrm,
699 "ldr", "sb $dst, $addr",
700 [(set GPR:$dst, (sextloadi8 addrmode3:$addr))]>;
704 def LDRD : AI3ldd<(outs GPR:$dst1, GPR:$dst2), (ins addrmode3:$addr), LdMiscFrm,
705 "ldr", "d $dst1, $addr", []>, Requires<[IsARM, HasV5T]>;
708 def LDR_PRE : AI2ldwpr<(outs GPR:$dst, GPR:$base_wb),
709 (ins addrmode2:$addr), LdFrm,
710 "ldr", " $dst, $addr!", "$addr.base = $base_wb", []>;
712 def LDR_POST : AI2ldwpo<(outs GPR:$dst, GPR:$base_wb),
713 (ins GPR:$base, am2offset:$offset), LdFrm,
714 "ldr", " $dst, [$base], $offset", "$base = $base_wb", []>;
716 def LDRH_PRE : AI3ldhpr<(outs GPR:$dst, GPR:$base_wb),
717 (ins addrmode3:$addr), LdMiscFrm,
718 "ldr", "h $dst, $addr!", "$addr.base = $base_wb", []>;
720 def LDRH_POST : AI3ldhpo<(outs GPR:$dst, GPR:$base_wb),
721 (ins GPR:$base,am3offset:$offset), LdMiscFrm,
722 "ldr", "h $dst, [$base], $offset", "$base = $base_wb", []>;
724 def LDRB_PRE : AI2ldbpr<(outs GPR:$dst, GPR:$base_wb),
725 (ins addrmode2:$addr), LdFrm,
726 "ldr", "b $dst, $addr!", "$addr.base = $base_wb", []>;
728 def LDRB_POST : AI2ldbpo<(outs GPR:$dst, GPR:$base_wb),
729 (ins GPR:$base,am2offset:$offset), LdFrm,
730 "ldr", "b $dst, [$base], $offset", "$base = $base_wb", []>;
732 def LDRSH_PRE : AI3ldshpr<(outs GPR:$dst, GPR:$base_wb),
733 (ins addrmode3:$addr), LdMiscFrm,
734 "ldr", "sh $dst, $addr!", "$addr.base = $base_wb", []>;
736 def LDRSH_POST: AI3ldshpo<(outs GPR:$dst, GPR:$base_wb),
737 (ins GPR:$base,am3offset:$offset), LdMiscFrm,
738 "ldr", "sh $dst, [$base], $offset", "$base = $base_wb", []>;
740 def LDRSB_PRE : AI3ldsbpr<(outs GPR:$dst, GPR:$base_wb),
741 (ins addrmode3:$addr), LdMiscFrm,
742 "ldr", "sb $dst, $addr!", "$addr.base = $base_wb", []>;
744 def LDRSB_POST: AI3ldsbpo<(outs GPR:$dst, GPR:$base_wb),
745 (ins GPR:$base,am3offset:$offset), LdMiscFrm,
746 "ldr", "sb $dst, [$base], $offset", "$base = $base_wb", []>;
750 def STR : AI2stw<(outs), (ins GPR:$src, addrmode2:$addr), StFrm,
751 "str", " $src, $addr",
752 [(store GPR:$src, addrmode2:$addr)]>;
754 // Stores with truncate
755 def STRH : AI3sth<(outs), (ins GPR:$src, addrmode3:$addr), StMiscFrm,
756 "str", "h $src, $addr",
757 [(truncstorei16 GPR:$src, addrmode3:$addr)]>;
759 def STRB : AI2stb<(outs), (ins GPR:$src, addrmode2:$addr), StFrm,
760 "str", "b $src, $addr",
761 [(truncstorei8 GPR:$src, addrmode2:$addr)]>;
765 def STRD : AI3std<(outs), (ins GPR:$src1, GPR:$src2, addrmode3:$addr),StMiscFrm,
766 "str", "d $src1, $addr", []>, Requires<[IsARM, HasV5T]>;
769 def STR_PRE : AI2stwpr<(outs GPR:$base_wb),
770 (ins GPR:$src, GPR:$base, am2offset:$offset), StFrm,
771 "str", " $src, [$base, $offset]!", "$base = $base_wb",
773 (pre_store GPR:$src, GPR:$base, am2offset:$offset))]>;
775 def STR_POST : AI2stwpo<(outs GPR:$base_wb),
776 (ins GPR:$src, GPR:$base,am2offset:$offset), StFrm,
777 "str", " $src, [$base], $offset", "$base = $base_wb",
779 (post_store GPR:$src, GPR:$base, am2offset:$offset))]>;
781 def STRH_PRE : AI3sthpr<(outs GPR:$base_wb),
782 (ins GPR:$src, GPR:$base,am3offset:$offset), StMiscFrm,
783 "str", "h $src, [$base, $offset]!", "$base = $base_wb",
785 (pre_truncsti16 GPR:$src, GPR:$base,am3offset:$offset))]>;
787 def STRH_POST: AI3sthpo<(outs GPR:$base_wb),
788 (ins GPR:$src, GPR:$base,am3offset:$offset), StMiscFrm,
789 "str", "h $src, [$base], $offset", "$base = $base_wb",
790 [(set GPR:$base_wb, (post_truncsti16 GPR:$src,
791 GPR:$base, am3offset:$offset))]>;
793 def STRB_PRE : AI2stbpr<(outs GPR:$base_wb),
794 (ins GPR:$src, GPR:$base,am2offset:$offset), StFrm,
795 "str", "b $src, [$base, $offset]!", "$base = $base_wb",
796 [(set GPR:$base_wb, (pre_truncsti8 GPR:$src,
797 GPR:$base, am2offset:$offset))]>;
799 def STRB_POST: AI2stbpo<(outs GPR:$base_wb),
800 (ins GPR:$src, GPR:$base,am2offset:$offset), StFrm,
801 "str", "b $src, [$base], $offset", "$base = $base_wb",
802 [(set GPR:$base_wb, (post_truncsti8 GPR:$src,
803 GPR:$base, am2offset:$offset))]>;
805 //===----------------------------------------------------------------------===//
806 // Load / store multiple Instructions.
809 // FIXME: $dst1 should be a def.
811 def LDM : AXI4ld<(outs),
812 (ins addrmode4:$addr, pred:$p, reglist:$dst1, variable_ops),
813 LdStMulFrm, "ldm${p}${addr:submode} $addr, $dst1",
817 def STM : AXI4st<(outs),
818 (ins addrmode4:$addr, pred:$p, reglist:$src1, variable_ops),
819 LdStMulFrm, "stm${p}${addr:submode} $addr, $src1",
822 //===----------------------------------------------------------------------===//
823 // Move Instructions.
826 let neverHasSideEffects = 1 in
827 def MOVr : AsI1<0b1101, (outs GPR:$dst), (ins GPR:$src), DPFrm,
828 "mov", " $dst, $src", []>, UnaryDP;
829 def MOVs : AsI1<0b1101, (outs GPR:$dst), (ins so_reg:$src), DPSoRegFrm,
830 "mov", " $dst, $src", [(set GPR:$dst, so_reg:$src)]>, UnaryDP;
832 let isReMaterializable = 1, isAsCheapAsAMove = 1 in
833 def MOVi : AsI1<0b1101, (outs GPR:$dst), (ins so_imm:$src), DPFrm,
834 "mov", " $dst, $src", [(set GPR:$dst, so_imm:$src)]>, UnaryDP;
836 def MOVrx : AsI1<0b1101, (outs GPR:$dst), (ins GPR:$src), Pseudo,
837 "mov", " $dst, $src, rrx",
838 [(set GPR:$dst, (ARMrrx GPR:$src))]>, UnaryDP;
840 // These aren't really mov instructions, but we have to define them this way
841 // due to flag operands.
843 let Defs = [CPSR] in {
844 def MOVsrl_flag : AI1<0b1101, (outs GPR:$dst), (ins GPR:$src), Pseudo,
845 "mov", "s $dst, $src, lsr #1",
846 [(set GPR:$dst, (ARMsrl_flag GPR:$src))]>, UnaryDP;
847 def MOVsra_flag : AI1<0b1101, (outs GPR:$dst), (ins GPR:$src), Pseudo,
848 "mov", "s $dst, $src, asr #1",
849 [(set GPR:$dst, (ARMsra_flag GPR:$src))]>, UnaryDP;
852 //===----------------------------------------------------------------------===//
853 // Extend Instructions.
858 defm SXTB : AI_unary_rrot<0b01101010,
859 "sxtb", UnOpFrag<(sext_inreg node:$Src, i8)>>;
860 defm SXTH : AI_unary_rrot<0b01101011,
861 "sxth", UnOpFrag<(sext_inreg node:$Src, i16)>>;
863 defm SXTAB : AI_bin_rrot<0b01101010,
864 "sxtab", BinOpFrag<(add node:$LHS, (sext_inreg node:$RHS, i8))>>;
865 defm SXTAH : AI_bin_rrot<0b01101011,
866 "sxtah", BinOpFrag<(add node:$LHS, (sext_inreg node:$RHS,i16))>>;
868 // TODO: SXT(A){B|H}16
872 let AddedComplexity = 16 in {
873 defm UXTB : AI_unary_rrot<0b01101110,
874 "uxtb" , UnOpFrag<(and node:$Src, 0x000000FF)>>;
875 defm UXTH : AI_unary_rrot<0b01101111,
876 "uxth" , UnOpFrag<(and node:$Src, 0x0000FFFF)>>;
877 defm UXTB16 : AI_unary_rrot<0b01101100,
878 "uxtb16", UnOpFrag<(and node:$Src, 0x00FF00FF)>>;
880 def : ARMV6Pat<(and (shl GPR:$Src, (i32 8)), 0xFF00FF),
881 (UXTB16r_rot GPR:$Src, 24)>;
882 def : ARMV6Pat<(and (srl GPR:$Src, (i32 8)), 0xFF00FF),
883 (UXTB16r_rot GPR:$Src, 8)>;
885 defm UXTAB : AI_bin_rrot<0b01101110, "uxtab",
886 BinOpFrag<(add node:$LHS, (and node:$RHS, 0x00FF))>>;
887 defm UXTAH : AI_bin_rrot<0b01101111, "uxtah",
888 BinOpFrag<(add node:$LHS, (and node:$RHS, 0xFFFF))>>;
891 // This isn't safe in general, the add is two 16-bit units, not a 32-bit add.
892 //defm UXTAB16 : xxx<"uxtab16", 0xff00ff>;
894 // TODO: UXT(A){B|H}16
896 //===----------------------------------------------------------------------===//
897 // Arithmetic Instructions.
900 defm ADD : AsI1_bin_irs<0b0100, "add",
901 BinOpFrag<(add node:$LHS, node:$RHS)>, 1>;
902 defm SUB : AsI1_bin_irs<0b0010, "sub",
903 BinOpFrag<(sub node:$LHS, node:$RHS)>>;
905 // ADD and SUB with 's' bit set.
906 defm ADDS : AI1_bin_s_irs<0b0100, "add",
907 BinOpFrag<(addc node:$LHS, node:$RHS)>>;
908 defm SUBS : AI1_bin_s_irs<0b0010, "sub",
909 BinOpFrag<(subc node:$LHS, node:$RHS)>>;
911 defm ADC : AI1_adde_sube_irs<0b0101, "adc",
912 BinOpFrag<(adde node:$LHS, node:$RHS)>, 1>;
913 defm SBC : AI1_adde_sube_irs<0b0110, "sbc",
914 BinOpFrag<(sube node:$LHS, node:$RHS)>>;
916 // These don't define reg/reg forms, because they are handled above.
917 def RSBri : AsI1<0b0011, (outs GPR:$dst), (ins GPR:$a, so_imm:$b), DPFrm,
918 "rsb", " $dst, $a, $b",
919 [(set GPR:$dst, (sub so_imm:$b, GPR:$a))]>;
921 def RSBrs : AsI1<0b0011, (outs GPR:$dst), (ins GPR:$a, so_reg:$b), DPSoRegFrm,
922 "rsb", " $dst, $a, $b",
923 [(set GPR:$dst, (sub so_reg:$b, GPR:$a))]>;
925 // RSB with 's' bit set.
926 let Defs = [CPSR] in {
927 def RSBSri : AI1<0b0011, (outs GPR:$dst), (ins GPR:$a, so_imm:$b), DPFrm,
928 "rsb", "s $dst, $a, $b",
929 [(set GPR:$dst, (subc so_imm:$b, GPR:$a))]>;
930 def RSBSrs : AI1<0b0011, (outs GPR:$dst), (ins GPR:$a, so_reg:$b), DPSoRegFrm,
931 "rsb", "s $dst, $a, $b",
932 [(set GPR:$dst, (subc so_reg:$b, GPR:$a))]>;
935 let Uses = [CPSR] in {
936 def RSCri : AsI1<0b0111, (outs GPR:$dst), (ins GPR:$a, so_imm:$b),
937 DPFrm, "rsc", " $dst, $a, $b",
938 [(set GPR:$dst, (sube so_imm:$b, GPR:$a))]>,
939 Requires<[IsARM, CarryDefIsUnused]>;
940 def RSCrs : AsI1<0b0111, (outs GPR:$dst), (ins GPR:$a, so_reg:$b),
941 DPSoRegFrm, "rsc", " $dst, $a, $b",
942 [(set GPR:$dst, (sube so_reg:$b, GPR:$a))]>,
943 Requires<[IsARM, CarryDefIsUnused]>;
946 // FIXME: Allow these to be predicated.
947 let Defs = [CPSR], Uses = [CPSR] in {
948 def RSCSri : AXI1<0b0111, (outs GPR:$dst), (ins GPR:$a, so_imm:$b),
949 DPFrm, "rscs $dst, $a, $b",
950 [(set GPR:$dst, (sube so_imm:$b, GPR:$a))]>,
951 Requires<[IsARM, CarryDefIsUnused]>;
952 def RSCSrs : AXI1<0b0111, (outs GPR:$dst), (ins GPR:$a, so_reg:$b),
953 DPSoRegFrm, "rscs $dst, $a, $b",
954 [(set GPR:$dst, (sube so_reg:$b, GPR:$a))]>,
955 Requires<[IsARM, CarryDefIsUnused]>;
958 // (sub X, imm) gets canonicalized to (add X, -imm). Match this form.
959 def : ARMPat<(add GPR:$src, so_imm_neg:$imm),
960 (SUBri GPR:$src, so_imm_neg:$imm)>;
962 //def : ARMPat<(addc GPR:$src, so_imm_neg:$imm),
963 // (SUBSri GPR:$src, so_imm_neg:$imm)>;
964 //def : ARMPat<(adde GPR:$src, so_imm_neg:$imm),
965 // (SBCri GPR:$src, so_imm_neg:$imm)>;
967 // Note: These are implemented in C++ code, because they have to generate
968 // ADD/SUBrs instructions, which use a complex pattern that a xform function
970 // (mul X, 2^n+1) -> (add (X << n), X)
971 // (mul X, 2^n-1) -> (rsb X, (X << n))
974 //===----------------------------------------------------------------------===//
975 // Bitwise Instructions.
978 defm AND : AsI1_bin_irs<0b0000, "and",
979 BinOpFrag<(and node:$LHS, node:$RHS)>, 1>;
980 defm ORR : AsI1_bin_irs<0b1100, "orr",
981 BinOpFrag<(or node:$LHS, node:$RHS)>, 1>;
982 defm EOR : AsI1_bin_irs<0b0001, "eor",
983 BinOpFrag<(xor node:$LHS, node:$RHS)>, 1>;
984 defm BIC : AsI1_bin_irs<0b1110, "bic",
985 BinOpFrag<(and node:$LHS, (not node:$RHS))>>;
987 def MVNr : AsI1<0b1111, (outs GPR:$dst), (ins GPR:$src), DPFrm,
988 "mvn", " $dst, $src",
989 [(set GPR:$dst, (not GPR:$src))]>, UnaryDP;
990 def MVNs : AsI1<0b1111, (outs GPR:$dst), (ins so_reg:$src), DPSoRegFrm,
991 "mvn", " $dst, $src",
992 [(set GPR:$dst, (not so_reg:$src))]>, UnaryDP;
993 let isReMaterializable = 1, isAsCheapAsAMove = 1 in
994 def MVNi : AsI1<0b1111, (outs GPR:$dst), (ins so_imm:$imm), DPFrm,
995 "mvn", " $dst, $imm",
996 [(set GPR:$dst, so_imm_not:$imm)]>,UnaryDP;
998 def : ARMPat<(and GPR:$src, so_imm_not:$imm),
999 (BICri GPR:$src, so_imm_not:$imm)>;
1001 //===----------------------------------------------------------------------===//
1002 // Multiply Instructions.
1005 let isCommutable = 1 in
1006 def MUL : AsMul1I<0b0000000, (outs GPR:$dst), (ins GPR:$a, GPR:$b),
1007 "mul", " $dst, $a, $b",
1008 [(set GPR:$dst, (mul GPR:$a, GPR:$b))]>;
1010 def MLA : AsMul1I<0b0000001, (outs GPR:$dst), (ins GPR:$a, GPR:$b, GPR:$c),
1011 "mla", " $dst, $a, $b, $c",
1012 [(set GPR:$dst, (add (mul GPR:$a, GPR:$b), GPR:$c))]>;
1014 // Extra precision multiplies with low / high results
1015 let neverHasSideEffects = 1 in {
1016 let isCommutable = 1 in {
1017 def SMULL : AsMul1I<0b0000110, (outs GPR:$ldst, GPR:$hdst),
1018 (ins GPR:$a, GPR:$b),
1019 "smull", " $ldst, $hdst, $a, $b", []>;
1021 def UMULL : AsMul1I<0b0000100, (outs GPR:$ldst, GPR:$hdst),
1022 (ins GPR:$a, GPR:$b),
1023 "umull", " $ldst, $hdst, $a, $b", []>;
1026 // Multiply + accumulate
1027 def SMLAL : AsMul1I<0b0000111, (outs GPR:$ldst, GPR:$hdst),
1028 (ins GPR:$a, GPR:$b),
1029 "smlal", " $ldst, $hdst, $a, $b", []>;
1031 def UMLAL : AsMul1I<0b0000101, (outs GPR:$ldst, GPR:$hdst),
1032 (ins GPR:$a, GPR:$b),
1033 "umlal", " $ldst, $hdst, $a, $b", []>;
1035 def UMAAL : AMul1I <0b0000010, (outs GPR:$ldst, GPR:$hdst),
1036 (ins GPR:$a, GPR:$b),
1037 "umaal", " $ldst, $hdst, $a, $b", []>,
1038 Requires<[IsARM, HasV6]>;
1039 } // neverHasSideEffects
1041 // Most significant word multiply
1042 def SMMUL : AMul2I <0b0111010, (outs GPR:$dst), (ins GPR:$a, GPR:$b),
1043 "smmul", " $dst, $a, $b",
1044 [(set GPR:$dst, (mulhs GPR:$a, GPR:$b))]>,
1045 Requires<[IsARM, HasV6]> {
1046 let Inst{7-4} = 0b0001;
1047 let Inst{15-12} = 0b1111;
1050 def SMMLA : AMul2I <0b0111010, (outs GPR:$dst), (ins GPR:$a, GPR:$b, GPR:$c),
1051 "smmla", " $dst, $a, $b, $c",
1052 [(set GPR:$dst, (add (mulhs GPR:$a, GPR:$b), GPR:$c))]>,
1053 Requires<[IsARM, HasV6]> {
1054 let Inst{7-4} = 0b0001;
1058 def SMMLS : AMul2I <0b0111010, (outs GPR:$dst), (ins GPR:$a, GPR:$b, GPR:$c),
1059 "smmls", " $dst, $a, $b, $c",
1060 [(set GPR:$dst, (sub GPR:$c, (mulhs GPR:$a, GPR:$b)))]>,
1061 Requires<[IsARM, HasV6]> {
1062 let Inst{7-4} = 0b1101;
1065 multiclass AI_smul<string opc, PatFrag opnode> {
1066 def BB : AMulxyI<0b0001011, (outs GPR:$dst), (ins GPR:$a, GPR:$b),
1067 !strconcat(opc, "bb"), " $dst, $a, $b",
1068 [(set GPR:$dst, (opnode (sext_inreg GPR:$a, i16),
1069 (sext_inreg GPR:$b, i16)))]>,
1070 Requires<[IsARM, HasV5TE]> {
1075 def BT : AMulxyI<0b0001011, (outs GPR:$dst), (ins GPR:$a, GPR:$b),
1076 !strconcat(opc, "bt"), " $dst, $a, $b",
1077 [(set GPR:$dst, (opnode (sext_inreg GPR:$a, i16),
1078 (sra GPR:$b, (i32 16))))]>,
1079 Requires<[IsARM, HasV5TE]> {
1084 def TB : AMulxyI<0b0001011, (outs GPR:$dst), (ins GPR:$a, GPR:$b),
1085 !strconcat(opc, "tb"), " $dst, $a, $b",
1086 [(set GPR:$dst, (opnode (sra GPR:$a, (i32 16)),
1087 (sext_inreg GPR:$b, i16)))]>,
1088 Requires<[IsARM, HasV5TE]> {
1093 def TT : AMulxyI<0b0001011, (outs GPR:$dst), (ins GPR:$a, GPR:$b),
1094 !strconcat(opc, "tt"), " $dst, $a, $b",
1095 [(set GPR:$dst, (opnode (sra GPR:$a, (i32 16)),
1096 (sra GPR:$b, (i32 16))))]>,
1097 Requires<[IsARM, HasV5TE]> {
1102 def WB : AMulxyI<0b0001001, (outs GPR:$dst), (ins GPR:$a, GPR:$b),
1103 !strconcat(opc, "wb"), " $dst, $a, $b",
1104 [(set GPR:$dst, (sra (opnode GPR:$a,
1105 (sext_inreg GPR:$b, i16)), (i32 16)))]>,
1106 Requires<[IsARM, HasV5TE]> {
1111 def WT : AMulxyI<0b0001001, (outs GPR:$dst), (ins GPR:$a, GPR:$b),
1112 !strconcat(opc, "wt"), " $dst, $a, $b",
1113 [(set GPR:$dst, (sra (opnode GPR:$a,
1114 (sra GPR:$b, (i32 16))), (i32 16)))]>,
1115 Requires<[IsARM, HasV5TE]> {
1122 multiclass AI_smla<string opc, PatFrag opnode> {
1123 def BB : AMulxyI<0b0001000, (outs GPR:$dst), (ins GPR:$a, GPR:$b, GPR:$acc),
1124 !strconcat(opc, "bb"), " $dst, $a, $b, $acc",
1125 [(set GPR:$dst, (add GPR:$acc,
1126 (opnode (sext_inreg GPR:$a, i16),
1127 (sext_inreg GPR:$b, i16))))]>,
1128 Requires<[IsARM, HasV5TE]> {
1133 def BT : AMulxyI<0b0001000, (outs GPR:$dst), (ins GPR:$a, GPR:$b, GPR:$acc),
1134 !strconcat(opc, "bt"), " $dst, $a, $b, $acc",
1135 [(set GPR:$dst, (add GPR:$acc, (opnode (sext_inreg GPR:$a, i16),
1136 (sra GPR:$b, (i32 16)))))]>,
1137 Requires<[IsARM, HasV5TE]> {
1142 def TB : AMulxyI<0b0001000, (outs GPR:$dst), (ins GPR:$a, GPR:$b, GPR:$acc),
1143 !strconcat(opc, "tb"), " $dst, $a, $b, $acc",
1144 [(set GPR:$dst, (add GPR:$acc, (opnode (sra GPR:$a, (i32 16)),
1145 (sext_inreg GPR:$b, i16))))]>,
1146 Requires<[IsARM, HasV5TE]> {
1151 def TT : AMulxyI<0b0001000, (outs GPR:$dst), (ins GPR:$a, GPR:$b, GPR:$acc),
1152 !strconcat(opc, "tt"), " $dst, $a, $b, $acc",
1153 [(set GPR:$dst, (add GPR:$acc, (opnode (sra GPR:$a, (i32 16)),
1154 (sra GPR:$b, (i32 16)))))]>,
1155 Requires<[IsARM, HasV5TE]> {
1160 def WB : AMulxyI<0b0001001, (outs GPR:$dst), (ins GPR:$a, GPR:$b, GPR:$acc),
1161 !strconcat(opc, "wb"), " $dst, $a, $b, $acc",
1162 [(set GPR:$dst, (add GPR:$acc, (sra (opnode GPR:$a,
1163 (sext_inreg GPR:$b, i16)), (i32 16))))]>,
1164 Requires<[IsARM, HasV5TE]> {
1169 def WT : AMulxyI<0b0001001, (outs GPR:$dst), (ins GPR:$a, GPR:$b, GPR:$acc),
1170 !strconcat(opc, "wt"), " $dst, $a, $b, $acc",
1171 [(set GPR:$dst, (add GPR:$acc, (sra (opnode GPR:$a,
1172 (sra GPR:$b, (i32 16))), (i32 16))))]>,
1173 Requires<[IsARM, HasV5TE]> {
1179 defm SMUL : AI_smul<"smul", BinOpFrag<(mul node:$LHS, node:$RHS)>>;
1180 defm SMLA : AI_smla<"smla", BinOpFrag<(mul node:$LHS, node:$RHS)>>;
1182 // TODO: Halfword multiple accumulate long: SMLAL<x><y>
1183 // TODO: Dual halfword multiple: SMUAD, SMUSD, SMLAD, SMLSD, SMLALD, SMLSLD
1185 //===----------------------------------------------------------------------===//
1186 // Misc. Arithmetic Instructions.
1189 def CLZ : AMiscA1I<0b000010110, (outs GPR:$dst), (ins GPR:$src),
1190 "clz", " $dst, $src",
1191 [(set GPR:$dst, (ctlz GPR:$src))]>, Requires<[IsARM, HasV5T]> {
1192 let Inst{7-4} = 0b0001;
1193 let Inst{11-8} = 0b1111;
1194 let Inst{19-16} = 0b1111;
1197 def REV : AMiscA1I<0b01101011, (outs GPR:$dst), (ins GPR:$src),
1198 "rev", " $dst, $src",
1199 [(set GPR:$dst, (bswap GPR:$src))]>, Requires<[IsARM, HasV6]> {
1200 let Inst{7-4} = 0b0011;
1201 let Inst{11-8} = 0b1111;
1202 let Inst{19-16} = 0b1111;
1205 def REV16 : AMiscA1I<0b01101011, (outs GPR:$dst), (ins GPR:$src),
1206 "rev16", " $dst, $src",
1208 (or (and (srl GPR:$src, (i32 8)), 0xFF),
1209 (or (and (shl GPR:$src, (i32 8)), 0xFF00),
1210 (or (and (srl GPR:$src, (i32 8)), 0xFF0000),
1211 (and (shl GPR:$src, (i32 8)), 0xFF000000)))))]>,
1212 Requires<[IsARM, HasV6]> {
1213 let Inst{7-4} = 0b1011;
1214 let Inst{11-8} = 0b1111;
1215 let Inst{19-16} = 0b1111;
1218 def REVSH : AMiscA1I<0b01101111, (outs GPR:$dst), (ins GPR:$src),
1219 "revsh", " $dst, $src",
1222 (or (srl (and GPR:$src, 0xFF00), (i32 8)),
1223 (shl GPR:$src, (i32 8))), i16))]>,
1224 Requires<[IsARM, HasV6]> {
1225 let Inst{7-4} = 0b1011;
1226 let Inst{11-8} = 0b1111;
1227 let Inst{19-16} = 0b1111;
1230 def PKHBT : AMiscA1I<0b01101000, (outs GPR:$dst),
1231 (ins GPR:$src1, GPR:$src2, i32imm:$shamt),
1232 "pkhbt", " $dst, $src1, $src2, LSL $shamt",
1233 [(set GPR:$dst, (or (and GPR:$src1, 0xFFFF),
1234 (and (shl GPR:$src2, (i32 imm:$shamt)),
1236 Requires<[IsARM, HasV6]> {
1237 let Inst{6-4} = 0b001;
1240 // Alternate cases for PKHBT where identities eliminate some nodes.
1241 def : ARMV6Pat<(or (and GPR:$src1, 0xFFFF), (and GPR:$src2, 0xFFFF0000)),
1242 (PKHBT GPR:$src1, GPR:$src2, 0)>;
1243 def : ARMV6Pat<(or (and GPR:$src1, 0xFFFF), (shl GPR:$src2, imm16_31:$shamt)),
1244 (PKHBT GPR:$src1, GPR:$src2, imm16_31:$shamt)>;
1247 def PKHTB : AMiscA1I<0b01101000, (outs GPR:$dst),
1248 (ins GPR:$src1, GPR:$src2, i32imm:$shamt),
1249 "pkhtb", " $dst, $src1, $src2, ASR $shamt",
1250 [(set GPR:$dst, (or (and GPR:$src1, 0xFFFF0000),
1251 (and (sra GPR:$src2, imm16_31:$shamt),
1252 0xFFFF)))]>, Requires<[IsARM, HasV6]> {
1253 let Inst{6-4} = 0b101;
1256 // Alternate cases for PKHTB where identities eliminate some nodes. Note that
1257 // a shift amount of 0 is *not legal* here, it is PKHBT instead.
1258 def : ARMV6Pat<(or (and GPR:$src1, 0xFFFF0000), (srl GPR:$src2, (i32 16))),
1259 (PKHTB GPR:$src1, GPR:$src2, 16)>;
1260 def : ARMV6Pat<(or (and GPR:$src1, 0xFFFF0000),
1261 (and (srl GPR:$src2, imm1_15:$shamt), 0xFFFF)),
1262 (PKHTB GPR:$src1, GPR:$src2, imm1_15:$shamt)>;
1264 //===----------------------------------------------------------------------===//
1265 // Comparison Instructions...
1268 defm CMP : AI1_cmp_irs<0b1010, "cmp",
1269 BinOpFrag<(ARMcmp node:$LHS, node:$RHS)>>;
1270 defm CMN : AI1_cmp_irs<0b1011, "cmn",
1271 BinOpFrag<(ARMcmp node:$LHS,(ineg node:$RHS))>>;
1273 // Note that TST/TEQ don't set all the same flags that CMP does!
1274 defm TST : AI1_cmp_irs<0b1000, "tst",
1275 BinOpFrag<(ARMcmpNZ (and node:$LHS, node:$RHS), 0)>, 1>;
1276 defm TEQ : AI1_cmp_irs<0b1001, "teq",
1277 BinOpFrag<(ARMcmpNZ (xor node:$LHS, node:$RHS), 0)>, 1>;
1279 defm CMPnz : AI1_cmp_irs<0b1010, "cmp",
1280 BinOpFrag<(ARMcmpNZ node:$LHS, node:$RHS)>>;
1281 defm CMNnz : AI1_cmp_irs<0b1011, "cmn",
1282 BinOpFrag<(ARMcmpNZ node:$LHS,(ineg node:$RHS))>>;
1284 def : ARMPat<(ARMcmp GPR:$src, so_imm_neg:$imm),
1285 (CMNri GPR:$src, so_imm_neg:$imm)>;
1287 def : ARMPat<(ARMcmpNZ GPR:$src, so_imm_neg:$imm),
1288 (CMNri GPR:$src, so_imm_neg:$imm)>;
1291 // Conditional moves
1292 // FIXME: should be able to write a pattern for ARMcmov, but can't use
1293 // a two-value operand where a dag node expects two operands. :(
1294 def MOVCCr : AI1<0b1101, (outs GPR:$dst), (ins GPR:$false, GPR:$true), DPFrm,
1295 "mov", " $dst, $true",
1296 [/*(set GPR:$dst, (ARMcmov GPR:$false, GPR:$true, imm:$cc, CCR:$ccr))*/]>,
1297 RegConstraint<"$false = $dst">, UnaryDP;
1299 def MOVCCs : AI1<0b1101, (outs GPR:$dst),
1300 (ins GPR:$false, so_reg:$true), DPSoRegFrm,
1301 "mov", " $dst, $true",
1302 [/*(set GPR:$dst, (ARMcmov GPR:$false, so_reg:$true, imm:$cc, CCR:$ccr))*/]>,
1303 RegConstraint<"$false = $dst">, UnaryDP;
1305 def MOVCCi : AI1<0b1101, (outs GPR:$dst),
1306 (ins GPR:$false, so_imm:$true), DPFrm,
1307 "mov", " $dst, $true",
1308 [/*(set GPR:$dst, (ARMcmov GPR:$false, so_imm:$true, imm:$cc, CCR:$ccr))*/]>,
1309 RegConstraint<"$false = $dst">, UnaryDP;
1312 //===----------------------------------------------------------------------===//
1316 // __aeabi_read_tp preserves the registers r1-r3.
1318 Defs = [R0, R12, LR, CPSR] in {
1319 def TPsoft : ABXI<0b1011, (outs), (ins),
1320 "bl __aeabi_read_tp",
1321 [(set R0, ARMthread_pointer)]>;
1324 //===----------------------------------------------------------------------===//
1325 // SJLJ Exception handling intrinsics
1326 // eh_sjlj_setjmp() is a three instruction sequence to store the return
1327 // address and save #0 in R0 for the non-longjmp case.
1328 // Since by its nature we may be coming from some other function to get
1329 // here, and we're using the stack frame for the containing function to
1330 // save/restore registers, we can't keep anything live in regs across
1331 // the eh_sjlj_setjmp(), else it will almost certainly have been tromped upon
1332 // when we get here from a longjmp(). We force everthing out of registers
1333 // except for our own input by listing the relevant registers in Defs. By
1334 // doing so, we also cause the prologue/epilogue code to actively preserve
1335 // all of the callee-saved resgisters, which is exactly what we want.
1337 [ R0, R1, R3, R4, R5, R6, R7, R8, R9, R10, R11, R12, LR,
1338 D0, D2, D3, D4, D5, D6, D7, D8, D9, D10, D11, D12, D13, D14, D15 ] in {
1339 def Int_eh_sjlj_setjmp : XI<(outs), (ins GPR:$src),
1340 AddrModeNone, SizeSpecial, IndexModeNone, Pseudo,
1341 "add r0, pc, #4\n\t"
1342 "str r0, [$src, #+4]\n\t"
1343 "mov r0, #0 @ eh_setjmp", "",
1344 [(set R0, (ARMeh_sjlj_setjmp GPR:$src))]>;
1347 //===----------------------------------------------------------------------===//
1348 // Non-Instruction Patterns
1351 // ConstantPool, GlobalAddress, and JumpTable
1352 def : ARMPat<(ARMWrapper tglobaladdr :$dst), (LEApcrel tglobaladdr :$dst)>;
1353 def : ARMPat<(ARMWrapper tconstpool :$dst), (LEApcrel tconstpool :$dst)>;
1354 def : ARMPat<(ARMWrapperJT tjumptable:$dst, imm:$id),
1355 (LEApcrelJT tjumptable:$dst, imm:$id)>;
1357 // Large immediate handling.
1359 // Two piece so_imms.
1360 let isReMaterializable = 1 in
1361 def MOVi2pieces : AI1x2<(outs GPR:$dst), (ins so_imm2part:$src), Pseudo,
1362 "mov", " $dst, $src",
1363 [(set GPR:$dst, so_imm2part:$src)]>;
1365 def : ARMPat<(or GPR:$LHS, so_imm2part:$RHS),
1366 (ORRri (ORRri GPR:$LHS, (so_imm2part_1 imm:$RHS)),
1367 (so_imm2part_2 imm:$RHS))>;
1368 def : ARMPat<(xor GPR:$LHS, so_imm2part:$RHS),
1369 (EORri (EORri GPR:$LHS, (so_imm2part_1 imm:$RHS)),
1370 (so_imm2part_2 imm:$RHS))>;
1372 // TODO: add,sub,and, 3-instr forms?
1376 def : ARMPat<(ARMcall texternalsym:$func), (BL texternalsym:$func)>,
1377 Requires<[IsNotDarwin]>;
1378 def : ARMPat<(ARMcall texternalsym:$func), (BLr9 texternalsym:$func)>,
1379 Requires<[IsDarwin]>;
1381 // zextload i1 -> zextload i8
1382 def : ARMPat<(zextloadi1 addrmode2:$addr), (LDRB addrmode2:$addr)>;
1384 // extload -> zextload
1385 def : ARMPat<(extloadi1 addrmode2:$addr), (LDRB addrmode2:$addr)>;
1386 def : ARMPat<(extloadi8 addrmode2:$addr), (LDRB addrmode2:$addr)>;
1387 def : ARMPat<(extloadi16 addrmode3:$addr), (LDRH addrmode3:$addr)>;
1389 def : ARMPat<(extloadi8 addrmodepc:$addr), (PICLDRB addrmodepc:$addr)>;
1390 def : ARMPat<(extloadi16 addrmodepc:$addr), (PICLDRH addrmodepc:$addr)>;
1393 def : ARMV5TEPat<(mul (sra (shl GPR:$a, (i32 16)), (i32 16)),
1394 (sra (shl GPR:$b, (i32 16)), (i32 16))),
1395 (SMULBB GPR:$a, GPR:$b)>;
1396 def : ARMV5TEPat<(mul sext_16_node:$a, sext_16_node:$b),
1397 (SMULBB GPR:$a, GPR:$b)>;
1398 def : ARMV5TEPat<(mul (sra (shl GPR:$a, (i32 16)), (i32 16)),
1399 (sra GPR:$b, (i32 16))),
1400 (SMULBT GPR:$a, GPR:$b)>;
1401 def : ARMV5TEPat<(mul sext_16_node:$a, (sra GPR:$b, (i32 16))),
1402 (SMULBT GPR:$a, GPR:$b)>;
1403 def : ARMV5TEPat<(mul (sra GPR:$a, (i32 16)),
1404 (sra (shl GPR:$b, (i32 16)), (i32 16))),
1405 (SMULTB GPR:$a, GPR:$b)>;
1406 def : ARMV5TEPat<(mul (sra GPR:$a, (i32 16)), sext_16_node:$b),
1407 (SMULTB GPR:$a, GPR:$b)>;
1408 def : ARMV5TEPat<(sra (mul GPR:$a, (sra (shl GPR:$b, (i32 16)), (i32 16))),
1410 (SMULWB GPR:$a, GPR:$b)>;
1411 def : ARMV5TEPat<(sra (mul GPR:$a, sext_16_node:$b), (i32 16)),
1412 (SMULWB GPR:$a, GPR:$b)>;
1414 def : ARMV5TEPat<(add GPR:$acc,
1415 (mul (sra (shl GPR:$a, (i32 16)), (i32 16)),
1416 (sra (shl GPR:$b, (i32 16)), (i32 16)))),
1417 (SMLABB GPR:$a, GPR:$b, GPR:$acc)>;
1418 def : ARMV5TEPat<(add GPR:$acc,
1419 (mul sext_16_node:$a, sext_16_node:$b)),
1420 (SMLABB GPR:$a, GPR:$b, GPR:$acc)>;
1421 def : ARMV5TEPat<(add GPR:$acc,
1422 (mul (sra (shl GPR:$a, (i32 16)), (i32 16)),
1423 (sra GPR:$b, (i32 16)))),
1424 (SMLABT GPR:$a, GPR:$b, GPR:$acc)>;
1425 def : ARMV5TEPat<(add GPR:$acc,
1426 (mul sext_16_node:$a, (sra GPR:$b, (i32 16)))),
1427 (SMLABT GPR:$a, GPR:$b, GPR:$acc)>;
1428 def : ARMV5TEPat<(add GPR:$acc,
1429 (mul (sra GPR:$a, (i32 16)),
1430 (sra (shl GPR:$b, (i32 16)), (i32 16)))),
1431 (SMLATB GPR:$a, GPR:$b, GPR:$acc)>;
1432 def : ARMV5TEPat<(add GPR:$acc,
1433 (mul (sra GPR:$a, (i32 16)), sext_16_node:$b)),
1434 (SMLATB GPR:$a, GPR:$b, GPR:$acc)>;
1435 def : ARMV5TEPat<(add GPR:$acc,
1436 (sra (mul GPR:$a, (sra (shl GPR:$b, (i32 16)), (i32 16))),
1438 (SMLAWB GPR:$a, GPR:$b, GPR:$acc)>;
1439 def : ARMV5TEPat<(add GPR:$acc,
1440 (sra (mul GPR:$a, sext_16_node:$b), (i32 16))),
1441 (SMLAWB GPR:$a, GPR:$b, GPR:$acc)>;
1443 //===----------------------------------------------------------------------===//
1447 include "ARMInstrThumb.td"
1449 //===----------------------------------------------------------------------===//
1453 include "ARMInstrThumb2.td"
1455 //===----------------------------------------------------------------------===//
1456 // Floating Point Support
1459 include "ARMInstrVFP.td"
1461 //===----------------------------------------------------------------------===//
1462 // Advanced SIMD (NEON) Support
1465 include "ARMInstrNEON.td"