1 //===- ARMInstrInfo.td - Target Description for ARM Target -*- tablegen -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file describes the ARM instructions in TableGen format.
12 //===----------------------------------------------------------------------===//
14 //===----------------------------------------------------------------------===//
15 // ARM specific DAG Nodes.
19 def SDT_ARMCallSeqStart : SDCallSeqStart<[ SDTCisVT<0, i32> ]>;
20 def SDT_ARMCallSeqEnd : SDCallSeqEnd<[ SDTCisVT<0, i32>, SDTCisVT<1, i32> ]>;
22 def SDT_ARMSaveCallPC : SDTypeProfile<0, 1, []>;
24 def SDT_ARMcall : SDTypeProfile<0, -1, [SDTCisPtrTy<0>]>;
26 def SDT_ARMCMov : SDTypeProfile<1, 3,
27 [SDTCisSameAs<0, 1>, SDTCisSameAs<0, 2>,
30 def SDT_ARMBrcond : SDTypeProfile<0, 2,
31 [SDTCisVT<0, OtherVT>, SDTCisVT<1, i32>]>;
33 def SDT_ARMBrJT : SDTypeProfile<0, 3,
34 [SDTCisPtrTy<0>, SDTCisVT<1, i32>,
37 def SDT_ARMBr2JT : SDTypeProfile<0, 4,
38 [SDTCisPtrTy<0>, SDTCisVT<1, i32>,
39 SDTCisVT<2, i32>, SDTCisVT<3, i32>]>;
41 def SDT_ARMBCC_i64 : SDTypeProfile<0, 6,
43 SDTCisVT<1, i32>, SDTCisVT<2, i32>,
44 SDTCisVT<3, i32>, SDTCisVT<4, i32>,
45 SDTCisVT<5, OtherVT>]>;
47 def SDT_ARMAnd : SDTypeProfile<1, 2,
48 [SDTCisVT<0, i32>, SDTCisVT<1, i32>,
51 def SDT_ARMCmp : SDTypeProfile<0, 2, [SDTCisSameAs<0, 1>]>;
53 def SDT_ARMPICAdd : SDTypeProfile<1, 2, [SDTCisSameAs<0, 1>,
54 SDTCisPtrTy<1>, SDTCisVT<2, i32>]>;
56 def SDT_ARMThreadPointer : SDTypeProfile<1, 0, [SDTCisPtrTy<0>]>;
57 def SDT_ARMEH_SJLJ_Setjmp : SDTypeProfile<1, 2, [SDTCisInt<0>, SDTCisPtrTy<1>,
59 def SDT_ARMEH_SJLJ_Longjmp: SDTypeProfile<0, 2, [SDTCisPtrTy<0>, SDTCisInt<1>]>;
61 def SDT_ARMEH_SJLJ_DispatchSetup: SDTypeProfile<0, 1, [SDTCisPtrTy<0>]>;
63 def SDT_ARMMEMBARRIER : SDTypeProfile<0, 1, [SDTCisInt<0>]>;
65 def SDT_ARMTCRET : SDTypeProfile<0, 1, [SDTCisPtrTy<0>]>;
67 def SDT_ARMBFI : SDTypeProfile<1, 3, [SDTCisVT<0, i32>, SDTCisVT<1, i32>,
68 SDTCisVT<2, i32>, SDTCisVT<3, i32>]>;
71 def ARMWrapper : SDNode<"ARMISD::Wrapper", SDTIntUnaryOp>;
72 def ARMWrapperDYN : SDNode<"ARMISD::WrapperDYN", SDTIntUnaryOp>;
73 def ARMWrapperPIC : SDNode<"ARMISD::WrapperPIC", SDTIntUnaryOp>;
74 def ARMWrapperJT : SDNode<"ARMISD::WrapperJT", SDTIntBinOp>;
76 def ARMcallseq_start : SDNode<"ISD::CALLSEQ_START", SDT_ARMCallSeqStart,
77 [SDNPHasChain, SDNPOutGlue]>;
78 def ARMcallseq_end : SDNode<"ISD::CALLSEQ_END", SDT_ARMCallSeqEnd,
79 [SDNPHasChain, SDNPOptInGlue, SDNPOutGlue]>;
81 def ARMcall : SDNode<"ARMISD::CALL", SDT_ARMcall,
82 [SDNPHasChain, SDNPOptInGlue, SDNPOutGlue,
84 def ARMcall_pred : SDNode<"ARMISD::CALL_PRED", SDT_ARMcall,
85 [SDNPHasChain, SDNPOptInGlue, SDNPOutGlue,
87 def ARMcall_nolink : SDNode<"ARMISD::CALL_NOLINK", SDT_ARMcall,
88 [SDNPHasChain, SDNPOptInGlue, SDNPOutGlue,
91 def ARMretflag : SDNode<"ARMISD::RET_FLAG", SDTNone,
92 [SDNPHasChain, SDNPOptInGlue]>;
94 def ARMcmov : SDNode<"ARMISD::CMOV", SDT_ARMCMov,
97 def ARMbrcond : SDNode<"ARMISD::BRCOND", SDT_ARMBrcond,
98 [SDNPHasChain, SDNPInGlue, SDNPOutGlue]>;
100 def ARMbrjt : SDNode<"ARMISD::BR_JT", SDT_ARMBrJT,
102 def ARMbr2jt : SDNode<"ARMISD::BR2_JT", SDT_ARMBr2JT,
105 def ARMBcci64 : SDNode<"ARMISD::BCC_i64", SDT_ARMBCC_i64,
108 def ARMcmp : SDNode<"ARMISD::CMP", SDT_ARMCmp,
111 def ARMcmpZ : SDNode<"ARMISD::CMPZ", SDT_ARMCmp,
112 [SDNPOutGlue, SDNPCommutative]>;
114 def ARMpic_add : SDNode<"ARMISD::PIC_ADD", SDT_ARMPICAdd>;
116 def ARMsrl_flag : SDNode<"ARMISD::SRL_FLAG", SDTIntUnaryOp, [SDNPOutGlue]>;
117 def ARMsra_flag : SDNode<"ARMISD::SRA_FLAG", SDTIntUnaryOp, [SDNPOutGlue]>;
118 def ARMrrx : SDNode<"ARMISD::RRX" , SDTIntUnaryOp, [SDNPInGlue ]>;
120 def ARMthread_pointer: SDNode<"ARMISD::THREAD_POINTER", SDT_ARMThreadPointer>;
121 def ARMeh_sjlj_setjmp: SDNode<"ARMISD::EH_SJLJ_SETJMP",
122 SDT_ARMEH_SJLJ_Setjmp, [SDNPHasChain]>;
123 def ARMeh_sjlj_longjmp: SDNode<"ARMISD::EH_SJLJ_LONGJMP",
124 SDT_ARMEH_SJLJ_Longjmp, [SDNPHasChain]>;
125 def ARMeh_sjlj_dispatchsetup: SDNode<"ARMISD::EH_SJLJ_DISPATCHSETUP",
126 SDT_ARMEH_SJLJ_DispatchSetup, [SDNPHasChain]>;
129 def ARMMemBarrier : SDNode<"ARMISD::MEMBARRIER", SDT_ARMMEMBARRIER,
131 def ARMMemBarrierMCR : SDNode<"ARMISD::MEMBARRIER_MCR", SDT_ARMMEMBARRIER,
133 def ARMPreload : SDNode<"ARMISD::PRELOAD", SDTPrefetch,
134 [SDNPHasChain, SDNPMayLoad, SDNPMayStore]>;
136 def ARMrbit : SDNode<"ARMISD::RBIT", SDTIntUnaryOp>;
138 def ARMtcret : SDNode<"ARMISD::TC_RETURN", SDT_ARMTCRET,
139 [SDNPHasChain, SDNPOptInGlue, SDNPVariadic]>;
142 def ARMbfi : SDNode<"ARMISD::BFI", SDT_ARMBFI>;
144 //===----------------------------------------------------------------------===//
145 // ARM Instruction Predicate Definitions.
147 def HasV4T : Predicate<"Subtarget->hasV4TOps()">, AssemblerPredicate;
148 def NoV4T : Predicate<"!Subtarget->hasV4TOps()">;
149 def HasV5T : Predicate<"Subtarget->hasV5TOps()">;
150 def HasV5TE : Predicate<"Subtarget->hasV5TEOps()">, AssemblerPredicate;
151 def HasV6 : Predicate<"Subtarget->hasV6Ops()">, AssemblerPredicate;
152 def NoV6 : Predicate<"!Subtarget->hasV6Ops()">;
153 def HasV6T2 : Predicate<"Subtarget->hasV6T2Ops()">, AssemblerPredicate;
154 def NoV6T2 : Predicate<"!Subtarget->hasV6T2Ops()">;
155 def HasV7 : Predicate<"Subtarget->hasV7Ops()">, AssemblerPredicate;
156 def NoVFP : Predicate<"!Subtarget->hasVFP2()">;
157 def HasVFP2 : Predicate<"Subtarget->hasVFP2()">, AssemblerPredicate;
158 def HasVFP3 : Predicate<"Subtarget->hasVFP3()">, AssemblerPredicate;
159 def HasNEON : Predicate<"Subtarget->hasNEON()">, AssemblerPredicate;
160 def HasFP16 : Predicate<"Subtarget->hasFP16()">, AssemblerPredicate;
161 def HasDivide : Predicate<"Subtarget->hasDivide()">, AssemblerPredicate;
162 def HasT2ExtractPack : Predicate<"Subtarget->hasT2ExtractPack()">,
164 def HasDB : Predicate<"Subtarget->hasDataBarrier()">,
166 def HasMP : Predicate<"Subtarget->hasMPExtension()">,
168 def UseNEONForFP : Predicate<"Subtarget->useNEONForSinglePrecisionFP()">;
169 def DontUseNEONForFP : Predicate<"!Subtarget->useNEONForSinglePrecisionFP()">;
170 def IsThumb : Predicate<"Subtarget->isThumb()">, AssemblerPredicate;
171 def IsThumb1Only : Predicate<"Subtarget->isThumb1Only()">;
172 def IsThumb2 : Predicate<"Subtarget->isThumb2()">, AssemblerPredicate;
173 def IsARM : Predicate<"!Subtarget->isThumb()">, AssemblerPredicate;
174 def IsDarwin : Predicate<"Subtarget->isTargetDarwin()">;
175 def IsNotDarwin : Predicate<"!Subtarget->isTargetDarwin()">;
177 // FIXME: Eventually this will be just "hasV6T2Ops".
178 def UseMovt : Predicate<"Subtarget->useMovt()">;
179 def DontUseMovt : Predicate<"!Subtarget->useMovt()">;
180 def UseFPVMLx : Predicate<"Subtarget->useFPVMLx()">;
182 //===----------------------------------------------------------------------===//
183 // ARM Flag Definitions.
185 class RegConstraint<string C> {
186 string Constraints = C;
189 //===----------------------------------------------------------------------===//
190 // ARM specific transformation functions and pattern fragments.
193 // so_imm_neg_XFORM - Return a so_imm value packed into the format described for
194 // so_imm_neg def below.
195 def so_imm_neg_XFORM : SDNodeXForm<imm, [{
196 return CurDAG->getTargetConstant(-(int)N->getZExtValue(), MVT::i32);
199 // so_imm_not_XFORM - Return a so_imm value packed into the format described for
200 // so_imm_not def below.
201 def so_imm_not_XFORM : SDNodeXForm<imm, [{
202 return CurDAG->getTargetConstant(~(int)N->getZExtValue(), MVT::i32);
205 /// imm1_15 predicate - True if the 32-bit immediate is in the range [1,15].
206 def imm1_15 : PatLeaf<(i32 imm), [{
207 return (int32_t)N->getZExtValue() >= 1 && (int32_t)N->getZExtValue() < 16;
210 /// imm16_31 predicate - True if the 32-bit immediate is in the range [16,31].
211 def imm16_31 : PatLeaf<(i32 imm), [{
212 return (int32_t)N->getZExtValue() >= 16 && (int32_t)N->getZExtValue() < 32;
217 return ARM_AM::getSOImmVal(-(uint32_t)N->getZExtValue()) != -1;
218 }], so_imm_neg_XFORM>;
222 return ARM_AM::getSOImmVal(~(uint32_t)N->getZExtValue()) != -1;
223 }], so_imm_not_XFORM>;
225 // sext_16_node predicate - True if the SDNode is sign-extended 16 or more bits.
226 def sext_16_node : PatLeaf<(i32 GPR:$a), [{
227 return CurDAG->ComputeNumSignBits(SDValue(N,0)) >= 17;
230 /// Split a 32-bit immediate into two 16 bit parts.
231 def hi16 : SDNodeXForm<imm, [{
232 return CurDAG->getTargetConstant((uint32_t)N->getZExtValue() >> 16, MVT::i32);
235 def lo16AllZero : PatLeaf<(i32 imm), [{
236 // Returns true if all low 16-bits are 0.
237 return (((uint32_t)N->getZExtValue()) & 0xFFFFUL) == 0;
240 /// imm0_65535 predicate - True if the 32-bit immediate is in the range
242 def imm0_65535 : PatLeaf<(i32 imm), [{
243 return (uint32_t)N->getZExtValue() < 65536;
246 class BinOpFrag<dag res> : PatFrag<(ops node:$LHS, node:$RHS), res>;
247 class UnOpFrag <dag res> : PatFrag<(ops node:$Src), res>;
249 /// adde and sube predicates - True based on whether the carry flag output
250 /// will be needed or not.
251 def adde_dead_carry :
252 PatFrag<(ops node:$LHS, node:$RHS), (adde node:$LHS, node:$RHS),
253 [{return !N->hasAnyUseOfValue(1);}]>;
254 def sube_dead_carry :
255 PatFrag<(ops node:$LHS, node:$RHS), (sube node:$LHS, node:$RHS),
256 [{return !N->hasAnyUseOfValue(1);}]>;
257 def adde_live_carry :
258 PatFrag<(ops node:$LHS, node:$RHS), (adde node:$LHS, node:$RHS),
259 [{return N->hasAnyUseOfValue(1);}]>;
260 def sube_live_carry :
261 PatFrag<(ops node:$LHS, node:$RHS), (sube node:$LHS, node:$RHS),
262 [{return N->hasAnyUseOfValue(1);}]>;
264 // An 'and' node with a single use.
265 def and_su : PatFrag<(ops node:$lhs, node:$rhs), (and node:$lhs, node:$rhs), [{
266 return N->hasOneUse();
269 // An 'xor' node with a single use.
270 def xor_su : PatFrag<(ops node:$lhs, node:$rhs), (xor node:$lhs, node:$rhs), [{
271 return N->hasOneUse();
274 // An 'fmul' node with a single use.
275 def fmul_su : PatFrag<(ops node:$lhs, node:$rhs), (fmul node:$lhs, node:$rhs),[{
276 return N->hasOneUse();
279 // An 'fadd' node which checks for single non-hazardous use.
280 def fadd_mlx : PatFrag<(ops node:$lhs, node:$rhs),(fadd node:$lhs, node:$rhs),[{
281 return hasNoVMLxHazardUse(N);
284 // An 'fsub' node which checks for single non-hazardous use.
285 def fsub_mlx : PatFrag<(ops node:$lhs, node:$rhs),(fsub node:$lhs, node:$rhs),[{
286 return hasNoVMLxHazardUse(N);
289 //===----------------------------------------------------------------------===//
290 // Operand Definitions.
294 // FIXME: rename brtarget to t2_brtarget
295 def brtarget : Operand<OtherVT> {
296 let EncoderMethod = "getBranchTargetOpValue";
299 // FIXME: get rid of this one?
300 def uncondbrtarget : Operand<OtherVT> {
301 let EncoderMethod = "getUnconditionalBranchTargetOpValue";
304 // Branch target for ARM. Handles conditional/unconditional
305 def br_target : Operand<OtherVT> {
306 let EncoderMethod = "getARMBranchTargetOpValue";
310 // FIXME: rename bltarget to t2_bl_target?
311 def bltarget : Operand<i32> {
312 // Encoded the same as branch targets.
313 let EncoderMethod = "getBranchTargetOpValue";
316 // Call target for ARM. Handles conditional/unconditional
317 // FIXME: rename bl_target to t2_bltarget?
318 def bl_target : Operand<i32> {
319 // Encoded the same as branch targets.
320 let EncoderMethod = "getARMBranchTargetOpValue";
324 // A list of registers separated by comma. Used by load/store multiple.
325 def RegListAsmOperand : AsmOperandClass {
326 let Name = "RegList";
327 let SuperClasses = [];
330 def DPRRegListAsmOperand : AsmOperandClass {
331 let Name = "DPRRegList";
332 let SuperClasses = [];
335 def SPRRegListAsmOperand : AsmOperandClass {
336 let Name = "SPRRegList";
337 let SuperClasses = [];
340 def reglist : Operand<i32> {
341 let EncoderMethod = "getRegisterListOpValue";
342 let ParserMatchClass = RegListAsmOperand;
343 let PrintMethod = "printRegisterList";
346 def dpr_reglist : Operand<i32> {
347 let EncoderMethod = "getRegisterListOpValue";
348 let ParserMatchClass = DPRRegListAsmOperand;
349 let PrintMethod = "printRegisterList";
352 def spr_reglist : Operand<i32> {
353 let EncoderMethod = "getRegisterListOpValue";
354 let ParserMatchClass = SPRRegListAsmOperand;
355 let PrintMethod = "printRegisterList";
358 // An operand for the CONSTPOOL_ENTRY pseudo-instruction.
359 def cpinst_operand : Operand<i32> {
360 let PrintMethod = "printCPInstOperand";
364 def pclabel : Operand<i32> {
365 let PrintMethod = "printPCLabel";
368 // ADR instruction labels.
369 def adrlabel : Operand<i32> {
370 let EncoderMethod = "getAdrLabelOpValue";
373 def neon_vcvt_imm32 : Operand<i32> {
374 let EncoderMethod = "getNEONVcvtImm32OpValue";
377 // rot_imm: An integer that encodes a rotate amount. Must be 8, 16, or 24.
378 def rot_imm : Operand<i32>, PatLeaf<(i32 imm), [{
379 int32_t v = (int32_t)N->getZExtValue();
380 return v == 8 || v == 16 || v == 24; }]> {
381 let EncoderMethod = "getRotImmOpValue";
384 def ShifterAsmOperand : AsmOperandClass {
385 let Name = "Shifter";
386 let SuperClasses = [];
389 // shift_imm: An integer that encodes a shift amount and the type of shift
390 // (currently either asr or lsl) using the same encoding used for the
391 // immediates in so_reg operands.
392 def shift_imm : Operand<i32> {
393 let PrintMethod = "printShiftImmOperand";
394 let ParserMatchClass = ShifterAsmOperand;
397 // shifter_operand operands: so_reg and so_imm.
398 def so_reg : Operand<i32>, // reg reg imm
399 ComplexPattern<i32, 3, "SelectShifterOperandReg",
400 [shl,srl,sra,rotr]> {
401 let EncoderMethod = "getSORegOpValue";
402 let PrintMethod = "printSORegOperand";
403 let MIOperandInfo = (ops GPR, GPR, shift_imm);
405 def shift_so_reg : Operand<i32>, // reg reg imm
406 ComplexPattern<i32, 3, "SelectShiftShifterOperandReg",
407 [shl,srl,sra,rotr]> {
408 let EncoderMethod = "getSORegOpValue";
409 let PrintMethod = "printSORegOperand";
410 let MIOperandInfo = (ops GPR, GPR, shift_imm);
413 // so_imm - Match a 32-bit shifter_operand immediate operand, which is an
414 // 8-bit immediate rotated by an arbitrary number of bits.
415 def so_imm : Operand<i32>, PatLeaf<(imm), [{ return Pred_so_imm(N); }]> {
416 let EncoderMethod = "getSOImmOpValue";
417 let PrintMethod = "printSOImmOperand";
420 // Break so_imm's up into two pieces. This handles immediates with up to 16
421 // bits set in them. This uses so_imm2part to match and so_imm2part_[12] to
422 // get the first/second pieces.
423 def so_imm2part : PatLeaf<(imm), [{
424 return ARM_AM::isSOImmTwoPartVal((unsigned)N->getZExtValue());
427 /// arm_i32imm - True for +V6T2, or true only if so_imm2part is true.
429 def arm_i32imm : PatLeaf<(imm), [{
430 if (Subtarget->hasV6T2Ops())
432 return ARM_AM::isSOImmTwoPartVal((unsigned)N->getZExtValue());
435 /// imm0_31 predicate - True if the 32-bit immediate is in the range [0,31].
436 def imm0_31 : Operand<i32>, PatLeaf<(imm), [{
437 return (int32_t)N->getZExtValue() < 32;
440 /// imm0_31_m1 - Matches and prints like imm0_31, but encodes as 'value - 1'.
441 def imm0_31_m1 : Operand<i32>, PatLeaf<(imm), [{
442 return (int32_t)N->getZExtValue() < 32;
444 let EncoderMethod = "getImmMinusOneOpValue";
447 // i32imm_hilo16 - For movt/movw - sets the MC Encoder method.
448 // The imm is split into imm{15-12}, imm{11-0}
450 def i32imm_hilo16 : Operand<i32> {
451 let EncoderMethod = "getHiLo16ImmOpValue";
454 /// bf_inv_mask_imm predicate - An AND mask to clear an arbitrary width bitfield
456 def bf_inv_mask_imm : Operand<i32>,
458 return ARM::isBitFieldInvertedMask(N->getZExtValue());
460 let EncoderMethod = "getBitfieldInvertedMaskOpValue";
461 let PrintMethod = "printBitfieldInvMaskImmOperand";
464 /// lsb_pos_imm - position of the lsb bit, used by BFI4p and t2BFI4p
465 def lsb_pos_imm : Operand<i32>, PatLeaf<(imm), [{
466 return isInt<5>(N->getSExtValue());
469 /// width_imm - number of bits to be copied, used by BFI4p and t2BFI4p
470 def width_imm : Operand<i32>, PatLeaf<(imm), [{
471 return N->getSExtValue() > 0 && N->getSExtValue() <= 32;
473 let EncoderMethod = "getMsbOpValue";
476 // Define ARM specific addressing modes.
479 // addrmode_imm12 := reg +/- imm12
481 def addrmode_imm12 : Operand<i32>,
482 ComplexPattern<i32, 2, "SelectAddrModeImm12", []> {
483 // 12-bit immediate operand. Note that instructions using this encode
484 // #0 and #-0 differently. We flag #-0 as the magic value INT32_MIN. All other
485 // immediate values are as normal.
487 let EncoderMethod = "getAddrModeImm12OpValue";
488 let PrintMethod = "printAddrModeImm12Operand";
489 let MIOperandInfo = (ops GPR:$base, i32imm:$offsimm);
491 // ldst_so_reg := reg +/- reg shop imm
493 def ldst_so_reg : Operand<i32>,
494 ComplexPattern<i32, 3, "SelectLdStSOReg", []> {
495 let EncoderMethod = "getLdStSORegOpValue";
496 // FIXME: Simplify the printer
497 let PrintMethod = "printAddrMode2Operand";
498 let MIOperandInfo = (ops GPR:$base, GPR:$offsreg, i32imm:$offsimm);
501 def MemMode2AsmOperand : AsmOperandClass {
502 let Name = "MemMode2";
503 let SuperClasses = [];
504 let ParserMethod = "tryParseMemMode2Operand";
507 // addrmode2 := reg +/- imm12
508 // := reg +/- reg shop imm
510 def addrmode2 : Operand<i32>,
511 ComplexPattern<i32, 3, "SelectAddrMode2", []> {
512 let EncoderMethod = "getAddrMode2OpValue";
513 let PrintMethod = "printAddrMode2Operand";
514 let ParserMatchClass = MemMode2AsmOperand;
515 let MIOperandInfo = (ops GPR:$base, GPR:$offsreg, i32imm:$offsimm);
518 def am2offset : Operand<i32>,
519 ComplexPattern<i32, 2, "SelectAddrMode2Offset",
520 [], [SDNPWantRoot]> {
521 let EncoderMethod = "getAddrMode2OffsetOpValue";
522 let PrintMethod = "printAddrMode2OffsetOperand";
523 let MIOperandInfo = (ops GPR, i32imm);
526 // addrmode3 := reg +/- reg
527 // addrmode3 := reg +/- imm8
529 def addrmode3 : Operand<i32>,
530 ComplexPattern<i32, 3, "SelectAddrMode3", []> {
531 let EncoderMethod = "getAddrMode3OpValue";
532 let PrintMethod = "printAddrMode3Operand";
533 let MIOperandInfo = (ops GPR:$base, GPR:$offsreg, i32imm:$offsimm);
536 def am3offset : Operand<i32>,
537 ComplexPattern<i32, 2, "SelectAddrMode3Offset",
538 [], [SDNPWantRoot]> {
539 let EncoderMethod = "getAddrMode3OffsetOpValue";
540 let PrintMethod = "printAddrMode3OffsetOperand";
541 let MIOperandInfo = (ops GPR, i32imm);
544 // ldstm_mode := {ia, ib, da, db}
546 def ldstm_mode : OptionalDefOperand<OtherVT, (ops i32), (ops (i32 1))> {
547 let EncoderMethod = "getLdStmModeOpValue";
548 let PrintMethod = "printLdStmModeOperand";
551 def MemMode5AsmOperand : AsmOperandClass {
552 let Name = "MemMode5";
553 let SuperClasses = [];
556 // addrmode5 := reg +/- imm8*4
558 def addrmode5 : Operand<i32>,
559 ComplexPattern<i32, 2, "SelectAddrMode5", []> {
560 let PrintMethod = "printAddrMode5Operand";
561 let MIOperandInfo = (ops GPR:$base, i32imm);
562 let ParserMatchClass = MemMode5AsmOperand;
563 let EncoderMethod = "getAddrMode5OpValue";
566 // addrmode6 := reg with optional alignment
568 def addrmode6 : Operand<i32>,
569 ComplexPattern<i32, 2, "SelectAddrMode6", [], [SDNPWantParent]>{
570 let PrintMethod = "printAddrMode6Operand";
571 let MIOperandInfo = (ops GPR:$addr, i32imm);
572 let EncoderMethod = "getAddrMode6AddressOpValue";
575 def am6offset : Operand<i32>,
576 ComplexPattern<i32, 1, "SelectAddrMode6Offset",
577 [], [SDNPWantRoot]> {
578 let PrintMethod = "printAddrMode6OffsetOperand";
579 let MIOperandInfo = (ops GPR);
580 let EncoderMethod = "getAddrMode6OffsetOpValue";
583 // Special version of addrmode6 to handle alignment encoding for VLD-dup
584 // instructions, specifically VLD4-dup.
585 def addrmode6dup : Operand<i32>,
586 ComplexPattern<i32, 2, "SelectAddrMode6", [], [SDNPWantParent]>{
587 let PrintMethod = "printAddrMode6Operand";
588 let MIOperandInfo = (ops GPR:$addr, i32imm);
589 let EncoderMethod = "getAddrMode6DupAddressOpValue";
592 // addrmodepc := pc + reg
594 def addrmodepc : Operand<i32>,
595 ComplexPattern<i32, 2, "SelectAddrModePC", []> {
596 let PrintMethod = "printAddrModePCOperand";
597 let MIOperandInfo = (ops GPR, i32imm);
600 def MemMode7AsmOperand : AsmOperandClass {
601 let Name = "MemMode7";
602 let SuperClasses = [];
606 // Used by load/store exclusive instructions. Useful to enable right assembly
607 // parsing and printing. Not used for any codegen matching.
609 def addrmode7 : Operand<i32> {
610 let PrintMethod = "printAddrMode7Operand";
611 let MIOperandInfo = (ops GPR);
612 let ParserMatchClass = MemMode7AsmOperand;
615 def nohash_imm : Operand<i32> {
616 let PrintMethod = "printNoHashImmediate";
619 def CoprocNumAsmOperand : AsmOperandClass {
620 let Name = "CoprocNum";
621 let SuperClasses = [];
622 let ParserMethod = "tryParseCoprocNumOperand";
625 def CoprocRegAsmOperand : AsmOperandClass {
626 let Name = "CoprocReg";
627 let SuperClasses = [];
628 let ParserMethod = "tryParseCoprocRegOperand";
631 def p_imm : Operand<i32> {
632 let PrintMethod = "printPImmediate";
633 let ParserMatchClass = CoprocNumAsmOperand;
636 def c_imm : Operand<i32> {
637 let PrintMethod = "printCImmediate";
638 let ParserMatchClass = CoprocRegAsmOperand;
641 //===----------------------------------------------------------------------===//
643 include "ARMInstrFormats.td"
645 //===----------------------------------------------------------------------===//
646 // Multiclass helpers...
649 /// AsI1_bin_irs - Defines a set of (op r, {so_imm|r|so_reg}) patterns for a
650 /// binop that produces a value.
651 multiclass AsI1_bin_irs<bits<4> opcod, string opc,
652 InstrItinClass iii, InstrItinClass iir, InstrItinClass iis,
653 PatFrag opnode, bit Commutable = 0> {
654 // The register-immediate version is re-materializable. This is useful
655 // in particular for taking the address of a local.
656 let isReMaterializable = 1 in {
657 def ri : AsI1<opcod, (outs GPR:$Rd), (ins GPR:$Rn, so_imm:$imm), DPFrm,
658 iii, opc, "\t$Rd, $Rn, $imm",
659 [(set GPR:$Rd, (opnode GPR:$Rn, so_imm:$imm))]> {
664 let Inst{19-16} = Rn;
665 let Inst{15-12} = Rd;
666 let Inst{11-0} = imm;
669 def rr : AsI1<opcod, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm), DPFrm,
670 iir, opc, "\t$Rd, $Rn, $Rm",
671 [(set GPR:$Rd, (opnode GPR:$Rn, GPR:$Rm))]> {
676 let isCommutable = Commutable;
677 let Inst{19-16} = Rn;
678 let Inst{15-12} = Rd;
679 let Inst{11-4} = 0b00000000;
682 def rs : AsI1<opcod, (outs GPR:$Rd), (ins GPR:$Rn, so_reg:$shift), DPSoRegFrm,
683 iis, opc, "\t$Rd, $Rn, $shift",
684 [(set GPR:$Rd, (opnode GPR:$Rn, so_reg:$shift))]> {
689 let Inst{19-16} = Rn;
690 let Inst{15-12} = Rd;
691 let Inst{11-0} = shift;
695 /// AI1_bin_s_irs - Similar to AsI1_bin_irs except it sets the 's' bit so the
696 /// instruction modifies the CPSR register.
697 let isCodeGenOnly = 1, Defs = [CPSR] in {
698 multiclass AI1_bin_s_irs<bits<4> opcod, string opc,
699 InstrItinClass iii, InstrItinClass iir, InstrItinClass iis,
700 PatFrag opnode, bit Commutable = 0> {
701 def ri : AI1<opcod, (outs GPR:$Rd), (ins GPR:$Rn, so_imm:$imm), DPFrm,
702 iii, opc, "\t$Rd, $Rn, $imm",
703 [(set GPR:$Rd, (opnode GPR:$Rn, so_imm:$imm))]> {
709 let Inst{19-16} = Rn;
710 let Inst{15-12} = Rd;
711 let Inst{11-0} = imm;
713 def rr : AI1<opcod, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm), DPFrm,
714 iir, opc, "\t$Rd, $Rn, $Rm",
715 [(set GPR:$Rd, (opnode GPR:$Rn, GPR:$Rm))]> {
719 let isCommutable = Commutable;
722 let Inst{19-16} = Rn;
723 let Inst{15-12} = Rd;
724 let Inst{11-4} = 0b00000000;
727 def rs : AI1<opcod, (outs GPR:$Rd), (ins GPR:$Rn, so_reg:$shift), DPSoRegFrm,
728 iis, opc, "\t$Rd, $Rn, $shift",
729 [(set GPR:$Rd, (opnode GPR:$Rn, so_reg:$shift))]> {
735 let Inst{19-16} = Rn;
736 let Inst{15-12} = Rd;
737 let Inst{11-0} = shift;
742 /// AI1_cmp_irs - Defines a set of (op r, {so_imm|r|so_reg}) cmp / test
743 /// patterns. Similar to AsI1_bin_irs except the instruction does not produce
744 /// a explicit result, only implicitly set CPSR.
745 let isCompare = 1, Defs = [CPSR] in {
746 multiclass AI1_cmp_irs<bits<4> opcod, string opc,
747 InstrItinClass iii, InstrItinClass iir, InstrItinClass iis,
748 PatFrag opnode, bit Commutable = 0> {
749 def ri : AI1<opcod, (outs), (ins GPR:$Rn, so_imm:$imm), DPFrm, iii,
751 [(opnode GPR:$Rn, so_imm:$imm)]> {
756 let Inst{19-16} = Rn;
757 let Inst{15-12} = 0b0000;
758 let Inst{11-0} = imm;
760 def rr : AI1<opcod, (outs), (ins GPR:$Rn, GPR:$Rm), DPFrm, iir,
762 [(opnode GPR:$Rn, GPR:$Rm)]> {
765 let isCommutable = Commutable;
768 let Inst{19-16} = Rn;
769 let Inst{15-12} = 0b0000;
770 let Inst{11-4} = 0b00000000;
773 def rs : AI1<opcod, (outs), (ins GPR:$Rn, so_reg:$shift), DPSoRegFrm, iis,
774 opc, "\t$Rn, $shift",
775 [(opnode GPR:$Rn, so_reg:$shift)]> {
780 let Inst{19-16} = Rn;
781 let Inst{15-12} = 0b0000;
782 let Inst{11-0} = shift;
787 /// AI_ext_rrot - A unary operation with two forms: one whose operand is a
788 /// register and one whose operand is a register rotated by 8/16/24.
789 /// FIXME: Remove the 'r' variant. Its rot_imm is zero.
790 multiclass AI_ext_rrot<bits<8> opcod, string opc, PatFrag opnode> {
791 def r : AExtI<opcod, (outs GPR:$Rd), (ins GPR:$Rm),
792 IIC_iEXTr, opc, "\t$Rd, $Rm",
793 [(set GPR:$Rd, (opnode GPR:$Rm))]>,
794 Requires<[IsARM, HasV6]> {
797 let Inst{19-16} = 0b1111;
798 let Inst{15-12} = Rd;
799 let Inst{11-10} = 0b00;
802 def r_rot : AExtI<opcod, (outs GPR:$Rd), (ins GPR:$Rm, rot_imm:$rot),
803 IIC_iEXTr, opc, "\t$Rd, $Rm, ror $rot",
804 [(set GPR:$Rd, (opnode (rotr GPR:$Rm, rot_imm:$rot)))]>,
805 Requires<[IsARM, HasV6]> {
809 let Inst{19-16} = 0b1111;
810 let Inst{15-12} = Rd;
811 let Inst{11-10} = rot;
816 multiclass AI_ext_rrot_np<bits<8> opcod, string opc> {
817 def r : AExtI<opcod, (outs GPR:$Rd), (ins GPR:$Rm),
818 IIC_iEXTr, opc, "\t$Rd, $Rm",
819 [/* For disassembly only; pattern left blank */]>,
820 Requires<[IsARM, HasV6]> {
821 let Inst{19-16} = 0b1111;
822 let Inst{11-10} = 0b00;
824 def r_rot : AExtI<opcod, (outs GPR:$Rd), (ins GPR:$Rm, rot_imm:$rot),
825 IIC_iEXTr, opc, "\t$Rd, $Rm, ror $rot",
826 [/* For disassembly only; pattern left blank */]>,
827 Requires<[IsARM, HasV6]> {
829 let Inst{19-16} = 0b1111;
830 let Inst{11-10} = rot;
834 /// AI_exta_rrot - A binary operation with two forms: one whose operand is a
835 /// register and one whose operand is a register rotated by 8/16/24.
836 multiclass AI_exta_rrot<bits<8> opcod, string opc, PatFrag opnode> {
837 def rr : AExtI<opcod, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm),
838 IIC_iEXTAr, opc, "\t$Rd, $Rn, $Rm",
839 [(set GPR:$Rd, (opnode GPR:$Rn, GPR:$Rm))]>,
840 Requires<[IsARM, HasV6]> {
844 let Inst{19-16} = Rn;
845 let Inst{15-12} = Rd;
846 let Inst{11-10} = 0b00;
847 let Inst{9-4} = 0b000111;
850 def rr_rot : AExtI<opcod, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm,
852 IIC_iEXTAr, opc, "\t$Rd, $Rn, $Rm, ror $rot",
853 [(set GPR:$Rd, (opnode GPR:$Rn,
854 (rotr GPR:$Rm, rot_imm:$rot)))]>,
855 Requires<[IsARM, HasV6]> {
860 let Inst{19-16} = Rn;
861 let Inst{15-12} = Rd;
862 let Inst{11-10} = rot;
863 let Inst{9-4} = 0b000111;
868 // For disassembly only.
869 multiclass AI_exta_rrot_np<bits<8> opcod, string opc> {
870 def rr : AExtI<opcod, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm),
871 IIC_iEXTAr, opc, "\t$Rd, $Rn, $Rm",
872 [/* For disassembly only; pattern left blank */]>,
873 Requires<[IsARM, HasV6]> {
874 let Inst{11-10} = 0b00;
876 def rr_rot : AExtI<opcod, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm,
878 IIC_iEXTAr, opc, "\t$Rd, $Rn, $Rm, ror $rot",
879 [/* For disassembly only; pattern left blank */]>,
880 Requires<[IsARM, HasV6]> {
883 let Inst{19-16} = Rn;
884 let Inst{11-10} = rot;
888 /// AI1_adde_sube_irs - Define instructions and patterns for adde and sube.
889 let Uses = [CPSR] in {
890 multiclass AI1_adde_sube_irs<bits<4> opcod, string opc, PatFrag opnode,
891 bit Commutable = 0> {
892 def ri : AsI1<opcod, (outs GPR:$Rd), (ins GPR:$Rn, so_imm:$imm),
893 DPFrm, IIC_iALUi, opc, "\t$Rd, $Rn, $imm",
894 [(set GPR:$Rd, (opnode GPR:$Rn, so_imm:$imm))]>,
900 let Inst{15-12} = Rd;
901 let Inst{19-16} = Rn;
902 let Inst{11-0} = imm;
904 def rr : AsI1<opcod, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm),
905 DPFrm, IIC_iALUr, opc, "\t$Rd, $Rn, $Rm",
906 [(set GPR:$Rd, (opnode GPR:$Rn, GPR:$Rm))]>,
911 let Inst{11-4} = 0b00000000;
913 let isCommutable = Commutable;
915 let Inst{15-12} = Rd;
916 let Inst{19-16} = Rn;
918 def rs : AsI1<opcod, (outs GPR:$Rd), (ins GPR:$Rn, so_reg:$shift),
919 DPSoRegFrm, IIC_iALUsr, opc, "\t$Rd, $Rn, $shift",
920 [(set GPR:$Rd, (opnode GPR:$Rn, so_reg:$shift))]>,
926 let Inst{11-0} = shift;
927 let Inst{15-12} = Rd;
928 let Inst{19-16} = Rn;
931 // Carry setting variants
932 let isCodeGenOnly = 1, Defs = [CPSR] in {
933 multiclass AI1_adde_sube_s_irs<bits<4> opcod, string opc, PatFrag opnode,
934 bit Commutable = 0> {
935 def Sri : AXI1<opcod, (outs GPR:$Rd), (ins GPR:$Rn, so_imm:$imm),
936 DPFrm, IIC_iALUi, !strconcat(opc, "\t$Rd, $Rn, $imm"),
937 [(set GPR:$Rd, (opnode GPR:$Rn, so_imm:$imm))]>,
942 let Inst{31-27} = 0b1110; // non-predicated
943 let Inst{15-12} = Rd;
944 let Inst{19-16} = Rn;
945 let Inst{11-0} = imm;
949 def Srr : AXI1<opcod, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm),
950 DPFrm, IIC_iALUr, !strconcat(opc, "\t$Rd, $Rn, $Rm"),
951 [(set GPR:$Rd, (opnode GPR:$Rn, GPR:$Rm))]>,
956 let Inst{31-27} = 0b1110; // non-predicated
957 let Inst{11-4} = 0b00000000;
958 let isCommutable = Commutable;
960 let Inst{15-12} = Rd;
961 let Inst{19-16} = Rn;
965 def Srs : AXI1<opcod, (outs GPR:$Rd), (ins GPR:$Rn, so_reg:$shift),
966 DPSoRegFrm, IIC_iALUsr, !strconcat(opc, "\t$Rd, $Rn, $shift"),
967 [(set GPR:$Rd, (opnode GPR:$Rn, so_reg:$shift))]>,
972 let Inst{31-27} = 0b1110; // non-predicated
973 let Inst{11-0} = shift;
974 let Inst{15-12} = Rd;
975 let Inst{19-16} = Rn;
983 let canFoldAsLoad = 1, isReMaterializable = 1 in {
984 multiclass AI_ldr1<bit isByte, string opc, InstrItinClass iii,
985 InstrItinClass iir, PatFrag opnode> {
986 // Note: We use the complex addrmode_imm12 rather than just an input
987 // GPR and a constrained immediate so that we can use this to match
988 // frame index references and avoid matching constant pool references.
989 def i12: AI2ldst<0b010, 1, isByte, (outs GPR:$Rt), (ins addrmode_imm12:$addr),
990 AddrMode_i12, LdFrm, iii, opc, "\t$Rt, $addr",
991 [(set GPR:$Rt, (opnode addrmode_imm12:$addr))]> {
994 let Inst{23} = addr{12}; // U (add = ('U' == 1))
995 let Inst{19-16} = addr{16-13}; // Rn
996 let Inst{15-12} = Rt;
997 let Inst{11-0} = addr{11-0}; // imm12
999 def rs : AI2ldst<0b011, 1, isByte, (outs GPR:$Rt), (ins ldst_so_reg:$shift),
1000 AddrModeNone, LdFrm, iir, opc, "\t$Rt, $shift",
1001 [(set GPR:$Rt, (opnode ldst_so_reg:$shift))]> {
1004 let shift{4} = 0; // Inst{4} = 0
1005 let Inst{23} = shift{12}; // U (add = ('U' == 1))
1006 let Inst{19-16} = shift{16-13}; // Rn
1007 let Inst{15-12} = Rt;
1008 let Inst{11-0} = shift{11-0};
1013 multiclass AI_str1<bit isByte, string opc, InstrItinClass iii,
1014 InstrItinClass iir, PatFrag opnode> {
1015 // Note: We use the complex addrmode_imm12 rather than just an input
1016 // GPR and a constrained immediate so that we can use this to match
1017 // frame index references and avoid matching constant pool references.
1018 def i12 : AI2ldst<0b010, 0, isByte, (outs),
1019 (ins GPR:$Rt, addrmode_imm12:$addr),
1020 AddrMode_i12, StFrm, iii, opc, "\t$Rt, $addr",
1021 [(opnode GPR:$Rt, addrmode_imm12:$addr)]> {
1024 let Inst{23} = addr{12}; // U (add = ('U' == 1))
1025 let Inst{19-16} = addr{16-13}; // Rn
1026 let Inst{15-12} = Rt;
1027 let Inst{11-0} = addr{11-0}; // imm12
1029 def rs : AI2ldst<0b011, 0, isByte, (outs), (ins GPR:$Rt, ldst_so_reg:$shift),
1030 AddrModeNone, StFrm, iir, opc, "\t$Rt, $shift",
1031 [(opnode GPR:$Rt, ldst_so_reg:$shift)]> {
1034 let shift{4} = 0; // Inst{4} = 0
1035 let Inst{23} = shift{12}; // U (add = ('U' == 1))
1036 let Inst{19-16} = shift{16-13}; // Rn
1037 let Inst{15-12} = Rt;
1038 let Inst{11-0} = shift{11-0};
1041 //===----------------------------------------------------------------------===//
1043 //===----------------------------------------------------------------------===//
1045 //===----------------------------------------------------------------------===//
1046 // Miscellaneous Instructions.
1049 /// CONSTPOOL_ENTRY - This instruction represents a floating constant pool in
1050 /// the function. The first operand is the ID# for this instruction, the second
1051 /// is the index into the MachineConstantPool that this is, the third is the
1052 /// size in bytes of this constant pool entry.
1053 let neverHasSideEffects = 1, isNotDuplicable = 1 in
1054 def CONSTPOOL_ENTRY :
1055 PseudoInst<(outs), (ins cpinst_operand:$instid, cpinst_operand:$cpidx,
1056 i32imm:$size), NoItinerary, []>;
1058 // FIXME: Marking these as hasSideEffects is necessary to prevent machine DCE
1059 // from removing one half of the matched pairs. That breaks PEI, which assumes
1060 // these will always be in pairs, and asserts if it finds otherwise. Better way?
1061 let Defs = [SP], Uses = [SP], hasSideEffects = 1 in {
1062 def ADJCALLSTACKUP :
1063 PseudoInst<(outs), (ins i32imm:$amt1, i32imm:$amt2, pred:$p), NoItinerary,
1064 [(ARMcallseq_end timm:$amt1, timm:$amt2)]>;
1066 def ADJCALLSTACKDOWN :
1067 PseudoInst<(outs), (ins i32imm:$amt, pred:$p), NoItinerary,
1068 [(ARMcallseq_start timm:$amt)]>;
1071 def NOP : AI<(outs), (ins), MiscFrm, NoItinerary, "nop", "",
1072 [/* For disassembly only; pattern left blank */]>,
1073 Requires<[IsARM, HasV6T2]> {
1074 let Inst{27-16} = 0b001100100000;
1075 let Inst{15-8} = 0b11110000;
1076 let Inst{7-0} = 0b00000000;
1079 def YIELD : AI<(outs), (ins), MiscFrm, NoItinerary, "yield", "",
1080 [/* For disassembly only; pattern left blank */]>,
1081 Requires<[IsARM, HasV6T2]> {
1082 let Inst{27-16} = 0b001100100000;
1083 let Inst{15-8} = 0b11110000;
1084 let Inst{7-0} = 0b00000001;
1087 def WFE : AI<(outs), (ins), MiscFrm, NoItinerary, "wfe", "",
1088 [/* For disassembly only; pattern left blank */]>,
1089 Requires<[IsARM, HasV6T2]> {
1090 let Inst{27-16} = 0b001100100000;
1091 let Inst{15-8} = 0b11110000;
1092 let Inst{7-0} = 0b00000010;
1095 def WFI : AI<(outs), (ins), MiscFrm, NoItinerary, "wfi", "",
1096 [/* For disassembly only; pattern left blank */]>,
1097 Requires<[IsARM, HasV6T2]> {
1098 let Inst{27-16} = 0b001100100000;
1099 let Inst{15-8} = 0b11110000;
1100 let Inst{7-0} = 0b00000011;
1103 def SEL : AI<(outs GPR:$dst), (ins GPR:$a, GPR:$b), DPFrm, NoItinerary, "sel",
1105 [/* For disassembly only; pattern left blank */]>,
1106 Requires<[IsARM, HasV6]> {
1111 let Inst{15-12} = Rd;
1112 let Inst{19-16} = Rn;
1113 let Inst{27-20} = 0b01101000;
1114 let Inst{7-4} = 0b1011;
1115 let Inst{11-8} = 0b1111;
1118 def SEV : AI<(outs), (ins), MiscFrm, NoItinerary, "sev", "",
1119 [/* For disassembly only; pattern left blank */]>,
1120 Requires<[IsARM, HasV6T2]> {
1121 let Inst{27-16} = 0b001100100000;
1122 let Inst{15-8} = 0b11110000;
1123 let Inst{7-0} = 0b00000100;
1126 // The i32imm operand $val can be used by a debugger to store more information
1127 // about the breakpoint.
1128 def BKPT : AI<(outs), (ins i32imm:$val), MiscFrm, NoItinerary, "bkpt", "\t$val",
1129 [/* For disassembly only; pattern left blank */]>,
1132 let Inst{3-0} = val{3-0};
1133 let Inst{19-8} = val{15-4};
1134 let Inst{27-20} = 0b00010010;
1135 let Inst{7-4} = 0b0111;
1138 // Change Processor State is a system instruction -- for disassembly and
1140 // FIXME: Since the asm parser has currently no clean way to handle optional
1141 // operands, create 3 versions of the same instruction. Once there's a clean
1142 // framework to represent optional operands, change this behavior.
1143 class CPS<dag iops, string asm_ops>
1144 : AXI<(outs), iops, MiscFrm, NoItinerary, !strconcat("cps", asm_ops),
1145 [/* For disassembly only; pattern left blank */]>, Requires<[IsARM]> {
1151 let Inst{31-28} = 0b1111;
1152 let Inst{27-20} = 0b00010000;
1153 let Inst{19-18} = imod;
1154 let Inst{17} = M; // Enabled if mode is set;
1156 let Inst{8-6} = iflags;
1158 let Inst{4-0} = mode;
1162 def CPS3p : CPS<(ins imod_op:$imod, iflags_op:$iflags, i32imm:$mode),
1163 "$imod\t$iflags, $mode">;
1164 let mode = 0, M = 0 in
1165 def CPS2p : CPS<(ins imod_op:$imod, iflags_op:$iflags), "$imod\t$iflags">;
1167 let imod = 0, iflags = 0, M = 1 in
1168 def CPS1p : CPS<(ins i32imm:$mode), "\t$mode">;
1170 // Preload signals the memory system of possible future data/instruction access.
1171 // These are for disassembly only.
1172 multiclass APreLoad<bits<1> read, bits<1> data, string opc> {
1174 def i12 : AXI<(outs), (ins addrmode_imm12:$addr), MiscFrm, IIC_Preload,
1175 !strconcat(opc, "\t$addr"),
1176 [(ARMPreload addrmode_imm12:$addr, (i32 read), (i32 data))]> {
1179 let Inst{31-26} = 0b111101;
1180 let Inst{25} = 0; // 0 for immediate form
1181 let Inst{24} = data;
1182 let Inst{23} = addr{12}; // U (add = ('U' == 1))
1183 let Inst{22} = read;
1184 let Inst{21-20} = 0b01;
1185 let Inst{19-16} = addr{16-13}; // Rn
1186 let Inst{15-12} = 0b1111;
1187 let Inst{11-0} = addr{11-0}; // imm12
1190 def rs : AXI<(outs), (ins ldst_so_reg:$shift), MiscFrm, IIC_Preload,
1191 !strconcat(opc, "\t$shift"),
1192 [(ARMPreload ldst_so_reg:$shift, (i32 read), (i32 data))]> {
1194 let Inst{31-26} = 0b111101;
1195 let Inst{25} = 1; // 1 for register form
1196 let Inst{24} = data;
1197 let Inst{23} = shift{12}; // U (add = ('U' == 1))
1198 let Inst{22} = read;
1199 let Inst{21-20} = 0b01;
1200 let Inst{19-16} = shift{16-13}; // Rn
1201 let Inst{15-12} = 0b1111;
1202 let Inst{11-0} = shift{11-0};
1206 defm PLD : APreLoad<1, 1, "pld">, Requires<[IsARM]>;
1207 defm PLDW : APreLoad<0, 1, "pldw">, Requires<[IsARM,HasV7,HasMP]>;
1208 defm PLI : APreLoad<1, 0, "pli">, Requires<[IsARM,HasV7]>;
1210 def SETEND : AXI<(outs),(ins setend_op:$end), MiscFrm, NoItinerary,
1212 [/* For disassembly only; pattern left blank */]>,
1215 let Inst{31-10} = 0b1111000100000001000000;
1220 def DBG : AI<(outs), (ins i32imm:$opt), MiscFrm, NoItinerary, "dbg", "\t$opt",
1221 [/* For disassembly only; pattern left blank */]>,
1222 Requires<[IsARM, HasV7]> {
1224 let Inst{27-4} = 0b001100100000111100001111;
1225 let Inst{3-0} = opt;
1228 // A5.4 Permanently UNDEFINED instructions.
1229 let isBarrier = 1, isTerminator = 1 in
1230 def TRAP : AXI<(outs), (ins), MiscFrm, NoItinerary,
1233 let Inst = 0xe7ffdefe;
1236 // Address computation and loads and stores in PIC mode.
1237 let isNotDuplicable = 1 in {
1238 def PICADD : ARMPseudoInst<(outs GPR:$dst), (ins GPR:$a, pclabel:$cp, pred:$p),
1239 Size4Bytes, IIC_iALUr,
1240 [(set GPR:$dst, (ARMpic_add GPR:$a, imm:$cp))]>;
1242 let AddedComplexity = 10 in {
1243 def PICLDR : ARMPseudoInst<(outs GPR:$dst), (ins addrmodepc:$addr, pred:$p),
1244 Size4Bytes, IIC_iLoad_r,
1245 [(set GPR:$dst, (load addrmodepc:$addr))]>;
1247 def PICLDRH : ARMPseudoInst<(outs GPR:$Rt), (ins addrmodepc:$addr, pred:$p),
1248 Size4Bytes, IIC_iLoad_bh_r,
1249 [(set GPR:$Rt, (zextloadi16 addrmodepc:$addr))]>;
1251 def PICLDRB : ARMPseudoInst<(outs GPR:$Rt), (ins addrmodepc:$addr, pred:$p),
1252 Size4Bytes, IIC_iLoad_bh_r,
1253 [(set GPR:$Rt, (zextloadi8 addrmodepc:$addr))]>;
1255 def PICLDRSH : ARMPseudoInst<(outs GPR:$Rt), (ins addrmodepc:$addr, pred:$p),
1256 Size4Bytes, IIC_iLoad_bh_r,
1257 [(set GPR:$Rt, (sextloadi16 addrmodepc:$addr))]>;
1259 def PICLDRSB : ARMPseudoInst<(outs GPR:$Rt), (ins addrmodepc:$addr, pred:$p),
1260 Size4Bytes, IIC_iLoad_bh_r,
1261 [(set GPR:$Rt, (sextloadi8 addrmodepc:$addr))]>;
1263 let AddedComplexity = 10 in {
1264 def PICSTR : ARMPseudoInst<(outs), (ins GPR:$src, addrmodepc:$addr, pred:$p),
1265 Size4Bytes, IIC_iStore_r, [(store GPR:$src, addrmodepc:$addr)]>;
1267 def PICSTRH : ARMPseudoInst<(outs), (ins GPR:$src, addrmodepc:$addr, pred:$p),
1268 Size4Bytes, IIC_iStore_bh_r, [(truncstorei16 GPR:$src,
1269 addrmodepc:$addr)]>;
1271 def PICSTRB : ARMPseudoInst<(outs), (ins GPR:$src, addrmodepc:$addr, pred:$p),
1272 Size4Bytes, IIC_iStore_bh_r, [(truncstorei8 GPR:$src, addrmodepc:$addr)]>;
1274 } // isNotDuplicable = 1
1277 // LEApcrel - Load a pc-relative address into a register without offending the
1279 let neverHasSideEffects = 1, isReMaterializable = 1 in
1280 // The 'adr' mnemonic encodes differently if the label is before or after
1281 // the instruction. The {24-21} opcode bits are set by the fixup, as we don't
1282 // know until then which form of the instruction will be used.
1283 def ADR : AI1<{0,?,?,0}, (outs GPR:$Rd), (ins adrlabel:$label),
1284 MiscFrm, IIC_iALUi, "adr", "\t$Rd, #$label", []> {
1287 let Inst{27-25} = 0b001;
1289 let Inst{19-16} = 0b1111;
1290 let Inst{15-12} = Rd;
1291 let Inst{11-0} = label;
1293 def LEApcrel : ARMPseudoInst<(outs GPR:$Rd), (ins i32imm:$label, pred:$p),
1294 Size4Bytes, IIC_iALUi, []>;
1296 def LEApcrelJT : ARMPseudoInst<(outs GPR:$Rd),
1297 (ins i32imm:$label, nohash_imm:$id, pred:$p),
1298 Size4Bytes, IIC_iALUi, []>;
1300 //===----------------------------------------------------------------------===//
1301 // Control Flow Instructions.
1304 let isReturn = 1, isTerminator = 1, isBarrier = 1 in {
1306 def BX_RET : AI<(outs), (ins), BrMiscFrm, IIC_Br,
1307 "bx", "\tlr", [(ARMretflag)]>,
1308 Requires<[IsARM, HasV4T]> {
1309 let Inst{27-0} = 0b0001001011111111111100011110;
1313 def MOVPCLR : AI<(outs), (ins), BrMiscFrm, IIC_Br,
1314 "mov", "\tpc, lr", [(ARMretflag)]>,
1315 Requires<[IsARM, NoV4T]> {
1316 let Inst{27-0} = 0b0001101000001111000000001110;
1320 // Indirect branches
1321 let isBranch = 1, isTerminator = 1, isBarrier = 1, isIndirectBranch = 1 in {
1323 def BX : AXI<(outs), (ins GPR:$dst), BrMiscFrm, IIC_Br, "bx\t$dst",
1324 [(brind GPR:$dst)]>,
1325 Requires<[IsARM, HasV4T]> {
1327 let Inst{31-4} = 0b1110000100101111111111110001;
1328 let Inst{3-0} = dst;
1332 // FIXME: We would really like to define this as a vanilla ARMPat like:
1333 // ARMPat<(brind GPR:$dst), (MOVr PC, GPR:$dst)>
1334 // With that, however, we can't set isBranch, isTerminator, etc..
1335 def MOVPCRX : ARMPseudoInst<(outs), (ins GPR:$dst),
1336 Size4Bytes, IIC_Br, [(brind GPR:$dst)]>,
1337 Requires<[IsARM, NoV4T]>;
1340 // All calls clobber the non-callee saved registers. SP is marked as
1341 // a use to prevent stack-pointer assignments that appear immediately
1342 // before calls from potentially appearing dead.
1344 // On non-Darwin platforms R9 is callee-saved.
1345 // FIXME: Do we really need a non-predicated version? If so, it should
1346 // at least be a pseudo instruction expanding to the predicated version
1347 // at MC lowering time.
1348 Defs = [R0, R1, R2, R3, R12, LR,
1349 D0, D1, D2, D3, D4, D5, D6, D7,
1350 D16, D17, D18, D19, D20, D21, D22, D23,
1351 D24, D25, D26, D27, D28, D29, D30, D31, CPSR, FPSCR],
1353 def BL : ABXI<0b1011, (outs), (ins bl_target:$func, variable_ops),
1354 IIC_Br, "bl\t$func",
1355 [(ARMcall tglobaladdr:$func)]>,
1356 Requires<[IsARM, IsNotDarwin]> {
1357 let Inst{31-28} = 0b1110;
1359 let Inst{23-0} = func;
1362 def BL_pred : ABI<0b1011, (outs), (ins bl_target:$func, variable_ops),
1363 IIC_Br, "bl", "\t$func",
1364 [(ARMcall_pred tglobaladdr:$func)]>,
1365 Requires<[IsARM, IsNotDarwin]> {
1367 let Inst{23-0} = func;
1371 def BLX : AXI<(outs), (ins GPR:$func, variable_ops), BrMiscFrm,
1372 IIC_Br, "blx\t$func",
1373 [(ARMcall GPR:$func)]>,
1374 Requires<[IsARM, HasV5T, IsNotDarwin]> {
1376 let Inst{31-4} = 0b1110000100101111111111110011;
1377 let Inst{3-0} = func;
1380 def BLX_pred : AI<(outs), (ins GPR:$func, variable_ops), BrMiscFrm,
1381 IIC_Br, "blx", "\t$func",
1382 [(ARMcall_pred GPR:$func)]>,
1383 Requires<[IsARM, HasV5T, IsNotDarwin]> {
1385 let Inst{27-4} = 0b000100101111111111110011;
1386 let Inst{3-0} = func;
1390 // Note: Restrict $func to the tGPR regclass to prevent it being in LR.
1391 def BX_CALL : ARMPseudoInst<(outs), (ins tGPR:$func, variable_ops),
1392 Size8Bytes, IIC_Br, [(ARMcall_nolink tGPR:$func)]>,
1393 Requires<[IsARM, HasV4T, IsNotDarwin]>;
1396 def BMOVPCRX_CALL : ARMPseudoInst<(outs), (ins tGPR:$func, variable_ops),
1397 Size8Bytes, IIC_Br, [(ARMcall_nolink tGPR:$func)]>,
1398 Requires<[IsARM, NoV4T, IsNotDarwin]>;
1402 // On Darwin R9 is call-clobbered.
1403 // R7 is marked as a use to prevent frame-pointer assignments from being
1404 // moved above / below calls.
1405 Defs = [R0, R1, R2, R3, R9, R12, LR,
1406 D0, D1, D2, D3, D4, D5, D6, D7,
1407 D16, D17, D18, D19, D20, D21, D22, D23,
1408 D24, D25, D26, D27, D28, D29, D30, D31, CPSR, FPSCR],
1409 Uses = [R7, SP] in {
1410 def BLr9 : ARMPseudoInst<(outs), (ins bltarget:$func, variable_ops),
1412 [(ARMcall tglobaladdr:$func)]>, Requires<[IsARM, IsDarwin]>;
1414 def BLr9_pred : ARMPseudoInst<(outs),
1415 (ins bltarget:$func, pred:$p, variable_ops),
1417 [(ARMcall_pred tglobaladdr:$func)]>,
1418 Requires<[IsARM, IsDarwin]>;
1421 def BLXr9 : ARMPseudoInst<(outs), (ins GPR:$func, variable_ops),
1423 [(ARMcall GPR:$func)]>, Requires<[IsARM, HasV5T, IsDarwin]>;
1425 def BLXr9_pred: ARMPseudoInst<(outs), (ins GPR:$func, pred:$p, variable_ops),
1427 [(ARMcall_pred GPR:$func)]>,
1428 Requires<[IsARM, HasV5T, IsDarwin]>;
1431 // Note: Restrict $func to the tGPR regclass to prevent it being in LR.
1432 def BXr9_CALL : ARMPseudoInst<(outs), (ins tGPR:$func, variable_ops),
1433 Size8Bytes, IIC_Br, [(ARMcall_nolink tGPR:$func)]>,
1434 Requires<[IsARM, HasV4T, IsDarwin]>;
1437 def BMOVPCRXr9_CALL : ARMPseudoInst<(outs), (ins tGPR:$func, variable_ops),
1438 Size8Bytes, IIC_Br, [(ARMcall_nolink tGPR:$func)]>,
1439 Requires<[IsARM, NoV4T, IsDarwin]>;
1444 // FIXME: The Thumb versions of these should live in ARMInstrThumb.td
1445 let isCall = 1, isTerminator = 1, isReturn = 1, isBarrier = 1 in {
1447 let Defs = [R0, R1, R2, R3, R9, R12,
1448 D0, D1, D2, D3, D4, D5, D6, D7,
1449 D16, D17, D18, D19, D20, D21, D22, D23, D24, D25, D26,
1450 D27, D28, D29, D30, D31, PC],
1452 def TCRETURNdi : PseudoInst<(outs), (ins i32imm:$dst, variable_ops),
1453 IIC_Br, []>, Requires<[IsDarwin]>;
1455 def TCRETURNri : PseudoInst<(outs), (ins tcGPR:$dst, variable_ops),
1456 IIC_Br, []>, Requires<[IsDarwin]>;
1458 def TAILJMPd : ARMPseudoInst<(outs), (ins brtarget:$dst, variable_ops),
1460 []>, Requires<[IsARM, IsDarwin]>;
1462 def tTAILJMPd: tPseudoInst<(outs), (ins brtarget:$dst, variable_ops),
1464 []>, Requires<[IsThumb, IsDarwin]>;
1466 def TAILJMPr : ARMPseudoInst<(outs), (ins tcGPR:$dst, variable_ops),
1468 []>, Requires<[IsARM, IsDarwin]>;
1470 def tTAILJMPr : tPseudoInst<(outs), (ins tcGPR:$dst, variable_ops),
1472 []>, Requires<[IsThumb, IsDarwin]>;
1475 // Non-Darwin versions (the difference is R9).
1476 let Defs = [R0, R1, R2, R3, R12,
1477 D0, D1, D2, D3, D4, D5, D6, D7,
1478 D16, D17, D18, D19, D20, D21, D22, D23, D24, D25, D26,
1479 D27, D28, D29, D30, D31, PC],
1481 def TCRETURNdiND : PseudoInst<(outs), (ins i32imm:$dst, variable_ops),
1482 IIC_Br, []>, Requires<[IsNotDarwin]>;
1484 def TCRETURNriND : PseudoInst<(outs), (ins tcGPR:$dst, variable_ops),
1485 IIC_Br, []>, Requires<[IsNotDarwin]>;
1487 def TAILJMPdND : ARMPseudoInst<(outs), (ins brtarget:$dst, variable_ops),
1489 []>, Requires<[IsARM, IsNotDarwin]>;
1491 def tTAILJMPdND : tPseudoInst<(outs), (ins brtarget:$dst, variable_ops),
1493 []>, Requires<[IsThumb, IsNotDarwin]>;
1495 def TAILJMPrND : ARMPseudoInst<(outs), (ins tcGPR:$dst, variable_ops),
1497 []>, Requires<[IsARM, IsNotDarwin]>;
1498 def tTAILJMPrND : tPseudoInst<(outs), (ins tcGPR:$dst, variable_ops),
1500 []>, Requires<[IsThumb, IsNotDarwin]>;
1504 let isBranch = 1, isTerminator = 1 in {
1505 // B is "predicable" since it's just a Bcc with an 'always' condition.
1506 let isBarrier = 1 in {
1507 let isPredicable = 1 in
1508 // FIXME: We shouldn't need this pseudo at all. Just using Bcc directly
1509 // should be sufficient.
1510 def B : ARMPseudoInst<(outs), (ins brtarget:$target), Size4Bytes, IIC_Br,
1513 let isNotDuplicable = 1, isIndirectBranch = 1 in {
1514 def BR_JTr : ARMPseudoInst<(outs),
1515 (ins GPR:$target, i32imm:$jt, i32imm:$id),
1516 SizeSpecial, IIC_Br,
1517 [(ARMbrjt GPR:$target, tjumptable:$jt, imm:$id)]>;
1518 // FIXME: This shouldn't use the generic "addrmode2," but rather be split
1519 // into i12 and rs suffixed versions.
1520 def BR_JTm : ARMPseudoInst<(outs),
1521 (ins addrmode2:$target, i32imm:$jt, i32imm:$id),
1522 SizeSpecial, IIC_Br,
1523 [(ARMbrjt (i32 (load addrmode2:$target)), tjumptable:$jt,
1525 def BR_JTadd : ARMPseudoInst<(outs),
1526 (ins GPR:$target, GPR:$idx, i32imm:$jt, i32imm:$id),
1527 SizeSpecial, IIC_Br,
1528 [(ARMbrjt (add GPR:$target, GPR:$idx), tjumptable:$jt,
1530 } // isNotDuplicable = 1, isIndirectBranch = 1
1533 // FIXME: should be able to write a pattern for ARMBrcond, but can't use
1534 // a two-value operand where a dag node expects two operands. :(
1535 def Bcc : ABI<0b1010, (outs), (ins br_target:$target),
1536 IIC_Br, "b", "\t$target",
1537 [/*(ARMbrcond bb:$target, imm:$cc, CCR:$ccr)*/]> {
1539 let Inst{23-0} = target;
1543 // BLX (immediate) -- for disassembly only
1544 def BLXi : AXI<(outs), (ins br_target:$target), BrMiscFrm, NoItinerary,
1545 "blx\t$target", [/* pattern left blank */]>,
1546 Requires<[IsARM, HasV5T]> {
1547 let Inst{31-25} = 0b1111101;
1549 let Inst{23-0} = target{24-1};
1550 let Inst{24} = target{0};
1553 // Branch and Exchange Jazelle -- for disassembly only
1554 def BXJ : ABI<0b0001, (outs), (ins GPR:$func), NoItinerary, "bxj", "\t$func",
1555 [/* For disassembly only; pattern left blank */]> {
1556 let Inst{23-20} = 0b0010;
1557 //let Inst{19-8} = 0xfff;
1558 let Inst{7-4} = 0b0010;
1561 // Secure Monitor Call is a system instruction -- for disassembly only
1562 def SMC : ABI<0b0001, (outs), (ins i32imm:$opt), NoItinerary, "smc", "\t$opt",
1563 [/* For disassembly only; pattern left blank */]> {
1565 let Inst{23-4} = 0b01100000000000000111;
1566 let Inst{3-0} = opt;
1569 // Supervisor Call (Software Interrupt) -- for disassembly only
1570 let isCall = 1, Uses = [SP] in {
1571 def SVC : ABI<0b1111, (outs), (ins i32imm:$svc), IIC_Br, "svc", "\t$svc",
1572 [/* For disassembly only; pattern left blank */]> {
1574 let Inst{23-0} = svc;
1577 def : MnemonicAlias<"swi", "svc">;
1579 // Store Return State is a system instruction -- for disassembly only
1580 let isCodeGenOnly = 1 in { // FIXME: This should not use submode!
1581 def SRSW : ABXI<{1,0,0,?}, (outs), (ins ldstm_mode:$amode, i32imm:$mode),
1582 NoItinerary, "srs${amode}\tsp!, $mode",
1583 [/* For disassembly only; pattern left blank */]> {
1584 let Inst{31-28} = 0b1111;
1585 let Inst{22-20} = 0b110; // W = 1
1588 def SRS : ABXI<{1,0,0,?}, (outs), (ins ldstm_mode:$amode, i32imm:$mode),
1589 NoItinerary, "srs${amode}\tsp, $mode",
1590 [/* For disassembly only; pattern left blank */]> {
1591 let Inst{31-28} = 0b1111;
1592 let Inst{22-20} = 0b100; // W = 0
1595 // Return From Exception is a system instruction -- for disassembly only
1596 def RFEW : ABXI<{1,0,0,?}, (outs), (ins ldstm_mode:$amode, GPR:$base),
1597 NoItinerary, "rfe${amode}\t$base!",
1598 [/* For disassembly only; pattern left blank */]> {
1599 let Inst{31-28} = 0b1111;
1600 let Inst{22-20} = 0b011; // W = 1
1603 def RFE : ABXI<{1,0,0,?}, (outs), (ins ldstm_mode:$amode, GPR:$base),
1604 NoItinerary, "rfe${amode}\t$base",
1605 [/* For disassembly only; pattern left blank */]> {
1606 let Inst{31-28} = 0b1111;
1607 let Inst{22-20} = 0b001; // W = 0
1609 } // isCodeGenOnly = 1
1611 //===----------------------------------------------------------------------===//
1612 // Load / store Instructions.
1618 defm LDR : AI_ldr1<0, "ldr", IIC_iLoad_r, IIC_iLoad_si,
1619 UnOpFrag<(load node:$Src)>>;
1620 defm LDRB : AI_ldr1<1, "ldrb", IIC_iLoad_bh_r, IIC_iLoad_bh_si,
1621 UnOpFrag<(zextloadi8 node:$Src)>>;
1622 defm STR : AI_str1<0, "str", IIC_iStore_r, IIC_iStore_si,
1623 BinOpFrag<(store node:$LHS, node:$RHS)>>;
1624 defm STRB : AI_str1<1, "strb", IIC_iStore_bh_r, IIC_iStore_bh_si,
1625 BinOpFrag<(truncstorei8 node:$LHS, node:$RHS)>>;
1627 // Special LDR for loads from non-pc-relative constpools.
1628 let canFoldAsLoad = 1, mayLoad = 1, neverHasSideEffects = 1,
1629 isReMaterializable = 1 in
1630 def LDRcp : AI2ldst<0b010, 1, 0, (outs GPR:$Rt), (ins addrmode_imm12:$addr),
1631 AddrMode_i12, LdFrm, IIC_iLoad_r, "ldr", "\t$Rt, $addr",
1635 let Inst{23} = addr{12}; // U (add = ('U' == 1))
1636 let Inst{19-16} = 0b1111;
1637 let Inst{15-12} = Rt;
1638 let Inst{11-0} = addr{11-0}; // imm12
1641 // Loads with zero extension
1642 def LDRH : AI3ld<0b1011, 1, (outs GPR:$Rt), (ins addrmode3:$addr), LdMiscFrm,
1643 IIC_iLoad_bh_r, "ldrh", "\t$Rt, $addr",
1644 [(set GPR:$Rt, (zextloadi16 addrmode3:$addr))]>;
1646 // Loads with sign extension
1647 def LDRSH : AI3ld<0b1111, 1, (outs GPR:$Rt), (ins addrmode3:$addr), LdMiscFrm,
1648 IIC_iLoad_bh_r, "ldrsh", "\t$Rt, $addr",
1649 [(set GPR:$Rt, (sextloadi16 addrmode3:$addr))]>;
1651 def LDRSB : AI3ld<0b1101, 1, (outs GPR:$Rt), (ins addrmode3:$addr), LdMiscFrm,
1652 IIC_iLoad_bh_r, "ldrsb", "\t$Rt, $addr",
1653 [(set GPR:$Rt, (sextloadi8 addrmode3:$addr))]>;
1655 let mayLoad = 1, neverHasSideEffects = 1, hasExtraDefRegAllocReq = 1 in {
1657 def LDRD : AI3ld<0b1101, 0, (outs GPR:$Rd, GPR:$dst2),
1658 (ins addrmode3:$addr), LdMiscFrm,
1659 IIC_iLoad_d_r, "ldrd", "\t$Rd, $dst2, $addr",
1660 []>, Requires<[IsARM, HasV5TE]>;
1664 multiclass AI2_ldridx<bit isByte, string opc, InstrItinClass itin> {
1665 def _PRE : AI2ldstidx<1, isByte, 1, (outs GPR:$Rt, GPR:$Rn_wb),
1666 (ins addrmode2:$addr), IndexModePre, LdFrm, itin,
1667 opc, "\t$Rt, $addr!", "$addr.base = $Rn_wb", []> {
1669 // {13} 1 == Rm, 0 == imm12
1673 let Inst{25} = addr{13};
1674 let Inst{23} = addr{12};
1675 let Inst{19-16} = addr{17-14};
1676 let Inst{11-0} = addr{11-0};
1677 let AsmMatchConverter = "CvtLdWriteBackRegAddrMode2";
1679 def _POST : AI2ldstidx<1, isByte, 0, (outs GPR:$Rt, GPR:$Rn_wb),
1680 (ins GPR:$Rn, am2offset:$offset),
1681 IndexModePost, LdFrm, itin,
1682 opc, "\t$Rt, [$Rn], $offset", "$Rn = $Rn_wb", []> {
1683 // {13} 1 == Rm, 0 == imm12
1688 let Inst{25} = offset{13};
1689 let Inst{23} = offset{12};
1690 let Inst{19-16} = Rn;
1691 let Inst{11-0} = offset{11-0};
1695 let mayLoad = 1, neverHasSideEffects = 1 in {
1696 defm LDR : AI2_ldridx<0, "ldr", IIC_iLoad_ru>;
1697 defm LDRB : AI2_ldridx<1, "ldrb", IIC_iLoad_bh_ru>;
1700 multiclass AI3_ldridx<bits<4> op, bit op20, string opc, InstrItinClass itin> {
1701 def _PRE : AI3ldstidx<op, op20, 1, 1, (outs GPR:$Rt, GPR:$Rn_wb),
1702 (ins addrmode3:$addr), IndexModePre,
1704 opc, "\t$Rt, $addr!", "$addr.base = $Rn_wb", []> {
1706 let Inst{23} = addr{8}; // U bit
1707 let Inst{22} = addr{13}; // 1 == imm8, 0 == Rm
1708 let Inst{19-16} = addr{12-9}; // Rn
1709 let Inst{11-8} = addr{7-4}; // imm7_4/zero
1710 let Inst{3-0} = addr{3-0}; // imm3_0/Rm
1712 def _POST : AI3ldstidx<op, op20, 1, 0, (outs GPR:$Rt, GPR:$Rn_wb),
1713 (ins GPR:$Rn, am3offset:$offset), IndexModePost,
1715 opc, "\t$Rt, [$Rn], $offset", "$Rn = $Rn_wb", []> {
1718 let Inst{23} = offset{8}; // U bit
1719 let Inst{22} = offset{9}; // 1 == imm8, 0 == Rm
1720 let Inst{19-16} = Rn;
1721 let Inst{11-8} = offset{7-4}; // imm7_4/zero
1722 let Inst{3-0} = offset{3-0}; // imm3_0/Rm
1726 let mayLoad = 1, neverHasSideEffects = 1 in {
1727 defm LDRH : AI3_ldridx<0b1011, 1, "ldrh", IIC_iLoad_bh_ru>;
1728 defm LDRSH : AI3_ldridx<0b1111, 1, "ldrsh", IIC_iLoad_bh_ru>;
1729 defm LDRSB : AI3_ldridx<0b1101, 1, "ldrsb", IIC_iLoad_bh_ru>;
1730 let hasExtraDefRegAllocReq = 1, isCodeGenOnly = 1 in
1731 defm LDRD : AI3_ldridx<0b1101, 0, "ldrd", IIC_iLoad_d_ru>;
1732 } // mayLoad = 1, neverHasSideEffects = 1
1734 // LDRT, LDRBT, LDRSBT, LDRHT, LDRSHT are for disassembly only.
1735 let mayLoad = 1, neverHasSideEffects = 1 in {
1736 def LDRT : AI2ldstidx<1, 0, 0, (outs GPR:$Rt, GPR:$base_wb),
1737 (ins addrmode2:$addr), IndexModePost, LdFrm, IIC_iLoad_ru,
1738 "ldrt", "\t$Rt, $addr", "$addr.base = $base_wb", []> {
1740 // {13} 1 == Rm, 0 == imm12
1744 let Inst{25} = addr{13};
1745 let Inst{23} = addr{12};
1746 let Inst{21} = 1; // overwrite
1747 let Inst{19-16} = addr{17-14};
1748 let Inst{11-0} = addr{11-0};
1749 let AsmMatchConverter = "CvtLdWriteBackRegAddrMode2";
1751 def LDRBT : AI2ldstidx<1, 1, 0, (outs GPR:$Rt, GPR:$base_wb),
1752 (ins addrmode2:$addr), IndexModePost, LdFrm, IIC_iLoad_bh_ru,
1753 "ldrbt", "\t$Rt, $addr", "$addr.base = $base_wb", []> {
1755 // {13} 1 == Rm, 0 == imm12
1759 let Inst{25} = addr{13};
1760 let Inst{23} = addr{12};
1761 let Inst{21} = 1; // overwrite
1762 let Inst{19-16} = addr{17-14};
1763 let Inst{11-0} = addr{11-0};
1764 let AsmMatchConverter = "CvtLdWriteBackRegAddrMode2";
1766 def LDRSBT : AI3ldstidx<0b1101, 1, 1, 0, (outs GPR:$dst, GPR:$base_wb),
1767 (ins GPR:$base, am3offset:$offset), IndexModePost,
1768 LdMiscFrm, IIC_iLoad_bh_ru,
1769 "ldrsbt", "\t$dst, [$base], $offset", "$base = $base_wb", []> {
1770 let Inst{21} = 1; // overwrite
1772 def LDRHT : AI3ldstidx<0b1011, 1, 1, 0, (outs GPR:$dst, GPR:$base_wb),
1773 (ins GPR:$base, am3offset:$offset), IndexModePost,
1774 LdMiscFrm, IIC_iLoad_bh_ru,
1775 "ldrht", "\t$dst, [$base], $offset", "$base = $base_wb", []> {
1776 let Inst{21} = 1; // overwrite
1778 def LDRSHT : AI3ldstidx<0b1111, 1, 1, 0, (outs GPR:$dst, GPR:$base_wb),
1779 (ins GPR:$base, am3offset:$offset), IndexModePost,
1780 LdMiscFrm, IIC_iLoad_bh_ru,
1781 "ldrsht", "\t$dst, [$base], $offset", "$base = $base_wb", []> {
1782 let Inst{21} = 1; // overwrite
1788 // Stores with truncate
1789 def STRH : AI3str<0b1011, (outs), (ins GPR:$Rt, addrmode3:$addr), StMiscFrm,
1790 IIC_iStore_bh_r, "strh", "\t$Rt, $addr",
1791 [(truncstorei16 GPR:$Rt, addrmode3:$addr)]>;
1794 let mayStore = 1, neverHasSideEffects = 1, hasExtraSrcRegAllocReq = 1 in
1795 def STRD : AI3str<0b1111, (outs), (ins GPR:$Rt, GPR:$src2, addrmode3:$addr),
1796 StMiscFrm, IIC_iStore_d_r,
1797 "strd", "\t$Rt, $src2, $addr", []>, Requires<[IsARM, HasV5TE]>;
1800 def STR_PRE : AI2stridx<0, 1, (outs GPR:$Rn_wb),
1801 (ins GPR:$Rt, GPR:$Rn, am2offset:$offset),
1802 IndexModePre, StFrm, IIC_iStore_ru,
1803 "str", "\t$Rt, [$Rn, $offset]!", "$Rn = $Rn_wb",
1805 (pre_store GPR:$Rt, GPR:$Rn, am2offset:$offset))]>;
1807 def STR_POST : AI2stridx<0, 0, (outs GPR:$Rn_wb),
1808 (ins GPR:$Rt, GPR:$Rn, am2offset:$offset),
1809 IndexModePost, StFrm, IIC_iStore_ru,
1810 "str", "\t$Rt, [$Rn], $offset", "$Rn = $Rn_wb",
1812 (post_store GPR:$Rt, GPR:$Rn, am2offset:$offset))]>;
1814 def STRB_PRE : AI2stridx<1, 1, (outs GPR:$Rn_wb),
1815 (ins GPR:$Rt, GPR:$Rn, am2offset:$offset),
1816 IndexModePre, StFrm, IIC_iStore_bh_ru,
1817 "strb", "\t$Rt, [$Rn, $offset]!", "$Rn = $Rn_wb",
1818 [(set GPR:$Rn_wb, (pre_truncsti8 GPR:$Rt,
1819 GPR:$Rn, am2offset:$offset))]>;
1820 def STRB_POST: AI2stridx<1, 0, (outs GPR:$Rn_wb),
1821 (ins GPR:$Rt, GPR:$Rn, am2offset:$offset),
1822 IndexModePost, StFrm, IIC_iStore_bh_ru,
1823 "strb", "\t$Rt, [$Rn], $offset", "$Rn = $Rn_wb",
1824 [(set GPR:$Rn_wb, (post_truncsti8 GPR:$Rt,
1825 GPR:$Rn, am2offset:$offset))]>;
1827 def STRH_PRE : AI3stridx<0b1011, 0, 1, (outs GPR:$Rn_wb),
1828 (ins GPR:$Rt, GPR:$Rn, am3offset:$offset),
1829 IndexModePre, StMiscFrm, IIC_iStore_ru,
1830 "strh", "\t$Rt, [$Rn, $offset]!", "$Rn = $Rn_wb",
1832 (pre_truncsti16 GPR:$Rt, GPR:$Rn, am3offset:$offset))]>;
1834 def STRH_POST: AI3stridx<0b1011, 0, 0, (outs GPR:$Rn_wb),
1835 (ins GPR:$Rt, GPR:$Rn, am3offset:$offset),
1836 IndexModePost, StMiscFrm, IIC_iStore_bh_ru,
1837 "strh", "\t$Rt, [$Rn], $offset", "$Rn = $Rn_wb",
1838 [(set GPR:$Rn_wb, (post_truncsti16 GPR:$Rt,
1839 GPR:$Rn, am3offset:$offset))]>;
1841 // For disassembly only
1842 def STRD_PRE : AI3stdpr<(outs GPR:$base_wb),
1843 (ins GPR:$src1, GPR:$src2, GPR:$base, am3offset:$offset),
1844 StMiscFrm, IIC_iStore_d_ru,
1845 "strd", "\t$src1, $src2, [$base, $offset]!",
1846 "$base = $base_wb", []>;
1848 // For disassembly only
1849 def STRD_POST: AI3stdpo<(outs GPR:$base_wb),
1850 (ins GPR:$src1, GPR:$src2, GPR:$base, am3offset:$offset),
1851 StMiscFrm, IIC_iStore_d_ru,
1852 "strd", "\t$src1, $src2, [$base], $offset",
1853 "$base = $base_wb", []>;
1855 // STRT, STRBT, and STRHT are for disassembly only.
1857 def STRT : AI2stridxT<0, 0, (outs GPR:$Rn_wb), (ins GPR:$Rt, addrmode2:$addr),
1858 IndexModePost, StFrm, IIC_iStore_ru,
1859 "strt", "\t$Rt, $addr", "$addr.base = $Rn_wb",
1860 [/* For disassembly only; pattern left blank */]> {
1861 let Inst{21} = 1; // overwrite
1862 let AsmMatchConverter = "CvtStWriteBackRegAddrMode2";
1865 def STRBT : AI2stridxT<1, 0, (outs GPR:$Rn_wb), (ins GPR:$Rt, addrmode2:$addr),
1866 IndexModePost, StFrm, IIC_iStore_bh_ru,
1867 "strbt", "\t$Rt, $addr", "$addr.base = $Rn_wb",
1868 [/* For disassembly only; pattern left blank */]> {
1869 let Inst{21} = 1; // overwrite
1870 let AsmMatchConverter = "CvtStWriteBackRegAddrMode2";
1873 def STRHT: AI3sthpo<(outs GPR:$base_wb),
1874 (ins GPR:$src, GPR:$base,am3offset:$offset),
1875 StMiscFrm, IIC_iStore_bh_ru,
1876 "strht", "\t$src, [$base], $offset", "$base = $base_wb",
1877 [/* For disassembly only; pattern left blank */]> {
1878 let Inst{21} = 1; // overwrite
1881 //===----------------------------------------------------------------------===//
1882 // Load / store multiple Instructions.
1885 multiclass arm_ldst_mult<string asm, bit L_bit, Format f,
1886 InstrItinClass itin, InstrItinClass itin_upd> {
1888 AXI4<(outs), (ins GPR:$Rn, pred:$p, reglist:$regs, variable_ops),
1889 IndexModeNone, f, itin,
1890 !strconcat(asm, "ia${p}\t$Rn, $regs"), "", []> {
1891 let Inst{24-23} = 0b01; // Increment After
1892 let Inst{21} = 0; // No writeback
1893 let Inst{20} = L_bit;
1896 AXI4<(outs GPR:$wb), (ins GPR:$Rn, pred:$p, reglist:$regs, variable_ops),
1897 IndexModeUpd, f, itin_upd,
1898 !strconcat(asm, "ia${p}\t$Rn!, $regs"), "$Rn = $wb", []> {
1899 let Inst{24-23} = 0b01; // Increment After
1900 let Inst{21} = 1; // Writeback
1901 let Inst{20} = L_bit;
1904 AXI4<(outs), (ins GPR:$Rn, pred:$p, reglist:$regs, variable_ops),
1905 IndexModeNone, f, itin,
1906 !strconcat(asm, "da${p}\t$Rn, $regs"), "", []> {
1907 let Inst{24-23} = 0b00; // Decrement After
1908 let Inst{21} = 0; // No writeback
1909 let Inst{20} = L_bit;
1912 AXI4<(outs GPR:$wb), (ins GPR:$Rn, pred:$p, reglist:$regs, variable_ops),
1913 IndexModeUpd, f, itin_upd,
1914 !strconcat(asm, "da${p}\t$Rn!, $regs"), "$Rn = $wb", []> {
1915 let Inst{24-23} = 0b00; // Decrement After
1916 let Inst{21} = 1; // Writeback
1917 let Inst{20} = L_bit;
1920 AXI4<(outs), (ins GPR:$Rn, pred:$p, reglist:$regs, variable_ops),
1921 IndexModeNone, f, itin,
1922 !strconcat(asm, "db${p}\t$Rn, $regs"), "", []> {
1923 let Inst{24-23} = 0b10; // Decrement Before
1924 let Inst{21} = 0; // No writeback
1925 let Inst{20} = L_bit;
1928 AXI4<(outs GPR:$wb), (ins GPR:$Rn, pred:$p, reglist:$regs, variable_ops),
1929 IndexModeUpd, f, itin_upd,
1930 !strconcat(asm, "db${p}\t$Rn!, $regs"), "$Rn = $wb", []> {
1931 let Inst{24-23} = 0b10; // Decrement Before
1932 let Inst{21} = 1; // Writeback
1933 let Inst{20} = L_bit;
1936 AXI4<(outs), (ins GPR:$Rn, pred:$p, reglist:$regs, variable_ops),
1937 IndexModeNone, f, itin,
1938 !strconcat(asm, "ib${p}\t$Rn, $regs"), "", []> {
1939 let Inst{24-23} = 0b11; // Increment Before
1940 let Inst{21} = 0; // No writeback
1941 let Inst{20} = L_bit;
1944 AXI4<(outs GPR:$wb), (ins GPR:$Rn, pred:$p, reglist:$regs, variable_ops),
1945 IndexModeUpd, f, itin_upd,
1946 !strconcat(asm, "ib${p}\t$Rn!, $regs"), "$Rn = $wb", []> {
1947 let Inst{24-23} = 0b11; // Increment Before
1948 let Inst{21} = 1; // Writeback
1949 let Inst{20} = L_bit;
1953 let neverHasSideEffects = 1 in {
1955 let mayLoad = 1, hasExtraDefRegAllocReq = 1 in
1956 defm LDM : arm_ldst_mult<"ldm", 1, LdStMulFrm, IIC_iLoad_m, IIC_iLoad_mu>;
1958 let mayStore = 1, hasExtraSrcRegAllocReq = 1 in
1959 defm STM : arm_ldst_mult<"stm", 0, LdStMulFrm, IIC_iStore_m, IIC_iStore_mu>;
1961 } // neverHasSideEffects
1963 // Load / Store Multiple Mnemonic Aliases
1964 def : MnemonicAlias<"ldm", "ldmia">;
1965 def : MnemonicAlias<"stm", "stmia">;
1967 // FIXME: remove when we have a way to marking a MI with these properties.
1968 // FIXME: Should pc be an implicit operand like PICADD, etc?
1969 let isReturn = 1, isTerminator = 1, isBarrier = 1, mayLoad = 1,
1970 hasExtraDefRegAllocReq = 1, isCodeGenOnly = 1 in
1971 def LDMIA_RET : ARMPseudoInst<(outs GPR:$wb), (ins GPR:$Rn, pred:$p,
1972 reglist:$regs, variable_ops),
1973 Size4Bytes, IIC_iLoad_mBr, []>,
1974 RegConstraint<"$Rn = $wb">;
1976 //===----------------------------------------------------------------------===//
1977 // Move Instructions.
1980 let neverHasSideEffects = 1 in
1981 def MOVr : AsI1<0b1101, (outs GPR:$Rd), (ins GPR:$Rm), DPFrm, IIC_iMOVr,
1982 "mov", "\t$Rd, $Rm", []>, UnaryDP {
1986 let Inst{19-16} = 0b0000;
1987 let Inst{11-4} = 0b00000000;
1990 let Inst{15-12} = Rd;
1993 // A version for the smaller set of tail call registers.
1994 let neverHasSideEffects = 1 in
1995 def MOVr_TC : AsI1<0b1101, (outs tcGPR:$Rd), (ins tcGPR:$Rm), DPFrm,
1996 IIC_iMOVr, "mov", "\t$Rd, $Rm", []>, UnaryDP {
2000 let Inst{11-4} = 0b00000000;
2003 let Inst{15-12} = Rd;
2006 def MOVs : AsI1<0b1101, (outs GPR:$Rd), (ins shift_so_reg:$src),
2007 DPSoRegFrm, IIC_iMOVsr,
2008 "mov", "\t$Rd, $src", [(set GPR:$Rd, shift_so_reg:$src)]>,
2012 let Inst{15-12} = Rd;
2013 let Inst{19-16} = 0b0000;
2014 let Inst{11-0} = src;
2018 let isReMaterializable = 1, isAsCheapAsAMove = 1, isMoveImm = 1 in
2019 def MOVi : AsI1<0b1101, (outs GPR:$Rd), (ins so_imm:$imm), DPFrm, IIC_iMOVi,
2020 "mov", "\t$Rd, $imm", [(set GPR:$Rd, so_imm:$imm)]>, UnaryDP {
2024 let Inst{15-12} = Rd;
2025 let Inst{19-16} = 0b0000;
2026 let Inst{11-0} = imm;
2029 let isReMaterializable = 1, isAsCheapAsAMove = 1, isMoveImm = 1 in
2030 def MOVi16 : AI1<0b1000, (outs GPR:$Rd), (ins i32imm_hilo16:$imm),
2032 "movw", "\t$Rd, $imm",
2033 [(set GPR:$Rd, imm0_65535:$imm)]>,
2034 Requires<[IsARM, HasV6T2]>, UnaryDP {
2037 let Inst{15-12} = Rd;
2038 let Inst{11-0} = imm{11-0};
2039 let Inst{19-16} = imm{15-12};
2044 def MOVi16_ga_pcrel : PseudoInst<(outs GPR:$Rd),
2045 (ins i32imm:$addr, pclabel:$id), IIC_iMOVi, []>;
2047 let Constraints = "$src = $Rd" in {
2048 def MOVTi16 : AI1<0b1010, (outs GPR:$Rd), (ins GPR:$src, i32imm_hilo16:$imm),
2050 "movt", "\t$Rd, $imm",
2052 (or (and GPR:$src, 0xffff),
2053 lo16AllZero:$imm))]>, UnaryDP,
2054 Requires<[IsARM, HasV6T2]> {
2057 let Inst{15-12} = Rd;
2058 let Inst{11-0} = imm{11-0};
2059 let Inst{19-16} = imm{15-12};
2064 def MOVTi16_ga_pcrel : PseudoInst<(outs GPR:$Rd),
2065 (ins GPR:$src, i32imm:$addr, pclabel:$id), IIC_iMOVi, []>;
2069 def : ARMPat<(or GPR:$src, 0xffff0000), (MOVTi16 GPR:$src, 0xffff)>,
2070 Requires<[IsARM, HasV6T2]>;
2072 let Uses = [CPSR] in
2073 def RRX: PseudoInst<(outs GPR:$Rd), (ins GPR:$Rm), IIC_iMOVsi,
2074 [(set GPR:$Rd, (ARMrrx GPR:$Rm))]>, UnaryDP,
2077 // These aren't really mov instructions, but we have to define them this way
2078 // due to flag operands.
2080 let Defs = [CPSR] in {
2081 def MOVsrl_flag : PseudoInst<(outs GPR:$dst), (ins GPR:$src), IIC_iMOVsi,
2082 [(set GPR:$dst, (ARMsrl_flag GPR:$src))]>, UnaryDP,
2084 def MOVsra_flag : PseudoInst<(outs GPR:$dst), (ins GPR:$src), IIC_iMOVsi,
2085 [(set GPR:$dst, (ARMsra_flag GPR:$src))]>, UnaryDP,
2089 //===----------------------------------------------------------------------===//
2090 // Extend Instructions.
2095 defm SXTB : AI_ext_rrot<0b01101010,
2096 "sxtb", UnOpFrag<(sext_inreg node:$Src, i8)>>;
2097 defm SXTH : AI_ext_rrot<0b01101011,
2098 "sxth", UnOpFrag<(sext_inreg node:$Src, i16)>>;
2100 defm SXTAB : AI_exta_rrot<0b01101010,
2101 "sxtab", BinOpFrag<(add node:$LHS, (sext_inreg node:$RHS, i8))>>;
2102 defm SXTAH : AI_exta_rrot<0b01101011,
2103 "sxtah", BinOpFrag<(add node:$LHS, (sext_inreg node:$RHS,i16))>>;
2105 // For disassembly only
2106 defm SXTB16 : AI_ext_rrot_np<0b01101000, "sxtb16">;
2108 // For disassembly only
2109 defm SXTAB16 : AI_exta_rrot_np<0b01101000, "sxtab16">;
2113 let AddedComplexity = 16 in {
2114 defm UXTB : AI_ext_rrot<0b01101110,
2115 "uxtb" , UnOpFrag<(and node:$Src, 0x000000FF)>>;
2116 defm UXTH : AI_ext_rrot<0b01101111,
2117 "uxth" , UnOpFrag<(and node:$Src, 0x0000FFFF)>>;
2118 defm UXTB16 : AI_ext_rrot<0b01101100,
2119 "uxtb16", UnOpFrag<(and node:$Src, 0x00FF00FF)>>;
2121 // FIXME: This pattern incorrectly assumes the shl operator is a rotate.
2122 // The transformation should probably be done as a combiner action
2123 // instead so we can include a check for masking back in the upper
2124 // eight bits of the source into the lower eight bits of the result.
2125 //def : ARMV6Pat<(and (shl GPR:$Src, (i32 8)), 0xFF00FF),
2126 // (UXTB16r_rot GPR:$Src, 24)>;
2127 def : ARMV6Pat<(and (srl GPR:$Src, (i32 8)), 0xFF00FF),
2128 (UXTB16r_rot GPR:$Src, 8)>;
2130 defm UXTAB : AI_exta_rrot<0b01101110, "uxtab",
2131 BinOpFrag<(add node:$LHS, (and node:$RHS, 0x00FF))>>;
2132 defm UXTAH : AI_exta_rrot<0b01101111, "uxtah",
2133 BinOpFrag<(add node:$LHS, (and node:$RHS, 0xFFFF))>>;
2136 // This isn't safe in general, the add is two 16-bit units, not a 32-bit add.
2137 // For disassembly only
2138 defm UXTAB16 : AI_exta_rrot_np<0b01101100, "uxtab16">;
2141 def SBFX : I<(outs GPR:$Rd),
2142 (ins GPR:$Rn, imm0_31:$lsb, imm0_31_m1:$width),
2143 AddrMode1, Size4Bytes, IndexModeNone, DPFrm, IIC_iUNAsi,
2144 "sbfx", "\t$Rd, $Rn, $lsb, $width", "", []>,
2145 Requires<[IsARM, HasV6T2]> {
2150 let Inst{27-21} = 0b0111101;
2151 let Inst{6-4} = 0b101;
2152 let Inst{20-16} = width;
2153 let Inst{15-12} = Rd;
2154 let Inst{11-7} = lsb;
2158 def UBFX : I<(outs GPR:$Rd),
2159 (ins GPR:$Rn, imm0_31:$lsb, imm0_31_m1:$width),
2160 AddrMode1, Size4Bytes, IndexModeNone, DPFrm, IIC_iUNAsi,
2161 "ubfx", "\t$Rd, $Rn, $lsb, $width", "", []>,
2162 Requires<[IsARM, HasV6T2]> {
2167 let Inst{27-21} = 0b0111111;
2168 let Inst{6-4} = 0b101;
2169 let Inst{20-16} = width;
2170 let Inst{15-12} = Rd;
2171 let Inst{11-7} = lsb;
2175 //===----------------------------------------------------------------------===//
2176 // Arithmetic Instructions.
2179 defm ADD : AsI1_bin_irs<0b0100, "add",
2180 IIC_iALUi, IIC_iALUr, IIC_iALUsr,
2181 BinOpFrag<(add node:$LHS, node:$RHS)>, 1>;
2182 defm SUB : AsI1_bin_irs<0b0010, "sub",
2183 IIC_iALUi, IIC_iALUr, IIC_iALUsr,
2184 BinOpFrag<(sub node:$LHS, node:$RHS)>>;
2186 // ADD and SUB with 's' bit set.
2187 defm ADDS : AI1_bin_s_irs<0b0100, "adds",
2188 IIC_iALUi, IIC_iALUr, IIC_iALUsr,
2189 BinOpFrag<(addc node:$LHS, node:$RHS)>, 1>;
2190 defm SUBS : AI1_bin_s_irs<0b0010, "subs",
2191 IIC_iALUi, IIC_iALUr, IIC_iALUsr,
2192 BinOpFrag<(subc node:$LHS, node:$RHS)>>;
2194 defm ADC : AI1_adde_sube_irs<0b0101, "adc",
2195 BinOpFrag<(adde_dead_carry node:$LHS, node:$RHS)>, 1>;
2196 defm SBC : AI1_adde_sube_irs<0b0110, "sbc",
2197 BinOpFrag<(sube_dead_carry node:$LHS, node:$RHS)>>;
2199 // ADC and SUBC with 's' bit set.
2200 defm ADCS : AI1_adde_sube_s_irs<0b0101, "adcs",
2201 BinOpFrag<(adde_live_carry node:$LHS, node:$RHS)>, 1>;
2202 defm SBCS : AI1_adde_sube_s_irs<0b0110, "sbcs",
2203 BinOpFrag<(sube_live_carry node:$LHS, node:$RHS) >>;
2205 def RSBri : AsI1<0b0011, (outs GPR:$Rd), (ins GPR:$Rn, so_imm:$imm), DPFrm,
2206 IIC_iALUi, "rsb", "\t$Rd, $Rn, $imm",
2207 [(set GPR:$Rd, (sub so_imm:$imm, GPR:$Rn))]> {
2212 let Inst{15-12} = Rd;
2213 let Inst{19-16} = Rn;
2214 let Inst{11-0} = imm;
2217 // The reg/reg form is only defined for the disassembler; for codegen it is
2218 // equivalent to SUBrr.
2219 def RSBrr : AsI1<0b0011, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm), DPFrm,
2220 IIC_iALUr, "rsb", "\t$Rd, $Rn, $Rm",
2221 [/* For disassembly only; pattern left blank */]> {
2225 let Inst{11-4} = 0b00000000;
2228 let Inst{15-12} = Rd;
2229 let Inst{19-16} = Rn;
2232 def RSBrs : AsI1<0b0011, (outs GPR:$Rd), (ins GPR:$Rn, so_reg:$shift),
2233 DPSoRegFrm, IIC_iALUsr, "rsb", "\t$Rd, $Rn, $shift",
2234 [(set GPR:$Rd, (sub so_reg:$shift, GPR:$Rn))]> {
2239 let Inst{11-0} = shift;
2240 let Inst{15-12} = Rd;
2241 let Inst{19-16} = Rn;
2244 // RSB with 's' bit set.
2245 let isCodeGenOnly = 1, Defs = [CPSR] in {
2246 def RSBSri : AI1<0b0011, (outs GPR:$Rd), (ins GPR:$Rn, so_imm:$imm), DPFrm,
2247 IIC_iALUi, "rsbs", "\t$Rd, $Rn, $imm",
2248 [(set GPR:$Rd, (subc so_imm:$imm, GPR:$Rn))]> {
2254 let Inst{15-12} = Rd;
2255 let Inst{19-16} = Rn;
2256 let Inst{11-0} = imm;
2258 def RSBSrr : AI1<0b0011, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm), DPFrm,
2259 IIC_iALUr, "rsbs", "\t$Rd, $Rn, $Rm",
2260 [/* For disassembly only; pattern left blank */]> {
2264 let Inst{11-4} = 0b00000000;
2268 let Inst{15-12} = Rd;
2269 let Inst{19-16} = Rn;
2271 def RSBSrs : AI1<0b0011, (outs GPR:$Rd), (ins GPR:$Rn, so_reg:$shift),
2272 DPSoRegFrm, IIC_iALUsr, "rsbs", "\t$Rd, $Rn, $shift",
2273 [(set GPR:$Rd, (subc so_reg:$shift, GPR:$Rn))]> {
2279 let Inst{11-0} = shift;
2280 let Inst{15-12} = Rd;
2281 let Inst{19-16} = Rn;
2285 let Uses = [CPSR] in {
2286 def RSCri : AsI1<0b0111, (outs GPR:$Rd), (ins GPR:$Rn, so_imm:$imm),
2287 DPFrm, IIC_iALUi, "rsc", "\t$Rd, $Rn, $imm",
2288 [(set GPR:$Rd, (sube_dead_carry so_imm:$imm, GPR:$Rn))]>,
2294 let Inst{15-12} = Rd;
2295 let Inst{19-16} = Rn;
2296 let Inst{11-0} = imm;
2298 // The reg/reg form is only defined for the disassembler; for codegen it is
2299 // equivalent to SUBrr.
2300 def RSCrr : AsI1<0b0111, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm),
2301 DPFrm, IIC_iALUr, "rsc", "\t$Rd, $Rn, $Rm",
2302 [/* For disassembly only; pattern left blank */]> {
2306 let Inst{11-4} = 0b00000000;
2309 let Inst{15-12} = Rd;
2310 let Inst{19-16} = Rn;
2312 def RSCrs : AsI1<0b0111, (outs GPR:$Rd), (ins GPR:$Rn, so_reg:$shift),
2313 DPSoRegFrm, IIC_iALUsr, "rsc", "\t$Rd, $Rn, $shift",
2314 [(set GPR:$Rd, (sube_dead_carry so_reg:$shift, GPR:$Rn))]>,
2320 let Inst{11-0} = shift;
2321 let Inst{15-12} = Rd;
2322 let Inst{19-16} = Rn;
2326 // FIXME: Allow these to be predicated.
2327 let isCodeGenOnly = 1, Defs = [CPSR], Uses = [CPSR] in {
2328 def RSCSri : AXI1<0b0111, (outs GPR:$Rd), (ins GPR:$Rn, so_imm:$imm),
2329 DPFrm, IIC_iALUi, "rscs\t$Rd, $Rn, $imm",
2330 [(set GPR:$Rd, (sube_dead_carry so_imm:$imm, GPR:$Rn))]>,
2337 let Inst{15-12} = Rd;
2338 let Inst{19-16} = Rn;
2339 let Inst{11-0} = imm;
2341 def RSCSrs : AXI1<0b0111, (outs GPR:$Rd), (ins GPR:$Rn, so_reg:$shift),
2342 DPSoRegFrm, IIC_iALUsr, "rscs\t$Rd, $Rn, $shift",
2343 [(set GPR:$Rd, (sube_dead_carry so_reg:$shift, GPR:$Rn))]>,
2350 let Inst{11-0} = shift;
2351 let Inst{15-12} = Rd;
2352 let Inst{19-16} = Rn;
2356 // (sub X, imm) gets canonicalized to (add X, -imm). Match this form.
2357 // The assume-no-carry-in form uses the negation of the input since add/sub
2358 // assume opposite meanings of the carry flag (i.e., carry == !borrow).
2359 // See the definition of AddWithCarry() in the ARM ARM A2.2.1 for the gory
2361 def : ARMPat<(add GPR:$src, so_imm_neg:$imm),
2362 (SUBri GPR:$src, so_imm_neg:$imm)>;
2363 def : ARMPat<(addc GPR:$src, so_imm_neg:$imm),
2364 (SUBSri GPR:$src, so_imm_neg:$imm)>;
2365 // The with-carry-in form matches bitwise not instead of the negation.
2366 // Effectively, the inverse interpretation of the carry flag already accounts
2367 // for part of the negation.
2368 def : ARMPat<(adde GPR:$src, so_imm_not:$imm),
2369 (SBCri GPR:$src, so_imm_not:$imm)>;
2371 // Note: These are implemented in C++ code, because they have to generate
2372 // ADD/SUBrs instructions, which use a complex pattern that a xform function
2374 // (mul X, 2^n+1) -> (add (X << n), X)
2375 // (mul X, 2^n-1) -> (rsb X, (X << n))
2377 // ARM Arithmetic Instruction -- for disassembly only
2378 // GPR:$dst = GPR:$a op GPR:$b
2379 class AAI<bits<8> op27_20, bits<8> op11_4, string opc,
2380 list<dag> pattern = [/* For disassembly only; pattern left blank */],
2381 dag iops = (ins GPR:$Rn, GPR:$Rm), string asm = "\t$Rd, $Rn, $Rm">
2382 : AI<(outs GPR:$Rd), iops, DPFrm, IIC_iALUr, opc, asm, pattern> {
2386 let Inst{27-20} = op27_20;
2387 let Inst{11-4} = op11_4;
2388 let Inst{19-16} = Rn;
2389 let Inst{15-12} = Rd;
2393 // Saturating add/subtract -- for disassembly only
2395 def QADD : AAI<0b00010000, 0b00000101, "qadd",
2396 [(set GPR:$Rd, (int_arm_qadd GPR:$Rm, GPR:$Rn))],
2397 (ins GPR:$Rm, GPR:$Rn), "\t$Rd, $Rm, $Rn">;
2398 def QSUB : AAI<0b00010010, 0b00000101, "qsub",
2399 [(set GPR:$Rd, (int_arm_qsub GPR:$Rm, GPR:$Rn))],
2400 (ins GPR:$Rm, GPR:$Rn), "\t$Rd, $Rm, $Rn">;
2401 def QDADD : AAI<0b00010100, 0b00000101, "qdadd", [], (ins GPR:$Rm, GPR:$Rn),
2403 def QDSUB : AAI<0b00010110, 0b00000101, "qdsub", [], (ins GPR:$Rm, GPR:$Rn),
2406 def QADD16 : AAI<0b01100010, 0b11110001, "qadd16">;
2407 def QADD8 : AAI<0b01100010, 0b11111001, "qadd8">;
2408 def QASX : AAI<0b01100010, 0b11110011, "qasx">;
2409 def QSAX : AAI<0b01100010, 0b11110101, "qsax">;
2410 def QSUB16 : AAI<0b01100010, 0b11110111, "qsub16">;
2411 def QSUB8 : AAI<0b01100010, 0b11111111, "qsub8">;
2412 def UQADD16 : AAI<0b01100110, 0b11110001, "uqadd16">;
2413 def UQADD8 : AAI<0b01100110, 0b11111001, "uqadd8">;
2414 def UQASX : AAI<0b01100110, 0b11110011, "uqasx">;
2415 def UQSAX : AAI<0b01100110, 0b11110101, "uqsax">;
2416 def UQSUB16 : AAI<0b01100110, 0b11110111, "uqsub16">;
2417 def UQSUB8 : AAI<0b01100110, 0b11111111, "uqsub8">;
2419 // Signed/Unsigned add/subtract -- for disassembly only
2421 def SASX : AAI<0b01100001, 0b11110011, "sasx">;
2422 def SADD16 : AAI<0b01100001, 0b11110001, "sadd16">;
2423 def SADD8 : AAI<0b01100001, 0b11111001, "sadd8">;
2424 def SSAX : AAI<0b01100001, 0b11110101, "ssax">;
2425 def SSUB16 : AAI<0b01100001, 0b11110111, "ssub16">;
2426 def SSUB8 : AAI<0b01100001, 0b11111111, "ssub8">;
2427 def UASX : AAI<0b01100101, 0b11110011, "uasx">;
2428 def UADD16 : AAI<0b01100101, 0b11110001, "uadd16">;
2429 def UADD8 : AAI<0b01100101, 0b11111001, "uadd8">;
2430 def USAX : AAI<0b01100101, 0b11110101, "usax">;
2431 def USUB16 : AAI<0b01100101, 0b11110111, "usub16">;
2432 def USUB8 : AAI<0b01100101, 0b11111111, "usub8">;
2434 // Signed/Unsigned halving add/subtract -- for disassembly only
2436 def SHASX : AAI<0b01100011, 0b11110011, "shasx">;
2437 def SHADD16 : AAI<0b01100011, 0b11110001, "shadd16">;
2438 def SHADD8 : AAI<0b01100011, 0b11111001, "shadd8">;
2439 def SHSAX : AAI<0b01100011, 0b11110101, "shsax">;
2440 def SHSUB16 : AAI<0b01100011, 0b11110111, "shsub16">;
2441 def SHSUB8 : AAI<0b01100011, 0b11111111, "shsub8">;
2442 def UHASX : AAI<0b01100111, 0b11110011, "uhasx">;
2443 def UHADD16 : AAI<0b01100111, 0b11110001, "uhadd16">;
2444 def UHADD8 : AAI<0b01100111, 0b11111001, "uhadd8">;
2445 def UHSAX : AAI<0b01100111, 0b11110101, "uhsax">;
2446 def UHSUB16 : AAI<0b01100111, 0b11110111, "uhsub16">;
2447 def UHSUB8 : AAI<0b01100111, 0b11111111, "uhsub8">;
2449 // Unsigned Sum of Absolute Differences [and Accumulate] -- for disassembly only
2451 def USAD8 : AI<(outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm),
2452 MulFrm /* for convenience */, NoItinerary, "usad8",
2453 "\t$Rd, $Rn, $Rm", []>,
2454 Requires<[IsARM, HasV6]> {
2458 let Inst{27-20} = 0b01111000;
2459 let Inst{15-12} = 0b1111;
2460 let Inst{7-4} = 0b0001;
2461 let Inst{19-16} = Rd;
2462 let Inst{11-8} = Rm;
2465 def USADA8 : AI<(outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm, GPR:$Ra),
2466 MulFrm /* for convenience */, NoItinerary, "usada8",
2467 "\t$Rd, $Rn, $Rm, $Ra", []>,
2468 Requires<[IsARM, HasV6]> {
2473 let Inst{27-20} = 0b01111000;
2474 let Inst{7-4} = 0b0001;
2475 let Inst{19-16} = Rd;
2476 let Inst{15-12} = Ra;
2477 let Inst{11-8} = Rm;
2481 // Signed/Unsigned saturate -- for disassembly only
2483 def SSAT : AI<(outs GPR:$Rd), (ins i32imm:$sat_imm, GPR:$a, shift_imm:$sh),
2484 SatFrm, NoItinerary, "ssat", "\t$Rd, $sat_imm, $a$sh",
2485 [/* For disassembly only; pattern left blank */]> {
2490 let Inst{27-21} = 0b0110101;
2491 let Inst{5-4} = 0b01;
2492 let Inst{20-16} = sat_imm;
2493 let Inst{15-12} = Rd;
2494 let Inst{11-7} = sh{7-3};
2495 let Inst{6} = sh{0};
2499 def SSAT16 : AI<(outs GPR:$Rd), (ins i32imm:$sat_imm, GPR:$Rn), SatFrm,
2500 NoItinerary, "ssat16", "\t$Rd, $sat_imm, $Rn",
2501 [/* For disassembly only; pattern left blank */]> {
2505 let Inst{27-20} = 0b01101010;
2506 let Inst{11-4} = 0b11110011;
2507 let Inst{15-12} = Rd;
2508 let Inst{19-16} = sat_imm;
2512 def USAT : AI<(outs GPR:$Rd), (ins i32imm:$sat_imm, GPR:$a, shift_imm:$sh),
2513 SatFrm, NoItinerary, "usat", "\t$Rd, $sat_imm, $a$sh",
2514 [/* For disassembly only; pattern left blank */]> {
2519 let Inst{27-21} = 0b0110111;
2520 let Inst{5-4} = 0b01;
2521 let Inst{15-12} = Rd;
2522 let Inst{11-7} = sh{7-3};
2523 let Inst{6} = sh{0};
2524 let Inst{20-16} = sat_imm;
2528 def USAT16 : AI<(outs GPR:$Rd), (ins i32imm:$sat_imm, GPR:$a), SatFrm,
2529 NoItinerary, "usat16", "\t$Rd, $sat_imm, $a",
2530 [/* For disassembly only; pattern left blank */]> {
2534 let Inst{27-20} = 0b01101110;
2535 let Inst{11-4} = 0b11110011;
2536 let Inst{15-12} = Rd;
2537 let Inst{19-16} = sat_imm;
2541 def : ARMV6Pat<(int_arm_ssat GPR:$a, imm:$pos), (SSAT imm:$pos, GPR:$a, 0)>;
2542 def : ARMV6Pat<(int_arm_usat GPR:$a, imm:$pos), (USAT imm:$pos, GPR:$a, 0)>;
2544 //===----------------------------------------------------------------------===//
2545 // Bitwise Instructions.
2548 defm AND : AsI1_bin_irs<0b0000, "and",
2549 IIC_iBITi, IIC_iBITr, IIC_iBITsr,
2550 BinOpFrag<(and node:$LHS, node:$RHS)>, 1>;
2551 defm ORR : AsI1_bin_irs<0b1100, "orr",
2552 IIC_iBITi, IIC_iBITr, IIC_iBITsr,
2553 BinOpFrag<(or node:$LHS, node:$RHS)>, 1>;
2554 defm EOR : AsI1_bin_irs<0b0001, "eor",
2555 IIC_iBITi, IIC_iBITr, IIC_iBITsr,
2556 BinOpFrag<(xor node:$LHS, node:$RHS)>, 1>;
2557 defm BIC : AsI1_bin_irs<0b1110, "bic",
2558 IIC_iBITi, IIC_iBITr, IIC_iBITsr,
2559 BinOpFrag<(and node:$LHS, (not node:$RHS))>>;
2561 def BFC : I<(outs GPR:$Rd), (ins GPR:$src, bf_inv_mask_imm:$imm),
2562 AddrMode1, Size4Bytes, IndexModeNone, DPFrm, IIC_iUNAsi,
2563 "bfc", "\t$Rd, $imm", "$src = $Rd",
2564 [(set GPR:$Rd, (and GPR:$src, bf_inv_mask_imm:$imm))]>,
2565 Requires<[IsARM, HasV6T2]> {
2568 let Inst{27-21} = 0b0111110;
2569 let Inst{6-0} = 0b0011111;
2570 let Inst{15-12} = Rd;
2571 let Inst{11-7} = imm{4-0}; // lsb
2572 let Inst{20-16} = imm{9-5}; // width
2575 // A8.6.18 BFI - Bitfield insert (Encoding A1)
2576 def BFI : I<(outs GPR:$Rd), (ins GPR:$src, GPR:$Rn, bf_inv_mask_imm:$imm),
2577 AddrMode1, Size4Bytes, IndexModeNone, DPFrm, IIC_iUNAsi,
2578 "bfi", "\t$Rd, $Rn, $imm", "$src = $Rd",
2579 [(set GPR:$Rd, (ARMbfi GPR:$src, GPR:$Rn,
2580 bf_inv_mask_imm:$imm))]>,
2581 Requires<[IsARM, HasV6T2]> {
2585 let Inst{27-21} = 0b0111110;
2586 let Inst{6-4} = 0b001; // Rn: Inst{3-0} != 15
2587 let Inst{15-12} = Rd;
2588 let Inst{11-7} = imm{4-0}; // lsb
2589 let Inst{20-16} = imm{9-5}; // width
2593 // GNU as only supports this form of bfi (w/ 4 arguments)
2594 let isAsmParserOnly = 1 in
2595 def BFI4p : I<(outs GPR:$Rd), (ins GPR:$src, GPR:$Rn,
2596 lsb_pos_imm:$lsb, width_imm:$width),
2597 AddrMode1, Size4Bytes, IndexModeNone, DPFrm, IIC_iUNAsi,
2598 "bfi", "\t$Rd, $Rn, $lsb, $width", "$src = $Rd",
2599 []>, Requires<[IsARM, HasV6T2]> {
2604 let Inst{27-21} = 0b0111110;
2605 let Inst{6-4} = 0b001; // Rn: Inst{3-0} != 15
2606 let Inst{15-12} = Rd;
2607 let Inst{11-7} = lsb;
2608 let Inst{20-16} = width; // Custom encoder => lsb+width-1
2612 def MVNr : AsI1<0b1111, (outs GPR:$Rd), (ins GPR:$Rm), DPFrm, IIC_iMVNr,
2613 "mvn", "\t$Rd, $Rm",
2614 [(set GPR:$Rd, (not GPR:$Rm))]>, UnaryDP {
2618 let Inst{19-16} = 0b0000;
2619 let Inst{11-4} = 0b00000000;
2620 let Inst{15-12} = Rd;
2623 def MVNs : AsI1<0b1111, (outs GPR:$Rd), (ins so_reg:$shift), DPSoRegFrm,
2624 IIC_iMVNsr, "mvn", "\t$Rd, $shift",
2625 [(set GPR:$Rd, (not so_reg:$shift))]>, UnaryDP {
2629 let Inst{19-16} = 0b0000;
2630 let Inst{15-12} = Rd;
2631 let Inst{11-0} = shift;
2633 let isReMaterializable = 1, isAsCheapAsAMove = 1, isMoveImm = 1 in
2634 def MVNi : AsI1<0b1111, (outs GPR:$Rd), (ins so_imm:$imm), DPFrm,
2635 IIC_iMVNi, "mvn", "\t$Rd, $imm",
2636 [(set GPR:$Rd, so_imm_not:$imm)]>,UnaryDP {
2640 let Inst{19-16} = 0b0000;
2641 let Inst{15-12} = Rd;
2642 let Inst{11-0} = imm;
2645 def : ARMPat<(and GPR:$src, so_imm_not:$imm),
2646 (BICri GPR:$src, so_imm_not:$imm)>;
2648 //===----------------------------------------------------------------------===//
2649 // Multiply Instructions.
2651 class AsMul1I32<bits<7> opcod, dag oops, dag iops, InstrItinClass itin,
2652 string opc, string asm, list<dag> pattern>
2653 : AsMul1I<opcod, oops, iops, itin, opc, asm, pattern> {
2657 let Inst{19-16} = Rd;
2658 let Inst{11-8} = Rm;
2661 class AsMul1I64<bits<7> opcod, dag oops, dag iops, InstrItinClass itin,
2662 string opc, string asm, list<dag> pattern>
2663 : AsMul1I<opcod, oops, iops, itin, opc, asm, pattern> {
2668 let Inst{19-16} = RdHi;
2669 let Inst{15-12} = RdLo;
2670 let Inst{11-8} = Rm;
2674 let isCommutable = 1 in {
2675 let Constraints = "@earlyclobber $Rd" in
2676 def MULv5: ARMPseudoInst<(outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm,
2677 pred:$p, cc_out:$s),
2678 Size4Bytes, IIC_iMUL32,
2679 [(set GPR:$Rd, (mul GPR:$Rn, GPR:$Rm))]>,
2680 Requires<[IsARM, NoV6]>;
2682 def MUL : AsMul1I32<0b0000000, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm),
2683 IIC_iMUL32, "mul", "\t$Rd, $Rn, $Rm",
2684 [(set GPR:$Rd, (mul GPR:$Rn, GPR:$Rm))]>,
2685 Requires<[IsARM, HasV6]>;
2688 let Constraints = "@earlyclobber $Rd" in
2689 def MLAv5: ARMPseudoInst<(outs GPR:$Rd),
2690 (ins GPR:$Rn, GPR:$Rm, GPR:$Ra, pred:$p, cc_out:$s),
2691 Size4Bytes, IIC_iMAC32,
2692 [(set GPR:$Rd, (add (mul GPR:$Rn, GPR:$Rm), GPR:$Ra))]>,
2693 Requires<[IsARM, NoV6]> {
2695 let Inst{15-12} = Ra;
2697 def MLA : AsMul1I32<0b0000001, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm, GPR:$Ra),
2698 IIC_iMAC32, "mla", "\t$Rd, $Rn, $Rm, $Ra",
2699 [(set GPR:$Rd, (add (mul GPR:$Rn, GPR:$Rm), GPR:$Ra))]>,
2700 Requires<[IsARM, HasV6]> {
2702 let Inst{15-12} = Ra;
2705 def MLS : AMul1I<0b0000011, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm, GPR:$Ra),
2706 IIC_iMAC32, "mls", "\t$Rd, $Rn, $Rm, $Ra",
2707 [(set GPR:$Rd, (sub GPR:$Ra, (mul GPR:$Rn, GPR:$Rm)))]>,
2708 Requires<[IsARM, HasV6T2]> {
2713 let Inst{19-16} = Rd;
2714 let Inst{15-12} = Ra;
2715 let Inst{11-8} = Rm;
2719 // Extra precision multiplies with low / high results
2721 let neverHasSideEffects = 1 in {
2722 let isCommutable = 1 in {
2723 let Constraints = "@earlyclobber $RdLo,@earlyclobber $RdHi" in {
2724 def SMULLv5 : ARMPseudoInst<(outs GPR:$RdLo, GPR:$RdHi),
2725 (ins GPR:$Rn, GPR:$Rm, pred:$p, cc_out:$s),
2726 Size4Bytes, IIC_iMUL64, []>,
2727 Requires<[IsARM, NoV6]>;
2729 def UMULLv5 : ARMPseudoInst<(outs GPR:$RdLo, GPR:$RdHi),
2730 (ins GPR:$Rn, GPR:$Rm, pred:$p, cc_out:$s),
2731 Size4Bytes, IIC_iMUL64, []>,
2732 Requires<[IsARM, NoV6]>;
2735 def SMULL : AsMul1I64<0b0000110, (outs GPR:$RdLo, GPR:$RdHi),
2736 (ins GPR:$Rn, GPR:$Rm), IIC_iMUL64,
2737 "smull", "\t$RdLo, $RdHi, $Rn, $Rm", []>,
2738 Requires<[IsARM, HasV6]>;
2740 def UMULL : AsMul1I64<0b0000100, (outs GPR:$RdLo, GPR:$RdHi),
2741 (ins GPR:$Rn, GPR:$Rm), IIC_iMUL64,
2742 "umull", "\t$RdLo, $RdHi, $Rn, $Rm", []>,
2743 Requires<[IsARM, HasV6]>;
2746 // Multiply + accumulate
2747 let Constraints = "@earlyclobber $RdLo,@earlyclobber $RdHi" in {
2748 def SMLALv5 : ARMPseudoInst<(outs GPR:$RdLo, GPR:$RdHi),
2749 (ins GPR:$Rn, GPR:$Rm, pred:$p, cc_out:$s),
2750 Size4Bytes, IIC_iMAC64, []>,
2751 Requires<[IsARM, NoV6]>;
2752 def UMLALv5 : ARMPseudoInst<(outs GPR:$RdLo, GPR:$RdHi),
2753 (ins GPR:$Rn, GPR:$Rm, pred:$p, cc_out:$s),
2754 Size4Bytes, IIC_iMAC64, []>,
2755 Requires<[IsARM, NoV6]>;
2756 def UMAALv5 : ARMPseudoInst<(outs GPR:$RdLo, GPR:$RdHi),
2757 (ins GPR:$Rn, GPR:$Rm, pred:$p, cc_out:$s),
2758 Size4Bytes, IIC_iMAC64, []>,
2759 Requires<[IsARM, NoV6]>;
2763 def SMLAL : AsMul1I64<0b0000111, (outs GPR:$RdLo, GPR:$RdHi),
2764 (ins GPR:$Rn, GPR:$Rm), IIC_iMAC64,
2765 "smlal", "\t$RdLo, $RdHi, $Rn, $Rm", []>,
2766 Requires<[IsARM, HasV6]>;
2767 def UMLAL : AsMul1I64<0b0000101, (outs GPR:$RdLo, GPR:$RdHi),
2768 (ins GPR:$Rn, GPR:$Rm), IIC_iMAC64,
2769 "umlal", "\t$RdLo, $RdHi, $Rn, $Rm", []>,
2770 Requires<[IsARM, HasV6]>;
2772 def UMAAL : AMul1I <0b0000010, (outs GPR:$RdLo, GPR:$RdHi),
2773 (ins GPR:$Rn, GPR:$Rm), IIC_iMAC64,
2774 "umaal", "\t$RdLo, $RdHi, $Rn, $Rm", []>,
2775 Requires<[IsARM, HasV6]> {
2780 let Inst{19-16} = RdLo;
2781 let Inst{15-12} = RdHi;
2782 let Inst{11-8} = Rm;
2785 } // neverHasSideEffects
2787 // Most significant word multiply
2788 def SMMUL : AMul2I <0b0111010, 0b0001, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm),
2789 IIC_iMUL32, "smmul", "\t$Rd, $Rn, $Rm",
2790 [(set GPR:$Rd, (mulhs GPR:$Rn, GPR:$Rm))]>,
2791 Requires<[IsARM, HasV6]> {
2792 let Inst{15-12} = 0b1111;
2795 def SMMULR : AMul2I <0b0111010, 0b0011, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm),
2796 IIC_iMUL32, "smmulr", "\t$Rd, $Rn, $Rm",
2797 [/* For disassembly only; pattern left blank */]>,
2798 Requires<[IsARM, HasV6]> {
2799 let Inst{15-12} = 0b1111;
2802 def SMMLA : AMul2Ia <0b0111010, 0b0001, (outs GPR:$Rd),
2803 (ins GPR:$Rn, GPR:$Rm, GPR:$Ra),
2804 IIC_iMAC32, "smmla", "\t$Rd, $Rn, $Rm, $Ra",
2805 [(set GPR:$Rd, (add (mulhs GPR:$Rn, GPR:$Rm), GPR:$Ra))]>,
2806 Requires<[IsARM, HasV6]>;
2808 def SMMLAR : AMul2Ia <0b0111010, 0b0011, (outs GPR:$Rd),
2809 (ins GPR:$Rn, GPR:$Rm, GPR:$Ra),
2810 IIC_iMAC32, "smmlar", "\t$Rd, $Rn, $Rm, $Ra",
2811 [/* For disassembly only; pattern left blank */]>,
2812 Requires<[IsARM, HasV6]>;
2814 def SMMLS : AMul2Ia <0b0111010, 0b1101, (outs GPR:$Rd),
2815 (ins GPR:$Rn, GPR:$Rm, GPR:$Ra),
2816 IIC_iMAC32, "smmls", "\t$Rd, $Rn, $Rm, $Ra",
2817 [(set GPR:$Rd, (sub GPR:$Ra, (mulhs GPR:$Rn, GPR:$Rm)))]>,
2818 Requires<[IsARM, HasV6]>;
2820 def SMMLSR : AMul2Ia <0b0111010, 0b1111, (outs GPR:$Rd),
2821 (ins GPR:$Rn, GPR:$Rm, GPR:$Ra),
2822 IIC_iMAC32, "smmlsr", "\t$Rd, $Rn, $Rm, $Ra",
2823 [/* For disassembly only; pattern left blank */]>,
2824 Requires<[IsARM, HasV6]>;
2826 multiclass AI_smul<string opc, PatFrag opnode> {
2827 def BB : AMulxyI<0b0001011, 0b00, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm),
2828 IIC_iMUL16, !strconcat(opc, "bb"), "\t$Rd, $Rn, $Rm",
2829 [(set GPR:$Rd, (opnode (sext_inreg GPR:$Rn, i16),
2830 (sext_inreg GPR:$Rm, i16)))]>,
2831 Requires<[IsARM, HasV5TE]>;
2833 def BT : AMulxyI<0b0001011, 0b10, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm),
2834 IIC_iMUL16, !strconcat(opc, "bt"), "\t$Rd, $Rn, $Rm",
2835 [(set GPR:$Rd, (opnode (sext_inreg GPR:$Rn, i16),
2836 (sra GPR:$Rm, (i32 16))))]>,
2837 Requires<[IsARM, HasV5TE]>;
2839 def TB : AMulxyI<0b0001011, 0b01, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm),
2840 IIC_iMUL16, !strconcat(opc, "tb"), "\t$Rd, $Rn, $Rm",
2841 [(set GPR:$Rd, (opnode (sra GPR:$Rn, (i32 16)),
2842 (sext_inreg GPR:$Rm, i16)))]>,
2843 Requires<[IsARM, HasV5TE]>;
2845 def TT : AMulxyI<0b0001011, 0b11, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm),
2846 IIC_iMUL16, !strconcat(opc, "tt"), "\t$Rd, $Rn, $Rm",
2847 [(set GPR:$Rd, (opnode (sra GPR:$Rn, (i32 16)),
2848 (sra GPR:$Rm, (i32 16))))]>,
2849 Requires<[IsARM, HasV5TE]>;
2851 def WB : AMulxyI<0b0001001, 0b01, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm),
2852 IIC_iMUL16, !strconcat(opc, "wb"), "\t$Rd, $Rn, $Rm",
2853 [(set GPR:$Rd, (sra (opnode GPR:$Rn,
2854 (sext_inreg GPR:$Rm, i16)), (i32 16)))]>,
2855 Requires<[IsARM, HasV5TE]>;
2857 def WT : AMulxyI<0b0001001, 0b11, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm),
2858 IIC_iMUL16, !strconcat(opc, "wt"), "\t$Rd, $Rn, $Rm",
2859 [(set GPR:$Rd, (sra (opnode GPR:$Rn,
2860 (sra GPR:$Rm, (i32 16))), (i32 16)))]>,
2861 Requires<[IsARM, HasV5TE]>;
2865 multiclass AI_smla<string opc, PatFrag opnode> {
2866 def BB : AMulxyIa<0b0001000, 0b00, (outs GPR:$Rd),
2867 (ins GPR:$Rn, GPR:$Rm, GPR:$Ra),
2868 IIC_iMAC16, !strconcat(opc, "bb"), "\t$Rd, $Rn, $Rm, $Ra",
2869 [(set GPR:$Rd, (add GPR:$Ra,
2870 (opnode (sext_inreg GPR:$Rn, i16),
2871 (sext_inreg GPR:$Rm, i16))))]>,
2872 Requires<[IsARM, HasV5TE]>;
2874 def BT : AMulxyIa<0b0001000, 0b10, (outs GPR:$Rd),
2875 (ins GPR:$Rn, GPR:$Rm, GPR:$Ra),
2876 IIC_iMAC16, !strconcat(opc, "bt"), "\t$Rd, $Rn, $Rm, $Ra",
2877 [(set GPR:$Rd, (add GPR:$Ra, (opnode (sext_inreg GPR:$Rn, i16),
2878 (sra GPR:$Rm, (i32 16)))))]>,
2879 Requires<[IsARM, HasV5TE]>;
2881 def TB : AMulxyIa<0b0001000, 0b01, (outs GPR:$Rd),
2882 (ins GPR:$Rn, GPR:$Rm, GPR:$Ra),
2883 IIC_iMAC16, !strconcat(opc, "tb"), "\t$Rd, $Rn, $Rm, $Ra",
2884 [(set GPR:$Rd, (add GPR:$Ra, (opnode (sra GPR:$Rn, (i32 16)),
2885 (sext_inreg GPR:$Rm, i16))))]>,
2886 Requires<[IsARM, HasV5TE]>;
2888 def TT : AMulxyIa<0b0001000, 0b11, (outs GPR:$Rd),
2889 (ins GPR:$Rn, GPR:$Rm, GPR:$Ra),
2890 IIC_iMAC16, !strconcat(opc, "tt"), "\t$Rd, $Rn, $Rm, $Ra",
2891 [(set GPR:$Rd, (add GPR:$Ra, (opnode (sra GPR:$Rn, (i32 16)),
2892 (sra GPR:$Rm, (i32 16)))))]>,
2893 Requires<[IsARM, HasV5TE]>;
2895 def WB : AMulxyIa<0b0001001, 0b00, (outs GPR:$Rd),
2896 (ins GPR:$Rn, GPR:$Rm, GPR:$Ra),
2897 IIC_iMAC16, !strconcat(opc, "wb"), "\t$Rd, $Rn, $Rm, $Ra",
2898 [(set GPR:$Rd, (add GPR:$Ra, (sra (opnode GPR:$Rn,
2899 (sext_inreg GPR:$Rm, i16)), (i32 16))))]>,
2900 Requires<[IsARM, HasV5TE]>;
2902 def WT : AMulxyIa<0b0001001, 0b10, (outs GPR:$Rd),
2903 (ins GPR:$Rn, GPR:$Rm, GPR:$Ra),
2904 IIC_iMAC16, !strconcat(opc, "wt"), "\t$Rd, $Rn, $Rm, $Ra",
2905 [(set GPR:$Rd, (add GPR:$Ra, (sra (opnode GPR:$Rn,
2906 (sra GPR:$Rm, (i32 16))), (i32 16))))]>,
2907 Requires<[IsARM, HasV5TE]>;
2910 defm SMUL : AI_smul<"smul", BinOpFrag<(mul node:$LHS, node:$RHS)>>;
2911 defm SMLA : AI_smla<"smla", BinOpFrag<(mul node:$LHS, node:$RHS)>>;
2913 // Halfword multiply accumulate long: SMLAL<x><y> -- for disassembly only
2914 def SMLALBB : AMulxyI64<0b0001010, 0b00, (outs GPR:$RdLo, GPR:$RdHi),
2915 (ins GPR:$Rn, GPR:$Rm),
2916 IIC_iMAC64, "smlalbb", "\t$RdLo, $RdHi, $Rn, $Rm",
2917 [/* For disassembly only; pattern left blank */]>,
2918 Requires<[IsARM, HasV5TE]>;
2920 def SMLALBT : AMulxyI64<0b0001010, 0b10, (outs GPR:$RdLo, GPR:$RdHi),
2921 (ins GPR:$Rn, GPR:$Rm),
2922 IIC_iMAC64, "smlalbt", "\t$RdLo, $RdHi, $Rn, $Rm",
2923 [/* For disassembly only; pattern left blank */]>,
2924 Requires<[IsARM, HasV5TE]>;
2926 def SMLALTB : AMulxyI64<0b0001010, 0b01, (outs GPR:$RdLo, GPR:$RdHi),
2927 (ins GPR:$Rn, GPR:$Rm),
2928 IIC_iMAC64, "smlaltb", "\t$RdLo, $RdHi, $Rn, $Rm",
2929 [/* For disassembly only; pattern left blank */]>,
2930 Requires<[IsARM, HasV5TE]>;
2932 def SMLALTT : AMulxyI64<0b0001010, 0b11, (outs GPR:$RdLo, GPR:$RdHi),
2933 (ins GPR:$Rn, GPR:$Rm),
2934 IIC_iMAC64, "smlaltt", "\t$RdLo, $RdHi, $Rn, $Rm",
2935 [/* For disassembly only; pattern left blank */]>,
2936 Requires<[IsARM, HasV5TE]>;
2938 // Helper class for AI_smld -- for disassembly only
2939 class AMulDualIbase<bit long, bit sub, bit swap, dag oops, dag iops,
2940 InstrItinClass itin, string opc, string asm>
2941 : AI<oops, iops, MulFrm, itin, opc, asm, []>, Requires<[IsARM, HasV6]> {
2948 let Inst{21-20} = 0b00;
2949 let Inst{22} = long;
2950 let Inst{27-23} = 0b01110;
2951 let Inst{11-8} = Rm;
2954 class AMulDualI<bit long, bit sub, bit swap, dag oops, dag iops,
2955 InstrItinClass itin, string opc, string asm>
2956 : AMulDualIbase<long, sub, swap, oops, iops, itin, opc, asm> {
2958 let Inst{15-12} = 0b1111;
2959 let Inst{19-16} = Rd;
2961 class AMulDualIa<bit long, bit sub, bit swap, dag oops, dag iops,
2962 InstrItinClass itin, string opc, string asm>
2963 : AMulDualIbase<long, sub, swap, oops, iops, itin, opc, asm> {
2965 let Inst{15-12} = Ra;
2967 class AMulDualI64<bit long, bit sub, bit swap, dag oops, dag iops,
2968 InstrItinClass itin, string opc, string asm>
2969 : AMulDualIbase<long, sub, swap, oops, iops, itin, opc, asm> {
2972 let Inst{19-16} = RdHi;
2973 let Inst{15-12} = RdLo;
2976 multiclass AI_smld<bit sub, string opc> {
2978 def D : AMulDualIa<0, sub, 0, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm, GPR:$Ra),
2979 NoItinerary, !strconcat(opc, "d"), "\t$Rd, $Rn, $Rm, $Ra">;
2981 def DX: AMulDualIa<0, sub, 1, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm, GPR:$Ra),
2982 NoItinerary, !strconcat(opc, "dx"), "\t$Rd, $Rn, $Rm, $Ra">;
2984 def LD: AMulDualI64<1, sub, 0, (outs GPR:$RdLo,GPR:$RdHi),
2985 (ins GPR:$Rn, GPR:$Rm), NoItinerary,
2986 !strconcat(opc, "ld"), "\t$RdLo, $RdHi, $Rn, $Rm">;
2988 def LDX : AMulDualI64<1, sub, 1, (outs GPR:$RdLo,GPR:$RdHi),
2989 (ins GPR:$Rn, GPR:$Rm), NoItinerary,
2990 !strconcat(opc, "ldx"),"\t$RdLo, $RdHi, $Rn, $Rm">;
2994 defm SMLA : AI_smld<0, "smla">;
2995 defm SMLS : AI_smld<1, "smls">;
2997 multiclass AI_sdml<bit sub, string opc> {
2999 def D : AMulDualI<0, sub, 0, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm),
3000 NoItinerary, !strconcat(opc, "d"), "\t$Rd, $Rn, $Rm">;
3001 def DX : AMulDualI<0, sub, 1, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm),
3002 NoItinerary, !strconcat(opc, "dx"), "\t$Rd, $Rn, $Rm">;
3005 defm SMUA : AI_sdml<0, "smua">;
3006 defm SMUS : AI_sdml<1, "smus">;
3008 //===----------------------------------------------------------------------===//
3009 // Misc. Arithmetic Instructions.
3012 def CLZ : AMiscA1I<0b000010110, 0b0001, (outs GPR:$Rd), (ins GPR:$Rm),
3013 IIC_iUNAr, "clz", "\t$Rd, $Rm",
3014 [(set GPR:$Rd, (ctlz GPR:$Rm))]>, Requires<[IsARM, HasV5T]>;
3016 def RBIT : AMiscA1I<0b01101111, 0b0011, (outs GPR:$Rd), (ins GPR:$Rm),
3017 IIC_iUNAr, "rbit", "\t$Rd, $Rm",
3018 [(set GPR:$Rd, (ARMrbit GPR:$Rm))]>,
3019 Requires<[IsARM, HasV6T2]>;
3021 def REV : AMiscA1I<0b01101011, 0b0011, (outs GPR:$Rd), (ins GPR:$Rm),
3022 IIC_iUNAr, "rev", "\t$Rd, $Rm",
3023 [(set GPR:$Rd, (bswap GPR:$Rm))]>, Requires<[IsARM, HasV6]>;
3025 def REV16 : AMiscA1I<0b01101011, 0b1011, (outs GPR:$Rd), (ins GPR:$Rm),
3026 IIC_iUNAr, "rev16", "\t$Rd, $Rm",
3028 (or (and (srl GPR:$Rm, (i32 8)), 0xFF),
3029 (or (and (shl GPR:$Rm, (i32 8)), 0xFF00),
3030 (or (and (srl GPR:$Rm, (i32 8)), 0xFF0000),
3031 (and (shl GPR:$Rm, (i32 8)), 0xFF000000)))))]>,
3032 Requires<[IsARM, HasV6]>;
3034 def REVSH : AMiscA1I<0b01101111, 0b1011, (outs GPR:$Rd), (ins GPR:$Rm),
3035 IIC_iUNAr, "revsh", "\t$Rd, $Rm",
3038 (or (srl GPR:$Rm, (i32 8)),
3039 (shl GPR:$Rm, (i32 8))), i16))]>,
3040 Requires<[IsARM, HasV6]>;
3042 def : ARMV6Pat<(sext_inreg (or (srl (and GPR:$Rm, 0xFF00), (i32 8)),
3043 (shl GPR:$Rm, (i32 8))), i16),
3046 // Need the AddedComplexity or else MOVs + REV would be chosen.
3047 let AddedComplexity = 5 in
3048 def : ARMV6Pat<(sra (bswap GPR:$Rm), (i32 16)), (REVSH GPR:$Rm)>;
3050 def lsl_shift_imm : SDNodeXForm<imm, [{
3051 unsigned Sh = ARM_AM::getSORegOpc(ARM_AM::lsl, N->getZExtValue());
3052 return CurDAG->getTargetConstant(Sh, MVT::i32);
3055 def lsl_amt : PatLeaf<(i32 imm), [{
3056 return (N->getZExtValue() < 32);
3059 def PKHBT : APKHI<0b01101000, 0, (outs GPR:$Rd),
3060 (ins GPR:$Rn, GPR:$Rm, shift_imm:$sh),
3061 IIC_iALUsi, "pkhbt", "\t$Rd, $Rn, $Rm$sh",
3062 [(set GPR:$Rd, (or (and GPR:$Rn, 0xFFFF),
3063 (and (shl GPR:$Rm, lsl_amt:$sh),
3065 Requires<[IsARM, HasV6]>;
3067 // Alternate cases for PKHBT where identities eliminate some nodes.
3068 def : ARMV6Pat<(or (and GPR:$Rn, 0xFFFF), (and GPR:$Rm, 0xFFFF0000)),
3069 (PKHBT GPR:$Rn, GPR:$Rm, 0)>;
3070 def : ARMV6Pat<(or (and GPR:$Rn, 0xFFFF), (shl GPR:$Rm, imm16_31:$sh)),
3071 (PKHBT GPR:$Rn, GPR:$Rm, (lsl_shift_imm imm16_31:$sh))>;
3073 def asr_shift_imm : SDNodeXForm<imm, [{
3074 unsigned Sh = ARM_AM::getSORegOpc(ARM_AM::asr, N->getZExtValue());
3075 return CurDAG->getTargetConstant(Sh, MVT::i32);
3078 def asr_amt : PatLeaf<(i32 imm), [{
3079 return (N->getZExtValue() <= 32);
3082 // Note: Shifts of 1-15 bits will be transformed to srl instead of sra and
3083 // will match the pattern below.
3084 def PKHTB : APKHI<0b01101000, 1, (outs GPR:$Rd),
3085 (ins GPR:$Rn, GPR:$Rm, shift_imm:$sh),
3086 IIC_iBITsi, "pkhtb", "\t$Rd, $Rn, $Rm$sh",
3087 [(set GPR:$Rd, (or (and GPR:$Rn, 0xFFFF0000),
3088 (and (sra GPR:$Rm, asr_amt:$sh),
3090 Requires<[IsARM, HasV6]>;
3092 // Alternate cases for PKHTB where identities eliminate some nodes. Note that
3093 // a shift amount of 0 is *not legal* here, it is PKHBT instead.
3094 def : ARMV6Pat<(or (and GPR:$src1, 0xFFFF0000), (srl GPR:$src2, imm16_31:$sh)),
3095 (PKHTB GPR:$src1, GPR:$src2, (asr_shift_imm imm16_31:$sh))>;
3096 def : ARMV6Pat<(or (and GPR:$src1, 0xFFFF0000),
3097 (and (srl GPR:$src2, imm1_15:$sh), 0xFFFF)),
3098 (PKHTB GPR:$src1, GPR:$src2, (asr_shift_imm imm1_15:$sh))>;
3100 //===----------------------------------------------------------------------===//
3101 // Comparison Instructions...
3104 defm CMP : AI1_cmp_irs<0b1010, "cmp",
3105 IIC_iCMPi, IIC_iCMPr, IIC_iCMPsr,
3106 BinOpFrag<(ARMcmp node:$LHS, node:$RHS)>>;
3108 // ARMcmpZ can re-use the above instruction definitions.
3109 def : ARMPat<(ARMcmpZ GPR:$src, so_imm:$imm),
3110 (CMPri GPR:$src, so_imm:$imm)>;
3111 def : ARMPat<(ARMcmpZ GPR:$src, GPR:$rhs),
3112 (CMPrr GPR:$src, GPR:$rhs)>;
3113 def : ARMPat<(ARMcmpZ GPR:$src, so_reg:$rhs),
3114 (CMPrs GPR:$src, so_reg:$rhs)>;
3116 // FIXME: We have to be careful when using the CMN instruction and comparison
3117 // with 0. One would expect these two pieces of code should give identical
3133 // However, the CMN gives the *opposite* result when r1 is 0. This is because
3134 // the carry flag is set in the CMP case but not in the CMN case. In short, the
3135 // CMP instruction doesn't perform a truncate of the (logical) NOT of 0 plus the
3136 // value of r0 and the carry bit (because the "carry bit" parameter to
3137 // AddWithCarry is defined as 1 in this case, the carry flag will always be set
3138 // when r0 >= 0). The CMN instruction doesn't perform a NOT of 0 so there is
3139 // never a "carry" when this AddWithCarry is performed (because the "carry bit"
3140 // parameter to AddWithCarry is defined as 0).
3142 // When x is 0 and unsigned:
3146 // ~x + 1 = 0x1 0000 0000
3147 // (-x = 0) != (0x1 0000 0000 = ~x + 1)
3149 // Therefore, we should disable CMN when comparing against zero, until we can
3150 // limit when the CMN instruction is used (when we know that the RHS is not 0 or
3151 // when it's a comparison which doesn't look at the 'carry' flag).
3153 // (See the ARM docs for the "AddWithCarry" pseudo-code.)
3155 // This is related to <rdar://problem/7569620>.
3157 //defm CMN : AI1_cmp_irs<0b1011, "cmn",
3158 // BinOpFrag<(ARMcmp node:$LHS,(ineg node:$RHS))>>;
3160 // Note that TST/TEQ don't set all the same flags that CMP does!
3161 defm TST : AI1_cmp_irs<0b1000, "tst",
3162 IIC_iTSTi, IIC_iTSTr, IIC_iTSTsr,
3163 BinOpFrag<(ARMcmpZ (and_su node:$LHS, node:$RHS), 0)>, 1>;
3164 defm TEQ : AI1_cmp_irs<0b1001, "teq",
3165 IIC_iTSTi, IIC_iTSTr, IIC_iTSTsr,
3166 BinOpFrag<(ARMcmpZ (xor_su node:$LHS, node:$RHS), 0)>, 1>;
3168 defm CMNz : AI1_cmp_irs<0b1011, "cmn",
3169 IIC_iCMPi, IIC_iCMPr, IIC_iCMPsr,
3170 BinOpFrag<(ARMcmpZ node:$LHS,(ineg node:$RHS))>>;
3172 //def : ARMPat<(ARMcmp GPR:$src, so_imm_neg:$imm),
3173 // (CMNri GPR:$src, so_imm_neg:$imm)>;
3175 def : ARMPat<(ARMcmpZ GPR:$src, so_imm_neg:$imm),
3176 (CMNzri GPR:$src, so_imm_neg:$imm)>;
3178 // Pseudo i64 compares for some floating point compares.
3179 let usesCustomInserter = 1, isBranch = 1, isTerminator = 1,
3181 def BCCi64 : PseudoInst<(outs),
3182 (ins i32imm:$cc, GPR:$lhs1, GPR:$lhs2, GPR:$rhs1, GPR:$rhs2, brtarget:$dst),
3184 [(ARMBcci64 imm:$cc, GPR:$lhs1, GPR:$lhs2, GPR:$rhs1, GPR:$rhs2, bb:$dst)]>;
3186 def BCCZi64 : PseudoInst<(outs),
3187 (ins i32imm:$cc, GPR:$lhs1, GPR:$lhs2, brtarget:$dst), IIC_Br,
3188 [(ARMBcci64 imm:$cc, GPR:$lhs1, GPR:$lhs2, 0, 0, bb:$dst)]>;
3189 } // usesCustomInserter
3192 // Conditional moves
3193 // FIXME: should be able to write a pattern for ARMcmov, but can't use
3194 // a two-value operand where a dag node expects two operands. :(
3195 let neverHasSideEffects = 1 in {
3196 def MOVCCr : ARMPseudoInst<(outs GPR:$Rd), (ins GPR:$false, GPR:$Rm, pred:$p),
3197 Size4Bytes, IIC_iCMOVr,
3198 [/*(set GPR:$Rd, (ARMcmov GPR:$false, GPR:$Rm, imm:$cc, CCR:$ccr))*/]>,
3199 RegConstraint<"$false = $Rd">;
3200 def MOVCCs : ARMPseudoInst<(outs GPR:$Rd),
3201 (ins GPR:$false, so_reg:$shift, pred:$p),
3202 Size4Bytes, IIC_iCMOVsr,
3203 [/*(set GPR:$Rd, (ARMcmov GPR:$false, so_reg:$shift, imm:$cc, CCR:$ccr))*/]>,
3204 RegConstraint<"$false = $Rd">;
3206 let isMoveImm = 1 in
3207 def MOVCCi16 : ARMPseudoInst<(outs GPR:$Rd),
3208 (ins GPR:$false, i32imm_hilo16:$imm, pred:$p),
3209 Size4Bytes, IIC_iMOVi,
3211 RegConstraint<"$false = $Rd">, Requires<[IsARM, HasV6T2]>;
3213 let isMoveImm = 1 in
3214 def MOVCCi : ARMPseudoInst<(outs GPR:$Rd),
3215 (ins GPR:$false, so_imm:$imm, pred:$p),
3216 Size4Bytes, IIC_iCMOVi,
3217 [/*(set GPR:$Rd, (ARMcmov GPR:$false, so_imm:$imm, imm:$cc, CCR:$ccr))*/]>,
3218 RegConstraint<"$false = $Rd">;
3220 // Two instruction predicate mov immediate.
3221 let isMoveImm = 1 in
3222 def MOVCCi32imm : ARMPseudoInst<(outs GPR:$Rd),
3223 (ins GPR:$false, i32imm:$src, pred:$p),
3224 Size8Bytes, IIC_iCMOVix2, []>, RegConstraint<"$false = $Rd">;
3226 let isMoveImm = 1 in
3227 def MVNCCi : ARMPseudoInst<(outs GPR:$Rd),
3228 (ins GPR:$false, so_imm:$imm, pred:$p),
3229 Size4Bytes, IIC_iCMOVi,
3230 [/*(set GPR:$Rd, (ARMcmov GPR:$false, so_imm_not:$imm, imm:$cc, CCR:$ccr))*/]>,
3231 RegConstraint<"$false = $Rd">;
3232 } // neverHasSideEffects
3234 //===----------------------------------------------------------------------===//
3235 // Atomic operations intrinsics
3238 def memb_opt : Operand<i32> {
3239 let PrintMethod = "printMemBOption";
3240 let ParserMatchClass = MemBarrierOptOperand;
3243 // memory barriers protect the atomic sequences
3244 let hasSideEffects = 1 in {
3245 def DMB : AInoP<(outs), (ins memb_opt:$opt), MiscFrm, NoItinerary,
3246 "dmb", "\t$opt", [(ARMMemBarrier (i32 imm:$opt))]>,
3247 Requires<[IsARM, HasDB]> {
3249 let Inst{31-4} = 0xf57ff05;
3250 let Inst{3-0} = opt;
3254 def DSB : AInoP<(outs), (ins memb_opt:$opt), MiscFrm, NoItinerary,
3256 [/* For disassembly only; pattern left blank */]>,
3257 Requires<[IsARM, HasDB]> {
3259 let Inst{31-4} = 0xf57ff04;
3260 let Inst{3-0} = opt;
3263 // ISB has only full system option -- for disassembly only
3264 def ISB : AInoP<(outs), (ins), MiscFrm, NoItinerary, "isb", "", []>,
3265 Requires<[IsARM, HasDB]> {
3266 let Inst{31-4} = 0xf57ff06;
3267 let Inst{3-0} = 0b1111;
3270 let usesCustomInserter = 1 in {
3271 let Uses = [CPSR] in {
3272 def ATOMIC_LOAD_ADD_I8 : PseudoInst<
3273 (outs GPR:$dst), (ins GPR:$ptr, GPR:$incr), NoItinerary,
3274 [(set GPR:$dst, (atomic_load_add_8 GPR:$ptr, GPR:$incr))]>;
3275 def ATOMIC_LOAD_SUB_I8 : PseudoInst<
3276 (outs GPR:$dst), (ins GPR:$ptr, GPR:$incr), NoItinerary,
3277 [(set GPR:$dst, (atomic_load_sub_8 GPR:$ptr, GPR:$incr))]>;
3278 def ATOMIC_LOAD_AND_I8 : PseudoInst<
3279 (outs GPR:$dst), (ins GPR:$ptr, GPR:$incr), NoItinerary,
3280 [(set GPR:$dst, (atomic_load_and_8 GPR:$ptr, GPR:$incr))]>;
3281 def ATOMIC_LOAD_OR_I8 : PseudoInst<
3282 (outs GPR:$dst), (ins GPR:$ptr, GPR:$incr), NoItinerary,
3283 [(set GPR:$dst, (atomic_load_or_8 GPR:$ptr, GPR:$incr))]>;
3284 def ATOMIC_LOAD_XOR_I8 : PseudoInst<
3285 (outs GPR:$dst), (ins GPR:$ptr, GPR:$incr), NoItinerary,
3286 [(set GPR:$dst, (atomic_load_xor_8 GPR:$ptr, GPR:$incr))]>;
3287 def ATOMIC_LOAD_NAND_I8 : PseudoInst<
3288 (outs GPR:$dst), (ins GPR:$ptr, GPR:$incr), NoItinerary,
3289 [(set GPR:$dst, (atomic_load_nand_8 GPR:$ptr, GPR:$incr))]>;
3290 def ATOMIC_LOAD_ADD_I16 : PseudoInst<
3291 (outs GPR:$dst), (ins GPR:$ptr, GPR:$incr), NoItinerary,
3292 [(set GPR:$dst, (atomic_load_add_16 GPR:$ptr, GPR:$incr))]>;
3293 def ATOMIC_LOAD_SUB_I16 : PseudoInst<
3294 (outs GPR:$dst), (ins GPR:$ptr, GPR:$incr), NoItinerary,
3295 [(set GPR:$dst, (atomic_load_sub_16 GPR:$ptr, GPR:$incr))]>;
3296 def ATOMIC_LOAD_AND_I16 : PseudoInst<
3297 (outs GPR:$dst), (ins GPR:$ptr, GPR:$incr), NoItinerary,
3298 [(set GPR:$dst, (atomic_load_and_16 GPR:$ptr, GPR:$incr))]>;
3299 def ATOMIC_LOAD_OR_I16 : PseudoInst<
3300 (outs GPR:$dst), (ins GPR:$ptr, GPR:$incr), NoItinerary,
3301 [(set GPR:$dst, (atomic_load_or_16 GPR:$ptr, GPR:$incr))]>;
3302 def ATOMIC_LOAD_XOR_I16 : PseudoInst<
3303 (outs GPR:$dst), (ins GPR:$ptr, GPR:$incr), NoItinerary,
3304 [(set GPR:$dst, (atomic_load_xor_16 GPR:$ptr, GPR:$incr))]>;
3305 def ATOMIC_LOAD_NAND_I16 : PseudoInst<
3306 (outs GPR:$dst), (ins GPR:$ptr, GPR:$incr), NoItinerary,
3307 [(set GPR:$dst, (atomic_load_nand_16 GPR:$ptr, GPR:$incr))]>;
3308 def ATOMIC_LOAD_ADD_I32 : PseudoInst<
3309 (outs GPR:$dst), (ins GPR:$ptr, GPR:$incr), NoItinerary,
3310 [(set GPR:$dst, (atomic_load_add_32 GPR:$ptr, GPR:$incr))]>;
3311 def ATOMIC_LOAD_SUB_I32 : PseudoInst<
3312 (outs GPR:$dst), (ins GPR:$ptr, GPR:$incr), NoItinerary,
3313 [(set GPR:$dst, (atomic_load_sub_32 GPR:$ptr, GPR:$incr))]>;
3314 def ATOMIC_LOAD_AND_I32 : PseudoInst<
3315 (outs GPR:$dst), (ins GPR:$ptr, GPR:$incr), NoItinerary,
3316 [(set GPR:$dst, (atomic_load_and_32 GPR:$ptr, GPR:$incr))]>;
3317 def ATOMIC_LOAD_OR_I32 : PseudoInst<
3318 (outs GPR:$dst), (ins GPR:$ptr, GPR:$incr), NoItinerary,
3319 [(set GPR:$dst, (atomic_load_or_32 GPR:$ptr, GPR:$incr))]>;
3320 def ATOMIC_LOAD_XOR_I32 : PseudoInst<
3321 (outs GPR:$dst), (ins GPR:$ptr, GPR:$incr), NoItinerary,
3322 [(set GPR:$dst, (atomic_load_xor_32 GPR:$ptr, GPR:$incr))]>;
3323 def ATOMIC_LOAD_NAND_I32 : PseudoInst<
3324 (outs GPR:$dst), (ins GPR:$ptr, GPR:$incr), NoItinerary,
3325 [(set GPR:$dst, (atomic_load_nand_32 GPR:$ptr, GPR:$incr))]>;
3327 def ATOMIC_SWAP_I8 : PseudoInst<
3328 (outs GPR:$dst), (ins GPR:$ptr, GPR:$new), NoItinerary,
3329 [(set GPR:$dst, (atomic_swap_8 GPR:$ptr, GPR:$new))]>;
3330 def ATOMIC_SWAP_I16 : PseudoInst<
3331 (outs GPR:$dst), (ins GPR:$ptr, GPR:$new), NoItinerary,
3332 [(set GPR:$dst, (atomic_swap_16 GPR:$ptr, GPR:$new))]>;
3333 def ATOMIC_SWAP_I32 : PseudoInst<
3334 (outs GPR:$dst), (ins GPR:$ptr, GPR:$new), NoItinerary,
3335 [(set GPR:$dst, (atomic_swap_32 GPR:$ptr, GPR:$new))]>;
3337 def ATOMIC_CMP_SWAP_I8 : PseudoInst<
3338 (outs GPR:$dst), (ins GPR:$ptr, GPR:$old, GPR:$new), NoItinerary,
3339 [(set GPR:$dst, (atomic_cmp_swap_8 GPR:$ptr, GPR:$old, GPR:$new))]>;
3340 def ATOMIC_CMP_SWAP_I16 : PseudoInst<
3341 (outs GPR:$dst), (ins GPR:$ptr, GPR:$old, GPR:$new), NoItinerary,
3342 [(set GPR:$dst, (atomic_cmp_swap_16 GPR:$ptr, GPR:$old, GPR:$new))]>;
3343 def ATOMIC_CMP_SWAP_I32 : PseudoInst<
3344 (outs GPR:$dst), (ins GPR:$ptr, GPR:$old, GPR:$new), NoItinerary,
3345 [(set GPR:$dst, (atomic_cmp_swap_32 GPR:$ptr, GPR:$old, GPR:$new))]>;
3349 let mayLoad = 1 in {
3350 def LDREXB : AIldrex<0b10, (outs GPR:$Rt), (ins addrmode7:$addr), NoItinerary,
3351 "ldrexb", "\t$Rt, $addr", []>;
3352 def LDREXH : AIldrex<0b11, (outs GPR:$Rt), (ins addrmode7:$addr), NoItinerary,
3353 "ldrexh", "\t$Rt, $addr", []>;
3354 def LDREX : AIldrex<0b00, (outs GPR:$Rt), (ins addrmode7:$addr), NoItinerary,
3355 "ldrex", "\t$Rt, $addr", []>;
3356 def LDREXD : AIldrex<0b01, (outs GPR:$Rt, GPR:$Rt2), (ins addrmode7:$addr),
3357 NoItinerary, "ldrexd", "\t$Rt, $Rt2, $addr", []>;
3360 let mayStore = 1, Constraints = "@earlyclobber $Rd" in {
3361 def STREXB : AIstrex<0b10, (outs GPR:$Rd), (ins GPR:$Rt, addrmode7:$addr),
3362 NoItinerary, "strexb", "\t$Rd, $Rt, $addr", []>;
3363 def STREXH : AIstrex<0b11, (outs GPR:$Rd), (ins GPR:$Rt, addrmode7:$addr),
3364 NoItinerary, "strexh", "\t$Rd, $Rt, $addr", []>;
3365 def STREX : AIstrex<0b00, (outs GPR:$Rd), (ins GPR:$Rt, addrmode7:$addr),
3366 NoItinerary, "strex", "\t$Rd, $Rt, $addr", []>;
3367 def STREXD : AIstrex<0b01, (outs GPR:$Rd),
3368 (ins GPR:$Rt, GPR:$Rt2, addrmode7:$addr),
3369 NoItinerary, "strexd", "\t$Rd, $Rt, $Rt2, $addr", []>;
3372 // Clear-Exclusive is for disassembly only.
3373 def CLREX : AXI<(outs), (ins), MiscFrm, NoItinerary, "clrex",
3374 [/* For disassembly only; pattern left blank */]>,
3375 Requires<[IsARM, HasV7]> {
3376 let Inst{31-0} = 0b11110101011111111111000000011111;
3379 // SWP/SWPB are deprecated in V6/V7 and for disassembly only.
3380 let mayLoad = 1 in {
3381 def SWP : AIswp<0, (outs GPR:$Rt), (ins GPR:$Rt2, GPR:$Rn), "swp",
3382 [/* For disassembly only; pattern left blank */]>;
3383 def SWPB : AIswp<1, (outs GPR:$Rt), (ins GPR:$Rt2, GPR:$Rn), "swpb",
3384 [/* For disassembly only; pattern left blank */]>;
3387 //===----------------------------------------------------------------------===//
3388 // Coprocessor Instructions.
3391 def CDP : ABI<0b1110, (outs), (ins p_imm:$cop, i32imm:$opc1,
3392 c_imm:$CRd, c_imm:$CRn, c_imm:$CRm, i32imm:$opc2),
3393 NoItinerary, "cdp", "\t$cop, $opc1, $CRd, $CRn, $CRm, $opc2",
3394 [/* For disassembly only; pattern left blank */]> {
3402 let Inst{3-0} = CRm;
3404 let Inst{7-5} = opc2;
3405 let Inst{11-8} = cop;
3406 let Inst{15-12} = CRd;
3407 let Inst{19-16} = CRn;
3408 let Inst{23-20} = opc1;
3411 def CDP2 : ABXI<0b1110, (outs), (ins p_imm:$cop, i32imm:$opc1,
3412 c_imm:$CRd, c_imm:$CRn, c_imm:$CRm, i32imm:$opc2),
3413 NoItinerary, "cdp2\t$cop, $opc1, $CRd, $CRn, $CRm, $opc2",
3414 [/* For disassembly only; pattern left blank */]> {
3415 let Inst{31-28} = 0b1111;
3423 let Inst{3-0} = CRm;
3425 let Inst{7-5} = opc2;
3426 let Inst{11-8} = cop;
3427 let Inst{15-12} = CRd;
3428 let Inst{19-16} = CRn;
3429 let Inst{23-20} = opc1;
3432 class ACI<dag oops, dag iops, string opc, string asm,
3433 IndexMode im = IndexModeNone>
3434 : I<oops, iops, AddrModeNone, Size4Bytes, im, BrFrm, NoItinerary,
3435 opc, asm, "", [/* For disassembly only; pattern left blank */]> {
3436 let Inst{27-25} = 0b110;
3439 multiclass LdStCop<bits<4> op31_28, bit load, string opc> {
3441 def _OFFSET : ACI<(outs),
3442 (ins nohash_imm:$cop, nohash_imm:$CRd, addrmode2:$addr),
3443 opc, "\tp$cop, cr$CRd, $addr"> {
3444 let Inst{31-28} = op31_28;
3445 let Inst{24} = 1; // P = 1
3446 let Inst{21} = 0; // W = 0
3447 let Inst{22} = 0; // D = 0
3448 let Inst{20} = load;
3451 def _PRE : ACI<(outs),
3452 (ins nohash_imm:$cop, nohash_imm:$CRd, addrmode2:$addr),
3453 opc, "\tp$cop, cr$CRd, $addr!", IndexModePre> {
3454 let Inst{31-28} = op31_28;
3455 let Inst{24} = 1; // P = 1
3456 let Inst{21} = 1; // W = 1
3457 let Inst{22} = 0; // D = 0
3458 let Inst{20} = load;
3461 def _POST : ACI<(outs),
3462 (ins nohash_imm:$cop, nohash_imm:$CRd, addrmode2:$addr),
3463 opc, "\tp$cop, cr$CRd, $addr", IndexModePost> {
3464 let Inst{31-28} = op31_28;
3465 let Inst{24} = 0; // P = 0
3466 let Inst{21} = 1; // W = 1
3467 let Inst{22} = 0; // D = 0
3468 let Inst{20} = load;
3471 def _OPTION : ACI<(outs),
3472 (ins nohash_imm:$cop, nohash_imm:$CRd, GPR:$base, nohash_imm:$option),
3473 opc, "\tp$cop, cr$CRd, [$base], \\{$option\\}"> {
3474 let Inst{31-28} = op31_28;
3475 let Inst{24} = 0; // P = 0
3476 let Inst{23} = 1; // U = 1
3477 let Inst{21} = 0; // W = 0
3478 let Inst{22} = 0; // D = 0
3479 let Inst{20} = load;
3482 def L_OFFSET : ACI<(outs),
3483 (ins nohash_imm:$cop, nohash_imm:$CRd, addrmode2:$addr),
3484 !strconcat(opc, "l"), "\tp$cop, cr$CRd, $addr"> {
3485 let Inst{31-28} = op31_28;
3486 let Inst{24} = 1; // P = 1
3487 let Inst{21} = 0; // W = 0
3488 let Inst{22} = 1; // D = 1
3489 let Inst{20} = load;
3492 def L_PRE : ACI<(outs),
3493 (ins nohash_imm:$cop, nohash_imm:$CRd, addrmode2:$addr),
3494 !strconcat(opc, "l"), "\tp$cop, cr$CRd, $addr!", IndexModePre> {
3495 let Inst{31-28} = op31_28;
3496 let Inst{24} = 1; // P = 1
3497 let Inst{21} = 1; // W = 1
3498 let Inst{22} = 1; // D = 1
3499 let Inst{20} = load;
3502 def L_POST : ACI<(outs),
3503 (ins nohash_imm:$cop, nohash_imm:$CRd, addrmode2:$addr),
3504 !strconcat(opc, "l"), "\tp$cop, cr$CRd, $addr", IndexModePost> {
3505 let Inst{31-28} = op31_28;
3506 let Inst{24} = 0; // P = 0
3507 let Inst{21} = 1; // W = 1
3508 let Inst{22} = 1; // D = 1
3509 let Inst{20} = load;
3512 def L_OPTION : ACI<(outs),
3513 (ins nohash_imm:$cop, nohash_imm:$CRd, GPR:$base, nohash_imm:$option),
3514 !strconcat(opc, "l"), "\tp$cop, cr$CRd, [$base], \\{$option\\}"> {
3515 let Inst{31-28} = op31_28;
3516 let Inst{24} = 0; // P = 0
3517 let Inst{23} = 1; // U = 1
3518 let Inst{21} = 0; // W = 0
3519 let Inst{22} = 1; // D = 1
3520 let Inst{20} = load;
3524 defm LDC : LdStCop<{?,?,?,?}, 1, "ldc">;
3525 defm LDC2 : LdStCop<0b1111, 1, "ldc2">;
3526 defm STC : LdStCop<{?,?,?,?}, 0, "stc">;
3527 defm STC2 : LdStCop<0b1111, 0, "stc2">;
3529 //===----------------------------------------------------------------------===//
3530 // Move between coprocessor and ARM core register -- for disassembly only
3533 class MovRCopro<string opc, bit direction, dag oops, dag iops>
3534 : ABI<0b1110, oops, iops, NoItinerary, opc,
3535 "\t$cop, $opc1, $Rt, $CRn, $CRm, $opc2",
3536 [/* For disassembly only; pattern left blank */]> {
3537 let Inst{20} = direction;
3547 let Inst{15-12} = Rt;
3548 let Inst{11-8} = cop;
3549 let Inst{23-21} = opc1;
3550 let Inst{7-5} = opc2;
3551 let Inst{3-0} = CRm;
3552 let Inst{19-16} = CRn;
3555 def MCR : MovRCopro<"mcr", 0 /* from ARM core register to coprocessor */,
3556 (outs), (ins p_imm:$cop, i32imm:$opc1,
3557 GPR:$Rt, c_imm:$CRn, c_imm:$CRm,
3559 def MRC : MovRCopro<"mrc", 1 /* from coprocessor to ARM core register */,
3560 (outs GPR:$Rt), (ins p_imm:$cop, i32imm:$opc1,
3561 c_imm:$CRn, c_imm:$CRm, i32imm:$opc2)>;
3563 class MovRCopro2<string opc, bit direction, dag oops, dag iops>
3564 : ABXI<0b1110, oops, iops, NoItinerary,
3565 !strconcat(opc, "\t$cop, $opc1, $Rt, $CRn, $CRm, $opc2"),
3566 [/* For disassembly only; pattern left blank */]> {
3567 let Inst{31-28} = 0b1111;
3568 let Inst{20} = direction;
3578 let Inst{15-12} = Rt;
3579 let Inst{11-8} = cop;
3580 let Inst{23-21} = opc1;
3581 let Inst{7-5} = opc2;
3582 let Inst{3-0} = CRm;
3583 let Inst{19-16} = CRn;
3586 def MCR2 : MovRCopro2<"mcr2", 0 /* from ARM core register to coprocessor */,
3587 (outs), (ins p_imm:$cop, i32imm:$opc1,
3588 GPR:$Rt, c_imm:$CRn, c_imm:$CRm,
3590 def MRC2 : MovRCopro2<"mrc2", 1 /* from coprocessor to ARM core register */,
3591 (outs GPR:$Rt), (ins p_imm:$cop, i32imm:$opc1,
3592 c_imm:$CRn, c_imm:$CRm,
3595 class MovRRCopro<string opc, bit direction>
3596 : ABI<0b1100, (outs), (ins p_imm:$cop, i32imm:$opc1,
3597 GPR:$Rt, GPR:$Rt2, c_imm:$CRm),
3598 NoItinerary, opc, "\t$cop, $opc1, $Rt, $Rt2, $CRm",
3599 [/* For disassembly only; pattern left blank */]> {
3600 let Inst{23-21} = 0b010;
3601 let Inst{20} = direction;
3609 let Inst{15-12} = Rt;
3610 let Inst{19-16} = Rt2;
3611 let Inst{11-8} = cop;
3612 let Inst{7-4} = opc1;
3613 let Inst{3-0} = CRm;
3616 def MCRR : MovRRCopro<"mcrr", 0 /* from ARM core register to coprocessor */>;
3617 def MRRC : MovRRCopro<"mrrc", 1 /* from coprocessor to ARM core register */>;
3619 class MovRRCopro2<string opc, bit direction>
3620 : ABXI<0b1100, (outs), (ins p_imm:$cop, i32imm:$opc1,
3621 GPR:$Rt, GPR:$Rt2, c_imm:$CRm),
3622 NoItinerary, !strconcat(opc, "\t$cop, $opc1, $Rt, $Rt2, $CRm"),
3623 [/* For disassembly only; pattern left blank */]> {
3624 let Inst{31-28} = 0b1111;
3625 let Inst{23-21} = 0b010;
3626 let Inst{20} = direction;
3634 let Inst{15-12} = Rt;
3635 let Inst{19-16} = Rt2;
3636 let Inst{11-8} = cop;
3637 let Inst{7-4} = opc1;
3638 let Inst{3-0} = CRm;
3641 def MCRR2 : MovRRCopro2<"mcrr2", 0 /* from ARM core register to coprocessor */>;
3642 def MRRC2 : MovRRCopro2<"mrrc2", 1 /* from coprocessor to ARM core register */>;
3644 //===----------------------------------------------------------------------===//
3645 // Move between special register and ARM core register -- for disassembly only
3648 // Move to ARM core register from Special Register
3649 def MRS : ABI<0b0001, (outs GPR:$Rd), (ins), NoItinerary, "mrs", "\t$Rd, cpsr",
3650 [/* For disassembly only; pattern left blank */]> {
3652 let Inst{23-16} = 0b00001111;
3653 let Inst{15-12} = Rd;
3654 let Inst{7-4} = 0b0000;
3657 def MRSsys : ABI<0b0001, (outs GPR:$Rd), (ins), NoItinerary,"mrs","\t$Rd, spsr",
3658 [/* For disassembly only; pattern left blank */]> {
3660 let Inst{23-16} = 0b01001111;
3661 let Inst{15-12} = Rd;
3662 let Inst{7-4} = 0b0000;
3665 // Move from ARM core register to Special Register
3667 // No need to have both system and application versions, the encodings are the
3668 // same and the assembly parser has no way to distinguish between them. The mask
3669 // operand contains the special register (R Bit) in bit 4 and bits 3-0 contains
3670 // the mask with the fields to be accessed in the special register.
3671 def MSR : ABI<0b0001, (outs), (ins msr_mask:$mask, GPR:$Rn), NoItinerary,
3672 "msr", "\t$mask, $Rn",
3673 [/* For disassembly only; pattern left blank */]> {
3678 let Inst{22} = mask{4}; // R bit
3679 let Inst{21-20} = 0b10;
3680 let Inst{19-16} = mask{3-0};
3681 let Inst{15-12} = 0b1111;
3682 let Inst{11-4} = 0b00000000;
3686 def MSRi : ABI<0b0011, (outs), (ins msr_mask:$mask, so_imm:$a), NoItinerary,
3687 "msr", "\t$mask, $a",
3688 [/* For disassembly only; pattern left blank */]> {
3693 let Inst{22} = mask{4}; // R bit
3694 let Inst{21-20} = 0b10;
3695 let Inst{19-16} = mask{3-0};
3696 let Inst{15-12} = 0b1111;
3700 //===----------------------------------------------------------------------===//
3704 // __aeabi_read_tp preserves the registers r1-r3.
3705 // This is a pseudo inst so that we can get the encoding right,
3706 // complete with fixup for the aeabi_read_tp function.
3708 Defs = [R0, R12, LR, CPSR], Uses = [SP] in {
3709 def TPsoft : PseudoInst<(outs), (ins), IIC_Br,
3710 [(set R0, ARMthread_pointer)]>;
3713 //===----------------------------------------------------------------------===//
3714 // SJLJ Exception handling intrinsics
3715 // eh_sjlj_setjmp() is an instruction sequence to store the return
3716 // address and save #0 in R0 for the non-longjmp case.
3717 // Since by its nature we may be coming from some other function to get
3718 // here, and we're using the stack frame for the containing function to
3719 // save/restore registers, we can't keep anything live in regs across
3720 // the eh_sjlj_setjmp(), else it will almost certainly have been tromped upon
3721 // when we get here from a longjmp(). We force everthing out of registers
3722 // except for our own input by listing the relevant registers in Defs. By
3723 // doing so, we also cause the prologue/epilogue code to actively preserve
3724 // all of the callee-saved resgisters, which is exactly what we want.
3725 // A constant value is passed in $val, and we use the location as a scratch.
3727 // These are pseudo-instructions and are lowered to individual MC-insts, so
3728 // no encoding information is necessary.
3730 [ R0, R1, R2, R3, R4, R5, R6, R7, R8, R9, R10, R11, R12, LR, D0,
3731 D1, D2, D3, D4, D5, D6, D7, D8, D9, D10, D11, D12, D13, D14, D15,
3732 D16, D17, D18, D19, D20, D21, D22, D23, D24, D25, D26, D27, D28, D29, D30,
3733 D31 ], hasSideEffects = 1, isBarrier = 1 in {
3734 def Int_eh_sjlj_setjmp : PseudoInst<(outs), (ins GPR:$src, GPR:$val),
3736 [(set R0, (ARMeh_sjlj_setjmp GPR:$src, GPR:$val))]>,
3737 Requires<[IsARM, HasVFP2]>;
3741 [ R0, R1, R2, R3, R4, R5, R6, R7, R8, R9, R10, R11, R12, LR ],
3742 hasSideEffects = 1, isBarrier = 1 in {
3743 def Int_eh_sjlj_setjmp_nofp : PseudoInst<(outs), (ins GPR:$src, GPR:$val),
3745 [(set R0, (ARMeh_sjlj_setjmp GPR:$src, GPR:$val))]>,
3746 Requires<[IsARM, NoVFP]>;
3749 // FIXME: Non-Darwin version(s)
3750 let isBarrier = 1, hasSideEffects = 1, isTerminator = 1,
3751 Defs = [ R7, LR, SP ] in {
3752 def Int_eh_sjlj_longjmp : PseudoInst<(outs), (ins GPR:$src, GPR:$scratch),
3754 [(ARMeh_sjlj_longjmp GPR:$src, GPR:$scratch)]>,
3755 Requires<[IsARM, IsDarwin]>;
3758 // eh.sjlj.dispatchsetup pseudo-instruction.
3759 // This pseudo is used for ARM, Thumb1 and Thumb2. Any differences are
3760 // handled when the pseudo is expanded (which happens before any passes
3761 // that need the instruction size).
3762 let isBarrier = 1, hasSideEffects = 1 in
3763 def Int_eh_sjlj_dispatchsetup :
3764 PseudoInst<(outs), (ins GPR:$src), NoItinerary,
3765 [(ARMeh_sjlj_dispatchsetup GPR:$src)]>,
3766 Requires<[IsDarwin]>;
3768 //===----------------------------------------------------------------------===//
3769 // Non-Instruction Patterns
3772 // Large immediate handling.
3774 // 32-bit immediate using two piece so_imms or movw + movt.
3775 // This is a single pseudo instruction, the benefit is that it can be remat'd
3776 // as a single unit instead of having to handle reg inputs.
3777 // FIXME: Remove this when we can do generalized remat.
3778 let isReMaterializable = 1, isMoveImm = 1 in
3779 def MOVi32imm : PseudoInst<(outs GPR:$dst), (ins i32imm:$src), IIC_iMOVix2,
3780 [(set GPR:$dst, (arm_i32imm:$src))]>,
3783 // Pseudo instruction that combines movw + movt + add pc (if PIC).
3784 // It also makes it possible to rematerialize the instructions.
3785 // FIXME: Remove this when we can do generalized remat and when machine licm
3786 // can properly the instructions.
3787 let isReMaterializable = 1 in {
3788 def MOV_ga_pcrel : PseudoInst<(outs GPR:$dst), (ins i32imm:$addr),
3790 [(set GPR:$dst, (ARMWrapperPIC tglobaladdr:$addr))]>,
3791 Requires<[IsARM, UseMovt]>;
3793 def MOV_ga_dyn : PseudoInst<(outs GPR:$dst), (ins i32imm:$addr),
3795 [(set GPR:$dst, (ARMWrapperDYN tglobaladdr:$addr))]>,
3796 Requires<[IsARM, UseMovt]>;
3798 let AddedComplexity = 10 in
3799 def MOV_ga_pcrel_ldr : PseudoInst<(outs GPR:$dst), (ins i32imm:$addr),
3801 [(set GPR:$dst, (load (ARMWrapperPIC tglobaladdr:$addr)))]>,
3802 Requires<[IsARM, UseMovt]>;
3803 } // isReMaterializable
3805 // ConstantPool, GlobalAddress, and JumpTable
3806 def : ARMPat<(ARMWrapper tglobaladdr :$dst), (LEApcrel tglobaladdr :$dst)>,
3807 Requires<[IsARM, DontUseMovt]>;
3808 def : ARMPat<(ARMWrapper tconstpool :$dst), (LEApcrel tconstpool :$dst)>;
3809 def : ARMPat<(ARMWrapper tglobaladdr :$dst), (MOVi32imm tglobaladdr :$dst)>,
3810 Requires<[IsARM, UseMovt]>;
3811 def : ARMPat<(ARMWrapperJT tjumptable:$dst, imm:$id),
3812 (LEApcrelJT tjumptable:$dst, imm:$id)>;
3814 // TODO: add,sub,and, 3-instr forms?
3817 def : ARMPat<(ARMtcret tcGPR:$dst),
3818 (TCRETURNri tcGPR:$dst)>, Requires<[IsDarwin]>;
3820 def : ARMPat<(ARMtcret (i32 tglobaladdr:$dst)),
3821 (TCRETURNdi texternalsym:$dst)>, Requires<[IsDarwin]>;
3823 def : ARMPat<(ARMtcret (i32 texternalsym:$dst)),
3824 (TCRETURNdi texternalsym:$dst)>, Requires<[IsDarwin]>;
3826 def : ARMPat<(ARMtcret tcGPR:$dst),
3827 (TCRETURNriND tcGPR:$dst)>, Requires<[IsNotDarwin]>;
3829 def : ARMPat<(ARMtcret (i32 tglobaladdr:$dst)),
3830 (TCRETURNdiND texternalsym:$dst)>, Requires<[IsNotDarwin]>;
3832 def : ARMPat<(ARMtcret (i32 texternalsym:$dst)),
3833 (TCRETURNdiND texternalsym:$dst)>, Requires<[IsNotDarwin]>;
3836 def : ARMPat<(ARMcall texternalsym:$func), (BL texternalsym:$func)>,
3837 Requires<[IsARM, IsNotDarwin]>;
3838 def : ARMPat<(ARMcall texternalsym:$func), (BLr9 texternalsym:$func)>,
3839 Requires<[IsARM, IsDarwin]>;
3841 // zextload i1 -> zextload i8
3842 def : ARMPat<(zextloadi1 addrmode_imm12:$addr), (LDRBi12 addrmode_imm12:$addr)>;
3843 def : ARMPat<(zextloadi1 ldst_so_reg:$addr), (LDRBrs ldst_so_reg:$addr)>;
3845 // extload -> zextload
3846 def : ARMPat<(extloadi1 addrmode_imm12:$addr), (LDRBi12 addrmode_imm12:$addr)>;
3847 def : ARMPat<(extloadi1 ldst_so_reg:$addr), (LDRBrs ldst_so_reg:$addr)>;
3848 def : ARMPat<(extloadi8 addrmode_imm12:$addr), (LDRBi12 addrmode_imm12:$addr)>;
3849 def : ARMPat<(extloadi8 ldst_so_reg:$addr), (LDRBrs ldst_so_reg:$addr)>;
3851 def : ARMPat<(extloadi16 addrmode3:$addr), (LDRH addrmode3:$addr)>;
3853 def : ARMPat<(extloadi8 addrmodepc:$addr), (PICLDRB addrmodepc:$addr)>;
3854 def : ARMPat<(extloadi16 addrmodepc:$addr), (PICLDRH addrmodepc:$addr)>;
3857 def : ARMV5TEPat<(mul (sra (shl GPR:$a, (i32 16)), (i32 16)),
3858 (sra (shl GPR:$b, (i32 16)), (i32 16))),
3859 (SMULBB GPR:$a, GPR:$b)>;
3860 def : ARMV5TEPat<(mul sext_16_node:$a, sext_16_node:$b),
3861 (SMULBB GPR:$a, GPR:$b)>;
3862 def : ARMV5TEPat<(mul (sra (shl GPR:$a, (i32 16)), (i32 16)),
3863 (sra GPR:$b, (i32 16))),
3864 (SMULBT GPR:$a, GPR:$b)>;
3865 def : ARMV5TEPat<(mul sext_16_node:$a, (sra GPR:$b, (i32 16))),
3866 (SMULBT GPR:$a, GPR:$b)>;
3867 def : ARMV5TEPat<(mul (sra GPR:$a, (i32 16)),
3868 (sra (shl GPR:$b, (i32 16)), (i32 16))),
3869 (SMULTB GPR:$a, GPR:$b)>;
3870 def : ARMV5TEPat<(mul (sra GPR:$a, (i32 16)), sext_16_node:$b),
3871 (SMULTB GPR:$a, GPR:$b)>;
3872 def : ARMV5TEPat<(sra (mul GPR:$a, (sra (shl GPR:$b, (i32 16)), (i32 16))),
3874 (SMULWB GPR:$a, GPR:$b)>;
3875 def : ARMV5TEPat<(sra (mul GPR:$a, sext_16_node:$b), (i32 16)),
3876 (SMULWB GPR:$a, GPR:$b)>;
3878 def : ARMV5TEPat<(add GPR:$acc,
3879 (mul (sra (shl GPR:$a, (i32 16)), (i32 16)),
3880 (sra (shl GPR:$b, (i32 16)), (i32 16)))),
3881 (SMLABB GPR:$a, GPR:$b, GPR:$acc)>;
3882 def : ARMV5TEPat<(add GPR:$acc,
3883 (mul sext_16_node:$a, sext_16_node:$b)),
3884 (SMLABB GPR:$a, GPR:$b, GPR:$acc)>;
3885 def : ARMV5TEPat<(add GPR:$acc,
3886 (mul (sra (shl GPR:$a, (i32 16)), (i32 16)),
3887 (sra GPR:$b, (i32 16)))),
3888 (SMLABT GPR:$a, GPR:$b, GPR:$acc)>;
3889 def : ARMV5TEPat<(add GPR:$acc,
3890 (mul sext_16_node:$a, (sra GPR:$b, (i32 16)))),
3891 (SMLABT GPR:$a, GPR:$b, GPR:$acc)>;
3892 def : ARMV5TEPat<(add GPR:$acc,
3893 (mul (sra GPR:$a, (i32 16)),
3894 (sra (shl GPR:$b, (i32 16)), (i32 16)))),
3895 (SMLATB GPR:$a, GPR:$b, GPR:$acc)>;
3896 def : ARMV5TEPat<(add GPR:$acc,
3897 (mul (sra GPR:$a, (i32 16)), sext_16_node:$b)),
3898 (SMLATB GPR:$a, GPR:$b, GPR:$acc)>;
3899 def : ARMV5TEPat<(add GPR:$acc,
3900 (sra (mul GPR:$a, (sra (shl GPR:$b, (i32 16)), (i32 16))),
3902 (SMLAWB GPR:$a, GPR:$b, GPR:$acc)>;
3903 def : ARMV5TEPat<(add GPR:$acc,
3904 (sra (mul GPR:$a, sext_16_node:$b), (i32 16))),
3905 (SMLAWB GPR:$a, GPR:$b, GPR:$acc)>;
3908 // Pre-v7 uses MCR for synchronization barriers.
3909 def : ARMPat<(ARMMemBarrierMCR GPR:$zero), (MCR 15, 0, GPR:$zero, 7, 10, 5)>,
3910 Requires<[IsARM, HasV6]>;
3913 //===----------------------------------------------------------------------===//
3917 include "ARMInstrThumb.td"
3919 //===----------------------------------------------------------------------===//
3923 include "ARMInstrThumb2.td"
3925 //===----------------------------------------------------------------------===//
3926 // Floating Point Support
3929 include "ARMInstrVFP.td"
3931 //===----------------------------------------------------------------------===//
3932 // Advanced SIMD (NEON) Support
3935 include "ARMInstrNEON.td"