1 //===- ARMInstrInfo.td - Target Description for ARM Target -*- tablegen -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file describes the ARM instructions in TableGen format.
12 //===----------------------------------------------------------------------===//
14 //===----------------------------------------------------------------------===//
15 // ARM specific DAG Nodes.
19 def SDT_ARMCallSeqStart : SDCallSeqStart<[ SDTCisVT<0, i32> ]>;
20 def SDT_ARMCallSeqEnd : SDCallSeqEnd<[ SDTCisVT<0, i32>, SDTCisVT<1, i32> ]>;
22 def SDT_ARMSaveCallPC : SDTypeProfile<0, 1, []>;
24 def SDT_ARMcall : SDTypeProfile<0, -1, [SDTCisInt<0>]>;
26 def SDT_ARMCMov : SDTypeProfile<1, 3,
27 [SDTCisSameAs<0, 1>, SDTCisSameAs<0, 2>,
30 def SDT_ARMBrcond : SDTypeProfile<0, 2,
31 [SDTCisVT<0, OtherVT>, SDTCisVT<1, i32>]>;
33 def SDT_ARMBrJT : SDTypeProfile<0, 3,
34 [SDTCisPtrTy<0>, SDTCisVT<1, i32>,
37 def SDT_ARMCmp : SDTypeProfile<0, 2, [SDTCisSameAs<0, 1>]>;
39 def SDT_ARMPICAdd : SDTypeProfile<1, 2, [SDTCisSameAs<0, 1>,
40 SDTCisPtrTy<1>, SDTCisVT<2, i32>]>;
42 def SDT_ARMThreadPointer : SDTypeProfile<1, 0, [SDTCisPtrTy<0>]>;
45 def ARMWrapper : SDNode<"ARMISD::Wrapper", SDTIntUnaryOp>;
46 def ARMWrapperJT : SDNode<"ARMISD::WrapperJT", SDTIntBinOp>;
48 def ARMcallseq_start : SDNode<"ISD::CALLSEQ_START", SDT_ARMCallSeqStart,
49 [SDNPHasChain, SDNPOutFlag]>;
50 def ARMcallseq_end : SDNode<"ISD::CALLSEQ_END", SDT_ARMCallSeqEnd,
51 [SDNPHasChain, SDNPOptInFlag, SDNPOutFlag]>;
53 def ARMcall : SDNode<"ARMISD::CALL", SDT_ARMcall,
54 [SDNPHasChain, SDNPOptInFlag, SDNPOutFlag]>;
55 def ARMcall_pred : SDNode<"ARMISD::CALL_PRED", SDT_ARMcall,
56 [SDNPHasChain, SDNPOptInFlag, SDNPOutFlag]>;
57 def ARMcall_nolink : SDNode<"ARMISD::CALL_NOLINK", SDT_ARMcall,
58 [SDNPHasChain, SDNPOptInFlag, SDNPOutFlag]>;
60 def ARMretflag : SDNode<"ARMISD::RET_FLAG", SDTNone,
61 [SDNPHasChain, SDNPOptInFlag]>;
63 def ARMcmov : SDNode<"ARMISD::CMOV", SDT_ARMCMov,
65 def ARMcneg : SDNode<"ARMISD::CNEG", SDT_ARMCMov,
68 def ARMbrcond : SDNode<"ARMISD::BRCOND", SDT_ARMBrcond,
69 [SDNPHasChain, SDNPInFlag, SDNPOutFlag]>;
71 def ARMbrjt : SDNode<"ARMISD::BR_JT", SDT_ARMBrJT,
74 def ARMcmp : SDNode<"ARMISD::CMP", SDT_ARMCmp,
77 def ARMcmpNZ : SDNode<"ARMISD::CMPNZ", SDT_ARMCmp,
80 def ARMpic_add : SDNode<"ARMISD::PIC_ADD", SDT_ARMPICAdd>;
82 def ARMsrl_flag : SDNode<"ARMISD::SRL_FLAG", SDTIntUnaryOp, [SDNPOutFlag]>;
83 def ARMsra_flag : SDNode<"ARMISD::SRA_FLAG", SDTIntUnaryOp, [SDNPOutFlag]>;
84 def ARMrrx : SDNode<"ARMISD::RRX" , SDTIntUnaryOp, [SDNPInFlag ]>;
86 def ARMthread_pointer: SDNode<"ARMISD::THREAD_POINTER", SDT_ARMThreadPointer>;
88 //===----------------------------------------------------------------------===//
89 // ARM Instruction Predicate Definitions.
91 def HasV5T : Predicate<"Subtarget->hasV5TOps()">;
92 def HasV5TE : Predicate<"Subtarget->hasV5TEOps()">;
93 def HasV6 : Predicate<"Subtarget->hasV6Ops()">;
94 def IsThumb : Predicate<"Subtarget->isThumb()">;
95 def IsARM : Predicate<"!Subtarget->isThumb()">;
97 //===----------------------------------------------------------------------===//
98 // ARM Flag Definitions.
100 class RegConstraint<string C> {
101 string Constraints = C;
104 //===----------------------------------------------------------------------===//
105 // ARM specific transformation functions and pattern fragments.
108 // so_imm_XFORM - Return a so_imm value packed into the format described for
110 def so_imm_XFORM : SDNodeXForm<imm, [{
111 return CurDAG->getTargetConstant(ARM_AM::getSOImmVal(N->getZExtValue()),
115 // so_imm_neg_XFORM - Return a so_imm value packed into the format described for
116 // so_imm_neg def below.
117 def so_imm_neg_XFORM : SDNodeXForm<imm, [{
118 return CurDAG->getTargetConstant(ARM_AM::getSOImmVal(-(int)N->getZExtValue()),
122 // so_imm_not_XFORM - Return a so_imm value packed into the format described for
123 // so_imm_not def below.
124 def so_imm_not_XFORM : SDNodeXForm<imm, [{
125 return CurDAG->getTargetConstant(ARM_AM::getSOImmVal(~(int)N->getZExtValue()),
129 // rot_imm predicate - True if the 32-bit immediate is equal to 8, 16, or 24.
130 def rot_imm : PatLeaf<(i32 imm), [{
131 int32_t v = (int32_t)N->getZExtValue();
132 return v == 8 || v == 16 || v == 24;
135 /// imm1_15 predicate - True if the 32-bit immediate is in the range [1,15].
136 def imm1_15 : PatLeaf<(i32 imm), [{
137 return (int32_t)N->getZExtValue() >= 1 && (int32_t)N->getZExtValue() < 16;
140 /// imm16_31 predicate - True if the 32-bit immediate is in the range [16,31].
141 def imm16_31 : PatLeaf<(i32 imm), [{
142 return (int32_t)N->getZExtValue() >= 16 && (int32_t)N->getZExtValue() < 32;
147 return ARM_AM::getSOImmVal(-(int)N->getZExtValue()) != -1;
148 }], so_imm_neg_XFORM>;
152 return ARM_AM::getSOImmVal(~(int)N->getZExtValue()) != -1;
153 }], so_imm_not_XFORM>;
155 // sext_16_node predicate - True if the SDNode is sign-extended 16 or more bits.
156 def sext_16_node : PatLeaf<(i32 GPR:$a), [{
157 return CurDAG->ComputeNumSignBits(SDValue(N,0)) >= 17;
160 class BinOpFrag<dag res> : PatFrag<(ops node:$LHS, node:$RHS), res>;
161 class UnOpFrag <dag res> : PatFrag<(ops node:$Src), res>;
163 //===----------------------------------------------------------------------===//
164 // Operand Definitions.
168 def brtarget : Operand<OtherVT>;
170 // A list of registers separated by comma. Used by load/store multiple.
171 def reglist : Operand<i32> {
172 let PrintMethod = "printRegisterList";
175 // An operand for the CONSTPOOL_ENTRY pseudo-instruction.
176 def cpinst_operand : Operand<i32> {
177 let PrintMethod = "printCPInstOperand";
180 def jtblock_operand : Operand<i32> {
181 let PrintMethod = "printJTBlockOperand";
185 def pclabel : Operand<i32> {
186 let PrintMethod = "printPCLabel";
189 // shifter_operand operands: so_reg and so_imm.
190 def so_reg : Operand<i32>, // reg reg imm
191 ComplexPattern<i32, 3, "SelectShifterOperandReg",
192 [shl,srl,sra,rotr]> {
193 let PrintMethod = "printSORegOperand";
194 let MIOperandInfo = (ops GPR, GPR, i32imm);
197 // so_imm - Match a 32-bit shifter_operand immediate operand, which is an
198 // 8-bit immediate rotated by an arbitrary number of bits. so_imm values are
199 // represented in the imm field in the same 12-bit form that they are encoded
200 // into so_imm instructions: the 8-bit immediate is the least significant bits
201 // [bits 0-7], the 4-bit shift amount is the next 4 bits [bits 8-11].
202 def so_imm : Operand<i32>,
204 [{ return ARM_AM::getSOImmVal(N->getZExtValue()) != -1; }],
206 let PrintMethod = "printSOImmOperand";
209 // Break so_imm's up into two pieces. This handles immediates with up to 16
210 // bits set in them. This uses so_imm2part to match and so_imm2part_[12] to
211 // get the first/second pieces.
212 def so_imm2part : Operand<i32>,
214 return ARM_AM::isSOImmTwoPartVal((unsigned)N->getZExtValue());
216 let PrintMethod = "printSOImm2PartOperand";
219 def so_imm2part_1 : SDNodeXForm<imm, [{
220 unsigned V = ARM_AM::getSOImmTwoPartFirst((unsigned)N->getZExtValue());
221 return CurDAG->getTargetConstant(ARM_AM::getSOImmVal(V), MVT::i32);
224 def so_imm2part_2 : SDNodeXForm<imm, [{
225 unsigned V = ARM_AM::getSOImmTwoPartSecond((unsigned)N->getZExtValue());
226 return CurDAG->getTargetConstant(ARM_AM::getSOImmVal(V), MVT::i32);
230 // Define ARM specific addressing modes.
232 // addrmode2 := reg +/- reg shop imm
233 // addrmode2 := reg +/- imm12
235 def addrmode2 : Operand<i32>,
236 ComplexPattern<i32, 3, "SelectAddrMode2", []> {
237 let PrintMethod = "printAddrMode2Operand";
238 let MIOperandInfo = (ops GPR:$base, GPR:$offsreg, i32imm:$offsimm);
241 def am2offset : Operand<i32>,
242 ComplexPattern<i32, 2, "SelectAddrMode2Offset", []> {
243 let PrintMethod = "printAddrMode2OffsetOperand";
244 let MIOperandInfo = (ops GPR, i32imm);
247 // addrmode3 := reg +/- reg
248 // addrmode3 := reg +/- imm8
250 def addrmode3 : Operand<i32>,
251 ComplexPattern<i32, 3, "SelectAddrMode3", []> {
252 let PrintMethod = "printAddrMode3Operand";
253 let MIOperandInfo = (ops GPR:$base, GPR:$offsreg, i32imm:$offsimm);
256 def am3offset : Operand<i32>,
257 ComplexPattern<i32, 2, "SelectAddrMode3Offset", []> {
258 let PrintMethod = "printAddrMode3OffsetOperand";
259 let MIOperandInfo = (ops GPR, i32imm);
262 // addrmode4 := reg, <mode|W>
264 def addrmode4 : Operand<i32>,
265 ComplexPattern<i32, 2, "", []> {
266 let PrintMethod = "printAddrMode4Operand";
267 let MIOperandInfo = (ops GPR, i32imm);
270 // addrmode5 := reg +/- imm8*4
272 def addrmode5 : Operand<i32>,
273 ComplexPattern<i32, 2, "SelectAddrMode5", []> {
274 let PrintMethod = "printAddrMode5Operand";
275 let MIOperandInfo = (ops GPR, i32imm);
278 // addrmodepc := pc + reg
280 def addrmodepc : Operand<i32>,
281 ComplexPattern<i32, 2, "SelectAddrModePC", []> {
282 let PrintMethod = "printAddrModePCOperand";
283 let MIOperandInfo = (ops GPR, i32imm);
286 // ARM Predicate operand. Default to 14 = always (AL). Second part is CC
287 // register whose default is 0 (no register).
288 def pred : PredicateOperand<OtherVT, (ops i32imm, CCR),
289 (ops (i32 14), (i32 zero_reg))> {
290 let PrintMethod = "printPredicateOperand";
293 // Conditional code result for instructions whose 's' bit is set, e.g. subs.
295 def cc_out : OptionalDefOperand<OtherVT, (ops CCR), (ops (i32 zero_reg))> {
296 let PrintMethod = "printSBitModifierOperand";
299 //===----------------------------------------------------------------------===//
300 // ARM Instruction flags. These need to match ARMInstrInfo.h.
304 class AddrMode<bits<4> val> {
307 def AddrModeNone : AddrMode<0>;
308 def AddrMode1 : AddrMode<1>;
309 def AddrMode2 : AddrMode<2>;
310 def AddrMode3 : AddrMode<3>;
311 def AddrMode4 : AddrMode<4>;
312 def AddrMode5 : AddrMode<5>;
313 def AddrModeT1 : AddrMode<6>;
314 def AddrModeT2 : AddrMode<7>;
315 def AddrModeT4 : AddrMode<8>;
316 def AddrModeTs : AddrMode<9>;
319 class SizeFlagVal<bits<3> val> {
322 def SizeInvalid : SizeFlagVal<0>; // Unset.
323 def SizeSpecial : SizeFlagVal<1>; // Pseudo or special.
324 def Size8Bytes : SizeFlagVal<2>;
325 def Size4Bytes : SizeFlagVal<3>;
326 def Size2Bytes : SizeFlagVal<4>;
328 // Load / store index mode.
329 class IndexMode<bits<2> val> {
332 def IndexModeNone : IndexMode<0>;
333 def IndexModePre : IndexMode<1>;
334 def IndexModePost : IndexMode<2>;
336 //===----------------------------------------------------------------------===//
338 include "ARMInstrFormats.td"
340 //===----------------------------------------------------------------------===//
341 // Multiclass helpers...
344 /// AsI1_bin_irs - Defines a set of (op r, {so_imm|r|so_reg}) patterns for a
345 /// binop that produces a value.
346 multiclass AsI1_bin_irs<bits<4> opcod, string opc, PatFrag opnode> {
347 def ri : AsI1<opcod, (outs GPR:$dst), (ins GPR:$a, so_imm:$b), DPFrm,
348 opc, " $dst, $a, $b",
349 [(set GPR:$dst, (opnode GPR:$a, so_imm:$b))]>;
350 def rr : AsI1<opcod, (outs GPR:$dst), (ins GPR:$a, GPR:$b), DPFrm,
351 opc, " $dst, $a, $b",
352 [(set GPR:$dst, (opnode GPR:$a, GPR:$b))]>;
353 def rs : AsI1<opcod, (outs GPR:$dst), (ins GPR:$a, so_reg:$b), DPSoRegFrm,
354 opc, " $dst, $a, $b",
355 [(set GPR:$dst, (opnode GPR:$a, so_reg:$b))]>;
358 /// ASI1_bin_s_irs - Similar to AsI1_bin_irs except it sets the 's' bit so the
359 /// instruction modifies the CSPR register.
360 let Defs = [CPSR] in {
361 multiclass ASI1_bin_s_irs<bits<4> opcod, string opc, PatFrag opnode> {
362 def ri : AI1<opcod, (outs GPR:$dst), (ins GPR:$a, so_imm:$b), DPFrm,
363 opc, "s $dst, $a, $b",
364 [(set GPR:$dst, (opnode GPR:$a, so_imm:$b))]>;
365 def rr : AI1<opcod, (outs GPR:$dst), (ins GPR:$a, GPR:$b), DPFrm,
366 opc, "s $dst, $a, $b",
367 [(set GPR:$dst, (opnode GPR:$a, GPR:$b))]>;
368 def rs : AI1<opcod, (outs GPR:$dst), (ins GPR:$a, so_reg:$b), DPSoRegFrm,
369 opc, "s $dst, $a, $b",
370 [(set GPR:$dst, (opnode GPR:$a, so_reg:$b))]>;
374 /// AI1_cmp_irs - Defines a set of (op r, {so_imm|r|so_reg}) cmp / test
375 /// patterns. Similar to AsI1_bin_irs except the instruction does not produce
376 /// a explicit result, only implicitly set CPSR.
377 let Defs = [CPSR] in {
378 multiclass AI1_cmp_irs<bits<4> opcod, string opc, PatFrag opnode> {
379 def ri : AI1<opcod, (outs), (ins GPR:$a, so_imm:$b), DPFrm,
381 [(opnode GPR:$a, so_imm:$b)]>;
382 def rr : AI1<opcod, (outs), (ins GPR:$a, GPR:$b), DPFrm,
384 [(opnode GPR:$a, GPR:$b)]>;
385 def rs : AI1<opcod, (outs), (ins GPR:$a, so_reg:$b), DPSoRegFrm,
387 [(opnode GPR:$a, so_reg:$b)]>;
391 /// AI_unary_rrot - A unary operation with two forms: one whose operand is a
392 /// register and one whose operand is a register rotated by 8/16/24.
393 multiclass AI_unary_rrot<string opc, PatFrag opnode> {
394 def r : AI<(outs GPR:$dst), (ins GPR:$Src), Pseudo,
396 [(set GPR:$dst, (opnode GPR:$Src))]>, Requires<[IsARM, HasV6]>;
397 def r_rot : AI<(outs GPR:$dst), (ins GPR:$Src, i32imm:$rot), Pseudo,
398 opc, " $dst, $Src, ror $rot",
399 [(set GPR:$dst, (opnode (rotr GPR:$Src, rot_imm:$rot)))]>,
400 Requires<[IsARM, HasV6]>;
403 /// AI_bin_rrot - A binary operation with two forms: one whose operand is a
404 /// register and one whose operand is a register rotated by 8/16/24.
405 multiclass AI_bin_rrot<string opc, PatFrag opnode> {
406 def rr : AI<(outs GPR:$dst), (ins GPR:$LHS, GPR:$RHS),
407 Pseudo, opc, " $dst, $LHS, $RHS",
408 [(set GPR:$dst, (opnode GPR:$LHS, GPR:$RHS))]>,
409 Requires<[IsARM, HasV6]>;
410 def rr_rot : AI<(outs GPR:$dst), (ins GPR:$LHS, GPR:$RHS, i32imm:$rot),
411 Pseudo, opc, " $dst, $LHS, $RHS, ror $rot",
412 [(set GPR:$dst, (opnode GPR:$LHS,
413 (rotr GPR:$RHS, rot_imm:$rot)))]>,
414 Requires<[IsARM, HasV6]>;
417 /// AsXI1_bin_c_irs - Same as AsI1_bin_irs but without the predicate operand and
418 /// setting carry bit. But it can optionally set CPSR.
419 let Uses = [CPSR] in {
420 multiclass AsXI1_bin_c_irs<bits<4> opcod, string opc, PatFrag opnode> {
421 def ri : AXI1<opcod, (outs GPR:$dst), (ins GPR:$a, so_imm:$b, cc_out:$s),
422 DPFrm, !strconcat(opc, "${s} $dst, $a, $b"),
423 [(set GPR:$dst, (opnode GPR:$a, so_imm:$b))]>;
424 def rr : AXI1<opcod, (outs GPR:$dst), (ins GPR:$a, GPR:$b, cc_out:$s),
425 DPFrm, !strconcat(opc, "${s} $dst, $a, $b"),
426 [(set GPR:$dst, (opnode GPR:$a, GPR:$b))]>;
427 def rs : AXI1<opcod, (outs GPR:$dst), (ins GPR:$a, so_reg:$b, cc_out:$s),
428 DPSoRegFrm, !strconcat(opc, "${s} $dst, $a, $b"),
429 [(set GPR:$dst, (opnode GPR:$a, so_reg:$b))]>;
433 //===----------------------------------------------------------------------===//
435 //===----------------------------------------------------------------------===//
437 //===----------------------------------------------------------------------===//
438 // Miscellaneous Instructions.
441 /// CONSTPOOL_ENTRY - This instruction represents a floating constant pool in
442 /// the function. The first operand is the ID# for this instruction, the second
443 /// is the index into the MachineConstantPool that this is, the third is the
444 /// size in bytes of this constant pool entry.
445 let isNotDuplicable = 1 in
446 def CONSTPOOL_ENTRY :
447 PseudoInst<(outs), (ins cpinst_operand:$instid, cpinst_operand:$cpidx,
449 "${instid:label} ${cpidx:cpentry}", []>;
451 let Defs = [SP], Uses = [SP] in {
453 PseudoInst<(outs), (ins i32imm:$amt1, i32imm:$amt2, pred:$p),
454 "@ ADJCALLSTACKUP $amt1",
455 [(ARMcallseq_end timm:$amt1, timm:$amt2)]>;
457 def ADJCALLSTACKDOWN :
458 PseudoInst<(outs), (ins i32imm:$amt, pred:$p),
459 "@ ADJCALLSTACKDOWN $amt",
460 [(ARMcallseq_start timm:$amt)]>;
464 PseudoInst<(outs), (ins i32imm:$line, i32imm:$col, i32imm:$file),
465 ".loc $file, $line, $col",
466 [(dwarf_loc (i32 imm:$line), (i32 imm:$col), (i32 imm:$file))]>;
469 // Address computation and loads and stores in PIC mode.
470 let isNotDuplicable = 1 in {
471 def PICADD : AXI1<0b0100, (outs GPR:$dst), (ins GPR:$a, pclabel:$cp, pred:$p),
472 Pseudo, "$cp:\n\tadd$p $dst, pc, $a",
473 [(set GPR:$dst, (ARMpic_add GPR:$a, imm:$cp))]>;
475 let AddedComplexity = 10 in {
476 let isSimpleLoad = 1 in
477 def PICLDR : AXI2ldw<(outs GPR:$dst), (ins addrmodepc:$addr, pred:$p),
478 Pseudo, "${addr:label}:\n\tldr$p $dst, $addr",
479 [(set GPR:$dst, (load addrmodepc:$addr))]>;
481 def PICLDRH : AXI3ldh<(outs GPR:$dst), (ins addrmodepc:$addr, pred:$p),
482 Pseudo, "${addr:label}:\n\tldr${p}h $dst, $addr",
483 [(set GPR:$dst, (zextloadi16 addrmodepc:$addr))]>;
485 def PICLDRB : AXI2ldb<(outs GPR:$dst), (ins addrmodepc:$addr, pred:$p),
486 Pseudo, "${addr:label}:\n\tldr${p}b $dst, $addr",
487 [(set GPR:$dst, (zextloadi8 addrmodepc:$addr))]>;
489 def PICLDRSH : AXI3ldsh<(outs GPR:$dst), (ins addrmodepc:$addr, pred:$p),
490 Pseudo, "${addr:label}:\n\tldr${p}sh $dst, $addr",
491 [(set GPR:$dst, (sextloadi16 addrmodepc:$addr))]>;
493 def PICLDRSB : AXI3ldsb<(outs GPR:$dst), (ins addrmodepc:$addr, pred:$p),
494 Pseudo, "${addr:label}:\n\tldr${p}sb $dst, $addr",
495 [(set GPR:$dst, (sextloadi8 addrmodepc:$addr))]>;
497 let AddedComplexity = 10 in {
498 def PICSTR : AXI2stw<(outs), (ins GPR:$src, addrmodepc:$addr, pred:$p),
499 Pseudo, "${addr:label}:\n\tstr$p $src, $addr",
500 [(store GPR:$src, addrmodepc:$addr)]>;
502 def PICSTRH : AXI3sth<(outs), (ins GPR:$src, addrmodepc:$addr, pred:$p),
503 Pseudo, "${addr:label}:\n\tstr${p}h $src, $addr",
504 [(truncstorei16 GPR:$src, addrmodepc:$addr)]>;
506 def PICSTRB : AXI2stb<(outs), (ins GPR:$src, addrmodepc:$addr, pred:$p),
507 Pseudo, "${addr:label}:\n\tstr${p}b $src, $addr",
508 [(truncstorei8 GPR:$src, addrmodepc:$addr)]>;
510 } // isNotDuplicable = 1
512 //===----------------------------------------------------------------------===//
513 // Control Flow Instructions.
516 let isReturn = 1, isTerminator = 1 in
517 def BX_RET : AI<(outs), (ins), BrMiscFrm, "bx", " lr", [(ARMretflag)]> {
518 let Inst{7-4} = 0b0001;
519 let Inst{19-8} = 0b111111111111;
520 let Inst{27-20} = 0b00010010;
523 // FIXME: remove when we have a way to marking a MI with these properties.
524 // FIXME: $dst1 should be a def. But the extra ops must be in the end of the
526 // FIXME: Should pc be an implicit operand like PICADD, etc?
527 let isReturn = 1, isTerminator = 1 in
528 def LDM_RET : AXI4ld<(outs),
529 (ins addrmode4:$addr, pred:$p, reglist:$dst1, variable_ops),
530 LdMulFrm, "ldm${p}${addr:submode} $addr, $dst1",
534 Defs = [R0, R1, R2, R3, R12, LR,
535 D0, D1, D2, D3, D4, D5, D6, D7, CPSR] in {
536 def BL : ABXI<0b1011, (outs), (ins i32imm:$func, variable_ops),
538 [(ARMcall tglobaladdr:$func)]>;
540 def BL_pred : ABI<0b1011, (outs), (ins i32imm:$func, variable_ops),
541 "bl", " ${func:call}",
542 [(ARMcall_pred tglobaladdr:$func)]>;
545 def BLX : AXI<(outs), (ins GPR:$func, variable_ops), BrMiscFrm,
547 [(ARMcall GPR:$func)]>, Requires<[IsARM, HasV5T]> {
548 let Inst{7-4} = 0b0011;
549 let Inst{19-8} = 0b111111111111;
550 let Inst{27-20} = 0b00010010;
555 def BX : ABXIx2<(outs), (ins GPR:$func, variable_ops),
556 "mov lr, pc\n\tbx $func",
557 [(ARMcall_nolink GPR:$func)]>;
561 let isBranch = 1, isTerminator = 1 in {
562 // B is "predicable" since it can be xformed into a Bcc.
563 let isBarrier = 1 in {
564 let isPredicable = 1 in
565 def B : ABXI<0b1010, (outs), (ins brtarget:$target), "b $target",
568 let isNotDuplicable = 1, isIndirectBranch = 1 in {
569 def BR_JTr : JTI<0b1101, (outs),
570 (ins GPR:$target, jtblock_operand:$jt, i32imm:$id),
571 "mov pc, $target \n$jt",
572 [(ARMbrjt GPR:$target, tjumptable:$jt, imm:$id)]>;
573 def BR_JTm : JTI2<0, (outs),
574 (ins addrmode2:$target, jtblock_operand:$jt, i32imm:$id),
575 "ldr pc, $target \n$jt",
576 [(ARMbrjt (i32 (load addrmode2:$target)), tjumptable:$jt,
578 def BR_JTadd : JTI1<0b0100, (outs),
579 (ins GPR:$target, GPR:$idx, jtblock_operand:$jt,
581 "add pc, $target, $idx \n$jt",
582 [(ARMbrjt (add GPR:$target, GPR:$idx), tjumptable:$jt,
587 // FIXME: should be able to write a pattern for ARMBrcond, but can't use
588 // a two-value operand where a dag node expects two operands. :(
589 def Bcc : ABI<0b1010, (outs), (ins brtarget:$target),
591 [/*(ARMbrcond bb:$target, imm:$cc, CCR:$ccr)*/]>;
594 //===----------------------------------------------------------------------===//
595 // Load / store Instructions.
599 let isSimpleLoad = 1 in
600 def LDR : AI2ldw<(outs GPR:$dst), (ins addrmode2:$addr), LdFrm,
601 "ldr", " $dst, $addr",
602 [(set GPR:$dst, (load addrmode2:$addr))]>;
604 // Special LDR for loads from non-pc-relative constpools.
605 let isSimpleLoad = 1, mayLoad = 1, isReMaterializable = 1 in
606 def LDRcp : AI2ldw<(outs GPR:$dst), (ins addrmode2:$addr), LdFrm,
607 "ldr", " $dst, $addr", []>;
609 // Loads with zero extension
610 def LDRH : AI3ldh<(outs GPR:$dst), (ins addrmode3:$addr), LdMiscFrm,
611 "ldr", "h $dst, $addr",
612 [(set GPR:$dst, (zextloadi16 addrmode3:$addr))]>;
614 def LDRB : AI2ldb<(outs GPR:$dst), (ins addrmode2:$addr), LdFrm,
615 "ldr", "b $dst, $addr",
616 [(set GPR:$dst, (zextloadi8 addrmode2:$addr))]>;
618 // Loads with sign extension
619 def LDRSH : AI3ldsh<(outs GPR:$dst), (ins addrmode3:$addr), LdMiscFrm,
620 "ldr", "sh $dst, $addr",
621 [(set GPR:$dst, (sextloadi16 addrmode3:$addr))]>;
623 def LDRSB : AI3ldsb<(outs GPR:$dst), (ins addrmode3:$addr), LdMiscFrm,
624 "ldr", "sb $dst, $addr",
625 [(set GPR:$dst, (sextloadi8 addrmode3:$addr))]>;
629 def LDRD : AI3ldd<(outs GPR:$dst), (ins addrmode3:$addr), LdMiscFrm,
630 "ldr", "d $dst, $addr",
631 []>, Requires<[IsARM, HasV5T]>;
634 def LDR_PRE : AI2ldwpr<(outs GPR:$dst, GPR:$base_wb),
635 (ins addrmode2:$addr), LdFrm,
636 "ldr", " $dst, $addr!", "$addr.base = $base_wb", []>;
638 def LDR_POST : AI2ldwpo<(outs GPR:$dst, GPR:$base_wb),
639 (ins GPR:$base, am2offset:$offset), LdFrm,
640 "ldr", " $dst, [$base], $offset", "$base = $base_wb", []>;
642 def LDRH_PRE : AI3ldhpr<(outs GPR:$dst, GPR:$base_wb),
643 (ins addrmode3:$addr), LdMiscFrm,
644 "ldr", "h $dst, $addr!", "$addr.base = $base_wb", []>;
646 def LDRH_POST : AI3ldhpo<(outs GPR:$dst, GPR:$base_wb),
647 (ins GPR:$base,am3offset:$offset), LdMiscFrm,
648 "ldr", "h $dst, [$base], $offset", "$base = $base_wb", []>;
650 def LDRB_PRE : AI2ldbpr<(outs GPR:$dst, GPR:$base_wb),
651 (ins addrmode2:$addr), LdFrm,
652 "ldr", "b $dst, $addr!", "$addr.base = $base_wb", []>;
654 def LDRB_POST : AI2ldbpo<(outs GPR:$dst, GPR:$base_wb),
655 (ins GPR:$base,am2offset:$offset), LdFrm,
656 "ldr", "b $dst, [$base], $offset", "$base = $base_wb", []>;
658 def LDRSH_PRE : AI3ldshpr<(outs GPR:$dst, GPR:$base_wb),
659 (ins addrmode3:$addr), LdMiscFrm,
660 "ldr", "sh $dst, $addr!", "$addr.base = $base_wb", []>;
662 def LDRSH_POST: AI3ldshpo<(outs GPR:$dst, GPR:$base_wb),
663 (ins GPR:$base,am3offset:$offset), LdMiscFrm,
664 "ldr", "sh $dst, [$base], $offset", "$base = $base_wb", []>;
666 def LDRSB_PRE : AI3ldsbpr<(outs GPR:$dst, GPR:$base_wb),
667 (ins addrmode3:$addr), LdMiscFrm,
668 "ldr", "sb $dst, $addr!", "$addr.base = $base_wb", []>;
670 def LDRSB_POST: AI3ldsbpo<(outs GPR:$dst, GPR:$base_wb),
671 (ins GPR:$base,am3offset:$offset), LdMiscFrm,
672 "ldr", "sb $dst, [$base], $offset", "$base = $base_wb", []>;
676 def STR : AI2stw<(outs), (ins GPR:$src, addrmode2:$addr), StFrm,
677 "str", " $src, $addr",
678 [(store GPR:$src, addrmode2:$addr)]>;
680 // Stores with truncate
681 def STRH : AI3sth<(outs), (ins GPR:$src, addrmode3:$addr), StMiscFrm,
682 "str", "h $src, $addr",
683 [(truncstorei16 GPR:$src, addrmode3:$addr)]>;
685 def STRB : AI2stb<(outs), (ins GPR:$src, addrmode2:$addr), StFrm,
686 "str", "b $src, $addr",
687 [(truncstorei8 GPR:$src, addrmode2:$addr)]>;
691 def STRD : AI3std<(outs), (ins GPR:$src, addrmode3:$addr), StMiscFrm,
692 "str", "d $src, $addr",
693 []>, Requires<[IsARM, HasV5T]>;
696 def STR_PRE : AI2stwpr<(outs GPR:$base_wb),
697 (ins GPR:$src, GPR:$base, am2offset:$offset), StFrm,
698 "str", " $src, [$base, $offset]!", "$base = $base_wb",
700 (pre_store GPR:$src, GPR:$base, am2offset:$offset))]>;
702 def STR_POST : AI2stwpo<(outs GPR:$base_wb),
703 (ins GPR:$src, GPR:$base,am2offset:$offset), StFrm,
704 "str", " $src, [$base], $offset", "$base = $base_wb",
706 (post_store GPR:$src, GPR:$base, am2offset:$offset))]>;
708 def STRH_PRE : AI3sthpr<(outs GPR:$base_wb),
709 (ins GPR:$src, GPR:$base,am3offset:$offset), StMiscFrm,
710 "str", "h $src, [$base, $offset]!", "$base = $base_wb",
712 (pre_truncsti16 GPR:$src, GPR:$base,am3offset:$offset))]>;
714 def STRH_POST: AI3sthpo<(outs GPR:$base_wb),
715 (ins GPR:$src, GPR:$base,am3offset:$offset), StMiscFrm,
716 "str", "h $src, [$base], $offset", "$base = $base_wb",
717 [(set GPR:$base_wb, (post_truncsti16 GPR:$src,
718 GPR:$base, am3offset:$offset))]>;
720 def STRB_PRE : AI2stbpr<(outs GPR:$base_wb),
721 (ins GPR:$src, GPR:$base,am2offset:$offset), StFrm,
722 "str", "b $src, [$base, $offset]!", "$base = $base_wb",
723 [(set GPR:$base_wb, (pre_truncsti8 GPR:$src,
724 GPR:$base, am2offset:$offset))]>;
726 def STRB_POST: AI2stbpo<(outs GPR:$base_wb),
727 (ins GPR:$src, GPR:$base,am2offset:$offset), StFrm,
728 "str", "b $src, [$base], $offset", "$base = $base_wb",
729 [(set GPR:$base_wb, (post_truncsti8 GPR:$src,
730 GPR:$base, am2offset:$offset))]>;
732 //===----------------------------------------------------------------------===//
733 // Load / store multiple Instructions.
736 // FIXME: $dst1 should be a def.
738 def LDM : AXI4ld<(outs),
739 (ins addrmode4:$addr, pred:$p, reglist:$dst1, variable_ops),
740 LdMulFrm, "ldm${p}${addr:submode} $addr, $dst1",
744 def STM : AXI4st<(outs),
745 (ins addrmode4:$addr, pred:$p, reglist:$src1, variable_ops),
746 StMulFrm, "stm${p}${addr:submode} $addr, $src1",
749 //===----------------------------------------------------------------------===//
750 // Move Instructions.
753 def MOVr : AsI1<0b1101, (outs GPR:$dst), (ins GPR:$src), DPFrm,
754 "mov", " $dst, $src", []>, UnaryDP;
755 def MOVs : AsI1<0b1101, (outs GPR:$dst), (ins so_reg:$src), DPSoRegFrm,
756 "mov", " $dst, $src", [(set GPR:$dst, so_reg:$src)]>, UnaryDP;
758 let isReMaterializable = 1 in
759 def MOVi : AsI1<0b1101, (outs GPR:$dst), (ins so_imm:$src), DPFrm,
760 "mov", " $dst, $src", [(set GPR:$dst, so_imm:$src)]>, UnaryDP;
762 def MOVrx : AsI1<0b1101, (outs GPR:$dst), (ins GPR:$src), DPFrm,
763 "mov", " $dst, $src, rrx",
764 [(set GPR:$dst, (ARMrrx GPR:$src))]>, UnaryDP;
766 // These aren't really mov instructions, but we have to define them this way
767 // due to flag operands.
769 let Defs = [CPSR] in {
770 def MOVsrl_flag : AI1<0b1101, (outs GPR:$dst), (ins GPR:$src), DPFrm,
771 "mov", "s $dst, $src, lsr #1",
772 [(set GPR:$dst, (ARMsrl_flag GPR:$src))]>, UnaryDP;
773 def MOVsra_flag : AI1<0b1101, (outs GPR:$dst), (ins GPR:$src), DPFrm,
774 "mov", "s $dst, $src, asr #1",
775 [(set GPR:$dst, (ARMsra_flag GPR:$src))]>, UnaryDP;
778 //===----------------------------------------------------------------------===//
779 // Extend Instructions.
784 defm SXTB : AI_unary_rrot<"sxtb", UnOpFrag<(sext_inreg node:$Src, i8)>>;
785 defm SXTH : AI_unary_rrot<"sxth", UnOpFrag<(sext_inreg node:$Src, i16)>>;
787 defm SXTAB : AI_bin_rrot<"sxtab",
788 BinOpFrag<(add node:$LHS, (sext_inreg node:$RHS, i8))>>;
789 defm SXTAH : AI_bin_rrot<"sxtah",
790 BinOpFrag<(add node:$LHS, (sext_inreg node:$RHS,i16))>>;
792 // TODO: SXT(A){B|H}16
796 let AddedComplexity = 16 in {
797 defm UXTB : AI_unary_rrot<"uxtb" , UnOpFrag<(and node:$Src, 0x000000FF)>>;
798 defm UXTH : AI_unary_rrot<"uxth" , UnOpFrag<(and node:$Src, 0x0000FFFF)>>;
799 defm UXTB16 : AI_unary_rrot<"uxtb16", UnOpFrag<(and node:$Src, 0x00FF00FF)>>;
801 def : ARMV6Pat<(and (shl GPR:$Src, 8), 0xFF00FF),
802 (UXTB16r_rot GPR:$Src, 24)>;
803 def : ARMV6Pat<(and (srl GPR:$Src, 8), 0xFF00FF),
804 (UXTB16r_rot GPR:$Src, 8)>;
806 defm UXTAB : AI_bin_rrot<"uxtab",
807 BinOpFrag<(add node:$LHS, (and node:$RHS, 0x00FF))>>;
808 defm UXTAH : AI_bin_rrot<"uxtah",
809 BinOpFrag<(add node:$LHS, (and node:$RHS, 0xFFFF))>>;
812 // This isn't safe in general, the add is two 16-bit units, not a 32-bit add.
813 //defm UXTAB16 : xxx<"uxtab16", 0xff00ff>;
815 // TODO: UXT(A){B|H}16
817 //===----------------------------------------------------------------------===//
818 // Arithmetic Instructions.
821 defm ADD : AsI1_bin_irs<0b0100, "add",
822 BinOpFrag<(add node:$LHS, node:$RHS)>>;
823 defm SUB : AsI1_bin_irs<0b0010, "sub",
824 BinOpFrag<(sub node:$LHS, node:$RHS)>>;
826 // ADD and SUB with 's' bit set.
827 defm ADDS : ASI1_bin_s_irs<0b0100, "add",
828 BinOpFrag<(addc node:$LHS, node:$RHS)>>;
829 defm SUBS : ASI1_bin_s_irs<0b0010, "sub",
830 BinOpFrag<(subc node:$LHS, node:$RHS)>>;
832 // FIXME: Do not allow ADC / SBC to be predicated for now.
833 defm ADC : AsXI1_bin_c_irs<0b0101, "adc",
834 BinOpFrag<(adde node:$LHS, node:$RHS)>>;
835 defm SBC : AsXI1_bin_c_irs<0b0110, "sbc",
836 BinOpFrag<(sube node:$LHS, node:$RHS)>>;
838 // These don't define reg/reg forms, because they are handled above.
839 def RSBri : AsI1<0b0011, (outs GPR:$dst), (ins GPR:$a, so_imm:$b), DPFrm,
840 "rsb", " $dst, $a, $b",
841 [(set GPR:$dst, (sub so_imm:$b, GPR:$a))]>;
843 def RSBrs : AsI1<0b0011, (outs GPR:$dst), (ins GPR:$a, so_reg:$b), DPSoRegFrm,
844 "rsb", " $dst, $a, $b",
845 [(set GPR:$dst, (sub so_reg:$b, GPR:$a))]>;
847 // RSB with 's' bit set.
848 let Defs = [CPSR] in {
849 def RSBSri : AI1<0b0011, (outs GPR:$dst), (ins GPR:$a, so_imm:$b), DPFrm,
850 "rsb", "s $dst, $a, $b",
851 [(set GPR:$dst, (subc so_imm:$b, GPR:$a))]>;
852 def RSBSrs : AI1<0b0011, (outs GPR:$dst), (ins GPR:$a, so_reg:$b), DPSoRegFrm,
853 "rsb", "s $dst, $a, $b",
854 [(set GPR:$dst, (subc so_reg:$b, GPR:$a))]>;
857 // FIXME: Do not allow RSC to be predicated for now. But they can set CPSR.
858 let Uses = [CPSR] in {
859 def RSCri : AXI1<0b0111, (outs GPR:$dst), (ins GPR:$a, so_imm:$b, cc_out:$s),
860 DPFrm, "rsc${s} $dst, $a, $b",
861 [(set GPR:$dst, (sube so_imm:$b, GPR:$a))]>;
862 def RSCrs : AXI1<0b0111, (outs GPR:$dst), (ins GPR:$a, so_reg:$b, cc_out:$s),
863 DPSoRegFrm, "rsc${s} $dst, $a, $b",
864 [(set GPR:$dst, (sube so_reg:$b, GPR:$a))]>;
867 // (sub X, imm) gets canonicalized to (add X, -imm). Match this form.
868 def : ARMPat<(add GPR:$src, so_imm_neg:$imm),
869 (SUBri GPR:$src, so_imm_neg:$imm)>;
871 //def : ARMPat<(addc GPR:$src, so_imm_neg:$imm),
872 // (SUBSri GPR:$src, so_imm_neg:$imm)>;
873 //def : ARMPat<(adde GPR:$src, so_imm_neg:$imm),
874 // (SBCri GPR:$src, so_imm_neg:$imm)>;
876 // Note: These are implemented in C++ code, because they have to generate
877 // ADD/SUBrs instructions, which use a complex pattern that a xform function
879 // (mul X, 2^n+1) -> (add (X << n), X)
880 // (mul X, 2^n-1) -> (rsb X, (X << n))
883 //===----------------------------------------------------------------------===//
884 // Bitwise Instructions.
887 defm AND : AsI1_bin_irs<0b0000, "and",
888 BinOpFrag<(and node:$LHS, node:$RHS)>>;
889 defm ORR : AsI1_bin_irs<0b1100, "orr",
890 BinOpFrag<(or node:$LHS, node:$RHS)>>;
891 defm EOR : AsI1_bin_irs<0b0001, "eor",
892 BinOpFrag<(xor node:$LHS, node:$RHS)>>;
893 defm BIC : AsI1_bin_irs<0b1110, "bic",
894 BinOpFrag<(and node:$LHS, (not node:$RHS))>>;
896 def MVNr : AsI1<0b1111, (outs GPR:$dst), (ins GPR:$src), DPFrm,
897 "mvn", " $dst, $src",
898 [(set GPR:$dst, (not GPR:$src))]>, UnaryDP;
899 def MVNs : AsI1<0b1111, (outs GPR:$dst), (ins so_reg:$src), DPSoRegFrm,
900 "mvn", " $dst, $src",
901 [(set GPR:$dst, (not so_reg:$src))]>, UnaryDP;
902 let isReMaterializable = 1 in
903 def MVNi : AsI1<0b1111, (outs GPR:$dst), (ins so_imm:$imm), DPFrm,
904 "mvn", " $dst, $imm",
905 [(set GPR:$dst, so_imm_not:$imm)]>,UnaryDP;
907 def : ARMPat<(and GPR:$src, so_imm_not:$imm),
908 (BICri GPR:$src, so_imm_not:$imm)>;
910 //===----------------------------------------------------------------------===//
911 // Multiply Instructions.
914 def MUL : AsMul1I<0b0000000, (outs GPR:$dst), (ins GPR:$a, GPR:$b),
915 "mul", " $dst, $a, $b",
916 [(set GPR:$dst, (mul GPR:$a, GPR:$b))]>;
918 def MLA : AsMul1I<0b0000001, (outs GPR:$dst), (ins GPR:$a, GPR:$b, GPR:$c),
919 "mla", " $dst, $a, $b, $c",
920 [(set GPR:$dst, (add (mul GPR:$a, GPR:$b), GPR:$c))]>;
922 // Extra precision multiplies with low / high results
923 def SMULL : AsMul1I<0b0000110, (outs GPR:$ldst, GPR:$hdst),
924 (ins GPR:$a, GPR:$b),
925 "smull", " $ldst, $hdst, $a, $b", []>;
927 def UMULL : AsMul1I<0b0000100, (outs GPR:$ldst, GPR:$hdst),
928 (ins GPR:$a, GPR:$b),
929 "umull", " $ldst, $hdst, $a, $b", []>;
931 // Multiply + accumulate
932 def SMLAL : AsMul1I<0b0000111, (outs GPR:$ldst, GPR:$hdst),
933 (ins GPR:$a, GPR:$b),
934 "smlal", " $ldst, $hdst, $a, $b", []>;
936 def UMLAL : AsMul1I<0b0000101, (outs GPR:$ldst, GPR:$hdst),
937 (ins GPR:$a, GPR:$b),
938 "umlal", " $ldst, $hdst, $a, $b", []>;
940 def UMAAL : AMul1I <0b0000010, (outs GPR:$ldst, GPR:$hdst),
941 (ins GPR:$a, GPR:$b),
942 "umaal", " $ldst, $hdst, $a, $b", []>,
943 Requires<[IsARM, HasV6]>;
945 // Most significant word multiply
946 def SMMUL : AMul2I <0b0111010, (outs GPR:$dst), (ins GPR:$a, GPR:$b),
947 "smmul", " $dst, $a, $b",
948 [(set GPR:$dst, (mulhs GPR:$a, GPR:$b))]>,
949 Requires<[IsARM, HasV6]> {
950 let Inst{7-4} = 0b0001;
951 let Inst{15-12} = 0b1111;
954 def SMMLA : AMul2I <0b0111010, (outs GPR:$dst), (ins GPR:$a, GPR:$b, GPR:$c),
955 "smmla", " $dst, $a, $b, $c",
956 [(set GPR:$dst, (add (mulhs GPR:$a, GPR:$b), GPR:$c))]>,
957 Requires<[IsARM, HasV6]> {
958 let Inst{7-4} = 0b0001;
962 def SMMLS : AMul2I <0b0111010, (outs GPR:$dst), (ins GPR:$a, GPR:$b, GPR:$c),
963 "smmls", " $dst, $a, $b, $c",
964 [(set GPR:$dst, (sub GPR:$c, (mulhs GPR:$a, GPR:$b)))]>,
965 Requires<[IsARM, HasV6]> {
966 let Inst{7-4} = 0b1101;
969 multiclass AI_smul<string opc, PatFrag opnode> {
970 def BB : AMulxyI<0b0001011, (outs GPR:$dst), (ins GPR:$a, GPR:$b),
971 !strconcat(opc, "bb"), " $dst, $a, $b",
972 [(set GPR:$dst, (opnode (sext_inreg GPR:$a, i16),
973 (sext_inreg GPR:$b, i16)))]>,
974 Requires<[IsARM, HasV5TE]> {
979 def BT : AMulxyI<0b0001011, (outs GPR:$dst), (ins GPR:$a, GPR:$b),
980 !strconcat(opc, "bt"), " $dst, $a, $b",
981 [(set GPR:$dst, (opnode (sext_inreg GPR:$a, i16),
982 (sra GPR:$b, 16)))]>,
983 Requires<[IsARM, HasV5TE]> {
988 def TB : AMulxyI<0b0001011, (outs GPR:$dst), (ins GPR:$a, GPR:$b),
989 !strconcat(opc, "tb"), " $dst, $a, $b",
990 [(set GPR:$dst, (opnode (sra GPR:$a, 16),
991 (sext_inreg GPR:$b, i16)))]>,
992 Requires<[IsARM, HasV5TE]> {
997 def TT : AMulxyI<0b0001011, (outs GPR:$dst), (ins GPR:$a, GPR:$b),
998 !strconcat(opc, "tt"), " $dst, $a, $b",
999 [(set GPR:$dst, (opnode (sra GPR:$a, 16),
1000 (sra GPR:$b, 16)))]>,
1001 Requires<[IsARM, HasV5TE]> {
1006 def WB : AMulxyI<0b0001001, (outs GPR:$dst), (ins GPR:$a, GPR:$b),
1007 !strconcat(opc, "wb"), " $dst, $a, $b",
1008 [(set GPR:$dst, (sra (opnode GPR:$a,
1009 (sext_inreg GPR:$b, i16)), 16))]>,
1010 Requires<[IsARM, HasV5TE]> {
1015 def WT : AMulxyI<0b0001001, (outs GPR:$dst), (ins GPR:$a, GPR:$b),
1016 !strconcat(opc, "wt"), " $dst, $a, $b",
1017 [(set GPR:$dst, (sra (opnode GPR:$a,
1018 (sra GPR:$b, 16)), 16))]>,
1019 Requires<[IsARM, HasV5TE]> {
1026 multiclass AI_smla<string opc, PatFrag opnode> {
1027 def BB : AMulxyI<0b0001000, (outs GPR:$dst), (ins GPR:$a, GPR:$b, GPR:$acc),
1028 !strconcat(opc, "bb"), " $dst, $a, $b, $acc",
1029 [(set GPR:$dst, (add GPR:$acc,
1030 (opnode (sext_inreg GPR:$a, i16),
1031 (sext_inreg GPR:$b, i16))))]>,
1032 Requires<[IsARM, HasV5TE]> {
1037 def BT : AMulxyI<0b0001000, (outs GPR:$dst), (ins GPR:$a, GPR:$b, GPR:$acc),
1038 !strconcat(opc, "bt"), " $dst, $a, $b, $acc",
1039 [(set GPR:$dst, (add GPR:$acc, (opnode (sext_inreg GPR:$a, i16),
1040 (sra GPR:$b, 16))))]>,
1041 Requires<[IsARM, HasV5TE]> {
1046 def TB : AMulxyI<0b0001000, (outs GPR:$dst), (ins GPR:$a, GPR:$b, GPR:$acc),
1047 !strconcat(opc, "tb"), " $dst, $a, $b, $acc",
1048 [(set GPR:$dst, (add GPR:$acc, (opnode (sra GPR:$a, 16),
1049 (sext_inreg GPR:$b, i16))))]>,
1050 Requires<[IsARM, HasV5TE]> {
1055 def TT : AMulxyI<0b0001000, (outs GPR:$dst), (ins GPR:$a, GPR:$b, GPR:$acc),
1056 !strconcat(opc, "tt"), " $dst, $a, $b, $acc",
1057 [(set GPR:$dst, (add GPR:$acc, (opnode (sra GPR:$a, 16),
1058 (sra GPR:$b, 16))))]>,
1059 Requires<[IsARM, HasV5TE]> {
1064 def WB : AMulxyI<0b0001001, (outs GPR:$dst), (ins GPR:$a, GPR:$b, GPR:$acc),
1065 !strconcat(opc, "wb"), " $dst, $a, $b, $acc",
1066 [(set GPR:$dst, (add GPR:$acc, (sra (opnode GPR:$a,
1067 (sext_inreg GPR:$b, i16)), 16)))]>,
1068 Requires<[IsARM, HasV5TE]> {
1073 def WT : AMulxyI<0b0001001, (outs GPR:$dst), (ins GPR:$a, GPR:$b, GPR:$acc),
1074 !strconcat(opc, "wt"), " $dst, $a, $b, $acc",
1075 [(set GPR:$dst, (add GPR:$acc, (sra (opnode GPR:$a,
1076 (sra GPR:$b, 16)), 16)))]>,
1077 Requires<[IsARM, HasV5TE]> {
1083 defm SMUL : AI_smul<"smul", BinOpFrag<(mul node:$LHS, node:$RHS)>>;
1084 defm SMLA : AI_smla<"smla", BinOpFrag<(mul node:$LHS, node:$RHS)>>;
1086 // TODO: Halfword multiple accumulate long: SMLAL<x><y>
1087 // TODO: Dual halfword multiple: SMUAD, SMUSD, SMLAD, SMLSD, SMLALD, SMLSLD
1089 //===----------------------------------------------------------------------===//
1090 // Misc. Arithmetic Instructions.
1093 def CLZ : AI<(outs GPR:$dst), (ins GPR:$src), ArithMisc,
1094 "clz", " $dst, $src",
1095 [(set GPR:$dst, (ctlz GPR:$src))]>, Requires<[IsARM, HasV5T]>;
1097 def REV : AI<(outs GPR:$dst), (ins GPR:$src), ArithMisc,
1098 "rev", " $dst, $src",
1099 [(set GPR:$dst, (bswap GPR:$src))]>, Requires<[IsARM, HasV6]>;
1101 def REV16 : AI<(outs GPR:$dst), (ins GPR:$src), ArithMisc,
1102 "rev16", " $dst, $src",
1104 (or (and (srl GPR:$src, 8), 0xFF),
1105 (or (and (shl GPR:$src, 8), 0xFF00),
1106 (or (and (srl GPR:$src, 8), 0xFF0000),
1107 (and (shl GPR:$src, 8), 0xFF000000)))))]>,
1108 Requires<[IsARM, HasV6]>;
1110 def REVSH : AI<(outs GPR:$dst), (ins GPR:$src), ArithMisc,
1111 "revsh", " $dst, $src",
1114 (or (srl (and GPR:$src, 0xFF00), 8),
1115 (shl GPR:$src, 8)), i16))]>,
1116 Requires<[IsARM, HasV6]>;
1118 def PKHBT : AI<(outs GPR:$dst), (ins GPR:$src1, GPR:$src2, i32imm:$shamt),
1119 Pseudo, "pkhbt", " $dst, $src1, $src2, LSL $shamt",
1120 [(set GPR:$dst, (or (and GPR:$src1, 0xFFFF),
1121 (and (shl GPR:$src2, (i32 imm:$shamt)),
1123 Requires<[IsARM, HasV6]>;
1125 // Alternate cases for PKHBT where identities eliminate some nodes.
1126 def : ARMV6Pat<(or (and GPR:$src1, 0xFFFF), (and GPR:$src2, 0xFFFF0000)),
1127 (PKHBT GPR:$src1, GPR:$src2, 0)>;
1128 def : ARMV6Pat<(or (and GPR:$src1, 0xFFFF), (shl GPR:$src2, imm16_31:$shamt)),
1129 (PKHBT GPR:$src1, GPR:$src2, imm16_31:$shamt)>;
1132 def PKHTB : AI<(outs GPR:$dst), (ins GPR:$src1, GPR:$src2, i32imm:$shamt),
1133 Pseudo, "pkhtb", " $dst, $src1, $src2, ASR $shamt",
1134 [(set GPR:$dst, (or (and GPR:$src1, 0xFFFF0000),
1135 (and (sra GPR:$src2, imm16_31:$shamt),
1136 0xFFFF)))]>, Requires<[IsARM, HasV6]>;
1138 // Alternate cases for PKHTB where identities eliminate some nodes. Note that
1139 // a shift amount of 0 is *not legal* here, it is PKHBT instead.
1140 def : ARMV6Pat<(or (and GPR:$src1, 0xFFFF0000), (srl GPR:$src2, 16)),
1141 (PKHTB GPR:$src1, GPR:$src2, 16)>;
1142 def : ARMV6Pat<(or (and GPR:$src1, 0xFFFF0000),
1143 (and (srl GPR:$src2, imm1_15:$shamt), 0xFFFF)),
1144 (PKHTB GPR:$src1, GPR:$src2, imm1_15:$shamt)>;
1146 //===----------------------------------------------------------------------===//
1147 // Comparison Instructions...
1150 defm CMP : AI1_cmp_irs<0b1010, "cmp",
1151 BinOpFrag<(ARMcmp node:$LHS, node:$RHS)>>;
1152 defm CMN : AI1_cmp_irs<0b1011, "cmn",
1153 BinOpFrag<(ARMcmp node:$LHS,(ineg node:$RHS))>>;
1155 // Note that TST/TEQ don't set all the same flags that CMP does!
1156 defm TST : AI1_cmp_irs<0b1000, "tst",
1157 BinOpFrag<(ARMcmpNZ (and node:$LHS, node:$RHS), 0)>>;
1158 defm TEQ : AI1_cmp_irs<0b1001, "teq",
1159 BinOpFrag<(ARMcmpNZ (xor node:$LHS, node:$RHS), 0)>>;
1161 defm CMPnz : AI1_cmp_irs<0b1010, "cmp",
1162 BinOpFrag<(ARMcmpNZ node:$LHS, node:$RHS)>>;
1163 defm CMNnz : AI1_cmp_irs<0b1011, "cmn",
1164 BinOpFrag<(ARMcmpNZ node:$LHS,(ineg node:$RHS))>>;
1166 def : ARMPat<(ARMcmp GPR:$src, so_imm_neg:$imm),
1167 (CMNri GPR:$src, so_imm_neg:$imm)>;
1169 def : ARMPat<(ARMcmpNZ GPR:$src, so_imm_neg:$imm),
1170 (CMNri GPR:$src, so_imm_neg:$imm)>;
1173 // Conditional moves
1174 // FIXME: should be able to write a pattern for ARMcmov, but can't use
1175 // a two-value operand where a dag node expects two operands. :(
1176 def MOVCCr : AI1<0b1101, (outs GPR:$dst), (ins GPR:$false, GPR:$true), DPFrm,
1177 "mov", " $dst, $true",
1178 [/*(set GPR:$dst, (ARMcmov GPR:$false, GPR:$true, imm:$cc, CCR:$ccr))*/]>,
1179 RegConstraint<"$false = $dst">, UnaryDP;
1181 def MOVCCs : AI1<0b1101, (outs GPR:$dst),
1182 (ins GPR:$false, so_reg:$true), DPSoRegFrm,
1183 "mov", " $dst, $true",
1184 [/*(set GPR:$dst, (ARMcmov GPR:$false, so_reg:$true, imm:$cc, CCR:$ccr))*/]>,
1185 RegConstraint<"$false = $dst">, UnaryDP;
1187 def MOVCCi : AI1<0b1101, (outs GPR:$dst),
1188 (ins GPR:$false, so_imm:$true), DPFrm,
1189 "mov", " $dst, $true",
1190 [/*(set GPR:$dst, (ARMcmov GPR:$false, so_imm:$true, imm:$cc, CCR:$ccr))*/]>,
1191 RegConstraint<"$false = $dst">, UnaryDP;
1194 // LEApcrel - Load a pc-relative address into a register without offending the
1196 def LEApcrel : AXI1<0x0, (outs GPR:$dst), (ins i32imm:$label, pred:$p), Pseudo,
1197 !strconcat(!strconcat(".set PCRELV${:uid}, ($label-(",
1198 "${:private}PCRELL${:uid}+8))\n"),
1199 !strconcat("${:private}PCRELL${:uid}:\n\t",
1200 "add$p $dst, pc, #PCRELV${:uid}")),
1203 def LEApcrelJT : AXI1<0x0, (outs GPR:$dst), (ins i32imm:$label, i32imm:$id, pred:$p),
1205 !strconcat(!strconcat(".set PCRELV${:uid}, (${label}_${id:no_hash}-(",
1206 "${:private}PCRELL${:uid}+8))\n"),
1207 !strconcat("${:private}PCRELL${:uid}:\n\t",
1208 "add$p $dst, pc, #PCRELV${:uid}")),
1211 //===----------------------------------------------------------------------===//
1215 // __aeabi_read_tp preserves the registers r1-r3.
1217 Defs = [R0, R12, LR, CPSR] in {
1218 def TPsoft : ABXI<0b1011, (outs), (ins),
1219 "bl __aeabi_read_tp",
1220 [(set R0, ARMthread_pointer)]>;
1223 //===----------------------------------------------------------------------===//
1224 // Non-Instruction Patterns
1227 // ConstantPool, GlobalAddress, and JumpTable
1228 def : ARMPat<(ARMWrapper tglobaladdr :$dst), (LEApcrel tglobaladdr :$dst)>;
1229 def : ARMPat<(ARMWrapper tconstpool :$dst), (LEApcrel tconstpool :$dst)>;
1230 def : ARMPat<(ARMWrapperJT tjumptable:$dst, imm:$id),
1231 (LEApcrelJT tjumptable:$dst, imm:$id)>;
1233 // Large immediate handling.
1235 // Two piece so_imms.
1236 let isReMaterializable = 1 in
1237 def MOVi2pieces : AI1x2<(outs GPR:$dst), (ins so_imm2part:$src), Pseudo,
1238 "mov", " $dst, $src",
1239 [(set GPR:$dst, so_imm2part:$src)]>;
1241 def : ARMPat<(or GPR:$LHS, so_imm2part:$RHS),
1242 (ORRri (ORRri GPR:$LHS, (so_imm2part_1 imm:$RHS)),
1243 (so_imm2part_2 imm:$RHS))>;
1244 def : ARMPat<(xor GPR:$LHS, so_imm2part:$RHS),
1245 (EORri (EORri GPR:$LHS, (so_imm2part_1 imm:$RHS)),
1246 (so_imm2part_2 imm:$RHS))>;
1248 // TODO: add,sub,and, 3-instr forms?
1252 def : ARMPat<(ARMcall texternalsym:$func), (BL texternalsym:$func)>;
1254 // zextload i1 -> zextload i8
1255 def : ARMPat<(zextloadi1 addrmode2:$addr), (LDRB addrmode2:$addr)>;
1257 // extload -> zextload
1258 def : ARMPat<(extloadi1 addrmode2:$addr), (LDRB addrmode2:$addr)>;
1259 def : ARMPat<(extloadi8 addrmode2:$addr), (LDRB addrmode2:$addr)>;
1260 def : ARMPat<(extloadi16 addrmode3:$addr), (LDRH addrmode3:$addr)>;
1262 def : ARMPat<(extloadi8 addrmodepc:$addr), (PICLDRB addrmodepc:$addr)>;
1263 def : ARMPat<(extloadi16 addrmodepc:$addr), (PICLDRH addrmodepc:$addr)>;
1266 def : ARMV5TEPat<(mul (sra (shl GPR:$a, 16), 16), (sra (shl GPR:$b, 16), 16)),
1267 (SMULBB GPR:$a, GPR:$b)>;
1268 def : ARMV5TEPat<(mul sext_16_node:$a, sext_16_node:$b),
1269 (SMULBB GPR:$a, GPR:$b)>;
1270 def : ARMV5TEPat<(mul (sra (shl GPR:$a, 16), 16), (sra GPR:$b, 16)),
1271 (SMULBT GPR:$a, GPR:$b)>;
1272 def : ARMV5TEPat<(mul sext_16_node:$a, (sra GPR:$b, 16)),
1273 (SMULBT GPR:$a, GPR:$b)>;
1274 def : ARMV5TEPat<(mul (sra GPR:$a, 16), (sra (shl GPR:$b, 16), 16)),
1275 (SMULTB GPR:$a, GPR:$b)>;
1276 def : ARMV5TEPat<(mul (sra GPR:$a, 16), sext_16_node:$b),
1277 (SMULTB GPR:$a, GPR:$b)>;
1278 def : ARMV5TEPat<(sra (mul GPR:$a, (sra (shl GPR:$b, 16), 16)), 16),
1279 (SMULWB GPR:$a, GPR:$b)>;
1280 def : ARMV5TEPat<(sra (mul GPR:$a, sext_16_node:$b), 16),
1281 (SMULWB GPR:$a, GPR:$b)>;
1283 def : ARMV5TEPat<(add GPR:$acc,
1284 (mul (sra (shl GPR:$a, 16), 16),
1285 (sra (shl GPR:$b, 16), 16))),
1286 (SMLABB GPR:$a, GPR:$b, GPR:$acc)>;
1287 def : ARMV5TEPat<(add GPR:$acc,
1288 (mul sext_16_node:$a, sext_16_node:$b)),
1289 (SMLABB GPR:$a, GPR:$b, GPR:$acc)>;
1290 def : ARMV5TEPat<(add GPR:$acc,
1291 (mul (sra (shl GPR:$a, 16), 16), (sra GPR:$b, 16))),
1292 (SMLABT GPR:$a, GPR:$b, GPR:$acc)>;
1293 def : ARMV5TEPat<(add GPR:$acc,
1294 (mul sext_16_node:$a, (sra GPR:$b, 16))),
1295 (SMLABT GPR:$a, GPR:$b, GPR:$acc)>;
1296 def : ARMV5TEPat<(add GPR:$acc,
1297 (mul (sra GPR:$a, 16), (sra (shl GPR:$b, 16), 16))),
1298 (SMLATB GPR:$a, GPR:$b, GPR:$acc)>;
1299 def : ARMV5TEPat<(add GPR:$acc,
1300 (mul (sra GPR:$a, 16), sext_16_node:$b)),
1301 (SMLATB GPR:$a, GPR:$b, GPR:$acc)>;
1302 def : ARMV5TEPat<(add GPR:$acc,
1303 (sra (mul GPR:$a, (sra (shl GPR:$b, 16), 16)), 16)),
1304 (SMLAWB GPR:$a, GPR:$b, GPR:$acc)>;
1305 def : ARMV5TEPat<(add GPR:$acc,
1306 (sra (mul GPR:$a, sext_16_node:$b), 16)),
1307 (SMLAWB GPR:$a, GPR:$b, GPR:$acc)>;
1309 //===----------------------------------------------------------------------===//
1313 include "ARMInstrThumb.td"
1315 //===----------------------------------------------------------------------===//
1316 // Floating Point Support
1319 include "ARMInstrVFP.td"