1 //===- ARMInstrInfo.td - Target Description for ARM Target -*- tablegen -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file describes the ARM instructions in TableGen format.
12 //===----------------------------------------------------------------------===//
14 //===----------------------------------------------------------------------===//
15 // ARM specific DAG Nodes.
19 def SDT_ARMCallSeqStart : SDCallSeqStart<[ SDTCisVT<0, i32> ]>;
20 def SDT_ARMCallSeqEnd : SDCallSeqEnd<[ SDTCisVT<0, i32>, SDTCisVT<1, i32> ]>;
21 def SDT_ARMStructByVal : SDTypeProfile<0, 4,
22 [SDTCisVT<0, i32>, SDTCisVT<1, i32>,
23 SDTCisVT<2, i32>, SDTCisVT<3, i32>]>;
25 def SDT_ARMSaveCallPC : SDTypeProfile<0, 1, []>;
27 def SDT_ARMcall : SDTypeProfile<0, -1, [SDTCisPtrTy<0>]>;
29 def SDT_ARMCMov : SDTypeProfile<1, 3,
30 [SDTCisSameAs<0, 1>, SDTCisSameAs<0, 2>,
33 def SDT_ARMBrcond : SDTypeProfile<0, 2,
34 [SDTCisVT<0, OtherVT>, SDTCisVT<1, i32>]>;
36 def SDT_ARMBrJT : SDTypeProfile<0, 3,
37 [SDTCisPtrTy<0>, SDTCisVT<1, i32>,
40 def SDT_ARMBr2JT : SDTypeProfile<0, 4,
41 [SDTCisPtrTy<0>, SDTCisVT<1, i32>,
42 SDTCisVT<2, i32>, SDTCisVT<3, i32>]>;
44 def SDT_ARMBCC_i64 : SDTypeProfile<0, 6,
46 SDTCisVT<1, i32>, SDTCisVT<2, i32>,
47 SDTCisVT<3, i32>, SDTCisVT<4, i32>,
48 SDTCisVT<5, OtherVT>]>;
50 def SDT_ARMAnd : SDTypeProfile<1, 2,
51 [SDTCisVT<0, i32>, SDTCisVT<1, i32>,
54 def SDT_ARMCmp : SDTypeProfile<0, 2, [SDTCisSameAs<0, 1>]>;
56 def SDT_ARMPICAdd : SDTypeProfile<1, 2, [SDTCisSameAs<0, 1>,
57 SDTCisPtrTy<1>, SDTCisVT<2, i32>]>;
59 def SDT_ARMThreadPointer : SDTypeProfile<1, 0, [SDTCisPtrTy<0>]>;
60 def SDT_ARMEH_SJLJ_Setjmp : SDTypeProfile<1, 2, [SDTCisInt<0>, SDTCisPtrTy<1>,
62 def SDT_ARMEH_SJLJ_Longjmp: SDTypeProfile<0, 2, [SDTCisPtrTy<0>, SDTCisInt<1>]>;
64 def SDT_ARMMEMBARRIER : SDTypeProfile<0, 1, [SDTCisInt<0>]>;
66 def SDT_ARMPREFETCH : SDTypeProfile<0, 3, [SDTCisPtrTy<0>, SDTCisSameAs<1, 2>,
69 def SDT_ARMTCRET : SDTypeProfile<0, 1, [SDTCisPtrTy<0>]>;
71 def SDT_ARMBFI : SDTypeProfile<1, 3, [SDTCisVT<0, i32>, SDTCisVT<1, i32>,
72 SDTCisVT<2, i32>, SDTCisVT<3, i32>]>;
74 def SDT_ARMVMAXNM : SDTypeProfile<1, 2, [SDTCisFP<0>, SDTCisFP<1>, SDTCisFP<2>]>;
75 def SDT_ARMVMINNM : SDTypeProfile<1, 2, [SDTCisFP<0>, SDTCisFP<1>, SDTCisFP<2>]>;
77 def SDTBinaryArithWithFlags : SDTypeProfile<2, 2,
80 SDTCisInt<0>, SDTCisVT<1, i32>]>;
82 // SDTBinaryArithWithFlagsInOut - RES1, CPSR = op LHS, RHS, CPSR
83 def SDTBinaryArithWithFlagsInOut : SDTypeProfile<2, 3,
90 def SDT_ARM64bitmlal : SDTypeProfile<2,4, [ SDTCisVT<0, i32>, SDTCisVT<1, i32>,
91 SDTCisVT<2, i32>, SDTCisVT<3, i32>,
92 SDTCisVT<4, i32>, SDTCisVT<5, i32> ] >;
93 def ARMUmlal : SDNode<"ARMISD::UMLAL", SDT_ARM64bitmlal>;
94 def ARMSmlal : SDNode<"ARMISD::SMLAL", SDT_ARM64bitmlal>;
97 def ARMWrapper : SDNode<"ARMISD::Wrapper", SDTIntUnaryOp>;
98 def ARMWrapperPIC : SDNode<"ARMISD::WrapperPIC", SDTIntUnaryOp>;
99 def ARMWrapperJT : SDNode<"ARMISD::WrapperJT", SDTIntBinOp>;
101 def ARMcallseq_start : SDNode<"ISD::CALLSEQ_START", SDT_ARMCallSeqStart,
102 [SDNPHasChain, SDNPSideEffect, SDNPOutGlue]>;
103 def ARMcallseq_end : SDNode<"ISD::CALLSEQ_END", SDT_ARMCallSeqEnd,
104 [SDNPHasChain, SDNPSideEffect,
105 SDNPOptInGlue, SDNPOutGlue]>;
106 def ARMcopystructbyval : SDNode<"ARMISD::COPY_STRUCT_BYVAL" ,
108 [SDNPHasChain, SDNPInGlue, SDNPOutGlue,
109 SDNPMayStore, SDNPMayLoad]>;
111 def ARMcall : SDNode<"ARMISD::CALL", SDT_ARMcall,
112 [SDNPHasChain, SDNPOptInGlue, SDNPOutGlue,
114 def ARMcall_pred : SDNode<"ARMISD::CALL_PRED", SDT_ARMcall,
115 [SDNPHasChain, SDNPOptInGlue, SDNPOutGlue,
117 def ARMcall_nolink : SDNode<"ARMISD::CALL_NOLINK", SDT_ARMcall,
118 [SDNPHasChain, SDNPOptInGlue, SDNPOutGlue,
121 def ARMretflag : SDNode<"ARMISD::RET_FLAG", SDTNone,
122 [SDNPHasChain, SDNPOptInGlue, SDNPVariadic]>;
123 def ARMintretflag : SDNode<"ARMISD::INTRET_FLAG", SDT_ARMcall,
124 [SDNPHasChain, SDNPOptInGlue, SDNPVariadic]>;
125 def ARMcmov : SDNode<"ARMISD::CMOV", SDT_ARMCMov,
128 def ARMbrcond : SDNode<"ARMISD::BRCOND", SDT_ARMBrcond,
129 [SDNPHasChain, SDNPInGlue, SDNPOutGlue]>;
131 def ARMbrjt : SDNode<"ARMISD::BR_JT", SDT_ARMBrJT,
133 def ARMbr2jt : SDNode<"ARMISD::BR2_JT", SDT_ARMBr2JT,
136 def ARMBcci64 : SDNode<"ARMISD::BCC_i64", SDT_ARMBCC_i64,
139 def ARMcmp : SDNode<"ARMISD::CMP", SDT_ARMCmp,
142 def ARMcmn : SDNode<"ARMISD::CMN", SDT_ARMCmp,
145 def ARMcmpZ : SDNode<"ARMISD::CMPZ", SDT_ARMCmp,
146 [SDNPOutGlue, SDNPCommutative]>;
148 def ARMpic_add : SDNode<"ARMISD::PIC_ADD", SDT_ARMPICAdd>;
150 def ARMsrl_flag : SDNode<"ARMISD::SRL_FLAG", SDTIntUnaryOp, [SDNPOutGlue]>;
151 def ARMsra_flag : SDNode<"ARMISD::SRA_FLAG", SDTIntUnaryOp, [SDNPOutGlue]>;
152 def ARMrrx : SDNode<"ARMISD::RRX" , SDTIntUnaryOp, [SDNPInGlue ]>;
154 def ARMaddc : SDNode<"ARMISD::ADDC", SDTBinaryArithWithFlags,
156 def ARMsubc : SDNode<"ARMISD::SUBC", SDTBinaryArithWithFlags>;
157 def ARMadde : SDNode<"ARMISD::ADDE", SDTBinaryArithWithFlagsInOut>;
158 def ARMsube : SDNode<"ARMISD::SUBE", SDTBinaryArithWithFlagsInOut>;
160 def ARMthread_pointer: SDNode<"ARMISD::THREAD_POINTER", SDT_ARMThreadPointer>;
161 def ARMeh_sjlj_setjmp: SDNode<"ARMISD::EH_SJLJ_SETJMP",
162 SDT_ARMEH_SJLJ_Setjmp,
163 [SDNPHasChain, SDNPSideEffect]>;
164 def ARMeh_sjlj_longjmp: SDNode<"ARMISD::EH_SJLJ_LONGJMP",
165 SDT_ARMEH_SJLJ_Longjmp,
166 [SDNPHasChain, SDNPSideEffect]>;
168 def ARMMemBarrierMCR : SDNode<"ARMISD::MEMBARRIER_MCR", SDT_ARMMEMBARRIER,
169 [SDNPHasChain, SDNPSideEffect]>;
170 def ARMPreload : SDNode<"ARMISD::PRELOAD", SDT_ARMPREFETCH,
171 [SDNPHasChain, SDNPMayLoad, SDNPMayStore]>;
173 def ARMrbit : SDNode<"ARMISD::RBIT", SDTIntUnaryOp>;
175 def ARMtcret : SDNode<"ARMISD::TC_RETURN", SDT_ARMTCRET,
176 [SDNPHasChain, SDNPOptInGlue, SDNPVariadic]>;
178 def ARMbfi : SDNode<"ARMISD::BFI", SDT_ARMBFI>;
180 def ARMvmaxnm : SDNode<"ARMISD::VMAXNM", SDT_ARMVMAXNM, []>;
181 def ARMvminnm : SDNode<"ARMISD::VMINNM", SDT_ARMVMINNM, []>;
183 //===----------------------------------------------------------------------===//
184 // ARM Instruction Predicate Definitions.
186 def HasV4T : Predicate<"Subtarget->hasV4TOps()">,
187 AssemblerPredicate<"HasV4TOps", "armv4t">;
188 def NoV4T : Predicate<"!Subtarget->hasV4TOps()">;
189 def HasV5T : Predicate<"Subtarget->hasV5TOps()">,
190 AssemblerPredicate<"HasV5TOps", "armv5t">;
191 def HasV5TE : Predicate<"Subtarget->hasV5TEOps()">,
192 AssemblerPredicate<"HasV5TEOps", "armv5te">;
193 def HasV6 : Predicate<"Subtarget->hasV6Ops()">,
194 AssemblerPredicate<"HasV6Ops", "armv6">;
195 def NoV6 : Predicate<"!Subtarget->hasV6Ops()">;
196 def HasV6M : Predicate<"Subtarget->hasV6MOps()">,
197 AssemblerPredicate<"HasV6MOps",
198 "armv6m or armv6t2">;
199 def HasV6T2 : Predicate<"Subtarget->hasV6T2Ops()">,
200 AssemblerPredicate<"HasV6T2Ops", "armv6t2">;
201 def NoV6T2 : Predicate<"!Subtarget->hasV6T2Ops()">;
202 def HasV7 : Predicate<"Subtarget->hasV7Ops()">,
203 AssemblerPredicate<"HasV7Ops", "armv7">;
204 def HasV8 : Predicate<"Subtarget->hasV8Ops()">,
205 AssemblerPredicate<"HasV8Ops", "armv8">;
206 def PreV8 : Predicate<"!Subtarget->hasV8Ops()">,
207 AssemblerPredicate<"!HasV8Ops", "armv7 or earlier">;
208 def NoVFP : Predicate<"!Subtarget->hasVFP2()">;
209 def HasVFP2 : Predicate<"Subtarget->hasVFP2()">,
210 AssemblerPredicate<"FeatureVFP2", "VFP2">;
211 def HasVFP3 : Predicate<"Subtarget->hasVFP3()">,
212 AssemblerPredicate<"FeatureVFP3", "VFP3">;
213 def HasVFP4 : Predicate<"Subtarget->hasVFP4()">,
214 AssemblerPredicate<"FeatureVFP4", "VFP4">;
215 def HasDPVFP : Predicate<"!Subtarget->isFPOnlySP()">,
216 AssemblerPredicate<"!FeatureVFPOnlySP",
217 "double precision VFP">;
218 def HasFPARMv8 : Predicate<"Subtarget->hasFPARMv8()">,
219 AssemblerPredicate<"FeatureFPARMv8", "FPARMv8">;
220 def HasNEON : Predicate<"Subtarget->hasNEON()">,
221 AssemblerPredicate<"FeatureNEON", "NEON">;
222 def HasCrypto : Predicate<"Subtarget->hasCrypto()">,
223 AssemblerPredicate<"FeatureCrypto", "crypto">;
224 def HasCRC : Predicate<"Subtarget->hasCRC()">,
225 AssemblerPredicate<"FeatureCRC", "crc">;
226 def HasFP16 : Predicate<"Subtarget->hasFP16()">,
227 AssemblerPredicate<"FeatureFP16","half-float">;
228 def HasDivide : Predicate<"Subtarget->hasDivide()">,
229 AssemblerPredicate<"FeatureHWDiv", "divide in THUMB">;
230 def HasDivideInARM : Predicate<"Subtarget->hasDivideInARMMode()">,
231 AssemblerPredicate<"FeatureHWDivARM", "divide in ARM">;
232 def HasT2ExtractPack : Predicate<"Subtarget->hasT2ExtractPack()">,
233 AssemblerPredicate<"FeatureT2XtPk",
235 def HasThumb2DSP : Predicate<"Subtarget->hasThumb2DSP()">,
236 AssemblerPredicate<"FeatureDSPThumb2",
238 def HasDB : Predicate<"Subtarget->hasDataBarrier()">,
239 AssemblerPredicate<"FeatureDB",
241 def HasMP : Predicate<"Subtarget->hasMPExtension()">,
242 AssemblerPredicate<"FeatureMP",
244 def HasTrustZone : Predicate<"Subtarget->hasTrustZone()">,
245 AssemblerPredicate<"FeatureTrustZone",
247 def HasZCZ : Predicate<"Subtarget->hasZeroCycleZeroing()">;
248 def UseNEONForFP : Predicate<"Subtarget->useNEONForSinglePrecisionFP()">;
249 def DontUseNEONForFP : Predicate<"!Subtarget->useNEONForSinglePrecisionFP()">;
250 def IsThumb : Predicate<"Subtarget->isThumb()">,
251 AssemblerPredicate<"ModeThumb", "thumb">;
252 def IsThumb1Only : Predicate<"Subtarget->isThumb1Only()">;
253 def IsThumb2 : Predicate<"Subtarget->isThumb2()">,
254 AssemblerPredicate<"ModeThumb,FeatureThumb2",
256 def IsMClass : Predicate<"Subtarget->isMClass()">,
257 AssemblerPredicate<"FeatureMClass", "armv*m">;
258 def IsNotMClass : Predicate<"!Subtarget->isMClass()">,
259 AssemblerPredicate<"!FeatureMClass",
261 def IsARM : Predicate<"!Subtarget->isThumb()">,
262 AssemblerPredicate<"!ModeThumb", "arm-mode">;
263 def IsIOS : Predicate<"Subtarget->isTargetIOS()">;
264 def IsNotIOS : Predicate<"!Subtarget->isTargetIOS()">;
265 def IsMachO : Predicate<"Subtarget->isTargetMachO()">;
266 def IsNotMachO : Predicate<"!Subtarget->isTargetMachO()">;
267 def IsNaCl : Predicate<"Subtarget->isTargetNaCl()">;
268 def UseNaClTrap : Predicate<"Subtarget->useNaClTrap()">,
269 AssemblerPredicate<"FeatureNaClTrap", "NaCl">;
270 def DontUseNaClTrap : Predicate<"!Subtarget->useNaClTrap()">;
272 // FIXME: Eventually this will be just "hasV6T2Ops".
273 def UseMovt : Predicate<"Subtarget->useMovt()">;
274 def DontUseMovt : Predicate<"!Subtarget->useMovt()">;
275 def UseFPVMLx : Predicate<"Subtarget->useFPVMLx()">;
276 def UseMulOps : Predicate<"Subtarget->useMulOps()">;
278 // Prefer fused MAC for fp mul + add over fp VMLA / VMLS if they are available.
279 // But only select them if more precision in FP computation is allowed.
280 // Do not use them for Darwin platforms.
281 def UseFusedMAC : Predicate<"(TM.Options.AllowFPOpFusion =="
282 " FPOpFusion::Fast && "
283 " Subtarget->hasVFP4()) && "
284 "!Subtarget->isTargetDarwin()">;
285 def DontUseFusedMAC : Predicate<"!(TM.Options.AllowFPOpFusion =="
286 " FPOpFusion::Fast &&"
287 " Subtarget->hasVFP4()) || "
288 "Subtarget->isTargetDarwin()">;
290 // VGETLNi32 is microcoded on Swift - prefer VMOV.
291 def HasFastVGETLNi32 : Predicate<"!Subtarget->isSwift()">;
292 def HasSlowVGETLNi32 : Predicate<"Subtarget->isSwift()">;
294 // VDUP.32 is microcoded on Swift - prefer VMOV.
295 def HasFastVDUP32 : Predicate<"!Subtarget->isSwift()">;
296 def HasSlowVDUP32 : Predicate<"Subtarget->isSwift()">;
298 // Cortex-A9 prefers VMOVSR to VMOVDRR even when using NEON for scalar FP, as
299 // this allows more effective execution domain optimization. See
300 // setExecutionDomain().
301 def UseVMOVSR : Predicate<"Subtarget->isCortexA9() || !Subtarget->useNEONForSinglePrecisionFP()">;
302 def DontUseVMOVSR : Predicate<"!Subtarget->isCortexA9() && Subtarget->useNEONForSinglePrecisionFP()">;
304 def IsLE : Predicate<"getTargetLowering()->isLittleEndian()">;
305 def IsBE : Predicate<"getTargetLowering()->isBigEndian()">;
307 //===----------------------------------------------------------------------===//
308 // ARM Flag Definitions.
310 class RegConstraint<string C> {
311 string Constraints = C;
314 //===----------------------------------------------------------------------===//
315 // ARM specific transformation functions and pattern fragments.
318 // imm_neg_XFORM - Return the negation of an i32 immediate value.
319 def imm_neg_XFORM : SDNodeXForm<imm, [{
320 return CurDAG->getTargetConstant(-(int)N->getZExtValue(), MVT::i32);
323 // imm_not_XFORM - Return the complement of a i32 immediate value.
324 def imm_not_XFORM : SDNodeXForm<imm, [{
325 return CurDAG->getTargetConstant(~(int)N->getZExtValue(), MVT::i32);
328 /// imm16_31 predicate - True if the 32-bit immediate is in the range [16,31].
329 def imm16_31 : ImmLeaf<i32, [{
330 return (int32_t)Imm >= 16 && (int32_t)Imm < 32;
333 def so_imm_neg_asmoperand : AsmOperandClass { let Name = "ARMSOImmNeg"; }
334 def so_imm_neg : Operand<i32>, PatLeaf<(imm), [{
335 unsigned Value = -(unsigned)N->getZExtValue();
336 return Value && ARM_AM::getSOImmVal(Value) != -1;
338 let ParserMatchClass = so_imm_neg_asmoperand;
341 // Note: this pattern doesn't require an encoder method and such, as it's
342 // only used on aliases (Pat<> and InstAlias<>). The actual encoding
343 // is handled by the destination instructions, which use so_imm.
344 def so_imm_not_asmoperand : AsmOperandClass { let Name = "ARMSOImmNot"; }
345 def so_imm_not : Operand<i32>, PatLeaf<(imm), [{
346 return ARM_AM::getSOImmVal(~(uint32_t)N->getZExtValue()) != -1;
348 let ParserMatchClass = so_imm_not_asmoperand;
351 // sext_16_node predicate - True if the SDNode is sign-extended 16 or more bits.
352 def sext_16_node : PatLeaf<(i32 GPR:$a), [{
353 return CurDAG->ComputeNumSignBits(SDValue(N,0)) >= 17;
356 /// Split a 32-bit immediate into two 16 bit parts.
357 def hi16 : SDNodeXForm<imm, [{
358 return CurDAG->getTargetConstant((uint32_t)N->getZExtValue() >> 16, MVT::i32);
361 def lo16AllZero : PatLeaf<(i32 imm), [{
362 // Returns true if all low 16-bits are 0.
363 return (((uint32_t)N->getZExtValue()) & 0xFFFFUL) == 0;
366 class BinOpWithFlagFrag<dag res> :
367 PatFrag<(ops node:$LHS, node:$RHS, node:$FLAG), res>;
368 class BinOpFrag<dag res> : PatFrag<(ops node:$LHS, node:$RHS), res>;
369 class UnOpFrag <dag res> : PatFrag<(ops node:$Src), res>;
371 // An 'and' node with a single use.
372 def and_su : PatFrag<(ops node:$lhs, node:$rhs), (and node:$lhs, node:$rhs), [{
373 return N->hasOneUse();
376 // An 'xor' node with a single use.
377 def xor_su : PatFrag<(ops node:$lhs, node:$rhs), (xor node:$lhs, node:$rhs), [{
378 return N->hasOneUse();
381 // An 'fmul' node with a single use.
382 def fmul_su : PatFrag<(ops node:$lhs, node:$rhs), (fmul node:$lhs, node:$rhs),[{
383 return N->hasOneUse();
386 // An 'fadd' node which checks for single non-hazardous use.
387 def fadd_mlx : PatFrag<(ops node:$lhs, node:$rhs),(fadd node:$lhs, node:$rhs),[{
388 return hasNoVMLxHazardUse(N);
391 // An 'fsub' node which checks for single non-hazardous use.
392 def fsub_mlx : PatFrag<(ops node:$lhs, node:$rhs),(fsub node:$lhs, node:$rhs),[{
393 return hasNoVMLxHazardUse(N);
396 //===----------------------------------------------------------------------===//
397 // Operand Definitions.
400 // Immediate operands with a shared generic asm render method.
401 class ImmAsmOperand : AsmOperandClass { let RenderMethod = "addImmOperands"; }
404 // FIXME: rename brtarget to t2_brtarget
405 def brtarget : Operand<OtherVT> {
406 let EncoderMethod = "getBranchTargetOpValue";
407 let OperandType = "OPERAND_PCREL";
408 let DecoderMethod = "DecodeT2BROperand";
411 // FIXME: get rid of this one?
412 def uncondbrtarget : Operand<OtherVT> {
413 let EncoderMethod = "getUnconditionalBranchTargetOpValue";
414 let OperandType = "OPERAND_PCREL";
417 // Branch target for ARM. Handles conditional/unconditional
418 def br_target : Operand<OtherVT> {
419 let EncoderMethod = "getARMBranchTargetOpValue";
420 let OperandType = "OPERAND_PCREL";
424 // FIXME: rename bltarget to t2_bl_target?
425 def bltarget : Operand<i32> {
426 // Encoded the same as branch targets.
427 let EncoderMethod = "getBranchTargetOpValue";
428 let OperandType = "OPERAND_PCREL";
431 // Call target for ARM. Handles conditional/unconditional
432 // FIXME: rename bl_target to t2_bltarget?
433 def bl_target : Operand<i32> {
434 let EncoderMethod = "getARMBLTargetOpValue";
435 let OperandType = "OPERAND_PCREL";
438 def blx_target : Operand<i32> {
439 let EncoderMethod = "getARMBLXTargetOpValue";
440 let OperandType = "OPERAND_PCREL";
443 // A list of registers separated by comma. Used by load/store multiple.
444 def RegListAsmOperand : AsmOperandClass { let Name = "RegList"; }
445 def reglist : Operand<i32> {
446 let EncoderMethod = "getRegisterListOpValue";
447 let ParserMatchClass = RegListAsmOperand;
448 let PrintMethod = "printRegisterList";
449 let DecoderMethod = "DecodeRegListOperand";
452 def GPRPairOp : RegisterOperand<GPRPair, "printGPRPairOperand">;
454 def DPRRegListAsmOperand : AsmOperandClass { let Name = "DPRRegList"; }
455 def dpr_reglist : Operand<i32> {
456 let EncoderMethod = "getRegisterListOpValue";
457 let ParserMatchClass = DPRRegListAsmOperand;
458 let PrintMethod = "printRegisterList";
459 let DecoderMethod = "DecodeDPRRegListOperand";
462 def SPRRegListAsmOperand : AsmOperandClass { let Name = "SPRRegList"; }
463 def spr_reglist : Operand<i32> {
464 let EncoderMethod = "getRegisterListOpValue";
465 let ParserMatchClass = SPRRegListAsmOperand;
466 let PrintMethod = "printRegisterList";
467 let DecoderMethod = "DecodeSPRRegListOperand";
470 // An operand for the CONSTPOOL_ENTRY pseudo-instruction.
471 def cpinst_operand : Operand<i32> {
472 let PrintMethod = "printCPInstOperand";
476 def pclabel : Operand<i32> {
477 let PrintMethod = "printPCLabel";
480 // ADR instruction labels.
481 def AdrLabelAsmOperand : AsmOperandClass { let Name = "AdrLabel"; }
482 def adrlabel : Operand<i32> {
483 let EncoderMethod = "getAdrLabelOpValue";
484 let ParserMatchClass = AdrLabelAsmOperand;
485 let PrintMethod = "printAdrLabelOperand<0>";
488 def neon_vcvt_imm32 : Operand<i32> {
489 let EncoderMethod = "getNEONVcvtImm32OpValue";
490 let DecoderMethod = "DecodeVCVTImmOperand";
493 // rot_imm: An integer that encodes a rotate amount. Must be 8, 16, or 24.
494 def rot_imm_XFORM: SDNodeXForm<imm, [{
495 switch (N->getZExtValue()){
497 case 0: return CurDAG->getTargetConstant(0, MVT::i32);
498 case 8: return CurDAG->getTargetConstant(1, MVT::i32);
499 case 16: return CurDAG->getTargetConstant(2, MVT::i32);
500 case 24: return CurDAG->getTargetConstant(3, MVT::i32);
503 def RotImmAsmOperand : AsmOperandClass {
505 let ParserMethod = "parseRotImm";
507 def rot_imm : Operand<i32>, PatLeaf<(i32 imm), [{
508 int32_t v = N->getZExtValue();
509 return v == 8 || v == 16 || v == 24; }],
511 let PrintMethod = "printRotImmOperand";
512 let ParserMatchClass = RotImmAsmOperand;
515 // shift_imm: An integer that encodes a shift amount and the type of shift
516 // (asr or lsl). The 6-bit immediate encodes as:
519 // {4-0} imm5 shift amount.
520 // asr #32 encoded as imm5 == 0.
521 def ShifterImmAsmOperand : AsmOperandClass {
522 let Name = "ShifterImm";
523 let ParserMethod = "parseShifterImm";
525 def shift_imm : Operand<i32> {
526 let PrintMethod = "printShiftImmOperand";
527 let ParserMatchClass = ShifterImmAsmOperand;
530 // shifter_operand operands: so_reg_reg, so_reg_imm, and so_imm.
531 def ShiftedRegAsmOperand : AsmOperandClass { let Name = "RegShiftedReg"; }
532 def so_reg_reg : Operand<i32>, // reg reg imm
533 ComplexPattern<i32, 3, "SelectRegShifterOperand",
534 [shl, srl, sra, rotr]> {
535 let EncoderMethod = "getSORegRegOpValue";
536 let PrintMethod = "printSORegRegOperand";
537 let DecoderMethod = "DecodeSORegRegOperand";
538 let ParserMatchClass = ShiftedRegAsmOperand;
539 let MIOperandInfo = (ops GPRnopc, GPRnopc, i32imm);
542 def ShiftedImmAsmOperand : AsmOperandClass { let Name = "RegShiftedImm"; }
543 def so_reg_imm : Operand<i32>, // reg imm
544 ComplexPattern<i32, 2, "SelectImmShifterOperand",
545 [shl, srl, sra, rotr]> {
546 let EncoderMethod = "getSORegImmOpValue";
547 let PrintMethod = "printSORegImmOperand";
548 let DecoderMethod = "DecodeSORegImmOperand";
549 let ParserMatchClass = ShiftedImmAsmOperand;
550 let MIOperandInfo = (ops GPR, i32imm);
553 // FIXME: Does this need to be distinct from so_reg?
554 def shift_so_reg_reg : Operand<i32>, // reg reg imm
555 ComplexPattern<i32, 3, "SelectShiftRegShifterOperand",
556 [shl,srl,sra,rotr]> {
557 let EncoderMethod = "getSORegRegOpValue";
558 let PrintMethod = "printSORegRegOperand";
559 let DecoderMethod = "DecodeSORegRegOperand";
560 let ParserMatchClass = ShiftedRegAsmOperand;
561 let MIOperandInfo = (ops GPR, GPR, i32imm);
564 // FIXME: Does this need to be distinct from so_reg?
565 def shift_so_reg_imm : Operand<i32>, // reg reg imm
566 ComplexPattern<i32, 2, "SelectShiftImmShifterOperand",
567 [shl,srl,sra,rotr]> {
568 let EncoderMethod = "getSORegImmOpValue";
569 let PrintMethod = "printSORegImmOperand";
570 let DecoderMethod = "DecodeSORegImmOperand";
571 let ParserMatchClass = ShiftedImmAsmOperand;
572 let MIOperandInfo = (ops GPR, i32imm);
576 // so_imm - Match a 32-bit shifter_operand immediate operand, which is an
577 // 8-bit immediate rotated by an arbitrary number of bits.
578 def SOImmAsmOperand: ImmAsmOperand { let Name = "ARMSOImm"; }
579 def so_imm : Operand<i32>, ImmLeaf<i32, [{
580 return ARM_AM::getSOImmVal(Imm) != -1;
582 let EncoderMethod = "getSOImmOpValue";
583 let ParserMatchClass = SOImmAsmOperand;
584 let DecoderMethod = "DecodeSOImmOperand";
587 // Break so_imm's up into two pieces. This handles immediates with up to 16
588 // bits set in them. This uses so_imm2part to match and so_imm2part_[12] to
589 // get the first/second pieces.
590 def so_imm2part : PatLeaf<(imm), [{
591 return ARM_AM::isSOImmTwoPartVal((unsigned)N->getZExtValue());
594 /// arm_i32imm - True for +V6T2, or true only if so_imm2part is true.
596 def arm_i32imm : PatLeaf<(imm), [{
597 if (Subtarget->useMovt())
599 return ARM_AM::isSOImmTwoPartVal((unsigned)N->getZExtValue());
602 /// imm0_1 predicate - Immediate in the range [0,1].
603 def Imm0_1AsmOperand: ImmAsmOperand { let Name = "Imm0_1"; }
604 def imm0_1 : Operand<i32> { let ParserMatchClass = Imm0_1AsmOperand; }
606 /// imm0_3 predicate - Immediate in the range [0,3].
607 def Imm0_3AsmOperand: ImmAsmOperand { let Name = "Imm0_3"; }
608 def imm0_3 : Operand<i32> { let ParserMatchClass = Imm0_3AsmOperand; }
610 /// imm0_7 predicate - Immediate in the range [0,7].
611 def Imm0_7AsmOperand: ImmAsmOperand { let Name = "Imm0_7"; }
612 def imm0_7 : Operand<i32>, ImmLeaf<i32, [{
613 return Imm >= 0 && Imm < 8;
615 let ParserMatchClass = Imm0_7AsmOperand;
618 /// imm8 predicate - Immediate is exactly 8.
619 def Imm8AsmOperand: ImmAsmOperand { let Name = "Imm8"; }
620 def imm8 : Operand<i32>, ImmLeaf<i32, [{ return Imm == 8; }]> {
621 let ParserMatchClass = Imm8AsmOperand;
624 /// imm16 predicate - Immediate is exactly 16.
625 def Imm16AsmOperand: ImmAsmOperand { let Name = "Imm16"; }
626 def imm16 : Operand<i32>, ImmLeaf<i32, [{ return Imm == 16; }]> {
627 let ParserMatchClass = Imm16AsmOperand;
630 /// imm32 predicate - Immediate is exactly 32.
631 def Imm32AsmOperand: ImmAsmOperand { let Name = "Imm32"; }
632 def imm32 : Operand<i32>, ImmLeaf<i32, [{ return Imm == 32; }]> {
633 let ParserMatchClass = Imm32AsmOperand;
636 /// imm1_7 predicate - Immediate in the range [1,7].
637 def Imm1_7AsmOperand: ImmAsmOperand { let Name = "Imm1_7"; }
638 def imm1_7 : Operand<i32>, ImmLeaf<i32, [{ return Imm > 0 && Imm < 8; }]> {
639 let ParserMatchClass = Imm1_7AsmOperand;
642 /// imm1_15 predicate - Immediate in the range [1,15].
643 def Imm1_15AsmOperand: ImmAsmOperand { let Name = "Imm1_15"; }
644 def imm1_15 : Operand<i32>, ImmLeaf<i32, [{ return Imm > 0 && Imm < 16; }]> {
645 let ParserMatchClass = Imm1_15AsmOperand;
648 /// imm1_31 predicate - Immediate in the range [1,31].
649 def Imm1_31AsmOperand: ImmAsmOperand { let Name = "Imm1_31"; }
650 def imm1_31 : Operand<i32>, ImmLeaf<i32, [{ return Imm > 0 && Imm < 32; }]> {
651 let ParserMatchClass = Imm1_31AsmOperand;
654 /// imm0_15 predicate - Immediate in the range [0,15].
655 def Imm0_15AsmOperand: ImmAsmOperand {
656 let Name = "Imm0_15";
657 let DiagnosticType = "ImmRange0_15";
659 def imm0_15 : Operand<i32>, ImmLeaf<i32, [{
660 return Imm >= 0 && Imm < 16;
662 let ParserMatchClass = Imm0_15AsmOperand;
665 /// imm0_31 predicate - True if the 32-bit immediate is in the range [0,31].
666 def Imm0_31AsmOperand: ImmAsmOperand { let Name = "Imm0_31"; }
667 def imm0_31 : Operand<i32>, ImmLeaf<i32, [{
668 return Imm >= 0 && Imm < 32;
670 let ParserMatchClass = Imm0_31AsmOperand;
673 /// imm0_32 predicate - True if the 32-bit immediate is in the range [0,32].
674 def Imm0_32AsmOperand: ImmAsmOperand { let Name = "Imm0_32"; }
675 def imm0_32 : Operand<i32>, ImmLeaf<i32, [{
676 return Imm >= 0 && Imm < 32;
678 let ParserMatchClass = Imm0_32AsmOperand;
681 /// imm0_63 predicate - True if the 32-bit immediate is in the range [0,63].
682 def Imm0_63AsmOperand: ImmAsmOperand { let Name = "Imm0_63"; }
683 def imm0_63 : Operand<i32>, ImmLeaf<i32, [{
684 return Imm >= 0 && Imm < 64;
686 let ParserMatchClass = Imm0_63AsmOperand;
689 /// imm0_239 predicate - Immediate in the range [0,239].
690 def Imm0_239AsmOperand : ImmAsmOperand {
691 let Name = "Imm0_239";
692 let DiagnosticType = "ImmRange0_239";
694 def imm0_239 : Operand<i32>, ImmLeaf<i32, [{ return Imm >= 0 && Imm < 240; }]> {
695 let ParserMatchClass = Imm0_239AsmOperand;
698 /// imm0_255 predicate - Immediate in the range [0,255].
699 def Imm0_255AsmOperand : ImmAsmOperand { let Name = "Imm0_255"; }
700 def imm0_255 : Operand<i32>, ImmLeaf<i32, [{ return Imm >= 0 && Imm < 256; }]> {
701 let ParserMatchClass = Imm0_255AsmOperand;
704 /// imm0_65535 - An immediate is in the range [0.65535].
705 def Imm0_65535AsmOperand: ImmAsmOperand { let Name = "Imm0_65535"; }
706 def imm0_65535 : Operand<i32>, ImmLeaf<i32, [{
707 return Imm >= 0 && Imm < 65536;
709 let ParserMatchClass = Imm0_65535AsmOperand;
712 // imm0_65535_neg - An immediate whose negative value is in the range [0.65535].
713 def imm0_65535_neg : Operand<i32>, ImmLeaf<i32, [{
714 return -Imm >= 0 && -Imm < 65536;
717 // imm0_65535_expr - For movt/movw - 16-bit immediate that can also reference
718 // a relocatable expression.
720 // FIXME: This really needs a Thumb version separate from the ARM version.
721 // While the range is the same, and can thus use the same match class,
722 // the encoding is different so it should have a different encoder method.
723 def Imm0_65535ExprAsmOperand: ImmAsmOperand { let Name = "Imm0_65535Expr"; }
724 def imm0_65535_expr : Operand<i32> {
725 let EncoderMethod = "getHiLo16ImmOpValue";
726 let ParserMatchClass = Imm0_65535ExprAsmOperand;
729 def Imm256_65535ExprAsmOperand: ImmAsmOperand { let Name = "Imm256_65535Expr"; }
730 def imm256_65535_expr : Operand<i32> {
731 let ParserMatchClass = Imm256_65535ExprAsmOperand;
734 /// imm24b - True if the 32-bit immediate is encodable in 24 bits.
735 def Imm24bitAsmOperand: ImmAsmOperand { let Name = "Imm24bit"; }
736 def imm24b : Operand<i32>, ImmLeaf<i32, [{
737 return Imm >= 0 && Imm <= 0xffffff;
739 let ParserMatchClass = Imm24bitAsmOperand;
743 /// bf_inv_mask_imm predicate - An AND mask to clear an arbitrary width bitfield
745 def BitfieldAsmOperand : AsmOperandClass {
746 let Name = "Bitfield";
747 let ParserMethod = "parseBitfield";
750 def bf_inv_mask_imm : Operand<i32>,
752 return ARM::isBitFieldInvertedMask(N->getZExtValue());
754 let EncoderMethod = "getBitfieldInvertedMaskOpValue";
755 let PrintMethod = "printBitfieldInvMaskImmOperand";
756 let DecoderMethod = "DecodeBitfieldMaskOperand";
757 let ParserMatchClass = BitfieldAsmOperand;
760 def imm1_32_XFORM: SDNodeXForm<imm, [{
761 return CurDAG->getTargetConstant((int)N->getZExtValue() - 1, MVT::i32);
763 def Imm1_32AsmOperand: AsmOperandClass { let Name = "Imm1_32"; }
764 def imm1_32 : Operand<i32>, PatLeaf<(imm), [{
765 uint64_t Imm = N->getZExtValue();
766 return Imm > 0 && Imm <= 32;
769 let PrintMethod = "printImmPlusOneOperand";
770 let ParserMatchClass = Imm1_32AsmOperand;
773 def imm1_16_XFORM: SDNodeXForm<imm, [{
774 return CurDAG->getTargetConstant((int)N->getZExtValue() - 1, MVT::i32);
776 def Imm1_16AsmOperand: AsmOperandClass { let Name = "Imm1_16"; }
777 def imm1_16 : Operand<i32>, PatLeaf<(imm), [{ return Imm > 0 && Imm <= 16; }],
779 let PrintMethod = "printImmPlusOneOperand";
780 let ParserMatchClass = Imm1_16AsmOperand;
783 // Define ARM specific addressing modes.
784 // addrmode_imm12 := reg +/- imm12
786 def MemImm12OffsetAsmOperand : AsmOperandClass { let Name = "MemImm12Offset"; }
787 class AddrMode_Imm12 : Operand<i32>,
788 ComplexPattern<i32, 2, "SelectAddrModeImm12", []> {
789 // 12-bit immediate operand. Note that instructions using this encode
790 // #0 and #-0 differently. We flag #-0 as the magic value INT32_MIN. All other
791 // immediate values are as normal.
793 let EncoderMethod = "getAddrModeImm12OpValue";
794 let DecoderMethod = "DecodeAddrModeImm12Operand";
795 let ParserMatchClass = MemImm12OffsetAsmOperand;
796 let MIOperandInfo = (ops GPR:$base, i32imm:$offsimm);
799 def addrmode_imm12 : AddrMode_Imm12 {
800 let PrintMethod = "printAddrModeImm12Operand<false>";
803 def addrmode_imm12_pre : AddrMode_Imm12 {
804 let PrintMethod = "printAddrModeImm12Operand<true>";
807 // ldst_so_reg := reg +/- reg shop imm
809 def MemRegOffsetAsmOperand : AsmOperandClass { let Name = "MemRegOffset"; }
810 def ldst_so_reg : Operand<i32>,
811 ComplexPattern<i32, 3, "SelectLdStSOReg", []> {
812 let EncoderMethod = "getLdStSORegOpValue";
813 // FIXME: Simplify the printer
814 let PrintMethod = "printAddrMode2Operand";
815 let DecoderMethod = "DecodeSORegMemOperand";
816 let ParserMatchClass = MemRegOffsetAsmOperand;
817 let MIOperandInfo = (ops GPR:$base, GPRnopc:$offsreg, i32imm:$shift);
820 // postidx_imm8 := +/- [0,255]
823 // {8} 1 is imm8 is non-negative. 0 otherwise.
824 // {7-0} [0,255] imm8 value.
825 def PostIdxImm8AsmOperand : AsmOperandClass { let Name = "PostIdxImm8"; }
826 def postidx_imm8 : Operand<i32> {
827 let PrintMethod = "printPostIdxImm8Operand";
828 let ParserMatchClass = PostIdxImm8AsmOperand;
829 let MIOperandInfo = (ops i32imm);
832 // postidx_imm8s4 := +/- [0,1020]
835 // {8} 1 is imm8 is non-negative. 0 otherwise.
836 // {7-0} [0,255] imm8 value, scaled by 4.
837 def PostIdxImm8s4AsmOperand : AsmOperandClass { let Name = "PostIdxImm8s4"; }
838 def postidx_imm8s4 : Operand<i32> {
839 let PrintMethod = "printPostIdxImm8s4Operand";
840 let ParserMatchClass = PostIdxImm8s4AsmOperand;
841 let MIOperandInfo = (ops i32imm);
845 // postidx_reg := +/- reg
847 def PostIdxRegAsmOperand : AsmOperandClass {
848 let Name = "PostIdxReg";
849 let ParserMethod = "parsePostIdxReg";
851 def postidx_reg : Operand<i32> {
852 let EncoderMethod = "getPostIdxRegOpValue";
853 let DecoderMethod = "DecodePostIdxReg";
854 let PrintMethod = "printPostIdxRegOperand";
855 let ParserMatchClass = PostIdxRegAsmOperand;
856 let MIOperandInfo = (ops GPRnopc, i32imm);
860 // addrmode2 := reg +/- imm12
861 // := reg +/- reg shop imm
863 // FIXME: addrmode2 should be refactored the rest of the way to always
864 // use explicit imm vs. reg versions above (addrmode_imm12 and ldst_so_reg).
865 def AddrMode2AsmOperand : AsmOperandClass { let Name = "AddrMode2"; }
866 def addrmode2 : Operand<i32>,
867 ComplexPattern<i32, 3, "SelectAddrMode2", []> {
868 let EncoderMethod = "getAddrMode2OpValue";
869 let PrintMethod = "printAddrMode2Operand";
870 let ParserMatchClass = AddrMode2AsmOperand;
871 let MIOperandInfo = (ops GPR:$base, GPR:$offsreg, i32imm:$offsimm);
874 def PostIdxRegShiftedAsmOperand : AsmOperandClass {
875 let Name = "PostIdxRegShifted";
876 let ParserMethod = "parsePostIdxReg";
878 def am2offset_reg : Operand<i32>,
879 ComplexPattern<i32, 2, "SelectAddrMode2OffsetReg",
880 [], [SDNPWantRoot]> {
881 let EncoderMethod = "getAddrMode2OffsetOpValue";
882 let PrintMethod = "printAddrMode2OffsetOperand";
883 // When using this for assembly, it's always as a post-index offset.
884 let ParserMatchClass = PostIdxRegShiftedAsmOperand;
885 let MIOperandInfo = (ops GPRnopc, i32imm);
888 // FIXME: am2offset_imm should only need the immediate, not the GPR. Having
889 // the GPR is purely vestigal at this point.
890 def AM2OffsetImmAsmOperand : AsmOperandClass { let Name = "AM2OffsetImm"; }
891 def am2offset_imm : Operand<i32>,
892 ComplexPattern<i32, 2, "SelectAddrMode2OffsetImm",
893 [], [SDNPWantRoot]> {
894 let EncoderMethod = "getAddrMode2OffsetOpValue";
895 let PrintMethod = "printAddrMode2OffsetOperand";
896 let ParserMatchClass = AM2OffsetImmAsmOperand;
897 let MIOperandInfo = (ops GPRnopc, i32imm);
901 // addrmode3 := reg +/- reg
902 // addrmode3 := reg +/- imm8
904 // FIXME: split into imm vs. reg versions.
905 def AddrMode3AsmOperand : AsmOperandClass { let Name = "AddrMode3"; }
906 class AddrMode3 : Operand<i32>,
907 ComplexPattern<i32, 3, "SelectAddrMode3", []> {
908 let EncoderMethod = "getAddrMode3OpValue";
909 let ParserMatchClass = AddrMode3AsmOperand;
910 let MIOperandInfo = (ops GPR:$base, GPR:$offsreg, i32imm:$offsimm);
913 def addrmode3 : AddrMode3
915 let PrintMethod = "printAddrMode3Operand<false>";
918 def addrmode3_pre : AddrMode3
920 let PrintMethod = "printAddrMode3Operand<true>";
923 // FIXME: split into imm vs. reg versions.
924 // FIXME: parser method to handle +/- register.
925 def AM3OffsetAsmOperand : AsmOperandClass {
926 let Name = "AM3Offset";
927 let ParserMethod = "parseAM3Offset";
929 def am3offset : Operand<i32>,
930 ComplexPattern<i32, 2, "SelectAddrMode3Offset",
931 [], [SDNPWantRoot]> {
932 let EncoderMethod = "getAddrMode3OffsetOpValue";
933 let PrintMethod = "printAddrMode3OffsetOperand";
934 let ParserMatchClass = AM3OffsetAsmOperand;
935 let MIOperandInfo = (ops GPR, i32imm);
938 // ldstm_mode := {ia, ib, da, db}
940 def ldstm_mode : OptionalDefOperand<OtherVT, (ops i32), (ops (i32 1))> {
941 let EncoderMethod = "getLdStmModeOpValue";
942 let PrintMethod = "printLdStmModeOperand";
945 // addrmode5 := reg +/- imm8*4
947 def AddrMode5AsmOperand : AsmOperandClass { let Name = "AddrMode5"; }
948 class AddrMode5 : Operand<i32>,
949 ComplexPattern<i32, 2, "SelectAddrMode5", []> {
950 let EncoderMethod = "getAddrMode5OpValue";
951 let DecoderMethod = "DecodeAddrMode5Operand";
952 let ParserMatchClass = AddrMode5AsmOperand;
953 let MIOperandInfo = (ops GPR:$base, i32imm);
956 def addrmode5 : AddrMode5 {
957 let PrintMethod = "printAddrMode5Operand<false>";
960 def addrmode5_pre : AddrMode5 {
961 let PrintMethod = "printAddrMode5Operand<true>";
964 // addrmode6 := reg with optional alignment
966 def AddrMode6AsmOperand : AsmOperandClass { let Name = "AlignedMemory"; }
967 def addrmode6 : Operand<i32>,
968 ComplexPattern<i32, 2, "SelectAddrMode6", [], [SDNPWantParent]>{
969 let PrintMethod = "printAddrMode6Operand";
970 let MIOperandInfo = (ops GPR:$addr, i32imm:$align);
971 let EncoderMethod = "getAddrMode6AddressOpValue";
972 let DecoderMethod = "DecodeAddrMode6Operand";
973 let ParserMatchClass = AddrMode6AsmOperand;
976 def am6offset : Operand<i32>,
977 ComplexPattern<i32, 1, "SelectAddrMode6Offset",
978 [], [SDNPWantRoot]> {
979 let PrintMethod = "printAddrMode6OffsetOperand";
980 let MIOperandInfo = (ops GPR);
981 let EncoderMethod = "getAddrMode6OffsetOpValue";
982 let DecoderMethod = "DecodeGPRRegisterClass";
985 // Special version of addrmode6 to handle alignment encoding for VST1/VLD1
986 // (single element from one lane) for size 32.
987 def addrmode6oneL32 : Operand<i32>,
988 ComplexPattern<i32, 2, "SelectAddrMode6", [], [SDNPWantParent]>{
989 let PrintMethod = "printAddrMode6Operand";
990 let MIOperandInfo = (ops GPR:$addr, i32imm);
991 let EncoderMethod = "getAddrMode6OneLane32AddressOpValue";
994 // Special version of addrmode6 to handle alignment encoding for VLD-dup
995 // instructions, specifically VLD4-dup.
996 def addrmode6dup : Operand<i32>,
997 ComplexPattern<i32, 2, "SelectAddrMode6", [], [SDNPWantParent]>{
998 let PrintMethod = "printAddrMode6Operand";
999 let MIOperandInfo = (ops GPR:$addr, i32imm);
1000 let EncoderMethod = "getAddrMode6DupAddressOpValue";
1001 // FIXME: This is close, but not quite right. The alignment specifier is
1003 let ParserMatchClass = AddrMode6AsmOperand;
1006 // addrmodepc := pc + reg
1008 def addrmodepc : Operand<i32>,
1009 ComplexPattern<i32, 2, "SelectAddrModePC", []> {
1010 let PrintMethod = "printAddrModePCOperand";
1011 let MIOperandInfo = (ops GPR, i32imm);
1014 // addr_offset_none := reg
1016 def MemNoOffsetAsmOperand : AsmOperandClass { let Name = "MemNoOffset"; }
1017 def addr_offset_none : Operand<i32>,
1018 ComplexPattern<i32, 1, "SelectAddrOffsetNone", []> {
1019 let PrintMethod = "printAddrMode7Operand";
1020 let DecoderMethod = "DecodeAddrMode7Operand";
1021 let ParserMatchClass = MemNoOffsetAsmOperand;
1022 let MIOperandInfo = (ops GPR:$base);
1025 def nohash_imm : Operand<i32> {
1026 let PrintMethod = "printNoHashImmediate";
1029 def CoprocNumAsmOperand : AsmOperandClass {
1030 let Name = "CoprocNum";
1031 let ParserMethod = "parseCoprocNumOperand";
1033 def p_imm : Operand<i32> {
1034 let PrintMethod = "printPImmediate";
1035 let ParserMatchClass = CoprocNumAsmOperand;
1036 let DecoderMethod = "DecodeCoprocessor";
1039 def CoprocRegAsmOperand : AsmOperandClass {
1040 let Name = "CoprocReg";
1041 let ParserMethod = "parseCoprocRegOperand";
1043 def c_imm : Operand<i32> {
1044 let PrintMethod = "printCImmediate";
1045 let ParserMatchClass = CoprocRegAsmOperand;
1047 def CoprocOptionAsmOperand : AsmOperandClass {
1048 let Name = "CoprocOption";
1049 let ParserMethod = "parseCoprocOptionOperand";
1051 def coproc_option_imm : Operand<i32> {
1052 let PrintMethod = "printCoprocOptionImm";
1053 let ParserMatchClass = CoprocOptionAsmOperand;
1056 //===----------------------------------------------------------------------===//
1058 include "ARMInstrFormats.td"
1060 //===----------------------------------------------------------------------===//
1061 // Multiclass helpers...
1064 /// AsI1_bin_irs - Defines a set of (op r, {so_imm|r|so_reg}) patterns for a
1065 /// binop that produces a value.
1066 let TwoOperandAliasConstraint = "$Rn = $Rd" in
1067 multiclass AsI1_bin_irs<bits<4> opcod, string opc,
1068 InstrItinClass iii, InstrItinClass iir, InstrItinClass iis,
1069 PatFrag opnode, bit Commutable = 0> {
1070 // The register-immediate version is re-materializable. This is useful
1071 // in particular for taking the address of a local.
1072 let isReMaterializable = 1 in {
1073 def ri : AsI1<opcod, (outs GPR:$Rd), (ins GPR:$Rn, so_imm:$imm), DPFrm,
1074 iii, opc, "\t$Rd, $Rn, $imm",
1075 [(set GPR:$Rd, (opnode GPR:$Rn, so_imm:$imm))]>,
1076 Sched<[WriteALU, ReadALU]> {
1081 let Inst{19-16} = Rn;
1082 let Inst{15-12} = Rd;
1083 let Inst{11-0} = imm;
1086 def rr : AsI1<opcod, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm), DPFrm,
1087 iir, opc, "\t$Rd, $Rn, $Rm",
1088 [(set GPR:$Rd, (opnode GPR:$Rn, GPR:$Rm))]>,
1089 Sched<[WriteALU, ReadALU, ReadALU]> {
1094 let isCommutable = Commutable;
1095 let Inst{19-16} = Rn;
1096 let Inst{15-12} = Rd;
1097 let Inst{11-4} = 0b00000000;
1101 def rsi : AsI1<opcod, (outs GPR:$Rd),
1102 (ins GPR:$Rn, so_reg_imm:$shift), DPSoRegImmFrm,
1103 iis, opc, "\t$Rd, $Rn, $shift",
1104 [(set GPR:$Rd, (opnode GPR:$Rn, so_reg_imm:$shift))]>,
1105 Sched<[WriteALUsi, ReadALU]> {
1110 let Inst{19-16} = Rn;
1111 let Inst{15-12} = Rd;
1112 let Inst{11-5} = shift{11-5};
1114 let Inst{3-0} = shift{3-0};
1117 def rsr : AsI1<opcod, (outs GPR:$Rd),
1118 (ins GPR:$Rn, so_reg_reg:$shift), DPSoRegRegFrm,
1119 iis, opc, "\t$Rd, $Rn, $shift",
1120 [(set GPR:$Rd, (opnode GPR:$Rn, so_reg_reg:$shift))]>,
1121 Sched<[WriteALUsr, ReadALUsr]> {
1126 let Inst{19-16} = Rn;
1127 let Inst{15-12} = Rd;
1128 let Inst{11-8} = shift{11-8};
1130 let Inst{6-5} = shift{6-5};
1132 let Inst{3-0} = shift{3-0};
1136 /// AsI1_rbin_irs - Same as AsI1_bin_irs except the order of operands are
1137 /// reversed. The 'rr' form is only defined for the disassembler; for codegen
1138 /// it is equivalent to the AsI1_bin_irs counterpart.
1139 let TwoOperandAliasConstraint = "$Rn = $Rd" in
1140 multiclass AsI1_rbin_irs<bits<4> opcod, string opc,
1141 InstrItinClass iii, InstrItinClass iir, InstrItinClass iis,
1142 PatFrag opnode, bit Commutable = 0> {
1143 // The register-immediate version is re-materializable. This is useful
1144 // in particular for taking the address of a local.
1145 let isReMaterializable = 1 in {
1146 def ri : AsI1<opcod, (outs GPR:$Rd), (ins GPR:$Rn, so_imm:$imm), DPFrm,
1147 iii, opc, "\t$Rd, $Rn, $imm",
1148 [(set GPR:$Rd, (opnode so_imm:$imm, GPR:$Rn))]>,
1149 Sched<[WriteALU, ReadALU]> {
1154 let Inst{19-16} = Rn;
1155 let Inst{15-12} = Rd;
1156 let Inst{11-0} = imm;
1159 def rr : AsI1<opcod, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm), DPFrm,
1160 iir, opc, "\t$Rd, $Rn, $Rm",
1161 [/* pattern left blank */]>,
1162 Sched<[WriteALU, ReadALU, ReadALU]> {
1166 let Inst{11-4} = 0b00000000;
1169 let Inst{15-12} = Rd;
1170 let Inst{19-16} = Rn;
1173 def rsi : AsI1<opcod, (outs GPR:$Rd),
1174 (ins GPR:$Rn, so_reg_imm:$shift), DPSoRegImmFrm,
1175 iis, opc, "\t$Rd, $Rn, $shift",
1176 [(set GPR:$Rd, (opnode so_reg_imm:$shift, GPR:$Rn))]>,
1177 Sched<[WriteALUsi, ReadALU]> {
1182 let Inst{19-16} = Rn;
1183 let Inst{15-12} = Rd;
1184 let Inst{11-5} = shift{11-5};
1186 let Inst{3-0} = shift{3-0};
1189 def rsr : AsI1<opcod, (outs GPR:$Rd),
1190 (ins GPR:$Rn, so_reg_reg:$shift), DPSoRegRegFrm,
1191 iis, opc, "\t$Rd, $Rn, $shift",
1192 [(set GPR:$Rd, (opnode so_reg_reg:$shift, GPR:$Rn))]>,
1193 Sched<[WriteALUsr, ReadALUsr]> {
1198 let Inst{19-16} = Rn;
1199 let Inst{15-12} = Rd;
1200 let Inst{11-8} = shift{11-8};
1202 let Inst{6-5} = shift{6-5};
1204 let Inst{3-0} = shift{3-0};
1208 /// AsI1_bin_s_irs - Same as AsI1_bin_irs except it sets the 's' bit by default.
1210 /// These opcodes will be converted to the real non-S opcodes by
1211 /// AdjustInstrPostInstrSelection after giving them an optional CPSR operand.
1212 let hasPostISelHook = 1, Defs = [CPSR] in {
1213 multiclass AsI1_bin_s_irs<InstrItinClass iii, InstrItinClass iir,
1214 InstrItinClass iis, PatFrag opnode,
1215 bit Commutable = 0> {
1216 def ri : ARMPseudoInst<(outs GPR:$Rd), (ins GPR:$Rn, so_imm:$imm, pred:$p),
1218 [(set GPR:$Rd, CPSR, (opnode GPR:$Rn, so_imm:$imm))]>,
1219 Sched<[WriteALU, ReadALU]>;
1221 def rr : ARMPseudoInst<(outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm, pred:$p),
1223 [(set GPR:$Rd, CPSR, (opnode GPR:$Rn, GPR:$Rm))]>,
1224 Sched<[WriteALU, ReadALU, ReadALU]> {
1225 let isCommutable = Commutable;
1227 def rsi : ARMPseudoInst<(outs GPR:$Rd),
1228 (ins GPR:$Rn, so_reg_imm:$shift, pred:$p),
1230 [(set GPR:$Rd, CPSR, (opnode GPR:$Rn,
1231 so_reg_imm:$shift))]>,
1232 Sched<[WriteALUsi, ReadALU]>;
1234 def rsr : ARMPseudoInst<(outs GPR:$Rd),
1235 (ins GPR:$Rn, so_reg_reg:$shift, pred:$p),
1237 [(set GPR:$Rd, CPSR, (opnode GPR:$Rn,
1238 so_reg_reg:$shift))]>,
1239 Sched<[WriteALUSsr, ReadALUsr]>;
1243 /// AsI1_rbin_s_is - Same as AsI1_bin_s_irs, except selection DAG
1244 /// operands are reversed.
1245 let hasPostISelHook = 1, Defs = [CPSR] in {
1246 multiclass AsI1_rbin_s_is<InstrItinClass iii, InstrItinClass iir,
1247 InstrItinClass iis, PatFrag opnode,
1248 bit Commutable = 0> {
1249 def ri : ARMPseudoInst<(outs GPR:$Rd), (ins GPR:$Rn, so_imm:$imm, pred:$p),
1251 [(set GPR:$Rd, CPSR, (opnode so_imm:$imm, GPR:$Rn))]>,
1252 Sched<[WriteALU, ReadALU]>;
1254 def rsi : ARMPseudoInst<(outs GPR:$Rd),
1255 (ins GPR:$Rn, so_reg_imm:$shift, pred:$p),
1257 [(set GPR:$Rd, CPSR, (opnode so_reg_imm:$shift,
1259 Sched<[WriteALUsi, ReadALU]>;
1261 def rsr : ARMPseudoInst<(outs GPR:$Rd),
1262 (ins GPR:$Rn, so_reg_reg:$shift, pred:$p),
1264 [(set GPR:$Rd, CPSR, (opnode so_reg_reg:$shift,
1266 Sched<[WriteALUSsr, ReadALUsr]>;
1270 /// AI1_cmp_irs - Defines a set of (op r, {so_imm|r|so_reg}) cmp / test
1271 /// patterns. Similar to AsI1_bin_irs except the instruction does not produce
1272 /// a explicit result, only implicitly set CPSR.
1273 let isCompare = 1, Defs = [CPSR] in {
1274 multiclass AI1_cmp_irs<bits<4> opcod, string opc,
1275 InstrItinClass iii, InstrItinClass iir, InstrItinClass iis,
1276 PatFrag opnode, bit Commutable = 0> {
1277 def ri : AI1<opcod, (outs), (ins GPR:$Rn, so_imm:$imm), DPFrm, iii,
1279 [(opnode GPR:$Rn, so_imm:$imm)]>,
1280 Sched<[WriteCMP, ReadALU]> {
1285 let Inst{19-16} = Rn;
1286 let Inst{15-12} = 0b0000;
1287 let Inst{11-0} = imm;
1289 let Unpredictable{15-12} = 0b1111;
1291 def rr : AI1<opcod, (outs), (ins GPR:$Rn, GPR:$Rm), DPFrm, iir,
1293 [(opnode GPR:$Rn, GPR:$Rm)]>,
1294 Sched<[WriteCMP, ReadALU, ReadALU]> {
1297 let isCommutable = Commutable;
1300 let Inst{19-16} = Rn;
1301 let Inst{15-12} = 0b0000;
1302 let Inst{11-4} = 0b00000000;
1305 let Unpredictable{15-12} = 0b1111;
1307 def rsi : AI1<opcod, (outs),
1308 (ins GPR:$Rn, so_reg_imm:$shift), DPSoRegImmFrm, iis,
1309 opc, "\t$Rn, $shift",
1310 [(opnode GPR:$Rn, so_reg_imm:$shift)]>,
1311 Sched<[WriteCMPsi, ReadALU]> {
1316 let Inst{19-16} = Rn;
1317 let Inst{15-12} = 0b0000;
1318 let Inst{11-5} = shift{11-5};
1320 let Inst{3-0} = shift{3-0};
1322 let Unpredictable{15-12} = 0b1111;
1324 def rsr : AI1<opcod, (outs),
1325 (ins GPRnopc:$Rn, so_reg_reg:$shift), DPSoRegRegFrm, iis,
1326 opc, "\t$Rn, $shift",
1327 [(opnode GPRnopc:$Rn, so_reg_reg:$shift)]>,
1328 Sched<[WriteCMPsr, ReadALU]> {
1333 let Inst{19-16} = Rn;
1334 let Inst{15-12} = 0b0000;
1335 let Inst{11-8} = shift{11-8};
1337 let Inst{6-5} = shift{6-5};
1339 let Inst{3-0} = shift{3-0};
1341 let Unpredictable{15-12} = 0b1111;
1347 /// AI_ext_rrot - A unary operation with two forms: one whose operand is a
1348 /// register and one whose operand is a register rotated by 8/16/24.
1349 /// FIXME: Remove the 'r' variant. Its rot_imm is zero.
1350 class AI_ext_rrot<bits<8> opcod, string opc, PatFrag opnode>
1351 : AExtI<opcod, (outs GPRnopc:$Rd), (ins GPRnopc:$Rm, rot_imm:$rot),
1352 IIC_iEXTr, opc, "\t$Rd, $Rm$rot",
1353 [(set GPRnopc:$Rd, (opnode (rotr GPRnopc:$Rm, rot_imm:$rot)))]>,
1354 Requires<[IsARM, HasV6]>, Sched<[WriteALUsi]> {
1358 let Inst{19-16} = 0b1111;
1359 let Inst{15-12} = Rd;
1360 let Inst{11-10} = rot;
1364 class AI_ext_rrot_np<bits<8> opcod, string opc>
1365 : AExtI<opcod, (outs GPRnopc:$Rd), (ins GPRnopc:$Rm, rot_imm:$rot),
1366 IIC_iEXTr, opc, "\t$Rd, $Rm$rot", []>,
1367 Requires<[IsARM, HasV6]>, Sched<[WriteALUsi]> {
1369 let Inst{19-16} = 0b1111;
1370 let Inst{11-10} = rot;
1373 /// AI_exta_rrot - A binary operation with two forms: one whose operand is a
1374 /// register and one whose operand is a register rotated by 8/16/24.
1375 class AI_exta_rrot<bits<8> opcod, string opc, PatFrag opnode>
1376 : AExtI<opcod, (outs GPRnopc:$Rd), (ins GPR:$Rn, GPRnopc:$Rm, rot_imm:$rot),
1377 IIC_iEXTAr, opc, "\t$Rd, $Rn, $Rm$rot",
1378 [(set GPRnopc:$Rd, (opnode GPR:$Rn,
1379 (rotr GPRnopc:$Rm, rot_imm:$rot)))]>,
1380 Requires<[IsARM, HasV6]>, Sched<[WriteALUsr]> {
1385 let Inst{19-16} = Rn;
1386 let Inst{15-12} = Rd;
1387 let Inst{11-10} = rot;
1388 let Inst{9-4} = 0b000111;
1392 class AI_exta_rrot_np<bits<8> opcod, string opc>
1393 : AExtI<opcod, (outs GPRnopc:$Rd), (ins GPR:$Rn, GPRnopc:$Rm, rot_imm:$rot),
1394 IIC_iEXTAr, opc, "\t$Rd, $Rn, $Rm$rot", []>,
1395 Requires<[IsARM, HasV6]>, Sched<[WriteALUsr]> {
1398 let Inst{19-16} = Rn;
1399 let Inst{11-10} = rot;
1402 /// AI1_adde_sube_irs - Define instructions and patterns for adde and sube.
1403 let TwoOperandAliasConstraint = "$Rn = $Rd" in
1404 multiclass AI1_adde_sube_irs<bits<4> opcod, string opc, PatFrag opnode,
1405 bit Commutable = 0> {
1406 let hasPostISelHook = 1, Defs = [CPSR], Uses = [CPSR] in {
1407 def ri : AsI1<opcod, (outs GPR:$Rd), (ins GPR:$Rn, so_imm:$imm),
1408 DPFrm, IIC_iALUi, opc, "\t$Rd, $Rn, $imm",
1409 [(set GPR:$Rd, CPSR, (opnode GPR:$Rn, so_imm:$imm, CPSR))]>,
1411 Sched<[WriteALU, ReadALU]> {
1416 let Inst{15-12} = Rd;
1417 let Inst{19-16} = Rn;
1418 let Inst{11-0} = imm;
1420 def rr : AsI1<opcod, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm),
1421 DPFrm, IIC_iALUr, opc, "\t$Rd, $Rn, $Rm",
1422 [(set GPR:$Rd, CPSR, (opnode GPR:$Rn, GPR:$Rm, CPSR))]>,
1424 Sched<[WriteALU, ReadALU, ReadALU]> {
1428 let Inst{11-4} = 0b00000000;
1430 let isCommutable = Commutable;
1432 let Inst{15-12} = Rd;
1433 let Inst{19-16} = Rn;
1435 def rsi : AsI1<opcod, (outs GPR:$Rd),
1436 (ins GPR:$Rn, so_reg_imm:$shift),
1437 DPSoRegImmFrm, IIC_iALUsr, opc, "\t$Rd, $Rn, $shift",
1438 [(set GPR:$Rd, CPSR, (opnode GPR:$Rn, so_reg_imm:$shift, CPSR))]>,
1440 Sched<[WriteALUsi, ReadALU]> {
1445 let Inst{19-16} = Rn;
1446 let Inst{15-12} = Rd;
1447 let Inst{11-5} = shift{11-5};
1449 let Inst{3-0} = shift{3-0};
1451 def rsr : AsI1<opcod, (outs GPRnopc:$Rd),
1452 (ins GPRnopc:$Rn, so_reg_reg:$shift),
1453 DPSoRegRegFrm, IIC_iALUsr, opc, "\t$Rd, $Rn, $shift",
1454 [(set GPRnopc:$Rd, CPSR,
1455 (opnode GPRnopc:$Rn, so_reg_reg:$shift, CPSR))]>,
1457 Sched<[WriteALUsr, ReadALUsr]> {
1462 let Inst{19-16} = Rn;
1463 let Inst{15-12} = Rd;
1464 let Inst{11-8} = shift{11-8};
1466 let Inst{6-5} = shift{6-5};
1468 let Inst{3-0} = shift{3-0};
1473 /// AI1_rsc_irs - Define instructions and patterns for rsc
1474 let TwoOperandAliasConstraint = "$Rn = $Rd" in
1475 multiclass AI1_rsc_irs<bits<4> opcod, string opc, PatFrag opnode> {
1476 let hasPostISelHook = 1, Defs = [CPSR], Uses = [CPSR] in {
1477 def ri : AsI1<opcod, (outs GPR:$Rd), (ins GPR:$Rn, so_imm:$imm),
1478 DPFrm, IIC_iALUi, opc, "\t$Rd, $Rn, $imm",
1479 [(set GPR:$Rd, CPSR, (opnode so_imm:$imm, GPR:$Rn, CPSR))]>,
1481 Sched<[WriteALU, ReadALU]> {
1486 let Inst{15-12} = Rd;
1487 let Inst{19-16} = Rn;
1488 let Inst{11-0} = imm;
1490 def rr : AsI1<opcod, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm),
1491 DPFrm, IIC_iALUr, opc, "\t$Rd, $Rn, $Rm",
1492 [/* pattern left blank */]>,
1493 Sched<[WriteALU, ReadALU, ReadALU]> {
1497 let Inst{11-4} = 0b00000000;
1500 let Inst{15-12} = Rd;
1501 let Inst{19-16} = Rn;
1503 def rsi : AsI1<opcod, (outs GPR:$Rd), (ins GPR:$Rn, so_reg_imm:$shift),
1504 DPSoRegImmFrm, IIC_iALUsr, opc, "\t$Rd, $Rn, $shift",
1505 [(set GPR:$Rd, CPSR, (opnode so_reg_imm:$shift, GPR:$Rn, CPSR))]>,
1507 Sched<[WriteALUsi, ReadALU]> {
1512 let Inst{19-16} = Rn;
1513 let Inst{15-12} = Rd;
1514 let Inst{11-5} = shift{11-5};
1516 let Inst{3-0} = shift{3-0};
1518 def rsr : AsI1<opcod, (outs GPR:$Rd), (ins GPR:$Rn, so_reg_reg:$shift),
1519 DPSoRegRegFrm, IIC_iALUsr, opc, "\t$Rd, $Rn, $shift",
1520 [(set GPR:$Rd, CPSR, (opnode so_reg_reg:$shift, GPR:$Rn, CPSR))]>,
1522 Sched<[WriteALUsr, ReadALUsr]> {
1527 let Inst{19-16} = Rn;
1528 let Inst{15-12} = Rd;
1529 let Inst{11-8} = shift{11-8};
1531 let Inst{6-5} = shift{6-5};
1533 let Inst{3-0} = shift{3-0};
1538 let canFoldAsLoad = 1, isReMaterializable = 1 in {
1539 multiclass AI_ldr1<bit isByte, string opc, InstrItinClass iii,
1540 InstrItinClass iir, PatFrag opnode> {
1541 // Note: We use the complex addrmode_imm12 rather than just an input
1542 // GPR and a constrained immediate so that we can use this to match
1543 // frame index references and avoid matching constant pool references.
1544 def i12: AI2ldst<0b010, 1, isByte, (outs GPR:$Rt), (ins addrmode_imm12:$addr),
1545 AddrMode_i12, LdFrm, iii, opc, "\t$Rt, $addr",
1546 [(set GPR:$Rt, (opnode addrmode_imm12:$addr))]> {
1549 let Inst{23} = addr{12}; // U (add = ('U' == 1))
1550 let Inst{19-16} = addr{16-13}; // Rn
1551 let Inst{15-12} = Rt;
1552 let Inst{11-0} = addr{11-0}; // imm12
1554 def rs : AI2ldst<0b011, 1, isByte, (outs GPR:$Rt), (ins ldst_so_reg:$shift),
1555 AddrModeNone, LdFrm, iir, opc, "\t$Rt, $shift",
1556 [(set GPR:$Rt, (opnode ldst_so_reg:$shift))]> {
1559 let shift{4} = 0; // Inst{4} = 0
1560 let Inst{23} = shift{12}; // U (add = ('U' == 1))
1561 let Inst{19-16} = shift{16-13}; // Rn
1562 let Inst{15-12} = Rt;
1563 let Inst{11-0} = shift{11-0};
1568 let canFoldAsLoad = 1, isReMaterializable = 1 in {
1569 multiclass AI_ldr1nopc<bit isByte, string opc, InstrItinClass iii,
1570 InstrItinClass iir, PatFrag opnode> {
1571 // Note: We use the complex addrmode_imm12 rather than just an input
1572 // GPR and a constrained immediate so that we can use this to match
1573 // frame index references and avoid matching constant pool references.
1574 def i12: AI2ldst<0b010, 1, isByte, (outs GPRnopc:$Rt),
1575 (ins addrmode_imm12:$addr),
1576 AddrMode_i12, LdFrm, iii, opc, "\t$Rt, $addr",
1577 [(set GPRnopc:$Rt, (opnode addrmode_imm12:$addr))]> {
1580 let Inst{23} = addr{12}; // U (add = ('U' == 1))
1581 let Inst{19-16} = addr{16-13}; // Rn
1582 let Inst{15-12} = Rt;
1583 let Inst{11-0} = addr{11-0}; // imm12
1585 def rs : AI2ldst<0b011, 1, isByte, (outs GPRnopc:$Rt),
1586 (ins ldst_so_reg:$shift),
1587 AddrModeNone, LdFrm, iir, opc, "\t$Rt, $shift",
1588 [(set GPRnopc:$Rt, (opnode ldst_so_reg:$shift))]> {
1591 let shift{4} = 0; // Inst{4} = 0
1592 let Inst{23} = shift{12}; // U (add = ('U' == 1))
1593 let Inst{19-16} = shift{16-13}; // Rn
1594 let Inst{15-12} = Rt;
1595 let Inst{11-0} = shift{11-0};
1601 multiclass AI_str1<bit isByte, string opc, InstrItinClass iii,
1602 InstrItinClass iir, PatFrag opnode> {
1603 // Note: We use the complex addrmode_imm12 rather than just an input
1604 // GPR and a constrained immediate so that we can use this to match
1605 // frame index references and avoid matching constant pool references.
1606 def i12 : AI2ldst<0b010, 0, isByte, (outs),
1607 (ins GPR:$Rt, addrmode_imm12:$addr),
1608 AddrMode_i12, StFrm, iii, opc, "\t$Rt, $addr",
1609 [(opnode GPR:$Rt, addrmode_imm12:$addr)]> {
1612 let Inst{23} = addr{12}; // U (add = ('U' == 1))
1613 let Inst{19-16} = addr{16-13}; // Rn
1614 let Inst{15-12} = Rt;
1615 let Inst{11-0} = addr{11-0}; // imm12
1617 def rs : AI2ldst<0b011, 0, isByte, (outs), (ins GPR:$Rt, ldst_so_reg:$shift),
1618 AddrModeNone, StFrm, iir, opc, "\t$Rt, $shift",
1619 [(opnode GPR:$Rt, ldst_so_reg:$shift)]> {
1622 let shift{4} = 0; // Inst{4} = 0
1623 let Inst{23} = shift{12}; // U (add = ('U' == 1))
1624 let Inst{19-16} = shift{16-13}; // Rn
1625 let Inst{15-12} = Rt;
1626 let Inst{11-0} = shift{11-0};
1630 multiclass AI_str1nopc<bit isByte, string opc, InstrItinClass iii,
1631 InstrItinClass iir, PatFrag opnode> {
1632 // Note: We use the complex addrmode_imm12 rather than just an input
1633 // GPR and a constrained immediate so that we can use this to match
1634 // frame index references and avoid matching constant pool references.
1635 def i12 : AI2ldst<0b010, 0, isByte, (outs),
1636 (ins GPRnopc:$Rt, addrmode_imm12:$addr),
1637 AddrMode_i12, StFrm, iii, opc, "\t$Rt, $addr",
1638 [(opnode GPRnopc:$Rt, addrmode_imm12:$addr)]> {
1641 let Inst{23} = addr{12}; // U (add = ('U' == 1))
1642 let Inst{19-16} = addr{16-13}; // Rn
1643 let Inst{15-12} = Rt;
1644 let Inst{11-0} = addr{11-0}; // imm12
1646 def rs : AI2ldst<0b011, 0, isByte, (outs),
1647 (ins GPRnopc:$Rt, ldst_so_reg:$shift),
1648 AddrModeNone, StFrm, iir, opc, "\t$Rt, $shift",
1649 [(opnode GPRnopc:$Rt, ldst_so_reg:$shift)]> {
1652 let shift{4} = 0; // Inst{4} = 0
1653 let Inst{23} = shift{12}; // U (add = ('U' == 1))
1654 let Inst{19-16} = shift{16-13}; // Rn
1655 let Inst{15-12} = Rt;
1656 let Inst{11-0} = shift{11-0};
1661 //===----------------------------------------------------------------------===//
1663 //===----------------------------------------------------------------------===//
1665 //===----------------------------------------------------------------------===//
1666 // Miscellaneous Instructions.
1669 /// CONSTPOOL_ENTRY - This instruction represents a floating constant pool in
1670 /// the function. The first operand is the ID# for this instruction, the second
1671 /// is the index into the MachineConstantPool that this is, the third is the
1672 /// size in bytes of this constant pool entry.
1673 let neverHasSideEffects = 1, isNotDuplicable = 1 in
1674 def CONSTPOOL_ENTRY :
1675 PseudoInst<(outs), (ins cpinst_operand:$instid, cpinst_operand:$cpidx,
1676 i32imm:$size), NoItinerary, []>;
1678 // FIXME: Marking these as hasSideEffects is necessary to prevent machine DCE
1679 // from removing one half of the matched pairs. That breaks PEI, which assumes
1680 // these will always be in pairs, and asserts if it finds otherwise. Better way?
1681 let Defs = [SP], Uses = [SP], hasSideEffects = 1 in {
1682 def ADJCALLSTACKUP :
1683 PseudoInst<(outs), (ins i32imm:$amt1, i32imm:$amt2, pred:$p), NoItinerary,
1684 [(ARMcallseq_end timm:$amt1, timm:$amt2)]>;
1686 def ADJCALLSTACKDOWN :
1687 PseudoInst<(outs), (ins i32imm:$amt, pred:$p), NoItinerary,
1688 [(ARMcallseq_start timm:$amt)]>;
1691 def HINT : AI<(outs), (ins imm0_239:$imm), MiscFrm, NoItinerary,
1692 "hint", "\t$imm", []>, Requires<[IsARM, HasV6]> {
1694 let Inst{27-8} = 0b00110010000011110000;
1695 let Inst{7-0} = imm;
1698 def : InstAlias<"nop$p", (HINT 0, pred:$p)>, Requires<[IsARM, HasV6T2]>;
1699 def : InstAlias<"yield$p", (HINT 1, pred:$p)>, Requires<[IsARM, HasV6T2]>;
1700 def : InstAlias<"wfe$p", (HINT 2, pred:$p)>, Requires<[IsARM, HasV6T2]>;
1701 def : InstAlias<"wfi$p", (HINT 3, pred:$p)>, Requires<[IsARM, HasV6T2]>;
1702 def : InstAlias<"sev$p", (HINT 4, pred:$p)>, Requires<[IsARM, HasV6T2]>;
1703 def : InstAlias<"sevl$p", (HINT 5, pred:$p)>, Requires<[IsARM, HasV8]>;
1705 def : Pat<(int_arm_sevl), (HINT 5)>;
1707 def SEL : AI<(outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm), DPFrm, NoItinerary, "sel",
1708 "\t$Rd, $Rn, $Rm", []>, Requires<[IsARM, HasV6]> {
1713 let Inst{15-12} = Rd;
1714 let Inst{19-16} = Rn;
1715 let Inst{27-20} = 0b01101000;
1716 let Inst{7-4} = 0b1011;
1717 let Inst{11-8} = 0b1111;
1718 let Unpredictable{11-8} = 0b1111;
1721 // The 16-bit operand $val can be used by a debugger to store more information
1722 // about the breakpoint.
1723 def BKPT : AInoP<(outs), (ins imm0_65535:$val), MiscFrm, NoItinerary,
1724 "bkpt", "\t$val", []>, Requires<[IsARM]> {
1726 let Inst{3-0} = val{3-0};
1727 let Inst{19-8} = val{15-4};
1728 let Inst{27-20} = 0b00010010;
1729 let Inst{31-28} = 0xe; // AL
1730 let Inst{7-4} = 0b0111;
1732 // default immediate for breakpoint mnemonic
1733 def : InstAlias<"bkpt", (BKPT 0)>, Requires<[IsARM]>;
1735 def HLT : AInoP<(outs), (ins imm0_65535:$val), MiscFrm, NoItinerary,
1736 "hlt", "\t$val", []>, Requires<[IsARM, HasV8]> {
1738 let Inst{3-0} = val{3-0};
1739 let Inst{19-8} = val{15-4};
1740 let Inst{27-20} = 0b00010000;
1741 let Inst{31-28} = 0xe; // AL
1742 let Inst{7-4} = 0b0111;
1745 // Change Processor State
1746 // FIXME: We should use InstAlias to handle the optional operands.
1747 class CPS<dag iops, string asm_ops>
1748 : AXI<(outs), iops, MiscFrm, NoItinerary, !strconcat("cps", asm_ops),
1749 []>, Requires<[IsARM]> {
1755 let Inst{31-28} = 0b1111;
1756 let Inst{27-20} = 0b00010000;
1757 let Inst{19-18} = imod;
1758 let Inst{17} = M; // Enabled if mode is set;
1759 let Inst{16-9} = 0b00000000;
1760 let Inst{8-6} = iflags;
1762 let Inst{4-0} = mode;
1765 let DecoderMethod = "DecodeCPSInstruction" in {
1767 def CPS3p : CPS<(ins imod_op:$imod, iflags_op:$iflags, imm0_31:$mode),
1768 "$imod\t$iflags, $mode">;
1769 let mode = 0, M = 0 in
1770 def CPS2p : CPS<(ins imod_op:$imod, iflags_op:$iflags), "$imod\t$iflags">;
1772 let imod = 0, iflags = 0, M = 1 in
1773 def CPS1p : CPS<(ins imm0_31:$mode), "\t$mode">;
1776 // Preload signals the memory system of possible future data/instruction access.
1777 multiclass APreLoad<bits<1> read, bits<1> data, string opc> {
1779 def i12 : AXIM<(outs), (ins addrmode_imm12:$addr), AddrMode_i12, MiscFrm,
1780 IIC_Preload, !strconcat(opc, "\t$addr"),
1781 [(ARMPreload addrmode_imm12:$addr, (i32 read), (i32 data))]>,
1782 Sched<[WritePreLd]> {
1785 let Inst{31-26} = 0b111101;
1786 let Inst{25} = 0; // 0 for immediate form
1787 let Inst{24} = data;
1788 let Inst{23} = addr{12}; // U (add = ('U' == 1))
1789 let Inst{22} = read;
1790 let Inst{21-20} = 0b01;
1791 let Inst{19-16} = addr{16-13}; // Rn
1792 let Inst{15-12} = 0b1111;
1793 let Inst{11-0} = addr{11-0}; // imm12
1796 def rs : AXI<(outs), (ins ldst_so_reg:$shift), MiscFrm, IIC_Preload,
1797 !strconcat(opc, "\t$shift"),
1798 [(ARMPreload ldst_so_reg:$shift, (i32 read), (i32 data))]>,
1799 Sched<[WritePreLd]> {
1801 let Inst{31-26} = 0b111101;
1802 let Inst{25} = 1; // 1 for register form
1803 let Inst{24} = data;
1804 let Inst{23} = shift{12}; // U (add = ('U' == 1))
1805 let Inst{22} = read;
1806 let Inst{21-20} = 0b01;
1807 let Inst{19-16} = shift{16-13}; // Rn
1808 let Inst{15-12} = 0b1111;
1809 let Inst{11-0} = shift{11-0};
1814 defm PLD : APreLoad<1, 1, "pld">, Requires<[IsARM]>;
1815 defm PLDW : APreLoad<0, 1, "pldw">, Requires<[IsARM,HasV7,HasMP]>;
1816 defm PLI : APreLoad<1, 0, "pli">, Requires<[IsARM,HasV7]>;
1818 def SETEND : AXI<(outs), (ins setend_op:$end), MiscFrm, NoItinerary,
1819 "setend\t$end", []>, Requires<[IsARM]>, Deprecated<HasV8Ops> {
1821 let Inst{31-10} = 0b1111000100000001000000;
1826 def DBG : AI<(outs), (ins imm0_15:$opt), MiscFrm, NoItinerary, "dbg", "\t$opt",
1827 []>, Requires<[IsARM, HasV7]> {
1829 let Inst{27-4} = 0b001100100000111100001111;
1830 let Inst{3-0} = opt;
1834 * A5.4 Permanently UNDEFINED instructions.
1836 * For most targets use UDF #65006, for which the OS will generate SIGTRAP.
1837 * Other UDF encodings generate SIGILL.
1839 * NaCl's OS instead chooses an ARM UDF encoding that's also a UDF in Thumb.
1841 * 1110 0111 1111 iiii iiii iiii 1111 iiii
1843 * 1101 1110 iiii iiii
1844 * It uses the following encoding:
1845 * 1110 0111 1111 1110 1101 1110 1111 0000
1846 * - In ARM: UDF #60896;
1847 * - In Thumb: UDF #254 followed by a branch-to-self.
1849 let isBarrier = 1, isTerminator = 1 in
1850 def TRAPNaCl : AXI<(outs), (ins), MiscFrm, NoItinerary,
1852 Requires<[IsARM,UseNaClTrap]> {
1853 let Inst = 0xe7fedef0;
1855 let isBarrier = 1, isTerminator = 1 in
1856 def TRAP : AXI<(outs), (ins), MiscFrm, NoItinerary,
1858 Requires<[IsARM,DontUseNaClTrap]> {
1859 let Inst = 0xe7ffdefe;
1862 // Address computation and loads and stores in PIC mode.
1863 let isNotDuplicable = 1 in {
1864 def PICADD : ARMPseudoInst<(outs GPR:$dst), (ins GPR:$a, pclabel:$cp, pred:$p),
1866 [(set GPR:$dst, (ARMpic_add GPR:$a, imm:$cp))]>,
1867 Sched<[WriteALU, ReadALU]>;
1869 let AddedComplexity = 10 in {
1870 def PICLDR : ARMPseudoInst<(outs GPR:$dst), (ins addrmodepc:$addr, pred:$p),
1872 [(set GPR:$dst, (load addrmodepc:$addr))]>;
1874 def PICLDRH : ARMPseudoInst<(outs GPR:$Rt), (ins addrmodepc:$addr, pred:$p),
1876 [(set GPR:$Rt, (zextloadi16 addrmodepc:$addr))]>;
1878 def PICLDRB : ARMPseudoInst<(outs GPR:$Rt), (ins addrmodepc:$addr, pred:$p),
1880 [(set GPR:$Rt, (zextloadi8 addrmodepc:$addr))]>;
1882 def PICLDRSH : ARMPseudoInst<(outs GPR:$Rt), (ins addrmodepc:$addr, pred:$p),
1884 [(set GPR:$Rt, (sextloadi16 addrmodepc:$addr))]>;
1886 def PICLDRSB : ARMPseudoInst<(outs GPR:$Rt), (ins addrmodepc:$addr, pred:$p),
1888 [(set GPR:$Rt, (sextloadi8 addrmodepc:$addr))]>;
1890 let AddedComplexity = 10 in {
1891 def PICSTR : ARMPseudoInst<(outs), (ins GPR:$src, addrmodepc:$addr, pred:$p),
1892 4, IIC_iStore_r, [(store GPR:$src, addrmodepc:$addr)]>;
1894 def PICSTRH : ARMPseudoInst<(outs), (ins GPR:$src, addrmodepc:$addr, pred:$p),
1895 4, IIC_iStore_bh_r, [(truncstorei16 GPR:$src,
1896 addrmodepc:$addr)]>;
1898 def PICSTRB : ARMPseudoInst<(outs), (ins GPR:$src, addrmodepc:$addr, pred:$p),
1899 4, IIC_iStore_bh_r, [(truncstorei8 GPR:$src, addrmodepc:$addr)]>;
1901 } // isNotDuplicable = 1
1904 // LEApcrel - Load a pc-relative address into a register without offending the
1906 let neverHasSideEffects = 1, isReMaterializable = 1 in
1907 // The 'adr' mnemonic encodes differently if the label is before or after
1908 // the instruction. The {24-21} opcode bits are set by the fixup, as we don't
1909 // know until then which form of the instruction will be used.
1910 def ADR : AI1<{0,?,?,0}, (outs GPR:$Rd), (ins adrlabel:$label),
1911 MiscFrm, IIC_iALUi, "adr", "\t$Rd, $label", []>,
1912 Sched<[WriteALU, ReadALU]> {
1915 let Inst{27-25} = 0b001;
1917 let Inst{23-22} = label{13-12};
1920 let Inst{19-16} = 0b1111;
1921 let Inst{15-12} = Rd;
1922 let Inst{11-0} = label{11-0};
1925 let hasSideEffects = 1 in {
1926 def LEApcrel : ARMPseudoInst<(outs GPR:$Rd), (ins i32imm:$label, pred:$p),
1927 4, IIC_iALUi, []>, Sched<[WriteALU, ReadALU]>;
1929 def LEApcrelJT : ARMPseudoInst<(outs GPR:$Rd),
1930 (ins i32imm:$label, nohash_imm:$id, pred:$p),
1931 4, IIC_iALUi, []>, Sched<[WriteALU, ReadALU]>;
1934 //===----------------------------------------------------------------------===//
1935 // Control Flow Instructions.
1938 let isReturn = 1, isTerminator = 1, isBarrier = 1 in {
1940 def BX_RET : AI<(outs), (ins), BrMiscFrm, IIC_Br,
1941 "bx", "\tlr", [(ARMretflag)]>,
1942 Requires<[IsARM, HasV4T]>, Sched<[WriteBr]> {
1943 let Inst{27-0} = 0b0001001011111111111100011110;
1947 def MOVPCLR : AI<(outs), (ins), BrMiscFrm, IIC_Br,
1948 "mov", "\tpc, lr", [(ARMretflag)]>,
1949 Requires<[IsARM, NoV4T]>, Sched<[WriteBr]> {
1950 let Inst{27-0} = 0b0001101000001111000000001110;
1953 // Exception return: N.b. doesn't set CPSR as far as we're concerned (it sets
1954 // the user-space one).
1955 def SUBS_PC_LR : ARMPseudoInst<(outs), (ins i32imm:$offset, pred:$p),
1957 [(ARMintretflag imm:$offset)]>;
1960 // Indirect branches
1961 let isBranch = 1, isTerminator = 1, isBarrier = 1, isIndirectBranch = 1 in {
1963 def BX : AXI<(outs), (ins GPR:$dst), BrMiscFrm, IIC_Br, "bx\t$dst",
1964 [(brind GPR:$dst)]>,
1965 Requires<[IsARM, HasV4T]>, Sched<[WriteBr]> {
1967 let Inst{31-4} = 0b1110000100101111111111110001;
1968 let Inst{3-0} = dst;
1971 def BX_pred : AI<(outs), (ins GPR:$dst), BrMiscFrm, IIC_Br,
1972 "bx", "\t$dst", [/* pattern left blank */]>,
1973 Requires<[IsARM, HasV4T]>, Sched<[WriteBr]> {
1975 let Inst{27-4} = 0b000100101111111111110001;
1976 let Inst{3-0} = dst;
1980 // SP is marked as a use to prevent stack-pointer assignments that appear
1981 // immediately before calls from potentially appearing dead.
1983 // FIXME: Do we really need a non-predicated version? If so, it should
1984 // at least be a pseudo instruction expanding to the predicated version
1985 // at MC lowering time.
1986 Defs = [LR], Uses = [SP] in {
1987 def BL : ABXI<0b1011, (outs), (ins bl_target:$func),
1988 IIC_Br, "bl\t$func",
1989 [(ARMcall tglobaladdr:$func)]>,
1990 Requires<[IsARM]>, Sched<[WriteBrL]> {
1991 let Inst{31-28} = 0b1110;
1993 let Inst{23-0} = func;
1994 let DecoderMethod = "DecodeBranchImmInstruction";
1997 def BL_pred : ABI<0b1011, (outs), (ins bl_target:$func),
1998 IIC_Br, "bl", "\t$func",
1999 [(ARMcall_pred tglobaladdr:$func)]>,
2000 Requires<[IsARM]>, Sched<[WriteBrL]> {
2002 let Inst{23-0} = func;
2003 let DecoderMethod = "DecodeBranchImmInstruction";
2007 def BLX : AXI<(outs), (ins GPR:$func), BrMiscFrm,
2008 IIC_Br, "blx\t$func",
2009 [(ARMcall GPR:$func)]>,
2010 Requires<[IsARM, HasV5T]>, Sched<[WriteBrL]> {
2012 let Inst{31-4} = 0b1110000100101111111111110011;
2013 let Inst{3-0} = func;
2016 def BLX_pred : AI<(outs), (ins GPR:$func), BrMiscFrm,
2017 IIC_Br, "blx", "\t$func",
2018 [(ARMcall_pred GPR:$func)]>,
2019 Requires<[IsARM, HasV5T]>, Sched<[WriteBrL]> {
2021 let Inst{27-4} = 0b000100101111111111110011;
2022 let Inst{3-0} = func;
2026 // Note: Restrict $func to the tGPR regclass to prevent it being in LR.
2027 def BX_CALL : ARMPseudoInst<(outs), (ins tGPR:$func),
2028 8, IIC_Br, [(ARMcall_nolink tGPR:$func)]>,
2029 Requires<[IsARM, HasV4T]>, Sched<[WriteBr]>;
2032 def BMOVPCRX_CALL : ARMPseudoInst<(outs), (ins tGPR:$func),
2033 8, IIC_Br, [(ARMcall_nolink tGPR:$func)]>,
2034 Requires<[IsARM, NoV4T]>, Sched<[WriteBr]>;
2036 // mov lr, pc; b if callee is marked noreturn to avoid confusing the
2037 // return stack predictor.
2038 def BMOVPCB_CALL : ARMPseudoInst<(outs), (ins bl_target:$func),
2039 8, IIC_Br, [(ARMcall_nolink tglobaladdr:$func)]>,
2040 Requires<[IsARM]>, Sched<[WriteBr]>;
2043 let isBranch = 1, isTerminator = 1 in {
2044 // FIXME: should be able to write a pattern for ARMBrcond, but can't use
2045 // a two-value operand where a dag node expects two operands. :(
2046 def Bcc : ABI<0b1010, (outs), (ins br_target:$target),
2047 IIC_Br, "b", "\t$target",
2048 [/*(ARMbrcond bb:$target, imm:$cc, CCR:$ccr)*/]>,
2051 let Inst{23-0} = target;
2052 let DecoderMethod = "DecodeBranchImmInstruction";
2055 let isBarrier = 1 in {
2056 // B is "predicable" since it's just a Bcc with an 'always' condition.
2057 let isPredicable = 1 in
2058 // FIXME: We shouldn't need this pseudo at all. Just using Bcc directly
2059 // should be sufficient.
2060 // FIXME: Is B really a Barrier? That doesn't seem right.
2061 def B : ARMPseudoExpand<(outs), (ins br_target:$target), 4, IIC_Br,
2062 [(br bb:$target)], (Bcc br_target:$target, (ops 14, zero_reg))>,
2065 let isNotDuplicable = 1, isIndirectBranch = 1 in {
2066 def BR_JTr : ARMPseudoInst<(outs),
2067 (ins GPR:$target, i32imm:$jt, i32imm:$id),
2069 [(ARMbrjt GPR:$target, tjumptable:$jt, imm:$id)]>,
2071 // FIXME: This shouldn't use the generic "addrmode2," but rather be split
2072 // into i12 and rs suffixed versions.
2073 def BR_JTm : ARMPseudoInst<(outs),
2074 (ins addrmode2:$target, i32imm:$jt, i32imm:$id),
2076 [(ARMbrjt (i32 (load addrmode2:$target)), tjumptable:$jt,
2077 imm:$id)]>, Sched<[WriteBrTbl]>;
2078 def BR_JTadd : ARMPseudoInst<(outs),
2079 (ins GPR:$target, GPR:$idx, i32imm:$jt, i32imm:$id),
2081 [(ARMbrjt (add GPR:$target, GPR:$idx), tjumptable:$jt,
2082 imm:$id)]>, Sched<[WriteBrTbl]>;
2083 } // isNotDuplicable = 1, isIndirectBranch = 1
2089 def BLXi : AXI<(outs), (ins blx_target:$target), BrMiscFrm, NoItinerary,
2090 "blx\t$target", []>,
2091 Requires<[IsARM, HasV5T]>, Sched<[WriteBrL]> {
2092 let Inst{31-25} = 0b1111101;
2094 let Inst{23-0} = target{24-1};
2095 let Inst{24} = target{0};
2098 // Branch and Exchange Jazelle
2099 def BXJ : ABI<0b0001, (outs), (ins GPR:$func), NoItinerary, "bxj", "\t$func",
2100 [/* pattern left blank */]>, Sched<[WriteBr]> {
2102 let Inst{23-20} = 0b0010;
2103 let Inst{19-8} = 0xfff;
2104 let Inst{7-4} = 0b0010;
2105 let Inst{3-0} = func;
2110 let isCall = 1, isTerminator = 1, isReturn = 1, isBarrier = 1, Uses = [SP] in {
2111 def TCRETURNdi : PseudoInst<(outs), (ins i32imm:$dst), IIC_Br, []>,
2114 def TCRETURNri : PseudoInst<(outs), (ins tcGPR:$dst), IIC_Br, []>,
2117 def TAILJMPd : ARMPseudoExpand<(outs), (ins br_target:$dst),
2119 (Bcc br_target:$dst, (ops 14, zero_reg))>,
2120 Requires<[IsARM]>, Sched<[WriteBr]>;
2122 def TAILJMPr : ARMPseudoExpand<(outs), (ins tcGPR:$dst),
2124 (BX GPR:$dst)>, Sched<[WriteBr]>,
2128 // Secure Monitor Call is a system instruction.
2129 def SMC : ABI<0b0001, (outs), (ins imm0_15:$opt), NoItinerary, "smc", "\t$opt",
2130 []>, Requires<[IsARM, HasTrustZone]> {
2132 let Inst{23-4} = 0b01100000000000000111;
2133 let Inst{3-0} = opt;
2136 // Supervisor Call (Software Interrupt)
2137 let isCall = 1, Uses = [SP] in {
2138 def SVC : ABI<0b1111, (outs), (ins imm24b:$svc), IIC_Br, "svc", "\t$svc", []>,
2141 let Inst{23-0} = svc;
2145 // Store Return State
2146 class SRSI<bit wb, string asm>
2147 : XI<(outs), (ins imm0_31:$mode), AddrModeNone, 4, IndexModeNone, BrFrm,
2148 NoItinerary, asm, "", []> {
2150 let Inst{31-28} = 0b1111;
2151 let Inst{27-25} = 0b100;
2155 let Inst{19-16} = 0b1101; // SP
2156 let Inst{15-5} = 0b00000101000;
2157 let Inst{4-0} = mode;
2160 def SRSDA : SRSI<0, "srsda\tsp, $mode"> {
2161 let Inst{24-23} = 0;
2163 def SRSDA_UPD : SRSI<1, "srsda\tsp!, $mode"> {
2164 let Inst{24-23} = 0;
2166 def SRSDB : SRSI<0, "srsdb\tsp, $mode"> {
2167 let Inst{24-23} = 0b10;
2169 def SRSDB_UPD : SRSI<1, "srsdb\tsp!, $mode"> {
2170 let Inst{24-23} = 0b10;
2172 def SRSIA : SRSI<0, "srsia\tsp, $mode"> {
2173 let Inst{24-23} = 0b01;
2175 def SRSIA_UPD : SRSI<1, "srsia\tsp!, $mode"> {
2176 let Inst{24-23} = 0b01;
2178 def SRSIB : SRSI<0, "srsib\tsp, $mode"> {
2179 let Inst{24-23} = 0b11;
2181 def SRSIB_UPD : SRSI<1, "srsib\tsp!, $mode"> {
2182 let Inst{24-23} = 0b11;
2185 def : ARMInstAlias<"srsda $mode", (SRSDA imm0_31:$mode)>;
2186 def : ARMInstAlias<"srsda $mode!", (SRSDA_UPD imm0_31:$mode)>;
2188 def : ARMInstAlias<"srsdb $mode", (SRSDB imm0_31:$mode)>;
2189 def : ARMInstAlias<"srsdb $mode!", (SRSDB_UPD imm0_31:$mode)>;
2191 def : ARMInstAlias<"srsia $mode", (SRSIA imm0_31:$mode)>;
2192 def : ARMInstAlias<"srsia $mode!", (SRSIA_UPD imm0_31:$mode)>;
2194 def : ARMInstAlias<"srsib $mode", (SRSIB imm0_31:$mode)>;
2195 def : ARMInstAlias<"srsib $mode!", (SRSIB_UPD imm0_31:$mode)>;
2197 // Return From Exception
2198 class RFEI<bit wb, string asm>
2199 : XI<(outs), (ins GPR:$Rn), AddrModeNone, 4, IndexModeNone, BrFrm,
2200 NoItinerary, asm, "", []> {
2202 let Inst{31-28} = 0b1111;
2203 let Inst{27-25} = 0b100;
2207 let Inst{19-16} = Rn;
2208 let Inst{15-0} = 0xa00;
2211 def RFEDA : RFEI<0, "rfeda\t$Rn"> {
2212 let Inst{24-23} = 0;
2214 def RFEDA_UPD : RFEI<1, "rfeda\t$Rn!"> {
2215 let Inst{24-23} = 0;
2217 def RFEDB : RFEI<0, "rfedb\t$Rn"> {
2218 let Inst{24-23} = 0b10;
2220 def RFEDB_UPD : RFEI<1, "rfedb\t$Rn!"> {
2221 let Inst{24-23} = 0b10;
2223 def RFEIA : RFEI<0, "rfeia\t$Rn"> {
2224 let Inst{24-23} = 0b01;
2226 def RFEIA_UPD : RFEI<1, "rfeia\t$Rn!"> {
2227 let Inst{24-23} = 0b01;
2229 def RFEIB : RFEI<0, "rfeib\t$Rn"> {
2230 let Inst{24-23} = 0b11;
2232 def RFEIB_UPD : RFEI<1, "rfeib\t$Rn!"> {
2233 let Inst{24-23} = 0b11;
2236 //===----------------------------------------------------------------------===//
2237 // Load / Store Instructions.
2243 defm LDR : AI_ldr1<0, "ldr", IIC_iLoad_r, IIC_iLoad_si,
2244 UnOpFrag<(load node:$Src)>>;
2245 defm LDRB : AI_ldr1nopc<1, "ldrb", IIC_iLoad_bh_r, IIC_iLoad_bh_si,
2246 UnOpFrag<(zextloadi8 node:$Src)>>;
2247 defm STR : AI_str1<0, "str", IIC_iStore_r, IIC_iStore_si,
2248 BinOpFrag<(store node:$LHS, node:$RHS)>>;
2249 defm STRB : AI_str1nopc<1, "strb", IIC_iStore_bh_r, IIC_iStore_bh_si,
2250 BinOpFrag<(truncstorei8 node:$LHS, node:$RHS)>>;
2252 // Special LDR for loads from non-pc-relative constpools.
2253 let canFoldAsLoad = 1, mayLoad = 1, neverHasSideEffects = 1,
2254 isReMaterializable = 1, isCodeGenOnly = 1 in
2255 def LDRcp : AI2ldst<0b010, 1, 0, (outs GPR:$Rt), (ins addrmode_imm12:$addr),
2256 AddrMode_i12, LdFrm, IIC_iLoad_r, "ldr", "\t$Rt, $addr",
2260 let Inst{23} = addr{12}; // U (add = ('U' == 1))
2261 let Inst{19-16} = 0b1111;
2262 let Inst{15-12} = Rt;
2263 let Inst{11-0} = addr{11-0}; // imm12
2266 // Loads with zero extension
2267 def LDRH : AI3ld<0b1011, 1, (outs GPR:$Rt), (ins addrmode3:$addr), LdMiscFrm,
2268 IIC_iLoad_bh_r, "ldrh", "\t$Rt, $addr",
2269 [(set GPR:$Rt, (zextloadi16 addrmode3:$addr))]>;
2271 // Loads with sign extension
2272 def LDRSH : AI3ld<0b1111, 1, (outs GPR:$Rt), (ins addrmode3:$addr), LdMiscFrm,
2273 IIC_iLoad_bh_r, "ldrsh", "\t$Rt, $addr",
2274 [(set GPR:$Rt, (sextloadi16 addrmode3:$addr))]>;
2276 def LDRSB : AI3ld<0b1101, 1, (outs GPR:$Rt), (ins addrmode3:$addr), LdMiscFrm,
2277 IIC_iLoad_bh_r, "ldrsb", "\t$Rt, $addr",
2278 [(set GPR:$Rt, (sextloadi8 addrmode3:$addr))]>;
2280 let mayLoad = 1, neverHasSideEffects = 1, hasExtraDefRegAllocReq = 1 in {
2282 def LDRD : AI3ld<0b1101, 0, (outs GPR:$Rt, GPR:$Rt2), (ins addrmode3:$addr),
2283 LdMiscFrm, IIC_iLoad_d_r, "ldrd", "\t$Rt, $Rt2, $addr", []>,
2284 Requires<[IsARM, HasV5TE]>;
2287 def LDA : AIldracq<0b00, (outs GPR:$Rt), (ins addr_offset_none:$addr),
2288 NoItinerary, "lda", "\t$Rt, $addr", []>;
2289 def LDAB : AIldracq<0b10, (outs GPR:$Rt), (ins addr_offset_none:$addr),
2290 NoItinerary, "ldab", "\t$Rt, $addr", []>;
2291 def LDAH : AIldracq<0b11, (outs GPR:$Rt), (ins addr_offset_none:$addr),
2292 NoItinerary, "ldah", "\t$Rt, $addr", []>;
2295 multiclass AI2_ldridx<bit isByte, string opc,
2296 InstrItinClass iii, InstrItinClass iir> {
2297 def _PRE_IMM : AI2ldstidx<1, isByte, 1, (outs GPR:$Rt, GPR:$Rn_wb),
2298 (ins addrmode_imm12_pre:$addr), IndexModePre, LdFrm, iii,
2299 opc, "\t$Rt, $addr!", "$addr.base = $Rn_wb", []> {
2302 let Inst{23} = addr{12};
2303 let Inst{19-16} = addr{16-13};
2304 let Inst{11-0} = addr{11-0};
2305 let DecoderMethod = "DecodeLDRPreImm";
2308 def _PRE_REG : AI2ldstidx<1, isByte, 1, (outs GPR:$Rt, GPR:$Rn_wb),
2309 (ins ldst_so_reg:$addr), IndexModePre, LdFrm, iir,
2310 opc, "\t$Rt, $addr!", "$addr.base = $Rn_wb", []> {
2313 let Inst{23} = addr{12};
2314 let Inst{19-16} = addr{16-13};
2315 let Inst{11-0} = addr{11-0};
2317 let DecoderMethod = "DecodeLDRPreReg";
2320 def _POST_REG : AI2ldstidx<1, isByte, 0, (outs GPR:$Rt, GPR:$Rn_wb),
2321 (ins addr_offset_none:$addr, am2offset_reg:$offset),
2322 IndexModePost, LdFrm, iir,
2323 opc, "\t$Rt, $addr, $offset",
2324 "$addr.base = $Rn_wb", []> {
2330 let Inst{23} = offset{12};
2331 let Inst{19-16} = addr;
2332 let Inst{11-0} = offset{11-0};
2335 let DecoderMethod = "DecodeAddrMode2IdxInstruction";
2338 def _POST_IMM : AI2ldstidx<1, isByte, 0, (outs GPR:$Rt, GPR:$Rn_wb),
2339 (ins addr_offset_none:$addr, am2offset_imm:$offset),
2340 IndexModePost, LdFrm, iii,
2341 opc, "\t$Rt, $addr, $offset",
2342 "$addr.base = $Rn_wb", []> {
2348 let Inst{23} = offset{12};
2349 let Inst{19-16} = addr;
2350 let Inst{11-0} = offset{11-0};
2352 let DecoderMethod = "DecodeAddrMode2IdxInstruction";
2357 let mayLoad = 1, neverHasSideEffects = 1 in {
2358 // FIXME: for LDR_PRE_REG etc. the itineray should be either IIC_iLoad_ru or
2359 // IIC_iLoad_siu depending on whether it the offset register is shifted.
2360 defm LDR : AI2_ldridx<0, "ldr", IIC_iLoad_iu, IIC_iLoad_ru>;
2361 defm LDRB : AI2_ldridx<1, "ldrb", IIC_iLoad_bh_iu, IIC_iLoad_bh_ru>;
2364 multiclass AI3_ldridx<bits<4> op, string opc, InstrItinClass itin> {
2365 def _PRE : AI3ldstidx<op, 1, 1, (outs GPR:$Rt, GPR:$Rn_wb),
2366 (ins addrmode3_pre:$addr), IndexModePre,
2368 opc, "\t$Rt, $addr!", "$addr.base = $Rn_wb", []> {
2370 let Inst{23} = addr{8}; // U bit
2371 let Inst{22} = addr{13}; // 1 == imm8, 0 == Rm
2372 let Inst{19-16} = addr{12-9}; // Rn
2373 let Inst{11-8} = addr{7-4}; // imm7_4/zero
2374 let Inst{3-0} = addr{3-0}; // imm3_0/Rm
2375 let DecoderMethod = "DecodeAddrMode3Instruction";
2377 def _POST : AI3ldstidx<op, 1, 0, (outs GPR:$Rt, GPR:$Rn_wb),
2378 (ins addr_offset_none:$addr, am3offset:$offset),
2379 IndexModePost, LdMiscFrm, itin,
2380 opc, "\t$Rt, $addr, $offset", "$addr.base = $Rn_wb",
2384 let Inst{23} = offset{8}; // U bit
2385 let Inst{22} = offset{9}; // 1 == imm8, 0 == Rm
2386 let Inst{19-16} = addr;
2387 let Inst{11-8} = offset{7-4}; // imm7_4/zero
2388 let Inst{3-0} = offset{3-0}; // imm3_0/Rm
2389 let DecoderMethod = "DecodeAddrMode3Instruction";
2393 let mayLoad = 1, neverHasSideEffects = 1 in {
2394 defm LDRH : AI3_ldridx<0b1011, "ldrh", IIC_iLoad_bh_ru>;
2395 defm LDRSH : AI3_ldridx<0b1111, "ldrsh", IIC_iLoad_bh_ru>;
2396 defm LDRSB : AI3_ldridx<0b1101, "ldrsb", IIC_iLoad_bh_ru>;
2397 let hasExtraDefRegAllocReq = 1 in {
2398 def LDRD_PRE : AI3ldstidx<0b1101, 0, 1, (outs GPR:$Rt, GPR:$Rt2, GPR:$Rn_wb),
2399 (ins addrmode3_pre:$addr), IndexModePre,
2400 LdMiscFrm, IIC_iLoad_d_ru,
2401 "ldrd", "\t$Rt, $Rt2, $addr!",
2402 "$addr.base = $Rn_wb", []> {
2404 let Inst{23} = addr{8}; // U bit
2405 let Inst{22} = addr{13}; // 1 == imm8, 0 == Rm
2406 let Inst{19-16} = addr{12-9}; // Rn
2407 let Inst{11-8} = addr{7-4}; // imm7_4/zero
2408 let Inst{3-0} = addr{3-0}; // imm3_0/Rm
2409 let DecoderMethod = "DecodeAddrMode3Instruction";
2411 def LDRD_POST: AI3ldstidx<0b1101, 0, 0, (outs GPR:$Rt, GPR:$Rt2, GPR:$Rn_wb),
2412 (ins addr_offset_none:$addr, am3offset:$offset),
2413 IndexModePost, LdMiscFrm, IIC_iLoad_d_ru,
2414 "ldrd", "\t$Rt, $Rt2, $addr, $offset",
2415 "$addr.base = $Rn_wb", []> {
2418 let Inst{23} = offset{8}; // U bit
2419 let Inst{22} = offset{9}; // 1 == imm8, 0 == Rm
2420 let Inst{19-16} = addr;
2421 let Inst{11-8} = offset{7-4}; // imm7_4/zero
2422 let Inst{3-0} = offset{3-0}; // imm3_0/Rm
2423 let DecoderMethod = "DecodeAddrMode3Instruction";
2425 } // hasExtraDefRegAllocReq = 1
2426 } // mayLoad = 1, neverHasSideEffects = 1
2428 // LDRT, LDRBT, LDRSBT, LDRHT, LDRSHT.
2429 let mayLoad = 1, neverHasSideEffects = 1 in {
2430 def LDRT_POST_REG : AI2ldstidx<1, 0, 0, (outs GPR:$Rt, GPR:$Rn_wb),
2431 (ins addr_offset_none:$addr, am2offset_reg:$offset),
2432 IndexModePost, LdFrm, IIC_iLoad_ru,
2433 "ldrt", "\t$Rt, $addr, $offset",
2434 "$addr.base = $Rn_wb", []> {
2440 let Inst{23} = offset{12};
2441 let Inst{21} = 1; // overwrite
2442 let Inst{19-16} = addr;
2443 let Inst{11-5} = offset{11-5};
2445 let Inst{3-0} = offset{3-0};
2446 let DecoderMethod = "DecodeAddrMode2IdxInstruction";
2450 : AI2ldstidx<1, 0, 0, (outs GPR:$Rt, GPR:$Rn_wb),
2451 (ins addr_offset_none:$addr, am2offset_imm:$offset),
2452 IndexModePost, LdFrm, IIC_iLoad_ru,
2453 "ldrt", "\t$Rt, $addr, $offset", "$addr.base = $Rn_wb", []> {
2459 let Inst{23} = offset{12};
2460 let Inst{21} = 1; // overwrite
2461 let Inst{19-16} = addr;
2462 let Inst{11-0} = offset{11-0};
2463 let DecoderMethod = "DecodeAddrMode2IdxInstruction";
2466 def LDRBT_POST_REG : AI2ldstidx<1, 1, 0, (outs GPR:$Rt, GPR:$Rn_wb),
2467 (ins addr_offset_none:$addr, am2offset_reg:$offset),
2468 IndexModePost, LdFrm, IIC_iLoad_bh_ru,
2469 "ldrbt", "\t$Rt, $addr, $offset",
2470 "$addr.base = $Rn_wb", []> {
2476 let Inst{23} = offset{12};
2477 let Inst{21} = 1; // overwrite
2478 let Inst{19-16} = addr;
2479 let Inst{11-5} = offset{11-5};
2481 let Inst{3-0} = offset{3-0};
2482 let DecoderMethod = "DecodeAddrMode2IdxInstruction";
2486 : AI2ldstidx<1, 1, 0, (outs GPR:$Rt, GPR:$Rn_wb),
2487 (ins addr_offset_none:$addr, am2offset_imm:$offset),
2488 IndexModePost, LdFrm, IIC_iLoad_bh_ru,
2489 "ldrbt", "\t$Rt, $addr, $offset", "$addr.base = $Rn_wb", []> {
2495 let Inst{23} = offset{12};
2496 let Inst{21} = 1; // overwrite
2497 let Inst{19-16} = addr;
2498 let Inst{11-0} = offset{11-0};
2499 let DecoderMethod = "DecodeAddrMode2IdxInstruction";
2502 multiclass AI3ldrT<bits<4> op, string opc> {
2503 def i : AI3ldstidxT<op, 1, (outs GPR:$Rt, GPR:$base_wb),
2504 (ins addr_offset_none:$addr, postidx_imm8:$offset),
2505 IndexModePost, LdMiscFrm, IIC_iLoad_bh_ru, opc,
2506 "\t$Rt, $addr, $offset", "$addr.base = $base_wb", []> {
2508 let Inst{23} = offset{8};
2510 let Inst{11-8} = offset{7-4};
2511 let Inst{3-0} = offset{3-0};
2513 def r : AI3ldstidxT<op, 1, (outs GPRnopc:$Rt, GPRnopc:$base_wb),
2514 (ins addr_offset_none:$addr, postidx_reg:$Rm),
2515 IndexModePost, LdMiscFrm, IIC_iLoad_bh_ru, opc,
2516 "\t$Rt, $addr, $Rm", "$addr.base = $base_wb", []> {
2518 let Inst{23} = Rm{4};
2521 let Unpredictable{11-8} = 0b1111;
2522 let Inst{3-0} = Rm{3-0};
2523 let DecoderMethod = "DecodeLDR";
2527 defm LDRSBT : AI3ldrT<0b1101, "ldrsbt">;
2528 defm LDRHT : AI3ldrT<0b1011, "ldrht">;
2529 defm LDRSHT : AI3ldrT<0b1111, "ldrsht">;
2533 : ARMAsmPseudo<"ldrt${q} $Rt, $addr", (ins addr_offset_none:$addr, pred:$q),
2537 : ARMAsmPseudo<"ldrbt${q} $Rt, $addr", (ins addr_offset_none:$addr, pred:$q),
2542 // Stores with truncate
2543 def STRH : AI3str<0b1011, (outs), (ins GPR:$Rt, addrmode3:$addr), StMiscFrm,
2544 IIC_iStore_bh_r, "strh", "\t$Rt, $addr",
2545 [(truncstorei16 GPR:$Rt, addrmode3:$addr)]>;
2548 let mayStore = 1, neverHasSideEffects = 1, hasExtraSrcRegAllocReq = 1 in {
2549 def STRD : AI3str<0b1111, (outs), (ins GPR:$Rt, GPR:$Rt2, addrmode3:$addr),
2550 StMiscFrm, IIC_iStore_d_r, "strd", "\t$Rt, $Rt2, $addr", []>,
2551 Requires<[IsARM, HasV5TE]> {
2557 multiclass AI2_stridx<bit isByte, string opc,
2558 InstrItinClass iii, InstrItinClass iir> {
2559 def _PRE_IMM : AI2ldstidx<0, isByte, 1, (outs GPR:$Rn_wb),
2560 (ins GPR:$Rt, addrmode_imm12_pre:$addr), IndexModePre,
2562 opc, "\t$Rt, $addr!", "$addr.base = $Rn_wb", []> {
2565 let Inst{23} = addr{12}; // U (add = ('U' == 1))
2566 let Inst{19-16} = addr{16-13}; // Rn
2567 let Inst{11-0} = addr{11-0}; // imm12
2568 let DecoderMethod = "DecodeSTRPreImm";
2571 def _PRE_REG : AI2ldstidx<0, isByte, 1, (outs GPR:$Rn_wb),
2572 (ins GPR:$Rt, ldst_so_reg:$addr),
2573 IndexModePre, StFrm, iir,
2574 opc, "\t$Rt, $addr!", "$addr.base = $Rn_wb", []> {
2577 let Inst{23} = addr{12}; // U (add = ('U' == 1))
2578 let Inst{19-16} = addr{16-13}; // Rn
2579 let Inst{11-0} = addr{11-0};
2580 let Inst{4} = 0; // Inst{4} = 0
2581 let DecoderMethod = "DecodeSTRPreReg";
2583 def _POST_REG : AI2ldstidx<0, isByte, 0, (outs GPR:$Rn_wb),
2584 (ins GPR:$Rt, addr_offset_none:$addr, am2offset_reg:$offset),
2585 IndexModePost, StFrm, iir,
2586 opc, "\t$Rt, $addr, $offset",
2587 "$addr.base = $Rn_wb", []> {
2593 let Inst{23} = offset{12};
2594 let Inst{19-16} = addr;
2595 let Inst{11-0} = offset{11-0};
2598 let DecoderMethod = "DecodeAddrMode2IdxInstruction";
2601 def _POST_IMM : AI2ldstidx<0, isByte, 0, (outs GPR:$Rn_wb),
2602 (ins GPR:$Rt, addr_offset_none:$addr, am2offset_imm:$offset),
2603 IndexModePost, StFrm, iii,
2604 opc, "\t$Rt, $addr, $offset",
2605 "$addr.base = $Rn_wb", []> {
2611 let Inst{23} = offset{12};
2612 let Inst{19-16} = addr;
2613 let Inst{11-0} = offset{11-0};
2615 let DecoderMethod = "DecodeAddrMode2IdxInstruction";
2619 let mayStore = 1, neverHasSideEffects = 1 in {
2620 // FIXME: for STR_PRE_REG etc. the itineray should be either IIC_iStore_ru or
2621 // IIC_iStore_siu depending on whether it the offset register is shifted.
2622 defm STR : AI2_stridx<0, "str", IIC_iStore_iu, IIC_iStore_ru>;
2623 defm STRB : AI2_stridx<1, "strb", IIC_iStore_bh_iu, IIC_iStore_bh_ru>;
2626 def : ARMPat<(post_store GPR:$Rt, addr_offset_none:$addr,
2627 am2offset_reg:$offset),
2628 (STR_POST_REG GPR:$Rt, addr_offset_none:$addr,
2629 am2offset_reg:$offset)>;
2630 def : ARMPat<(post_store GPR:$Rt, addr_offset_none:$addr,
2631 am2offset_imm:$offset),
2632 (STR_POST_IMM GPR:$Rt, addr_offset_none:$addr,
2633 am2offset_imm:$offset)>;
2634 def : ARMPat<(post_truncsti8 GPR:$Rt, addr_offset_none:$addr,
2635 am2offset_reg:$offset),
2636 (STRB_POST_REG GPR:$Rt, addr_offset_none:$addr,
2637 am2offset_reg:$offset)>;
2638 def : ARMPat<(post_truncsti8 GPR:$Rt, addr_offset_none:$addr,
2639 am2offset_imm:$offset),
2640 (STRB_POST_IMM GPR:$Rt, addr_offset_none:$addr,
2641 am2offset_imm:$offset)>;
2643 // Pseudo-instructions for pattern matching the pre-indexed stores. We can't
2644 // put the patterns on the instruction definitions directly as ISel wants
2645 // the address base and offset to be separate operands, not a single
2646 // complex operand like we represent the instructions themselves. The
2647 // pseudos map between the two.
2648 let usesCustomInserter = 1,
2649 Constraints = "$Rn = $Rn_wb,@earlyclobber $Rn_wb" in {
2650 def STRi_preidx: ARMPseudoInst<(outs GPR:$Rn_wb),
2651 (ins GPR:$Rt, GPR:$Rn, am2offset_imm:$offset, pred:$p),
2654 (pre_store GPR:$Rt, GPR:$Rn, am2offset_imm:$offset))]>;
2655 def STRr_preidx: ARMPseudoInst<(outs GPR:$Rn_wb),
2656 (ins GPR:$Rt, GPR:$Rn, am2offset_reg:$offset, pred:$p),
2659 (pre_store GPR:$Rt, GPR:$Rn, am2offset_reg:$offset))]>;
2660 def STRBi_preidx: ARMPseudoInst<(outs GPR:$Rn_wb),
2661 (ins GPR:$Rt, GPR:$Rn, am2offset_imm:$offset, pred:$p),
2664 (pre_truncsti8 GPR:$Rt, GPR:$Rn, am2offset_imm:$offset))]>;
2665 def STRBr_preidx: ARMPseudoInst<(outs GPR:$Rn_wb),
2666 (ins GPR:$Rt, GPR:$Rn, am2offset_reg:$offset, pred:$p),
2669 (pre_truncsti8 GPR:$Rt, GPR:$Rn, am2offset_reg:$offset))]>;
2670 def STRH_preidx: ARMPseudoInst<(outs GPR:$Rn_wb),
2671 (ins GPR:$Rt, GPR:$Rn, am3offset:$offset, pred:$p),
2674 (pre_truncsti16 GPR:$Rt, GPR:$Rn, am3offset:$offset))]>;
2679 def STRH_PRE : AI3ldstidx<0b1011, 0, 1, (outs GPR:$Rn_wb),
2680 (ins GPR:$Rt, addrmode3_pre:$addr), IndexModePre,
2681 StMiscFrm, IIC_iStore_bh_ru,
2682 "strh", "\t$Rt, $addr!", "$addr.base = $Rn_wb", []> {
2684 let Inst{23} = addr{8}; // U bit
2685 let Inst{22} = addr{13}; // 1 == imm8, 0 == Rm
2686 let Inst{19-16} = addr{12-9}; // Rn
2687 let Inst{11-8} = addr{7-4}; // imm7_4/zero
2688 let Inst{3-0} = addr{3-0}; // imm3_0/Rm
2689 let DecoderMethod = "DecodeAddrMode3Instruction";
2692 def STRH_POST : AI3ldstidx<0b1011, 0, 0, (outs GPR:$Rn_wb),
2693 (ins GPR:$Rt, addr_offset_none:$addr, am3offset:$offset),
2694 IndexModePost, StMiscFrm, IIC_iStore_bh_ru,
2695 "strh", "\t$Rt, $addr, $offset", "$addr.base = $Rn_wb",
2696 [(set GPR:$Rn_wb, (post_truncsti16 GPR:$Rt,
2697 addr_offset_none:$addr,
2698 am3offset:$offset))]> {
2701 let Inst{23} = offset{8}; // U bit
2702 let Inst{22} = offset{9}; // 1 == imm8, 0 == Rm
2703 let Inst{19-16} = addr;
2704 let Inst{11-8} = offset{7-4}; // imm7_4/zero
2705 let Inst{3-0} = offset{3-0}; // imm3_0/Rm
2706 let DecoderMethod = "DecodeAddrMode3Instruction";
2709 let mayStore = 1, neverHasSideEffects = 1, hasExtraSrcRegAllocReq = 1 in {
2710 def STRD_PRE : AI3ldstidx<0b1111, 0, 1, (outs GPR:$Rn_wb),
2711 (ins GPR:$Rt, GPR:$Rt2, addrmode3_pre:$addr),
2712 IndexModePre, StMiscFrm, IIC_iStore_d_ru,
2713 "strd", "\t$Rt, $Rt2, $addr!",
2714 "$addr.base = $Rn_wb", []> {
2716 let Inst{23} = addr{8}; // U bit
2717 let Inst{22} = addr{13}; // 1 == imm8, 0 == Rm
2718 let Inst{19-16} = addr{12-9}; // Rn
2719 let Inst{11-8} = addr{7-4}; // imm7_4/zero
2720 let Inst{3-0} = addr{3-0}; // imm3_0/Rm
2721 let DecoderMethod = "DecodeAddrMode3Instruction";
2724 def STRD_POST: AI3ldstidx<0b1111, 0, 0, (outs GPR:$Rn_wb),
2725 (ins GPR:$Rt, GPR:$Rt2, addr_offset_none:$addr,
2727 IndexModePost, StMiscFrm, IIC_iStore_d_ru,
2728 "strd", "\t$Rt, $Rt2, $addr, $offset",
2729 "$addr.base = $Rn_wb", []> {
2732 let Inst{23} = offset{8}; // U bit
2733 let Inst{22} = offset{9}; // 1 == imm8, 0 == Rm
2734 let Inst{19-16} = addr;
2735 let Inst{11-8} = offset{7-4}; // imm7_4/zero
2736 let Inst{3-0} = offset{3-0}; // imm3_0/Rm
2737 let DecoderMethod = "DecodeAddrMode3Instruction";
2739 } // mayStore = 1, neverHasSideEffects = 1, hasExtraSrcRegAllocReq = 1
2741 // STRT, STRBT, and STRHT
2743 def STRBT_POST_REG : AI2ldstidx<0, 1, 0, (outs GPR:$Rn_wb),
2744 (ins GPR:$Rt, addr_offset_none:$addr, am2offset_reg:$offset),
2745 IndexModePost, StFrm, IIC_iStore_bh_ru,
2746 "strbt", "\t$Rt, $addr, $offset",
2747 "$addr.base = $Rn_wb", []> {
2753 let Inst{23} = offset{12};
2754 let Inst{21} = 1; // overwrite
2755 let Inst{19-16} = addr;
2756 let Inst{11-5} = offset{11-5};
2758 let Inst{3-0} = offset{3-0};
2759 let DecoderMethod = "DecodeAddrMode2IdxInstruction";
2763 : AI2ldstidx<0, 1, 0, (outs GPR:$Rn_wb),
2764 (ins GPR:$Rt, addr_offset_none:$addr, am2offset_imm:$offset),
2765 IndexModePost, StFrm, IIC_iStore_bh_ru,
2766 "strbt", "\t$Rt, $addr, $offset", "$addr.base = $Rn_wb", []> {
2772 let Inst{23} = offset{12};
2773 let Inst{21} = 1; // overwrite
2774 let Inst{19-16} = addr;
2775 let Inst{11-0} = offset{11-0};
2776 let DecoderMethod = "DecodeAddrMode2IdxInstruction";
2780 : ARMAsmPseudo<"strbt${q} $Rt, $addr",
2781 (ins GPR:$Rt, addr_offset_none:$addr, pred:$q)>;
2783 let mayStore = 1, neverHasSideEffects = 1 in {
2784 def STRT_POST_REG : AI2ldstidx<0, 0, 0, (outs GPR:$Rn_wb),
2785 (ins GPR:$Rt, addr_offset_none:$addr, am2offset_reg:$offset),
2786 IndexModePost, StFrm, IIC_iStore_ru,
2787 "strt", "\t$Rt, $addr, $offset",
2788 "$addr.base = $Rn_wb", []> {
2794 let Inst{23} = offset{12};
2795 let Inst{21} = 1; // overwrite
2796 let Inst{19-16} = addr;
2797 let Inst{11-5} = offset{11-5};
2799 let Inst{3-0} = offset{3-0};
2800 let DecoderMethod = "DecodeAddrMode2IdxInstruction";
2804 : AI2ldstidx<0, 0, 0, (outs GPR:$Rn_wb),
2805 (ins GPR:$Rt, addr_offset_none:$addr, am2offset_imm:$offset),
2806 IndexModePost, StFrm, IIC_iStore_ru,
2807 "strt", "\t$Rt, $addr, $offset", "$addr.base = $Rn_wb", []> {
2813 let Inst{23} = offset{12};
2814 let Inst{21} = 1; // overwrite
2815 let Inst{19-16} = addr;
2816 let Inst{11-0} = offset{11-0};
2817 let DecoderMethod = "DecodeAddrMode2IdxInstruction";
2822 : ARMAsmPseudo<"strt${q} $Rt, $addr",
2823 (ins GPR:$Rt, addr_offset_none:$addr, pred:$q)>;
2825 multiclass AI3strT<bits<4> op, string opc> {
2826 def i : AI3ldstidxT<op, 0, (outs GPR:$base_wb),
2827 (ins GPR:$Rt, addr_offset_none:$addr, postidx_imm8:$offset),
2828 IndexModePost, StMiscFrm, IIC_iStore_bh_ru, opc,
2829 "\t$Rt, $addr, $offset", "$addr.base = $base_wb", []> {
2831 let Inst{23} = offset{8};
2833 let Inst{11-8} = offset{7-4};
2834 let Inst{3-0} = offset{3-0};
2836 def r : AI3ldstidxT<op, 0, (outs GPR:$base_wb),
2837 (ins GPR:$Rt, addr_offset_none:$addr, postidx_reg:$Rm),
2838 IndexModePost, StMiscFrm, IIC_iStore_bh_ru, opc,
2839 "\t$Rt, $addr, $Rm", "$addr.base = $base_wb", []> {
2841 let Inst{23} = Rm{4};
2844 let Inst{3-0} = Rm{3-0};
2849 defm STRHT : AI3strT<0b1011, "strht">;
2851 def STL : AIstrrel<0b00, (outs), (ins GPR:$Rt, addr_offset_none:$addr),
2852 NoItinerary, "stl", "\t$Rt, $addr", []>;
2853 def STLB : AIstrrel<0b10, (outs), (ins GPR:$Rt, addr_offset_none:$addr),
2854 NoItinerary, "stlb", "\t$Rt, $addr", []>;
2855 def STLH : AIstrrel<0b11, (outs), (ins GPR:$Rt, addr_offset_none:$addr),
2856 NoItinerary, "stlh", "\t$Rt, $addr", []>;
2858 //===----------------------------------------------------------------------===//
2859 // Load / store multiple Instructions.
2862 multiclass arm_ldst_mult<string asm, string sfx, bit L_bit, bit P_bit, Format f,
2863 InstrItinClass itin, InstrItinClass itin_upd> {
2864 // IA is the default, so no need for an explicit suffix on the
2865 // mnemonic here. Without it is the canonical spelling.
2867 AXI4<(outs), (ins GPR:$Rn, pred:$p, reglist:$regs, variable_ops),
2868 IndexModeNone, f, itin,
2869 !strconcat(asm, "${p}\t$Rn, $regs", sfx), "", []> {
2870 let Inst{24-23} = 0b01; // Increment After
2871 let Inst{22} = P_bit;
2872 let Inst{21} = 0; // No writeback
2873 let Inst{20} = L_bit;
2876 AXI4<(outs GPR:$wb), (ins GPR:$Rn, pred:$p, reglist:$regs, variable_ops),
2877 IndexModeUpd, f, itin_upd,
2878 !strconcat(asm, "${p}\t$Rn!, $regs", sfx), "$Rn = $wb", []> {
2879 let Inst{24-23} = 0b01; // Increment After
2880 let Inst{22} = P_bit;
2881 let Inst{21} = 1; // Writeback
2882 let Inst{20} = L_bit;
2884 let DecoderMethod = "DecodeMemMultipleWritebackInstruction";
2887 AXI4<(outs), (ins GPR:$Rn, pred:$p, reglist:$regs, variable_ops),
2888 IndexModeNone, f, itin,
2889 !strconcat(asm, "da${p}\t$Rn, $regs", sfx), "", []> {
2890 let Inst{24-23} = 0b00; // Decrement After
2891 let Inst{22} = P_bit;
2892 let Inst{21} = 0; // No writeback
2893 let Inst{20} = L_bit;
2896 AXI4<(outs GPR:$wb), (ins GPR:$Rn, pred:$p, reglist:$regs, variable_ops),
2897 IndexModeUpd, f, itin_upd,
2898 !strconcat(asm, "da${p}\t$Rn!, $regs", sfx), "$Rn = $wb", []> {
2899 let Inst{24-23} = 0b00; // Decrement After
2900 let Inst{22} = P_bit;
2901 let Inst{21} = 1; // Writeback
2902 let Inst{20} = L_bit;
2904 let DecoderMethod = "DecodeMemMultipleWritebackInstruction";
2907 AXI4<(outs), (ins GPR:$Rn, pred:$p, reglist:$regs, variable_ops),
2908 IndexModeNone, f, itin,
2909 !strconcat(asm, "db${p}\t$Rn, $regs", sfx), "", []> {
2910 let Inst{24-23} = 0b10; // Decrement Before
2911 let Inst{22} = P_bit;
2912 let Inst{21} = 0; // No writeback
2913 let Inst{20} = L_bit;
2916 AXI4<(outs GPR:$wb), (ins GPR:$Rn, pred:$p, reglist:$regs, variable_ops),
2917 IndexModeUpd, f, itin_upd,
2918 !strconcat(asm, "db${p}\t$Rn!, $regs", sfx), "$Rn = $wb", []> {
2919 let Inst{24-23} = 0b10; // Decrement Before
2920 let Inst{22} = P_bit;
2921 let Inst{21} = 1; // Writeback
2922 let Inst{20} = L_bit;
2924 let DecoderMethod = "DecodeMemMultipleWritebackInstruction";
2927 AXI4<(outs), (ins GPR:$Rn, pred:$p, reglist:$regs, variable_ops),
2928 IndexModeNone, f, itin,
2929 !strconcat(asm, "ib${p}\t$Rn, $regs", sfx), "", []> {
2930 let Inst{24-23} = 0b11; // Increment Before
2931 let Inst{22} = P_bit;
2932 let Inst{21} = 0; // No writeback
2933 let Inst{20} = L_bit;
2936 AXI4<(outs GPR:$wb), (ins GPR:$Rn, pred:$p, reglist:$regs, variable_ops),
2937 IndexModeUpd, f, itin_upd,
2938 !strconcat(asm, "ib${p}\t$Rn!, $regs", sfx), "$Rn = $wb", []> {
2939 let Inst{24-23} = 0b11; // Increment Before
2940 let Inst{22} = P_bit;
2941 let Inst{21} = 1; // Writeback
2942 let Inst{20} = L_bit;
2944 let DecoderMethod = "DecodeMemMultipleWritebackInstruction";
2948 let neverHasSideEffects = 1 in {
2950 let mayLoad = 1, hasExtraDefRegAllocReq = 1 in
2951 defm LDM : arm_ldst_mult<"ldm", "", 1, 0, LdStMulFrm, IIC_iLoad_m,
2954 let mayStore = 1, hasExtraSrcRegAllocReq = 1 in
2955 defm STM : arm_ldst_mult<"stm", "", 0, 0, LdStMulFrm, IIC_iStore_m,
2958 } // neverHasSideEffects
2960 // FIXME: remove when we have a way to marking a MI with these properties.
2961 // FIXME: Should pc be an implicit operand like PICADD, etc?
2962 let isReturn = 1, isTerminator = 1, isBarrier = 1, mayLoad = 1,
2963 hasExtraDefRegAllocReq = 1, isCodeGenOnly = 1 in
2964 def LDMIA_RET : ARMPseudoExpand<(outs GPR:$wb), (ins GPR:$Rn, pred:$p,
2965 reglist:$regs, variable_ops),
2966 4, IIC_iLoad_mBr, [],
2967 (LDMIA_UPD GPR:$wb, GPR:$Rn, pred:$p, reglist:$regs)>,
2968 RegConstraint<"$Rn = $wb">;
2970 let mayLoad = 1, hasExtraDefRegAllocReq = 1 in
2971 defm sysLDM : arm_ldst_mult<"ldm", " ^", 1, 1, LdStMulFrm, IIC_iLoad_m,
2974 let mayStore = 1, hasExtraSrcRegAllocReq = 1 in
2975 defm sysSTM : arm_ldst_mult<"stm", " ^", 0, 1, LdStMulFrm, IIC_iStore_m,
2980 //===----------------------------------------------------------------------===//
2981 // Move Instructions.
2984 let neverHasSideEffects = 1 in
2985 def MOVr : AsI1<0b1101, (outs GPR:$Rd), (ins GPR:$Rm), DPFrm, IIC_iMOVr,
2986 "mov", "\t$Rd, $Rm", []>, UnaryDP, Sched<[WriteALU]> {
2990 let Inst{19-16} = 0b0000;
2991 let Inst{11-4} = 0b00000000;
2994 let Inst{15-12} = Rd;
2997 // A version for the smaller set of tail call registers.
2998 let neverHasSideEffects = 1 in
2999 def MOVr_TC : AsI1<0b1101, (outs tcGPR:$Rd), (ins tcGPR:$Rm), DPFrm,
3000 IIC_iMOVr, "mov", "\t$Rd, $Rm", []>, UnaryDP, Sched<[WriteALU]> {
3004 let Inst{11-4} = 0b00000000;
3007 let Inst{15-12} = Rd;
3010 def MOVsr : AsI1<0b1101, (outs GPRnopc:$Rd), (ins shift_so_reg_reg:$src),
3011 DPSoRegRegFrm, IIC_iMOVsr,
3012 "mov", "\t$Rd, $src",
3013 [(set GPRnopc:$Rd, shift_so_reg_reg:$src)]>, UnaryDP,
3017 let Inst{15-12} = Rd;
3018 let Inst{19-16} = 0b0000;
3019 let Inst{11-8} = src{11-8};
3021 let Inst{6-5} = src{6-5};
3023 let Inst{3-0} = src{3-0};
3027 def MOVsi : AsI1<0b1101, (outs GPR:$Rd), (ins shift_so_reg_imm:$src),
3028 DPSoRegImmFrm, IIC_iMOVsr,
3029 "mov", "\t$Rd, $src", [(set GPR:$Rd, shift_so_reg_imm:$src)]>,
3030 UnaryDP, Sched<[WriteALU]> {
3033 let Inst{15-12} = Rd;
3034 let Inst{19-16} = 0b0000;
3035 let Inst{11-5} = src{11-5};
3037 let Inst{3-0} = src{3-0};
3041 let isReMaterializable = 1, isAsCheapAsAMove = 1, isMoveImm = 1 in
3042 def MOVi : AsI1<0b1101, (outs GPR:$Rd), (ins so_imm:$imm), DPFrm, IIC_iMOVi,
3043 "mov", "\t$Rd, $imm", [(set GPR:$Rd, so_imm:$imm)]>, UnaryDP,
3048 let Inst{15-12} = Rd;
3049 let Inst{19-16} = 0b0000;
3050 let Inst{11-0} = imm;
3053 let isReMaterializable = 1, isAsCheapAsAMove = 1, isMoveImm = 1 in
3054 def MOVi16 : AI1<0b1000, (outs GPR:$Rd), (ins imm0_65535_expr:$imm),
3056 "movw", "\t$Rd, $imm",
3057 [(set GPR:$Rd, imm0_65535:$imm)]>,
3058 Requires<[IsARM, HasV6T2]>, UnaryDP, Sched<[WriteALU]> {
3061 let Inst{15-12} = Rd;
3062 let Inst{11-0} = imm{11-0};
3063 let Inst{19-16} = imm{15-12};
3066 let DecoderMethod = "DecodeArmMOVTWInstruction";
3069 def : InstAlias<"mov${p} $Rd, $imm",
3070 (MOVi16 GPR:$Rd, imm0_65535_expr:$imm, pred:$p)>,
3073 def MOVi16_ga_pcrel : PseudoInst<(outs GPR:$Rd),
3074 (ins i32imm:$addr, pclabel:$id), IIC_iMOVi, []>,
3077 let Constraints = "$src = $Rd" in {
3078 def MOVTi16 : AI1<0b1010, (outs GPRnopc:$Rd),
3079 (ins GPR:$src, imm0_65535_expr:$imm),
3081 "movt", "\t$Rd, $imm",
3083 (or (and GPR:$src, 0xffff),
3084 lo16AllZero:$imm))]>, UnaryDP,
3085 Requires<[IsARM, HasV6T2]>, Sched<[WriteALU]> {
3088 let Inst{15-12} = Rd;
3089 let Inst{11-0} = imm{11-0};
3090 let Inst{19-16} = imm{15-12};
3093 let DecoderMethod = "DecodeArmMOVTWInstruction";
3096 def MOVTi16_ga_pcrel : PseudoInst<(outs GPR:$Rd),
3097 (ins GPR:$src, i32imm:$addr, pclabel:$id), IIC_iMOVi, []>,
3102 def : ARMPat<(or GPR:$src, 0xffff0000), (MOVTi16 GPR:$src, 0xffff)>,
3103 Requires<[IsARM, HasV6T2]>;
3105 let Uses = [CPSR] in
3106 def RRX: PseudoInst<(outs GPR:$Rd), (ins GPR:$Rm), IIC_iMOVsi,
3107 [(set GPR:$Rd, (ARMrrx GPR:$Rm))]>, UnaryDP,
3108 Requires<[IsARM]>, Sched<[WriteALU]>;
3110 // These aren't really mov instructions, but we have to define them this way
3111 // due to flag operands.
3113 let Defs = [CPSR] in {
3114 def MOVsrl_flag : PseudoInst<(outs GPR:$dst), (ins GPR:$src), IIC_iMOVsi,
3115 [(set GPR:$dst, (ARMsrl_flag GPR:$src))]>, UnaryDP,
3116 Sched<[WriteALU]>, Requires<[IsARM]>;
3117 def MOVsra_flag : PseudoInst<(outs GPR:$dst), (ins GPR:$src), IIC_iMOVsi,
3118 [(set GPR:$dst, (ARMsra_flag GPR:$src))]>, UnaryDP,
3119 Sched<[WriteALU]>, Requires<[IsARM]>;
3122 //===----------------------------------------------------------------------===//
3123 // Extend Instructions.
3128 def SXTB : AI_ext_rrot<0b01101010,
3129 "sxtb", UnOpFrag<(sext_inreg node:$Src, i8)>>;
3130 def SXTH : AI_ext_rrot<0b01101011,
3131 "sxth", UnOpFrag<(sext_inreg node:$Src, i16)>>;
3133 def SXTAB : AI_exta_rrot<0b01101010,
3134 "sxtab", BinOpFrag<(add node:$LHS, (sext_inreg node:$RHS, i8))>>;
3135 def SXTAH : AI_exta_rrot<0b01101011,
3136 "sxtah", BinOpFrag<(add node:$LHS, (sext_inreg node:$RHS,i16))>>;
3138 def SXTB16 : AI_ext_rrot_np<0b01101000, "sxtb16">;
3140 def SXTAB16 : AI_exta_rrot_np<0b01101000, "sxtab16">;
3144 let AddedComplexity = 16 in {
3145 def UXTB : AI_ext_rrot<0b01101110,
3146 "uxtb" , UnOpFrag<(and node:$Src, 0x000000FF)>>;
3147 def UXTH : AI_ext_rrot<0b01101111,
3148 "uxth" , UnOpFrag<(and node:$Src, 0x0000FFFF)>>;
3149 def UXTB16 : AI_ext_rrot<0b01101100,
3150 "uxtb16", UnOpFrag<(and node:$Src, 0x00FF00FF)>>;
3152 // FIXME: This pattern incorrectly assumes the shl operator is a rotate.
3153 // The transformation should probably be done as a combiner action
3154 // instead so we can include a check for masking back in the upper
3155 // eight bits of the source into the lower eight bits of the result.
3156 //def : ARMV6Pat<(and (shl GPR:$Src, (i32 8)), 0xFF00FF),
3157 // (UXTB16r_rot GPR:$Src, 3)>;
3158 def : ARMV6Pat<(and (srl GPR:$Src, (i32 8)), 0xFF00FF),
3159 (UXTB16 GPR:$Src, 1)>;
3161 def UXTAB : AI_exta_rrot<0b01101110, "uxtab",
3162 BinOpFrag<(add node:$LHS, (and node:$RHS, 0x00FF))>>;
3163 def UXTAH : AI_exta_rrot<0b01101111, "uxtah",
3164 BinOpFrag<(add node:$LHS, (and node:$RHS, 0xFFFF))>>;
3167 // This isn't safe in general, the add is two 16-bit units, not a 32-bit add.
3168 def UXTAB16 : AI_exta_rrot_np<0b01101100, "uxtab16">;
3171 def SBFX : I<(outs GPRnopc:$Rd),
3172 (ins GPRnopc:$Rn, imm0_31:$lsb, imm1_32:$width),
3173 AddrMode1, 4, IndexModeNone, DPFrm, IIC_iUNAsi,
3174 "sbfx", "\t$Rd, $Rn, $lsb, $width", "", []>,
3175 Requires<[IsARM, HasV6T2]> {
3180 let Inst{27-21} = 0b0111101;
3181 let Inst{6-4} = 0b101;
3182 let Inst{20-16} = width;
3183 let Inst{15-12} = Rd;
3184 let Inst{11-7} = lsb;
3188 def UBFX : I<(outs GPR:$Rd),
3189 (ins GPR:$Rn, imm0_31:$lsb, imm1_32:$width),
3190 AddrMode1, 4, IndexModeNone, DPFrm, IIC_iUNAsi,
3191 "ubfx", "\t$Rd, $Rn, $lsb, $width", "", []>,
3192 Requires<[IsARM, HasV6T2]> {
3197 let Inst{27-21} = 0b0111111;
3198 let Inst{6-4} = 0b101;
3199 let Inst{20-16} = width;
3200 let Inst{15-12} = Rd;
3201 let Inst{11-7} = lsb;
3205 //===----------------------------------------------------------------------===//
3206 // Arithmetic Instructions.
3209 defm ADD : AsI1_bin_irs<0b0100, "add",
3210 IIC_iALUi, IIC_iALUr, IIC_iALUsr,
3211 BinOpFrag<(add node:$LHS, node:$RHS)>, 1>;
3212 defm SUB : AsI1_bin_irs<0b0010, "sub",
3213 IIC_iALUi, IIC_iALUr, IIC_iALUsr,
3214 BinOpFrag<(sub node:$LHS, node:$RHS)>>;
3216 // ADD and SUB with 's' bit set.
3218 // Currently, ADDS/SUBS are pseudo opcodes that exist only in the
3219 // selection DAG. They are "lowered" to real ADD/SUB opcodes by
3220 // AdjustInstrPostInstrSelection where we determine whether or not to
3221 // set the "s" bit based on CPSR liveness.
3223 // FIXME: Eliminate ADDS/SUBS pseudo opcodes after adding tablegen
3224 // support for an optional CPSR definition that corresponds to the DAG
3225 // node's second value. We can then eliminate the implicit def of CPSR.
3226 defm ADDS : AsI1_bin_s_irs<IIC_iALUi, IIC_iALUr, IIC_iALUsr,
3227 BinOpFrag<(ARMaddc node:$LHS, node:$RHS)>, 1>;
3228 defm SUBS : AsI1_bin_s_irs<IIC_iALUi, IIC_iALUr, IIC_iALUsr,
3229 BinOpFrag<(ARMsubc node:$LHS, node:$RHS)>>;
3231 defm ADC : AI1_adde_sube_irs<0b0101, "adc",
3232 BinOpWithFlagFrag<(ARMadde node:$LHS, node:$RHS, node:$FLAG)>, 1>;
3233 defm SBC : AI1_adde_sube_irs<0b0110, "sbc",
3234 BinOpWithFlagFrag<(ARMsube node:$LHS, node:$RHS, node:$FLAG)>>;
3236 defm RSB : AsI1_rbin_irs<0b0011, "rsb",
3237 IIC_iALUi, IIC_iALUr, IIC_iALUsr,
3238 BinOpFrag<(sub node:$LHS, node:$RHS)>>;
3240 // FIXME: Eliminate them if we can write def : Pat patterns which defines
3241 // CPSR and the implicit def of CPSR is not needed.
3242 defm RSBS : AsI1_rbin_s_is<IIC_iALUi, IIC_iALUr, IIC_iALUsr,
3243 BinOpFrag<(ARMsubc node:$LHS, node:$RHS)>>;
3245 defm RSC : AI1_rsc_irs<0b0111, "rsc",
3246 BinOpWithFlagFrag<(ARMsube node:$LHS, node:$RHS, node:$FLAG)>>;
3248 // (sub X, imm) gets canonicalized to (add X, -imm). Match this form.
3249 // The assume-no-carry-in form uses the negation of the input since add/sub
3250 // assume opposite meanings of the carry flag (i.e., carry == !borrow).
3251 // See the definition of AddWithCarry() in the ARM ARM A2.2.1 for the gory
3253 def : ARMPat<(add GPR:$src, so_imm_neg:$imm),
3254 (SUBri GPR:$src, so_imm_neg:$imm)>;
3255 def : ARMPat<(ARMaddc GPR:$src, so_imm_neg:$imm),
3256 (SUBSri GPR:$src, so_imm_neg:$imm)>;
3258 def : ARMPat<(add GPR:$src, imm0_65535_neg:$imm),
3259 (SUBrr GPR:$src, (MOVi16 (imm_neg_XFORM imm:$imm)))>,
3260 Requires<[IsARM, HasV6T2]>;
3261 def : ARMPat<(ARMaddc GPR:$src, imm0_65535_neg:$imm),
3262 (SUBSrr GPR:$src, (MOVi16 (imm_neg_XFORM imm:$imm)))>,
3263 Requires<[IsARM, HasV6T2]>;
3265 // The with-carry-in form matches bitwise not instead of the negation.
3266 // Effectively, the inverse interpretation of the carry flag already accounts
3267 // for part of the negation.
3268 def : ARMPat<(ARMadde GPR:$src, so_imm_not:$imm, CPSR),
3269 (SBCri GPR:$src, so_imm_not:$imm)>;
3270 def : ARMPat<(ARMadde GPR:$src, imm0_65535_neg:$imm, CPSR),
3271 (SBCrr GPR:$src, (MOVi16 (imm_not_XFORM imm:$imm)))>;
3273 // Note: These are implemented in C++ code, because they have to generate
3274 // ADD/SUBrs instructions, which use a complex pattern that a xform function
3276 // (mul X, 2^n+1) -> (add (X << n), X)
3277 // (mul X, 2^n-1) -> (rsb X, (X << n))
3279 // ARM Arithmetic Instruction
3280 // GPR:$dst = GPR:$a op GPR:$b
3281 class AAI<bits<8> op27_20, bits<8> op11_4, string opc,
3282 list<dag> pattern = [],
3283 dag iops = (ins GPRnopc:$Rn, GPRnopc:$Rm),
3284 string asm = "\t$Rd, $Rn, $Rm">
3285 : AI<(outs GPRnopc:$Rd), iops, DPFrm, IIC_iALUr, opc, asm, pattern>,
3286 Sched<[WriteALU, ReadALU, ReadALU]> {
3290 let Inst{27-20} = op27_20;
3291 let Inst{11-4} = op11_4;
3292 let Inst{19-16} = Rn;
3293 let Inst{15-12} = Rd;
3296 let Unpredictable{11-8} = 0b1111;
3299 // Saturating add/subtract
3301 let DecoderMethod = "DecodeQADDInstruction" in
3302 def QADD : AAI<0b00010000, 0b00000101, "qadd",
3303 [(set GPRnopc:$Rd, (int_arm_qadd GPRnopc:$Rm, GPRnopc:$Rn))],
3304 (ins GPRnopc:$Rm, GPRnopc:$Rn), "\t$Rd, $Rm, $Rn">;
3306 def QSUB : AAI<0b00010010, 0b00000101, "qsub",
3307 [(set GPRnopc:$Rd, (int_arm_qsub GPRnopc:$Rm, GPRnopc:$Rn))],
3308 (ins GPRnopc:$Rm, GPRnopc:$Rn), "\t$Rd, $Rm, $Rn">;
3309 def QDADD : AAI<0b00010100, 0b00000101, "qdadd", [],
3310 (ins GPRnopc:$Rm, GPRnopc:$Rn),
3312 def QDSUB : AAI<0b00010110, 0b00000101, "qdsub", [],
3313 (ins GPRnopc:$Rm, GPRnopc:$Rn),
3316 def QADD16 : AAI<0b01100010, 0b11110001, "qadd16">;
3317 def QADD8 : AAI<0b01100010, 0b11111001, "qadd8">;
3318 def QASX : AAI<0b01100010, 0b11110011, "qasx">;
3319 def QSAX : AAI<0b01100010, 0b11110101, "qsax">;
3320 def QSUB16 : AAI<0b01100010, 0b11110111, "qsub16">;
3321 def QSUB8 : AAI<0b01100010, 0b11111111, "qsub8">;
3322 def UQADD16 : AAI<0b01100110, 0b11110001, "uqadd16">;
3323 def UQADD8 : AAI<0b01100110, 0b11111001, "uqadd8">;
3324 def UQASX : AAI<0b01100110, 0b11110011, "uqasx">;
3325 def UQSAX : AAI<0b01100110, 0b11110101, "uqsax">;
3326 def UQSUB16 : AAI<0b01100110, 0b11110111, "uqsub16">;
3327 def UQSUB8 : AAI<0b01100110, 0b11111111, "uqsub8">;
3329 // Signed/Unsigned add/subtract
3331 def SASX : AAI<0b01100001, 0b11110011, "sasx">;
3332 def SADD16 : AAI<0b01100001, 0b11110001, "sadd16">;
3333 def SADD8 : AAI<0b01100001, 0b11111001, "sadd8">;
3334 def SSAX : AAI<0b01100001, 0b11110101, "ssax">;
3335 def SSUB16 : AAI<0b01100001, 0b11110111, "ssub16">;
3336 def SSUB8 : AAI<0b01100001, 0b11111111, "ssub8">;
3337 def UASX : AAI<0b01100101, 0b11110011, "uasx">;
3338 def UADD16 : AAI<0b01100101, 0b11110001, "uadd16">;
3339 def UADD8 : AAI<0b01100101, 0b11111001, "uadd8">;
3340 def USAX : AAI<0b01100101, 0b11110101, "usax">;
3341 def USUB16 : AAI<0b01100101, 0b11110111, "usub16">;
3342 def USUB8 : AAI<0b01100101, 0b11111111, "usub8">;
3344 // Signed/Unsigned halving add/subtract
3346 def SHASX : AAI<0b01100011, 0b11110011, "shasx">;
3347 def SHADD16 : AAI<0b01100011, 0b11110001, "shadd16">;
3348 def SHADD8 : AAI<0b01100011, 0b11111001, "shadd8">;
3349 def SHSAX : AAI<0b01100011, 0b11110101, "shsax">;
3350 def SHSUB16 : AAI<0b01100011, 0b11110111, "shsub16">;
3351 def SHSUB8 : AAI<0b01100011, 0b11111111, "shsub8">;
3352 def UHASX : AAI<0b01100111, 0b11110011, "uhasx">;
3353 def UHADD16 : AAI<0b01100111, 0b11110001, "uhadd16">;
3354 def UHADD8 : AAI<0b01100111, 0b11111001, "uhadd8">;
3355 def UHSAX : AAI<0b01100111, 0b11110101, "uhsax">;
3356 def UHSUB16 : AAI<0b01100111, 0b11110111, "uhsub16">;
3357 def UHSUB8 : AAI<0b01100111, 0b11111111, "uhsub8">;
3359 // Unsigned Sum of Absolute Differences [and Accumulate].
3361 def USAD8 : AI<(outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm),
3362 MulFrm /* for convenience */, NoItinerary, "usad8",
3363 "\t$Rd, $Rn, $Rm", []>,
3364 Requires<[IsARM, HasV6]>, Sched<[WriteALU, ReadALU, ReadALU]> {
3368 let Inst{27-20} = 0b01111000;
3369 let Inst{15-12} = 0b1111;
3370 let Inst{7-4} = 0b0001;
3371 let Inst{19-16} = Rd;
3372 let Inst{11-8} = Rm;
3375 def USADA8 : AI<(outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm, GPR:$Ra),
3376 MulFrm /* for convenience */, NoItinerary, "usada8",
3377 "\t$Rd, $Rn, $Rm, $Ra", []>,
3378 Requires<[IsARM, HasV6]>, Sched<[WriteALU, ReadALU, ReadALU]>{
3383 let Inst{27-20} = 0b01111000;
3384 let Inst{7-4} = 0b0001;
3385 let Inst{19-16} = Rd;
3386 let Inst{15-12} = Ra;
3387 let Inst{11-8} = Rm;
3391 // Signed/Unsigned saturate
3393 def SSAT : AI<(outs GPRnopc:$Rd),
3394 (ins imm1_32:$sat_imm, GPRnopc:$Rn, shift_imm:$sh),
3395 SatFrm, NoItinerary, "ssat", "\t$Rd, $sat_imm, $Rn$sh", []> {
3400 let Inst{27-21} = 0b0110101;
3401 let Inst{5-4} = 0b01;
3402 let Inst{20-16} = sat_imm;
3403 let Inst{15-12} = Rd;
3404 let Inst{11-7} = sh{4-0};
3405 let Inst{6} = sh{5};
3409 def SSAT16 : AI<(outs GPRnopc:$Rd),
3410 (ins imm1_16:$sat_imm, GPRnopc:$Rn), SatFrm,
3411 NoItinerary, "ssat16", "\t$Rd, $sat_imm, $Rn", []> {
3415 let Inst{27-20} = 0b01101010;
3416 let Inst{11-4} = 0b11110011;
3417 let Inst{15-12} = Rd;
3418 let Inst{19-16} = sat_imm;
3422 def USAT : AI<(outs GPRnopc:$Rd),
3423 (ins imm0_31:$sat_imm, GPRnopc:$Rn, shift_imm:$sh),
3424 SatFrm, NoItinerary, "usat", "\t$Rd, $sat_imm, $Rn$sh", []> {
3429 let Inst{27-21} = 0b0110111;
3430 let Inst{5-4} = 0b01;
3431 let Inst{15-12} = Rd;
3432 let Inst{11-7} = sh{4-0};
3433 let Inst{6} = sh{5};
3434 let Inst{20-16} = sat_imm;
3438 def USAT16 : AI<(outs GPRnopc:$Rd),
3439 (ins imm0_15:$sat_imm, GPRnopc:$Rn), SatFrm,
3440 NoItinerary, "usat16", "\t$Rd, $sat_imm, $Rn", []> {
3444 let Inst{27-20} = 0b01101110;
3445 let Inst{11-4} = 0b11110011;
3446 let Inst{15-12} = Rd;
3447 let Inst{19-16} = sat_imm;
3451 def : ARMV6Pat<(int_arm_ssat GPRnopc:$a, imm:$pos),
3452 (SSAT imm:$pos, GPRnopc:$a, 0)>;
3453 def : ARMV6Pat<(int_arm_usat GPRnopc:$a, imm:$pos),
3454 (USAT imm:$pos, GPRnopc:$a, 0)>;
3456 //===----------------------------------------------------------------------===//
3457 // Bitwise Instructions.
3460 defm AND : AsI1_bin_irs<0b0000, "and",
3461 IIC_iBITi, IIC_iBITr, IIC_iBITsr,
3462 BinOpFrag<(and node:$LHS, node:$RHS)>, 1>;
3463 defm ORR : AsI1_bin_irs<0b1100, "orr",
3464 IIC_iBITi, IIC_iBITr, IIC_iBITsr,
3465 BinOpFrag<(or node:$LHS, node:$RHS)>, 1>;
3466 defm EOR : AsI1_bin_irs<0b0001, "eor",
3467 IIC_iBITi, IIC_iBITr, IIC_iBITsr,
3468 BinOpFrag<(xor node:$LHS, node:$RHS)>, 1>;
3469 defm BIC : AsI1_bin_irs<0b1110, "bic",
3470 IIC_iBITi, IIC_iBITr, IIC_iBITsr,
3471 BinOpFrag<(and node:$LHS, (not node:$RHS))>>;
3473 // FIXME: bf_inv_mask_imm should be two operands, the lsb and the msb, just
3474 // like in the actual instruction encoding. The complexity of mapping the mask
3475 // to the lsb/msb pair should be handled by ISel, not encapsulated in the
3476 // instruction description.
3477 def BFC : I<(outs GPR:$Rd), (ins GPR:$src, bf_inv_mask_imm:$imm),
3478 AddrMode1, 4, IndexModeNone, DPFrm, IIC_iUNAsi,
3479 "bfc", "\t$Rd, $imm", "$src = $Rd",
3480 [(set GPR:$Rd, (and GPR:$src, bf_inv_mask_imm:$imm))]>,
3481 Requires<[IsARM, HasV6T2]> {
3484 let Inst{27-21} = 0b0111110;
3485 let Inst{6-0} = 0b0011111;
3486 let Inst{15-12} = Rd;
3487 let Inst{11-7} = imm{4-0}; // lsb
3488 let Inst{20-16} = imm{9-5}; // msb
3491 // A8.6.18 BFI - Bitfield insert (Encoding A1)
3492 def BFI:I<(outs GPRnopc:$Rd), (ins GPRnopc:$src, GPR:$Rn, bf_inv_mask_imm:$imm),
3493 AddrMode1, 4, IndexModeNone, DPFrm, IIC_iUNAsi,
3494 "bfi", "\t$Rd, $Rn, $imm", "$src = $Rd",
3495 [(set GPRnopc:$Rd, (ARMbfi GPRnopc:$src, GPR:$Rn,
3496 bf_inv_mask_imm:$imm))]>,
3497 Requires<[IsARM, HasV6T2]> {
3501 let Inst{27-21} = 0b0111110;
3502 let Inst{6-4} = 0b001; // Rn: Inst{3-0} != 15
3503 let Inst{15-12} = Rd;
3504 let Inst{11-7} = imm{4-0}; // lsb
3505 let Inst{20-16} = imm{9-5}; // width
3509 def MVNr : AsI1<0b1111, (outs GPR:$Rd), (ins GPR:$Rm), DPFrm, IIC_iMVNr,
3510 "mvn", "\t$Rd, $Rm",
3511 [(set GPR:$Rd, (not GPR:$Rm))]>, UnaryDP, Sched<[WriteALU]> {
3515 let Inst{19-16} = 0b0000;
3516 let Inst{11-4} = 0b00000000;
3517 let Inst{15-12} = Rd;
3520 def MVNsi : AsI1<0b1111, (outs GPR:$Rd), (ins so_reg_imm:$shift),
3521 DPSoRegImmFrm, IIC_iMVNsr, "mvn", "\t$Rd, $shift",
3522 [(set GPR:$Rd, (not so_reg_imm:$shift))]>, UnaryDP,
3527 let Inst{19-16} = 0b0000;
3528 let Inst{15-12} = Rd;
3529 let Inst{11-5} = shift{11-5};
3531 let Inst{3-0} = shift{3-0};
3533 def MVNsr : AsI1<0b1111, (outs GPR:$Rd), (ins so_reg_reg:$shift),
3534 DPSoRegRegFrm, IIC_iMVNsr, "mvn", "\t$Rd, $shift",
3535 [(set GPR:$Rd, (not so_reg_reg:$shift))]>, UnaryDP,
3540 let Inst{19-16} = 0b0000;
3541 let Inst{15-12} = Rd;
3542 let Inst{11-8} = shift{11-8};
3544 let Inst{6-5} = shift{6-5};
3546 let Inst{3-0} = shift{3-0};
3548 let isReMaterializable = 1, isAsCheapAsAMove = 1, isMoveImm = 1 in
3549 def MVNi : AsI1<0b1111, (outs GPR:$Rd), (ins so_imm:$imm), DPFrm,
3550 IIC_iMVNi, "mvn", "\t$Rd, $imm",
3551 [(set GPR:$Rd, so_imm_not:$imm)]>,UnaryDP, Sched<[WriteALU]> {
3555 let Inst{19-16} = 0b0000;
3556 let Inst{15-12} = Rd;
3557 let Inst{11-0} = imm;
3560 def : ARMPat<(and GPR:$src, so_imm_not:$imm),
3561 (BICri GPR:$src, so_imm_not:$imm)>;
3563 //===----------------------------------------------------------------------===//
3564 // Multiply Instructions.
3566 class AsMul1I32<bits<7> opcod, dag oops, dag iops, InstrItinClass itin,
3567 string opc, string asm, list<dag> pattern>
3568 : AsMul1I<opcod, oops, iops, itin, opc, asm, pattern> {
3572 let Inst{19-16} = Rd;
3573 let Inst{11-8} = Rm;
3576 class AsMul1I64<bits<7> opcod, dag oops, dag iops, InstrItinClass itin,
3577 string opc, string asm, list<dag> pattern>
3578 : AsMul1I<opcod, oops, iops, itin, opc, asm, pattern> {
3583 let Inst{19-16} = RdHi;
3584 let Inst{15-12} = RdLo;
3585 let Inst{11-8} = Rm;
3588 class AsMla1I64<bits<7> opcod, dag oops, dag iops, InstrItinClass itin,
3589 string opc, string asm, list<dag> pattern>
3590 : AsMul1I<opcod, oops, iops, itin, opc, asm, pattern> {
3595 let Inst{19-16} = RdHi;
3596 let Inst{15-12} = RdLo;
3597 let Inst{11-8} = Rm;
3601 // FIXME: The v5 pseudos are only necessary for the additional Constraint
3602 // property. Remove them when it's possible to add those properties
3603 // on an individual MachineInstr, not just an instruction description.
3604 let isCommutable = 1, TwoOperandAliasConstraint = "$Rn = $Rd" in {
3605 def MUL : AsMul1I32<0b0000000, (outs GPRnopc:$Rd),
3606 (ins GPRnopc:$Rn, GPRnopc:$Rm),
3607 IIC_iMUL32, "mul", "\t$Rd, $Rn, $Rm",
3608 [(set GPRnopc:$Rd, (mul GPRnopc:$Rn, GPRnopc:$Rm))]>,
3609 Requires<[IsARM, HasV6]> {
3610 let Inst{15-12} = 0b0000;
3611 let Unpredictable{15-12} = 0b1111;
3614 let Constraints = "@earlyclobber $Rd" in
3615 def MULv5: ARMPseudoExpand<(outs GPRnopc:$Rd), (ins GPRnopc:$Rn, GPRnopc:$Rm,
3616 pred:$p, cc_out:$s),
3618 [(set GPRnopc:$Rd, (mul GPRnopc:$Rn, GPRnopc:$Rm))],
3619 (MUL GPRnopc:$Rd, GPRnopc:$Rn, GPRnopc:$Rm, pred:$p, cc_out:$s)>,
3620 Requires<[IsARM, NoV6, UseMulOps]>;
3623 def MLA : AsMul1I32<0b0000001, (outs GPRnopc:$Rd),
3624 (ins GPRnopc:$Rn, GPRnopc:$Rm, GPRnopc:$Ra),
3625 IIC_iMAC32, "mla", "\t$Rd, $Rn, $Rm, $Ra",
3626 [(set GPRnopc:$Rd, (add (mul GPRnopc:$Rn, GPRnopc:$Rm), GPRnopc:$Ra))]>,
3627 Requires<[IsARM, HasV6, UseMulOps]> {
3629 let Inst{15-12} = Ra;
3632 let Constraints = "@earlyclobber $Rd" in
3633 def MLAv5: ARMPseudoExpand<(outs GPRnopc:$Rd),
3634 (ins GPRnopc:$Rn, GPRnopc:$Rm, GPRnopc:$Ra,
3635 pred:$p, cc_out:$s), 4, IIC_iMAC32,
3636 [(set GPRnopc:$Rd, (add (mul GPRnopc:$Rn, GPRnopc:$Rm), GPRnopc:$Ra))],
3637 (MLA GPRnopc:$Rd, GPRnopc:$Rn, GPRnopc:$Rm, GPRnopc:$Ra, pred:$p, cc_out:$s)>,
3638 Requires<[IsARM, NoV6]>;
3640 def MLS : AMul1I<0b0000011, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm, GPR:$Ra),
3641 IIC_iMAC32, "mls", "\t$Rd, $Rn, $Rm, $Ra",
3642 [(set GPR:$Rd, (sub GPR:$Ra, (mul GPR:$Rn, GPR:$Rm)))]>,
3643 Requires<[IsARM, HasV6T2, UseMulOps]> {
3648 let Inst{19-16} = Rd;
3649 let Inst{15-12} = Ra;
3650 let Inst{11-8} = Rm;
3654 // Extra precision multiplies with low / high results
3655 let neverHasSideEffects = 1 in {
3656 let isCommutable = 1 in {
3657 def SMULL : AsMul1I64<0b0000110, (outs GPR:$RdLo, GPR:$RdHi),
3658 (ins GPR:$Rn, GPR:$Rm), IIC_iMUL64,
3659 "smull", "\t$RdLo, $RdHi, $Rn, $Rm", []>,
3660 Requires<[IsARM, HasV6]>;
3662 def UMULL : AsMul1I64<0b0000100, (outs GPR:$RdLo, GPR:$RdHi),
3663 (ins GPR:$Rn, GPR:$Rm), IIC_iMUL64,
3664 "umull", "\t$RdLo, $RdHi, $Rn, $Rm", []>,
3665 Requires<[IsARM, HasV6]>;
3667 let Constraints = "@earlyclobber $RdLo,@earlyclobber $RdHi" in {
3668 def SMULLv5 : ARMPseudoExpand<(outs GPR:$RdLo, GPR:$RdHi),
3669 (ins GPR:$Rn, GPR:$Rm, pred:$p, cc_out:$s),
3671 (SMULL GPR:$RdLo, GPR:$RdHi, GPR:$Rn, GPR:$Rm, pred:$p, cc_out:$s)>,
3672 Requires<[IsARM, NoV6]>;
3674 def UMULLv5 : ARMPseudoExpand<(outs GPR:$RdLo, GPR:$RdHi),
3675 (ins GPR:$Rn, GPR:$Rm, pred:$p, cc_out:$s),
3677 (UMULL GPR:$RdLo, GPR:$RdHi, GPR:$Rn, GPR:$Rm, pred:$p, cc_out:$s)>,
3678 Requires<[IsARM, NoV6]>;
3682 // Multiply + accumulate
3683 def SMLAL : AsMla1I64<0b0000111, (outs GPR:$RdLo, GPR:$RdHi),
3684 (ins GPR:$Rn, GPR:$Rm, GPR:$RLo, GPR:$RHi), IIC_iMAC64,
3685 "smlal", "\t$RdLo, $RdHi, $Rn, $Rm", []>,
3686 RegConstraint<"$RLo = $RdLo, $RHi = $RdHi">, Requires<[IsARM, HasV6]>;
3687 def UMLAL : AsMla1I64<0b0000101, (outs GPR:$RdLo, GPR:$RdHi),
3688 (ins GPR:$Rn, GPR:$Rm, GPR:$RLo, GPR:$RHi), IIC_iMAC64,
3689 "umlal", "\t$RdLo, $RdHi, $Rn, $Rm", []>,
3690 RegConstraint<"$RLo = $RdLo, $RHi = $RdHi">, Requires<[IsARM, HasV6]>;
3692 def UMAAL : AMul1I <0b0000010, (outs GPR:$RdLo, GPR:$RdHi),
3693 (ins GPR:$Rn, GPR:$Rm), IIC_iMAC64,
3694 "umaal", "\t$RdLo, $RdHi, $Rn, $Rm", []>,
3695 Requires<[IsARM, HasV6]> {
3700 let Inst{19-16} = RdHi;
3701 let Inst{15-12} = RdLo;
3702 let Inst{11-8} = Rm;
3707 "@earlyclobber $RdLo,@earlyclobber $RdHi,$RLo = $RdLo,$RHi = $RdHi" in {
3708 def SMLALv5 : ARMPseudoExpand<(outs GPR:$RdLo, GPR:$RdHi),
3709 (ins GPR:$Rn, GPR:$Rm, GPR:$RLo, GPR:$RHi, pred:$p, cc_out:$s),
3711 (SMLAL GPR:$RdLo, GPR:$RdHi, GPR:$Rn, GPR:$Rm, GPR:$RLo, GPR:$RHi,
3712 pred:$p, cc_out:$s)>,
3713 Requires<[IsARM, NoV6]>;
3714 def UMLALv5 : ARMPseudoExpand<(outs GPR:$RdLo, GPR:$RdHi),
3715 (ins GPR:$Rn, GPR:$Rm, GPR:$RLo, GPR:$RHi, pred:$p, cc_out:$s),
3717 (UMLAL GPR:$RdLo, GPR:$RdHi, GPR:$Rn, GPR:$Rm, GPR:$RLo, GPR:$RHi,
3718 pred:$p, cc_out:$s)>,
3719 Requires<[IsARM, NoV6]>;
3722 } // neverHasSideEffects
3724 // Most significant word multiply
3725 def SMMUL : AMul2I <0b0111010, 0b0001, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm),
3726 IIC_iMUL32, "smmul", "\t$Rd, $Rn, $Rm",
3727 [(set GPR:$Rd, (mulhs GPR:$Rn, GPR:$Rm))]>,
3728 Requires<[IsARM, HasV6]> {
3729 let Inst{15-12} = 0b1111;
3732 def SMMULR : AMul2I <0b0111010, 0b0011, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm),
3733 IIC_iMUL32, "smmulr", "\t$Rd, $Rn, $Rm", []>,
3734 Requires<[IsARM, HasV6]> {
3735 let Inst{15-12} = 0b1111;
3738 def SMMLA : AMul2Ia <0b0111010, 0b0001, (outs GPR:$Rd),
3739 (ins GPR:$Rn, GPR:$Rm, GPR:$Ra),
3740 IIC_iMAC32, "smmla", "\t$Rd, $Rn, $Rm, $Ra",
3741 [(set GPR:$Rd, (add (mulhs GPR:$Rn, GPR:$Rm), GPR:$Ra))]>,
3742 Requires<[IsARM, HasV6, UseMulOps]>;
3744 def SMMLAR : AMul2Ia <0b0111010, 0b0011, (outs GPR:$Rd),
3745 (ins GPR:$Rn, GPR:$Rm, GPR:$Ra),
3746 IIC_iMAC32, "smmlar", "\t$Rd, $Rn, $Rm, $Ra", []>,
3747 Requires<[IsARM, HasV6]>;
3749 def SMMLS : AMul2Ia <0b0111010, 0b1101, (outs GPR:$Rd),
3750 (ins GPR:$Rn, GPR:$Rm, GPR:$Ra),
3751 IIC_iMAC32, "smmls", "\t$Rd, $Rn, $Rm, $Ra", []>,
3752 Requires<[IsARM, HasV6, UseMulOps]>;
3754 def SMMLSR : AMul2Ia <0b0111010, 0b1111, (outs GPR:$Rd),
3755 (ins GPR:$Rn, GPR:$Rm, GPR:$Ra),
3756 IIC_iMAC32, "smmlsr", "\t$Rd, $Rn, $Rm, $Ra", []>,
3757 Requires<[IsARM, HasV6]>;
3759 multiclass AI_smul<string opc, PatFrag opnode> {
3760 def BB : AMulxyI<0b0001011, 0b00, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm),
3761 IIC_iMUL16, !strconcat(opc, "bb"), "\t$Rd, $Rn, $Rm",
3762 [(set GPR:$Rd, (opnode (sext_inreg GPR:$Rn, i16),
3763 (sext_inreg GPR:$Rm, i16)))]>,
3764 Requires<[IsARM, HasV5TE]>;
3766 def BT : AMulxyI<0b0001011, 0b10, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm),
3767 IIC_iMUL16, !strconcat(opc, "bt"), "\t$Rd, $Rn, $Rm",
3768 [(set GPR:$Rd, (opnode (sext_inreg GPR:$Rn, i16),
3769 (sra GPR:$Rm, (i32 16))))]>,
3770 Requires<[IsARM, HasV5TE]>;
3772 def TB : AMulxyI<0b0001011, 0b01, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm),
3773 IIC_iMUL16, !strconcat(opc, "tb"), "\t$Rd, $Rn, $Rm",
3774 [(set GPR:$Rd, (opnode (sra GPR:$Rn, (i32 16)),
3775 (sext_inreg GPR:$Rm, i16)))]>,
3776 Requires<[IsARM, HasV5TE]>;
3778 def TT : AMulxyI<0b0001011, 0b11, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm),
3779 IIC_iMUL16, !strconcat(opc, "tt"), "\t$Rd, $Rn, $Rm",
3780 [(set GPR:$Rd, (opnode (sra GPR:$Rn, (i32 16)),
3781 (sra GPR:$Rm, (i32 16))))]>,
3782 Requires<[IsARM, HasV5TE]>;
3784 def WB : AMulxyI<0b0001001, 0b01, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm),
3785 IIC_iMUL16, !strconcat(opc, "wb"), "\t$Rd, $Rn, $Rm",
3786 [(set GPR:$Rd, (sra (opnode GPR:$Rn,
3787 (sext_inreg GPR:$Rm, i16)), (i32 16)))]>,
3788 Requires<[IsARM, HasV5TE]>;
3790 def WT : AMulxyI<0b0001001, 0b11, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm),
3791 IIC_iMUL16, !strconcat(opc, "wt"), "\t$Rd, $Rn, $Rm",
3792 [(set GPR:$Rd, (sra (opnode GPR:$Rn,
3793 (sra GPR:$Rm, (i32 16))), (i32 16)))]>,
3794 Requires<[IsARM, HasV5TE]>;
3798 multiclass AI_smla<string opc, PatFrag opnode> {
3799 let DecoderMethod = "DecodeSMLAInstruction" in {
3800 def BB : AMulxyIa<0b0001000, 0b00, (outs GPRnopc:$Rd),
3801 (ins GPRnopc:$Rn, GPRnopc:$Rm, GPR:$Ra),
3802 IIC_iMAC16, !strconcat(opc, "bb"), "\t$Rd, $Rn, $Rm, $Ra",
3803 [(set GPRnopc:$Rd, (add GPR:$Ra,
3804 (opnode (sext_inreg GPRnopc:$Rn, i16),
3805 (sext_inreg GPRnopc:$Rm, i16))))]>,
3806 Requires<[IsARM, HasV5TE, UseMulOps]>;
3808 def BT : AMulxyIa<0b0001000, 0b10, (outs GPRnopc:$Rd),
3809 (ins GPRnopc:$Rn, GPRnopc:$Rm, GPR:$Ra),
3810 IIC_iMAC16, !strconcat(opc, "bt"), "\t$Rd, $Rn, $Rm, $Ra",
3812 (add GPR:$Ra, (opnode (sext_inreg GPRnopc:$Rn, i16),
3813 (sra GPRnopc:$Rm, (i32 16)))))]>,
3814 Requires<[IsARM, HasV5TE, UseMulOps]>;
3816 def TB : AMulxyIa<0b0001000, 0b01, (outs GPRnopc:$Rd),
3817 (ins GPRnopc:$Rn, GPRnopc:$Rm, GPR:$Ra),
3818 IIC_iMAC16, !strconcat(opc, "tb"), "\t$Rd, $Rn, $Rm, $Ra",
3820 (add GPR:$Ra, (opnode (sra GPRnopc:$Rn, (i32 16)),
3821 (sext_inreg GPRnopc:$Rm, i16))))]>,
3822 Requires<[IsARM, HasV5TE, UseMulOps]>;
3824 def TT : AMulxyIa<0b0001000, 0b11, (outs GPRnopc:$Rd),
3825 (ins GPRnopc:$Rn, GPRnopc:$Rm, GPR:$Ra),
3826 IIC_iMAC16, !strconcat(opc, "tt"), "\t$Rd, $Rn, $Rm, $Ra",
3828 (add GPR:$Ra, (opnode (sra GPRnopc:$Rn, (i32 16)),
3829 (sra GPRnopc:$Rm, (i32 16)))))]>,
3830 Requires<[IsARM, HasV5TE, UseMulOps]>;
3832 def WB : AMulxyIa<0b0001001, 0b00, (outs GPRnopc:$Rd),
3833 (ins GPRnopc:$Rn, GPRnopc:$Rm, GPR:$Ra),
3834 IIC_iMAC16, !strconcat(opc, "wb"), "\t$Rd, $Rn, $Rm, $Ra",
3836 (add GPR:$Ra, (sra (opnode GPRnopc:$Rn,
3837 (sext_inreg GPRnopc:$Rm, i16)), (i32 16))))]>,
3838 Requires<[IsARM, HasV5TE, UseMulOps]>;
3840 def WT : AMulxyIa<0b0001001, 0b10, (outs GPRnopc:$Rd),
3841 (ins GPRnopc:$Rn, GPRnopc:$Rm, GPR:$Ra),
3842 IIC_iMAC16, !strconcat(opc, "wt"), "\t$Rd, $Rn, $Rm, $Ra",
3844 (add GPR:$Ra, (sra (opnode GPRnopc:$Rn,
3845 (sra GPRnopc:$Rm, (i32 16))), (i32 16))))]>,
3846 Requires<[IsARM, HasV5TE, UseMulOps]>;
3850 defm SMUL : AI_smul<"smul", BinOpFrag<(mul node:$LHS, node:$RHS)>>;
3851 defm SMLA : AI_smla<"smla", BinOpFrag<(mul node:$LHS, node:$RHS)>>;
3853 // Halfword multiply accumulate long: SMLAL<x><y>.
3854 def SMLALBB : AMulxyI64<0b0001010, 0b00, (outs GPRnopc:$RdLo, GPRnopc:$RdHi),
3855 (ins GPRnopc:$Rn, GPRnopc:$Rm),
3856 IIC_iMAC64, "smlalbb", "\t$RdLo, $RdHi, $Rn, $Rm", []>,
3857 Requires<[IsARM, HasV5TE]>;
3859 def SMLALBT : AMulxyI64<0b0001010, 0b10, (outs GPRnopc:$RdLo, GPRnopc:$RdHi),
3860 (ins GPRnopc:$Rn, GPRnopc:$Rm),
3861 IIC_iMAC64, "smlalbt", "\t$RdLo, $RdHi, $Rn, $Rm", []>,
3862 Requires<[IsARM, HasV5TE]>;
3864 def SMLALTB : AMulxyI64<0b0001010, 0b01, (outs GPRnopc:$RdLo, GPRnopc:$RdHi),
3865 (ins GPRnopc:$Rn, GPRnopc:$Rm),
3866 IIC_iMAC64, "smlaltb", "\t$RdLo, $RdHi, $Rn, $Rm", []>,
3867 Requires<[IsARM, HasV5TE]>;
3869 def SMLALTT : AMulxyI64<0b0001010, 0b11, (outs GPRnopc:$RdLo, GPRnopc:$RdHi),
3870 (ins GPRnopc:$Rn, GPRnopc:$Rm),
3871 IIC_iMAC64, "smlaltt", "\t$RdLo, $RdHi, $Rn, $Rm", []>,
3872 Requires<[IsARM, HasV5TE]>;
3874 // Helper class for AI_smld.
3875 class AMulDualIbase<bit long, bit sub, bit swap, dag oops, dag iops,
3876 InstrItinClass itin, string opc, string asm>
3877 : AI<oops, iops, MulFrm, itin, opc, asm, []>, Requires<[IsARM, HasV6]> {
3880 let Inst{27-23} = 0b01110;
3881 let Inst{22} = long;
3882 let Inst{21-20} = 0b00;
3883 let Inst{11-8} = Rm;
3890 class AMulDualI<bit long, bit sub, bit swap, dag oops, dag iops,
3891 InstrItinClass itin, string opc, string asm>
3892 : AMulDualIbase<long, sub, swap, oops, iops, itin, opc, asm> {
3894 let Inst{15-12} = 0b1111;
3895 let Inst{19-16} = Rd;
3897 class AMulDualIa<bit long, bit sub, bit swap, dag oops, dag iops,
3898 InstrItinClass itin, string opc, string asm>
3899 : AMulDualIbase<long, sub, swap, oops, iops, itin, opc, asm> {
3902 let Inst{19-16} = Rd;
3903 let Inst{15-12} = Ra;
3905 class AMulDualI64<bit long, bit sub, bit swap, dag oops, dag iops,
3906 InstrItinClass itin, string opc, string asm>
3907 : AMulDualIbase<long, sub, swap, oops, iops, itin, opc, asm> {
3910 let Inst{19-16} = RdHi;
3911 let Inst{15-12} = RdLo;
3914 multiclass AI_smld<bit sub, string opc> {
3916 def D : AMulDualIa<0, sub, 0, (outs GPRnopc:$Rd),
3917 (ins GPRnopc:$Rn, GPRnopc:$Rm, GPR:$Ra),
3918 NoItinerary, !strconcat(opc, "d"), "\t$Rd, $Rn, $Rm, $Ra">;
3920 def DX: AMulDualIa<0, sub, 1, (outs GPRnopc:$Rd),
3921 (ins GPRnopc:$Rn, GPRnopc:$Rm, GPR:$Ra),
3922 NoItinerary, !strconcat(opc, "dx"), "\t$Rd, $Rn, $Rm, $Ra">;
3924 def LD: AMulDualI64<1, sub, 0, (outs GPRnopc:$RdLo, GPRnopc:$RdHi),
3925 (ins GPRnopc:$Rn, GPRnopc:$Rm), NoItinerary,
3926 !strconcat(opc, "ld"), "\t$RdLo, $RdHi, $Rn, $Rm">;
3928 def LDX : AMulDualI64<1, sub, 1, (outs GPRnopc:$RdLo, GPRnopc:$RdHi),
3929 (ins GPRnopc:$Rn, GPRnopc:$Rm), NoItinerary,
3930 !strconcat(opc, "ldx"),"\t$RdLo, $RdHi, $Rn, $Rm">;
3934 defm SMLA : AI_smld<0, "smla">;
3935 defm SMLS : AI_smld<1, "smls">;
3937 multiclass AI_sdml<bit sub, string opc> {
3939 def D:AMulDualI<0, sub, 0, (outs GPRnopc:$Rd), (ins GPRnopc:$Rn, GPRnopc:$Rm),
3940 NoItinerary, !strconcat(opc, "d"), "\t$Rd, $Rn, $Rm">;
3941 def DX:AMulDualI<0, sub, 1, (outs GPRnopc:$Rd),(ins GPRnopc:$Rn, GPRnopc:$Rm),
3942 NoItinerary, !strconcat(opc, "dx"), "\t$Rd, $Rn, $Rm">;
3945 defm SMUA : AI_sdml<0, "smua">;
3946 defm SMUS : AI_sdml<1, "smus">;
3948 //===----------------------------------------------------------------------===//
3949 // Division Instructions (ARMv7-A with virtualization extension)
3951 def SDIV : ADivA1I<0b001, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm), IIC_iDIV,
3952 "sdiv", "\t$Rd, $Rn, $Rm",
3953 [(set GPR:$Rd, (sdiv GPR:$Rn, GPR:$Rm))]>,
3954 Requires<[IsARM, HasDivideInARM]>;
3956 def UDIV : ADivA1I<0b011, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm), IIC_iDIV,
3957 "udiv", "\t$Rd, $Rn, $Rm",
3958 [(set GPR:$Rd, (udiv GPR:$Rn, GPR:$Rm))]>,
3959 Requires<[IsARM, HasDivideInARM]>;
3961 //===----------------------------------------------------------------------===//
3962 // Misc. Arithmetic Instructions.
3965 def CLZ : AMiscA1I<0b000010110, 0b0001, (outs GPR:$Rd), (ins GPR:$Rm),
3966 IIC_iUNAr, "clz", "\t$Rd, $Rm",
3967 [(set GPR:$Rd, (ctlz GPR:$Rm))]>, Requires<[IsARM, HasV5T]>,
3970 def RBIT : AMiscA1I<0b01101111, 0b0011, (outs GPR:$Rd), (ins GPR:$Rm),
3971 IIC_iUNAr, "rbit", "\t$Rd, $Rm",
3972 [(set GPR:$Rd, (ARMrbit GPR:$Rm))]>,
3973 Requires<[IsARM, HasV6T2]>,
3976 def REV : AMiscA1I<0b01101011, 0b0011, (outs GPR:$Rd), (ins GPR:$Rm),
3977 IIC_iUNAr, "rev", "\t$Rd, $Rm",
3978 [(set GPR:$Rd, (bswap GPR:$Rm))]>, Requires<[IsARM, HasV6]>,
3981 let AddedComplexity = 5 in
3982 def REV16 : AMiscA1I<0b01101011, 0b1011, (outs GPR:$Rd), (ins GPR:$Rm),
3983 IIC_iUNAr, "rev16", "\t$Rd, $Rm",
3984 [(set GPR:$Rd, (rotr (bswap GPR:$Rm), (i32 16)))]>,
3985 Requires<[IsARM, HasV6]>,
3988 let AddedComplexity = 5 in
3989 def REVSH : AMiscA1I<0b01101111, 0b1011, (outs GPR:$Rd), (ins GPR:$Rm),
3990 IIC_iUNAr, "revsh", "\t$Rd, $Rm",
3991 [(set GPR:$Rd, (sra (bswap GPR:$Rm), (i32 16)))]>,
3992 Requires<[IsARM, HasV6]>,
3995 def : ARMV6Pat<(or (sra (shl GPR:$Rm, (i32 24)), (i32 16)),
3996 (and (srl GPR:$Rm, (i32 8)), 0xFF)),
3999 def PKHBT : APKHI<0b01101000, 0, (outs GPRnopc:$Rd),
4000 (ins GPRnopc:$Rn, GPRnopc:$Rm, pkh_lsl_amt:$sh),
4001 IIC_iALUsi, "pkhbt", "\t$Rd, $Rn, $Rm$sh",
4002 [(set GPRnopc:$Rd, (or (and GPRnopc:$Rn, 0xFFFF),
4003 (and (shl GPRnopc:$Rm, pkh_lsl_amt:$sh),
4005 Requires<[IsARM, HasV6]>,
4006 Sched<[WriteALUsi, ReadALU]>;
4008 // Alternate cases for PKHBT where identities eliminate some nodes.
4009 def : ARMV6Pat<(or (and GPRnopc:$Rn, 0xFFFF), (and GPRnopc:$Rm, 0xFFFF0000)),
4010 (PKHBT GPRnopc:$Rn, GPRnopc:$Rm, 0)>;
4011 def : ARMV6Pat<(or (and GPRnopc:$Rn, 0xFFFF), (shl GPRnopc:$Rm, imm16_31:$sh)),
4012 (PKHBT GPRnopc:$Rn, GPRnopc:$Rm, imm16_31:$sh)>;
4014 // Note: Shifts of 1-15 bits will be transformed to srl instead of sra and
4015 // will match the pattern below.
4016 def PKHTB : APKHI<0b01101000, 1, (outs GPRnopc:$Rd),
4017 (ins GPRnopc:$Rn, GPRnopc:$Rm, pkh_asr_amt:$sh),
4018 IIC_iBITsi, "pkhtb", "\t$Rd, $Rn, $Rm$sh",
4019 [(set GPRnopc:$Rd, (or (and GPRnopc:$Rn, 0xFFFF0000),
4020 (and (sra GPRnopc:$Rm, pkh_asr_amt:$sh),
4022 Requires<[IsARM, HasV6]>,
4023 Sched<[WriteALUsi, ReadALU]>;
4025 // Alternate cases for PKHTB where identities eliminate some nodes. Note that
4026 // a shift amount of 0 is *not legal* here, it is PKHBT instead.
4027 // We also can not replace a srl (17..31) by an arithmetic shift we would use in
4028 // pkhtb src1, src2, asr (17..31).
4029 def : ARMV6Pat<(or (and GPRnopc:$src1, 0xFFFF0000),
4030 (srl GPRnopc:$src2, imm16:$sh)),
4031 (PKHTB GPRnopc:$src1, GPRnopc:$src2, imm16:$sh)>;
4032 def : ARMV6Pat<(or (and GPRnopc:$src1, 0xFFFF0000),
4033 (sra GPRnopc:$src2, imm16_31:$sh)),
4034 (PKHTB GPRnopc:$src1, GPRnopc:$src2, imm16_31:$sh)>;
4035 def : ARMV6Pat<(or (and GPRnopc:$src1, 0xFFFF0000),
4036 (and (srl GPRnopc:$src2, imm1_15:$sh), 0xFFFF)),
4037 (PKHTB GPRnopc:$src1, GPRnopc:$src2, imm1_15:$sh)>;
4039 //===----------------------------------------------------------------------===//
4043 // + CRC32{B,H,W} 0x04C11DB7
4044 // + CRC32C{B,H,W} 0x1EDC6F41
4047 class AI_crc32<bit C, bits<2> sz, string suffix, SDPatternOperator builtin>
4048 : AInoP<(outs GPRnopc:$Rd), (ins GPRnopc:$Rn, GPRnopc:$Rm), MiscFrm, NoItinerary,
4049 !strconcat("crc32", suffix), "\t$Rd, $Rn, $Rm",
4050 [(set GPRnopc:$Rd, (builtin GPRnopc:$Rn, GPRnopc:$Rm))]>,
4051 Requires<[IsARM, HasV8, HasCRC]> {
4056 let Inst{31-28} = 0b1110;
4057 let Inst{27-23} = 0b00010;
4058 let Inst{22-21} = sz;
4060 let Inst{19-16} = Rn;
4061 let Inst{15-12} = Rd;
4062 let Inst{11-10} = 0b00;
4065 let Inst{7-4} = 0b0100;
4068 let Unpredictable{11-8} = 0b1101;
4071 def CRC32B : AI_crc32<0, 0b00, "b", int_arm_crc32b>;
4072 def CRC32CB : AI_crc32<1, 0b00, "cb", int_arm_crc32cb>;
4073 def CRC32H : AI_crc32<0, 0b01, "h", int_arm_crc32h>;
4074 def CRC32CH : AI_crc32<1, 0b01, "ch", int_arm_crc32ch>;
4075 def CRC32W : AI_crc32<0, 0b10, "w", int_arm_crc32w>;
4076 def CRC32CW : AI_crc32<1, 0b10, "cw", int_arm_crc32cw>;
4078 //===----------------------------------------------------------------------===//
4079 // Comparison Instructions...
4082 defm CMP : AI1_cmp_irs<0b1010, "cmp",
4083 IIC_iCMPi, IIC_iCMPr, IIC_iCMPsr,
4084 BinOpFrag<(ARMcmp node:$LHS, node:$RHS)>>;
4086 // ARMcmpZ can re-use the above instruction definitions.
4087 def : ARMPat<(ARMcmpZ GPR:$src, so_imm:$imm),
4088 (CMPri GPR:$src, so_imm:$imm)>;
4089 def : ARMPat<(ARMcmpZ GPR:$src, GPR:$rhs),
4090 (CMPrr GPR:$src, GPR:$rhs)>;
4091 def : ARMPat<(ARMcmpZ GPR:$src, so_reg_imm:$rhs),
4092 (CMPrsi GPR:$src, so_reg_imm:$rhs)>;
4093 def : ARMPat<(ARMcmpZ GPR:$src, so_reg_reg:$rhs),
4094 (CMPrsr GPR:$src, so_reg_reg:$rhs)>;
4096 // CMN register-integer
4097 let isCompare = 1, Defs = [CPSR] in {
4098 def CMNri : AI1<0b1011, (outs), (ins GPR:$Rn, so_imm:$imm), DPFrm, IIC_iCMPi,
4099 "cmn", "\t$Rn, $imm",
4100 [(ARMcmn GPR:$Rn, so_imm:$imm)]>,
4101 Sched<[WriteCMP, ReadALU]> {
4106 let Inst{19-16} = Rn;
4107 let Inst{15-12} = 0b0000;
4108 let Inst{11-0} = imm;
4110 let Unpredictable{15-12} = 0b1111;
4113 // CMN register-register/shift
4114 def CMNzrr : AI1<0b1011, (outs), (ins GPR:$Rn, GPR:$Rm), DPFrm, IIC_iCMPr,
4115 "cmn", "\t$Rn, $Rm",
4116 [(BinOpFrag<(ARMcmpZ node:$LHS,(ineg node:$RHS))>
4117 GPR:$Rn, GPR:$Rm)]>, Sched<[WriteCMP, ReadALU, ReadALU]> {
4120 let isCommutable = 1;
4123 let Inst{19-16} = Rn;
4124 let Inst{15-12} = 0b0000;
4125 let Inst{11-4} = 0b00000000;
4128 let Unpredictable{15-12} = 0b1111;
4131 def CMNzrsi : AI1<0b1011, (outs),
4132 (ins GPR:$Rn, so_reg_imm:$shift), DPSoRegImmFrm, IIC_iCMPsr,
4133 "cmn", "\t$Rn, $shift",
4134 [(BinOpFrag<(ARMcmpZ node:$LHS,(ineg node:$RHS))>
4135 GPR:$Rn, so_reg_imm:$shift)]>,
4136 Sched<[WriteCMPsi, ReadALU]> {
4141 let Inst{19-16} = Rn;
4142 let Inst{15-12} = 0b0000;
4143 let Inst{11-5} = shift{11-5};
4145 let Inst{3-0} = shift{3-0};
4147 let Unpredictable{15-12} = 0b1111;
4150 def CMNzrsr : AI1<0b1011, (outs),
4151 (ins GPRnopc:$Rn, so_reg_reg:$shift), DPSoRegRegFrm, IIC_iCMPsr,
4152 "cmn", "\t$Rn, $shift",
4153 [(BinOpFrag<(ARMcmpZ node:$LHS,(ineg node:$RHS))>
4154 GPRnopc:$Rn, so_reg_reg:$shift)]>,
4155 Sched<[WriteCMPsr, ReadALU]> {
4160 let Inst{19-16} = Rn;
4161 let Inst{15-12} = 0b0000;
4162 let Inst{11-8} = shift{11-8};
4164 let Inst{6-5} = shift{6-5};
4166 let Inst{3-0} = shift{3-0};
4168 let Unpredictable{15-12} = 0b1111;
4173 def : ARMPat<(ARMcmp GPR:$src, so_imm_neg:$imm),
4174 (CMNri GPR:$src, so_imm_neg:$imm)>;
4176 def : ARMPat<(ARMcmpZ GPR:$src, so_imm_neg:$imm),
4177 (CMNri GPR:$src, so_imm_neg:$imm)>;
4179 // Note that TST/TEQ don't set all the same flags that CMP does!
4180 defm TST : AI1_cmp_irs<0b1000, "tst",
4181 IIC_iTSTi, IIC_iTSTr, IIC_iTSTsr,
4182 BinOpFrag<(ARMcmpZ (and_su node:$LHS, node:$RHS), 0)>, 1>;
4183 defm TEQ : AI1_cmp_irs<0b1001, "teq",
4184 IIC_iTSTi, IIC_iTSTr, IIC_iTSTsr,
4185 BinOpFrag<(ARMcmpZ (xor_su node:$LHS, node:$RHS), 0)>, 1>;
4187 // Pseudo i64 compares for some floating point compares.
4188 let usesCustomInserter = 1, isBranch = 1, isTerminator = 1,
4190 def BCCi64 : PseudoInst<(outs),
4191 (ins i32imm:$cc, GPR:$lhs1, GPR:$lhs2, GPR:$rhs1, GPR:$rhs2, brtarget:$dst),
4193 [(ARMBcci64 imm:$cc, GPR:$lhs1, GPR:$lhs2, GPR:$rhs1, GPR:$rhs2, bb:$dst)]>,
4196 def BCCZi64 : PseudoInst<(outs),
4197 (ins i32imm:$cc, GPR:$lhs1, GPR:$lhs2, brtarget:$dst), IIC_Br,
4198 [(ARMBcci64 imm:$cc, GPR:$lhs1, GPR:$lhs2, 0, 0, bb:$dst)]>,
4200 } // usesCustomInserter
4203 // Conditional moves
4204 let neverHasSideEffects = 1 in {
4206 let isCommutable = 1, isSelect = 1 in
4207 def MOVCCr : ARMPseudoInst<(outs GPR:$Rd),
4208 (ins GPR:$false, GPR:$Rm, cmovpred:$p),
4210 [(set GPR:$Rd, (ARMcmov GPR:$false, GPR:$Rm,
4212 RegConstraint<"$false = $Rd">, Sched<[WriteALU]>;
4214 def MOVCCsi : ARMPseudoInst<(outs GPR:$Rd),
4215 (ins GPR:$false, so_reg_imm:$shift, cmovpred:$p),
4218 (ARMcmov GPR:$false, so_reg_imm:$shift,
4220 RegConstraint<"$false = $Rd">, Sched<[WriteALU]>;
4221 def MOVCCsr : ARMPseudoInst<(outs GPR:$Rd),
4222 (ins GPR:$false, so_reg_reg:$shift, cmovpred:$p),
4224 [(set GPR:$Rd, (ARMcmov GPR:$false, so_reg_reg:$shift,
4226 RegConstraint<"$false = $Rd">, Sched<[WriteALU]>;
4229 let isMoveImm = 1 in
4231 : ARMPseudoInst<(outs GPR:$Rd),
4232 (ins GPR:$false, imm0_65535_expr:$imm, cmovpred:$p),
4234 [(set GPR:$Rd, (ARMcmov GPR:$false, imm0_65535:$imm,
4236 RegConstraint<"$false = $Rd">, Requires<[IsARM, HasV6T2]>,
4239 let isMoveImm = 1 in
4240 def MOVCCi : ARMPseudoInst<(outs GPR:$Rd),
4241 (ins GPR:$false, so_imm:$imm, cmovpred:$p),
4243 [(set GPR:$Rd, (ARMcmov GPR:$false, so_imm:$imm,
4245 RegConstraint<"$false = $Rd">, Sched<[WriteALU]>;
4247 // Two instruction predicate mov immediate.
4248 let isMoveImm = 1 in
4250 : ARMPseudoInst<(outs GPR:$Rd),
4251 (ins GPR:$false, i32imm:$src, cmovpred:$p),
4253 [(set GPR:$Rd, (ARMcmov GPR:$false, imm:$src,
4255 RegConstraint<"$false = $Rd">, Requires<[IsARM, HasV6T2]>;
4257 let isMoveImm = 1 in
4258 def MVNCCi : ARMPseudoInst<(outs GPR:$Rd),
4259 (ins GPR:$false, so_imm:$imm, cmovpred:$p),
4261 [(set GPR:$Rd, (ARMcmov GPR:$false, so_imm_not:$imm,
4263 RegConstraint<"$false = $Rd">, Sched<[WriteALU]>;
4265 } // neverHasSideEffects
4268 //===----------------------------------------------------------------------===//
4269 // Atomic operations intrinsics
4272 def MemBarrierOptOperand : AsmOperandClass {
4273 let Name = "MemBarrierOpt";
4274 let ParserMethod = "parseMemBarrierOptOperand";
4276 def memb_opt : Operand<i32> {
4277 let PrintMethod = "printMemBOption";
4278 let ParserMatchClass = MemBarrierOptOperand;
4279 let DecoderMethod = "DecodeMemBarrierOption";
4282 def InstSyncBarrierOptOperand : AsmOperandClass {
4283 let Name = "InstSyncBarrierOpt";
4284 let ParserMethod = "parseInstSyncBarrierOptOperand";
4286 def instsyncb_opt : Operand<i32> {
4287 let PrintMethod = "printInstSyncBOption";
4288 let ParserMatchClass = InstSyncBarrierOptOperand;
4289 let DecoderMethod = "DecodeInstSyncBarrierOption";
4292 // memory barriers protect the atomic sequences
4293 let hasSideEffects = 1 in {
4294 def DMB : AInoP<(outs), (ins memb_opt:$opt), MiscFrm, NoItinerary,
4295 "dmb", "\t$opt", [(int_arm_dmb (i32 imm0_15:$opt))]>,
4296 Requires<[IsARM, HasDB]> {
4298 let Inst{31-4} = 0xf57ff05;
4299 let Inst{3-0} = opt;
4303 def DSB : AInoP<(outs), (ins memb_opt:$opt), MiscFrm, NoItinerary,
4304 "dsb", "\t$opt", [(int_arm_dsb (i32 imm0_15:$opt))]>,
4305 Requires<[IsARM, HasDB]> {
4307 let Inst{31-4} = 0xf57ff04;
4308 let Inst{3-0} = opt;
4311 // ISB has only full system option
4312 def ISB : AInoP<(outs), (ins instsyncb_opt:$opt), MiscFrm, NoItinerary,
4313 "isb", "\t$opt", []>,
4314 Requires<[IsARM, HasDB]> {
4316 let Inst{31-4} = 0xf57ff06;
4317 let Inst{3-0} = opt;
4320 let usesCustomInserter = 1, Defs = [CPSR] in {
4322 // Pseudo instruction that combines movs + predicated rsbmi
4323 // to implement integer ABS
4324 def ABS : ARMPseudoInst<(outs GPR:$dst), (ins GPR:$src), 8, NoItinerary, []>;
4327 let usesCustomInserter = 1 in {
4328 def COPY_STRUCT_BYVAL_I32 : PseudoInst<
4329 (outs), (ins GPR:$dst, GPR:$src, i32imm:$size, i32imm:$alignment),
4331 [(ARMcopystructbyval GPR:$dst, GPR:$src, imm:$size, imm:$alignment)]>;
4334 def ldrex_1 : PatFrag<(ops node:$ptr), (int_arm_ldrex node:$ptr), [{
4335 return cast<MemIntrinsicSDNode>(N)->getMemoryVT() == MVT::i8;
4338 def ldrex_2 : PatFrag<(ops node:$ptr), (int_arm_ldrex node:$ptr), [{
4339 return cast<MemIntrinsicSDNode>(N)->getMemoryVT() == MVT::i16;
4342 def ldrex_4 : PatFrag<(ops node:$ptr), (int_arm_ldrex node:$ptr), [{
4343 return cast<MemIntrinsicSDNode>(N)->getMemoryVT() == MVT::i32;
4346 def strex_1 : PatFrag<(ops node:$val, node:$ptr),
4347 (int_arm_strex node:$val, node:$ptr), [{
4348 return cast<MemIntrinsicSDNode>(N)->getMemoryVT() == MVT::i8;
4351 def strex_2 : PatFrag<(ops node:$val, node:$ptr),
4352 (int_arm_strex node:$val, node:$ptr), [{
4353 return cast<MemIntrinsicSDNode>(N)->getMemoryVT() == MVT::i16;
4356 def strex_4 : PatFrag<(ops node:$val, node:$ptr),
4357 (int_arm_strex node:$val, node:$ptr), [{
4358 return cast<MemIntrinsicSDNode>(N)->getMemoryVT() == MVT::i32;
4361 def ldaex_1 : PatFrag<(ops node:$ptr), (int_arm_ldaex node:$ptr), [{
4362 return cast<MemIntrinsicSDNode>(N)->getMemoryVT() == MVT::i8;
4365 def ldaex_2 : PatFrag<(ops node:$ptr), (int_arm_ldaex node:$ptr), [{
4366 return cast<MemIntrinsicSDNode>(N)->getMemoryVT() == MVT::i16;
4369 def ldaex_4 : PatFrag<(ops node:$ptr), (int_arm_ldaex node:$ptr), [{
4370 return cast<MemIntrinsicSDNode>(N)->getMemoryVT() == MVT::i32;
4373 def stlex_1 : PatFrag<(ops node:$val, node:$ptr),
4374 (int_arm_stlex node:$val, node:$ptr), [{
4375 return cast<MemIntrinsicSDNode>(N)->getMemoryVT() == MVT::i8;
4378 def stlex_2 : PatFrag<(ops node:$val, node:$ptr),
4379 (int_arm_stlex node:$val, node:$ptr), [{
4380 return cast<MemIntrinsicSDNode>(N)->getMemoryVT() == MVT::i16;
4383 def stlex_4 : PatFrag<(ops node:$val, node:$ptr),
4384 (int_arm_stlex node:$val, node:$ptr), [{
4385 return cast<MemIntrinsicSDNode>(N)->getMemoryVT() == MVT::i32;
4388 let mayLoad = 1 in {
4389 def LDREXB : AIldrex<0b10, (outs GPR:$Rt), (ins addr_offset_none:$addr),
4390 NoItinerary, "ldrexb", "\t$Rt, $addr",
4391 [(set GPR:$Rt, (ldrex_1 addr_offset_none:$addr))]>;
4392 def LDREXH : AIldrex<0b11, (outs GPR:$Rt), (ins addr_offset_none:$addr),
4393 NoItinerary, "ldrexh", "\t$Rt, $addr",
4394 [(set GPR:$Rt, (ldrex_2 addr_offset_none:$addr))]>;
4395 def LDREX : AIldrex<0b00, (outs GPR:$Rt), (ins addr_offset_none:$addr),
4396 NoItinerary, "ldrex", "\t$Rt, $addr",
4397 [(set GPR:$Rt, (ldrex_4 addr_offset_none:$addr))]>;
4398 let hasExtraDefRegAllocReq = 1 in
4399 def LDREXD : AIldrex<0b01, (outs GPRPairOp:$Rt),(ins addr_offset_none:$addr),
4400 NoItinerary, "ldrexd", "\t$Rt, $addr", []> {
4401 let DecoderMethod = "DecodeDoubleRegLoad";
4404 def LDAEXB : AIldaex<0b10, (outs GPR:$Rt), (ins addr_offset_none:$addr),
4405 NoItinerary, "ldaexb", "\t$Rt, $addr",
4406 [(set GPR:$Rt, (ldaex_1 addr_offset_none:$addr))]>;
4407 def LDAEXH : AIldaex<0b11, (outs GPR:$Rt), (ins addr_offset_none:$addr),
4408 NoItinerary, "ldaexh", "\t$Rt, $addr",
4409 [(set GPR:$Rt, (ldaex_2 addr_offset_none:$addr))]>;
4410 def LDAEX : AIldaex<0b00, (outs GPR:$Rt), (ins addr_offset_none:$addr),
4411 NoItinerary, "ldaex", "\t$Rt, $addr",
4412 [(set GPR:$Rt, (ldaex_4 addr_offset_none:$addr))]>;
4413 let hasExtraDefRegAllocReq = 1 in
4414 def LDAEXD : AIldaex<0b01, (outs GPRPairOp:$Rt),(ins addr_offset_none:$addr),
4415 NoItinerary, "ldaexd", "\t$Rt, $addr", []> {
4416 let DecoderMethod = "DecodeDoubleRegLoad";
4420 let mayStore = 1, Constraints = "@earlyclobber $Rd" in {
4421 def STREXB: AIstrex<0b10, (outs GPR:$Rd), (ins GPR:$Rt, addr_offset_none:$addr),
4422 NoItinerary, "strexb", "\t$Rd, $Rt, $addr",
4423 [(set GPR:$Rd, (strex_1 GPR:$Rt,
4424 addr_offset_none:$addr))]>;
4425 def STREXH: AIstrex<0b11, (outs GPR:$Rd), (ins GPR:$Rt, addr_offset_none:$addr),
4426 NoItinerary, "strexh", "\t$Rd, $Rt, $addr",
4427 [(set GPR:$Rd, (strex_2 GPR:$Rt,
4428 addr_offset_none:$addr))]>;
4429 def STREX : AIstrex<0b00, (outs GPR:$Rd), (ins GPR:$Rt, addr_offset_none:$addr),
4430 NoItinerary, "strex", "\t$Rd, $Rt, $addr",
4431 [(set GPR:$Rd, (strex_4 GPR:$Rt,
4432 addr_offset_none:$addr))]>;
4433 let hasExtraSrcRegAllocReq = 1 in
4434 def STREXD : AIstrex<0b01, (outs GPR:$Rd),
4435 (ins GPRPairOp:$Rt, addr_offset_none:$addr),
4436 NoItinerary, "strexd", "\t$Rd, $Rt, $addr", []> {
4437 let DecoderMethod = "DecodeDoubleRegStore";
4439 def STLEXB: AIstlex<0b10, (outs GPR:$Rd), (ins GPR:$Rt, addr_offset_none:$addr),
4440 NoItinerary, "stlexb", "\t$Rd, $Rt, $addr",
4442 (stlex_1 GPR:$Rt, addr_offset_none:$addr))]>;
4443 def STLEXH: AIstlex<0b11, (outs GPR:$Rd), (ins GPR:$Rt, addr_offset_none:$addr),
4444 NoItinerary, "stlexh", "\t$Rd, $Rt, $addr",
4446 (stlex_2 GPR:$Rt, addr_offset_none:$addr))]>;
4447 def STLEX : AIstlex<0b00, (outs GPR:$Rd), (ins GPR:$Rt, addr_offset_none:$addr),
4448 NoItinerary, "stlex", "\t$Rd, $Rt, $addr",
4450 (stlex_4 GPR:$Rt, addr_offset_none:$addr))]>;
4451 let hasExtraSrcRegAllocReq = 1 in
4452 def STLEXD : AIstlex<0b01, (outs GPR:$Rd),
4453 (ins GPRPairOp:$Rt, addr_offset_none:$addr),
4454 NoItinerary, "stlexd", "\t$Rd, $Rt, $addr", []> {
4455 let DecoderMethod = "DecodeDoubleRegStore";
4459 def CLREX : AXI<(outs), (ins), MiscFrm, NoItinerary, "clrex",
4461 Requires<[IsARM, HasV7]> {
4462 let Inst{31-0} = 0b11110101011111111111000000011111;
4465 def : ARMPat<(strex_1 (and GPR:$Rt, 0xff), addr_offset_none:$addr),
4466 (STREXB GPR:$Rt, addr_offset_none:$addr)>;
4467 def : ARMPat<(strex_2 (and GPR:$Rt, 0xffff), addr_offset_none:$addr),
4468 (STREXH GPR:$Rt, addr_offset_none:$addr)>;
4470 def : ARMPat<(stlex_1 (and GPR:$Rt, 0xff), addr_offset_none:$addr),
4471 (STLEXB GPR:$Rt, addr_offset_none:$addr)>;
4472 def : ARMPat<(stlex_2 (and GPR:$Rt, 0xffff), addr_offset_none:$addr),
4473 (STLEXH GPR:$Rt, addr_offset_none:$addr)>;
4475 class acquiring_load<PatFrag base>
4476 : PatFrag<(ops node:$ptr), (base node:$ptr), [{
4477 AtomicOrdering Ordering = cast<AtomicSDNode>(N)->getOrdering();
4478 return Ordering == Acquire || Ordering == SequentiallyConsistent;
4481 def atomic_load_acquire_8 : acquiring_load<atomic_load_8>;
4482 def atomic_load_acquire_16 : acquiring_load<atomic_load_16>;
4483 def atomic_load_acquire_32 : acquiring_load<atomic_load_32>;
4485 class releasing_store<PatFrag base>
4486 : PatFrag<(ops node:$ptr, node:$val), (base node:$ptr, node:$val), [{
4487 AtomicOrdering Ordering = cast<AtomicSDNode>(N)->getOrdering();
4488 return Ordering == Release || Ordering == SequentiallyConsistent;
4491 def atomic_store_release_8 : releasing_store<atomic_store_8>;
4492 def atomic_store_release_16 : releasing_store<atomic_store_16>;
4493 def atomic_store_release_32 : releasing_store<atomic_store_32>;
4495 let AddedComplexity = 8 in {
4496 def : ARMPat<(atomic_load_acquire_8 addr_offset_none:$addr), (LDAB addr_offset_none:$addr)>;
4497 def : ARMPat<(atomic_load_acquire_16 addr_offset_none:$addr), (LDAH addr_offset_none:$addr)>;
4498 def : ARMPat<(atomic_load_acquire_32 addr_offset_none:$addr), (LDA addr_offset_none:$addr)>;
4499 def : ARMPat<(atomic_store_release_8 addr_offset_none:$addr, GPR:$val), (STLB GPR:$val, addr_offset_none:$addr)>;
4500 def : ARMPat<(atomic_store_release_16 addr_offset_none:$addr, GPR:$val), (STLH GPR:$val, addr_offset_none:$addr)>;
4501 def : ARMPat<(atomic_store_release_32 addr_offset_none:$addr, GPR:$val), (STL GPR:$val, addr_offset_none:$addr)>;
4504 // SWP/SWPB are deprecated in V6/V7.
4505 let mayLoad = 1, mayStore = 1 in {
4506 def SWP : AIswp<0, (outs GPRnopc:$Rt),
4507 (ins GPRnopc:$Rt2, addr_offset_none:$addr), "swp", []>,
4509 def SWPB: AIswp<1, (outs GPRnopc:$Rt),
4510 (ins GPRnopc:$Rt2, addr_offset_none:$addr), "swpb", []>,
4514 //===----------------------------------------------------------------------===//
4515 // Coprocessor Instructions.
4518 def CDP : ABI<0b1110, (outs), (ins p_imm:$cop, imm0_15:$opc1,
4519 c_imm:$CRd, c_imm:$CRn, c_imm:$CRm, imm0_7:$opc2),
4520 NoItinerary, "cdp", "\t$cop, $opc1, $CRd, $CRn, $CRm, $opc2",
4521 [(int_arm_cdp imm:$cop, imm:$opc1, imm:$CRd, imm:$CRn,
4522 imm:$CRm, imm:$opc2)]>,
4531 let Inst{3-0} = CRm;
4533 let Inst{7-5} = opc2;
4534 let Inst{11-8} = cop;
4535 let Inst{15-12} = CRd;
4536 let Inst{19-16} = CRn;
4537 let Inst{23-20} = opc1;
4540 def CDP2 : ABXI<0b1110, (outs), (ins p_imm:$cop, imm0_15:$opc1,
4541 c_imm:$CRd, c_imm:$CRn, c_imm:$CRm, imm0_7:$opc2),
4542 NoItinerary, "cdp2\t$cop, $opc1, $CRd, $CRn, $CRm, $opc2",
4543 [(int_arm_cdp2 imm:$cop, imm:$opc1, imm:$CRd, imm:$CRn,
4544 imm:$CRm, imm:$opc2)]>,
4546 let Inst{31-28} = 0b1111;
4554 let Inst{3-0} = CRm;
4556 let Inst{7-5} = opc2;
4557 let Inst{11-8} = cop;
4558 let Inst{15-12} = CRd;
4559 let Inst{19-16} = CRn;
4560 let Inst{23-20} = opc1;
4563 class ACI<dag oops, dag iops, string opc, string asm,
4564 IndexMode im = IndexModeNone>
4565 : I<oops, iops, AddrModeNone, 4, im, BrFrm, NoItinerary,
4567 let Inst{27-25} = 0b110;
4569 class ACInoP<dag oops, dag iops, string opc, string asm,
4570 IndexMode im = IndexModeNone>
4571 : InoP<oops, iops, AddrModeNone, 4, im, BrFrm, NoItinerary,
4573 let Inst{31-28} = 0b1111;
4574 let Inst{27-25} = 0b110;
4576 multiclass LdStCop<bit load, bit Dbit, string asm> {
4577 def _OFFSET : ACI<(outs), (ins p_imm:$cop, c_imm:$CRd, addrmode5:$addr),
4578 asm, "\t$cop, $CRd, $addr"> {
4582 let Inst{24} = 1; // P = 1
4583 let Inst{23} = addr{8};
4584 let Inst{22} = Dbit;
4585 let Inst{21} = 0; // W = 0
4586 let Inst{20} = load;
4587 let Inst{19-16} = addr{12-9};
4588 let Inst{15-12} = CRd;
4589 let Inst{11-8} = cop;
4590 let Inst{7-0} = addr{7-0};
4591 let DecoderMethod = "DecodeCopMemInstruction";
4593 def _PRE : ACI<(outs), (ins p_imm:$cop, c_imm:$CRd, addrmode5_pre:$addr),
4594 asm, "\t$cop, $CRd, $addr!", IndexModePre> {
4598 let Inst{24} = 1; // P = 1
4599 let Inst{23} = addr{8};
4600 let Inst{22} = Dbit;
4601 let Inst{21} = 1; // W = 1
4602 let Inst{20} = load;
4603 let Inst{19-16} = addr{12-9};
4604 let Inst{15-12} = CRd;
4605 let Inst{11-8} = cop;
4606 let Inst{7-0} = addr{7-0};
4607 let DecoderMethod = "DecodeCopMemInstruction";
4609 def _POST: ACI<(outs), (ins p_imm:$cop, c_imm:$CRd, addr_offset_none:$addr,
4610 postidx_imm8s4:$offset),
4611 asm, "\t$cop, $CRd, $addr, $offset", IndexModePost> {
4616 let Inst{24} = 0; // P = 0
4617 let Inst{23} = offset{8};
4618 let Inst{22} = Dbit;
4619 let Inst{21} = 1; // W = 1
4620 let Inst{20} = load;
4621 let Inst{19-16} = addr;
4622 let Inst{15-12} = CRd;
4623 let Inst{11-8} = cop;
4624 let Inst{7-0} = offset{7-0};
4625 let DecoderMethod = "DecodeCopMemInstruction";
4627 def _OPTION : ACI<(outs),
4628 (ins p_imm:$cop, c_imm:$CRd, addr_offset_none:$addr,
4629 coproc_option_imm:$option),
4630 asm, "\t$cop, $CRd, $addr, $option"> {
4635 let Inst{24} = 0; // P = 0
4636 let Inst{23} = 1; // U = 1
4637 let Inst{22} = Dbit;
4638 let Inst{21} = 0; // W = 0
4639 let Inst{20} = load;
4640 let Inst{19-16} = addr;
4641 let Inst{15-12} = CRd;
4642 let Inst{11-8} = cop;
4643 let Inst{7-0} = option;
4644 let DecoderMethod = "DecodeCopMemInstruction";
4647 multiclass LdSt2Cop<bit load, bit Dbit, string asm> {
4648 def _OFFSET : ACInoP<(outs), (ins p_imm:$cop, c_imm:$CRd, addrmode5:$addr),
4649 asm, "\t$cop, $CRd, $addr"> {
4653 let Inst{24} = 1; // P = 1
4654 let Inst{23} = addr{8};
4655 let Inst{22} = Dbit;
4656 let Inst{21} = 0; // W = 0
4657 let Inst{20} = load;
4658 let Inst{19-16} = addr{12-9};
4659 let Inst{15-12} = CRd;
4660 let Inst{11-8} = cop;
4661 let Inst{7-0} = addr{7-0};
4662 let DecoderMethod = "DecodeCopMemInstruction";
4664 def _PRE : ACInoP<(outs), (ins p_imm:$cop, c_imm:$CRd, addrmode5_pre:$addr),
4665 asm, "\t$cop, $CRd, $addr!", IndexModePre> {
4669 let Inst{24} = 1; // P = 1
4670 let Inst{23} = addr{8};
4671 let Inst{22} = Dbit;
4672 let Inst{21} = 1; // W = 1
4673 let Inst{20} = load;
4674 let Inst{19-16} = addr{12-9};
4675 let Inst{15-12} = CRd;
4676 let Inst{11-8} = cop;
4677 let Inst{7-0} = addr{7-0};
4678 let DecoderMethod = "DecodeCopMemInstruction";
4680 def _POST: ACInoP<(outs), (ins p_imm:$cop, c_imm:$CRd, addr_offset_none:$addr,
4681 postidx_imm8s4:$offset),
4682 asm, "\t$cop, $CRd, $addr, $offset", IndexModePost> {
4687 let Inst{24} = 0; // P = 0
4688 let Inst{23} = offset{8};
4689 let Inst{22} = Dbit;
4690 let Inst{21} = 1; // W = 1
4691 let Inst{20} = load;
4692 let Inst{19-16} = addr;
4693 let Inst{15-12} = CRd;
4694 let Inst{11-8} = cop;
4695 let Inst{7-0} = offset{7-0};
4696 let DecoderMethod = "DecodeCopMemInstruction";
4698 def _OPTION : ACInoP<(outs),
4699 (ins p_imm:$cop, c_imm:$CRd, addr_offset_none:$addr,
4700 coproc_option_imm:$option),
4701 asm, "\t$cop, $CRd, $addr, $option"> {
4706 let Inst{24} = 0; // P = 0
4707 let Inst{23} = 1; // U = 1
4708 let Inst{22} = Dbit;
4709 let Inst{21} = 0; // W = 0
4710 let Inst{20} = load;
4711 let Inst{19-16} = addr;
4712 let Inst{15-12} = CRd;
4713 let Inst{11-8} = cop;
4714 let Inst{7-0} = option;
4715 let DecoderMethod = "DecodeCopMemInstruction";
4719 defm LDC : LdStCop <1, 0, "ldc">;
4720 defm LDCL : LdStCop <1, 1, "ldcl">;
4721 defm STC : LdStCop <0, 0, "stc">;
4722 defm STCL : LdStCop <0, 1, "stcl">;
4723 defm LDC2 : LdSt2Cop<1, 0, "ldc2">, Requires<[PreV8]>;
4724 defm LDC2L : LdSt2Cop<1, 1, "ldc2l">, Requires<[PreV8]>;
4725 defm STC2 : LdSt2Cop<0, 0, "stc2">, Requires<[PreV8]>;
4726 defm STC2L : LdSt2Cop<0, 1, "stc2l">, Requires<[PreV8]>;
4728 //===----------------------------------------------------------------------===//
4729 // Move between coprocessor and ARM core register.
4732 class MovRCopro<string opc, bit direction, dag oops, dag iops,
4734 : ABI<0b1110, oops, iops, NoItinerary, opc,
4735 "\t$cop, $opc1, $Rt, $CRn, $CRm, $opc2", pattern> {
4736 let Inst{20} = direction;
4746 let Inst{15-12} = Rt;
4747 let Inst{11-8} = cop;
4748 let Inst{23-21} = opc1;
4749 let Inst{7-5} = opc2;
4750 let Inst{3-0} = CRm;
4751 let Inst{19-16} = CRn;
4754 def MCR : MovRCopro<"mcr", 0 /* from ARM core register to coprocessor */,
4756 (ins p_imm:$cop, imm0_7:$opc1, GPR:$Rt, c_imm:$CRn,
4757 c_imm:$CRm, imm0_7:$opc2),
4758 [(int_arm_mcr imm:$cop, imm:$opc1, GPR:$Rt, imm:$CRn,
4759 imm:$CRm, imm:$opc2)]>,
4760 ComplexDeprecationPredicate<"MCR">;
4761 def : ARMInstAlias<"mcr${p} $cop, $opc1, $Rt, $CRn, $CRm",
4762 (MCR p_imm:$cop, imm0_7:$opc1, GPR:$Rt, c_imm:$CRn,
4763 c_imm:$CRm, 0, pred:$p)>;
4764 def MRC : MovRCopro<"mrc", 1 /* from coprocessor to ARM core register */,
4765 (outs GPRwithAPSR:$Rt),
4766 (ins p_imm:$cop, imm0_7:$opc1, c_imm:$CRn, c_imm:$CRm,
4768 def : ARMInstAlias<"mrc${p} $cop, $opc1, $Rt, $CRn, $CRm",
4769 (MRC GPRwithAPSR:$Rt, p_imm:$cop, imm0_7:$opc1, c_imm:$CRn,
4770 c_imm:$CRm, 0, pred:$p)>;
4772 def : ARMPat<(int_arm_mrc imm:$cop, imm:$opc1, imm:$CRn, imm:$CRm, imm:$opc2),
4773 (MRC imm:$cop, imm:$opc1, imm:$CRn, imm:$CRm, imm:$opc2)>;
4775 class MovRCopro2<string opc, bit direction, dag oops, dag iops,
4777 : ABXI<0b1110, oops, iops, NoItinerary,
4778 !strconcat(opc, "\t$cop, $opc1, $Rt, $CRn, $CRm, $opc2"), pattern> {
4779 let Inst{31-24} = 0b11111110;
4780 let Inst{20} = direction;
4790 let Inst{15-12} = Rt;
4791 let Inst{11-8} = cop;
4792 let Inst{23-21} = opc1;
4793 let Inst{7-5} = opc2;
4794 let Inst{3-0} = CRm;
4795 let Inst{19-16} = CRn;
4798 def MCR2 : MovRCopro2<"mcr2", 0 /* from ARM core register to coprocessor */,
4800 (ins p_imm:$cop, imm0_7:$opc1, GPR:$Rt, c_imm:$CRn,
4801 c_imm:$CRm, imm0_7:$opc2),
4802 [(int_arm_mcr2 imm:$cop, imm:$opc1, GPR:$Rt, imm:$CRn,
4803 imm:$CRm, imm:$opc2)]>,
4805 def : ARMInstAlias<"mcr2$ $cop, $opc1, $Rt, $CRn, $CRm",
4806 (MCR2 p_imm:$cop, imm0_7:$opc1, GPR:$Rt, c_imm:$CRn,
4808 def MRC2 : MovRCopro2<"mrc2", 1 /* from coprocessor to ARM core register */,
4809 (outs GPRwithAPSR:$Rt),
4810 (ins p_imm:$cop, imm0_7:$opc1, c_imm:$CRn, c_imm:$CRm,
4813 def : ARMInstAlias<"mrc2$ $cop, $opc1, $Rt, $CRn, $CRm",
4814 (MRC2 GPRwithAPSR:$Rt, p_imm:$cop, imm0_7:$opc1, c_imm:$CRn,
4817 def : ARMV5TPat<(int_arm_mrc2 imm:$cop, imm:$opc1, imm:$CRn,
4818 imm:$CRm, imm:$opc2),
4819 (MRC2 imm:$cop, imm:$opc1, imm:$CRn, imm:$CRm, imm:$opc2)>;
4821 class MovRRCopro<string opc, bit direction, list<dag> pattern = []>
4822 : ABI<0b1100, (outs), (ins p_imm:$cop, imm0_15:$opc1,
4823 GPRnopc:$Rt, GPRnopc:$Rt2, c_imm:$CRm),
4824 NoItinerary, opc, "\t$cop, $opc1, $Rt, $Rt2, $CRm", pattern> {
4825 let Inst{23-21} = 0b010;
4826 let Inst{20} = direction;
4834 let Inst{15-12} = Rt;
4835 let Inst{19-16} = Rt2;
4836 let Inst{11-8} = cop;
4837 let Inst{7-4} = opc1;
4838 let Inst{3-0} = CRm;
4841 def MCRR : MovRRCopro<"mcrr", 0 /* from ARM core register to coprocessor */,
4842 [(int_arm_mcrr imm:$cop, imm:$opc1, GPRnopc:$Rt,
4843 GPRnopc:$Rt2, imm:$CRm)]>;
4844 def MRRC : MovRRCopro<"mrrc", 1 /* from coprocessor to ARM core register */>;
4846 class MovRRCopro2<string opc, bit direction, list<dag> pattern = []>
4847 : ABXI<0b1100, (outs), (ins p_imm:$cop, imm0_15:$opc1,
4848 GPRnopc:$Rt, GPRnopc:$Rt2, c_imm:$CRm), NoItinerary,
4849 !strconcat(opc, "\t$cop, $opc1, $Rt, $Rt2, $CRm"), pattern>,
4851 let Inst{31-28} = 0b1111;
4852 let Inst{23-21} = 0b010;
4853 let Inst{20} = direction;
4861 let Inst{15-12} = Rt;
4862 let Inst{19-16} = Rt2;
4863 let Inst{11-8} = cop;
4864 let Inst{7-4} = opc1;
4865 let Inst{3-0} = CRm;
4867 let DecoderMethod = "DecodeMRRC2";
4870 def MCRR2 : MovRRCopro2<"mcrr2", 0 /* from ARM core register to coprocessor */,
4871 [(int_arm_mcrr2 imm:$cop, imm:$opc1, GPRnopc:$Rt,
4872 GPRnopc:$Rt2, imm:$CRm)]>;
4873 def MRRC2 : MovRRCopro2<"mrrc2", 1 /* from coprocessor to ARM core register */>;
4875 //===----------------------------------------------------------------------===//
4876 // Move between special register and ARM core register
4879 // Move to ARM core register from Special Register
4880 def MRS : ABI<0b0001, (outs GPRnopc:$Rd), (ins), NoItinerary,
4881 "mrs", "\t$Rd, apsr", []> {
4883 let Inst{23-16} = 0b00001111;
4884 let Unpredictable{19-17} = 0b111;
4886 let Inst{15-12} = Rd;
4888 let Inst{11-0} = 0b000000000000;
4889 let Unpredictable{11-0} = 0b110100001111;
4892 def : InstAlias<"mrs${p} $Rd, cpsr", (MRS GPRnopc:$Rd, pred:$p)>,
4895 // The MRSsys instruction is the MRS instruction from the ARM ARM,
4896 // section B9.3.9, with the R bit set to 1.
4897 def MRSsys : ABI<0b0001, (outs GPRnopc:$Rd), (ins), NoItinerary,
4898 "mrs", "\t$Rd, spsr", []> {
4900 let Inst{23-16} = 0b01001111;
4901 let Unpredictable{19-16} = 0b1111;
4903 let Inst{15-12} = Rd;
4905 let Inst{11-0} = 0b000000000000;
4906 let Unpredictable{11-0} = 0b110100001111;
4909 // Move from ARM core register to Special Register
4911 // No need to have both system and application versions, the encodings are the
4912 // same and the assembly parser has no way to distinguish between them. The mask
4913 // operand contains the special register (R Bit) in bit 4 and bits 3-0 contains
4914 // the mask with the fields to be accessed in the special register.
4915 def MSR : ABI<0b0001, (outs), (ins msr_mask:$mask, GPR:$Rn), NoItinerary,
4916 "msr", "\t$mask, $Rn", []> {
4921 let Inst{22} = mask{4}; // R bit
4922 let Inst{21-20} = 0b10;
4923 let Inst{19-16} = mask{3-0};
4924 let Inst{15-12} = 0b1111;
4925 let Inst{11-4} = 0b00000000;
4929 def MSRi : ABI<0b0011, (outs), (ins msr_mask:$mask, so_imm:$a), NoItinerary,
4930 "msr", "\t$mask, $a", []> {
4935 let Inst{22} = mask{4}; // R bit
4936 let Inst{21-20} = 0b10;
4937 let Inst{19-16} = mask{3-0};
4938 let Inst{15-12} = 0b1111;
4942 //===----------------------------------------------------------------------===//
4946 // __aeabi_read_tp preserves the registers r1-r3.
4947 // This is a pseudo inst so that we can get the encoding right,
4948 // complete with fixup for the aeabi_read_tp function.
4950 Defs = [R0, R12, LR, CPSR], Uses = [SP] in {
4951 def TPsoft : PseudoInst<(outs), (ins), IIC_Br,
4952 [(set R0, ARMthread_pointer)]>, Sched<[WriteBr]>;
4955 //===----------------------------------------------------------------------===//
4956 // SJLJ Exception handling intrinsics
4957 // eh_sjlj_setjmp() is an instruction sequence to store the return
4958 // address and save #0 in R0 for the non-longjmp case.
4959 // Since by its nature we may be coming from some other function to get
4960 // here, and we're using the stack frame for the containing function to
4961 // save/restore registers, we can't keep anything live in regs across
4962 // the eh_sjlj_setjmp(), else it will almost certainly have been tromped upon
4963 // when we get here from a longjmp(). We force everything out of registers
4964 // except for our own input by listing the relevant registers in Defs. By
4965 // doing so, we also cause the prologue/epilogue code to actively preserve
4966 // all of the callee-saved resgisters, which is exactly what we want.
4967 // A constant value is passed in $val, and we use the location as a scratch.
4969 // These are pseudo-instructions and are lowered to individual MC-insts, so
4970 // no encoding information is necessary.
4972 [ R0, R1, R2, R3, R4, R5, R6, R7, R8, R9, R10, R11, R12, LR, CPSR,
4973 Q0, Q1, Q2, Q3, Q4, Q5, Q6, Q7, Q8, Q9, Q10, Q11, Q12, Q13, Q14, Q15 ],
4974 hasSideEffects = 1, isBarrier = 1, usesCustomInserter = 1 in {
4975 def Int_eh_sjlj_setjmp : PseudoInst<(outs), (ins GPR:$src, GPR:$val),
4977 [(set R0, (ARMeh_sjlj_setjmp GPR:$src, GPR:$val))]>,
4978 Requires<[IsARM, HasVFP2]>;
4982 [ R0, R1, R2, R3, R4, R5, R6, R7, R8, R9, R10, R11, R12, LR, CPSR ],
4983 hasSideEffects = 1, isBarrier = 1, usesCustomInserter = 1 in {
4984 def Int_eh_sjlj_setjmp_nofp : PseudoInst<(outs), (ins GPR:$src, GPR:$val),
4986 [(set R0, (ARMeh_sjlj_setjmp GPR:$src, GPR:$val))]>,
4987 Requires<[IsARM, NoVFP]>;
4990 // FIXME: Non-IOS version(s)
4991 let isBarrier = 1, hasSideEffects = 1, isTerminator = 1,
4992 Defs = [ R7, LR, SP ] in {
4993 def Int_eh_sjlj_longjmp : PseudoInst<(outs), (ins GPR:$src, GPR:$scratch),
4995 [(ARMeh_sjlj_longjmp GPR:$src, GPR:$scratch)]>,
4996 Requires<[IsARM, IsIOS]>;
4999 // eh.sjlj.dispatchsetup pseudo-instruction.
5000 // This pseudo is used for both ARM and Thumb. Any differences are handled when
5001 // the pseudo is expanded (which happens before any passes that need the
5002 // instruction size).
5003 let isBarrier = 1 in
5004 def Int_eh_sjlj_dispatchsetup : PseudoInst<(outs), (ins), NoItinerary, []>;
5007 //===----------------------------------------------------------------------===//
5008 // Non-Instruction Patterns
5011 // ARMv4 indirect branch using (MOVr PC, dst)
5012 let isBranch = 1, isTerminator = 1, isBarrier = 1, isIndirectBranch = 1 in
5013 def MOVPCRX : ARMPseudoExpand<(outs), (ins GPR:$dst),
5014 4, IIC_Br, [(brind GPR:$dst)],
5015 (MOVr PC, GPR:$dst, (ops 14, zero_reg), zero_reg)>,
5016 Requires<[IsARM, NoV4T]>, Sched<[WriteBr]>;
5018 // Large immediate handling.
5020 // 32-bit immediate using two piece so_imms or movw + movt.
5021 // This is a single pseudo instruction, the benefit is that it can be remat'd
5022 // as a single unit instead of having to handle reg inputs.
5023 // FIXME: Remove this when we can do generalized remat.
5024 let isReMaterializable = 1, isMoveImm = 1 in
5025 def MOVi32imm : PseudoInst<(outs GPR:$dst), (ins i32imm:$src), IIC_iMOVix2,
5026 [(set GPR:$dst, (arm_i32imm:$src))]>,
5029 def LDRLIT_ga_abs : PseudoInst<(outs GPR:$dst), (ins i32imm:$src), IIC_iLoad_i,
5030 [(set GPR:$dst, (ARMWrapper tglobaladdr:$src))]>,
5031 Requires<[IsARM, DontUseMovt]>;
5033 // Pseudo instruction that combines movw + movt + add pc (if PIC).
5034 // It also makes it possible to rematerialize the instructions.
5035 // FIXME: Remove this when we can do generalized remat and when machine licm
5036 // can properly the instructions.
5037 let isReMaterializable = 1 in {
5038 def MOV_ga_pcrel : PseudoInst<(outs GPR:$dst), (ins i32imm:$addr),
5040 [(set GPR:$dst, (ARMWrapperPIC tglobaladdr:$addr))]>,
5041 Requires<[IsARM, UseMovt]>;
5043 def LDRLIT_ga_pcrel : PseudoInst<(outs GPR:$dst), (ins i32imm:$addr),
5046 (ARMWrapperPIC tglobaladdr:$addr))]>,
5047 Requires<[IsARM, DontUseMovt]>;
5049 def LDRLIT_ga_pcrel_ldr : PseudoInst<(outs GPR:$dst), (ins i32imm:$addr),
5052 (load (ARMWrapperPIC tglobaladdr:$addr)))]>,
5053 Requires<[IsARM, DontUseMovt]>;
5055 let AddedComplexity = 10 in
5056 def MOV_ga_pcrel_ldr : PseudoInst<(outs GPR:$dst), (ins i32imm:$addr),
5058 [(set GPR:$dst, (load (ARMWrapperPIC tglobaladdr:$addr)))]>,
5059 Requires<[IsARM, UseMovt]>;
5060 } // isReMaterializable
5062 // ConstantPool, GlobalAddress, and JumpTable
5063 def : ARMPat<(ARMWrapper tconstpool :$dst), (LEApcrel tconstpool :$dst)>;
5064 def : ARMPat<(ARMWrapper tglobaladdr :$dst), (MOVi32imm tglobaladdr :$dst)>,
5065 Requires<[IsARM, UseMovt]>;
5066 def : ARMPat<(ARMWrapperJT tjumptable:$dst, imm:$id),
5067 (LEApcrelJT tjumptable:$dst, imm:$id)>;
5069 // TODO: add,sub,and, 3-instr forms?
5071 // Tail calls. These patterns also apply to Thumb mode.
5072 def : Pat<(ARMtcret tcGPR:$dst), (TCRETURNri tcGPR:$dst)>;
5073 def : Pat<(ARMtcret (i32 tglobaladdr:$dst)), (TCRETURNdi texternalsym:$dst)>;
5074 def : Pat<(ARMtcret (i32 texternalsym:$dst)), (TCRETURNdi texternalsym:$dst)>;
5077 def : ARMPat<(ARMcall texternalsym:$func), (BL texternalsym:$func)>;
5078 def : ARMPat<(ARMcall_nolink texternalsym:$func),
5079 (BMOVPCB_CALL texternalsym:$func)>;
5081 // zextload i1 -> zextload i8
5082 def : ARMPat<(zextloadi1 addrmode_imm12:$addr), (LDRBi12 addrmode_imm12:$addr)>;
5083 def : ARMPat<(zextloadi1 ldst_so_reg:$addr), (LDRBrs ldst_so_reg:$addr)>;
5085 // extload -> zextload
5086 def : ARMPat<(extloadi1 addrmode_imm12:$addr), (LDRBi12 addrmode_imm12:$addr)>;
5087 def : ARMPat<(extloadi1 ldst_so_reg:$addr), (LDRBrs ldst_so_reg:$addr)>;
5088 def : ARMPat<(extloadi8 addrmode_imm12:$addr), (LDRBi12 addrmode_imm12:$addr)>;
5089 def : ARMPat<(extloadi8 ldst_so_reg:$addr), (LDRBrs ldst_so_reg:$addr)>;
5091 def : ARMPat<(extloadi16 addrmode3:$addr), (LDRH addrmode3:$addr)>;
5093 def : ARMPat<(extloadi8 addrmodepc:$addr), (PICLDRB addrmodepc:$addr)>;
5094 def : ARMPat<(extloadi16 addrmodepc:$addr), (PICLDRH addrmodepc:$addr)>;
5097 def : ARMV5TEPat<(mul (sra (shl GPR:$a, (i32 16)), (i32 16)),
5098 (sra (shl GPR:$b, (i32 16)), (i32 16))),
5099 (SMULBB GPR:$a, GPR:$b)>;
5100 def : ARMV5TEPat<(mul sext_16_node:$a, sext_16_node:$b),
5101 (SMULBB GPR:$a, GPR:$b)>;
5102 def : ARMV5TEPat<(mul (sra (shl GPR:$a, (i32 16)), (i32 16)),
5103 (sra GPR:$b, (i32 16))),
5104 (SMULBT GPR:$a, GPR:$b)>;
5105 def : ARMV5TEPat<(mul sext_16_node:$a, (sra GPR:$b, (i32 16))),
5106 (SMULBT GPR:$a, GPR:$b)>;
5107 def : ARMV5TEPat<(mul (sra GPR:$a, (i32 16)),
5108 (sra (shl GPR:$b, (i32 16)), (i32 16))),
5109 (SMULTB GPR:$a, GPR:$b)>;
5110 def : ARMV5TEPat<(mul (sra GPR:$a, (i32 16)), sext_16_node:$b),
5111 (SMULTB GPR:$a, GPR:$b)>;
5112 def : ARMV5TEPat<(sra (mul GPR:$a, (sra (shl GPR:$b, (i32 16)), (i32 16))),
5114 (SMULWB GPR:$a, GPR:$b)>;
5115 def : ARMV5TEPat<(sra (mul GPR:$a, sext_16_node:$b), (i32 16)),
5116 (SMULWB GPR:$a, GPR:$b)>;
5118 def : ARMV5MOPat<(add GPR:$acc,
5119 (mul (sra (shl GPR:$a, (i32 16)), (i32 16)),
5120 (sra (shl GPR:$b, (i32 16)), (i32 16)))),
5121 (SMLABB GPR:$a, GPR:$b, GPR:$acc)>;
5122 def : ARMV5MOPat<(add GPR:$acc,
5123 (mul sext_16_node:$a, sext_16_node:$b)),
5124 (SMLABB GPR:$a, GPR:$b, GPR:$acc)>;
5125 def : ARMV5MOPat<(add GPR:$acc,
5126 (mul (sra (shl GPR:$a, (i32 16)), (i32 16)),
5127 (sra GPR:$b, (i32 16)))),
5128 (SMLABT GPR:$a, GPR:$b, GPR:$acc)>;
5129 def : ARMV5MOPat<(add GPR:$acc,
5130 (mul sext_16_node:$a, (sra GPR:$b, (i32 16)))),
5131 (SMLABT GPR:$a, GPR:$b, GPR:$acc)>;
5132 def : ARMV5MOPat<(add GPR:$acc,
5133 (mul (sra GPR:$a, (i32 16)),
5134 (sra (shl GPR:$b, (i32 16)), (i32 16)))),
5135 (SMLATB GPR:$a, GPR:$b, GPR:$acc)>;
5136 def : ARMV5MOPat<(add GPR:$acc,
5137 (mul (sra GPR:$a, (i32 16)), sext_16_node:$b)),
5138 (SMLATB GPR:$a, GPR:$b, GPR:$acc)>;
5139 def : ARMV5MOPat<(add GPR:$acc,
5140 (sra (mul GPR:$a, (sra (shl GPR:$b, (i32 16)), (i32 16))),
5142 (SMLAWB GPR:$a, GPR:$b, GPR:$acc)>;
5143 def : ARMV5MOPat<(add GPR:$acc,
5144 (sra (mul GPR:$a, sext_16_node:$b), (i32 16))),
5145 (SMLAWB GPR:$a, GPR:$b, GPR:$acc)>;
5148 // Pre-v7 uses MCR for synchronization barriers.
5149 def : ARMPat<(ARMMemBarrierMCR GPR:$zero), (MCR 15, 0, GPR:$zero, 7, 10, 5)>,
5150 Requires<[IsARM, HasV6]>;
5152 // SXT/UXT with no rotate
5153 let AddedComplexity = 16 in {
5154 def : ARMV6Pat<(and GPR:$Src, 0x000000FF), (UXTB GPR:$Src, 0)>;
5155 def : ARMV6Pat<(and GPR:$Src, 0x0000FFFF), (UXTH GPR:$Src, 0)>;
5156 def : ARMV6Pat<(and GPR:$Src, 0x00FF00FF), (UXTB16 GPR:$Src, 0)>;
5157 def : ARMV6Pat<(add GPR:$Rn, (and GPR:$Rm, 0x00FF)),
5158 (UXTAB GPR:$Rn, GPR:$Rm, 0)>;
5159 def : ARMV6Pat<(add GPR:$Rn, (and GPR:$Rm, 0xFFFF)),
5160 (UXTAH GPR:$Rn, GPR:$Rm, 0)>;
5163 def : ARMV6Pat<(sext_inreg GPR:$Src, i8), (SXTB GPR:$Src, 0)>;
5164 def : ARMV6Pat<(sext_inreg GPR:$Src, i16), (SXTH GPR:$Src, 0)>;
5166 def : ARMV6Pat<(add GPR:$Rn, (sext_inreg GPRnopc:$Rm, i8)),
5167 (SXTAB GPR:$Rn, GPRnopc:$Rm, 0)>;
5168 def : ARMV6Pat<(add GPR:$Rn, (sext_inreg GPRnopc:$Rm, i16)),
5169 (SXTAH GPR:$Rn, GPRnopc:$Rm, 0)>;
5171 // Atomic load/store patterns
5172 def : ARMPat<(atomic_load_8 ldst_so_reg:$src),
5173 (LDRBrs ldst_so_reg:$src)>;
5174 def : ARMPat<(atomic_load_8 addrmode_imm12:$src),
5175 (LDRBi12 addrmode_imm12:$src)>;
5176 def : ARMPat<(atomic_load_16 addrmode3:$src),
5177 (LDRH addrmode3:$src)>;
5178 def : ARMPat<(atomic_load_32 ldst_so_reg:$src),
5179 (LDRrs ldst_so_reg:$src)>;
5180 def : ARMPat<(atomic_load_32 addrmode_imm12:$src),
5181 (LDRi12 addrmode_imm12:$src)>;
5182 def : ARMPat<(atomic_store_8 ldst_so_reg:$ptr, GPR:$val),
5183 (STRBrs GPR:$val, ldst_so_reg:$ptr)>;
5184 def : ARMPat<(atomic_store_8 addrmode_imm12:$ptr, GPR:$val),
5185 (STRBi12 GPR:$val, addrmode_imm12:$ptr)>;
5186 def : ARMPat<(atomic_store_16 addrmode3:$ptr, GPR:$val),
5187 (STRH GPR:$val, addrmode3:$ptr)>;
5188 def : ARMPat<(atomic_store_32 ldst_so_reg:$ptr, GPR:$val),
5189 (STRrs GPR:$val, ldst_so_reg:$ptr)>;
5190 def : ARMPat<(atomic_store_32 addrmode_imm12:$ptr, GPR:$val),
5191 (STRi12 GPR:$val, addrmode_imm12:$ptr)>;
5194 //===----------------------------------------------------------------------===//
5198 include "ARMInstrThumb.td"
5200 //===----------------------------------------------------------------------===//
5204 include "ARMInstrThumb2.td"
5206 //===----------------------------------------------------------------------===//
5207 // Floating Point Support
5210 include "ARMInstrVFP.td"
5212 //===----------------------------------------------------------------------===//
5213 // Advanced SIMD (NEON) Support
5216 include "ARMInstrNEON.td"
5218 //===----------------------------------------------------------------------===//
5219 // Assembler aliases
5223 def : InstAlias<"dmb", (DMB 0xf)>, Requires<[IsARM, HasDB]>;
5224 def : InstAlias<"dsb", (DSB 0xf)>, Requires<[IsARM, HasDB]>;
5225 def : InstAlias<"isb", (ISB 0xf)>, Requires<[IsARM, HasDB]>;
5227 // System instructions
5228 def : MnemonicAlias<"swi", "svc">;
5230 // Load / Store Multiple
5231 def : MnemonicAlias<"ldmfd", "ldm">;
5232 def : MnemonicAlias<"ldmia", "ldm">;
5233 def : MnemonicAlias<"ldmea", "ldmdb">;
5234 def : MnemonicAlias<"stmfd", "stmdb">;
5235 def : MnemonicAlias<"stmia", "stm">;
5236 def : MnemonicAlias<"stmea", "stm">;
5238 // PKHBT/PKHTB with default shift amount. PKHTB is equivalent to PKHBT when the
5239 // shift amount is zero (i.e., unspecified).
5240 def : InstAlias<"pkhbt${p} $Rd, $Rn, $Rm",
5241 (PKHBT GPRnopc:$Rd, GPRnopc:$Rn, GPRnopc:$Rm, 0, pred:$p)>,
5242 Requires<[IsARM, HasV6]>;
5243 def : InstAlias<"pkhtb${p} $Rd, $Rn, $Rm",
5244 (PKHBT GPRnopc:$Rd, GPRnopc:$Rn, GPRnopc:$Rm, 0, pred:$p)>,
5245 Requires<[IsARM, HasV6]>;
5247 // PUSH/POP aliases for STM/LDM
5248 def : ARMInstAlias<"push${p} $regs", (STMDB_UPD SP, pred:$p, reglist:$regs)>;
5249 def : ARMInstAlias<"pop${p} $regs", (LDMIA_UPD SP, pred:$p, reglist:$regs)>;
5251 // SSAT/USAT optional shift operand.
5252 def : ARMInstAlias<"ssat${p} $Rd, $sat_imm, $Rn",
5253 (SSAT GPRnopc:$Rd, imm1_32:$sat_imm, GPRnopc:$Rn, 0, pred:$p)>;
5254 def : ARMInstAlias<"usat${p} $Rd, $sat_imm, $Rn",
5255 (USAT GPRnopc:$Rd, imm0_31:$sat_imm, GPRnopc:$Rn, 0, pred:$p)>;
5258 // Extend instruction optional rotate operand.
5259 def : ARMInstAlias<"sxtab${p} $Rd, $Rn, $Rm",
5260 (SXTAB GPRnopc:$Rd, GPR:$Rn, GPRnopc:$Rm, 0, pred:$p)>;
5261 def : ARMInstAlias<"sxtah${p} $Rd, $Rn, $Rm",
5262 (SXTAH GPRnopc:$Rd, GPR:$Rn, GPRnopc:$Rm, 0, pred:$p)>;
5263 def : ARMInstAlias<"sxtab16${p} $Rd, $Rn, $Rm",
5264 (SXTAB16 GPRnopc:$Rd, GPR:$Rn, GPRnopc:$Rm, 0, pred:$p)>;
5265 def : ARMInstAlias<"sxtb${p} $Rd, $Rm",
5266 (SXTB GPRnopc:$Rd, GPRnopc:$Rm, 0, pred:$p)>;
5267 def : ARMInstAlias<"sxtb16${p} $Rd, $Rm",
5268 (SXTB16 GPRnopc:$Rd, GPRnopc:$Rm, 0, pred:$p)>;
5269 def : ARMInstAlias<"sxth${p} $Rd, $Rm",
5270 (SXTH GPRnopc:$Rd, GPRnopc:$Rm, 0, pred:$p)>;
5272 def : ARMInstAlias<"uxtab${p} $Rd, $Rn, $Rm",
5273 (UXTAB GPRnopc:$Rd, GPR:$Rn, GPRnopc:$Rm, 0, pred:$p)>;
5274 def : ARMInstAlias<"uxtah${p} $Rd, $Rn, $Rm",
5275 (UXTAH GPRnopc:$Rd, GPR:$Rn, GPRnopc:$Rm, 0, pred:$p)>;
5276 def : ARMInstAlias<"uxtab16${p} $Rd, $Rn, $Rm",
5277 (UXTAB16 GPRnopc:$Rd, GPR:$Rn, GPRnopc:$Rm, 0, pred:$p)>;
5278 def : ARMInstAlias<"uxtb${p} $Rd, $Rm",
5279 (UXTB GPRnopc:$Rd, GPRnopc:$Rm, 0, pred:$p)>;
5280 def : ARMInstAlias<"uxtb16${p} $Rd, $Rm",
5281 (UXTB16 GPRnopc:$Rd, GPRnopc:$Rm, 0, pred:$p)>;
5282 def : ARMInstAlias<"uxth${p} $Rd, $Rm",
5283 (UXTH GPRnopc:$Rd, GPRnopc:$Rm, 0, pred:$p)>;
5287 def : MnemonicAlias<"rfefa", "rfeda">;
5288 def : MnemonicAlias<"rfeea", "rfedb">;
5289 def : MnemonicAlias<"rfefd", "rfeia">;
5290 def : MnemonicAlias<"rfeed", "rfeib">;
5291 def : MnemonicAlias<"rfe", "rfeia">;
5294 def : MnemonicAlias<"srsfa", "srsib">;
5295 def : MnemonicAlias<"srsea", "srsia">;
5296 def : MnemonicAlias<"srsfd", "srsdb">;
5297 def : MnemonicAlias<"srsed", "srsda">;
5298 def : MnemonicAlias<"srs", "srsia">;
5301 def : MnemonicAlias<"qsubaddx", "qsax">;
5303 def : MnemonicAlias<"saddsubx", "sasx">;
5304 // SHASX == SHADDSUBX
5305 def : MnemonicAlias<"shaddsubx", "shasx">;
5306 // SHSAX == SHSUBADDX
5307 def : MnemonicAlias<"shsubaddx", "shsax">;
5309 def : MnemonicAlias<"ssubaddx", "ssax">;
5311 def : MnemonicAlias<"uaddsubx", "uasx">;
5312 // UHASX == UHADDSUBX
5313 def : MnemonicAlias<"uhaddsubx", "uhasx">;
5314 // UHSAX == UHSUBADDX
5315 def : MnemonicAlias<"uhsubaddx", "uhsax">;
5316 // UQASX == UQADDSUBX
5317 def : MnemonicAlias<"uqaddsubx", "uqasx">;
5318 // UQSAX == UQSUBADDX
5319 def : MnemonicAlias<"uqsubaddx", "uqsax">;
5321 def : MnemonicAlias<"usubaddx", "usax">;
5323 // "mov Rd, so_imm_not" can be handled via "mvn" in assembly, just like
5325 def : ARMInstAlias<"mov${s}${p} $Rd, $imm",
5326 (MVNi rGPR:$Rd, so_imm_not:$imm, pred:$p, cc_out:$s)>;
5327 def : ARMInstAlias<"mvn${s}${p} $Rd, $imm",
5328 (MOVi rGPR:$Rd, so_imm_not:$imm, pred:$p, cc_out:$s)>;
5329 // Same for AND <--> BIC
5330 def : ARMInstAlias<"bic${s}${p} $Rd, $Rn, $imm",
5331 (ANDri rGPR:$Rd, rGPR:$Rn, so_imm_not:$imm,
5332 pred:$p, cc_out:$s)>;
5333 def : ARMInstAlias<"bic${s}${p} $Rdn, $imm",
5334 (ANDri rGPR:$Rdn, rGPR:$Rdn, so_imm_not:$imm,
5335 pred:$p, cc_out:$s)>;
5336 def : ARMInstAlias<"and${s}${p} $Rd, $Rn, $imm",
5337 (BICri rGPR:$Rd, rGPR:$Rn, so_imm_not:$imm,
5338 pred:$p, cc_out:$s)>;
5339 def : ARMInstAlias<"and${s}${p} $Rdn, $imm",
5340 (BICri rGPR:$Rdn, rGPR:$Rdn, so_imm_not:$imm,
5341 pred:$p, cc_out:$s)>;
5343 // Likewise, "add Rd, so_imm_neg" -> sub
5344 def : ARMInstAlias<"add${s}${p} $Rd, $Rn, $imm",
5345 (SUBri GPR:$Rd, GPR:$Rn, so_imm_neg:$imm, pred:$p, cc_out:$s)>;
5346 def : ARMInstAlias<"add${s}${p} $Rd, $imm",
5347 (SUBri GPR:$Rd, GPR:$Rd, so_imm_neg:$imm, pred:$p, cc_out:$s)>;
5348 // Same for CMP <--> CMN via so_imm_neg
5349 def : ARMInstAlias<"cmp${p} $Rd, $imm",
5350 (CMNri rGPR:$Rd, so_imm_neg:$imm, pred:$p)>;
5351 def : ARMInstAlias<"cmn${p} $Rd, $imm",
5352 (CMPri rGPR:$Rd, so_imm_neg:$imm, pred:$p)>;
5354 // The shifter forms of the MOV instruction are aliased to the ASR, LSL,
5355 // LSR, ROR, and RRX instructions.
5356 // FIXME: We need C++ parser hooks to map the alias to the MOV
5357 // encoding. It seems we should be able to do that sort of thing
5358 // in tblgen, but it could get ugly.
5359 let TwoOperandAliasConstraint = "$Rm = $Rd" in {
5360 def ASRi : ARMAsmPseudo<"asr${s}${p} $Rd, $Rm, $imm",
5361 (ins GPR:$Rd, GPR:$Rm, imm0_32:$imm, pred:$p,
5363 def LSRi : ARMAsmPseudo<"lsr${s}${p} $Rd, $Rm, $imm",
5364 (ins GPR:$Rd, GPR:$Rm, imm0_32:$imm, pred:$p,
5366 def LSLi : ARMAsmPseudo<"lsl${s}${p} $Rd, $Rm, $imm",
5367 (ins GPR:$Rd, GPR:$Rm, imm0_31:$imm, pred:$p,
5369 def RORi : ARMAsmPseudo<"ror${s}${p} $Rd, $Rm, $imm",
5370 (ins GPR:$Rd, GPR:$Rm, imm0_31:$imm, pred:$p,
5373 def RRXi : ARMAsmPseudo<"rrx${s}${p} $Rd, $Rm",
5374 (ins GPR:$Rd, GPR:$Rm, pred:$p, cc_out:$s)>;
5375 let TwoOperandAliasConstraint = "$Rn = $Rd" in {
5376 def ASRr : ARMAsmPseudo<"asr${s}${p} $Rd, $Rn, $Rm",
5377 (ins GPRnopc:$Rd, GPRnopc:$Rn, GPRnopc:$Rm, pred:$p,
5379 def LSRr : ARMAsmPseudo<"lsr${s}${p} $Rd, $Rn, $Rm",
5380 (ins GPRnopc:$Rd, GPRnopc:$Rn, GPRnopc:$Rm, pred:$p,
5382 def LSLr : ARMAsmPseudo<"lsl${s}${p} $Rd, $Rn, $Rm",
5383 (ins GPRnopc:$Rd, GPRnopc:$Rn, GPRnopc:$Rm, pred:$p,
5385 def RORr : ARMAsmPseudo<"ror${s}${p} $Rd, $Rn, $Rm",
5386 (ins GPRnopc:$Rd, GPRnopc:$Rn, GPRnopc:$Rm, pred:$p,
5390 // "neg" is and alias for "rsb rd, rn, #0"
5391 def : ARMInstAlias<"neg${s}${p} $Rd, $Rm",
5392 (RSBri GPR:$Rd, GPR:$Rm, 0, pred:$p, cc_out:$s)>;
5394 // Pre-v6, 'mov r0, r0' was used as a NOP encoding.
5395 def : InstAlias<"nop${p}", (MOVr R0, R0, pred:$p, zero_reg)>,
5396 Requires<[IsARM, NoV6]>;
5398 // MUL/UMLAL/SMLAL/UMULL/SMULL are available on all arches, but
5399 // the instruction definitions need difference constraints pre-v6.
5400 // Use these aliases for the assembly parsing on pre-v6.
5401 def : InstAlias<"mul${s}${p} $Rd, $Rn, $Rm",
5402 (MUL GPRnopc:$Rd, GPRnopc:$Rn, GPRnopc:$Rm, pred:$p, cc_out:$s)>,
5403 Requires<[IsARM, NoV6]>;
5404 def : InstAlias<"mla${s}${p} $Rd, $Rn, $Rm, $Ra",
5405 (MLA GPRnopc:$Rd, GPRnopc:$Rn, GPRnopc:$Rm, GPRnopc:$Ra,
5406 pred:$p, cc_out:$s)>,
5407 Requires<[IsARM, NoV6]>;
5408 def : InstAlias<"smlal${s}${p} $RdLo, $RdHi, $Rn, $Rm",
5409 (SMLAL GPR:$RdLo, GPR:$RdHi, GPR:$Rn, GPR:$Rm, pred:$p, cc_out:$s)>,
5410 Requires<[IsARM, NoV6]>;
5411 def : InstAlias<"umlal${s}${p} $RdLo, $RdHi, $Rn, $Rm",
5412 (UMLAL GPR:$RdLo, GPR:$RdHi, GPR:$Rn, GPR:$Rm, pred:$p, cc_out:$s)>,
5413 Requires<[IsARM, NoV6]>;
5414 def : InstAlias<"smull${s}${p} $RdLo, $RdHi, $Rn, $Rm",
5415 (SMULL GPR:$RdLo, GPR:$RdHi, GPR:$Rn, GPR:$Rm, pred:$p, cc_out:$s)>,
5416 Requires<[IsARM, NoV6]>;
5417 def : InstAlias<"umull${s}${p} $RdLo, $RdHi, $Rn, $Rm",
5418 (UMULL GPR:$RdLo, GPR:$RdHi, GPR:$Rn, GPR:$Rm, pred:$p, cc_out:$s)>,
5419 Requires<[IsARM, NoV6]>;
5421 // 'it' blocks in ARM mode just validate the predicates. The IT itself
5423 def ITasm : ARMAsmPseudo<"it$mask $cc", (ins it_pred:$cc, it_mask:$mask)>,
5424 ComplexDeprecationPredicate<"IT">;