1 //===- ARMInstrInfo.td - Target Description for ARM Target -*- tablegen -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file describes the ARM instructions in TableGen format.
12 //===----------------------------------------------------------------------===//
14 //===----------------------------------------------------------------------===//
15 // ARM specific DAG Nodes.
19 def SDT_ARMCallSeqStart : SDCallSeqStart<[ SDTCisVT<0, i32> ]>;
20 def SDT_ARMCallSeqEnd : SDCallSeqEnd<[ SDTCisVT<0, i32>, SDTCisVT<1, i32> ]>;
22 def SDT_ARMSaveCallPC : SDTypeProfile<0, 1, []>;
24 def SDT_ARMcall : SDTypeProfile<0, -1, [SDTCisPtrTy<0>]>;
26 def SDT_ARMCMov : SDTypeProfile<1, 3,
27 [SDTCisSameAs<0, 1>, SDTCisSameAs<0, 2>,
30 def SDT_ARMBrcond : SDTypeProfile<0, 2,
31 [SDTCisVT<0, OtherVT>, SDTCisVT<1, i32>]>;
33 def SDT_ARMBrJT : SDTypeProfile<0, 3,
34 [SDTCisPtrTy<0>, SDTCisVT<1, i32>,
37 def SDT_ARMBr2JT : SDTypeProfile<0, 4,
38 [SDTCisPtrTy<0>, SDTCisVT<1, i32>,
39 SDTCisVT<2, i32>, SDTCisVT<3, i32>]>;
41 def SDT_ARMBCC_i64 : SDTypeProfile<0, 6,
43 SDTCisVT<1, i32>, SDTCisVT<2, i32>,
44 SDTCisVT<3, i32>, SDTCisVT<4, i32>,
45 SDTCisVT<5, OtherVT>]>;
47 def SDT_ARMAnd : SDTypeProfile<1, 2,
48 [SDTCisVT<0, i32>, SDTCisVT<1, i32>,
51 def SDT_ARMCmp : SDTypeProfile<0, 2, [SDTCisSameAs<0, 1>]>;
53 def SDT_ARMPICAdd : SDTypeProfile<1, 2, [SDTCisSameAs<0, 1>,
54 SDTCisPtrTy<1>, SDTCisVT<2, i32>]>;
56 def SDT_ARMThreadPointer : SDTypeProfile<1, 0, [SDTCisPtrTy<0>]>;
57 def SDT_ARMEH_SJLJ_Setjmp : SDTypeProfile<1, 2, [SDTCisInt<0>, SDTCisPtrTy<1>,
59 def SDT_ARMEH_SJLJ_Longjmp: SDTypeProfile<0, 2, [SDTCisPtrTy<0>, SDTCisInt<1>]>;
61 def SDT_ARMEH_SJLJ_DispatchSetup: SDTypeProfile<0, 1, [SDTCisPtrTy<0>]>;
63 def SDT_ARMMEMBARRIER : SDTypeProfile<0, 1, [SDTCisInt<0>]>;
65 def SDT_ARMTCRET : SDTypeProfile<0, 1, [SDTCisPtrTy<0>]>;
67 def SDT_ARMBFI : SDTypeProfile<1, 3, [SDTCisVT<0, i32>, SDTCisVT<1, i32>,
68 SDTCisVT<2, i32>, SDTCisVT<3, i32>]>;
71 def ARMWrapper : SDNode<"ARMISD::Wrapper", SDTIntUnaryOp>;
72 def ARMWrapperDYN : SDNode<"ARMISD::WrapperDYN", SDTIntUnaryOp>;
73 def ARMWrapperPIC : SDNode<"ARMISD::WrapperPIC", SDTIntUnaryOp>;
74 def ARMWrapperJT : SDNode<"ARMISD::WrapperJT", SDTIntBinOp>;
76 def ARMcallseq_start : SDNode<"ISD::CALLSEQ_START", SDT_ARMCallSeqStart,
77 [SDNPHasChain, SDNPOutGlue]>;
78 def ARMcallseq_end : SDNode<"ISD::CALLSEQ_END", SDT_ARMCallSeqEnd,
79 [SDNPHasChain, SDNPOptInGlue, SDNPOutGlue]>;
81 def ARMcall : SDNode<"ARMISD::CALL", SDT_ARMcall,
82 [SDNPHasChain, SDNPOptInGlue, SDNPOutGlue,
84 def ARMcall_pred : SDNode<"ARMISD::CALL_PRED", SDT_ARMcall,
85 [SDNPHasChain, SDNPOptInGlue, SDNPOutGlue,
87 def ARMcall_nolink : SDNode<"ARMISD::CALL_NOLINK", SDT_ARMcall,
88 [SDNPHasChain, SDNPOptInGlue, SDNPOutGlue,
91 def ARMretflag : SDNode<"ARMISD::RET_FLAG", SDTNone,
92 [SDNPHasChain, SDNPOptInGlue]>;
94 def ARMcmov : SDNode<"ARMISD::CMOV", SDT_ARMCMov,
97 def ARMbrcond : SDNode<"ARMISD::BRCOND", SDT_ARMBrcond,
98 [SDNPHasChain, SDNPInGlue, SDNPOutGlue]>;
100 def ARMbrjt : SDNode<"ARMISD::BR_JT", SDT_ARMBrJT,
102 def ARMbr2jt : SDNode<"ARMISD::BR2_JT", SDT_ARMBr2JT,
105 def ARMBcci64 : SDNode<"ARMISD::BCC_i64", SDT_ARMBCC_i64,
108 def ARMcmp : SDNode<"ARMISD::CMP", SDT_ARMCmp,
111 def ARMcmpZ : SDNode<"ARMISD::CMPZ", SDT_ARMCmp,
112 [SDNPOutGlue, SDNPCommutative]>;
114 def ARMpic_add : SDNode<"ARMISD::PIC_ADD", SDT_ARMPICAdd>;
116 def ARMsrl_flag : SDNode<"ARMISD::SRL_FLAG", SDTIntUnaryOp, [SDNPOutGlue]>;
117 def ARMsra_flag : SDNode<"ARMISD::SRA_FLAG", SDTIntUnaryOp, [SDNPOutGlue]>;
118 def ARMrrx : SDNode<"ARMISD::RRX" , SDTIntUnaryOp, [SDNPInGlue ]>;
120 def ARMthread_pointer: SDNode<"ARMISD::THREAD_POINTER", SDT_ARMThreadPointer>;
121 def ARMeh_sjlj_setjmp: SDNode<"ARMISD::EH_SJLJ_SETJMP",
122 SDT_ARMEH_SJLJ_Setjmp, [SDNPHasChain]>;
123 def ARMeh_sjlj_longjmp: SDNode<"ARMISD::EH_SJLJ_LONGJMP",
124 SDT_ARMEH_SJLJ_Longjmp, [SDNPHasChain]>;
125 def ARMeh_sjlj_dispatchsetup: SDNode<"ARMISD::EH_SJLJ_DISPATCHSETUP",
126 SDT_ARMEH_SJLJ_DispatchSetup, [SDNPHasChain]>;
129 def ARMMemBarrier : SDNode<"ARMISD::MEMBARRIER", SDT_ARMMEMBARRIER,
131 def ARMMemBarrierMCR : SDNode<"ARMISD::MEMBARRIER_MCR", SDT_ARMMEMBARRIER,
133 def ARMPreload : SDNode<"ARMISD::PRELOAD", SDTPrefetch,
134 [SDNPHasChain, SDNPMayLoad, SDNPMayStore]>;
136 def ARMrbit : SDNode<"ARMISD::RBIT", SDTIntUnaryOp>;
138 def ARMtcret : SDNode<"ARMISD::TC_RETURN", SDT_ARMTCRET,
139 [SDNPHasChain, SDNPOptInGlue, SDNPVariadic]>;
142 def ARMbfi : SDNode<"ARMISD::BFI", SDT_ARMBFI>;
144 //===----------------------------------------------------------------------===//
145 // ARM Instruction Predicate Definitions.
147 def HasV4T : Predicate<"Subtarget->hasV4TOps()">, AssemblerPredicate;
148 def NoV4T : Predicate<"!Subtarget->hasV4TOps()">;
149 def HasV5T : Predicate<"Subtarget->hasV5TOps()">;
150 def HasV5TE : Predicate<"Subtarget->hasV5TEOps()">, AssemblerPredicate;
151 def HasV6 : Predicate<"Subtarget->hasV6Ops()">, AssemblerPredicate;
152 def NoV6 : Predicate<"!Subtarget->hasV6Ops()">;
153 def HasV6T2 : Predicate<"Subtarget->hasV6T2Ops()">, AssemblerPredicate;
154 def NoV6T2 : Predicate<"!Subtarget->hasV6T2Ops()">;
155 def HasV7 : Predicate<"Subtarget->hasV7Ops()">, AssemblerPredicate;
156 def NoVFP : Predicate<"!Subtarget->hasVFP2()">;
157 def HasVFP2 : Predicate<"Subtarget->hasVFP2()">, AssemblerPredicate;
158 def HasVFP3 : Predicate<"Subtarget->hasVFP3()">, AssemblerPredicate;
159 def HasNEON : Predicate<"Subtarget->hasNEON()">, AssemblerPredicate;
160 def HasFP16 : Predicate<"Subtarget->hasFP16()">, AssemblerPredicate;
161 def HasDivide : Predicate<"Subtarget->hasDivide()">, AssemblerPredicate;
162 def HasT2ExtractPack : Predicate<"Subtarget->hasT2ExtractPack()">,
164 def HasDB : Predicate<"Subtarget->hasDataBarrier()">,
166 def HasMP : Predicate<"Subtarget->hasMPExtension()">,
168 def UseNEONForFP : Predicate<"Subtarget->useNEONForSinglePrecisionFP()">;
169 def DontUseNEONForFP : Predicate<"!Subtarget->useNEONForSinglePrecisionFP()">;
170 def IsThumb : Predicate<"Subtarget->isThumb()">, AssemblerPredicate;
171 def IsThumb1Only : Predicate<"Subtarget->isThumb1Only()">;
172 def IsThumb2 : Predicate<"Subtarget->isThumb2()">, AssemblerPredicate;
173 def IsARM : Predicate<"!Subtarget->isThumb()">, AssemblerPredicate;
174 def IsDarwin : Predicate<"Subtarget->isTargetDarwin()">;
175 def IsNotDarwin : Predicate<"!Subtarget->isTargetDarwin()">;
177 // FIXME: Eventually this will be just "hasV6T2Ops".
178 def UseMovt : Predicate<"Subtarget->useMovt()">;
179 def DontUseMovt : Predicate<"!Subtarget->useMovt()">;
180 def UseFPVMLx : Predicate<"Subtarget->useFPVMLx()">;
182 //===----------------------------------------------------------------------===//
183 // ARM Flag Definitions.
185 class RegConstraint<string C> {
186 string Constraints = C;
189 //===----------------------------------------------------------------------===//
190 // ARM specific transformation functions and pattern fragments.
193 // so_imm_neg_XFORM - Return a so_imm value packed into the format described for
194 // so_imm_neg def below.
195 def so_imm_neg_XFORM : SDNodeXForm<imm, [{
196 return CurDAG->getTargetConstant(-(int)N->getZExtValue(), MVT::i32);
199 // so_imm_not_XFORM - Return a so_imm value packed into the format described for
200 // so_imm_not def below.
201 def so_imm_not_XFORM : SDNodeXForm<imm, [{
202 return CurDAG->getTargetConstant(~(int)N->getZExtValue(), MVT::i32);
205 /// imm1_15 predicate - True if the 32-bit immediate is in the range [1,15].
206 def imm1_15 : PatLeaf<(i32 imm), [{
207 return (int32_t)N->getZExtValue() >= 1 && (int32_t)N->getZExtValue() < 16;
210 /// imm16_31 predicate - True if the 32-bit immediate is in the range [16,31].
211 def imm16_31 : PatLeaf<(i32 imm), [{
212 return (int32_t)N->getZExtValue() >= 16 && (int32_t)N->getZExtValue() < 32;
217 return ARM_AM::getSOImmVal(-(uint32_t)N->getZExtValue()) != -1;
218 }], so_imm_neg_XFORM>;
222 return ARM_AM::getSOImmVal(~(uint32_t)N->getZExtValue()) != -1;
223 }], so_imm_not_XFORM>;
225 // sext_16_node predicate - True if the SDNode is sign-extended 16 or more bits.
226 def sext_16_node : PatLeaf<(i32 GPR:$a), [{
227 return CurDAG->ComputeNumSignBits(SDValue(N,0)) >= 17;
230 /// Split a 32-bit immediate into two 16 bit parts.
231 def hi16 : SDNodeXForm<imm, [{
232 return CurDAG->getTargetConstant((uint32_t)N->getZExtValue() >> 16, MVT::i32);
235 def lo16AllZero : PatLeaf<(i32 imm), [{
236 // Returns true if all low 16-bits are 0.
237 return (((uint32_t)N->getZExtValue()) & 0xFFFFUL) == 0;
240 /// imm0_65535 predicate - True if the 32-bit immediate is in the range
242 def imm0_65535 : PatLeaf<(i32 imm), [{
243 return (uint32_t)N->getZExtValue() < 65536;
246 class BinOpFrag<dag res> : PatFrag<(ops node:$LHS, node:$RHS), res>;
247 class UnOpFrag <dag res> : PatFrag<(ops node:$Src), res>;
249 /// adde and sube predicates - True based on whether the carry flag output
250 /// will be needed or not.
251 def adde_dead_carry :
252 PatFrag<(ops node:$LHS, node:$RHS), (adde node:$LHS, node:$RHS),
253 [{return !N->hasAnyUseOfValue(1);}]>;
254 def sube_dead_carry :
255 PatFrag<(ops node:$LHS, node:$RHS), (sube node:$LHS, node:$RHS),
256 [{return !N->hasAnyUseOfValue(1);}]>;
257 def adde_live_carry :
258 PatFrag<(ops node:$LHS, node:$RHS), (adde node:$LHS, node:$RHS),
259 [{return N->hasAnyUseOfValue(1);}]>;
260 def sube_live_carry :
261 PatFrag<(ops node:$LHS, node:$RHS), (sube node:$LHS, node:$RHS),
262 [{return N->hasAnyUseOfValue(1);}]>;
264 // An 'and' node with a single use.
265 def and_su : PatFrag<(ops node:$lhs, node:$rhs), (and node:$lhs, node:$rhs), [{
266 return N->hasOneUse();
269 // An 'xor' node with a single use.
270 def xor_su : PatFrag<(ops node:$lhs, node:$rhs), (xor node:$lhs, node:$rhs), [{
271 return N->hasOneUse();
274 // An 'fmul' node with a single use.
275 def fmul_su : PatFrag<(ops node:$lhs, node:$rhs), (fmul node:$lhs, node:$rhs),[{
276 return N->hasOneUse();
279 // An 'fadd' node which checks for single non-hazardous use.
280 def fadd_mlx : PatFrag<(ops node:$lhs, node:$rhs),(fadd node:$lhs, node:$rhs),[{
281 return hasNoVMLxHazardUse(N);
284 // An 'fsub' node which checks for single non-hazardous use.
285 def fsub_mlx : PatFrag<(ops node:$lhs, node:$rhs),(fsub node:$lhs, node:$rhs),[{
286 return hasNoVMLxHazardUse(N);
289 //===----------------------------------------------------------------------===//
290 // Operand Definitions.
294 // FIXME: rename brtarget to t2_brtarget
295 def brtarget : Operand<OtherVT> {
296 let EncoderMethod = "getBranchTargetOpValue";
299 // FIXME: get rid of this one?
300 def uncondbrtarget : Operand<OtherVT> {
301 let EncoderMethod = "getUnconditionalBranchTargetOpValue";
304 // Branch target for ARM. Handles conditional/unconditional
305 def br_target : Operand<OtherVT> {
306 let EncoderMethod = "getARMBranchTargetOpValue";
310 // FIXME: rename bltarget to t2_bl_target?
311 def bltarget : Operand<i32> {
312 // Encoded the same as branch targets.
313 let EncoderMethod = "getBranchTargetOpValue";
316 // Call target for ARM. Handles conditional/unconditional
317 // FIXME: rename bl_target to t2_bltarget?
318 def bl_target : Operand<i32> {
319 // Encoded the same as branch targets.
320 let EncoderMethod = "getARMBranchTargetOpValue";
324 // A list of registers separated by comma. Used by load/store multiple.
325 def RegListAsmOperand : AsmOperandClass {
326 let Name = "RegList";
327 let SuperClasses = [];
330 def DPRRegListAsmOperand : AsmOperandClass {
331 let Name = "DPRRegList";
332 let SuperClasses = [];
335 def SPRRegListAsmOperand : AsmOperandClass {
336 let Name = "SPRRegList";
337 let SuperClasses = [];
340 def reglist : Operand<i32> {
341 let EncoderMethod = "getRegisterListOpValue";
342 let ParserMatchClass = RegListAsmOperand;
343 let PrintMethod = "printRegisterList";
346 def dpr_reglist : Operand<i32> {
347 let EncoderMethod = "getRegisterListOpValue";
348 let ParserMatchClass = DPRRegListAsmOperand;
349 let PrintMethod = "printRegisterList";
352 def spr_reglist : Operand<i32> {
353 let EncoderMethod = "getRegisterListOpValue";
354 let ParserMatchClass = SPRRegListAsmOperand;
355 let PrintMethod = "printRegisterList";
358 // An operand for the CONSTPOOL_ENTRY pseudo-instruction.
359 def cpinst_operand : Operand<i32> {
360 let PrintMethod = "printCPInstOperand";
364 def pclabel : Operand<i32> {
365 let PrintMethod = "printPCLabel";
368 // ADR instruction labels.
369 def adrlabel : Operand<i32> {
370 let EncoderMethod = "getAdrLabelOpValue";
373 def neon_vcvt_imm32 : Operand<i32> {
374 let EncoderMethod = "getNEONVcvtImm32OpValue";
377 // rot_imm: An integer that encodes a rotate amount. Must be 8, 16, or 24.
378 def rot_imm : Operand<i32>, PatLeaf<(i32 imm), [{
379 int32_t v = (int32_t)N->getZExtValue();
380 return v == 8 || v == 16 || v == 24; }]> {
381 let EncoderMethod = "getRotImmOpValue";
384 def ShifterAsmOperand : AsmOperandClass {
385 let Name = "Shifter";
386 let SuperClasses = [];
389 // shift_imm: An integer that encodes a shift amount and the type of shift
390 // (currently either asr or lsl) using the same encoding used for the
391 // immediates in so_reg operands.
392 def shift_imm : Operand<i32> {
393 let PrintMethod = "printShiftImmOperand";
394 let ParserMatchClass = ShifterAsmOperand;
397 // shifter_operand operands: so_reg and so_imm.
398 def so_reg : Operand<i32>, // reg reg imm
399 ComplexPattern<i32, 3, "SelectShifterOperandReg",
400 [shl,srl,sra,rotr]> {
401 let EncoderMethod = "getSORegOpValue";
402 let PrintMethod = "printSORegOperand";
403 let MIOperandInfo = (ops GPR, GPR, shift_imm);
405 def shift_so_reg : Operand<i32>, // reg reg imm
406 ComplexPattern<i32, 3, "SelectShiftShifterOperandReg",
407 [shl,srl,sra,rotr]> {
408 let EncoderMethod = "getSORegOpValue";
409 let PrintMethod = "printSORegOperand";
410 let MIOperandInfo = (ops GPR, GPR, shift_imm);
413 // so_imm - Match a 32-bit shifter_operand immediate operand, which is an
414 // 8-bit immediate rotated by an arbitrary number of bits.
415 def so_imm : Operand<i32>, PatLeaf<(imm), [{ return Pred_so_imm(N); }]> {
416 let EncoderMethod = "getSOImmOpValue";
417 let PrintMethod = "printSOImmOperand";
420 // Break so_imm's up into two pieces. This handles immediates with up to 16
421 // bits set in them. This uses so_imm2part to match and so_imm2part_[12] to
422 // get the first/second pieces.
423 def so_imm2part : PatLeaf<(imm), [{
424 return ARM_AM::isSOImmTwoPartVal((unsigned)N->getZExtValue());
427 /// arm_i32imm - True for +V6T2, or true only if so_imm2part is true.
429 def arm_i32imm : PatLeaf<(imm), [{
430 if (Subtarget->hasV6T2Ops())
432 return ARM_AM::isSOImmTwoPartVal((unsigned)N->getZExtValue());
435 /// imm0_31 predicate - True if the 32-bit immediate is in the range [0,31].
436 def imm0_31 : Operand<i32>, PatLeaf<(imm), [{
437 return (int32_t)N->getZExtValue() < 32;
440 /// imm0_31_m1 - Matches and prints like imm0_31, but encodes as 'value - 1'.
441 def imm0_31_m1 : Operand<i32>, PatLeaf<(imm), [{
442 return (int32_t)N->getZExtValue() < 32;
444 let EncoderMethod = "getImmMinusOneOpValue";
447 // i32imm_hilo16 - For movt/movw - sets the MC Encoder method.
448 // The imm is split into imm{15-12}, imm{11-0}
450 def i32imm_hilo16 : Operand<i32> {
451 let EncoderMethod = "getHiLo16ImmOpValue";
454 /// bf_inv_mask_imm predicate - An AND mask to clear an arbitrary width bitfield
456 def bf_inv_mask_imm : Operand<i32>,
458 return ARM::isBitFieldInvertedMask(N->getZExtValue());
460 let EncoderMethod = "getBitfieldInvertedMaskOpValue";
461 let PrintMethod = "printBitfieldInvMaskImmOperand";
464 /// lsb_pos_imm - position of the lsb bit, used by BFI4p and t2BFI4p
465 def lsb_pos_imm : Operand<i32>, PatLeaf<(imm), [{
466 return isInt<5>(N->getSExtValue());
469 /// width_imm - number of bits to be copied, used by BFI4p and t2BFI4p
470 def width_imm : Operand<i32>, PatLeaf<(imm), [{
471 return N->getSExtValue() > 0 && N->getSExtValue() <= 32;
473 let EncoderMethod = "getMsbOpValue";
476 // Define ARM specific addressing modes.
478 def MemMode2AsmOperand : AsmOperandClass {
479 let Name = "MemMode2";
480 let SuperClasses = [];
481 let ParserMethod = "tryParseMemMode2Operand";
484 def MemMode3AsmOperand : AsmOperandClass {
485 let Name = "MemMode3";
486 let SuperClasses = [];
487 let ParserMethod = "tryParseMemMode3Operand";
490 // addrmode_imm12 := reg +/- imm12
492 def addrmode_imm12 : Operand<i32>,
493 ComplexPattern<i32, 2, "SelectAddrModeImm12", []> {
494 // 12-bit immediate operand. Note that instructions using this encode
495 // #0 and #-0 differently. We flag #-0 as the magic value INT32_MIN. All other
496 // immediate values are as normal.
498 let EncoderMethod = "getAddrModeImm12OpValue";
499 let PrintMethod = "printAddrModeImm12Operand";
500 let MIOperandInfo = (ops GPR:$base, i32imm:$offsimm);
502 // ldst_so_reg := reg +/- reg shop imm
504 def ldst_so_reg : Operand<i32>,
505 ComplexPattern<i32, 3, "SelectLdStSOReg", []> {
506 let EncoderMethod = "getLdStSORegOpValue";
507 // FIXME: Simplify the printer
508 let PrintMethod = "printAddrMode2Operand";
509 let MIOperandInfo = (ops GPR:$base, GPR:$offsreg, i32imm:$offsimm);
512 // addrmode2 := reg +/- imm12
513 // := reg +/- reg shop imm
515 def addrmode2 : Operand<i32>,
516 ComplexPattern<i32, 3, "SelectAddrMode2", []> {
517 let EncoderMethod = "getAddrMode2OpValue";
518 let PrintMethod = "printAddrMode2Operand";
519 let ParserMatchClass = MemMode2AsmOperand;
520 let MIOperandInfo = (ops GPR:$base, GPR:$offsreg, i32imm:$offsimm);
523 def am2offset : Operand<i32>,
524 ComplexPattern<i32, 2, "SelectAddrMode2Offset",
525 [], [SDNPWantRoot]> {
526 let EncoderMethod = "getAddrMode2OffsetOpValue";
527 let PrintMethod = "printAddrMode2OffsetOperand";
528 let MIOperandInfo = (ops GPR, i32imm);
531 // addrmode3 := reg +/- reg
532 // addrmode3 := reg +/- imm8
534 def addrmode3 : Operand<i32>,
535 ComplexPattern<i32, 3, "SelectAddrMode3", []> {
536 let EncoderMethod = "getAddrMode3OpValue";
537 let PrintMethod = "printAddrMode3Operand";
538 let ParserMatchClass = MemMode3AsmOperand;
539 let MIOperandInfo = (ops GPR:$base, GPR:$offsreg, i32imm:$offsimm);
542 def am3offset : Operand<i32>,
543 ComplexPattern<i32, 2, "SelectAddrMode3Offset",
544 [], [SDNPWantRoot]> {
545 let EncoderMethod = "getAddrMode3OffsetOpValue";
546 let PrintMethod = "printAddrMode3OffsetOperand";
547 let MIOperandInfo = (ops GPR, i32imm);
550 // ldstm_mode := {ia, ib, da, db}
552 def ldstm_mode : OptionalDefOperand<OtherVT, (ops i32), (ops (i32 1))> {
553 let EncoderMethod = "getLdStmModeOpValue";
554 let PrintMethod = "printLdStmModeOperand";
557 def MemMode5AsmOperand : AsmOperandClass {
558 let Name = "MemMode5";
559 let SuperClasses = [];
562 // addrmode5 := reg +/- imm8*4
564 def addrmode5 : Operand<i32>,
565 ComplexPattern<i32, 2, "SelectAddrMode5", []> {
566 let PrintMethod = "printAddrMode5Operand";
567 let MIOperandInfo = (ops GPR:$base, i32imm);
568 let ParserMatchClass = MemMode5AsmOperand;
569 let EncoderMethod = "getAddrMode5OpValue";
572 // addrmode6 := reg with optional alignment
574 def addrmode6 : Operand<i32>,
575 ComplexPattern<i32, 2, "SelectAddrMode6", [], [SDNPWantParent]>{
576 let PrintMethod = "printAddrMode6Operand";
577 let MIOperandInfo = (ops GPR:$addr, i32imm);
578 let EncoderMethod = "getAddrMode6AddressOpValue";
581 def am6offset : Operand<i32>,
582 ComplexPattern<i32, 1, "SelectAddrMode6Offset",
583 [], [SDNPWantRoot]> {
584 let PrintMethod = "printAddrMode6OffsetOperand";
585 let MIOperandInfo = (ops GPR);
586 let EncoderMethod = "getAddrMode6OffsetOpValue";
589 // Special version of addrmode6 to handle alignment encoding for VLD-dup
590 // instructions, specifically VLD4-dup.
591 def addrmode6dup : Operand<i32>,
592 ComplexPattern<i32, 2, "SelectAddrMode6", [], [SDNPWantParent]>{
593 let PrintMethod = "printAddrMode6Operand";
594 let MIOperandInfo = (ops GPR:$addr, i32imm);
595 let EncoderMethod = "getAddrMode6DupAddressOpValue";
598 // addrmodepc := pc + reg
600 def addrmodepc : Operand<i32>,
601 ComplexPattern<i32, 2, "SelectAddrModePC", []> {
602 let PrintMethod = "printAddrModePCOperand";
603 let MIOperandInfo = (ops GPR, i32imm);
606 def MemMode7AsmOperand : AsmOperandClass {
607 let Name = "MemMode7";
608 let SuperClasses = [];
612 // Used by load/store exclusive instructions. Useful to enable right assembly
613 // parsing and printing. Not used for any codegen matching.
615 def addrmode7 : Operand<i32> {
616 let PrintMethod = "printAddrMode7Operand";
617 let MIOperandInfo = (ops GPR);
618 let ParserMatchClass = MemMode7AsmOperand;
621 def nohash_imm : Operand<i32> {
622 let PrintMethod = "printNoHashImmediate";
625 def CoprocNumAsmOperand : AsmOperandClass {
626 let Name = "CoprocNum";
627 let SuperClasses = [];
628 let ParserMethod = "tryParseCoprocNumOperand";
631 def CoprocRegAsmOperand : AsmOperandClass {
632 let Name = "CoprocReg";
633 let SuperClasses = [];
634 let ParserMethod = "tryParseCoprocRegOperand";
637 def p_imm : Operand<i32> {
638 let PrintMethod = "printPImmediate";
639 let ParserMatchClass = CoprocNumAsmOperand;
642 def c_imm : Operand<i32> {
643 let PrintMethod = "printCImmediate";
644 let ParserMatchClass = CoprocRegAsmOperand;
647 //===----------------------------------------------------------------------===//
649 include "ARMInstrFormats.td"
651 //===----------------------------------------------------------------------===//
652 // Multiclass helpers...
655 /// AsI1_bin_irs - Defines a set of (op r, {so_imm|r|so_reg}) patterns for a
656 /// binop that produces a value.
657 multiclass AsI1_bin_irs<bits<4> opcod, string opc,
658 InstrItinClass iii, InstrItinClass iir, InstrItinClass iis,
659 PatFrag opnode, bit Commutable = 0> {
660 // The register-immediate version is re-materializable. This is useful
661 // in particular for taking the address of a local.
662 let isReMaterializable = 1 in {
663 def ri : AsI1<opcod, (outs GPR:$Rd), (ins GPR:$Rn, so_imm:$imm), DPFrm,
664 iii, opc, "\t$Rd, $Rn, $imm",
665 [(set GPR:$Rd, (opnode GPR:$Rn, so_imm:$imm))]> {
670 let Inst{19-16} = Rn;
671 let Inst{15-12} = Rd;
672 let Inst{11-0} = imm;
675 def rr : AsI1<opcod, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm), DPFrm,
676 iir, opc, "\t$Rd, $Rn, $Rm",
677 [(set GPR:$Rd, (opnode GPR:$Rn, GPR:$Rm))]> {
682 let isCommutable = Commutable;
683 let Inst{19-16} = Rn;
684 let Inst{15-12} = Rd;
685 let Inst{11-4} = 0b00000000;
688 def rs : AsI1<opcod, (outs GPR:$Rd), (ins GPR:$Rn, so_reg:$shift), DPSoRegFrm,
689 iis, opc, "\t$Rd, $Rn, $shift",
690 [(set GPR:$Rd, (opnode GPR:$Rn, so_reg:$shift))]> {
695 let Inst{19-16} = Rn;
696 let Inst{15-12} = Rd;
697 let Inst{11-0} = shift;
701 /// AI1_bin_s_irs - Similar to AsI1_bin_irs except it sets the 's' bit so the
702 /// instruction modifies the CPSR register.
703 let isCodeGenOnly = 1, Defs = [CPSR] in {
704 multiclass AI1_bin_s_irs<bits<4> opcod, string opc,
705 InstrItinClass iii, InstrItinClass iir, InstrItinClass iis,
706 PatFrag opnode, bit Commutable = 0> {
707 def ri : AI1<opcod, (outs GPR:$Rd), (ins GPR:$Rn, so_imm:$imm), DPFrm,
708 iii, opc, "\t$Rd, $Rn, $imm",
709 [(set GPR:$Rd, (opnode GPR:$Rn, so_imm:$imm))]> {
715 let Inst{19-16} = Rn;
716 let Inst{15-12} = Rd;
717 let Inst{11-0} = imm;
719 def rr : AI1<opcod, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm), DPFrm,
720 iir, opc, "\t$Rd, $Rn, $Rm",
721 [(set GPR:$Rd, (opnode GPR:$Rn, GPR:$Rm))]> {
725 let isCommutable = Commutable;
728 let Inst{19-16} = Rn;
729 let Inst{15-12} = Rd;
730 let Inst{11-4} = 0b00000000;
733 def rs : AI1<opcod, (outs GPR:$Rd), (ins GPR:$Rn, so_reg:$shift), DPSoRegFrm,
734 iis, opc, "\t$Rd, $Rn, $shift",
735 [(set GPR:$Rd, (opnode GPR:$Rn, so_reg:$shift))]> {
741 let Inst{19-16} = Rn;
742 let Inst{15-12} = Rd;
743 let Inst{11-0} = shift;
748 /// AI1_cmp_irs - Defines a set of (op r, {so_imm|r|so_reg}) cmp / test
749 /// patterns. Similar to AsI1_bin_irs except the instruction does not produce
750 /// a explicit result, only implicitly set CPSR.
751 let isCompare = 1, Defs = [CPSR] in {
752 multiclass AI1_cmp_irs<bits<4> opcod, string opc,
753 InstrItinClass iii, InstrItinClass iir, InstrItinClass iis,
754 PatFrag opnode, bit Commutable = 0> {
755 def ri : AI1<opcod, (outs), (ins GPR:$Rn, so_imm:$imm), DPFrm, iii,
757 [(opnode GPR:$Rn, so_imm:$imm)]> {
762 let Inst{19-16} = Rn;
763 let Inst{15-12} = 0b0000;
764 let Inst{11-0} = imm;
766 def rr : AI1<opcod, (outs), (ins GPR:$Rn, GPR:$Rm), DPFrm, iir,
768 [(opnode GPR:$Rn, GPR:$Rm)]> {
771 let isCommutable = Commutable;
774 let Inst{19-16} = Rn;
775 let Inst{15-12} = 0b0000;
776 let Inst{11-4} = 0b00000000;
779 def rs : AI1<opcod, (outs), (ins GPR:$Rn, so_reg:$shift), DPSoRegFrm, iis,
780 opc, "\t$Rn, $shift",
781 [(opnode GPR:$Rn, so_reg:$shift)]> {
786 let Inst{19-16} = Rn;
787 let Inst{15-12} = 0b0000;
788 let Inst{11-0} = shift;
793 /// AI_ext_rrot - A unary operation with two forms: one whose operand is a
794 /// register and one whose operand is a register rotated by 8/16/24.
795 /// FIXME: Remove the 'r' variant. Its rot_imm is zero.
796 multiclass AI_ext_rrot<bits<8> opcod, string opc, PatFrag opnode> {
797 def r : AExtI<opcod, (outs GPR:$Rd), (ins GPR:$Rm),
798 IIC_iEXTr, opc, "\t$Rd, $Rm",
799 [(set GPR:$Rd, (opnode GPR:$Rm))]>,
800 Requires<[IsARM, HasV6]> {
803 let Inst{19-16} = 0b1111;
804 let Inst{15-12} = Rd;
805 let Inst{11-10} = 0b00;
808 def r_rot : AExtI<opcod, (outs GPR:$Rd), (ins GPR:$Rm, rot_imm:$rot),
809 IIC_iEXTr, opc, "\t$Rd, $Rm, ror $rot",
810 [(set GPR:$Rd, (opnode (rotr GPR:$Rm, rot_imm:$rot)))]>,
811 Requires<[IsARM, HasV6]> {
815 let Inst{19-16} = 0b1111;
816 let Inst{15-12} = Rd;
817 let Inst{11-10} = rot;
822 multiclass AI_ext_rrot_np<bits<8> opcod, string opc> {
823 def r : AExtI<opcod, (outs GPR:$Rd), (ins GPR:$Rm),
824 IIC_iEXTr, opc, "\t$Rd, $Rm",
825 [/* For disassembly only; pattern left blank */]>,
826 Requires<[IsARM, HasV6]> {
827 let Inst{19-16} = 0b1111;
828 let Inst{11-10} = 0b00;
830 def r_rot : AExtI<opcod, (outs GPR:$Rd), (ins GPR:$Rm, rot_imm:$rot),
831 IIC_iEXTr, opc, "\t$Rd, $Rm, ror $rot",
832 [/* For disassembly only; pattern left blank */]>,
833 Requires<[IsARM, HasV6]> {
835 let Inst{19-16} = 0b1111;
836 let Inst{11-10} = rot;
840 /// AI_exta_rrot - A binary operation with two forms: one whose operand is a
841 /// register and one whose operand is a register rotated by 8/16/24.
842 multiclass AI_exta_rrot<bits<8> opcod, string opc, PatFrag opnode> {
843 def rr : AExtI<opcod, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm),
844 IIC_iEXTAr, opc, "\t$Rd, $Rn, $Rm",
845 [(set GPR:$Rd, (opnode GPR:$Rn, GPR:$Rm))]>,
846 Requires<[IsARM, HasV6]> {
850 let Inst{19-16} = Rn;
851 let Inst{15-12} = Rd;
852 let Inst{11-10} = 0b00;
853 let Inst{9-4} = 0b000111;
856 def rr_rot : AExtI<opcod, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm,
858 IIC_iEXTAr, opc, "\t$Rd, $Rn, $Rm, ror $rot",
859 [(set GPR:$Rd, (opnode GPR:$Rn,
860 (rotr GPR:$Rm, rot_imm:$rot)))]>,
861 Requires<[IsARM, HasV6]> {
866 let Inst{19-16} = Rn;
867 let Inst{15-12} = Rd;
868 let Inst{11-10} = rot;
869 let Inst{9-4} = 0b000111;
874 // For disassembly only.
875 multiclass AI_exta_rrot_np<bits<8> opcod, string opc> {
876 def rr : AExtI<opcod, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm),
877 IIC_iEXTAr, opc, "\t$Rd, $Rn, $Rm",
878 [/* For disassembly only; pattern left blank */]>,
879 Requires<[IsARM, HasV6]> {
880 let Inst{11-10} = 0b00;
882 def rr_rot : AExtI<opcod, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm,
884 IIC_iEXTAr, opc, "\t$Rd, $Rn, $Rm, ror $rot",
885 [/* For disassembly only; pattern left blank */]>,
886 Requires<[IsARM, HasV6]> {
889 let Inst{19-16} = Rn;
890 let Inst{11-10} = rot;
894 /// AI1_adde_sube_irs - Define instructions and patterns for adde and sube.
895 let Uses = [CPSR] in {
896 multiclass AI1_adde_sube_irs<bits<4> opcod, string opc, PatFrag opnode,
897 bit Commutable = 0> {
898 def ri : AsI1<opcod, (outs GPR:$Rd), (ins GPR:$Rn, so_imm:$imm),
899 DPFrm, IIC_iALUi, opc, "\t$Rd, $Rn, $imm",
900 [(set GPR:$Rd, (opnode GPR:$Rn, so_imm:$imm))]>,
906 let Inst{15-12} = Rd;
907 let Inst{19-16} = Rn;
908 let Inst{11-0} = imm;
910 def rr : AsI1<opcod, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm),
911 DPFrm, IIC_iALUr, opc, "\t$Rd, $Rn, $Rm",
912 [(set GPR:$Rd, (opnode GPR:$Rn, GPR:$Rm))]>,
917 let Inst{11-4} = 0b00000000;
919 let isCommutable = Commutable;
921 let Inst{15-12} = Rd;
922 let Inst{19-16} = Rn;
924 def rs : AsI1<opcod, (outs GPR:$Rd), (ins GPR:$Rn, so_reg:$shift),
925 DPSoRegFrm, IIC_iALUsr, opc, "\t$Rd, $Rn, $shift",
926 [(set GPR:$Rd, (opnode GPR:$Rn, so_reg:$shift))]>,
932 let Inst{11-0} = shift;
933 let Inst{15-12} = Rd;
934 let Inst{19-16} = Rn;
937 // Carry setting variants
938 let isCodeGenOnly = 1, Defs = [CPSR] in {
939 multiclass AI1_adde_sube_s_irs<bits<4> opcod, string opc, PatFrag opnode,
940 bit Commutable = 0> {
941 def Sri : AXI1<opcod, (outs GPR:$Rd), (ins GPR:$Rn, so_imm:$imm),
942 DPFrm, IIC_iALUi, !strconcat(opc, "\t$Rd, $Rn, $imm"),
943 [(set GPR:$Rd, (opnode GPR:$Rn, so_imm:$imm))]>,
948 let Inst{31-27} = 0b1110; // non-predicated
949 let Inst{15-12} = Rd;
950 let Inst{19-16} = Rn;
951 let Inst{11-0} = imm;
955 def Srr : AXI1<opcod, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm),
956 DPFrm, IIC_iALUr, !strconcat(opc, "\t$Rd, $Rn, $Rm"),
957 [(set GPR:$Rd, (opnode GPR:$Rn, GPR:$Rm))]>,
962 let Inst{31-27} = 0b1110; // non-predicated
963 let Inst{11-4} = 0b00000000;
964 let isCommutable = Commutable;
966 let Inst{15-12} = Rd;
967 let Inst{19-16} = Rn;
971 def Srs : AXI1<opcod, (outs GPR:$Rd), (ins GPR:$Rn, so_reg:$shift),
972 DPSoRegFrm, IIC_iALUsr, !strconcat(opc, "\t$Rd, $Rn, $shift"),
973 [(set GPR:$Rd, (opnode GPR:$Rn, so_reg:$shift))]>,
978 let Inst{31-27} = 0b1110; // non-predicated
979 let Inst{11-0} = shift;
980 let Inst{15-12} = Rd;
981 let Inst{19-16} = Rn;
989 let canFoldAsLoad = 1, isReMaterializable = 1 in {
990 multiclass AI_ldr1<bit isByte, string opc, InstrItinClass iii,
991 InstrItinClass iir, PatFrag opnode> {
992 // Note: We use the complex addrmode_imm12 rather than just an input
993 // GPR and a constrained immediate so that we can use this to match
994 // frame index references and avoid matching constant pool references.
995 def i12: AI2ldst<0b010, 1, isByte, (outs GPR:$Rt), (ins addrmode_imm12:$addr),
996 AddrMode_i12, LdFrm, iii, opc, "\t$Rt, $addr",
997 [(set GPR:$Rt, (opnode addrmode_imm12:$addr))]> {
1000 let Inst{23} = addr{12}; // U (add = ('U' == 1))
1001 let Inst{19-16} = addr{16-13}; // Rn
1002 let Inst{15-12} = Rt;
1003 let Inst{11-0} = addr{11-0}; // imm12
1005 def rs : AI2ldst<0b011, 1, isByte, (outs GPR:$Rt), (ins ldst_so_reg:$shift),
1006 AddrModeNone, LdFrm, iir, opc, "\t$Rt, $shift",
1007 [(set GPR:$Rt, (opnode ldst_so_reg:$shift))]> {
1010 let shift{4} = 0; // Inst{4} = 0
1011 let Inst{23} = shift{12}; // U (add = ('U' == 1))
1012 let Inst{19-16} = shift{16-13}; // Rn
1013 let Inst{15-12} = Rt;
1014 let Inst{11-0} = shift{11-0};
1019 multiclass AI_str1<bit isByte, string opc, InstrItinClass iii,
1020 InstrItinClass iir, PatFrag opnode> {
1021 // Note: We use the complex addrmode_imm12 rather than just an input
1022 // GPR and a constrained immediate so that we can use this to match
1023 // frame index references and avoid matching constant pool references.
1024 def i12 : AI2ldst<0b010, 0, isByte, (outs),
1025 (ins GPR:$Rt, addrmode_imm12:$addr),
1026 AddrMode_i12, StFrm, iii, opc, "\t$Rt, $addr",
1027 [(opnode GPR:$Rt, addrmode_imm12:$addr)]> {
1030 let Inst{23} = addr{12}; // U (add = ('U' == 1))
1031 let Inst{19-16} = addr{16-13}; // Rn
1032 let Inst{15-12} = Rt;
1033 let Inst{11-0} = addr{11-0}; // imm12
1035 def rs : AI2ldst<0b011, 0, isByte, (outs), (ins GPR:$Rt, ldst_so_reg:$shift),
1036 AddrModeNone, StFrm, iir, opc, "\t$Rt, $shift",
1037 [(opnode GPR:$Rt, ldst_so_reg:$shift)]> {
1040 let shift{4} = 0; // Inst{4} = 0
1041 let Inst{23} = shift{12}; // U (add = ('U' == 1))
1042 let Inst{19-16} = shift{16-13}; // Rn
1043 let Inst{15-12} = Rt;
1044 let Inst{11-0} = shift{11-0};
1047 //===----------------------------------------------------------------------===//
1049 //===----------------------------------------------------------------------===//
1051 //===----------------------------------------------------------------------===//
1052 // Miscellaneous Instructions.
1055 /// CONSTPOOL_ENTRY - This instruction represents a floating constant pool in
1056 /// the function. The first operand is the ID# for this instruction, the second
1057 /// is the index into the MachineConstantPool that this is, the third is the
1058 /// size in bytes of this constant pool entry.
1059 let neverHasSideEffects = 1, isNotDuplicable = 1 in
1060 def CONSTPOOL_ENTRY :
1061 PseudoInst<(outs), (ins cpinst_operand:$instid, cpinst_operand:$cpidx,
1062 i32imm:$size), NoItinerary, []>;
1064 // FIXME: Marking these as hasSideEffects is necessary to prevent machine DCE
1065 // from removing one half of the matched pairs. That breaks PEI, which assumes
1066 // these will always be in pairs, and asserts if it finds otherwise. Better way?
1067 let Defs = [SP], Uses = [SP], hasSideEffects = 1 in {
1068 def ADJCALLSTACKUP :
1069 PseudoInst<(outs), (ins i32imm:$amt1, i32imm:$amt2, pred:$p), NoItinerary,
1070 [(ARMcallseq_end timm:$amt1, timm:$amt2)]>;
1072 def ADJCALLSTACKDOWN :
1073 PseudoInst<(outs), (ins i32imm:$amt, pred:$p), NoItinerary,
1074 [(ARMcallseq_start timm:$amt)]>;
1077 def NOP : AI<(outs), (ins), MiscFrm, NoItinerary, "nop", "",
1078 [/* For disassembly only; pattern left blank */]>,
1079 Requires<[IsARM, HasV6T2]> {
1080 let Inst{27-16} = 0b001100100000;
1081 let Inst{15-8} = 0b11110000;
1082 let Inst{7-0} = 0b00000000;
1085 def YIELD : AI<(outs), (ins), MiscFrm, NoItinerary, "yield", "",
1086 [/* For disassembly only; pattern left blank */]>,
1087 Requires<[IsARM, HasV6T2]> {
1088 let Inst{27-16} = 0b001100100000;
1089 let Inst{15-8} = 0b11110000;
1090 let Inst{7-0} = 0b00000001;
1093 def WFE : AI<(outs), (ins), MiscFrm, NoItinerary, "wfe", "",
1094 [/* For disassembly only; pattern left blank */]>,
1095 Requires<[IsARM, HasV6T2]> {
1096 let Inst{27-16} = 0b001100100000;
1097 let Inst{15-8} = 0b11110000;
1098 let Inst{7-0} = 0b00000010;
1101 def WFI : AI<(outs), (ins), MiscFrm, NoItinerary, "wfi", "",
1102 [/* For disassembly only; pattern left blank */]>,
1103 Requires<[IsARM, HasV6T2]> {
1104 let Inst{27-16} = 0b001100100000;
1105 let Inst{15-8} = 0b11110000;
1106 let Inst{7-0} = 0b00000011;
1109 def SEL : AI<(outs GPR:$dst), (ins GPR:$a, GPR:$b), DPFrm, NoItinerary, "sel",
1111 [/* For disassembly only; pattern left blank */]>,
1112 Requires<[IsARM, HasV6]> {
1117 let Inst{15-12} = Rd;
1118 let Inst{19-16} = Rn;
1119 let Inst{27-20} = 0b01101000;
1120 let Inst{7-4} = 0b1011;
1121 let Inst{11-8} = 0b1111;
1124 def SEV : AI<(outs), (ins), MiscFrm, NoItinerary, "sev", "",
1125 [/* For disassembly only; pattern left blank */]>,
1126 Requires<[IsARM, HasV6T2]> {
1127 let Inst{27-16} = 0b001100100000;
1128 let Inst{15-8} = 0b11110000;
1129 let Inst{7-0} = 0b00000100;
1132 // The i32imm operand $val can be used by a debugger to store more information
1133 // about the breakpoint.
1134 def BKPT : AI<(outs), (ins i32imm:$val), MiscFrm, NoItinerary, "bkpt", "\t$val",
1135 [/* For disassembly only; pattern left blank */]>,
1138 let Inst{3-0} = val{3-0};
1139 let Inst{19-8} = val{15-4};
1140 let Inst{27-20} = 0b00010010;
1141 let Inst{7-4} = 0b0111;
1144 // Change Processor State is a system instruction -- for disassembly and
1146 // FIXME: Since the asm parser has currently no clean way to handle optional
1147 // operands, create 3 versions of the same instruction. Once there's a clean
1148 // framework to represent optional operands, change this behavior.
1149 class CPS<dag iops, string asm_ops>
1150 : AXI<(outs), iops, MiscFrm, NoItinerary, !strconcat("cps", asm_ops),
1151 [/* For disassembly only; pattern left blank */]>, Requires<[IsARM]> {
1157 let Inst{31-28} = 0b1111;
1158 let Inst{27-20} = 0b00010000;
1159 let Inst{19-18} = imod;
1160 let Inst{17} = M; // Enabled if mode is set;
1162 let Inst{8-6} = iflags;
1164 let Inst{4-0} = mode;
1168 def CPS3p : CPS<(ins imod_op:$imod, iflags_op:$iflags, i32imm:$mode),
1169 "$imod\t$iflags, $mode">;
1170 let mode = 0, M = 0 in
1171 def CPS2p : CPS<(ins imod_op:$imod, iflags_op:$iflags), "$imod\t$iflags">;
1173 let imod = 0, iflags = 0, M = 1 in
1174 def CPS1p : CPS<(ins i32imm:$mode), "\t$mode">;
1176 // Preload signals the memory system of possible future data/instruction access.
1177 // These are for disassembly only.
1178 multiclass APreLoad<bits<1> read, bits<1> data, string opc> {
1180 def i12 : AXI<(outs), (ins addrmode_imm12:$addr), MiscFrm, IIC_Preload,
1181 !strconcat(opc, "\t$addr"),
1182 [(ARMPreload addrmode_imm12:$addr, (i32 read), (i32 data))]> {
1185 let Inst{31-26} = 0b111101;
1186 let Inst{25} = 0; // 0 for immediate form
1187 let Inst{24} = data;
1188 let Inst{23} = addr{12}; // U (add = ('U' == 1))
1189 let Inst{22} = read;
1190 let Inst{21-20} = 0b01;
1191 let Inst{19-16} = addr{16-13}; // Rn
1192 let Inst{15-12} = 0b1111;
1193 let Inst{11-0} = addr{11-0}; // imm12
1196 def rs : AXI<(outs), (ins ldst_so_reg:$shift), MiscFrm, IIC_Preload,
1197 !strconcat(opc, "\t$shift"),
1198 [(ARMPreload ldst_so_reg:$shift, (i32 read), (i32 data))]> {
1200 let Inst{31-26} = 0b111101;
1201 let Inst{25} = 1; // 1 for register form
1202 let Inst{24} = data;
1203 let Inst{23} = shift{12}; // U (add = ('U' == 1))
1204 let Inst{22} = read;
1205 let Inst{21-20} = 0b01;
1206 let Inst{19-16} = shift{16-13}; // Rn
1207 let Inst{15-12} = 0b1111;
1208 let Inst{11-0} = shift{11-0};
1212 defm PLD : APreLoad<1, 1, "pld">, Requires<[IsARM]>;
1213 defm PLDW : APreLoad<0, 1, "pldw">, Requires<[IsARM,HasV7,HasMP]>;
1214 defm PLI : APreLoad<1, 0, "pli">, Requires<[IsARM,HasV7]>;
1216 def SETEND : AXI<(outs),(ins setend_op:$end), MiscFrm, NoItinerary,
1218 [/* For disassembly only; pattern left blank */]>,
1221 let Inst{31-10} = 0b1111000100000001000000;
1226 def DBG : AI<(outs), (ins i32imm:$opt), MiscFrm, NoItinerary, "dbg", "\t$opt",
1227 [/* For disassembly only; pattern left blank */]>,
1228 Requires<[IsARM, HasV7]> {
1230 let Inst{27-4} = 0b001100100000111100001111;
1231 let Inst{3-0} = opt;
1234 // A5.4 Permanently UNDEFINED instructions.
1235 let isBarrier = 1, isTerminator = 1 in
1236 def TRAP : AXI<(outs), (ins), MiscFrm, NoItinerary,
1239 let Inst = 0xe7ffdefe;
1242 // Address computation and loads and stores in PIC mode.
1243 let isNotDuplicable = 1 in {
1244 def PICADD : ARMPseudoInst<(outs GPR:$dst), (ins GPR:$a, pclabel:$cp, pred:$p),
1245 Size4Bytes, IIC_iALUr,
1246 [(set GPR:$dst, (ARMpic_add GPR:$a, imm:$cp))]>;
1248 let AddedComplexity = 10 in {
1249 def PICLDR : ARMPseudoInst<(outs GPR:$dst), (ins addrmodepc:$addr, pred:$p),
1250 Size4Bytes, IIC_iLoad_r,
1251 [(set GPR:$dst, (load addrmodepc:$addr))]>;
1253 def PICLDRH : ARMPseudoInst<(outs GPR:$Rt), (ins addrmodepc:$addr, pred:$p),
1254 Size4Bytes, IIC_iLoad_bh_r,
1255 [(set GPR:$Rt, (zextloadi16 addrmodepc:$addr))]>;
1257 def PICLDRB : ARMPseudoInst<(outs GPR:$Rt), (ins addrmodepc:$addr, pred:$p),
1258 Size4Bytes, IIC_iLoad_bh_r,
1259 [(set GPR:$Rt, (zextloadi8 addrmodepc:$addr))]>;
1261 def PICLDRSH : ARMPseudoInst<(outs GPR:$Rt), (ins addrmodepc:$addr, pred:$p),
1262 Size4Bytes, IIC_iLoad_bh_r,
1263 [(set GPR:$Rt, (sextloadi16 addrmodepc:$addr))]>;
1265 def PICLDRSB : ARMPseudoInst<(outs GPR:$Rt), (ins addrmodepc:$addr, pred:$p),
1266 Size4Bytes, IIC_iLoad_bh_r,
1267 [(set GPR:$Rt, (sextloadi8 addrmodepc:$addr))]>;
1269 let AddedComplexity = 10 in {
1270 def PICSTR : ARMPseudoInst<(outs), (ins GPR:$src, addrmodepc:$addr, pred:$p),
1271 Size4Bytes, IIC_iStore_r, [(store GPR:$src, addrmodepc:$addr)]>;
1273 def PICSTRH : ARMPseudoInst<(outs), (ins GPR:$src, addrmodepc:$addr, pred:$p),
1274 Size4Bytes, IIC_iStore_bh_r, [(truncstorei16 GPR:$src,
1275 addrmodepc:$addr)]>;
1277 def PICSTRB : ARMPseudoInst<(outs), (ins GPR:$src, addrmodepc:$addr, pred:$p),
1278 Size4Bytes, IIC_iStore_bh_r, [(truncstorei8 GPR:$src, addrmodepc:$addr)]>;
1280 } // isNotDuplicable = 1
1283 // LEApcrel - Load a pc-relative address into a register without offending the
1285 let neverHasSideEffects = 1, isReMaterializable = 1 in
1286 // The 'adr' mnemonic encodes differently if the label is before or after
1287 // the instruction. The {24-21} opcode bits are set by the fixup, as we don't
1288 // know until then which form of the instruction will be used.
1289 def ADR : AI1<{0,?,?,0}, (outs GPR:$Rd), (ins adrlabel:$label),
1290 MiscFrm, IIC_iALUi, "adr", "\t$Rd, #$label", []> {
1293 let Inst{27-25} = 0b001;
1295 let Inst{19-16} = 0b1111;
1296 let Inst{15-12} = Rd;
1297 let Inst{11-0} = label;
1299 def LEApcrel : ARMPseudoInst<(outs GPR:$Rd), (ins i32imm:$label, pred:$p),
1300 Size4Bytes, IIC_iALUi, []>;
1302 def LEApcrelJT : ARMPseudoInst<(outs GPR:$Rd),
1303 (ins i32imm:$label, nohash_imm:$id, pred:$p),
1304 Size4Bytes, IIC_iALUi, []>;
1306 //===----------------------------------------------------------------------===//
1307 // Control Flow Instructions.
1310 let isReturn = 1, isTerminator = 1, isBarrier = 1 in {
1312 def BX_RET : AI<(outs), (ins), BrMiscFrm, IIC_Br,
1313 "bx", "\tlr", [(ARMretflag)]>,
1314 Requires<[IsARM, HasV4T]> {
1315 let Inst{27-0} = 0b0001001011111111111100011110;
1319 def MOVPCLR : AI<(outs), (ins), BrMiscFrm, IIC_Br,
1320 "mov", "\tpc, lr", [(ARMretflag)]>,
1321 Requires<[IsARM, NoV4T]> {
1322 let Inst{27-0} = 0b0001101000001111000000001110;
1326 // Indirect branches
1327 let isBranch = 1, isTerminator = 1, isBarrier = 1, isIndirectBranch = 1 in {
1329 def BX : AXI<(outs), (ins GPR:$dst), BrMiscFrm, IIC_Br, "bx\t$dst",
1330 [(brind GPR:$dst)]>,
1331 Requires<[IsARM, HasV4T]> {
1333 let Inst{31-4} = 0b1110000100101111111111110001;
1334 let Inst{3-0} = dst;
1338 // FIXME: We would really like to define this as a vanilla ARMPat like:
1339 // ARMPat<(brind GPR:$dst), (MOVr PC, GPR:$dst)>
1340 // With that, however, we can't set isBranch, isTerminator, etc..
1341 def MOVPCRX : ARMPseudoInst<(outs), (ins GPR:$dst),
1342 Size4Bytes, IIC_Br, [(brind GPR:$dst)]>,
1343 Requires<[IsARM, NoV4T]>;
1346 // All calls clobber the non-callee saved registers. SP is marked as
1347 // a use to prevent stack-pointer assignments that appear immediately
1348 // before calls from potentially appearing dead.
1350 // On non-Darwin platforms R9 is callee-saved.
1351 // FIXME: Do we really need a non-predicated version? If so, it should
1352 // at least be a pseudo instruction expanding to the predicated version
1353 // at MC lowering time.
1354 Defs = [R0, R1, R2, R3, R12, LR,
1355 D0, D1, D2, D3, D4, D5, D6, D7,
1356 D16, D17, D18, D19, D20, D21, D22, D23,
1357 D24, D25, D26, D27, D28, D29, D30, D31, CPSR, FPSCR],
1359 def BL : ABXI<0b1011, (outs), (ins bl_target:$func, variable_ops),
1360 IIC_Br, "bl\t$func",
1361 [(ARMcall tglobaladdr:$func)]>,
1362 Requires<[IsARM, IsNotDarwin]> {
1363 let Inst{31-28} = 0b1110;
1365 let Inst{23-0} = func;
1368 def BL_pred : ABI<0b1011, (outs), (ins bl_target:$func, variable_ops),
1369 IIC_Br, "bl", "\t$func",
1370 [(ARMcall_pred tglobaladdr:$func)]>,
1371 Requires<[IsARM, IsNotDarwin]> {
1373 let Inst{23-0} = func;
1377 def BLX : AXI<(outs), (ins GPR:$func, variable_ops), BrMiscFrm,
1378 IIC_Br, "blx\t$func",
1379 [(ARMcall GPR:$func)]>,
1380 Requires<[IsARM, HasV5T, IsNotDarwin]> {
1382 let Inst{31-4} = 0b1110000100101111111111110011;
1383 let Inst{3-0} = func;
1386 def BLX_pred : AI<(outs), (ins GPR:$func, variable_ops), BrMiscFrm,
1387 IIC_Br, "blx", "\t$func",
1388 [(ARMcall_pred GPR:$func)]>,
1389 Requires<[IsARM, HasV5T, IsNotDarwin]> {
1391 let Inst{27-4} = 0b000100101111111111110011;
1392 let Inst{3-0} = func;
1396 // Note: Restrict $func to the tGPR regclass to prevent it being in LR.
1397 def BX_CALL : ARMPseudoInst<(outs), (ins tGPR:$func, variable_ops),
1398 Size8Bytes, IIC_Br, [(ARMcall_nolink tGPR:$func)]>,
1399 Requires<[IsARM, HasV4T, IsNotDarwin]>;
1402 def BMOVPCRX_CALL : ARMPseudoInst<(outs), (ins tGPR:$func, variable_ops),
1403 Size8Bytes, IIC_Br, [(ARMcall_nolink tGPR:$func)]>,
1404 Requires<[IsARM, NoV4T, IsNotDarwin]>;
1408 // On Darwin R9 is call-clobbered.
1409 // R7 is marked as a use to prevent frame-pointer assignments from being
1410 // moved above / below calls.
1411 Defs = [R0, R1, R2, R3, R9, R12, LR,
1412 D0, D1, D2, D3, D4, D5, D6, D7,
1413 D16, D17, D18, D19, D20, D21, D22, D23,
1414 D24, D25, D26, D27, D28, D29, D30, D31, CPSR, FPSCR],
1415 Uses = [R7, SP] in {
1416 def BLr9 : ARMPseudoInst<(outs), (ins bltarget:$func, variable_ops),
1418 [(ARMcall tglobaladdr:$func)]>, Requires<[IsARM, IsDarwin]>;
1420 def BLr9_pred : ARMPseudoInst<(outs),
1421 (ins bltarget:$func, pred:$p, variable_ops),
1423 [(ARMcall_pred tglobaladdr:$func)]>,
1424 Requires<[IsARM, IsDarwin]>;
1427 def BLXr9 : ARMPseudoInst<(outs), (ins GPR:$func, variable_ops),
1429 [(ARMcall GPR:$func)]>, Requires<[IsARM, HasV5T, IsDarwin]>;
1431 def BLXr9_pred: ARMPseudoInst<(outs), (ins GPR:$func, pred:$p, variable_ops),
1433 [(ARMcall_pred GPR:$func)]>,
1434 Requires<[IsARM, HasV5T, IsDarwin]>;
1437 // Note: Restrict $func to the tGPR regclass to prevent it being in LR.
1438 def BXr9_CALL : ARMPseudoInst<(outs), (ins tGPR:$func, variable_ops),
1439 Size8Bytes, IIC_Br, [(ARMcall_nolink tGPR:$func)]>,
1440 Requires<[IsARM, HasV4T, IsDarwin]>;
1443 def BMOVPCRXr9_CALL : ARMPseudoInst<(outs), (ins tGPR:$func, variable_ops),
1444 Size8Bytes, IIC_Br, [(ARMcall_nolink tGPR:$func)]>,
1445 Requires<[IsARM, NoV4T, IsDarwin]>;
1450 // FIXME: The Thumb versions of these should live in ARMInstrThumb.td
1451 let isCall = 1, isTerminator = 1, isReturn = 1, isBarrier = 1 in {
1453 let Defs = [R0, R1, R2, R3, R9, R12,
1454 D0, D1, D2, D3, D4, D5, D6, D7,
1455 D16, D17, D18, D19, D20, D21, D22, D23, D24, D25, D26,
1456 D27, D28, D29, D30, D31, PC],
1458 def TCRETURNdi : PseudoInst<(outs), (ins i32imm:$dst, variable_ops),
1459 IIC_Br, []>, Requires<[IsDarwin]>;
1461 def TCRETURNri : PseudoInst<(outs), (ins tcGPR:$dst, variable_ops),
1462 IIC_Br, []>, Requires<[IsDarwin]>;
1464 def TAILJMPd : ARMPseudoInst<(outs), (ins brtarget:$dst, variable_ops),
1466 []>, Requires<[IsARM, IsDarwin]>;
1468 def tTAILJMPd: tPseudoInst<(outs), (ins brtarget:$dst, variable_ops),
1470 []>, Requires<[IsThumb, IsDarwin]>;
1472 def TAILJMPr : ARMPseudoInst<(outs), (ins tcGPR:$dst, variable_ops),
1474 []>, Requires<[IsARM, IsDarwin]>;
1476 def tTAILJMPr : tPseudoInst<(outs), (ins tcGPR:$dst, variable_ops),
1478 []>, Requires<[IsThumb, IsDarwin]>;
1481 // Non-Darwin versions (the difference is R9).
1482 let Defs = [R0, R1, R2, R3, R12,
1483 D0, D1, D2, D3, D4, D5, D6, D7,
1484 D16, D17, D18, D19, D20, D21, D22, D23, D24, D25, D26,
1485 D27, D28, D29, D30, D31, PC],
1487 def TCRETURNdiND : PseudoInst<(outs), (ins i32imm:$dst, variable_ops),
1488 IIC_Br, []>, Requires<[IsNotDarwin]>;
1490 def TCRETURNriND : PseudoInst<(outs), (ins tcGPR:$dst, variable_ops),
1491 IIC_Br, []>, Requires<[IsNotDarwin]>;
1493 def TAILJMPdND : ARMPseudoInst<(outs), (ins brtarget:$dst, variable_ops),
1495 []>, Requires<[IsARM, IsNotDarwin]>;
1497 def tTAILJMPdND : tPseudoInst<(outs), (ins brtarget:$dst, variable_ops),
1499 []>, Requires<[IsThumb, IsNotDarwin]>;
1501 def TAILJMPrND : ARMPseudoInst<(outs), (ins tcGPR:$dst, variable_ops),
1503 []>, Requires<[IsARM, IsNotDarwin]>;
1504 def tTAILJMPrND : tPseudoInst<(outs), (ins tcGPR:$dst, variable_ops),
1506 []>, Requires<[IsThumb, IsNotDarwin]>;
1510 let isBranch = 1, isTerminator = 1 in {
1511 // B is "predicable" since it's just a Bcc with an 'always' condition.
1512 let isBarrier = 1 in {
1513 let isPredicable = 1 in
1514 // FIXME: We shouldn't need this pseudo at all. Just using Bcc directly
1515 // should be sufficient.
1516 def B : ARMPseudoInst<(outs), (ins brtarget:$target), Size4Bytes, IIC_Br,
1519 let isNotDuplicable = 1, isIndirectBranch = 1 in {
1520 def BR_JTr : ARMPseudoInst<(outs),
1521 (ins GPR:$target, i32imm:$jt, i32imm:$id),
1522 SizeSpecial, IIC_Br,
1523 [(ARMbrjt GPR:$target, tjumptable:$jt, imm:$id)]>;
1524 // FIXME: This shouldn't use the generic "addrmode2," but rather be split
1525 // into i12 and rs suffixed versions.
1526 def BR_JTm : ARMPseudoInst<(outs),
1527 (ins addrmode2:$target, i32imm:$jt, i32imm:$id),
1528 SizeSpecial, IIC_Br,
1529 [(ARMbrjt (i32 (load addrmode2:$target)), tjumptable:$jt,
1531 def BR_JTadd : ARMPseudoInst<(outs),
1532 (ins GPR:$target, GPR:$idx, i32imm:$jt, i32imm:$id),
1533 SizeSpecial, IIC_Br,
1534 [(ARMbrjt (add GPR:$target, GPR:$idx), tjumptable:$jt,
1536 } // isNotDuplicable = 1, isIndirectBranch = 1
1539 // FIXME: should be able to write a pattern for ARMBrcond, but can't use
1540 // a two-value operand where a dag node expects two operands. :(
1541 def Bcc : ABI<0b1010, (outs), (ins br_target:$target),
1542 IIC_Br, "b", "\t$target",
1543 [/*(ARMbrcond bb:$target, imm:$cc, CCR:$ccr)*/]> {
1545 let Inst{23-0} = target;
1549 // BLX (immediate) -- for disassembly only
1550 def BLXi : AXI<(outs), (ins br_target:$target), BrMiscFrm, NoItinerary,
1551 "blx\t$target", [/* pattern left blank */]>,
1552 Requires<[IsARM, HasV5T]> {
1553 let Inst{31-25} = 0b1111101;
1555 let Inst{23-0} = target{24-1};
1556 let Inst{24} = target{0};
1559 // Branch and Exchange Jazelle -- for disassembly only
1560 def BXJ : ABI<0b0001, (outs), (ins GPR:$func), NoItinerary, "bxj", "\t$func",
1561 [/* For disassembly only; pattern left blank */]> {
1562 let Inst{23-20} = 0b0010;
1563 //let Inst{19-8} = 0xfff;
1564 let Inst{7-4} = 0b0010;
1567 // Secure Monitor Call is a system instruction -- for disassembly only
1568 def SMC : ABI<0b0001, (outs), (ins i32imm:$opt), NoItinerary, "smc", "\t$opt",
1569 [/* For disassembly only; pattern left blank */]> {
1571 let Inst{23-4} = 0b01100000000000000111;
1572 let Inst{3-0} = opt;
1575 // Supervisor Call (Software Interrupt) -- for disassembly only
1576 let isCall = 1, Uses = [SP] in {
1577 def SVC : ABI<0b1111, (outs), (ins i32imm:$svc), IIC_Br, "svc", "\t$svc",
1578 [/* For disassembly only; pattern left blank */]> {
1580 let Inst{23-0} = svc;
1583 def : MnemonicAlias<"swi", "svc">;
1585 // Store Return State is a system instruction -- for disassembly only
1586 let isCodeGenOnly = 1 in { // FIXME: This should not use submode!
1587 def SRSW : ABXI<{1,0,0,?}, (outs), (ins ldstm_mode:$amode, i32imm:$mode),
1588 NoItinerary, "srs${amode}\tsp!, $mode",
1589 [/* For disassembly only; pattern left blank */]> {
1590 let Inst{31-28} = 0b1111;
1591 let Inst{22-20} = 0b110; // W = 1
1592 let Inst{19-8} = 0xd05;
1593 let Inst{7-5} = 0b000;
1596 def SRS : ABXI<{1,0,0,?}, (outs), (ins ldstm_mode:$amode, i32imm:$mode),
1597 NoItinerary, "srs${amode}\tsp, $mode",
1598 [/* For disassembly only; pattern left blank */]> {
1599 let Inst{31-28} = 0b1111;
1600 let Inst{22-20} = 0b100; // W = 0
1601 let Inst{19-8} = 0xd05;
1602 let Inst{7-5} = 0b000;
1605 // Return From Exception is a system instruction -- for disassembly only
1606 def RFEW : ABXI<{1,0,0,?}, (outs), (ins ldstm_mode:$amode, GPR:$base),
1607 NoItinerary, "rfe${amode}\t$base!",
1608 [/* For disassembly only; pattern left blank */]> {
1609 let Inst{31-28} = 0b1111;
1610 let Inst{22-20} = 0b011; // W = 1
1611 let Inst{15-0} = 0x0a00;
1614 def RFE : ABXI<{1,0,0,?}, (outs), (ins ldstm_mode:$amode, GPR:$base),
1615 NoItinerary, "rfe${amode}\t$base",
1616 [/* For disassembly only; pattern left blank */]> {
1617 let Inst{31-28} = 0b1111;
1618 let Inst{22-20} = 0b001; // W = 0
1619 let Inst{15-0} = 0x0a00;
1621 } // isCodeGenOnly = 1
1623 //===----------------------------------------------------------------------===//
1624 // Load / store Instructions.
1630 defm LDR : AI_ldr1<0, "ldr", IIC_iLoad_r, IIC_iLoad_si,
1631 UnOpFrag<(load node:$Src)>>;
1632 defm LDRB : AI_ldr1<1, "ldrb", IIC_iLoad_bh_r, IIC_iLoad_bh_si,
1633 UnOpFrag<(zextloadi8 node:$Src)>>;
1634 defm STR : AI_str1<0, "str", IIC_iStore_r, IIC_iStore_si,
1635 BinOpFrag<(store node:$LHS, node:$RHS)>>;
1636 defm STRB : AI_str1<1, "strb", IIC_iStore_bh_r, IIC_iStore_bh_si,
1637 BinOpFrag<(truncstorei8 node:$LHS, node:$RHS)>>;
1639 // Special LDR for loads from non-pc-relative constpools.
1640 let canFoldAsLoad = 1, mayLoad = 1, neverHasSideEffects = 1,
1641 isReMaterializable = 1 in
1642 def LDRcp : AI2ldst<0b010, 1, 0, (outs GPR:$Rt), (ins addrmode_imm12:$addr),
1643 AddrMode_i12, LdFrm, IIC_iLoad_r, "ldr", "\t$Rt, $addr",
1647 let Inst{23} = addr{12}; // U (add = ('U' == 1))
1648 let Inst{19-16} = 0b1111;
1649 let Inst{15-12} = Rt;
1650 let Inst{11-0} = addr{11-0}; // imm12
1653 // Loads with zero extension
1654 def LDRH : AI3ld<0b1011, 1, (outs GPR:$Rt), (ins addrmode3:$addr), LdMiscFrm,
1655 IIC_iLoad_bh_r, "ldrh", "\t$Rt, $addr",
1656 [(set GPR:$Rt, (zextloadi16 addrmode3:$addr))]>;
1658 // Loads with sign extension
1659 def LDRSH : AI3ld<0b1111, 1, (outs GPR:$Rt), (ins addrmode3:$addr), LdMiscFrm,
1660 IIC_iLoad_bh_r, "ldrsh", "\t$Rt, $addr",
1661 [(set GPR:$Rt, (sextloadi16 addrmode3:$addr))]>;
1663 def LDRSB : AI3ld<0b1101, 1, (outs GPR:$Rt), (ins addrmode3:$addr), LdMiscFrm,
1664 IIC_iLoad_bh_r, "ldrsb", "\t$Rt, $addr",
1665 [(set GPR:$Rt, (sextloadi8 addrmode3:$addr))]>;
1667 let mayLoad = 1, neverHasSideEffects = 1, hasExtraDefRegAllocReq = 1 in {
1669 def LDRD : AI3ld<0b1101, 0, (outs GPR:$Rd, GPR:$dst2),
1670 (ins addrmode3:$addr), LdMiscFrm,
1671 IIC_iLoad_d_r, "ldrd", "\t$Rd, $dst2, $addr",
1672 []>, Requires<[IsARM, HasV5TE]>;
1676 multiclass AI2_ldridx<bit isByte, string opc, InstrItinClass itin> {
1677 def _PRE : AI2ldstidx<1, isByte, 1, (outs GPR:$Rt, GPR:$Rn_wb),
1678 (ins addrmode2:$addr), IndexModePre, LdFrm, itin,
1679 opc, "\t$Rt, $addr!", "$addr.base = $Rn_wb", []> {
1681 // {13} 1 == Rm, 0 == imm12
1685 let Inst{25} = addr{13};
1686 let Inst{23} = addr{12};
1687 let Inst{19-16} = addr{17-14};
1688 let Inst{11-0} = addr{11-0};
1689 let AsmMatchConverter = "CvtLdWriteBackRegAddrMode2";
1691 def _POST : AI2ldstidx<1, isByte, 0, (outs GPR:$Rt, GPR:$Rn_wb),
1692 (ins GPR:$Rn, am2offset:$offset),
1693 IndexModePost, LdFrm, itin,
1694 opc, "\t$Rt, [$Rn], $offset", "$Rn = $Rn_wb", []> {
1695 // {13} 1 == Rm, 0 == imm12
1700 let Inst{25} = offset{13};
1701 let Inst{23} = offset{12};
1702 let Inst{19-16} = Rn;
1703 let Inst{11-0} = offset{11-0};
1707 let mayLoad = 1, neverHasSideEffects = 1 in {
1708 defm LDR : AI2_ldridx<0, "ldr", IIC_iLoad_ru>;
1709 defm LDRB : AI2_ldridx<1, "ldrb", IIC_iLoad_bh_ru>;
1712 multiclass AI3_ldridx<bits<4> op, bit op20, string opc, InstrItinClass itin> {
1713 def _PRE : AI3ldstidx<op, op20, 1, 1, (outs GPR:$Rt, GPR:$Rn_wb),
1714 (ins addrmode3:$addr), IndexModePre,
1716 opc, "\t$Rt, $addr!", "$addr.base = $Rn_wb", []> {
1718 let Inst{23} = addr{8}; // U bit
1719 let Inst{22} = addr{13}; // 1 == imm8, 0 == Rm
1720 let Inst{19-16} = addr{12-9}; // Rn
1721 let Inst{11-8} = addr{7-4}; // imm7_4/zero
1722 let Inst{3-0} = addr{3-0}; // imm3_0/Rm
1724 def _POST : AI3ldstidx<op, op20, 1, 0, (outs GPR:$Rt, GPR:$Rn_wb),
1725 (ins GPR:$Rn, am3offset:$offset), IndexModePost,
1727 opc, "\t$Rt, [$Rn], $offset", "$Rn = $Rn_wb", []> {
1730 let Inst{23} = offset{8}; // U bit
1731 let Inst{22} = offset{9}; // 1 == imm8, 0 == Rm
1732 let Inst{19-16} = Rn;
1733 let Inst{11-8} = offset{7-4}; // imm7_4/zero
1734 let Inst{3-0} = offset{3-0}; // imm3_0/Rm
1738 let mayLoad = 1, neverHasSideEffects = 1 in {
1739 defm LDRH : AI3_ldridx<0b1011, 1, "ldrh", IIC_iLoad_bh_ru>;
1740 defm LDRSH : AI3_ldridx<0b1111, 1, "ldrsh", IIC_iLoad_bh_ru>;
1741 defm LDRSB : AI3_ldridx<0b1101, 1, "ldrsb", IIC_iLoad_bh_ru>;
1742 let hasExtraDefRegAllocReq = 1, isCodeGenOnly = 1 in
1743 defm LDRD : AI3_ldridx<0b1101, 0, "ldrd", IIC_iLoad_d_ru>;
1744 } // mayLoad = 1, neverHasSideEffects = 1
1746 // LDRT, LDRBT, LDRSBT, LDRHT, LDRSHT are for disassembly only.
1747 let mayLoad = 1, neverHasSideEffects = 1 in {
1748 def LDRT : AI2ldstidx<1, 0, 0, (outs GPR:$Rt, GPR:$base_wb),
1749 (ins addrmode2:$addr), IndexModePost, LdFrm, IIC_iLoad_ru,
1750 "ldrt", "\t$Rt, $addr", "$addr.base = $base_wb", []> {
1752 // {13} 1 == Rm, 0 == imm12
1756 let Inst{25} = addr{13};
1757 let Inst{23} = addr{12};
1758 let Inst{21} = 1; // overwrite
1759 let Inst{19-16} = addr{17-14};
1760 let Inst{11-0} = addr{11-0};
1761 let AsmMatchConverter = "CvtLdWriteBackRegAddrMode2";
1763 def LDRBT : AI2ldstidx<1, 1, 0, (outs GPR:$Rt, GPR:$base_wb),
1764 (ins addrmode2:$addr), IndexModePost, LdFrm, IIC_iLoad_bh_ru,
1765 "ldrbt", "\t$Rt, $addr", "$addr.base = $base_wb", []> {
1767 // {13} 1 == Rm, 0 == imm12
1771 let Inst{25} = addr{13};
1772 let Inst{23} = addr{12};
1773 let Inst{21} = 1; // overwrite
1774 let Inst{19-16} = addr{17-14};
1775 let Inst{11-0} = addr{11-0};
1776 let AsmMatchConverter = "CvtLdWriteBackRegAddrMode2";
1778 def LDRSBT : AI3ldstidxT<0b1101, 1, 1, 0, (outs GPR:$Rt, GPR:$base_wb),
1779 (ins addrmode3:$addr), IndexModePost, LdMiscFrm, IIC_iLoad_bh_ru,
1780 "ldrsbt", "\t$Rt, $addr", "$addr.base = $base_wb", []> {
1781 let Inst{21} = 1; // overwrite
1783 def LDRHT : AI3ldstidxT<0b1011, 1, 1, 0, (outs GPR:$Rt, GPR:$base_wb),
1784 (ins addrmode3:$addr), IndexModePost, LdMiscFrm, IIC_iLoad_bh_ru,
1785 "ldrht", "\t$Rt, $addr", "$addr.base = $base_wb", []> {
1786 let Inst{21} = 1; // overwrite
1788 def LDRSHT : AI3ldstidxT<0b1111, 1, 1, 0, (outs GPR:$Rt, GPR:$base_wb),
1789 (ins addrmode3:$addr), IndexModePost, LdMiscFrm, IIC_iLoad_bh_ru,
1790 "ldrsht", "\t$Rt, $addr", "$addr.base = $base_wb", []> {
1791 let Inst{21} = 1; // overwrite
1797 // Stores with truncate
1798 def STRH : AI3str<0b1011, (outs), (ins GPR:$Rt, addrmode3:$addr), StMiscFrm,
1799 IIC_iStore_bh_r, "strh", "\t$Rt, $addr",
1800 [(truncstorei16 GPR:$Rt, addrmode3:$addr)]>;
1803 let mayStore = 1, neverHasSideEffects = 1, hasExtraSrcRegAllocReq = 1 in
1804 def STRD : AI3str<0b1111, (outs), (ins GPR:$Rt, GPR:$src2, addrmode3:$addr),
1805 StMiscFrm, IIC_iStore_d_r,
1806 "strd", "\t$Rt, $src2, $addr", []>, Requires<[IsARM, HasV5TE]>;
1809 def STR_PRE : AI2stridx<0, 1, (outs GPR:$Rn_wb),
1810 (ins GPR:$Rt, GPR:$Rn, am2offset:$offset),
1811 IndexModePre, StFrm, IIC_iStore_ru,
1812 "str", "\t$Rt, [$Rn, $offset]!", "$Rn = $Rn_wb",
1814 (pre_store GPR:$Rt, GPR:$Rn, am2offset:$offset))]>;
1816 def STR_POST : AI2stridx<0, 0, (outs GPR:$Rn_wb),
1817 (ins GPR:$Rt, GPR:$Rn, am2offset:$offset),
1818 IndexModePost, StFrm, IIC_iStore_ru,
1819 "str", "\t$Rt, [$Rn], $offset", "$Rn = $Rn_wb",
1821 (post_store GPR:$Rt, GPR:$Rn, am2offset:$offset))]>;
1823 def STRB_PRE : AI2stridx<1, 1, (outs GPR:$Rn_wb),
1824 (ins GPR:$Rt, GPR:$Rn, am2offset:$offset),
1825 IndexModePre, StFrm, IIC_iStore_bh_ru,
1826 "strb", "\t$Rt, [$Rn, $offset]!", "$Rn = $Rn_wb",
1827 [(set GPR:$Rn_wb, (pre_truncsti8 GPR:$Rt,
1828 GPR:$Rn, am2offset:$offset))]>;
1829 def STRB_POST: AI2stridx<1, 0, (outs GPR:$Rn_wb),
1830 (ins GPR:$Rt, GPR:$Rn, am2offset:$offset),
1831 IndexModePost, StFrm, IIC_iStore_bh_ru,
1832 "strb", "\t$Rt, [$Rn], $offset", "$Rn = $Rn_wb",
1833 [(set GPR:$Rn_wb, (post_truncsti8 GPR:$Rt,
1834 GPR:$Rn, am2offset:$offset))]>;
1836 def STRH_PRE : AI3stridx<0b1011, 0, 1, (outs GPR:$Rn_wb),
1837 (ins GPR:$Rt, GPR:$Rn, am3offset:$offset),
1838 IndexModePre, StMiscFrm, IIC_iStore_ru,
1839 "strh", "\t$Rt, [$Rn, $offset]!", "$Rn = $Rn_wb",
1841 (pre_truncsti16 GPR:$Rt, GPR:$Rn, am3offset:$offset))]>;
1843 def STRH_POST: AI3stridx<0b1011, 0, 0, (outs GPR:$Rn_wb),
1844 (ins GPR:$Rt, GPR:$Rn, am3offset:$offset),
1845 IndexModePost, StMiscFrm, IIC_iStore_bh_ru,
1846 "strh", "\t$Rt, [$Rn], $offset", "$Rn = $Rn_wb",
1847 [(set GPR:$Rn_wb, (post_truncsti16 GPR:$Rt,
1848 GPR:$Rn, am3offset:$offset))]>;
1850 // For disassembly only
1851 def STRD_PRE : AI3stdpr<(outs GPR:$base_wb),
1852 (ins GPR:$src1, GPR:$src2, GPR:$base, am3offset:$offset),
1853 StMiscFrm, IIC_iStore_d_ru,
1854 "strd", "\t$src1, $src2, [$base, $offset]!",
1855 "$base = $base_wb", []>;
1857 // For disassembly only
1858 def STRD_POST: AI3stdpo<(outs GPR:$base_wb),
1859 (ins GPR:$src1, GPR:$src2, GPR:$base, am3offset:$offset),
1860 StMiscFrm, IIC_iStore_d_ru,
1861 "strd", "\t$src1, $src2, [$base], $offset",
1862 "$base = $base_wb", []>;
1864 // STRT, STRBT, and STRHT are for disassembly only.
1866 def STRT : AI2stridxT<0, 0, (outs GPR:$Rn_wb), (ins GPR:$Rt, addrmode2:$addr),
1867 IndexModePost, StFrm, IIC_iStore_ru,
1868 "strt", "\t$Rt, $addr", "$addr.base = $Rn_wb",
1869 [/* For disassembly only; pattern left blank */]> {
1870 let Inst{21} = 1; // overwrite
1871 let AsmMatchConverter = "CvtStWriteBackRegAddrMode2";
1874 def STRBT : AI2stridxT<1, 0, (outs GPR:$Rn_wb), (ins GPR:$Rt, addrmode2:$addr),
1875 IndexModePost, StFrm, IIC_iStore_bh_ru,
1876 "strbt", "\t$Rt, $addr", "$addr.base = $Rn_wb",
1877 [/* For disassembly only; pattern left blank */]> {
1878 let Inst{21} = 1; // overwrite
1879 let AsmMatchConverter = "CvtStWriteBackRegAddrMode2";
1882 def STRHT: AI3sthpo<(outs GPR:$base_wb), (ins GPR:$Rt, addrmode3:$addr),
1883 StMiscFrm, IIC_iStore_bh_ru,
1884 "strht", "\t$Rt, $addr", "$addr.base = $base_wb",
1885 [/* For disassembly only; pattern left blank */]> {
1886 let Inst{21} = 1; // overwrite
1887 let AsmMatchConverter = "CvtStWriteBackRegAddrMode3";
1890 //===----------------------------------------------------------------------===//
1891 // Load / store multiple Instructions.
1894 multiclass arm_ldst_mult<string asm, bit L_bit, Format f,
1895 InstrItinClass itin, InstrItinClass itin_upd> {
1897 AXI4<(outs), (ins GPR:$Rn, pred:$p, reglist:$regs, variable_ops),
1898 IndexModeNone, f, itin,
1899 !strconcat(asm, "ia${p}\t$Rn, $regs"), "", []> {
1900 let Inst{24-23} = 0b01; // Increment After
1901 let Inst{21} = 0; // No writeback
1902 let Inst{20} = L_bit;
1905 AXI4<(outs GPR:$wb), (ins GPR:$Rn, pred:$p, reglist:$regs, variable_ops),
1906 IndexModeUpd, f, itin_upd,
1907 !strconcat(asm, "ia${p}\t$Rn!, $regs"), "$Rn = $wb", []> {
1908 let Inst{24-23} = 0b01; // Increment After
1909 let Inst{21} = 1; // Writeback
1910 let Inst{20} = L_bit;
1913 AXI4<(outs), (ins GPR:$Rn, pred:$p, reglist:$regs, variable_ops),
1914 IndexModeNone, f, itin,
1915 !strconcat(asm, "da${p}\t$Rn, $regs"), "", []> {
1916 let Inst{24-23} = 0b00; // Decrement After
1917 let Inst{21} = 0; // No writeback
1918 let Inst{20} = L_bit;
1921 AXI4<(outs GPR:$wb), (ins GPR:$Rn, pred:$p, reglist:$regs, variable_ops),
1922 IndexModeUpd, f, itin_upd,
1923 !strconcat(asm, "da${p}\t$Rn!, $regs"), "$Rn = $wb", []> {
1924 let Inst{24-23} = 0b00; // Decrement After
1925 let Inst{21} = 1; // Writeback
1926 let Inst{20} = L_bit;
1929 AXI4<(outs), (ins GPR:$Rn, pred:$p, reglist:$regs, variable_ops),
1930 IndexModeNone, f, itin,
1931 !strconcat(asm, "db${p}\t$Rn, $regs"), "", []> {
1932 let Inst{24-23} = 0b10; // Decrement Before
1933 let Inst{21} = 0; // No writeback
1934 let Inst{20} = L_bit;
1937 AXI4<(outs GPR:$wb), (ins GPR:$Rn, pred:$p, reglist:$regs, variable_ops),
1938 IndexModeUpd, f, itin_upd,
1939 !strconcat(asm, "db${p}\t$Rn!, $regs"), "$Rn = $wb", []> {
1940 let Inst{24-23} = 0b10; // Decrement Before
1941 let Inst{21} = 1; // Writeback
1942 let Inst{20} = L_bit;
1945 AXI4<(outs), (ins GPR:$Rn, pred:$p, reglist:$regs, variable_ops),
1946 IndexModeNone, f, itin,
1947 !strconcat(asm, "ib${p}\t$Rn, $regs"), "", []> {
1948 let Inst{24-23} = 0b11; // Increment Before
1949 let Inst{21} = 0; // No writeback
1950 let Inst{20} = L_bit;
1953 AXI4<(outs GPR:$wb), (ins GPR:$Rn, pred:$p, reglist:$regs, variable_ops),
1954 IndexModeUpd, f, itin_upd,
1955 !strconcat(asm, "ib${p}\t$Rn!, $regs"), "$Rn = $wb", []> {
1956 let Inst{24-23} = 0b11; // Increment Before
1957 let Inst{21} = 1; // Writeback
1958 let Inst{20} = L_bit;
1962 let neverHasSideEffects = 1 in {
1964 let mayLoad = 1, hasExtraDefRegAllocReq = 1 in
1965 defm LDM : arm_ldst_mult<"ldm", 1, LdStMulFrm, IIC_iLoad_m, IIC_iLoad_mu>;
1967 let mayStore = 1, hasExtraSrcRegAllocReq = 1 in
1968 defm STM : arm_ldst_mult<"stm", 0, LdStMulFrm, IIC_iStore_m, IIC_iStore_mu>;
1970 } // neverHasSideEffects
1972 // Load / Store Multiple Mnemonic Aliases
1973 def : MnemonicAlias<"ldm", "ldmia">;
1974 def : MnemonicAlias<"stm", "stmia">;
1976 // FIXME: remove when we have a way to marking a MI with these properties.
1977 // FIXME: Should pc be an implicit operand like PICADD, etc?
1978 let isReturn = 1, isTerminator = 1, isBarrier = 1, mayLoad = 1,
1979 hasExtraDefRegAllocReq = 1, isCodeGenOnly = 1 in
1980 def LDMIA_RET : ARMPseudoInst<(outs GPR:$wb), (ins GPR:$Rn, pred:$p,
1981 reglist:$regs, variable_ops),
1982 Size4Bytes, IIC_iLoad_mBr, []>,
1983 RegConstraint<"$Rn = $wb">;
1985 //===----------------------------------------------------------------------===//
1986 // Move Instructions.
1989 let neverHasSideEffects = 1 in
1990 def MOVr : AsI1<0b1101, (outs GPR:$Rd), (ins GPR:$Rm), DPFrm, IIC_iMOVr,
1991 "mov", "\t$Rd, $Rm", []>, UnaryDP {
1995 let Inst{19-16} = 0b0000;
1996 let Inst{11-4} = 0b00000000;
1999 let Inst{15-12} = Rd;
2002 // A version for the smaller set of tail call registers.
2003 let neverHasSideEffects = 1 in
2004 def MOVr_TC : AsI1<0b1101, (outs tcGPR:$Rd), (ins tcGPR:$Rm), DPFrm,
2005 IIC_iMOVr, "mov", "\t$Rd, $Rm", []>, UnaryDP {
2009 let Inst{11-4} = 0b00000000;
2012 let Inst{15-12} = Rd;
2015 def MOVs : AsI1<0b1101, (outs GPR:$Rd), (ins shift_so_reg:$src),
2016 DPSoRegFrm, IIC_iMOVsr,
2017 "mov", "\t$Rd, $src", [(set GPR:$Rd, shift_so_reg:$src)]>,
2021 let Inst{15-12} = Rd;
2022 let Inst{19-16} = 0b0000;
2023 let Inst{11-0} = src;
2027 let isReMaterializable = 1, isAsCheapAsAMove = 1, isMoveImm = 1 in
2028 def MOVi : AsI1<0b1101, (outs GPR:$Rd), (ins so_imm:$imm), DPFrm, IIC_iMOVi,
2029 "mov", "\t$Rd, $imm", [(set GPR:$Rd, so_imm:$imm)]>, UnaryDP {
2033 let Inst{15-12} = Rd;
2034 let Inst{19-16} = 0b0000;
2035 let Inst{11-0} = imm;
2038 let isReMaterializable = 1, isAsCheapAsAMove = 1, isMoveImm = 1 in
2039 def MOVi16 : AI1<0b1000, (outs GPR:$Rd), (ins i32imm_hilo16:$imm),
2041 "movw", "\t$Rd, $imm",
2042 [(set GPR:$Rd, imm0_65535:$imm)]>,
2043 Requires<[IsARM, HasV6T2]>, UnaryDP {
2046 let Inst{15-12} = Rd;
2047 let Inst{11-0} = imm{11-0};
2048 let Inst{19-16} = imm{15-12};
2053 def MOVi16_ga_pcrel : PseudoInst<(outs GPR:$Rd),
2054 (ins i32imm:$addr, pclabel:$id), IIC_iMOVi, []>;
2056 let Constraints = "$src = $Rd" in {
2057 def MOVTi16 : AI1<0b1010, (outs GPR:$Rd), (ins GPR:$src, i32imm_hilo16:$imm),
2059 "movt", "\t$Rd, $imm",
2061 (or (and GPR:$src, 0xffff),
2062 lo16AllZero:$imm))]>, UnaryDP,
2063 Requires<[IsARM, HasV6T2]> {
2066 let Inst{15-12} = Rd;
2067 let Inst{11-0} = imm{11-0};
2068 let Inst{19-16} = imm{15-12};
2073 def MOVTi16_ga_pcrel : PseudoInst<(outs GPR:$Rd),
2074 (ins GPR:$src, i32imm:$addr, pclabel:$id), IIC_iMOVi, []>;
2078 def : ARMPat<(or GPR:$src, 0xffff0000), (MOVTi16 GPR:$src, 0xffff)>,
2079 Requires<[IsARM, HasV6T2]>;
2081 let Uses = [CPSR] in
2082 def RRX: PseudoInst<(outs GPR:$Rd), (ins GPR:$Rm), IIC_iMOVsi,
2083 [(set GPR:$Rd, (ARMrrx GPR:$Rm))]>, UnaryDP,
2086 // These aren't really mov instructions, but we have to define them this way
2087 // due to flag operands.
2089 let Defs = [CPSR] in {
2090 def MOVsrl_flag : PseudoInst<(outs GPR:$dst), (ins GPR:$src), IIC_iMOVsi,
2091 [(set GPR:$dst, (ARMsrl_flag GPR:$src))]>, UnaryDP,
2093 def MOVsra_flag : PseudoInst<(outs GPR:$dst), (ins GPR:$src), IIC_iMOVsi,
2094 [(set GPR:$dst, (ARMsra_flag GPR:$src))]>, UnaryDP,
2098 //===----------------------------------------------------------------------===//
2099 // Extend Instructions.
2104 defm SXTB : AI_ext_rrot<0b01101010,
2105 "sxtb", UnOpFrag<(sext_inreg node:$Src, i8)>>;
2106 defm SXTH : AI_ext_rrot<0b01101011,
2107 "sxth", UnOpFrag<(sext_inreg node:$Src, i16)>>;
2109 defm SXTAB : AI_exta_rrot<0b01101010,
2110 "sxtab", BinOpFrag<(add node:$LHS, (sext_inreg node:$RHS, i8))>>;
2111 defm SXTAH : AI_exta_rrot<0b01101011,
2112 "sxtah", BinOpFrag<(add node:$LHS, (sext_inreg node:$RHS,i16))>>;
2114 // For disassembly only
2115 defm SXTB16 : AI_ext_rrot_np<0b01101000, "sxtb16">;
2117 // For disassembly only
2118 defm SXTAB16 : AI_exta_rrot_np<0b01101000, "sxtab16">;
2122 let AddedComplexity = 16 in {
2123 defm UXTB : AI_ext_rrot<0b01101110,
2124 "uxtb" , UnOpFrag<(and node:$Src, 0x000000FF)>>;
2125 defm UXTH : AI_ext_rrot<0b01101111,
2126 "uxth" , UnOpFrag<(and node:$Src, 0x0000FFFF)>>;
2127 defm UXTB16 : AI_ext_rrot<0b01101100,
2128 "uxtb16", UnOpFrag<(and node:$Src, 0x00FF00FF)>>;
2130 // FIXME: This pattern incorrectly assumes the shl operator is a rotate.
2131 // The transformation should probably be done as a combiner action
2132 // instead so we can include a check for masking back in the upper
2133 // eight bits of the source into the lower eight bits of the result.
2134 //def : ARMV6Pat<(and (shl GPR:$Src, (i32 8)), 0xFF00FF),
2135 // (UXTB16r_rot GPR:$Src, 24)>;
2136 def : ARMV6Pat<(and (srl GPR:$Src, (i32 8)), 0xFF00FF),
2137 (UXTB16r_rot GPR:$Src, 8)>;
2139 defm UXTAB : AI_exta_rrot<0b01101110, "uxtab",
2140 BinOpFrag<(add node:$LHS, (and node:$RHS, 0x00FF))>>;
2141 defm UXTAH : AI_exta_rrot<0b01101111, "uxtah",
2142 BinOpFrag<(add node:$LHS, (and node:$RHS, 0xFFFF))>>;
2145 // This isn't safe in general, the add is two 16-bit units, not a 32-bit add.
2146 // For disassembly only
2147 defm UXTAB16 : AI_exta_rrot_np<0b01101100, "uxtab16">;
2150 def SBFX : I<(outs GPR:$Rd),
2151 (ins GPR:$Rn, imm0_31:$lsb, imm0_31_m1:$width),
2152 AddrMode1, Size4Bytes, IndexModeNone, DPFrm, IIC_iUNAsi,
2153 "sbfx", "\t$Rd, $Rn, $lsb, $width", "", []>,
2154 Requires<[IsARM, HasV6T2]> {
2159 let Inst{27-21} = 0b0111101;
2160 let Inst{6-4} = 0b101;
2161 let Inst{20-16} = width;
2162 let Inst{15-12} = Rd;
2163 let Inst{11-7} = lsb;
2167 def UBFX : I<(outs GPR:$Rd),
2168 (ins GPR:$Rn, imm0_31:$lsb, imm0_31_m1:$width),
2169 AddrMode1, Size4Bytes, IndexModeNone, DPFrm, IIC_iUNAsi,
2170 "ubfx", "\t$Rd, $Rn, $lsb, $width", "", []>,
2171 Requires<[IsARM, HasV6T2]> {
2176 let Inst{27-21} = 0b0111111;
2177 let Inst{6-4} = 0b101;
2178 let Inst{20-16} = width;
2179 let Inst{15-12} = Rd;
2180 let Inst{11-7} = lsb;
2184 //===----------------------------------------------------------------------===//
2185 // Arithmetic Instructions.
2188 defm ADD : AsI1_bin_irs<0b0100, "add",
2189 IIC_iALUi, IIC_iALUr, IIC_iALUsr,
2190 BinOpFrag<(add node:$LHS, node:$RHS)>, 1>;
2191 defm SUB : AsI1_bin_irs<0b0010, "sub",
2192 IIC_iALUi, IIC_iALUr, IIC_iALUsr,
2193 BinOpFrag<(sub node:$LHS, node:$RHS)>>;
2195 // ADD and SUB with 's' bit set.
2196 defm ADDS : AI1_bin_s_irs<0b0100, "adds",
2197 IIC_iALUi, IIC_iALUr, IIC_iALUsr,
2198 BinOpFrag<(addc node:$LHS, node:$RHS)>, 1>;
2199 defm SUBS : AI1_bin_s_irs<0b0010, "subs",
2200 IIC_iALUi, IIC_iALUr, IIC_iALUsr,
2201 BinOpFrag<(subc node:$LHS, node:$RHS)>>;
2203 defm ADC : AI1_adde_sube_irs<0b0101, "adc",
2204 BinOpFrag<(adde_dead_carry node:$LHS, node:$RHS)>, 1>;
2205 defm SBC : AI1_adde_sube_irs<0b0110, "sbc",
2206 BinOpFrag<(sube_dead_carry node:$LHS, node:$RHS)>>;
2208 // ADC and SUBC with 's' bit set.
2209 defm ADCS : AI1_adde_sube_s_irs<0b0101, "adcs",
2210 BinOpFrag<(adde_live_carry node:$LHS, node:$RHS)>, 1>;
2211 defm SBCS : AI1_adde_sube_s_irs<0b0110, "sbcs",
2212 BinOpFrag<(sube_live_carry node:$LHS, node:$RHS) >>;
2214 def RSBri : AsI1<0b0011, (outs GPR:$Rd), (ins GPR:$Rn, so_imm:$imm), DPFrm,
2215 IIC_iALUi, "rsb", "\t$Rd, $Rn, $imm",
2216 [(set GPR:$Rd, (sub so_imm:$imm, GPR:$Rn))]> {
2221 let Inst{15-12} = Rd;
2222 let Inst{19-16} = Rn;
2223 let Inst{11-0} = imm;
2226 // The reg/reg form is only defined for the disassembler; for codegen it is
2227 // equivalent to SUBrr.
2228 def RSBrr : AsI1<0b0011, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm), DPFrm,
2229 IIC_iALUr, "rsb", "\t$Rd, $Rn, $Rm",
2230 [/* For disassembly only; pattern left blank */]> {
2234 let Inst{11-4} = 0b00000000;
2237 let Inst{15-12} = Rd;
2238 let Inst{19-16} = Rn;
2241 def RSBrs : AsI1<0b0011, (outs GPR:$Rd), (ins GPR:$Rn, so_reg:$shift),
2242 DPSoRegFrm, IIC_iALUsr, "rsb", "\t$Rd, $Rn, $shift",
2243 [(set GPR:$Rd, (sub so_reg:$shift, GPR:$Rn))]> {
2248 let Inst{11-0} = shift;
2249 let Inst{15-12} = Rd;
2250 let Inst{19-16} = Rn;
2253 // RSB with 's' bit set.
2254 let isCodeGenOnly = 1, Defs = [CPSR] in {
2255 def RSBSri : AI1<0b0011, (outs GPR:$Rd), (ins GPR:$Rn, so_imm:$imm), DPFrm,
2256 IIC_iALUi, "rsbs", "\t$Rd, $Rn, $imm",
2257 [(set GPR:$Rd, (subc so_imm:$imm, GPR:$Rn))]> {
2263 let Inst{15-12} = Rd;
2264 let Inst{19-16} = Rn;
2265 let Inst{11-0} = imm;
2267 def RSBSrr : AI1<0b0011, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm), DPFrm,
2268 IIC_iALUr, "rsbs", "\t$Rd, $Rn, $Rm",
2269 [/* For disassembly only; pattern left blank */]> {
2273 let Inst{11-4} = 0b00000000;
2277 let Inst{15-12} = Rd;
2278 let Inst{19-16} = Rn;
2280 def RSBSrs : AI1<0b0011, (outs GPR:$Rd), (ins GPR:$Rn, so_reg:$shift),
2281 DPSoRegFrm, IIC_iALUsr, "rsbs", "\t$Rd, $Rn, $shift",
2282 [(set GPR:$Rd, (subc so_reg:$shift, GPR:$Rn))]> {
2288 let Inst{11-0} = shift;
2289 let Inst{15-12} = Rd;
2290 let Inst{19-16} = Rn;
2294 let Uses = [CPSR] in {
2295 def RSCri : AsI1<0b0111, (outs GPR:$Rd), (ins GPR:$Rn, so_imm:$imm),
2296 DPFrm, IIC_iALUi, "rsc", "\t$Rd, $Rn, $imm",
2297 [(set GPR:$Rd, (sube_dead_carry so_imm:$imm, GPR:$Rn))]>,
2303 let Inst{15-12} = Rd;
2304 let Inst{19-16} = Rn;
2305 let Inst{11-0} = imm;
2307 // The reg/reg form is only defined for the disassembler; for codegen it is
2308 // equivalent to SUBrr.
2309 def RSCrr : AsI1<0b0111, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm),
2310 DPFrm, IIC_iALUr, "rsc", "\t$Rd, $Rn, $Rm",
2311 [/* For disassembly only; pattern left blank */]> {
2315 let Inst{11-4} = 0b00000000;
2318 let Inst{15-12} = Rd;
2319 let Inst{19-16} = Rn;
2321 def RSCrs : AsI1<0b0111, (outs GPR:$Rd), (ins GPR:$Rn, so_reg:$shift),
2322 DPSoRegFrm, IIC_iALUsr, "rsc", "\t$Rd, $Rn, $shift",
2323 [(set GPR:$Rd, (sube_dead_carry so_reg:$shift, GPR:$Rn))]>,
2329 let Inst{11-0} = shift;
2330 let Inst{15-12} = Rd;
2331 let Inst{19-16} = Rn;
2335 // FIXME: Allow these to be predicated.
2336 let isCodeGenOnly = 1, Defs = [CPSR], Uses = [CPSR] in {
2337 def RSCSri : AXI1<0b0111, (outs GPR:$Rd), (ins GPR:$Rn, so_imm:$imm),
2338 DPFrm, IIC_iALUi, "rscs\t$Rd, $Rn, $imm",
2339 [(set GPR:$Rd, (sube_dead_carry so_imm:$imm, GPR:$Rn))]>,
2346 let Inst{15-12} = Rd;
2347 let Inst{19-16} = Rn;
2348 let Inst{11-0} = imm;
2350 def RSCSrs : AXI1<0b0111, (outs GPR:$Rd), (ins GPR:$Rn, so_reg:$shift),
2351 DPSoRegFrm, IIC_iALUsr, "rscs\t$Rd, $Rn, $shift",
2352 [(set GPR:$Rd, (sube_dead_carry so_reg:$shift, GPR:$Rn))]>,
2359 let Inst{11-0} = shift;
2360 let Inst{15-12} = Rd;
2361 let Inst{19-16} = Rn;
2365 // (sub X, imm) gets canonicalized to (add X, -imm). Match this form.
2366 // The assume-no-carry-in form uses the negation of the input since add/sub
2367 // assume opposite meanings of the carry flag (i.e., carry == !borrow).
2368 // See the definition of AddWithCarry() in the ARM ARM A2.2.1 for the gory
2370 def : ARMPat<(add GPR:$src, so_imm_neg:$imm),
2371 (SUBri GPR:$src, so_imm_neg:$imm)>;
2372 def : ARMPat<(addc GPR:$src, so_imm_neg:$imm),
2373 (SUBSri GPR:$src, so_imm_neg:$imm)>;
2374 // The with-carry-in form matches bitwise not instead of the negation.
2375 // Effectively, the inverse interpretation of the carry flag already accounts
2376 // for part of the negation.
2377 def : ARMPat<(adde GPR:$src, so_imm_not:$imm),
2378 (SBCri GPR:$src, so_imm_not:$imm)>;
2380 // Note: These are implemented in C++ code, because they have to generate
2381 // ADD/SUBrs instructions, which use a complex pattern that a xform function
2383 // (mul X, 2^n+1) -> (add (X << n), X)
2384 // (mul X, 2^n-1) -> (rsb X, (X << n))
2386 // ARM Arithmetic Instruction -- for disassembly only
2387 // GPR:$dst = GPR:$a op GPR:$b
2388 class AAI<bits<8> op27_20, bits<8> op11_4, string opc,
2389 list<dag> pattern = [/* For disassembly only; pattern left blank */],
2390 dag iops = (ins GPR:$Rn, GPR:$Rm), string asm = "\t$Rd, $Rn, $Rm">
2391 : AI<(outs GPR:$Rd), iops, DPFrm, IIC_iALUr, opc, asm, pattern> {
2395 let Inst{27-20} = op27_20;
2396 let Inst{11-4} = op11_4;
2397 let Inst{19-16} = Rn;
2398 let Inst{15-12} = Rd;
2402 // Saturating add/subtract -- for disassembly only
2404 def QADD : AAI<0b00010000, 0b00000101, "qadd",
2405 [(set GPR:$Rd, (int_arm_qadd GPR:$Rm, GPR:$Rn))],
2406 (ins GPR:$Rm, GPR:$Rn), "\t$Rd, $Rm, $Rn">;
2407 def QSUB : AAI<0b00010010, 0b00000101, "qsub",
2408 [(set GPR:$Rd, (int_arm_qsub GPR:$Rm, GPR:$Rn))],
2409 (ins GPR:$Rm, GPR:$Rn), "\t$Rd, $Rm, $Rn">;
2410 def QDADD : AAI<0b00010100, 0b00000101, "qdadd", [], (ins GPR:$Rm, GPR:$Rn),
2412 def QDSUB : AAI<0b00010110, 0b00000101, "qdsub", [], (ins GPR:$Rm, GPR:$Rn),
2415 def QADD16 : AAI<0b01100010, 0b11110001, "qadd16">;
2416 def QADD8 : AAI<0b01100010, 0b11111001, "qadd8">;
2417 def QASX : AAI<0b01100010, 0b11110011, "qasx">;
2418 def QSAX : AAI<0b01100010, 0b11110101, "qsax">;
2419 def QSUB16 : AAI<0b01100010, 0b11110111, "qsub16">;
2420 def QSUB8 : AAI<0b01100010, 0b11111111, "qsub8">;
2421 def UQADD16 : AAI<0b01100110, 0b11110001, "uqadd16">;
2422 def UQADD8 : AAI<0b01100110, 0b11111001, "uqadd8">;
2423 def UQASX : AAI<0b01100110, 0b11110011, "uqasx">;
2424 def UQSAX : AAI<0b01100110, 0b11110101, "uqsax">;
2425 def UQSUB16 : AAI<0b01100110, 0b11110111, "uqsub16">;
2426 def UQSUB8 : AAI<0b01100110, 0b11111111, "uqsub8">;
2428 // Signed/Unsigned add/subtract -- for disassembly only
2430 def SASX : AAI<0b01100001, 0b11110011, "sasx">;
2431 def SADD16 : AAI<0b01100001, 0b11110001, "sadd16">;
2432 def SADD8 : AAI<0b01100001, 0b11111001, "sadd8">;
2433 def SSAX : AAI<0b01100001, 0b11110101, "ssax">;
2434 def SSUB16 : AAI<0b01100001, 0b11110111, "ssub16">;
2435 def SSUB8 : AAI<0b01100001, 0b11111111, "ssub8">;
2436 def UASX : AAI<0b01100101, 0b11110011, "uasx">;
2437 def UADD16 : AAI<0b01100101, 0b11110001, "uadd16">;
2438 def UADD8 : AAI<0b01100101, 0b11111001, "uadd8">;
2439 def USAX : AAI<0b01100101, 0b11110101, "usax">;
2440 def USUB16 : AAI<0b01100101, 0b11110111, "usub16">;
2441 def USUB8 : AAI<0b01100101, 0b11111111, "usub8">;
2443 // Signed/Unsigned halving add/subtract -- for disassembly only
2445 def SHASX : AAI<0b01100011, 0b11110011, "shasx">;
2446 def SHADD16 : AAI<0b01100011, 0b11110001, "shadd16">;
2447 def SHADD8 : AAI<0b01100011, 0b11111001, "shadd8">;
2448 def SHSAX : AAI<0b01100011, 0b11110101, "shsax">;
2449 def SHSUB16 : AAI<0b01100011, 0b11110111, "shsub16">;
2450 def SHSUB8 : AAI<0b01100011, 0b11111111, "shsub8">;
2451 def UHASX : AAI<0b01100111, 0b11110011, "uhasx">;
2452 def UHADD16 : AAI<0b01100111, 0b11110001, "uhadd16">;
2453 def UHADD8 : AAI<0b01100111, 0b11111001, "uhadd8">;
2454 def UHSAX : AAI<0b01100111, 0b11110101, "uhsax">;
2455 def UHSUB16 : AAI<0b01100111, 0b11110111, "uhsub16">;
2456 def UHSUB8 : AAI<0b01100111, 0b11111111, "uhsub8">;
2458 // Unsigned Sum of Absolute Differences [and Accumulate] -- for disassembly only
2460 def USAD8 : AI<(outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm),
2461 MulFrm /* for convenience */, NoItinerary, "usad8",
2462 "\t$Rd, $Rn, $Rm", []>,
2463 Requires<[IsARM, HasV6]> {
2467 let Inst{27-20} = 0b01111000;
2468 let Inst{15-12} = 0b1111;
2469 let Inst{7-4} = 0b0001;
2470 let Inst{19-16} = Rd;
2471 let Inst{11-8} = Rm;
2474 def USADA8 : AI<(outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm, GPR:$Ra),
2475 MulFrm /* for convenience */, NoItinerary, "usada8",
2476 "\t$Rd, $Rn, $Rm, $Ra", []>,
2477 Requires<[IsARM, HasV6]> {
2482 let Inst{27-20} = 0b01111000;
2483 let Inst{7-4} = 0b0001;
2484 let Inst{19-16} = Rd;
2485 let Inst{15-12} = Ra;
2486 let Inst{11-8} = Rm;
2490 // Signed/Unsigned saturate -- for disassembly only
2492 def SSAT : AI<(outs GPR:$Rd), (ins i32imm:$sat_imm, GPR:$a, shift_imm:$sh),
2493 SatFrm, NoItinerary, "ssat", "\t$Rd, $sat_imm, $a$sh",
2494 [/* For disassembly only; pattern left blank */]> {
2499 let Inst{27-21} = 0b0110101;
2500 let Inst{5-4} = 0b01;
2501 let Inst{20-16} = sat_imm;
2502 let Inst{15-12} = Rd;
2503 let Inst{11-7} = sh{7-3};
2504 let Inst{6} = sh{0};
2508 def SSAT16 : AI<(outs GPR:$Rd), (ins i32imm:$sat_imm, GPR:$Rn), SatFrm,
2509 NoItinerary, "ssat16", "\t$Rd, $sat_imm, $Rn",
2510 [/* For disassembly only; pattern left blank */]> {
2514 let Inst{27-20} = 0b01101010;
2515 let Inst{11-4} = 0b11110011;
2516 let Inst{15-12} = Rd;
2517 let Inst{19-16} = sat_imm;
2521 def USAT : AI<(outs GPR:$Rd), (ins i32imm:$sat_imm, GPR:$a, shift_imm:$sh),
2522 SatFrm, NoItinerary, "usat", "\t$Rd, $sat_imm, $a$sh",
2523 [/* For disassembly only; pattern left blank */]> {
2528 let Inst{27-21} = 0b0110111;
2529 let Inst{5-4} = 0b01;
2530 let Inst{15-12} = Rd;
2531 let Inst{11-7} = sh{7-3};
2532 let Inst{6} = sh{0};
2533 let Inst{20-16} = sat_imm;
2537 def USAT16 : AI<(outs GPR:$Rd), (ins i32imm:$sat_imm, GPR:$a), SatFrm,
2538 NoItinerary, "usat16", "\t$Rd, $sat_imm, $a",
2539 [/* For disassembly only; pattern left blank */]> {
2543 let Inst{27-20} = 0b01101110;
2544 let Inst{11-4} = 0b11110011;
2545 let Inst{15-12} = Rd;
2546 let Inst{19-16} = sat_imm;
2550 def : ARMV6Pat<(int_arm_ssat GPR:$a, imm:$pos), (SSAT imm:$pos, GPR:$a, 0)>;
2551 def : ARMV6Pat<(int_arm_usat GPR:$a, imm:$pos), (USAT imm:$pos, GPR:$a, 0)>;
2553 //===----------------------------------------------------------------------===//
2554 // Bitwise Instructions.
2557 defm AND : AsI1_bin_irs<0b0000, "and",
2558 IIC_iBITi, IIC_iBITr, IIC_iBITsr,
2559 BinOpFrag<(and node:$LHS, node:$RHS)>, 1>;
2560 defm ORR : AsI1_bin_irs<0b1100, "orr",
2561 IIC_iBITi, IIC_iBITr, IIC_iBITsr,
2562 BinOpFrag<(or node:$LHS, node:$RHS)>, 1>;
2563 defm EOR : AsI1_bin_irs<0b0001, "eor",
2564 IIC_iBITi, IIC_iBITr, IIC_iBITsr,
2565 BinOpFrag<(xor node:$LHS, node:$RHS)>, 1>;
2566 defm BIC : AsI1_bin_irs<0b1110, "bic",
2567 IIC_iBITi, IIC_iBITr, IIC_iBITsr,
2568 BinOpFrag<(and node:$LHS, (not node:$RHS))>>;
2570 def BFC : I<(outs GPR:$Rd), (ins GPR:$src, bf_inv_mask_imm:$imm),
2571 AddrMode1, Size4Bytes, IndexModeNone, DPFrm, IIC_iUNAsi,
2572 "bfc", "\t$Rd, $imm", "$src = $Rd",
2573 [(set GPR:$Rd, (and GPR:$src, bf_inv_mask_imm:$imm))]>,
2574 Requires<[IsARM, HasV6T2]> {
2577 let Inst{27-21} = 0b0111110;
2578 let Inst{6-0} = 0b0011111;
2579 let Inst{15-12} = Rd;
2580 let Inst{11-7} = imm{4-0}; // lsb
2581 let Inst{20-16} = imm{9-5}; // width
2584 // A8.6.18 BFI - Bitfield insert (Encoding A1)
2585 def BFI : I<(outs GPR:$Rd), (ins GPR:$src, GPR:$Rn, bf_inv_mask_imm:$imm),
2586 AddrMode1, Size4Bytes, IndexModeNone, DPFrm, IIC_iUNAsi,
2587 "bfi", "\t$Rd, $Rn, $imm", "$src = $Rd",
2588 [(set GPR:$Rd, (ARMbfi GPR:$src, GPR:$Rn,
2589 bf_inv_mask_imm:$imm))]>,
2590 Requires<[IsARM, HasV6T2]> {
2594 let Inst{27-21} = 0b0111110;
2595 let Inst{6-4} = 0b001; // Rn: Inst{3-0} != 15
2596 let Inst{15-12} = Rd;
2597 let Inst{11-7} = imm{4-0}; // lsb
2598 let Inst{20-16} = imm{9-5}; // width
2602 // GNU as only supports this form of bfi (w/ 4 arguments)
2603 let isAsmParserOnly = 1 in
2604 def BFI4p : I<(outs GPR:$Rd), (ins GPR:$src, GPR:$Rn,
2605 lsb_pos_imm:$lsb, width_imm:$width),
2606 AddrMode1, Size4Bytes, IndexModeNone, DPFrm, IIC_iUNAsi,
2607 "bfi", "\t$Rd, $Rn, $lsb, $width", "$src = $Rd",
2608 []>, Requires<[IsARM, HasV6T2]> {
2613 let Inst{27-21} = 0b0111110;
2614 let Inst{6-4} = 0b001; // Rn: Inst{3-0} != 15
2615 let Inst{15-12} = Rd;
2616 let Inst{11-7} = lsb;
2617 let Inst{20-16} = width; // Custom encoder => lsb+width-1
2621 def MVNr : AsI1<0b1111, (outs GPR:$Rd), (ins GPR:$Rm), DPFrm, IIC_iMVNr,
2622 "mvn", "\t$Rd, $Rm",
2623 [(set GPR:$Rd, (not GPR:$Rm))]>, UnaryDP {
2627 let Inst{19-16} = 0b0000;
2628 let Inst{11-4} = 0b00000000;
2629 let Inst{15-12} = Rd;
2632 def MVNs : AsI1<0b1111, (outs GPR:$Rd), (ins so_reg:$shift), DPSoRegFrm,
2633 IIC_iMVNsr, "mvn", "\t$Rd, $shift",
2634 [(set GPR:$Rd, (not so_reg:$shift))]>, UnaryDP {
2638 let Inst{19-16} = 0b0000;
2639 let Inst{15-12} = Rd;
2640 let Inst{11-0} = shift;
2642 let isReMaterializable = 1, isAsCheapAsAMove = 1, isMoveImm = 1 in
2643 def MVNi : AsI1<0b1111, (outs GPR:$Rd), (ins so_imm:$imm), DPFrm,
2644 IIC_iMVNi, "mvn", "\t$Rd, $imm",
2645 [(set GPR:$Rd, so_imm_not:$imm)]>,UnaryDP {
2649 let Inst{19-16} = 0b0000;
2650 let Inst{15-12} = Rd;
2651 let Inst{11-0} = imm;
2654 def : ARMPat<(and GPR:$src, so_imm_not:$imm),
2655 (BICri GPR:$src, so_imm_not:$imm)>;
2657 //===----------------------------------------------------------------------===//
2658 // Multiply Instructions.
2660 class AsMul1I32<bits<7> opcod, dag oops, dag iops, InstrItinClass itin,
2661 string opc, string asm, list<dag> pattern>
2662 : AsMul1I<opcod, oops, iops, itin, opc, asm, pattern> {
2666 let Inst{19-16} = Rd;
2667 let Inst{11-8} = Rm;
2670 class AsMul1I64<bits<7> opcod, dag oops, dag iops, InstrItinClass itin,
2671 string opc, string asm, list<dag> pattern>
2672 : AsMul1I<opcod, oops, iops, itin, opc, asm, pattern> {
2677 let Inst{19-16} = RdHi;
2678 let Inst{15-12} = RdLo;
2679 let Inst{11-8} = Rm;
2683 let isCommutable = 1 in {
2684 let Constraints = "@earlyclobber $Rd" in
2685 def MULv5: ARMPseudoInst<(outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm,
2686 pred:$p, cc_out:$s),
2687 Size4Bytes, IIC_iMUL32,
2688 [(set GPR:$Rd, (mul GPR:$Rn, GPR:$Rm))]>,
2689 Requires<[IsARM, NoV6]>;
2691 def MUL : AsMul1I32<0b0000000, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm),
2692 IIC_iMUL32, "mul", "\t$Rd, $Rn, $Rm",
2693 [(set GPR:$Rd, (mul GPR:$Rn, GPR:$Rm))]>,
2694 Requires<[IsARM, HasV6]> {
2695 let Inst{15-12} = 0b0000;
2699 let Constraints = "@earlyclobber $Rd" in
2700 def MLAv5: ARMPseudoInst<(outs GPR:$Rd),
2701 (ins GPR:$Rn, GPR:$Rm, GPR:$Ra, pred:$p, cc_out:$s),
2702 Size4Bytes, IIC_iMAC32,
2703 [(set GPR:$Rd, (add (mul GPR:$Rn, GPR:$Rm), GPR:$Ra))]>,
2704 Requires<[IsARM, NoV6]> {
2706 let Inst{15-12} = Ra;
2708 def MLA : AsMul1I32<0b0000001, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm, GPR:$Ra),
2709 IIC_iMAC32, "mla", "\t$Rd, $Rn, $Rm, $Ra",
2710 [(set GPR:$Rd, (add (mul GPR:$Rn, GPR:$Rm), GPR:$Ra))]>,
2711 Requires<[IsARM, HasV6]> {
2713 let Inst{15-12} = Ra;
2716 def MLS : AMul1I<0b0000011, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm, GPR:$Ra),
2717 IIC_iMAC32, "mls", "\t$Rd, $Rn, $Rm, $Ra",
2718 [(set GPR:$Rd, (sub GPR:$Ra, (mul GPR:$Rn, GPR:$Rm)))]>,
2719 Requires<[IsARM, HasV6T2]> {
2724 let Inst{19-16} = Rd;
2725 let Inst{15-12} = Ra;
2726 let Inst{11-8} = Rm;
2730 // Extra precision multiplies with low / high results
2732 let neverHasSideEffects = 1 in {
2733 let isCommutable = 1 in {
2734 let Constraints = "@earlyclobber $RdLo,@earlyclobber $RdHi" in {
2735 def SMULLv5 : ARMPseudoInst<(outs GPR:$RdLo, GPR:$RdHi),
2736 (ins GPR:$Rn, GPR:$Rm, pred:$p, cc_out:$s),
2737 Size4Bytes, IIC_iMUL64, []>,
2738 Requires<[IsARM, NoV6]>;
2740 def UMULLv5 : ARMPseudoInst<(outs GPR:$RdLo, GPR:$RdHi),
2741 (ins GPR:$Rn, GPR:$Rm, pred:$p, cc_out:$s),
2742 Size4Bytes, IIC_iMUL64, []>,
2743 Requires<[IsARM, NoV6]>;
2746 def SMULL : AsMul1I64<0b0000110, (outs GPR:$RdLo, GPR:$RdHi),
2747 (ins GPR:$Rn, GPR:$Rm), IIC_iMUL64,
2748 "smull", "\t$RdLo, $RdHi, $Rn, $Rm", []>,
2749 Requires<[IsARM, HasV6]>;
2751 def UMULL : AsMul1I64<0b0000100, (outs GPR:$RdLo, GPR:$RdHi),
2752 (ins GPR:$Rn, GPR:$Rm), IIC_iMUL64,
2753 "umull", "\t$RdLo, $RdHi, $Rn, $Rm", []>,
2754 Requires<[IsARM, HasV6]>;
2757 // Multiply + accumulate
2758 let Constraints = "@earlyclobber $RdLo,@earlyclobber $RdHi" in {
2759 def SMLALv5 : ARMPseudoInst<(outs GPR:$RdLo, GPR:$RdHi),
2760 (ins GPR:$Rn, GPR:$Rm, pred:$p, cc_out:$s),
2761 Size4Bytes, IIC_iMAC64, []>,
2762 Requires<[IsARM, NoV6]>;
2763 def UMLALv5 : ARMPseudoInst<(outs GPR:$RdLo, GPR:$RdHi),
2764 (ins GPR:$Rn, GPR:$Rm, pred:$p, cc_out:$s),
2765 Size4Bytes, IIC_iMAC64, []>,
2766 Requires<[IsARM, NoV6]>;
2767 def UMAALv5 : ARMPseudoInst<(outs GPR:$RdLo, GPR:$RdHi),
2768 (ins GPR:$Rn, GPR:$Rm, pred:$p, cc_out:$s),
2769 Size4Bytes, IIC_iMAC64, []>,
2770 Requires<[IsARM, NoV6]>;
2774 def SMLAL : AsMul1I64<0b0000111, (outs GPR:$RdLo, GPR:$RdHi),
2775 (ins GPR:$Rn, GPR:$Rm), IIC_iMAC64,
2776 "smlal", "\t$RdLo, $RdHi, $Rn, $Rm", []>,
2777 Requires<[IsARM, HasV6]>;
2778 def UMLAL : AsMul1I64<0b0000101, (outs GPR:$RdLo, GPR:$RdHi),
2779 (ins GPR:$Rn, GPR:$Rm), IIC_iMAC64,
2780 "umlal", "\t$RdLo, $RdHi, $Rn, $Rm", []>,
2781 Requires<[IsARM, HasV6]>;
2783 def UMAAL : AMul1I <0b0000010, (outs GPR:$RdLo, GPR:$RdHi),
2784 (ins GPR:$Rn, GPR:$Rm), IIC_iMAC64,
2785 "umaal", "\t$RdLo, $RdHi, $Rn, $Rm", []>,
2786 Requires<[IsARM, HasV6]> {
2791 let Inst{19-16} = RdLo;
2792 let Inst{15-12} = RdHi;
2793 let Inst{11-8} = Rm;
2796 } // neverHasSideEffects
2798 // Most significant word multiply
2799 def SMMUL : AMul2I <0b0111010, 0b0001, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm),
2800 IIC_iMUL32, "smmul", "\t$Rd, $Rn, $Rm",
2801 [(set GPR:$Rd, (mulhs GPR:$Rn, GPR:$Rm))]>,
2802 Requires<[IsARM, HasV6]> {
2803 let Inst{15-12} = 0b1111;
2806 def SMMULR : AMul2I <0b0111010, 0b0011, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm),
2807 IIC_iMUL32, "smmulr", "\t$Rd, $Rn, $Rm",
2808 [/* For disassembly only; pattern left blank */]>,
2809 Requires<[IsARM, HasV6]> {
2810 let Inst{15-12} = 0b1111;
2813 def SMMLA : AMul2Ia <0b0111010, 0b0001, (outs GPR:$Rd),
2814 (ins GPR:$Rn, GPR:$Rm, GPR:$Ra),
2815 IIC_iMAC32, "smmla", "\t$Rd, $Rn, $Rm, $Ra",
2816 [(set GPR:$Rd, (add (mulhs GPR:$Rn, GPR:$Rm), GPR:$Ra))]>,
2817 Requires<[IsARM, HasV6]>;
2819 def SMMLAR : AMul2Ia <0b0111010, 0b0011, (outs GPR:$Rd),
2820 (ins GPR:$Rn, GPR:$Rm, GPR:$Ra),
2821 IIC_iMAC32, "smmlar", "\t$Rd, $Rn, $Rm, $Ra",
2822 [/* For disassembly only; pattern left blank */]>,
2823 Requires<[IsARM, HasV6]>;
2825 def SMMLS : AMul2Ia <0b0111010, 0b1101, (outs GPR:$Rd),
2826 (ins GPR:$Rn, GPR:$Rm, GPR:$Ra),
2827 IIC_iMAC32, "smmls", "\t$Rd, $Rn, $Rm, $Ra",
2828 [(set GPR:$Rd, (sub GPR:$Ra, (mulhs GPR:$Rn, GPR:$Rm)))]>,
2829 Requires<[IsARM, HasV6]>;
2831 def SMMLSR : AMul2Ia <0b0111010, 0b1111, (outs GPR:$Rd),
2832 (ins GPR:$Rn, GPR:$Rm, GPR:$Ra),
2833 IIC_iMAC32, "smmlsr", "\t$Rd, $Rn, $Rm, $Ra",
2834 [/* For disassembly only; pattern left blank */]>,
2835 Requires<[IsARM, HasV6]>;
2837 multiclass AI_smul<string opc, PatFrag opnode> {
2838 def BB : AMulxyI<0b0001011, 0b00, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm),
2839 IIC_iMUL16, !strconcat(opc, "bb"), "\t$Rd, $Rn, $Rm",
2840 [(set GPR:$Rd, (opnode (sext_inreg GPR:$Rn, i16),
2841 (sext_inreg GPR:$Rm, i16)))]>,
2842 Requires<[IsARM, HasV5TE]>;
2844 def BT : AMulxyI<0b0001011, 0b10, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm),
2845 IIC_iMUL16, !strconcat(opc, "bt"), "\t$Rd, $Rn, $Rm",
2846 [(set GPR:$Rd, (opnode (sext_inreg GPR:$Rn, i16),
2847 (sra GPR:$Rm, (i32 16))))]>,
2848 Requires<[IsARM, HasV5TE]>;
2850 def TB : AMulxyI<0b0001011, 0b01, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm),
2851 IIC_iMUL16, !strconcat(opc, "tb"), "\t$Rd, $Rn, $Rm",
2852 [(set GPR:$Rd, (opnode (sra GPR:$Rn, (i32 16)),
2853 (sext_inreg GPR:$Rm, i16)))]>,
2854 Requires<[IsARM, HasV5TE]>;
2856 def TT : AMulxyI<0b0001011, 0b11, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm),
2857 IIC_iMUL16, !strconcat(opc, "tt"), "\t$Rd, $Rn, $Rm",
2858 [(set GPR:$Rd, (opnode (sra GPR:$Rn, (i32 16)),
2859 (sra GPR:$Rm, (i32 16))))]>,
2860 Requires<[IsARM, HasV5TE]>;
2862 def WB : AMulxyI<0b0001001, 0b01, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm),
2863 IIC_iMUL16, !strconcat(opc, "wb"), "\t$Rd, $Rn, $Rm",
2864 [(set GPR:$Rd, (sra (opnode GPR:$Rn,
2865 (sext_inreg GPR:$Rm, i16)), (i32 16)))]>,
2866 Requires<[IsARM, HasV5TE]>;
2868 def WT : AMulxyI<0b0001001, 0b11, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm),
2869 IIC_iMUL16, !strconcat(opc, "wt"), "\t$Rd, $Rn, $Rm",
2870 [(set GPR:$Rd, (sra (opnode GPR:$Rn,
2871 (sra GPR:$Rm, (i32 16))), (i32 16)))]>,
2872 Requires<[IsARM, HasV5TE]>;
2876 multiclass AI_smla<string opc, PatFrag opnode> {
2877 def BB : AMulxyIa<0b0001000, 0b00, (outs GPR:$Rd),
2878 (ins GPR:$Rn, GPR:$Rm, GPR:$Ra),
2879 IIC_iMAC16, !strconcat(opc, "bb"), "\t$Rd, $Rn, $Rm, $Ra",
2880 [(set GPR:$Rd, (add GPR:$Ra,
2881 (opnode (sext_inreg GPR:$Rn, i16),
2882 (sext_inreg GPR:$Rm, i16))))]>,
2883 Requires<[IsARM, HasV5TE]>;
2885 def BT : AMulxyIa<0b0001000, 0b10, (outs GPR:$Rd),
2886 (ins GPR:$Rn, GPR:$Rm, GPR:$Ra),
2887 IIC_iMAC16, !strconcat(opc, "bt"), "\t$Rd, $Rn, $Rm, $Ra",
2888 [(set GPR:$Rd, (add GPR:$Ra, (opnode (sext_inreg GPR:$Rn, i16),
2889 (sra GPR:$Rm, (i32 16)))))]>,
2890 Requires<[IsARM, HasV5TE]>;
2892 def TB : AMulxyIa<0b0001000, 0b01, (outs GPR:$Rd),
2893 (ins GPR:$Rn, GPR:$Rm, GPR:$Ra),
2894 IIC_iMAC16, !strconcat(opc, "tb"), "\t$Rd, $Rn, $Rm, $Ra",
2895 [(set GPR:$Rd, (add GPR:$Ra, (opnode (sra GPR:$Rn, (i32 16)),
2896 (sext_inreg GPR:$Rm, i16))))]>,
2897 Requires<[IsARM, HasV5TE]>;
2899 def TT : AMulxyIa<0b0001000, 0b11, (outs GPR:$Rd),
2900 (ins GPR:$Rn, GPR:$Rm, GPR:$Ra),
2901 IIC_iMAC16, !strconcat(opc, "tt"), "\t$Rd, $Rn, $Rm, $Ra",
2902 [(set GPR:$Rd, (add GPR:$Ra, (opnode (sra GPR:$Rn, (i32 16)),
2903 (sra GPR:$Rm, (i32 16)))))]>,
2904 Requires<[IsARM, HasV5TE]>;
2906 def WB : AMulxyIa<0b0001001, 0b00, (outs GPR:$Rd),
2907 (ins GPR:$Rn, GPR:$Rm, GPR:$Ra),
2908 IIC_iMAC16, !strconcat(opc, "wb"), "\t$Rd, $Rn, $Rm, $Ra",
2909 [(set GPR:$Rd, (add GPR:$Ra, (sra (opnode GPR:$Rn,
2910 (sext_inreg GPR:$Rm, i16)), (i32 16))))]>,
2911 Requires<[IsARM, HasV5TE]>;
2913 def WT : AMulxyIa<0b0001001, 0b10, (outs GPR:$Rd),
2914 (ins GPR:$Rn, GPR:$Rm, GPR:$Ra),
2915 IIC_iMAC16, !strconcat(opc, "wt"), "\t$Rd, $Rn, $Rm, $Ra",
2916 [(set GPR:$Rd, (add GPR:$Ra, (sra (opnode GPR:$Rn,
2917 (sra GPR:$Rm, (i32 16))), (i32 16))))]>,
2918 Requires<[IsARM, HasV5TE]>;
2921 defm SMUL : AI_smul<"smul", BinOpFrag<(mul node:$LHS, node:$RHS)>>;
2922 defm SMLA : AI_smla<"smla", BinOpFrag<(mul node:$LHS, node:$RHS)>>;
2924 // Halfword multiply accumulate long: SMLAL<x><y> -- for disassembly only
2925 def SMLALBB : AMulxyI64<0b0001010, 0b00, (outs GPR:$RdLo, GPR:$RdHi),
2926 (ins GPR:$Rn, GPR:$Rm),
2927 IIC_iMAC64, "smlalbb", "\t$RdLo, $RdHi, $Rn, $Rm",
2928 [/* For disassembly only; pattern left blank */]>,
2929 Requires<[IsARM, HasV5TE]>;
2931 def SMLALBT : AMulxyI64<0b0001010, 0b10, (outs GPR:$RdLo, GPR:$RdHi),
2932 (ins GPR:$Rn, GPR:$Rm),
2933 IIC_iMAC64, "smlalbt", "\t$RdLo, $RdHi, $Rn, $Rm",
2934 [/* For disassembly only; pattern left blank */]>,
2935 Requires<[IsARM, HasV5TE]>;
2937 def SMLALTB : AMulxyI64<0b0001010, 0b01, (outs GPR:$RdLo, GPR:$RdHi),
2938 (ins GPR:$Rn, GPR:$Rm),
2939 IIC_iMAC64, "smlaltb", "\t$RdLo, $RdHi, $Rn, $Rm",
2940 [/* For disassembly only; pattern left blank */]>,
2941 Requires<[IsARM, HasV5TE]>;
2943 def SMLALTT : AMulxyI64<0b0001010, 0b11, (outs GPR:$RdLo, GPR:$RdHi),
2944 (ins GPR:$Rn, GPR:$Rm),
2945 IIC_iMAC64, "smlaltt", "\t$RdLo, $RdHi, $Rn, $Rm",
2946 [/* For disassembly only; pattern left blank */]>,
2947 Requires<[IsARM, HasV5TE]>;
2949 // Helper class for AI_smld -- for disassembly only
2950 class AMulDualIbase<bit long, bit sub, bit swap, dag oops, dag iops,
2951 InstrItinClass itin, string opc, string asm>
2952 : AI<oops, iops, MulFrm, itin, opc, asm, []>, Requires<[IsARM, HasV6]> {
2959 let Inst{21-20} = 0b00;
2960 let Inst{22} = long;
2961 let Inst{27-23} = 0b01110;
2962 let Inst{11-8} = Rm;
2965 class AMulDualI<bit long, bit sub, bit swap, dag oops, dag iops,
2966 InstrItinClass itin, string opc, string asm>
2967 : AMulDualIbase<long, sub, swap, oops, iops, itin, opc, asm> {
2969 let Inst{15-12} = 0b1111;
2970 let Inst{19-16} = Rd;
2972 class AMulDualIa<bit long, bit sub, bit swap, dag oops, dag iops,
2973 InstrItinClass itin, string opc, string asm>
2974 : AMulDualIbase<long, sub, swap, oops, iops, itin, opc, asm> {
2976 let Inst{15-12} = Ra;
2978 class AMulDualI64<bit long, bit sub, bit swap, dag oops, dag iops,
2979 InstrItinClass itin, string opc, string asm>
2980 : AMulDualIbase<long, sub, swap, oops, iops, itin, opc, asm> {
2983 let Inst{19-16} = RdHi;
2984 let Inst{15-12} = RdLo;
2987 multiclass AI_smld<bit sub, string opc> {
2989 def D : AMulDualIa<0, sub, 0, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm, GPR:$Ra),
2990 NoItinerary, !strconcat(opc, "d"), "\t$Rd, $Rn, $Rm, $Ra">;
2992 def DX: AMulDualIa<0, sub, 1, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm, GPR:$Ra),
2993 NoItinerary, !strconcat(opc, "dx"), "\t$Rd, $Rn, $Rm, $Ra">;
2995 def LD: AMulDualI64<1, sub, 0, (outs GPR:$RdLo,GPR:$RdHi),
2996 (ins GPR:$Rn, GPR:$Rm), NoItinerary,
2997 !strconcat(opc, "ld"), "\t$RdLo, $RdHi, $Rn, $Rm">;
2999 def LDX : AMulDualI64<1, sub, 1, (outs GPR:$RdLo,GPR:$RdHi),
3000 (ins GPR:$Rn, GPR:$Rm), NoItinerary,
3001 !strconcat(opc, "ldx"),"\t$RdLo, $RdHi, $Rn, $Rm">;
3005 defm SMLA : AI_smld<0, "smla">;
3006 defm SMLS : AI_smld<1, "smls">;
3008 multiclass AI_sdml<bit sub, string opc> {
3010 def D : AMulDualI<0, sub, 0, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm),
3011 NoItinerary, !strconcat(opc, "d"), "\t$Rd, $Rn, $Rm">;
3012 def DX : AMulDualI<0, sub, 1, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm),
3013 NoItinerary, !strconcat(opc, "dx"), "\t$Rd, $Rn, $Rm">;
3016 defm SMUA : AI_sdml<0, "smua">;
3017 defm SMUS : AI_sdml<1, "smus">;
3019 //===----------------------------------------------------------------------===//
3020 // Misc. Arithmetic Instructions.
3023 def CLZ : AMiscA1I<0b000010110, 0b0001, (outs GPR:$Rd), (ins GPR:$Rm),
3024 IIC_iUNAr, "clz", "\t$Rd, $Rm",
3025 [(set GPR:$Rd, (ctlz GPR:$Rm))]>, Requires<[IsARM, HasV5T]>;
3027 def RBIT : AMiscA1I<0b01101111, 0b0011, (outs GPR:$Rd), (ins GPR:$Rm),
3028 IIC_iUNAr, "rbit", "\t$Rd, $Rm",
3029 [(set GPR:$Rd, (ARMrbit GPR:$Rm))]>,
3030 Requires<[IsARM, HasV6T2]>;
3032 def REV : AMiscA1I<0b01101011, 0b0011, (outs GPR:$Rd), (ins GPR:$Rm),
3033 IIC_iUNAr, "rev", "\t$Rd, $Rm",
3034 [(set GPR:$Rd, (bswap GPR:$Rm))]>, Requires<[IsARM, HasV6]>;
3036 def REV16 : AMiscA1I<0b01101011, 0b1011, (outs GPR:$Rd), (ins GPR:$Rm),
3037 IIC_iUNAr, "rev16", "\t$Rd, $Rm",
3039 (or (and (srl GPR:$Rm, (i32 8)), 0xFF),
3040 (or (and (shl GPR:$Rm, (i32 8)), 0xFF00),
3041 (or (and (srl GPR:$Rm, (i32 8)), 0xFF0000),
3042 (and (shl GPR:$Rm, (i32 8)), 0xFF000000)))))]>,
3043 Requires<[IsARM, HasV6]>;
3045 def REVSH : AMiscA1I<0b01101111, 0b1011, (outs GPR:$Rd), (ins GPR:$Rm),
3046 IIC_iUNAr, "revsh", "\t$Rd, $Rm",
3049 (or (srl GPR:$Rm, (i32 8)),
3050 (shl GPR:$Rm, (i32 8))), i16))]>,
3051 Requires<[IsARM, HasV6]>;
3053 def : ARMV6Pat<(sext_inreg (or (srl (and GPR:$Rm, 0xFF00), (i32 8)),
3054 (shl GPR:$Rm, (i32 8))), i16),
3057 // Need the AddedComplexity or else MOVs + REV would be chosen.
3058 let AddedComplexity = 5 in
3059 def : ARMV6Pat<(sra (bswap GPR:$Rm), (i32 16)), (REVSH GPR:$Rm)>;
3061 def lsl_shift_imm : SDNodeXForm<imm, [{
3062 unsigned Sh = ARM_AM::getSORegOpc(ARM_AM::lsl, N->getZExtValue());
3063 return CurDAG->getTargetConstant(Sh, MVT::i32);
3066 def lsl_amt : PatLeaf<(i32 imm), [{
3067 return (N->getZExtValue() < 32);
3070 def PKHBT : APKHI<0b01101000, 0, (outs GPR:$Rd),
3071 (ins GPR:$Rn, GPR:$Rm, shift_imm:$sh),
3072 IIC_iALUsi, "pkhbt", "\t$Rd, $Rn, $Rm$sh",
3073 [(set GPR:$Rd, (or (and GPR:$Rn, 0xFFFF),
3074 (and (shl GPR:$Rm, lsl_amt:$sh),
3076 Requires<[IsARM, HasV6]>;
3078 // Alternate cases for PKHBT where identities eliminate some nodes.
3079 def : ARMV6Pat<(or (and GPR:$Rn, 0xFFFF), (and GPR:$Rm, 0xFFFF0000)),
3080 (PKHBT GPR:$Rn, GPR:$Rm, 0)>;
3081 def : ARMV6Pat<(or (and GPR:$Rn, 0xFFFF), (shl GPR:$Rm, imm16_31:$sh)),
3082 (PKHBT GPR:$Rn, GPR:$Rm, (lsl_shift_imm imm16_31:$sh))>;
3084 def asr_shift_imm : SDNodeXForm<imm, [{
3085 unsigned Sh = ARM_AM::getSORegOpc(ARM_AM::asr, N->getZExtValue());
3086 return CurDAG->getTargetConstant(Sh, MVT::i32);
3089 def asr_amt : PatLeaf<(i32 imm), [{
3090 return (N->getZExtValue() <= 32);
3093 // Note: Shifts of 1-15 bits will be transformed to srl instead of sra and
3094 // will match the pattern below.
3095 def PKHTB : APKHI<0b01101000, 1, (outs GPR:$Rd),
3096 (ins GPR:$Rn, GPR:$Rm, shift_imm:$sh),
3097 IIC_iBITsi, "pkhtb", "\t$Rd, $Rn, $Rm$sh",
3098 [(set GPR:$Rd, (or (and GPR:$Rn, 0xFFFF0000),
3099 (and (sra GPR:$Rm, asr_amt:$sh),
3101 Requires<[IsARM, HasV6]>;
3103 // Alternate cases for PKHTB where identities eliminate some nodes. Note that
3104 // a shift amount of 0 is *not legal* here, it is PKHBT instead.
3105 def : ARMV6Pat<(or (and GPR:$src1, 0xFFFF0000), (srl GPR:$src2, imm16_31:$sh)),
3106 (PKHTB GPR:$src1, GPR:$src2, (asr_shift_imm imm16_31:$sh))>;
3107 def : ARMV6Pat<(or (and GPR:$src1, 0xFFFF0000),
3108 (and (srl GPR:$src2, imm1_15:$sh), 0xFFFF)),
3109 (PKHTB GPR:$src1, GPR:$src2, (asr_shift_imm imm1_15:$sh))>;
3111 //===----------------------------------------------------------------------===//
3112 // Comparison Instructions...
3115 defm CMP : AI1_cmp_irs<0b1010, "cmp",
3116 IIC_iCMPi, IIC_iCMPr, IIC_iCMPsr,
3117 BinOpFrag<(ARMcmp node:$LHS, node:$RHS)>>;
3119 // ARMcmpZ can re-use the above instruction definitions.
3120 def : ARMPat<(ARMcmpZ GPR:$src, so_imm:$imm),
3121 (CMPri GPR:$src, so_imm:$imm)>;
3122 def : ARMPat<(ARMcmpZ GPR:$src, GPR:$rhs),
3123 (CMPrr GPR:$src, GPR:$rhs)>;
3124 def : ARMPat<(ARMcmpZ GPR:$src, so_reg:$rhs),
3125 (CMPrs GPR:$src, so_reg:$rhs)>;
3127 // FIXME: We have to be careful when using the CMN instruction and comparison
3128 // with 0. One would expect these two pieces of code should give identical
3144 // However, the CMN gives the *opposite* result when r1 is 0. This is because
3145 // the carry flag is set in the CMP case but not in the CMN case. In short, the
3146 // CMP instruction doesn't perform a truncate of the (logical) NOT of 0 plus the
3147 // value of r0 and the carry bit (because the "carry bit" parameter to
3148 // AddWithCarry is defined as 1 in this case, the carry flag will always be set
3149 // when r0 >= 0). The CMN instruction doesn't perform a NOT of 0 so there is
3150 // never a "carry" when this AddWithCarry is performed (because the "carry bit"
3151 // parameter to AddWithCarry is defined as 0).
3153 // When x is 0 and unsigned:
3157 // ~x + 1 = 0x1 0000 0000
3158 // (-x = 0) != (0x1 0000 0000 = ~x + 1)
3160 // Therefore, we should disable CMN when comparing against zero, until we can
3161 // limit when the CMN instruction is used (when we know that the RHS is not 0 or
3162 // when it's a comparison which doesn't look at the 'carry' flag).
3164 // (See the ARM docs for the "AddWithCarry" pseudo-code.)
3166 // This is related to <rdar://problem/7569620>.
3168 //defm CMN : AI1_cmp_irs<0b1011, "cmn",
3169 // BinOpFrag<(ARMcmp node:$LHS,(ineg node:$RHS))>>;
3171 // Note that TST/TEQ don't set all the same flags that CMP does!
3172 defm TST : AI1_cmp_irs<0b1000, "tst",
3173 IIC_iTSTi, IIC_iTSTr, IIC_iTSTsr,
3174 BinOpFrag<(ARMcmpZ (and_su node:$LHS, node:$RHS), 0)>, 1>;
3175 defm TEQ : AI1_cmp_irs<0b1001, "teq",
3176 IIC_iTSTi, IIC_iTSTr, IIC_iTSTsr,
3177 BinOpFrag<(ARMcmpZ (xor_su node:$LHS, node:$RHS), 0)>, 1>;
3179 defm CMNz : AI1_cmp_irs<0b1011, "cmn",
3180 IIC_iCMPi, IIC_iCMPr, IIC_iCMPsr,
3181 BinOpFrag<(ARMcmpZ node:$LHS,(ineg node:$RHS))>>;
3183 //def : ARMPat<(ARMcmp GPR:$src, so_imm_neg:$imm),
3184 // (CMNri GPR:$src, so_imm_neg:$imm)>;
3186 def : ARMPat<(ARMcmpZ GPR:$src, so_imm_neg:$imm),
3187 (CMNzri GPR:$src, so_imm_neg:$imm)>;
3189 // Pseudo i64 compares for some floating point compares.
3190 let usesCustomInserter = 1, isBranch = 1, isTerminator = 1,
3192 def BCCi64 : PseudoInst<(outs),
3193 (ins i32imm:$cc, GPR:$lhs1, GPR:$lhs2, GPR:$rhs1, GPR:$rhs2, brtarget:$dst),
3195 [(ARMBcci64 imm:$cc, GPR:$lhs1, GPR:$lhs2, GPR:$rhs1, GPR:$rhs2, bb:$dst)]>;
3197 def BCCZi64 : PseudoInst<(outs),
3198 (ins i32imm:$cc, GPR:$lhs1, GPR:$lhs2, brtarget:$dst), IIC_Br,
3199 [(ARMBcci64 imm:$cc, GPR:$lhs1, GPR:$lhs2, 0, 0, bb:$dst)]>;
3200 } // usesCustomInserter
3203 // Conditional moves
3204 // FIXME: should be able to write a pattern for ARMcmov, but can't use
3205 // a two-value operand where a dag node expects two operands. :(
3206 let neverHasSideEffects = 1 in {
3207 def MOVCCr : ARMPseudoInst<(outs GPR:$Rd), (ins GPR:$false, GPR:$Rm, pred:$p),
3208 Size4Bytes, IIC_iCMOVr,
3209 [/*(set GPR:$Rd, (ARMcmov GPR:$false, GPR:$Rm, imm:$cc, CCR:$ccr))*/]>,
3210 RegConstraint<"$false = $Rd">;
3211 def MOVCCs : ARMPseudoInst<(outs GPR:$Rd),
3212 (ins GPR:$false, so_reg:$shift, pred:$p),
3213 Size4Bytes, IIC_iCMOVsr,
3214 [/*(set GPR:$Rd, (ARMcmov GPR:$false, so_reg:$shift, imm:$cc, CCR:$ccr))*/]>,
3215 RegConstraint<"$false = $Rd">;
3217 let isMoveImm = 1 in
3218 def MOVCCi16 : ARMPseudoInst<(outs GPR:$Rd),
3219 (ins GPR:$false, i32imm_hilo16:$imm, pred:$p),
3220 Size4Bytes, IIC_iMOVi,
3222 RegConstraint<"$false = $Rd">, Requires<[IsARM, HasV6T2]>;
3224 let isMoveImm = 1 in
3225 def MOVCCi : ARMPseudoInst<(outs GPR:$Rd),
3226 (ins GPR:$false, so_imm:$imm, pred:$p),
3227 Size4Bytes, IIC_iCMOVi,
3228 [/*(set GPR:$Rd, (ARMcmov GPR:$false, so_imm:$imm, imm:$cc, CCR:$ccr))*/]>,
3229 RegConstraint<"$false = $Rd">;
3231 // Two instruction predicate mov immediate.
3232 let isMoveImm = 1 in
3233 def MOVCCi32imm : ARMPseudoInst<(outs GPR:$Rd),
3234 (ins GPR:$false, i32imm:$src, pred:$p),
3235 Size8Bytes, IIC_iCMOVix2, []>, RegConstraint<"$false = $Rd">;
3237 let isMoveImm = 1 in
3238 def MVNCCi : ARMPseudoInst<(outs GPR:$Rd),
3239 (ins GPR:$false, so_imm:$imm, pred:$p),
3240 Size4Bytes, IIC_iCMOVi,
3241 [/*(set GPR:$Rd, (ARMcmov GPR:$false, so_imm_not:$imm, imm:$cc, CCR:$ccr))*/]>,
3242 RegConstraint<"$false = $Rd">;
3243 } // neverHasSideEffects
3245 //===----------------------------------------------------------------------===//
3246 // Atomic operations intrinsics
3249 def memb_opt : Operand<i32> {
3250 let PrintMethod = "printMemBOption";
3251 let ParserMatchClass = MemBarrierOptOperand;
3254 // memory barriers protect the atomic sequences
3255 let hasSideEffects = 1 in {
3256 def DMB : AInoP<(outs), (ins memb_opt:$opt), MiscFrm, NoItinerary,
3257 "dmb", "\t$opt", [(ARMMemBarrier (i32 imm:$opt))]>,
3258 Requires<[IsARM, HasDB]> {
3260 let Inst{31-4} = 0xf57ff05;
3261 let Inst{3-0} = opt;
3265 def DSB : AInoP<(outs), (ins memb_opt:$opt), MiscFrm, NoItinerary,
3267 [/* For disassembly only; pattern left blank */]>,
3268 Requires<[IsARM, HasDB]> {
3270 let Inst{31-4} = 0xf57ff04;
3271 let Inst{3-0} = opt;
3274 // ISB has only full system option -- for disassembly only
3275 def ISB : AInoP<(outs), (ins), MiscFrm, NoItinerary, "isb", "", []>,
3276 Requires<[IsARM, HasDB]> {
3277 let Inst{31-4} = 0xf57ff06;
3278 let Inst{3-0} = 0b1111;
3281 let usesCustomInserter = 1 in {
3282 let Uses = [CPSR] in {
3283 def ATOMIC_LOAD_ADD_I8 : PseudoInst<
3284 (outs GPR:$dst), (ins GPR:$ptr, GPR:$incr), NoItinerary,
3285 [(set GPR:$dst, (atomic_load_add_8 GPR:$ptr, GPR:$incr))]>;
3286 def ATOMIC_LOAD_SUB_I8 : PseudoInst<
3287 (outs GPR:$dst), (ins GPR:$ptr, GPR:$incr), NoItinerary,
3288 [(set GPR:$dst, (atomic_load_sub_8 GPR:$ptr, GPR:$incr))]>;
3289 def ATOMIC_LOAD_AND_I8 : PseudoInst<
3290 (outs GPR:$dst), (ins GPR:$ptr, GPR:$incr), NoItinerary,
3291 [(set GPR:$dst, (atomic_load_and_8 GPR:$ptr, GPR:$incr))]>;
3292 def ATOMIC_LOAD_OR_I8 : PseudoInst<
3293 (outs GPR:$dst), (ins GPR:$ptr, GPR:$incr), NoItinerary,
3294 [(set GPR:$dst, (atomic_load_or_8 GPR:$ptr, GPR:$incr))]>;
3295 def ATOMIC_LOAD_XOR_I8 : PseudoInst<
3296 (outs GPR:$dst), (ins GPR:$ptr, GPR:$incr), NoItinerary,
3297 [(set GPR:$dst, (atomic_load_xor_8 GPR:$ptr, GPR:$incr))]>;
3298 def ATOMIC_LOAD_NAND_I8 : PseudoInst<
3299 (outs GPR:$dst), (ins GPR:$ptr, GPR:$incr), NoItinerary,
3300 [(set GPR:$dst, (atomic_load_nand_8 GPR:$ptr, GPR:$incr))]>;
3301 def ATOMIC_LOAD_ADD_I16 : PseudoInst<
3302 (outs GPR:$dst), (ins GPR:$ptr, GPR:$incr), NoItinerary,
3303 [(set GPR:$dst, (atomic_load_add_16 GPR:$ptr, GPR:$incr))]>;
3304 def ATOMIC_LOAD_SUB_I16 : PseudoInst<
3305 (outs GPR:$dst), (ins GPR:$ptr, GPR:$incr), NoItinerary,
3306 [(set GPR:$dst, (atomic_load_sub_16 GPR:$ptr, GPR:$incr))]>;
3307 def ATOMIC_LOAD_AND_I16 : PseudoInst<
3308 (outs GPR:$dst), (ins GPR:$ptr, GPR:$incr), NoItinerary,
3309 [(set GPR:$dst, (atomic_load_and_16 GPR:$ptr, GPR:$incr))]>;
3310 def ATOMIC_LOAD_OR_I16 : PseudoInst<
3311 (outs GPR:$dst), (ins GPR:$ptr, GPR:$incr), NoItinerary,
3312 [(set GPR:$dst, (atomic_load_or_16 GPR:$ptr, GPR:$incr))]>;
3313 def ATOMIC_LOAD_XOR_I16 : PseudoInst<
3314 (outs GPR:$dst), (ins GPR:$ptr, GPR:$incr), NoItinerary,
3315 [(set GPR:$dst, (atomic_load_xor_16 GPR:$ptr, GPR:$incr))]>;
3316 def ATOMIC_LOAD_NAND_I16 : PseudoInst<
3317 (outs GPR:$dst), (ins GPR:$ptr, GPR:$incr), NoItinerary,
3318 [(set GPR:$dst, (atomic_load_nand_16 GPR:$ptr, GPR:$incr))]>;
3319 def ATOMIC_LOAD_ADD_I32 : PseudoInst<
3320 (outs GPR:$dst), (ins GPR:$ptr, GPR:$incr), NoItinerary,
3321 [(set GPR:$dst, (atomic_load_add_32 GPR:$ptr, GPR:$incr))]>;
3322 def ATOMIC_LOAD_SUB_I32 : PseudoInst<
3323 (outs GPR:$dst), (ins GPR:$ptr, GPR:$incr), NoItinerary,
3324 [(set GPR:$dst, (atomic_load_sub_32 GPR:$ptr, GPR:$incr))]>;
3325 def ATOMIC_LOAD_AND_I32 : PseudoInst<
3326 (outs GPR:$dst), (ins GPR:$ptr, GPR:$incr), NoItinerary,
3327 [(set GPR:$dst, (atomic_load_and_32 GPR:$ptr, GPR:$incr))]>;
3328 def ATOMIC_LOAD_OR_I32 : PseudoInst<
3329 (outs GPR:$dst), (ins GPR:$ptr, GPR:$incr), NoItinerary,
3330 [(set GPR:$dst, (atomic_load_or_32 GPR:$ptr, GPR:$incr))]>;
3331 def ATOMIC_LOAD_XOR_I32 : PseudoInst<
3332 (outs GPR:$dst), (ins GPR:$ptr, GPR:$incr), NoItinerary,
3333 [(set GPR:$dst, (atomic_load_xor_32 GPR:$ptr, GPR:$incr))]>;
3334 def ATOMIC_LOAD_NAND_I32 : PseudoInst<
3335 (outs GPR:$dst), (ins GPR:$ptr, GPR:$incr), NoItinerary,
3336 [(set GPR:$dst, (atomic_load_nand_32 GPR:$ptr, GPR:$incr))]>;
3338 def ATOMIC_SWAP_I8 : PseudoInst<
3339 (outs GPR:$dst), (ins GPR:$ptr, GPR:$new), NoItinerary,
3340 [(set GPR:$dst, (atomic_swap_8 GPR:$ptr, GPR:$new))]>;
3341 def ATOMIC_SWAP_I16 : PseudoInst<
3342 (outs GPR:$dst), (ins GPR:$ptr, GPR:$new), NoItinerary,
3343 [(set GPR:$dst, (atomic_swap_16 GPR:$ptr, GPR:$new))]>;
3344 def ATOMIC_SWAP_I32 : PseudoInst<
3345 (outs GPR:$dst), (ins GPR:$ptr, GPR:$new), NoItinerary,
3346 [(set GPR:$dst, (atomic_swap_32 GPR:$ptr, GPR:$new))]>;
3348 def ATOMIC_CMP_SWAP_I8 : PseudoInst<
3349 (outs GPR:$dst), (ins GPR:$ptr, GPR:$old, GPR:$new), NoItinerary,
3350 [(set GPR:$dst, (atomic_cmp_swap_8 GPR:$ptr, GPR:$old, GPR:$new))]>;
3351 def ATOMIC_CMP_SWAP_I16 : PseudoInst<
3352 (outs GPR:$dst), (ins GPR:$ptr, GPR:$old, GPR:$new), NoItinerary,
3353 [(set GPR:$dst, (atomic_cmp_swap_16 GPR:$ptr, GPR:$old, GPR:$new))]>;
3354 def ATOMIC_CMP_SWAP_I32 : PseudoInst<
3355 (outs GPR:$dst), (ins GPR:$ptr, GPR:$old, GPR:$new), NoItinerary,
3356 [(set GPR:$dst, (atomic_cmp_swap_32 GPR:$ptr, GPR:$old, GPR:$new))]>;
3360 let mayLoad = 1 in {
3361 def LDREXB : AIldrex<0b10, (outs GPR:$Rt), (ins addrmode7:$addr), NoItinerary,
3362 "ldrexb", "\t$Rt, $addr", []>;
3363 def LDREXH : AIldrex<0b11, (outs GPR:$Rt), (ins addrmode7:$addr), NoItinerary,
3364 "ldrexh", "\t$Rt, $addr", []>;
3365 def LDREX : AIldrex<0b00, (outs GPR:$Rt), (ins addrmode7:$addr), NoItinerary,
3366 "ldrex", "\t$Rt, $addr", []>;
3367 def LDREXD : AIldrex<0b01, (outs GPR:$Rt, GPR:$Rt2), (ins addrmode7:$addr),
3368 NoItinerary, "ldrexd", "\t$Rt, $Rt2, $addr", []>;
3371 let mayStore = 1, Constraints = "@earlyclobber $Rd" in {
3372 def STREXB : AIstrex<0b10, (outs GPR:$Rd), (ins GPR:$Rt, addrmode7:$addr),
3373 NoItinerary, "strexb", "\t$Rd, $Rt, $addr", []>;
3374 def STREXH : AIstrex<0b11, (outs GPR:$Rd), (ins GPR:$Rt, addrmode7:$addr),
3375 NoItinerary, "strexh", "\t$Rd, $Rt, $addr", []>;
3376 def STREX : AIstrex<0b00, (outs GPR:$Rd), (ins GPR:$Rt, addrmode7:$addr),
3377 NoItinerary, "strex", "\t$Rd, $Rt, $addr", []>;
3378 def STREXD : AIstrex<0b01, (outs GPR:$Rd),
3379 (ins GPR:$Rt, GPR:$Rt2, addrmode7:$addr),
3380 NoItinerary, "strexd", "\t$Rd, $Rt, $Rt2, $addr", []>;
3383 // Clear-Exclusive is for disassembly only.
3384 def CLREX : AXI<(outs), (ins), MiscFrm, NoItinerary, "clrex",
3385 [/* For disassembly only; pattern left blank */]>,
3386 Requires<[IsARM, HasV7]> {
3387 let Inst{31-0} = 0b11110101011111111111000000011111;
3390 // SWP/SWPB are deprecated in V6/V7 and for disassembly only.
3391 let mayLoad = 1 in {
3392 def SWP : AIswp<0, (outs GPR:$Rt), (ins GPR:$Rt2, GPR:$Rn), "swp",
3393 [/* For disassembly only; pattern left blank */]>;
3394 def SWPB : AIswp<1, (outs GPR:$Rt), (ins GPR:$Rt2, GPR:$Rn), "swpb",
3395 [/* For disassembly only; pattern left blank */]>;
3398 //===----------------------------------------------------------------------===//
3399 // Coprocessor Instructions.
3402 def CDP : ABI<0b1110, (outs), (ins p_imm:$cop, i32imm:$opc1,
3403 c_imm:$CRd, c_imm:$CRn, c_imm:$CRm, i32imm:$opc2),
3404 NoItinerary, "cdp", "\t$cop, $opc1, $CRd, $CRn, $CRm, $opc2",
3405 [/* For disassembly only; pattern left blank */]> {
3413 let Inst{3-0} = CRm;
3415 let Inst{7-5} = opc2;
3416 let Inst{11-8} = cop;
3417 let Inst{15-12} = CRd;
3418 let Inst{19-16} = CRn;
3419 let Inst{23-20} = opc1;
3422 def CDP2 : ABXI<0b1110, (outs), (ins p_imm:$cop, i32imm:$opc1,
3423 c_imm:$CRd, c_imm:$CRn, c_imm:$CRm, i32imm:$opc2),
3424 NoItinerary, "cdp2\t$cop, $opc1, $CRd, $CRn, $CRm, $opc2",
3425 [/* For disassembly only; pattern left blank */]> {
3426 let Inst{31-28} = 0b1111;
3434 let Inst{3-0} = CRm;
3436 let Inst{7-5} = opc2;
3437 let Inst{11-8} = cop;
3438 let Inst{15-12} = CRd;
3439 let Inst{19-16} = CRn;
3440 let Inst{23-20} = opc1;
3443 class ACI<dag oops, dag iops, string opc, string asm,
3444 IndexMode im = IndexModeNone>
3445 : InoP<oops, iops, AddrModeNone, Size4Bytes, im, BrFrm, NoItinerary,
3446 opc, asm, "", [/* For disassembly only; pattern left blank */]> {
3447 let Inst{27-25} = 0b110;
3450 multiclass LdStCop<bits<4> op31_28, bit load, dag ops, string opc, string cond>{
3452 def _OFFSET : ACI<(outs),
3453 !con((ins nohash_imm:$cop, nohash_imm:$CRd, addrmode2:$addr), ops),
3454 !strconcat(opc, cond), "\tp$cop, cr$CRd, $addr"> {
3455 let Inst{31-28} = op31_28;
3456 let Inst{24} = 1; // P = 1
3457 let Inst{21} = 0; // W = 0
3458 let Inst{22} = 0; // D = 0
3459 let Inst{20} = load;
3462 def _PRE : ACI<(outs),
3463 !con((ins nohash_imm:$cop, nohash_imm:$CRd, addrmode2:$addr), ops),
3464 !strconcat(opc, cond), "\tp$cop, cr$CRd, $addr!", IndexModePre> {
3465 let Inst{31-28} = op31_28;
3466 let Inst{24} = 1; // P = 1
3467 let Inst{21} = 1; // W = 1
3468 let Inst{22} = 0; // D = 0
3469 let Inst{20} = load;
3472 def _POST : ACI<(outs),
3473 !con((ins nohash_imm:$cop, nohash_imm:$CRd, addrmode2:$addr), ops),
3474 !strconcat(opc, cond), "\tp$cop, cr$CRd, $addr", IndexModePost> {
3475 let Inst{31-28} = op31_28;
3476 let Inst{24} = 0; // P = 0
3477 let Inst{21} = 1; // W = 1
3478 let Inst{22} = 0; // D = 0
3479 let Inst{20} = load;
3482 def _OPTION : ACI<(outs),
3483 !con((ins nohash_imm:$cop,nohash_imm:$CRd,GPR:$base, nohash_imm:$option),
3485 !strconcat(opc, cond), "\tp$cop, cr$CRd, [$base], \\{$option\\}"> {
3486 let Inst{31-28} = op31_28;
3487 let Inst{24} = 0; // P = 0
3488 let Inst{23} = 1; // U = 1
3489 let Inst{21} = 0; // W = 0
3490 let Inst{22} = 0; // D = 0
3491 let Inst{20} = load;
3494 def L_OFFSET : ACI<(outs),
3495 !con((ins nohash_imm:$cop, nohash_imm:$CRd, addrmode2:$addr), ops),
3496 !strconcat(!strconcat(opc, "l"), cond), "\tp$cop, cr$CRd, $addr"> {
3497 let Inst{31-28} = op31_28;
3498 let Inst{24} = 1; // P = 1
3499 let Inst{21} = 0; // W = 0
3500 let Inst{22} = 1; // D = 1
3501 let Inst{20} = load;
3504 def L_PRE : ACI<(outs),
3505 !con((ins nohash_imm:$cop, nohash_imm:$CRd, addrmode2:$addr), ops),
3506 !strconcat(!strconcat(opc, "l"), cond), "\tp$cop, cr$CRd, $addr!",
3508 let Inst{31-28} = op31_28;
3509 let Inst{24} = 1; // P = 1
3510 let Inst{21} = 1; // W = 1
3511 let Inst{22} = 1; // D = 1
3512 let Inst{20} = load;
3515 def L_POST : ACI<(outs),
3516 !con((ins nohash_imm:$cop, nohash_imm:$CRd, addrmode2:$addr), ops),
3517 !strconcat(!strconcat(opc, "l"), cond), "\tp$cop, cr$CRd, $addr",
3519 let Inst{31-28} = op31_28;
3520 let Inst{24} = 0; // P = 0
3521 let Inst{21} = 1; // W = 1
3522 let Inst{22} = 1; // D = 1
3523 let Inst{20} = load;
3526 def L_OPTION : ACI<(outs),
3527 !con((ins nohash_imm:$cop, nohash_imm:$CRd,GPR:$base,nohash_imm:$option),
3529 !strconcat(!strconcat(opc, "l"), cond),
3530 "\tp$cop, cr$CRd, [$base], \\{$option\\}"> {
3531 let Inst{31-28} = op31_28;
3532 let Inst{24} = 0; // P = 0
3533 let Inst{23} = 1; // U = 1
3534 let Inst{21} = 0; // W = 0
3535 let Inst{22} = 1; // D = 1
3536 let Inst{20} = load;
3540 defm LDC : LdStCop<{?,?,?,?}, 1, (ins pred:$p), "ldc", "${p}">;
3541 defm LDC2 : LdStCop<0b1111, 1, (ins), "ldc2", "">;
3542 defm STC : LdStCop<{?,?,?,?}, 0, (ins pred:$p), "stc", "${p}">;
3543 defm STC2 : LdStCop<0b1111, 0, (ins), "stc2", "">;
3545 //===----------------------------------------------------------------------===//
3546 // Move between coprocessor and ARM core register -- for disassembly only
3549 class MovRCopro<string opc, bit direction, dag oops, dag iops>
3550 : ABI<0b1110, oops, iops, NoItinerary, opc,
3551 "\t$cop, $opc1, $Rt, $CRn, $CRm, $opc2",
3552 [/* For disassembly only; pattern left blank */]> {
3553 let Inst{20} = direction;
3563 let Inst{15-12} = Rt;
3564 let Inst{11-8} = cop;
3565 let Inst{23-21} = opc1;
3566 let Inst{7-5} = opc2;
3567 let Inst{3-0} = CRm;
3568 let Inst{19-16} = CRn;
3571 def MCR : MovRCopro<"mcr", 0 /* from ARM core register to coprocessor */,
3572 (outs), (ins p_imm:$cop, i32imm:$opc1,
3573 GPR:$Rt, c_imm:$CRn, c_imm:$CRm,
3575 def MRC : MovRCopro<"mrc", 1 /* from coprocessor to ARM core register */,
3576 (outs GPR:$Rt), (ins p_imm:$cop, i32imm:$opc1,
3577 c_imm:$CRn, c_imm:$CRm, i32imm:$opc2)>;
3579 class MovRCopro2<string opc, bit direction, dag oops, dag iops>
3580 : ABXI<0b1110, oops, iops, NoItinerary,
3581 !strconcat(opc, "\t$cop, $opc1, $Rt, $CRn, $CRm, $opc2"),
3582 [/* For disassembly only; pattern left blank */]> {
3583 let Inst{31-28} = 0b1111;
3584 let Inst{20} = direction;
3594 let Inst{15-12} = Rt;
3595 let Inst{11-8} = cop;
3596 let Inst{23-21} = opc1;
3597 let Inst{7-5} = opc2;
3598 let Inst{3-0} = CRm;
3599 let Inst{19-16} = CRn;
3602 def MCR2 : MovRCopro2<"mcr2", 0 /* from ARM core register to coprocessor */,
3603 (outs), (ins p_imm:$cop, i32imm:$opc1,
3604 GPR:$Rt, c_imm:$CRn, c_imm:$CRm,
3606 def MRC2 : MovRCopro2<"mrc2", 1 /* from coprocessor to ARM core register */,
3607 (outs GPR:$Rt), (ins p_imm:$cop, i32imm:$opc1,
3608 c_imm:$CRn, c_imm:$CRm,
3611 class MovRRCopro<string opc, bit direction>
3612 : ABI<0b1100, (outs), (ins p_imm:$cop, i32imm:$opc1,
3613 GPR:$Rt, GPR:$Rt2, c_imm:$CRm),
3614 NoItinerary, opc, "\t$cop, $opc1, $Rt, $Rt2, $CRm",
3615 [/* For disassembly only; pattern left blank */]> {
3616 let Inst{23-21} = 0b010;
3617 let Inst{20} = direction;
3625 let Inst{15-12} = Rt;
3626 let Inst{19-16} = Rt2;
3627 let Inst{11-8} = cop;
3628 let Inst{7-4} = opc1;
3629 let Inst{3-0} = CRm;
3632 def MCRR : MovRRCopro<"mcrr", 0 /* from ARM core register to coprocessor */>;
3633 def MRRC : MovRRCopro<"mrrc", 1 /* from coprocessor to ARM core register */>;
3635 class MovRRCopro2<string opc, bit direction>
3636 : ABXI<0b1100, (outs), (ins p_imm:$cop, i32imm:$opc1,
3637 GPR:$Rt, GPR:$Rt2, c_imm:$CRm),
3638 NoItinerary, !strconcat(opc, "\t$cop, $opc1, $Rt, $Rt2, $CRm"),
3639 [/* For disassembly only; pattern left blank */]> {
3640 let Inst{31-28} = 0b1111;
3641 let Inst{23-21} = 0b010;
3642 let Inst{20} = direction;
3650 let Inst{15-12} = Rt;
3651 let Inst{19-16} = Rt2;
3652 let Inst{11-8} = cop;
3653 let Inst{7-4} = opc1;
3654 let Inst{3-0} = CRm;
3657 def MCRR2 : MovRRCopro2<"mcrr2", 0 /* from ARM core register to coprocessor */>;
3658 def MRRC2 : MovRRCopro2<"mrrc2", 1 /* from coprocessor to ARM core register */>;
3660 //===----------------------------------------------------------------------===//
3661 // Move between special register and ARM core register -- for disassembly only
3664 // Move to ARM core register from Special Register
3665 def MRS : ABI<0b0001, (outs GPR:$Rd), (ins), NoItinerary, "mrs", "\t$Rd, cpsr",
3666 [/* For disassembly only; pattern left blank */]> {
3668 let Inst{23-16} = 0b00001111;
3669 let Inst{15-12} = Rd;
3670 let Inst{7-4} = 0b0000;
3673 def MRSsys : ABI<0b0001, (outs GPR:$Rd), (ins), NoItinerary,"mrs","\t$Rd, spsr",
3674 [/* For disassembly only; pattern left blank */]> {
3676 let Inst{23-16} = 0b01001111;
3677 let Inst{15-12} = Rd;
3678 let Inst{7-4} = 0b0000;
3681 // Move from ARM core register to Special Register
3683 // No need to have both system and application versions, the encodings are the
3684 // same and the assembly parser has no way to distinguish between them. The mask
3685 // operand contains the special register (R Bit) in bit 4 and bits 3-0 contains
3686 // the mask with the fields to be accessed in the special register.
3687 def MSR : ABI<0b0001, (outs), (ins msr_mask:$mask, GPR:$Rn), NoItinerary,
3688 "msr", "\t$mask, $Rn",
3689 [/* For disassembly only; pattern left blank */]> {
3694 let Inst{22} = mask{4}; // R bit
3695 let Inst{21-20} = 0b10;
3696 let Inst{19-16} = mask{3-0};
3697 let Inst{15-12} = 0b1111;
3698 let Inst{11-4} = 0b00000000;
3702 def MSRi : ABI<0b0011, (outs), (ins msr_mask:$mask, so_imm:$a), NoItinerary,
3703 "msr", "\t$mask, $a",
3704 [/* For disassembly only; pattern left blank */]> {
3709 let Inst{22} = mask{4}; // R bit
3710 let Inst{21-20} = 0b10;
3711 let Inst{19-16} = mask{3-0};
3712 let Inst{15-12} = 0b1111;
3716 //===----------------------------------------------------------------------===//
3720 // __aeabi_read_tp preserves the registers r1-r3.
3721 // This is a pseudo inst so that we can get the encoding right,
3722 // complete with fixup for the aeabi_read_tp function.
3724 Defs = [R0, R12, LR, CPSR], Uses = [SP] in {
3725 def TPsoft : PseudoInst<(outs), (ins), IIC_Br,
3726 [(set R0, ARMthread_pointer)]>;
3729 //===----------------------------------------------------------------------===//
3730 // SJLJ Exception handling intrinsics
3731 // eh_sjlj_setjmp() is an instruction sequence to store the return
3732 // address and save #0 in R0 for the non-longjmp case.
3733 // Since by its nature we may be coming from some other function to get
3734 // here, and we're using the stack frame for the containing function to
3735 // save/restore registers, we can't keep anything live in regs across
3736 // the eh_sjlj_setjmp(), else it will almost certainly have been tromped upon
3737 // when we get here from a longjmp(). We force everthing out of registers
3738 // except for our own input by listing the relevant registers in Defs. By
3739 // doing so, we also cause the prologue/epilogue code to actively preserve
3740 // all of the callee-saved resgisters, which is exactly what we want.
3741 // A constant value is passed in $val, and we use the location as a scratch.
3743 // These are pseudo-instructions and are lowered to individual MC-insts, so
3744 // no encoding information is necessary.
3746 [ R0, R1, R2, R3, R4, R5, R6, R7, R8, R9, R10, R11, R12, LR, D0,
3747 D1, D2, D3, D4, D5, D6, D7, D8, D9, D10, D11, D12, D13, D14, D15,
3748 D16, D17, D18, D19, D20, D21, D22, D23, D24, D25, D26, D27, D28, D29, D30,
3749 D31 ], hasSideEffects = 1, isBarrier = 1 in {
3750 def Int_eh_sjlj_setjmp : PseudoInst<(outs), (ins GPR:$src, GPR:$val),
3752 [(set R0, (ARMeh_sjlj_setjmp GPR:$src, GPR:$val))]>,
3753 Requires<[IsARM, HasVFP2]>;
3757 [ R0, R1, R2, R3, R4, R5, R6, R7, R8, R9, R10, R11, R12, LR ],
3758 hasSideEffects = 1, isBarrier = 1 in {
3759 def Int_eh_sjlj_setjmp_nofp : PseudoInst<(outs), (ins GPR:$src, GPR:$val),
3761 [(set R0, (ARMeh_sjlj_setjmp GPR:$src, GPR:$val))]>,
3762 Requires<[IsARM, NoVFP]>;
3765 // FIXME: Non-Darwin version(s)
3766 let isBarrier = 1, hasSideEffects = 1, isTerminator = 1,
3767 Defs = [ R7, LR, SP ] in {
3768 def Int_eh_sjlj_longjmp : PseudoInst<(outs), (ins GPR:$src, GPR:$scratch),
3770 [(ARMeh_sjlj_longjmp GPR:$src, GPR:$scratch)]>,
3771 Requires<[IsARM, IsDarwin]>;
3774 // eh.sjlj.dispatchsetup pseudo-instruction.
3775 // This pseudo is used for ARM, Thumb1 and Thumb2. Any differences are
3776 // handled when the pseudo is expanded (which happens before any passes
3777 // that need the instruction size).
3778 let isBarrier = 1, hasSideEffects = 1 in
3779 def Int_eh_sjlj_dispatchsetup :
3780 PseudoInst<(outs), (ins GPR:$src), NoItinerary,
3781 [(ARMeh_sjlj_dispatchsetup GPR:$src)]>,
3782 Requires<[IsDarwin]>;
3784 //===----------------------------------------------------------------------===//
3785 // Non-Instruction Patterns
3788 // Large immediate handling.
3790 // 32-bit immediate using two piece so_imms or movw + movt.
3791 // This is a single pseudo instruction, the benefit is that it can be remat'd
3792 // as a single unit instead of having to handle reg inputs.
3793 // FIXME: Remove this when we can do generalized remat.
3794 let isReMaterializable = 1, isMoveImm = 1 in
3795 def MOVi32imm : PseudoInst<(outs GPR:$dst), (ins i32imm:$src), IIC_iMOVix2,
3796 [(set GPR:$dst, (arm_i32imm:$src))]>,
3799 // Pseudo instruction that combines movw + movt + add pc (if PIC).
3800 // It also makes it possible to rematerialize the instructions.
3801 // FIXME: Remove this when we can do generalized remat and when machine licm
3802 // can properly the instructions.
3803 let isReMaterializable = 1 in {
3804 def MOV_ga_pcrel : PseudoInst<(outs GPR:$dst), (ins i32imm:$addr),
3806 [(set GPR:$dst, (ARMWrapperPIC tglobaladdr:$addr))]>,
3807 Requires<[IsARM, UseMovt]>;
3809 def MOV_ga_dyn : PseudoInst<(outs GPR:$dst), (ins i32imm:$addr),
3811 [(set GPR:$dst, (ARMWrapperDYN tglobaladdr:$addr))]>,
3812 Requires<[IsARM, UseMovt]>;
3814 let AddedComplexity = 10 in
3815 def MOV_ga_pcrel_ldr : PseudoInst<(outs GPR:$dst), (ins i32imm:$addr),
3817 [(set GPR:$dst, (load (ARMWrapperPIC tglobaladdr:$addr)))]>,
3818 Requires<[IsARM, UseMovt]>;
3819 } // isReMaterializable
3821 // ConstantPool, GlobalAddress, and JumpTable
3822 def : ARMPat<(ARMWrapper tglobaladdr :$dst), (LEApcrel tglobaladdr :$dst)>,
3823 Requires<[IsARM, DontUseMovt]>;
3824 def : ARMPat<(ARMWrapper tconstpool :$dst), (LEApcrel tconstpool :$dst)>;
3825 def : ARMPat<(ARMWrapper tglobaladdr :$dst), (MOVi32imm tglobaladdr :$dst)>,
3826 Requires<[IsARM, UseMovt]>;
3827 def : ARMPat<(ARMWrapperJT tjumptable:$dst, imm:$id),
3828 (LEApcrelJT tjumptable:$dst, imm:$id)>;
3830 // TODO: add,sub,and, 3-instr forms?
3833 def : ARMPat<(ARMtcret tcGPR:$dst),
3834 (TCRETURNri tcGPR:$dst)>, Requires<[IsDarwin]>;
3836 def : ARMPat<(ARMtcret (i32 tglobaladdr:$dst)),
3837 (TCRETURNdi texternalsym:$dst)>, Requires<[IsDarwin]>;
3839 def : ARMPat<(ARMtcret (i32 texternalsym:$dst)),
3840 (TCRETURNdi texternalsym:$dst)>, Requires<[IsDarwin]>;
3842 def : ARMPat<(ARMtcret tcGPR:$dst),
3843 (TCRETURNriND tcGPR:$dst)>, Requires<[IsNotDarwin]>;
3845 def : ARMPat<(ARMtcret (i32 tglobaladdr:$dst)),
3846 (TCRETURNdiND texternalsym:$dst)>, Requires<[IsNotDarwin]>;
3848 def : ARMPat<(ARMtcret (i32 texternalsym:$dst)),
3849 (TCRETURNdiND texternalsym:$dst)>, Requires<[IsNotDarwin]>;
3852 def : ARMPat<(ARMcall texternalsym:$func), (BL texternalsym:$func)>,
3853 Requires<[IsARM, IsNotDarwin]>;
3854 def : ARMPat<(ARMcall texternalsym:$func), (BLr9 texternalsym:$func)>,
3855 Requires<[IsARM, IsDarwin]>;
3857 // zextload i1 -> zextload i8
3858 def : ARMPat<(zextloadi1 addrmode_imm12:$addr), (LDRBi12 addrmode_imm12:$addr)>;
3859 def : ARMPat<(zextloadi1 ldst_so_reg:$addr), (LDRBrs ldst_so_reg:$addr)>;
3861 // extload -> zextload
3862 def : ARMPat<(extloadi1 addrmode_imm12:$addr), (LDRBi12 addrmode_imm12:$addr)>;
3863 def : ARMPat<(extloadi1 ldst_so_reg:$addr), (LDRBrs ldst_so_reg:$addr)>;
3864 def : ARMPat<(extloadi8 addrmode_imm12:$addr), (LDRBi12 addrmode_imm12:$addr)>;
3865 def : ARMPat<(extloadi8 ldst_so_reg:$addr), (LDRBrs ldst_so_reg:$addr)>;
3867 def : ARMPat<(extloadi16 addrmode3:$addr), (LDRH addrmode3:$addr)>;
3869 def : ARMPat<(extloadi8 addrmodepc:$addr), (PICLDRB addrmodepc:$addr)>;
3870 def : ARMPat<(extloadi16 addrmodepc:$addr), (PICLDRH addrmodepc:$addr)>;
3873 def : ARMV5TEPat<(mul (sra (shl GPR:$a, (i32 16)), (i32 16)),
3874 (sra (shl GPR:$b, (i32 16)), (i32 16))),
3875 (SMULBB GPR:$a, GPR:$b)>;
3876 def : ARMV5TEPat<(mul sext_16_node:$a, sext_16_node:$b),
3877 (SMULBB GPR:$a, GPR:$b)>;
3878 def : ARMV5TEPat<(mul (sra (shl GPR:$a, (i32 16)), (i32 16)),
3879 (sra GPR:$b, (i32 16))),
3880 (SMULBT GPR:$a, GPR:$b)>;
3881 def : ARMV5TEPat<(mul sext_16_node:$a, (sra GPR:$b, (i32 16))),
3882 (SMULBT GPR:$a, GPR:$b)>;
3883 def : ARMV5TEPat<(mul (sra GPR:$a, (i32 16)),
3884 (sra (shl GPR:$b, (i32 16)), (i32 16))),
3885 (SMULTB GPR:$a, GPR:$b)>;
3886 def : ARMV5TEPat<(mul (sra GPR:$a, (i32 16)), sext_16_node:$b),
3887 (SMULTB GPR:$a, GPR:$b)>;
3888 def : ARMV5TEPat<(sra (mul GPR:$a, (sra (shl GPR:$b, (i32 16)), (i32 16))),
3890 (SMULWB GPR:$a, GPR:$b)>;
3891 def : ARMV5TEPat<(sra (mul GPR:$a, sext_16_node:$b), (i32 16)),
3892 (SMULWB GPR:$a, GPR:$b)>;
3894 def : ARMV5TEPat<(add GPR:$acc,
3895 (mul (sra (shl GPR:$a, (i32 16)), (i32 16)),
3896 (sra (shl GPR:$b, (i32 16)), (i32 16)))),
3897 (SMLABB GPR:$a, GPR:$b, GPR:$acc)>;
3898 def : ARMV5TEPat<(add GPR:$acc,
3899 (mul sext_16_node:$a, sext_16_node:$b)),
3900 (SMLABB GPR:$a, GPR:$b, GPR:$acc)>;
3901 def : ARMV5TEPat<(add GPR:$acc,
3902 (mul (sra (shl GPR:$a, (i32 16)), (i32 16)),
3903 (sra GPR:$b, (i32 16)))),
3904 (SMLABT GPR:$a, GPR:$b, GPR:$acc)>;
3905 def : ARMV5TEPat<(add GPR:$acc,
3906 (mul sext_16_node:$a, (sra GPR:$b, (i32 16)))),
3907 (SMLABT GPR:$a, GPR:$b, GPR:$acc)>;
3908 def : ARMV5TEPat<(add GPR:$acc,
3909 (mul (sra GPR:$a, (i32 16)),
3910 (sra (shl GPR:$b, (i32 16)), (i32 16)))),
3911 (SMLATB GPR:$a, GPR:$b, GPR:$acc)>;
3912 def : ARMV5TEPat<(add GPR:$acc,
3913 (mul (sra GPR:$a, (i32 16)), sext_16_node:$b)),
3914 (SMLATB GPR:$a, GPR:$b, GPR:$acc)>;
3915 def : ARMV5TEPat<(add GPR:$acc,
3916 (sra (mul GPR:$a, (sra (shl GPR:$b, (i32 16)), (i32 16))),
3918 (SMLAWB GPR:$a, GPR:$b, GPR:$acc)>;
3919 def : ARMV5TEPat<(add GPR:$acc,
3920 (sra (mul GPR:$a, sext_16_node:$b), (i32 16))),
3921 (SMLAWB GPR:$a, GPR:$b, GPR:$acc)>;
3924 // Pre-v7 uses MCR for synchronization barriers.
3925 def : ARMPat<(ARMMemBarrierMCR GPR:$zero), (MCR 15, 0, GPR:$zero, 7, 10, 5)>,
3926 Requires<[IsARM, HasV6]>;
3929 //===----------------------------------------------------------------------===//
3933 include "ARMInstrThumb.td"
3935 //===----------------------------------------------------------------------===//
3939 include "ARMInstrThumb2.td"
3941 //===----------------------------------------------------------------------===//
3942 // Floating Point Support
3945 include "ARMInstrVFP.td"
3947 //===----------------------------------------------------------------------===//
3948 // Advanced SIMD (NEON) Support
3951 include "ARMInstrNEON.td"