1 //===- ARMInstrInfo.td - Target Description for ARM Target -*- tablegen -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file describes the ARM instructions in TableGen format.
12 //===----------------------------------------------------------------------===//
14 //===----------------------------------------------------------------------===//
15 // ARM specific DAG Nodes.
19 def SDT_ARMCallSeqStart : SDCallSeqStart<[ SDTCisVT<0, i32> ]>;
20 def SDT_ARMCallSeqEnd : SDCallSeqEnd<[ SDTCisVT<0, i32>, SDTCisVT<1, i32> ]>;
22 def SDT_ARMSaveCallPC : SDTypeProfile<0, 1, []>;
24 def SDT_ARMcall : SDTypeProfile<0, -1, [SDTCisPtrTy<0>]>;
26 def SDT_ARMCMov : SDTypeProfile<1, 3,
27 [SDTCisSameAs<0, 1>, SDTCisSameAs<0, 2>,
30 def SDT_ARMBrcond : SDTypeProfile<0, 2,
31 [SDTCisVT<0, OtherVT>, SDTCisVT<1, i32>]>;
33 def SDT_ARMBrJT : SDTypeProfile<0, 3,
34 [SDTCisPtrTy<0>, SDTCisVT<1, i32>,
37 def SDT_ARMBr2JT : SDTypeProfile<0, 4,
38 [SDTCisPtrTy<0>, SDTCisVT<1, i32>,
39 SDTCisVT<2, i32>, SDTCisVT<3, i32>]>;
41 def SDT_ARMBCC_i64 : SDTypeProfile<0, 6,
43 SDTCisVT<1, i32>, SDTCisVT<2, i32>,
44 SDTCisVT<3, i32>, SDTCisVT<4, i32>,
45 SDTCisVT<5, OtherVT>]>;
47 def SDT_ARMAnd : SDTypeProfile<1, 2,
48 [SDTCisVT<0, i32>, SDTCisVT<1, i32>,
51 def SDT_ARMCmp : SDTypeProfile<0, 2, [SDTCisSameAs<0, 1>]>;
53 def SDT_ARMPICAdd : SDTypeProfile<1, 2, [SDTCisSameAs<0, 1>,
54 SDTCisPtrTy<1>, SDTCisVT<2, i32>]>;
56 def SDT_ARMThreadPointer : SDTypeProfile<1, 0, [SDTCisPtrTy<0>]>;
57 def SDT_ARMEH_SJLJ_Setjmp : SDTypeProfile<1, 2, [SDTCisInt<0>, SDTCisPtrTy<1>,
59 def SDT_ARMEH_SJLJ_Longjmp: SDTypeProfile<0, 2, [SDTCisPtrTy<0>, SDTCisInt<1>]>;
61 def SDT_ARMEH_SJLJ_DispatchSetup: SDTypeProfile<0, 0, []>;
63 def SDT_ARMMEMBARRIER : SDTypeProfile<0, 1, [SDTCisInt<0>]>;
65 def SDT_ARMTCRET : SDTypeProfile<0, 1, [SDTCisPtrTy<0>]>;
67 def SDT_ARMBFI : SDTypeProfile<1, 3, [SDTCisVT<0, i32>, SDTCisVT<1, i32>,
68 SDTCisVT<2, i32>, SDTCisVT<3, i32>]>;
71 def ARMWrapper : SDNode<"ARMISD::Wrapper", SDTIntUnaryOp>;
72 def ARMWrapperDYN : SDNode<"ARMISD::WrapperDYN", SDTIntUnaryOp>;
73 def ARMWrapperPIC : SDNode<"ARMISD::WrapperPIC", SDTIntUnaryOp>;
74 def ARMWrapperJT : SDNode<"ARMISD::WrapperJT", SDTIntBinOp>;
76 def ARMcallseq_start : SDNode<"ISD::CALLSEQ_START", SDT_ARMCallSeqStart,
77 [SDNPHasChain, SDNPOutGlue]>;
78 def ARMcallseq_end : SDNode<"ISD::CALLSEQ_END", SDT_ARMCallSeqEnd,
79 [SDNPHasChain, SDNPOptInGlue, SDNPOutGlue]>;
81 def ARMcall : SDNode<"ARMISD::CALL", SDT_ARMcall,
82 [SDNPHasChain, SDNPOptInGlue, SDNPOutGlue,
84 def ARMcall_pred : SDNode<"ARMISD::CALL_PRED", SDT_ARMcall,
85 [SDNPHasChain, SDNPOptInGlue, SDNPOutGlue,
87 def ARMcall_nolink : SDNode<"ARMISD::CALL_NOLINK", SDT_ARMcall,
88 [SDNPHasChain, SDNPOptInGlue, SDNPOutGlue,
91 def ARMretflag : SDNode<"ARMISD::RET_FLAG", SDTNone,
92 [SDNPHasChain, SDNPOptInGlue]>;
94 def ARMcmov : SDNode<"ARMISD::CMOV", SDT_ARMCMov,
97 def ARMbrcond : SDNode<"ARMISD::BRCOND", SDT_ARMBrcond,
98 [SDNPHasChain, SDNPInGlue, SDNPOutGlue]>;
100 def ARMbrjt : SDNode<"ARMISD::BR_JT", SDT_ARMBrJT,
102 def ARMbr2jt : SDNode<"ARMISD::BR2_JT", SDT_ARMBr2JT,
105 def ARMBcci64 : SDNode<"ARMISD::BCC_i64", SDT_ARMBCC_i64,
108 def ARMcmp : SDNode<"ARMISD::CMP", SDT_ARMCmp,
111 def ARMcmpZ : SDNode<"ARMISD::CMPZ", SDT_ARMCmp,
112 [SDNPOutGlue, SDNPCommutative]>;
114 def ARMpic_add : SDNode<"ARMISD::PIC_ADD", SDT_ARMPICAdd>;
116 def ARMsrl_flag : SDNode<"ARMISD::SRL_FLAG", SDTIntUnaryOp, [SDNPOutGlue]>;
117 def ARMsra_flag : SDNode<"ARMISD::SRA_FLAG", SDTIntUnaryOp, [SDNPOutGlue]>;
118 def ARMrrx : SDNode<"ARMISD::RRX" , SDTIntUnaryOp, [SDNPInGlue ]>;
120 def ARMthread_pointer: SDNode<"ARMISD::THREAD_POINTER", SDT_ARMThreadPointer>;
121 def ARMeh_sjlj_setjmp: SDNode<"ARMISD::EH_SJLJ_SETJMP",
122 SDT_ARMEH_SJLJ_Setjmp, [SDNPHasChain]>;
123 def ARMeh_sjlj_longjmp: SDNode<"ARMISD::EH_SJLJ_LONGJMP",
124 SDT_ARMEH_SJLJ_Longjmp, [SDNPHasChain]>;
125 def ARMeh_sjlj_dispatchsetup: SDNode<"ARMISD::EH_SJLJ_DISPATCHSETUP",
126 SDT_ARMEH_SJLJ_DispatchSetup, [SDNPHasChain]>;
129 def ARMMemBarrier : SDNode<"ARMISD::MEMBARRIER", SDT_ARMMEMBARRIER,
131 def ARMMemBarrierMCR : SDNode<"ARMISD::MEMBARRIER_MCR", SDT_ARMMEMBARRIER,
133 def ARMPreload : SDNode<"ARMISD::PRELOAD", SDTPrefetch,
134 [SDNPHasChain, SDNPMayLoad, SDNPMayStore]>;
136 def ARMrbit : SDNode<"ARMISD::RBIT", SDTIntUnaryOp>;
138 def ARMtcret : SDNode<"ARMISD::TC_RETURN", SDT_ARMTCRET,
139 [SDNPHasChain, SDNPOptInGlue, SDNPVariadic]>;
142 def ARMbfi : SDNode<"ARMISD::BFI", SDT_ARMBFI>;
144 //===----------------------------------------------------------------------===//
145 // ARM Instruction Predicate Definitions.
147 def HasV4T : Predicate<"Subtarget->hasV4TOps()">, AssemblerPredicate;
148 def NoV4T : Predicate<"!Subtarget->hasV4TOps()">;
149 def HasV5T : Predicate<"Subtarget->hasV5TOps()">;
150 def HasV5TE : Predicate<"Subtarget->hasV5TEOps()">, AssemblerPredicate;
151 def HasV6 : Predicate<"Subtarget->hasV6Ops()">, AssemblerPredicate;
152 def NoV6 : Predicate<"!Subtarget->hasV6Ops()">;
153 def HasV6T2 : Predicate<"Subtarget->hasV6T2Ops()">, AssemblerPredicate;
154 def NoV6T2 : Predicate<"!Subtarget->hasV6T2Ops()">;
155 def HasV7 : Predicate<"Subtarget->hasV7Ops()">, AssemblerPredicate;
156 def NoVFP : Predicate<"!Subtarget->hasVFP2()">;
157 def HasVFP2 : Predicate<"Subtarget->hasVFP2()">, AssemblerPredicate;
158 def HasVFP3 : Predicate<"Subtarget->hasVFP3()">, AssemblerPredicate;
159 def HasNEON : Predicate<"Subtarget->hasNEON()">, AssemblerPredicate;
160 def HasFP16 : Predicate<"Subtarget->hasFP16()">, AssemblerPredicate;
161 def HasDivide : Predicate<"Subtarget->hasDivide()">, AssemblerPredicate;
162 def HasT2ExtractPack : Predicate<"Subtarget->hasT2ExtractPack()">,
164 def HasDB : Predicate<"Subtarget->hasDataBarrier()">,
166 def HasMP : Predicate<"Subtarget->hasMPExtension()">,
168 def UseNEONForFP : Predicate<"Subtarget->useNEONForSinglePrecisionFP()">;
169 def DontUseNEONForFP : Predicate<"!Subtarget->useNEONForSinglePrecisionFP()">;
170 def IsThumb : Predicate<"Subtarget->isThumb()">, AssemblerPredicate;
171 def IsThumb1Only : Predicate<"Subtarget->isThumb1Only()">;
172 def IsThumb2 : Predicate<"Subtarget->isThumb2()">, AssemblerPredicate;
173 def IsARM : Predicate<"!Subtarget->isThumb()">, AssemblerPredicate;
174 def IsDarwin : Predicate<"Subtarget->isTargetDarwin()">;
175 def IsNotDarwin : Predicate<"!Subtarget->isTargetDarwin()">;
177 // FIXME: Eventually this will be just "hasV6T2Ops".
178 def UseMovt : Predicate<"Subtarget->useMovt()">;
179 def DontUseMovt : Predicate<"!Subtarget->useMovt()">;
180 def UseFPVMLx : Predicate<"Subtarget->useFPVMLx()">;
182 //===----------------------------------------------------------------------===//
183 // ARM Flag Definitions.
185 class RegConstraint<string C> {
186 string Constraints = C;
189 //===----------------------------------------------------------------------===//
190 // ARM specific transformation functions and pattern fragments.
193 // so_imm_neg_XFORM - Return a so_imm value packed into the format described for
194 // so_imm_neg def below.
195 def so_imm_neg_XFORM : SDNodeXForm<imm, [{
196 return CurDAG->getTargetConstant(-(int)N->getZExtValue(), MVT::i32);
199 // so_imm_not_XFORM - Return a so_imm value packed into the format described for
200 // so_imm_not def below.
201 def so_imm_not_XFORM : SDNodeXForm<imm, [{
202 return CurDAG->getTargetConstant(~(int)N->getZExtValue(), MVT::i32);
205 /// imm1_15 predicate - True if the 32-bit immediate is in the range [1,15].
206 def imm1_15 : PatLeaf<(i32 imm), [{
207 return (int32_t)N->getZExtValue() >= 1 && (int32_t)N->getZExtValue() < 16;
210 /// imm16_31 predicate - True if the 32-bit immediate is in the range [16,31].
211 def imm16_31 : PatLeaf<(i32 imm), [{
212 return (int32_t)N->getZExtValue() >= 16 && (int32_t)N->getZExtValue() < 32;
217 return ARM_AM::getSOImmVal(-(uint32_t)N->getZExtValue()) != -1;
218 }], so_imm_neg_XFORM>;
222 return ARM_AM::getSOImmVal(~(uint32_t)N->getZExtValue()) != -1;
223 }], so_imm_not_XFORM>;
225 // sext_16_node predicate - True if the SDNode is sign-extended 16 or more bits.
226 def sext_16_node : PatLeaf<(i32 GPR:$a), [{
227 return CurDAG->ComputeNumSignBits(SDValue(N,0)) >= 17;
230 /// Split a 32-bit immediate into two 16 bit parts.
231 def hi16 : SDNodeXForm<imm, [{
232 return CurDAG->getTargetConstant((uint32_t)N->getZExtValue() >> 16, MVT::i32);
235 def lo16AllZero : PatLeaf<(i32 imm), [{
236 // Returns true if all low 16-bits are 0.
237 return (((uint32_t)N->getZExtValue()) & 0xFFFFUL) == 0;
240 /// imm0_65535 predicate - True if the 32-bit immediate is in the range
242 def imm0_65535 : PatLeaf<(i32 imm), [{
243 return (uint32_t)N->getZExtValue() < 65536;
246 class BinOpFrag<dag res> : PatFrag<(ops node:$LHS, node:$RHS), res>;
247 class UnOpFrag <dag res> : PatFrag<(ops node:$Src), res>;
249 /// adde and sube predicates - True based on whether the carry flag output
250 /// will be needed or not.
251 def adde_dead_carry :
252 PatFrag<(ops node:$LHS, node:$RHS), (adde node:$LHS, node:$RHS),
253 [{return !N->hasAnyUseOfValue(1);}]>;
254 def sube_dead_carry :
255 PatFrag<(ops node:$LHS, node:$RHS), (sube node:$LHS, node:$RHS),
256 [{return !N->hasAnyUseOfValue(1);}]>;
257 def adde_live_carry :
258 PatFrag<(ops node:$LHS, node:$RHS), (adde node:$LHS, node:$RHS),
259 [{return N->hasAnyUseOfValue(1);}]>;
260 def sube_live_carry :
261 PatFrag<(ops node:$LHS, node:$RHS), (sube node:$LHS, node:$RHS),
262 [{return N->hasAnyUseOfValue(1);}]>;
264 // An 'and' node with a single use.
265 def and_su : PatFrag<(ops node:$lhs, node:$rhs), (and node:$lhs, node:$rhs), [{
266 return N->hasOneUse();
269 // An 'xor' node with a single use.
270 def xor_su : PatFrag<(ops node:$lhs, node:$rhs), (xor node:$lhs, node:$rhs), [{
271 return N->hasOneUse();
274 // An 'fmul' node with a single use.
275 def fmul_su : PatFrag<(ops node:$lhs, node:$rhs), (fmul node:$lhs, node:$rhs),[{
276 return N->hasOneUse();
279 // An 'fadd' node which checks for single non-hazardous use.
280 def fadd_mlx : PatFrag<(ops node:$lhs, node:$rhs),(fadd node:$lhs, node:$rhs),[{
281 return hasNoVMLxHazardUse(N);
284 // An 'fsub' node which checks for single non-hazardous use.
285 def fsub_mlx : PatFrag<(ops node:$lhs, node:$rhs),(fsub node:$lhs, node:$rhs),[{
286 return hasNoVMLxHazardUse(N);
289 //===----------------------------------------------------------------------===//
290 // Operand Definitions.
294 // FIXME: rename brtarget to t2_brtarget
295 def brtarget : Operand<OtherVT> {
296 let EncoderMethod = "getBranchTargetOpValue";
299 // FIXME: get rid of this one?
300 def uncondbrtarget : Operand<OtherVT> {
301 let EncoderMethod = "getUnconditionalBranchTargetOpValue";
304 // Branch target for ARM. Handles conditional/unconditional
305 def br_target : Operand<OtherVT> {
306 let EncoderMethod = "getARMBranchTargetOpValue";
310 // FIXME: rename bltarget to t2_bl_target?
311 def bltarget : Operand<i32> {
312 // Encoded the same as branch targets.
313 let EncoderMethod = "getBranchTargetOpValue";
316 // Call target for ARM. Handles conditional/unconditional
317 // FIXME: rename bl_target to t2_bltarget?
318 def bl_target : Operand<i32> {
319 // Encoded the same as branch targets.
320 let EncoderMethod = "getARMBranchTargetOpValue";
324 // A list of registers separated by comma. Used by load/store multiple.
325 def RegListAsmOperand : AsmOperandClass {
326 let Name = "RegList";
327 let SuperClasses = [];
330 def DPRRegListAsmOperand : AsmOperandClass {
331 let Name = "DPRRegList";
332 let SuperClasses = [];
335 def SPRRegListAsmOperand : AsmOperandClass {
336 let Name = "SPRRegList";
337 let SuperClasses = [];
340 def reglist : Operand<i32> {
341 let EncoderMethod = "getRegisterListOpValue";
342 let ParserMatchClass = RegListAsmOperand;
343 let PrintMethod = "printRegisterList";
346 def dpr_reglist : Operand<i32> {
347 let EncoderMethod = "getRegisterListOpValue";
348 let ParserMatchClass = DPRRegListAsmOperand;
349 let PrintMethod = "printRegisterList";
352 def spr_reglist : Operand<i32> {
353 let EncoderMethod = "getRegisterListOpValue";
354 let ParserMatchClass = SPRRegListAsmOperand;
355 let PrintMethod = "printRegisterList";
358 // An operand for the CONSTPOOL_ENTRY pseudo-instruction.
359 def cpinst_operand : Operand<i32> {
360 let PrintMethod = "printCPInstOperand";
364 def pclabel : Operand<i32> {
365 let PrintMethod = "printPCLabel";
368 // ADR instruction labels.
369 def adrlabel : Operand<i32> {
370 let EncoderMethod = "getAdrLabelOpValue";
373 def neon_vcvt_imm32 : Operand<i32> {
374 let EncoderMethod = "getNEONVcvtImm32OpValue";
377 // rot_imm: An integer that encodes a rotate amount. Must be 8, 16, or 24.
378 def rot_imm : Operand<i32>, PatLeaf<(i32 imm), [{
379 int32_t v = (int32_t)N->getZExtValue();
380 return v == 8 || v == 16 || v == 24; }]> {
381 let EncoderMethod = "getRotImmOpValue";
384 def ShifterAsmOperand : AsmOperandClass {
385 let Name = "Shifter";
386 let SuperClasses = [];
389 // shift_imm: An integer that encodes a shift amount and the type of shift
390 // (currently either asr or lsl) using the same encoding used for the
391 // immediates in so_reg operands.
392 def shift_imm : Operand<i32> {
393 let PrintMethod = "printShiftImmOperand";
394 let ParserMatchClass = ShifterAsmOperand;
397 // shifter_operand operands: so_reg and so_imm.
398 def so_reg : Operand<i32>, // reg reg imm
399 ComplexPattern<i32, 3, "SelectShifterOperandReg",
400 [shl,srl,sra,rotr]> {
401 let EncoderMethod = "getSORegOpValue";
402 let PrintMethod = "printSORegOperand";
403 let MIOperandInfo = (ops GPR, GPR, shift_imm);
405 def shift_so_reg : Operand<i32>, // reg reg imm
406 ComplexPattern<i32, 3, "SelectShiftShifterOperandReg",
407 [shl,srl,sra,rotr]> {
408 let EncoderMethod = "getSORegOpValue";
409 let PrintMethod = "printSORegOperand";
410 let MIOperandInfo = (ops GPR, GPR, shift_imm);
413 // so_imm - Match a 32-bit shifter_operand immediate operand, which is an
414 // 8-bit immediate rotated by an arbitrary number of bits.
415 def so_imm : Operand<i32>, PatLeaf<(imm), [{ return Pred_so_imm(N); }]> {
416 let EncoderMethod = "getSOImmOpValue";
417 let PrintMethod = "printSOImmOperand";
420 // Break so_imm's up into two pieces. This handles immediates with up to 16
421 // bits set in them. This uses so_imm2part to match and so_imm2part_[12] to
422 // get the first/second pieces.
423 def so_imm2part : PatLeaf<(imm), [{
424 return ARM_AM::isSOImmTwoPartVal((unsigned)N->getZExtValue());
427 /// arm_i32imm - True for +V6T2, or true only if so_imm2part is true.
429 def arm_i32imm : PatLeaf<(imm), [{
430 if (Subtarget->hasV6T2Ops())
432 return ARM_AM::isSOImmTwoPartVal((unsigned)N->getZExtValue());
435 /// imm0_31 predicate - True if the 32-bit immediate is in the range [0,31].
436 def imm0_31 : Operand<i32>, PatLeaf<(imm), [{
437 return (int32_t)N->getZExtValue() < 32;
440 /// imm0_31_m1 - Matches and prints like imm0_31, but encodes as 'value - 1'.
441 def imm0_31_m1 : Operand<i32>, PatLeaf<(imm), [{
442 return (int32_t)N->getZExtValue() < 32;
444 let EncoderMethod = "getImmMinusOneOpValue";
447 // i32imm_hilo16 - For movt/movw - sets the MC Encoder method.
448 // The imm is split into imm{15-12}, imm{11-0}
450 def i32imm_hilo16 : Operand<i32> {
451 let EncoderMethod = "getHiLo16ImmOpValue";
454 /// bf_inv_mask_imm predicate - An AND mask to clear an arbitrary width bitfield
456 def bf_inv_mask_imm : Operand<i32>,
458 return ARM::isBitFieldInvertedMask(N->getZExtValue());
460 let EncoderMethod = "getBitfieldInvertedMaskOpValue";
461 let PrintMethod = "printBitfieldInvMaskImmOperand";
464 /// lsb_pos_imm - position of the lsb bit, used by BFI4p and t2BFI4p
465 def lsb_pos_imm : Operand<i32>, PatLeaf<(imm), [{
466 return isInt<5>(N->getSExtValue());
469 /// width_imm - number of bits to be copied, used by BFI4p and t2BFI4p
470 def width_imm : Operand<i32>, PatLeaf<(imm), [{
471 return N->getSExtValue() > 0 && N->getSExtValue() <= 32;
473 let EncoderMethod = "getMsbOpValue";
476 // Define ARM specific addressing modes.
478 def MemMode2AsmOperand : AsmOperandClass {
479 let Name = "MemMode2";
480 let SuperClasses = [];
481 let ParserMethod = "tryParseMemMode2Operand";
484 def MemMode3AsmOperand : AsmOperandClass {
485 let Name = "MemMode3";
486 let SuperClasses = [];
487 let ParserMethod = "tryParseMemMode3Operand";
490 // addrmode_imm12 := reg +/- imm12
492 def addrmode_imm12 : Operand<i32>,
493 ComplexPattern<i32, 2, "SelectAddrModeImm12", []> {
494 // 12-bit immediate operand. Note that instructions using this encode
495 // #0 and #-0 differently. We flag #-0 as the magic value INT32_MIN. All other
496 // immediate values are as normal.
498 let EncoderMethod = "getAddrModeImm12OpValue";
499 let PrintMethod = "printAddrModeImm12Operand";
500 let MIOperandInfo = (ops GPR:$base, i32imm:$offsimm);
502 // ldst_so_reg := reg +/- reg shop imm
504 def ldst_so_reg : Operand<i32>,
505 ComplexPattern<i32, 3, "SelectLdStSOReg", []> {
506 let EncoderMethod = "getLdStSORegOpValue";
507 // FIXME: Simplify the printer
508 let PrintMethod = "printAddrMode2Operand";
509 let MIOperandInfo = (ops GPR:$base, GPR:$offsreg, i32imm:$offsimm);
512 // addrmode2 := reg +/- imm12
513 // := reg +/- reg shop imm
515 def addrmode2 : Operand<i32>,
516 ComplexPattern<i32, 3, "SelectAddrMode2", []> {
517 let EncoderMethod = "getAddrMode2OpValue";
518 let PrintMethod = "printAddrMode2Operand";
519 let ParserMatchClass = MemMode2AsmOperand;
520 let MIOperandInfo = (ops GPR:$base, GPR:$offsreg, i32imm:$offsimm);
523 def am2offset : Operand<i32>,
524 ComplexPattern<i32, 2, "SelectAddrMode2Offset",
525 [], [SDNPWantRoot]> {
526 let EncoderMethod = "getAddrMode2OffsetOpValue";
527 let PrintMethod = "printAddrMode2OffsetOperand";
528 let MIOperandInfo = (ops GPR, i32imm);
531 // addrmode3 := reg +/- reg
532 // addrmode3 := reg +/- imm8
534 def addrmode3 : Operand<i32>,
535 ComplexPattern<i32, 3, "SelectAddrMode3", []> {
536 let EncoderMethod = "getAddrMode3OpValue";
537 let PrintMethod = "printAddrMode3Operand";
538 let ParserMatchClass = MemMode3AsmOperand;
539 let MIOperandInfo = (ops GPR:$base, GPR:$offsreg, i32imm:$offsimm);
542 def am3offset : Operand<i32>,
543 ComplexPattern<i32, 2, "SelectAddrMode3Offset",
544 [], [SDNPWantRoot]> {
545 let EncoderMethod = "getAddrMode3OffsetOpValue";
546 let PrintMethod = "printAddrMode3OffsetOperand";
547 let MIOperandInfo = (ops GPR, i32imm);
550 // ldstm_mode := {ia, ib, da, db}
552 def ldstm_mode : OptionalDefOperand<OtherVT, (ops i32), (ops (i32 1))> {
553 let EncoderMethod = "getLdStmModeOpValue";
554 let PrintMethod = "printLdStmModeOperand";
557 def MemMode5AsmOperand : AsmOperandClass {
558 let Name = "MemMode5";
559 let SuperClasses = [];
562 // addrmode5 := reg +/- imm8*4
564 def addrmode5 : Operand<i32>,
565 ComplexPattern<i32, 2, "SelectAddrMode5", []> {
566 let PrintMethod = "printAddrMode5Operand";
567 let MIOperandInfo = (ops GPR:$base, i32imm);
568 let ParserMatchClass = MemMode5AsmOperand;
569 let EncoderMethod = "getAddrMode5OpValue";
572 // addrmode6 := reg with optional alignment
574 def addrmode6 : Operand<i32>,
575 ComplexPattern<i32, 2, "SelectAddrMode6", [], [SDNPWantParent]>{
576 let PrintMethod = "printAddrMode6Operand";
577 let MIOperandInfo = (ops GPR:$addr, i32imm);
578 let EncoderMethod = "getAddrMode6AddressOpValue";
581 def am6offset : Operand<i32>,
582 ComplexPattern<i32, 1, "SelectAddrMode6Offset",
583 [], [SDNPWantRoot]> {
584 let PrintMethod = "printAddrMode6OffsetOperand";
585 let MIOperandInfo = (ops GPR);
586 let EncoderMethod = "getAddrMode6OffsetOpValue";
589 // Special version of addrmode6 to handle alignment encoding for VLD-dup
590 // instructions, specifically VLD4-dup.
591 def addrmode6dup : Operand<i32>,
592 ComplexPattern<i32, 2, "SelectAddrMode6", [], [SDNPWantParent]>{
593 let PrintMethod = "printAddrMode6Operand";
594 let MIOperandInfo = (ops GPR:$addr, i32imm);
595 let EncoderMethod = "getAddrMode6DupAddressOpValue";
598 // addrmodepc := pc + reg
600 def addrmodepc : Operand<i32>,
601 ComplexPattern<i32, 2, "SelectAddrModePC", []> {
602 let PrintMethod = "printAddrModePCOperand";
603 let MIOperandInfo = (ops GPR, i32imm);
606 def MemMode7AsmOperand : AsmOperandClass {
607 let Name = "MemMode7";
608 let SuperClasses = [];
612 // Used by load/store exclusive instructions. Useful to enable right assembly
613 // parsing and printing. Not used for any codegen matching.
615 def addrmode7 : Operand<i32> {
616 let PrintMethod = "printAddrMode7Operand";
617 let MIOperandInfo = (ops GPR);
618 let ParserMatchClass = MemMode7AsmOperand;
621 def nohash_imm : Operand<i32> {
622 let PrintMethod = "printNoHashImmediate";
625 def CoprocNumAsmOperand : AsmOperandClass {
626 let Name = "CoprocNum";
627 let SuperClasses = [];
628 let ParserMethod = "tryParseCoprocNumOperand";
631 def CoprocRegAsmOperand : AsmOperandClass {
632 let Name = "CoprocReg";
633 let SuperClasses = [];
634 let ParserMethod = "tryParseCoprocRegOperand";
637 def p_imm : Operand<i32> {
638 let PrintMethod = "printPImmediate";
639 let ParserMatchClass = CoprocNumAsmOperand;
642 def c_imm : Operand<i32> {
643 let PrintMethod = "printCImmediate";
644 let ParserMatchClass = CoprocRegAsmOperand;
647 //===----------------------------------------------------------------------===//
649 include "ARMInstrFormats.td"
651 //===----------------------------------------------------------------------===//
652 // Multiclass helpers...
655 /// AsI1_bin_irs - Defines a set of (op r, {so_imm|r|so_reg}) patterns for a
656 /// binop that produces a value.
657 multiclass AsI1_bin_irs<bits<4> opcod, string opc,
658 InstrItinClass iii, InstrItinClass iir, InstrItinClass iis,
659 PatFrag opnode, bit Commutable = 0> {
660 // The register-immediate version is re-materializable. This is useful
661 // in particular for taking the address of a local.
662 let isReMaterializable = 1 in {
663 def ri : AsI1<opcod, (outs GPR:$Rd), (ins GPR:$Rn, so_imm:$imm), DPFrm,
664 iii, opc, "\t$Rd, $Rn, $imm",
665 [(set GPR:$Rd, (opnode GPR:$Rn, so_imm:$imm))]> {
670 let Inst{19-16} = Rn;
671 let Inst{15-12} = Rd;
672 let Inst{11-0} = imm;
675 def rr : AsI1<opcod, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm), DPFrm,
676 iir, opc, "\t$Rd, $Rn, $Rm",
677 [(set GPR:$Rd, (opnode GPR:$Rn, GPR:$Rm))]> {
682 let isCommutable = Commutable;
683 let Inst{19-16} = Rn;
684 let Inst{15-12} = Rd;
685 let Inst{11-4} = 0b00000000;
688 def rs : AsI1<opcod, (outs GPR:$Rd), (ins GPR:$Rn, so_reg:$shift), DPSoRegFrm,
689 iis, opc, "\t$Rd, $Rn, $shift",
690 [(set GPR:$Rd, (opnode GPR:$Rn, so_reg:$shift))]> {
695 let Inst{19-16} = Rn;
696 let Inst{15-12} = Rd;
697 let Inst{11-0} = shift;
701 /// AI1_bin_s_irs - Similar to AsI1_bin_irs except it sets the 's' bit so the
702 /// instruction modifies the CPSR register.
703 let isCodeGenOnly = 1, Defs = [CPSR] in {
704 multiclass AI1_bin_s_irs<bits<4> opcod, string opc,
705 InstrItinClass iii, InstrItinClass iir, InstrItinClass iis,
706 PatFrag opnode, bit Commutable = 0> {
707 def ri : AI1<opcod, (outs GPR:$Rd), (ins GPR:$Rn, so_imm:$imm), DPFrm,
708 iii, opc, "\t$Rd, $Rn, $imm",
709 [(set GPR:$Rd, (opnode GPR:$Rn, so_imm:$imm))]> {
715 let Inst{19-16} = Rn;
716 let Inst{15-12} = Rd;
717 let Inst{11-0} = imm;
719 def rr : AI1<opcod, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm), DPFrm,
720 iir, opc, "\t$Rd, $Rn, $Rm",
721 [(set GPR:$Rd, (opnode GPR:$Rn, GPR:$Rm))]> {
725 let isCommutable = Commutable;
728 let Inst{19-16} = Rn;
729 let Inst{15-12} = Rd;
730 let Inst{11-4} = 0b00000000;
733 def rs : AI1<opcod, (outs GPR:$Rd), (ins GPR:$Rn, so_reg:$shift), DPSoRegFrm,
734 iis, opc, "\t$Rd, $Rn, $shift",
735 [(set GPR:$Rd, (opnode GPR:$Rn, so_reg:$shift))]> {
741 let Inst{19-16} = Rn;
742 let Inst{15-12} = Rd;
743 let Inst{11-0} = shift;
748 /// AI1_cmp_irs - Defines a set of (op r, {so_imm|r|so_reg}) cmp / test
749 /// patterns. Similar to AsI1_bin_irs except the instruction does not produce
750 /// a explicit result, only implicitly set CPSR.
751 let isCompare = 1, Defs = [CPSR] in {
752 multiclass AI1_cmp_irs<bits<4> opcod, string opc,
753 InstrItinClass iii, InstrItinClass iir, InstrItinClass iis,
754 PatFrag opnode, bit Commutable = 0> {
755 def ri : AI1<opcod, (outs), (ins GPR:$Rn, so_imm:$imm), DPFrm, iii,
757 [(opnode GPR:$Rn, so_imm:$imm)]> {
762 let Inst{19-16} = Rn;
763 let Inst{15-12} = 0b0000;
764 let Inst{11-0} = imm;
766 def rr : AI1<opcod, (outs), (ins GPR:$Rn, GPR:$Rm), DPFrm, iir,
768 [(opnode GPR:$Rn, GPR:$Rm)]> {
771 let isCommutable = Commutable;
774 let Inst{19-16} = Rn;
775 let Inst{15-12} = 0b0000;
776 let Inst{11-4} = 0b00000000;
779 def rs : AI1<opcod, (outs), (ins GPR:$Rn, so_reg:$shift), DPSoRegFrm, iis,
780 opc, "\t$Rn, $shift",
781 [(opnode GPR:$Rn, so_reg:$shift)]> {
786 let Inst{19-16} = Rn;
787 let Inst{15-12} = 0b0000;
788 let Inst{11-0} = shift;
793 /// AI_ext_rrot - A unary operation with two forms: one whose operand is a
794 /// register and one whose operand is a register rotated by 8/16/24.
795 /// FIXME: Remove the 'r' variant. Its rot_imm is zero.
796 multiclass AI_ext_rrot<bits<8> opcod, string opc, PatFrag opnode> {
797 def r : AExtI<opcod, (outs GPR:$Rd), (ins GPR:$Rm),
798 IIC_iEXTr, opc, "\t$Rd, $Rm",
799 [(set GPR:$Rd, (opnode GPR:$Rm))]>,
800 Requires<[IsARM, HasV6]> {
803 let Inst{19-16} = 0b1111;
804 let Inst{15-12} = Rd;
805 let Inst{11-10} = 0b00;
808 def r_rot : AExtI<opcod, (outs GPR:$Rd), (ins GPR:$Rm, rot_imm:$rot),
809 IIC_iEXTr, opc, "\t$Rd, $Rm, ror $rot",
810 [(set GPR:$Rd, (opnode (rotr GPR:$Rm, rot_imm:$rot)))]>,
811 Requires<[IsARM, HasV6]> {
815 let Inst{19-16} = 0b1111;
816 let Inst{15-12} = Rd;
817 let Inst{11-10} = rot;
822 multiclass AI_ext_rrot_np<bits<8> opcod, string opc> {
823 def r : AExtI<opcod, (outs GPR:$Rd), (ins GPR:$Rm),
824 IIC_iEXTr, opc, "\t$Rd, $Rm",
825 [/* For disassembly only; pattern left blank */]>,
826 Requires<[IsARM, HasV6]> {
827 let Inst{19-16} = 0b1111;
828 let Inst{11-10} = 0b00;
830 def r_rot : AExtI<opcod, (outs GPR:$Rd), (ins GPR:$Rm, rot_imm:$rot),
831 IIC_iEXTr, opc, "\t$Rd, $Rm, ror $rot",
832 [/* For disassembly only; pattern left blank */]>,
833 Requires<[IsARM, HasV6]> {
835 let Inst{19-16} = 0b1111;
836 let Inst{11-10} = rot;
840 /// AI_exta_rrot - A binary operation with two forms: one whose operand is a
841 /// register and one whose operand is a register rotated by 8/16/24.
842 multiclass AI_exta_rrot<bits<8> opcod, string opc, PatFrag opnode> {
843 def rr : AExtI<opcod, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm),
844 IIC_iEXTAr, opc, "\t$Rd, $Rn, $Rm",
845 [(set GPR:$Rd, (opnode GPR:$Rn, GPR:$Rm))]>,
846 Requires<[IsARM, HasV6]> {
850 let Inst{19-16} = Rn;
851 let Inst{15-12} = Rd;
852 let Inst{11-10} = 0b00;
853 let Inst{9-4} = 0b000111;
856 def rr_rot : AExtI<opcod, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm,
858 IIC_iEXTAr, opc, "\t$Rd, $Rn, $Rm, ror $rot",
859 [(set GPR:$Rd, (opnode GPR:$Rn,
860 (rotr GPR:$Rm, rot_imm:$rot)))]>,
861 Requires<[IsARM, HasV6]> {
866 let Inst{19-16} = Rn;
867 let Inst{15-12} = Rd;
868 let Inst{11-10} = rot;
869 let Inst{9-4} = 0b000111;
874 // For disassembly only.
875 multiclass AI_exta_rrot_np<bits<8> opcod, string opc> {
876 def rr : AExtI<opcod, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm),
877 IIC_iEXTAr, opc, "\t$Rd, $Rn, $Rm",
878 [/* For disassembly only; pattern left blank */]>,
879 Requires<[IsARM, HasV6]> {
880 let Inst{11-10} = 0b00;
882 def rr_rot : AExtI<opcod, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm,
884 IIC_iEXTAr, opc, "\t$Rd, $Rn, $Rm, ror $rot",
885 [/* For disassembly only; pattern left blank */]>,
886 Requires<[IsARM, HasV6]> {
889 let Inst{19-16} = Rn;
890 let Inst{11-10} = rot;
894 /// AI1_adde_sube_irs - Define instructions and patterns for adde and sube.
895 let Uses = [CPSR] in {
896 multiclass AI1_adde_sube_irs<bits<4> opcod, string opc, PatFrag opnode,
897 bit Commutable = 0> {
898 def ri : AsI1<opcod, (outs GPR:$Rd), (ins GPR:$Rn, so_imm:$imm),
899 DPFrm, IIC_iALUi, opc, "\t$Rd, $Rn, $imm",
900 [(set GPR:$Rd, (opnode GPR:$Rn, so_imm:$imm))]>,
906 let Inst{15-12} = Rd;
907 let Inst{19-16} = Rn;
908 let Inst{11-0} = imm;
910 def rr : AsI1<opcod, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm),
911 DPFrm, IIC_iALUr, opc, "\t$Rd, $Rn, $Rm",
912 [(set GPR:$Rd, (opnode GPR:$Rn, GPR:$Rm))]>,
917 let Inst{11-4} = 0b00000000;
919 let isCommutable = Commutable;
921 let Inst{15-12} = Rd;
922 let Inst{19-16} = Rn;
924 def rs : AsI1<opcod, (outs GPR:$Rd), (ins GPR:$Rn, so_reg:$shift),
925 DPSoRegFrm, IIC_iALUsr, opc, "\t$Rd, $Rn, $shift",
926 [(set GPR:$Rd, (opnode GPR:$Rn, so_reg:$shift))]>,
932 let Inst{11-0} = shift;
933 let Inst{15-12} = Rd;
934 let Inst{19-16} = Rn;
937 // Carry setting variants
938 let isCodeGenOnly = 1, Defs = [CPSR] in {
939 multiclass AI1_adde_sube_s_irs<bits<4> opcod, string opc, PatFrag opnode,
940 bit Commutable = 0> {
941 def Sri : ARMPseudoInst<(outs GPR:$Rd), (ins GPR:$Rn, so_imm:$imm),
942 Size4Bytes, IIC_iALUi,
943 [(set GPR:$Rd, (opnode GPR:$Rn, so_imm:$imm))]>,
945 def Srr : ARMPseudoInst<(outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm),
946 Size4Bytes, IIC_iALUr,
947 [(set GPR:$Rd, (opnode GPR:$Rn, GPR:$Rm))]>,
949 def Srs : ARMPseudoInst<(outs GPR:$Rd), (ins GPR:$Rn, so_reg:$shift),
950 Size4Bytes, IIC_iALUsr,
951 [(set GPR:$Rd, (opnode GPR:$Rn, so_reg:$shift))]>,
957 let canFoldAsLoad = 1, isReMaterializable = 1 in {
958 multiclass AI_ldr1<bit isByte, string opc, InstrItinClass iii,
959 InstrItinClass iir, PatFrag opnode> {
960 // Note: We use the complex addrmode_imm12 rather than just an input
961 // GPR and a constrained immediate so that we can use this to match
962 // frame index references and avoid matching constant pool references.
963 def i12: AI2ldst<0b010, 1, isByte, (outs GPR:$Rt), (ins addrmode_imm12:$addr),
964 AddrMode_i12, LdFrm, iii, opc, "\t$Rt, $addr",
965 [(set GPR:$Rt, (opnode addrmode_imm12:$addr))]> {
968 let Inst{23} = addr{12}; // U (add = ('U' == 1))
969 let Inst{19-16} = addr{16-13}; // Rn
970 let Inst{15-12} = Rt;
971 let Inst{11-0} = addr{11-0}; // imm12
973 def rs : AI2ldst<0b011, 1, isByte, (outs GPR:$Rt), (ins ldst_so_reg:$shift),
974 AddrModeNone, LdFrm, iir, opc, "\t$Rt, $shift",
975 [(set GPR:$Rt, (opnode ldst_so_reg:$shift))]> {
978 let shift{4} = 0; // Inst{4} = 0
979 let Inst{23} = shift{12}; // U (add = ('U' == 1))
980 let Inst{19-16} = shift{16-13}; // Rn
981 let Inst{15-12} = Rt;
982 let Inst{11-0} = shift{11-0};
987 multiclass AI_str1<bit isByte, string opc, InstrItinClass iii,
988 InstrItinClass iir, PatFrag opnode> {
989 // Note: We use the complex addrmode_imm12 rather than just an input
990 // GPR and a constrained immediate so that we can use this to match
991 // frame index references and avoid matching constant pool references.
992 def i12 : AI2ldst<0b010, 0, isByte, (outs),
993 (ins GPR:$Rt, addrmode_imm12:$addr),
994 AddrMode_i12, StFrm, iii, opc, "\t$Rt, $addr",
995 [(opnode GPR:$Rt, addrmode_imm12:$addr)]> {
998 let Inst{23} = addr{12}; // U (add = ('U' == 1))
999 let Inst{19-16} = addr{16-13}; // Rn
1000 let Inst{15-12} = Rt;
1001 let Inst{11-0} = addr{11-0}; // imm12
1003 def rs : AI2ldst<0b011, 0, isByte, (outs), (ins GPR:$Rt, ldst_so_reg:$shift),
1004 AddrModeNone, StFrm, iir, opc, "\t$Rt, $shift",
1005 [(opnode GPR:$Rt, ldst_so_reg:$shift)]> {
1008 let shift{4} = 0; // Inst{4} = 0
1009 let Inst{23} = shift{12}; // U (add = ('U' == 1))
1010 let Inst{19-16} = shift{16-13}; // Rn
1011 let Inst{15-12} = Rt;
1012 let Inst{11-0} = shift{11-0};
1015 //===----------------------------------------------------------------------===//
1017 //===----------------------------------------------------------------------===//
1019 //===----------------------------------------------------------------------===//
1020 // Miscellaneous Instructions.
1023 /// CONSTPOOL_ENTRY - This instruction represents a floating constant pool in
1024 /// the function. The first operand is the ID# for this instruction, the second
1025 /// is the index into the MachineConstantPool that this is, the third is the
1026 /// size in bytes of this constant pool entry.
1027 let neverHasSideEffects = 1, isNotDuplicable = 1 in
1028 def CONSTPOOL_ENTRY :
1029 PseudoInst<(outs), (ins cpinst_operand:$instid, cpinst_operand:$cpidx,
1030 i32imm:$size), NoItinerary, []>;
1032 // FIXME: Marking these as hasSideEffects is necessary to prevent machine DCE
1033 // from removing one half of the matched pairs. That breaks PEI, which assumes
1034 // these will always be in pairs, and asserts if it finds otherwise. Better way?
1035 let Defs = [SP], Uses = [SP], hasSideEffects = 1 in {
1036 def ADJCALLSTACKUP :
1037 PseudoInst<(outs), (ins i32imm:$amt1, i32imm:$amt2, pred:$p), NoItinerary,
1038 [(ARMcallseq_end timm:$amt1, timm:$amt2)]>;
1040 def ADJCALLSTACKDOWN :
1041 PseudoInst<(outs), (ins i32imm:$amt, pred:$p), NoItinerary,
1042 [(ARMcallseq_start timm:$amt)]>;
1045 def NOP : AI<(outs), (ins), MiscFrm, NoItinerary, "nop", "",
1046 [/* For disassembly only; pattern left blank */]>,
1047 Requires<[IsARM, HasV6T2]> {
1048 let Inst{27-16} = 0b001100100000;
1049 let Inst{15-8} = 0b11110000;
1050 let Inst{7-0} = 0b00000000;
1053 def YIELD : AI<(outs), (ins), MiscFrm, NoItinerary, "yield", "",
1054 [/* For disassembly only; pattern left blank */]>,
1055 Requires<[IsARM, HasV6T2]> {
1056 let Inst{27-16} = 0b001100100000;
1057 let Inst{15-8} = 0b11110000;
1058 let Inst{7-0} = 0b00000001;
1061 def WFE : AI<(outs), (ins), MiscFrm, NoItinerary, "wfe", "",
1062 [/* For disassembly only; pattern left blank */]>,
1063 Requires<[IsARM, HasV6T2]> {
1064 let Inst{27-16} = 0b001100100000;
1065 let Inst{15-8} = 0b11110000;
1066 let Inst{7-0} = 0b00000010;
1069 def WFI : AI<(outs), (ins), MiscFrm, NoItinerary, "wfi", "",
1070 [/* For disassembly only; pattern left blank */]>,
1071 Requires<[IsARM, HasV6T2]> {
1072 let Inst{27-16} = 0b001100100000;
1073 let Inst{15-8} = 0b11110000;
1074 let Inst{7-0} = 0b00000011;
1077 def SEL : AI<(outs GPR:$dst), (ins GPR:$a, GPR:$b), DPFrm, NoItinerary, "sel",
1079 [/* For disassembly only; pattern left blank */]>,
1080 Requires<[IsARM, HasV6]> {
1085 let Inst{15-12} = Rd;
1086 let Inst{19-16} = Rn;
1087 let Inst{27-20} = 0b01101000;
1088 let Inst{7-4} = 0b1011;
1089 let Inst{11-8} = 0b1111;
1092 def SEV : AI<(outs), (ins), MiscFrm, NoItinerary, "sev", "",
1093 [/* For disassembly only; pattern left blank */]>,
1094 Requires<[IsARM, HasV6T2]> {
1095 let Inst{27-16} = 0b001100100000;
1096 let Inst{15-8} = 0b11110000;
1097 let Inst{7-0} = 0b00000100;
1100 // The i32imm operand $val can be used by a debugger to store more information
1101 // about the breakpoint.
1102 def BKPT : AI<(outs), (ins i32imm:$val), MiscFrm, NoItinerary, "bkpt", "\t$val",
1103 [/* For disassembly only; pattern left blank */]>,
1106 let Inst{3-0} = val{3-0};
1107 let Inst{19-8} = val{15-4};
1108 let Inst{27-20} = 0b00010010;
1109 let Inst{7-4} = 0b0111;
1112 // Change Processor State is a system instruction -- for disassembly and
1114 // FIXME: Since the asm parser has currently no clean way to handle optional
1115 // operands, create 3 versions of the same instruction. Once there's a clean
1116 // framework to represent optional operands, change this behavior.
1117 class CPS<dag iops, string asm_ops>
1118 : AXI<(outs), iops, MiscFrm, NoItinerary, !strconcat("cps", asm_ops),
1119 [/* For disassembly only; pattern left blank */]>, Requires<[IsARM]> {
1125 let Inst{31-28} = 0b1111;
1126 let Inst{27-20} = 0b00010000;
1127 let Inst{19-18} = imod;
1128 let Inst{17} = M; // Enabled if mode is set;
1130 let Inst{8-6} = iflags;
1132 let Inst{4-0} = mode;
1136 def CPS3p : CPS<(ins imod_op:$imod, iflags_op:$iflags, i32imm:$mode),
1137 "$imod\t$iflags, $mode">;
1138 let mode = 0, M = 0 in
1139 def CPS2p : CPS<(ins imod_op:$imod, iflags_op:$iflags), "$imod\t$iflags">;
1141 let imod = 0, iflags = 0, M = 1 in
1142 def CPS1p : CPS<(ins i32imm:$mode), "\t$mode">;
1144 // Preload signals the memory system of possible future data/instruction access.
1145 // These are for disassembly only.
1146 multiclass APreLoad<bits<1> read, bits<1> data, string opc> {
1148 def i12 : AXI<(outs), (ins addrmode_imm12:$addr), MiscFrm, IIC_Preload,
1149 !strconcat(opc, "\t$addr"),
1150 [(ARMPreload addrmode_imm12:$addr, (i32 read), (i32 data))]> {
1153 let Inst{31-26} = 0b111101;
1154 let Inst{25} = 0; // 0 for immediate form
1155 let Inst{24} = data;
1156 let Inst{23} = addr{12}; // U (add = ('U' == 1))
1157 let Inst{22} = read;
1158 let Inst{21-20} = 0b01;
1159 let Inst{19-16} = addr{16-13}; // Rn
1160 let Inst{15-12} = 0b1111;
1161 let Inst{11-0} = addr{11-0}; // imm12
1164 def rs : AXI<(outs), (ins ldst_so_reg:$shift), MiscFrm, IIC_Preload,
1165 !strconcat(opc, "\t$shift"),
1166 [(ARMPreload ldst_so_reg:$shift, (i32 read), (i32 data))]> {
1168 let Inst{31-26} = 0b111101;
1169 let Inst{25} = 1; // 1 for register form
1170 let Inst{24} = data;
1171 let Inst{23} = shift{12}; // U (add = ('U' == 1))
1172 let Inst{22} = read;
1173 let Inst{21-20} = 0b01;
1174 let Inst{19-16} = shift{16-13}; // Rn
1175 let Inst{15-12} = 0b1111;
1176 let Inst{11-0} = shift{11-0};
1180 defm PLD : APreLoad<1, 1, "pld">, Requires<[IsARM]>;
1181 defm PLDW : APreLoad<0, 1, "pldw">, Requires<[IsARM,HasV7,HasMP]>;
1182 defm PLI : APreLoad<1, 0, "pli">, Requires<[IsARM,HasV7]>;
1184 def SETEND : AXI<(outs),(ins setend_op:$end), MiscFrm, NoItinerary,
1186 [/* For disassembly only; pattern left blank */]>,
1189 let Inst{31-10} = 0b1111000100000001000000;
1194 def DBG : AI<(outs), (ins i32imm:$opt), MiscFrm, NoItinerary, "dbg", "\t$opt",
1195 [/* For disassembly only; pattern left blank */]>,
1196 Requires<[IsARM, HasV7]> {
1198 let Inst{27-4} = 0b001100100000111100001111;
1199 let Inst{3-0} = opt;
1202 // A5.4 Permanently UNDEFINED instructions.
1203 let isBarrier = 1, isTerminator = 1 in
1204 def TRAP : AXI<(outs), (ins), MiscFrm, NoItinerary,
1207 let Inst = 0xe7ffdefe;
1210 // Address computation and loads and stores in PIC mode.
1211 let isNotDuplicable = 1 in {
1212 def PICADD : ARMPseudoInst<(outs GPR:$dst), (ins GPR:$a, pclabel:$cp, pred:$p),
1213 Size4Bytes, IIC_iALUr,
1214 [(set GPR:$dst, (ARMpic_add GPR:$a, imm:$cp))]>;
1216 let AddedComplexity = 10 in {
1217 def PICLDR : ARMPseudoInst<(outs GPR:$dst), (ins addrmodepc:$addr, pred:$p),
1218 Size4Bytes, IIC_iLoad_r,
1219 [(set GPR:$dst, (load addrmodepc:$addr))]>;
1221 def PICLDRH : ARMPseudoInst<(outs GPR:$Rt), (ins addrmodepc:$addr, pred:$p),
1222 Size4Bytes, IIC_iLoad_bh_r,
1223 [(set GPR:$Rt, (zextloadi16 addrmodepc:$addr))]>;
1225 def PICLDRB : ARMPseudoInst<(outs GPR:$Rt), (ins addrmodepc:$addr, pred:$p),
1226 Size4Bytes, IIC_iLoad_bh_r,
1227 [(set GPR:$Rt, (zextloadi8 addrmodepc:$addr))]>;
1229 def PICLDRSH : ARMPseudoInst<(outs GPR:$Rt), (ins addrmodepc:$addr, pred:$p),
1230 Size4Bytes, IIC_iLoad_bh_r,
1231 [(set GPR:$Rt, (sextloadi16 addrmodepc:$addr))]>;
1233 def PICLDRSB : ARMPseudoInst<(outs GPR:$Rt), (ins addrmodepc:$addr, pred:$p),
1234 Size4Bytes, IIC_iLoad_bh_r,
1235 [(set GPR:$Rt, (sextloadi8 addrmodepc:$addr))]>;
1237 let AddedComplexity = 10 in {
1238 def PICSTR : ARMPseudoInst<(outs), (ins GPR:$src, addrmodepc:$addr, pred:$p),
1239 Size4Bytes, IIC_iStore_r, [(store GPR:$src, addrmodepc:$addr)]>;
1241 def PICSTRH : ARMPseudoInst<(outs), (ins GPR:$src, addrmodepc:$addr, pred:$p),
1242 Size4Bytes, IIC_iStore_bh_r, [(truncstorei16 GPR:$src,
1243 addrmodepc:$addr)]>;
1245 def PICSTRB : ARMPseudoInst<(outs), (ins GPR:$src, addrmodepc:$addr, pred:$p),
1246 Size4Bytes, IIC_iStore_bh_r, [(truncstorei8 GPR:$src, addrmodepc:$addr)]>;
1248 } // isNotDuplicable = 1
1251 // LEApcrel - Load a pc-relative address into a register without offending the
1253 let neverHasSideEffects = 1, isReMaterializable = 1 in
1254 // The 'adr' mnemonic encodes differently if the label is before or after
1255 // the instruction. The {24-21} opcode bits are set by the fixup, as we don't
1256 // know until then which form of the instruction will be used.
1257 def ADR : AI1<{0,?,?,0}, (outs GPR:$Rd), (ins adrlabel:$label),
1258 MiscFrm, IIC_iALUi, "adr", "\t$Rd, #$label", []> {
1261 let Inst{27-25} = 0b001;
1263 let Inst{19-16} = 0b1111;
1264 let Inst{15-12} = Rd;
1265 let Inst{11-0} = label;
1267 def LEApcrel : ARMPseudoInst<(outs GPR:$Rd), (ins i32imm:$label, pred:$p),
1268 Size4Bytes, IIC_iALUi, []>;
1270 def LEApcrelJT : ARMPseudoInst<(outs GPR:$Rd),
1271 (ins i32imm:$label, nohash_imm:$id, pred:$p),
1272 Size4Bytes, IIC_iALUi, []>;
1274 //===----------------------------------------------------------------------===//
1275 // Control Flow Instructions.
1278 let isReturn = 1, isTerminator = 1, isBarrier = 1 in {
1280 def BX_RET : AI<(outs), (ins), BrMiscFrm, IIC_Br,
1281 "bx", "\tlr", [(ARMretflag)]>,
1282 Requires<[IsARM, HasV4T]> {
1283 let Inst{27-0} = 0b0001001011111111111100011110;
1287 def MOVPCLR : AI<(outs), (ins), BrMiscFrm, IIC_Br,
1288 "mov", "\tpc, lr", [(ARMretflag)]>,
1289 Requires<[IsARM, NoV4T]> {
1290 let Inst{27-0} = 0b0001101000001111000000001110;
1294 // Indirect branches
1295 let isBranch = 1, isTerminator = 1, isBarrier = 1, isIndirectBranch = 1 in {
1297 def BX : AXI<(outs), (ins GPR:$dst), BrMiscFrm, IIC_Br, "bx\t$dst",
1298 [(brind GPR:$dst)]>,
1299 Requires<[IsARM, HasV4T]> {
1301 let Inst{31-4} = 0b1110000100101111111111110001;
1302 let Inst{3-0} = dst;
1306 // FIXME: We would really like to define this as a vanilla ARMPat like:
1307 // ARMPat<(brind GPR:$dst), (MOVr PC, GPR:$dst)>
1308 // With that, however, we can't set isBranch, isTerminator, etc..
1309 def MOVPCRX : ARMPseudoInst<(outs), (ins GPR:$dst),
1310 Size4Bytes, IIC_Br, [(brind GPR:$dst)]>,
1311 Requires<[IsARM, NoV4T]>;
1314 // All calls clobber the non-callee saved registers. SP is marked as
1315 // a use to prevent stack-pointer assignments that appear immediately
1316 // before calls from potentially appearing dead.
1318 // On non-Darwin platforms R9 is callee-saved.
1319 // FIXME: Do we really need a non-predicated version? If so, it should
1320 // at least be a pseudo instruction expanding to the predicated version
1321 // at MC lowering time.
1322 Defs = [R0, R1, R2, R3, R12, LR,
1323 D0, D1, D2, D3, D4, D5, D6, D7,
1324 D16, D17, D18, D19, D20, D21, D22, D23,
1325 D24, D25, D26, D27, D28, D29, D30, D31, CPSR, FPSCR],
1327 def BL : ABXI<0b1011, (outs), (ins bl_target:$func, variable_ops),
1328 IIC_Br, "bl\t$func",
1329 [(ARMcall tglobaladdr:$func)]>,
1330 Requires<[IsARM, IsNotDarwin]> {
1331 let Inst{31-28} = 0b1110;
1333 let Inst{23-0} = func;
1336 def BL_pred : ABI<0b1011, (outs), (ins bl_target:$func, variable_ops),
1337 IIC_Br, "bl", "\t$func",
1338 [(ARMcall_pred tglobaladdr:$func)]>,
1339 Requires<[IsARM, IsNotDarwin]> {
1341 let Inst{23-0} = func;
1345 def BLX : AXI<(outs), (ins GPR:$func, variable_ops), BrMiscFrm,
1346 IIC_Br, "blx\t$func",
1347 [(ARMcall GPR:$func)]>,
1348 Requires<[IsARM, HasV5T, IsNotDarwin]> {
1350 let Inst{31-4} = 0b1110000100101111111111110011;
1351 let Inst{3-0} = func;
1354 def BLX_pred : AI<(outs), (ins GPR:$func, variable_ops), BrMiscFrm,
1355 IIC_Br, "blx", "\t$func",
1356 [(ARMcall_pred GPR:$func)]>,
1357 Requires<[IsARM, HasV5T, IsNotDarwin]> {
1359 let Inst{27-4} = 0b000100101111111111110011;
1360 let Inst{3-0} = func;
1364 // Note: Restrict $func to the tGPR regclass to prevent it being in LR.
1365 def BX_CALL : ARMPseudoInst<(outs), (ins tGPR:$func, variable_ops),
1366 Size8Bytes, IIC_Br, [(ARMcall_nolink tGPR:$func)]>,
1367 Requires<[IsARM, HasV4T, IsNotDarwin]>;
1370 def BMOVPCRX_CALL : ARMPseudoInst<(outs), (ins tGPR:$func, variable_ops),
1371 Size8Bytes, IIC_Br, [(ARMcall_nolink tGPR:$func)]>,
1372 Requires<[IsARM, NoV4T, IsNotDarwin]>;
1376 // On Darwin R9 is call-clobbered.
1377 // R7 is marked as a use to prevent frame-pointer assignments from being
1378 // moved above / below calls.
1379 Defs = [R0, R1, R2, R3, R9, R12, LR,
1380 D0, D1, D2, D3, D4, D5, D6, D7,
1381 D16, D17, D18, D19, D20, D21, D22, D23,
1382 D24, D25, D26, D27, D28, D29, D30, D31, CPSR, FPSCR],
1383 Uses = [R7, SP] in {
1384 def BLr9 : ARMPseudoInst<(outs), (ins bltarget:$func, variable_ops),
1386 [(ARMcall tglobaladdr:$func)]>, Requires<[IsARM, IsDarwin]>;
1388 def BLr9_pred : ARMPseudoInst<(outs),
1389 (ins bltarget:$func, pred:$p, variable_ops),
1391 [(ARMcall_pred tglobaladdr:$func)]>,
1392 Requires<[IsARM, IsDarwin]>;
1395 def BLXr9 : ARMPseudoInst<(outs), (ins GPR:$func, variable_ops),
1397 [(ARMcall GPR:$func)]>, Requires<[IsARM, HasV5T, IsDarwin]>;
1399 def BLXr9_pred: ARMPseudoInst<(outs), (ins GPR:$func, pred:$p, variable_ops),
1401 [(ARMcall_pred GPR:$func)]>,
1402 Requires<[IsARM, HasV5T, IsDarwin]>;
1405 // Note: Restrict $func to the tGPR regclass to prevent it being in LR.
1406 def BXr9_CALL : ARMPseudoInst<(outs), (ins tGPR:$func, variable_ops),
1407 Size8Bytes, IIC_Br, [(ARMcall_nolink tGPR:$func)]>,
1408 Requires<[IsARM, HasV4T, IsDarwin]>;
1411 def BMOVPCRXr9_CALL : ARMPseudoInst<(outs), (ins tGPR:$func, variable_ops),
1412 Size8Bytes, IIC_Br, [(ARMcall_nolink tGPR:$func)]>,
1413 Requires<[IsARM, NoV4T, IsDarwin]>;
1418 // FIXME: The Thumb versions of these should live in ARMInstrThumb.td
1419 let isCall = 1, isTerminator = 1, isReturn = 1, isBarrier = 1 in {
1421 let Defs = [R0, R1, R2, R3, R9, R12,
1422 D0, D1, D2, D3, D4, D5, D6, D7,
1423 D16, D17, D18, D19, D20, D21, D22, D23, D24, D25, D26,
1424 D27, D28, D29, D30, D31, PC],
1426 def TCRETURNdi : PseudoInst<(outs), (ins i32imm:$dst, variable_ops),
1427 IIC_Br, []>, Requires<[IsDarwin]>;
1429 def TCRETURNri : PseudoInst<(outs), (ins tcGPR:$dst, variable_ops),
1430 IIC_Br, []>, Requires<[IsDarwin]>;
1432 def TAILJMPd : ARMPseudoInst<(outs), (ins brtarget:$dst, variable_ops),
1434 []>, Requires<[IsARM, IsDarwin]>;
1436 def tTAILJMPd: tPseudoInst<(outs), (ins brtarget:$dst, variable_ops),
1438 []>, Requires<[IsThumb, IsDarwin]>;
1440 def TAILJMPr : ARMPseudoInst<(outs), (ins tcGPR:$dst, variable_ops),
1442 []>, Requires<[IsARM, IsDarwin]>;
1444 def tTAILJMPr : tPseudoInst<(outs), (ins tcGPR:$dst, variable_ops),
1446 []>, Requires<[IsThumb, IsDarwin]>;
1449 // Non-Darwin versions (the difference is R9).
1450 let Defs = [R0, R1, R2, R3, R12,
1451 D0, D1, D2, D3, D4, D5, D6, D7,
1452 D16, D17, D18, D19, D20, D21, D22, D23, D24, D25, D26,
1453 D27, D28, D29, D30, D31, PC],
1455 def TCRETURNdiND : PseudoInst<(outs), (ins i32imm:$dst, variable_ops),
1456 IIC_Br, []>, Requires<[IsNotDarwin]>;
1458 def TCRETURNriND : PseudoInst<(outs), (ins tcGPR:$dst, variable_ops),
1459 IIC_Br, []>, Requires<[IsNotDarwin]>;
1461 def TAILJMPdND : ARMPseudoInst<(outs), (ins brtarget:$dst, variable_ops),
1463 []>, Requires<[IsARM, IsNotDarwin]>;
1465 def tTAILJMPdND : tPseudoInst<(outs), (ins brtarget:$dst, variable_ops),
1467 []>, Requires<[IsThumb, IsNotDarwin]>;
1469 def TAILJMPrND : ARMPseudoInst<(outs), (ins tcGPR:$dst, variable_ops),
1471 []>, Requires<[IsARM, IsNotDarwin]>;
1472 def tTAILJMPrND : tPseudoInst<(outs), (ins tcGPR:$dst, variable_ops),
1474 []>, Requires<[IsThumb, IsNotDarwin]>;
1478 let isBranch = 1, isTerminator = 1 in {
1479 // B is "predicable" since it's just a Bcc with an 'always' condition.
1480 let isBarrier = 1 in {
1481 let isPredicable = 1 in
1482 // FIXME: We shouldn't need this pseudo at all. Just using Bcc directly
1483 // should be sufficient.
1484 def B : ARMPseudoInst<(outs), (ins brtarget:$target), Size4Bytes, IIC_Br,
1487 let isNotDuplicable = 1, isIndirectBranch = 1 in {
1488 def BR_JTr : ARMPseudoInst<(outs),
1489 (ins GPR:$target, i32imm:$jt, i32imm:$id),
1490 SizeSpecial, IIC_Br,
1491 [(ARMbrjt GPR:$target, tjumptable:$jt, imm:$id)]>;
1492 // FIXME: This shouldn't use the generic "addrmode2," but rather be split
1493 // into i12 and rs suffixed versions.
1494 def BR_JTm : ARMPseudoInst<(outs),
1495 (ins addrmode2:$target, i32imm:$jt, i32imm:$id),
1496 SizeSpecial, IIC_Br,
1497 [(ARMbrjt (i32 (load addrmode2:$target)), tjumptable:$jt,
1499 def BR_JTadd : ARMPseudoInst<(outs),
1500 (ins GPR:$target, GPR:$idx, i32imm:$jt, i32imm:$id),
1501 SizeSpecial, IIC_Br,
1502 [(ARMbrjt (add GPR:$target, GPR:$idx), tjumptable:$jt,
1504 } // isNotDuplicable = 1, isIndirectBranch = 1
1507 // FIXME: should be able to write a pattern for ARMBrcond, but can't use
1508 // a two-value operand where a dag node expects two operands. :(
1509 def Bcc : ABI<0b1010, (outs), (ins br_target:$target),
1510 IIC_Br, "b", "\t$target",
1511 [/*(ARMbrcond bb:$target, imm:$cc, CCR:$ccr)*/]> {
1513 let Inst{23-0} = target;
1517 // BLX (immediate) -- for disassembly only
1518 def BLXi : AXI<(outs), (ins br_target:$target), BrMiscFrm, NoItinerary,
1519 "blx\t$target", [/* pattern left blank */]>,
1520 Requires<[IsARM, HasV5T]> {
1521 let Inst{31-25} = 0b1111101;
1523 let Inst{23-0} = target{24-1};
1524 let Inst{24} = target{0};
1527 // Branch and Exchange Jazelle -- for disassembly only
1528 def BXJ : ABI<0b0001, (outs), (ins GPR:$func), NoItinerary, "bxj", "\t$func",
1529 [/* For disassembly only; pattern left blank */]> {
1530 let Inst{23-20} = 0b0010;
1531 //let Inst{19-8} = 0xfff;
1532 let Inst{7-4} = 0b0010;
1535 // Secure Monitor Call is a system instruction -- for disassembly only
1536 def SMC : ABI<0b0001, (outs), (ins i32imm:$opt), NoItinerary, "smc", "\t$opt",
1537 [/* For disassembly only; pattern left blank */]> {
1539 let Inst{23-4} = 0b01100000000000000111;
1540 let Inst{3-0} = opt;
1543 // Supervisor Call (Software Interrupt) -- for disassembly only
1544 let isCall = 1, Uses = [SP] in {
1545 def SVC : ABI<0b1111, (outs), (ins i32imm:$svc), IIC_Br, "svc", "\t$svc",
1546 [/* For disassembly only; pattern left blank */]> {
1548 let Inst{23-0} = svc;
1551 def : MnemonicAlias<"swi", "svc">;
1553 // Store Return State is a system instruction -- for disassembly only
1554 let isCodeGenOnly = 1 in { // FIXME: This should not use submode!
1555 def SRSW : ABXI<{1,0,0,?}, (outs), (ins ldstm_mode:$amode, i32imm:$mode),
1556 NoItinerary, "srs${amode}\tsp!, $mode",
1557 [/* For disassembly only; pattern left blank */]> {
1558 let Inst{31-28} = 0b1111;
1559 let Inst{22-20} = 0b110; // W = 1
1560 let Inst{19-8} = 0xd05;
1561 let Inst{7-5} = 0b000;
1564 def SRS : ABXI<{1,0,0,?}, (outs), (ins ldstm_mode:$amode, i32imm:$mode),
1565 NoItinerary, "srs${amode}\tsp, $mode",
1566 [/* For disassembly only; pattern left blank */]> {
1567 let Inst{31-28} = 0b1111;
1568 let Inst{22-20} = 0b100; // W = 0
1569 let Inst{19-8} = 0xd05;
1570 let Inst{7-5} = 0b000;
1573 // Return From Exception is a system instruction -- for disassembly only
1574 def RFEW : ABXI<{1,0,0,?}, (outs), (ins ldstm_mode:$amode, GPR:$base),
1575 NoItinerary, "rfe${amode}\t$base!",
1576 [/* For disassembly only; pattern left blank */]> {
1577 let Inst{31-28} = 0b1111;
1578 let Inst{22-20} = 0b011; // W = 1
1579 let Inst{15-0} = 0x0a00;
1582 def RFE : ABXI<{1,0,0,?}, (outs), (ins ldstm_mode:$amode, GPR:$base),
1583 NoItinerary, "rfe${amode}\t$base",
1584 [/* For disassembly only; pattern left blank */]> {
1585 let Inst{31-28} = 0b1111;
1586 let Inst{22-20} = 0b001; // W = 0
1587 let Inst{15-0} = 0x0a00;
1589 } // isCodeGenOnly = 1
1591 //===----------------------------------------------------------------------===//
1592 // Load / store Instructions.
1598 defm LDR : AI_ldr1<0, "ldr", IIC_iLoad_r, IIC_iLoad_si,
1599 UnOpFrag<(load node:$Src)>>;
1600 defm LDRB : AI_ldr1<1, "ldrb", IIC_iLoad_bh_r, IIC_iLoad_bh_si,
1601 UnOpFrag<(zextloadi8 node:$Src)>>;
1602 defm STR : AI_str1<0, "str", IIC_iStore_r, IIC_iStore_si,
1603 BinOpFrag<(store node:$LHS, node:$RHS)>>;
1604 defm STRB : AI_str1<1, "strb", IIC_iStore_bh_r, IIC_iStore_bh_si,
1605 BinOpFrag<(truncstorei8 node:$LHS, node:$RHS)>>;
1607 // Special LDR for loads from non-pc-relative constpools.
1608 let canFoldAsLoad = 1, mayLoad = 1, neverHasSideEffects = 1,
1609 isReMaterializable = 1 in
1610 def LDRcp : AI2ldst<0b010, 1, 0, (outs GPR:$Rt), (ins addrmode_imm12:$addr),
1611 AddrMode_i12, LdFrm, IIC_iLoad_r, "ldr", "\t$Rt, $addr",
1615 let Inst{23} = addr{12}; // U (add = ('U' == 1))
1616 let Inst{19-16} = 0b1111;
1617 let Inst{15-12} = Rt;
1618 let Inst{11-0} = addr{11-0}; // imm12
1621 // Loads with zero extension
1622 def LDRH : AI3ld<0b1011, 1, (outs GPR:$Rt), (ins addrmode3:$addr), LdMiscFrm,
1623 IIC_iLoad_bh_r, "ldrh", "\t$Rt, $addr",
1624 [(set GPR:$Rt, (zextloadi16 addrmode3:$addr))]>;
1626 // Loads with sign extension
1627 def LDRSH : AI3ld<0b1111, 1, (outs GPR:$Rt), (ins addrmode3:$addr), LdMiscFrm,
1628 IIC_iLoad_bh_r, "ldrsh", "\t$Rt, $addr",
1629 [(set GPR:$Rt, (sextloadi16 addrmode3:$addr))]>;
1631 def LDRSB : AI3ld<0b1101, 1, (outs GPR:$Rt), (ins addrmode3:$addr), LdMiscFrm,
1632 IIC_iLoad_bh_r, "ldrsb", "\t$Rt, $addr",
1633 [(set GPR:$Rt, (sextloadi8 addrmode3:$addr))]>;
1635 let mayLoad = 1, neverHasSideEffects = 1, hasExtraDefRegAllocReq = 1 in {
1637 def LDRD : AI3ld<0b1101, 0, (outs GPR:$Rd, GPR:$dst2),
1638 (ins addrmode3:$addr), LdMiscFrm,
1639 IIC_iLoad_d_r, "ldrd", "\t$Rd, $dst2, $addr",
1640 []>, Requires<[IsARM, HasV5TE]>;
1644 multiclass AI2_ldridx<bit isByte, string opc, InstrItinClass itin> {
1645 def _PRE : AI2ldstidx<1, isByte, 1, (outs GPR:$Rt, GPR:$Rn_wb),
1646 (ins addrmode2:$addr), IndexModePre, LdFrm, itin,
1647 opc, "\t$Rt, $addr!", "$addr.base = $Rn_wb", []> {
1649 // {13} 1 == Rm, 0 == imm12
1653 let Inst{25} = addr{13};
1654 let Inst{23} = addr{12};
1655 let Inst{19-16} = addr{17-14};
1656 let Inst{11-0} = addr{11-0};
1657 let AsmMatchConverter = "CvtLdWriteBackRegAddrMode2";
1659 def _POST : AI2ldstidx<1, isByte, 0, (outs GPR:$Rt, GPR:$Rn_wb),
1660 (ins GPR:$Rn, am2offset:$offset),
1661 IndexModePost, LdFrm, itin,
1662 opc, "\t$Rt, [$Rn], $offset", "$Rn = $Rn_wb", []> {
1663 // {13} 1 == Rm, 0 == imm12
1668 let Inst{25} = offset{13};
1669 let Inst{23} = offset{12};
1670 let Inst{19-16} = Rn;
1671 let Inst{11-0} = offset{11-0};
1675 let mayLoad = 1, neverHasSideEffects = 1 in {
1676 defm LDR : AI2_ldridx<0, "ldr", IIC_iLoad_ru>;
1677 defm LDRB : AI2_ldridx<1, "ldrb", IIC_iLoad_bh_ru>;
1680 multiclass AI3_ldridx<bits<4> op, bit op20, string opc, InstrItinClass itin> {
1681 def _PRE : AI3ldstidx<op, op20, 1, 1, (outs GPR:$Rt, GPR:$Rn_wb),
1682 (ins addrmode3:$addr), IndexModePre,
1684 opc, "\t$Rt, $addr!", "$addr.base = $Rn_wb", []> {
1686 let Inst{23} = addr{8}; // U bit
1687 let Inst{22} = addr{13}; // 1 == imm8, 0 == Rm
1688 let Inst{19-16} = addr{12-9}; // Rn
1689 let Inst{11-8} = addr{7-4}; // imm7_4/zero
1690 let Inst{3-0} = addr{3-0}; // imm3_0/Rm
1692 def _POST : AI3ldstidx<op, op20, 1, 0, (outs GPR:$Rt, GPR:$Rn_wb),
1693 (ins GPR:$Rn, am3offset:$offset), IndexModePost,
1695 opc, "\t$Rt, [$Rn], $offset", "$Rn = $Rn_wb", []> {
1698 let Inst{23} = offset{8}; // U bit
1699 let Inst{22} = offset{9}; // 1 == imm8, 0 == Rm
1700 let Inst{19-16} = Rn;
1701 let Inst{11-8} = offset{7-4}; // imm7_4/zero
1702 let Inst{3-0} = offset{3-0}; // imm3_0/Rm
1706 let mayLoad = 1, neverHasSideEffects = 1 in {
1707 defm LDRH : AI3_ldridx<0b1011, 1, "ldrh", IIC_iLoad_bh_ru>;
1708 defm LDRSH : AI3_ldridx<0b1111, 1, "ldrsh", IIC_iLoad_bh_ru>;
1709 defm LDRSB : AI3_ldridx<0b1101, 1, "ldrsb", IIC_iLoad_bh_ru>;
1710 let hasExtraDefRegAllocReq = 1, isCodeGenOnly = 1 in
1711 defm LDRD : AI3_ldridx<0b1101, 0, "ldrd", IIC_iLoad_d_ru>;
1712 } // mayLoad = 1, neverHasSideEffects = 1
1714 // LDRT, LDRBT, LDRSBT, LDRHT, LDRSHT are for disassembly only.
1715 let mayLoad = 1, neverHasSideEffects = 1 in {
1716 def LDRT : AI2ldstidx<1, 0, 0, (outs GPR:$Rt, GPR:$base_wb),
1717 (ins addrmode2:$addr), IndexModePost, LdFrm, IIC_iLoad_ru,
1718 "ldrt", "\t$Rt, $addr", "$addr.base = $base_wb", []> {
1720 // {13} 1 == Rm, 0 == imm12
1724 let Inst{25} = addr{13};
1725 let Inst{23} = addr{12};
1726 let Inst{21} = 1; // overwrite
1727 let Inst{19-16} = addr{17-14};
1728 let Inst{11-0} = addr{11-0};
1729 let AsmMatchConverter = "CvtLdWriteBackRegAddrMode2";
1731 def LDRBT : AI2ldstidx<1, 1, 0, (outs GPR:$Rt, GPR:$base_wb),
1732 (ins addrmode2:$addr), IndexModePost, LdFrm, IIC_iLoad_bh_ru,
1733 "ldrbt", "\t$Rt, $addr", "$addr.base = $base_wb", []> {
1735 // {13} 1 == Rm, 0 == imm12
1739 let Inst{25} = addr{13};
1740 let Inst{23} = addr{12};
1741 let Inst{21} = 1; // overwrite
1742 let Inst{19-16} = addr{17-14};
1743 let Inst{11-0} = addr{11-0};
1744 let AsmMatchConverter = "CvtLdWriteBackRegAddrMode2";
1746 def LDRSBT : AI3ldstidxT<0b1101, 1, 1, 0, (outs GPR:$Rt, GPR:$base_wb),
1747 (ins addrmode3:$addr), IndexModePost, LdMiscFrm, IIC_iLoad_bh_ru,
1748 "ldrsbt", "\t$Rt, $addr", "$addr.base = $base_wb", []> {
1749 let Inst{21} = 1; // overwrite
1751 def LDRHT : AI3ldstidxT<0b1011, 1, 1, 0, (outs GPR:$Rt, GPR:$base_wb),
1752 (ins addrmode3:$addr), IndexModePost, LdMiscFrm, IIC_iLoad_bh_ru,
1753 "ldrht", "\t$Rt, $addr", "$addr.base = $base_wb", []> {
1754 let Inst{21} = 1; // overwrite
1756 def LDRSHT : AI3ldstidxT<0b1111, 1, 1, 0, (outs GPR:$Rt, GPR:$base_wb),
1757 (ins addrmode3:$addr), IndexModePost, LdMiscFrm, IIC_iLoad_bh_ru,
1758 "ldrsht", "\t$Rt, $addr", "$addr.base = $base_wb", []> {
1759 let Inst{21} = 1; // overwrite
1765 // Stores with truncate
1766 def STRH : AI3str<0b1011, (outs), (ins GPR:$Rt, addrmode3:$addr), StMiscFrm,
1767 IIC_iStore_bh_r, "strh", "\t$Rt, $addr",
1768 [(truncstorei16 GPR:$Rt, addrmode3:$addr)]>;
1771 let mayStore = 1, neverHasSideEffects = 1, hasExtraSrcRegAllocReq = 1 in
1772 def STRD : AI3str<0b1111, (outs), (ins GPR:$Rt, GPR:$src2, addrmode3:$addr),
1773 StMiscFrm, IIC_iStore_d_r,
1774 "strd", "\t$Rt, $src2, $addr", []>, Requires<[IsARM, HasV5TE]>;
1777 def STR_PRE : AI2stridx<0, 1, (outs GPR:$Rn_wb),
1778 (ins GPR:$Rt, GPR:$Rn, am2offset:$offset),
1779 IndexModePre, StFrm, IIC_iStore_ru,
1780 "str", "\t$Rt, [$Rn, $offset]!", "$Rn = $Rn_wb",
1782 (pre_store GPR:$Rt, GPR:$Rn, am2offset:$offset))]>;
1784 def STR_POST : AI2stridx<0, 0, (outs GPR:$Rn_wb),
1785 (ins GPR:$Rt, GPR:$Rn, am2offset:$offset),
1786 IndexModePost, StFrm, IIC_iStore_ru,
1787 "str", "\t$Rt, [$Rn], $offset", "$Rn = $Rn_wb",
1789 (post_store GPR:$Rt, GPR:$Rn, am2offset:$offset))]>;
1791 def STRB_PRE : AI2stridx<1, 1, (outs GPR:$Rn_wb),
1792 (ins GPR:$Rt, GPR:$Rn, am2offset:$offset),
1793 IndexModePre, StFrm, IIC_iStore_bh_ru,
1794 "strb", "\t$Rt, [$Rn, $offset]!", "$Rn = $Rn_wb",
1795 [(set GPR:$Rn_wb, (pre_truncsti8 GPR:$Rt,
1796 GPR:$Rn, am2offset:$offset))]>;
1797 def STRB_POST: AI2stridx<1, 0, (outs GPR:$Rn_wb),
1798 (ins GPR:$Rt, GPR:$Rn, am2offset:$offset),
1799 IndexModePost, StFrm, IIC_iStore_bh_ru,
1800 "strb", "\t$Rt, [$Rn], $offset", "$Rn = $Rn_wb",
1801 [(set GPR:$Rn_wb, (post_truncsti8 GPR:$Rt,
1802 GPR:$Rn, am2offset:$offset))]>;
1804 def STRH_PRE : AI3stridx<0b1011, 0, 1, (outs GPR:$Rn_wb),
1805 (ins GPR:$Rt, GPR:$Rn, am3offset:$offset),
1806 IndexModePre, StMiscFrm, IIC_iStore_ru,
1807 "strh", "\t$Rt, [$Rn, $offset]!", "$Rn = $Rn_wb",
1809 (pre_truncsti16 GPR:$Rt, GPR:$Rn, am3offset:$offset))]>;
1811 def STRH_POST: AI3stridx<0b1011, 0, 0, (outs GPR:$Rn_wb),
1812 (ins GPR:$Rt, GPR:$Rn, am3offset:$offset),
1813 IndexModePost, StMiscFrm, IIC_iStore_bh_ru,
1814 "strh", "\t$Rt, [$Rn], $offset", "$Rn = $Rn_wb",
1815 [(set GPR:$Rn_wb, (post_truncsti16 GPR:$Rt,
1816 GPR:$Rn, am3offset:$offset))]>;
1818 // For disassembly only
1819 def STRD_PRE : AI3stdpr<(outs GPR:$base_wb),
1820 (ins GPR:$src1, GPR:$src2, GPR:$base, am3offset:$offset),
1821 StMiscFrm, IIC_iStore_d_ru,
1822 "strd", "\t$src1, $src2, [$base, $offset]!",
1823 "$base = $base_wb", []>;
1825 // For disassembly only
1826 def STRD_POST: AI3stdpo<(outs GPR:$base_wb),
1827 (ins GPR:$src1, GPR:$src2, GPR:$base, am3offset:$offset),
1828 StMiscFrm, IIC_iStore_d_ru,
1829 "strd", "\t$src1, $src2, [$base], $offset",
1830 "$base = $base_wb", []>;
1832 // STRT, STRBT, and STRHT are for disassembly only.
1834 def STRT : AI2stridxT<0, 0, (outs GPR:$Rn_wb), (ins GPR:$Rt, addrmode2:$addr),
1835 IndexModePost, StFrm, IIC_iStore_ru,
1836 "strt", "\t$Rt, $addr", "$addr.base = $Rn_wb",
1837 [/* For disassembly only; pattern left blank */]> {
1838 let Inst{21} = 1; // overwrite
1839 let AsmMatchConverter = "CvtStWriteBackRegAddrMode2";
1842 def STRBT : AI2stridxT<1, 0, (outs GPR:$Rn_wb), (ins GPR:$Rt, addrmode2:$addr),
1843 IndexModePost, StFrm, IIC_iStore_bh_ru,
1844 "strbt", "\t$Rt, $addr", "$addr.base = $Rn_wb",
1845 [/* For disassembly only; pattern left blank */]> {
1846 let Inst{21} = 1; // overwrite
1847 let AsmMatchConverter = "CvtStWriteBackRegAddrMode2";
1850 def STRHT: AI3sthpo<(outs GPR:$base_wb), (ins GPR:$Rt, addrmode3:$addr),
1851 StMiscFrm, IIC_iStore_bh_ru,
1852 "strht", "\t$Rt, $addr", "$addr.base = $base_wb",
1853 [/* For disassembly only; pattern left blank */]> {
1854 let Inst{21} = 1; // overwrite
1855 let AsmMatchConverter = "CvtStWriteBackRegAddrMode3";
1858 //===----------------------------------------------------------------------===//
1859 // Load / store multiple Instructions.
1862 multiclass arm_ldst_mult<string asm, bit L_bit, Format f,
1863 InstrItinClass itin, InstrItinClass itin_upd> {
1865 AXI4<(outs), (ins GPR:$Rn, pred:$p, reglist:$regs, variable_ops),
1866 IndexModeNone, f, itin,
1867 !strconcat(asm, "ia${p}\t$Rn, $regs"), "", []> {
1868 let Inst{24-23} = 0b01; // Increment After
1869 let Inst{21} = 0; // No writeback
1870 let Inst{20} = L_bit;
1873 AXI4<(outs GPR:$wb), (ins GPR:$Rn, pred:$p, reglist:$regs, variable_ops),
1874 IndexModeUpd, f, itin_upd,
1875 !strconcat(asm, "ia${p}\t$Rn!, $regs"), "$Rn = $wb", []> {
1876 let Inst{24-23} = 0b01; // Increment After
1877 let Inst{21} = 1; // Writeback
1878 let Inst{20} = L_bit;
1881 AXI4<(outs), (ins GPR:$Rn, pred:$p, reglist:$regs, variable_ops),
1882 IndexModeNone, f, itin,
1883 !strconcat(asm, "da${p}\t$Rn, $regs"), "", []> {
1884 let Inst{24-23} = 0b00; // Decrement After
1885 let Inst{21} = 0; // No writeback
1886 let Inst{20} = L_bit;
1889 AXI4<(outs GPR:$wb), (ins GPR:$Rn, pred:$p, reglist:$regs, variable_ops),
1890 IndexModeUpd, f, itin_upd,
1891 !strconcat(asm, "da${p}\t$Rn!, $regs"), "$Rn = $wb", []> {
1892 let Inst{24-23} = 0b00; // Decrement After
1893 let Inst{21} = 1; // Writeback
1894 let Inst{20} = L_bit;
1897 AXI4<(outs), (ins GPR:$Rn, pred:$p, reglist:$regs, variable_ops),
1898 IndexModeNone, f, itin,
1899 !strconcat(asm, "db${p}\t$Rn, $regs"), "", []> {
1900 let Inst{24-23} = 0b10; // Decrement Before
1901 let Inst{21} = 0; // No writeback
1902 let Inst{20} = L_bit;
1905 AXI4<(outs GPR:$wb), (ins GPR:$Rn, pred:$p, reglist:$regs, variable_ops),
1906 IndexModeUpd, f, itin_upd,
1907 !strconcat(asm, "db${p}\t$Rn!, $regs"), "$Rn = $wb", []> {
1908 let Inst{24-23} = 0b10; // Decrement Before
1909 let Inst{21} = 1; // Writeback
1910 let Inst{20} = L_bit;
1913 AXI4<(outs), (ins GPR:$Rn, pred:$p, reglist:$regs, variable_ops),
1914 IndexModeNone, f, itin,
1915 !strconcat(asm, "ib${p}\t$Rn, $regs"), "", []> {
1916 let Inst{24-23} = 0b11; // Increment Before
1917 let Inst{21} = 0; // No writeback
1918 let Inst{20} = L_bit;
1921 AXI4<(outs GPR:$wb), (ins GPR:$Rn, pred:$p, reglist:$regs, variable_ops),
1922 IndexModeUpd, f, itin_upd,
1923 !strconcat(asm, "ib${p}\t$Rn!, $regs"), "$Rn = $wb", []> {
1924 let Inst{24-23} = 0b11; // Increment Before
1925 let Inst{21} = 1; // Writeback
1926 let Inst{20} = L_bit;
1930 let neverHasSideEffects = 1 in {
1932 let mayLoad = 1, hasExtraDefRegAllocReq = 1 in
1933 defm LDM : arm_ldst_mult<"ldm", 1, LdStMulFrm, IIC_iLoad_m, IIC_iLoad_mu>;
1935 let mayStore = 1, hasExtraSrcRegAllocReq = 1 in
1936 defm STM : arm_ldst_mult<"stm", 0, LdStMulFrm, IIC_iStore_m, IIC_iStore_mu>;
1938 } // neverHasSideEffects
1940 // Load / Store Multiple Mnemonic Aliases
1941 def : MnemonicAlias<"ldm", "ldmia">;
1942 def : MnemonicAlias<"stm", "stmia">;
1944 // FIXME: remove when we have a way to marking a MI with these properties.
1945 // FIXME: Should pc be an implicit operand like PICADD, etc?
1946 let isReturn = 1, isTerminator = 1, isBarrier = 1, mayLoad = 1,
1947 hasExtraDefRegAllocReq = 1, isCodeGenOnly = 1 in
1948 def LDMIA_RET : ARMPseudoInst<(outs GPR:$wb), (ins GPR:$Rn, pred:$p,
1949 reglist:$regs, variable_ops),
1950 Size4Bytes, IIC_iLoad_mBr, []>,
1951 RegConstraint<"$Rn = $wb">;
1953 //===----------------------------------------------------------------------===//
1954 // Move Instructions.
1957 let neverHasSideEffects = 1 in
1958 def MOVr : AsI1<0b1101, (outs GPR:$Rd), (ins GPR:$Rm), DPFrm, IIC_iMOVr,
1959 "mov", "\t$Rd, $Rm", []>, UnaryDP {
1963 let Inst{19-16} = 0b0000;
1964 let Inst{11-4} = 0b00000000;
1967 let Inst{15-12} = Rd;
1970 // A version for the smaller set of tail call registers.
1971 let neverHasSideEffects = 1 in
1972 def MOVr_TC : AsI1<0b1101, (outs tcGPR:$Rd), (ins tcGPR:$Rm), DPFrm,
1973 IIC_iMOVr, "mov", "\t$Rd, $Rm", []>, UnaryDP {
1977 let Inst{11-4} = 0b00000000;
1980 let Inst{15-12} = Rd;
1983 def MOVs : AsI1<0b1101, (outs GPR:$Rd), (ins shift_so_reg:$src),
1984 DPSoRegFrm, IIC_iMOVsr,
1985 "mov", "\t$Rd, $src", [(set GPR:$Rd, shift_so_reg:$src)]>,
1989 let Inst{15-12} = Rd;
1990 let Inst{19-16} = 0b0000;
1991 let Inst{11-0} = src;
1995 let isReMaterializable = 1, isAsCheapAsAMove = 1, isMoveImm = 1 in
1996 def MOVi : AsI1<0b1101, (outs GPR:$Rd), (ins so_imm:$imm), DPFrm, IIC_iMOVi,
1997 "mov", "\t$Rd, $imm", [(set GPR:$Rd, so_imm:$imm)]>, UnaryDP {
2001 let Inst{15-12} = Rd;
2002 let Inst{19-16} = 0b0000;
2003 let Inst{11-0} = imm;
2006 let isReMaterializable = 1, isAsCheapAsAMove = 1, isMoveImm = 1 in
2007 def MOVi16 : AI1<0b1000, (outs GPR:$Rd), (ins i32imm_hilo16:$imm),
2009 "movw", "\t$Rd, $imm",
2010 [(set GPR:$Rd, imm0_65535:$imm)]>,
2011 Requires<[IsARM, HasV6T2]>, UnaryDP {
2014 let Inst{15-12} = Rd;
2015 let Inst{11-0} = imm{11-0};
2016 let Inst{19-16} = imm{15-12};
2021 def MOVi16_ga_pcrel : PseudoInst<(outs GPR:$Rd),
2022 (ins i32imm:$addr, pclabel:$id), IIC_iMOVi, []>;
2024 let Constraints = "$src = $Rd" in {
2025 def MOVTi16 : AI1<0b1010, (outs GPR:$Rd), (ins GPR:$src, i32imm_hilo16:$imm),
2027 "movt", "\t$Rd, $imm",
2029 (or (and GPR:$src, 0xffff),
2030 lo16AllZero:$imm))]>, UnaryDP,
2031 Requires<[IsARM, HasV6T2]> {
2034 let Inst{15-12} = Rd;
2035 let Inst{11-0} = imm{11-0};
2036 let Inst{19-16} = imm{15-12};
2041 def MOVTi16_ga_pcrel : PseudoInst<(outs GPR:$Rd),
2042 (ins GPR:$src, i32imm:$addr, pclabel:$id), IIC_iMOVi, []>;
2046 def : ARMPat<(or GPR:$src, 0xffff0000), (MOVTi16 GPR:$src, 0xffff)>,
2047 Requires<[IsARM, HasV6T2]>;
2049 let Uses = [CPSR] in
2050 def RRX: PseudoInst<(outs GPR:$Rd), (ins GPR:$Rm), IIC_iMOVsi,
2051 [(set GPR:$Rd, (ARMrrx GPR:$Rm))]>, UnaryDP,
2054 // These aren't really mov instructions, but we have to define them this way
2055 // due to flag operands.
2057 let Defs = [CPSR] in {
2058 def MOVsrl_flag : PseudoInst<(outs GPR:$dst), (ins GPR:$src), IIC_iMOVsi,
2059 [(set GPR:$dst, (ARMsrl_flag GPR:$src))]>, UnaryDP,
2061 def MOVsra_flag : PseudoInst<(outs GPR:$dst), (ins GPR:$src), IIC_iMOVsi,
2062 [(set GPR:$dst, (ARMsra_flag GPR:$src))]>, UnaryDP,
2066 //===----------------------------------------------------------------------===//
2067 // Extend Instructions.
2072 defm SXTB : AI_ext_rrot<0b01101010,
2073 "sxtb", UnOpFrag<(sext_inreg node:$Src, i8)>>;
2074 defm SXTH : AI_ext_rrot<0b01101011,
2075 "sxth", UnOpFrag<(sext_inreg node:$Src, i16)>>;
2077 defm SXTAB : AI_exta_rrot<0b01101010,
2078 "sxtab", BinOpFrag<(add node:$LHS, (sext_inreg node:$RHS, i8))>>;
2079 defm SXTAH : AI_exta_rrot<0b01101011,
2080 "sxtah", BinOpFrag<(add node:$LHS, (sext_inreg node:$RHS,i16))>>;
2082 // For disassembly only
2083 defm SXTB16 : AI_ext_rrot_np<0b01101000, "sxtb16">;
2085 // For disassembly only
2086 defm SXTAB16 : AI_exta_rrot_np<0b01101000, "sxtab16">;
2090 let AddedComplexity = 16 in {
2091 defm UXTB : AI_ext_rrot<0b01101110,
2092 "uxtb" , UnOpFrag<(and node:$Src, 0x000000FF)>>;
2093 defm UXTH : AI_ext_rrot<0b01101111,
2094 "uxth" , UnOpFrag<(and node:$Src, 0x0000FFFF)>>;
2095 defm UXTB16 : AI_ext_rrot<0b01101100,
2096 "uxtb16", UnOpFrag<(and node:$Src, 0x00FF00FF)>>;
2098 // FIXME: This pattern incorrectly assumes the shl operator is a rotate.
2099 // The transformation should probably be done as a combiner action
2100 // instead so we can include a check for masking back in the upper
2101 // eight bits of the source into the lower eight bits of the result.
2102 //def : ARMV6Pat<(and (shl GPR:$Src, (i32 8)), 0xFF00FF),
2103 // (UXTB16r_rot GPR:$Src, 24)>;
2104 def : ARMV6Pat<(and (srl GPR:$Src, (i32 8)), 0xFF00FF),
2105 (UXTB16r_rot GPR:$Src, 8)>;
2107 defm UXTAB : AI_exta_rrot<0b01101110, "uxtab",
2108 BinOpFrag<(add node:$LHS, (and node:$RHS, 0x00FF))>>;
2109 defm UXTAH : AI_exta_rrot<0b01101111, "uxtah",
2110 BinOpFrag<(add node:$LHS, (and node:$RHS, 0xFFFF))>>;
2113 // This isn't safe in general, the add is two 16-bit units, not a 32-bit add.
2114 // For disassembly only
2115 defm UXTAB16 : AI_exta_rrot_np<0b01101100, "uxtab16">;
2118 def SBFX : I<(outs GPR:$Rd),
2119 (ins GPR:$Rn, imm0_31:$lsb, imm0_31_m1:$width),
2120 AddrMode1, Size4Bytes, IndexModeNone, DPFrm, IIC_iUNAsi,
2121 "sbfx", "\t$Rd, $Rn, $lsb, $width", "", []>,
2122 Requires<[IsARM, HasV6T2]> {
2127 let Inst{27-21} = 0b0111101;
2128 let Inst{6-4} = 0b101;
2129 let Inst{20-16} = width;
2130 let Inst{15-12} = Rd;
2131 let Inst{11-7} = lsb;
2135 def UBFX : I<(outs GPR:$Rd),
2136 (ins GPR:$Rn, imm0_31:$lsb, imm0_31_m1:$width),
2137 AddrMode1, Size4Bytes, IndexModeNone, DPFrm, IIC_iUNAsi,
2138 "ubfx", "\t$Rd, $Rn, $lsb, $width", "", []>,
2139 Requires<[IsARM, HasV6T2]> {
2144 let Inst{27-21} = 0b0111111;
2145 let Inst{6-4} = 0b101;
2146 let Inst{20-16} = width;
2147 let Inst{15-12} = Rd;
2148 let Inst{11-7} = lsb;
2152 //===----------------------------------------------------------------------===//
2153 // Arithmetic Instructions.
2156 defm ADD : AsI1_bin_irs<0b0100, "add",
2157 IIC_iALUi, IIC_iALUr, IIC_iALUsr,
2158 BinOpFrag<(add node:$LHS, node:$RHS)>, 1>;
2159 defm SUB : AsI1_bin_irs<0b0010, "sub",
2160 IIC_iALUi, IIC_iALUr, IIC_iALUsr,
2161 BinOpFrag<(sub node:$LHS, node:$RHS)>>;
2163 // ADD and SUB with 's' bit set.
2164 defm ADDS : AI1_bin_s_irs<0b0100, "adds",
2165 IIC_iALUi, IIC_iALUr, IIC_iALUsr,
2166 BinOpFrag<(addc node:$LHS, node:$RHS)>, 1>;
2167 defm SUBS : AI1_bin_s_irs<0b0010, "subs",
2168 IIC_iALUi, IIC_iALUr, IIC_iALUsr,
2169 BinOpFrag<(subc node:$LHS, node:$RHS)>>;
2171 defm ADC : AI1_adde_sube_irs<0b0101, "adc",
2172 BinOpFrag<(adde_dead_carry node:$LHS, node:$RHS)>, 1>;
2173 defm SBC : AI1_adde_sube_irs<0b0110, "sbc",
2174 BinOpFrag<(sube_dead_carry node:$LHS, node:$RHS)>>;
2176 // ADC and SUBC with 's' bit set.
2177 defm ADCS : AI1_adde_sube_s_irs<0b0101, "adcs",
2178 BinOpFrag<(adde_live_carry node:$LHS, node:$RHS)>, 1>;
2179 defm SBCS : AI1_adde_sube_s_irs<0b0110, "sbcs",
2180 BinOpFrag<(sube_live_carry node:$LHS, node:$RHS) >>;
2182 def RSBri : AsI1<0b0011, (outs GPR:$Rd), (ins GPR:$Rn, so_imm:$imm), DPFrm,
2183 IIC_iALUi, "rsb", "\t$Rd, $Rn, $imm",
2184 [(set GPR:$Rd, (sub so_imm:$imm, GPR:$Rn))]> {
2189 let Inst{15-12} = Rd;
2190 let Inst{19-16} = Rn;
2191 let Inst{11-0} = imm;
2194 // The reg/reg form is only defined for the disassembler; for codegen it is
2195 // equivalent to SUBrr.
2196 def RSBrr : AsI1<0b0011, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm), DPFrm,
2197 IIC_iALUr, "rsb", "\t$Rd, $Rn, $Rm",
2198 [/* For disassembly only; pattern left blank */]> {
2202 let Inst{11-4} = 0b00000000;
2205 let Inst{15-12} = Rd;
2206 let Inst{19-16} = Rn;
2209 def RSBrs : AsI1<0b0011, (outs GPR:$Rd), (ins GPR:$Rn, so_reg:$shift),
2210 DPSoRegFrm, IIC_iALUsr, "rsb", "\t$Rd, $Rn, $shift",
2211 [(set GPR:$Rd, (sub so_reg:$shift, GPR:$Rn))]> {
2216 let Inst{11-0} = shift;
2217 let Inst{15-12} = Rd;
2218 let Inst{19-16} = Rn;
2221 // RSB with 's' bit set.
2222 let isCodeGenOnly = 1, Defs = [CPSR] in {
2223 def RSBSri : AI1<0b0011, (outs GPR:$Rd), (ins GPR:$Rn, so_imm:$imm), DPFrm,
2224 IIC_iALUi, "rsbs", "\t$Rd, $Rn, $imm",
2225 [(set GPR:$Rd, (subc so_imm:$imm, GPR:$Rn))]> {
2231 let Inst{15-12} = Rd;
2232 let Inst{19-16} = Rn;
2233 let Inst{11-0} = imm;
2235 def RSBSrr : AI1<0b0011, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm), DPFrm,
2236 IIC_iALUr, "rsbs", "\t$Rd, $Rn, $Rm",
2237 [/* For disassembly only; pattern left blank */]> {
2241 let Inst{11-4} = 0b00000000;
2245 let Inst{15-12} = Rd;
2246 let Inst{19-16} = Rn;
2248 def RSBSrs : AI1<0b0011, (outs GPR:$Rd), (ins GPR:$Rn, so_reg:$shift),
2249 DPSoRegFrm, IIC_iALUsr, "rsbs", "\t$Rd, $Rn, $shift",
2250 [(set GPR:$Rd, (subc so_reg:$shift, GPR:$Rn))]> {
2256 let Inst{11-0} = shift;
2257 let Inst{15-12} = Rd;
2258 let Inst{19-16} = Rn;
2262 let Uses = [CPSR] in {
2263 def RSCri : AsI1<0b0111, (outs GPR:$Rd), (ins GPR:$Rn, so_imm:$imm),
2264 DPFrm, IIC_iALUi, "rsc", "\t$Rd, $Rn, $imm",
2265 [(set GPR:$Rd, (sube_dead_carry so_imm:$imm, GPR:$Rn))]>,
2271 let Inst{15-12} = Rd;
2272 let Inst{19-16} = Rn;
2273 let Inst{11-0} = imm;
2275 // The reg/reg form is only defined for the disassembler; for codegen it is
2276 // equivalent to SUBrr.
2277 def RSCrr : AsI1<0b0111, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm),
2278 DPFrm, IIC_iALUr, "rsc", "\t$Rd, $Rn, $Rm",
2279 [/* For disassembly only; pattern left blank */]> {
2283 let Inst{11-4} = 0b00000000;
2286 let Inst{15-12} = Rd;
2287 let Inst{19-16} = Rn;
2289 def RSCrs : AsI1<0b0111, (outs GPR:$Rd), (ins GPR:$Rn, so_reg:$shift),
2290 DPSoRegFrm, IIC_iALUsr, "rsc", "\t$Rd, $Rn, $shift",
2291 [(set GPR:$Rd, (sube_dead_carry so_reg:$shift, GPR:$Rn))]>,
2297 let Inst{11-0} = shift;
2298 let Inst{15-12} = Rd;
2299 let Inst{19-16} = Rn;
2303 // FIXME: Allow these to be predicated.
2304 let isCodeGenOnly = 1, Defs = [CPSR], Uses = [CPSR] in {
2305 def RSCSri : AXI1<0b0111, (outs GPR:$Rd), (ins GPR:$Rn, so_imm:$imm),
2306 DPFrm, IIC_iALUi, "rscs\t$Rd, $Rn, $imm",
2307 [(set GPR:$Rd, (sube_dead_carry so_imm:$imm, GPR:$Rn))]>,
2314 let Inst{15-12} = Rd;
2315 let Inst{19-16} = Rn;
2316 let Inst{11-0} = imm;
2318 def RSCSrs : AXI1<0b0111, (outs GPR:$Rd), (ins GPR:$Rn, so_reg:$shift),
2319 DPSoRegFrm, IIC_iALUsr, "rscs\t$Rd, $Rn, $shift",
2320 [(set GPR:$Rd, (sube_dead_carry so_reg:$shift, GPR:$Rn))]>,
2327 let Inst{11-0} = shift;
2328 let Inst{15-12} = Rd;
2329 let Inst{19-16} = Rn;
2333 // (sub X, imm) gets canonicalized to (add X, -imm). Match this form.
2334 // The assume-no-carry-in form uses the negation of the input since add/sub
2335 // assume opposite meanings of the carry flag (i.e., carry == !borrow).
2336 // See the definition of AddWithCarry() in the ARM ARM A2.2.1 for the gory
2338 def : ARMPat<(add GPR:$src, so_imm_neg:$imm),
2339 (SUBri GPR:$src, so_imm_neg:$imm)>;
2340 def : ARMPat<(addc GPR:$src, so_imm_neg:$imm),
2341 (SUBSri GPR:$src, so_imm_neg:$imm)>;
2342 // The with-carry-in form matches bitwise not instead of the negation.
2343 // Effectively, the inverse interpretation of the carry flag already accounts
2344 // for part of the negation.
2345 def : ARMPat<(adde GPR:$src, so_imm_not:$imm),
2346 (SBCri GPR:$src, so_imm_not:$imm)>;
2348 // Note: These are implemented in C++ code, because they have to generate
2349 // ADD/SUBrs instructions, which use a complex pattern that a xform function
2351 // (mul X, 2^n+1) -> (add (X << n), X)
2352 // (mul X, 2^n-1) -> (rsb X, (X << n))
2354 // ARM Arithmetic Instruction -- for disassembly only
2355 // GPR:$dst = GPR:$a op GPR:$b
2356 class AAI<bits<8> op27_20, bits<8> op11_4, string opc,
2357 list<dag> pattern = [/* For disassembly only; pattern left blank */],
2358 dag iops = (ins GPR:$Rn, GPR:$Rm), string asm = "\t$Rd, $Rn, $Rm">
2359 : AI<(outs GPR:$Rd), iops, DPFrm, IIC_iALUr, opc, asm, pattern> {
2363 let Inst{27-20} = op27_20;
2364 let Inst{11-4} = op11_4;
2365 let Inst{19-16} = Rn;
2366 let Inst{15-12} = Rd;
2370 // Saturating add/subtract -- for disassembly only
2372 def QADD : AAI<0b00010000, 0b00000101, "qadd",
2373 [(set GPR:$Rd, (int_arm_qadd GPR:$Rm, GPR:$Rn))],
2374 (ins GPR:$Rm, GPR:$Rn), "\t$Rd, $Rm, $Rn">;
2375 def QSUB : AAI<0b00010010, 0b00000101, "qsub",
2376 [(set GPR:$Rd, (int_arm_qsub GPR:$Rm, GPR:$Rn))],
2377 (ins GPR:$Rm, GPR:$Rn), "\t$Rd, $Rm, $Rn">;
2378 def QDADD : AAI<0b00010100, 0b00000101, "qdadd", [], (ins GPR:$Rm, GPR:$Rn),
2380 def QDSUB : AAI<0b00010110, 0b00000101, "qdsub", [], (ins GPR:$Rm, GPR:$Rn),
2383 def QADD16 : AAI<0b01100010, 0b11110001, "qadd16">;
2384 def QADD8 : AAI<0b01100010, 0b11111001, "qadd8">;
2385 def QASX : AAI<0b01100010, 0b11110011, "qasx">;
2386 def QSAX : AAI<0b01100010, 0b11110101, "qsax">;
2387 def QSUB16 : AAI<0b01100010, 0b11110111, "qsub16">;
2388 def QSUB8 : AAI<0b01100010, 0b11111111, "qsub8">;
2389 def UQADD16 : AAI<0b01100110, 0b11110001, "uqadd16">;
2390 def UQADD8 : AAI<0b01100110, 0b11111001, "uqadd8">;
2391 def UQASX : AAI<0b01100110, 0b11110011, "uqasx">;
2392 def UQSAX : AAI<0b01100110, 0b11110101, "uqsax">;
2393 def UQSUB16 : AAI<0b01100110, 0b11110111, "uqsub16">;
2394 def UQSUB8 : AAI<0b01100110, 0b11111111, "uqsub8">;
2396 // Signed/Unsigned add/subtract -- for disassembly only
2398 def SASX : AAI<0b01100001, 0b11110011, "sasx">;
2399 def SADD16 : AAI<0b01100001, 0b11110001, "sadd16">;
2400 def SADD8 : AAI<0b01100001, 0b11111001, "sadd8">;
2401 def SSAX : AAI<0b01100001, 0b11110101, "ssax">;
2402 def SSUB16 : AAI<0b01100001, 0b11110111, "ssub16">;
2403 def SSUB8 : AAI<0b01100001, 0b11111111, "ssub8">;
2404 def UASX : AAI<0b01100101, 0b11110011, "uasx">;
2405 def UADD16 : AAI<0b01100101, 0b11110001, "uadd16">;
2406 def UADD8 : AAI<0b01100101, 0b11111001, "uadd8">;
2407 def USAX : AAI<0b01100101, 0b11110101, "usax">;
2408 def USUB16 : AAI<0b01100101, 0b11110111, "usub16">;
2409 def USUB8 : AAI<0b01100101, 0b11111111, "usub8">;
2411 // Signed/Unsigned halving add/subtract -- for disassembly only
2413 def SHASX : AAI<0b01100011, 0b11110011, "shasx">;
2414 def SHADD16 : AAI<0b01100011, 0b11110001, "shadd16">;
2415 def SHADD8 : AAI<0b01100011, 0b11111001, "shadd8">;
2416 def SHSAX : AAI<0b01100011, 0b11110101, "shsax">;
2417 def SHSUB16 : AAI<0b01100011, 0b11110111, "shsub16">;
2418 def SHSUB8 : AAI<0b01100011, 0b11111111, "shsub8">;
2419 def UHASX : AAI<0b01100111, 0b11110011, "uhasx">;
2420 def UHADD16 : AAI<0b01100111, 0b11110001, "uhadd16">;
2421 def UHADD8 : AAI<0b01100111, 0b11111001, "uhadd8">;
2422 def UHSAX : AAI<0b01100111, 0b11110101, "uhsax">;
2423 def UHSUB16 : AAI<0b01100111, 0b11110111, "uhsub16">;
2424 def UHSUB8 : AAI<0b01100111, 0b11111111, "uhsub8">;
2426 // Unsigned Sum of Absolute Differences [and Accumulate] -- for disassembly only
2428 def USAD8 : AI<(outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm),
2429 MulFrm /* for convenience */, NoItinerary, "usad8",
2430 "\t$Rd, $Rn, $Rm", []>,
2431 Requires<[IsARM, HasV6]> {
2435 let Inst{27-20} = 0b01111000;
2436 let Inst{15-12} = 0b1111;
2437 let Inst{7-4} = 0b0001;
2438 let Inst{19-16} = Rd;
2439 let Inst{11-8} = Rm;
2442 def USADA8 : AI<(outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm, GPR:$Ra),
2443 MulFrm /* for convenience */, NoItinerary, "usada8",
2444 "\t$Rd, $Rn, $Rm, $Ra", []>,
2445 Requires<[IsARM, HasV6]> {
2450 let Inst{27-20} = 0b01111000;
2451 let Inst{7-4} = 0b0001;
2452 let Inst{19-16} = Rd;
2453 let Inst{15-12} = Ra;
2454 let Inst{11-8} = Rm;
2458 // Signed/Unsigned saturate -- for disassembly only
2460 def SSAT : AI<(outs GPR:$Rd), (ins i32imm:$sat_imm, GPR:$a, shift_imm:$sh),
2461 SatFrm, NoItinerary, "ssat", "\t$Rd, $sat_imm, $a$sh",
2462 [/* For disassembly only; pattern left blank */]> {
2467 let Inst{27-21} = 0b0110101;
2468 let Inst{5-4} = 0b01;
2469 let Inst{20-16} = sat_imm;
2470 let Inst{15-12} = Rd;
2471 let Inst{11-7} = sh{7-3};
2472 let Inst{6} = sh{0};
2476 def SSAT16 : AI<(outs GPR:$Rd), (ins i32imm:$sat_imm, GPR:$Rn), SatFrm,
2477 NoItinerary, "ssat16", "\t$Rd, $sat_imm, $Rn",
2478 [/* For disassembly only; pattern left blank */]> {
2482 let Inst{27-20} = 0b01101010;
2483 let Inst{11-4} = 0b11110011;
2484 let Inst{15-12} = Rd;
2485 let Inst{19-16} = sat_imm;
2489 def USAT : AI<(outs GPR:$Rd), (ins i32imm:$sat_imm, GPR:$a, shift_imm:$sh),
2490 SatFrm, NoItinerary, "usat", "\t$Rd, $sat_imm, $a$sh",
2491 [/* For disassembly only; pattern left blank */]> {
2496 let Inst{27-21} = 0b0110111;
2497 let Inst{5-4} = 0b01;
2498 let Inst{15-12} = Rd;
2499 let Inst{11-7} = sh{7-3};
2500 let Inst{6} = sh{0};
2501 let Inst{20-16} = sat_imm;
2505 def USAT16 : AI<(outs GPR:$Rd), (ins i32imm:$sat_imm, GPR:$a), SatFrm,
2506 NoItinerary, "usat16", "\t$Rd, $sat_imm, $a",
2507 [/* For disassembly only; pattern left blank */]> {
2511 let Inst{27-20} = 0b01101110;
2512 let Inst{11-4} = 0b11110011;
2513 let Inst{15-12} = Rd;
2514 let Inst{19-16} = sat_imm;
2518 def : ARMV6Pat<(int_arm_ssat GPR:$a, imm:$pos), (SSAT imm:$pos, GPR:$a, 0)>;
2519 def : ARMV6Pat<(int_arm_usat GPR:$a, imm:$pos), (USAT imm:$pos, GPR:$a, 0)>;
2521 //===----------------------------------------------------------------------===//
2522 // Bitwise Instructions.
2525 defm AND : AsI1_bin_irs<0b0000, "and",
2526 IIC_iBITi, IIC_iBITr, IIC_iBITsr,
2527 BinOpFrag<(and node:$LHS, node:$RHS)>, 1>;
2528 defm ORR : AsI1_bin_irs<0b1100, "orr",
2529 IIC_iBITi, IIC_iBITr, IIC_iBITsr,
2530 BinOpFrag<(or node:$LHS, node:$RHS)>, 1>;
2531 defm EOR : AsI1_bin_irs<0b0001, "eor",
2532 IIC_iBITi, IIC_iBITr, IIC_iBITsr,
2533 BinOpFrag<(xor node:$LHS, node:$RHS)>, 1>;
2534 defm BIC : AsI1_bin_irs<0b1110, "bic",
2535 IIC_iBITi, IIC_iBITr, IIC_iBITsr,
2536 BinOpFrag<(and node:$LHS, (not node:$RHS))>>;
2538 def BFC : I<(outs GPR:$Rd), (ins GPR:$src, bf_inv_mask_imm:$imm),
2539 AddrMode1, Size4Bytes, IndexModeNone, DPFrm, IIC_iUNAsi,
2540 "bfc", "\t$Rd, $imm", "$src = $Rd",
2541 [(set GPR:$Rd, (and GPR:$src, bf_inv_mask_imm:$imm))]>,
2542 Requires<[IsARM, HasV6T2]> {
2545 let Inst{27-21} = 0b0111110;
2546 let Inst{6-0} = 0b0011111;
2547 let Inst{15-12} = Rd;
2548 let Inst{11-7} = imm{4-0}; // lsb
2549 let Inst{20-16} = imm{9-5}; // width
2552 // A8.6.18 BFI - Bitfield insert (Encoding A1)
2553 def BFI : I<(outs GPR:$Rd), (ins GPR:$src, GPR:$Rn, bf_inv_mask_imm:$imm),
2554 AddrMode1, Size4Bytes, IndexModeNone, DPFrm, IIC_iUNAsi,
2555 "bfi", "\t$Rd, $Rn, $imm", "$src = $Rd",
2556 [(set GPR:$Rd, (ARMbfi GPR:$src, GPR:$Rn,
2557 bf_inv_mask_imm:$imm))]>,
2558 Requires<[IsARM, HasV6T2]> {
2562 let Inst{27-21} = 0b0111110;
2563 let Inst{6-4} = 0b001; // Rn: Inst{3-0} != 15
2564 let Inst{15-12} = Rd;
2565 let Inst{11-7} = imm{4-0}; // lsb
2566 let Inst{20-16} = imm{9-5}; // width
2570 // GNU as only supports this form of bfi (w/ 4 arguments)
2571 let isAsmParserOnly = 1 in
2572 def BFI4p : I<(outs GPR:$Rd), (ins GPR:$src, GPR:$Rn,
2573 lsb_pos_imm:$lsb, width_imm:$width),
2574 AddrMode1, Size4Bytes, IndexModeNone, DPFrm, IIC_iUNAsi,
2575 "bfi", "\t$Rd, $Rn, $lsb, $width", "$src = $Rd",
2576 []>, Requires<[IsARM, HasV6T2]> {
2581 let Inst{27-21} = 0b0111110;
2582 let Inst{6-4} = 0b001; // Rn: Inst{3-0} != 15
2583 let Inst{15-12} = Rd;
2584 let Inst{11-7} = lsb;
2585 let Inst{20-16} = width; // Custom encoder => lsb+width-1
2589 def MVNr : AsI1<0b1111, (outs GPR:$Rd), (ins GPR:$Rm), DPFrm, IIC_iMVNr,
2590 "mvn", "\t$Rd, $Rm",
2591 [(set GPR:$Rd, (not GPR:$Rm))]>, UnaryDP {
2595 let Inst{19-16} = 0b0000;
2596 let Inst{11-4} = 0b00000000;
2597 let Inst{15-12} = Rd;
2600 def MVNs : AsI1<0b1111, (outs GPR:$Rd), (ins so_reg:$shift), DPSoRegFrm,
2601 IIC_iMVNsr, "mvn", "\t$Rd, $shift",
2602 [(set GPR:$Rd, (not so_reg:$shift))]>, UnaryDP {
2606 let Inst{19-16} = 0b0000;
2607 let Inst{15-12} = Rd;
2608 let Inst{11-0} = shift;
2610 let isReMaterializable = 1, isAsCheapAsAMove = 1, isMoveImm = 1 in
2611 def MVNi : AsI1<0b1111, (outs GPR:$Rd), (ins so_imm:$imm), DPFrm,
2612 IIC_iMVNi, "mvn", "\t$Rd, $imm",
2613 [(set GPR:$Rd, so_imm_not:$imm)]>,UnaryDP {
2617 let Inst{19-16} = 0b0000;
2618 let Inst{15-12} = Rd;
2619 let Inst{11-0} = imm;
2622 def : ARMPat<(and GPR:$src, so_imm_not:$imm),
2623 (BICri GPR:$src, so_imm_not:$imm)>;
2625 //===----------------------------------------------------------------------===//
2626 // Multiply Instructions.
2628 class AsMul1I32<bits<7> opcod, dag oops, dag iops, InstrItinClass itin,
2629 string opc, string asm, list<dag> pattern>
2630 : AsMul1I<opcod, oops, iops, itin, opc, asm, pattern> {
2634 let Inst{19-16} = Rd;
2635 let Inst{11-8} = Rm;
2638 class AsMul1I64<bits<7> opcod, dag oops, dag iops, InstrItinClass itin,
2639 string opc, string asm, list<dag> pattern>
2640 : AsMul1I<opcod, oops, iops, itin, opc, asm, pattern> {
2645 let Inst{19-16} = RdHi;
2646 let Inst{15-12} = RdLo;
2647 let Inst{11-8} = Rm;
2651 let isCommutable = 1 in {
2652 let Constraints = "@earlyclobber $Rd" in
2653 def MULv5: ARMPseudoInst<(outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm,
2654 pred:$p, cc_out:$s),
2655 Size4Bytes, IIC_iMUL32,
2656 [(set GPR:$Rd, (mul GPR:$Rn, GPR:$Rm))]>,
2657 Requires<[IsARM, NoV6]>;
2659 def MUL : AsMul1I32<0b0000000, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm),
2660 IIC_iMUL32, "mul", "\t$Rd, $Rn, $Rm",
2661 [(set GPR:$Rd, (mul GPR:$Rn, GPR:$Rm))]>,
2662 Requires<[IsARM, HasV6]> {
2663 let Inst{15-12} = 0b0000;
2667 let Constraints = "@earlyclobber $Rd" in
2668 def MLAv5: ARMPseudoInst<(outs GPR:$Rd),
2669 (ins GPR:$Rn, GPR:$Rm, GPR:$Ra, pred:$p, cc_out:$s),
2670 Size4Bytes, IIC_iMAC32,
2671 [(set GPR:$Rd, (add (mul GPR:$Rn, GPR:$Rm), GPR:$Ra))]>,
2672 Requires<[IsARM, NoV6]> {
2674 let Inst{15-12} = Ra;
2676 def MLA : AsMul1I32<0b0000001, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm, GPR:$Ra),
2677 IIC_iMAC32, "mla", "\t$Rd, $Rn, $Rm, $Ra",
2678 [(set GPR:$Rd, (add (mul GPR:$Rn, GPR:$Rm), GPR:$Ra))]>,
2679 Requires<[IsARM, HasV6]> {
2681 let Inst{15-12} = Ra;
2684 def MLS : AMul1I<0b0000011, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm, GPR:$Ra),
2685 IIC_iMAC32, "mls", "\t$Rd, $Rn, $Rm, $Ra",
2686 [(set GPR:$Rd, (sub GPR:$Ra, (mul GPR:$Rn, GPR:$Rm)))]>,
2687 Requires<[IsARM, HasV6T2]> {
2692 let Inst{19-16} = Rd;
2693 let Inst{15-12} = Ra;
2694 let Inst{11-8} = Rm;
2698 // Extra precision multiplies with low / high results
2700 let neverHasSideEffects = 1 in {
2701 let isCommutable = 1 in {
2702 let Constraints = "@earlyclobber $RdLo,@earlyclobber $RdHi" in {
2703 def SMULLv5 : ARMPseudoInst<(outs GPR:$RdLo, GPR:$RdHi),
2704 (ins GPR:$Rn, GPR:$Rm, pred:$p, cc_out:$s),
2705 Size4Bytes, IIC_iMUL64, []>,
2706 Requires<[IsARM, NoV6]>;
2708 def UMULLv5 : ARMPseudoInst<(outs GPR:$RdLo, GPR:$RdHi),
2709 (ins GPR:$Rn, GPR:$Rm, pred:$p, cc_out:$s),
2710 Size4Bytes, IIC_iMUL64, []>,
2711 Requires<[IsARM, NoV6]>;
2714 def SMULL : AsMul1I64<0b0000110, (outs GPR:$RdLo, GPR:$RdHi),
2715 (ins GPR:$Rn, GPR:$Rm), IIC_iMUL64,
2716 "smull", "\t$RdLo, $RdHi, $Rn, $Rm", []>,
2717 Requires<[IsARM, HasV6]>;
2719 def UMULL : AsMul1I64<0b0000100, (outs GPR:$RdLo, GPR:$RdHi),
2720 (ins GPR:$Rn, GPR:$Rm), IIC_iMUL64,
2721 "umull", "\t$RdLo, $RdHi, $Rn, $Rm", []>,
2722 Requires<[IsARM, HasV6]>;
2725 // Multiply + accumulate
2726 let Constraints = "@earlyclobber $RdLo,@earlyclobber $RdHi" in {
2727 def SMLALv5 : ARMPseudoInst<(outs GPR:$RdLo, GPR:$RdHi),
2728 (ins GPR:$Rn, GPR:$Rm, pred:$p, cc_out:$s),
2729 Size4Bytes, IIC_iMAC64, []>,
2730 Requires<[IsARM, NoV6]>;
2731 def UMLALv5 : ARMPseudoInst<(outs GPR:$RdLo, GPR:$RdHi),
2732 (ins GPR:$Rn, GPR:$Rm, pred:$p, cc_out:$s),
2733 Size4Bytes, IIC_iMAC64, []>,
2734 Requires<[IsARM, NoV6]>;
2735 def UMAALv5 : ARMPseudoInst<(outs GPR:$RdLo, GPR:$RdHi),
2736 (ins GPR:$Rn, GPR:$Rm, pred:$p, cc_out:$s),
2737 Size4Bytes, IIC_iMAC64, []>,
2738 Requires<[IsARM, NoV6]>;
2742 def SMLAL : AsMul1I64<0b0000111, (outs GPR:$RdLo, GPR:$RdHi),
2743 (ins GPR:$Rn, GPR:$Rm), IIC_iMAC64,
2744 "smlal", "\t$RdLo, $RdHi, $Rn, $Rm", []>,
2745 Requires<[IsARM, HasV6]>;
2746 def UMLAL : AsMul1I64<0b0000101, (outs GPR:$RdLo, GPR:$RdHi),
2747 (ins GPR:$Rn, GPR:$Rm), IIC_iMAC64,
2748 "umlal", "\t$RdLo, $RdHi, $Rn, $Rm", []>,
2749 Requires<[IsARM, HasV6]>;
2751 def UMAAL : AMul1I <0b0000010, (outs GPR:$RdLo, GPR:$RdHi),
2752 (ins GPR:$Rn, GPR:$Rm), IIC_iMAC64,
2753 "umaal", "\t$RdLo, $RdHi, $Rn, $Rm", []>,
2754 Requires<[IsARM, HasV6]> {
2759 let Inst{19-16} = RdLo;
2760 let Inst{15-12} = RdHi;
2761 let Inst{11-8} = Rm;
2764 } // neverHasSideEffects
2766 // Most significant word multiply
2767 def SMMUL : AMul2I <0b0111010, 0b0001, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm),
2768 IIC_iMUL32, "smmul", "\t$Rd, $Rn, $Rm",
2769 [(set GPR:$Rd, (mulhs GPR:$Rn, GPR:$Rm))]>,
2770 Requires<[IsARM, HasV6]> {
2771 let Inst{15-12} = 0b1111;
2774 def SMMULR : AMul2I <0b0111010, 0b0011, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm),
2775 IIC_iMUL32, "smmulr", "\t$Rd, $Rn, $Rm",
2776 [/* For disassembly only; pattern left blank */]>,
2777 Requires<[IsARM, HasV6]> {
2778 let Inst{15-12} = 0b1111;
2781 def SMMLA : AMul2Ia <0b0111010, 0b0001, (outs GPR:$Rd),
2782 (ins GPR:$Rn, GPR:$Rm, GPR:$Ra),
2783 IIC_iMAC32, "smmla", "\t$Rd, $Rn, $Rm, $Ra",
2784 [(set GPR:$Rd, (add (mulhs GPR:$Rn, GPR:$Rm), GPR:$Ra))]>,
2785 Requires<[IsARM, HasV6]>;
2787 def SMMLAR : AMul2Ia <0b0111010, 0b0011, (outs GPR:$Rd),
2788 (ins GPR:$Rn, GPR:$Rm, GPR:$Ra),
2789 IIC_iMAC32, "smmlar", "\t$Rd, $Rn, $Rm, $Ra",
2790 [/* For disassembly only; pattern left blank */]>,
2791 Requires<[IsARM, HasV6]>;
2793 def SMMLS : AMul2Ia <0b0111010, 0b1101, (outs GPR:$Rd),
2794 (ins GPR:$Rn, GPR:$Rm, GPR:$Ra),
2795 IIC_iMAC32, "smmls", "\t$Rd, $Rn, $Rm, $Ra",
2796 [(set GPR:$Rd, (sub GPR:$Ra, (mulhs GPR:$Rn, GPR:$Rm)))]>,
2797 Requires<[IsARM, HasV6]>;
2799 def SMMLSR : AMul2Ia <0b0111010, 0b1111, (outs GPR:$Rd),
2800 (ins GPR:$Rn, GPR:$Rm, GPR:$Ra),
2801 IIC_iMAC32, "smmlsr", "\t$Rd, $Rn, $Rm, $Ra",
2802 [/* For disassembly only; pattern left blank */]>,
2803 Requires<[IsARM, HasV6]>;
2805 multiclass AI_smul<string opc, PatFrag opnode> {
2806 def BB : AMulxyI<0b0001011, 0b00, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm),
2807 IIC_iMUL16, !strconcat(opc, "bb"), "\t$Rd, $Rn, $Rm",
2808 [(set GPR:$Rd, (opnode (sext_inreg GPR:$Rn, i16),
2809 (sext_inreg GPR:$Rm, i16)))]>,
2810 Requires<[IsARM, HasV5TE]>;
2812 def BT : AMulxyI<0b0001011, 0b10, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm),
2813 IIC_iMUL16, !strconcat(opc, "bt"), "\t$Rd, $Rn, $Rm",
2814 [(set GPR:$Rd, (opnode (sext_inreg GPR:$Rn, i16),
2815 (sra GPR:$Rm, (i32 16))))]>,
2816 Requires<[IsARM, HasV5TE]>;
2818 def TB : AMulxyI<0b0001011, 0b01, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm),
2819 IIC_iMUL16, !strconcat(opc, "tb"), "\t$Rd, $Rn, $Rm",
2820 [(set GPR:$Rd, (opnode (sra GPR:$Rn, (i32 16)),
2821 (sext_inreg GPR:$Rm, i16)))]>,
2822 Requires<[IsARM, HasV5TE]>;
2824 def TT : AMulxyI<0b0001011, 0b11, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm),
2825 IIC_iMUL16, !strconcat(opc, "tt"), "\t$Rd, $Rn, $Rm",
2826 [(set GPR:$Rd, (opnode (sra GPR:$Rn, (i32 16)),
2827 (sra GPR:$Rm, (i32 16))))]>,
2828 Requires<[IsARM, HasV5TE]>;
2830 def WB : AMulxyI<0b0001001, 0b01, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm),
2831 IIC_iMUL16, !strconcat(opc, "wb"), "\t$Rd, $Rn, $Rm",
2832 [(set GPR:$Rd, (sra (opnode GPR:$Rn,
2833 (sext_inreg GPR:$Rm, i16)), (i32 16)))]>,
2834 Requires<[IsARM, HasV5TE]>;
2836 def WT : AMulxyI<0b0001001, 0b11, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm),
2837 IIC_iMUL16, !strconcat(opc, "wt"), "\t$Rd, $Rn, $Rm",
2838 [(set GPR:$Rd, (sra (opnode GPR:$Rn,
2839 (sra GPR:$Rm, (i32 16))), (i32 16)))]>,
2840 Requires<[IsARM, HasV5TE]>;
2844 multiclass AI_smla<string opc, PatFrag opnode> {
2845 def BB : AMulxyIa<0b0001000, 0b00, (outs GPR:$Rd),
2846 (ins GPR:$Rn, GPR:$Rm, GPR:$Ra),
2847 IIC_iMAC16, !strconcat(opc, "bb"), "\t$Rd, $Rn, $Rm, $Ra",
2848 [(set GPR:$Rd, (add GPR:$Ra,
2849 (opnode (sext_inreg GPR:$Rn, i16),
2850 (sext_inreg GPR:$Rm, i16))))]>,
2851 Requires<[IsARM, HasV5TE]>;
2853 def BT : AMulxyIa<0b0001000, 0b10, (outs GPR:$Rd),
2854 (ins GPR:$Rn, GPR:$Rm, GPR:$Ra),
2855 IIC_iMAC16, !strconcat(opc, "bt"), "\t$Rd, $Rn, $Rm, $Ra",
2856 [(set GPR:$Rd, (add GPR:$Ra, (opnode (sext_inreg GPR:$Rn, i16),
2857 (sra GPR:$Rm, (i32 16)))))]>,
2858 Requires<[IsARM, HasV5TE]>;
2860 def TB : AMulxyIa<0b0001000, 0b01, (outs GPR:$Rd),
2861 (ins GPR:$Rn, GPR:$Rm, GPR:$Ra),
2862 IIC_iMAC16, !strconcat(opc, "tb"), "\t$Rd, $Rn, $Rm, $Ra",
2863 [(set GPR:$Rd, (add GPR:$Ra, (opnode (sra GPR:$Rn, (i32 16)),
2864 (sext_inreg GPR:$Rm, i16))))]>,
2865 Requires<[IsARM, HasV5TE]>;
2867 def TT : AMulxyIa<0b0001000, 0b11, (outs GPR:$Rd),
2868 (ins GPR:$Rn, GPR:$Rm, GPR:$Ra),
2869 IIC_iMAC16, !strconcat(opc, "tt"), "\t$Rd, $Rn, $Rm, $Ra",
2870 [(set GPR:$Rd, (add GPR:$Ra, (opnode (sra GPR:$Rn, (i32 16)),
2871 (sra GPR:$Rm, (i32 16)))))]>,
2872 Requires<[IsARM, HasV5TE]>;
2874 def WB : AMulxyIa<0b0001001, 0b00, (outs GPR:$Rd),
2875 (ins GPR:$Rn, GPR:$Rm, GPR:$Ra),
2876 IIC_iMAC16, !strconcat(opc, "wb"), "\t$Rd, $Rn, $Rm, $Ra",
2877 [(set GPR:$Rd, (add GPR:$Ra, (sra (opnode GPR:$Rn,
2878 (sext_inreg GPR:$Rm, i16)), (i32 16))))]>,
2879 Requires<[IsARM, HasV5TE]>;
2881 def WT : AMulxyIa<0b0001001, 0b10, (outs GPR:$Rd),
2882 (ins GPR:$Rn, GPR:$Rm, GPR:$Ra),
2883 IIC_iMAC16, !strconcat(opc, "wt"), "\t$Rd, $Rn, $Rm, $Ra",
2884 [(set GPR:$Rd, (add GPR:$Ra, (sra (opnode GPR:$Rn,
2885 (sra GPR:$Rm, (i32 16))), (i32 16))))]>,
2886 Requires<[IsARM, HasV5TE]>;
2889 defm SMUL : AI_smul<"smul", BinOpFrag<(mul node:$LHS, node:$RHS)>>;
2890 defm SMLA : AI_smla<"smla", BinOpFrag<(mul node:$LHS, node:$RHS)>>;
2892 // Halfword multiply accumulate long: SMLAL<x><y> -- for disassembly only
2893 def SMLALBB : AMulxyI64<0b0001010, 0b00, (outs GPR:$RdLo, GPR:$RdHi),
2894 (ins GPR:$Rn, GPR:$Rm),
2895 IIC_iMAC64, "smlalbb", "\t$RdLo, $RdHi, $Rn, $Rm",
2896 [/* For disassembly only; pattern left blank */]>,
2897 Requires<[IsARM, HasV5TE]>;
2899 def SMLALBT : AMulxyI64<0b0001010, 0b10, (outs GPR:$RdLo, GPR:$RdHi),
2900 (ins GPR:$Rn, GPR:$Rm),
2901 IIC_iMAC64, "smlalbt", "\t$RdLo, $RdHi, $Rn, $Rm",
2902 [/* For disassembly only; pattern left blank */]>,
2903 Requires<[IsARM, HasV5TE]>;
2905 def SMLALTB : AMulxyI64<0b0001010, 0b01, (outs GPR:$RdLo, GPR:$RdHi),
2906 (ins GPR:$Rn, GPR:$Rm),
2907 IIC_iMAC64, "smlaltb", "\t$RdLo, $RdHi, $Rn, $Rm",
2908 [/* For disassembly only; pattern left blank */]>,
2909 Requires<[IsARM, HasV5TE]>;
2911 def SMLALTT : AMulxyI64<0b0001010, 0b11, (outs GPR:$RdLo, GPR:$RdHi),
2912 (ins GPR:$Rn, GPR:$Rm),
2913 IIC_iMAC64, "smlaltt", "\t$RdLo, $RdHi, $Rn, $Rm",
2914 [/* For disassembly only; pattern left blank */]>,
2915 Requires<[IsARM, HasV5TE]>;
2917 // Helper class for AI_smld -- for disassembly only
2918 class AMulDualIbase<bit long, bit sub, bit swap, dag oops, dag iops,
2919 InstrItinClass itin, string opc, string asm>
2920 : AI<oops, iops, MulFrm, itin, opc, asm, []>, Requires<[IsARM, HasV6]> {
2927 let Inst{21-20} = 0b00;
2928 let Inst{22} = long;
2929 let Inst{27-23} = 0b01110;
2930 let Inst{11-8} = Rm;
2933 class AMulDualI<bit long, bit sub, bit swap, dag oops, dag iops,
2934 InstrItinClass itin, string opc, string asm>
2935 : AMulDualIbase<long, sub, swap, oops, iops, itin, opc, asm> {
2937 let Inst{15-12} = 0b1111;
2938 let Inst{19-16} = Rd;
2940 class AMulDualIa<bit long, bit sub, bit swap, dag oops, dag iops,
2941 InstrItinClass itin, string opc, string asm>
2942 : AMulDualIbase<long, sub, swap, oops, iops, itin, opc, asm> {
2944 let Inst{15-12} = Ra;
2946 class AMulDualI64<bit long, bit sub, bit swap, dag oops, dag iops,
2947 InstrItinClass itin, string opc, string asm>
2948 : AMulDualIbase<long, sub, swap, oops, iops, itin, opc, asm> {
2951 let Inst{19-16} = RdHi;
2952 let Inst{15-12} = RdLo;
2955 multiclass AI_smld<bit sub, string opc> {
2957 def D : AMulDualIa<0, sub, 0, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm, GPR:$Ra),
2958 NoItinerary, !strconcat(opc, "d"), "\t$Rd, $Rn, $Rm, $Ra">;
2960 def DX: AMulDualIa<0, sub, 1, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm, GPR:$Ra),
2961 NoItinerary, !strconcat(opc, "dx"), "\t$Rd, $Rn, $Rm, $Ra">;
2963 def LD: AMulDualI64<1, sub, 0, (outs GPR:$RdLo,GPR:$RdHi),
2964 (ins GPR:$Rn, GPR:$Rm), NoItinerary,
2965 !strconcat(opc, "ld"), "\t$RdLo, $RdHi, $Rn, $Rm">;
2967 def LDX : AMulDualI64<1, sub, 1, (outs GPR:$RdLo,GPR:$RdHi),
2968 (ins GPR:$Rn, GPR:$Rm), NoItinerary,
2969 !strconcat(opc, "ldx"),"\t$RdLo, $RdHi, $Rn, $Rm">;
2973 defm SMLA : AI_smld<0, "smla">;
2974 defm SMLS : AI_smld<1, "smls">;
2976 multiclass AI_sdml<bit sub, string opc> {
2978 def D : AMulDualI<0, sub, 0, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm),
2979 NoItinerary, !strconcat(opc, "d"), "\t$Rd, $Rn, $Rm">;
2980 def DX : AMulDualI<0, sub, 1, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm),
2981 NoItinerary, !strconcat(opc, "dx"), "\t$Rd, $Rn, $Rm">;
2984 defm SMUA : AI_sdml<0, "smua">;
2985 defm SMUS : AI_sdml<1, "smus">;
2987 //===----------------------------------------------------------------------===//
2988 // Misc. Arithmetic Instructions.
2991 def CLZ : AMiscA1I<0b000010110, 0b0001, (outs GPR:$Rd), (ins GPR:$Rm),
2992 IIC_iUNAr, "clz", "\t$Rd, $Rm",
2993 [(set GPR:$Rd, (ctlz GPR:$Rm))]>, Requires<[IsARM, HasV5T]>;
2995 def RBIT : AMiscA1I<0b01101111, 0b0011, (outs GPR:$Rd), (ins GPR:$Rm),
2996 IIC_iUNAr, "rbit", "\t$Rd, $Rm",
2997 [(set GPR:$Rd, (ARMrbit GPR:$Rm))]>,
2998 Requires<[IsARM, HasV6T2]>;
3000 def REV : AMiscA1I<0b01101011, 0b0011, (outs GPR:$Rd), (ins GPR:$Rm),
3001 IIC_iUNAr, "rev", "\t$Rd, $Rm",
3002 [(set GPR:$Rd, (bswap GPR:$Rm))]>, Requires<[IsARM, HasV6]>;
3004 def REV16 : AMiscA1I<0b01101011, 0b1011, (outs GPR:$Rd), (ins GPR:$Rm),
3005 IIC_iUNAr, "rev16", "\t$Rd, $Rm",
3007 (or (and (srl GPR:$Rm, (i32 8)), 0xFF),
3008 (or (and (shl GPR:$Rm, (i32 8)), 0xFF00),
3009 (or (and (srl GPR:$Rm, (i32 8)), 0xFF0000),
3010 (and (shl GPR:$Rm, (i32 8)), 0xFF000000)))))]>,
3011 Requires<[IsARM, HasV6]>;
3013 def REVSH : AMiscA1I<0b01101111, 0b1011, (outs GPR:$Rd), (ins GPR:$Rm),
3014 IIC_iUNAr, "revsh", "\t$Rd, $Rm",
3017 (or (srl GPR:$Rm, (i32 8)),
3018 (shl GPR:$Rm, (i32 8))), i16))]>,
3019 Requires<[IsARM, HasV6]>;
3021 def : ARMV6Pat<(sext_inreg (or (srl (and GPR:$Rm, 0xFF00), (i32 8)),
3022 (shl GPR:$Rm, (i32 8))), i16),
3025 // Need the AddedComplexity or else MOVs + REV would be chosen.
3026 let AddedComplexity = 5 in
3027 def : ARMV6Pat<(sra (bswap GPR:$Rm), (i32 16)), (REVSH GPR:$Rm)>;
3029 def lsl_shift_imm : SDNodeXForm<imm, [{
3030 unsigned Sh = ARM_AM::getSORegOpc(ARM_AM::lsl, N->getZExtValue());
3031 return CurDAG->getTargetConstant(Sh, MVT::i32);
3034 def lsl_amt : PatLeaf<(i32 imm), [{
3035 return (N->getZExtValue() < 32);
3038 def PKHBT : APKHI<0b01101000, 0, (outs GPR:$Rd),
3039 (ins GPR:$Rn, GPR:$Rm, shift_imm:$sh),
3040 IIC_iALUsi, "pkhbt", "\t$Rd, $Rn, $Rm$sh",
3041 [(set GPR:$Rd, (or (and GPR:$Rn, 0xFFFF),
3042 (and (shl GPR:$Rm, lsl_amt:$sh),
3044 Requires<[IsARM, HasV6]>;
3046 // Alternate cases for PKHBT where identities eliminate some nodes.
3047 def : ARMV6Pat<(or (and GPR:$Rn, 0xFFFF), (and GPR:$Rm, 0xFFFF0000)),
3048 (PKHBT GPR:$Rn, GPR:$Rm, 0)>;
3049 def : ARMV6Pat<(or (and GPR:$Rn, 0xFFFF), (shl GPR:$Rm, imm16_31:$sh)),
3050 (PKHBT GPR:$Rn, GPR:$Rm, (lsl_shift_imm imm16_31:$sh))>;
3052 def asr_shift_imm : SDNodeXForm<imm, [{
3053 unsigned Sh = ARM_AM::getSORegOpc(ARM_AM::asr, N->getZExtValue());
3054 return CurDAG->getTargetConstant(Sh, MVT::i32);
3057 def asr_amt : PatLeaf<(i32 imm), [{
3058 return (N->getZExtValue() <= 32);
3061 // Note: Shifts of 1-15 bits will be transformed to srl instead of sra and
3062 // will match the pattern below.
3063 def PKHTB : APKHI<0b01101000, 1, (outs GPR:$Rd),
3064 (ins GPR:$Rn, GPR:$Rm, shift_imm:$sh),
3065 IIC_iBITsi, "pkhtb", "\t$Rd, $Rn, $Rm$sh",
3066 [(set GPR:$Rd, (or (and GPR:$Rn, 0xFFFF0000),
3067 (and (sra GPR:$Rm, asr_amt:$sh),
3069 Requires<[IsARM, HasV6]>;
3071 // Alternate cases for PKHTB where identities eliminate some nodes. Note that
3072 // a shift amount of 0 is *not legal* here, it is PKHBT instead.
3073 def : ARMV6Pat<(or (and GPR:$src1, 0xFFFF0000), (srl GPR:$src2, imm16_31:$sh)),
3074 (PKHTB GPR:$src1, GPR:$src2, (asr_shift_imm imm16_31:$sh))>;
3075 def : ARMV6Pat<(or (and GPR:$src1, 0xFFFF0000),
3076 (and (srl GPR:$src2, imm1_15:$sh), 0xFFFF)),
3077 (PKHTB GPR:$src1, GPR:$src2, (asr_shift_imm imm1_15:$sh))>;
3079 //===----------------------------------------------------------------------===//
3080 // Comparison Instructions...
3083 defm CMP : AI1_cmp_irs<0b1010, "cmp",
3084 IIC_iCMPi, IIC_iCMPr, IIC_iCMPsr,
3085 BinOpFrag<(ARMcmp node:$LHS, node:$RHS)>>;
3087 // ARMcmpZ can re-use the above instruction definitions.
3088 def : ARMPat<(ARMcmpZ GPR:$src, so_imm:$imm),
3089 (CMPri GPR:$src, so_imm:$imm)>;
3090 def : ARMPat<(ARMcmpZ GPR:$src, GPR:$rhs),
3091 (CMPrr GPR:$src, GPR:$rhs)>;
3092 def : ARMPat<(ARMcmpZ GPR:$src, so_reg:$rhs),
3093 (CMPrs GPR:$src, so_reg:$rhs)>;
3095 // FIXME: We have to be careful when using the CMN instruction and comparison
3096 // with 0. One would expect these two pieces of code should give identical
3112 // However, the CMN gives the *opposite* result when r1 is 0. This is because
3113 // the carry flag is set in the CMP case but not in the CMN case. In short, the
3114 // CMP instruction doesn't perform a truncate of the (logical) NOT of 0 plus the
3115 // value of r0 and the carry bit (because the "carry bit" parameter to
3116 // AddWithCarry is defined as 1 in this case, the carry flag will always be set
3117 // when r0 >= 0). The CMN instruction doesn't perform a NOT of 0 so there is
3118 // never a "carry" when this AddWithCarry is performed (because the "carry bit"
3119 // parameter to AddWithCarry is defined as 0).
3121 // When x is 0 and unsigned:
3125 // ~x + 1 = 0x1 0000 0000
3126 // (-x = 0) != (0x1 0000 0000 = ~x + 1)
3128 // Therefore, we should disable CMN when comparing against zero, until we can
3129 // limit when the CMN instruction is used (when we know that the RHS is not 0 or
3130 // when it's a comparison which doesn't look at the 'carry' flag).
3132 // (See the ARM docs for the "AddWithCarry" pseudo-code.)
3134 // This is related to <rdar://problem/7569620>.
3136 //defm CMN : AI1_cmp_irs<0b1011, "cmn",
3137 // BinOpFrag<(ARMcmp node:$LHS,(ineg node:$RHS))>>;
3139 // Note that TST/TEQ don't set all the same flags that CMP does!
3140 defm TST : AI1_cmp_irs<0b1000, "tst",
3141 IIC_iTSTi, IIC_iTSTr, IIC_iTSTsr,
3142 BinOpFrag<(ARMcmpZ (and_su node:$LHS, node:$RHS), 0)>, 1>;
3143 defm TEQ : AI1_cmp_irs<0b1001, "teq",
3144 IIC_iTSTi, IIC_iTSTr, IIC_iTSTsr,
3145 BinOpFrag<(ARMcmpZ (xor_su node:$LHS, node:$RHS), 0)>, 1>;
3147 defm CMNz : AI1_cmp_irs<0b1011, "cmn",
3148 IIC_iCMPi, IIC_iCMPr, IIC_iCMPsr,
3149 BinOpFrag<(ARMcmpZ node:$LHS,(ineg node:$RHS))>>;
3151 //def : ARMPat<(ARMcmp GPR:$src, so_imm_neg:$imm),
3152 // (CMNri GPR:$src, so_imm_neg:$imm)>;
3154 def : ARMPat<(ARMcmpZ GPR:$src, so_imm_neg:$imm),
3155 (CMNzri GPR:$src, so_imm_neg:$imm)>;
3157 // Pseudo i64 compares for some floating point compares.
3158 let usesCustomInserter = 1, isBranch = 1, isTerminator = 1,
3160 def BCCi64 : PseudoInst<(outs),
3161 (ins i32imm:$cc, GPR:$lhs1, GPR:$lhs2, GPR:$rhs1, GPR:$rhs2, brtarget:$dst),
3163 [(ARMBcci64 imm:$cc, GPR:$lhs1, GPR:$lhs2, GPR:$rhs1, GPR:$rhs2, bb:$dst)]>;
3165 def BCCZi64 : PseudoInst<(outs),
3166 (ins i32imm:$cc, GPR:$lhs1, GPR:$lhs2, brtarget:$dst), IIC_Br,
3167 [(ARMBcci64 imm:$cc, GPR:$lhs1, GPR:$lhs2, 0, 0, bb:$dst)]>;
3168 } // usesCustomInserter
3171 // Conditional moves
3172 // FIXME: should be able to write a pattern for ARMcmov, but can't use
3173 // a two-value operand where a dag node expects two operands. :(
3174 let neverHasSideEffects = 1 in {
3175 def MOVCCr : ARMPseudoInst<(outs GPR:$Rd), (ins GPR:$false, GPR:$Rm, pred:$p),
3176 Size4Bytes, IIC_iCMOVr,
3177 [/*(set GPR:$Rd, (ARMcmov GPR:$false, GPR:$Rm, imm:$cc, CCR:$ccr))*/]>,
3178 RegConstraint<"$false = $Rd">;
3179 def MOVCCs : ARMPseudoInst<(outs GPR:$Rd),
3180 (ins GPR:$false, so_reg:$shift, pred:$p),
3181 Size4Bytes, IIC_iCMOVsr,
3182 [/*(set GPR:$Rd, (ARMcmov GPR:$false, so_reg:$shift, imm:$cc, CCR:$ccr))*/]>,
3183 RegConstraint<"$false = $Rd">;
3185 let isMoveImm = 1 in
3186 def MOVCCi16 : ARMPseudoInst<(outs GPR:$Rd),
3187 (ins GPR:$false, i32imm_hilo16:$imm, pred:$p),
3188 Size4Bytes, IIC_iMOVi,
3190 RegConstraint<"$false = $Rd">, Requires<[IsARM, HasV6T2]>;
3192 let isMoveImm = 1 in
3193 def MOVCCi : ARMPseudoInst<(outs GPR:$Rd),
3194 (ins GPR:$false, so_imm:$imm, pred:$p),
3195 Size4Bytes, IIC_iCMOVi,
3196 [/*(set GPR:$Rd, (ARMcmov GPR:$false, so_imm:$imm, imm:$cc, CCR:$ccr))*/]>,
3197 RegConstraint<"$false = $Rd">;
3199 // Two instruction predicate mov immediate.
3200 let isMoveImm = 1 in
3201 def MOVCCi32imm : ARMPseudoInst<(outs GPR:$Rd),
3202 (ins GPR:$false, i32imm:$src, pred:$p),
3203 Size8Bytes, IIC_iCMOVix2, []>, RegConstraint<"$false = $Rd">;
3205 let isMoveImm = 1 in
3206 def MVNCCi : ARMPseudoInst<(outs GPR:$Rd),
3207 (ins GPR:$false, so_imm:$imm, pred:$p),
3208 Size4Bytes, IIC_iCMOVi,
3209 [/*(set GPR:$Rd, (ARMcmov GPR:$false, so_imm_not:$imm, imm:$cc, CCR:$ccr))*/]>,
3210 RegConstraint<"$false = $Rd">;
3211 } // neverHasSideEffects
3213 //===----------------------------------------------------------------------===//
3214 // Atomic operations intrinsics
3217 def memb_opt : Operand<i32> {
3218 let PrintMethod = "printMemBOption";
3219 let ParserMatchClass = MemBarrierOptOperand;
3222 // memory barriers protect the atomic sequences
3223 let hasSideEffects = 1 in {
3224 def DMB : AInoP<(outs), (ins memb_opt:$opt), MiscFrm, NoItinerary,
3225 "dmb", "\t$opt", [(ARMMemBarrier (i32 imm:$opt))]>,
3226 Requires<[IsARM, HasDB]> {
3228 let Inst{31-4} = 0xf57ff05;
3229 let Inst{3-0} = opt;
3233 def DSB : AInoP<(outs), (ins memb_opt:$opt), MiscFrm, NoItinerary,
3235 [/* For disassembly only; pattern left blank */]>,
3236 Requires<[IsARM, HasDB]> {
3238 let Inst{31-4} = 0xf57ff04;
3239 let Inst{3-0} = opt;
3242 // ISB has only full system option -- for disassembly only
3243 def ISB : AInoP<(outs), (ins), MiscFrm, NoItinerary, "isb", "", []>,
3244 Requires<[IsARM, HasDB]> {
3245 let Inst{31-4} = 0xf57ff06;
3246 let Inst{3-0} = 0b1111;
3249 let usesCustomInserter = 1 in {
3250 let Uses = [CPSR] in {
3251 def ATOMIC_LOAD_ADD_I8 : PseudoInst<
3252 (outs GPR:$dst), (ins GPR:$ptr, GPR:$incr), NoItinerary,
3253 [(set GPR:$dst, (atomic_load_add_8 GPR:$ptr, GPR:$incr))]>;
3254 def ATOMIC_LOAD_SUB_I8 : PseudoInst<
3255 (outs GPR:$dst), (ins GPR:$ptr, GPR:$incr), NoItinerary,
3256 [(set GPR:$dst, (atomic_load_sub_8 GPR:$ptr, GPR:$incr))]>;
3257 def ATOMIC_LOAD_AND_I8 : PseudoInst<
3258 (outs GPR:$dst), (ins GPR:$ptr, GPR:$incr), NoItinerary,
3259 [(set GPR:$dst, (atomic_load_and_8 GPR:$ptr, GPR:$incr))]>;
3260 def ATOMIC_LOAD_OR_I8 : PseudoInst<
3261 (outs GPR:$dst), (ins GPR:$ptr, GPR:$incr), NoItinerary,
3262 [(set GPR:$dst, (atomic_load_or_8 GPR:$ptr, GPR:$incr))]>;
3263 def ATOMIC_LOAD_XOR_I8 : PseudoInst<
3264 (outs GPR:$dst), (ins GPR:$ptr, GPR:$incr), NoItinerary,
3265 [(set GPR:$dst, (atomic_load_xor_8 GPR:$ptr, GPR:$incr))]>;
3266 def ATOMIC_LOAD_NAND_I8 : PseudoInst<
3267 (outs GPR:$dst), (ins GPR:$ptr, GPR:$incr), NoItinerary,
3268 [(set GPR:$dst, (atomic_load_nand_8 GPR:$ptr, GPR:$incr))]>;
3269 def ATOMIC_LOAD_ADD_I16 : PseudoInst<
3270 (outs GPR:$dst), (ins GPR:$ptr, GPR:$incr), NoItinerary,
3271 [(set GPR:$dst, (atomic_load_add_16 GPR:$ptr, GPR:$incr))]>;
3272 def ATOMIC_LOAD_SUB_I16 : PseudoInst<
3273 (outs GPR:$dst), (ins GPR:$ptr, GPR:$incr), NoItinerary,
3274 [(set GPR:$dst, (atomic_load_sub_16 GPR:$ptr, GPR:$incr))]>;
3275 def ATOMIC_LOAD_AND_I16 : PseudoInst<
3276 (outs GPR:$dst), (ins GPR:$ptr, GPR:$incr), NoItinerary,
3277 [(set GPR:$dst, (atomic_load_and_16 GPR:$ptr, GPR:$incr))]>;
3278 def ATOMIC_LOAD_OR_I16 : PseudoInst<
3279 (outs GPR:$dst), (ins GPR:$ptr, GPR:$incr), NoItinerary,
3280 [(set GPR:$dst, (atomic_load_or_16 GPR:$ptr, GPR:$incr))]>;
3281 def ATOMIC_LOAD_XOR_I16 : PseudoInst<
3282 (outs GPR:$dst), (ins GPR:$ptr, GPR:$incr), NoItinerary,
3283 [(set GPR:$dst, (atomic_load_xor_16 GPR:$ptr, GPR:$incr))]>;
3284 def ATOMIC_LOAD_NAND_I16 : PseudoInst<
3285 (outs GPR:$dst), (ins GPR:$ptr, GPR:$incr), NoItinerary,
3286 [(set GPR:$dst, (atomic_load_nand_16 GPR:$ptr, GPR:$incr))]>;
3287 def ATOMIC_LOAD_ADD_I32 : PseudoInst<
3288 (outs GPR:$dst), (ins GPR:$ptr, GPR:$incr), NoItinerary,
3289 [(set GPR:$dst, (atomic_load_add_32 GPR:$ptr, GPR:$incr))]>;
3290 def ATOMIC_LOAD_SUB_I32 : PseudoInst<
3291 (outs GPR:$dst), (ins GPR:$ptr, GPR:$incr), NoItinerary,
3292 [(set GPR:$dst, (atomic_load_sub_32 GPR:$ptr, GPR:$incr))]>;
3293 def ATOMIC_LOAD_AND_I32 : PseudoInst<
3294 (outs GPR:$dst), (ins GPR:$ptr, GPR:$incr), NoItinerary,
3295 [(set GPR:$dst, (atomic_load_and_32 GPR:$ptr, GPR:$incr))]>;
3296 def ATOMIC_LOAD_OR_I32 : PseudoInst<
3297 (outs GPR:$dst), (ins GPR:$ptr, GPR:$incr), NoItinerary,
3298 [(set GPR:$dst, (atomic_load_or_32 GPR:$ptr, GPR:$incr))]>;
3299 def ATOMIC_LOAD_XOR_I32 : PseudoInst<
3300 (outs GPR:$dst), (ins GPR:$ptr, GPR:$incr), NoItinerary,
3301 [(set GPR:$dst, (atomic_load_xor_32 GPR:$ptr, GPR:$incr))]>;
3302 def ATOMIC_LOAD_NAND_I32 : PseudoInst<
3303 (outs GPR:$dst), (ins GPR:$ptr, GPR:$incr), NoItinerary,
3304 [(set GPR:$dst, (atomic_load_nand_32 GPR:$ptr, GPR:$incr))]>;
3306 def ATOMIC_SWAP_I8 : PseudoInst<
3307 (outs GPR:$dst), (ins GPR:$ptr, GPR:$new), NoItinerary,
3308 [(set GPR:$dst, (atomic_swap_8 GPR:$ptr, GPR:$new))]>;
3309 def ATOMIC_SWAP_I16 : PseudoInst<
3310 (outs GPR:$dst), (ins GPR:$ptr, GPR:$new), NoItinerary,
3311 [(set GPR:$dst, (atomic_swap_16 GPR:$ptr, GPR:$new))]>;
3312 def ATOMIC_SWAP_I32 : PseudoInst<
3313 (outs GPR:$dst), (ins GPR:$ptr, GPR:$new), NoItinerary,
3314 [(set GPR:$dst, (atomic_swap_32 GPR:$ptr, GPR:$new))]>;
3316 def ATOMIC_CMP_SWAP_I8 : PseudoInst<
3317 (outs GPR:$dst), (ins GPR:$ptr, GPR:$old, GPR:$new), NoItinerary,
3318 [(set GPR:$dst, (atomic_cmp_swap_8 GPR:$ptr, GPR:$old, GPR:$new))]>;
3319 def ATOMIC_CMP_SWAP_I16 : PseudoInst<
3320 (outs GPR:$dst), (ins GPR:$ptr, GPR:$old, GPR:$new), NoItinerary,
3321 [(set GPR:$dst, (atomic_cmp_swap_16 GPR:$ptr, GPR:$old, GPR:$new))]>;
3322 def ATOMIC_CMP_SWAP_I32 : PseudoInst<
3323 (outs GPR:$dst), (ins GPR:$ptr, GPR:$old, GPR:$new), NoItinerary,
3324 [(set GPR:$dst, (atomic_cmp_swap_32 GPR:$ptr, GPR:$old, GPR:$new))]>;
3328 let mayLoad = 1 in {
3329 def LDREXB : AIldrex<0b10, (outs GPR:$Rt), (ins addrmode7:$addr), NoItinerary,
3330 "ldrexb", "\t$Rt, $addr", []>;
3331 def LDREXH : AIldrex<0b11, (outs GPR:$Rt), (ins addrmode7:$addr), NoItinerary,
3332 "ldrexh", "\t$Rt, $addr", []>;
3333 def LDREX : AIldrex<0b00, (outs GPR:$Rt), (ins addrmode7:$addr), NoItinerary,
3334 "ldrex", "\t$Rt, $addr", []>;
3335 def LDREXD : AIldrex<0b01, (outs GPR:$Rt, GPR:$Rt2), (ins addrmode7:$addr),
3336 NoItinerary, "ldrexd", "\t$Rt, $Rt2, $addr", []>;
3339 let mayStore = 1, Constraints = "@earlyclobber $Rd" in {
3340 def STREXB : AIstrex<0b10, (outs GPR:$Rd), (ins GPR:$Rt, addrmode7:$addr),
3341 NoItinerary, "strexb", "\t$Rd, $Rt, $addr", []>;
3342 def STREXH : AIstrex<0b11, (outs GPR:$Rd), (ins GPR:$Rt, addrmode7:$addr),
3343 NoItinerary, "strexh", "\t$Rd, $Rt, $addr", []>;
3344 def STREX : AIstrex<0b00, (outs GPR:$Rd), (ins GPR:$Rt, addrmode7:$addr),
3345 NoItinerary, "strex", "\t$Rd, $Rt, $addr", []>;
3346 def STREXD : AIstrex<0b01, (outs GPR:$Rd),
3347 (ins GPR:$Rt, GPR:$Rt2, addrmode7:$addr),
3348 NoItinerary, "strexd", "\t$Rd, $Rt, $Rt2, $addr", []>;
3351 // Clear-Exclusive is for disassembly only.
3352 def CLREX : AXI<(outs), (ins), MiscFrm, NoItinerary, "clrex",
3353 [/* For disassembly only; pattern left blank */]>,
3354 Requires<[IsARM, HasV7]> {
3355 let Inst{31-0} = 0b11110101011111111111000000011111;
3358 // SWP/SWPB are deprecated in V6/V7 and for disassembly only.
3359 let mayLoad = 1 in {
3360 def SWP : AIswp<0, (outs GPR:$Rt), (ins GPR:$Rt2, GPR:$Rn), "swp",
3361 [/* For disassembly only; pattern left blank */]>;
3362 def SWPB : AIswp<1, (outs GPR:$Rt), (ins GPR:$Rt2, GPR:$Rn), "swpb",
3363 [/* For disassembly only; pattern left blank */]>;
3366 //===----------------------------------------------------------------------===//
3367 // Coprocessor Instructions.
3370 def CDP : ABI<0b1110, (outs), (ins p_imm:$cop, i32imm:$opc1,
3371 c_imm:$CRd, c_imm:$CRn, c_imm:$CRm, i32imm:$opc2),
3372 NoItinerary, "cdp", "\t$cop, $opc1, $CRd, $CRn, $CRm, $opc2",
3373 [/* For disassembly only; pattern left blank */]> {
3381 let Inst{3-0} = CRm;
3383 let Inst{7-5} = opc2;
3384 let Inst{11-8} = cop;
3385 let Inst{15-12} = CRd;
3386 let Inst{19-16} = CRn;
3387 let Inst{23-20} = opc1;
3390 def CDP2 : ABXI<0b1110, (outs), (ins p_imm:$cop, i32imm:$opc1,
3391 c_imm:$CRd, c_imm:$CRn, c_imm:$CRm, i32imm:$opc2),
3392 NoItinerary, "cdp2\t$cop, $opc1, $CRd, $CRn, $CRm, $opc2",
3393 [/* For disassembly only; pattern left blank */]> {
3394 let Inst{31-28} = 0b1111;
3402 let Inst{3-0} = CRm;
3404 let Inst{7-5} = opc2;
3405 let Inst{11-8} = cop;
3406 let Inst{15-12} = CRd;
3407 let Inst{19-16} = CRn;
3408 let Inst{23-20} = opc1;
3411 class ACI<dag oops, dag iops, string opc, string asm,
3412 IndexMode im = IndexModeNone>
3413 : InoP<oops, iops, AddrModeNone, Size4Bytes, im, BrFrm, NoItinerary,
3414 opc, asm, "", [/* For disassembly only; pattern left blank */]> {
3415 let Inst{27-25} = 0b110;
3418 multiclass LdStCop<bits<4> op31_28, bit load, dag ops, string opc, string cond>{
3420 def _OFFSET : ACI<(outs),
3421 !con((ins nohash_imm:$cop, nohash_imm:$CRd, addrmode2:$addr), ops),
3422 !strconcat(opc, cond), "\tp$cop, cr$CRd, $addr"> {
3423 let Inst{31-28} = op31_28;
3424 let Inst{24} = 1; // P = 1
3425 let Inst{21} = 0; // W = 0
3426 let Inst{22} = 0; // D = 0
3427 let Inst{20} = load;
3430 def _PRE : ACI<(outs),
3431 !con((ins nohash_imm:$cop, nohash_imm:$CRd, addrmode2:$addr), ops),
3432 !strconcat(opc, cond), "\tp$cop, cr$CRd, $addr!", IndexModePre> {
3433 let Inst{31-28} = op31_28;
3434 let Inst{24} = 1; // P = 1
3435 let Inst{21} = 1; // W = 1
3436 let Inst{22} = 0; // D = 0
3437 let Inst{20} = load;
3440 def _POST : ACI<(outs),
3441 !con((ins nohash_imm:$cop, nohash_imm:$CRd, addrmode2:$addr), ops),
3442 !strconcat(opc, cond), "\tp$cop, cr$CRd, $addr", IndexModePost> {
3443 let Inst{31-28} = op31_28;
3444 let Inst{24} = 0; // P = 0
3445 let Inst{21} = 1; // W = 1
3446 let Inst{22} = 0; // D = 0
3447 let Inst{20} = load;
3450 def _OPTION : ACI<(outs),
3451 !con((ins nohash_imm:$cop,nohash_imm:$CRd,GPR:$base, nohash_imm:$option),
3453 !strconcat(opc, cond), "\tp$cop, cr$CRd, [$base], \\{$option\\}"> {
3454 let Inst{31-28} = op31_28;
3455 let Inst{24} = 0; // P = 0
3456 let Inst{23} = 1; // U = 1
3457 let Inst{21} = 0; // W = 0
3458 let Inst{22} = 0; // D = 0
3459 let Inst{20} = load;
3462 def L_OFFSET : ACI<(outs),
3463 !con((ins nohash_imm:$cop, nohash_imm:$CRd, addrmode2:$addr), ops),
3464 !strconcat(!strconcat(opc, "l"), cond), "\tp$cop, cr$CRd, $addr"> {
3465 let Inst{31-28} = op31_28;
3466 let Inst{24} = 1; // P = 1
3467 let Inst{21} = 0; // W = 0
3468 let Inst{22} = 1; // D = 1
3469 let Inst{20} = load;
3472 def L_PRE : ACI<(outs),
3473 !con((ins nohash_imm:$cop, nohash_imm:$CRd, addrmode2:$addr), ops),
3474 !strconcat(!strconcat(opc, "l"), cond), "\tp$cop, cr$CRd, $addr!",
3476 let Inst{31-28} = op31_28;
3477 let Inst{24} = 1; // P = 1
3478 let Inst{21} = 1; // W = 1
3479 let Inst{22} = 1; // D = 1
3480 let Inst{20} = load;
3483 def L_POST : ACI<(outs),
3484 !con((ins nohash_imm:$cop, nohash_imm:$CRd, addrmode2:$addr), ops),
3485 !strconcat(!strconcat(opc, "l"), cond), "\tp$cop, cr$CRd, $addr",
3487 let Inst{31-28} = op31_28;
3488 let Inst{24} = 0; // P = 0
3489 let Inst{21} = 1; // W = 1
3490 let Inst{22} = 1; // D = 1
3491 let Inst{20} = load;
3494 def L_OPTION : ACI<(outs),
3495 !con((ins nohash_imm:$cop, nohash_imm:$CRd,GPR:$base,nohash_imm:$option),
3497 !strconcat(!strconcat(opc, "l"), cond),
3498 "\tp$cop, cr$CRd, [$base], \\{$option\\}"> {
3499 let Inst{31-28} = op31_28;
3500 let Inst{24} = 0; // P = 0
3501 let Inst{23} = 1; // U = 1
3502 let Inst{21} = 0; // W = 0
3503 let Inst{22} = 1; // D = 1
3504 let Inst{20} = load;
3508 defm LDC : LdStCop<{?,?,?,?}, 1, (ins pred:$p), "ldc", "${p}">;
3509 defm LDC2 : LdStCop<0b1111, 1, (ins), "ldc2", "">;
3510 defm STC : LdStCop<{?,?,?,?}, 0, (ins pred:$p), "stc", "${p}">;
3511 defm STC2 : LdStCop<0b1111, 0, (ins), "stc2", "">;
3513 //===----------------------------------------------------------------------===//
3514 // Move between coprocessor and ARM core register -- for disassembly only
3517 class MovRCopro<string opc, bit direction, dag oops, dag iops>
3518 : ABI<0b1110, oops, iops, NoItinerary, opc,
3519 "\t$cop, $opc1, $Rt, $CRn, $CRm, $opc2",
3520 [/* For disassembly only; pattern left blank */]> {
3521 let Inst{20} = direction;
3531 let Inst{15-12} = Rt;
3532 let Inst{11-8} = cop;
3533 let Inst{23-21} = opc1;
3534 let Inst{7-5} = opc2;
3535 let Inst{3-0} = CRm;
3536 let Inst{19-16} = CRn;
3539 def MCR : MovRCopro<"mcr", 0 /* from ARM core register to coprocessor */,
3540 (outs), (ins p_imm:$cop, i32imm:$opc1,
3541 GPR:$Rt, c_imm:$CRn, c_imm:$CRm,
3543 def MRC : MovRCopro<"mrc", 1 /* from coprocessor to ARM core register */,
3544 (outs GPR:$Rt), (ins p_imm:$cop, i32imm:$opc1,
3545 c_imm:$CRn, c_imm:$CRm, i32imm:$opc2)>;
3547 class MovRCopro2<string opc, bit direction, dag oops, dag iops>
3548 : ABXI<0b1110, oops, iops, NoItinerary,
3549 !strconcat(opc, "\t$cop, $opc1, $Rt, $CRn, $CRm, $opc2"),
3550 [/* For disassembly only; pattern left blank */]> {
3551 let Inst{31-28} = 0b1111;
3552 let Inst{20} = direction;
3562 let Inst{15-12} = Rt;
3563 let Inst{11-8} = cop;
3564 let Inst{23-21} = opc1;
3565 let Inst{7-5} = opc2;
3566 let Inst{3-0} = CRm;
3567 let Inst{19-16} = CRn;
3570 def MCR2 : MovRCopro2<"mcr2", 0 /* from ARM core register to coprocessor */,
3571 (outs), (ins p_imm:$cop, i32imm:$opc1,
3572 GPR:$Rt, c_imm:$CRn, c_imm:$CRm,
3574 def MRC2 : MovRCopro2<"mrc2", 1 /* from coprocessor to ARM core register */,
3575 (outs GPR:$Rt), (ins p_imm:$cop, i32imm:$opc1,
3576 c_imm:$CRn, c_imm:$CRm,
3579 class MovRRCopro<string opc, bit direction>
3580 : ABI<0b1100, (outs), (ins p_imm:$cop, i32imm:$opc1,
3581 GPR:$Rt, GPR:$Rt2, c_imm:$CRm),
3582 NoItinerary, opc, "\t$cop, $opc1, $Rt, $Rt2, $CRm",
3583 [/* For disassembly only; pattern left blank */]> {
3584 let Inst{23-21} = 0b010;
3585 let Inst{20} = direction;
3593 let Inst{15-12} = Rt;
3594 let Inst{19-16} = Rt2;
3595 let Inst{11-8} = cop;
3596 let Inst{7-4} = opc1;
3597 let Inst{3-0} = CRm;
3600 def MCRR : MovRRCopro<"mcrr", 0 /* from ARM core register to coprocessor */>;
3601 def MRRC : MovRRCopro<"mrrc", 1 /* from coprocessor to ARM core register */>;
3603 class MovRRCopro2<string opc, bit direction>
3604 : ABXI<0b1100, (outs), (ins p_imm:$cop, i32imm:$opc1,
3605 GPR:$Rt, GPR:$Rt2, c_imm:$CRm),
3606 NoItinerary, !strconcat(opc, "\t$cop, $opc1, $Rt, $Rt2, $CRm"),
3607 [/* For disassembly only; pattern left blank */]> {
3608 let Inst{31-28} = 0b1111;
3609 let Inst{23-21} = 0b010;
3610 let Inst{20} = direction;
3618 let Inst{15-12} = Rt;
3619 let Inst{19-16} = Rt2;
3620 let Inst{11-8} = cop;
3621 let Inst{7-4} = opc1;
3622 let Inst{3-0} = CRm;
3625 def MCRR2 : MovRRCopro2<"mcrr2", 0 /* from ARM core register to coprocessor */>;
3626 def MRRC2 : MovRRCopro2<"mrrc2", 1 /* from coprocessor to ARM core register */>;
3628 //===----------------------------------------------------------------------===//
3629 // Move between special register and ARM core register -- for disassembly only
3632 // Move to ARM core register from Special Register
3633 def MRS : ABI<0b0001, (outs GPR:$Rd), (ins), NoItinerary, "mrs", "\t$Rd, cpsr",
3634 [/* For disassembly only; pattern left blank */]> {
3636 let Inst{23-16} = 0b00001111;
3637 let Inst{15-12} = Rd;
3638 let Inst{7-4} = 0b0000;
3641 def MRSsys : ABI<0b0001, (outs GPR:$Rd), (ins), NoItinerary,"mrs","\t$Rd, spsr",
3642 [/* For disassembly only; pattern left blank */]> {
3644 let Inst{23-16} = 0b01001111;
3645 let Inst{15-12} = Rd;
3646 let Inst{7-4} = 0b0000;
3649 // Move from ARM core register to Special Register
3651 // No need to have both system and application versions, the encodings are the
3652 // same and the assembly parser has no way to distinguish between them. The mask
3653 // operand contains the special register (R Bit) in bit 4 and bits 3-0 contains
3654 // the mask with the fields to be accessed in the special register.
3655 def MSR : ABI<0b0001, (outs), (ins msr_mask:$mask, GPR:$Rn), NoItinerary,
3656 "msr", "\t$mask, $Rn",
3657 [/* For disassembly only; pattern left blank */]> {
3662 let Inst{22} = mask{4}; // R bit
3663 let Inst{21-20} = 0b10;
3664 let Inst{19-16} = mask{3-0};
3665 let Inst{15-12} = 0b1111;
3666 let Inst{11-4} = 0b00000000;
3670 def MSRi : ABI<0b0011, (outs), (ins msr_mask:$mask, so_imm:$a), NoItinerary,
3671 "msr", "\t$mask, $a",
3672 [/* For disassembly only; pattern left blank */]> {
3677 let Inst{22} = mask{4}; // R bit
3678 let Inst{21-20} = 0b10;
3679 let Inst{19-16} = mask{3-0};
3680 let Inst{15-12} = 0b1111;
3684 //===----------------------------------------------------------------------===//
3688 // __aeabi_read_tp preserves the registers r1-r3.
3689 // This is a pseudo inst so that we can get the encoding right,
3690 // complete with fixup for the aeabi_read_tp function.
3692 Defs = [R0, R12, LR, CPSR], Uses = [SP] in {
3693 def TPsoft : PseudoInst<(outs), (ins), IIC_Br,
3694 [(set R0, ARMthread_pointer)]>;
3697 //===----------------------------------------------------------------------===//
3698 // SJLJ Exception handling intrinsics
3699 // eh_sjlj_setjmp() is an instruction sequence to store the return
3700 // address and save #0 in R0 for the non-longjmp case.
3701 // Since by its nature we may be coming from some other function to get
3702 // here, and we're using the stack frame for the containing function to
3703 // save/restore registers, we can't keep anything live in regs across
3704 // the eh_sjlj_setjmp(), else it will almost certainly have been tromped upon
3705 // when we get here from a longjmp(). We force everthing out of registers
3706 // except for our own input by listing the relevant registers in Defs. By
3707 // doing so, we also cause the prologue/epilogue code to actively preserve
3708 // all of the callee-saved resgisters, which is exactly what we want.
3709 // A constant value is passed in $val, and we use the location as a scratch.
3711 // These are pseudo-instructions and are lowered to individual MC-insts, so
3712 // no encoding information is necessary.
3714 [ R0, R1, R2, R3, R4, R5, R6, R7, R8, R9, R10, R11, R12, LR, D0,
3715 D1, D2, D3, D4, D5, D6, D7, D8, D9, D10, D11, D12, D13, D14, D15,
3716 D16, D17, D18, D19, D20, D21, D22, D23, D24, D25, D26, D27, D28, D29, D30,
3717 D31 ], hasSideEffects = 1, isBarrier = 1 in {
3718 def Int_eh_sjlj_setjmp : PseudoInst<(outs), (ins GPR:$src, GPR:$val),
3720 [(set R0, (ARMeh_sjlj_setjmp GPR:$src, GPR:$val))]>,
3721 Requires<[IsARM, HasVFP2]>;
3725 [ R0, R1, R2, R3, R4, R5, R6, R7, R8, R9, R10, R11, R12, LR ],
3726 hasSideEffects = 1, isBarrier = 1 in {
3727 def Int_eh_sjlj_setjmp_nofp : PseudoInst<(outs), (ins GPR:$src, GPR:$val),
3729 [(set R0, (ARMeh_sjlj_setjmp GPR:$src, GPR:$val))]>,
3730 Requires<[IsARM, NoVFP]>;
3733 // FIXME: Non-Darwin version(s)
3734 let isBarrier = 1, hasSideEffects = 1, isTerminator = 1,
3735 Defs = [ R7, LR, SP ] in {
3736 def Int_eh_sjlj_longjmp : PseudoInst<(outs), (ins GPR:$src, GPR:$scratch),
3738 [(ARMeh_sjlj_longjmp GPR:$src, GPR:$scratch)]>,
3739 Requires<[IsARM, IsDarwin]>;
3742 // eh.sjlj.dispatchsetup pseudo-instruction.
3743 // This pseudo is used for ARM, Thumb1 and Thumb2. Any differences are
3744 // handled when the pseudo is expanded (which happens before any passes
3745 // that need the instruction size).
3746 let isBarrier = 1, hasSideEffects = 1 in
3747 def Int_eh_sjlj_dispatchsetup :
3748 PseudoInst<(outs), (ins), NoItinerary,
3749 [(ARMeh_sjlj_dispatchsetup)]>,
3750 Requires<[IsDarwin]>;
3752 //===----------------------------------------------------------------------===//
3753 // Non-Instruction Patterns
3756 // Large immediate handling.
3758 // 32-bit immediate using two piece so_imms or movw + movt.
3759 // This is a single pseudo instruction, the benefit is that it can be remat'd
3760 // as a single unit instead of having to handle reg inputs.
3761 // FIXME: Remove this when we can do generalized remat.
3762 let isReMaterializable = 1, isMoveImm = 1 in
3763 def MOVi32imm : PseudoInst<(outs GPR:$dst), (ins i32imm:$src), IIC_iMOVix2,
3764 [(set GPR:$dst, (arm_i32imm:$src))]>,
3767 // Pseudo instruction that combines movw + movt + add pc (if PIC).
3768 // It also makes it possible to rematerialize the instructions.
3769 // FIXME: Remove this when we can do generalized remat and when machine licm
3770 // can properly the instructions.
3771 let isReMaterializable = 1 in {
3772 def MOV_ga_pcrel : PseudoInst<(outs GPR:$dst), (ins i32imm:$addr),
3774 [(set GPR:$dst, (ARMWrapperPIC tglobaladdr:$addr))]>,
3775 Requires<[IsARM, UseMovt]>;
3777 def MOV_ga_dyn : PseudoInst<(outs GPR:$dst), (ins i32imm:$addr),
3779 [(set GPR:$dst, (ARMWrapperDYN tglobaladdr:$addr))]>,
3780 Requires<[IsARM, UseMovt]>;
3782 let AddedComplexity = 10 in
3783 def MOV_ga_pcrel_ldr : PseudoInst<(outs GPR:$dst), (ins i32imm:$addr),
3785 [(set GPR:$dst, (load (ARMWrapperPIC tglobaladdr:$addr)))]>,
3786 Requires<[IsARM, UseMovt]>;
3787 } // isReMaterializable
3789 // ConstantPool, GlobalAddress, and JumpTable
3790 def : ARMPat<(ARMWrapper tglobaladdr :$dst), (LEApcrel tglobaladdr :$dst)>,
3791 Requires<[IsARM, DontUseMovt]>;
3792 def : ARMPat<(ARMWrapper tconstpool :$dst), (LEApcrel tconstpool :$dst)>;
3793 def : ARMPat<(ARMWrapper tglobaladdr :$dst), (MOVi32imm tglobaladdr :$dst)>,
3794 Requires<[IsARM, UseMovt]>;
3795 def : ARMPat<(ARMWrapperJT tjumptable:$dst, imm:$id),
3796 (LEApcrelJT tjumptable:$dst, imm:$id)>;
3798 // TODO: add,sub,and, 3-instr forms?
3801 def : ARMPat<(ARMtcret tcGPR:$dst),
3802 (TCRETURNri tcGPR:$dst)>, Requires<[IsDarwin]>;
3804 def : ARMPat<(ARMtcret (i32 tglobaladdr:$dst)),
3805 (TCRETURNdi texternalsym:$dst)>, Requires<[IsDarwin]>;
3807 def : ARMPat<(ARMtcret (i32 texternalsym:$dst)),
3808 (TCRETURNdi texternalsym:$dst)>, Requires<[IsDarwin]>;
3810 def : ARMPat<(ARMtcret tcGPR:$dst),
3811 (TCRETURNriND tcGPR:$dst)>, Requires<[IsNotDarwin]>;
3813 def : ARMPat<(ARMtcret (i32 tglobaladdr:$dst)),
3814 (TCRETURNdiND texternalsym:$dst)>, Requires<[IsNotDarwin]>;
3816 def : ARMPat<(ARMtcret (i32 texternalsym:$dst)),
3817 (TCRETURNdiND texternalsym:$dst)>, Requires<[IsNotDarwin]>;
3820 def : ARMPat<(ARMcall texternalsym:$func), (BL texternalsym:$func)>,
3821 Requires<[IsARM, IsNotDarwin]>;
3822 def : ARMPat<(ARMcall texternalsym:$func), (BLr9 texternalsym:$func)>,
3823 Requires<[IsARM, IsDarwin]>;
3825 // zextload i1 -> zextload i8
3826 def : ARMPat<(zextloadi1 addrmode_imm12:$addr), (LDRBi12 addrmode_imm12:$addr)>;
3827 def : ARMPat<(zextloadi1 ldst_so_reg:$addr), (LDRBrs ldst_so_reg:$addr)>;
3829 // extload -> zextload
3830 def : ARMPat<(extloadi1 addrmode_imm12:$addr), (LDRBi12 addrmode_imm12:$addr)>;
3831 def : ARMPat<(extloadi1 ldst_so_reg:$addr), (LDRBrs ldst_so_reg:$addr)>;
3832 def : ARMPat<(extloadi8 addrmode_imm12:$addr), (LDRBi12 addrmode_imm12:$addr)>;
3833 def : ARMPat<(extloadi8 ldst_so_reg:$addr), (LDRBrs ldst_so_reg:$addr)>;
3835 def : ARMPat<(extloadi16 addrmode3:$addr), (LDRH addrmode3:$addr)>;
3837 def : ARMPat<(extloadi8 addrmodepc:$addr), (PICLDRB addrmodepc:$addr)>;
3838 def : ARMPat<(extloadi16 addrmodepc:$addr), (PICLDRH addrmodepc:$addr)>;
3841 def : ARMV5TEPat<(mul (sra (shl GPR:$a, (i32 16)), (i32 16)),
3842 (sra (shl GPR:$b, (i32 16)), (i32 16))),
3843 (SMULBB GPR:$a, GPR:$b)>;
3844 def : ARMV5TEPat<(mul sext_16_node:$a, sext_16_node:$b),
3845 (SMULBB GPR:$a, GPR:$b)>;
3846 def : ARMV5TEPat<(mul (sra (shl GPR:$a, (i32 16)), (i32 16)),
3847 (sra GPR:$b, (i32 16))),
3848 (SMULBT GPR:$a, GPR:$b)>;
3849 def : ARMV5TEPat<(mul sext_16_node:$a, (sra GPR:$b, (i32 16))),
3850 (SMULBT GPR:$a, GPR:$b)>;
3851 def : ARMV5TEPat<(mul (sra GPR:$a, (i32 16)),
3852 (sra (shl GPR:$b, (i32 16)), (i32 16))),
3853 (SMULTB GPR:$a, GPR:$b)>;
3854 def : ARMV5TEPat<(mul (sra GPR:$a, (i32 16)), sext_16_node:$b),
3855 (SMULTB GPR:$a, GPR:$b)>;
3856 def : ARMV5TEPat<(sra (mul GPR:$a, (sra (shl GPR:$b, (i32 16)), (i32 16))),
3858 (SMULWB GPR:$a, GPR:$b)>;
3859 def : ARMV5TEPat<(sra (mul GPR:$a, sext_16_node:$b), (i32 16)),
3860 (SMULWB GPR:$a, GPR:$b)>;
3862 def : ARMV5TEPat<(add GPR:$acc,
3863 (mul (sra (shl GPR:$a, (i32 16)), (i32 16)),
3864 (sra (shl GPR:$b, (i32 16)), (i32 16)))),
3865 (SMLABB GPR:$a, GPR:$b, GPR:$acc)>;
3866 def : ARMV5TEPat<(add GPR:$acc,
3867 (mul sext_16_node:$a, sext_16_node:$b)),
3868 (SMLABB GPR:$a, GPR:$b, GPR:$acc)>;
3869 def : ARMV5TEPat<(add GPR:$acc,
3870 (mul (sra (shl GPR:$a, (i32 16)), (i32 16)),
3871 (sra GPR:$b, (i32 16)))),
3872 (SMLABT GPR:$a, GPR:$b, GPR:$acc)>;
3873 def : ARMV5TEPat<(add GPR:$acc,
3874 (mul sext_16_node:$a, (sra GPR:$b, (i32 16)))),
3875 (SMLABT GPR:$a, GPR:$b, GPR:$acc)>;
3876 def : ARMV5TEPat<(add GPR:$acc,
3877 (mul (sra GPR:$a, (i32 16)),
3878 (sra (shl GPR:$b, (i32 16)), (i32 16)))),
3879 (SMLATB GPR:$a, GPR:$b, GPR:$acc)>;
3880 def : ARMV5TEPat<(add GPR:$acc,
3881 (mul (sra GPR:$a, (i32 16)), sext_16_node:$b)),
3882 (SMLATB GPR:$a, GPR:$b, GPR:$acc)>;
3883 def : ARMV5TEPat<(add GPR:$acc,
3884 (sra (mul GPR:$a, (sra (shl GPR:$b, (i32 16)), (i32 16))),
3886 (SMLAWB GPR:$a, GPR:$b, GPR:$acc)>;
3887 def : ARMV5TEPat<(add GPR:$acc,
3888 (sra (mul GPR:$a, sext_16_node:$b), (i32 16))),
3889 (SMLAWB GPR:$a, GPR:$b, GPR:$acc)>;
3892 // Pre-v7 uses MCR for synchronization barriers.
3893 def : ARMPat<(ARMMemBarrierMCR GPR:$zero), (MCR 15, 0, GPR:$zero, 7, 10, 5)>,
3894 Requires<[IsARM, HasV6]>;
3897 //===----------------------------------------------------------------------===//
3901 include "ARMInstrThumb.td"
3903 //===----------------------------------------------------------------------===//
3907 include "ARMInstrThumb2.td"
3909 //===----------------------------------------------------------------------===//
3910 // Floating Point Support
3913 include "ARMInstrVFP.td"
3915 //===----------------------------------------------------------------------===//
3916 // Advanced SIMD (NEON) Support
3919 include "ARMInstrNEON.td"