1 //===- ARMInstrInfo.td - Target Description for ARM Target -*- tablegen -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file describes the ARM instructions in TableGen format.
12 //===----------------------------------------------------------------------===//
14 //===----------------------------------------------------------------------===//
15 // ARM specific DAG Nodes.
19 def SDT_ARMCallSeqStart : SDCallSeqStart<[ SDTCisVT<0, i32> ]>;
20 def SDT_ARMCallSeqEnd : SDCallSeqEnd<[ SDTCisVT<0, i32>, SDTCisVT<1, i32> ]>;
22 def SDT_ARMSaveCallPC : SDTypeProfile<0, 1, []>;
24 def SDT_ARMcall : SDTypeProfile<0, -1, [SDTCisPtrTy<0>]>;
26 def SDT_ARMCMov : SDTypeProfile<1, 3,
27 [SDTCisSameAs<0, 1>, SDTCisSameAs<0, 2>,
30 def SDT_ARMBrcond : SDTypeProfile<0, 2,
31 [SDTCisVT<0, OtherVT>, SDTCisVT<1, i32>]>;
33 def SDT_ARMBrJT : SDTypeProfile<0, 3,
34 [SDTCisPtrTy<0>, SDTCisVT<1, i32>,
37 def SDT_ARMBr2JT : SDTypeProfile<0, 4,
38 [SDTCisPtrTy<0>, SDTCisVT<1, i32>,
39 SDTCisVT<2, i32>, SDTCisVT<3, i32>]>;
41 def SDT_ARMBCC_i64 : SDTypeProfile<0, 6,
43 SDTCisVT<1, i32>, SDTCisVT<2, i32>,
44 SDTCisVT<3, i32>, SDTCisVT<4, i32>,
45 SDTCisVT<5, OtherVT>]>;
47 def SDT_ARMCmp : SDTypeProfile<0, 2, [SDTCisSameAs<0, 1>]>;
49 def SDT_ARMPICAdd : SDTypeProfile<1, 2, [SDTCisSameAs<0, 1>,
50 SDTCisPtrTy<1>, SDTCisVT<2, i32>]>;
52 def SDT_ARMThreadPointer : SDTypeProfile<1, 0, [SDTCisPtrTy<0>]>;
53 def SDT_ARMEH_SJLJ_Setjmp : SDTypeProfile<1, 2, [SDTCisInt<0>, SDTCisPtrTy<1>,
55 def SDT_ARMEH_SJLJ_Longjmp: SDTypeProfile<0, 2, [SDTCisPtrTy<0>, SDTCisInt<1>]>;
57 def SDT_ARMMEMBARRIERV7 : SDTypeProfile<0, 0, []>;
58 def SDT_ARMSYNCBARRIERV7 : SDTypeProfile<0, 0, []>;
59 def SDT_ARMMEMBARRIERV6 : SDTypeProfile<0, 1, [SDTCisInt<0>]>;
60 def SDT_ARMSYNCBARRIERV6 : SDTypeProfile<0, 1, [SDTCisInt<0>]>;
62 def SDT_ARMTCRET : SDTypeProfile<0, 1, [SDTCisPtrTy<0>]>;
65 def ARMWrapper : SDNode<"ARMISD::Wrapper", SDTIntUnaryOp>;
66 def ARMWrapperJT : SDNode<"ARMISD::WrapperJT", SDTIntBinOp>;
68 def ARMcallseq_start : SDNode<"ISD::CALLSEQ_START", SDT_ARMCallSeqStart,
69 [SDNPHasChain, SDNPOutFlag]>;
70 def ARMcallseq_end : SDNode<"ISD::CALLSEQ_END", SDT_ARMCallSeqEnd,
71 [SDNPHasChain, SDNPOptInFlag, SDNPOutFlag]>;
73 def ARMcall : SDNode<"ARMISD::CALL", SDT_ARMcall,
74 [SDNPHasChain, SDNPOptInFlag, SDNPOutFlag,
76 def ARMcall_pred : SDNode<"ARMISD::CALL_PRED", SDT_ARMcall,
77 [SDNPHasChain, SDNPOptInFlag, SDNPOutFlag,
79 def ARMcall_nolink : SDNode<"ARMISD::CALL_NOLINK", SDT_ARMcall,
80 [SDNPHasChain, SDNPOptInFlag, SDNPOutFlag,
83 def ARMretflag : SDNode<"ARMISD::RET_FLAG", SDTNone,
84 [SDNPHasChain, SDNPOptInFlag]>;
86 def ARMcmov : SDNode<"ARMISD::CMOV", SDT_ARMCMov,
88 def ARMcneg : SDNode<"ARMISD::CNEG", SDT_ARMCMov,
91 def ARMbrcond : SDNode<"ARMISD::BRCOND", SDT_ARMBrcond,
92 [SDNPHasChain, SDNPInFlag, SDNPOutFlag]>;
94 def ARMbrjt : SDNode<"ARMISD::BR_JT", SDT_ARMBrJT,
96 def ARMbr2jt : SDNode<"ARMISD::BR2_JT", SDT_ARMBr2JT,
99 def ARMBcci64 : SDNode<"ARMISD::BCC_i64", SDT_ARMBCC_i64,
102 def ARMcmp : SDNode<"ARMISD::CMP", SDT_ARMCmp,
105 def ARMcmpZ : SDNode<"ARMISD::CMPZ", SDT_ARMCmp,
106 [SDNPOutFlag,SDNPCommutative]>;
108 def ARMpic_add : SDNode<"ARMISD::PIC_ADD", SDT_ARMPICAdd>;
110 def ARMsrl_flag : SDNode<"ARMISD::SRL_FLAG", SDTIntUnaryOp, [SDNPOutFlag]>;
111 def ARMsra_flag : SDNode<"ARMISD::SRA_FLAG", SDTIntUnaryOp, [SDNPOutFlag]>;
112 def ARMrrx : SDNode<"ARMISD::RRX" , SDTIntUnaryOp, [SDNPInFlag ]>;
114 def ARMthread_pointer: SDNode<"ARMISD::THREAD_POINTER", SDT_ARMThreadPointer>;
115 def ARMeh_sjlj_setjmp: SDNode<"ARMISD::EH_SJLJ_SETJMP",
116 SDT_ARMEH_SJLJ_Setjmp, [SDNPHasChain]>;
117 def ARMeh_sjlj_longjmp: SDNode<"ARMISD::EH_SJLJ_LONGJMP",
118 SDT_ARMEH_SJLJ_Longjmp, [SDNPHasChain]>;
120 def ARMMemBarrierV7 : SDNode<"ARMISD::MEMBARRIER", SDT_ARMMEMBARRIERV7,
122 def ARMSyncBarrierV7 : SDNode<"ARMISD::SYNCBARRIER", SDT_ARMMEMBARRIERV7,
124 def ARMMemBarrierV6 : SDNode<"ARMISD::MEMBARRIER", SDT_ARMMEMBARRIERV6,
126 def ARMSyncBarrierV6 : SDNode<"ARMISD::SYNCBARRIER", SDT_ARMMEMBARRIERV6,
129 def ARMrbit : SDNode<"ARMISD::RBIT", SDTIntUnaryOp>;
131 def ARMtcret : SDNode<"ARMISD::TC_RETURN", SDT_ARMTCRET,
132 [SDNPHasChain, SDNPOptInFlag, SDNPVariadic]>;
134 //===----------------------------------------------------------------------===//
135 // ARM Instruction Predicate Definitions.
137 def HasV4T : Predicate<"Subtarget->hasV4TOps()">;
138 def NoV4T : Predicate<"!Subtarget->hasV4TOps()">;
139 def HasV5T : Predicate<"Subtarget->hasV5TOps()">;
140 def HasV5TE : Predicate<"Subtarget->hasV5TEOps()">;
141 def HasV6 : Predicate<"Subtarget->hasV6Ops()">;
142 def HasV6T2 : Predicate<"Subtarget->hasV6T2Ops()">;
143 def NoV6T2 : Predicate<"!Subtarget->hasV6T2Ops()">;
144 def HasV7 : Predicate<"Subtarget->hasV7Ops()">;
145 def NoVFP : Predicate<"!Subtarget->hasVFP2()">;
146 def HasVFP2 : Predicate<"Subtarget->hasVFP2()">;
147 def HasVFP3 : Predicate<"Subtarget->hasVFP3()">;
148 def HasNEON : Predicate<"Subtarget->hasNEON()">;
149 def HasDivide : Predicate<"Subtarget->hasDivide()">;
150 def HasT2ExtractPack : Predicate<"Subtarget->hasT2ExtractPack()">;
151 def UseNEONForFP : Predicate<"Subtarget->useNEONForSinglePrecisionFP()">;
152 def DontUseNEONForFP : Predicate<"!Subtarget->useNEONForSinglePrecisionFP()">;
153 def IsThumb : Predicate<"Subtarget->isThumb()">;
154 def IsThumb1Only : Predicate<"Subtarget->isThumb1Only()">;
155 def IsThumb2 : Predicate<"Subtarget->isThumb2()">;
156 def IsARM : Predicate<"!Subtarget->isThumb()">;
157 def IsDarwin : Predicate<"Subtarget->isTargetDarwin()">;
158 def IsNotDarwin : Predicate<"!Subtarget->isTargetDarwin()">;
160 // FIXME: Eventually this will be just "hasV6T2Ops".
161 def UseMovt : Predicate<"Subtarget->useMovt()">;
162 def DontUseMovt : Predicate<"!Subtarget->useMovt()">;
164 def UseVMLx : Predicate<"Subtarget->useVMLx()">;
166 //===----------------------------------------------------------------------===//
167 // ARM Flag Definitions.
169 class RegConstraint<string C> {
170 string Constraints = C;
173 //===----------------------------------------------------------------------===//
174 // ARM specific transformation functions and pattern fragments.
177 // so_imm_neg_XFORM - Return a so_imm value packed into the format described for
178 // so_imm_neg def below.
179 def so_imm_neg_XFORM : SDNodeXForm<imm, [{
180 return CurDAG->getTargetConstant(-(int)N->getZExtValue(), MVT::i32);
183 // so_imm_not_XFORM - Return a so_imm value packed into the format described for
184 // so_imm_not def below.
185 def so_imm_not_XFORM : SDNodeXForm<imm, [{
186 return CurDAG->getTargetConstant(~(int)N->getZExtValue(), MVT::i32);
189 // rot_imm predicate - True if the 32-bit immediate is equal to 8, 16, or 24.
190 def rot_imm : PatLeaf<(i32 imm), [{
191 int32_t v = (int32_t)N->getZExtValue();
192 return v == 8 || v == 16 || v == 24;
195 /// imm1_15 predicate - True if the 32-bit immediate is in the range [1,15].
196 def imm1_15 : PatLeaf<(i32 imm), [{
197 return (int32_t)N->getZExtValue() >= 1 && (int32_t)N->getZExtValue() < 16;
200 /// imm16_31 predicate - True if the 32-bit immediate is in the range [16,31].
201 def imm16_31 : PatLeaf<(i32 imm), [{
202 return (int32_t)N->getZExtValue() >= 16 && (int32_t)N->getZExtValue() < 32;
207 return ARM_AM::getSOImmVal(-(int)N->getZExtValue()) != -1;
208 }], so_imm_neg_XFORM>;
212 return ARM_AM::getSOImmVal(~(int)N->getZExtValue()) != -1;
213 }], so_imm_not_XFORM>;
215 // sext_16_node predicate - True if the SDNode is sign-extended 16 or more bits.
216 def sext_16_node : PatLeaf<(i32 GPR:$a), [{
217 return CurDAG->ComputeNumSignBits(SDValue(N,0)) >= 17;
220 /// bf_inv_mask_imm predicate - An AND mask to clear an arbitrary width bitfield
222 def bf_inv_mask_imm : Operand<i32>,
224 uint32_t v = (uint32_t)N->getZExtValue();
227 // there can be 1's on either or both "outsides", all the "inside"
229 unsigned int lsb = 0, msb = 31;
230 while (v & (1 << msb)) --msb;
231 while (v & (1 << lsb)) ++lsb;
232 for (unsigned int i = lsb; i <= msb; ++i) {
238 let PrintMethod = "printBitfieldInvMaskImmOperand";
241 /// Split a 32-bit immediate into two 16 bit parts.
242 def lo16 : SDNodeXForm<imm, [{
243 return CurDAG->getTargetConstant((uint32_t)N->getZExtValue() & 0xffff,
247 def hi16 : SDNodeXForm<imm, [{
248 return CurDAG->getTargetConstant((uint32_t)N->getZExtValue() >> 16, MVT::i32);
251 def lo16AllZero : PatLeaf<(i32 imm), [{
252 // Returns true if all low 16-bits are 0.
253 return (((uint32_t)N->getZExtValue()) & 0xFFFFUL) == 0;
256 /// imm0_65535 predicate - True if the 32-bit immediate is in the range
258 def imm0_65535 : PatLeaf<(i32 imm), [{
259 return (uint32_t)N->getZExtValue() < 65536;
262 class BinOpFrag<dag res> : PatFrag<(ops node:$LHS, node:$RHS), res>;
263 class UnOpFrag <dag res> : PatFrag<(ops node:$Src), res>;
265 /// adde and sube predicates - True based on whether the carry flag output
266 /// will be needed or not.
267 def adde_dead_carry :
268 PatFrag<(ops node:$LHS, node:$RHS), (adde node:$LHS, node:$RHS),
269 [{return !N->hasAnyUseOfValue(1);}]>;
270 def sube_dead_carry :
271 PatFrag<(ops node:$LHS, node:$RHS), (sube node:$LHS, node:$RHS),
272 [{return !N->hasAnyUseOfValue(1);}]>;
273 def adde_live_carry :
274 PatFrag<(ops node:$LHS, node:$RHS), (adde node:$LHS, node:$RHS),
275 [{return N->hasAnyUseOfValue(1);}]>;
276 def sube_live_carry :
277 PatFrag<(ops node:$LHS, node:$RHS), (sube node:$LHS, node:$RHS),
278 [{return N->hasAnyUseOfValue(1);}]>;
280 //===----------------------------------------------------------------------===//
281 // Operand Definitions.
285 def brtarget : Operand<OtherVT>;
287 // A list of registers separated by comma. Used by load/store multiple.
288 def reglist : Operand<i32> {
289 let PrintMethod = "printRegisterList";
292 // An operand for the CONSTPOOL_ENTRY pseudo-instruction.
293 def cpinst_operand : Operand<i32> {
294 let PrintMethod = "printCPInstOperand";
297 def jtblock_operand : Operand<i32> {
298 let PrintMethod = "printJTBlockOperand";
300 def jt2block_operand : Operand<i32> {
301 let PrintMethod = "printJT2BlockOperand";
305 def pclabel : Operand<i32> {
306 let PrintMethod = "printPCLabel";
309 // shifter_operand operands: so_reg and so_imm.
310 def so_reg : Operand<i32>, // reg reg imm
311 ComplexPattern<i32, 3, "SelectShifterOperandReg",
312 [shl,srl,sra,rotr]> {
313 let PrintMethod = "printSORegOperand";
314 let MIOperandInfo = (ops GPR, GPR, i32imm);
317 // so_imm - Match a 32-bit shifter_operand immediate operand, which is an
318 // 8-bit immediate rotated by an arbitrary number of bits. so_imm values are
319 // represented in the imm field in the same 12-bit form that they are encoded
320 // into so_imm instructions: the 8-bit immediate is the least significant bits
321 // [bits 0-7], the 4-bit shift amount is the next 4 bits [bits 8-11].
322 def so_imm : Operand<i32>,
324 return ARM_AM::getSOImmVal(N->getZExtValue()) != -1;
326 let PrintMethod = "printSOImmOperand";
329 // Break so_imm's up into two pieces. This handles immediates with up to 16
330 // bits set in them. This uses so_imm2part to match and so_imm2part_[12] to
331 // get the first/second pieces.
332 def so_imm2part : Operand<i32>,
334 return ARM_AM::isSOImmTwoPartVal((unsigned)N->getZExtValue());
336 let PrintMethod = "printSOImm2PartOperand";
339 def so_imm2part_1 : SDNodeXForm<imm, [{
340 unsigned V = ARM_AM::getSOImmTwoPartFirst((unsigned)N->getZExtValue());
341 return CurDAG->getTargetConstant(V, MVT::i32);
344 def so_imm2part_2 : SDNodeXForm<imm, [{
345 unsigned V = ARM_AM::getSOImmTwoPartSecond((unsigned)N->getZExtValue());
346 return CurDAG->getTargetConstant(V, MVT::i32);
349 def so_neg_imm2part : Operand<i32>, PatLeaf<(imm), [{
350 return ARM_AM::isSOImmTwoPartVal(-(int)N->getZExtValue());
352 let PrintMethod = "printSOImm2PartOperand";
355 def so_neg_imm2part_1 : SDNodeXForm<imm, [{
356 unsigned V = ARM_AM::getSOImmTwoPartFirst(-(int)N->getZExtValue());
357 return CurDAG->getTargetConstant(V, MVT::i32);
360 def so_neg_imm2part_2 : SDNodeXForm<imm, [{
361 unsigned V = ARM_AM::getSOImmTwoPartSecond(-(int)N->getZExtValue());
362 return CurDAG->getTargetConstant(V, MVT::i32);
365 /// imm0_31 predicate - True if the 32-bit immediate is in the range [0,31].
366 def imm0_31 : Operand<i32>, PatLeaf<(imm), [{
367 return (int32_t)N->getZExtValue() < 32;
370 // Define ARM specific addressing modes.
372 // addrmode2 := reg +/- reg shop imm
373 // addrmode2 := reg +/- imm12
375 def addrmode2 : Operand<i32>,
376 ComplexPattern<i32, 3, "SelectAddrMode2", []> {
377 let PrintMethod = "printAddrMode2Operand";
378 let MIOperandInfo = (ops GPR:$base, GPR:$offsreg, i32imm:$offsimm);
381 def am2offset : Operand<i32>,
382 ComplexPattern<i32, 2, "SelectAddrMode2Offset", []> {
383 let PrintMethod = "printAddrMode2OffsetOperand";
384 let MIOperandInfo = (ops GPR, i32imm);
387 // addrmode3 := reg +/- reg
388 // addrmode3 := reg +/- imm8
390 def addrmode3 : Operand<i32>,
391 ComplexPattern<i32, 3, "SelectAddrMode3", []> {
392 let PrintMethod = "printAddrMode3Operand";
393 let MIOperandInfo = (ops GPR:$base, GPR:$offsreg, i32imm:$offsimm);
396 def am3offset : Operand<i32>,
397 ComplexPattern<i32, 2, "SelectAddrMode3Offset", []> {
398 let PrintMethod = "printAddrMode3OffsetOperand";
399 let MIOperandInfo = (ops GPR, i32imm);
402 // addrmode4 := reg, <mode|W>
404 def addrmode4 : Operand<i32>,
405 ComplexPattern<i32, 2, "SelectAddrMode4", []> {
406 let PrintMethod = "printAddrMode4Operand";
407 let MIOperandInfo = (ops GPR:$addr, i32imm);
410 // addrmode5 := reg +/- imm8*4
412 def addrmode5 : Operand<i32>,
413 ComplexPattern<i32, 2, "SelectAddrMode5", []> {
414 let PrintMethod = "printAddrMode5Operand";
415 let MIOperandInfo = (ops GPR:$base, i32imm);
418 // addrmode6 := reg with optional writeback
420 def addrmode6 : Operand<i32>,
421 ComplexPattern<i32, 2, "SelectAddrMode6", []> {
422 let PrintMethod = "printAddrMode6Operand";
423 let MIOperandInfo = (ops GPR:$addr, i32imm);
426 def am6offset : Operand<i32> {
427 let PrintMethod = "printAddrMode6OffsetOperand";
428 let MIOperandInfo = (ops GPR);
431 // addrmodepc := pc + reg
433 def addrmodepc : Operand<i32>,
434 ComplexPattern<i32, 2, "SelectAddrModePC", []> {
435 let PrintMethod = "printAddrModePCOperand";
436 let MIOperandInfo = (ops GPR, i32imm);
439 def nohash_imm : Operand<i32> {
440 let PrintMethod = "printNoHashImmediate";
443 //===----------------------------------------------------------------------===//
445 include "ARMInstrFormats.td"
447 //===----------------------------------------------------------------------===//
448 // Multiclass helpers...
451 /// AsI1_bin_irs - Defines a set of (op r, {so_imm|r|so_reg}) patterns for a
452 /// binop that produces a value.
453 multiclass AsI1_bin_irs<bits<4> opcod, string opc, PatFrag opnode,
454 bit Commutable = 0> {
455 def ri : AsI1<opcod, (outs GPR:$dst), (ins GPR:$a, so_imm:$b), DPFrm,
456 IIC_iALUi, opc, "\t$dst, $a, $b",
457 [(set GPR:$dst, (opnode GPR:$a, so_imm:$b))]> {
460 def rr : AsI1<opcod, (outs GPR:$dst), (ins GPR:$a, GPR:$b), DPFrm,
461 IIC_iALUr, opc, "\t$dst, $a, $b",
462 [(set GPR:$dst, (opnode GPR:$a, GPR:$b))]> {
463 let Inst{11-4} = 0b00000000;
465 let isCommutable = Commutable;
467 def rs : AsI1<opcod, (outs GPR:$dst), (ins GPR:$a, so_reg:$b), DPSoRegFrm,
468 IIC_iALUsr, opc, "\t$dst, $a, $b",
469 [(set GPR:$dst, (opnode GPR:$a, so_reg:$b))]> {
474 /// AI1_bin_s_irs - Similar to AsI1_bin_irs except it sets the 's' bit so the
475 /// instruction modifies the CPSR register.
476 let Defs = [CPSR] in {
477 multiclass AI1_bin_s_irs<bits<4> opcod, string opc, PatFrag opnode,
478 bit Commutable = 0> {
479 def ri : AI1<opcod, (outs GPR:$dst), (ins GPR:$a, so_imm:$b), DPFrm,
480 IIC_iALUi, opc, "\t$dst, $a, $b",
481 [(set GPR:$dst, (opnode GPR:$a, so_imm:$b))]> {
485 def rr : AI1<opcod, (outs GPR:$dst), (ins GPR:$a, GPR:$b), DPFrm,
486 IIC_iALUr, opc, "\t$dst, $a, $b",
487 [(set GPR:$dst, (opnode GPR:$a, GPR:$b))]> {
488 let isCommutable = Commutable;
489 let Inst{11-4} = 0b00000000;
493 def rs : AI1<opcod, (outs GPR:$dst), (ins GPR:$a, so_reg:$b), DPSoRegFrm,
494 IIC_iALUsr, opc, "\t$dst, $a, $b",
495 [(set GPR:$dst, (opnode GPR:$a, so_reg:$b))]> {
502 /// AI1_cmp_irs - Defines a set of (op r, {so_imm|r|so_reg}) cmp / test
503 /// patterns. Similar to AsI1_bin_irs except the instruction does not produce
504 /// a explicit result, only implicitly set CPSR.
505 let Defs = [CPSR] in {
506 multiclass AI1_cmp_irs<bits<4> opcod, string opc, PatFrag opnode,
507 bit Commutable = 0> {
508 def ri : AI1<opcod, (outs), (ins GPR:$a, so_imm:$b), DPFrm, IIC_iCMPi,
510 [(opnode GPR:$a, so_imm:$b)]> {
514 def rr : AI1<opcod, (outs), (ins GPR:$a, GPR:$b), DPFrm, IIC_iCMPr,
516 [(opnode GPR:$a, GPR:$b)]> {
517 let Inst{11-4} = 0b00000000;
520 let isCommutable = Commutable;
522 def rs : AI1<opcod, (outs), (ins GPR:$a, so_reg:$b), DPSoRegFrm, IIC_iCMPsr,
524 [(opnode GPR:$a, so_reg:$b)]> {
531 /// AI_unary_rrot - A unary operation with two forms: one whose operand is a
532 /// register and one whose operand is a register rotated by 8/16/24.
533 /// FIXME: Remove the 'r' variant. Its rot_imm is zero.
534 multiclass AI_unary_rrot<bits<8> opcod, string opc, PatFrag opnode> {
535 def r : AExtI<opcod, (outs GPR:$dst), (ins GPR:$src),
536 IIC_iUNAr, opc, "\t$dst, $src",
537 [(set GPR:$dst, (opnode GPR:$src))]>,
538 Requires<[IsARM, HasV6]> {
539 let Inst{11-10} = 0b00;
540 let Inst{19-16} = 0b1111;
542 def r_rot : AExtI<opcod, (outs GPR:$dst), (ins GPR:$src, i32imm:$rot),
543 IIC_iUNAsi, opc, "\t$dst, $src, ror $rot",
544 [(set GPR:$dst, (opnode (rotr GPR:$src, rot_imm:$rot)))]>,
545 Requires<[IsARM, HasV6]> {
546 let Inst{19-16} = 0b1111;
550 multiclass AI_unary_rrot_np<bits<8> opcod, string opc> {
551 def r : AExtI<opcod, (outs GPR:$dst), (ins GPR:$src),
552 IIC_iUNAr, opc, "\t$dst, $src",
553 [/* For disassembly only; pattern left blank */]>,
554 Requires<[IsARM, HasV6]> {
555 let Inst{11-10} = 0b00;
556 let Inst{19-16} = 0b1111;
558 def r_rot : AExtI<opcod, (outs GPR:$dst), (ins GPR:$src, i32imm:$rot),
559 IIC_iUNAsi, opc, "\t$dst, $src, ror $rot",
560 [/* For disassembly only; pattern left blank */]>,
561 Requires<[IsARM, HasV6]> {
562 let Inst{19-16} = 0b1111;
566 /// AI_bin_rrot - A binary operation with two forms: one whose operand is a
567 /// register and one whose operand is a register rotated by 8/16/24.
568 multiclass AI_bin_rrot<bits<8> opcod, string opc, PatFrag opnode> {
569 def rr : AExtI<opcod, (outs GPR:$dst), (ins GPR:$LHS, GPR:$RHS),
570 IIC_iALUr, opc, "\t$dst, $LHS, $RHS",
571 [(set GPR:$dst, (opnode GPR:$LHS, GPR:$RHS))]>,
572 Requires<[IsARM, HasV6]> {
573 let Inst{11-10} = 0b00;
575 def rr_rot : AExtI<opcod, (outs GPR:$dst), (ins GPR:$LHS, GPR:$RHS,
577 IIC_iALUsi, opc, "\t$dst, $LHS, $RHS, ror $rot",
578 [(set GPR:$dst, (opnode GPR:$LHS,
579 (rotr GPR:$RHS, rot_imm:$rot)))]>,
580 Requires<[IsARM, HasV6]>;
583 // For disassembly only.
584 multiclass AI_bin_rrot_np<bits<8> opcod, string opc> {
585 def rr : AExtI<opcod, (outs GPR:$dst), (ins GPR:$LHS, GPR:$RHS),
586 IIC_iALUr, opc, "\t$dst, $LHS, $RHS",
587 [/* For disassembly only; pattern left blank */]>,
588 Requires<[IsARM, HasV6]> {
589 let Inst{11-10} = 0b00;
591 def rr_rot : AExtI<opcod, (outs GPR:$dst), (ins GPR:$LHS, GPR:$RHS,
593 IIC_iALUsi, opc, "\t$dst, $LHS, $RHS, ror $rot",
594 [/* For disassembly only; pattern left blank */]>,
595 Requires<[IsARM, HasV6]>;
598 /// AI1_adde_sube_irs - Define instructions and patterns for adde and sube.
599 let Uses = [CPSR] in {
600 multiclass AI1_adde_sube_irs<bits<4> opcod, string opc, PatFrag opnode,
601 bit Commutable = 0> {
602 def ri : AsI1<opcod, (outs GPR:$dst), (ins GPR:$a, so_imm:$b),
603 DPFrm, IIC_iALUi, opc, "\t$dst, $a, $b",
604 [(set GPR:$dst, (opnode GPR:$a, so_imm:$b))]>,
608 def rr : AsI1<opcod, (outs GPR:$dst), (ins GPR:$a, GPR:$b),
609 DPFrm, IIC_iALUr, opc, "\t$dst, $a, $b",
610 [(set GPR:$dst, (opnode GPR:$a, GPR:$b))]>,
612 let isCommutable = Commutable;
613 let Inst{11-4} = 0b00000000;
616 def rs : AsI1<opcod, (outs GPR:$dst), (ins GPR:$a, so_reg:$b),
617 DPSoRegFrm, IIC_iALUsr, opc, "\t$dst, $a, $b",
618 [(set GPR:$dst, (opnode GPR:$a, so_reg:$b))]>,
623 // Carry setting variants
624 let Defs = [CPSR] in {
625 multiclass AI1_adde_sube_s_irs<bits<4> opcod, string opc, PatFrag opnode,
626 bit Commutable = 0> {
627 def Sri : AXI1<opcod, (outs GPR:$dst), (ins GPR:$a, so_imm:$b),
628 DPFrm, IIC_iALUi, !strconcat(opc, "\t$dst, $a, $b"),
629 [(set GPR:$dst, (opnode GPR:$a, so_imm:$b))]>,
634 def Srr : AXI1<opcod, (outs GPR:$dst), (ins GPR:$a, GPR:$b),
635 DPFrm, IIC_iALUr, !strconcat(opc, "\t$dst, $a, $b"),
636 [(set GPR:$dst, (opnode GPR:$a, GPR:$b))]>,
638 let Inst{11-4} = 0b00000000;
642 def Srs : AXI1<opcod, (outs GPR:$dst), (ins GPR:$a, so_reg:$b),
643 DPSoRegFrm, IIC_iALUsr, !strconcat(opc, "\t$dst, $a, $b"),
644 [(set GPR:$dst, (opnode GPR:$a, so_reg:$b))]>,
653 //===----------------------------------------------------------------------===//
655 //===----------------------------------------------------------------------===//
657 //===----------------------------------------------------------------------===//
658 // Miscellaneous Instructions.
661 /// CONSTPOOL_ENTRY - This instruction represents a floating constant pool in
662 /// the function. The first operand is the ID# for this instruction, the second
663 /// is the index into the MachineConstantPool that this is, the third is the
664 /// size in bytes of this constant pool entry.
665 let neverHasSideEffects = 1, isNotDuplicable = 1 in
666 def CONSTPOOL_ENTRY :
667 PseudoInst<(outs), (ins cpinst_operand:$instid, cpinst_operand:$cpidx,
668 i32imm:$size), NoItinerary,
669 "${instid:label} ${cpidx:cpentry}", []>;
671 // FIXME: Marking these as hasSideEffects is necessary to prevent machine DCE
672 // from removing one half of the matched pairs. That breaks PEI, which assumes
673 // these will always be in pairs, and asserts if it finds otherwise. Better way?
674 let Defs = [SP], Uses = [SP], hasSideEffects = 1 in {
676 PseudoInst<(outs), (ins i32imm:$amt1, i32imm:$amt2, pred:$p), NoItinerary,
677 "${:comment} ADJCALLSTACKUP $amt1",
678 [(ARMcallseq_end timm:$amt1, timm:$amt2)]>;
680 def ADJCALLSTACKDOWN :
681 PseudoInst<(outs), (ins i32imm:$amt, pred:$p), NoItinerary,
682 "${:comment} ADJCALLSTACKDOWN $amt",
683 [(ARMcallseq_start timm:$amt)]>;
686 def NOP : AI<(outs), (ins), MiscFrm, NoItinerary, "nop", "",
687 [/* For disassembly only; pattern left blank */]>,
688 Requires<[IsARM, HasV6T2]> {
689 let Inst{27-16} = 0b001100100000;
690 let Inst{7-0} = 0b00000000;
693 def YIELD : AI<(outs), (ins), MiscFrm, NoItinerary, "yield", "",
694 [/* For disassembly only; pattern left blank */]>,
695 Requires<[IsARM, HasV6T2]> {
696 let Inst{27-16} = 0b001100100000;
697 let Inst{7-0} = 0b00000001;
700 def WFE : AI<(outs), (ins), MiscFrm, NoItinerary, "wfe", "",
701 [/* For disassembly only; pattern left blank */]>,
702 Requires<[IsARM, HasV6T2]> {
703 let Inst{27-16} = 0b001100100000;
704 let Inst{7-0} = 0b00000010;
707 def WFI : AI<(outs), (ins), MiscFrm, NoItinerary, "wfi", "",
708 [/* For disassembly only; pattern left blank */]>,
709 Requires<[IsARM, HasV6T2]> {
710 let Inst{27-16} = 0b001100100000;
711 let Inst{7-0} = 0b00000011;
714 def SEL : AI<(outs GPR:$dst), (ins GPR:$a, GPR:$b), DPFrm, NoItinerary, "sel",
716 [/* For disassembly only; pattern left blank */]>,
717 Requires<[IsARM, HasV6]> {
718 let Inst{27-20} = 0b01101000;
719 let Inst{7-4} = 0b1011;
722 def SEV : AI<(outs), (ins), MiscFrm, NoItinerary, "sev", "",
723 [/* For disassembly only; pattern left blank */]>,
724 Requires<[IsARM, HasV6T2]> {
725 let Inst{27-16} = 0b001100100000;
726 let Inst{7-0} = 0b00000100;
729 // The i32imm operand $val can be used by a debugger to store more information
730 // about the breakpoint.
731 def BKPT : AI<(outs), (ins i32imm:$val), MiscFrm, NoItinerary, "bkpt", "\t$val",
732 [/* For disassembly only; pattern left blank */]>,
734 let Inst{27-20} = 0b00010010;
735 let Inst{7-4} = 0b0111;
738 // Change Processor State is a system instruction -- for disassembly only.
739 // The singleton $opt operand contains the following information:
740 // opt{4-0} = mode from Inst{4-0}
741 // opt{5} = changemode from Inst{17}
742 // opt{8-6} = AIF from Inst{8-6}
743 // opt{10-9} = imod from Inst{19-18} with 0b10 as enable and 0b11 as disable
744 def CPS : AXI<(outs), (ins cps_opt:$opt), MiscFrm, NoItinerary, "cps$opt",
745 [/* For disassembly only; pattern left blank */]>,
747 let Inst{31-28} = 0b1111;
748 let Inst{27-20} = 0b00010000;
753 // Preload signals the memory system of possible future data/instruction access.
754 // These are for disassembly only.
756 // A8.6.117, A8.6.118. Different instructions are generated for #0 and #-0.
757 // The neg_zero operand translates -0 to -1, -1 to -2, ..., etc.
758 multiclass APreLoad<bit data, bit read, string opc> {
760 def i : AXI<(outs), (ins GPR:$base, neg_zero:$imm), MiscFrm, NoItinerary,
761 !strconcat(opc, "\t[$base, $imm]"), []> {
762 let Inst{31-26} = 0b111101;
763 let Inst{25} = 0; // 0 for immediate form
766 let Inst{21-20} = 0b01;
769 def r : AXI<(outs), (ins addrmode2:$addr), MiscFrm, NoItinerary,
770 !strconcat(opc, "\t$addr"), []> {
771 let Inst{31-26} = 0b111101;
772 let Inst{25} = 1; // 1 for register form
775 let Inst{21-20} = 0b01;
780 defm PLD : APreLoad<1, 1, "pld">;
781 defm PLDW : APreLoad<1, 0, "pldw">;
782 defm PLI : APreLoad<0, 1, "pli">;
784 def SETENDBE : AXI<(outs),(ins), MiscFrm, NoItinerary, "setend\tbe",
785 [/* For disassembly only; pattern left blank */]>,
787 let Inst{31-28} = 0b1111;
788 let Inst{27-20} = 0b00010000;
791 let Inst{7-4} = 0b0000;
794 def SETENDLE : AXI<(outs),(ins), MiscFrm, NoItinerary, "setend\tle",
795 [/* For disassembly only; pattern left blank */]>,
797 let Inst{31-28} = 0b1111;
798 let Inst{27-20} = 0b00010000;
801 let Inst{7-4} = 0b0000;
804 def DBG : AI<(outs), (ins i32imm:$opt), MiscFrm, NoItinerary, "dbg", "\t$opt",
805 [/* For disassembly only; pattern left blank */]>,
806 Requires<[IsARM, HasV7]> {
807 let Inst{27-16} = 0b001100100000;
808 let Inst{7-4} = 0b1111;
811 // A5.4 Permanently UNDEFINED instructions.
812 // FIXME: Temporary emitted as raw bytes until this pseudo-op will be added to
814 let isBarrier = 1, isTerminator = 1 in
815 def TRAP : AXI<(outs), (ins), MiscFrm, NoItinerary,
816 ".long 0xe7ffdefe ${:comment} trap", [(trap)]>,
818 let Inst{27-25} = 0b011;
819 let Inst{24-20} = 0b11111;
820 let Inst{7-5} = 0b111;
824 // Address computation and loads and stores in PIC mode.
825 let isNotDuplicable = 1 in {
826 def PICADD : AXI1<0b0100, (outs GPR:$dst), (ins GPR:$a, pclabel:$cp, pred:$p),
827 Pseudo, IIC_iALUr, "\n$cp:\n\tadd$p\t$dst, pc, $a",
828 [(set GPR:$dst, (ARMpic_add GPR:$a, imm:$cp))]>;
830 let AddedComplexity = 10 in {
831 def PICLDR : AXI2ldw<(outs GPR:$dst), (ins addrmodepc:$addr, pred:$p),
832 Pseudo, IIC_iLoadr, "\n${addr:label}:\n\tldr$p\t$dst, $addr",
833 [(set GPR:$dst, (load addrmodepc:$addr))]>;
835 def PICLDRH : AXI3ldh<(outs GPR:$dst), (ins addrmodepc:$addr, pred:$p),
836 Pseudo, IIC_iLoadr, "\n${addr:label}:\n\tldrh${p}\t$dst, $addr",
837 [(set GPR:$dst, (zextloadi16 addrmodepc:$addr))]>;
839 def PICLDRB : AXI2ldb<(outs GPR:$dst), (ins addrmodepc:$addr, pred:$p),
840 Pseudo, IIC_iLoadr, "\n${addr:label}:\n\tldrb${p}\t$dst, $addr",
841 [(set GPR:$dst, (zextloadi8 addrmodepc:$addr))]>;
843 def PICLDRSH : AXI3ldsh<(outs GPR:$dst), (ins addrmodepc:$addr, pred:$p),
844 Pseudo, IIC_iLoadr, "\n${addr:label}:\n\tldrsh${p}\t$dst, $addr",
845 [(set GPR:$dst, (sextloadi16 addrmodepc:$addr))]>;
847 def PICLDRSB : AXI3ldsb<(outs GPR:$dst), (ins addrmodepc:$addr, pred:$p),
848 Pseudo, IIC_iLoadr, "\n${addr:label}:\n\tldrsb${p}\t$dst, $addr",
849 [(set GPR:$dst, (sextloadi8 addrmodepc:$addr))]>;
851 let AddedComplexity = 10 in {
852 def PICSTR : AXI2stw<(outs), (ins GPR:$src, addrmodepc:$addr, pred:$p),
853 Pseudo, IIC_iStorer, "\n${addr:label}:\n\tstr$p\t$src, $addr",
854 [(store GPR:$src, addrmodepc:$addr)]>;
856 def PICSTRH : AXI3sth<(outs), (ins GPR:$src, addrmodepc:$addr, pred:$p),
857 Pseudo, IIC_iStorer, "\n${addr:label}:\n\tstrh${p}\t$src, $addr",
858 [(truncstorei16 GPR:$src, addrmodepc:$addr)]>;
860 def PICSTRB : AXI2stb<(outs), (ins GPR:$src, addrmodepc:$addr, pred:$p),
861 Pseudo, IIC_iStorer, "\n${addr:label}:\n\tstrb${p}\t$src, $addr",
862 [(truncstorei8 GPR:$src, addrmodepc:$addr)]>;
864 } // isNotDuplicable = 1
867 // LEApcrel - Load a pc-relative address into a register without offending the
869 let neverHasSideEffects = 1 in {
870 let isReMaterializable = 1 in
871 def LEApcrel : AXI1<0x0, (outs GPR:$dst), (ins i32imm:$label, pred:$p),
873 "adr$p\t$dst, #$label", []>;
875 } // neverHasSideEffects
876 def LEApcrelJT : AXI1<0x0, (outs GPR:$dst),
877 (ins i32imm:$label, nohash_imm:$id, pred:$p),
879 "adr$p\t$dst, #${label}_${id}", []> {
883 //===----------------------------------------------------------------------===//
884 // Control Flow Instructions.
887 let isReturn = 1, isTerminator = 1, isBarrier = 1 in {
889 def BX_RET : AI<(outs), (ins), BrMiscFrm, IIC_Br,
890 "bx", "\tlr", [(ARMretflag)]>,
891 Requires<[IsARM, HasV4T]> {
892 let Inst{3-0} = 0b1110;
893 let Inst{7-4} = 0b0001;
894 let Inst{19-8} = 0b111111111111;
895 let Inst{27-20} = 0b00010010;
899 def MOVPCLR : AI<(outs), (ins), BrMiscFrm, IIC_Br,
900 "mov", "\tpc, lr", [(ARMretflag)]>,
901 Requires<[IsARM, NoV4T]> {
902 let Inst{11-0} = 0b000000001110;
903 let Inst{15-12} = 0b1111;
904 let Inst{19-16} = 0b0000;
905 let Inst{27-20} = 0b00011010;
910 let isBranch = 1, isTerminator = 1, isBarrier = 1, isIndirectBranch = 1 in {
912 def BRIND : AXI<(outs), (ins GPR:$dst), BrMiscFrm, IIC_Br, "bx\t$dst",
914 Requires<[IsARM, HasV4T]> {
915 let Inst{7-4} = 0b0001;
916 let Inst{19-8} = 0b111111111111;
917 let Inst{27-20} = 0b00010010;
918 let Inst{31-28} = 0b1110;
922 def MOVPCRX : AXI<(outs), (ins GPR:$dst), BrMiscFrm, IIC_Br, "mov\tpc, $dst",
924 Requires<[IsARM, NoV4T]> {
925 let Inst{11-4} = 0b00000000;
926 let Inst{15-12} = 0b1111;
927 let Inst{19-16} = 0b0000;
928 let Inst{27-20} = 0b00011010;
929 let Inst{31-28} = 0b1110;
933 // FIXME: remove when we have a way to marking a MI with these properties.
934 // FIXME: Should pc be an implicit operand like PICADD, etc?
935 let isReturn = 1, isTerminator = 1, isBarrier = 1, mayLoad = 1,
936 hasExtraDefRegAllocReq = 1 in
937 def LDM_RET : AXI4ld<(outs GPR:$wb), (ins addrmode4:$addr, pred:$p,
938 reglist:$dsts, variable_ops),
939 IndexModeUpd, LdStMulFrm, IIC_Br,
940 "ldm${addr:submode}${p}\t$addr!, $dsts",
941 "$addr.addr = $wb", []>;
943 // On non-Darwin platforms R9 is callee-saved.
945 Defs = [R0, R1, R2, R3, R12, LR,
946 D0, D1, D2, D3, D4, D5, D6, D7,
947 D16, D17, D18, D19, D20, D21, D22, D23,
948 D24, D25, D26, D27, D28, D29, D30, D31, CPSR, FPSCR] in {
949 def BL : ABXI<0b1011, (outs), (ins i32imm:$func, variable_ops),
950 IIC_Br, "bl\t${func:call}",
951 [(ARMcall tglobaladdr:$func)]>,
952 Requires<[IsARM, IsNotDarwin]> {
953 let Inst{31-28} = 0b1110;
956 def BL_pred : ABI<0b1011, (outs), (ins i32imm:$func, variable_ops),
957 IIC_Br, "bl", "\t${func:call}",
958 [(ARMcall_pred tglobaladdr:$func)]>,
959 Requires<[IsARM, IsNotDarwin]>;
962 def BLX : AXI<(outs), (ins GPR:$func, variable_ops), BrMiscFrm,
963 IIC_Br, "blx\t$func",
964 [(ARMcall GPR:$func)]>,
965 Requires<[IsARM, HasV5T, IsNotDarwin]> {
966 let Inst{7-4} = 0b0011;
967 let Inst{19-8} = 0b111111111111;
968 let Inst{27-20} = 0b00010010;
972 // Note: Restrict $func to the tGPR regclass to prevent it being in LR.
973 def BX : ABXIx2<(outs), (ins tGPR:$func, variable_ops),
974 IIC_Br, "mov\tlr, pc\n\tbx\t$func",
975 [(ARMcall_nolink tGPR:$func)]>,
976 Requires<[IsARM, HasV4T, IsNotDarwin]> {
977 let Inst{7-4} = 0b0001;
978 let Inst{19-8} = 0b111111111111;
979 let Inst{27-20} = 0b00010010;
983 def BMOVPCRX : ABXIx2<(outs), (ins tGPR:$func, variable_ops),
984 IIC_Br, "mov\tlr, pc\n\tmov\tpc, $func",
985 [(ARMcall_nolink tGPR:$func)]>,
986 Requires<[IsARM, NoV4T, IsNotDarwin]> {
987 let Inst{11-4} = 0b00000000;
988 let Inst{15-12} = 0b1111;
989 let Inst{19-16} = 0b0000;
990 let Inst{27-20} = 0b00011010;
994 // On Darwin R9 is call-clobbered.
996 Defs = [R0, R1, R2, R3, R9, R12, LR,
997 D0, D1, D2, D3, D4, D5, D6, D7,
998 D16, D17, D18, D19, D20, D21, D22, D23,
999 D24, D25, D26, D27, D28, D29, D30, D31, CPSR, FPSCR] in {
1000 def BLr9 : ABXI<0b1011, (outs), (ins i32imm:$func, variable_ops),
1001 IIC_Br, "bl\t${func:call}",
1002 [(ARMcall tglobaladdr:$func)]>, Requires<[IsARM, IsDarwin]> {
1003 let Inst{31-28} = 0b1110;
1006 def BLr9_pred : ABI<0b1011, (outs), (ins i32imm:$func, variable_ops),
1007 IIC_Br, "bl", "\t${func:call}",
1008 [(ARMcall_pred tglobaladdr:$func)]>,
1009 Requires<[IsARM, IsDarwin]>;
1012 def BLXr9 : AXI<(outs), (ins GPR:$func, variable_ops), BrMiscFrm,
1013 IIC_Br, "blx\t$func",
1014 [(ARMcall GPR:$func)]>, Requires<[IsARM, HasV5T, IsDarwin]> {
1015 let Inst{7-4} = 0b0011;
1016 let Inst{19-8} = 0b111111111111;
1017 let Inst{27-20} = 0b00010010;
1021 // Note: Restrict $func to the tGPR regclass to prevent it being in LR.
1022 def BXr9 : ABXIx2<(outs), (ins tGPR:$func, variable_ops),
1023 IIC_Br, "mov\tlr, pc\n\tbx\t$func",
1024 [(ARMcall_nolink tGPR:$func)]>,
1025 Requires<[IsARM, HasV4T, IsDarwin]> {
1026 let Inst{7-4} = 0b0001;
1027 let Inst{19-8} = 0b111111111111;
1028 let Inst{27-20} = 0b00010010;
1032 def BMOVPCRXr9 : ABXIx2<(outs), (ins tGPR:$func, variable_ops),
1033 IIC_Br, "mov\tlr, pc\n\tmov\tpc, $func",
1034 [(ARMcall_nolink tGPR:$func)]>,
1035 Requires<[IsARM, NoV4T, IsDarwin]> {
1036 let Inst{11-4} = 0b00000000;
1037 let Inst{15-12} = 0b1111;
1038 let Inst{19-16} = 0b0000;
1039 let Inst{27-20} = 0b00011010;
1045 let isCall = 1, isTerminator = 1, isReturn = 1, isBarrier = 1 in {
1047 let Defs = [R0, R1, R2, R3, R9, R12,
1048 D0, D1, D2, D3, D4, D5, D6, D7,
1049 D16, D17, D18, D19, D20, D21, D22, D23, D24, D25, D26,
1050 D27, D28, D29, D30, D31, PC],
1052 def TCRETURNdi : AInoP<(outs), (ins i32imm:$dst, variable_ops),
1054 "@TC_RETURN","\t$dst", []>, Requires<[IsDarwin]>;
1056 def TCRETURNri : AInoP<(outs), (ins tcGPR:$dst, variable_ops),
1058 "@TC_RETURN","\t$dst", []>, Requires<[IsDarwin]>;
1060 def TAILJMPd : ABXI<0b1010, (outs), (ins brtarget:$dst, variable_ops),
1061 IIC_Br, "b\t$dst @ TAILCALL",
1062 []>, Requires<[IsDarwin]>;
1064 def TAILJMPdt: ABXI<0b1010, (outs), (ins brtarget:$dst, variable_ops),
1065 IIC_Br, "b.w\t$dst @ TAILCALL",
1066 []>, Requires<[IsDarwin]>;
1068 def TAILJMPr : AXI<(outs), (ins tcGPR:$dst, variable_ops),
1069 BrMiscFrm, IIC_Br, "bx\t$dst @ TAILCALL",
1070 []>, Requires<[IsDarwin]> {
1071 let Inst{7-4} = 0b0001;
1072 let Inst{19-8} = 0b111111111111;
1073 let Inst{27-20} = 0b00010010;
1074 let Inst{31-28} = 0b1110;
1078 // Non-Darwin versions (the difference is R9).
1079 let Defs = [R0, R1, R2, R3, R12,
1080 D0, D1, D2, D3, D4, D5, D6, D7,
1081 D16, D17, D18, D19, D20, D21, D22, D23, D24, D25, D26,
1082 D27, D28, D29, D30, D31, PC],
1084 def TCRETURNdiND : AInoP<(outs), (ins i32imm:$dst, variable_ops),
1086 "@TC_RETURN","\t$dst", []>, Requires<[IsNotDarwin]>;
1088 def TCRETURNriND : AInoP<(outs), (ins tcGPR:$dst, variable_ops),
1090 "@TC_RETURN","\t$dst", []>, Requires<[IsNotDarwin]>;
1092 def TAILJMPdND : ABXI<0b1010, (outs), (ins brtarget:$dst, variable_ops),
1093 IIC_Br, "b\t$dst @ TAILCALL",
1094 []>, Requires<[IsARM, IsNotDarwin]>;
1096 def TAILJMPdNDt : ABXI<0b1010, (outs), (ins brtarget:$dst, variable_ops),
1097 IIC_Br, "b.w\t$dst @ TAILCALL",
1098 []>, Requires<[IsThumb, IsNotDarwin]>;
1100 def TAILJMPrND : AXI<(outs), (ins tcGPR:$dst, variable_ops),
1101 BrMiscFrm, IIC_Br, "bx\t$dst @ TAILCALL",
1102 []>, Requires<[IsNotDarwin]> {
1103 let Inst{7-4} = 0b0001;
1104 let Inst{19-8} = 0b111111111111;
1105 let Inst{27-20} = 0b00010010;
1106 let Inst{31-28} = 0b1110;
1111 let isBranch = 1, isTerminator = 1 in {
1112 // B is "predicable" since it can be xformed into a Bcc.
1113 let isBarrier = 1 in {
1114 let isPredicable = 1 in
1115 def B : ABXI<0b1010, (outs), (ins brtarget:$target), IIC_Br,
1116 "b\t$target", [(br bb:$target)]>;
1118 let isNotDuplicable = 1, isIndirectBranch = 1 in {
1119 def BR_JTr : JTI<(outs), (ins GPR:$target, jtblock_operand:$jt, i32imm:$id),
1120 IIC_Br, "mov\tpc, $target \n$jt",
1121 [(ARMbrjt GPR:$target, tjumptable:$jt, imm:$id)]> {
1122 let Inst{11-4} = 0b00000000;
1123 let Inst{15-12} = 0b1111;
1124 let Inst{20} = 0; // S Bit
1125 let Inst{24-21} = 0b1101;
1126 let Inst{27-25} = 0b000;
1128 def BR_JTm : JTI<(outs),
1129 (ins addrmode2:$target, jtblock_operand:$jt, i32imm:$id),
1130 IIC_Br, "ldr\tpc, $target \n$jt",
1131 [(ARMbrjt (i32 (load addrmode2:$target)), tjumptable:$jt,
1133 let Inst{15-12} = 0b1111;
1134 let Inst{20} = 1; // L bit
1135 let Inst{21} = 0; // W bit
1136 let Inst{22} = 0; // B bit
1137 let Inst{24} = 1; // P bit
1138 let Inst{27-25} = 0b011;
1140 def BR_JTadd : JTI<(outs),
1141 (ins GPR:$target, GPR:$idx, jtblock_operand:$jt, i32imm:$id),
1142 IIC_Br, "add\tpc, $target, $idx \n$jt",
1143 [(ARMbrjt (add GPR:$target, GPR:$idx), tjumptable:$jt,
1145 let Inst{15-12} = 0b1111;
1146 let Inst{20} = 0; // S bit
1147 let Inst{24-21} = 0b0100;
1148 let Inst{27-25} = 0b000;
1150 } // isNotDuplicable = 1, isIndirectBranch = 1
1153 // FIXME: should be able to write a pattern for ARMBrcond, but can't use
1154 // a two-value operand where a dag node expects two operands. :(
1155 def Bcc : ABI<0b1010, (outs), (ins brtarget:$target),
1156 IIC_Br, "b", "\t$target",
1157 [/*(ARMbrcond bb:$target, imm:$cc, CCR:$ccr)*/]>;
1160 // Branch and Exchange Jazelle -- for disassembly only
1161 def BXJ : ABI<0b0001, (outs), (ins GPR:$func), NoItinerary, "bxj", "\t$func",
1162 [/* For disassembly only; pattern left blank */]> {
1163 let Inst{23-20} = 0b0010;
1164 //let Inst{19-8} = 0xfff;
1165 let Inst{7-4} = 0b0010;
1168 // Secure Monitor Call is a system instruction -- for disassembly only
1169 def SMC : ABI<0b0001, (outs), (ins i32imm:$opt), NoItinerary, "smc", "\t$opt",
1170 [/* For disassembly only; pattern left blank */]> {
1171 let Inst{23-20} = 0b0110;
1172 let Inst{7-4} = 0b0111;
1175 // Supervisor Call (Software Interrupt) -- for disassembly only
1177 def SVC : ABI<0b1111, (outs), (ins i32imm:$svc), IIC_Br, "svc", "\t$svc",
1178 [/* For disassembly only; pattern left blank */]>;
1181 // Store Return State is a system instruction -- for disassembly only
1182 def SRSW : ABXI<{1,0,0,?}, (outs), (ins addrmode4:$addr, i32imm:$mode),
1183 NoItinerary, "srs${addr:submode}\tsp!, $mode",
1184 [/* For disassembly only; pattern left blank */]> {
1185 let Inst{31-28} = 0b1111;
1186 let Inst{22-20} = 0b110; // W = 1
1189 def SRS : ABXI<{1,0,0,?}, (outs), (ins addrmode4:$addr, i32imm:$mode),
1190 NoItinerary, "srs${addr:submode}\tsp, $mode",
1191 [/* For disassembly only; pattern left blank */]> {
1192 let Inst{31-28} = 0b1111;
1193 let Inst{22-20} = 0b100; // W = 0
1196 // Return From Exception is a system instruction -- for disassembly only
1197 def RFEW : ABXI<{1,0,0,?}, (outs), (ins addrmode4:$addr, GPR:$base),
1198 NoItinerary, "rfe${addr:submode}\t$base!",
1199 [/* For disassembly only; pattern left blank */]> {
1200 let Inst{31-28} = 0b1111;
1201 let Inst{22-20} = 0b011; // W = 1
1204 def RFE : ABXI<{1,0,0,?}, (outs), (ins addrmode4:$addr, GPR:$base),
1205 NoItinerary, "rfe${addr:submode}\t$base",
1206 [/* For disassembly only; pattern left blank */]> {
1207 let Inst{31-28} = 0b1111;
1208 let Inst{22-20} = 0b001; // W = 0
1211 //===----------------------------------------------------------------------===//
1212 // Load / store Instructions.
1216 let canFoldAsLoad = 1, isReMaterializable = 1 in
1217 def LDR : AI2ldw<(outs GPR:$dst), (ins addrmode2:$addr), LdFrm, IIC_iLoadr,
1218 "ldr", "\t$dst, $addr",
1219 [(set GPR:$dst, (load addrmode2:$addr))]>;
1221 // Special LDR for loads from non-pc-relative constpools.
1222 let canFoldAsLoad = 1, mayLoad = 1, neverHasSideEffects = 1,
1223 isReMaterializable = 1 in
1224 def LDRcp : AI2ldw<(outs GPR:$dst), (ins addrmode2:$addr), LdFrm, IIC_iLoadr,
1225 "ldr", "\t$dst, $addr", []>;
1227 // Loads with zero extension
1228 def LDRH : AI3ldh<(outs GPR:$dst), (ins addrmode3:$addr), LdMiscFrm,
1229 IIC_iLoadr, "ldrh", "\t$dst, $addr",
1230 [(set GPR:$dst, (zextloadi16 addrmode3:$addr))]>;
1232 def LDRB : AI2ldb<(outs GPR:$dst), (ins addrmode2:$addr), LdFrm,
1233 IIC_iLoadr, "ldrb", "\t$dst, $addr",
1234 [(set GPR:$dst, (zextloadi8 addrmode2:$addr))]>;
1236 // Loads with sign extension
1237 def LDRSH : AI3ldsh<(outs GPR:$dst), (ins addrmode3:$addr), LdMiscFrm,
1238 IIC_iLoadr, "ldrsh", "\t$dst, $addr",
1239 [(set GPR:$dst, (sextloadi16 addrmode3:$addr))]>;
1241 def LDRSB : AI3ldsb<(outs GPR:$dst), (ins addrmode3:$addr), LdMiscFrm,
1242 IIC_iLoadr, "ldrsb", "\t$dst, $addr",
1243 [(set GPR:$dst, (sextloadi8 addrmode3:$addr))]>;
1245 let mayLoad = 1, neverHasSideEffects = 1, hasExtraDefRegAllocReq = 1 in {
1247 def LDRD : AI3ldd<(outs GPR:$dst1, GPR:$dst2), (ins addrmode3:$addr), LdMiscFrm,
1248 IIC_iLoadr, "ldrd", "\t$dst1, $addr",
1249 []>, Requires<[IsARM, HasV5TE]>;
1252 def LDR_PRE : AI2ldwpr<(outs GPR:$dst, GPR:$base_wb),
1253 (ins addrmode2:$addr), LdFrm, IIC_iLoadru,
1254 "ldr", "\t$dst, $addr!", "$addr.base = $base_wb", []>;
1256 def LDR_POST : AI2ldwpo<(outs GPR:$dst, GPR:$base_wb),
1257 (ins GPR:$base, am2offset:$offset), LdFrm, IIC_iLoadru,
1258 "ldr", "\t$dst, [$base], $offset", "$base = $base_wb", []>;
1260 def LDRH_PRE : AI3ldhpr<(outs GPR:$dst, GPR:$base_wb),
1261 (ins addrmode3:$addr), LdMiscFrm, IIC_iLoadru,
1262 "ldrh", "\t$dst, $addr!", "$addr.base = $base_wb", []>;
1264 def LDRH_POST : AI3ldhpo<(outs GPR:$dst, GPR:$base_wb),
1265 (ins GPR:$base,am3offset:$offset), LdMiscFrm, IIC_iLoadru,
1266 "ldrh", "\t$dst, [$base], $offset", "$base = $base_wb", []>;
1268 def LDRB_PRE : AI2ldbpr<(outs GPR:$dst, GPR:$base_wb),
1269 (ins addrmode2:$addr), LdFrm, IIC_iLoadru,
1270 "ldrb", "\t$dst, $addr!", "$addr.base = $base_wb", []>;
1272 def LDRB_POST : AI2ldbpo<(outs GPR:$dst, GPR:$base_wb),
1273 (ins GPR:$base,am2offset:$offset), LdFrm, IIC_iLoadru,
1274 "ldrb", "\t$dst, [$base], $offset", "$base = $base_wb", []>;
1276 def LDRSH_PRE : AI3ldshpr<(outs GPR:$dst, GPR:$base_wb),
1277 (ins addrmode3:$addr), LdMiscFrm, IIC_iLoadru,
1278 "ldrsh", "\t$dst, $addr!", "$addr.base = $base_wb", []>;
1280 def LDRSH_POST: AI3ldshpo<(outs GPR:$dst, GPR:$base_wb),
1281 (ins GPR:$base,am3offset:$offset), LdMiscFrm, IIC_iLoadru,
1282 "ldrsh", "\t$dst, [$base], $offset", "$base = $base_wb", []>;
1284 def LDRSB_PRE : AI3ldsbpr<(outs GPR:$dst, GPR:$base_wb),
1285 (ins addrmode3:$addr), LdMiscFrm, IIC_iLoadru,
1286 "ldrsb", "\t$dst, $addr!", "$addr.base = $base_wb", []>;
1288 def LDRSB_POST: AI3ldsbpo<(outs GPR:$dst, GPR:$base_wb),
1289 (ins GPR:$base,am3offset:$offset), LdMiscFrm, IIC_iLoadru,
1290 "ldrsb", "\t$dst, [$base], $offset", "$base = $base_wb", []>;
1292 // For disassembly only
1293 def LDRD_PRE : AI3lddpr<(outs GPR:$dst1, GPR:$dst2, GPR:$base_wb),
1294 (ins addrmode3:$addr), LdMiscFrm, IIC_iLoadr,
1295 "ldrd", "\t$dst1, $dst2, $addr!", "$addr.base = $base_wb", []>,
1296 Requires<[IsARM, HasV5TE]>;
1298 // For disassembly only
1299 def LDRD_POST : AI3lddpo<(outs GPR:$dst1, GPR:$dst2, GPR:$base_wb),
1300 (ins GPR:$base,am3offset:$offset), LdMiscFrm, IIC_iLoadr,
1301 "ldrd", "\t$dst1, $dst2, [$base], $offset", "$base = $base_wb", []>,
1302 Requires<[IsARM, HasV5TE]>;
1304 } // mayLoad = 1, neverHasSideEffects = 1, hasExtraDefRegAllocReq = 1
1306 // LDRT, LDRBT, LDRSBT, LDRHT, LDRSHT are for disassembly only.
1308 def LDRT : AI2ldwpo<(outs GPR:$dst, GPR:$base_wb),
1309 (ins GPR:$base, am2offset:$offset), LdFrm, IIC_iLoadru,
1310 "ldrt", "\t$dst, [$base], $offset", "$base = $base_wb", []> {
1311 let Inst{21} = 1; // overwrite
1314 def LDRBT : AI2ldbpo<(outs GPR:$dst, GPR:$base_wb),
1315 (ins GPR:$base,am2offset:$offset), LdFrm, IIC_iLoadru,
1316 "ldrbt", "\t$dst, [$base], $offset", "$base = $base_wb", []> {
1317 let Inst{21} = 1; // overwrite
1320 def LDRSBT : AI3ldsbpo<(outs GPR:$dst, GPR:$base_wb),
1321 (ins GPR:$base,am3offset:$offset), LdMiscFrm, IIC_iLoadru,
1322 "ldrsbt", "\t$dst, [$base], $offset", "$base = $base_wb", []> {
1323 let Inst{21} = 1; // overwrite
1326 def LDRHT : AI3ldhpo<(outs GPR:$dst, GPR:$base_wb),
1327 (ins GPR:$base, am3offset:$offset), LdMiscFrm, IIC_iLoadru,
1328 "ldrht", "\t$dst, [$base], $offset", "$base = $base_wb", []> {
1329 let Inst{21} = 1; // overwrite
1332 def LDRSHT : AI3ldshpo<(outs GPR:$dst, GPR:$base_wb),
1333 (ins GPR:$base,am3offset:$offset), LdMiscFrm, IIC_iLoadru,
1334 "ldrsht", "\t$dst, [$base], $offset", "$base = $base_wb", []> {
1335 let Inst{21} = 1; // overwrite
1339 def STR : AI2stw<(outs), (ins GPR:$src, addrmode2:$addr), StFrm, IIC_iStorer,
1340 "str", "\t$src, $addr",
1341 [(store GPR:$src, addrmode2:$addr)]>;
1343 // Stores with truncate
1344 def STRH : AI3sth<(outs), (ins GPR:$src, addrmode3:$addr), StMiscFrm,
1345 IIC_iStorer, "strh", "\t$src, $addr",
1346 [(truncstorei16 GPR:$src, addrmode3:$addr)]>;
1348 def STRB : AI2stb<(outs), (ins GPR:$src, addrmode2:$addr), StFrm, IIC_iStorer,
1349 "strb", "\t$src, $addr",
1350 [(truncstorei8 GPR:$src, addrmode2:$addr)]>;
1353 let mayStore = 1, neverHasSideEffects = 1, hasExtraSrcRegAllocReq = 1 in
1354 def STRD : AI3std<(outs), (ins GPR:$src1, GPR:$src2, addrmode3:$addr),
1355 StMiscFrm, IIC_iStorer,
1356 "strd", "\t$src1, $addr", []>, Requires<[IsARM, HasV5TE]>;
1359 def STR_PRE : AI2stwpr<(outs GPR:$base_wb),
1360 (ins GPR:$src, GPR:$base, am2offset:$offset),
1361 StFrm, IIC_iStoreru,
1362 "str", "\t$src, [$base, $offset]!", "$base = $base_wb",
1364 (pre_store GPR:$src, GPR:$base, am2offset:$offset))]>;
1366 def STR_POST : AI2stwpo<(outs GPR:$base_wb),
1367 (ins GPR:$src, GPR:$base,am2offset:$offset),
1368 StFrm, IIC_iStoreru,
1369 "str", "\t$src, [$base], $offset", "$base = $base_wb",
1371 (post_store GPR:$src, GPR:$base, am2offset:$offset))]>;
1373 def STRH_PRE : AI3sthpr<(outs GPR:$base_wb),
1374 (ins GPR:$src, GPR:$base,am3offset:$offset),
1375 StMiscFrm, IIC_iStoreru,
1376 "strh", "\t$src, [$base, $offset]!", "$base = $base_wb",
1378 (pre_truncsti16 GPR:$src, GPR:$base,am3offset:$offset))]>;
1380 def STRH_POST: AI3sthpo<(outs GPR:$base_wb),
1381 (ins GPR:$src, GPR:$base,am3offset:$offset),
1382 StMiscFrm, IIC_iStoreru,
1383 "strh", "\t$src, [$base], $offset", "$base = $base_wb",
1384 [(set GPR:$base_wb, (post_truncsti16 GPR:$src,
1385 GPR:$base, am3offset:$offset))]>;
1387 def STRB_PRE : AI2stbpr<(outs GPR:$base_wb),
1388 (ins GPR:$src, GPR:$base,am2offset:$offset),
1389 StFrm, IIC_iStoreru,
1390 "strb", "\t$src, [$base, $offset]!", "$base = $base_wb",
1391 [(set GPR:$base_wb, (pre_truncsti8 GPR:$src,
1392 GPR:$base, am2offset:$offset))]>;
1394 def STRB_POST: AI2stbpo<(outs GPR:$base_wb),
1395 (ins GPR:$src, GPR:$base,am2offset:$offset),
1396 StFrm, IIC_iStoreru,
1397 "strb", "\t$src, [$base], $offset", "$base = $base_wb",
1398 [(set GPR:$base_wb, (post_truncsti8 GPR:$src,
1399 GPR:$base, am2offset:$offset))]>;
1401 // For disassembly only
1402 def STRD_PRE : AI3stdpr<(outs GPR:$base_wb),
1403 (ins GPR:$src1, GPR:$src2, GPR:$base, am3offset:$offset),
1404 StMiscFrm, IIC_iStoreru,
1405 "strd", "\t$src1, $src2, [$base, $offset]!",
1406 "$base = $base_wb", []>;
1408 // For disassembly only
1409 def STRD_POST: AI3stdpo<(outs GPR:$base_wb),
1410 (ins GPR:$src1, GPR:$src2, GPR:$base, am3offset:$offset),
1411 StMiscFrm, IIC_iStoreru,
1412 "strd", "\t$src1, $src2, [$base], $offset",
1413 "$base = $base_wb", []>;
1415 // STRT, STRBT, and STRHT are for disassembly only.
1417 def STRT : AI2stwpo<(outs GPR:$base_wb),
1418 (ins GPR:$src, GPR:$base,am2offset:$offset),
1419 StFrm, IIC_iStoreru,
1420 "strt", "\t$src, [$base], $offset", "$base = $base_wb",
1421 [/* For disassembly only; pattern left blank */]> {
1422 let Inst{21} = 1; // overwrite
1425 def STRBT : AI2stbpo<(outs GPR:$base_wb),
1426 (ins GPR:$src, GPR:$base,am2offset:$offset),
1427 StFrm, IIC_iStoreru,
1428 "strbt", "\t$src, [$base], $offset", "$base = $base_wb",
1429 [/* For disassembly only; pattern left blank */]> {
1430 let Inst{21} = 1; // overwrite
1433 def STRHT: AI3sthpo<(outs GPR:$base_wb),
1434 (ins GPR:$src, GPR:$base,am3offset:$offset),
1435 StMiscFrm, IIC_iStoreru,
1436 "strht", "\t$src, [$base], $offset", "$base = $base_wb",
1437 [/* For disassembly only; pattern left blank */]> {
1438 let Inst{21} = 1; // overwrite
1441 //===----------------------------------------------------------------------===//
1442 // Load / store multiple Instructions.
1445 let mayLoad = 1, neverHasSideEffects = 1, hasExtraDefRegAllocReq = 1 in {
1446 def LDM : AXI4ld<(outs), (ins addrmode4:$addr, pred:$p,
1447 reglist:$dsts, variable_ops),
1448 IndexModeNone, LdStMulFrm, IIC_iLoadm,
1449 "ldm${addr:submode}${p}\t$addr, $dsts", "", []>;
1451 def LDM_UPD : AXI4ld<(outs GPR:$wb), (ins addrmode4:$addr, pred:$p,
1452 reglist:$dsts, variable_ops),
1453 IndexModeUpd, LdStMulFrm, IIC_iLoadm,
1454 "ldm${addr:submode}${p}\t$addr!, $dsts",
1455 "$addr.addr = $wb", []>;
1456 } // mayLoad, neverHasSideEffects, hasExtraDefRegAllocReq
1458 let mayStore = 1, neverHasSideEffects = 1, hasExtraSrcRegAllocReq = 1 in {
1459 def STM : AXI4st<(outs), (ins addrmode4:$addr, pred:$p,
1460 reglist:$srcs, variable_ops),
1461 IndexModeNone, LdStMulFrm, IIC_iStorem,
1462 "stm${addr:submode}${p}\t$addr, $srcs", "", []>;
1464 def STM_UPD : AXI4st<(outs GPR:$wb), (ins addrmode4:$addr, pred:$p,
1465 reglist:$srcs, variable_ops),
1466 IndexModeUpd, LdStMulFrm, IIC_iStorem,
1467 "stm${addr:submode}${p}\t$addr!, $srcs",
1468 "$addr.addr = $wb", []>;
1469 } // mayStore, neverHasSideEffects, hasExtraSrcRegAllocReq
1471 //===----------------------------------------------------------------------===//
1472 // Move Instructions.
1475 let neverHasSideEffects = 1 in
1476 def MOVr : AsI1<0b1101, (outs GPR:$dst), (ins GPR:$src), DPFrm, IIC_iMOVr,
1477 "mov", "\t$dst, $src", []>, UnaryDP {
1478 let Inst{11-4} = 0b00000000;
1482 // A version for the smaller set of tail call registers.
1483 let neverHasSideEffects = 1 in
1484 def MOVr_TC : AsI1<0b1101, (outs tcGPR:$dst), (ins tcGPR:$src), DPFrm,
1485 IIC_iMOVr, "mov", "\t$dst, $src", []>, UnaryDP {
1486 let Inst{11-4} = 0b00000000;
1490 def MOVs : AsI1<0b1101, (outs GPR:$dst), (ins so_reg:$src),
1491 DPSoRegFrm, IIC_iMOVsr,
1492 "mov", "\t$dst, $src", [(set GPR:$dst, so_reg:$src)]>, UnaryDP {
1496 let isReMaterializable = 1, isAsCheapAsAMove = 1 in
1497 def MOVi : AsI1<0b1101, (outs GPR:$dst), (ins so_imm:$src), DPFrm, IIC_iMOVi,
1498 "mov", "\t$dst, $src", [(set GPR:$dst, so_imm:$src)]>, UnaryDP {
1502 let isReMaterializable = 1, isAsCheapAsAMove = 1 in
1503 def MOVi16 : AI1<0b1000, (outs GPR:$dst), (ins i32imm:$src),
1505 "movw", "\t$dst, $src",
1506 [(set GPR:$dst, imm0_65535:$src)]>,
1507 Requires<[IsARM, HasV6T2]>, UnaryDP {
1512 let Constraints = "$src = $dst" in
1513 def MOVTi16 : AI1<0b1010, (outs GPR:$dst), (ins GPR:$src, i32imm:$imm),
1515 "movt", "\t$dst, $imm",
1517 (or (and GPR:$src, 0xffff),
1518 lo16AllZero:$imm))]>, UnaryDP,
1519 Requires<[IsARM, HasV6T2]> {
1524 def : ARMPat<(or GPR:$src, 0xffff0000), (MOVTi16 GPR:$src, 0xffff)>,
1525 Requires<[IsARM, HasV6T2]>;
1527 let Uses = [CPSR] in
1528 def MOVrx : AsI1<0b1101, (outs GPR:$dst), (ins GPR:$src), Pseudo, IIC_iMOVsi,
1529 "mov", "\t$dst, $src, rrx",
1530 [(set GPR:$dst, (ARMrrx GPR:$src))]>, UnaryDP;
1532 // These aren't really mov instructions, but we have to define them this way
1533 // due to flag operands.
1535 let Defs = [CPSR] in {
1536 def MOVsrl_flag : AI1<0b1101, (outs GPR:$dst), (ins GPR:$src), Pseudo,
1537 IIC_iMOVsi, "movs", "\t$dst, $src, lsr #1",
1538 [(set GPR:$dst, (ARMsrl_flag GPR:$src))]>, UnaryDP;
1539 def MOVsra_flag : AI1<0b1101, (outs GPR:$dst), (ins GPR:$src), Pseudo,
1540 IIC_iMOVsi, "movs", "\t$dst, $src, asr #1",
1541 [(set GPR:$dst, (ARMsra_flag GPR:$src))]>, UnaryDP;
1544 //===----------------------------------------------------------------------===//
1545 // Extend Instructions.
1550 defm SXTB : AI_unary_rrot<0b01101010,
1551 "sxtb", UnOpFrag<(sext_inreg node:$Src, i8)>>;
1552 defm SXTH : AI_unary_rrot<0b01101011,
1553 "sxth", UnOpFrag<(sext_inreg node:$Src, i16)>>;
1555 defm SXTAB : AI_bin_rrot<0b01101010,
1556 "sxtab", BinOpFrag<(add node:$LHS, (sext_inreg node:$RHS, i8))>>;
1557 defm SXTAH : AI_bin_rrot<0b01101011,
1558 "sxtah", BinOpFrag<(add node:$LHS, (sext_inreg node:$RHS,i16))>>;
1560 // For disassembly only
1561 defm SXTB16 : AI_unary_rrot_np<0b01101000, "sxtb16">;
1563 // For disassembly only
1564 defm SXTAB16 : AI_bin_rrot_np<0b01101000, "sxtab16">;
1568 let AddedComplexity = 16 in {
1569 defm UXTB : AI_unary_rrot<0b01101110,
1570 "uxtb" , UnOpFrag<(and node:$Src, 0x000000FF)>>;
1571 defm UXTH : AI_unary_rrot<0b01101111,
1572 "uxth" , UnOpFrag<(and node:$Src, 0x0000FFFF)>>;
1573 defm UXTB16 : AI_unary_rrot<0b01101100,
1574 "uxtb16", UnOpFrag<(and node:$Src, 0x00FF00FF)>>;
1576 def : ARMV6Pat<(and (shl GPR:$Src, (i32 8)), 0xFF00FF),
1577 (UXTB16r_rot GPR:$Src, 24)>;
1578 def : ARMV6Pat<(and (srl GPR:$Src, (i32 8)), 0xFF00FF),
1579 (UXTB16r_rot GPR:$Src, 8)>;
1581 defm UXTAB : AI_bin_rrot<0b01101110, "uxtab",
1582 BinOpFrag<(add node:$LHS, (and node:$RHS, 0x00FF))>>;
1583 defm UXTAH : AI_bin_rrot<0b01101111, "uxtah",
1584 BinOpFrag<(add node:$LHS, (and node:$RHS, 0xFFFF))>>;
1587 // This isn't safe in general, the add is two 16-bit units, not a 32-bit add.
1588 // For disassembly only
1589 defm UXTAB16 : AI_bin_rrot_np<0b01101100, "uxtab16">;
1592 def SBFX : I<(outs GPR:$dst),
1593 (ins GPR:$src, imm0_31:$lsb, imm0_31:$width),
1594 AddrMode1, Size4Bytes, IndexModeNone, DPFrm, IIC_iALUi,
1595 "sbfx", "\t$dst, $src, $lsb, $width", "", []>,
1596 Requires<[IsARM, HasV6T2]> {
1597 let Inst{27-21} = 0b0111101;
1598 let Inst{6-4} = 0b101;
1601 def UBFX : I<(outs GPR:$dst),
1602 (ins GPR:$src, imm0_31:$lsb, imm0_31:$width),
1603 AddrMode1, Size4Bytes, IndexModeNone, DPFrm, IIC_iALUi,
1604 "ubfx", "\t$dst, $src, $lsb, $width", "", []>,
1605 Requires<[IsARM, HasV6T2]> {
1606 let Inst{27-21} = 0b0111111;
1607 let Inst{6-4} = 0b101;
1610 //===----------------------------------------------------------------------===//
1611 // Arithmetic Instructions.
1614 defm ADD : AsI1_bin_irs<0b0100, "add",
1615 BinOpFrag<(add node:$LHS, node:$RHS)>, 1>;
1616 defm SUB : AsI1_bin_irs<0b0010, "sub",
1617 BinOpFrag<(sub node:$LHS, node:$RHS)>>;
1619 // ADD and SUB with 's' bit set.
1620 defm ADDS : AI1_bin_s_irs<0b0100, "adds",
1621 BinOpFrag<(addc node:$LHS, node:$RHS)>, 1>;
1622 defm SUBS : AI1_bin_s_irs<0b0010, "subs",
1623 BinOpFrag<(subc node:$LHS, node:$RHS)>>;
1625 defm ADC : AI1_adde_sube_irs<0b0101, "adc",
1626 BinOpFrag<(adde_dead_carry node:$LHS, node:$RHS)>, 1>;
1627 defm SBC : AI1_adde_sube_irs<0b0110, "sbc",
1628 BinOpFrag<(sube_dead_carry node:$LHS, node:$RHS)>>;
1629 defm ADCS : AI1_adde_sube_s_irs<0b0101, "adcs",
1630 BinOpFrag<(adde_live_carry node:$LHS, node:$RHS)>, 1>;
1631 defm SBCS : AI1_adde_sube_s_irs<0b0110, "sbcs",
1632 BinOpFrag<(sube_live_carry node:$LHS, node:$RHS) >>;
1634 // These don't define reg/reg forms, because they are handled above.
1635 def RSBri : AsI1<0b0011, (outs GPR:$dst), (ins GPR:$a, so_imm:$b), DPFrm,
1636 IIC_iALUi, "rsb", "\t$dst, $a, $b",
1637 [(set GPR:$dst, (sub so_imm:$b, GPR:$a))]> {
1641 def RSBrs : AsI1<0b0011, (outs GPR:$dst), (ins GPR:$a, so_reg:$b), DPSoRegFrm,
1642 IIC_iALUsr, "rsb", "\t$dst, $a, $b",
1643 [(set GPR:$dst, (sub so_reg:$b, GPR:$a))]> {
1647 // RSB with 's' bit set.
1648 let Defs = [CPSR] in {
1649 def RSBSri : AI1<0b0011, (outs GPR:$dst), (ins GPR:$a, so_imm:$b), DPFrm,
1650 IIC_iALUi, "rsbs", "\t$dst, $a, $b",
1651 [(set GPR:$dst, (subc so_imm:$b, GPR:$a))]> {
1655 def RSBSrs : AI1<0b0011, (outs GPR:$dst), (ins GPR:$a, so_reg:$b), DPSoRegFrm,
1656 IIC_iALUsr, "rsbs", "\t$dst, $a, $b",
1657 [(set GPR:$dst, (subc so_reg:$b, GPR:$a))]> {
1663 let Uses = [CPSR] in {
1664 def RSCri : AsI1<0b0111, (outs GPR:$dst), (ins GPR:$a, so_imm:$b),
1665 DPFrm, IIC_iALUi, "rsc", "\t$dst, $a, $b",
1666 [(set GPR:$dst, (sube_dead_carry so_imm:$b, GPR:$a))]>,
1670 def RSCrs : AsI1<0b0111, (outs GPR:$dst), (ins GPR:$a, so_reg:$b),
1671 DPSoRegFrm, IIC_iALUsr, "rsc", "\t$dst, $a, $b",
1672 [(set GPR:$dst, (sube_dead_carry so_reg:$b, GPR:$a))]>,
1678 // FIXME: Allow these to be predicated.
1679 let Defs = [CPSR], Uses = [CPSR] in {
1680 def RSCSri : AXI1<0b0111, (outs GPR:$dst), (ins GPR:$a, so_imm:$b),
1681 DPFrm, IIC_iALUi, "rscs\t$dst, $a, $b",
1682 [(set GPR:$dst, (sube_dead_carry so_imm:$b, GPR:$a))]>,
1687 def RSCSrs : AXI1<0b0111, (outs GPR:$dst), (ins GPR:$a, so_reg:$b),
1688 DPSoRegFrm, IIC_iALUsr, "rscs\t$dst, $a, $b",
1689 [(set GPR:$dst, (sube_dead_carry so_reg:$b, GPR:$a))]>,
1696 // (sub X, imm) gets canonicalized to (add X, -imm). Match this form.
1697 def : ARMPat<(add GPR:$src, so_imm_neg:$imm),
1698 (SUBri GPR:$src, so_imm_neg:$imm)>;
1700 //def : ARMPat<(addc GPR:$src, so_imm_neg:$imm),
1701 // (SUBSri GPR:$src, so_imm_neg:$imm)>;
1702 //def : ARMPat<(adde GPR:$src, so_imm_neg:$imm),
1703 // (SBCri GPR:$src, so_imm_neg:$imm)>;
1705 // Note: These are implemented in C++ code, because they have to generate
1706 // ADD/SUBrs instructions, which use a complex pattern that a xform function
1708 // (mul X, 2^n+1) -> (add (X << n), X)
1709 // (mul X, 2^n-1) -> (rsb X, (X << n))
1711 // ARM Arithmetic Instruction -- for disassembly only
1712 // GPR:$dst = GPR:$a op GPR:$b
1713 class AAI<bits<8> op27_20, bits<4> op7_4, string opc>
1714 : AI<(outs GPR:$dst), (ins GPR:$a, GPR:$b), DPFrm, IIC_iALUr,
1715 opc, "\t$dst, $a, $b",
1716 [/* For disassembly only; pattern left blank */]> {
1717 let Inst{27-20} = op27_20;
1718 let Inst{7-4} = op7_4;
1721 // Saturating add/subtract -- for disassembly only
1723 def QADD : AAI<0b00010000, 0b0101, "qadd">;
1724 def QADD16 : AAI<0b01100010, 0b0001, "qadd16">;
1725 def QADD8 : AAI<0b01100010, 0b1001, "qadd8">;
1726 def QASX : AAI<0b01100010, 0b0011, "qasx">;
1727 def QDADD : AAI<0b00010100, 0b0101, "qdadd">;
1728 def QDSUB : AAI<0b00010110, 0b0101, "qdsub">;
1729 def QSAX : AAI<0b01100010, 0b0101, "qsax">;
1730 def QSUB : AAI<0b00010010, 0b0101, "qsub">;
1731 def QSUB16 : AAI<0b01100010, 0b0111, "qsub16">;
1732 def QSUB8 : AAI<0b01100010, 0b1111, "qsub8">;
1733 def UQADD16 : AAI<0b01100110, 0b0001, "uqadd16">;
1734 def UQADD8 : AAI<0b01100110, 0b1001, "uqadd8">;
1735 def UQASX : AAI<0b01100110, 0b0011, "uqasx">;
1736 def UQSAX : AAI<0b01100110, 0b0101, "uqsax">;
1737 def UQSUB16 : AAI<0b01100110, 0b0111, "uqsub16">;
1738 def UQSUB8 : AAI<0b01100110, 0b1111, "uqsub8">;
1740 // Signed/Unsigned add/subtract -- for disassembly only
1742 def SASX : AAI<0b01100001, 0b0011, "sasx">;
1743 def SADD16 : AAI<0b01100001, 0b0001, "sadd16">;
1744 def SADD8 : AAI<0b01100001, 0b1001, "sadd8">;
1745 def SSAX : AAI<0b01100001, 0b0101, "ssax">;
1746 def SSUB16 : AAI<0b01100001, 0b0111, "ssub16">;
1747 def SSUB8 : AAI<0b01100001, 0b1111, "ssub8">;
1748 def UASX : AAI<0b01100101, 0b0011, "uasx">;
1749 def UADD16 : AAI<0b01100101, 0b0001, "uadd16">;
1750 def UADD8 : AAI<0b01100101, 0b1001, "uadd8">;
1751 def USAX : AAI<0b01100101, 0b0101, "usax">;
1752 def USUB16 : AAI<0b01100101, 0b0111, "usub16">;
1753 def USUB8 : AAI<0b01100101, 0b1111, "usub8">;
1755 // Signed/Unsigned halving add/subtract -- for disassembly only
1757 def SHASX : AAI<0b01100011, 0b0011, "shasx">;
1758 def SHADD16 : AAI<0b01100011, 0b0001, "shadd16">;
1759 def SHADD8 : AAI<0b01100011, 0b1001, "shadd8">;
1760 def SHSAX : AAI<0b01100011, 0b0101, "shsax">;
1761 def SHSUB16 : AAI<0b01100011, 0b0111, "shsub16">;
1762 def SHSUB8 : AAI<0b01100011, 0b1111, "shsub8">;
1763 def UHASX : AAI<0b01100111, 0b0011, "uhasx">;
1764 def UHADD16 : AAI<0b01100111, 0b0001, "uhadd16">;
1765 def UHADD8 : AAI<0b01100111, 0b1001, "uhadd8">;
1766 def UHSAX : AAI<0b01100111, 0b0101, "uhsax">;
1767 def UHSUB16 : AAI<0b01100111, 0b0111, "uhsub16">;
1768 def UHSUB8 : AAI<0b01100111, 0b1111, "uhsub8">;
1770 // Unsigned Sum of Absolute Differences [and Accumulate] -- for disassembly only
1772 def USAD8 : AI<(outs GPR:$dst), (ins GPR:$a, GPR:$b),
1773 MulFrm /* for convenience */, NoItinerary, "usad8",
1774 "\t$dst, $a, $b", []>,
1775 Requires<[IsARM, HasV6]> {
1776 let Inst{27-20} = 0b01111000;
1777 let Inst{15-12} = 0b1111;
1778 let Inst{7-4} = 0b0001;
1780 def USADA8 : AI<(outs GPR:$dst), (ins GPR:$a, GPR:$b, GPR:$acc),
1781 MulFrm /* for convenience */, NoItinerary, "usada8",
1782 "\t$dst, $a, $b, $acc", []>,
1783 Requires<[IsARM, HasV6]> {
1784 let Inst{27-20} = 0b01111000;
1785 let Inst{7-4} = 0b0001;
1788 // Signed/Unsigned saturate -- for disassembly only
1790 def SSATlsl : AI<(outs GPR:$dst), (ins i32imm:$bit_pos, GPR:$a, i32imm:$shamt),
1791 DPFrm, NoItinerary, "ssat", "\t$dst, $bit_pos, $a, lsl $shamt",
1792 [/* For disassembly only; pattern left blank */]> {
1793 let Inst{27-21} = 0b0110101;
1794 let Inst{6-4} = 0b001;
1797 def SSATasr : AI<(outs GPR:$dst), (ins i32imm:$bit_pos, GPR:$a, i32imm:$shamt),
1798 DPFrm, NoItinerary, "ssat", "\t$dst, $bit_pos, $a, asr $shamt",
1799 [/* For disassembly only; pattern left blank */]> {
1800 let Inst{27-21} = 0b0110101;
1801 let Inst{6-4} = 0b101;
1804 def SSAT16 : AI<(outs GPR:$dst), (ins i32imm:$bit_pos, GPR:$a), DPFrm,
1805 NoItinerary, "ssat16", "\t$dst, $bit_pos, $a",
1806 [/* For disassembly only; pattern left blank */]> {
1807 let Inst{27-20} = 0b01101010;
1808 let Inst{7-4} = 0b0011;
1811 def USATlsl : AI<(outs GPR:$dst), (ins i32imm:$bit_pos, GPR:$a, i32imm:$shamt),
1812 DPFrm, NoItinerary, "usat", "\t$dst, $bit_pos, $a, lsl $shamt",
1813 [/* For disassembly only; pattern left blank */]> {
1814 let Inst{27-21} = 0b0110111;
1815 let Inst{6-4} = 0b001;
1818 def USATasr : AI<(outs GPR:$dst), (ins i32imm:$bit_pos, GPR:$a, i32imm:$shamt),
1819 DPFrm, NoItinerary, "usat", "\t$dst, $bit_pos, $a, asr $shamt",
1820 [/* For disassembly only; pattern left blank */]> {
1821 let Inst{27-21} = 0b0110111;
1822 let Inst{6-4} = 0b101;
1825 def USAT16 : AI<(outs GPR:$dst), (ins i32imm:$bit_pos, GPR:$a), DPFrm,
1826 NoItinerary, "usat16", "\t$dst, $bit_pos, $a",
1827 [/* For disassembly only; pattern left blank */]> {
1828 let Inst{27-20} = 0b01101110;
1829 let Inst{7-4} = 0b0011;
1832 //===----------------------------------------------------------------------===//
1833 // Bitwise Instructions.
1836 defm AND : AsI1_bin_irs<0b0000, "and",
1837 BinOpFrag<(and node:$LHS, node:$RHS)>, 1>;
1838 defm ORR : AsI1_bin_irs<0b1100, "orr",
1839 BinOpFrag<(or node:$LHS, node:$RHS)>, 1>;
1840 defm EOR : AsI1_bin_irs<0b0001, "eor",
1841 BinOpFrag<(xor node:$LHS, node:$RHS)>, 1>;
1842 defm BIC : AsI1_bin_irs<0b1110, "bic",
1843 BinOpFrag<(and node:$LHS, (not node:$RHS))>>;
1845 def BFC : I<(outs GPR:$dst), (ins GPR:$src, bf_inv_mask_imm:$imm),
1846 AddrMode1, Size4Bytes, IndexModeNone, DPFrm, IIC_iUNAsi,
1847 "bfc", "\t$dst, $imm", "$src = $dst",
1848 [(set GPR:$dst, (and GPR:$src, bf_inv_mask_imm:$imm))]>,
1849 Requires<[IsARM, HasV6T2]> {
1850 let Inst{27-21} = 0b0111110;
1851 let Inst{6-0} = 0b0011111;
1854 // A8.6.18 BFI - Bitfield insert (Encoding A1)
1855 // Added for disassembler with the pattern field purposely left blank.
1856 def BFI : I<(outs GPR:$dst), (ins GPR:$src, bf_inv_mask_imm:$imm),
1857 AddrMode1, Size4Bytes, IndexModeNone, DPFrm, IIC_iUNAsi,
1858 "bfi", "\t$dst, $src, $imm", "",
1859 [/* For disassembly only; pattern left blank */]>,
1860 Requires<[IsARM, HasV6T2]> {
1861 let Inst{27-21} = 0b0111110;
1862 let Inst{6-4} = 0b001; // Rn: Inst{3-0} != 15
1865 def MVNr : AsI1<0b1111, (outs GPR:$dst), (ins GPR:$src), DPFrm, IIC_iMOVr,
1866 "mvn", "\t$dst, $src",
1867 [(set GPR:$dst, (not GPR:$src))]>, UnaryDP {
1869 let Inst{11-4} = 0b00000000;
1871 def MVNs : AsI1<0b1111, (outs GPR:$dst), (ins so_reg:$src), DPSoRegFrm,
1872 IIC_iMOVsr, "mvn", "\t$dst, $src",
1873 [(set GPR:$dst, (not so_reg:$src))]>, UnaryDP {
1876 let isReMaterializable = 1, isAsCheapAsAMove = 1 in
1877 def MVNi : AsI1<0b1111, (outs GPR:$dst), (ins so_imm:$imm), DPFrm,
1878 IIC_iMOVi, "mvn", "\t$dst, $imm",
1879 [(set GPR:$dst, so_imm_not:$imm)]>,UnaryDP {
1883 def : ARMPat<(and GPR:$src, so_imm_not:$imm),
1884 (BICri GPR:$src, so_imm_not:$imm)>;
1886 //===----------------------------------------------------------------------===//
1887 // Multiply Instructions.
1890 let isCommutable = 1 in
1891 def MUL : AsMul1I<0b0000000, (outs GPR:$dst), (ins GPR:$a, GPR:$b),
1892 IIC_iMUL32, "mul", "\t$dst, $a, $b",
1893 [(set GPR:$dst, (mul GPR:$a, GPR:$b))]>;
1895 def MLA : AsMul1I<0b0000001, (outs GPR:$dst), (ins GPR:$a, GPR:$b, GPR:$c),
1896 IIC_iMAC32, "mla", "\t$dst, $a, $b, $c",
1897 [(set GPR:$dst, (add (mul GPR:$a, GPR:$b), GPR:$c))]>;
1899 def MLS : AMul1I<0b0000011, (outs GPR:$dst), (ins GPR:$a, GPR:$b, GPR:$c),
1900 IIC_iMAC32, "mls", "\t$dst, $a, $b, $c",
1901 [(set GPR:$dst, (sub GPR:$c, (mul GPR:$a, GPR:$b)))]>,
1902 Requires<[IsARM, HasV6T2]>;
1904 // Extra precision multiplies with low / high results
1905 let neverHasSideEffects = 1 in {
1906 let isCommutable = 1 in {
1907 def SMULL : AsMul1I<0b0000110, (outs GPR:$ldst, GPR:$hdst),
1908 (ins GPR:$a, GPR:$b), IIC_iMUL64,
1909 "smull", "\t$ldst, $hdst, $a, $b", []>;
1911 def UMULL : AsMul1I<0b0000100, (outs GPR:$ldst, GPR:$hdst),
1912 (ins GPR:$a, GPR:$b), IIC_iMUL64,
1913 "umull", "\t$ldst, $hdst, $a, $b", []>;
1916 // Multiply + accumulate
1917 def SMLAL : AsMul1I<0b0000111, (outs GPR:$ldst, GPR:$hdst),
1918 (ins GPR:$a, GPR:$b), IIC_iMAC64,
1919 "smlal", "\t$ldst, $hdst, $a, $b", []>;
1921 def UMLAL : AsMul1I<0b0000101, (outs GPR:$ldst, GPR:$hdst),
1922 (ins GPR:$a, GPR:$b), IIC_iMAC64,
1923 "umlal", "\t$ldst, $hdst, $a, $b", []>;
1925 def UMAAL : AMul1I <0b0000010, (outs GPR:$ldst, GPR:$hdst),
1926 (ins GPR:$a, GPR:$b), IIC_iMAC64,
1927 "umaal", "\t$ldst, $hdst, $a, $b", []>,
1928 Requires<[IsARM, HasV6]>;
1929 } // neverHasSideEffects
1931 // Most significant word multiply
1932 def SMMUL : AMul2I <0b0111010, (outs GPR:$dst), (ins GPR:$a, GPR:$b),
1933 IIC_iMUL32, "smmul", "\t$dst, $a, $b",
1934 [(set GPR:$dst, (mulhs GPR:$a, GPR:$b))]>,
1935 Requires<[IsARM, HasV6]> {
1936 let Inst{7-4} = 0b0001;
1937 let Inst{15-12} = 0b1111;
1940 def SMMULR : AMul2I <0b0111010, (outs GPR:$dst), (ins GPR:$a, GPR:$b),
1941 IIC_iMUL32, "smmulr", "\t$dst, $a, $b",
1942 [/* For disassembly only; pattern left blank */]>,
1943 Requires<[IsARM, HasV6]> {
1944 let Inst{7-4} = 0b0011; // R = 1
1945 let Inst{15-12} = 0b1111;
1948 def SMMLA : AMul2I <0b0111010, (outs GPR:$dst), (ins GPR:$a, GPR:$b, GPR:$c),
1949 IIC_iMAC32, "smmla", "\t$dst, $a, $b, $c",
1950 [(set GPR:$dst, (add (mulhs GPR:$a, GPR:$b), GPR:$c))]>,
1951 Requires<[IsARM, HasV6]> {
1952 let Inst{7-4} = 0b0001;
1955 def SMMLAR : AMul2I <0b0111010, (outs GPR:$dst), (ins GPR:$a, GPR:$b, GPR:$c),
1956 IIC_iMAC32, "smmlar", "\t$dst, $a, $b, $c",
1957 [/* For disassembly only; pattern left blank */]>,
1958 Requires<[IsARM, HasV6]> {
1959 let Inst{7-4} = 0b0011; // R = 1
1962 def SMMLS : AMul2I <0b0111010, (outs GPR:$dst), (ins GPR:$a, GPR:$b, GPR:$c),
1963 IIC_iMAC32, "smmls", "\t$dst, $a, $b, $c",
1964 [(set GPR:$dst, (sub GPR:$c, (mulhs GPR:$a, GPR:$b)))]>,
1965 Requires<[IsARM, HasV6]> {
1966 let Inst{7-4} = 0b1101;
1969 def SMMLSR : AMul2I <0b0111010, (outs GPR:$dst), (ins GPR:$a, GPR:$b, GPR:$c),
1970 IIC_iMAC32, "smmlsr", "\t$dst, $a, $b, $c",
1971 [/* For disassembly only; pattern left blank */]>,
1972 Requires<[IsARM, HasV6]> {
1973 let Inst{7-4} = 0b1111; // R = 1
1976 multiclass AI_smul<string opc, PatFrag opnode> {
1977 def BB : AMulxyI<0b0001011, (outs GPR:$dst), (ins GPR:$a, GPR:$b),
1978 IIC_iMUL32, !strconcat(opc, "bb"), "\t$dst, $a, $b",
1979 [(set GPR:$dst, (opnode (sext_inreg GPR:$a, i16),
1980 (sext_inreg GPR:$b, i16)))]>,
1981 Requires<[IsARM, HasV5TE]> {
1986 def BT : AMulxyI<0b0001011, (outs GPR:$dst), (ins GPR:$a, GPR:$b),
1987 IIC_iMUL32, !strconcat(opc, "bt"), "\t$dst, $a, $b",
1988 [(set GPR:$dst, (opnode (sext_inreg GPR:$a, i16),
1989 (sra GPR:$b, (i32 16))))]>,
1990 Requires<[IsARM, HasV5TE]> {
1995 def TB : AMulxyI<0b0001011, (outs GPR:$dst), (ins GPR:$a, GPR:$b),
1996 IIC_iMUL32, !strconcat(opc, "tb"), "\t$dst, $a, $b",
1997 [(set GPR:$dst, (opnode (sra GPR:$a, (i32 16)),
1998 (sext_inreg GPR:$b, i16)))]>,
1999 Requires<[IsARM, HasV5TE]> {
2004 def TT : AMulxyI<0b0001011, (outs GPR:$dst), (ins GPR:$a, GPR:$b),
2005 IIC_iMUL32, !strconcat(opc, "tt"), "\t$dst, $a, $b",
2006 [(set GPR:$dst, (opnode (sra GPR:$a, (i32 16)),
2007 (sra GPR:$b, (i32 16))))]>,
2008 Requires<[IsARM, HasV5TE]> {
2013 def WB : AMulxyI<0b0001001, (outs GPR:$dst), (ins GPR:$a, GPR:$b),
2014 IIC_iMUL16, !strconcat(opc, "wb"), "\t$dst, $a, $b",
2015 [(set GPR:$dst, (sra (opnode GPR:$a,
2016 (sext_inreg GPR:$b, i16)), (i32 16)))]>,
2017 Requires<[IsARM, HasV5TE]> {
2022 def WT : AMulxyI<0b0001001, (outs GPR:$dst), (ins GPR:$a, GPR:$b),
2023 IIC_iMUL16, !strconcat(opc, "wt"), "\t$dst, $a, $b",
2024 [(set GPR:$dst, (sra (opnode GPR:$a,
2025 (sra GPR:$b, (i32 16))), (i32 16)))]>,
2026 Requires<[IsARM, HasV5TE]> {
2033 multiclass AI_smla<string opc, PatFrag opnode> {
2034 def BB : AMulxyI<0b0001000, (outs GPR:$dst), (ins GPR:$a, GPR:$b, GPR:$acc),
2035 IIC_iMAC16, !strconcat(opc, "bb"), "\t$dst, $a, $b, $acc",
2036 [(set GPR:$dst, (add GPR:$acc,
2037 (opnode (sext_inreg GPR:$a, i16),
2038 (sext_inreg GPR:$b, i16))))]>,
2039 Requires<[IsARM, HasV5TE]> {
2044 def BT : AMulxyI<0b0001000, (outs GPR:$dst), (ins GPR:$a, GPR:$b, GPR:$acc),
2045 IIC_iMAC16, !strconcat(opc, "bt"), "\t$dst, $a, $b, $acc",
2046 [(set GPR:$dst, (add GPR:$acc, (opnode (sext_inreg GPR:$a, i16),
2047 (sra GPR:$b, (i32 16)))))]>,
2048 Requires<[IsARM, HasV5TE]> {
2053 def TB : AMulxyI<0b0001000, (outs GPR:$dst), (ins GPR:$a, GPR:$b, GPR:$acc),
2054 IIC_iMAC16, !strconcat(opc, "tb"), "\t$dst, $a, $b, $acc",
2055 [(set GPR:$dst, (add GPR:$acc, (opnode (sra GPR:$a, (i32 16)),
2056 (sext_inreg GPR:$b, i16))))]>,
2057 Requires<[IsARM, HasV5TE]> {
2062 def TT : AMulxyI<0b0001000, (outs GPR:$dst), (ins GPR:$a, GPR:$b, GPR:$acc),
2063 IIC_iMAC16, !strconcat(opc, "tt"), "\t$dst, $a, $b, $acc",
2064 [(set GPR:$dst, (add GPR:$acc, (opnode (sra GPR:$a, (i32 16)),
2065 (sra GPR:$b, (i32 16)))))]>,
2066 Requires<[IsARM, HasV5TE]> {
2071 def WB : AMulxyI<0b0001001, (outs GPR:$dst), (ins GPR:$a, GPR:$b, GPR:$acc),
2072 IIC_iMAC16, !strconcat(opc, "wb"), "\t$dst, $a, $b, $acc",
2073 [(set GPR:$dst, (add GPR:$acc, (sra (opnode GPR:$a,
2074 (sext_inreg GPR:$b, i16)), (i32 16))))]>,
2075 Requires<[IsARM, HasV5TE]> {
2080 def WT : AMulxyI<0b0001001, (outs GPR:$dst), (ins GPR:$a, GPR:$b, GPR:$acc),
2081 IIC_iMAC16, !strconcat(opc, "wt"), "\t$dst, $a, $b, $acc",
2082 [(set GPR:$dst, (add GPR:$acc, (sra (opnode GPR:$a,
2083 (sra GPR:$b, (i32 16))), (i32 16))))]>,
2084 Requires<[IsARM, HasV5TE]> {
2090 defm SMUL : AI_smul<"smul", BinOpFrag<(mul node:$LHS, node:$RHS)>>;
2091 defm SMLA : AI_smla<"smla", BinOpFrag<(mul node:$LHS, node:$RHS)>>;
2093 // Halfword multiply accumulate long: SMLAL<x><y> -- for disassembly only
2094 def SMLALBB : AMulxyI<0b0001010,(outs GPR:$ldst,GPR:$hdst),(ins GPR:$a,GPR:$b),
2095 IIC_iMAC64, "smlalbb", "\t$ldst, $hdst, $a, $b",
2096 [/* For disassembly only; pattern left blank */]>,
2097 Requires<[IsARM, HasV5TE]> {
2102 def SMLALBT : AMulxyI<0b0001010,(outs GPR:$ldst,GPR:$hdst),(ins GPR:$a,GPR:$b),
2103 IIC_iMAC64, "smlalbt", "\t$ldst, $hdst, $a, $b",
2104 [/* For disassembly only; pattern left blank */]>,
2105 Requires<[IsARM, HasV5TE]> {
2110 def SMLALTB : AMulxyI<0b0001010,(outs GPR:$ldst,GPR:$hdst),(ins GPR:$a,GPR:$b),
2111 IIC_iMAC64, "smlaltb", "\t$ldst, $hdst, $a, $b",
2112 [/* For disassembly only; pattern left blank */]>,
2113 Requires<[IsARM, HasV5TE]> {
2118 def SMLALTT : AMulxyI<0b0001010,(outs GPR:$ldst,GPR:$hdst),(ins GPR:$a,GPR:$b),
2119 IIC_iMAC64, "smlaltt", "\t$ldst, $hdst, $a, $b",
2120 [/* For disassembly only; pattern left blank */]>,
2121 Requires<[IsARM, HasV5TE]> {
2126 // Helper class for AI_smld -- for disassembly only
2127 class AMulDualI<bit long, bit sub, bit swap, dag oops, dag iops,
2128 InstrItinClass itin, string opc, string asm>
2129 : AI<oops, iops, MulFrm, itin, opc, asm, []>, Requires<[IsARM, HasV6]> {
2134 let Inst{21-20} = 0b00;
2135 let Inst{22} = long;
2136 let Inst{27-23} = 0b01110;
2139 multiclass AI_smld<bit sub, string opc> {
2141 def D : AMulDualI<0, sub, 0, (outs GPR:$dst), (ins GPR:$a, GPR:$b, GPR:$acc),
2142 NoItinerary, !strconcat(opc, "d"), "\t$dst, $a, $b, $acc">;
2144 def DX : AMulDualI<0, sub, 1, (outs GPR:$dst), (ins GPR:$a, GPR:$b, GPR:$acc),
2145 NoItinerary, !strconcat(opc, "dx"), "\t$dst, $a, $b, $acc">;
2147 def LD : AMulDualI<1, sub, 0, (outs GPR:$ldst,GPR:$hdst), (ins GPR:$a,GPR:$b),
2148 NoItinerary, !strconcat(opc, "ld"), "\t$ldst, $hdst, $a, $b">;
2150 def LDX : AMulDualI<1, sub, 1, (outs GPR:$ldst,GPR:$hdst),(ins GPR:$a,GPR:$b),
2151 NoItinerary, !strconcat(opc, "ldx"),"\t$ldst, $hdst, $a, $b">;
2155 defm SMLA : AI_smld<0, "smla">;
2156 defm SMLS : AI_smld<1, "smls">;
2158 multiclass AI_sdml<bit sub, string opc> {
2160 def D : AMulDualI<0, sub, 0, (outs GPR:$dst), (ins GPR:$a, GPR:$b),
2161 NoItinerary, !strconcat(opc, "d"), "\t$dst, $a, $b"> {
2162 let Inst{15-12} = 0b1111;
2165 def DX : AMulDualI<0, sub, 1, (outs GPR:$dst), (ins GPR:$a, GPR:$b),
2166 NoItinerary, !strconcat(opc, "dx"), "\t$dst, $a, $b"> {
2167 let Inst{15-12} = 0b1111;
2172 defm SMUA : AI_sdml<0, "smua">;
2173 defm SMUS : AI_sdml<1, "smus">;
2175 //===----------------------------------------------------------------------===//
2176 // Misc. Arithmetic Instructions.
2179 def CLZ : AMiscA1I<0b000010110, (outs GPR:$dst), (ins GPR:$src), IIC_iUNAr,
2180 "clz", "\t$dst, $src",
2181 [(set GPR:$dst, (ctlz GPR:$src))]>, Requires<[IsARM, HasV5T]> {
2182 let Inst{7-4} = 0b0001;
2183 let Inst{11-8} = 0b1111;
2184 let Inst{19-16} = 0b1111;
2187 def RBIT : AMiscA1I<0b01101111, (outs GPR:$dst), (ins GPR:$src), IIC_iUNAr,
2188 "rbit", "\t$dst, $src",
2189 [(set GPR:$dst, (ARMrbit GPR:$src))]>,
2190 Requires<[IsARM, HasV6T2]> {
2191 let Inst{7-4} = 0b0011;
2192 let Inst{11-8} = 0b1111;
2193 let Inst{19-16} = 0b1111;
2196 def REV : AMiscA1I<0b01101011, (outs GPR:$dst), (ins GPR:$src), IIC_iUNAr,
2197 "rev", "\t$dst, $src",
2198 [(set GPR:$dst, (bswap GPR:$src))]>, Requires<[IsARM, HasV6]> {
2199 let Inst{7-4} = 0b0011;
2200 let Inst{11-8} = 0b1111;
2201 let Inst{19-16} = 0b1111;
2204 def REV16 : AMiscA1I<0b01101011, (outs GPR:$dst), (ins GPR:$src), IIC_iUNAr,
2205 "rev16", "\t$dst, $src",
2207 (or (and (srl GPR:$src, (i32 8)), 0xFF),
2208 (or (and (shl GPR:$src, (i32 8)), 0xFF00),
2209 (or (and (srl GPR:$src, (i32 8)), 0xFF0000),
2210 (and (shl GPR:$src, (i32 8)), 0xFF000000)))))]>,
2211 Requires<[IsARM, HasV6]> {
2212 let Inst{7-4} = 0b1011;
2213 let Inst{11-8} = 0b1111;
2214 let Inst{19-16} = 0b1111;
2217 def REVSH : AMiscA1I<0b01101111, (outs GPR:$dst), (ins GPR:$src), IIC_iUNAr,
2218 "revsh", "\t$dst, $src",
2221 (or (srl (and GPR:$src, 0xFF00), (i32 8)),
2222 (shl GPR:$src, (i32 8))), i16))]>,
2223 Requires<[IsARM, HasV6]> {
2224 let Inst{7-4} = 0b1011;
2225 let Inst{11-8} = 0b1111;
2226 let Inst{19-16} = 0b1111;
2229 def PKHBT : AMiscA1I<0b01101000, (outs GPR:$dst),
2230 (ins GPR:$src1, GPR:$src2, i32imm:$shamt),
2231 IIC_iALUsi, "pkhbt", "\t$dst, $src1, $src2, lsl $shamt",
2232 [(set GPR:$dst, (or (and GPR:$src1, 0xFFFF),
2233 (and (shl GPR:$src2, (i32 imm:$shamt)),
2235 Requires<[IsARM, HasV6]> {
2236 let Inst{6-4} = 0b001;
2239 // Alternate cases for PKHBT where identities eliminate some nodes.
2240 def : ARMV6Pat<(or (and GPR:$src1, 0xFFFF), (and GPR:$src2, 0xFFFF0000)),
2241 (PKHBT GPR:$src1, GPR:$src2, 0)>;
2242 def : ARMV6Pat<(or (and GPR:$src1, 0xFFFF), (shl GPR:$src2, imm16_31:$shamt)),
2243 (PKHBT GPR:$src1, GPR:$src2, imm16_31:$shamt)>;
2246 def PKHTB : AMiscA1I<0b01101000, (outs GPR:$dst),
2247 (ins GPR:$src1, GPR:$src2, i32imm:$shamt),
2248 IIC_iALUsi, "pkhtb", "\t$dst, $src1, $src2, asr $shamt",
2249 [(set GPR:$dst, (or (and GPR:$src1, 0xFFFF0000),
2250 (and (sra GPR:$src2, imm16_31:$shamt),
2251 0xFFFF)))]>, Requires<[IsARM, HasV6]> {
2252 let Inst{6-4} = 0b101;
2255 // Alternate cases for PKHTB where identities eliminate some nodes. Note that
2256 // a shift amount of 0 is *not legal* here, it is PKHBT instead.
2257 def : ARMV6Pat<(or (and GPR:$src1, 0xFFFF0000), (srl GPR:$src2, (i32 16))),
2258 (PKHTB GPR:$src1, GPR:$src2, 16)>;
2259 def : ARMV6Pat<(or (and GPR:$src1, 0xFFFF0000),
2260 (and (srl GPR:$src2, imm1_15:$shamt), 0xFFFF)),
2261 (PKHTB GPR:$src1, GPR:$src2, imm1_15:$shamt)>;
2263 //===----------------------------------------------------------------------===//
2264 // Comparison Instructions...
2267 defm CMP : AI1_cmp_irs<0b1010, "cmp",
2268 BinOpFrag<(ARMcmp node:$LHS, node:$RHS)>>;
2269 //FIXME: Disable CMN, as CCodes are backwards from compare expectations
2270 // Compare-to-zero still works out, just not the relationals
2271 //defm CMN : AI1_cmp_irs<0b1011, "cmn",
2272 // BinOpFrag<(ARMcmp node:$LHS,(ineg node:$RHS))>>;
2274 // Note that TST/TEQ don't set all the same flags that CMP does!
2275 defm TST : AI1_cmp_irs<0b1000, "tst",
2276 BinOpFrag<(ARMcmpZ (and node:$LHS, node:$RHS), 0)>, 1>;
2277 defm TEQ : AI1_cmp_irs<0b1001, "teq",
2278 BinOpFrag<(ARMcmpZ (xor node:$LHS, node:$RHS), 0)>, 1>;
2280 defm CMPz : AI1_cmp_irs<0b1010, "cmp",
2281 BinOpFrag<(ARMcmpZ node:$LHS, node:$RHS)>>;
2282 defm CMNz : AI1_cmp_irs<0b1011, "cmn",
2283 BinOpFrag<(ARMcmpZ node:$LHS,(ineg node:$RHS))>>;
2285 //def : ARMPat<(ARMcmp GPR:$src, so_imm_neg:$imm),
2286 // (CMNri GPR:$src, so_imm_neg:$imm)>;
2288 def : ARMPat<(ARMcmpZ GPR:$src, so_imm_neg:$imm),
2289 (CMNzri GPR:$src, so_imm_neg:$imm)>;
2291 // Pseudo i64 compares for some floating point compares.
2292 let usesCustomInserter = 1, isBranch = 1, isTerminator = 1,
2294 def BCCi64 : PseudoInst<(outs),
2295 (ins i32imm:$cc, GPR:$lhs1, GPR:$lhs2, GPR:$rhs1, GPR:$rhs2, brtarget:$dst),
2297 "${:comment} B\t$dst GPR:$lhs1, GPR:$lhs2, GPR:$rhs1, GPR:$rhs2, imm:$cc",
2298 [(ARMBcci64 imm:$cc, GPR:$lhs1, GPR:$lhs2, GPR:$rhs1, GPR:$rhs2, bb:$dst)]>;
2300 def BCCZi64 : PseudoInst<(outs),
2301 (ins i32imm:$cc, GPR:$lhs1, GPR:$lhs2, brtarget:$dst),
2303 "${:comment} B\t$dst GPR:$lhs1, GPR:$lhs2, 0, 0, imm:$cc",
2304 [(ARMBcci64 imm:$cc, GPR:$lhs1, GPR:$lhs2, 0, 0, bb:$dst)]>;
2305 } // usesCustomInserter
2308 // Conditional moves
2309 // FIXME: should be able to write a pattern for ARMcmov, but can't use
2310 // a two-value operand where a dag node expects two operands. :(
2311 let neverHasSideEffects = 1 in {
2312 def MOVCCr : AI1<0b1101, (outs GPR:$dst), (ins GPR:$false, GPR:$true), DPFrm,
2313 IIC_iCMOVr, "mov", "\t$dst, $true",
2314 [/*(set GPR:$dst, (ARMcmov GPR:$false, GPR:$true, imm:$cc, CCR:$ccr))*/]>,
2315 RegConstraint<"$false = $dst">, UnaryDP {
2316 let Inst{11-4} = 0b00000000;
2320 def MOVCCs : AI1<0b1101, (outs GPR:$dst),
2321 (ins GPR:$false, so_reg:$true), DPSoRegFrm, IIC_iCMOVsr,
2322 "mov", "\t$dst, $true",
2323 [/*(set GPR:$dst, (ARMcmov GPR:$false, so_reg:$true, imm:$cc, CCR:$ccr))*/]>,
2324 RegConstraint<"$false = $dst">, UnaryDP {
2328 def MOVCCi : AI1<0b1101, (outs GPR:$dst),
2329 (ins GPR:$false, so_imm:$true), DPFrm, IIC_iCMOVi,
2330 "mov", "\t$dst, $true",
2331 [/*(set GPR:$dst, (ARMcmov GPR:$false, so_imm:$true, imm:$cc, CCR:$ccr))*/]>,
2332 RegConstraint<"$false = $dst">, UnaryDP {
2335 } // neverHasSideEffects
2337 //===----------------------------------------------------------------------===//
2338 // Atomic operations intrinsics
2341 // memory barriers protect the atomic sequences
2342 let hasSideEffects = 1 in {
2343 def Int_MemBarrierV7 : AInoP<(outs), (ins),
2344 Pseudo, NoItinerary,
2346 [(ARMMemBarrierV7)]>,
2347 Requires<[IsARM, HasV7]> {
2348 let Inst{31-4} = 0xf57ff05;
2349 // FIXME: add support for options other than a full system DMB
2350 // See DMB disassembly-only variants below.
2351 let Inst{3-0} = 0b1111;
2354 def Int_SyncBarrierV7 : AInoP<(outs), (ins),
2355 Pseudo, NoItinerary,
2357 [(ARMSyncBarrierV7)]>,
2358 Requires<[IsARM, HasV7]> {
2359 let Inst{31-4} = 0xf57ff04;
2360 // FIXME: add support for options other than a full system DSB
2361 // See DSB disassembly-only variants below.
2362 let Inst{3-0} = 0b1111;
2365 def Int_MemBarrierV6 : AInoP<(outs), (ins GPR:$zero),
2366 Pseudo, NoItinerary,
2367 "mcr", "\tp15, 0, $zero, c7, c10, 5",
2368 [(ARMMemBarrierV6 GPR:$zero)]>,
2369 Requires<[IsARM, HasV6]> {
2370 // FIXME: add support for options other than a full system DMB
2371 // FIXME: add encoding
2374 def Int_SyncBarrierV6 : AInoP<(outs), (ins GPR:$zero),
2375 Pseudo, NoItinerary,
2376 "mcr", "\tp15, 0, $zero, c7, c10, 4",
2377 [(ARMSyncBarrierV6 GPR:$zero)]>,
2378 Requires<[IsARM, HasV6]> {
2379 // FIXME: add support for options other than a full system DSB
2380 // FIXME: add encoding
2384 // Helper class for multiclass MemB -- for disassembly only
2385 class AMBI<string opc, string asm>
2386 : AInoP<(outs), (ins), MiscFrm, NoItinerary, opc, asm,
2387 [/* For disassembly only; pattern left blank */]>,
2388 Requires<[IsARM, HasV7]> {
2389 let Inst{31-20} = 0xf57;
2392 multiclass MemB<bits<4> op7_4, string opc> {
2394 def st : AMBI<opc, "\tst"> {
2395 let Inst{7-4} = op7_4;
2396 let Inst{3-0} = 0b1110;
2399 def ish : AMBI<opc, "\tish"> {
2400 let Inst{7-4} = op7_4;
2401 let Inst{3-0} = 0b1011;
2404 def ishst : AMBI<opc, "\tishst"> {
2405 let Inst{7-4} = op7_4;
2406 let Inst{3-0} = 0b1010;
2409 def nsh : AMBI<opc, "\tnsh"> {
2410 let Inst{7-4} = op7_4;
2411 let Inst{3-0} = 0b0111;
2414 def nshst : AMBI<opc, "\tnshst"> {
2415 let Inst{7-4} = op7_4;
2416 let Inst{3-0} = 0b0110;
2419 def osh : AMBI<opc, "\tosh"> {
2420 let Inst{7-4} = op7_4;
2421 let Inst{3-0} = 0b0011;
2424 def oshst : AMBI<opc, "\toshst"> {
2425 let Inst{7-4} = op7_4;
2426 let Inst{3-0} = 0b0010;
2430 // These DMB variants are for disassembly only.
2431 defm DMB : MemB<0b0101, "dmb">;
2433 // These DSB variants are for disassembly only.
2434 defm DSB : MemB<0b0100, "dsb">;
2436 // ISB has only full system option -- for disassembly only
2437 def ISBsy : AMBI<"isb", ""> {
2438 let Inst{7-4} = 0b0110;
2439 let Inst{3-0} = 0b1111;
2442 let usesCustomInserter = 1 in {
2443 let Uses = [CPSR] in {
2444 def ATOMIC_LOAD_ADD_I8 : PseudoInst<
2445 (outs GPR:$dst), (ins GPR:$ptr, GPR:$incr), NoItinerary,
2446 "${:comment} ATOMIC_LOAD_ADD_I8 PSEUDO!",
2447 [(set GPR:$dst, (atomic_load_add_8 GPR:$ptr, GPR:$incr))]>;
2448 def ATOMIC_LOAD_SUB_I8 : PseudoInst<
2449 (outs GPR:$dst), (ins GPR:$ptr, GPR:$incr), NoItinerary,
2450 "${:comment} ATOMIC_LOAD_SUB_I8 PSEUDO!",
2451 [(set GPR:$dst, (atomic_load_sub_8 GPR:$ptr, GPR:$incr))]>;
2452 def ATOMIC_LOAD_AND_I8 : PseudoInst<
2453 (outs GPR:$dst), (ins GPR:$ptr, GPR:$incr), NoItinerary,
2454 "${:comment} ATOMIC_LOAD_AND_I8 PSEUDO!",
2455 [(set GPR:$dst, (atomic_load_and_8 GPR:$ptr, GPR:$incr))]>;
2456 def ATOMIC_LOAD_OR_I8 : PseudoInst<
2457 (outs GPR:$dst), (ins GPR:$ptr, GPR:$incr), NoItinerary,
2458 "${:comment} ATOMIC_LOAD_OR_I8 PSEUDO!",
2459 [(set GPR:$dst, (atomic_load_or_8 GPR:$ptr, GPR:$incr))]>;
2460 def ATOMIC_LOAD_XOR_I8 : PseudoInst<
2461 (outs GPR:$dst), (ins GPR:$ptr, GPR:$incr), NoItinerary,
2462 "${:comment} ATOMIC_LOAD_XOR_I8 PSEUDO!",
2463 [(set GPR:$dst, (atomic_load_xor_8 GPR:$ptr, GPR:$incr))]>;
2464 def ATOMIC_LOAD_NAND_I8 : PseudoInst<
2465 (outs GPR:$dst), (ins GPR:$ptr, GPR:$incr), NoItinerary,
2466 "${:comment} ATOMIC_LOAD_NAND_I8 PSEUDO!",
2467 [(set GPR:$dst, (atomic_load_nand_8 GPR:$ptr, GPR:$incr))]>;
2468 def ATOMIC_LOAD_ADD_I16 : PseudoInst<
2469 (outs GPR:$dst), (ins GPR:$ptr, GPR:$incr), NoItinerary,
2470 "${:comment} ATOMIC_LOAD_ADD_I16 PSEUDO!",
2471 [(set GPR:$dst, (atomic_load_add_16 GPR:$ptr, GPR:$incr))]>;
2472 def ATOMIC_LOAD_SUB_I16 : PseudoInst<
2473 (outs GPR:$dst), (ins GPR:$ptr, GPR:$incr), NoItinerary,
2474 "${:comment} ATOMIC_LOAD_SUB_I16 PSEUDO!",
2475 [(set GPR:$dst, (atomic_load_sub_16 GPR:$ptr, GPR:$incr))]>;
2476 def ATOMIC_LOAD_AND_I16 : PseudoInst<
2477 (outs GPR:$dst), (ins GPR:$ptr, GPR:$incr), NoItinerary,
2478 "${:comment} ATOMIC_LOAD_AND_I16 PSEUDO!",
2479 [(set GPR:$dst, (atomic_load_and_16 GPR:$ptr, GPR:$incr))]>;
2480 def ATOMIC_LOAD_OR_I16 : PseudoInst<
2481 (outs GPR:$dst), (ins GPR:$ptr, GPR:$incr), NoItinerary,
2482 "${:comment} ATOMIC_LOAD_OR_I16 PSEUDO!",
2483 [(set GPR:$dst, (atomic_load_or_16 GPR:$ptr, GPR:$incr))]>;
2484 def ATOMIC_LOAD_XOR_I16 : PseudoInst<
2485 (outs GPR:$dst), (ins GPR:$ptr, GPR:$incr), NoItinerary,
2486 "${:comment} ATOMIC_LOAD_XOR_I16 PSEUDO!",
2487 [(set GPR:$dst, (atomic_load_xor_16 GPR:$ptr, GPR:$incr))]>;
2488 def ATOMIC_LOAD_NAND_I16 : PseudoInst<
2489 (outs GPR:$dst), (ins GPR:$ptr, GPR:$incr), NoItinerary,
2490 "${:comment} ATOMIC_LOAD_NAND_I16 PSEUDO!",
2491 [(set GPR:$dst, (atomic_load_nand_16 GPR:$ptr, GPR:$incr))]>;
2492 def ATOMIC_LOAD_ADD_I32 : PseudoInst<
2493 (outs GPR:$dst), (ins GPR:$ptr, GPR:$incr), NoItinerary,
2494 "${:comment} ATOMIC_LOAD_ADD_I32 PSEUDO!",
2495 [(set GPR:$dst, (atomic_load_add_32 GPR:$ptr, GPR:$incr))]>;
2496 def ATOMIC_LOAD_SUB_I32 : PseudoInst<
2497 (outs GPR:$dst), (ins GPR:$ptr, GPR:$incr), NoItinerary,
2498 "${:comment} ATOMIC_LOAD_SUB_I32 PSEUDO!",
2499 [(set GPR:$dst, (atomic_load_sub_32 GPR:$ptr, GPR:$incr))]>;
2500 def ATOMIC_LOAD_AND_I32 : PseudoInst<
2501 (outs GPR:$dst), (ins GPR:$ptr, GPR:$incr), NoItinerary,
2502 "${:comment} ATOMIC_LOAD_AND_I32 PSEUDO!",
2503 [(set GPR:$dst, (atomic_load_and_32 GPR:$ptr, GPR:$incr))]>;
2504 def ATOMIC_LOAD_OR_I32 : PseudoInst<
2505 (outs GPR:$dst), (ins GPR:$ptr, GPR:$incr), NoItinerary,
2506 "${:comment} ATOMIC_LOAD_OR_I32 PSEUDO!",
2507 [(set GPR:$dst, (atomic_load_or_32 GPR:$ptr, GPR:$incr))]>;
2508 def ATOMIC_LOAD_XOR_I32 : PseudoInst<
2509 (outs GPR:$dst), (ins GPR:$ptr, GPR:$incr), NoItinerary,
2510 "${:comment} ATOMIC_LOAD_XOR_I32 PSEUDO!",
2511 [(set GPR:$dst, (atomic_load_xor_32 GPR:$ptr, GPR:$incr))]>;
2512 def ATOMIC_LOAD_NAND_I32 : PseudoInst<
2513 (outs GPR:$dst), (ins GPR:$ptr, GPR:$incr), NoItinerary,
2514 "${:comment} ATOMIC_LOAD_NAND_I32 PSEUDO!",
2515 [(set GPR:$dst, (atomic_load_nand_32 GPR:$ptr, GPR:$incr))]>;
2517 def ATOMIC_SWAP_I8 : PseudoInst<
2518 (outs GPR:$dst), (ins GPR:$ptr, GPR:$new), NoItinerary,
2519 "${:comment} ATOMIC_SWAP_I8 PSEUDO!",
2520 [(set GPR:$dst, (atomic_swap_8 GPR:$ptr, GPR:$new))]>;
2521 def ATOMIC_SWAP_I16 : PseudoInst<
2522 (outs GPR:$dst), (ins GPR:$ptr, GPR:$new), NoItinerary,
2523 "${:comment} ATOMIC_SWAP_I16 PSEUDO!",
2524 [(set GPR:$dst, (atomic_swap_16 GPR:$ptr, GPR:$new))]>;
2525 def ATOMIC_SWAP_I32 : PseudoInst<
2526 (outs GPR:$dst), (ins GPR:$ptr, GPR:$new), NoItinerary,
2527 "${:comment} ATOMIC_SWAP_I32 PSEUDO!",
2528 [(set GPR:$dst, (atomic_swap_32 GPR:$ptr, GPR:$new))]>;
2530 def ATOMIC_CMP_SWAP_I8 : PseudoInst<
2531 (outs GPR:$dst), (ins GPR:$ptr, GPR:$old, GPR:$new), NoItinerary,
2532 "${:comment} ATOMIC_CMP_SWAP_I8 PSEUDO!",
2533 [(set GPR:$dst, (atomic_cmp_swap_8 GPR:$ptr, GPR:$old, GPR:$new))]>;
2534 def ATOMIC_CMP_SWAP_I16 : PseudoInst<
2535 (outs GPR:$dst), (ins GPR:$ptr, GPR:$old, GPR:$new), NoItinerary,
2536 "${:comment} ATOMIC_CMP_SWAP_I16 PSEUDO!",
2537 [(set GPR:$dst, (atomic_cmp_swap_16 GPR:$ptr, GPR:$old, GPR:$new))]>;
2538 def ATOMIC_CMP_SWAP_I32 : PseudoInst<
2539 (outs GPR:$dst), (ins GPR:$ptr, GPR:$old, GPR:$new), NoItinerary,
2540 "${:comment} ATOMIC_CMP_SWAP_I32 PSEUDO!",
2541 [(set GPR:$dst, (atomic_cmp_swap_32 GPR:$ptr, GPR:$old, GPR:$new))]>;
2545 let mayLoad = 1 in {
2546 def LDREXB : AIldrex<0b10, (outs GPR:$dest), (ins GPR:$ptr), NoItinerary,
2547 "ldrexb", "\t$dest, [$ptr]",
2549 def LDREXH : AIldrex<0b11, (outs GPR:$dest), (ins GPR:$ptr), NoItinerary,
2550 "ldrexh", "\t$dest, [$ptr]",
2552 def LDREX : AIldrex<0b00, (outs GPR:$dest), (ins GPR:$ptr), NoItinerary,
2553 "ldrex", "\t$dest, [$ptr]",
2555 def LDREXD : AIldrex<0b01, (outs GPR:$dest, GPR:$dest2), (ins GPR:$ptr),
2557 "ldrexd", "\t$dest, $dest2, [$ptr]",
2561 let mayStore = 1, Constraints = "@earlyclobber $success" in {
2562 def STREXB : AIstrex<0b10, (outs GPR:$success), (ins GPR:$src, GPR:$ptr),
2564 "strexb", "\t$success, $src, [$ptr]",
2566 def STREXH : AIstrex<0b11, (outs GPR:$success), (ins GPR:$src, GPR:$ptr),
2568 "strexh", "\t$success, $src, [$ptr]",
2570 def STREX : AIstrex<0b00, (outs GPR:$success), (ins GPR:$src, GPR:$ptr),
2572 "strex", "\t$success, $src, [$ptr]",
2574 def STREXD : AIstrex<0b01, (outs GPR:$success),
2575 (ins GPR:$src, GPR:$src2, GPR:$ptr),
2577 "strexd", "\t$success, $src, $src2, [$ptr]",
2581 // Clear-Exclusive is for disassembly only.
2582 def CLREX : AXI<(outs), (ins), MiscFrm, NoItinerary, "clrex",
2583 [/* For disassembly only; pattern left blank */]>,
2584 Requires<[IsARM, HasV7]> {
2585 let Inst{31-20} = 0xf57;
2586 let Inst{7-4} = 0b0001;
2589 // SWP/SWPB are deprecated in V6/V7 and for disassembly only.
2590 let mayLoad = 1 in {
2591 def SWP : AI<(outs GPR:$dst), (ins GPR:$src, GPR:$ptr), LdStExFrm, NoItinerary,
2592 "swp", "\t$dst, $src, [$ptr]",
2593 [/* For disassembly only; pattern left blank */]> {
2594 let Inst{27-23} = 0b00010;
2595 let Inst{22} = 0; // B = 0
2596 let Inst{21-20} = 0b00;
2597 let Inst{7-4} = 0b1001;
2600 def SWPB : AI<(outs GPR:$dst), (ins GPR:$src, GPR:$ptr), LdStExFrm, NoItinerary,
2601 "swpb", "\t$dst, $src, [$ptr]",
2602 [/* For disassembly only; pattern left blank */]> {
2603 let Inst{27-23} = 0b00010;
2604 let Inst{22} = 1; // B = 1
2605 let Inst{21-20} = 0b00;
2606 let Inst{7-4} = 0b1001;
2610 //===----------------------------------------------------------------------===//
2614 // __aeabi_read_tp preserves the registers r1-r3.
2616 Defs = [R0, R12, LR, CPSR] in {
2617 def TPsoft : ABXI<0b1011, (outs), (ins), IIC_Br,
2618 "bl\t__aeabi_read_tp",
2619 [(set R0, ARMthread_pointer)]>;
2622 //===----------------------------------------------------------------------===//
2623 // SJLJ Exception handling intrinsics
2624 // eh_sjlj_setjmp() is an instruction sequence to store the return
2625 // address and save #0 in R0 for the non-longjmp case.
2626 // Since by its nature we may be coming from some other function to get
2627 // here, and we're using the stack frame for the containing function to
2628 // save/restore registers, we can't keep anything live in regs across
2629 // the eh_sjlj_setjmp(), else it will almost certainly have been tromped upon
2630 // when we get here from a longjmp(). We force everthing out of registers
2631 // except for our own input by listing the relevant registers in Defs. By
2632 // doing so, we also cause the prologue/epilogue code to actively preserve
2633 // all of the callee-saved resgisters, which is exactly what we want.
2634 // A constant value is passed in $val, and we use the location as a scratch.
2636 [ R0, R1, R2, R3, R4, R5, R6, R7, R8, R9, R10, R11, R12, LR, D0,
2637 D1, D2, D3, D4, D5, D6, D7, D8, D9, D10, D11, D12, D13, D14, D15,
2638 D16, D17, D18, D19, D20, D21, D22, D23, D24, D25, D26, D27, D28, D29, D30,
2639 D31 ], hasSideEffects = 1, isBarrier = 1 in {
2640 def Int_eh_sjlj_setjmp : XI<(outs), (ins GPR:$src, GPR:$val),
2641 AddrModeNone, SizeSpecial, IndexModeNone,
2642 Pseudo, NoItinerary,
2643 "add\t$val, pc, #8\t${:comment} eh_setjmp begin\n\t"
2644 "str\t$val, [$src, #+4]\n\t"
2646 "add\tpc, pc, #0\n\t"
2647 "mov\tr0, #1 ${:comment} eh_setjmp end", "",
2648 [(set R0, (ARMeh_sjlj_setjmp GPR:$src, GPR:$val))]>,
2649 Requires<[IsARM, HasVFP2]>;
2653 [ R0, R1, R2, R3, R4, R5, R6, R7, R8, R9, R10, R11, R12, LR ],
2654 hasSideEffects = 1, isBarrier = 1 in {
2655 def Int_eh_sjlj_setjmp_nofp : XI<(outs), (ins GPR:$src, GPR:$val),
2656 AddrModeNone, SizeSpecial, IndexModeNone,
2657 Pseudo, NoItinerary,
2658 "add\t$val, pc, #8\n ${:comment} eh_setjmp begin\n\t"
2659 "str\t$val, [$src, #+4]\n\t"
2661 "add\tpc, pc, #0\n\t"
2662 "mov\tr0, #1 ${:comment} eh_setjmp end", "",
2663 [(set R0, (ARMeh_sjlj_setjmp GPR:$src, GPR:$val))]>,
2664 Requires<[IsARM, NoVFP]>;
2667 // FIXME: Non-Darwin version(s)
2668 let isBarrier = 1, hasSideEffects = 1, isTerminator = 1,
2669 Defs = [ R7, LR, SP ] in {
2670 def Int_eh_sjlj_longjmp : XI<(outs), (ins GPR:$src, GPR:$scratch),
2671 AddrModeNone, SizeSpecial, IndexModeNone,
2672 Pseudo, NoItinerary,
2673 "ldr\tsp, [$src, #8]\n\t"
2674 "ldr\t$scratch, [$src, #4]\n\t"
2675 "ldr\tr7, [$src]\n\t"
2677 [(ARMeh_sjlj_longjmp GPR:$src, GPR:$scratch)]>,
2678 Requires<[IsARM, IsDarwin]>;
2681 //===----------------------------------------------------------------------===//
2682 // Non-Instruction Patterns
2685 // Large immediate handling.
2687 // Two piece so_imms.
2688 let isReMaterializable = 1 in
2689 def MOVi2pieces : AI1x2<(outs GPR:$dst), (ins so_imm2part:$src),
2691 "mov", "\t$dst, $src",
2692 [(set GPR:$dst, so_imm2part:$src)]>,
2693 Requires<[IsARM, NoV6T2]>;
2695 def : ARMPat<(or GPR:$LHS, so_imm2part:$RHS),
2696 (ORRri (ORRri GPR:$LHS, (so_imm2part_1 imm:$RHS)),
2697 (so_imm2part_2 imm:$RHS))>;
2698 def : ARMPat<(xor GPR:$LHS, so_imm2part:$RHS),
2699 (EORri (EORri GPR:$LHS, (so_imm2part_1 imm:$RHS)),
2700 (so_imm2part_2 imm:$RHS))>;
2701 def : ARMPat<(add GPR:$LHS, so_imm2part:$RHS),
2702 (ADDri (ADDri GPR:$LHS, (so_imm2part_1 imm:$RHS)),
2703 (so_imm2part_2 imm:$RHS))>;
2704 def : ARMPat<(add GPR:$LHS, so_neg_imm2part:$RHS),
2705 (SUBri (SUBri GPR:$LHS, (so_neg_imm2part_1 imm:$RHS)),
2706 (so_neg_imm2part_2 imm:$RHS))>;
2708 // 32-bit immediate using movw + movt.
2709 // This is a single pseudo instruction, the benefit is that it can be remat'd
2710 // as a single unit instead of having to handle reg inputs.
2711 // FIXME: Remove this when we can do generalized remat.
2712 let isReMaterializable = 1 in
2713 def MOVi32imm : AI1x2<(outs GPR:$dst), (ins i32imm:$src), Pseudo, IIC_iMOVi,
2714 "movw", "\t$dst, ${src:lo16}\n\tmovt${p}\t$dst, ${src:hi16}",
2715 [(set GPR:$dst, (i32 imm:$src))]>,
2716 Requires<[IsARM, HasV6T2]>;
2718 // ConstantPool, GlobalAddress, and JumpTable
2719 def : ARMPat<(ARMWrapper tglobaladdr :$dst), (LEApcrel tglobaladdr :$dst)>,
2720 Requires<[IsARM, DontUseMovt]>;
2721 def : ARMPat<(ARMWrapper tconstpool :$dst), (LEApcrel tconstpool :$dst)>;
2722 def : ARMPat<(ARMWrapper tglobaladdr :$dst), (MOVi32imm tglobaladdr :$dst)>,
2723 Requires<[IsARM, UseMovt]>;
2724 def : ARMPat<(ARMWrapperJT tjumptable:$dst, imm:$id),
2725 (LEApcrelJT tjumptable:$dst, imm:$id)>;
2727 // TODO: add,sub,and, 3-instr forms?
2730 def : ARMPat<(ARMtcret tcGPR:$dst),
2731 (TCRETURNri tcGPR:$dst)>, Requires<[IsDarwin]>;
2733 def : ARMPat<(ARMtcret (i32 tglobaladdr:$dst)),
2734 (TCRETURNdi texternalsym:$dst)>, Requires<[IsDarwin]>;
2736 def : ARMPat<(ARMtcret (i32 texternalsym:$dst)),
2737 (TCRETURNdi texternalsym:$dst)>, Requires<[IsDarwin]>;
2739 def : ARMPat<(ARMtcret tcGPR:$dst),
2740 (TCRETURNriND tcGPR:$dst)>, Requires<[IsNotDarwin]>;
2742 def : ARMPat<(ARMtcret (i32 tglobaladdr:$dst)),
2743 (TCRETURNdiND texternalsym:$dst)>, Requires<[IsNotDarwin]>;
2745 def : ARMPat<(ARMtcret (i32 texternalsym:$dst)),
2746 (TCRETURNdiND texternalsym:$dst)>, Requires<[IsNotDarwin]>;
2749 def : ARMPat<(ARMcall texternalsym:$func), (BL texternalsym:$func)>,
2750 Requires<[IsARM, IsNotDarwin]>;
2751 def : ARMPat<(ARMcall texternalsym:$func), (BLr9 texternalsym:$func)>,
2752 Requires<[IsARM, IsDarwin]>;
2754 // zextload i1 -> zextload i8
2755 def : ARMPat<(zextloadi1 addrmode2:$addr), (LDRB addrmode2:$addr)>;
2757 // extload -> zextload
2758 def : ARMPat<(extloadi1 addrmode2:$addr), (LDRB addrmode2:$addr)>;
2759 def : ARMPat<(extloadi8 addrmode2:$addr), (LDRB addrmode2:$addr)>;
2760 def : ARMPat<(extloadi16 addrmode3:$addr), (LDRH addrmode3:$addr)>;
2762 def : ARMPat<(extloadi8 addrmodepc:$addr), (PICLDRB addrmodepc:$addr)>;
2763 def : ARMPat<(extloadi16 addrmodepc:$addr), (PICLDRH addrmodepc:$addr)>;
2766 def : ARMV5TEPat<(mul (sra (shl GPR:$a, (i32 16)), (i32 16)),
2767 (sra (shl GPR:$b, (i32 16)), (i32 16))),
2768 (SMULBB GPR:$a, GPR:$b)>;
2769 def : ARMV5TEPat<(mul sext_16_node:$a, sext_16_node:$b),
2770 (SMULBB GPR:$a, GPR:$b)>;
2771 def : ARMV5TEPat<(mul (sra (shl GPR:$a, (i32 16)), (i32 16)),
2772 (sra GPR:$b, (i32 16))),
2773 (SMULBT GPR:$a, GPR:$b)>;
2774 def : ARMV5TEPat<(mul sext_16_node:$a, (sra GPR:$b, (i32 16))),
2775 (SMULBT GPR:$a, GPR:$b)>;
2776 def : ARMV5TEPat<(mul (sra GPR:$a, (i32 16)),
2777 (sra (shl GPR:$b, (i32 16)), (i32 16))),
2778 (SMULTB GPR:$a, GPR:$b)>;
2779 def : ARMV5TEPat<(mul (sra GPR:$a, (i32 16)), sext_16_node:$b),
2780 (SMULTB GPR:$a, GPR:$b)>;
2781 def : ARMV5TEPat<(sra (mul GPR:$a, (sra (shl GPR:$b, (i32 16)), (i32 16))),
2783 (SMULWB GPR:$a, GPR:$b)>;
2784 def : ARMV5TEPat<(sra (mul GPR:$a, sext_16_node:$b), (i32 16)),
2785 (SMULWB GPR:$a, GPR:$b)>;
2787 def : ARMV5TEPat<(add GPR:$acc,
2788 (mul (sra (shl GPR:$a, (i32 16)), (i32 16)),
2789 (sra (shl GPR:$b, (i32 16)), (i32 16)))),
2790 (SMLABB GPR:$a, GPR:$b, GPR:$acc)>;
2791 def : ARMV5TEPat<(add GPR:$acc,
2792 (mul sext_16_node:$a, sext_16_node:$b)),
2793 (SMLABB GPR:$a, GPR:$b, GPR:$acc)>;
2794 def : ARMV5TEPat<(add GPR:$acc,
2795 (mul (sra (shl GPR:$a, (i32 16)), (i32 16)),
2796 (sra GPR:$b, (i32 16)))),
2797 (SMLABT GPR:$a, GPR:$b, GPR:$acc)>;
2798 def : ARMV5TEPat<(add GPR:$acc,
2799 (mul sext_16_node:$a, (sra GPR:$b, (i32 16)))),
2800 (SMLABT GPR:$a, GPR:$b, GPR:$acc)>;
2801 def : ARMV5TEPat<(add GPR:$acc,
2802 (mul (sra GPR:$a, (i32 16)),
2803 (sra (shl GPR:$b, (i32 16)), (i32 16)))),
2804 (SMLATB GPR:$a, GPR:$b, GPR:$acc)>;
2805 def : ARMV5TEPat<(add GPR:$acc,
2806 (mul (sra GPR:$a, (i32 16)), sext_16_node:$b)),
2807 (SMLATB GPR:$a, GPR:$b, GPR:$acc)>;
2808 def : ARMV5TEPat<(add GPR:$acc,
2809 (sra (mul GPR:$a, (sra (shl GPR:$b, (i32 16)), (i32 16))),
2811 (SMLAWB GPR:$a, GPR:$b, GPR:$acc)>;
2812 def : ARMV5TEPat<(add GPR:$acc,
2813 (sra (mul GPR:$a, sext_16_node:$b), (i32 16))),
2814 (SMLAWB GPR:$a, GPR:$b, GPR:$acc)>;
2816 //===----------------------------------------------------------------------===//
2820 include "ARMInstrThumb.td"
2822 //===----------------------------------------------------------------------===//
2826 include "ARMInstrThumb2.td"
2828 //===----------------------------------------------------------------------===//
2829 // Floating Point Support
2832 include "ARMInstrVFP.td"
2834 //===----------------------------------------------------------------------===//
2835 // Advanced SIMD (NEON) Support
2838 include "ARMInstrNEON.td"
2840 //===----------------------------------------------------------------------===//
2841 // Coprocessor Instructions. For disassembly only.
2844 def CDP : ABI<0b1110, (outs), (ins nohash_imm:$cop, i32imm:$opc1,
2845 nohash_imm:$CRd, nohash_imm:$CRn, nohash_imm:$CRm, i32imm:$opc2),
2846 NoItinerary, "cdp", "\tp$cop, $opc1, cr$CRd, cr$CRn, cr$CRm, $opc2",
2847 [/* For disassembly only; pattern left blank */]> {
2851 def CDP2 : ABXI<0b1110, (outs), (ins nohash_imm:$cop, i32imm:$opc1,
2852 nohash_imm:$CRd, nohash_imm:$CRn, nohash_imm:$CRm, i32imm:$opc2),
2853 NoItinerary, "cdp2\tp$cop, $opc1, cr$CRd, cr$CRn, cr$CRm, $opc2",
2854 [/* For disassembly only; pattern left blank */]> {
2855 let Inst{31-28} = 0b1111;
2859 class ACI<dag oops, dag iops, string opc, string asm>
2860 : I<oops, iops, AddrModeNone, Size4Bytes, IndexModeNone, BrFrm, NoItinerary,
2861 opc, asm, "", [/* For disassembly only; pattern left blank */]> {
2862 let Inst{27-25} = 0b110;
2865 multiclass LdStCop<bits<4> op31_28, bit load, string opc> {
2867 def _OFFSET : ACI<(outs),
2868 (ins nohash_imm:$cop, nohash_imm:$CRd, addrmode2:$addr),
2869 opc, "\tp$cop, cr$CRd, $addr"> {
2870 let Inst{31-28} = op31_28;
2871 let Inst{24} = 1; // P = 1
2872 let Inst{21} = 0; // W = 0
2873 let Inst{22} = 0; // D = 0
2874 let Inst{20} = load;
2877 def _PRE : ACI<(outs),
2878 (ins nohash_imm:$cop, nohash_imm:$CRd, addrmode2:$addr),
2879 opc, "\tp$cop, cr$CRd, $addr!"> {
2880 let Inst{31-28} = op31_28;
2881 let Inst{24} = 1; // P = 1
2882 let Inst{21} = 1; // W = 1
2883 let Inst{22} = 0; // D = 0
2884 let Inst{20} = load;
2887 def _POST : ACI<(outs),
2888 (ins nohash_imm:$cop, nohash_imm:$CRd, GPR:$base, am2offset:$offset),
2889 opc, "\tp$cop, cr$CRd, [$base], $offset"> {
2890 let Inst{31-28} = op31_28;
2891 let Inst{24} = 0; // P = 0
2892 let Inst{21} = 1; // W = 1
2893 let Inst{22} = 0; // D = 0
2894 let Inst{20} = load;
2897 def _OPTION : ACI<(outs),
2898 (ins nohash_imm:$cop, nohash_imm:$CRd, GPR:$base, i32imm:$option),
2899 opc, "\tp$cop, cr$CRd, [$base], $option"> {
2900 let Inst{31-28} = op31_28;
2901 let Inst{24} = 0; // P = 0
2902 let Inst{23} = 1; // U = 1
2903 let Inst{21} = 0; // W = 0
2904 let Inst{22} = 0; // D = 0
2905 let Inst{20} = load;
2908 def L_OFFSET : ACI<(outs),
2909 (ins nohash_imm:$cop, nohash_imm:$CRd, addrmode2:$addr),
2910 !strconcat(opc, "l"), "\tp$cop, cr$CRd, $addr"> {
2911 let Inst{31-28} = op31_28;
2912 let Inst{24} = 1; // P = 1
2913 let Inst{21} = 0; // W = 0
2914 let Inst{22} = 1; // D = 1
2915 let Inst{20} = load;
2918 def L_PRE : ACI<(outs),
2919 (ins nohash_imm:$cop, nohash_imm:$CRd, addrmode2:$addr),
2920 !strconcat(opc, "l"), "\tp$cop, cr$CRd, $addr!"> {
2921 let Inst{31-28} = op31_28;
2922 let Inst{24} = 1; // P = 1
2923 let Inst{21} = 1; // W = 1
2924 let Inst{22} = 1; // D = 1
2925 let Inst{20} = load;
2928 def L_POST : ACI<(outs),
2929 (ins nohash_imm:$cop, nohash_imm:$CRd, GPR:$base, am2offset:$offset),
2930 !strconcat(opc, "l"), "\tp$cop, cr$CRd, [$base], $offset"> {
2931 let Inst{31-28} = op31_28;
2932 let Inst{24} = 0; // P = 0
2933 let Inst{21} = 1; // W = 1
2934 let Inst{22} = 1; // D = 1
2935 let Inst{20} = load;
2938 def L_OPTION : ACI<(outs),
2939 (ins nohash_imm:$cop, nohash_imm:$CRd, GPR:$base, nohash_imm:$option),
2940 !strconcat(opc, "l"), "\tp$cop, cr$CRd, [$base], $option"> {
2941 let Inst{31-28} = op31_28;
2942 let Inst{24} = 0; // P = 0
2943 let Inst{23} = 1; // U = 1
2944 let Inst{21} = 0; // W = 0
2945 let Inst{22} = 1; // D = 1
2946 let Inst{20} = load;
2950 defm LDC : LdStCop<{?,?,?,?}, 1, "ldc">;
2951 defm LDC2 : LdStCop<0b1111, 1, "ldc2">;
2952 defm STC : LdStCop<{?,?,?,?}, 0, "stc">;
2953 defm STC2 : LdStCop<0b1111, 0, "stc2">;
2955 def MCR : ABI<0b1110, (outs), (ins nohash_imm:$cop, i32imm:$opc1,
2956 GPR:$Rt, nohash_imm:$CRn, nohash_imm:$CRm, i32imm:$opc2),
2957 NoItinerary, "mcr", "\tp$cop, $opc1, $Rt, cr$CRn, cr$CRm, $opc2",
2958 [/* For disassembly only; pattern left blank */]> {
2963 def MCR2 : ABXI<0b1110, (outs), (ins nohash_imm:$cop, i32imm:$opc1,
2964 GPR:$Rt, nohash_imm:$CRn, nohash_imm:$CRm, i32imm:$opc2),
2965 NoItinerary, "mcr2\tp$cop, $opc1, $Rt, cr$CRn, cr$CRm, $opc2",
2966 [/* For disassembly only; pattern left blank */]> {
2967 let Inst{31-28} = 0b1111;
2972 def MRC : ABI<0b1110, (outs), (ins nohash_imm:$cop, i32imm:$opc1,
2973 GPR:$Rt, nohash_imm:$CRn, nohash_imm:$CRm, i32imm:$opc2),
2974 NoItinerary, "mrc", "\tp$cop, $opc1, $Rt, cr$CRn, cr$CRm, $opc2",
2975 [/* For disassembly only; pattern left blank */]> {
2980 def MRC2 : ABXI<0b1110, (outs), (ins nohash_imm:$cop, i32imm:$opc1,
2981 GPR:$Rt, nohash_imm:$CRn, nohash_imm:$CRm, i32imm:$opc2),
2982 NoItinerary, "mrc2\tp$cop, $opc1, $Rt, cr$CRn, cr$CRm, $opc2",
2983 [/* For disassembly only; pattern left blank */]> {
2984 let Inst{31-28} = 0b1111;
2989 def MCRR : ABI<0b1100, (outs), (ins nohash_imm:$cop, i32imm:$opc,
2990 GPR:$Rt, GPR:$Rt2, nohash_imm:$CRm),
2991 NoItinerary, "mcrr", "\tp$cop, $opc, $Rt, $Rt2, cr$CRm",
2992 [/* For disassembly only; pattern left blank */]> {
2993 let Inst{23-20} = 0b0100;
2996 def MCRR2 : ABXI<0b1100, (outs), (ins nohash_imm:$cop, i32imm:$opc,
2997 GPR:$Rt, GPR:$Rt2, nohash_imm:$CRm),
2998 NoItinerary, "mcrr2\tp$cop, $opc, $Rt, $Rt2, cr$CRm",
2999 [/* For disassembly only; pattern left blank */]> {
3000 let Inst{31-28} = 0b1111;
3001 let Inst{23-20} = 0b0100;
3004 def MRRC : ABI<0b1100, (outs), (ins nohash_imm:$cop, i32imm:$opc,
3005 GPR:$Rt, GPR:$Rt2, nohash_imm:$CRm),
3006 NoItinerary, "mrrc", "\tp$cop, $opc, $Rt, $Rt2, cr$CRm",
3007 [/* For disassembly only; pattern left blank */]> {
3008 let Inst{23-20} = 0b0101;
3011 def MRRC2 : ABXI<0b1100, (outs), (ins nohash_imm:$cop, i32imm:$opc,
3012 GPR:$Rt, GPR:$Rt2, nohash_imm:$CRm),
3013 NoItinerary, "mrrc2\tp$cop, $opc, $Rt, $Rt2, cr$CRm",
3014 [/* For disassembly only; pattern left blank */]> {
3015 let Inst{31-28} = 0b1111;
3016 let Inst{23-20} = 0b0101;
3019 //===----------------------------------------------------------------------===//
3020 // Move between special register and ARM core register -- for disassembly only
3023 def MRS : ABI<0b0001,(outs GPR:$dst),(ins), NoItinerary, "mrs", "\t$dst, cpsr",
3024 [/* For disassembly only; pattern left blank */]> {
3025 let Inst{23-20} = 0b0000;
3026 let Inst{7-4} = 0b0000;
3029 def MRSsys : ABI<0b0001,(outs GPR:$dst),(ins), NoItinerary,"mrs","\t$dst, spsr",
3030 [/* For disassembly only; pattern left blank */]> {
3031 let Inst{23-20} = 0b0100;
3032 let Inst{7-4} = 0b0000;
3035 def MSR : ABI<0b0001, (outs), (ins GPR:$src, msr_mask:$mask), NoItinerary,
3036 "msr", "\tcpsr$mask, $src",
3037 [/* For disassembly only; pattern left blank */]> {
3038 let Inst{23-20} = 0b0010;
3039 let Inst{7-4} = 0b0000;
3042 def MSRi : ABI<0b0011, (outs), (ins so_imm:$a, msr_mask:$mask), NoItinerary,
3043 "msr", "\tcpsr$mask, $a",
3044 [/* For disassembly only; pattern left blank */]> {
3045 let Inst{23-20} = 0b0010;
3046 let Inst{7-4} = 0b0000;
3049 def MSRsys : ABI<0b0001, (outs), (ins GPR:$src, msr_mask:$mask), NoItinerary,
3050 "msr", "\tspsr$mask, $src",
3051 [/* For disassembly only; pattern left blank */]> {
3052 let Inst{23-20} = 0b0110;
3053 let Inst{7-4} = 0b0000;
3056 def MSRsysi : ABI<0b0011, (outs), (ins so_imm:$a, msr_mask:$mask), NoItinerary,
3057 "msr", "\tspsr$mask, $a",
3058 [/* For disassembly only; pattern left blank */]> {
3059 let Inst{23-20} = 0b0110;
3060 let Inst{7-4} = 0b0000;