1 //===- ARMInstrInfo.td - Target Description for ARM Target -*- tablegen -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file describes the ARM instructions in TableGen format.
12 //===----------------------------------------------------------------------===//
14 //===----------------------------------------------------------------------===//
15 // ARM specific DAG Nodes.
19 def SDT_ARMCallSeqStart : SDCallSeqStart<[ SDTCisVT<0, i32> ]>;
20 def SDT_ARMCallSeqEnd : SDCallSeqEnd<[ SDTCisVT<0, i32>, SDTCisVT<1, i32> ]>;
21 def SDT_ARMStructByVal : SDTypeProfile<0, 4,
22 [SDTCisVT<0, i32>, SDTCisVT<1, i32>,
23 SDTCisVT<2, i32>, SDTCisVT<3, i32>]>;
25 def SDT_ARMSaveCallPC : SDTypeProfile<0, 1, []>;
27 def SDT_ARMcall : SDTypeProfile<0, -1, [SDTCisPtrTy<0>]>;
29 def SDT_ARMCMov : SDTypeProfile<1, 3,
30 [SDTCisSameAs<0, 1>, SDTCisSameAs<0, 2>,
33 def SDT_ARMBrcond : SDTypeProfile<0, 2,
34 [SDTCisVT<0, OtherVT>, SDTCisVT<1, i32>]>;
36 def SDT_ARMBrJT : SDTypeProfile<0, 2,
37 [SDTCisPtrTy<0>, SDTCisVT<1, i32>]>;
39 def SDT_ARMBr2JT : SDTypeProfile<0, 3,
40 [SDTCisPtrTy<0>, SDTCisVT<1, i32>,
43 def SDT_ARMBCC_i64 : SDTypeProfile<0, 6,
45 SDTCisVT<1, i32>, SDTCisVT<2, i32>,
46 SDTCisVT<3, i32>, SDTCisVT<4, i32>,
47 SDTCisVT<5, OtherVT>]>;
49 def SDT_ARMAnd : SDTypeProfile<1, 2,
50 [SDTCisVT<0, i32>, SDTCisVT<1, i32>,
53 def SDT_ARMCmp : SDTypeProfile<0, 2, [SDTCisSameAs<0, 1>]>;
55 def SDT_ARMPICAdd : SDTypeProfile<1, 2, [SDTCisSameAs<0, 1>,
56 SDTCisPtrTy<1>, SDTCisVT<2, i32>]>;
58 def SDT_ARMThreadPointer : SDTypeProfile<1, 0, [SDTCisPtrTy<0>]>;
59 def SDT_ARMEH_SJLJ_Setjmp : SDTypeProfile<1, 2, [SDTCisInt<0>, SDTCisPtrTy<1>,
61 def SDT_ARMEH_SJLJ_Longjmp: SDTypeProfile<0, 2, [SDTCisPtrTy<0>, SDTCisInt<1>]>;
63 def SDT_ARMMEMBARRIER : SDTypeProfile<0, 1, [SDTCisInt<0>]>;
65 def SDT_ARMPREFETCH : SDTypeProfile<0, 3, [SDTCisPtrTy<0>, SDTCisSameAs<1, 2>,
68 def SDT_ARMTCRET : SDTypeProfile<0, 1, [SDTCisPtrTy<0>]>;
70 def SDT_ARMBFI : SDTypeProfile<1, 3, [SDTCisVT<0, i32>, SDTCisVT<1, i32>,
71 SDTCisVT<2, i32>, SDTCisVT<3, i32>]>;
73 def SDT_ARMVMAXNM : SDTypeProfile<1, 2, [SDTCisFP<0>, SDTCisFP<1>, SDTCisFP<2>]>;
74 def SDT_ARMVMINNM : SDTypeProfile<1, 2, [SDTCisFP<0>, SDTCisFP<1>, SDTCisFP<2>]>;
76 def SDT_ARMMCOPY : SDTypeProfile<2, 3, [SDTCisVT<0, i32>, SDTCisVT<1, i32>,
77 SDTCisVT<2, i32>, SDTCisVT<3, i32>,
80 def SDTBinaryArithWithFlags : SDTypeProfile<2, 2,
83 SDTCisInt<0>, SDTCisVT<1, i32>]>;
85 // SDTBinaryArithWithFlagsInOut - RES1, CPSR = op LHS, RHS, CPSR
86 def SDTBinaryArithWithFlagsInOut : SDTypeProfile<2, 3,
93 def SDT_ARM64bitmlal : SDTypeProfile<2,4, [ SDTCisVT<0, i32>, SDTCisVT<1, i32>,
94 SDTCisVT<2, i32>, SDTCisVT<3, i32>,
95 SDTCisVT<4, i32>, SDTCisVT<5, i32> ] >;
96 def ARMUmlal : SDNode<"ARMISD::UMLAL", SDT_ARM64bitmlal>;
97 def ARMSmlal : SDNode<"ARMISD::SMLAL", SDT_ARM64bitmlal>;
100 def ARMWrapper : SDNode<"ARMISD::Wrapper", SDTIntUnaryOp>;
101 def ARMWrapperPIC : SDNode<"ARMISD::WrapperPIC", SDTIntUnaryOp>;
102 def ARMWrapperJT : SDNode<"ARMISD::WrapperJT", SDTIntUnaryOp>;
104 def ARMcallseq_start : SDNode<"ISD::CALLSEQ_START", SDT_ARMCallSeqStart,
105 [SDNPHasChain, SDNPSideEffect, SDNPOutGlue]>;
106 def ARMcallseq_end : SDNode<"ISD::CALLSEQ_END", SDT_ARMCallSeqEnd,
107 [SDNPHasChain, SDNPSideEffect,
108 SDNPOptInGlue, SDNPOutGlue]>;
109 def ARMcopystructbyval : SDNode<"ARMISD::COPY_STRUCT_BYVAL" ,
111 [SDNPHasChain, SDNPInGlue, SDNPOutGlue,
112 SDNPMayStore, SDNPMayLoad]>;
114 def ARMcall : SDNode<"ARMISD::CALL", SDT_ARMcall,
115 [SDNPHasChain, SDNPOptInGlue, SDNPOutGlue,
117 def ARMcall_pred : SDNode<"ARMISD::CALL_PRED", SDT_ARMcall,
118 [SDNPHasChain, SDNPOptInGlue, SDNPOutGlue,
120 def ARMcall_nolink : SDNode<"ARMISD::CALL_NOLINK", SDT_ARMcall,
121 [SDNPHasChain, SDNPOptInGlue, SDNPOutGlue,
124 def ARMretflag : SDNode<"ARMISD::RET_FLAG", SDTNone,
125 [SDNPHasChain, SDNPOptInGlue, SDNPVariadic]>;
126 def ARMintretflag : SDNode<"ARMISD::INTRET_FLAG", SDT_ARMcall,
127 [SDNPHasChain, SDNPOptInGlue, SDNPVariadic]>;
128 def ARMcmov : SDNode<"ARMISD::CMOV", SDT_ARMCMov,
131 def ARMbrcond : SDNode<"ARMISD::BRCOND", SDT_ARMBrcond,
132 [SDNPHasChain, SDNPInGlue, SDNPOutGlue]>;
134 def ARMbrjt : SDNode<"ARMISD::BR_JT", SDT_ARMBrJT,
136 def ARMbr2jt : SDNode<"ARMISD::BR2_JT", SDT_ARMBr2JT,
139 def ARMBcci64 : SDNode<"ARMISD::BCC_i64", SDT_ARMBCC_i64,
142 def ARMcmp : SDNode<"ARMISD::CMP", SDT_ARMCmp,
145 def ARMcmn : SDNode<"ARMISD::CMN", SDT_ARMCmp,
148 def ARMcmpZ : SDNode<"ARMISD::CMPZ", SDT_ARMCmp,
149 [SDNPOutGlue, SDNPCommutative]>;
151 def ARMpic_add : SDNode<"ARMISD::PIC_ADD", SDT_ARMPICAdd>;
153 def ARMsrl_flag : SDNode<"ARMISD::SRL_FLAG", SDTIntUnaryOp, [SDNPOutGlue]>;
154 def ARMsra_flag : SDNode<"ARMISD::SRA_FLAG", SDTIntUnaryOp, [SDNPOutGlue]>;
155 def ARMrrx : SDNode<"ARMISD::RRX" , SDTIntUnaryOp, [SDNPInGlue ]>;
157 def ARMaddc : SDNode<"ARMISD::ADDC", SDTBinaryArithWithFlags,
159 def ARMsubc : SDNode<"ARMISD::SUBC", SDTBinaryArithWithFlags>;
160 def ARMadde : SDNode<"ARMISD::ADDE", SDTBinaryArithWithFlagsInOut>;
161 def ARMsube : SDNode<"ARMISD::SUBE", SDTBinaryArithWithFlagsInOut>;
163 def ARMthread_pointer: SDNode<"ARMISD::THREAD_POINTER", SDT_ARMThreadPointer>;
164 def ARMeh_sjlj_setjmp: SDNode<"ARMISD::EH_SJLJ_SETJMP",
165 SDT_ARMEH_SJLJ_Setjmp,
166 [SDNPHasChain, SDNPSideEffect]>;
167 def ARMeh_sjlj_longjmp: SDNode<"ARMISD::EH_SJLJ_LONGJMP",
168 SDT_ARMEH_SJLJ_Longjmp,
169 [SDNPHasChain, SDNPSideEffect]>;
171 def ARMMemBarrierMCR : SDNode<"ARMISD::MEMBARRIER_MCR", SDT_ARMMEMBARRIER,
172 [SDNPHasChain, SDNPSideEffect]>;
173 def ARMPreload : SDNode<"ARMISD::PRELOAD", SDT_ARMPREFETCH,
174 [SDNPHasChain, SDNPMayLoad, SDNPMayStore]>;
176 def ARMrbit : SDNode<"ARMISD::RBIT", SDTIntUnaryOp>;
178 def ARMtcret : SDNode<"ARMISD::TC_RETURN", SDT_ARMTCRET,
179 [SDNPHasChain, SDNPOptInGlue, SDNPVariadic]>;
181 def ARMbfi : SDNode<"ARMISD::BFI", SDT_ARMBFI>;
183 def ARMvmaxnm : SDNode<"ARMISD::VMAXNM", SDT_ARMVMAXNM, []>;
184 def ARMvminnm : SDNode<"ARMISD::VMINNM", SDT_ARMVMINNM, []>;
186 def ARMmcopy : SDNode<"ARMISD::MCOPY", SDT_ARMMCOPY,
187 [SDNPHasChain, SDNPInGlue, SDNPOutGlue,
188 SDNPMayStore, SDNPMayLoad]>;
190 //===----------------------------------------------------------------------===//
191 // ARM Instruction Predicate Definitions.
193 def HasV4T : Predicate<"Subtarget->hasV4TOps()">,
194 AssemblerPredicate<"HasV4TOps", "armv4t">;
195 def NoV4T : Predicate<"!Subtarget->hasV4TOps()">;
196 def HasV5T : Predicate<"Subtarget->hasV5TOps()">,
197 AssemblerPredicate<"HasV5TOps", "armv5t">;
198 def HasV5TE : Predicate<"Subtarget->hasV5TEOps()">,
199 AssemblerPredicate<"HasV5TEOps", "armv5te">;
200 def HasV6 : Predicate<"Subtarget->hasV6Ops()">,
201 AssemblerPredicate<"HasV6Ops", "armv6">;
202 def NoV6 : Predicate<"!Subtarget->hasV6Ops()">;
203 def HasV6M : Predicate<"Subtarget->hasV6MOps()">,
204 AssemblerPredicate<"HasV6MOps",
205 "armv6m or armv6t2">;
206 def HasV6T2 : Predicate<"Subtarget->hasV6T2Ops()">,
207 AssemblerPredicate<"HasV6T2Ops", "armv6t2">;
208 def NoV6T2 : Predicate<"!Subtarget->hasV6T2Ops()">;
209 def HasV6K : Predicate<"Subtarget->hasV6KOps()">,
210 AssemblerPredicate<"HasV6KOps", "armv6k">;
211 def NoV6K : Predicate<"!Subtarget->hasV6KOps()">;
212 def HasV7 : Predicate<"Subtarget->hasV7Ops()">,
213 AssemblerPredicate<"HasV7Ops", "armv7">;
214 def HasV8 : Predicate<"Subtarget->hasV8Ops()">,
215 AssemblerPredicate<"HasV8Ops", "armv8">;
216 def PreV8 : Predicate<"!Subtarget->hasV8Ops()">,
217 AssemblerPredicate<"!HasV8Ops", "armv7 or earlier">;
218 def HasV8_1a : Predicate<"Subtarget->hasV8_1aOps()">,
219 AssemblerPredicate<"HasV8_1aOps", "armv8.1a">;
220 def NoVFP : Predicate<"!Subtarget->hasVFP2()">;
221 def HasVFP2 : Predicate<"Subtarget->hasVFP2()">,
222 AssemblerPredicate<"FeatureVFP2", "VFP2">;
223 def HasVFP3 : Predicate<"Subtarget->hasVFP3()">,
224 AssemblerPredicate<"FeatureVFP3", "VFP3">;
225 def HasVFP4 : Predicate<"Subtarget->hasVFP4()">,
226 AssemblerPredicate<"FeatureVFP4", "VFP4">;
227 def HasDPVFP : Predicate<"!Subtarget->isFPOnlySP()">,
228 AssemblerPredicate<"!FeatureVFPOnlySP",
229 "double precision VFP">;
230 def HasFPARMv8 : Predicate<"Subtarget->hasFPARMv8()">,
231 AssemblerPredicate<"FeatureFPARMv8", "FPARMv8">;
232 def HasNEON : Predicate<"Subtarget->hasNEON()">,
233 AssemblerPredicate<"FeatureNEON", "NEON">;
234 def HasCrypto : Predicate<"Subtarget->hasCrypto()">,
235 AssemblerPredicate<"FeatureCrypto", "crypto">;
236 def HasCRC : Predicate<"Subtarget->hasCRC()">,
237 AssemblerPredicate<"FeatureCRC", "crc">;
238 def HasFP16 : Predicate<"Subtarget->hasFP16()">,
239 AssemblerPredicate<"FeatureFP16","half-float">;
240 def HasDivide : Predicate<"Subtarget->hasDivide()">,
241 AssemblerPredicate<"FeatureHWDiv", "divide in THUMB">;
242 def HasDivideInARM : Predicate<"Subtarget->hasDivideInARMMode()">,
243 AssemblerPredicate<"FeatureHWDivARM", "divide in ARM">;
244 def HasT2ExtractPack : Predicate<"Subtarget->hasT2ExtractPack()">,
245 AssemblerPredicate<"FeatureT2XtPk",
247 def HasThumb2DSP : Predicate<"Subtarget->hasThumb2DSP()">,
248 AssemblerPredicate<"FeatureDSPThumb2",
250 def HasDB : Predicate<"Subtarget->hasDataBarrier()">,
251 AssemblerPredicate<"FeatureDB",
253 def HasMP : Predicate<"Subtarget->hasMPExtension()">,
254 AssemblerPredicate<"FeatureMP",
256 def HasVirtualization: Predicate<"false">,
257 AssemblerPredicate<"FeatureVirtualization",
258 "virtualization-extensions">;
259 def HasTrustZone : Predicate<"Subtarget->hasTrustZone()">,
260 AssemblerPredicate<"FeatureTrustZone",
262 def HasZCZ : Predicate<"Subtarget->hasZeroCycleZeroing()">;
263 def UseNEONForFP : Predicate<"Subtarget->useNEONForSinglePrecisionFP()">;
264 def DontUseNEONForFP : Predicate<"!Subtarget->useNEONForSinglePrecisionFP()">;
265 def IsThumb : Predicate<"Subtarget->isThumb()">,
266 AssemblerPredicate<"ModeThumb", "thumb">;
267 def IsThumb1Only : Predicate<"Subtarget->isThumb1Only()">;
268 def IsThumb2 : Predicate<"Subtarget->isThumb2()">,
269 AssemblerPredicate<"ModeThumb,FeatureThumb2",
271 def IsMClass : Predicate<"Subtarget->isMClass()">,
272 AssemblerPredicate<"FeatureMClass", "armv*m">;
273 def IsNotMClass : Predicate<"!Subtarget->isMClass()">,
274 AssemblerPredicate<"!FeatureMClass",
276 def IsARM : Predicate<"!Subtarget->isThumb()">,
277 AssemblerPredicate<"!ModeThumb", "arm-mode">;
278 def IsMachO : Predicate<"Subtarget->isTargetMachO()">;
279 def IsNotMachO : Predicate<"!Subtarget->isTargetMachO()">;
280 def IsNaCl : Predicate<"Subtarget->isTargetNaCl()">;
281 def UseNaClTrap : Predicate<"Subtarget->useNaClTrap()">,
282 AssemblerPredicate<"FeatureNaClTrap", "NaCl">;
283 def DontUseNaClTrap : Predicate<"!Subtarget->useNaClTrap()">;
285 // FIXME: Eventually this will be just "hasV6T2Ops".
286 def UseMovt : Predicate<"Subtarget->useMovt(*MF)">;
287 def DontUseMovt : Predicate<"!Subtarget->useMovt(*MF)">;
288 def UseFPVMLx : Predicate<"Subtarget->useFPVMLx()">;
289 def UseMulOps : Predicate<"Subtarget->useMulOps()">;
291 // Prefer fused MAC for fp mul + add over fp VMLA / VMLS if they are available.
292 // But only select them if more precision in FP computation is allowed.
293 // Do not use them for Darwin platforms.
294 def UseFusedMAC : Predicate<"(TM.Options.AllowFPOpFusion =="
295 " FPOpFusion::Fast && "
296 " Subtarget->hasVFP4()) && "
297 "!Subtarget->isTargetDarwin()">;
298 def DontUseFusedMAC : Predicate<"!(TM.Options.AllowFPOpFusion =="
299 " FPOpFusion::Fast &&"
300 " Subtarget->hasVFP4()) || "
301 "Subtarget->isTargetDarwin()">;
303 // VGETLNi32 is microcoded on Swift - prefer VMOV.
304 def HasFastVGETLNi32 : Predicate<"!Subtarget->isSwift()">;
305 def HasSlowVGETLNi32 : Predicate<"Subtarget->isSwift()">;
307 // VDUP.32 is microcoded on Swift - prefer VMOV.
308 def HasFastVDUP32 : Predicate<"!Subtarget->isSwift()">;
309 def HasSlowVDUP32 : Predicate<"Subtarget->isSwift()">;
311 // Cortex-A9 prefers VMOVSR to VMOVDRR even when using NEON for scalar FP, as
312 // this allows more effective execution domain optimization. See
313 // setExecutionDomain().
314 def UseVMOVSR : Predicate<"Subtarget->isCortexA9() || !Subtarget->useNEONForSinglePrecisionFP()">;
315 def DontUseVMOVSR : Predicate<"!Subtarget->isCortexA9() && Subtarget->useNEONForSinglePrecisionFP()">;
317 def IsLE : Predicate<"getTargetLowering()->isLittleEndian()">;
318 def IsBE : Predicate<"getTargetLowering()->isBigEndian()">;
320 //===----------------------------------------------------------------------===//
321 // ARM Flag Definitions.
323 class RegConstraint<string C> {
324 string Constraints = C;
327 //===----------------------------------------------------------------------===//
328 // ARM specific transformation functions and pattern fragments.
331 // imm_neg_XFORM - Return the negation of an i32 immediate value.
332 def imm_neg_XFORM : SDNodeXForm<imm, [{
333 return CurDAG->getTargetConstant(-(int)N->getZExtValue(), SDLoc(N), MVT::i32);
336 // imm_not_XFORM - Return the complement of a i32 immediate value.
337 def imm_not_XFORM : SDNodeXForm<imm, [{
338 return CurDAG->getTargetConstant(~(int)N->getZExtValue(), SDLoc(N), MVT::i32);
341 /// imm16_31 predicate - True if the 32-bit immediate is in the range [16,31].
342 def imm16_31 : ImmLeaf<i32, [{
343 return (int32_t)Imm >= 16 && (int32_t)Imm < 32;
346 // sext_16_node predicate - True if the SDNode is sign-extended 16 or more bits.
347 def sext_16_node : PatLeaf<(i32 GPR:$a), [{
348 return CurDAG->ComputeNumSignBits(SDValue(N,0)) >= 17;
351 /// Split a 32-bit immediate into two 16 bit parts.
352 def hi16 : SDNodeXForm<imm, [{
353 return CurDAG->getTargetConstant((uint32_t)N->getZExtValue() >> 16, SDLoc(N),
357 def lo16AllZero : PatLeaf<(i32 imm), [{
358 // Returns true if all low 16-bits are 0.
359 return (((uint32_t)N->getZExtValue()) & 0xFFFFUL) == 0;
362 class BinOpWithFlagFrag<dag res> :
363 PatFrag<(ops node:$LHS, node:$RHS, node:$FLAG), res>;
364 class BinOpFrag<dag res> : PatFrag<(ops node:$LHS, node:$RHS), res>;
365 class UnOpFrag <dag res> : PatFrag<(ops node:$Src), res>;
367 // An 'and' node with a single use.
368 def and_su : PatFrag<(ops node:$lhs, node:$rhs), (and node:$lhs, node:$rhs), [{
369 return N->hasOneUse();
372 // An 'xor' node with a single use.
373 def xor_su : PatFrag<(ops node:$lhs, node:$rhs), (xor node:$lhs, node:$rhs), [{
374 return N->hasOneUse();
377 // An 'fmul' node with a single use.
378 def fmul_su : PatFrag<(ops node:$lhs, node:$rhs), (fmul node:$lhs, node:$rhs),[{
379 return N->hasOneUse();
382 // An 'fadd' node which checks for single non-hazardous use.
383 def fadd_mlx : PatFrag<(ops node:$lhs, node:$rhs),(fadd node:$lhs, node:$rhs),[{
384 return hasNoVMLxHazardUse(N);
387 // An 'fsub' node which checks for single non-hazardous use.
388 def fsub_mlx : PatFrag<(ops node:$lhs, node:$rhs),(fsub node:$lhs, node:$rhs),[{
389 return hasNoVMLxHazardUse(N);
392 //===----------------------------------------------------------------------===//
393 // Operand Definitions.
396 // Immediate operands with a shared generic asm render method.
397 class ImmAsmOperand : AsmOperandClass { let RenderMethod = "addImmOperands"; }
399 // Operands that are part of a memory addressing mode.
400 class MemOperand : Operand<i32> { let OperandType = "OPERAND_MEMORY"; }
403 // FIXME: rename brtarget to t2_brtarget
404 def brtarget : Operand<OtherVT> {
405 let EncoderMethod = "getBranchTargetOpValue";
406 let OperandType = "OPERAND_PCREL";
407 let DecoderMethod = "DecodeT2BROperand";
410 // FIXME: get rid of this one?
411 def uncondbrtarget : Operand<OtherVT> {
412 let EncoderMethod = "getUnconditionalBranchTargetOpValue";
413 let OperandType = "OPERAND_PCREL";
416 // Branch target for ARM. Handles conditional/unconditional
417 def br_target : Operand<OtherVT> {
418 let EncoderMethod = "getARMBranchTargetOpValue";
419 let OperandType = "OPERAND_PCREL";
423 // FIXME: rename bltarget to t2_bl_target?
424 def bltarget : Operand<i32> {
425 // Encoded the same as branch targets.
426 let EncoderMethod = "getBranchTargetOpValue";
427 let OperandType = "OPERAND_PCREL";
430 // Call target for ARM. Handles conditional/unconditional
431 // FIXME: rename bl_target to t2_bltarget?
432 def bl_target : Operand<i32> {
433 let EncoderMethod = "getARMBLTargetOpValue";
434 let OperandType = "OPERAND_PCREL";
437 def blx_target : Operand<i32> {
438 let EncoderMethod = "getARMBLXTargetOpValue";
439 let OperandType = "OPERAND_PCREL";
442 // A list of registers separated by comma. Used by load/store multiple.
443 def RegListAsmOperand : AsmOperandClass { let Name = "RegList"; }
444 def reglist : Operand<i32> {
445 let EncoderMethod = "getRegisterListOpValue";
446 let ParserMatchClass = RegListAsmOperand;
447 let PrintMethod = "printRegisterList";
448 let DecoderMethod = "DecodeRegListOperand";
451 def GPRPairOp : RegisterOperand<GPRPair, "printGPRPairOperand">;
453 def DPRRegListAsmOperand : AsmOperandClass { let Name = "DPRRegList"; }
454 def dpr_reglist : Operand<i32> {
455 let EncoderMethod = "getRegisterListOpValue";
456 let ParserMatchClass = DPRRegListAsmOperand;
457 let PrintMethod = "printRegisterList";
458 let DecoderMethod = "DecodeDPRRegListOperand";
461 def SPRRegListAsmOperand : AsmOperandClass { let Name = "SPRRegList"; }
462 def spr_reglist : Operand<i32> {
463 let EncoderMethod = "getRegisterListOpValue";
464 let ParserMatchClass = SPRRegListAsmOperand;
465 let PrintMethod = "printRegisterList";
466 let DecoderMethod = "DecodeSPRRegListOperand";
469 // An operand for the CONSTPOOL_ENTRY pseudo-instruction.
470 def cpinst_operand : Operand<i32> {
471 let PrintMethod = "printCPInstOperand";
475 def pclabel : Operand<i32> {
476 let PrintMethod = "printPCLabel";
479 // ADR instruction labels.
480 def AdrLabelAsmOperand : AsmOperandClass { let Name = "AdrLabel"; }
481 def adrlabel : Operand<i32> {
482 let EncoderMethod = "getAdrLabelOpValue";
483 let ParserMatchClass = AdrLabelAsmOperand;
484 let PrintMethod = "printAdrLabelOperand<0>";
487 def neon_vcvt_imm32 : Operand<i32> {
488 let EncoderMethod = "getNEONVcvtImm32OpValue";
489 let DecoderMethod = "DecodeVCVTImmOperand";
492 // rot_imm: An integer that encodes a rotate amount. Must be 8, 16, or 24.
493 def rot_imm_XFORM: SDNodeXForm<imm, [{
494 switch (N->getZExtValue()){
495 default: llvm_unreachable(nullptr);
496 case 0: return CurDAG->getTargetConstant(0, SDLoc(N), MVT::i32);
497 case 8: return CurDAG->getTargetConstant(1, SDLoc(N), MVT::i32);
498 case 16: return CurDAG->getTargetConstant(2, SDLoc(N), MVT::i32);
499 case 24: return CurDAG->getTargetConstant(3, SDLoc(N), MVT::i32);
502 def RotImmAsmOperand : AsmOperandClass {
504 let ParserMethod = "parseRotImm";
506 def rot_imm : Operand<i32>, PatLeaf<(i32 imm), [{
507 int32_t v = N->getZExtValue();
508 return v == 8 || v == 16 || v == 24; }],
510 let PrintMethod = "printRotImmOperand";
511 let ParserMatchClass = RotImmAsmOperand;
514 // shift_imm: An integer that encodes a shift amount and the type of shift
515 // (asr or lsl). The 6-bit immediate encodes as:
518 // {4-0} imm5 shift amount.
519 // asr #32 encoded as imm5 == 0.
520 def ShifterImmAsmOperand : AsmOperandClass {
521 let Name = "ShifterImm";
522 let ParserMethod = "parseShifterImm";
524 def shift_imm : Operand<i32> {
525 let PrintMethod = "printShiftImmOperand";
526 let ParserMatchClass = ShifterImmAsmOperand;
529 // shifter_operand operands: so_reg_reg, so_reg_imm, and mod_imm.
530 def ShiftedRegAsmOperand : AsmOperandClass { let Name = "RegShiftedReg"; }
531 def so_reg_reg : Operand<i32>, // reg reg imm
532 ComplexPattern<i32, 3, "SelectRegShifterOperand",
533 [shl, srl, sra, rotr]> {
534 let EncoderMethod = "getSORegRegOpValue";
535 let PrintMethod = "printSORegRegOperand";
536 let DecoderMethod = "DecodeSORegRegOperand";
537 let ParserMatchClass = ShiftedRegAsmOperand;
538 let MIOperandInfo = (ops GPRnopc, GPRnopc, i32imm);
541 def ShiftedImmAsmOperand : AsmOperandClass { let Name = "RegShiftedImm"; }
542 def so_reg_imm : Operand<i32>, // reg imm
543 ComplexPattern<i32, 2, "SelectImmShifterOperand",
544 [shl, srl, sra, rotr]> {
545 let EncoderMethod = "getSORegImmOpValue";
546 let PrintMethod = "printSORegImmOperand";
547 let DecoderMethod = "DecodeSORegImmOperand";
548 let ParserMatchClass = ShiftedImmAsmOperand;
549 let MIOperandInfo = (ops GPR, i32imm);
552 // FIXME: Does this need to be distinct from so_reg?
553 def shift_so_reg_reg : Operand<i32>, // reg reg imm
554 ComplexPattern<i32, 3, "SelectShiftRegShifterOperand",
555 [shl,srl,sra,rotr]> {
556 let EncoderMethod = "getSORegRegOpValue";
557 let PrintMethod = "printSORegRegOperand";
558 let DecoderMethod = "DecodeSORegRegOperand";
559 let ParserMatchClass = ShiftedRegAsmOperand;
560 let MIOperandInfo = (ops GPR, GPR, i32imm);
563 // FIXME: Does this need to be distinct from so_reg?
564 def shift_so_reg_imm : Operand<i32>, // reg reg imm
565 ComplexPattern<i32, 2, "SelectShiftImmShifterOperand",
566 [shl,srl,sra,rotr]> {
567 let EncoderMethod = "getSORegImmOpValue";
568 let PrintMethod = "printSORegImmOperand";
569 let DecoderMethod = "DecodeSORegImmOperand";
570 let ParserMatchClass = ShiftedImmAsmOperand;
571 let MIOperandInfo = (ops GPR, i32imm);
574 // mod_imm: match a 32-bit immediate operand, which can be encoded into
575 // a 12-bit immediate; an 8-bit integer and a 4-bit rotator (See ARMARM
576 // - "Modified Immediate Constants"). Within the MC layer we keep this
577 // immediate in its encoded form.
578 def ModImmAsmOperand: AsmOperandClass {
580 let ParserMethod = "parseModImm";
582 def mod_imm : Operand<i32>, ImmLeaf<i32, [{
583 return ARM_AM::getSOImmVal(Imm) != -1;
585 let EncoderMethod = "getModImmOpValue";
586 let PrintMethod = "printModImmOperand";
587 let ParserMatchClass = ModImmAsmOperand;
590 // Note: the patterns mod_imm_not and mod_imm_neg do not require an encoder
591 // method and such, as they are only used on aliases (Pat<> and InstAlias<>).
592 // The actual parsing, encoding, decoding are handled by the destination
593 // instructions, which use mod_imm.
595 def ModImmNotAsmOperand : AsmOperandClass { let Name = "ModImmNot"; }
596 def mod_imm_not : Operand<i32>, PatLeaf<(imm), [{
597 return ARM_AM::getSOImmVal(~(uint32_t)N->getZExtValue()) != -1;
599 let ParserMatchClass = ModImmNotAsmOperand;
602 def ModImmNegAsmOperand : AsmOperandClass { let Name = "ModImmNeg"; }
603 def mod_imm_neg : Operand<i32>, PatLeaf<(imm), [{
604 unsigned Value = -(unsigned)N->getZExtValue();
605 return Value && ARM_AM::getSOImmVal(Value) != -1;
607 let ParserMatchClass = ModImmNegAsmOperand;
610 /// arm_i32imm - True for +V6T2, or when isSOImmTwoParVal()
611 def arm_i32imm : PatLeaf<(imm), [{
612 if (Subtarget->useMovt(*MF))
614 return ARM_AM::isSOImmTwoPartVal((unsigned)N->getZExtValue());
617 /// imm0_1 predicate - Immediate in the range [0,1].
618 def Imm0_1AsmOperand: ImmAsmOperand { let Name = "Imm0_1"; }
619 def imm0_1 : Operand<i32> { let ParserMatchClass = Imm0_1AsmOperand; }
621 /// imm0_3 predicate - Immediate in the range [0,3].
622 def Imm0_3AsmOperand: ImmAsmOperand { let Name = "Imm0_3"; }
623 def imm0_3 : Operand<i32> { let ParserMatchClass = Imm0_3AsmOperand; }
625 /// imm0_7 predicate - Immediate in the range [0,7].
626 def Imm0_7AsmOperand: ImmAsmOperand { let Name = "Imm0_7"; }
627 def imm0_7 : Operand<i32>, ImmLeaf<i32, [{
628 return Imm >= 0 && Imm < 8;
630 let ParserMatchClass = Imm0_7AsmOperand;
633 /// imm8 predicate - Immediate is exactly 8.
634 def Imm8AsmOperand: ImmAsmOperand { let Name = "Imm8"; }
635 def imm8 : Operand<i32>, ImmLeaf<i32, [{ return Imm == 8; }]> {
636 let ParserMatchClass = Imm8AsmOperand;
639 /// imm16 predicate - Immediate is exactly 16.
640 def Imm16AsmOperand: ImmAsmOperand { let Name = "Imm16"; }
641 def imm16 : Operand<i32>, ImmLeaf<i32, [{ return Imm == 16; }]> {
642 let ParserMatchClass = Imm16AsmOperand;
645 /// imm32 predicate - Immediate is exactly 32.
646 def Imm32AsmOperand: ImmAsmOperand { let Name = "Imm32"; }
647 def imm32 : Operand<i32>, ImmLeaf<i32, [{ return Imm == 32; }]> {
648 let ParserMatchClass = Imm32AsmOperand;
651 def imm8_or_16 : ImmLeaf<i32, [{ return Imm == 8 || Imm == 16;}]>;
653 /// imm1_7 predicate - Immediate in the range [1,7].
654 def Imm1_7AsmOperand: ImmAsmOperand { let Name = "Imm1_7"; }
655 def imm1_7 : Operand<i32>, ImmLeaf<i32, [{ return Imm > 0 && Imm < 8; }]> {
656 let ParserMatchClass = Imm1_7AsmOperand;
659 /// imm1_15 predicate - Immediate in the range [1,15].
660 def Imm1_15AsmOperand: ImmAsmOperand { let Name = "Imm1_15"; }
661 def imm1_15 : Operand<i32>, ImmLeaf<i32, [{ return Imm > 0 && Imm < 16; }]> {
662 let ParserMatchClass = Imm1_15AsmOperand;
665 /// imm1_31 predicate - Immediate in the range [1,31].
666 def Imm1_31AsmOperand: ImmAsmOperand { let Name = "Imm1_31"; }
667 def imm1_31 : Operand<i32>, ImmLeaf<i32, [{ return Imm > 0 && Imm < 32; }]> {
668 let ParserMatchClass = Imm1_31AsmOperand;
671 /// imm0_15 predicate - Immediate in the range [0,15].
672 def Imm0_15AsmOperand: ImmAsmOperand {
673 let Name = "Imm0_15";
674 let DiagnosticType = "ImmRange0_15";
676 def imm0_15 : Operand<i32>, ImmLeaf<i32, [{
677 return Imm >= 0 && Imm < 16;
679 let ParserMatchClass = Imm0_15AsmOperand;
682 /// imm0_31 predicate - True if the 32-bit immediate is in the range [0,31].
683 def Imm0_31AsmOperand: ImmAsmOperand { let Name = "Imm0_31"; }
684 def imm0_31 : Operand<i32>, ImmLeaf<i32, [{
685 return Imm >= 0 && Imm < 32;
687 let ParserMatchClass = Imm0_31AsmOperand;
690 /// imm0_32 predicate - True if the 32-bit immediate is in the range [0,32].
691 def Imm0_32AsmOperand: ImmAsmOperand { let Name = "Imm0_32"; }
692 def imm0_32 : Operand<i32>, ImmLeaf<i32, [{
693 return Imm >= 0 && Imm < 32;
695 let ParserMatchClass = Imm0_32AsmOperand;
698 /// imm0_63 predicate - True if the 32-bit immediate is in the range [0,63].
699 def Imm0_63AsmOperand: ImmAsmOperand { let Name = "Imm0_63"; }
700 def imm0_63 : Operand<i32>, ImmLeaf<i32, [{
701 return Imm >= 0 && Imm < 64;
703 let ParserMatchClass = Imm0_63AsmOperand;
706 /// imm0_239 predicate - Immediate in the range [0,239].
707 def Imm0_239AsmOperand : ImmAsmOperand {
708 let Name = "Imm0_239";
709 let DiagnosticType = "ImmRange0_239";
711 def imm0_239 : Operand<i32>, ImmLeaf<i32, [{ return Imm >= 0 && Imm < 240; }]> {
712 let ParserMatchClass = Imm0_239AsmOperand;
715 /// imm0_255 predicate - Immediate in the range [0,255].
716 def Imm0_255AsmOperand : ImmAsmOperand { let Name = "Imm0_255"; }
717 def imm0_255 : Operand<i32>, ImmLeaf<i32, [{ return Imm >= 0 && Imm < 256; }]> {
718 let ParserMatchClass = Imm0_255AsmOperand;
721 /// imm0_65535 - An immediate is in the range [0.65535].
722 def Imm0_65535AsmOperand: ImmAsmOperand { let Name = "Imm0_65535"; }
723 def imm0_65535 : Operand<i32>, ImmLeaf<i32, [{
724 return Imm >= 0 && Imm < 65536;
726 let ParserMatchClass = Imm0_65535AsmOperand;
729 // imm0_65535_neg - An immediate whose negative value is in the range [0.65535].
730 def imm0_65535_neg : Operand<i32>, ImmLeaf<i32, [{
731 return -Imm >= 0 && -Imm < 65536;
734 // imm0_65535_expr - For movt/movw - 16-bit immediate that can also reference
735 // a relocatable expression.
737 // FIXME: This really needs a Thumb version separate from the ARM version.
738 // While the range is the same, and can thus use the same match class,
739 // the encoding is different so it should have a different encoder method.
740 def Imm0_65535ExprAsmOperand: ImmAsmOperand { let Name = "Imm0_65535Expr"; }
741 def imm0_65535_expr : Operand<i32> {
742 let EncoderMethod = "getHiLo16ImmOpValue";
743 let ParserMatchClass = Imm0_65535ExprAsmOperand;
746 def Imm256_65535ExprAsmOperand: ImmAsmOperand { let Name = "Imm256_65535Expr"; }
747 def imm256_65535_expr : Operand<i32> {
748 let ParserMatchClass = Imm256_65535ExprAsmOperand;
751 /// imm24b - True if the 32-bit immediate is encodable in 24 bits.
752 def Imm24bitAsmOperand: ImmAsmOperand { let Name = "Imm24bit"; }
753 def imm24b : Operand<i32>, ImmLeaf<i32, [{
754 return Imm >= 0 && Imm <= 0xffffff;
756 let ParserMatchClass = Imm24bitAsmOperand;
760 /// bf_inv_mask_imm predicate - An AND mask to clear an arbitrary width bitfield
762 def BitfieldAsmOperand : AsmOperandClass {
763 let Name = "Bitfield";
764 let ParserMethod = "parseBitfield";
767 def bf_inv_mask_imm : Operand<i32>,
769 return ARM::isBitFieldInvertedMask(N->getZExtValue());
771 let EncoderMethod = "getBitfieldInvertedMaskOpValue";
772 let PrintMethod = "printBitfieldInvMaskImmOperand";
773 let DecoderMethod = "DecodeBitfieldMaskOperand";
774 let ParserMatchClass = BitfieldAsmOperand;
777 def imm1_32_XFORM: SDNodeXForm<imm, [{
778 return CurDAG->getTargetConstant((int)N->getZExtValue() - 1, SDLoc(N),
781 def Imm1_32AsmOperand: AsmOperandClass { let Name = "Imm1_32"; }
782 def imm1_32 : Operand<i32>, PatLeaf<(imm), [{
783 uint64_t Imm = N->getZExtValue();
784 return Imm > 0 && Imm <= 32;
787 let PrintMethod = "printImmPlusOneOperand";
788 let ParserMatchClass = Imm1_32AsmOperand;
791 def imm1_16_XFORM: SDNodeXForm<imm, [{
792 return CurDAG->getTargetConstant((int)N->getZExtValue() - 1, SDLoc(N),
795 def Imm1_16AsmOperand: AsmOperandClass { let Name = "Imm1_16"; }
796 def imm1_16 : Operand<i32>, PatLeaf<(imm), [{ return Imm > 0 && Imm <= 16; }],
798 let PrintMethod = "printImmPlusOneOperand";
799 let ParserMatchClass = Imm1_16AsmOperand;
802 // Define ARM specific addressing modes.
803 // addrmode_imm12 := reg +/- imm12
805 def MemImm12OffsetAsmOperand : AsmOperandClass { let Name = "MemImm12Offset"; }
806 class AddrMode_Imm12 : MemOperand,
807 ComplexPattern<i32, 2, "SelectAddrModeImm12", []> {
808 // 12-bit immediate operand. Note that instructions using this encode
809 // #0 and #-0 differently. We flag #-0 as the magic value INT32_MIN. All other
810 // immediate values are as normal.
812 let EncoderMethod = "getAddrModeImm12OpValue";
813 let DecoderMethod = "DecodeAddrModeImm12Operand";
814 let ParserMatchClass = MemImm12OffsetAsmOperand;
815 let MIOperandInfo = (ops GPR:$base, i32imm:$offsimm);
818 def addrmode_imm12 : AddrMode_Imm12 {
819 let PrintMethod = "printAddrModeImm12Operand<false>";
822 def addrmode_imm12_pre : AddrMode_Imm12 {
823 let PrintMethod = "printAddrModeImm12Operand<true>";
826 // ldst_so_reg := reg +/- reg shop imm
828 def MemRegOffsetAsmOperand : AsmOperandClass { let Name = "MemRegOffset"; }
829 def ldst_so_reg : MemOperand,
830 ComplexPattern<i32, 3, "SelectLdStSOReg", []> {
831 let EncoderMethod = "getLdStSORegOpValue";
832 // FIXME: Simplify the printer
833 let PrintMethod = "printAddrMode2Operand";
834 let DecoderMethod = "DecodeSORegMemOperand";
835 let ParserMatchClass = MemRegOffsetAsmOperand;
836 let MIOperandInfo = (ops GPR:$base, GPRnopc:$offsreg, i32imm:$shift);
839 // postidx_imm8 := +/- [0,255]
842 // {8} 1 is imm8 is non-negative. 0 otherwise.
843 // {7-0} [0,255] imm8 value.
844 def PostIdxImm8AsmOperand : AsmOperandClass { let Name = "PostIdxImm8"; }
845 def postidx_imm8 : MemOperand {
846 let PrintMethod = "printPostIdxImm8Operand";
847 let ParserMatchClass = PostIdxImm8AsmOperand;
848 let MIOperandInfo = (ops i32imm);
851 // postidx_imm8s4 := +/- [0,1020]
854 // {8} 1 is imm8 is non-negative. 0 otherwise.
855 // {7-0} [0,255] imm8 value, scaled by 4.
856 def PostIdxImm8s4AsmOperand : AsmOperandClass { let Name = "PostIdxImm8s4"; }
857 def postidx_imm8s4 : MemOperand {
858 let PrintMethod = "printPostIdxImm8s4Operand";
859 let ParserMatchClass = PostIdxImm8s4AsmOperand;
860 let MIOperandInfo = (ops i32imm);
864 // postidx_reg := +/- reg
866 def PostIdxRegAsmOperand : AsmOperandClass {
867 let Name = "PostIdxReg";
868 let ParserMethod = "parsePostIdxReg";
870 def postidx_reg : MemOperand {
871 let EncoderMethod = "getPostIdxRegOpValue";
872 let DecoderMethod = "DecodePostIdxReg";
873 let PrintMethod = "printPostIdxRegOperand";
874 let ParserMatchClass = PostIdxRegAsmOperand;
875 let MIOperandInfo = (ops GPRnopc, i32imm);
879 // addrmode2 := reg +/- imm12
880 // := reg +/- reg shop imm
882 // FIXME: addrmode2 should be refactored the rest of the way to always
883 // use explicit imm vs. reg versions above (addrmode_imm12 and ldst_so_reg).
884 def AddrMode2AsmOperand : AsmOperandClass { let Name = "AddrMode2"; }
885 def addrmode2 : MemOperand,
886 ComplexPattern<i32, 3, "SelectAddrMode2", []> {
887 let EncoderMethod = "getAddrMode2OpValue";
888 let PrintMethod = "printAddrMode2Operand";
889 let ParserMatchClass = AddrMode2AsmOperand;
890 let MIOperandInfo = (ops GPR:$base, GPR:$offsreg, i32imm:$offsimm);
893 def PostIdxRegShiftedAsmOperand : AsmOperandClass {
894 let Name = "PostIdxRegShifted";
895 let ParserMethod = "parsePostIdxReg";
897 def am2offset_reg : MemOperand,
898 ComplexPattern<i32, 2, "SelectAddrMode2OffsetReg",
899 [], [SDNPWantRoot]> {
900 let EncoderMethod = "getAddrMode2OffsetOpValue";
901 let PrintMethod = "printAddrMode2OffsetOperand";
902 // When using this for assembly, it's always as a post-index offset.
903 let ParserMatchClass = PostIdxRegShiftedAsmOperand;
904 let MIOperandInfo = (ops GPRnopc, i32imm);
907 // FIXME: am2offset_imm should only need the immediate, not the GPR. Having
908 // the GPR is purely vestigal at this point.
909 def AM2OffsetImmAsmOperand : AsmOperandClass { let Name = "AM2OffsetImm"; }
910 def am2offset_imm : MemOperand,
911 ComplexPattern<i32, 2, "SelectAddrMode2OffsetImm",
912 [], [SDNPWantRoot]> {
913 let EncoderMethod = "getAddrMode2OffsetOpValue";
914 let PrintMethod = "printAddrMode2OffsetOperand";
915 let ParserMatchClass = AM2OffsetImmAsmOperand;
916 let MIOperandInfo = (ops GPRnopc, i32imm);
920 // addrmode3 := reg +/- reg
921 // addrmode3 := reg +/- imm8
923 // FIXME: split into imm vs. reg versions.
924 def AddrMode3AsmOperand : AsmOperandClass { let Name = "AddrMode3"; }
925 class AddrMode3 : MemOperand,
926 ComplexPattern<i32, 3, "SelectAddrMode3", []> {
927 let EncoderMethod = "getAddrMode3OpValue";
928 let ParserMatchClass = AddrMode3AsmOperand;
929 let MIOperandInfo = (ops GPR:$base, GPR:$offsreg, i32imm:$offsimm);
932 def addrmode3 : AddrMode3
934 let PrintMethod = "printAddrMode3Operand<false>";
937 def addrmode3_pre : AddrMode3
939 let PrintMethod = "printAddrMode3Operand<true>";
942 // FIXME: split into imm vs. reg versions.
943 // FIXME: parser method to handle +/- register.
944 def AM3OffsetAsmOperand : AsmOperandClass {
945 let Name = "AM3Offset";
946 let ParserMethod = "parseAM3Offset";
948 def am3offset : MemOperand,
949 ComplexPattern<i32, 2, "SelectAddrMode3Offset",
950 [], [SDNPWantRoot]> {
951 let EncoderMethod = "getAddrMode3OffsetOpValue";
952 let PrintMethod = "printAddrMode3OffsetOperand";
953 let ParserMatchClass = AM3OffsetAsmOperand;
954 let MIOperandInfo = (ops GPR, i32imm);
957 // ldstm_mode := {ia, ib, da, db}
959 def ldstm_mode : OptionalDefOperand<OtherVT, (ops i32), (ops (i32 1))> {
960 let EncoderMethod = "getLdStmModeOpValue";
961 let PrintMethod = "printLdStmModeOperand";
964 // addrmode5 := reg +/- imm8*4
966 def AddrMode5AsmOperand : AsmOperandClass { let Name = "AddrMode5"; }
967 class AddrMode5 : MemOperand,
968 ComplexPattern<i32, 2, "SelectAddrMode5", []> {
969 let EncoderMethod = "getAddrMode5OpValue";
970 let DecoderMethod = "DecodeAddrMode5Operand";
971 let ParserMatchClass = AddrMode5AsmOperand;
972 let MIOperandInfo = (ops GPR:$base, i32imm);
975 def addrmode5 : AddrMode5 {
976 let PrintMethod = "printAddrMode5Operand<false>";
979 def addrmode5_pre : AddrMode5 {
980 let PrintMethod = "printAddrMode5Operand<true>";
983 // addrmode6 := reg with optional alignment
985 def AddrMode6AsmOperand : AsmOperandClass { let Name = "AlignedMemory"; }
986 def addrmode6 : MemOperand,
987 ComplexPattern<i32, 2, "SelectAddrMode6", [], [SDNPWantParent]>{
988 let PrintMethod = "printAddrMode6Operand";
989 let MIOperandInfo = (ops GPR:$addr, i32imm:$align);
990 let EncoderMethod = "getAddrMode6AddressOpValue";
991 let DecoderMethod = "DecodeAddrMode6Operand";
992 let ParserMatchClass = AddrMode6AsmOperand;
995 def am6offset : MemOperand,
996 ComplexPattern<i32, 1, "SelectAddrMode6Offset",
997 [], [SDNPWantRoot]> {
998 let PrintMethod = "printAddrMode6OffsetOperand";
999 let MIOperandInfo = (ops GPR);
1000 let EncoderMethod = "getAddrMode6OffsetOpValue";
1001 let DecoderMethod = "DecodeGPRRegisterClass";
1004 // Special version of addrmode6 to handle alignment encoding for VST1/VLD1
1005 // (single element from one lane) for size 32.
1006 def addrmode6oneL32 : MemOperand,
1007 ComplexPattern<i32, 2, "SelectAddrMode6", [], [SDNPWantParent]>{
1008 let PrintMethod = "printAddrMode6Operand";
1009 let MIOperandInfo = (ops GPR:$addr, i32imm);
1010 let EncoderMethod = "getAddrMode6OneLane32AddressOpValue";
1013 // Base class for addrmode6 with specific alignment restrictions.
1014 class AddrMode6Align : MemOperand,
1015 ComplexPattern<i32, 2, "SelectAddrMode6", [], [SDNPWantParent]>{
1016 let PrintMethod = "printAddrMode6Operand";
1017 let MIOperandInfo = (ops GPR:$addr, i32imm:$align);
1018 let EncoderMethod = "getAddrMode6AddressOpValue";
1019 let DecoderMethod = "DecodeAddrMode6Operand";
1022 // Special version of addrmode6 to handle no allowed alignment encoding for
1023 // VLD/VST instructions and checking the alignment is not specified.
1024 def AddrMode6AlignNoneAsmOperand : AsmOperandClass {
1025 let Name = "AlignedMemoryNone";
1026 let DiagnosticType = "AlignedMemoryRequiresNone";
1028 def addrmode6alignNone : AddrMode6Align {
1029 // The alignment specifier can only be omitted.
1030 let ParserMatchClass = AddrMode6AlignNoneAsmOperand;
1033 // Special version of addrmode6 to handle 16-bit alignment encoding for
1034 // VLD/VST instructions and checking the alignment value.
1035 def AddrMode6Align16AsmOperand : AsmOperandClass {
1036 let Name = "AlignedMemory16";
1037 let DiagnosticType = "AlignedMemoryRequires16";
1039 def addrmode6align16 : AddrMode6Align {
1040 // The alignment specifier can only be 16 or omitted.
1041 let ParserMatchClass = AddrMode6Align16AsmOperand;
1044 // Special version of addrmode6 to handle 32-bit alignment encoding for
1045 // VLD/VST instructions and checking the alignment value.
1046 def AddrMode6Align32AsmOperand : AsmOperandClass {
1047 let Name = "AlignedMemory32";
1048 let DiagnosticType = "AlignedMemoryRequires32";
1050 def addrmode6align32 : AddrMode6Align {
1051 // The alignment specifier can only be 32 or omitted.
1052 let ParserMatchClass = AddrMode6Align32AsmOperand;
1055 // Special version of addrmode6 to handle 64-bit alignment encoding for
1056 // VLD/VST instructions and checking the alignment value.
1057 def AddrMode6Align64AsmOperand : AsmOperandClass {
1058 let Name = "AlignedMemory64";
1059 let DiagnosticType = "AlignedMemoryRequires64";
1061 def addrmode6align64 : AddrMode6Align {
1062 // The alignment specifier can only be 64 or omitted.
1063 let ParserMatchClass = AddrMode6Align64AsmOperand;
1066 // Special version of addrmode6 to handle 64-bit or 128-bit alignment encoding
1067 // for VLD/VST instructions and checking the alignment value.
1068 def AddrMode6Align64or128AsmOperand : AsmOperandClass {
1069 let Name = "AlignedMemory64or128";
1070 let DiagnosticType = "AlignedMemoryRequires64or128";
1072 def addrmode6align64or128 : AddrMode6Align {
1073 // The alignment specifier can only be 64, 128 or omitted.
1074 let ParserMatchClass = AddrMode6Align64or128AsmOperand;
1077 // Special version of addrmode6 to handle 64-bit, 128-bit or 256-bit alignment
1078 // encoding for VLD/VST instructions and checking the alignment value.
1079 def AddrMode6Align64or128or256AsmOperand : AsmOperandClass {
1080 let Name = "AlignedMemory64or128or256";
1081 let DiagnosticType = "AlignedMemoryRequires64or128or256";
1083 def addrmode6align64or128or256 : AddrMode6Align {
1084 // The alignment specifier can only be 64, 128, 256 or omitted.
1085 let ParserMatchClass = AddrMode6Align64or128or256AsmOperand;
1088 // Special version of addrmode6 to handle alignment encoding for VLD-dup
1089 // instructions, specifically VLD4-dup.
1090 def addrmode6dup : MemOperand,
1091 ComplexPattern<i32, 2, "SelectAddrMode6", [], [SDNPWantParent]>{
1092 let PrintMethod = "printAddrMode6Operand";
1093 let MIOperandInfo = (ops GPR:$addr, i32imm);
1094 let EncoderMethod = "getAddrMode6DupAddressOpValue";
1095 // FIXME: This is close, but not quite right. The alignment specifier is
1097 let ParserMatchClass = AddrMode6AsmOperand;
1100 // Base class for addrmode6dup with specific alignment restrictions.
1101 class AddrMode6DupAlign : MemOperand,
1102 ComplexPattern<i32, 2, "SelectAddrMode6", [], [SDNPWantParent]>{
1103 let PrintMethod = "printAddrMode6Operand";
1104 let MIOperandInfo = (ops GPR:$addr, i32imm);
1105 let EncoderMethod = "getAddrMode6DupAddressOpValue";
1108 // Special version of addrmode6 to handle no allowed alignment encoding for
1109 // VLD-dup instruction and checking the alignment is not specified.
1110 def AddrMode6dupAlignNoneAsmOperand : AsmOperandClass {
1111 let Name = "DupAlignedMemoryNone";
1112 let DiagnosticType = "DupAlignedMemoryRequiresNone";
1114 def addrmode6dupalignNone : AddrMode6DupAlign {
1115 // The alignment specifier can only be omitted.
1116 let ParserMatchClass = AddrMode6dupAlignNoneAsmOperand;
1119 // Special version of addrmode6 to handle 16-bit alignment encoding for VLD-dup
1120 // instruction and checking the alignment value.
1121 def AddrMode6dupAlign16AsmOperand : AsmOperandClass {
1122 let Name = "DupAlignedMemory16";
1123 let DiagnosticType = "DupAlignedMemoryRequires16";
1125 def addrmode6dupalign16 : AddrMode6DupAlign {
1126 // The alignment specifier can only be 16 or omitted.
1127 let ParserMatchClass = AddrMode6dupAlign16AsmOperand;
1130 // Special version of addrmode6 to handle 32-bit alignment encoding for VLD-dup
1131 // instruction and checking the alignment value.
1132 def AddrMode6dupAlign32AsmOperand : AsmOperandClass {
1133 let Name = "DupAlignedMemory32";
1134 let DiagnosticType = "DupAlignedMemoryRequires32";
1136 def addrmode6dupalign32 : AddrMode6DupAlign {
1137 // The alignment specifier can only be 32 or omitted.
1138 let ParserMatchClass = AddrMode6dupAlign32AsmOperand;
1141 // Special version of addrmode6 to handle 64-bit alignment encoding for VLD
1142 // instructions and checking the alignment value.
1143 def AddrMode6dupAlign64AsmOperand : AsmOperandClass {
1144 let Name = "DupAlignedMemory64";
1145 let DiagnosticType = "DupAlignedMemoryRequires64";
1147 def addrmode6dupalign64 : AddrMode6DupAlign {
1148 // The alignment specifier can only be 64 or omitted.
1149 let ParserMatchClass = AddrMode6dupAlign64AsmOperand;
1152 // Special version of addrmode6 to handle 64-bit or 128-bit alignment encoding
1153 // for VLD instructions and checking the alignment value.
1154 def AddrMode6dupAlign64or128AsmOperand : AsmOperandClass {
1155 let Name = "DupAlignedMemory64or128";
1156 let DiagnosticType = "DupAlignedMemoryRequires64or128";
1158 def addrmode6dupalign64or128 : AddrMode6DupAlign {
1159 // The alignment specifier can only be 64, 128 or omitted.
1160 let ParserMatchClass = AddrMode6dupAlign64or128AsmOperand;
1163 // addrmodepc := pc + reg
1165 def addrmodepc : MemOperand,
1166 ComplexPattern<i32, 2, "SelectAddrModePC", []> {
1167 let PrintMethod = "printAddrModePCOperand";
1168 let MIOperandInfo = (ops GPR, i32imm);
1171 // addr_offset_none := reg
1173 def MemNoOffsetAsmOperand : AsmOperandClass { let Name = "MemNoOffset"; }
1174 def addr_offset_none : MemOperand,
1175 ComplexPattern<i32, 1, "SelectAddrOffsetNone", []> {
1176 let PrintMethod = "printAddrMode7Operand";
1177 let DecoderMethod = "DecodeAddrMode7Operand";
1178 let ParserMatchClass = MemNoOffsetAsmOperand;
1179 let MIOperandInfo = (ops GPR:$base);
1182 def nohash_imm : Operand<i32> {
1183 let PrintMethod = "printNoHashImmediate";
1186 def CoprocNumAsmOperand : AsmOperandClass {
1187 let Name = "CoprocNum";
1188 let ParserMethod = "parseCoprocNumOperand";
1190 def p_imm : Operand<i32> {
1191 let PrintMethod = "printPImmediate";
1192 let ParserMatchClass = CoprocNumAsmOperand;
1193 let DecoderMethod = "DecodeCoprocessor";
1196 def CoprocRegAsmOperand : AsmOperandClass {
1197 let Name = "CoprocReg";
1198 let ParserMethod = "parseCoprocRegOperand";
1200 def c_imm : Operand<i32> {
1201 let PrintMethod = "printCImmediate";
1202 let ParserMatchClass = CoprocRegAsmOperand;
1204 def CoprocOptionAsmOperand : AsmOperandClass {
1205 let Name = "CoprocOption";
1206 let ParserMethod = "parseCoprocOptionOperand";
1208 def coproc_option_imm : Operand<i32> {
1209 let PrintMethod = "printCoprocOptionImm";
1210 let ParserMatchClass = CoprocOptionAsmOperand;
1213 //===----------------------------------------------------------------------===//
1215 include "ARMInstrFormats.td"
1217 //===----------------------------------------------------------------------===//
1218 // Multiclass helpers...
1221 /// AsI1_bin_irs - Defines a set of (op r, {mod_imm|r|so_reg}) patterns for a
1222 /// binop that produces a value.
1223 let TwoOperandAliasConstraint = "$Rn = $Rd" in
1224 multiclass AsI1_bin_irs<bits<4> opcod, string opc,
1225 InstrItinClass iii, InstrItinClass iir, InstrItinClass iis,
1226 PatFrag opnode, bit Commutable = 0> {
1227 // The register-immediate version is re-materializable. This is useful
1228 // in particular for taking the address of a local.
1229 let isReMaterializable = 1 in {
1230 def ri : AsI1<opcod, (outs GPR:$Rd), (ins GPR:$Rn, mod_imm:$imm), DPFrm,
1231 iii, opc, "\t$Rd, $Rn, $imm",
1232 [(set GPR:$Rd, (opnode GPR:$Rn, mod_imm:$imm))]>,
1233 Sched<[WriteALU, ReadALU]> {
1238 let Inst{19-16} = Rn;
1239 let Inst{15-12} = Rd;
1240 let Inst{11-0} = imm;
1243 def rr : AsI1<opcod, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm), DPFrm,
1244 iir, opc, "\t$Rd, $Rn, $Rm",
1245 [(set GPR:$Rd, (opnode GPR:$Rn, GPR:$Rm))]>,
1246 Sched<[WriteALU, ReadALU, ReadALU]> {
1251 let isCommutable = Commutable;
1252 let Inst{19-16} = Rn;
1253 let Inst{15-12} = Rd;
1254 let Inst{11-4} = 0b00000000;
1258 def rsi : AsI1<opcod, (outs GPR:$Rd),
1259 (ins GPR:$Rn, so_reg_imm:$shift), DPSoRegImmFrm,
1260 iis, opc, "\t$Rd, $Rn, $shift",
1261 [(set GPR:$Rd, (opnode GPR:$Rn, so_reg_imm:$shift))]>,
1262 Sched<[WriteALUsi, ReadALU]> {
1267 let Inst{19-16} = Rn;
1268 let Inst{15-12} = Rd;
1269 let Inst{11-5} = shift{11-5};
1271 let Inst{3-0} = shift{3-0};
1274 def rsr : AsI1<opcod, (outs GPR:$Rd),
1275 (ins GPR:$Rn, so_reg_reg:$shift), DPSoRegRegFrm,
1276 iis, opc, "\t$Rd, $Rn, $shift",
1277 [(set GPR:$Rd, (opnode GPR:$Rn, so_reg_reg:$shift))]>,
1278 Sched<[WriteALUsr, ReadALUsr]> {
1283 let Inst{19-16} = Rn;
1284 let Inst{15-12} = Rd;
1285 let Inst{11-8} = shift{11-8};
1287 let Inst{6-5} = shift{6-5};
1289 let Inst{3-0} = shift{3-0};
1293 /// AsI1_rbin_irs - Same as AsI1_bin_irs except the order of operands are
1294 /// reversed. The 'rr' form is only defined for the disassembler; for codegen
1295 /// it is equivalent to the AsI1_bin_irs counterpart.
1296 let TwoOperandAliasConstraint = "$Rn = $Rd" in
1297 multiclass AsI1_rbin_irs<bits<4> opcod, string opc,
1298 InstrItinClass iii, InstrItinClass iir, InstrItinClass iis,
1299 PatFrag opnode, bit Commutable = 0> {
1300 // The register-immediate version is re-materializable. This is useful
1301 // in particular for taking the address of a local.
1302 let isReMaterializable = 1 in {
1303 def ri : AsI1<opcod, (outs GPR:$Rd), (ins GPR:$Rn, mod_imm:$imm), DPFrm,
1304 iii, opc, "\t$Rd, $Rn, $imm",
1305 [(set GPR:$Rd, (opnode mod_imm:$imm, GPR:$Rn))]>,
1306 Sched<[WriteALU, ReadALU]> {
1311 let Inst{19-16} = Rn;
1312 let Inst{15-12} = Rd;
1313 let Inst{11-0} = imm;
1316 def rr : AsI1<opcod, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm), DPFrm,
1317 iir, opc, "\t$Rd, $Rn, $Rm",
1318 [/* pattern left blank */]>,
1319 Sched<[WriteALU, ReadALU, ReadALU]> {
1323 let Inst{11-4} = 0b00000000;
1326 let Inst{15-12} = Rd;
1327 let Inst{19-16} = Rn;
1330 def rsi : AsI1<opcod, (outs GPR:$Rd),
1331 (ins GPR:$Rn, so_reg_imm:$shift), DPSoRegImmFrm,
1332 iis, opc, "\t$Rd, $Rn, $shift",
1333 [(set GPR:$Rd, (opnode so_reg_imm:$shift, GPR:$Rn))]>,
1334 Sched<[WriteALUsi, ReadALU]> {
1339 let Inst{19-16} = Rn;
1340 let Inst{15-12} = Rd;
1341 let Inst{11-5} = shift{11-5};
1343 let Inst{3-0} = shift{3-0};
1346 def rsr : AsI1<opcod, (outs GPR:$Rd),
1347 (ins GPR:$Rn, so_reg_reg:$shift), DPSoRegRegFrm,
1348 iis, opc, "\t$Rd, $Rn, $shift",
1349 [(set GPR:$Rd, (opnode so_reg_reg:$shift, GPR:$Rn))]>,
1350 Sched<[WriteALUsr, ReadALUsr]> {
1355 let Inst{19-16} = Rn;
1356 let Inst{15-12} = Rd;
1357 let Inst{11-8} = shift{11-8};
1359 let Inst{6-5} = shift{6-5};
1361 let Inst{3-0} = shift{3-0};
1365 /// AsI1_bin_s_irs - Same as AsI1_bin_irs except it sets the 's' bit by default.
1367 /// These opcodes will be converted to the real non-S opcodes by
1368 /// AdjustInstrPostInstrSelection after giving them an optional CPSR operand.
1369 let hasPostISelHook = 1, Defs = [CPSR] in {
1370 multiclass AsI1_bin_s_irs<InstrItinClass iii, InstrItinClass iir,
1371 InstrItinClass iis, PatFrag opnode,
1372 bit Commutable = 0> {
1373 def ri : ARMPseudoInst<(outs GPR:$Rd), (ins GPR:$Rn, mod_imm:$imm, pred:$p),
1375 [(set GPR:$Rd, CPSR, (opnode GPR:$Rn, mod_imm:$imm))]>,
1376 Sched<[WriteALU, ReadALU]>;
1378 def rr : ARMPseudoInst<(outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm, pred:$p),
1380 [(set GPR:$Rd, CPSR, (opnode GPR:$Rn, GPR:$Rm))]>,
1381 Sched<[WriteALU, ReadALU, ReadALU]> {
1382 let isCommutable = Commutable;
1384 def rsi : ARMPseudoInst<(outs GPR:$Rd),
1385 (ins GPR:$Rn, so_reg_imm:$shift, pred:$p),
1387 [(set GPR:$Rd, CPSR, (opnode GPR:$Rn,
1388 so_reg_imm:$shift))]>,
1389 Sched<[WriteALUsi, ReadALU]>;
1391 def rsr : ARMPseudoInst<(outs GPR:$Rd),
1392 (ins GPR:$Rn, so_reg_reg:$shift, pred:$p),
1394 [(set GPR:$Rd, CPSR, (opnode GPR:$Rn,
1395 so_reg_reg:$shift))]>,
1396 Sched<[WriteALUSsr, ReadALUsr]>;
1400 /// AsI1_rbin_s_is - Same as AsI1_bin_s_irs, except selection DAG
1401 /// operands are reversed.
1402 let hasPostISelHook = 1, Defs = [CPSR] in {
1403 multiclass AsI1_rbin_s_is<InstrItinClass iii, InstrItinClass iir,
1404 InstrItinClass iis, PatFrag opnode,
1405 bit Commutable = 0> {
1406 def ri : ARMPseudoInst<(outs GPR:$Rd), (ins GPR:$Rn, mod_imm:$imm, pred:$p),
1408 [(set GPR:$Rd, CPSR, (opnode mod_imm:$imm, GPR:$Rn))]>,
1409 Sched<[WriteALU, ReadALU]>;
1411 def rsi : ARMPseudoInst<(outs GPR:$Rd),
1412 (ins GPR:$Rn, so_reg_imm:$shift, pred:$p),
1414 [(set GPR:$Rd, CPSR, (opnode so_reg_imm:$shift,
1416 Sched<[WriteALUsi, ReadALU]>;
1418 def rsr : ARMPseudoInst<(outs GPR:$Rd),
1419 (ins GPR:$Rn, so_reg_reg:$shift, pred:$p),
1421 [(set GPR:$Rd, CPSR, (opnode so_reg_reg:$shift,
1423 Sched<[WriteALUSsr, ReadALUsr]>;
1427 /// AI1_cmp_irs - Defines a set of (op r, {mod_imm|r|so_reg}) cmp / test
1428 /// patterns. Similar to AsI1_bin_irs except the instruction does not produce
1429 /// a explicit result, only implicitly set CPSR.
1430 let isCompare = 1, Defs = [CPSR] in {
1431 multiclass AI1_cmp_irs<bits<4> opcod, string opc,
1432 InstrItinClass iii, InstrItinClass iir, InstrItinClass iis,
1433 PatFrag opnode, bit Commutable = 0,
1434 string rrDecoderMethod = ""> {
1435 def ri : AI1<opcod, (outs), (ins GPR:$Rn, mod_imm:$imm), DPFrm, iii,
1437 [(opnode GPR:$Rn, mod_imm:$imm)]>,
1438 Sched<[WriteCMP, ReadALU]> {
1443 let Inst{19-16} = Rn;
1444 let Inst{15-12} = 0b0000;
1445 let Inst{11-0} = imm;
1447 let Unpredictable{15-12} = 0b1111;
1449 def rr : AI1<opcod, (outs), (ins GPR:$Rn, GPR:$Rm), DPFrm, iir,
1451 [(opnode GPR:$Rn, GPR:$Rm)]>,
1452 Sched<[WriteCMP, ReadALU, ReadALU]> {
1455 let isCommutable = Commutable;
1458 let Inst{19-16} = Rn;
1459 let Inst{15-12} = 0b0000;
1460 let Inst{11-4} = 0b00000000;
1462 let DecoderMethod = rrDecoderMethod;
1464 let Unpredictable{15-12} = 0b1111;
1466 def rsi : AI1<opcod, (outs),
1467 (ins GPR:$Rn, so_reg_imm:$shift), DPSoRegImmFrm, iis,
1468 opc, "\t$Rn, $shift",
1469 [(opnode GPR:$Rn, so_reg_imm:$shift)]>,
1470 Sched<[WriteCMPsi, ReadALU]> {
1475 let Inst{19-16} = Rn;
1476 let Inst{15-12} = 0b0000;
1477 let Inst{11-5} = shift{11-5};
1479 let Inst{3-0} = shift{3-0};
1481 let Unpredictable{15-12} = 0b1111;
1483 def rsr : AI1<opcod, (outs),
1484 (ins GPRnopc:$Rn, so_reg_reg:$shift), DPSoRegRegFrm, iis,
1485 opc, "\t$Rn, $shift",
1486 [(opnode GPRnopc:$Rn, so_reg_reg:$shift)]>,
1487 Sched<[WriteCMPsr, ReadALU]> {
1492 let Inst{19-16} = Rn;
1493 let Inst{15-12} = 0b0000;
1494 let Inst{11-8} = shift{11-8};
1496 let Inst{6-5} = shift{6-5};
1498 let Inst{3-0} = shift{3-0};
1500 let Unpredictable{15-12} = 0b1111;
1506 /// AI_ext_rrot - A unary operation with two forms: one whose operand is a
1507 /// register and one whose operand is a register rotated by 8/16/24.
1508 /// FIXME: Remove the 'r' variant. Its rot_imm is zero.
1509 class AI_ext_rrot<bits<8> opcod, string opc, PatFrag opnode>
1510 : AExtI<opcod, (outs GPRnopc:$Rd), (ins GPRnopc:$Rm, rot_imm:$rot),
1511 IIC_iEXTr, opc, "\t$Rd, $Rm$rot",
1512 [(set GPRnopc:$Rd, (opnode (rotr GPRnopc:$Rm, rot_imm:$rot)))]>,
1513 Requires<[IsARM, HasV6]>, Sched<[WriteALUsi]> {
1517 let Inst{19-16} = 0b1111;
1518 let Inst{15-12} = Rd;
1519 let Inst{11-10} = rot;
1523 class AI_ext_rrot_np<bits<8> opcod, string opc>
1524 : AExtI<opcod, (outs GPRnopc:$Rd), (ins GPRnopc:$Rm, rot_imm:$rot),
1525 IIC_iEXTr, opc, "\t$Rd, $Rm$rot", []>,
1526 Requires<[IsARM, HasV6]>, Sched<[WriteALUsi]> {
1528 let Inst{19-16} = 0b1111;
1529 let Inst{11-10} = rot;
1532 /// AI_exta_rrot - A binary operation with two forms: one whose operand is a
1533 /// register and one whose operand is a register rotated by 8/16/24.
1534 class AI_exta_rrot<bits<8> opcod, string opc, PatFrag opnode>
1535 : AExtI<opcod, (outs GPRnopc:$Rd), (ins GPR:$Rn, GPRnopc:$Rm, rot_imm:$rot),
1536 IIC_iEXTAr, opc, "\t$Rd, $Rn, $Rm$rot",
1537 [(set GPRnopc:$Rd, (opnode GPR:$Rn,
1538 (rotr GPRnopc:$Rm, rot_imm:$rot)))]>,
1539 Requires<[IsARM, HasV6]>, Sched<[WriteALUsr]> {
1544 let Inst{19-16} = Rn;
1545 let Inst{15-12} = Rd;
1546 let Inst{11-10} = rot;
1547 let Inst{9-4} = 0b000111;
1551 class AI_exta_rrot_np<bits<8> opcod, string opc>
1552 : AExtI<opcod, (outs GPRnopc:$Rd), (ins GPR:$Rn, GPRnopc:$Rm, rot_imm:$rot),
1553 IIC_iEXTAr, opc, "\t$Rd, $Rn, $Rm$rot", []>,
1554 Requires<[IsARM, HasV6]>, Sched<[WriteALUsr]> {
1557 let Inst{19-16} = Rn;
1558 let Inst{11-10} = rot;
1561 /// AI1_adde_sube_irs - Define instructions and patterns for adde and sube.
1562 let TwoOperandAliasConstraint = "$Rn = $Rd" in
1563 multiclass AI1_adde_sube_irs<bits<4> opcod, string opc, PatFrag opnode,
1564 bit Commutable = 0> {
1565 let hasPostISelHook = 1, Defs = [CPSR], Uses = [CPSR] in {
1566 def ri : AsI1<opcod, (outs GPR:$Rd), (ins GPR:$Rn, mod_imm:$imm),
1567 DPFrm, IIC_iALUi, opc, "\t$Rd, $Rn, $imm",
1568 [(set GPR:$Rd, CPSR, (opnode GPR:$Rn, mod_imm:$imm, CPSR))]>,
1570 Sched<[WriteALU, ReadALU]> {
1575 let Inst{15-12} = Rd;
1576 let Inst{19-16} = Rn;
1577 let Inst{11-0} = imm;
1579 def rr : AsI1<opcod, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm),
1580 DPFrm, IIC_iALUr, opc, "\t$Rd, $Rn, $Rm",
1581 [(set GPR:$Rd, CPSR, (opnode GPR:$Rn, GPR:$Rm, CPSR))]>,
1583 Sched<[WriteALU, ReadALU, ReadALU]> {
1587 let Inst{11-4} = 0b00000000;
1589 let isCommutable = Commutable;
1591 let Inst{15-12} = Rd;
1592 let Inst{19-16} = Rn;
1594 def rsi : AsI1<opcod, (outs GPR:$Rd),
1595 (ins GPR:$Rn, so_reg_imm:$shift),
1596 DPSoRegImmFrm, IIC_iALUsr, opc, "\t$Rd, $Rn, $shift",
1597 [(set GPR:$Rd, CPSR, (opnode GPR:$Rn, so_reg_imm:$shift, CPSR))]>,
1599 Sched<[WriteALUsi, ReadALU]> {
1604 let Inst{19-16} = Rn;
1605 let Inst{15-12} = Rd;
1606 let Inst{11-5} = shift{11-5};
1608 let Inst{3-0} = shift{3-0};
1610 def rsr : AsI1<opcod, (outs GPRnopc:$Rd),
1611 (ins GPRnopc:$Rn, so_reg_reg:$shift),
1612 DPSoRegRegFrm, IIC_iALUsr, opc, "\t$Rd, $Rn, $shift",
1613 [(set GPRnopc:$Rd, CPSR,
1614 (opnode GPRnopc:$Rn, so_reg_reg:$shift, CPSR))]>,
1616 Sched<[WriteALUsr, ReadALUsr]> {
1621 let Inst{19-16} = Rn;
1622 let Inst{15-12} = Rd;
1623 let Inst{11-8} = shift{11-8};
1625 let Inst{6-5} = shift{6-5};
1627 let Inst{3-0} = shift{3-0};
1632 /// AI1_rsc_irs - Define instructions and patterns for rsc
1633 let TwoOperandAliasConstraint = "$Rn = $Rd" in
1634 multiclass AI1_rsc_irs<bits<4> opcod, string opc, PatFrag opnode> {
1635 let hasPostISelHook = 1, Defs = [CPSR], Uses = [CPSR] in {
1636 def ri : AsI1<opcod, (outs GPR:$Rd), (ins GPR:$Rn, mod_imm:$imm),
1637 DPFrm, IIC_iALUi, opc, "\t$Rd, $Rn, $imm",
1638 [(set GPR:$Rd, CPSR, (opnode mod_imm:$imm, GPR:$Rn, CPSR))]>,
1640 Sched<[WriteALU, ReadALU]> {
1645 let Inst{15-12} = Rd;
1646 let Inst{19-16} = Rn;
1647 let Inst{11-0} = imm;
1649 def rr : AsI1<opcod, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm),
1650 DPFrm, IIC_iALUr, opc, "\t$Rd, $Rn, $Rm",
1651 [/* pattern left blank */]>,
1652 Sched<[WriteALU, ReadALU, ReadALU]> {
1656 let Inst{11-4} = 0b00000000;
1659 let Inst{15-12} = Rd;
1660 let Inst{19-16} = Rn;
1662 def rsi : AsI1<opcod, (outs GPR:$Rd), (ins GPR:$Rn, so_reg_imm:$shift),
1663 DPSoRegImmFrm, IIC_iALUsr, opc, "\t$Rd, $Rn, $shift",
1664 [(set GPR:$Rd, CPSR, (opnode so_reg_imm:$shift, GPR:$Rn, CPSR))]>,
1666 Sched<[WriteALUsi, ReadALU]> {
1671 let Inst{19-16} = Rn;
1672 let Inst{15-12} = Rd;
1673 let Inst{11-5} = shift{11-5};
1675 let Inst{3-0} = shift{3-0};
1677 def rsr : AsI1<opcod, (outs GPR:$Rd), (ins GPR:$Rn, so_reg_reg:$shift),
1678 DPSoRegRegFrm, IIC_iALUsr, opc, "\t$Rd, $Rn, $shift",
1679 [(set GPR:$Rd, CPSR, (opnode so_reg_reg:$shift, GPR:$Rn, CPSR))]>,
1681 Sched<[WriteALUsr, ReadALUsr]> {
1686 let Inst{19-16} = Rn;
1687 let Inst{15-12} = Rd;
1688 let Inst{11-8} = shift{11-8};
1690 let Inst{6-5} = shift{6-5};
1692 let Inst{3-0} = shift{3-0};
1697 let canFoldAsLoad = 1, isReMaterializable = 1 in {
1698 multiclass AI_ldr1<bit isByte, string opc, InstrItinClass iii,
1699 InstrItinClass iir, PatFrag opnode> {
1700 // Note: We use the complex addrmode_imm12 rather than just an input
1701 // GPR and a constrained immediate so that we can use this to match
1702 // frame index references and avoid matching constant pool references.
1703 def i12: AI2ldst<0b010, 1, isByte, (outs GPR:$Rt), (ins addrmode_imm12:$addr),
1704 AddrMode_i12, LdFrm, iii, opc, "\t$Rt, $addr",
1705 [(set GPR:$Rt, (opnode addrmode_imm12:$addr))]> {
1708 let Inst{23} = addr{12}; // U (add = ('U' == 1))
1709 let Inst{19-16} = addr{16-13}; // Rn
1710 let Inst{15-12} = Rt;
1711 let Inst{11-0} = addr{11-0}; // imm12
1713 def rs : AI2ldst<0b011, 1, isByte, (outs GPR:$Rt), (ins ldst_so_reg:$shift),
1714 AddrModeNone, LdFrm, iir, opc, "\t$Rt, $shift",
1715 [(set GPR:$Rt, (opnode ldst_so_reg:$shift))]> {
1718 let shift{4} = 0; // Inst{4} = 0
1719 let Inst{23} = shift{12}; // U (add = ('U' == 1))
1720 let Inst{19-16} = shift{16-13}; // Rn
1721 let Inst{15-12} = Rt;
1722 let Inst{11-0} = shift{11-0};
1727 let canFoldAsLoad = 1, isReMaterializable = 1 in {
1728 multiclass AI_ldr1nopc<bit isByte, string opc, InstrItinClass iii,
1729 InstrItinClass iir, PatFrag opnode> {
1730 // Note: We use the complex addrmode_imm12 rather than just an input
1731 // GPR and a constrained immediate so that we can use this to match
1732 // frame index references and avoid matching constant pool references.
1733 def i12: AI2ldst<0b010, 1, isByte, (outs GPRnopc:$Rt),
1734 (ins addrmode_imm12:$addr),
1735 AddrMode_i12, LdFrm, iii, opc, "\t$Rt, $addr",
1736 [(set GPRnopc:$Rt, (opnode addrmode_imm12:$addr))]> {
1739 let Inst{23} = addr{12}; // U (add = ('U' == 1))
1740 let Inst{19-16} = addr{16-13}; // Rn
1741 let Inst{15-12} = Rt;
1742 let Inst{11-0} = addr{11-0}; // imm12
1744 def rs : AI2ldst<0b011, 1, isByte, (outs GPRnopc:$Rt),
1745 (ins ldst_so_reg:$shift),
1746 AddrModeNone, LdFrm, iir, opc, "\t$Rt, $shift",
1747 [(set GPRnopc:$Rt, (opnode ldst_so_reg:$shift))]> {
1750 let shift{4} = 0; // Inst{4} = 0
1751 let Inst{23} = shift{12}; // U (add = ('U' == 1))
1752 let Inst{19-16} = shift{16-13}; // Rn
1753 let Inst{15-12} = Rt;
1754 let Inst{11-0} = shift{11-0};
1760 multiclass AI_str1<bit isByte, string opc, InstrItinClass iii,
1761 InstrItinClass iir, PatFrag opnode> {
1762 // Note: We use the complex addrmode_imm12 rather than just an input
1763 // GPR and a constrained immediate so that we can use this to match
1764 // frame index references and avoid matching constant pool references.
1765 def i12 : AI2ldst<0b010, 0, isByte, (outs),
1766 (ins GPR:$Rt, addrmode_imm12:$addr),
1767 AddrMode_i12, StFrm, iii, opc, "\t$Rt, $addr",
1768 [(opnode GPR:$Rt, addrmode_imm12:$addr)]> {
1771 let Inst{23} = addr{12}; // U (add = ('U' == 1))
1772 let Inst{19-16} = addr{16-13}; // Rn
1773 let Inst{15-12} = Rt;
1774 let Inst{11-0} = addr{11-0}; // imm12
1776 def rs : AI2ldst<0b011, 0, isByte, (outs), (ins GPR:$Rt, ldst_so_reg:$shift),
1777 AddrModeNone, StFrm, iir, opc, "\t$Rt, $shift",
1778 [(opnode GPR:$Rt, ldst_so_reg:$shift)]> {
1781 let shift{4} = 0; // Inst{4} = 0
1782 let Inst{23} = shift{12}; // U (add = ('U' == 1))
1783 let Inst{19-16} = shift{16-13}; // Rn
1784 let Inst{15-12} = Rt;
1785 let Inst{11-0} = shift{11-0};
1789 multiclass AI_str1nopc<bit isByte, string opc, InstrItinClass iii,
1790 InstrItinClass iir, PatFrag opnode> {
1791 // Note: We use the complex addrmode_imm12 rather than just an input
1792 // GPR and a constrained immediate so that we can use this to match
1793 // frame index references and avoid matching constant pool references.
1794 def i12 : AI2ldst<0b010, 0, isByte, (outs),
1795 (ins GPRnopc:$Rt, addrmode_imm12:$addr),
1796 AddrMode_i12, StFrm, iii, opc, "\t$Rt, $addr",
1797 [(opnode GPRnopc:$Rt, addrmode_imm12:$addr)]> {
1800 let Inst{23} = addr{12}; // U (add = ('U' == 1))
1801 let Inst{19-16} = addr{16-13}; // Rn
1802 let Inst{15-12} = Rt;
1803 let Inst{11-0} = addr{11-0}; // imm12
1805 def rs : AI2ldst<0b011, 0, isByte, (outs),
1806 (ins GPRnopc:$Rt, ldst_so_reg:$shift),
1807 AddrModeNone, StFrm, iir, opc, "\t$Rt, $shift",
1808 [(opnode GPRnopc:$Rt, ldst_so_reg:$shift)]> {
1811 let shift{4} = 0; // Inst{4} = 0
1812 let Inst{23} = shift{12}; // U (add = ('U' == 1))
1813 let Inst{19-16} = shift{16-13}; // Rn
1814 let Inst{15-12} = Rt;
1815 let Inst{11-0} = shift{11-0};
1820 //===----------------------------------------------------------------------===//
1822 //===----------------------------------------------------------------------===//
1824 //===----------------------------------------------------------------------===//
1825 // Miscellaneous Instructions.
1828 /// CONSTPOOL_ENTRY - This instruction represents a floating constant pool in
1829 /// the function. The first operand is the ID# for this instruction, the second
1830 /// is the index into the MachineConstantPool that this is, the third is the
1831 /// size in bytes of this constant pool entry.
1832 let hasSideEffects = 0, isNotDuplicable = 1 in
1833 def CONSTPOOL_ENTRY :
1834 PseudoInst<(outs), (ins cpinst_operand:$instid, cpinst_operand:$cpidx,
1835 i32imm:$size), NoItinerary, []>;
1837 // FIXME: Marking these as hasSideEffects is necessary to prevent machine DCE
1838 // from removing one half of the matched pairs. That breaks PEI, which assumes
1839 // these will always be in pairs, and asserts if it finds otherwise. Better way?
1840 let Defs = [SP], Uses = [SP], hasSideEffects = 1 in {
1841 def ADJCALLSTACKUP :
1842 PseudoInst<(outs), (ins i32imm:$amt1, i32imm:$amt2, pred:$p), NoItinerary,
1843 [(ARMcallseq_end timm:$amt1, timm:$amt2)]>;
1845 def ADJCALLSTACKDOWN :
1846 PseudoInst<(outs), (ins i32imm:$amt, pred:$p), NoItinerary,
1847 [(ARMcallseq_start timm:$amt)]>;
1850 def HINT : AI<(outs), (ins imm0_239:$imm), MiscFrm, NoItinerary,
1851 "hint", "\t$imm", [(int_arm_hint imm0_239:$imm)]>,
1852 Requires<[IsARM, HasV6]> {
1854 let Inst{27-8} = 0b00110010000011110000;
1855 let Inst{7-0} = imm;
1858 def : InstAlias<"nop$p", (HINT 0, pred:$p)>, Requires<[IsARM, HasV6K]>;
1859 def : InstAlias<"yield$p", (HINT 1, pred:$p)>, Requires<[IsARM, HasV6K]>;
1860 def : InstAlias<"wfe$p", (HINT 2, pred:$p)>, Requires<[IsARM, HasV6K]>;
1861 def : InstAlias<"wfi$p", (HINT 3, pred:$p)>, Requires<[IsARM, HasV6K]>;
1862 def : InstAlias<"sev$p", (HINT 4, pred:$p)>, Requires<[IsARM, HasV6K]>;
1863 def : InstAlias<"sevl$p", (HINT 5, pred:$p)>, Requires<[IsARM, HasV8]>;
1865 def SEL : AI<(outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm), DPFrm, NoItinerary, "sel",
1866 "\t$Rd, $Rn, $Rm", []>, Requires<[IsARM, HasV6]> {
1871 let Inst{15-12} = Rd;
1872 let Inst{19-16} = Rn;
1873 let Inst{27-20} = 0b01101000;
1874 let Inst{7-4} = 0b1011;
1875 let Inst{11-8} = 0b1111;
1876 let Unpredictable{11-8} = 0b1111;
1879 // The 16-bit operand $val can be used by a debugger to store more information
1880 // about the breakpoint.
1881 def BKPT : AInoP<(outs), (ins imm0_65535:$val), MiscFrm, NoItinerary,
1882 "bkpt", "\t$val", []>, Requires<[IsARM]> {
1884 let Inst{3-0} = val{3-0};
1885 let Inst{19-8} = val{15-4};
1886 let Inst{27-20} = 0b00010010;
1887 let Inst{31-28} = 0xe; // AL
1888 let Inst{7-4} = 0b0111;
1890 // default immediate for breakpoint mnemonic
1891 def : InstAlias<"bkpt", (BKPT 0)>, Requires<[IsARM]>;
1893 def HLT : AInoP<(outs), (ins imm0_65535:$val), MiscFrm, NoItinerary,
1894 "hlt", "\t$val", []>, Requires<[IsARM, HasV8]> {
1896 let Inst{3-0} = val{3-0};
1897 let Inst{19-8} = val{15-4};
1898 let Inst{27-20} = 0b00010000;
1899 let Inst{31-28} = 0xe; // AL
1900 let Inst{7-4} = 0b0111;
1903 // Change Processor State
1904 // FIXME: We should use InstAlias to handle the optional operands.
1905 class CPS<dag iops, string asm_ops>
1906 : AXI<(outs), iops, MiscFrm, NoItinerary, !strconcat("cps", asm_ops),
1907 []>, Requires<[IsARM]> {
1913 let Inst{31-28} = 0b1111;
1914 let Inst{27-20} = 0b00010000;
1915 let Inst{19-18} = imod;
1916 let Inst{17} = M; // Enabled if mode is set;
1917 let Inst{16-9} = 0b00000000;
1918 let Inst{8-6} = iflags;
1920 let Inst{4-0} = mode;
1923 let DecoderMethod = "DecodeCPSInstruction" in {
1925 def CPS3p : CPS<(ins imod_op:$imod, iflags_op:$iflags, imm0_31:$mode),
1926 "$imod\t$iflags, $mode">;
1927 let mode = 0, M = 0 in
1928 def CPS2p : CPS<(ins imod_op:$imod, iflags_op:$iflags), "$imod\t$iflags">;
1930 let imod = 0, iflags = 0, M = 1 in
1931 def CPS1p : CPS<(ins imm0_31:$mode), "\t$mode">;
1934 // Preload signals the memory system of possible future data/instruction access.
1935 multiclass APreLoad<bits<1> read, bits<1> data, string opc> {
1937 def i12 : AXIM<(outs), (ins addrmode_imm12:$addr), AddrMode_i12, MiscFrm,
1938 IIC_Preload, !strconcat(opc, "\t$addr"),
1939 [(ARMPreload addrmode_imm12:$addr, (i32 read), (i32 data))]>,
1940 Sched<[WritePreLd]> {
1943 let Inst{31-26} = 0b111101;
1944 let Inst{25} = 0; // 0 for immediate form
1945 let Inst{24} = data;
1946 let Inst{23} = addr{12}; // U (add = ('U' == 1))
1947 let Inst{22} = read;
1948 let Inst{21-20} = 0b01;
1949 let Inst{19-16} = addr{16-13}; // Rn
1950 let Inst{15-12} = 0b1111;
1951 let Inst{11-0} = addr{11-0}; // imm12
1954 def rs : AXI<(outs), (ins ldst_so_reg:$shift), MiscFrm, IIC_Preload,
1955 !strconcat(opc, "\t$shift"),
1956 [(ARMPreload ldst_so_reg:$shift, (i32 read), (i32 data))]>,
1957 Sched<[WritePreLd]> {
1959 let Inst{31-26} = 0b111101;
1960 let Inst{25} = 1; // 1 for register form
1961 let Inst{24} = data;
1962 let Inst{23} = shift{12}; // U (add = ('U' == 1))
1963 let Inst{22} = read;
1964 let Inst{21-20} = 0b01;
1965 let Inst{19-16} = shift{16-13}; // Rn
1966 let Inst{15-12} = 0b1111;
1967 let Inst{11-0} = shift{11-0};
1972 defm PLD : APreLoad<1, 1, "pld">, Requires<[IsARM]>;
1973 defm PLDW : APreLoad<0, 1, "pldw">, Requires<[IsARM,HasV7,HasMP]>;
1974 defm PLI : APreLoad<1, 0, "pli">, Requires<[IsARM,HasV7]>;
1976 def SETEND : AXI<(outs), (ins setend_op:$end), MiscFrm, NoItinerary,
1977 "setend\t$end", []>, Requires<[IsARM]>, Deprecated<HasV8Ops> {
1979 let Inst{31-10} = 0b1111000100000001000000;
1984 def DBG : AI<(outs), (ins imm0_15:$opt), MiscFrm, NoItinerary, "dbg", "\t$opt",
1985 [(int_arm_dbg imm0_15:$opt)]>, Requires<[IsARM, HasV7]> {
1987 let Inst{27-4} = 0b001100100000111100001111;
1988 let Inst{3-0} = opt;
1991 // A8.8.247 UDF - Undefined (Encoding A1)
1992 def UDF : AInoP<(outs), (ins imm0_65535:$imm16), MiscFrm, NoItinerary,
1993 "udf", "\t$imm16", [(int_arm_undefined imm0_65535:$imm16)]> {
1995 let Inst{31-28} = 0b1110; // AL
1996 let Inst{27-25} = 0b011;
1997 let Inst{24-20} = 0b11111;
1998 let Inst{19-8} = imm16{15-4};
1999 let Inst{7-4} = 0b1111;
2000 let Inst{3-0} = imm16{3-0};
2004 * A5.4 Permanently UNDEFINED instructions.
2006 * For most targets use UDF #65006, for which the OS will generate SIGTRAP.
2007 * Other UDF encodings generate SIGILL.
2009 * NaCl's OS instead chooses an ARM UDF encoding that's also a UDF in Thumb.
2011 * 1110 0111 1111 iiii iiii iiii 1111 iiii
2013 * 1101 1110 iiii iiii
2014 * It uses the following encoding:
2015 * 1110 0111 1111 1110 1101 1110 1111 0000
2016 * - In ARM: UDF #60896;
2017 * - In Thumb: UDF #254 followed by a branch-to-self.
2019 let isBarrier = 1, isTerminator = 1 in
2020 def TRAPNaCl : AXI<(outs), (ins), MiscFrm, NoItinerary,
2022 Requires<[IsARM,UseNaClTrap]> {
2023 let Inst = 0xe7fedef0;
2025 let isBarrier = 1, isTerminator = 1 in
2026 def TRAP : AXI<(outs), (ins), MiscFrm, NoItinerary,
2028 Requires<[IsARM,DontUseNaClTrap]> {
2029 let Inst = 0xe7ffdefe;
2032 // Address computation and loads and stores in PIC mode.
2033 let isNotDuplicable = 1 in {
2034 def PICADD : ARMPseudoInst<(outs GPR:$dst), (ins GPR:$a, pclabel:$cp, pred:$p),
2036 [(set GPR:$dst, (ARMpic_add GPR:$a, imm:$cp))]>,
2037 Sched<[WriteALU, ReadALU]>;
2039 let AddedComplexity = 10 in {
2040 def PICLDR : ARMPseudoInst<(outs GPR:$dst), (ins addrmodepc:$addr, pred:$p),
2042 [(set GPR:$dst, (load addrmodepc:$addr))]>;
2044 def PICLDRH : ARMPseudoInst<(outs GPR:$Rt), (ins addrmodepc:$addr, pred:$p),
2046 [(set GPR:$Rt, (zextloadi16 addrmodepc:$addr))]>;
2048 def PICLDRB : ARMPseudoInst<(outs GPR:$Rt), (ins addrmodepc:$addr, pred:$p),
2050 [(set GPR:$Rt, (zextloadi8 addrmodepc:$addr))]>;
2052 def PICLDRSH : ARMPseudoInst<(outs GPR:$Rt), (ins addrmodepc:$addr, pred:$p),
2054 [(set GPR:$Rt, (sextloadi16 addrmodepc:$addr))]>;
2056 def PICLDRSB : ARMPseudoInst<(outs GPR:$Rt), (ins addrmodepc:$addr, pred:$p),
2058 [(set GPR:$Rt, (sextloadi8 addrmodepc:$addr))]>;
2060 let AddedComplexity = 10 in {
2061 def PICSTR : ARMPseudoInst<(outs), (ins GPR:$src, addrmodepc:$addr, pred:$p),
2062 4, IIC_iStore_r, [(store GPR:$src, addrmodepc:$addr)]>;
2064 def PICSTRH : ARMPseudoInst<(outs), (ins GPR:$src, addrmodepc:$addr, pred:$p),
2065 4, IIC_iStore_bh_r, [(truncstorei16 GPR:$src,
2066 addrmodepc:$addr)]>;
2068 def PICSTRB : ARMPseudoInst<(outs), (ins GPR:$src, addrmodepc:$addr, pred:$p),
2069 4, IIC_iStore_bh_r, [(truncstorei8 GPR:$src, addrmodepc:$addr)]>;
2071 } // isNotDuplicable = 1
2074 // LEApcrel - Load a pc-relative address into a register without offending the
2076 let hasSideEffects = 0, isReMaterializable = 1 in
2077 // The 'adr' mnemonic encodes differently if the label is before or after
2078 // the instruction. The {24-21} opcode bits are set by the fixup, as we don't
2079 // know until then which form of the instruction will be used.
2080 def ADR : AI1<{0,?,?,0}, (outs GPR:$Rd), (ins adrlabel:$label),
2081 MiscFrm, IIC_iALUi, "adr", "\t$Rd, $label", []>,
2082 Sched<[WriteALU, ReadALU]> {
2085 let Inst{27-25} = 0b001;
2087 let Inst{23-22} = label{13-12};
2090 let Inst{19-16} = 0b1111;
2091 let Inst{15-12} = Rd;
2092 let Inst{11-0} = label{11-0};
2095 let hasSideEffects = 1 in {
2096 def LEApcrel : ARMPseudoInst<(outs GPR:$Rd), (ins i32imm:$label, pred:$p),
2097 4, IIC_iALUi, []>, Sched<[WriteALU, ReadALU]>;
2099 def LEApcrelJT : ARMPseudoInst<(outs GPR:$Rd),
2100 (ins i32imm:$label, pred:$p),
2101 4, IIC_iALUi, []>, Sched<[WriteALU, ReadALU]>;
2104 //===----------------------------------------------------------------------===//
2105 // Control Flow Instructions.
2108 let isReturn = 1, isTerminator = 1, isBarrier = 1 in {
2110 def BX_RET : AI<(outs), (ins), BrMiscFrm, IIC_Br,
2111 "bx", "\tlr", [(ARMretflag)]>,
2112 Requires<[IsARM, HasV4T]>, Sched<[WriteBr]> {
2113 let Inst{27-0} = 0b0001001011111111111100011110;
2117 def MOVPCLR : AI<(outs), (ins), BrMiscFrm, IIC_Br,
2118 "mov", "\tpc, lr", [(ARMretflag)]>,
2119 Requires<[IsARM, NoV4T]>, Sched<[WriteBr]> {
2120 let Inst{27-0} = 0b0001101000001111000000001110;
2123 // Exception return: N.b. doesn't set CPSR as far as we're concerned (it sets
2124 // the user-space one).
2125 def SUBS_PC_LR : ARMPseudoInst<(outs), (ins i32imm:$offset, pred:$p),
2127 [(ARMintretflag imm:$offset)]>;
2130 // Indirect branches
2131 let isBranch = 1, isTerminator = 1, isBarrier = 1, isIndirectBranch = 1 in {
2133 def BX : AXI<(outs), (ins GPR:$dst), BrMiscFrm, IIC_Br, "bx\t$dst",
2134 [(brind GPR:$dst)]>,
2135 Requires<[IsARM, HasV4T]>, Sched<[WriteBr]> {
2137 let Inst{31-4} = 0b1110000100101111111111110001;
2138 let Inst{3-0} = dst;
2141 def BX_pred : AI<(outs), (ins GPR:$dst), BrMiscFrm, IIC_Br,
2142 "bx", "\t$dst", [/* pattern left blank */]>,
2143 Requires<[IsARM, HasV4T]>, Sched<[WriteBr]> {
2145 let Inst{27-4} = 0b000100101111111111110001;
2146 let Inst{3-0} = dst;
2150 // SP is marked as a use to prevent stack-pointer assignments that appear
2151 // immediately before calls from potentially appearing dead.
2153 // FIXME: Do we really need a non-predicated version? If so, it should
2154 // at least be a pseudo instruction expanding to the predicated version
2155 // at MC lowering time.
2156 Defs = [LR], Uses = [SP] in {
2157 def BL : ABXI<0b1011, (outs), (ins bl_target:$func),
2158 IIC_Br, "bl\t$func",
2159 [(ARMcall tglobaladdr:$func)]>,
2160 Requires<[IsARM]>, Sched<[WriteBrL]> {
2161 let Inst{31-28} = 0b1110;
2163 let Inst{23-0} = func;
2164 let DecoderMethod = "DecodeBranchImmInstruction";
2167 def BL_pred : ABI<0b1011, (outs), (ins bl_target:$func),
2168 IIC_Br, "bl", "\t$func",
2169 [(ARMcall_pred tglobaladdr:$func)]>,
2170 Requires<[IsARM]>, Sched<[WriteBrL]> {
2172 let Inst{23-0} = func;
2173 let DecoderMethod = "DecodeBranchImmInstruction";
2177 def BLX : AXI<(outs), (ins GPR:$func), BrMiscFrm,
2178 IIC_Br, "blx\t$func",
2179 [(ARMcall GPR:$func)]>,
2180 Requires<[IsARM, HasV5T]>, Sched<[WriteBrL]> {
2182 let Inst{31-4} = 0b1110000100101111111111110011;
2183 let Inst{3-0} = func;
2186 def BLX_pred : AI<(outs), (ins GPR:$func), BrMiscFrm,
2187 IIC_Br, "blx", "\t$func",
2188 [(ARMcall_pred GPR:$func)]>,
2189 Requires<[IsARM, HasV5T]>, Sched<[WriteBrL]> {
2191 let Inst{27-4} = 0b000100101111111111110011;
2192 let Inst{3-0} = func;
2196 // Note: Restrict $func to the tGPR regclass to prevent it being in LR.
2197 def BX_CALL : ARMPseudoInst<(outs), (ins tGPR:$func),
2198 8, IIC_Br, [(ARMcall_nolink tGPR:$func)]>,
2199 Requires<[IsARM, HasV4T]>, Sched<[WriteBr]>;
2202 def BMOVPCRX_CALL : ARMPseudoInst<(outs), (ins tGPR:$func),
2203 8, IIC_Br, [(ARMcall_nolink tGPR:$func)]>,
2204 Requires<[IsARM, NoV4T]>, Sched<[WriteBr]>;
2206 // mov lr, pc; b if callee is marked noreturn to avoid confusing the
2207 // return stack predictor.
2208 def BMOVPCB_CALL : ARMPseudoInst<(outs), (ins bl_target:$func),
2209 8, IIC_Br, [(ARMcall_nolink tglobaladdr:$func)]>,
2210 Requires<[IsARM]>, Sched<[WriteBr]>;
2213 let isBranch = 1, isTerminator = 1 in {
2214 // FIXME: should be able to write a pattern for ARMBrcond, but can't use
2215 // a two-value operand where a dag node expects two operands. :(
2216 def Bcc : ABI<0b1010, (outs), (ins br_target:$target),
2217 IIC_Br, "b", "\t$target",
2218 [/*(ARMbrcond bb:$target, imm:$cc, CCR:$ccr)*/]>,
2221 let Inst{23-0} = target;
2222 let DecoderMethod = "DecodeBranchImmInstruction";
2225 let isBarrier = 1 in {
2226 // B is "predicable" since it's just a Bcc with an 'always' condition.
2227 let isPredicable = 1 in
2228 // FIXME: We shouldn't need this pseudo at all. Just using Bcc directly
2229 // should be sufficient.
2230 // FIXME: Is B really a Barrier? That doesn't seem right.
2231 def B : ARMPseudoExpand<(outs), (ins br_target:$target), 4, IIC_Br,
2232 [(br bb:$target)], (Bcc br_target:$target, (ops 14, zero_reg))>,
2235 let isNotDuplicable = 1, isIndirectBranch = 1 in {
2236 def BR_JTr : ARMPseudoInst<(outs),
2237 (ins GPR:$target, i32imm:$jt),
2239 [(ARMbrjt GPR:$target, tjumptable:$jt)]>,
2241 // FIXME: This shouldn't use the generic "addrmode2," but rather be split
2242 // into i12 and rs suffixed versions.
2243 def BR_JTm : ARMPseudoInst<(outs),
2244 (ins addrmode2:$target, i32imm:$jt),
2246 [(ARMbrjt (i32 (load addrmode2:$target)),
2247 tjumptable:$jt)]>, Sched<[WriteBrTbl]>;
2248 def BR_JTadd : ARMPseudoInst<(outs),
2249 (ins GPR:$target, GPR:$idx, i32imm:$jt),
2251 [(ARMbrjt (add GPR:$target, GPR:$idx), tjumptable:$jt)]>,
2252 Sched<[WriteBrTbl]>;
2253 } // isNotDuplicable = 1, isIndirectBranch = 1
2259 def BLXi : AXI<(outs), (ins blx_target:$target), BrMiscFrm, NoItinerary,
2260 "blx\t$target", []>,
2261 Requires<[IsARM, HasV5T]>, Sched<[WriteBrL]> {
2262 let Inst{31-25} = 0b1111101;
2264 let Inst{23-0} = target{24-1};
2265 let Inst{24} = target{0};
2269 // Branch and Exchange Jazelle
2270 def BXJ : ABI<0b0001, (outs), (ins GPR:$func), NoItinerary, "bxj", "\t$func",
2271 [/* pattern left blank */]>, Sched<[WriteBr]> {
2273 let Inst{23-20} = 0b0010;
2274 let Inst{19-8} = 0xfff;
2275 let Inst{7-4} = 0b0010;
2276 let Inst{3-0} = func;
2282 let isCall = 1, isTerminator = 1, isReturn = 1, isBarrier = 1, Uses = [SP] in {
2283 def TCRETURNdi : PseudoInst<(outs), (ins i32imm:$dst), IIC_Br, []>,
2286 def TCRETURNri : PseudoInst<(outs), (ins tcGPR:$dst), IIC_Br, []>,
2289 def TAILJMPd : ARMPseudoExpand<(outs), (ins br_target:$dst),
2291 (Bcc br_target:$dst, (ops 14, zero_reg))>,
2292 Requires<[IsARM]>, Sched<[WriteBr]>;
2294 def TAILJMPr : ARMPseudoExpand<(outs), (ins tcGPR:$dst),
2296 (BX GPR:$dst)>, Sched<[WriteBr]>,
2300 // Secure Monitor Call is a system instruction.
2301 def SMC : ABI<0b0001, (outs), (ins imm0_15:$opt), NoItinerary, "smc", "\t$opt",
2302 []>, Requires<[IsARM, HasTrustZone]> {
2304 let Inst{23-4} = 0b01100000000000000111;
2305 let Inst{3-0} = opt;
2308 // Supervisor Call (Software Interrupt)
2309 let isCall = 1, Uses = [SP] in {
2310 def SVC : ABI<0b1111, (outs), (ins imm24b:$svc), IIC_Br, "svc", "\t$svc", []>,
2313 let Inst{23-0} = svc;
2317 // Store Return State
2318 class SRSI<bit wb, string asm>
2319 : XI<(outs), (ins imm0_31:$mode), AddrModeNone, 4, IndexModeNone, BrFrm,
2320 NoItinerary, asm, "", []> {
2322 let Inst{31-28} = 0b1111;
2323 let Inst{27-25} = 0b100;
2327 let Inst{19-16} = 0b1101; // SP
2328 let Inst{15-5} = 0b00000101000;
2329 let Inst{4-0} = mode;
2332 def SRSDA : SRSI<0, "srsda\tsp, $mode"> {
2333 let Inst{24-23} = 0;
2335 def SRSDA_UPD : SRSI<1, "srsda\tsp!, $mode"> {
2336 let Inst{24-23} = 0;
2338 def SRSDB : SRSI<0, "srsdb\tsp, $mode"> {
2339 let Inst{24-23} = 0b10;
2341 def SRSDB_UPD : SRSI<1, "srsdb\tsp!, $mode"> {
2342 let Inst{24-23} = 0b10;
2344 def SRSIA : SRSI<0, "srsia\tsp, $mode"> {
2345 let Inst{24-23} = 0b01;
2347 def SRSIA_UPD : SRSI<1, "srsia\tsp!, $mode"> {
2348 let Inst{24-23} = 0b01;
2350 def SRSIB : SRSI<0, "srsib\tsp, $mode"> {
2351 let Inst{24-23} = 0b11;
2353 def SRSIB_UPD : SRSI<1, "srsib\tsp!, $mode"> {
2354 let Inst{24-23} = 0b11;
2357 def : ARMInstAlias<"srsda $mode", (SRSDA imm0_31:$mode)>;
2358 def : ARMInstAlias<"srsda $mode!", (SRSDA_UPD imm0_31:$mode)>;
2360 def : ARMInstAlias<"srsdb $mode", (SRSDB imm0_31:$mode)>;
2361 def : ARMInstAlias<"srsdb $mode!", (SRSDB_UPD imm0_31:$mode)>;
2363 def : ARMInstAlias<"srsia $mode", (SRSIA imm0_31:$mode)>;
2364 def : ARMInstAlias<"srsia $mode!", (SRSIA_UPD imm0_31:$mode)>;
2366 def : ARMInstAlias<"srsib $mode", (SRSIB imm0_31:$mode)>;
2367 def : ARMInstAlias<"srsib $mode!", (SRSIB_UPD imm0_31:$mode)>;
2369 // Return From Exception
2370 class RFEI<bit wb, string asm>
2371 : XI<(outs), (ins GPR:$Rn), AddrModeNone, 4, IndexModeNone, BrFrm,
2372 NoItinerary, asm, "", []> {
2374 let Inst{31-28} = 0b1111;
2375 let Inst{27-25} = 0b100;
2379 let Inst{19-16} = Rn;
2380 let Inst{15-0} = 0xa00;
2383 def RFEDA : RFEI<0, "rfeda\t$Rn"> {
2384 let Inst{24-23} = 0;
2386 def RFEDA_UPD : RFEI<1, "rfeda\t$Rn!"> {
2387 let Inst{24-23} = 0;
2389 def RFEDB : RFEI<0, "rfedb\t$Rn"> {
2390 let Inst{24-23} = 0b10;
2392 def RFEDB_UPD : RFEI<1, "rfedb\t$Rn!"> {
2393 let Inst{24-23} = 0b10;
2395 def RFEIA : RFEI<0, "rfeia\t$Rn"> {
2396 let Inst{24-23} = 0b01;
2398 def RFEIA_UPD : RFEI<1, "rfeia\t$Rn!"> {
2399 let Inst{24-23} = 0b01;
2401 def RFEIB : RFEI<0, "rfeib\t$Rn"> {
2402 let Inst{24-23} = 0b11;
2404 def RFEIB_UPD : RFEI<1, "rfeib\t$Rn!"> {
2405 let Inst{24-23} = 0b11;
2408 // Hypervisor Call is a system instruction
2410 def HVC : AInoP< (outs), (ins imm0_65535:$imm), BrFrm, NoItinerary,
2411 "hvc", "\t$imm", []>,
2412 Requires<[IsARM, HasVirtualization]> {
2415 // Even though HVC isn't predicable, it's encoding includes a condition field.
2416 // The instruction is undefined if the condition field is 0xf otherwise it is
2417 // unpredictable if it isn't condition AL (0xe).
2418 let Inst{31-28} = 0b1110;
2419 let Unpredictable{31-28} = 0b1111;
2420 let Inst{27-24} = 0b0001;
2421 let Inst{23-20} = 0b0100;
2422 let Inst{19-8} = imm{15-4};
2423 let Inst{7-4} = 0b0111;
2424 let Inst{3-0} = imm{3-0};
2428 // Return from exception in Hypervisor mode.
2429 let isReturn = 1, isBarrier = 1, isTerminator = 1, Defs = [PC] in
2430 def ERET : ABI<0b0001, (outs), (ins), NoItinerary, "eret", "", []>,
2431 Requires<[IsARM, HasVirtualization]> {
2432 let Inst{23-0} = 0b011000000000000001101110;
2435 //===----------------------------------------------------------------------===//
2436 // Load / Store Instructions.
2442 defm LDR : AI_ldr1<0, "ldr", IIC_iLoad_r, IIC_iLoad_si,
2443 UnOpFrag<(load node:$Src)>>;
2444 defm LDRB : AI_ldr1nopc<1, "ldrb", IIC_iLoad_bh_r, IIC_iLoad_bh_si,
2445 UnOpFrag<(zextloadi8 node:$Src)>>;
2446 defm STR : AI_str1<0, "str", IIC_iStore_r, IIC_iStore_si,
2447 BinOpFrag<(store node:$LHS, node:$RHS)>>;
2448 defm STRB : AI_str1nopc<1, "strb", IIC_iStore_bh_r, IIC_iStore_bh_si,
2449 BinOpFrag<(truncstorei8 node:$LHS, node:$RHS)>>;
2451 // Special LDR for loads from non-pc-relative constpools.
2452 let canFoldAsLoad = 1, mayLoad = 1, hasSideEffects = 0,
2453 isReMaterializable = 1, isCodeGenOnly = 1 in
2454 def LDRcp : AI2ldst<0b010, 1, 0, (outs GPR:$Rt), (ins addrmode_imm12:$addr),
2455 AddrMode_i12, LdFrm, IIC_iLoad_r, "ldr", "\t$Rt, $addr",
2459 let Inst{23} = addr{12}; // U (add = ('U' == 1))
2460 let Inst{19-16} = 0b1111;
2461 let Inst{15-12} = Rt;
2462 let Inst{11-0} = addr{11-0}; // imm12
2465 // Loads with zero extension
2466 def LDRH : AI3ld<0b1011, 1, (outs GPR:$Rt), (ins addrmode3:$addr), LdMiscFrm,
2467 IIC_iLoad_bh_r, "ldrh", "\t$Rt, $addr",
2468 [(set GPR:$Rt, (zextloadi16 addrmode3:$addr))]>;
2470 // Loads with sign extension
2471 def LDRSH : AI3ld<0b1111, 1, (outs GPR:$Rt), (ins addrmode3:$addr), LdMiscFrm,
2472 IIC_iLoad_bh_r, "ldrsh", "\t$Rt, $addr",
2473 [(set GPR:$Rt, (sextloadi16 addrmode3:$addr))]>;
2475 def LDRSB : AI3ld<0b1101, 1, (outs GPR:$Rt), (ins addrmode3:$addr), LdMiscFrm,
2476 IIC_iLoad_bh_r, "ldrsb", "\t$Rt, $addr",
2477 [(set GPR:$Rt, (sextloadi8 addrmode3:$addr))]>;
2479 let mayLoad = 1, hasSideEffects = 0, hasExtraDefRegAllocReq = 1 in {
2481 def LDRD : AI3ld<0b1101, 0, (outs GPR:$Rt, GPR:$Rt2), (ins addrmode3:$addr),
2482 LdMiscFrm, IIC_iLoad_d_r, "ldrd", "\t$Rt, $Rt2, $addr", []>,
2483 Requires<[IsARM, HasV5TE]>;
2486 def LDA : AIldracq<0b00, (outs GPR:$Rt), (ins addr_offset_none:$addr),
2487 NoItinerary, "lda", "\t$Rt, $addr", []>;
2488 def LDAB : AIldracq<0b10, (outs GPR:$Rt), (ins addr_offset_none:$addr),
2489 NoItinerary, "ldab", "\t$Rt, $addr", []>;
2490 def LDAH : AIldracq<0b11, (outs GPR:$Rt), (ins addr_offset_none:$addr),
2491 NoItinerary, "ldah", "\t$Rt, $addr", []>;
2494 multiclass AI2_ldridx<bit isByte, string opc,
2495 InstrItinClass iii, InstrItinClass iir> {
2496 def _PRE_IMM : AI2ldstidx<1, isByte, 1, (outs GPR:$Rt, GPR:$Rn_wb),
2497 (ins addrmode_imm12_pre:$addr), IndexModePre, LdFrm, iii,
2498 opc, "\t$Rt, $addr!", "$addr.base = $Rn_wb", []> {
2501 let Inst{23} = addr{12};
2502 let Inst{19-16} = addr{16-13};
2503 let Inst{11-0} = addr{11-0};
2504 let DecoderMethod = "DecodeLDRPreImm";
2507 def _PRE_REG : AI2ldstidx<1, isByte, 1, (outs GPR:$Rt, GPR:$Rn_wb),
2508 (ins ldst_so_reg:$addr), IndexModePre, LdFrm, iir,
2509 opc, "\t$Rt, $addr!", "$addr.base = $Rn_wb", []> {
2512 let Inst{23} = addr{12};
2513 let Inst{19-16} = addr{16-13};
2514 let Inst{11-0} = addr{11-0};
2516 let DecoderMethod = "DecodeLDRPreReg";
2519 def _POST_REG : AI2ldstidx<1, isByte, 0, (outs GPR:$Rt, GPR:$Rn_wb),
2520 (ins addr_offset_none:$addr, am2offset_reg:$offset),
2521 IndexModePost, LdFrm, iir,
2522 opc, "\t$Rt, $addr, $offset",
2523 "$addr.base = $Rn_wb", []> {
2529 let Inst{23} = offset{12};
2530 let Inst{19-16} = addr;
2531 let Inst{11-0} = offset{11-0};
2534 let DecoderMethod = "DecodeAddrMode2IdxInstruction";
2537 def _POST_IMM : AI2ldstidx<1, isByte, 0, (outs GPR:$Rt, GPR:$Rn_wb),
2538 (ins addr_offset_none:$addr, am2offset_imm:$offset),
2539 IndexModePost, LdFrm, iii,
2540 opc, "\t$Rt, $addr, $offset",
2541 "$addr.base = $Rn_wb", []> {
2547 let Inst{23} = offset{12};
2548 let Inst{19-16} = addr;
2549 let Inst{11-0} = offset{11-0};
2551 let DecoderMethod = "DecodeAddrMode2IdxInstruction";
2556 let mayLoad = 1, hasSideEffects = 0 in {
2557 // FIXME: for LDR_PRE_REG etc. the itineray should be either IIC_iLoad_ru or
2558 // IIC_iLoad_siu depending on whether it the offset register is shifted.
2559 defm LDR : AI2_ldridx<0, "ldr", IIC_iLoad_iu, IIC_iLoad_ru>;
2560 defm LDRB : AI2_ldridx<1, "ldrb", IIC_iLoad_bh_iu, IIC_iLoad_bh_ru>;
2563 multiclass AI3_ldridx<bits<4> op, string opc, InstrItinClass itin> {
2564 def _PRE : AI3ldstidx<op, 1, 1, (outs GPR:$Rt, GPR:$Rn_wb),
2565 (ins addrmode3_pre:$addr), IndexModePre,
2567 opc, "\t$Rt, $addr!", "$addr.base = $Rn_wb", []> {
2569 let Inst{23} = addr{8}; // U bit
2570 let Inst{22} = addr{13}; // 1 == imm8, 0 == Rm
2571 let Inst{19-16} = addr{12-9}; // Rn
2572 let Inst{11-8} = addr{7-4}; // imm7_4/zero
2573 let Inst{3-0} = addr{3-0}; // imm3_0/Rm
2574 let DecoderMethod = "DecodeAddrMode3Instruction";
2576 def _POST : AI3ldstidx<op, 1, 0, (outs GPR:$Rt, GPR:$Rn_wb),
2577 (ins addr_offset_none:$addr, am3offset:$offset),
2578 IndexModePost, LdMiscFrm, itin,
2579 opc, "\t$Rt, $addr, $offset", "$addr.base = $Rn_wb",
2583 let Inst{23} = offset{8}; // U bit
2584 let Inst{22} = offset{9}; // 1 == imm8, 0 == Rm
2585 let Inst{19-16} = addr;
2586 let Inst{11-8} = offset{7-4}; // imm7_4/zero
2587 let Inst{3-0} = offset{3-0}; // imm3_0/Rm
2588 let DecoderMethod = "DecodeAddrMode3Instruction";
2592 let mayLoad = 1, hasSideEffects = 0 in {
2593 defm LDRH : AI3_ldridx<0b1011, "ldrh", IIC_iLoad_bh_ru>;
2594 defm LDRSH : AI3_ldridx<0b1111, "ldrsh", IIC_iLoad_bh_ru>;
2595 defm LDRSB : AI3_ldridx<0b1101, "ldrsb", IIC_iLoad_bh_ru>;
2596 let hasExtraDefRegAllocReq = 1 in {
2597 def LDRD_PRE : AI3ldstidx<0b1101, 0, 1, (outs GPR:$Rt, GPR:$Rt2, GPR:$Rn_wb),
2598 (ins addrmode3_pre:$addr), IndexModePre,
2599 LdMiscFrm, IIC_iLoad_d_ru,
2600 "ldrd", "\t$Rt, $Rt2, $addr!",
2601 "$addr.base = $Rn_wb", []> {
2603 let Inst{23} = addr{8}; // U bit
2604 let Inst{22} = addr{13}; // 1 == imm8, 0 == Rm
2605 let Inst{19-16} = addr{12-9}; // Rn
2606 let Inst{11-8} = addr{7-4}; // imm7_4/zero
2607 let Inst{3-0} = addr{3-0}; // imm3_0/Rm
2608 let DecoderMethod = "DecodeAddrMode3Instruction";
2610 def LDRD_POST: AI3ldstidx<0b1101, 0, 0, (outs GPR:$Rt, GPR:$Rt2, GPR:$Rn_wb),
2611 (ins addr_offset_none:$addr, am3offset:$offset),
2612 IndexModePost, LdMiscFrm, IIC_iLoad_d_ru,
2613 "ldrd", "\t$Rt, $Rt2, $addr, $offset",
2614 "$addr.base = $Rn_wb", []> {
2617 let Inst{23} = offset{8}; // U bit
2618 let Inst{22} = offset{9}; // 1 == imm8, 0 == Rm
2619 let Inst{19-16} = addr;
2620 let Inst{11-8} = offset{7-4}; // imm7_4/zero
2621 let Inst{3-0} = offset{3-0}; // imm3_0/Rm
2622 let DecoderMethod = "DecodeAddrMode3Instruction";
2624 } // hasExtraDefRegAllocReq = 1
2625 } // mayLoad = 1, hasSideEffects = 0
2627 // LDRT, LDRBT, LDRSBT, LDRHT, LDRSHT.
2628 let mayLoad = 1, hasSideEffects = 0 in {
2629 def LDRT_POST_REG : AI2ldstidx<1, 0, 0, (outs GPR:$Rt, GPR:$Rn_wb),
2630 (ins addr_offset_none:$addr, am2offset_reg:$offset),
2631 IndexModePost, LdFrm, IIC_iLoad_ru,
2632 "ldrt", "\t$Rt, $addr, $offset",
2633 "$addr.base = $Rn_wb", []> {
2639 let Inst{23} = offset{12};
2640 let Inst{21} = 1; // overwrite
2641 let Inst{19-16} = addr;
2642 let Inst{11-5} = offset{11-5};
2644 let Inst{3-0} = offset{3-0};
2645 let DecoderMethod = "DecodeAddrMode2IdxInstruction";
2649 : AI2ldstidx<1, 0, 0, (outs GPR:$Rt, GPR:$Rn_wb),
2650 (ins addr_offset_none:$addr, am2offset_imm:$offset),
2651 IndexModePost, LdFrm, IIC_iLoad_ru,
2652 "ldrt", "\t$Rt, $addr, $offset", "$addr.base = $Rn_wb", []> {
2658 let Inst{23} = offset{12};
2659 let Inst{21} = 1; // overwrite
2660 let Inst{19-16} = addr;
2661 let Inst{11-0} = offset{11-0};
2662 let DecoderMethod = "DecodeAddrMode2IdxInstruction";
2665 def LDRBT_POST_REG : AI2ldstidx<1, 1, 0, (outs GPR:$Rt, GPR:$Rn_wb),
2666 (ins addr_offset_none:$addr, am2offset_reg:$offset),
2667 IndexModePost, LdFrm, IIC_iLoad_bh_ru,
2668 "ldrbt", "\t$Rt, $addr, $offset",
2669 "$addr.base = $Rn_wb", []> {
2675 let Inst{23} = offset{12};
2676 let Inst{21} = 1; // overwrite
2677 let Inst{19-16} = addr;
2678 let Inst{11-5} = offset{11-5};
2680 let Inst{3-0} = offset{3-0};
2681 let DecoderMethod = "DecodeAddrMode2IdxInstruction";
2685 : AI2ldstidx<1, 1, 0, (outs GPR:$Rt, GPR:$Rn_wb),
2686 (ins addr_offset_none:$addr, am2offset_imm:$offset),
2687 IndexModePost, LdFrm, IIC_iLoad_bh_ru,
2688 "ldrbt", "\t$Rt, $addr, $offset", "$addr.base = $Rn_wb", []> {
2694 let Inst{23} = offset{12};
2695 let Inst{21} = 1; // overwrite
2696 let Inst{19-16} = addr;
2697 let Inst{11-0} = offset{11-0};
2698 let DecoderMethod = "DecodeAddrMode2IdxInstruction";
2701 multiclass AI3ldrT<bits<4> op, string opc> {
2702 def i : AI3ldstidxT<op, 1, (outs GPR:$Rt, GPR:$base_wb),
2703 (ins addr_offset_none:$addr, postidx_imm8:$offset),
2704 IndexModePost, LdMiscFrm, IIC_iLoad_bh_ru, opc,
2705 "\t$Rt, $addr, $offset", "$addr.base = $base_wb", []> {
2707 let Inst{23} = offset{8};
2709 let Inst{11-8} = offset{7-4};
2710 let Inst{3-0} = offset{3-0};
2712 def r : AI3ldstidxT<op, 1, (outs GPRnopc:$Rt, GPRnopc:$base_wb),
2713 (ins addr_offset_none:$addr, postidx_reg:$Rm),
2714 IndexModePost, LdMiscFrm, IIC_iLoad_bh_ru, opc,
2715 "\t$Rt, $addr, $Rm", "$addr.base = $base_wb", []> {
2717 let Inst{23} = Rm{4};
2720 let Unpredictable{11-8} = 0b1111;
2721 let Inst{3-0} = Rm{3-0};
2722 let DecoderMethod = "DecodeLDR";
2726 defm LDRSBT : AI3ldrT<0b1101, "ldrsbt">;
2727 defm LDRHT : AI3ldrT<0b1011, "ldrht">;
2728 defm LDRSHT : AI3ldrT<0b1111, "ldrsht">;
2732 : ARMAsmPseudo<"ldrt${q} $Rt, $addr", (ins addr_offset_none:$addr, pred:$q),
2736 : ARMAsmPseudo<"ldrbt${q} $Rt, $addr", (ins addr_offset_none:$addr, pred:$q),
2741 // Stores with truncate
2742 def STRH : AI3str<0b1011, (outs), (ins GPR:$Rt, addrmode3:$addr), StMiscFrm,
2743 IIC_iStore_bh_r, "strh", "\t$Rt, $addr",
2744 [(truncstorei16 GPR:$Rt, addrmode3:$addr)]>;
2747 let mayStore = 1, hasSideEffects = 0, hasExtraSrcRegAllocReq = 1 in {
2748 def STRD : AI3str<0b1111, (outs), (ins GPR:$Rt, GPR:$Rt2, addrmode3:$addr),
2749 StMiscFrm, IIC_iStore_d_r, "strd", "\t$Rt, $Rt2, $addr", []>,
2750 Requires<[IsARM, HasV5TE]> {
2756 multiclass AI2_stridx<bit isByte, string opc,
2757 InstrItinClass iii, InstrItinClass iir> {
2758 def _PRE_IMM : AI2ldstidx<0, isByte, 1, (outs GPR:$Rn_wb),
2759 (ins GPR:$Rt, addrmode_imm12_pre:$addr), IndexModePre,
2761 opc, "\t$Rt, $addr!",
2762 "$addr.base = $Rn_wb,@earlyclobber $Rn_wb", []> {
2765 let Inst{23} = addr{12}; // U (add = ('U' == 1))
2766 let Inst{19-16} = addr{16-13}; // Rn
2767 let Inst{11-0} = addr{11-0}; // imm12
2768 let DecoderMethod = "DecodeSTRPreImm";
2771 def _PRE_REG : AI2ldstidx<0, isByte, 1, (outs GPR:$Rn_wb),
2772 (ins GPR:$Rt, ldst_so_reg:$addr),
2773 IndexModePre, StFrm, iir,
2774 opc, "\t$Rt, $addr!",
2775 "$addr.base = $Rn_wb,@earlyclobber $Rn_wb", []> {
2778 let Inst{23} = addr{12}; // U (add = ('U' == 1))
2779 let Inst{19-16} = addr{16-13}; // Rn
2780 let Inst{11-0} = addr{11-0};
2781 let Inst{4} = 0; // Inst{4} = 0
2782 let DecoderMethod = "DecodeSTRPreReg";
2784 def _POST_REG : AI2ldstidx<0, isByte, 0, (outs GPR:$Rn_wb),
2785 (ins GPR:$Rt, addr_offset_none:$addr, am2offset_reg:$offset),
2786 IndexModePost, StFrm, iir,
2787 opc, "\t$Rt, $addr, $offset",
2788 "$addr.base = $Rn_wb,@earlyclobber $Rn_wb", []> {
2794 let Inst{23} = offset{12};
2795 let Inst{19-16} = addr;
2796 let Inst{11-0} = offset{11-0};
2799 let DecoderMethod = "DecodeAddrMode2IdxInstruction";
2802 def _POST_IMM : AI2ldstidx<0, isByte, 0, (outs GPR:$Rn_wb),
2803 (ins GPR:$Rt, addr_offset_none:$addr, am2offset_imm:$offset),
2804 IndexModePost, StFrm, iii,
2805 opc, "\t$Rt, $addr, $offset",
2806 "$addr.base = $Rn_wb,@earlyclobber $Rn_wb", []> {
2812 let Inst{23} = offset{12};
2813 let Inst{19-16} = addr;
2814 let Inst{11-0} = offset{11-0};
2816 let DecoderMethod = "DecodeAddrMode2IdxInstruction";
2820 let mayStore = 1, hasSideEffects = 0 in {
2821 // FIXME: for STR_PRE_REG etc. the itineray should be either IIC_iStore_ru or
2822 // IIC_iStore_siu depending on whether it the offset register is shifted.
2823 defm STR : AI2_stridx<0, "str", IIC_iStore_iu, IIC_iStore_ru>;
2824 defm STRB : AI2_stridx<1, "strb", IIC_iStore_bh_iu, IIC_iStore_bh_ru>;
2827 def : ARMPat<(post_store GPR:$Rt, addr_offset_none:$addr,
2828 am2offset_reg:$offset),
2829 (STR_POST_REG GPR:$Rt, addr_offset_none:$addr,
2830 am2offset_reg:$offset)>;
2831 def : ARMPat<(post_store GPR:$Rt, addr_offset_none:$addr,
2832 am2offset_imm:$offset),
2833 (STR_POST_IMM GPR:$Rt, addr_offset_none:$addr,
2834 am2offset_imm:$offset)>;
2835 def : ARMPat<(post_truncsti8 GPR:$Rt, addr_offset_none:$addr,
2836 am2offset_reg:$offset),
2837 (STRB_POST_REG GPR:$Rt, addr_offset_none:$addr,
2838 am2offset_reg:$offset)>;
2839 def : ARMPat<(post_truncsti8 GPR:$Rt, addr_offset_none:$addr,
2840 am2offset_imm:$offset),
2841 (STRB_POST_IMM GPR:$Rt, addr_offset_none:$addr,
2842 am2offset_imm:$offset)>;
2844 // Pseudo-instructions for pattern matching the pre-indexed stores. We can't
2845 // put the patterns on the instruction definitions directly as ISel wants
2846 // the address base and offset to be separate operands, not a single
2847 // complex operand like we represent the instructions themselves. The
2848 // pseudos map between the two.
2849 let usesCustomInserter = 1,
2850 Constraints = "$Rn = $Rn_wb,@earlyclobber $Rn_wb" in {
2851 def STRi_preidx: ARMPseudoInst<(outs GPR:$Rn_wb),
2852 (ins GPR:$Rt, GPR:$Rn, am2offset_imm:$offset, pred:$p),
2855 (pre_store GPR:$Rt, GPR:$Rn, am2offset_imm:$offset))]>;
2856 def STRr_preidx: ARMPseudoInst<(outs GPR:$Rn_wb),
2857 (ins GPR:$Rt, GPR:$Rn, am2offset_reg:$offset, pred:$p),
2860 (pre_store GPR:$Rt, GPR:$Rn, am2offset_reg:$offset))]>;
2861 def STRBi_preidx: ARMPseudoInst<(outs GPR:$Rn_wb),
2862 (ins GPR:$Rt, GPR:$Rn, am2offset_imm:$offset, pred:$p),
2865 (pre_truncsti8 GPR:$Rt, GPR:$Rn, am2offset_imm:$offset))]>;
2866 def STRBr_preidx: ARMPseudoInst<(outs GPR:$Rn_wb),
2867 (ins GPR:$Rt, GPR:$Rn, am2offset_reg:$offset, pred:$p),
2870 (pre_truncsti8 GPR:$Rt, GPR:$Rn, am2offset_reg:$offset))]>;
2871 def STRH_preidx: ARMPseudoInst<(outs GPR:$Rn_wb),
2872 (ins GPR:$Rt, GPR:$Rn, am3offset:$offset, pred:$p),
2875 (pre_truncsti16 GPR:$Rt, GPR:$Rn, am3offset:$offset))]>;
2880 def STRH_PRE : AI3ldstidx<0b1011, 0, 1, (outs GPR:$Rn_wb),
2881 (ins GPR:$Rt, addrmode3_pre:$addr), IndexModePre,
2882 StMiscFrm, IIC_iStore_bh_ru,
2883 "strh", "\t$Rt, $addr!",
2884 "$addr.base = $Rn_wb,@earlyclobber $Rn_wb", []> {
2886 let Inst{23} = addr{8}; // U bit
2887 let Inst{22} = addr{13}; // 1 == imm8, 0 == Rm
2888 let Inst{19-16} = addr{12-9}; // Rn
2889 let Inst{11-8} = addr{7-4}; // imm7_4/zero
2890 let Inst{3-0} = addr{3-0}; // imm3_0/Rm
2891 let DecoderMethod = "DecodeAddrMode3Instruction";
2894 def STRH_POST : AI3ldstidx<0b1011, 0, 0, (outs GPR:$Rn_wb),
2895 (ins GPR:$Rt, addr_offset_none:$addr, am3offset:$offset),
2896 IndexModePost, StMiscFrm, IIC_iStore_bh_ru,
2897 "strh", "\t$Rt, $addr, $offset",
2898 "$addr.base = $Rn_wb,@earlyclobber $Rn_wb",
2899 [(set GPR:$Rn_wb, (post_truncsti16 GPR:$Rt,
2900 addr_offset_none:$addr,
2901 am3offset:$offset))]> {
2904 let Inst{23} = offset{8}; // U bit
2905 let Inst{22} = offset{9}; // 1 == imm8, 0 == Rm
2906 let Inst{19-16} = addr;
2907 let Inst{11-8} = offset{7-4}; // imm7_4/zero
2908 let Inst{3-0} = offset{3-0}; // imm3_0/Rm
2909 let DecoderMethod = "DecodeAddrMode3Instruction";
2912 let mayStore = 1, hasSideEffects = 0, hasExtraSrcRegAllocReq = 1 in {
2913 def STRD_PRE : AI3ldstidx<0b1111, 0, 1, (outs GPR:$Rn_wb),
2914 (ins GPR:$Rt, GPR:$Rt2, addrmode3_pre:$addr),
2915 IndexModePre, StMiscFrm, IIC_iStore_d_ru,
2916 "strd", "\t$Rt, $Rt2, $addr!",
2917 "$addr.base = $Rn_wb", []> {
2919 let Inst{23} = addr{8}; // U bit
2920 let Inst{22} = addr{13}; // 1 == imm8, 0 == Rm
2921 let Inst{19-16} = addr{12-9}; // Rn
2922 let Inst{11-8} = addr{7-4}; // imm7_4/zero
2923 let Inst{3-0} = addr{3-0}; // imm3_0/Rm
2924 let DecoderMethod = "DecodeAddrMode3Instruction";
2927 def STRD_POST: AI3ldstidx<0b1111, 0, 0, (outs GPR:$Rn_wb),
2928 (ins GPR:$Rt, GPR:$Rt2, addr_offset_none:$addr,
2930 IndexModePost, StMiscFrm, IIC_iStore_d_ru,
2931 "strd", "\t$Rt, $Rt2, $addr, $offset",
2932 "$addr.base = $Rn_wb", []> {
2935 let Inst{23} = offset{8}; // U bit
2936 let Inst{22} = offset{9}; // 1 == imm8, 0 == Rm
2937 let Inst{19-16} = addr;
2938 let Inst{11-8} = offset{7-4}; // imm7_4/zero
2939 let Inst{3-0} = offset{3-0}; // imm3_0/Rm
2940 let DecoderMethod = "DecodeAddrMode3Instruction";
2942 } // mayStore = 1, hasSideEffects = 0, hasExtraSrcRegAllocReq = 1
2944 // STRT, STRBT, and STRHT
2946 def STRBT_POST_REG : AI2ldstidx<0, 1, 0, (outs GPR:$Rn_wb),
2947 (ins GPR:$Rt, addr_offset_none:$addr, am2offset_reg:$offset),
2948 IndexModePost, StFrm, IIC_iStore_bh_ru,
2949 "strbt", "\t$Rt, $addr, $offset",
2950 "$addr.base = $Rn_wb", []> {
2956 let Inst{23} = offset{12};
2957 let Inst{21} = 1; // overwrite
2958 let Inst{19-16} = addr;
2959 let Inst{11-5} = offset{11-5};
2961 let Inst{3-0} = offset{3-0};
2962 let DecoderMethod = "DecodeAddrMode2IdxInstruction";
2966 : AI2ldstidx<0, 1, 0, (outs GPR:$Rn_wb),
2967 (ins GPR:$Rt, addr_offset_none:$addr, am2offset_imm:$offset),
2968 IndexModePost, StFrm, IIC_iStore_bh_ru,
2969 "strbt", "\t$Rt, $addr, $offset", "$addr.base = $Rn_wb", []> {
2975 let Inst{23} = offset{12};
2976 let Inst{21} = 1; // overwrite
2977 let Inst{19-16} = addr;
2978 let Inst{11-0} = offset{11-0};
2979 let DecoderMethod = "DecodeAddrMode2IdxInstruction";
2983 : ARMAsmPseudo<"strbt${q} $Rt, $addr",
2984 (ins GPR:$Rt, addr_offset_none:$addr, pred:$q)>;
2986 let mayStore = 1, hasSideEffects = 0 in {
2987 def STRT_POST_REG : AI2ldstidx<0, 0, 0, (outs GPR:$Rn_wb),
2988 (ins GPR:$Rt, addr_offset_none:$addr, am2offset_reg:$offset),
2989 IndexModePost, StFrm, IIC_iStore_ru,
2990 "strt", "\t$Rt, $addr, $offset",
2991 "$addr.base = $Rn_wb", []> {
2997 let Inst{23} = offset{12};
2998 let Inst{21} = 1; // overwrite
2999 let Inst{19-16} = addr;
3000 let Inst{11-5} = offset{11-5};
3002 let Inst{3-0} = offset{3-0};
3003 let DecoderMethod = "DecodeAddrMode2IdxInstruction";
3007 : AI2ldstidx<0, 0, 0, (outs GPR:$Rn_wb),
3008 (ins GPR:$Rt, addr_offset_none:$addr, am2offset_imm:$offset),
3009 IndexModePost, StFrm, IIC_iStore_ru,
3010 "strt", "\t$Rt, $addr, $offset", "$addr.base = $Rn_wb", []> {
3016 let Inst{23} = offset{12};
3017 let Inst{21} = 1; // overwrite
3018 let Inst{19-16} = addr;
3019 let Inst{11-0} = offset{11-0};
3020 let DecoderMethod = "DecodeAddrMode2IdxInstruction";
3025 : ARMAsmPseudo<"strt${q} $Rt, $addr",
3026 (ins GPR:$Rt, addr_offset_none:$addr, pred:$q)>;
3028 multiclass AI3strT<bits<4> op, string opc> {
3029 def i : AI3ldstidxT<op, 0, (outs GPR:$base_wb),
3030 (ins GPR:$Rt, addr_offset_none:$addr, postidx_imm8:$offset),
3031 IndexModePost, StMiscFrm, IIC_iStore_bh_ru, opc,
3032 "\t$Rt, $addr, $offset", "$addr.base = $base_wb", []> {
3034 let Inst{23} = offset{8};
3036 let Inst{11-8} = offset{7-4};
3037 let Inst{3-0} = offset{3-0};
3039 def r : AI3ldstidxT<op, 0, (outs GPR:$base_wb),
3040 (ins GPR:$Rt, addr_offset_none:$addr, postidx_reg:$Rm),
3041 IndexModePost, StMiscFrm, IIC_iStore_bh_ru, opc,
3042 "\t$Rt, $addr, $Rm", "$addr.base = $base_wb", []> {
3044 let Inst{23} = Rm{4};
3047 let Inst{3-0} = Rm{3-0};
3052 defm STRHT : AI3strT<0b1011, "strht">;
3054 def STL : AIstrrel<0b00, (outs), (ins GPR:$Rt, addr_offset_none:$addr),
3055 NoItinerary, "stl", "\t$Rt, $addr", []>;
3056 def STLB : AIstrrel<0b10, (outs), (ins GPR:$Rt, addr_offset_none:$addr),
3057 NoItinerary, "stlb", "\t$Rt, $addr", []>;
3058 def STLH : AIstrrel<0b11, (outs), (ins GPR:$Rt, addr_offset_none:$addr),
3059 NoItinerary, "stlh", "\t$Rt, $addr", []>;
3061 //===----------------------------------------------------------------------===//
3062 // Load / store multiple Instructions.
3065 multiclass arm_ldst_mult<string asm, string sfx, bit L_bit, bit P_bit, Format f,
3066 InstrItinClass itin, InstrItinClass itin_upd> {
3067 // IA is the default, so no need for an explicit suffix on the
3068 // mnemonic here. Without it is the canonical spelling.
3070 AXI4<(outs), (ins GPR:$Rn, pred:$p, reglist:$regs, variable_ops),
3071 IndexModeNone, f, itin,
3072 !strconcat(asm, "${p}\t$Rn, $regs", sfx), "", []> {
3073 let Inst{24-23} = 0b01; // Increment After
3074 let Inst{22} = P_bit;
3075 let Inst{21} = 0; // No writeback
3076 let Inst{20} = L_bit;
3079 AXI4<(outs GPR:$wb), (ins GPR:$Rn, pred:$p, reglist:$regs, variable_ops),
3080 IndexModeUpd, f, itin_upd,
3081 !strconcat(asm, "${p}\t$Rn!, $regs", sfx), "$Rn = $wb", []> {
3082 let Inst{24-23} = 0b01; // Increment After
3083 let Inst{22} = P_bit;
3084 let Inst{21} = 1; // Writeback
3085 let Inst{20} = L_bit;
3087 let DecoderMethod = "DecodeMemMultipleWritebackInstruction";
3090 AXI4<(outs), (ins GPR:$Rn, pred:$p, reglist:$regs, variable_ops),
3091 IndexModeNone, f, itin,
3092 !strconcat(asm, "da${p}\t$Rn, $regs", sfx), "", []> {
3093 let Inst{24-23} = 0b00; // Decrement After
3094 let Inst{22} = P_bit;
3095 let Inst{21} = 0; // No writeback
3096 let Inst{20} = L_bit;
3099 AXI4<(outs GPR:$wb), (ins GPR:$Rn, pred:$p, reglist:$regs, variable_ops),
3100 IndexModeUpd, f, itin_upd,
3101 !strconcat(asm, "da${p}\t$Rn!, $regs", sfx), "$Rn = $wb", []> {
3102 let Inst{24-23} = 0b00; // Decrement After
3103 let Inst{22} = P_bit;
3104 let Inst{21} = 1; // Writeback
3105 let Inst{20} = L_bit;
3107 let DecoderMethod = "DecodeMemMultipleWritebackInstruction";
3110 AXI4<(outs), (ins GPR:$Rn, pred:$p, reglist:$regs, variable_ops),
3111 IndexModeNone, f, itin,
3112 !strconcat(asm, "db${p}\t$Rn, $regs", sfx), "", []> {
3113 let Inst{24-23} = 0b10; // Decrement Before
3114 let Inst{22} = P_bit;
3115 let Inst{21} = 0; // No writeback
3116 let Inst{20} = L_bit;
3119 AXI4<(outs GPR:$wb), (ins GPR:$Rn, pred:$p, reglist:$regs, variable_ops),
3120 IndexModeUpd, f, itin_upd,
3121 !strconcat(asm, "db${p}\t$Rn!, $regs", sfx), "$Rn = $wb", []> {
3122 let Inst{24-23} = 0b10; // Decrement Before
3123 let Inst{22} = P_bit;
3124 let Inst{21} = 1; // Writeback
3125 let Inst{20} = L_bit;
3127 let DecoderMethod = "DecodeMemMultipleWritebackInstruction";
3130 AXI4<(outs), (ins GPR:$Rn, pred:$p, reglist:$regs, variable_ops),
3131 IndexModeNone, f, itin,
3132 !strconcat(asm, "ib${p}\t$Rn, $regs", sfx), "", []> {
3133 let Inst{24-23} = 0b11; // Increment Before
3134 let Inst{22} = P_bit;
3135 let Inst{21} = 0; // No writeback
3136 let Inst{20} = L_bit;
3139 AXI4<(outs GPR:$wb), (ins GPR:$Rn, pred:$p, reglist:$regs, variable_ops),
3140 IndexModeUpd, f, itin_upd,
3141 !strconcat(asm, "ib${p}\t$Rn!, $regs", sfx), "$Rn = $wb", []> {
3142 let Inst{24-23} = 0b11; // Increment Before
3143 let Inst{22} = P_bit;
3144 let Inst{21} = 1; // Writeback
3145 let Inst{20} = L_bit;
3147 let DecoderMethod = "DecodeMemMultipleWritebackInstruction";
3151 let hasSideEffects = 0 in {
3153 let mayLoad = 1, hasExtraDefRegAllocReq = 1 in
3154 defm LDM : arm_ldst_mult<"ldm", "", 1, 0, LdStMulFrm, IIC_iLoad_m,
3155 IIC_iLoad_mu>, ComplexDeprecationPredicate<"ARMLoad">;
3157 let mayStore = 1, hasExtraSrcRegAllocReq = 1 in
3158 defm STM : arm_ldst_mult<"stm", "", 0, 0, LdStMulFrm, IIC_iStore_m,
3160 ComplexDeprecationPredicate<"ARMStore">;
3164 // FIXME: remove when we have a way to marking a MI with these properties.
3165 // FIXME: Should pc be an implicit operand like PICADD, etc?
3166 let isReturn = 1, isTerminator = 1, isBarrier = 1, mayLoad = 1,
3167 hasExtraDefRegAllocReq = 1, isCodeGenOnly = 1 in
3168 def LDMIA_RET : ARMPseudoExpand<(outs GPR:$wb), (ins GPR:$Rn, pred:$p,
3169 reglist:$regs, variable_ops),
3170 4, IIC_iLoad_mBr, [],
3171 (LDMIA_UPD GPR:$wb, GPR:$Rn, pred:$p, reglist:$regs)>,
3172 RegConstraint<"$Rn = $wb">;
3174 let mayLoad = 1, hasExtraDefRegAllocReq = 1 in
3175 defm sysLDM : arm_ldst_mult<"ldm", " ^", 1, 1, LdStMulFrm, IIC_iLoad_m,
3178 let mayStore = 1, hasExtraSrcRegAllocReq = 1 in
3179 defm sysSTM : arm_ldst_mult<"stm", " ^", 0, 1, LdStMulFrm, IIC_iStore_m,
3184 //===----------------------------------------------------------------------===//
3185 // Move Instructions.
3188 let hasSideEffects = 0 in
3189 def MOVr : AsI1<0b1101, (outs GPR:$Rd), (ins GPR:$Rm), DPFrm, IIC_iMOVr,
3190 "mov", "\t$Rd, $Rm", []>, UnaryDP, Sched<[WriteALU]> {
3194 let Inst{19-16} = 0b0000;
3195 let Inst{11-4} = 0b00000000;
3198 let Inst{15-12} = Rd;
3201 // A version for the smaller set of tail call registers.
3202 let hasSideEffects = 0 in
3203 def MOVr_TC : AsI1<0b1101, (outs tcGPR:$Rd), (ins tcGPR:$Rm), DPFrm,
3204 IIC_iMOVr, "mov", "\t$Rd, $Rm", []>, UnaryDP, Sched<[WriteALU]> {
3208 let Inst{11-4} = 0b00000000;
3211 let Inst{15-12} = Rd;
3214 def MOVsr : AsI1<0b1101, (outs GPRnopc:$Rd), (ins shift_so_reg_reg:$src),
3215 DPSoRegRegFrm, IIC_iMOVsr,
3216 "mov", "\t$Rd, $src",
3217 [(set GPRnopc:$Rd, shift_so_reg_reg:$src)]>, UnaryDP,
3221 let Inst{15-12} = Rd;
3222 let Inst{19-16} = 0b0000;
3223 let Inst{11-8} = src{11-8};
3225 let Inst{6-5} = src{6-5};
3227 let Inst{3-0} = src{3-0};
3231 def MOVsi : AsI1<0b1101, (outs GPR:$Rd), (ins shift_so_reg_imm:$src),
3232 DPSoRegImmFrm, IIC_iMOVsr,
3233 "mov", "\t$Rd, $src", [(set GPR:$Rd, shift_so_reg_imm:$src)]>,
3234 UnaryDP, Sched<[WriteALU]> {
3237 let Inst{15-12} = Rd;
3238 let Inst{19-16} = 0b0000;
3239 let Inst{11-5} = src{11-5};
3241 let Inst{3-0} = src{3-0};
3245 let isReMaterializable = 1, isAsCheapAsAMove = 1, isMoveImm = 1 in
3246 def MOVi : AsI1<0b1101, (outs GPR:$Rd), (ins mod_imm:$imm), DPFrm, IIC_iMOVi,
3247 "mov", "\t$Rd, $imm", [(set GPR:$Rd, mod_imm:$imm)]>, UnaryDP,
3252 let Inst{15-12} = Rd;
3253 let Inst{19-16} = 0b0000;
3254 let Inst{11-0} = imm;
3257 let isReMaterializable = 1, isAsCheapAsAMove = 1, isMoveImm = 1 in
3258 def MOVi16 : AI1<0b1000, (outs GPR:$Rd), (ins imm0_65535_expr:$imm),
3260 "movw", "\t$Rd, $imm",
3261 [(set GPR:$Rd, imm0_65535:$imm)]>,
3262 Requires<[IsARM, HasV6T2]>, UnaryDP, Sched<[WriteALU]> {
3265 let Inst{15-12} = Rd;
3266 let Inst{11-0} = imm{11-0};
3267 let Inst{19-16} = imm{15-12};
3270 let DecoderMethod = "DecodeArmMOVTWInstruction";
3273 def : InstAlias<"mov${p} $Rd, $imm",
3274 (MOVi16 GPR:$Rd, imm0_65535_expr:$imm, pred:$p)>,
3277 def MOVi16_ga_pcrel : PseudoInst<(outs GPR:$Rd),
3278 (ins i32imm:$addr, pclabel:$id), IIC_iMOVi, []>,
3281 let Constraints = "$src = $Rd" in {
3282 def MOVTi16 : AI1<0b1010, (outs GPRnopc:$Rd),
3283 (ins GPR:$src, imm0_65535_expr:$imm),
3285 "movt", "\t$Rd, $imm",
3287 (or (and GPR:$src, 0xffff),
3288 lo16AllZero:$imm))]>, UnaryDP,
3289 Requires<[IsARM, HasV6T2]>, Sched<[WriteALU]> {
3292 let Inst{15-12} = Rd;
3293 let Inst{11-0} = imm{11-0};
3294 let Inst{19-16} = imm{15-12};
3297 let DecoderMethod = "DecodeArmMOVTWInstruction";
3300 def MOVTi16_ga_pcrel : PseudoInst<(outs GPR:$Rd),
3301 (ins GPR:$src, i32imm:$addr, pclabel:$id), IIC_iMOVi, []>,
3306 def : ARMPat<(or GPR:$src, 0xffff0000), (MOVTi16 GPR:$src, 0xffff)>,
3307 Requires<[IsARM, HasV6T2]>;
3309 let Uses = [CPSR] in
3310 def RRX: PseudoInst<(outs GPR:$Rd), (ins GPR:$Rm), IIC_iMOVsi,
3311 [(set GPR:$Rd, (ARMrrx GPR:$Rm))]>, UnaryDP,
3312 Requires<[IsARM]>, Sched<[WriteALU]>;
3314 // These aren't really mov instructions, but we have to define them this way
3315 // due to flag operands.
3317 let Defs = [CPSR] in {
3318 def MOVsrl_flag : PseudoInst<(outs GPR:$dst), (ins GPR:$src), IIC_iMOVsi,
3319 [(set GPR:$dst, (ARMsrl_flag GPR:$src))]>, UnaryDP,
3320 Sched<[WriteALU]>, Requires<[IsARM]>;
3321 def MOVsra_flag : PseudoInst<(outs GPR:$dst), (ins GPR:$src), IIC_iMOVsi,
3322 [(set GPR:$dst, (ARMsra_flag GPR:$src))]>, UnaryDP,
3323 Sched<[WriteALU]>, Requires<[IsARM]>;
3326 //===----------------------------------------------------------------------===//
3327 // Extend Instructions.
3332 def SXTB : AI_ext_rrot<0b01101010,
3333 "sxtb", UnOpFrag<(sext_inreg node:$Src, i8)>>;
3334 def SXTH : AI_ext_rrot<0b01101011,
3335 "sxth", UnOpFrag<(sext_inreg node:$Src, i16)>>;
3337 def SXTAB : AI_exta_rrot<0b01101010,
3338 "sxtab", BinOpFrag<(add node:$LHS, (sext_inreg node:$RHS, i8))>>;
3339 def SXTAH : AI_exta_rrot<0b01101011,
3340 "sxtah", BinOpFrag<(add node:$LHS, (sext_inreg node:$RHS,i16))>>;
3342 def SXTB16 : AI_ext_rrot_np<0b01101000, "sxtb16">;
3344 def SXTAB16 : AI_exta_rrot_np<0b01101000, "sxtab16">;
3348 let AddedComplexity = 16 in {
3349 def UXTB : AI_ext_rrot<0b01101110,
3350 "uxtb" , UnOpFrag<(and node:$Src, 0x000000FF)>>;
3351 def UXTH : AI_ext_rrot<0b01101111,
3352 "uxth" , UnOpFrag<(and node:$Src, 0x0000FFFF)>>;
3353 def UXTB16 : AI_ext_rrot<0b01101100,
3354 "uxtb16", UnOpFrag<(and node:$Src, 0x00FF00FF)>>;
3356 // FIXME: This pattern incorrectly assumes the shl operator is a rotate.
3357 // The transformation should probably be done as a combiner action
3358 // instead so we can include a check for masking back in the upper
3359 // eight bits of the source into the lower eight bits of the result.
3360 //def : ARMV6Pat<(and (shl GPR:$Src, (i32 8)), 0xFF00FF),
3361 // (UXTB16r_rot GPR:$Src, 3)>;
3362 def : ARMV6Pat<(and (srl GPR:$Src, (i32 8)), 0xFF00FF),
3363 (UXTB16 GPR:$Src, 1)>;
3365 def UXTAB : AI_exta_rrot<0b01101110, "uxtab",
3366 BinOpFrag<(add node:$LHS, (and node:$RHS, 0x00FF))>>;
3367 def UXTAH : AI_exta_rrot<0b01101111, "uxtah",
3368 BinOpFrag<(add node:$LHS, (and node:$RHS, 0xFFFF))>>;
3371 // This isn't safe in general, the add is two 16-bit units, not a 32-bit add.
3372 def UXTAB16 : AI_exta_rrot_np<0b01101100, "uxtab16">;
3375 def SBFX : I<(outs GPRnopc:$Rd),
3376 (ins GPRnopc:$Rn, imm0_31:$lsb, imm1_32:$width),
3377 AddrMode1, 4, IndexModeNone, DPFrm, IIC_iUNAsi,
3378 "sbfx", "\t$Rd, $Rn, $lsb, $width", "", []>,
3379 Requires<[IsARM, HasV6T2]> {
3384 let Inst{27-21} = 0b0111101;
3385 let Inst{6-4} = 0b101;
3386 let Inst{20-16} = width;
3387 let Inst{15-12} = Rd;
3388 let Inst{11-7} = lsb;
3392 def UBFX : I<(outs GPRnopc:$Rd),
3393 (ins GPRnopc:$Rn, imm0_31:$lsb, imm1_32:$width),
3394 AddrMode1, 4, IndexModeNone, DPFrm, IIC_iUNAsi,
3395 "ubfx", "\t$Rd, $Rn, $lsb, $width", "", []>,
3396 Requires<[IsARM, HasV6T2]> {
3401 let Inst{27-21} = 0b0111111;
3402 let Inst{6-4} = 0b101;
3403 let Inst{20-16} = width;
3404 let Inst{15-12} = Rd;
3405 let Inst{11-7} = lsb;
3409 //===----------------------------------------------------------------------===//
3410 // Arithmetic Instructions.
3413 defm ADD : AsI1_bin_irs<0b0100, "add",
3414 IIC_iALUi, IIC_iALUr, IIC_iALUsr,
3415 BinOpFrag<(add node:$LHS, node:$RHS)>, 1>;
3416 defm SUB : AsI1_bin_irs<0b0010, "sub",
3417 IIC_iALUi, IIC_iALUr, IIC_iALUsr,
3418 BinOpFrag<(sub node:$LHS, node:$RHS)>>;
3420 // ADD and SUB with 's' bit set.
3422 // Currently, ADDS/SUBS are pseudo opcodes that exist only in the
3423 // selection DAG. They are "lowered" to real ADD/SUB opcodes by
3424 // AdjustInstrPostInstrSelection where we determine whether or not to
3425 // set the "s" bit based on CPSR liveness.
3427 // FIXME: Eliminate ADDS/SUBS pseudo opcodes after adding tablegen
3428 // support for an optional CPSR definition that corresponds to the DAG
3429 // node's second value. We can then eliminate the implicit def of CPSR.
3430 defm ADDS : AsI1_bin_s_irs<IIC_iALUi, IIC_iALUr, IIC_iALUsr,
3431 BinOpFrag<(ARMaddc node:$LHS, node:$RHS)>, 1>;
3432 defm SUBS : AsI1_bin_s_irs<IIC_iALUi, IIC_iALUr, IIC_iALUsr,
3433 BinOpFrag<(ARMsubc node:$LHS, node:$RHS)>>;
3435 defm ADC : AI1_adde_sube_irs<0b0101, "adc",
3436 BinOpWithFlagFrag<(ARMadde node:$LHS, node:$RHS, node:$FLAG)>, 1>;
3437 defm SBC : AI1_adde_sube_irs<0b0110, "sbc",
3438 BinOpWithFlagFrag<(ARMsube node:$LHS, node:$RHS, node:$FLAG)>>;
3440 defm RSB : AsI1_rbin_irs<0b0011, "rsb",
3441 IIC_iALUi, IIC_iALUr, IIC_iALUsr,
3442 BinOpFrag<(sub node:$LHS, node:$RHS)>>;
3444 // FIXME: Eliminate them if we can write def : Pat patterns which defines
3445 // CPSR and the implicit def of CPSR is not needed.
3446 defm RSBS : AsI1_rbin_s_is<IIC_iALUi, IIC_iALUr, IIC_iALUsr,
3447 BinOpFrag<(ARMsubc node:$LHS, node:$RHS)>>;
3449 defm RSC : AI1_rsc_irs<0b0111, "rsc",
3450 BinOpWithFlagFrag<(ARMsube node:$LHS, node:$RHS, node:$FLAG)>>;
3452 // (sub X, imm) gets canonicalized to (add X, -imm). Match this form.
3453 // The assume-no-carry-in form uses the negation of the input since add/sub
3454 // assume opposite meanings of the carry flag (i.e., carry == !borrow).
3455 // See the definition of AddWithCarry() in the ARM ARM A2.2.1 for the gory
3457 def : ARMPat<(add GPR:$src, mod_imm_neg:$imm),
3458 (SUBri GPR:$src, mod_imm_neg:$imm)>;
3459 def : ARMPat<(ARMaddc GPR:$src, mod_imm_neg:$imm),
3460 (SUBSri GPR:$src, mod_imm_neg:$imm)>;
3462 def : ARMPat<(add GPR:$src, imm0_65535_neg:$imm),
3463 (SUBrr GPR:$src, (MOVi16 (imm_neg_XFORM imm:$imm)))>,
3464 Requires<[IsARM, HasV6T2]>;
3465 def : ARMPat<(ARMaddc GPR:$src, imm0_65535_neg:$imm),
3466 (SUBSrr GPR:$src, (MOVi16 (imm_neg_XFORM imm:$imm)))>,
3467 Requires<[IsARM, HasV6T2]>;
3469 // The with-carry-in form matches bitwise not instead of the negation.
3470 // Effectively, the inverse interpretation of the carry flag already accounts
3471 // for part of the negation.
3472 def : ARMPat<(ARMadde GPR:$src, mod_imm_not:$imm, CPSR),
3473 (SBCri GPR:$src, mod_imm_not:$imm)>;
3474 def : ARMPat<(ARMadde GPR:$src, imm0_65535_neg:$imm, CPSR),
3475 (SBCrr GPR:$src, (MOVi16 (imm_not_XFORM imm:$imm)))>,
3476 Requires<[IsARM, HasV6T2]>;
3478 // Note: These are implemented in C++ code, because they have to generate
3479 // ADD/SUBrs instructions, which use a complex pattern that a xform function
3481 // (mul X, 2^n+1) -> (add (X << n), X)
3482 // (mul X, 2^n-1) -> (rsb X, (X << n))
3484 // ARM Arithmetic Instruction
3485 // GPR:$dst = GPR:$a op GPR:$b
3486 class AAI<bits<8> op27_20, bits<8> op11_4, string opc,
3487 list<dag> pattern = [],
3488 dag iops = (ins GPRnopc:$Rn, GPRnopc:$Rm),
3489 string asm = "\t$Rd, $Rn, $Rm">
3490 : AI<(outs GPRnopc:$Rd), iops, DPFrm, IIC_iALUr, opc, asm, pattern>,
3491 Sched<[WriteALU, ReadALU, ReadALU]> {
3495 let Inst{27-20} = op27_20;
3496 let Inst{11-4} = op11_4;
3497 let Inst{19-16} = Rn;
3498 let Inst{15-12} = Rd;
3501 let Unpredictable{11-8} = 0b1111;
3504 // Saturating add/subtract
3506 let DecoderMethod = "DecodeQADDInstruction" in
3507 def QADD : AAI<0b00010000, 0b00000101, "qadd",
3508 [(set GPRnopc:$Rd, (int_arm_qadd GPRnopc:$Rm, GPRnopc:$Rn))],
3509 (ins GPRnopc:$Rm, GPRnopc:$Rn), "\t$Rd, $Rm, $Rn">;
3511 def QSUB : AAI<0b00010010, 0b00000101, "qsub",
3512 [(set GPRnopc:$Rd, (int_arm_qsub GPRnopc:$Rm, GPRnopc:$Rn))],
3513 (ins GPRnopc:$Rm, GPRnopc:$Rn), "\t$Rd, $Rm, $Rn">;
3514 def QDADD : AAI<0b00010100, 0b00000101, "qdadd", [],
3515 (ins GPRnopc:$Rm, GPRnopc:$Rn),
3517 def QDSUB : AAI<0b00010110, 0b00000101, "qdsub", [],
3518 (ins GPRnopc:$Rm, GPRnopc:$Rn),
3521 def QADD16 : AAI<0b01100010, 0b11110001, "qadd16">;
3522 def QADD8 : AAI<0b01100010, 0b11111001, "qadd8">;
3523 def QASX : AAI<0b01100010, 0b11110011, "qasx">;
3524 def QSAX : AAI<0b01100010, 0b11110101, "qsax">;
3525 def QSUB16 : AAI<0b01100010, 0b11110111, "qsub16">;
3526 def QSUB8 : AAI<0b01100010, 0b11111111, "qsub8">;
3527 def UQADD16 : AAI<0b01100110, 0b11110001, "uqadd16">;
3528 def UQADD8 : AAI<0b01100110, 0b11111001, "uqadd8">;
3529 def UQASX : AAI<0b01100110, 0b11110011, "uqasx">;
3530 def UQSAX : AAI<0b01100110, 0b11110101, "uqsax">;
3531 def UQSUB16 : AAI<0b01100110, 0b11110111, "uqsub16">;
3532 def UQSUB8 : AAI<0b01100110, 0b11111111, "uqsub8">;
3534 // Signed/Unsigned add/subtract
3536 def SASX : AAI<0b01100001, 0b11110011, "sasx">;
3537 def SADD16 : AAI<0b01100001, 0b11110001, "sadd16">;
3538 def SADD8 : AAI<0b01100001, 0b11111001, "sadd8">;
3539 def SSAX : AAI<0b01100001, 0b11110101, "ssax">;
3540 def SSUB16 : AAI<0b01100001, 0b11110111, "ssub16">;
3541 def SSUB8 : AAI<0b01100001, 0b11111111, "ssub8">;
3542 def UASX : AAI<0b01100101, 0b11110011, "uasx">;
3543 def UADD16 : AAI<0b01100101, 0b11110001, "uadd16">;
3544 def UADD8 : AAI<0b01100101, 0b11111001, "uadd8">;
3545 def USAX : AAI<0b01100101, 0b11110101, "usax">;
3546 def USUB16 : AAI<0b01100101, 0b11110111, "usub16">;
3547 def USUB8 : AAI<0b01100101, 0b11111111, "usub8">;
3549 // Signed/Unsigned halving add/subtract
3551 def SHASX : AAI<0b01100011, 0b11110011, "shasx">;
3552 def SHADD16 : AAI<0b01100011, 0b11110001, "shadd16">;
3553 def SHADD8 : AAI<0b01100011, 0b11111001, "shadd8">;
3554 def SHSAX : AAI<0b01100011, 0b11110101, "shsax">;
3555 def SHSUB16 : AAI<0b01100011, 0b11110111, "shsub16">;
3556 def SHSUB8 : AAI<0b01100011, 0b11111111, "shsub8">;
3557 def UHASX : AAI<0b01100111, 0b11110011, "uhasx">;
3558 def UHADD16 : AAI<0b01100111, 0b11110001, "uhadd16">;
3559 def UHADD8 : AAI<0b01100111, 0b11111001, "uhadd8">;
3560 def UHSAX : AAI<0b01100111, 0b11110101, "uhsax">;
3561 def UHSUB16 : AAI<0b01100111, 0b11110111, "uhsub16">;
3562 def UHSUB8 : AAI<0b01100111, 0b11111111, "uhsub8">;
3564 // Unsigned Sum of Absolute Differences [and Accumulate].
3566 def USAD8 : AI<(outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm),
3567 MulFrm /* for convenience */, NoItinerary, "usad8",
3568 "\t$Rd, $Rn, $Rm", []>,
3569 Requires<[IsARM, HasV6]>, Sched<[WriteALU, ReadALU, ReadALU]> {
3573 let Inst{27-20} = 0b01111000;
3574 let Inst{15-12} = 0b1111;
3575 let Inst{7-4} = 0b0001;
3576 let Inst{19-16} = Rd;
3577 let Inst{11-8} = Rm;
3580 def USADA8 : AI<(outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm, GPR:$Ra),
3581 MulFrm /* for convenience */, NoItinerary, "usada8",
3582 "\t$Rd, $Rn, $Rm, $Ra", []>,
3583 Requires<[IsARM, HasV6]>, Sched<[WriteALU, ReadALU, ReadALU]>{
3588 let Inst{27-20} = 0b01111000;
3589 let Inst{7-4} = 0b0001;
3590 let Inst{19-16} = Rd;
3591 let Inst{15-12} = Ra;
3592 let Inst{11-8} = Rm;
3596 // Signed/Unsigned saturate
3598 def SSAT : AI<(outs GPRnopc:$Rd),
3599 (ins imm1_32:$sat_imm, GPRnopc:$Rn, shift_imm:$sh),
3600 SatFrm, NoItinerary, "ssat", "\t$Rd, $sat_imm, $Rn$sh", []> {
3605 let Inst{27-21} = 0b0110101;
3606 let Inst{5-4} = 0b01;
3607 let Inst{20-16} = sat_imm;
3608 let Inst{15-12} = Rd;
3609 let Inst{11-7} = sh{4-0};
3610 let Inst{6} = sh{5};
3614 def SSAT16 : AI<(outs GPRnopc:$Rd),
3615 (ins imm1_16:$sat_imm, GPRnopc:$Rn), SatFrm,
3616 NoItinerary, "ssat16", "\t$Rd, $sat_imm, $Rn", []> {
3620 let Inst{27-20} = 0b01101010;
3621 let Inst{11-4} = 0b11110011;
3622 let Inst{15-12} = Rd;
3623 let Inst{19-16} = sat_imm;
3627 def USAT : AI<(outs GPRnopc:$Rd),
3628 (ins imm0_31:$sat_imm, GPRnopc:$Rn, shift_imm:$sh),
3629 SatFrm, NoItinerary, "usat", "\t$Rd, $sat_imm, $Rn$sh", []> {
3634 let Inst{27-21} = 0b0110111;
3635 let Inst{5-4} = 0b01;
3636 let Inst{15-12} = Rd;
3637 let Inst{11-7} = sh{4-0};
3638 let Inst{6} = sh{5};
3639 let Inst{20-16} = sat_imm;
3643 def USAT16 : AI<(outs GPRnopc:$Rd),
3644 (ins imm0_15:$sat_imm, GPRnopc:$Rn), SatFrm,
3645 NoItinerary, "usat16", "\t$Rd, $sat_imm, $Rn", []> {
3649 let Inst{27-20} = 0b01101110;
3650 let Inst{11-4} = 0b11110011;
3651 let Inst{15-12} = Rd;
3652 let Inst{19-16} = sat_imm;
3656 def : ARMV6Pat<(int_arm_ssat GPRnopc:$a, imm:$pos),
3657 (SSAT imm:$pos, GPRnopc:$a, 0)>;
3658 def : ARMV6Pat<(int_arm_usat GPRnopc:$a, imm:$pos),
3659 (USAT imm:$pos, GPRnopc:$a, 0)>;
3661 //===----------------------------------------------------------------------===//
3662 // Bitwise Instructions.
3665 defm AND : AsI1_bin_irs<0b0000, "and",
3666 IIC_iBITi, IIC_iBITr, IIC_iBITsr,
3667 BinOpFrag<(and node:$LHS, node:$RHS)>, 1>;
3668 defm ORR : AsI1_bin_irs<0b1100, "orr",
3669 IIC_iBITi, IIC_iBITr, IIC_iBITsr,
3670 BinOpFrag<(or node:$LHS, node:$RHS)>, 1>;
3671 defm EOR : AsI1_bin_irs<0b0001, "eor",
3672 IIC_iBITi, IIC_iBITr, IIC_iBITsr,
3673 BinOpFrag<(xor node:$LHS, node:$RHS)>, 1>;
3674 defm BIC : AsI1_bin_irs<0b1110, "bic",
3675 IIC_iBITi, IIC_iBITr, IIC_iBITsr,
3676 BinOpFrag<(and node:$LHS, (not node:$RHS))>>;
3678 // FIXME: bf_inv_mask_imm should be two operands, the lsb and the msb, just
3679 // like in the actual instruction encoding. The complexity of mapping the mask
3680 // to the lsb/msb pair should be handled by ISel, not encapsulated in the
3681 // instruction description.
3682 def BFC : I<(outs GPR:$Rd), (ins GPR:$src, bf_inv_mask_imm:$imm),
3683 AddrMode1, 4, IndexModeNone, DPFrm, IIC_iUNAsi,
3684 "bfc", "\t$Rd, $imm", "$src = $Rd",
3685 [(set GPR:$Rd, (and GPR:$src, bf_inv_mask_imm:$imm))]>,
3686 Requires<[IsARM, HasV6T2]> {
3689 let Inst{27-21} = 0b0111110;
3690 let Inst{6-0} = 0b0011111;
3691 let Inst{15-12} = Rd;
3692 let Inst{11-7} = imm{4-0}; // lsb
3693 let Inst{20-16} = imm{9-5}; // msb
3696 // A8.6.18 BFI - Bitfield insert (Encoding A1)
3697 def BFI:I<(outs GPRnopc:$Rd), (ins GPRnopc:$src, GPR:$Rn, bf_inv_mask_imm:$imm),
3698 AddrMode1, 4, IndexModeNone, DPFrm, IIC_iUNAsi,
3699 "bfi", "\t$Rd, $Rn, $imm", "$src = $Rd",
3700 [(set GPRnopc:$Rd, (ARMbfi GPRnopc:$src, GPR:$Rn,
3701 bf_inv_mask_imm:$imm))]>,
3702 Requires<[IsARM, HasV6T2]> {
3706 let Inst{27-21} = 0b0111110;
3707 let Inst{6-4} = 0b001; // Rn: Inst{3-0} != 15
3708 let Inst{15-12} = Rd;
3709 let Inst{11-7} = imm{4-0}; // lsb
3710 let Inst{20-16} = imm{9-5}; // width
3714 def MVNr : AsI1<0b1111, (outs GPR:$Rd), (ins GPR:$Rm), DPFrm, IIC_iMVNr,
3715 "mvn", "\t$Rd, $Rm",
3716 [(set GPR:$Rd, (not GPR:$Rm))]>, UnaryDP, Sched<[WriteALU]> {
3720 let Inst{19-16} = 0b0000;
3721 let Inst{11-4} = 0b00000000;
3722 let Inst{15-12} = Rd;
3725 def MVNsi : AsI1<0b1111, (outs GPR:$Rd), (ins so_reg_imm:$shift),
3726 DPSoRegImmFrm, IIC_iMVNsr, "mvn", "\t$Rd, $shift",
3727 [(set GPR:$Rd, (not so_reg_imm:$shift))]>, UnaryDP,
3732 let Inst{19-16} = 0b0000;
3733 let Inst{15-12} = Rd;
3734 let Inst{11-5} = shift{11-5};
3736 let Inst{3-0} = shift{3-0};
3738 def MVNsr : AsI1<0b1111, (outs GPR:$Rd), (ins so_reg_reg:$shift),
3739 DPSoRegRegFrm, IIC_iMVNsr, "mvn", "\t$Rd, $shift",
3740 [(set GPR:$Rd, (not so_reg_reg:$shift))]>, UnaryDP,
3745 let Inst{19-16} = 0b0000;
3746 let Inst{15-12} = Rd;
3747 let Inst{11-8} = shift{11-8};
3749 let Inst{6-5} = shift{6-5};
3751 let Inst{3-0} = shift{3-0};
3753 let isReMaterializable = 1, isAsCheapAsAMove = 1, isMoveImm = 1 in
3754 def MVNi : AsI1<0b1111, (outs GPR:$Rd), (ins mod_imm:$imm), DPFrm,
3755 IIC_iMVNi, "mvn", "\t$Rd, $imm",
3756 [(set GPR:$Rd, mod_imm_not:$imm)]>,UnaryDP, Sched<[WriteALU]> {
3760 let Inst{19-16} = 0b0000;
3761 let Inst{15-12} = Rd;
3762 let Inst{11-0} = imm;
3765 def : ARMPat<(and GPR:$src, mod_imm_not:$imm),
3766 (BICri GPR:$src, mod_imm_not:$imm)>;
3768 //===----------------------------------------------------------------------===//
3769 // Multiply Instructions.
3771 class AsMul1I32<bits<7> opcod, dag oops, dag iops, InstrItinClass itin,
3772 string opc, string asm, list<dag> pattern>
3773 : AsMul1I<opcod, oops, iops, itin, opc, asm, pattern> {
3777 let Inst{19-16} = Rd;
3778 let Inst{11-8} = Rm;
3781 class AsMul1I64<bits<7> opcod, dag oops, dag iops, InstrItinClass itin,
3782 string opc, string asm, list<dag> pattern>
3783 : AsMul1I<opcod, oops, iops, itin, opc, asm, pattern> {
3788 let Inst{19-16} = RdHi;
3789 let Inst{15-12} = RdLo;
3790 let Inst{11-8} = Rm;
3793 class AsMla1I64<bits<7> opcod, dag oops, dag iops, InstrItinClass itin,
3794 string opc, string asm, list<dag> pattern>
3795 : AsMul1I<opcod, oops, iops, itin, opc, asm, pattern> {
3800 let Inst{19-16} = RdHi;
3801 let Inst{15-12} = RdLo;
3802 let Inst{11-8} = Rm;
3806 // FIXME: The v5 pseudos are only necessary for the additional Constraint
3807 // property. Remove them when it's possible to add those properties
3808 // on an individual MachineInstr, not just an instruction description.
3809 let isCommutable = 1, TwoOperandAliasConstraint = "$Rn = $Rd" in {
3810 def MUL : AsMul1I32<0b0000000, (outs GPRnopc:$Rd),
3811 (ins GPRnopc:$Rn, GPRnopc:$Rm),
3812 IIC_iMUL32, "mul", "\t$Rd, $Rn, $Rm",
3813 [(set GPRnopc:$Rd, (mul GPRnopc:$Rn, GPRnopc:$Rm))]>,
3814 Requires<[IsARM, HasV6]> {
3815 let Inst{15-12} = 0b0000;
3816 let Unpredictable{15-12} = 0b1111;
3819 let Constraints = "@earlyclobber $Rd" in
3820 def MULv5: ARMPseudoExpand<(outs GPRnopc:$Rd), (ins GPRnopc:$Rn, GPRnopc:$Rm,
3821 pred:$p, cc_out:$s),
3823 [(set GPRnopc:$Rd, (mul GPRnopc:$Rn, GPRnopc:$Rm))],
3824 (MUL GPRnopc:$Rd, GPRnopc:$Rn, GPRnopc:$Rm, pred:$p, cc_out:$s)>,
3825 Requires<[IsARM, NoV6, UseMulOps]>;
3828 def MLA : AsMul1I32<0b0000001, (outs GPRnopc:$Rd),
3829 (ins GPRnopc:$Rn, GPRnopc:$Rm, GPRnopc:$Ra),
3830 IIC_iMAC32, "mla", "\t$Rd, $Rn, $Rm, $Ra",
3831 [(set GPRnopc:$Rd, (add (mul GPRnopc:$Rn, GPRnopc:$Rm), GPRnopc:$Ra))]>,
3832 Requires<[IsARM, HasV6, UseMulOps]> {
3834 let Inst{15-12} = Ra;
3837 let Constraints = "@earlyclobber $Rd" in
3838 def MLAv5: ARMPseudoExpand<(outs GPRnopc:$Rd),
3839 (ins GPRnopc:$Rn, GPRnopc:$Rm, GPRnopc:$Ra,
3840 pred:$p, cc_out:$s), 4, IIC_iMAC32,
3841 [(set GPRnopc:$Rd, (add (mul GPRnopc:$Rn, GPRnopc:$Rm), GPRnopc:$Ra))],
3842 (MLA GPRnopc:$Rd, GPRnopc:$Rn, GPRnopc:$Rm, GPRnopc:$Ra, pred:$p, cc_out:$s)>,
3843 Requires<[IsARM, NoV6]>;
3845 def MLS : AMul1I<0b0000011, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm, GPR:$Ra),
3846 IIC_iMAC32, "mls", "\t$Rd, $Rn, $Rm, $Ra",
3847 [(set GPR:$Rd, (sub GPR:$Ra, (mul GPR:$Rn, GPR:$Rm)))]>,
3848 Requires<[IsARM, HasV6T2, UseMulOps]> {
3853 let Inst{19-16} = Rd;
3854 let Inst{15-12} = Ra;
3855 let Inst{11-8} = Rm;
3859 // Extra precision multiplies with low / high results
3860 let hasSideEffects = 0 in {
3861 let isCommutable = 1 in {
3862 def SMULL : AsMul1I64<0b0000110, (outs GPR:$RdLo, GPR:$RdHi),
3863 (ins GPR:$Rn, GPR:$Rm), IIC_iMUL64,
3864 "smull", "\t$RdLo, $RdHi, $Rn, $Rm", []>,
3865 Requires<[IsARM, HasV6]>;
3867 def UMULL : AsMul1I64<0b0000100, (outs GPR:$RdLo, GPR:$RdHi),
3868 (ins GPR:$Rn, GPR:$Rm), IIC_iMUL64,
3869 "umull", "\t$RdLo, $RdHi, $Rn, $Rm", []>,
3870 Requires<[IsARM, HasV6]>;
3872 let Constraints = "@earlyclobber $RdLo,@earlyclobber $RdHi" in {
3873 def SMULLv5 : ARMPseudoExpand<(outs GPR:$RdLo, GPR:$RdHi),
3874 (ins GPR:$Rn, GPR:$Rm, pred:$p, cc_out:$s),
3876 (SMULL GPR:$RdLo, GPR:$RdHi, GPR:$Rn, GPR:$Rm, pred:$p, cc_out:$s)>,
3877 Requires<[IsARM, NoV6]>;
3879 def UMULLv5 : ARMPseudoExpand<(outs GPR:$RdLo, GPR:$RdHi),
3880 (ins GPR:$Rn, GPR:$Rm, pred:$p, cc_out:$s),
3882 (UMULL GPR:$RdLo, GPR:$RdHi, GPR:$Rn, GPR:$Rm, pred:$p, cc_out:$s)>,
3883 Requires<[IsARM, NoV6]>;
3887 // Multiply + accumulate
3888 def SMLAL : AsMla1I64<0b0000111, (outs GPR:$RdLo, GPR:$RdHi),
3889 (ins GPR:$Rn, GPR:$Rm, GPR:$RLo, GPR:$RHi), IIC_iMAC64,
3890 "smlal", "\t$RdLo, $RdHi, $Rn, $Rm", []>,
3891 RegConstraint<"$RLo = $RdLo, $RHi = $RdHi">, Requires<[IsARM, HasV6]>;
3892 def UMLAL : AsMla1I64<0b0000101, (outs GPR:$RdLo, GPR:$RdHi),
3893 (ins GPR:$Rn, GPR:$Rm, GPR:$RLo, GPR:$RHi), IIC_iMAC64,
3894 "umlal", "\t$RdLo, $RdHi, $Rn, $Rm", []>,
3895 RegConstraint<"$RLo = $RdLo, $RHi = $RdHi">, Requires<[IsARM, HasV6]>;
3897 def UMAAL : AMul1I <0b0000010, (outs GPR:$RdLo, GPR:$RdHi),
3898 (ins GPR:$Rn, GPR:$Rm), IIC_iMAC64,
3899 "umaal", "\t$RdLo, $RdHi, $Rn, $Rm", []>,
3900 Requires<[IsARM, HasV6]> {
3905 let Inst{19-16} = RdHi;
3906 let Inst{15-12} = RdLo;
3907 let Inst{11-8} = Rm;
3912 "@earlyclobber $RdLo,@earlyclobber $RdHi,$RLo = $RdLo,$RHi = $RdHi" in {
3913 def SMLALv5 : ARMPseudoExpand<(outs GPR:$RdLo, GPR:$RdHi),
3914 (ins GPR:$Rn, GPR:$Rm, GPR:$RLo, GPR:$RHi, pred:$p, cc_out:$s),
3916 (SMLAL GPR:$RdLo, GPR:$RdHi, GPR:$Rn, GPR:$Rm, GPR:$RLo, GPR:$RHi,
3917 pred:$p, cc_out:$s)>,
3918 Requires<[IsARM, NoV6]>;
3919 def UMLALv5 : ARMPseudoExpand<(outs GPR:$RdLo, GPR:$RdHi),
3920 (ins GPR:$Rn, GPR:$Rm, GPR:$RLo, GPR:$RHi, pred:$p, cc_out:$s),
3922 (UMLAL GPR:$RdLo, GPR:$RdHi, GPR:$Rn, GPR:$Rm, GPR:$RLo, GPR:$RHi,
3923 pred:$p, cc_out:$s)>,
3924 Requires<[IsARM, NoV6]>;
3929 // Most significant word multiply
3930 def SMMUL : AMul2I <0b0111010, 0b0001, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm),
3931 IIC_iMUL32, "smmul", "\t$Rd, $Rn, $Rm",
3932 [(set GPR:$Rd, (mulhs GPR:$Rn, GPR:$Rm))]>,
3933 Requires<[IsARM, HasV6]> {
3934 let Inst{15-12} = 0b1111;
3937 def SMMULR : AMul2I <0b0111010, 0b0011, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm),
3938 IIC_iMUL32, "smmulr", "\t$Rd, $Rn, $Rm", []>,
3939 Requires<[IsARM, HasV6]> {
3940 let Inst{15-12} = 0b1111;
3943 def SMMLA : AMul2Ia <0b0111010, 0b0001, (outs GPR:$Rd),
3944 (ins GPR:$Rn, GPR:$Rm, GPR:$Ra),
3945 IIC_iMAC32, "smmla", "\t$Rd, $Rn, $Rm, $Ra",
3946 [(set GPR:$Rd, (add (mulhs GPR:$Rn, GPR:$Rm), GPR:$Ra))]>,
3947 Requires<[IsARM, HasV6, UseMulOps]>;
3949 def SMMLAR : AMul2Ia <0b0111010, 0b0011, (outs GPR:$Rd),
3950 (ins GPR:$Rn, GPR:$Rm, GPR:$Ra),
3951 IIC_iMAC32, "smmlar", "\t$Rd, $Rn, $Rm, $Ra", []>,
3952 Requires<[IsARM, HasV6]>;
3954 def SMMLS : AMul2Ia <0b0111010, 0b1101, (outs GPR:$Rd),
3955 (ins GPR:$Rn, GPR:$Rm, GPR:$Ra),
3956 IIC_iMAC32, "smmls", "\t$Rd, $Rn, $Rm, $Ra", []>,
3957 Requires<[IsARM, HasV6, UseMulOps]>;
3959 def SMMLSR : AMul2Ia <0b0111010, 0b1111, (outs GPR:$Rd),
3960 (ins GPR:$Rn, GPR:$Rm, GPR:$Ra),
3961 IIC_iMAC32, "smmlsr", "\t$Rd, $Rn, $Rm, $Ra", []>,
3962 Requires<[IsARM, HasV6]>;
3964 multiclass AI_smul<string opc, PatFrag opnode> {
3965 def BB : AMulxyI<0b0001011, 0b00, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm),
3966 IIC_iMUL16, !strconcat(opc, "bb"), "\t$Rd, $Rn, $Rm",
3967 [(set GPR:$Rd, (opnode (sext_inreg GPR:$Rn, i16),
3968 (sext_inreg GPR:$Rm, i16)))]>,
3969 Requires<[IsARM, HasV5TE]>;
3971 def BT : AMulxyI<0b0001011, 0b10, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm),
3972 IIC_iMUL16, !strconcat(opc, "bt"), "\t$Rd, $Rn, $Rm",
3973 [(set GPR:$Rd, (opnode (sext_inreg GPR:$Rn, i16),
3974 (sra GPR:$Rm, (i32 16))))]>,
3975 Requires<[IsARM, HasV5TE]>;
3977 def TB : AMulxyI<0b0001011, 0b01, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm),
3978 IIC_iMUL16, !strconcat(opc, "tb"), "\t$Rd, $Rn, $Rm",
3979 [(set GPR:$Rd, (opnode (sra GPR:$Rn, (i32 16)),
3980 (sext_inreg GPR:$Rm, i16)))]>,
3981 Requires<[IsARM, HasV5TE]>;
3983 def TT : AMulxyI<0b0001011, 0b11, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm),
3984 IIC_iMUL16, !strconcat(opc, "tt"), "\t$Rd, $Rn, $Rm",
3985 [(set GPR:$Rd, (opnode (sra GPR:$Rn, (i32 16)),
3986 (sra GPR:$Rm, (i32 16))))]>,
3987 Requires<[IsARM, HasV5TE]>;
3989 def WB : AMulxyI<0b0001001, 0b01, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm),
3990 IIC_iMUL16, !strconcat(opc, "wb"), "\t$Rd, $Rn, $Rm",
3992 Requires<[IsARM, HasV5TE]>;
3994 def WT : AMulxyI<0b0001001, 0b11, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm),
3995 IIC_iMUL16, !strconcat(opc, "wt"), "\t$Rd, $Rn, $Rm",
3997 Requires<[IsARM, HasV5TE]>;
4001 multiclass AI_smla<string opc, PatFrag opnode> {
4002 let DecoderMethod = "DecodeSMLAInstruction" in {
4003 def BB : AMulxyIa<0b0001000, 0b00, (outs GPRnopc:$Rd),
4004 (ins GPRnopc:$Rn, GPRnopc:$Rm, GPR:$Ra),
4005 IIC_iMAC16, !strconcat(opc, "bb"), "\t$Rd, $Rn, $Rm, $Ra",
4006 [(set GPRnopc:$Rd, (add GPR:$Ra,
4007 (opnode (sext_inreg GPRnopc:$Rn, i16),
4008 (sext_inreg GPRnopc:$Rm, i16))))]>,
4009 Requires<[IsARM, HasV5TE, UseMulOps]>;
4011 def BT : AMulxyIa<0b0001000, 0b10, (outs GPRnopc:$Rd),
4012 (ins GPRnopc:$Rn, GPRnopc:$Rm, GPR:$Ra),
4013 IIC_iMAC16, !strconcat(opc, "bt"), "\t$Rd, $Rn, $Rm, $Ra",
4015 (add GPR:$Ra, (opnode (sext_inreg GPRnopc:$Rn, i16),
4016 (sra GPRnopc:$Rm, (i32 16)))))]>,
4017 Requires<[IsARM, HasV5TE, UseMulOps]>;
4019 def TB : AMulxyIa<0b0001000, 0b01, (outs GPRnopc:$Rd),
4020 (ins GPRnopc:$Rn, GPRnopc:$Rm, GPR:$Ra),
4021 IIC_iMAC16, !strconcat(opc, "tb"), "\t$Rd, $Rn, $Rm, $Ra",
4023 (add GPR:$Ra, (opnode (sra GPRnopc:$Rn, (i32 16)),
4024 (sext_inreg GPRnopc:$Rm, i16))))]>,
4025 Requires<[IsARM, HasV5TE, UseMulOps]>;
4027 def TT : AMulxyIa<0b0001000, 0b11, (outs GPRnopc:$Rd),
4028 (ins GPRnopc:$Rn, GPRnopc:$Rm, GPR:$Ra),
4029 IIC_iMAC16, !strconcat(opc, "tt"), "\t$Rd, $Rn, $Rm, $Ra",
4031 (add GPR:$Ra, (opnode (sra GPRnopc:$Rn, (i32 16)),
4032 (sra GPRnopc:$Rm, (i32 16)))))]>,
4033 Requires<[IsARM, HasV5TE, UseMulOps]>;
4035 def WB : AMulxyIa<0b0001001, 0b00, (outs GPRnopc:$Rd),
4036 (ins GPRnopc:$Rn, GPRnopc:$Rm, GPR:$Ra),
4037 IIC_iMAC16, !strconcat(opc, "wb"), "\t$Rd, $Rn, $Rm, $Ra",
4039 Requires<[IsARM, HasV5TE, UseMulOps]>;
4041 def WT : AMulxyIa<0b0001001, 0b10, (outs GPRnopc:$Rd),
4042 (ins GPRnopc:$Rn, GPRnopc:$Rm, GPR:$Ra),
4043 IIC_iMAC16, !strconcat(opc, "wt"), "\t$Rd, $Rn, $Rm, $Ra",
4045 Requires<[IsARM, HasV5TE, UseMulOps]>;
4049 defm SMUL : AI_smul<"smul", BinOpFrag<(mul node:$LHS, node:$RHS)>>;
4050 defm SMLA : AI_smla<"smla", BinOpFrag<(mul node:$LHS, node:$RHS)>>;
4052 // Halfword multiply accumulate long: SMLAL<x><y>.
4053 def SMLALBB : AMulxyI64<0b0001010, 0b00, (outs GPRnopc:$RdLo, GPRnopc:$RdHi),
4054 (ins GPRnopc:$Rn, GPRnopc:$Rm),
4055 IIC_iMAC64, "smlalbb", "\t$RdLo, $RdHi, $Rn, $Rm", []>,
4056 Requires<[IsARM, HasV5TE]>;
4058 def SMLALBT : AMulxyI64<0b0001010, 0b10, (outs GPRnopc:$RdLo, GPRnopc:$RdHi),
4059 (ins GPRnopc:$Rn, GPRnopc:$Rm),
4060 IIC_iMAC64, "smlalbt", "\t$RdLo, $RdHi, $Rn, $Rm", []>,
4061 Requires<[IsARM, HasV5TE]>;
4063 def SMLALTB : AMulxyI64<0b0001010, 0b01, (outs GPRnopc:$RdLo, GPRnopc:$RdHi),
4064 (ins GPRnopc:$Rn, GPRnopc:$Rm),
4065 IIC_iMAC64, "smlaltb", "\t$RdLo, $RdHi, $Rn, $Rm", []>,
4066 Requires<[IsARM, HasV5TE]>;
4068 def SMLALTT : AMulxyI64<0b0001010, 0b11, (outs GPRnopc:$RdLo, GPRnopc:$RdHi),
4069 (ins GPRnopc:$Rn, GPRnopc:$Rm),
4070 IIC_iMAC64, "smlaltt", "\t$RdLo, $RdHi, $Rn, $Rm", []>,
4071 Requires<[IsARM, HasV5TE]>;
4073 // Helper class for AI_smld.
4074 class AMulDualIbase<bit long, bit sub, bit swap, dag oops, dag iops,
4075 InstrItinClass itin, string opc, string asm>
4076 : AI<oops, iops, MulFrm, itin, opc, asm, []>, Requires<[IsARM, HasV6]> {
4079 let Inst{27-23} = 0b01110;
4080 let Inst{22} = long;
4081 let Inst{21-20} = 0b00;
4082 let Inst{11-8} = Rm;
4089 class AMulDualI<bit long, bit sub, bit swap, dag oops, dag iops,
4090 InstrItinClass itin, string opc, string asm>
4091 : AMulDualIbase<long, sub, swap, oops, iops, itin, opc, asm> {
4093 let Inst{15-12} = 0b1111;
4094 let Inst{19-16} = Rd;
4096 class AMulDualIa<bit long, bit sub, bit swap, dag oops, dag iops,
4097 InstrItinClass itin, string opc, string asm>
4098 : AMulDualIbase<long, sub, swap, oops, iops, itin, opc, asm> {
4101 let Inst{19-16} = Rd;
4102 let Inst{15-12} = Ra;
4104 class AMulDualI64<bit long, bit sub, bit swap, dag oops, dag iops,
4105 InstrItinClass itin, string opc, string asm>
4106 : AMulDualIbase<long, sub, swap, oops, iops, itin, opc, asm> {
4109 let Inst{19-16} = RdHi;
4110 let Inst{15-12} = RdLo;
4113 multiclass AI_smld<bit sub, string opc> {
4115 def D : AMulDualIa<0, sub, 0, (outs GPRnopc:$Rd),
4116 (ins GPRnopc:$Rn, GPRnopc:$Rm, GPR:$Ra),
4117 NoItinerary, !strconcat(opc, "d"), "\t$Rd, $Rn, $Rm, $Ra">;
4119 def DX: AMulDualIa<0, sub, 1, (outs GPRnopc:$Rd),
4120 (ins GPRnopc:$Rn, GPRnopc:$Rm, GPR:$Ra),
4121 NoItinerary, !strconcat(opc, "dx"), "\t$Rd, $Rn, $Rm, $Ra">;
4123 def LD: AMulDualI64<1, sub, 0, (outs GPRnopc:$RdLo, GPRnopc:$RdHi),
4124 (ins GPRnopc:$Rn, GPRnopc:$Rm), NoItinerary,
4125 !strconcat(opc, "ld"), "\t$RdLo, $RdHi, $Rn, $Rm">;
4127 def LDX : AMulDualI64<1, sub, 1, (outs GPRnopc:$RdLo, GPRnopc:$RdHi),
4128 (ins GPRnopc:$Rn, GPRnopc:$Rm), NoItinerary,
4129 !strconcat(opc, "ldx"),"\t$RdLo, $RdHi, $Rn, $Rm">;
4133 defm SMLA : AI_smld<0, "smla">;
4134 defm SMLS : AI_smld<1, "smls">;
4136 multiclass AI_sdml<bit sub, string opc> {
4138 def D:AMulDualI<0, sub, 0, (outs GPRnopc:$Rd), (ins GPRnopc:$Rn, GPRnopc:$Rm),
4139 NoItinerary, !strconcat(opc, "d"), "\t$Rd, $Rn, $Rm">;
4140 def DX:AMulDualI<0, sub, 1, (outs GPRnopc:$Rd),(ins GPRnopc:$Rn, GPRnopc:$Rm),
4141 NoItinerary, !strconcat(opc, "dx"), "\t$Rd, $Rn, $Rm">;
4144 defm SMUA : AI_sdml<0, "smua">;
4145 defm SMUS : AI_sdml<1, "smus">;
4147 //===----------------------------------------------------------------------===//
4148 // Division Instructions (ARMv7-A with virtualization extension)
4150 def SDIV : ADivA1I<0b001, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm), IIC_iDIV,
4151 "sdiv", "\t$Rd, $Rn, $Rm",
4152 [(set GPR:$Rd, (sdiv GPR:$Rn, GPR:$Rm))]>,
4153 Requires<[IsARM, HasDivideInARM]>;
4155 def UDIV : ADivA1I<0b011, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm), IIC_iDIV,
4156 "udiv", "\t$Rd, $Rn, $Rm",
4157 [(set GPR:$Rd, (udiv GPR:$Rn, GPR:$Rm))]>,
4158 Requires<[IsARM, HasDivideInARM]>;
4160 //===----------------------------------------------------------------------===//
4161 // Misc. Arithmetic Instructions.
4164 def CLZ : AMiscA1I<0b00010110, 0b0001, (outs GPR:$Rd), (ins GPR:$Rm),
4165 IIC_iUNAr, "clz", "\t$Rd, $Rm",
4166 [(set GPR:$Rd, (ctlz GPR:$Rm))]>, Requires<[IsARM, HasV5T]>,
4169 def RBIT : AMiscA1I<0b01101111, 0b0011, (outs GPR:$Rd), (ins GPR:$Rm),
4170 IIC_iUNAr, "rbit", "\t$Rd, $Rm",
4171 [(set GPR:$Rd, (ARMrbit GPR:$Rm))]>,
4172 Requires<[IsARM, HasV6T2]>,
4175 def REV : AMiscA1I<0b01101011, 0b0011, (outs GPR:$Rd), (ins GPR:$Rm),
4176 IIC_iUNAr, "rev", "\t$Rd, $Rm",
4177 [(set GPR:$Rd, (bswap GPR:$Rm))]>, Requires<[IsARM, HasV6]>,
4180 let AddedComplexity = 5 in
4181 def REV16 : AMiscA1I<0b01101011, 0b1011, (outs GPR:$Rd), (ins GPR:$Rm),
4182 IIC_iUNAr, "rev16", "\t$Rd, $Rm",
4183 [(set GPR:$Rd, (rotr (bswap GPR:$Rm), (i32 16)))]>,
4184 Requires<[IsARM, HasV6]>,
4187 def : ARMV6Pat<(srl (bswap (extloadi16 addrmode3:$addr)), (i32 16)),
4188 (REV16 (LDRH addrmode3:$addr))>;
4189 def : ARMV6Pat<(truncstorei16 (srl (bswap GPR:$Rn), (i32 16)), addrmode3:$addr),
4190 (STRH (REV16 GPR:$Rn), addrmode3:$addr)>;
4192 let AddedComplexity = 5 in
4193 def REVSH : AMiscA1I<0b01101111, 0b1011, (outs GPR:$Rd), (ins GPR:$Rm),
4194 IIC_iUNAr, "revsh", "\t$Rd, $Rm",
4195 [(set GPR:$Rd, (sra (bswap GPR:$Rm), (i32 16)))]>,
4196 Requires<[IsARM, HasV6]>,
4199 def : ARMV6Pat<(or (sra (shl GPR:$Rm, (i32 24)), (i32 16)),
4200 (and (srl GPR:$Rm, (i32 8)), 0xFF)),
4203 def PKHBT : APKHI<0b01101000, 0, (outs GPRnopc:$Rd),
4204 (ins GPRnopc:$Rn, GPRnopc:$Rm, pkh_lsl_amt:$sh),
4205 IIC_iALUsi, "pkhbt", "\t$Rd, $Rn, $Rm$sh",
4206 [(set GPRnopc:$Rd, (or (and GPRnopc:$Rn, 0xFFFF),
4207 (and (shl GPRnopc:$Rm, pkh_lsl_amt:$sh),
4209 Requires<[IsARM, HasV6]>,
4210 Sched<[WriteALUsi, ReadALU]>;
4212 // Alternate cases for PKHBT where identities eliminate some nodes.
4213 def : ARMV6Pat<(or (and GPRnopc:$Rn, 0xFFFF), (and GPRnopc:$Rm, 0xFFFF0000)),
4214 (PKHBT GPRnopc:$Rn, GPRnopc:$Rm, 0)>;
4215 def : ARMV6Pat<(or (and GPRnopc:$Rn, 0xFFFF), (shl GPRnopc:$Rm, imm16_31:$sh)),
4216 (PKHBT GPRnopc:$Rn, GPRnopc:$Rm, imm16_31:$sh)>;
4218 // Note: Shifts of 1-15 bits will be transformed to srl instead of sra and
4219 // will match the pattern below.
4220 def PKHTB : APKHI<0b01101000, 1, (outs GPRnopc:$Rd),
4221 (ins GPRnopc:$Rn, GPRnopc:$Rm, pkh_asr_amt:$sh),
4222 IIC_iBITsi, "pkhtb", "\t$Rd, $Rn, $Rm$sh",
4223 [(set GPRnopc:$Rd, (or (and GPRnopc:$Rn, 0xFFFF0000),
4224 (and (sra GPRnopc:$Rm, pkh_asr_amt:$sh),
4226 Requires<[IsARM, HasV6]>,
4227 Sched<[WriteALUsi, ReadALU]>;
4229 // Alternate cases for PKHTB where identities eliminate some nodes. Note that
4230 // a shift amount of 0 is *not legal* here, it is PKHBT instead.
4231 // We also can not replace a srl (17..31) by an arithmetic shift we would use in
4232 // pkhtb src1, src2, asr (17..31).
4233 def : ARMV6Pat<(or (and GPRnopc:$src1, 0xFFFF0000),
4234 (srl GPRnopc:$src2, imm16:$sh)),
4235 (PKHTB GPRnopc:$src1, GPRnopc:$src2, imm16:$sh)>;
4236 def : ARMV6Pat<(or (and GPRnopc:$src1, 0xFFFF0000),
4237 (sra GPRnopc:$src2, imm16_31:$sh)),
4238 (PKHTB GPRnopc:$src1, GPRnopc:$src2, imm16_31:$sh)>;
4239 def : ARMV6Pat<(or (and GPRnopc:$src1, 0xFFFF0000),
4240 (and (srl GPRnopc:$src2, imm1_15:$sh), 0xFFFF)),
4241 (PKHTB GPRnopc:$src1, GPRnopc:$src2, imm1_15:$sh)>;
4243 //===----------------------------------------------------------------------===//
4247 // + CRC32{B,H,W} 0x04C11DB7
4248 // + CRC32C{B,H,W} 0x1EDC6F41
4251 class AI_crc32<bit C, bits<2> sz, string suffix, SDPatternOperator builtin>
4252 : AInoP<(outs GPRnopc:$Rd), (ins GPRnopc:$Rn, GPRnopc:$Rm), MiscFrm, NoItinerary,
4253 !strconcat("crc32", suffix), "\t$Rd, $Rn, $Rm",
4254 [(set GPRnopc:$Rd, (builtin GPRnopc:$Rn, GPRnopc:$Rm))]>,
4255 Requires<[IsARM, HasV8, HasCRC]> {
4260 let Inst{31-28} = 0b1110;
4261 let Inst{27-23} = 0b00010;
4262 let Inst{22-21} = sz;
4264 let Inst{19-16} = Rn;
4265 let Inst{15-12} = Rd;
4266 let Inst{11-10} = 0b00;
4269 let Inst{7-4} = 0b0100;
4272 let Unpredictable{11-8} = 0b1101;
4275 def CRC32B : AI_crc32<0, 0b00, "b", int_arm_crc32b>;
4276 def CRC32CB : AI_crc32<1, 0b00, "cb", int_arm_crc32cb>;
4277 def CRC32H : AI_crc32<0, 0b01, "h", int_arm_crc32h>;
4278 def CRC32CH : AI_crc32<1, 0b01, "ch", int_arm_crc32ch>;
4279 def CRC32W : AI_crc32<0, 0b10, "w", int_arm_crc32w>;
4280 def CRC32CW : AI_crc32<1, 0b10, "cw", int_arm_crc32cw>;
4282 //===----------------------------------------------------------------------===//
4283 // ARMv8.1a Privilege Access Never extension
4287 def SETPAN : AInoP<(outs), (ins imm0_1:$imm), MiscFrm, NoItinerary, "setpan",
4288 "\t$imm", []>, Requires<[IsARM, HasV8, HasV8_1a]> {
4291 let Inst{31-28} = 0b1111;
4292 let Inst{27-20} = 0b00010001;
4293 let Inst{19-16} = 0b0000;
4294 let Inst{15-10} = 0b000000;
4297 let Inst{7-4} = 0b0000;
4298 let Inst{3-0} = 0b0000;
4300 let Unpredictable{19-16} = 0b1111;
4301 let Unpredictable{15-10} = 0b111111;
4302 let Unpredictable{8} = 0b1;
4303 let Unpredictable{3-0} = 0b1111;
4306 //===----------------------------------------------------------------------===//
4307 // Comparison Instructions...
4310 defm CMP : AI1_cmp_irs<0b1010, "cmp",
4311 IIC_iCMPi, IIC_iCMPr, IIC_iCMPsr,
4312 BinOpFrag<(ARMcmp node:$LHS, node:$RHS)>>;
4314 // ARMcmpZ can re-use the above instruction definitions.
4315 def : ARMPat<(ARMcmpZ GPR:$src, mod_imm:$imm),
4316 (CMPri GPR:$src, mod_imm:$imm)>;
4317 def : ARMPat<(ARMcmpZ GPR:$src, GPR:$rhs),
4318 (CMPrr GPR:$src, GPR:$rhs)>;
4319 def : ARMPat<(ARMcmpZ GPR:$src, so_reg_imm:$rhs),
4320 (CMPrsi GPR:$src, so_reg_imm:$rhs)>;
4321 def : ARMPat<(ARMcmpZ GPR:$src, so_reg_reg:$rhs),
4322 (CMPrsr GPR:$src, so_reg_reg:$rhs)>;
4324 // CMN register-integer
4325 let isCompare = 1, Defs = [CPSR] in {
4326 def CMNri : AI1<0b1011, (outs), (ins GPR:$Rn, mod_imm:$imm), DPFrm, IIC_iCMPi,
4327 "cmn", "\t$Rn, $imm",
4328 [(ARMcmn GPR:$Rn, mod_imm:$imm)]>,
4329 Sched<[WriteCMP, ReadALU]> {
4334 let Inst{19-16} = Rn;
4335 let Inst{15-12} = 0b0000;
4336 let Inst{11-0} = imm;
4338 let Unpredictable{15-12} = 0b1111;
4341 // CMN register-register/shift
4342 def CMNzrr : AI1<0b1011, (outs), (ins GPR:$Rn, GPR:$Rm), DPFrm, IIC_iCMPr,
4343 "cmn", "\t$Rn, $Rm",
4344 [(BinOpFrag<(ARMcmpZ node:$LHS,(ineg node:$RHS))>
4345 GPR:$Rn, GPR:$Rm)]>, Sched<[WriteCMP, ReadALU, ReadALU]> {
4348 let isCommutable = 1;
4351 let Inst{19-16} = Rn;
4352 let Inst{15-12} = 0b0000;
4353 let Inst{11-4} = 0b00000000;
4356 let Unpredictable{15-12} = 0b1111;
4359 def CMNzrsi : AI1<0b1011, (outs),
4360 (ins GPR:$Rn, so_reg_imm:$shift), DPSoRegImmFrm, IIC_iCMPsr,
4361 "cmn", "\t$Rn, $shift",
4362 [(BinOpFrag<(ARMcmpZ node:$LHS,(ineg node:$RHS))>
4363 GPR:$Rn, so_reg_imm:$shift)]>,
4364 Sched<[WriteCMPsi, ReadALU]> {
4369 let Inst{19-16} = Rn;
4370 let Inst{15-12} = 0b0000;
4371 let Inst{11-5} = shift{11-5};
4373 let Inst{3-0} = shift{3-0};
4375 let Unpredictable{15-12} = 0b1111;
4378 def CMNzrsr : AI1<0b1011, (outs),
4379 (ins GPRnopc:$Rn, so_reg_reg:$shift), DPSoRegRegFrm, IIC_iCMPsr,
4380 "cmn", "\t$Rn, $shift",
4381 [(BinOpFrag<(ARMcmpZ node:$LHS,(ineg node:$RHS))>
4382 GPRnopc:$Rn, so_reg_reg:$shift)]>,
4383 Sched<[WriteCMPsr, ReadALU]> {
4388 let Inst{19-16} = Rn;
4389 let Inst{15-12} = 0b0000;
4390 let Inst{11-8} = shift{11-8};
4392 let Inst{6-5} = shift{6-5};
4394 let Inst{3-0} = shift{3-0};
4396 let Unpredictable{15-12} = 0b1111;
4401 def : ARMPat<(ARMcmp GPR:$src, mod_imm_neg:$imm),
4402 (CMNri GPR:$src, mod_imm_neg:$imm)>;
4404 def : ARMPat<(ARMcmpZ GPR:$src, mod_imm_neg:$imm),
4405 (CMNri GPR:$src, mod_imm_neg:$imm)>;
4407 // Note that TST/TEQ don't set all the same flags that CMP does!
4408 defm TST : AI1_cmp_irs<0b1000, "tst",
4409 IIC_iTSTi, IIC_iTSTr, IIC_iTSTsr,
4410 BinOpFrag<(ARMcmpZ (and_su node:$LHS, node:$RHS), 0)>, 1,
4411 "DecodeTSTInstruction">;
4412 defm TEQ : AI1_cmp_irs<0b1001, "teq",
4413 IIC_iTSTi, IIC_iTSTr, IIC_iTSTsr,
4414 BinOpFrag<(ARMcmpZ (xor_su node:$LHS, node:$RHS), 0)>, 1>;
4416 // Pseudo i64 compares for some floating point compares.
4417 let usesCustomInserter = 1, isBranch = 1, isTerminator = 1,
4419 def BCCi64 : PseudoInst<(outs),
4420 (ins i32imm:$cc, GPR:$lhs1, GPR:$lhs2, GPR:$rhs1, GPR:$rhs2, brtarget:$dst),
4422 [(ARMBcci64 imm:$cc, GPR:$lhs1, GPR:$lhs2, GPR:$rhs1, GPR:$rhs2, bb:$dst)]>,
4425 def BCCZi64 : PseudoInst<(outs),
4426 (ins i32imm:$cc, GPR:$lhs1, GPR:$lhs2, brtarget:$dst), IIC_Br,
4427 [(ARMBcci64 imm:$cc, GPR:$lhs1, GPR:$lhs2, 0, 0, bb:$dst)]>,
4429 } // usesCustomInserter
4432 // Conditional moves
4433 let hasSideEffects = 0 in {
4435 let isCommutable = 1, isSelect = 1 in
4436 def MOVCCr : ARMPseudoInst<(outs GPR:$Rd),
4437 (ins GPR:$false, GPR:$Rm, cmovpred:$p),
4439 [(set GPR:$Rd, (ARMcmov GPR:$false, GPR:$Rm,
4441 RegConstraint<"$false = $Rd">, Sched<[WriteALU]>;
4443 def MOVCCsi : ARMPseudoInst<(outs GPR:$Rd),
4444 (ins GPR:$false, so_reg_imm:$shift, cmovpred:$p),
4447 (ARMcmov GPR:$false, so_reg_imm:$shift,
4449 RegConstraint<"$false = $Rd">, Sched<[WriteALU]>;
4450 def MOVCCsr : ARMPseudoInst<(outs GPR:$Rd),
4451 (ins GPR:$false, so_reg_reg:$shift, cmovpred:$p),
4453 [(set GPR:$Rd, (ARMcmov GPR:$false, so_reg_reg:$shift,
4455 RegConstraint<"$false = $Rd">, Sched<[WriteALU]>;
4458 let isMoveImm = 1 in
4460 : ARMPseudoInst<(outs GPR:$Rd),
4461 (ins GPR:$false, imm0_65535_expr:$imm, cmovpred:$p),
4463 [(set GPR:$Rd, (ARMcmov GPR:$false, imm0_65535:$imm,
4465 RegConstraint<"$false = $Rd">, Requires<[IsARM, HasV6T2]>,
4468 let isMoveImm = 1 in
4469 def MOVCCi : ARMPseudoInst<(outs GPR:$Rd),
4470 (ins GPR:$false, mod_imm:$imm, cmovpred:$p),
4472 [(set GPR:$Rd, (ARMcmov GPR:$false, mod_imm:$imm,
4474 RegConstraint<"$false = $Rd">, Sched<[WriteALU]>;
4476 // Two instruction predicate mov immediate.
4477 let isMoveImm = 1 in
4479 : ARMPseudoInst<(outs GPR:$Rd),
4480 (ins GPR:$false, i32imm:$src, cmovpred:$p),
4482 [(set GPR:$Rd, (ARMcmov GPR:$false, imm:$src,
4484 RegConstraint<"$false = $Rd">, Requires<[IsARM, HasV6T2]>;
4486 let isMoveImm = 1 in
4487 def MVNCCi : ARMPseudoInst<(outs GPR:$Rd),
4488 (ins GPR:$false, mod_imm:$imm, cmovpred:$p),
4490 [(set GPR:$Rd, (ARMcmov GPR:$false, mod_imm_not:$imm,
4492 RegConstraint<"$false = $Rd">, Sched<[WriteALU]>;
4497 //===----------------------------------------------------------------------===//
4498 // Atomic operations intrinsics
4501 def MemBarrierOptOperand : AsmOperandClass {
4502 let Name = "MemBarrierOpt";
4503 let ParserMethod = "parseMemBarrierOptOperand";
4505 def memb_opt : Operand<i32> {
4506 let PrintMethod = "printMemBOption";
4507 let ParserMatchClass = MemBarrierOptOperand;
4508 let DecoderMethod = "DecodeMemBarrierOption";
4511 def InstSyncBarrierOptOperand : AsmOperandClass {
4512 let Name = "InstSyncBarrierOpt";
4513 let ParserMethod = "parseInstSyncBarrierOptOperand";
4515 def instsyncb_opt : Operand<i32> {
4516 let PrintMethod = "printInstSyncBOption";
4517 let ParserMatchClass = InstSyncBarrierOptOperand;
4518 let DecoderMethod = "DecodeInstSyncBarrierOption";
4521 // Memory barriers protect the atomic sequences
4522 let hasSideEffects = 1 in {
4523 def DMB : AInoP<(outs), (ins memb_opt:$opt), MiscFrm, NoItinerary,
4524 "dmb", "\t$opt", [(int_arm_dmb (i32 imm0_15:$opt))]>,
4525 Requires<[IsARM, HasDB]> {
4527 let Inst{31-4} = 0xf57ff05;
4528 let Inst{3-0} = opt;
4531 def DSB : AInoP<(outs), (ins memb_opt:$opt), MiscFrm, NoItinerary,
4532 "dsb", "\t$opt", [(int_arm_dsb (i32 imm0_15:$opt))]>,
4533 Requires<[IsARM, HasDB]> {
4535 let Inst{31-4} = 0xf57ff04;
4536 let Inst{3-0} = opt;
4539 // ISB has only full system option
4540 def ISB : AInoP<(outs), (ins instsyncb_opt:$opt), MiscFrm, NoItinerary,
4541 "isb", "\t$opt", [(int_arm_isb (i32 imm0_15:$opt))]>,
4542 Requires<[IsARM, HasDB]> {
4544 let Inst{31-4} = 0xf57ff06;
4545 let Inst{3-0} = opt;
4549 let usesCustomInserter = 1, Defs = [CPSR] in {
4551 // Pseudo instruction that combines movs + predicated rsbmi
4552 // to implement integer ABS
4553 def ABS : ARMPseudoInst<(outs GPR:$dst), (ins GPR:$src), 8, NoItinerary, []>;
4556 let usesCustomInserter = 1 in {
4557 def COPY_STRUCT_BYVAL_I32 : PseudoInst<
4558 (outs), (ins GPR:$dst, GPR:$src, i32imm:$size, i32imm:$alignment),
4560 [(ARMcopystructbyval GPR:$dst, GPR:$src, imm:$size, imm:$alignment)]>;
4563 let hasPostISelHook = 1 in {
4564 def MCOPY : PseudoInst<
4565 (outs GPR:$newdst, GPR:$newsrc), (ins GPR:$dst, GPR:$src, i32imm:$nreg),
4567 [(set GPR:$newdst, GPR:$newsrc, (ARMmcopy GPR:$dst, GPR:$src, imm:$nreg))]>;
4570 def ldrex_1 : PatFrag<(ops node:$ptr), (int_arm_ldrex node:$ptr), [{
4571 return cast<MemIntrinsicSDNode>(N)->getMemoryVT() == MVT::i8;
4574 def ldrex_2 : PatFrag<(ops node:$ptr), (int_arm_ldrex node:$ptr), [{
4575 return cast<MemIntrinsicSDNode>(N)->getMemoryVT() == MVT::i16;
4578 def ldrex_4 : PatFrag<(ops node:$ptr), (int_arm_ldrex node:$ptr), [{
4579 return cast<MemIntrinsicSDNode>(N)->getMemoryVT() == MVT::i32;
4582 def strex_1 : PatFrag<(ops node:$val, node:$ptr),
4583 (int_arm_strex node:$val, node:$ptr), [{
4584 return cast<MemIntrinsicSDNode>(N)->getMemoryVT() == MVT::i8;
4587 def strex_2 : PatFrag<(ops node:$val, node:$ptr),
4588 (int_arm_strex node:$val, node:$ptr), [{
4589 return cast<MemIntrinsicSDNode>(N)->getMemoryVT() == MVT::i16;
4592 def strex_4 : PatFrag<(ops node:$val, node:$ptr),
4593 (int_arm_strex node:$val, node:$ptr), [{
4594 return cast<MemIntrinsicSDNode>(N)->getMemoryVT() == MVT::i32;
4597 def ldaex_1 : PatFrag<(ops node:$ptr), (int_arm_ldaex node:$ptr), [{
4598 return cast<MemIntrinsicSDNode>(N)->getMemoryVT() == MVT::i8;
4601 def ldaex_2 : PatFrag<(ops node:$ptr), (int_arm_ldaex node:$ptr), [{
4602 return cast<MemIntrinsicSDNode>(N)->getMemoryVT() == MVT::i16;
4605 def ldaex_4 : PatFrag<(ops node:$ptr), (int_arm_ldaex node:$ptr), [{
4606 return cast<MemIntrinsicSDNode>(N)->getMemoryVT() == MVT::i32;
4609 def stlex_1 : PatFrag<(ops node:$val, node:$ptr),
4610 (int_arm_stlex node:$val, node:$ptr), [{
4611 return cast<MemIntrinsicSDNode>(N)->getMemoryVT() == MVT::i8;
4614 def stlex_2 : PatFrag<(ops node:$val, node:$ptr),
4615 (int_arm_stlex node:$val, node:$ptr), [{
4616 return cast<MemIntrinsicSDNode>(N)->getMemoryVT() == MVT::i16;
4619 def stlex_4 : PatFrag<(ops node:$val, node:$ptr),
4620 (int_arm_stlex node:$val, node:$ptr), [{
4621 return cast<MemIntrinsicSDNode>(N)->getMemoryVT() == MVT::i32;
4624 let mayLoad = 1 in {
4625 def LDREXB : AIldrex<0b10, (outs GPR:$Rt), (ins addr_offset_none:$addr),
4626 NoItinerary, "ldrexb", "\t$Rt, $addr",
4627 [(set GPR:$Rt, (ldrex_1 addr_offset_none:$addr))]>;
4628 def LDREXH : AIldrex<0b11, (outs GPR:$Rt), (ins addr_offset_none:$addr),
4629 NoItinerary, "ldrexh", "\t$Rt, $addr",
4630 [(set GPR:$Rt, (ldrex_2 addr_offset_none:$addr))]>;
4631 def LDREX : AIldrex<0b00, (outs GPR:$Rt), (ins addr_offset_none:$addr),
4632 NoItinerary, "ldrex", "\t$Rt, $addr",
4633 [(set GPR:$Rt, (ldrex_4 addr_offset_none:$addr))]>;
4634 let hasExtraDefRegAllocReq = 1 in
4635 def LDREXD : AIldrex<0b01, (outs GPRPairOp:$Rt),(ins addr_offset_none:$addr),
4636 NoItinerary, "ldrexd", "\t$Rt, $addr", []> {
4637 let DecoderMethod = "DecodeDoubleRegLoad";
4640 def LDAEXB : AIldaex<0b10, (outs GPR:$Rt), (ins addr_offset_none:$addr),
4641 NoItinerary, "ldaexb", "\t$Rt, $addr",
4642 [(set GPR:$Rt, (ldaex_1 addr_offset_none:$addr))]>;
4643 def LDAEXH : AIldaex<0b11, (outs GPR:$Rt), (ins addr_offset_none:$addr),
4644 NoItinerary, "ldaexh", "\t$Rt, $addr",
4645 [(set GPR:$Rt, (ldaex_2 addr_offset_none:$addr))]>;
4646 def LDAEX : AIldaex<0b00, (outs GPR:$Rt), (ins addr_offset_none:$addr),
4647 NoItinerary, "ldaex", "\t$Rt, $addr",
4648 [(set GPR:$Rt, (ldaex_4 addr_offset_none:$addr))]>;
4649 let hasExtraDefRegAllocReq = 1 in
4650 def LDAEXD : AIldaex<0b01, (outs GPRPairOp:$Rt),(ins addr_offset_none:$addr),
4651 NoItinerary, "ldaexd", "\t$Rt, $addr", []> {
4652 let DecoderMethod = "DecodeDoubleRegLoad";
4656 let mayStore = 1, Constraints = "@earlyclobber $Rd" in {
4657 def STREXB: AIstrex<0b10, (outs GPR:$Rd), (ins GPR:$Rt, addr_offset_none:$addr),
4658 NoItinerary, "strexb", "\t$Rd, $Rt, $addr",
4659 [(set GPR:$Rd, (strex_1 GPR:$Rt,
4660 addr_offset_none:$addr))]>;
4661 def STREXH: AIstrex<0b11, (outs GPR:$Rd), (ins GPR:$Rt, addr_offset_none:$addr),
4662 NoItinerary, "strexh", "\t$Rd, $Rt, $addr",
4663 [(set GPR:$Rd, (strex_2 GPR:$Rt,
4664 addr_offset_none:$addr))]>;
4665 def STREX : AIstrex<0b00, (outs GPR:$Rd), (ins GPR:$Rt, addr_offset_none:$addr),
4666 NoItinerary, "strex", "\t$Rd, $Rt, $addr",
4667 [(set GPR:$Rd, (strex_4 GPR:$Rt,
4668 addr_offset_none:$addr))]>;
4669 let hasExtraSrcRegAllocReq = 1 in
4670 def STREXD : AIstrex<0b01, (outs GPR:$Rd),
4671 (ins GPRPairOp:$Rt, addr_offset_none:$addr),
4672 NoItinerary, "strexd", "\t$Rd, $Rt, $addr", []> {
4673 let DecoderMethod = "DecodeDoubleRegStore";
4675 def STLEXB: AIstlex<0b10, (outs GPR:$Rd), (ins GPR:$Rt, addr_offset_none:$addr),
4676 NoItinerary, "stlexb", "\t$Rd, $Rt, $addr",
4678 (stlex_1 GPR:$Rt, addr_offset_none:$addr))]>;
4679 def STLEXH: AIstlex<0b11, (outs GPR:$Rd), (ins GPR:$Rt, addr_offset_none:$addr),
4680 NoItinerary, "stlexh", "\t$Rd, $Rt, $addr",
4682 (stlex_2 GPR:$Rt, addr_offset_none:$addr))]>;
4683 def STLEX : AIstlex<0b00, (outs GPR:$Rd), (ins GPR:$Rt, addr_offset_none:$addr),
4684 NoItinerary, "stlex", "\t$Rd, $Rt, $addr",
4686 (stlex_4 GPR:$Rt, addr_offset_none:$addr))]>;
4687 let hasExtraSrcRegAllocReq = 1 in
4688 def STLEXD : AIstlex<0b01, (outs GPR:$Rd),
4689 (ins GPRPairOp:$Rt, addr_offset_none:$addr),
4690 NoItinerary, "stlexd", "\t$Rd, $Rt, $addr", []> {
4691 let DecoderMethod = "DecodeDoubleRegStore";
4695 def CLREX : AXI<(outs), (ins), MiscFrm, NoItinerary, "clrex",
4697 Requires<[IsARM, HasV7]> {
4698 let Inst{31-0} = 0b11110101011111111111000000011111;
4701 def : ARMPat<(strex_1 (and GPR:$Rt, 0xff), addr_offset_none:$addr),
4702 (STREXB GPR:$Rt, addr_offset_none:$addr)>;
4703 def : ARMPat<(strex_2 (and GPR:$Rt, 0xffff), addr_offset_none:$addr),
4704 (STREXH GPR:$Rt, addr_offset_none:$addr)>;
4706 def : ARMPat<(stlex_1 (and GPR:$Rt, 0xff), addr_offset_none:$addr),
4707 (STLEXB GPR:$Rt, addr_offset_none:$addr)>;
4708 def : ARMPat<(stlex_2 (and GPR:$Rt, 0xffff), addr_offset_none:$addr),
4709 (STLEXH GPR:$Rt, addr_offset_none:$addr)>;
4711 class acquiring_load<PatFrag base>
4712 : PatFrag<(ops node:$ptr), (base node:$ptr), [{
4713 AtomicOrdering Ordering = cast<AtomicSDNode>(N)->getOrdering();
4714 return isAtLeastAcquire(Ordering);
4717 def atomic_load_acquire_8 : acquiring_load<atomic_load_8>;
4718 def atomic_load_acquire_16 : acquiring_load<atomic_load_16>;
4719 def atomic_load_acquire_32 : acquiring_load<atomic_load_32>;
4721 class releasing_store<PatFrag base>
4722 : PatFrag<(ops node:$ptr, node:$val), (base node:$ptr, node:$val), [{
4723 AtomicOrdering Ordering = cast<AtomicSDNode>(N)->getOrdering();
4724 return isAtLeastRelease(Ordering);
4727 def atomic_store_release_8 : releasing_store<atomic_store_8>;
4728 def atomic_store_release_16 : releasing_store<atomic_store_16>;
4729 def atomic_store_release_32 : releasing_store<atomic_store_32>;
4731 let AddedComplexity = 8 in {
4732 def : ARMPat<(atomic_load_acquire_8 addr_offset_none:$addr), (LDAB addr_offset_none:$addr)>;
4733 def : ARMPat<(atomic_load_acquire_16 addr_offset_none:$addr), (LDAH addr_offset_none:$addr)>;
4734 def : ARMPat<(atomic_load_acquire_32 addr_offset_none:$addr), (LDA addr_offset_none:$addr)>;
4735 def : ARMPat<(atomic_store_release_8 addr_offset_none:$addr, GPR:$val), (STLB GPR:$val, addr_offset_none:$addr)>;
4736 def : ARMPat<(atomic_store_release_16 addr_offset_none:$addr, GPR:$val), (STLH GPR:$val, addr_offset_none:$addr)>;
4737 def : ARMPat<(atomic_store_release_32 addr_offset_none:$addr, GPR:$val), (STL GPR:$val, addr_offset_none:$addr)>;
4740 // SWP/SWPB are deprecated in V6/V7.
4741 let mayLoad = 1, mayStore = 1 in {
4742 def SWP : AIswp<0, (outs GPRnopc:$Rt),
4743 (ins GPRnopc:$Rt2, addr_offset_none:$addr), "swp", []>,
4745 def SWPB: AIswp<1, (outs GPRnopc:$Rt),
4746 (ins GPRnopc:$Rt2, addr_offset_none:$addr), "swpb", []>,
4750 //===----------------------------------------------------------------------===//
4751 // Coprocessor Instructions.
4754 def CDP : ABI<0b1110, (outs), (ins p_imm:$cop, imm0_15:$opc1,
4755 c_imm:$CRd, c_imm:$CRn, c_imm:$CRm, imm0_7:$opc2),
4756 NoItinerary, "cdp", "\t$cop, $opc1, $CRd, $CRn, $CRm, $opc2",
4757 [(int_arm_cdp imm:$cop, imm:$opc1, imm:$CRd, imm:$CRn,
4758 imm:$CRm, imm:$opc2)]>,
4767 let Inst{3-0} = CRm;
4769 let Inst{7-5} = opc2;
4770 let Inst{11-8} = cop;
4771 let Inst{15-12} = CRd;
4772 let Inst{19-16} = CRn;
4773 let Inst{23-20} = opc1;
4776 def CDP2 : ABXI<0b1110, (outs), (ins p_imm:$cop, imm0_15:$opc1,
4777 c_imm:$CRd, c_imm:$CRn, c_imm:$CRm, imm0_7:$opc2),
4778 NoItinerary, "cdp2\t$cop, $opc1, $CRd, $CRn, $CRm, $opc2",
4779 [(int_arm_cdp2 imm:$cop, imm:$opc1, imm:$CRd, imm:$CRn,
4780 imm:$CRm, imm:$opc2)]>,
4782 let Inst{31-28} = 0b1111;
4790 let Inst{3-0} = CRm;
4792 let Inst{7-5} = opc2;
4793 let Inst{11-8} = cop;
4794 let Inst{15-12} = CRd;
4795 let Inst{19-16} = CRn;
4796 let Inst{23-20} = opc1;
4799 class ACI<dag oops, dag iops, string opc, string asm,
4800 IndexMode im = IndexModeNone>
4801 : I<oops, iops, AddrModeNone, 4, im, BrFrm, NoItinerary,
4803 let Inst{27-25} = 0b110;
4805 class ACInoP<dag oops, dag iops, string opc, string asm,
4806 IndexMode im = IndexModeNone>
4807 : InoP<oops, iops, AddrModeNone, 4, im, BrFrm, NoItinerary,
4809 let Inst{31-28} = 0b1111;
4810 let Inst{27-25} = 0b110;
4812 multiclass LdStCop<bit load, bit Dbit, string asm> {
4813 def _OFFSET : ACI<(outs), (ins p_imm:$cop, c_imm:$CRd, addrmode5:$addr),
4814 asm, "\t$cop, $CRd, $addr"> {
4818 let Inst{24} = 1; // P = 1
4819 let Inst{23} = addr{8};
4820 let Inst{22} = Dbit;
4821 let Inst{21} = 0; // W = 0
4822 let Inst{20} = load;
4823 let Inst{19-16} = addr{12-9};
4824 let Inst{15-12} = CRd;
4825 let Inst{11-8} = cop;
4826 let Inst{7-0} = addr{7-0};
4827 let DecoderMethod = "DecodeCopMemInstruction";
4829 def _PRE : ACI<(outs), (ins p_imm:$cop, c_imm:$CRd, addrmode5_pre:$addr),
4830 asm, "\t$cop, $CRd, $addr!", IndexModePre> {
4834 let Inst{24} = 1; // P = 1
4835 let Inst{23} = addr{8};
4836 let Inst{22} = Dbit;
4837 let Inst{21} = 1; // W = 1
4838 let Inst{20} = load;
4839 let Inst{19-16} = addr{12-9};
4840 let Inst{15-12} = CRd;
4841 let Inst{11-8} = cop;
4842 let Inst{7-0} = addr{7-0};
4843 let DecoderMethod = "DecodeCopMemInstruction";
4845 def _POST: ACI<(outs), (ins p_imm:$cop, c_imm:$CRd, addr_offset_none:$addr,
4846 postidx_imm8s4:$offset),
4847 asm, "\t$cop, $CRd, $addr, $offset", IndexModePost> {
4852 let Inst{24} = 0; // P = 0
4853 let Inst{23} = offset{8};
4854 let Inst{22} = Dbit;
4855 let Inst{21} = 1; // W = 1
4856 let Inst{20} = load;
4857 let Inst{19-16} = addr;
4858 let Inst{15-12} = CRd;
4859 let Inst{11-8} = cop;
4860 let Inst{7-0} = offset{7-0};
4861 let DecoderMethod = "DecodeCopMemInstruction";
4863 def _OPTION : ACI<(outs),
4864 (ins p_imm:$cop, c_imm:$CRd, addr_offset_none:$addr,
4865 coproc_option_imm:$option),
4866 asm, "\t$cop, $CRd, $addr, $option"> {
4871 let Inst{24} = 0; // P = 0
4872 let Inst{23} = 1; // U = 1
4873 let Inst{22} = Dbit;
4874 let Inst{21} = 0; // W = 0
4875 let Inst{20} = load;
4876 let Inst{19-16} = addr;
4877 let Inst{15-12} = CRd;
4878 let Inst{11-8} = cop;
4879 let Inst{7-0} = option;
4880 let DecoderMethod = "DecodeCopMemInstruction";
4883 multiclass LdSt2Cop<bit load, bit Dbit, string asm> {
4884 def _OFFSET : ACInoP<(outs), (ins p_imm:$cop, c_imm:$CRd, addrmode5:$addr),
4885 asm, "\t$cop, $CRd, $addr"> {
4889 let Inst{24} = 1; // P = 1
4890 let Inst{23} = addr{8};
4891 let Inst{22} = Dbit;
4892 let Inst{21} = 0; // W = 0
4893 let Inst{20} = load;
4894 let Inst{19-16} = addr{12-9};
4895 let Inst{15-12} = CRd;
4896 let Inst{11-8} = cop;
4897 let Inst{7-0} = addr{7-0};
4898 let DecoderMethod = "DecodeCopMemInstruction";
4900 def _PRE : ACInoP<(outs), (ins p_imm:$cop, c_imm:$CRd, addrmode5_pre:$addr),
4901 asm, "\t$cop, $CRd, $addr!", IndexModePre> {
4905 let Inst{24} = 1; // P = 1
4906 let Inst{23} = addr{8};
4907 let Inst{22} = Dbit;
4908 let Inst{21} = 1; // W = 1
4909 let Inst{20} = load;
4910 let Inst{19-16} = addr{12-9};
4911 let Inst{15-12} = CRd;
4912 let Inst{11-8} = cop;
4913 let Inst{7-0} = addr{7-0};
4914 let DecoderMethod = "DecodeCopMemInstruction";
4916 def _POST: ACInoP<(outs), (ins p_imm:$cop, c_imm:$CRd, addr_offset_none:$addr,
4917 postidx_imm8s4:$offset),
4918 asm, "\t$cop, $CRd, $addr, $offset", IndexModePost> {
4923 let Inst{24} = 0; // P = 0
4924 let Inst{23} = offset{8};
4925 let Inst{22} = Dbit;
4926 let Inst{21} = 1; // W = 1
4927 let Inst{20} = load;
4928 let Inst{19-16} = addr;
4929 let Inst{15-12} = CRd;
4930 let Inst{11-8} = cop;
4931 let Inst{7-0} = offset{7-0};
4932 let DecoderMethod = "DecodeCopMemInstruction";
4934 def _OPTION : ACInoP<(outs),
4935 (ins p_imm:$cop, c_imm:$CRd, addr_offset_none:$addr,
4936 coproc_option_imm:$option),
4937 asm, "\t$cop, $CRd, $addr, $option"> {
4942 let Inst{24} = 0; // P = 0
4943 let Inst{23} = 1; // U = 1
4944 let Inst{22} = Dbit;
4945 let Inst{21} = 0; // W = 0
4946 let Inst{20} = load;
4947 let Inst{19-16} = addr;
4948 let Inst{15-12} = CRd;
4949 let Inst{11-8} = cop;
4950 let Inst{7-0} = option;
4951 let DecoderMethod = "DecodeCopMemInstruction";
4955 defm LDC : LdStCop <1, 0, "ldc">;
4956 defm LDCL : LdStCop <1, 1, "ldcl">;
4957 defm STC : LdStCop <0, 0, "stc">;
4958 defm STCL : LdStCop <0, 1, "stcl">;
4959 defm LDC2 : LdSt2Cop<1, 0, "ldc2">, Requires<[PreV8]>;
4960 defm LDC2L : LdSt2Cop<1, 1, "ldc2l">, Requires<[PreV8]>;
4961 defm STC2 : LdSt2Cop<0, 0, "stc2">, Requires<[PreV8]>;
4962 defm STC2L : LdSt2Cop<0, 1, "stc2l">, Requires<[PreV8]>;
4964 //===----------------------------------------------------------------------===//
4965 // Move between coprocessor and ARM core register.
4968 class MovRCopro<string opc, bit direction, dag oops, dag iops,
4970 : ABI<0b1110, oops, iops, NoItinerary, opc,
4971 "\t$cop, $opc1, $Rt, $CRn, $CRm, $opc2", pattern> {
4972 let Inst{20} = direction;
4982 let Inst{15-12} = Rt;
4983 let Inst{11-8} = cop;
4984 let Inst{23-21} = opc1;
4985 let Inst{7-5} = opc2;
4986 let Inst{3-0} = CRm;
4987 let Inst{19-16} = CRn;
4990 def MCR : MovRCopro<"mcr", 0 /* from ARM core register to coprocessor */,
4992 (ins p_imm:$cop, imm0_7:$opc1, GPR:$Rt, c_imm:$CRn,
4993 c_imm:$CRm, imm0_7:$opc2),
4994 [(int_arm_mcr imm:$cop, imm:$opc1, GPR:$Rt, imm:$CRn,
4995 imm:$CRm, imm:$opc2)]>,
4996 ComplexDeprecationPredicate<"MCR">;
4997 def : ARMInstAlias<"mcr${p} $cop, $opc1, $Rt, $CRn, $CRm",
4998 (MCR p_imm:$cop, imm0_7:$opc1, GPR:$Rt, c_imm:$CRn,
4999 c_imm:$CRm, 0, pred:$p)>;
5000 def MRC : MovRCopro<"mrc", 1 /* from coprocessor to ARM core register */,
5001 (outs GPRwithAPSR:$Rt),
5002 (ins p_imm:$cop, imm0_7:$opc1, c_imm:$CRn, c_imm:$CRm,
5004 def : ARMInstAlias<"mrc${p} $cop, $opc1, $Rt, $CRn, $CRm",
5005 (MRC GPRwithAPSR:$Rt, p_imm:$cop, imm0_7:$opc1, c_imm:$CRn,
5006 c_imm:$CRm, 0, pred:$p)>;
5008 def : ARMPat<(int_arm_mrc imm:$cop, imm:$opc1, imm:$CRn, imm:$CRm, imm:$opc2),
5009 (MRC imm:$cop, imm:$opc1, imm:$CRn, imm:$CRm, imm:$opc2)>;
5011 class MovRCopro2<string opc, bit direction, dag oops, dag iops,
5013 : ABXI<0b1110, oops, iops, NoItinerary,
5014 !strconcat(opc, "\t$cop, $opc1, $Rt, $CRn, $CRm, $opc2"), pattern> {
5015 let Inst{31-24} = 0b11111110;
5016 let Inst{20} = direction;
5026 let Inst{15-12} = Rt;
5027 let Inst{11-8} = cop;
5028 let Inst{23-21} = opc1;
5029 let Inst{7-5} = opc2;
5030 let Inst{3-0} = CRm;
5031 let Inst{19-16} = CRn;
5034 def MCR2 : MovRCopro2<"mcr2", 0 /* from ARM core register to coprocessor */,
5036 (ins p_imm:$cop, imm0_7:$opc1, GPR:$Rt, c_imm:$CRn,
5037 c_imm:$CRm, imm0_7:$opc2),
5038 [(int_arm_mcr2 imm:$cop, imm:$opc1, GPR:$Rt, imm:$CRn,
5039 imm:$CRm, imm:$opc2)]>,
5041 def : ARMInstAlias<"mcr2 $cop, $opc1, $Rt, $CRn, $CRm",
5042 (MCR2 p_imm:$cop, imm0_7:$opc1, GPR:$Rt, c_imm:$CRn,
5044 def MRC2 : MovRCopro2<"mrc2", 1 /* from coprocessor to ARM core register */,
5045 (outs GPRwithAPSR:$Rt),
5046 (ins p_imm:$cop, imm0_7:$opc1, c_imm:$CRn, c_imm:$CRm,
5049 def : ARMInstAlias<"mrc2 $cop, $opc1, $Rt, $CRn, $CRm",
5050 (MRC2 GPRwithAPSR:$Rt, p_imm:$cop, imm0_7:$opc1, c_imm:$CRn,
5053 def : ARMV5TPat<(int_arm_mrc2 imm:$cop, imm:$opc1, imm:$CRn,
5054 imm:$CRm, imm:$opc2),
5055 (MRC2 imm:$cop, imm:$opc1, imm:$CRn, imm:$CRm, imm:$opc2)>;
5057 class MovRRCopro<string opc, bit direction, list<dag> pattern = []>
5058 : ABI<0b1100, (outs), (ins p_imm:$cop, imm0_15:$opc1,
5059 GPRnopc:$Rt, GPRnopc:$Rt2, c_imm:$CRm),
5060 NoItinerary, opc, "\t$cop, $opc1, $Rt, $Rt2, $CRm", pattern> {
5061 let Inst{23-21} = 0b010;
5062 let Inst{20} = direction;
5070 let Inst{15-12} = Rt;
5071 let Inst{19-16} = Rt2;
5072 let Inst{11-8} = cop;
5073 let Inst{7-4} = opc1;
5074 let Inst{3-0} = CRm;
5077 def MCRR : MovRRCopro<"mcrr", 0 /* from ARM core register to coprocessor */,
5078 [(int_arm_mcrr imm:$cop, imm:$opc1, GPRnopc:$Rt,
5079 GPRnopc:$Rt2, imm:$CRm)]>;
5080 def MRRC : MovRRCopro<"mrrc", 1 /* from coprocessor to ARM core register */>;
5082 class MovRRCopro2<string opc, bit direction, list<dag> pattern = []>
5083 : ABXI<0b1100, (outs), (ins p_imm:$cop, imm0_15:$opc1,
5084 GPRnopc:$Rt, GPRnopc:$Rt2, c_imm:$CRm), NoItinerary,
5085 !strconcat(opc, "\t$cop, $opc1, $Rt, $Rt2, $CRm"), pattern>,
5087 let Inst{31-28} = 0b1111;
5088 let Inst{23-21} = 0b010;
5089 let Inst{20} = direction;
5097 let Inst{15-12} = Rt;
5098 let Inst{19-16} = Rt2;
5099 let Inst{11-8} = cop;
5100 let Inst{7-4} = opc1;
5101 let Inst{3-0} = CRm;
5103 let DecoderMethod = "DecodeMRRC2";
5106 def MCRR2 : MovRRCopro2<"mcrr2", 0 /* from ARM core register to coprocessor */,
5107 [(int_arm_mcrr2 imm:$cop, imm:$opc1, GPRnopc:$Rt,
5108 GPRnopc:$Rt2, imm:$CRm)]>;
5109 def MRRC2 : MovRRCopro2<"mrrc2", 1 /* from coprocessor to ARM core register */>;
5111 //===----------------------------------------------------------------------===//
5112 // Move between special register and ARM core register
5115 // Move to ARM core register from Special Register
5116 def MRS : ABI<0b0001, (outs GPRnopc:$Rd), (ins), NoItinerary,
5117 "mrs", "\t$Rd, apsr", []> {
5119 let Inst{23-16} = 0b00001111;
5120 let Unpredictable{19-17} = 0b111;
5122 let Inst{15-12} = Rd;
5124 let Inst{11-0} = 0b000000000000;
5125 let Unpredictable{11-0} = 0b110100001111;
5128 def : InstAlias<"mrs${p} $Rd, cpsr", (MRS GPRnopc:$Rd, pred:$p)>,
5131 // The MRSsys instruction is the MRS instruction from the ARM ARM,
5132 // section B9.3.9, with the R bit set to 1.
5133 def MRSsys : ABI<0b0001, (outs GPRnopc:$Rd), (ins), NoItinerary,
5134 "mrs", "\t$Rd, spsr", []> {
5136 let Inst{23-16} = 0b01001111;
5137 let Unpredictable{19-16} = 0b1111;
5139 let Inst{15-12} = Rd;
5141 let Inst{11-0} = 0b000000000000;
5142 let Unpredictable{11-0} = 0b110100001111;
5145 // However, the MRS (banked register) system instruction (ARMv7VE) *does* have a
5146 // separate encoding (distinguished by bit 5.
5147 def MRSbanked : ABI<0b0001, (outs GPRnopc:$Rd), (ins banked_reg:$banked),
5148 NoItinerary, "mrs", "\t$Rd, $banked", []>,
5149 Requires<[IsARM, HasVirtualization]> {
5154 let Inst{22} = banked{5}; // R bit
5155 let Inst{21-20} = 0b00;
5156 let Inst{19-16} = banked{3-0};
5157 let Inst{15-12} = Rd;
5158 let Inst{11-9} = 0b001;
5159 let Inst{8} = banked{4};
5160 let Inst{7-0} = 0b00000000;
5163 // Move from ARM core register to Special Register
5165 // No need to have both system and application versions of MSR (immediate) or
5166 // MSR (register), the encodings are the same and the assembly parser has no way
5167 // to distinguish between them. The mask operand contains the special register
5168 // (R Bit) in bit 4 and bits 3-0 contains the mask with the fields to be
5169 // accessed in the special register.
5170 def MSR : ABI<0b0001, (outs), (ins msr_mask:$mask, GPR:$Rn), NoItinerary,
5171 "msr", "\t$mask, $Rn", []> {
5176 let Inst{22} = mask{4}; // R bit
5177 let Inst{21-20} = 0b10;
5178 let Inst{19-16} = mask{3-0};
5179 let Inst{15-12} = 0b1111;
5180 let Inst{11-4} = 0b00000000;
5184 def MSRi : ABI<0b0011, (outs), (ins msr_mask:$mask, mod_imm:$imm), NoItinerary,
5185 "msr", "\t$mask, $imm", []> {
5190 let Inst{22} = mask{4}; // R bit
5191 let Inst{21-20} = 0b10;
5192 let Inst{19-16} = mask{3-0};
5193 let Inst{15-12} = 0b1111;
5194 let Inst{11-0} = imm;
5197 // However, the MSR (banked register) system instruction (ARMv7VE) *does* have a
5198 // separate encoding (distinguished by bit 5.
5199 def MSRbanked : ABI<0b0001, (outs), (ins banked_reg:$banked, GPRnopc:$Rn),
5200 NoItinerary, "msr", "\t$banked, $Rn", []>,
5201 Requires<[IsARM, HasVirtualization]> {
5206 let Inst{22} = banked{5}; // R bit
5207 let Inst{21-20} = 0b10;
5208 let Inst{19-16} = banked{3-0};
5209 let Inst{15-12} = 0b1111;
5210 let Inst{11-9} = 0b001;
5211 let Inst{8} = banked{4};
5212 let Inst{7-4} = 0b0000;
5216 // Dynamic stack allocation yields a _chkstk for Windows targets. These calls
5217 // are needed to probe the stack when allocating more than
5218 // 4k bytes in one go. Touching the stack at 4K increments is necessary to
5219 // ensure that the guard pages used by the OS virtual memory manager are
5220 // allocated in correct sequence.
5221 // The main point of having separate instruction are extra unmodelled effects
5222 // (compared to ordinary calls) like stack pointer change.
5224 def win__chkstk : SDNode<"ARMISD::WIN__CHKSTK", SDTNone,
5225 [SDNPHasChain, SDNPSideEffect]>;
5226 let usesCustomInserter = 1, Uses = [R4], Defs = [R4, SP] in
5227 def WIN__CHKSTK : PseudoInst<(outs), (ins), NoItinerary, [(win__chkstk)]>;
5229 //===----------------------------------------------------------------------===//
5233 // __aeabi_read_tp preserves the registers r1-r3.
5234 // This is a pseudo inst so that we can get the encoding right,
5235 // complete with fixup for the aeabi_read_tp function.
5236 // TPsoft is valid for ARM mode only, in case of Thumb mode a tTPsoft pattern
5237 // is defined in "ARMInstrThumb.td".
5239 Defs = [R0, R12, LR, CPSR], Uses = [SP] in {
5240 def TPsoft : ARMPseudoInst<(outs), (ins), 4, IIC_Br,
5241 [(set R0, ARMthread_pointer)]>, Sched<[WriteBr]>;
5244 //===----------------------------------------------------------------------===//
5245 // SJLJ Exception handling intrinsics
5246 // eh_sjlj_setjmp() is an instruction sequence to store the return
5247 // address and save #0 in R0 for the non-longjmp case.
5248 // Since by its nature we may be coming from some other function to get
5249 // here, and we're using the stack frame for the containing function to
5250 // save/restore registers, we can't keep anything live in regs across
5251 // the eh_sjlj_setjmp(), else it will almost certainly have been tromped upon
5252 // when we get here from a longjmp(). We force everything out of registers
5253 // except for our own input by listing the relevant registers in Defs. By
5254 // doing so, we also cause the prologue/epilogue code to actively preserve
5255 // all of the callee-saved resgisters, which is exactly what we want.
5256 // A constant value is passed in $val, and we use the location as a scratch.
5258 // These are pseudo-instructions and are lowered to individual MC-insts, so
5259 // no encoding information is necessary.
5261 [ R0, R1, R2, R3, R4, R5, R6, R7, R8, R9, R10, R11, R12, LR, CPSR,
5262 Q0, Q1, Q2, Q3, Q4, Q5, Q6, Q7, Q8, Q9, Q10, Q11, Q12, Q13, Q14, Q15 ],
5263 hasSideEffects = 1, isBarrier = 1, usesCustomInserter = 1 in {
5264 def Int_eh_sjlj_setjmp : PseudoInst<(outs), (ins GPR:$src, GPR:$val),
5266 [(set R0, (ARMeh_sjlj_setjmp GPR:$src, GPR:$val))]>,
5267 Requires<[IsARM, HasVFP2]>;
5271 [ R0, R1, R2, R3, R4, R5, R6, R7, R8, R9, R10, R11, R12, LR, CPSR ],
5272 hasSideEffects = 1, isBarrier = 1, usesCustomInserter = 1 in {
5273 def Int_eh_sjlj_setjmp_nofp : PseudoInst<(outs), (ins GPR:$src, GPR:$val),
5275 [(set R0, (ARMeh_sjlj_setjmp GPR:$src, GPR:$val))]>,
5276 Requires<[IsARM, NoVFP]>;
5279 // FIXME: Non-IOS version(s)
5280 let isBarrier = 1, hasSideEffects = 1, isTerminator = 1,
5281 Defs = [ R7, LR, SP ] in {
5282 def Int_eh_sjlj_longjmp : PseudoInst<(outs), (ins GPR:$src, GPR:$scratch),
5284 [(ARMeh_sjlj_longjmp GPR:$src, GPR:$scratch)]>,
5288 // eh.sjlj.dispatchsetup pseudo-instruction.
5289 // This pseudo is used for both ARM and Thumb. Any differences are handled when
5290 // the pseudo is expanded (which happens before any passes that need the
5291 // instruction size).
5292 let isBarrier = 1 in
5293 def Int_eh_sjlj_dispatchsetup : PseudoInst<(outs), (ins), NoItinerary, []>;
5296 //===----------------------------------------------------------------------===//
5297 // Non-Instruction Patterns
5300 // ARMv4 indirect branch using (MOVr PC, dst)
5301 let isBranch = 1, isTerminator = 1, isBarrier = 1, isIndirectBranch = 1 in
5302 def MOVPCRX : ARMPseudoExpand<(outs), (ins GPR:$dst),
5303 4, IIC_Br, [(brind GPR:$dst)],
5304 (MOVr PC, GPR:$dst, (ops 14, zero_reg), zero_reg)>,
5305 Requires<[IsARM, NoV4T]>, Sched<[WriteBr]>;
5307 // Large immediate handling.
5309 // 32-bit immediate using two piece mod_imms or movw + movt.
5310 // This is a single pseudo instruction, the benefit is that it can be remat'd
5311 // as a single unit instead of having to handle reg inputs.
5312 // FIXME: Remove this when we can do generalized remat.
5313 let isReMaterializable = 1, isMoveImm = 1 in
5314 def MOVi32imm : PseudoInst<(outs GPR:$dst), (ins i32imm:$src), IIC_iMOVix2,
5315 [(set GPR:$dst, (arm_i32imm:$src))]>,
5318 def LDRLIT_ga_abs : PseudoInst<(outs GPR:$dst), (ins i32imm:$src), IIC_iLoad_i,
5319 [(set GPR:$dst, (ARMWrapper tglobaladdr:$src))]>,
5320 Requires<[IsARM, DontUseMovt]>;
5322 // Pseudo instruction that combines movw + movt + add pc (if PIC).
5323 // It also makes it possible to rematerialize the instructions.
5324 // FIXME: Remove this when we can do generalized remat and when machine licm
5325 // can properly the instructions.
5326 let isReMaterializable = 1 in {
5327 def MOV_ga_pcrel : PseudoInst<(outs GPR:$dst), (ins i32imm:$addr),
5329 [(set GPR:$dst, (ARMWrapperPIC tglobaladdr:$addr))]>,
5330 Requires<[IsARM, UseMovt]>;
5332 def LDRLIT_ga_pcrel : PseudoInst<(outs GPR:$dst), (ins i32imm:$addr),
5335 (ARMWrapperPIC tglobaladdr:$addr))]>,
5336 Requires<[IsARM, DontUseMovt]>;
5338 let AddedComplexity = 10 in
5339 def LDRLIT_ga_pcrel_ldr : PseudoInst<(outs GPR:$dst), (ins i32imm:$addr),
5342 (load (ARMWrapperPIC tglobaladdr:$addr)))]>,
5343 Requires<[IsARM, DontUseMovt]>;
5345 let AddedComplexity = 10 in
5346 def MOV_ga_pcrel_ldr : PseudoInst<(outs GPR:$dst), (ins i32imm:$addr),
5348 [(set GPR:$dst, (load (ARMWrapperPIC tglobaladdr:$addr)))]>,
5349 Requires<[IsARM, UseMovt]>;
5350 } // isReMaterializable
5352 // ConstantPool, GlobalAddress, and JumpTable
5353 def : ARMPat<(ARMWrapper tconstpool :$dst), (LEApcrel tconstpool :$dst)>;
5354 def : ARMPat<(ARMWrapper tglobaladdr :$dst), (MOVi32imm tglobaladdr :$dst)>,
5355 Requires<[IsARM, UseMovt]>;
5356 def : ARMPat<(ARMWrapperJT tjumptable:$dst),
5357 (LEApcrelJT tjumptable:$dst)>;
5359 // TODO: add,sub,and, 3-instr forms?
5361 // Tail calls. These patterns also apply to Thumb mode.
5362 def : Pat<(ARMtcret tcGPR:$dst), (TCRETURNri tcGPR:$dst)>;
5363 def : Pat<(ARMtcret (i32 tglobaladdr:$dst)), (TCRETURNdi texternalsym:$dst)>;
5364 def : Pat<(ARMtcret (i32 texternalsym:$dst)), (TCRETURNdi texternalsym:$dst)>;
5367 def : ARMPat<(ARMcall texternalsym:$func), (BL texternalsym:$func)>;
5368 def : ARMPat<(ARMcall_nolink texternalsym:$func),
5369 (BMOVPCB_CALL texternalsym:$func)>;
5371 // zextload i1 -> zextload i8
5372 def : ARMPat<(zextloadi1 addrmode_imm12:$addr), (LDRBi12 addrmode_imm12:$addr)>;
5373 def : ARMPat<(zextloadi1 ldst_so_reg:$addr), (LDRBrs ldst_so_reg:$addr)>;
5375 // extload -> zextload
5376 def : ARMPat<(extloadi1 addrmode_imm12:$addr), (LDRBi12 addrmode_imm12:$addr)>;
5377 def : ARMPat<(extloadi1 ldst_so_reg:$addr), (LDRBrs ldst_so_reg:$addr)>;
5378 def : ARMPat<(extloadi8 addrmode_imm12:$addr), (LDRBi12 addrmode_imm12:$addr)>;
5379 def : ARMPat<(extloadi8 ldst_so_reg:$addr), (LDRBrs ldst_so_reg:$addr)>;
5381 def : ARMPat<(extloadi16 addrmode3:$addr), (LDRH addrmode3:$addr)>;
5383 def : ARMPat<(extloadi8 addrmodepc:$addr), (PICLDRB addrmodepc:$addr)>;
5384 def : ARMPat<(extloadi16 addrmodepc:$addr), (PICLDRH addrmodepc:$addr)>;
5387 def : ARMV5TEPat<(mul (sra (shl GPR:$a, (i32 16)), (i32 16)),
5388 (sra (shl GPR:$b, (i32 16)), (i32 16))),
5389 (SMULBB GPR:$a, GPR:$b)>;
5390 def : ARMV5TEPat<(mul sext_16_node:$a, sext_16_node:$b),
5391 (SMULBB GPR:$a, GPR:$b)>;
5392 def : ARMV5TEPat<(mul (sra (shl GPR:$a, (i32 16)), (i32 16)),
5393 (sra GPR:$b, (i32 16))),
5394 (SMULBT GPR:$a, GPR:$b)>;
5395 def : ARMV5TEPat<(mul sext_16_node:$a, (sra GPR:$b, (i32 16))),
5396 (SMULBT GPR:$a, GPR:$b)>;
5397 def : ARMV5TEPat<(mul (sra GPR:$a, (i32 16)),
5398 (sra (shl GPR:$b, (i32 16)), (i32 16))),
5399 (SMULTB GPR:$a, GPR:$b)>;
5400 def : ARMV5TEPat<(mul (sra GPR:$a, (i32 16)), sext_16_node:$b),
5401 (SMULTB GPR:$a, GPR:$b)>;
5403 def : ARMV5MOPat<(add GPR:$acc,
5404 (mul (sra (shl GPR:$a, (i32 16)), (i32 16)),
5405 (sra (shl GPR:$b, (i32 16)), (i32 16)))),
5406 (SMLABB GPR:$a, GPR:$b, GPR:$acc)>;
5407 def : ARMV5MOPat<(add GPR:$acc,
5408 (mul sext_16_node:$a, sext_16_node:$b)),
5409 (SMLABB GPR:$a, GPR:$b, GPR:$acc)>;
5410 def : ARMV5MOPat<(add GPR:$acc,
5411 (mul (sra (shl GPR:$a, (i32 16)), (i32 16)),
5412 (sra GPR:$b, (i32 16)))),
5413 (SMLABT GPR:$a, GPR:$b, GPR:$acc)>;
5414 def : ARMV5MOPat<(add GPR:$acc,
5415 (mul sext_16_node:$a, (sra GPR:$b, (i32 16)))),
5416 (SMLABT GPR:$a, GPR:$b, GPR:$acc)>;
5417 def : ARMV5MOPat<(add GPR:$acc,
5418 (mul (sra GPR:$a, (i32 16)),
5419 (sra (shl GPR:$b, (i32 16)), (i32 16)))),
5420 (SMLATB GPR:$a, GPR:$b, GPR:$acc)>;
5421 def : ARMV5MOPat<(add GPR:$acc,
5422 (mul (sra GPR:$a, (i32 16)), sext_16_node:$b)),
5423 (SMLATB GPR:$a, GPR:$b, GPR:$acc)>;
5426 // Pre-v7 uses MCR for synchronization barriers.
5427 def : ARMPat<(ARMMemBarrierMCR GPR:$zero), (MCR 15, 0, GPR:$zero, 7, 10, 5)>,
5428 Requires<[IsARM, HasV6]>;
5430 // SXT/UXT with no rotate
5431 let AddedComplexity = 16 in {
5432 def : ARMV6Pat<(and GPR:$Src, 0x000000FF), (UXTB GPR:$Src, 0)>;
5433 def : ARMV6Pat<(and GPR:$Src, 0x0000FFFF), (UXTH GPR:$Src, 0)>;
5434 def : ARMV6Pat<(and GPR:$Src, 0x00FF00FF), (UXTB16 GPR:$Src, 0)>;
5435 def : ARMV6Pat<(add GPR:$Rn, (and GPR:$Rm, 0x00FF)),
5436 (UXTAB GPR:$Rn, GPR:$Rm, 0)>;
5437 def : ARMV6Pat<(add GPR:$Rn, (and GPR:$Rm, 0xFFFF)),
5438 (UXTAH GPR:$Rn, GPR:$Rm, 0)>;
5441 def : ARMV6Pat<(sext_inreg GPR:$Src, i8), (SXTB GPR:$Src, 0)>;
5442 def : ARMV6Pat<(sext_inreg GPR:$Src, i16), (SXTH GPR:$Src, 0)>;
5444 def : ARMV6Pat<(add GPR:$Rn, (sext_inreg GPRnopc:$Rm, i8)),
5445 (SXTAB GPR:$Rn, GPRnopc:$Rm, 0)>;
5446 def : ARMV6Pat<(add GPR:$Rn, (sext_inreg GPRnopc:$Rm, i16)),
5447 (SXTAH GPR:$Rn, GPRnopc:$Rm, 0)>;
5449 // Atomic load/store patterns
5450 def : ARMPat<(atomic_load_8 ldst_so_reg:$src),
5451 (LDRBrs ldst_so_reg:$src)>;
5452 def : ARMPat<(atomic_load_8 addrmode_imm12:$src),
5453 (LDRBi12 addrmode_imm12:$src)>;
5454 def : ARMPat<(atomic_load_16 addrmode3:$src),
5455 (LDRH addrmode3:$src)>;
5456 def : ARMPat<(atomic_load_32 ldst_so_reg:$src),
5457 (LDRrs ldst_so_reg:$src)>;
5458 def : ARMPat<(atomic_load_32 addrmode_imm12:$src),
5459 (LDRi12 addrmode_imm12:$src)>;
5460 def : ARMPat<(atomic_store_8 ldst_so_reg:$ptr, GPR:$val),
5461 (STRBrs GPR:$val, ldst_so_reg:$ptr)>;
5462 def : ARMPat<(atomic_store_8 addrmode_imm12:$ptr, GPR:$val),
5463 (STRBi12 GPR:$val, addrmode_imm12:$ptr)>;
5464 def : ARMPat<(atomic_store_16 addrmode3:$ptr, GPR:$val),
5465 (STRH GPR:$val, addrmode3:$ptr)>;
5466 def : ARMPat<(atomic_store_32 ldst_so_reg:$ptr, GPR:$val),
5467 (STRrs GPR:$val, ldst_so_reg:$ptr)>;
5468 def : ARMPat<(atomic_store_32 addrmode_imm12:$ptr, GPR:$val),
5469 (STRi12 GPR:$val, addrmode_imm12:$ptr)>;
5472 //===----------------------------------------------------------------------===//
5476 include "ARMInstrThumb.td"
5478 //===----------------------------------------------------------------------===//
5482 include "ARMInstrThumb2.td"
5484 //===----------------------------------------------------------------------===//
5485 // Floating Point Support
5488 include "ARMInstrVFP.td"
5490 //===----------------------------------------------------------------------===//
5491 // Advanced SIMD (NEON) Support
5494 include "ARMInstrNEON.td"
5496 //===----------------------------------------------------------------------===//
5497 // Assembler aliases
5501 def : InstAlias<"dmb", (DMB 0xf)>, Requires<[IsARM, HasDB]>;
5502 def : InstAlias<"dsb", (DSB 0xf)>, Requires<[IsARM, HasDB]>;
5503 def : InstAlias<"isb", (ISB 0xf)>, Requires<[IsARM, HasDB]>;
5505 // System instructions
5506 def : MnemonicAlias<"swi", "svc">;
5508 // Load / Store Multiple
5509 def : MnemonicAlias<"ldmfd", "ldm">;
5510 def : MnemonicAlias<"ldmia", "ldm">;
5511 def : MnemonicAlias<"ldmea", "ldmdb">;
5512 def : MnemonicAlias<"stmfd", "stmdb">;
5513 def : MnemonicAlias<"stmia", "stm">;
5514 def : MnemonicAlias<"stmea", "stm">;
5516 // PKHBT/PKHTB with default shift amount. PKHTB is equivalent to PKHBT when the
5517 // shift amount is zero (i.e., unspecified).
5518 def : InstAlias<"pkhbt${p} $Rd, $Rn, $Rm",
5519 (PKHBT GPRnopc:$Rd, GPRnopc:$Rn, GPRnopc:$Rm, 0, pred:$p)>,
5520 Requires<[IsARM, HasV6]>;
5521 def : InstAlias<"pkhtb${p} $Rd, $Rn, $Rm",
5522 (PKHBT GPRnopc:$Rd, GPRnopc:$Rn, GPRnopc:$Rm, 0, pred:$p)>,
5523 Requires<[IsARM, HasV6]>;
5525 // PUSH/POP aliases for STM/LDM
5526 def : ARMInstAlias<"push${p} $regs", (STMDB_UPD SP, pred:$p, reglist:$regs)>;
5527 def : ARMInstAlias<"pop${p} $regs", (LDMIA_UPD SP, pred:$p, reglist:$regs)>;
5529 // SSAT/USAT optional shift operand.
5530 def : ARMInstAlias<"ssat${p} $Rd, $sat_imm, $Rn",
5531 (SSAT GPRnopc:$Rd, imm1_32:$sat_imm, GPRnopc:$Rn, 0, pred:$p)>;
5532 def : ARMInstAlias<"usat${p} $Rd, $sat_imm, $Rn",
5533 (USAT GPRnopc:$Rd, imm0_31:$sat_imm, GPRnopc:$Rn, 0, pred:$p)>;
5536 // Extend instruction optional rotate operand.
5537 def : ARMInstAlias<"sxtab${p} $Rd, $Rn, $Rm",
5538 (SXTAB GPRnopc:$Rd, GPR:$Rn, GPRnopc:$Rm, 0, pred:$p)>;
5539 def : ARMInstAlias<"sxtah${p} $Rd, $Rn, $Rm",
5540 (SXTAH GPRnopc:$Rd, GPR:$Rn, GPRnopc:$Rm, 0, pred:$p)>;
5541 def : ARMInstAlias<"sxtab16${p} $Rd, $Rn, $Rm",
5542 (SXTAB16 GPRnopc:$Rd, GPR:$Rn, GPRnopc:$Rm, 0, pred:$p)>;
5543 def : ARMInstAlias<"sxtb${p} $Rd, $Rm",
5544 (SXTB GPRnopc:$Rd, GPRnopc:$Rm, 0, pred:$p)>;
5545 def : ARMInstAlias<"sxtb16${p} $Rd, $Rm",
5546 (SXTB16 GPRnopc:$Rd, GPRnopc:$Rm, 0, pred:$p)>;
5547 def : ARMInstAlias<"sxth${p} $Rd, $Rm",
5548 (SXTH GPRnopc:$Rd, GPRnopc:$Rm, 0, pred:$p)>;
5550 def : ARMInstAlias<"uxtab${p} $Rd, $Rn, $Rm",
5551 (UXTAB GPRnopc:$Rd, GPR:$Rn, GPRnopc:$Rm, 0, pred:$p)>;
5552 def : ARMInstAlias<"uxtah${p} $Rd, $Rn, $Rm",
5553 (UXTAH GPRnopc:$Rd, GPR:$Rn, GPRnopc:$Rm, 0, pred:$p)>;
5554 def : ARMInstAlias<"uxtab16${p} $Rd, $Rn, $Rm",
5555 (UXTAB16 GPRnopc:$Rd, GPR:$Rn, GPRnopc:$Rm, 0, pred:$p)>;
5556 def : ARMInstAlias<"uxtb${p} $Rd, $Rm",
5557 (UXTB GPRnopc:$Rd, GPRnopc:$Rm, 0, pred:$p)>;
5558 def : ARMInstAlias<"uxtb16${p} $Rd, $Rm",
5559 (UXTB16 GPRnopc:$Rd, GPRnopc:$Rm, 0, pred:$p)>;
5560 def : ARMInstAlias<"uxth${p} $Rd, $Rm",
5561 (UXTH GPRnopc:$Rd, GPRnopc:$Rm, 0, pred:$p)>;
5565 def : MnemonicAlias<"rfefa", "rfeda">;
5566 def : MnemonicAlias<"rfeea", "rfedb">;
5567 def : MnemonicAlias<"rfefd", "rfeia">;
5568 def : MnemonicAlias<"rfeed", "rfeib">;
5569 def : MnemonicAlias<"rfe", "rfeia">;
5572 def : MnemonicAlias<"srsfa", "srsib">;
5573 def : MnemonicAlias<"srsea", "srsia">;
5574 def : MnemonicAlias<"srsfd", "srsdb">;
5575 def : MnemonicAlias<"srsed", "srsda">;
5576 def : MnemonicAlias<"srs", "srsia">;
5579 def : MnemonicAlias<"qsubaddx", "qsax">;
5581 def : MnemonicAlias<"saddsubx", "sasx">;
5582 // SHASX == SHADDSUBX
5583 def : MnemonicAlias<"shaddsubx", "shasx">;
5584 // SHSAX == SHSUBADDX
5585 def : MnemonicAlias<"shsubaddx", "shsax">;
5587 def : MnemonicAlias<"ssubaddx", "ssax">;
5589 def : MnemonicAlias<"uaddsubx", "uasx">;
5590 // UHASX == UHADDSUBX
5591 def : MnemonicAlias<"uhaddsubx", "uhasx">;
5592 // UHSAX == UHSUBADDX
5593 def : MnemonicAlias<"uhsubaddx", "uhsax">;
5594 // UQASX == UQADDSUBX
5595 def : MnemonicAlias<"uqaddsubx", "uqasx">;
5596 // UQSAX == UQSUBADDX
5597 def : MnemonicAlias<"uqsubaddx", "uqsax">;
5599 def : MnemonicAlias<"usubaddx", "usax">;
5601 // "mov Rd, mod_imm_not" can be handled via "mvn" in assembly, just like
5603 def : ARMInstAlias<"mov${s}${p} $Rd, $imm",
5604 (MVNi rGPR:$Rd, mod_imm_not:$imm, pred:$p, cc_out:$s)>;
5605 def : ARMInstAlias<"mvn${s}${p} $Rd, $imm",
5606 (MOVi rGPR:$Rd, mod_imm_not:$imm, pred:$p, cc_out:$s)>;
5607 // Same for AND <--> BIC
5608 def : ARMInstAlias<"bic${s}${p} $Rd, $Rn, $imm",
5609 (ANDri rGPR:$Rd, rGPR:$Rn, mod_imm_not:$imm,
5610 pred:$p, cc_out:$s)>;
5611 def : ARMInstAlias<"bic${s}${p} $Rdn, $imm",
5612 (ANDri rGPR:$Rdn, rGPR:$Rdn, mod_imm_not:$imm,
5613 pred:$p, cc_out:$s)>;
5614 def : ARMInstAlias<"and${s}${p} $Rd, $Rn, $imm",
5615 (BICri rGPR:$Rd, rGPR:$Rn, mod_imm_not:$imm,
5616 pred:$p, cc_out:$s)>;
5617 def : ARMInstAlias<"and${s}${p} $Rdn, $imm",
5618 (BICri rGPR:$Rdn, rGPR:$Rdn, mod_imm_not:$imm,
5619 pred:$p, cc_out:$s)>;
5621 // Likewise, "add Rd, mod_imm_neg" -> sub
5622 def : ARMInstAlias<"add${s}${p} $Rd, $Rn, $imm",
5623 (SUBri GPR:$Rd, GPR:$Rn, mod_imm_neg:$imm, pred:$p, cc_out:$s)>;
5624 def : ARMInstAlias<"add${s}${p} $Rd, $imm",
5625 (SUBri GPR:$Rd, GPR:$Rd, mod_imm_neg:$imm, pred:$p, cc_out:$s)>;
5626 // Same for CMP <--> CMN via mod_imm_neg
5627 def : ARMInstAlias<"cmp${p} $Rd, $imm",
5628 (CMNri rGPR:$Rd, mod_imm_neg:$imm, pred:$p)>;
5629 def : ARMInstAlias<"cmn${p} $Rd, $imm",
5630 (CMPri rGPR:$Rd, mod_imm_neg:$imm, pred:$p)>;
5632 // The shifter forms of the MOV instruction are aliased to the ASR, LSL,
5633 // LSR, ROR, and RRX instructions.
5634 // FIXME: We need C++ parser hooks to map the alias to the MOV
5635 // encoding. It seems we should be able to do that sort of thing
5636 // in tblgen, but it could get ugly.
5637 let TwoOperandAliasConstraint = "$Rm = $Rd" in {
5638 def ASRi : ARMAsmPseudo<"asr${s}${p} $Rd, $Rm, $imm",
5639 (ins GPR:$Rd, GPR:$Rm, imm0_32:$imm, pred:$p,
5641 def LSRi : ARMAsmPseudo<"lsr${s}${p} $Rd, $Rm, $imm",
5642 (ins GPR:$Rd, GPR:$Rm, imm0_32:$imm, pred:$p,
5644 def LSLi : ARMAsmPseudo<"lsl${s}${p} $Rd, $Rm, $imm",
5645 (ins GPR:$Rd, GPR:$Rm, imm0_31:$imm, pred:$p,
5647 def RORi : ARMAsmPseudo<"ror${s}${p} $Rd, $Rm, $imm",
5648 (ins GPR:$Rd, GPR:$Rm, imm0_31:$imm, pred:$p,
5651 def RRXi : ARMAsmPseudo<"rrx${s}${p} $Rd, $Rm",
5652 (ins GPR:$Rd, GPR:$Rm, pred:$p, cc_out:$s)>;
5653 let TwoOperandAliasConstraint = "$Rn = $Rd" in {
5654 def ASRr : ARMAsmPseudo<"asr${s}${p} $Rd, $Rn, $Rm",
5655 (ins GPRnopc:$Rd, GPRnopc:$Rn, GPRnopc:$Rm, pred:$p,
5657 def LSRr : ARMAsmPseudo<"lsr${s}${p} $Rd, $Rn, $Rm",
5658 (ins GPRnopc:$Rd, GPRnopc:$Rn, GPRnopc:$Rm, pred:$p,
5660 def LSLr : ARMAsmPseudo<"lsl${s}${p} $Rd, $Rn, $Rm",
5661 (ins GPRnopc:$Rd, GPRnopc:$Rn, GPRnopc:$Rm, pred:$p,
5663 def RORr : ARMAsmPseudo<"ror${s}${p} $Rd, $Rn, $Rm",
5664 (ins GPRnopc:$Rd, GPRnopc:$Rn, GPRnopc:$Rm, pred:$p,
5668 // "neg" is and alias for "rsb rd, rn, #0"
5669 def : ARMInstAlias<"neg${s}${p} $Rd, $Rm",
5670 (RSBri GPR:$Rd, GPR:$Rm, 0, pred:$p, cc_out:$s)>;
5672 // Pre-v6, 'mov r0, r0' was used as a NOP encoding.
5673 def : InstAlias<"nop${p}", (MOVr R0, R0, pred:$p, zero_reg)>,
5674 Requires<[IsARM, NoV6]>;
5676 // MUL/UMLAL/SMLAL/UMULL/SMULL are available on all arches, but
5677 // the instruction definitions need difference constraints pre-v6.
5678 // Use these aliases for the assembly parsing on pre-v6.
5679 def : InstAlias<"mul${s}${p} $Rd, $Rn, $Rm",
5680 (MUL GPRnopc:$Rd, GPRnopc:$Rn, GPRnopc:$Rm, pred:$p, cc_out:$s)>,
5681 Requires<[IsARM, NoV6]>;
5682 def : InstAlias<"mla${s}${p} $Rd, $Rn, $Rm, $Ra",
5683 (MLA GPRnopc:$Rd, GPRnopc:$Rn, GPRnopc:$Rm, GPRnopc:$Ra,
5684 pred:$p, cc_out:$s)>,
5685 Requires<[IsARM, NoV6]>;
5686 def : InstAlias<"smlal${s}${p} $RdLo, $RdHi, $Rn, $Rm",
5687 (SMLAL GPR:$RdLo, GPR:$RdHi, GPR:$Rn, GPR:$Rm, pred:$p, cc_out:$s)>,
5688 Requires<[IsARM, NoV6]>;
5689 def : InstAlias<"umlal${s}${p} $RdLo, $RdHi, $Rn, $Rm",
5690 (UMLAL GPR:$RdLo, GPR:$RdHi, GPR:$Rn, GPR:$Rm, pred:$p, cc_out:$s)>,
5691 Requires<[IsARM, NoV6]>;
5692 def : InstAlias<"smull${s}${p} $RdLo, $RdHi, $Rn, $Rm",
5693 (SMULL GPR:$RdLo, GPR:$RdHi, GPR:$Rn, GPR:$Rm, pred:$p, cc_out:$s)>,
5694 Requires<[IsARM, NoV6]>;
5695 def : InstAlias<"umull${s}${p} $RdLo, $RdHi, $Rn, $Rm",
5696 (UMULL GPR:$RdLo, GPR:$RdHi, GPR:$Rn, GPR:$Rm, pred:$p, cc_out:$s)>,
5697 Requires<[IsARM, NoV6]>;
5699 // 'it' blocks in ARM mode just validate the predicates. The IT itself
5701 def ITasm : ARMAsmPseudo<"it$mask $cc", (ins it_pred:$cc, it_mask:$mask)>,
5702 ComplexDeprecationPredicate<"IT">;
5704 let mayLoad = 1, mayStore =1, hasSideEffects = 1 in
5705 def SPACE : PseudoInst<(outs GPR:$Rd), (ins i32imm:$size, GPR:$Rn),
5707 [(set GPR:$Rd, (int_arm_space imm:$size, GPR:$Rn))]>;