1 //===- ARMInstrInfo.td - Target Description for ARM Target -*- tablegen -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file describes the ARM instructions in TableGen format.
12 //===----------------------------------------------------------------------===//
14 //===----------------------------------------------------------------------===//
15 // ARM specific DAG Nodes.
19 def SDT_ARMCallSeqStart : SDCallSeqStart<[ SDTCisVT<0, i32> ]>;
20 def SDT_ARMCallSeqEnd : SDCallSeqEnd<[ SDTCisVT<0, i32>, SDTCisVT<1, i32> ]>;
22 def SDT_ARMSaveCallPC : SDTypeProfile<0, 1, []>;
24 def SDT_ARMcall : SDTypeProfile<0, -1, [SDTCisPtrTy<0>]>;
26 def SDT_ARMCMov : SDTypeProfile<1, 3,
27 [SDTCisSameAs<0, 1>, SDTCisSameAs<0, 2>,
30 def SDT_ARMBrcond : SDTypeProfile<0, 2,
31 [SDTCisVT<0, OtherVT>, SDTCisVT<1, i32>]>;
33 def SDT_ARMBrJT : SDTypeProfile<0, 3,
34 [SDTCisPtrTy<0>, SDTCisVT<1, i32>,
37 def SDT_ARMBr2JT : SDTypeProfile<0, 4,
38 [SDTCisPtrTy<0>, SDTCisVT<1, i32>,
39 SDTCisVT<2, i32>, SDTCisVT<3, i32>]>;
41 def SDT_ARMBCC_i64 : SDTypeProfile<0, 6,
43 SDTCisVT<1, i32>, SDTCisVT<2, i32>,
44 SDTCisVT<3, i32>, SDTCisVT<4, i32>,
45 SDTCisVT<5, OtherVT>]>;
47 def SDT_ARMAnd : SDTypeProfile<1, 2,
48 [SDTCisVT<0, i32>, SDTCisVT<1, i32>,
51 def SDT_ARMCmp : SDTypeProfile<0, 2, [SDTCisSameAs<0, 1>]>;
53 def SDT_ARMPICAdd : SDTypeProfile<1, 2, [SDTCisSameAs<0, 1>,
54 SDTCisPtrTy<1>, SDTCisVT<2, i32>]>;
56 def SDT_ARMThreadPointer : SDTypeProfile<1, 0, [SDTCisPtrTy<0>]>;
57 def SDT_ARMEH_SJLJ_Setjmp : SDTypeProfile<1, 2, [SDTCisInt<0>, SDTCisPtrTy<1>,
59 def SDT_ARMEH_SJLJ_Longjmp: SDTypeProfile<0, 2, [SDTCisPtrTy<0>, SDTCisInt<1>]>;
61 def SDT_ARMEH_SJLJ_DispatchSetup: SDTypeProfile<0, 1, [SDTCisPtrTy<0>]>;
63 def SDT_ARMMEMBARRIER : SDTypeProfile<0, 1, [SDTCisInt<0>]>;
65 def SDT_ARMTCRET : SDTypeProfile<0, 1, [SDTCisPtrTy<0>]>;
67 def SDT_ARMBFI : SDTypeProfile<1, 3, [SDTCisVT<0, i32>, SDTCisVT<1, i32>,
68 SDTCisVT<2, i32>, SDTCisVT<3, i32>]>;
71 def ARMWrapper : SDNode<"ARMISD::Wrapper", SDTIntUnaryOp>;
72 def ARMWrapperJT : SDNode<"ARMISD::WrapperJT", SDTIntBinOp>;
74 def ARMcallseq_start : SDNode<"ISD::CALLSEQ_START", SDT_ARMCallSeqStart,
75 [SDNPHasChain, SDNPOutFlag]>;
76 def ARMcallseq_end : SDNode<"ISD::CALLSEQ_END", SDT_ARMCallSeqEnd,
77 [SDNPHasChain, SDNPOptInFlag, SDNPOutFlag]>;
79 def ARMcall : SDNode<"ARMISD::CALL", SDT_ARMcall,
80 [SDNPHasChain, SDNPOptInFlag, SDNPOutFlag,
82 def ARMcall_pred : SDNode<"ARMISD::CALL_PRED", SDT_ARMcall,
83 [SDNPHasChain, SDNPOptInFlag, SDNPOutFlag,
85 def ARMcall_nolink : SDNode<"ARMISD::CALL_NOLINK", SDT_ARMcall,
86 [SDNPHasChain, SDNPOptInFlag, SDNPOutFlag,
89 def ARMretflag : SDNode<"ARMISD::RET_FLAG", SDTNone,
90 [SDNPHasChain, SDNPOptInFlag]>;
92 def ARMcmov : SDNode<"ARMISD::CMOV", SDT_ARMCMov,
94 def ARMcneg : SDNode<"ARMISD::CNEG", SDT_ARMCMov,
97 def ARMbrcond : SDNode<"ARMISD::BRCOND", SDT_ARMBrcond,
98 [SDNPHasChain, SDNPInFlag, SDNPOutFlag]>;
100 def ARMbrjt : SDNode<"ARMISD::BR_JT", SDT_ARMBrJT,
102 def ARMbr2jt : SDNode<"ARMISD::BR2_JT", SDT_ARMBr2JT,
105 def ARMBcci64 : SDNode<"ARMISD::BCC_i64", SDT_ARMBCC_i64,
108 def ARMcmp : SDNode<"ARMISD::CMP", SDT_ARMCmp,
111 def ARMcmpZ : SDNode<"ARMISD::CMPZ", SDT_ARMCmp,
112 [SDNPOutFlag, SDNPCommutative]>;
114 def ARMpic_add : SDNode<"ARMISD::PIC_ADD", SDT_ARMPICAdd>;
116 def ARMsrl_flag : SDNode<"ARMISD::SRL_FLAG", SDTIntUnaryOp, [SDNPOutFlag]>;
117 def ARMsra_flag : SDNode<"ARMISD::SRA_FLAG", SDTIntUnaryOp, [SDNPOutFlag]>;
118 def ARMrrx : SDNode<"ARMISD::RRX" , SDTIntUnaryOp, [SDNPInFlag ]>;
120 def ARMthread_pointer: SDNode<"ARMISD::THREAD_POINTER", SDT_ARMThreadPointer>;
121 def ARMeh_sjlj_setjmp: SDNode<"ARMISD::EH_SJLJ_SETJMP",
122 SDT_ARMEH_SJLJ_Setjmp, [SDNPHasChain]>;
123 def ARMeh_sjlj_longjmp: SDNode<"ARMISD::EH_SJLJ_LONGJMP",
124 SDT_ARMEH_SJLJ_Longjmp, [SDNPHasChain]>;
125 def ARMeh_sjlj_dispatchsetup: SDNode<"ARMISD::EH_SJLJ_DISPATCHSETUP",
126 SDT_ARMEH_SJLJ_DispatchSetup, [SDNPHasChain]>;
129 def ARMMemBarrier : SDNode<"ARMISD::MEMBARRIER", SDT_ARMMEMBARRIER,
131 def ARMMemBarrierMCR : SDNode<"ARMISD::MEMBARRIER_MCR", SDT_ARMMEMBARRIER,
133 def ARMPreload : SDNode<"ARMISD::PRELOAD", SDTPrefetch,
134 [SDNPHasChain, SDNPMayLoad, SDNPMayStore]>;
136 def ARMrbit : SDNode<"ARMISD::RBIT", SDTIntUnaryOp>;
138 def ARMtcret : SDNode<"ARMISD::TC_RETURN", SDT_ARMTCRET,
139 [SDNPHasChain, SDNPOptInFlag, SDNPVariadic]>;
142 def ARMbfi : SDNode<"ARMISD::BFI", SDT_ARMBFI>;
144 //===----------------------------------------------------------------------===//
145 // ARM Instruction Predicate Definitions.
147 def HasV4T : Predicate<"Subtarget->hasV4TOps()">, AssemblerPredicate;
148 def NoV4T : Predicate<"!Subtarget->hasV4TOps()">;
149 def HasV5T : Predicate<"Subtarget->hasV5TOps()">;
150 def HasV5TE : Predicate<"Subtarget->hasV5TEOps()">, AssemblerPredicate;
151 def HasV6 : Predicate<"Subtarget->hasV6Ops()">, AssemblerPredicate;
152 def HasV6T2 : Predicate<"Subtarget->hasV6T2Ops()">, AssemblerPredicate;
153 def NoV6T2 : Predicate<"!Subtarget->hasV6T2Ops()">;
154 def HasV7 : Predicate<"Subtarget->hasV7Ops()">, AssemblerPredicate;
155 def NoVFP : Predicate<"!Subtarget->hasVFP2()">;
156 def HasVFP2 : Predicate<"Subtarget->hasVFP2()">, AssemblerPredicate;
157 def HasVFP3 : Predicate<"Subtarget->hasVFP3()">, AssemblerPredicate;
158 def HasNEON : Predicate<"Subtarget->hasNEON()">, AssemblerPredicate;
159 def HasDivide : Predicate<"Subtarget->hasDivide()">, AssemblerPredicate;
160 def HasT2ExtractPack : Predicate<"Subtarget->hasT2ExtractPack()">,
162 def HasDB : Predicate<"Subtarget->hasDataBarrier()">,
164 def HasMP : Predicate<"Subtarget->hasMPExtension()">,
166 def UseNEONForFP : Predicate<"Subtarget->useNEONForSinglePrecisionFP()">;
167 def DontUseNEONForFP : Predicate<"!Subtarget->useNEONForSinglePrecisionFP()">;
168 def IsThumb : Predicate<"Subtarget->isThumb()">, AssemblerPredicate;
169 def IsThumb1Only : Predicate<"Subtarget->isThumb1Only()">;
170 def IsThumb2 : Predicate<"Subtarget->isThumb2()">, AssemblerPredicate;
171 def IsARM : Predicate<"!Subtarget->isThumb()">, AssemblerPredicate;
172 def IsDarwin : Predicate<"Subtarget->isTargetDarwin()">;
173 def IsNotDarwin : Predicate<"!Subtarget->isTargetDarwin()">;
175 // FIXME: Eventually this will be just "hasV6T2Ops".
176 def UseMovt : Predicate<"Subtarget->useMovt()">;
177 def DontUseMovt : Predicate<"!Subtarget->useMovt()">;
178 def UseVMLx : Predicate<"Subtarget->useVMLx()">;
180 //===----------------------------------------------------------------------===//
181 // ARM Flag Definitions.
183 class RegConstraint<string C> {
184 string Constraints = C;
187 //===----------------------------------------------------------------------===//
188 // ARM specific transformation functions and pattern fragments.
191 // so_imm_neg_XFORM - Return a so_imm value packed into the format described for
192 // so_imm_neg def below.
193 def so_imm_neg_XFORM : SDNodeXForm<imm, [{
194 return CurDAG->getTargetConstant(-(int)N->getZExtValue(), MVT::i32);
197 // so_imm_not_XFORM - Return a so_imm value packed into the format described for
198 // so_imm_not def below.
199 def so_imm_not_XFORM : SDNodeXForm<imm, [{
200 return CurDAG->getTargetConstant(~(int)N->getZExtValue(), MVT::i32);
203 /// imm1_15 predicate - True if the 32-bit immediate is in the range [1,15].
204 def imm1_15 : PatLeaf<(i32 imm), [{
205 return (int32_t)N->getZExtValue() >= 1 && (int32_t)N->getZExtValue() < 16;
208 /// imm16_31 predicate - True if the 32-bit immediate is in the range [16,31].
209 def imm16_31 : PatLeaf<(i32 imm), [{
210 return (int32_t)N->getZExtValue() >= 16 && (int32_t)N->getZExtValue() < 32;
215 return ARM_AM::getSOImmVal(-(uint32_t)N->getZExtValue()) != -1;
216 }], so_imm_neg_XFORM>;
220 return ARM_AM::getSOImmVal(~(uint32_t)N->getZExtValue()) != -1;
221 }], so_imm_not_XFORM>;
223 // sext_16_node predicate - True if the SDNode is sign-extended 16 or more bits.
224 def sext_16_node : PatLeaf<(i32 GPR:$a), [{
225 return CurDAG->ComputeNumSignBits(SDValue(N,0)) >= 17;
228 /// bf_inv_mask_imm predicate - An AND mask to clear an arbitrary width bitfield
230 def bf_inv_mask_imm : Operand<i32>,
232 return ARM::isBitFieldInvertedMask(N->getZExtValue());
234 let EncoderMethod = "getBitfieldInvertedMaskOpValue";
235 let PrintMethod = "printBitfieldInvMaskImmOperand";
238 /// Split a 32-bit immediate into two 16 bit parts.
239 def hi16 : SDNodeXForm<imm, [{
240 return CurDAG->getTargetConstant((uint32_t)N->getZExtValue() >> 16, MVT::i32);
243 def lo16AllZero : PatLeaf<(i32 imm), [{
244 // Returns true if all low 16-bits are 0.
245 return (((uint32_t)N->getZExtValue()) & 0xFFFFUL) == 0;
248 /// imm0_65535 predicate - True if the 32-bit immediate is in the range
250 def imm0_65535 : PatLeaf<(i32 imm), [{
251 return (uint32_t)N->getZExtValue() < 65536;
254 class BinOpFrag<dag res> : PatFrag<(ops node:$LHS, node:$RHS), res>;
255 class UnOpFrag <dag res> : PatFrag<(ops node:$Src), res>;
257 /// adde and sube predicates - True based on whether the carry flag output
258 /// will be needed or not.
259 def adde_dead_carry :
260 PatFrag<(ops node:$LHS, node:$RHS), (adde node:$LHS, node:$RHS),
261 [{return !N->hasAnyUseOfValue(1);}]>;
262 def sube_dead_carry :
263 PatFrag<(ops node:$LHS, node:$RHS), (sube node:$LHS, node:$RHS),
264 [{return !N->hasAnyUseOfValue(1);}]>;
265 def adde_live_carry :
266 PatFrag<(ops node:$LHS, node:$RHS), (adde node:$LHS, node:$RHS),
267 [{return N->hasAnyUseOfValue(1);}]>;
268 def sube_live_carry :
269 PatFrag<(ops node:$LHS, node:$RHS), (sube node:$LHS, node:$RHS),
270 [{return N->hasAnyUseOfValue(1);}]>;
272 //===----------------------------------------------------------------------===//
273 // Operand Definitions.
277 def brtarget : Operand<OtherVT> {
278 let EncoderMethod = "getBranchTargetOpValue";
282 def bltarget : Operand<i32> {
283 // Encoded the same as branch targets.
284 let EncoderMethod = "getBranchTargetOpValue";
287 // A list of registers separated by comma. Used by load/store multiple.
288 def RegListAsmOperand : AsmOperandClass {
289 let Name = "RegList";
290 let SuperClasses = [];
293 def reglist : Operand<i32> {
294 let EncoderMethod = "getRegisterListOpValue";
295 let ParserMatchClass = RegListAsmOperand;
296 let PrintMethod = "printRegisterList";
299 // An operand for the CONSTPOOL_ENTRY pseudo-instruction.
300 def cpinst_operand : Operand<i32> {
301 let PrintMethod = "printCPInstOperand";
304 def jtblock_operand : Operand<i32> {
305 let PrintMethod = "printJTBlockOperand";
307 def jt2block_operand : Operand<i32> {
308 let PrintMethod = "printJT2BlockOperand";
312 def pclabel : Operand<i32> {
313 let PrintMethod = "printPCLabel";
316 def neon_vcvt_imm32 : Operand<i32> {
317 let EncoderMethod = "getNEONVcvtImm32OpValue";
320 // rot_imm: An integer that encodes a rotate amount. Must be 8, 16, or 24.
321 def rot_imm : Operand<i32>, PatLeaf<(i32 imm), [{
322 int32_t v = (int32_t)N->getZExtValue();
323 return v == 8 || v == 16 || v == 24; }]> {
324 let EncoderMethod = "getRotImmOpValue";
327 // shift_imm: An integer that encodes a shift amount and the type of shift
328 // (currently either asr or lsl) using the same encoding used for the
329 // immediates in so_reg operands.
330 def shift_imm : Operand<i32> {
331 let PrintMethod = "printShiftImmOperand";
334 // shifter_operand operands: so_reg and so_imm.
335 def so_reg : Operand<i32>, // reg reg imm
336 ComplexPattern<i32, 3, "SelectShifterOperandReg",
337 [shl,srl,sra,rotr]> {
338 let EncoderMethod = "getSORegOpValue";
339 let PrintMethod = "printSORegOperand";
340 let MIOperandInfo = (ops GPR, GPR, i32imm);
342 def shift_so_reg : Operand<i32>, // reg reg imm
343 ComplexPattern<i32, 3, "SelectShiftShifterOperandReg",
344 [shl,srl,sra,rotr]> {
345 let EncoderMethod = "getSORegOpValue";
346 let PrintMethod = "printSORegOperand";
347 let MIOperandInfo = (ops GPR, GPR, i32imm);
350 // so_imm - Match a 32-bit shifter_operand immediate operand, which is an
351 // 8-bit immediate rotated by an arbitrary number of bits. so_imm values are
352 // represented in the imm field in the same 12-bit form that they are encoded
353 // into so_imm instructions: the 8-bit immediate is the least significant bits
354 // [bits 0-7], the 4-bit shift amount is the next 4 bits [bits 8-11].
355 def so_imm : Operand<i32>, PatLeaf<(imm), [{ return Pred_so_imm(N); }]> {
356 let EncoderMethod = "getSOImmOpValue";
357 let PrintMethod = "printSOImmOperand";
360 // Break so_imm's up into two pieces. This handles immediates with up to 16
361 // bits set in them. This uses so_imm2part to match and so_imm2part_[12] to
362 // get the first/second pieces.
363 def so_imm2part : PatLeaf<(imm), [{
364 return ARM_AM::isSOImmTwoPartVal((unsigned)N->getZExtValue());
367 /// arm_i32imm - True for +V6T2, or true only if so_imm2part is true.
369 def arm_i32imm : PatLeaf<(imm), [{
370 if (Subtarget->hasV6T2Ops())
372 return ARM_AM::isSOImmTwoPartVal((unsigned)N->getZExtValue());
375 def so_imm2part_1 : SDNodeXForm<imm, [{
376 unsigned V = ARM_AM::getSOImmTwoPartFirst((unsigned)N->getZExtValue());
377 return CurDAG->getTargetConstant(V, MVT::i32);
380 def so_imm2part_2 : SDNodeXForm<imm, [{
381 unsigned V = ARM_AM::getSOImmTwoPartSecond((unsigned)N->getZExtValue());
382 return CurDAG->getTargetConstant(V, MVT::i32);
385 def so_neg_imm2part : Operand<i32>, PatLeaf<(imm), [{
386 return ARM_AM::isSOImmTwoPartVal(-(int)N->getZExtValue());
388 let PrintMethod = "printSOImm2PartOperand";
391 def so_neg_imm2part_1 : SDNodeXForm<imm, [{
392 unsigned V = ARM_AM::getSOImmTwoPartFirst(-(int)N->getZExtValue());
393 return CurDAG->getTargetConstant(V, MVT::i32);
396 def so_neg_imm2part_2 : SDNodeXForm<imm, [{
397 unsigned V = ARM_AM::getSOImmTwoPartSecond(-(int)N->getZExtValue());
398 return CurDAG->getTargetConstant(V, MVT::i32);
401 /// imm0_31 predicate - True if the 32-bit immediate is in the range [0,31].
402 def imm0_31 : Operand<i32>, PatLeaf<(imm), [{
403 return (int32_t)N->getZExtValue() < 32;
406 /// imm0_31_m1 - Matches and prints like imm0_31, but encodes as 'value - 1'.
407 def imm0_31_m1 : Operand<i32>, PatLeaf<(imm), [{
408 return (int32_t)N->getZExtValue() < 32;
410 let EncoderMethod = "getImmMinusOneOpValue";
413 // Define ARM specific addressing modes.
416 // addrmode_imm12 := reg +/- imm12
418 def addrmode_imm12 : Operand<i32>,
419 ComplexPattern<i32, 2, "SelectAddrModeImm12", []> {
420 // 12-bit immediate operand. Note that instructions using this encode
421 // #0 and #-0 differently. We flag #-0 as the magic value INT32_MIN. All other
422 // immediate values are as normal.
424 let EncoderMethod = "getAddrModeImm12OpValue";
425 let PrintMethod = "printAddrModeImm12Operand";
426 let MIOperandInfo = (ops GPR:$base, i32imm:$offsimm);
428 // ldst_so_reg := reg +/- reg shop imm
430 def ldst_so_reg : Operand<i32>,
431 ComplexPattern<i32, 3, "SelectLdStSOReg", []> {
432 let EncoderMethod = "getLdStSORegOpValue";
433 // FIXME: Simplify the printer
434 let PrintMethod = "printAddrMode2Operand";
435 let MIOperandInfo = (ops GPR:$base, GPR:$offsreg, i32imm:$offsimm);
438 // addrmode2 := reg +/- imm12
439 // := reg +/- reg shop imm
441 def addrmode2 : Operand<i32>,
442 ComplexPattern<i32, 3, "SelectAddrMode2", []> {
443 let PrintMethod = "printAddrMode2Operand";
444 let MIOperandInfo = (ops GPR:$base, GPR:$offsreg, i32imm:$offsimm);
447 def am2offset : Operand<i32>,
448 ComplexPattern<i32, 2, "SelectAddrMode2Offset",
449 [], [SDNPWantRoot]> {
450 let PrintMethod = "printAddrMode2OffsetOperand";
451 let MIOperandInfo = (ops GPR, i32imm);
454 // addrmode3 := reg +/- reg
455 // addrmode3 := reg +/- imm8
457 def addrmode3 : Operand<i32>,
458 ComplexPattern<i32, 3, "SelectAddrMode3", []> {
459 let EncoderMethod = "getAddrMode3OpValue";
460 let PrintMethod = "printAddrMode3Operand";
461 let MIOperandInfo = (ops GPR:$base, GPR:$offsreg, i32imm:$offsimm);
464 def am3offset : Operand<i32>,
465 ComplexPattern<i32, 2, "SelectAddrMode3Offset",
466 [], [SDNPWantRoot]> {
467 let EncoderMethod = "getAddrMode3OffsetOpValue";
468 let PrintMethod = "printAddrMode3OffsetOperand";
469 let MIOperandInfo = (ops GPR, i32imm);
472 // ldstm_mode := {ia, ib, da, db}
474 def ldstm_mode : OptionalDefOperand<OtherVT, (ops i32), (ops (i32 1))> {
475 let EncoderMethod = "getLdStmModeOpValue";
476 let PrintMethod = "printLdStmModeOperand";
479 def MemMode5AsmOperand : AsmOperandClass {
480 let Name = "MemMode5";
481 let SuperClasses = [];
484 // addrmode5 := reg +/- imm8*4
486 def addrmode5 : Operand<i32>,
487 ComplexPattern<i32, 2, "SelectAddrMode5", []> {
488 let PrintMethod = "printAddrMode5Operand";
489 let MIOperandInfo = (ops GPR:$base, i32imm);
490 let ParserMatchClass = MemMode5AsmOperand;
491 let EncoderMethod = "getAddrMode5OpValue";
494 // addrmode6 := reg with optional writeback
496 def addrmode6 : Operand<i32>,
497 ComplexPattern<i32, 2, "SelectAddrMode6", [], [SDNPWantParent]>{
498 let PrintMethod = "printAddrMode6Operand";
499 let MIOperandInfo = (ops GPR:$addr, i32imm);
500 let EncoderMethod = "getAddrMode6AddressOpValue";
503 def am6offset : Operand<i32> {
504 let PrintMethod = "printAddrMode6OffsetOperand";
505 let MIOperandInfo = (ops GPR);
506 let EncoderMethod = "getAddrMode6OffsetOpValue";
509 // addrmodepc := pc + reg
511 def addrmodepc : Operand<i32>,
512 ComplexPattern<i32, 2, "SelectAddrModePC", []> {
513 let PrintMethod = "printAddrModePCOperand";
514 let MIOperandInfo = (ops GPR, i32imm);
517 def nohash_imm : Operand<i32> {
518 let PrintMethod = "printNoHashImmediate";
521 //===----------------------------------------------------------------------===//
523 include "ARMInstrFormats.td"
525 //===----------------------------------------------------------------------===//
526 // Multiclass helpers...
529 /// AsI1_bin_irs - Defines a set of (op r, {so_imm|r|so_reg}) patterns for a
530 /// binop that produces a value.
531 multiclass AsI1_bin_irs<bits<4> opcod, string opc,
532 InstrItinClass iii, InstrItinClass iir, InstrItinClass iis,
533 PatFrag opnode, bit Commutable = 0> {
534 // The register-immediate version is re-materializable. This is useful
535 // in particular for taking the address of a local.
536 let isReMaterializable = 1 in {
537 def ri : AsI1<opcod, (outs GPR:$Rd), (ins GPR:$Rn, so_imm:$imm), DPFrm,
538 iii, opc, "\t$Rd, $Rn, $imm",
539 [(set GPR:$Rd, (opnode GPR:$Rn, so_imm:$imm))]> {
544 let Inst{19-16} = Rn;
545 let Inst{15-12} = Rd;
546 let Inst{11-0} = imm;
549 def rr : AsI1<opcod, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm), DPFrm,
550 iir, opc, "\t$Rd, $Rn, $Rm",
551 [(set GPR:$Rd, (opnode GPR:$Rn, GPR:$Rm))]> {
556 let isCommutable = Commutable;
557 let Inst{19-16} = Rn;
558 let Inst{15-12} = Rd;
559 let Inst{11-4} = 0b00000000;
562 def rs : AsI1<opcod, (outs GPR:$Rd), (ins GPR:$Rn, so_reg:$shift), DPSoRegFrm,
563 iis, opc, "\t$Rd, $Rn, $shift",
564 [(set GPR:$Rd, (opnode GPR:$Rn, so_reg:$shift))]> {
569 let Inst{19-16} = Rn;
570 let Inst{15-12} = Rd;
571 let Inst{11-0} = shift;
575 /// AI1_bin_s_irs - Similar to AsI1_bin_irs except it sets the 's' bit so the
576 /// instruction modifies the CPSR register.
577 let Defs = [CPSR] in {
578 multiclass AI1_bin_s_irs<bits<4> opcod, string opc,
579 InstrItinClass iii, InstrItinClass iir, InstrItinClass iis,
580 PatFrag opnode, bit Commutable = 0> {
581 def ri : AI1<opcod, (outs GPR:$Rd), (ins GPR:$Rn, so_imm:$imm), DPFrm,
582 iii, opc, "\t$Rd, $Rn, $imm",
583 [(set GPR:$Rd, (opnode GPR:$Rn, so_imm:$imm))]> {
589 let Inst{19-16} = Rn;
590 let Inst{15-12} = Rd;
591 let Inst{11-0} = imm;
593 def rr : AI1<opcod, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm), DPFrm,
594 iir, opc, "\t$Rd, $Rn, $Rm",
595 [(set GPR:$Rd, (opnode GPR:$Rn, GPR:$Rm))]> {
599 let isCommutable = Commutable;
602 let Inst{19-16} = Rn;
603 let Inst{15-12} = Rd;
604 let Inst{11-4} = 0b00000000;
607 def rs : AI1<opcod, (outs GPR:$Rd), (ins GPR:$Rn, so_reg:$shift), DPSoRegFrm,
608 iis, opc, "\t$Rd, $Rn, $shift",
609 [(set GPR:$Rd, (opnode GPR:$Rn, so_reg:$shift))]> {
615 let Inst{19-16} = Rn;
616 let Inst{15-12} = Rd;
617 let Inst{11-0} = shift;
622 /// AI1_cmp_irs - Defines a set of (op r, {so_imm|r|so_reg}) cmp / test
623 /// patterns. Similar to AsI1_bin_irs except the instruction does not produce
624 /// a explicit result, only implicitly set CPSR.
625 let isCompare = 1, Defs = [CPSR] in {
626 multiclass AI1_cmp_irs<bits<4> opcod, string opc,
627 InstrItinClass iii, InstrItinClass iir, InstrItinClass iis,
628 PatFrag opnode, bit Commutable = 0> {
629 def ri : AI1<opcod, (outs), (ins GPR:$Rn, so_imm:$imm), DPFrm, iii,
631 [(opnode GPR:$Rn, so_imm:$imm)]> {
636 let Inst{19-16} = Rn;
637 let Inst{15-12} = 0b0000;
638 let Inst{11-0} = imm;
640 def rr : AI1<opcod, (outs), (ins GPR:$Rn, GPR:$Rm), DPFrm, iir,
642 [(opnode GPR:$Rn, GPR:$Rm)]> {
645 let isCommutable = Commutable;
648 let Inst{19-16} = Rn;
649 let Inst{15-12} = 0b0000;
650 let Inst{11-4} = 0b00000000;
653 def rs : AI1<opcod, (outs), (ins GPR:$Rn, so_reg:$shift), DPSoRegFrm, iis,
654 opc, "\t$Rn, $shift",
655 [(opnode GPR:$Rn, so_reg:$shift)]> {
660 let Inst{19-16} = Rn;
661 let Inst{15-12} = 0b0000;
662 let Inst{11-0} = shift;
667 /// AI_ext_rrot - A unary operation with two forms: one whose operand is a
668 /// register and one whose operand is a register rotated by 8/16/24.
669 /// FIXME: Remove the 'r' variant. Its rot_imm is zero.
670 multiclass AI_ext_rrot<bits<8> opcod, string opc, PatFrag opnode> {
671 def r : AExtI<opcod, (outs GPR:$Rd), (ins GPR:$Rm),
672 IIC_iEXTr, opc, "\t$Rd, $Rm",
673 [(set GPR:$Rd, (opnode GPR:$Rm))]>,
674 Requires<[IsARM, HasV6]> {
677 let Inst{19-16} = 0b1111;
678 let Inst{15-12} = Rd;
679 let Inst{11-10} = 0b00;
682 def r_rot : AExtI<opcod, (outs GPR:$Rd), (ins GPR:$Rm, rot_imm:$rot),
683 IIC_iEXTr, opc, "\t$Rd, $Rm, ror $rot",
684 [(set GPR:$Rd, (opnode (rotr GPR:$Rm, rot_imm:$rot)))]>,
685 Requires<[IsARM, HasV6]> {
689 let Inst{19-16} = 0b1111;
690 let Inst{15-12} = Rd;
691 let Inst{11-10} = rot;
696 multiclass AI_ext_rrot_np<bits<8> opcod, string opc> {
697 def r : AExtI<opcod, (outs GPR:$Rd), (ins GPR:$Rm),
698 IIC_iEXTr, opc, "\t$Rd, $Rm",
699 [/* For disassembly only; pattern left blank */]>,
700 Requires<[IsARM, HasV6]> {
701 let Inst{19-16} = 0b1111;
702 let Inst{11-10} = 0b00;
704 def r_rot : AExtI<opcod, (outs GPR:$Rd), (ins GPR:$Rm, rot_imm:$rot),
705 IIC_iEXTr, opc, "\t$Rd, $Rm, ror $rot",
706 [/* For disassembly only; pattern left blank */]>,
707 Requires<[IsARM, HasV6]> {
709 let Inst{19-16} = 0b1111;
710 let Inst{11-10} = rot;
714 /// AI_exta_rrot - A binary operation with two forms: one whose operand is a
715 /// register and one whose operand is a register rotated by 8/16/24.
716 multiclass AI_exta_rrot<bits<8> opcod, string opc, PatFrag opnode> {
717 def rr : AExtI<opcod, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm),
718 IIC_iEXTAr, opc, "\t$Rd, $Rn, $Rm",
719 [(set GPR:$Rd, (opnode GPR:$Rn, GPR:$Rm))]>,
720 Requires<[IsARM, HasV6]> {
721 let Inst{11-10} = 0b00;
723 def rr_rot : AExtI<opcod, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm,
725 IIC_iEXTAr, opc, "\t$Rd, $Rn, $Rm, ror $rot",
726 [(set GPR:$Rd, (opnode GPR:$Rn,
727 (rotr GPR:$Rm, rot_imm:$rot)))]>,
728 Requires<[IsARM, HasV6]> {
731 let Inst{19-16} = Rn;
732 let Inst{11-10} = rot;
736 // For disassembly only.
737 multiclass AI_exta_rrot_np<bits<8> opcod, string opc> {
738 def rr : AExtI<opcod, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm),
739 IIC_iEXTAr, opc, "\t$Rd, $Rn, $Rm",
740 [/* For disassembly only; pattern left blank */]>,
741 Requires<[IsARM, HasV6]> {
742 let Inst{11-10} = 0b00;
744 def rr_rot : AExtI<opcod, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm,
746 IIC_iEXTAr, opc, "\t$Rd, $Rn, $Rm, ror $rot",
747 [/* For disassembly only; pattern left blank */]>,
748 Requires<[IsARM, HasV6]> {
751 let Inst{19-16} = Rn;
752 let Inst{11-10} = rot;
756 /// AI1_adde_sube_irs - Define instructions and patterns for adde and sube.
757 let Uses = [CPSR] in {
758 multiclass AI1_adde_sube_irs<bits<4> opcod, string opc, PatFrag opnode,
759 bit Commutable = 0> {
760 def ri : AsI1<opcod, (outs GPR:$Rd), (ins GPR:$Rn, so_imm:$imm),
761 DPFrm, IIC_iALUi, opc, "\t$Rd, $Rn, $imm",
762 [(set GPR:$Rd, (opnode GPR:$Rn, so_imm:$imm))]>,
768 let Inst{15-12} = Rd;
769 let Inst{19-16} = Rn;
770 let Inst{11-0} = imm;
772 def rr : AsI1<opcod, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm),
773 DPFrm, IIC_iALUr, opc, "\t$Rd, $Rn, $Rm",
774 [(set GPR:$Rd, (opnode GPR:$Rn, GPR:$Rm))]>,
779 let Inst{11-4} = 0b00000000;
781 let isCommutable = Commutable;
783 let Inst{15-12} = Rd;
784 let Inst{19-16} = Rn;
786 def rs : AsI1<opcod, (outs GPR:$Rd), (ins GPR:$Rn, so_reg:$shift),
787 DPSoRegFrm, IIC_iALUsr, opc, "\t$Rd, $Rn, $shift",
788 [(set GPR:$Rd, (opnode GPR:$Rn, so_reg:$shift))]>,
794 let Inst{11-0} = shift;
795 let Inst{15-12} = Rd;
796 let Inst{19-16} = Rn;
799 // Carry setting variants
800 let Defs = [CPSR] in {
801 multiclass AI1_adde_sube_s_irs<bits<4> opcod, string opc, PatFrag opnode,
802 bit Commutable = 0> {
803 def Sri : AXI1<opcod, (outs GPR:$Rd), (ins GPR:$Rn, so_imm:$imm),
804 DPFrm, IIC_iALUi, !strconcat(opc, "\t$Rd, $Rn, $imm"),
805 [(set GPR:$Rd, (opnode GPR:$Rn, so_imm:$imm))]>,
810 let Inst{15-12} = Rd;
811 let Inst{19-16} = Rn;
812 let Inst{11-0} = imm;
816 def Srr : AXI1<opcod, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm),
817 DPFrm, IIC_iALUr, !strconcat(opc, "\t$Rd, $Rn, $Rm"),
818 [(set GPR:$Rd, (opnode GPR:$Rn, GPR:$Rm))]>,
823 let Inst{11-4} = 0b00000000;
824 let isCommutable = Commutable;
826 let Inst{15-12} = Rd;
827 let Inst{19-16} = Rn;
831 def Srs : AXI1<opcod, (outs GPR:$Rd), (ins GPR:$Rn, so_reg:$shift),
832 DPSoRegFrm, IIC_iALUsr, !strconcat(opc, "\t$Rd, $Rn, $shift"),
833 [(set GPR:$Rd, (opnode GPR:$Rn, so_reg:$shift))]>,
838 let Inst{11-0} = shift;
839 let Inst{15-12} = Rd;
840 let Inst{19-16} = Rn;
848 let canFoldAsLoad = 1, isReMaterializable = 1 in {
849 multiclass AI_ldr1<bit isByte, string opc, InstrItinClass iii,
850 InstrItinClass iir, PatFrag opnode> {
851 // Note: We use the complex addrmode_imm12 rather than just an input
852 // GPR and a constrained immediate so that we can use this to match
853 // frame index references and avoid matching constant pool references.
854 def i12: AIldst1<0b010, 1, isByte, (outs GPR:$Rt), (ins addrmode_imm12:$addr),
855 AddrMode_i12, LdFrm, iii, opc, "\t$Rt, $addr",
856 [(set GPR:$Rt, (opnode addrmode_imm12:$addr))]> {
859 let Inst{23} = addr{12}; // U (add = ('U' == 1))
860 let Inst{19-16} = addr{16-13}; // Rn
861 let Inst{15-12} = Rt;
862 let Inst{11-0} = addr{11-0}; // imm12
864 def rs : AIldst1<0b011, 1, isByte, (outs GPR:$Rt), (ins ldst_so_reg:$shift),
865 AddrModeNone, LdFrm, iir, opc, "\t$Rt, $shift",
866 [(set GPR:$Rt, (opnode ldst_so_reg:$shift))]> {
869 let Inst{23} = shift{12}; // U (add = ('U' == 1))
870 let Inst{19-16} = shift{16-13}; // Rn
871 let Inst{15-12} = Rt;
872 let Inst{11-0} = shift{11-0};
877 multiclass AI_str1<bit isByte, string opc, InstrItinClass iii,
878 InstrItinClass iir, PatFrag opnode> {
879 // Note: We use the complex addrmode_imm12 rather than just an input
880 // GPR and a constrained immediate so that we can use this to match
881 // frame index references and avoid matching constant pool references.
882 def i12 : AIldst1<0b010, 0, isByte, (outs),
883 (ins GPR:$Rt, addrmode_imm12:$addr),
884 AddrMode_i12, StFrm, iii, opc, "\t$Rt, $addr",
885 [(opnode GPR:$Rt, addrmode_imm12:$addr)]> {
888 let Inst{23} = addr{12}; // U (add = ('U' == 1))
889 let Inst{19-16} = addr{16-13}; // Rn
890 let Inst{15-12} = Rt;
891 let Inst{11-0} = addr{11-0}; // imm12
893 def rs : AIldst1<0b011, 0, isByte, (outs), (ins GPR:$Rt, ldst_so_reg:$shift),
894 AddrModeNone, StFrm, iir, opc, "\t$Rt, $shift",
895 [(opnode GPR:$Rt, ldst_so_reg:$shift)]> {
898 let Inst{23} = shift{12}; // U (add = ('U' == 1))
899 let Inst{19-16} = shift{16-13}; // Rn
900 let Inst{15-12} = Rt;
901 let Inst{11-0} = shift{11-0};
904 //===----------------------------------------------------------------------===//
906 //===----------------------------------------------------------------------===//
908 //===----------------------------------------------------------------------===//
909 // Miscellaneous Instructions.
912 /// CONSTPOOL_ENTRY - This instruction represents a floating constant pool in
913 /// the function. The first operand is the ID# for this instruction, the second
914 /// is the index into the MachineConstantPool that this is, the third is the
915 /// size in bytes of this constant pool entry.
916 let neverHasSideEffects = 1, isNotDuplicable = 1 in
917 def CONSTPOOL_ENTRY :
918 PseudoInst<(outs), (ins cpinst_operand:$instid, cpinst_operand:$cpidx,
919 i32imm:$size), NoItinerary, "", []>;
921 // FIXME: Marking these as hasSideEffects is necessary to prevent machine DCE
922 // from removing one half of the matched pairs. That breaks PEI, which assumes
923 // these will always be in pairs, and asserts if it finds otherwise. Better way?
924 let Defs = [SP], Uses = [SP], hasSideEffects = 1 in {
926 PseudoInst<(outs), (ins i32imm:$amt1, i32imm:$amt2, pred:$p), NoItinerary, "",
927 [(ARMcallseq_end timm:$amt1, timm:$amt2)]>;
929 def ADJCALLSTACKDOWN :
930 PseudoInst<(outs), (ins i32imm:$amt, pred:$p), NoItinerary, "",
931 [(ARMcallseq_start timm:$amt)]>;
934 def NOP : AI<(outs), (ins), MiscFrm, NoItinerary, "nop", "",
935 [/* For disassembly only; pattern left blank */]>,
936 Requires<[IsARM, HasV6T2]> {
937 let Inst{27-16} = 0b001100100000;
938 let Inst{15-8} = 0b11110000;
939 let Inst{7-0} = 0b00000000;
942 def YIELD : AI<(outs), (ins), MiscFrm, NoItinerary, "yield", "",
943 [/* For disassembly only; pattern left blank */]>,
944 Requires<[IsARM, HasV6T2]> {
945 let Inst{27-16} = 0b001100100000;
946 let Inst{15-8} = 0b11110000;
947 let Inst{7-0} = 0b00000001;
950 def WFE : AI<(outs), (ins), MiscFrm, NoItinerary, "wfe", "",
951 [/* For disassembly only; pattern left blank */]>,
952 Requires<[IsARM, HasV6T2]> {
953 let Inst{27-16} = 0b001100100000;
954 let Inst{15-8} = 0b11110000;
955 let Inst{7-0} = 0b00000010;
958 def WFI : AI<(outs), (ins), MiscFrm, NoItinerary, "wfi", "",
959 [/* For disassembly only; pattern left blank */]>,
960 Requires<[IsARM, HasV6T2]> {
961 let Inst{27-16} = 0b001100100000;
962 let Inst{15-8} = 0b11110000;
963 let Inst{7-0} = 0b00000011;
966 def SEL : AI<(outs GPR:$dst), (ins GPR:$a, GPR:$b), DPFrm, NoItinerary, "sel",
968 [/* For disassembly only; pattern left blank */]>,
969 Requires<[IsARM, HasV6]> {
974 let Inst{15-12} = Rd;
975 let Inst{19-16} = Rn;
976 let Inst{27-20} = 0b01101000;
977 let Inst{7-4} = 0b1011;
978 let Inst{11-8} = 0b1111;
981 def SEV : AI<(outs), (ins), MiscFrm, NoItinerary, "sev", "",
982 [/* For disassembly only; pattern left blank */]>,
983 Requires<[IsARM, HasV6T2]> {
984 let Inst{27-16} = 0b001100100000;
985 let Inst{15-8} = 0b11110000;
986 let Inst{7-0} = 0b00000100;
989 // The i32imm operand $val can be used by a debugger to store more information
990 // about the breakpoint.
991 def BKPT : AI<(outs), (ins i32imm:$val), MiscFrm, NoItinerary, "bkpt", "\t$val",
992 [/* For disassembly only; pattern left blank */]>,
995 let Inst{3-0} = val{3-0};
996 let Inst{19-8} = val{15-4};
997 let Inst{27-20} = 0b00010010;
998 let Inst{7-4} = 0b0111;
1001 // Change Processor State is a system instruction -- for disassembly only.
1002 // The singleton $opt operand contains the following information:
1003 // opt{4-0} = mode from Inst{4-0}
1004 // opt{5} = changemode from Inst{17}
1005 // opt{8-6} = AIF from Inst{8-6}
1006 // opt{10-9} = imod from Inst{19-18} with 0b10 as enable and 0b11 as disable
1007 // FIXME: Integrated assembler will need these split out.
1008 def CPS : AXI<(outs), (ins cps_opt:$opt), MiscFrm, NoItinerary, "cps$opt",
1009 [/* For disassembly only; pattern left blank */]>,
1011 let Inst{31-28} = 0b1111;
1012 let Inst{27-20} = 0b00010000;
1017 // Preload signals the memory system of possible future data/instruction access.
1018 // These are for disassembly only.
1019 multiclass APreLoad<bits<1> read, bits<1> data, string opc> {
1021 def i12 : AXI<(outs), (ins addrmode_imm12:$addr), MiscFrm, IIC_Preload,
1022 !strconcat(opc, "\t$addr"),
1023 [(ARMPreload addrmode_imm12:$addr, (i32 read), (i32 data))]> {
1026 let Inst{31-26} = 0b111101;
1027 let Inst{25} = 0; // 0 for immediate form
1028 let Inst{24} = data;
1029 let Inst{23} = addr{12}; // U (add = ('U' == 1))
1030 let Inst{22} = read;
1031 let Inst{21-20} = 0b01;
1032 let Inst{19-16} = addr{16-13}; // Rn
1033 let Inst{15-12} = Rt;
1034 let Inst{11-0} = addr{11-0}; // imm12
1037 def rs : AXI<(outs), (ins ldst_so_reg:$shift), MiscFrm, IIC_Preload,
1038 !strconcat(opc, "\t$shift"),
1039 [(ARMPreload ldst_so_reg:$shift, (i32 read), (i32 data))]> {
1042 let Inst{31-26} = 0b111101;
1043 let Inst{25} = 1; // 1 for register form
1044 let Inst{24} = data;
1045 let Inst{23} = shift{12}; // U (add = ('U' == 1))
1046 let Inst{22} = read;
1047 let Inst{21-20} = 0b01;
1048 let Inst{19-16} = shift{16-13}; // Rn
1049 let Inst{11-0} = shift{11-0};
1053 defm PLD : APreLoad<1, 1, "pld">, Requires<[IsARM]>;
1054 defm PLDW : APreLoad<0, 1, "pldw">, Requires<[IsARM,HasV7,HasMP]>;
1055 defm PLI : APreLoad<1, 0, "pli">, Requires<[IsARM,HasV7]>;
1057 def SETEND : AXI<(outs),(ins setend_op:$end), MiscFrm, NoItinerary,
1059 [/* For disassembly only; pattern left blank */]>,
1062 let Inst{31-10} = 0b1111000100000001000000;
1067 def DBG : AI<(outs), (ins i32imm:$opt), MiscFrm, NoItinerary, "dbg", "\t$opt",
1068 [/* For disassembly only; pattern left blank */]>,
1069 Requires<[IsARM, HasV7]> {
1071 let Inst{27-4} = 0b001100100000111100001111;
1072 let Inst{3-0} = opt;
1075 // A5.4 Permanently UNDEFINED instructions.
1076 let isBarrier = 1, isTerminator = 1 in
1077 def TRAP : AXI<(outs), (ins), MiscFrm, NoItinerary,
1080 let Inst{27-25} = 0b011;
1081 let Inst{24-20} = 0b11111;
1082 let Inst{7-5} = 0b111;
1086 // Address computation and loads and stores in PIC mode.
1087 // FIXME: These PIC insn patterns are pseudos, but derive from the normal insn
1088 // classes (AXI1, et.al.) and so have encoding information and such,
1089 // which is suboptimal. Once the rest of the code emitter (including
1090 // JIT) is MC-ized we should look at refactoring these into true
1091 // pseudos. As is, the encoding information ends up being ignored,
1092 // as these instructions are lowered to individual MC-insts.
1093 let isNotDuplicable = 1 in {
1094 def PICADD : AXI1<0b0100, (outs GPR:$dst), (ins GPR:$a, pclabel:$cp, pred:$p),
1095 Pseudo, IIC_iALUr, "",
1096 [(set GPR:$dst, (ARMpic_add GPR:$a, imm:$cp))]>;
1098 let AddedComplexity = 10 in {
1099 def PICLDR : AXI2ldw<(outs GPR:$dst), (ins addrmodepc:$addr, pred:$p),
1100 Pseudo, IIC_iLoad_r, "",
1101 [(set GPR:$dst, (load addrmodepc:$addr))]>;
1103 def PICLDRH : AXI3ldh<(outs GPR:$dst), (ins addrmodepc:$addr, pred:$p),
1104 Pseudo, IIC_iLoad_bh_r, "",
1105 [(set GPR:$dst, (zextloadi16 addrmodepc:$addr))]>;
1107 def PICLDRB : AXI2ldb<(outs GPR:$dst), (ins addrmodepc:$addr, pred:$p),
1108 Pseudo, IIC_iLoad_bh_r, "",
1109 [(set GPR:$dst, (zextloadi8 addrmodepc:$addr))]>;
1111 def PICLDRSH : AXI3ldsh<(outs GPR:$dst), (ins addrmodepc:$addr, pred:$p),
1112 Pseudo, IIC_iLoad_bh_r, "",
1113 [(set GPR:$dst, (sextloadi16 addrmodepc:$addr))]>;
1115 def PICLDRSB : AXI3ldsb<(outs GPR:$dst), (ins addrmodepc:$addr, pred:$p),
1116 Pseudo, IIC_iLoad_bh_r, "",
1117 [(set GPR:$dst, (sextloadi8 addrmodepc:$addr))]>;
1119 let AddedComplexity = 10 in {
1120 def PICSTR : AXI2stw<(outs), (ins GPR:$src, addrmodepc:$addr, pred:$p),
1121 Pseudo, IIC_iStore_r, "",
1122 [(store GPR:$src, addrmodepc:$addr)]>;
1124 def PICSTRH : AXI3sth<(outs), (ins GPR:$src, addrmodepc:$addr, pred:$p),
1125 Pseudo, IIC_iStore_bh_r, "",
1126 [(truncstorei16 GPR:$src, addrmodepc:$addr)]>;
1128 def PICSTRB : AXI2stb<(outs), (ins GPR:$src, addrmodepc:$addr, pred:$p),
1129 Pseudo, IIC_iStore_bh_r, "",
1130 [(truncstorei8 GPR:$src, addrmodepc:$addr)]>;
1132 } // isNotDuplicable = 1
1135 // LEApcrel - Load a pc-relative address into a register without offending the
1137 // FIXME: These are marked as pseudos, but they're really not(?). They're just
1138 // the ADR instruction. Is this the right way to handle that? They need
1139 // encoding information regardless.
1140 let neverHasSideEffects = 1 in {
1141 let isReMaterializable = 1 in
1142 def LEApcrel : AXI1<0x0, (outs GPR:$dst), (ins i32imm:$label, pred:$p),
1144 "adr$p\t$dst, #$label", []>;
1146 } // neverHasSideEffects
1147 def LEApcrelJT : AXI1<0x0, (outs GPR:$dst),
1148 (ins i32imm:$label, nohash_imm:$id, pred:$p),
1150 "adr$p\t$dst, #${label}_${id}", []> {
1154 //===----------------------------------------------------------------------===//
1155 // Control Flow Instructions.
1158 let isReturn = 1, isTerminator = 1, isBarrier = 1 in {
1160 def BX_RET : AI<(outs), (ins), BrMiscFrm, IIC_Br,
1161 "bx", "\tlr", [(ARMretflag)]>,
1162 Requires<[IsARM, HasV4T]> {
1163 let Inst{27-0} = 0b0001001011111111111100011110;
1167 def MOVPCLR : AI<(outs), (ins), BrMiscFrm, IIC_Br,
1168 "mov", "\tpc, lr", [(ARMretflag)]>,
1169 Requires<[IsARM, NoV4T]> {
1170 let Inst{27-0} = 0b0001101000001111000000001110;
1174 // Indirect branches
1175 let isBranch = 1, isTerminator = 1, isBarrier = 1, isIndirectBranch = 1 in {
1177 def BRIND : AXI<(outs), (ins GPR:$dst), BrMiscFrm, IIC_Br, "bx\t$dst",
1178 [(brind GPR:$dst)]>,
1179 Requires<[IsARM, HasV4T]> {
1181 let Inst{31-4} = 0b1110000100101111111111110001;
1182 let Inst{3-0} = dst;
1186 def MOVPCRX : AXI<(outs), (ins GPR:$dst), BrMiscFrm, IIC_Br, "mov\tpc, $dst",
1187 [(brind GPR:$dst)]>,
1188 Requires<[IsARM, NoV4T]> {
1190 let Inst{31-4} = 0b1110000110100000111100000000;
1191 let Inst{3-0} = dst;
1195 // FIXME: remove when we have a way to marking a MI with these properties.
1196 // FIXME: Should pc be an implicit operand like PICADD, etc?
1197 let isReturn = 1, isTerminator = 1, isBarrier = 1, mayLoad = 1,
1198 hasExtraDefRegAllocReq = 1, isCodeGenOnly = 1 in
1199 def LDM_RET : AXI4ld<(outs GPR:$wb), (ins GPR:$Rn, ldstm_mode:$mode, pred:$p,
1200 reglist:$dsts, variable_ops),
1201 IndexModeUpd, LdStMulFrm, IIC_iLoad_mBr,
1202 "ldm${mode}${p}\t$Rn!, $dsts",
1207 // On non-Darwin platforms R9 is callee-saved.
1209 Defs = [R0, R1, R2, R3, R12, LR,
1210 D0, D1, D2, D3, D4, D5, D6, D7,
1211 D16, D17, D18, D19, D20, D21, D22, D23,
1212 D24, D25, D26, D27, D28, D29, D30, D31, CPSR, FPSCR] in {
1213 def BL : ABXI<0b1011, (outs), (ins bltarget:$func, variable_ops),
1214 IIC_Br, "bl\t$func",
1215 [(ARMcall tglobaladdr:$func)]>,
1216 Requires<[IsARM, IsNotDarwin]> {
1217 let Inst{31-28} = 0b1110;
1219 let Inst{23-0} = func;
1222 def BL_pred : ABI<0b1011, (outs), (ins bltarget:$func, variable_ops),
1223 IIC_Br, "bl", "\t$func",
1224 [(ARMcall_pred tglobaladdr:$func)]>,
1225 Requires<[IsARM, IsNotDarwin]> {
1227 let Inst{23-0} = func;
1231 def BLX : AXI<(outs), (ins GPR:$func, variable_ops), BrMiscFrm,
1232 IIC_Br, "blx\t$func",
1233 [(ARMcall GPR:$func)]>,
1234 Requires<[IsARM, HasV5T, IsNotDarwin]> {
1236 let Inst{27-4} = 0b000100101111111111110011;
1237 let Inst{3-0} = func;
1241 // Note: Restrict $func to the tGPR regclass to prevent it being in LR.
1242 def BX : ABXIx2<(outs), (ins tGPR:$func, variable_ops),
1243 IIC_Br, "mov\tlr, pc\n\tbx\t$func",
1244 [(ARMcall_nolink tGPR:$func)]>,
1245 Requires<[IsARM, HasV4T, IsNotDarwin]> {
1247 let Inst{27-4} = 0b000100101111111111110001;
1248 let Inst{3-0} = func;
1252 def BMOVPCRX : ABXIx2<(outs), (ins tGPR:$func, variable_ops),
1253 IIC_Br, "mov\tlr, pc\n\tmov\tpc, $func",
1254 [(ARMcall_nolink tGPR:$func)]>,
1255 Requires<[IsARM, NoV4T, IsNotDarwin]> {
1257 let Inst{27-4} = 0b000110100000111100000000;
1258 let Inst{3-0} = func;
1262 // On Darwin R9 is call-clobbered.
1264 Defs = [R0, R1, R2, R3, R9, R12, LR,
1265 D0, D1, D2, D3, D4, D5, D6, D7,
1266 D16, D17, D18, D19, D20, D21, D22, D23,
1267 D24, D25, D26, D27, D28, D29, D30, D31, CPSR, FPSCR] in {
1268 def BLr9 : ABXI<0b1011, (outs), (ins bltarget:$func, variable_ops),
1269 IIC_Br, "bl\t$func",
1270 [(ARMcall tglobaladdr:$func)]>, Requires<[IsARM, IsDarwin]> {
1271 let Inst{31-28} = 0b1110;
1273 let Inst{23-0} = func;
1276 def BLr9_pred : ABI<0b1011, (outs), (ins bltarget:$func, variable_ops),
1277 IIC_Br, "bl", "\t$func",
1278 [(ARMcall_pred tglobaladdr:$func)]>,
1279 Requires<[IsARM, IsDarwin]> {
1281 let Inst{23-0} = func;
1285 def BLXr9 : AXI<(outs), (ins GPR:$func, variable_ops), BrMiscFrm,
1286 IIC_Br, "blx\t$func",
1287 [(ARMcall GPR:$func)]>, Requires<[IsARM, HasV5T, IsDarwin]> {
1289 let Inst{27-4} = 0b000100101111111111110011;
1290 let Inst{3-0} = func;
1294 // Note: Restrict $func to the tGPR regclass to prevent it being in LR.
1295 def BXr9 : ABXIx2<(outs), (ins tGPR:$func, variable_ops),
1296 IIC_Br, "mov\tlr, pc\n\tbx\t$func",
1297 [(ARMcall_nolink tGPR:$func)]>,
1298 Requires<[IsARM, HasV4T, IsDarwin]> {
1300 let Inst{27-4} = 0b000100101111111111110001;
1301 let Inst{3-0} = func;
1305 def BMOVPCRXr9 : ABXIx2<(outs), (ins tGPR:$func, variable_ops),
1306 IIC_Br, "mov\tlr, pc\n\tmov\tpc, $func",
1307 [(ARMcall_nolink tGPR:$func)]>,
1308 Requires<[IsARM, NoV4T, IsDarwin]> {
1310 let Inst{27-4} = 0b000110100000111100000000;
1311 let Inst{3-0} = func;
1317 // FIXME: These should probably be xformed into the non-TC versions of the
1318 // instructions as part of MC lowering.
1319 let isCall = 1, isTerminator = 1, isReturn = 1, isBarrier = 1 in {
1321 let Defs = [R0, R1, R2, R3, R9, R12,
1322 D0, D1, D2, D3, D4, D5, D6, D7,
1323 D16, D17, D18, D19, D20, D21, D22, D23, D24, D25, D26,
1324 D27, D28, D29, D30, D31, PC],
1326 def TCRETURNdi : AInoP<(outs), (ins i32imm:$dst, variable_ops),
1328 "@TC_RETURN","\t$dst", []>, Requires<[IsDarwin]>;
1330 def TCRETURNri : AInoP<(outs), (ins tcGPR:$dst, variable_ops),
1332 "@TC_RETURN","\t$dst", []>, Requires<[IsDarwin]>;
1334 def TAILJMPd : ABXI<0b1010, (outs), (ins brtarget:$dst, variable_ops),
1335 IIC_Br, "b\t$dst @ TAILCALL",
1336 []>, Requires<[IsDarwin]>;
1338 def TAILJMPdt: ABXI<0b1010, (outs), (ins brtarget:$dst, variable_ops),
1339 IIC_Br, "b.w\t$dst @ TAILCALL",
1340 []>, Requires<[IsDarwin]>;
1342 def TAILJMPr : AXI<(outs), (ins tcGPR:$dst, variable_ops),
1343 BrMiscFrm, IIC_Br, "bx\t$dst @ TAILCALL",
1344 []>, Requires<[IsDarwin]> {
1346 let Inst{31-4} = 0b1110000100101111111111110001;
1347 let Inst{3-0} = dst;
1351 // Non-Darwin versions (the difference is R9).
1352 let Defs = [R0, R1, R2, R3, R12,
1353 D0, D1, D2, D3, D4, D5, D6, D7,
1354 D16, D17, D18, D19, D20, D21, D22, D23, D24, D25, D26,
1355 D27, D28, D29, D30, D31, PC],
1357 def TCRETURNdiND : AInoP<(outs), (ins i32imm:$dst, variable_ops),
1359 "@TC_RETURN","\t$dst", []>, Requires<[IsNotDarwin]>;
1361 def TCRETURNriND : AInoP<(outs), (ins tcGPR:$dst, variable_ops),
1363 "@TC_RETURN","\t$dst", []>, Requires<[IsNotDarwin]>;
1365 def TAILJMPdND : ABXI<0b1010, (outs), (ins brtarget:$dst, variable_ops),
1366 IIC_Br, "b\t$dst @ TAILCALL",
1367 []>, Requires<[IsARM, IsNotDarwin]>;
1369 def TAILJMPdNDt : ABXI<0b1010, (outs), (ins brtarget:$dst, variable_ops),
1370 IIC_Br, "b.w\t$dst @ TAILCALL",
1371 []>, Requires<[IsThumb, IsNotDarwin]>;
1373 def TAILJMPrND : AXI<(outs), (ins tcGPR:$dst, variable_ops),
1374 BrMiscFrm, IIC_Br, "bx\t$dst @ TAILCALL",
1375 []>, Requires<[IsNotDarwin]> {
1377 let Inst{31-4} = 0b1110000100101111111111110001;
1378 let Inst{3-0} = dst;
1383 let isBranch = 1, isTerminator = 1 in {
1384 // B is "predicable" since it can be xformed into a Bcc.
1385 let isBarrier = 1 in {
1386 let isPredicable = 1 in
1387 def B : ABXI<0b1010, (outs), (ins brtarget:$target), IIC_Br,
1388 "b\t$target", [(br bb:$target)]> {
1390 let Inst{31-28} = 0b1110;
1391 let Inst{23-0} = target;
1394 let isNotDuplicable = 1, isIndirectBranch = 1,
1395 // FIXME: $imm field is not specified by asm string. Mark as cgonly.
1396 isCodeGenOnly = 1 in {
1397 def BR_JTr : JTI<(outs), (ins GPR:$target, jtblock_operand:$jt, i32imm:$id),
1398 IIC_Br, "mov\tpc, $target$jt",
1399 [(ARMbrjt GPR:$target, tjumptable:$jt, imm:$id)]> {
1400 let Inst{11-4} = 0b00000000;
1401 let Inst{15-12} = 0b1111;
1402 let Inst{20} = 0; // S Bit
1403 let Inst{24-21} = 0b1101;
1404 let Inst{27-25} = 0b000;
1406 def BR_JTm : JTI<(outs),
1407 (ins addrmode2:$target, jtblock_operand:$jt, i32imm:$id),
1408 IIC_Br, "ldr\tpc, $target$jt",
1409 [(ARMbrjt (i32 (load addrmode2:$target)), tjumptable:$jt,
1411 let Inst{15-12} = 0b1111;
1412 let Inst{20} = 1; // L bit
1413 let Inst{21} = 0; // W bit
1414 let Inst{22} = 0; // B bit
1415 let Inst{24} = 1; // P bit
1416 let Inst{27-25} = 0b011;
1418 def BR_JTadd : JTI<(outs),
1419 (ins GPR:$target, GPR:$idx, jtblock_operand:$jt, i32imm:$id),
1420 IIC_Br, "add\tpc, $target, $idx$jt",
1421 [(ARMbrjt (add GPR:$target, GPR:$idx), tjumptable:$jt,
1423 let Inst{15-12} = 0b1111;
1424 let Inst{20} = 0; // S bit
1425 let Inst{24-21} = 0b0100;
1426 let Inst{27-25} = 0b000;
1428 } // isNotDuplicable = 1, isIndirectBranch = 1
1431 // FIXME: should be able to write a pattern for ARMBrcond, but can't use
1432 // a two-value operand where a dag node expects two operands. :(
1433 def Bcc : ABI<0b1010, (outs), (ins brtarget:$target),
1434 IIC_Br, "b", "\t$target",
1435 [/*(ARMbrcond bb:$target, imm:$cc, CCR:$ccr)*/]> {
1437 let Inst{23-0} = target;
1441 // Branch and Exchange Jazelle -- for disassembly only
1442 def BXJ : ABI<0b0001, (outs), (ins GPR:$func), NoItinerary, "bxj", "\t$func",
1443 [/* For disassembly only; pattern left blank */]> {
1444 let Inst{23-20} = 0b0010;
1445 //let Inst{19-8} = 0xfff;
1446 let Inst{7-4} = 0b0010;
1449 // Secure Monitor Call is a system instruction -- for disassembly only
1450 def SMC : ABI<0b0001, (outs), (ins i32imm:$opt), NoItinerary, "smc", "\t$opt",
1451 [/* For disassembly only; pattern left blank */]> {
1453 let Inst{23-4} = 0b01100000000000000111;
1454 let Inst{3-0} = opt;
1457 // Supervisor Call (Software Interrupt) -- for disassembly only
1459 def SVC : ABI<0b1111, (outs), (ins i32imm:$svc), IIC_Br, "svc", "\t$svc",
1460 [/* For disassembly only; pattern left blank */]> {
1462 let Inst{23-0} = svc;
1466 // Store Return State is a system instruction -- for disassembly only
1467 let isCodeGenOnly = 1 in { // FIXME: This should not use submode!
1468 def SRSW : ABXI<{1,0,0,?}, (outs), (ins ldstm_mode:$amode, i32imm:$mode),
1469 NoItinerary, "srs${amode}\tsp!, $mode",
1470 [/* For disassembly only; pattern left blank */]> {
1471 let Inst{31-28} = 0b1111;
1472 let Inst{22-20} = 0b110; // W = 1
1475 def SRS : ABXI<{1,0,0,?}, (outs), (ins ldstm_mode:$amode, i32imm:$mode),
1476 NoItinerary, "srs${amode}\tsp, $mode",
1477 [/* For disassembly only; pattern left blank */]> {
1478 let Inst{31-28} = 0b1111;
1479 let Inst{22-20} = 0b100; // W = 0
1482 // Return From Exception is a system instruction -- for disassembly only
1483 def RFEW : ABXI<{1,0,0,?}, (outs), (ins ldstm_mode:$amode, GPR:$base),
1484 NoItinerary, "rfe${amode}\t$base!",
1485 [/* For disassembly only; pattern left blank */]> {
1486 let Inst{31-28} = 0b1111;
1487 let Inst{22-20} = 0b011; // W = 1
1490 def RFE : ABXI<{1,0,0,?}, (outs), (ins ldstm_mode:$amode, GPR:$base),
1491 NoItinerary, "rfe${amode}\t$base",
1492 [/* For disassembly only; pattern left blank */]> {
1493 let Inst{31-28} = 0b1111;
1494 let Inst{22-20} = 0b001; // W = 0
1496 } // isCodeGenOnly = 1
1498 //===----------------------------------------------------------------------===//
1499 // Load / store Instructions.
1505 defm LDR : AI_ldr1<0, "ldr", IIC_iLoad_r, IIC_iLoad_si,
1506 UnOpFrag<(load node:$Src)>>;
1507 defm LDRB : AI_ldr1<1, "ldrb", IIC_iLoad_bh_r, IIC_iLoad_bh_si,
1508 UnOpFrag<(zextloadi8 node:$Src)>>;
1509 defm STR : AI_str1<0, "str", IIC_iStore_r, IIC_iStore_si,
1510 BinOpFrag<(store node:$LHS, node:$RHS)>>;
1511 defm STRB : AI_str1<1, "strb", IIC_iStore_bh_r, IIC_iStore_bh_si,
1512 BinOpFrag<(truncstorei8 node:$LHS, node:$RHS)>>;
1514 // Special LDR for loads from non-pc-relative constpools.
1515 let canFoldAsLoad = 1, mayLoad = 1, neverHasSideEffects = 1,
1516 isReMaterializable = 1 in
1517 def LDRcp : AIldst1<0b010, 1, 0, (outs GPR:$Rt), (ins addrmode_imm12:$addr),
1518 AddrMode_i12, LdFrm, IIC_iLoad_r, "ldr", "\t$Rt, $addr",
1522 let Inst{23} = addr{12}; // U (add = ('U' == 1))
1523 let Inst{19-16} = 0b1111;
1524 let Inst{15-12} = Rt;
1525 let Inst{11-0} = addr{11-0}; // imm12
1528 // Loads with zero extension
1529 def LDRH : AI3ldh<(outs GPR:$dst), (ins addrmode3:$addr), LdMiscFrm,
1530 IIC_iLoad_bh_r, "ldrh", "\t$dst, $addr",
1531 [(set GPR:$dst, (zextloadi16 addrmode3:$addr))]>;
1533 // Loads with sign extension
1534 def LDRSH : AI3ldsh<(outs GPR:$dst), (ins addrmode3:$addr), LdMiscFrm,
1535 IIC_iLoad_bh_r, "ldrsh", "\t$dst, $addr",
1536 [(set GPR:$dst, (sextloadi16 addrmode3:$addr))]>;
1538 def LDRSB : AI3ldsb<(outs GPR:$dst), (ins addrmode3:$addr), LdMiscFrm,
1539 IIC_iLoad_bh_r, "ldrsb", "\t$dst, $addr",
1540 [(set GPR:$dst, (sextloadi8 addrmode3:$addr))]>;
1542 let mayLoad = 1, neverHasSideEffects = 1, hasExtraDefRegAllocReq = 1,
1543 isCodeGenOnly = 1 in { // $dst2 doesn't exist in asmstring?
1545 def LDRD : AI3ldd<(outs GPR:$dst1, GPR:$dst2), (ins addrmode3:$addr), LdMiscFrm,
1546 IIC_iLoad_d_r, "ldrd", "\t$dst1, $addr",
1547 []>, Requires<[IsARM, HasV5TE]>;
1550 multiclass AI2_ldridx<bit isByte, string opc, InstrItinClass itin> {
1551 def _PRE : AI2ldstidx<1, isByte, 1, (outs GPR:$Rt, GPR:$Rn_wb),
1552 (ins addrmode2:$addr), IndexModePre, LdFrm, itin,
1553 opc, "\t$Rt, $addr!", "$addr.base = $Rn_wb", []> {
1554 let Inst{21} = 1; // W bit (overwrite)
1556 def _POST : AI2ldstidx<1, isByte, 0, (outs GPR:$Rt, GPR:$Rn_wb),
1557 (ins GPR:$Rn, am2offset:$offset),
1558 IndexModePost, LdFrm, itin,
1559 opc, "\t$Rt, [$Rn], $offset", "$Rn = $Rn_wb", []>;
1562 defm LDR : AI2_ldridx<0, "ldr", IIC_iLoad_ru>;
1563 defm LDRB : AI2_ldridx<1, "ldrb", IIC_iLoad_bh_ru>;
1565 def LDRH_PRE : AI3ldhpr<(outs GPR:$Rt, GPR:$Rn_wb),
1566 (ins addrmode3:$addr), LdMiscFrm, IIC_iLoad_bh_ru,
1567 "ldrh", "\t$Rt, $addr!", "$addr.base = $Rn_wb", []>;
1569 def LDRH_POST : AI3ldhpo<(outs GPR:$Rt, GPR:$Rn_wb),
1570 (ins GPR:$Rn,am3offset:$offset), LdMiscFrm, IIC_iLoad_bh_ru,
1571 "ldrh", "\t$Rt, [$Rn], $offset", "$Rn = $Rn_wb", []>;
1573 def LDRSH_PRE : AI3ldshpr<(outs GPR:$Rt, GPR:$Rn_wb),
1574 (ins addrmode3:$addr), LdMiscFrm, IIC_iLoad_bh_ru,
1575 "ldrsh", "\t$Rt, $addr!", "$addr.base = $Rn_wb", []>;
1577 def LDRSH_POST: AI3ldshpo<(outs GPR:$Rt, GPR:$Rn_wb),
1578 (ins GPR:$Rn,am3offset:$offset), LdMiscFrm, IIC_iLoad_bh_ru,
1579 "ldrsh", "\t$Rt, [$Rn], $offset", "$Rn = $Rn_wb", []>;
1581 def LDRSB_PRE : AI3ldsbpr<(outs GPR:$Rt, GPR:$Rn_wb),
1582 (ins addrmode3:$addr), LdMiscFrm, IIC_iLoad_bh_ru,
1583 "ldrsb", "\t$Rt, $addr!", "$addr.base = $Rn_wb", []>;
1585 def LDRSB_POST: AI3ldsbpo<(outs GPR:$Rt, GPR:$Rn_wb),
1586 (ins GPR:$Rn,am3offset:$offset), LdMiscFrm, IIC_iLoad_ru,
1587 "ldrsb", "\t$Rt, [$Rn], $offset", "$Rn = $Rn_wb", []>;
1589 // For disassembly only
1590 def LDRD_PRE : AI3lddpr<(outs GPR:$dst1, GPR:$dst2, GPR:$base_wb),
1591 (ins addrmode3:$addr), LdMiscFrm, IIC_iLoad_d_ru,
1592 "ldrd", "\t$dst1, $dst2, $addr!", "$addr.base = $base_wb", []>,
1593 Requires<[IsARM, HasV5TE]>;
1595 // For disassembly only
1596 def LDRD_POST : AI3lddpo<(outs GPR:$dst1, GPR:$dst2, GPR:$base_wb),
1597 (ins GPR:$base,am3offset:$offset), LdMiscFrm, IIC_iLoad_d_ru,
1598 "ldrd", "\t$dst1, $dst2, [$base], $offset", "$base = $base_wb", []>,
1599 Requires<[IsARM, HasV5TE]>;
1601 } // mayLoad = 1, neverHasSideEffects = 1, hasExtraDefRegAllocReq = 1
1603 // LDRT, LDRBT, LDRSBT, LDRHT, LDRSHT are for disassembly only.
1605 def LDRT : AI2ldstidx<1, 0, 0, (outs GPR:$dst, GPR:$base_wb),
1606 (ins GPR:$base, am2offset:$offset), IndexModeNone,
1607 LdFrm, IIC_iLoad_ru,
1608 "ldrt", "\t$dst, [$base], $offset", "$base = $base_wb", []> {
1609 let Inst{21} = 1; // overwrite
1612 def LDRBT : AI2ldstidx<1, 1, 0, (outs GPR:$dst, GPR:$base_wb),
1613 (ins GPR:$base,am2offset:$offset), IndexModeNone,
1614 LdFrm, IIC_iLoad_bh_ru,
1615 "ldrbt", "\t$dst, [$base], $offset", "$base = $base_wb", []> {
1616 let Inst{21} = 1; // overwrite
1619 def LDRSBT : AI3ldsbpo<(outs GPR:$dst, GPR:$base_wb),
1620 (ins GPR:$base,am3offset:$offset), LdMiscFrm, IIC_iLoad_bh_ru,
1621 "ldrsbt", "\t$dst, [$base], $offset", "$base = $base_wb", []> {
1622 let Inst{21} = 1; // overwrite
1625 def LDRHT : AI3ldhpo<(outs GPR:$dst, GPR:$base_wb),
1626 (ins GPR:$base, am3offset:$offset), LdMiscFrm, IIC_iLoad_bh_ru,
1627 "ldrht", "\t$dst, [$base], $offset", "$base = $base_wb", []> {
1628 let Inst{21} = 1; // overwrite
1631 def LDRSHT : AI3ldshpo<(outs GPR:$dst, GPR:$base_wb),
1632 (ins GPR:$base,am3offset:$offset), LdMiscFrm, IIC_iLoad_bh_ru,
1633 "ldrsht", "\t$dst, [$base], $offset", "$base = $base_wb", []> {
1634 let Inst{21} = 1; // overwrite
1639 // Stores with truncate
1640 def STRH : AI3sth<(outs), (ins GPR:$Rt, addrmode3:$addr), StMiscFrm,
1641 IIC_iStore_bh_r, "strh", "\t$Rt, $addr",
1642 [(truncstorei16 GPR:$Rt, addrmode3:$addr)]>;
1645 let mayStore = 1, neverHasSideEffects = 1, hasExtraSrcRegAllocReq = 1,
1646 isCodeGenOnly = 1 in // $src2 doesn't exist in asm string
1647 def STRD : AI3std<(outs), (ins GPR:$src1, GPR:$src2, addrmode3:$addr),
1648 StMiscFrm, IIC_iStore_d_r,
1649 "strd", "\t$src1, $addr", []>, Requires<[IsARM, HasV5TE]>;
1652 def STR_PRE : AI2ldstidx<0, 0, 1, (outs GPR:$base_wb),
1653 (ins GPR:$src, GPR:$base, am2offset:$offset),
1654 IndexModePre, StFrm, IIC_iStore_ru,
1655 "str", "\t$src, [$base, $offset]!", "$base = $base_wb",
1657 (pre_store GPR:$src, GPR:$base, am2offset:$offset))]>;
1659 def STR_POST : AI2ldstidx<0, 0, 0, (outs GPR:$base_wb),
1660 (ins GPR:$src, GPR:$base,am2offset:$offset),
1661 IndexModePost, StFrm, IIC_iStore_ru,
1662 "str", "\t$src, [$base], $offset", "$base = $base_wb",
1664 (post_store GPR:$src, GPR:$base, am2offset:$offset))]>;
1666 def STRH_PRE : AI3sthpr<(outs GPR:$base_wb),
1667 (ins GPR:$src, GPR:$base,am3offset:$offset),
1668 StMiscFrm, IIC_iStore_ru,
1669 "strh", "\t$src, [$base, $offset]!", "$base = $base_wb",
1671 (pre_truncsti16 GPR:$src, GPR:$base,am3offset:$offset))]>;
1673 def STRH_POST: AI3sthpo<(outs GPR:$base_wb),
1674 (ins GPR:$src, GPR:$base,am3offset:$offset),
1675 StMiscFrm, IIC_iStore_bh_ru,
1676 "strh", "\t$src, [$base], $offset", "$base = $base_wb",
1677 [(set GPR:$base_wb, (post_truncsti16 GPR:$src,
1678 GPR:$base, am3offset:$offset))]>;
1680 def STRB_PRE : AI2ldstidx<0, 1, 1, (outs GPR:$base_wb),
1681 (ins GPR:$src, GPR:$base,am2offset:$offset),
1682 IndexModePre, StFrm, IIC_iStore_bh_ru,
1683 "strb", "\t$src, [$base, $offset]!", "$base = $base_wb",
1684 [(set GPR:$base_wb, (pre_truncsti8 GPR:$src,
1685 GPR:$base, am2offset:$offset))]>;
1687 def STRB_POST: AI2ldstidx<0, 1, 0, (outs GPR:$base_wb),
1688 (ins GPR:$src, GPR:$base,am2offset:$offset),
1689 IndexModePost, StFrm, IIC_iStore_bh_ru,
1690 "strb", "\t$src, [$base], $offset", "$base = $base_wb",
1691 [(set GPR:$base_wb, (post_truncsti8 GPR:$src,
1692 GPR:$base, am2offset:$offset))]>;
1694 // For disassembly only
1695 def STRD_PRE : AI3stdpr<(outs GPR:$base_wb),
1696 (ins GPR:$src1, GPR:$src2, GPR:$base, am3offset:$offset),
1697 StMiscFrm, IIC_iStore_d_ru,
1698 "strd", "\t$src1, $src2, [$base, $offset]!",
1699 "$base = $base_wb", []>;
1701 // For disassembly only
1702 def STRD_POST: AI3stdpo<(outs GPR:$base_wb),
1703 (ins GPR:$src1, GPR:$src2, GPR:$base, am3offset:$offset),
1704 StMiscFrm, IIC_iStore_d_ru,
1705 "strd", "\t$src1, $src2, [$base], $offset",
1706 "$base = $base_wb", []>;
1708 // STRT, STRBT, and STRHT are for disassembly only.
1710 def STRT : AI2ldstidx<0, 0, 0, (outs GPR:$base_wb),
1711 (ins GPR:$src, GPR:$base,am2offset:$offset),
1712 IndexModeNone, StFrm, IIC_iStore_ru,
1713 "strt", "\t$src, [$base], $offset", "$base = $base_wb",
1714 [/* For disassembly only; pattern left blank */]> {
1715 let Inst{21} = 1; // overwrite
1718 def STRBT : AI2ldstidx<0, 1, 0, (outs GPR:$base_wb),
1719 (ins GPR:$src, GPR:$base,am2offset:$offset),
1720 IndexModeNone, StFrm, IIC_iStore_bh_ru,
1721 "strbt", "\t$src, [$base], $offset", "$base = $base_wb",
1722 [/* For disassembly only; pattern left blank */]> {
1723 let Inst{21} = 1; // overwrite
1726 def STRHT: AI3sthpo<(outs GPR:$base_wb),
1727 (ins GPR:$src, GPR:$base,am3offset:$offset),
1728 StMiscFrm, IIC_iStore_bh_ru,
1729 "strht", "\t$src, [$base], $offset", "$base = $base_wb",
1730 [/* For disassembly only; pattern left blank */]> {
1731 let Inst{21} = 1; // overwrite
1734 //===----------------------------------------------------------------------===//
1735 // Load / store multiple Instructions.
1738 multiclass arm_ldst_mult<string asm, bit L_bit, Format f,
1739 InstrItinClass itin, InstrItinClass itin_upd> {
1741 AXI4<(outs), (ins GPR:$Rn, pred:$p, reglist:$regs, variable_ops),
1742 IndexModeNone, f, itin,
1743 !strconcat(asm, "${p}\t$Rn, $regs"), "", []> {
1744 let Inst{24-23} = 0b01; // Increment After
1745 let Inst{21} = 0; // No writeback
1746 let Inst{20} = L_bit;
1749 AXI4<(outs GPR:$wb), (ins GPR:$Rn, pred:$p, reglist:$regs, variable_ops),
1750 IndexModeUpd, f, itin_upd,
1751 !strconcat(asm, "${p}\t$Rn!, $regs"), "$Rn = $wb", []> {
1752 let Inst{24-23} = 0b01; // Increment After
1753 let Inst{21} = 1; // No writeback
1754 let Inst{20} = L_bit;
1757 AXI4<(outs), (ins GPR:$Rn, pred:$p, reglist:$regs, variable_ops),
1758 IndexModeNone, f, itin,
1759 !strconcat(asm, "da${p}\t$Rn, $regs"), "", []> {
1760 let Inst{24-23} = 0b00; // Decrement After
1761 let Inst{21} = 0; // No writeback
1762 let Inst{20} = L_bit;
1765 AXI4<(outs GPR:$wb), (ins GPR:$Rn, pred:$p, reglist:$regs, variable_ops),
1766 IndexModeUpd, f, itin_upd,
1767 !strconcat(asm, "da${p}\t$Rn!, $regs"), "$Rn = $wb", []> {
1768 let Inst{24-23} = 0b00; // Decrement After
1769 let Inst{21} = 1; // No writeback
1770 let Inst{20} = L_bit;
1773 AXI4<(outs), (ins GPR:$Rn, pred:$p, reglist:$regs, variable_ops),
1774 IndexModeNone, f, itin,
1775 !strconcat(asm, "db${p}\t$Rn, $regs"), "", []> {
1776 let Inst{24-23} = 0b10; // Decrement Before
1777 let Inst{21} = 0; // No writeback
1778 let Inst{20} = L_bit;
1781 AXI4<(outs GPR:$wb), (ins GPR:$Rn, pred:$p, reglist:$regs, variable_ops),
1782 IndexModeUpd, f, itin_upd,
1783 !strconcat(asm, "db${p}\t$Rn!, $regs"), "$Rn = $wb", []> {
1784 let Inst{24-23} = 0b10; // Decrement Before
1785 let Inst{21} = 1; // No writeback
1786 let Inst{20} = L_bit;
1789 AXI4<(outs), (ins GPR:$Rn, pred:$p, reglist:$regs, variable_ops),
1790 IndexModeNone, f, itin,
1791 !strconcat(asm, "ib${p}\t$Rn, $regs"), "", []> {
1792 let Inst{24-23} = 0b11; // Increment Before
1793 let Inst{21} = 0; // No writeback
1794 let Inst{20} = L_bit;
1797 AXI4<(outs GPR:$wb), (ins GPR:$Rn, pred:$p, reglist:$regs, variable_ops),
1798 IndexModeUpd, f, itin_upd,
1799 !strconcat(asm, "ib${p}\t$Rn!, $regs"), "$Rn = $wb", []> {
1800 let Inst{24-23} = 0b11; // Increment Before
1801 let Inst{21} = 1; // No writeback
1802 let Inst{20} = L_bit;
1807 let neverHasSideEffects = 1 in {
1809 let mayLoad = 1, hasExtraDefRegAllocReq = 1 in
1810 defm LDM : arm_ldst_mult<"ldm", 1, LdStMulFrm, IIC_iLoad_m, IIC_iLoad_mu>;
1812 let mayStore = 1, hasExtraSrcRegAllocReq = 1 in
1813 defm STM : arm_ldst_mult<"stm", 0, LdStMulFrm, IIC_iStore_m, IIC_iStore_mu>;
1815 } // neverHasSideEffects
1818 let mayLoad = 1, neverHasSideEffects = 1, hasExtraDefRegAllocReq = 1,
1819 isCodeGenOnly = 1 in {
1820 def LDM : AXI4ld<(outs), (ins GPR:$Rn, ldstm_mode:$amode, pred:$p,
1821 reglist:$dsts, variable_ops),
1822 IndexModeNone, LdStMulFrm, IIC_iLoad_m,
1823 "ldm${amode}${p}\t$Rn, $dsts", "", []> {
1827 def LDM_UPD : AXI4ld<(outs GPR:$wb), (ins GPR:$Rn, ldstm_mode:$amode, pred:$p,
1828 reglist:$dsts, variable_ops),
1829 IndexModeUpd, LdStMulFrm, IIC_iLoad_mu,
1830 "ldm${amode}${p}\t$Rn!, $dsts",
1834 } // mayLoad, neverHasSideEffects, hasExtraDefRegAllocReq
1836 let mayStore = 1, neverHasSideEffects = 1, hasExtraSrcRegAllocReq = 1,
1837 isCodeGenOnly = 1 in {
1838 def STM : AXI4st<(outs), (ins GPR:$Rn, ldstm_mode:$amode, pred:$p,
1839 reglist:$srcs, variable_ops),
1840 IndexModeNone, LdStMulFrm, IIC_iStore_m,
1841 "stm${amode}${p}\t$Rn, $srcs", "", []> {
1845 def STM_UPD : AXI4st<(outs GPR:$wb), (ins GPR:$Rn, ldstm_mode:$amode, pred:$p,
1846 reglist:$srcs, variable_ops),
1847 IndexModeUpd, LdStMulFrm, IIC_iStore_mu,
1848 "stm${amode}${p}\t$Rn!, $srcs",
1851 let Inst{31-28} = p;
1854 } // mayStore, neverHasSideEffects, hasExtraSrcRegAllocReq
1856 //===----------------------------------------------------------------------===//
1857 // Move Instructions.
1860 let neverHasSideEffects = 1 in
1861 def MOVr : AsI1<0b1101, (outs GPR:$Rd), (ins GPR:$Rm), DPFrm, IIC_iMOVr,
1862 "mov", "\t$Rd, $Rm", []>, UnaryDP {
1866 let Inst{11-4} = 0b00000000;
1869 let Inst{15-12} = Rd;
1872 // A version for the smaller set of tail call registers.
1873 let neverHasSideEffects = 1 in
1874 def MOVr_TC : AsI1<0b1101, (outs tcGPR:$Rd), (ins tcGPR:$Rm), DPFrm,
1875 IIC_iMOVr, "mov", "\t$Rd, $Rm", []>, UnaryDP {
1879 let Inst{11-4} = 0b00000000;
1882 let Inst{15-12} = Rd;
1885 def MOVs : AsI1<0b1101, (outs GPR:$Rd), (ins shift_so_reg:$src),
1886 DPSoRegFrm, IIC_iMOVsr,
1887 "mov", "\t$Rd, $src", [(set GPR:$Rd, shift_so_reg:$src)]>,
1891 let Inst{15-12} = Rd;
1892 let Inst{11-0} = src;
1896 let isReMaterializable = 1, isAsCheapAsAMove = 1 in
1897 def MOVi : AsI1<0b1101, (outs GPR:$Rd), (ins so_imm:$imm), DPFrm, IIC_iMOVi,
1898 "mov", "\t$Rd, $imm", [(set GPR:$Rd, so_imm:$imm)]>, UnaryDP {
1902 let Inst{15-12} = Rd;
1903 let Inst{19-16} = 0b0000;
1904 let Inst{11-0} = imm;
1907 let isReMaterializable = 1, isAsCheapAsAMove = 1 in
1908 def MOVi16 : AI1<0b1000, (outs GPR:$Rd), (ins i32imm:$imm),
1910 "movw", "\t$Rd, $imm",
1911 [(set GPR:$Rd, imm0_65535:$imm)]>,
1912 Requires<[IsARM, HasV6T2]>, UnaryDP {
1915 let Inst{15-12} = Rd;
1916 let Inst{11-0} = imm{11-0};
1917 let Inst{19-16} = imm{15-12};
1922 let Constraints = "$src = $Rd" in
1923 def MOVTi16 : AI1<0b1010, (outs GPR:$Rd), (ins GPR:$src, i32imm:$imm),
1925 "movt", "\t$Rd, $imm",
1927 (or (and GPR:$src, 0xffff),
1928 lo16AllZero:$imm))]>, UnaryDP,
1929 Requires<[IsARM, HasV6T2]> {
1932 let Inst{15-12} = Rd;
1933 let Inst{11-0} = imm{11-0};
1934 let Inst{19-16} = imm{15-12};
1939 def : ARMPat<(or GPR:$src, 0xffff0000), (MOVTi16 GPR:$src, 0xffff)>,
1940 Requires<[IsARM, HasV6T2]>;
1942 let Uses = [CPSR] in
1943 def RRX: PseudoInst<(outs GPR:$Rd), (ins GPR:$Rm), IIC_iMOVsi, "",
1944 [(set GPR:$Rd, (ARMrrx GPR:$Rm))]>, UnaryDP,
1947 // These aren't really mov instructions, but we have to define them this way
1948 // due to flag operands.
1950 let Defs = [CPSR] in {
1951 def MOVsrl_flag : PseudoInst<(outs GPR:$dst), (ins GPR:$src), IIC_iMOVsi, "",
1952 [(set GPR:$dst, (ARMsrl_flag GPR:$src))]>, UnaryDP,
1954 def MOVsra_flag : PseudoInst<(outs GPR:$dst), (ins GPR:$src), IIC_iMOVsi, "",
1955 [(set GPR:$dst, (ARMsra_flag GPR:$src))]>, UnaryDP,
1959 //===----------------------------------------------------------------------===//
1960 // Extend Instructions.
1965 defm SXTB : AI_ext_rrot<0b01101010,
1966 "sxtb", UnOpFrag<(sext_inreg node:$Src, i8)>>;
1967 defm SXTH : AI_ext_rrot<0b01101011,
1968 "sxth", UnOpFrag<(sext_inreg node:$Src, i16)>>;
1970 defm SXTAB : AI_exta_rrot<0b01101010,
1971 "sxtab", BinOpFrag<(add node:$LHS, (sext_inreg node:$RHS, i8))>>;
1972 defm SXTAH : AI_exta_rrot<0b01101011,
1973 "sxtah", BinOpFrag<(add node:$LHS, (sext_inreg node:$RHS,i16))>>;
1975 // For disassembly only
1976 defm SXTB16 : AI_ext_rrot_np<0b01101000, "sxtb16">;
1978 // For disassembly only
1979 defm SXTAB16 : AI_exta_rrot_np<0b01101000, "sxtab16">;
1983 let AddedComplexity = 16 in {
1984 defm UXTB : AI_ext_rrot<0b01101110,
1985 "uxtb" , UnOpFrag<(and node:$Src, 0x000000FF)>>;
1986 defm UXTH : AI_ext_rrot<0b01101111,
1987 "uxth" , UnOpFrag<(and node:$Src, 0x0000FFFF)>>;
1988 defm UXTB16 : AI_ext_rrot<0b01101100,
1989 "uxtb16", UnOpFrag<(and node:$Src, 0x00FF00FF)>>;
1991 // FIXME: This pattern incorrectly assumes the shl operator is a rotate.
1992 // The transformation should probably be done as a combiner action
1993 // instead so we can include a check for masking back in the upper
1994 // eight bits of the source into the lower eight bits of the result.
1995 //def : ARMV6Pat<(and (shl GPR:$Src, (i32 8)), 0xFF00FF),
1996 // (UXTB16r_rot GPR:$Src, 24)>;
1997 def : ARMV6Pat<(and (srl GPR:$Src, (i32 8)), 0xFF00FF),
1998 (UXTB16r_rot GPR:$Src, 8)>;
2000 defm UXTAB : AI_exta_rrot<0b01101110, "uxtab",
2001 BinOpFrag<(add node:$LHS, (and node:$RHS, 0x00FF))>>;
2002 defm UXTAH : AI_exta_rrot<0b01101111, "uxtah",
2003 BinOpFrag<(add node:$LHS, (and node:$RHS, 0xFFFF))>>;
2006 // This isn't safe in general, the add is two 16-bit units, not a 32-bit add.
2007 // For disassembly only
2008 defm UXTAB16 : AI_exta_rrot_np<0b01101100, "uxtab16">;
2011 def SBFX : I<(outs GPR:$Rd),
2012 (ins GPR:$Rn, imm0_31:$lsb, imm0_31_m1:$width),
2013 AddrMode1, Size4Bytes, IndexModeNone, DPFrm, IIC_iUNAsi,
2014 "sbfx", "\t$Rd, $Rn, $lsb, $width", "", []>,
2015 Requires<[IsARM, HasV6T2]> {
2020 let Inst{27-21} = 0b0111101;
2021 let Inst{6-4} = 0b101;
2022 let Inst{20-16} = width;
2023 let Inst{15-12} = Rd;
2024 let Inst{11-7} = lsb;
2028 def UBFX : I<(outs GPR:$Rd),
2029 (ins GPR:$Rn, imm0_31:$lsb, imm0_31_m1:$width),
2030 AddrMode1, Size4Bytes, IndexModeNone, DPFrm, IIC_iUNAsi,
2031 "ubfx", "\t$Rd, $Rn, $lsb, $width", "", []>,
2032 Requires<[IsARM, HasV6T2]> {
2037 let Inst{27-21} = 0b0111111;
2038 let Inst{6-4} = 0b101;
2039 let Inst{20-16} = width;
2040 let Inst{15-12} = Rd;
2041 let Inst{11-7} = lsb;
2045 //===----------------------------------------------------------------------===//
2046 // Arithmetic Instructions.
2049 defm ADD : AsI1_bin_irs<0b0100, "add",
2050 IIC_iALUi, IIC_iALUr, IIC_iALUsr,
2051 BinOpFrag<(add node:$LHS, node:$RHS)>, 1>;
2052 defm SUB : AsI1_bin_irs<0b0010, "sub",
2053 IIC_iALUi, IIC_iALUr, IIC_iALUsr,
2054 BinOpFrag<(sub node:$LHS, node:$RHS)>>;
2056 // ADD and SUB with 's' bit set.
2057 defm ADDS : AI1_bin_s_irs<0b0100, "adds",
2058 IIC_iALUi, IIC_iALUr, IIC_iALUsr,
2059 BinOpFrag<(addc node:$LHS, node:$RHS)>, 1>;
2060 defm SUBS : AI1_bin_s_irs<0b0010, "subs",
2061 IIC_iALUi, IIC_iALUr, IIC_iALUsr,
2062 BinOpFrag<(subc node:$LHS, node:$RHS)>>;
2064 defm ADC : AI1_adde_sube_irs<0b0101, "adc",
2065 BinOpFrag<(adde_dead_carry node:$LHS, node:$RHS)>, 1>;
2066 defm SBC : AI1_adde_sube_irs<0b0110, "sbc",
2067 BinOpFrag<(sube_dead_carry node:$LHS, node:$RHS)>>;
2068 defm ADCS : AI1_adde_sube_s_irs<0b0101, "adcs",
2069 BinOpFrag<(adde_live_carry node:$LHS, node:$RHS)>, 1>;
2070 defm SBCS : AI1_adde_sube_s_irs<0b0110, "sbcs",
2071 BinOpFrag<(sube_live_carry node:$LHS, node:$RHS) >>;
2073 def RSBri : AsI1<0b0011, (outs GPR:$Rd), (ins GPR:$Rn, so_imm:$imm), DPFrm,
2074 IIC_iALUi, "rsb", "\t$Rd, $Rn, $imm",
2075 [(set GPR:$Rd, (sub so_imm:$imm, GPR:$Rn))]> {
2080 let Inst{15-12} = Rd;
2081 let Inst{19-16} = Rn;
2082 let Inst{11-0} = imm;
2085 // The reg/reg form is only defined for the disassembler; for codegen it is
2086 // equivalent to SUBrr.
2087 def RSBrr : AsI1<0b0011, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm), DPFrm,
2088 IIC_iALUr, "rsb", "\t$Rd, $Rn, $Rm",
2089 [/* For disassembly only; pattern left blank */]> {
2093 let Inst{11-4} = 0b00000000;
2096 let Inst{15-12} = Rd;
2097 let Inst{19-16} = Rn;
2100 def RSBrs : AsI1<0b0011, (outs GPR:$Rd), (ins GPR:$Rn, so_reg:$shift),
2101 DPSoRegFrm, IIC_iALUsr, "rsb", "\t$Rd, $Rn, $shift",
2102 [(set GPR:$Rd, (sub so_reg:$shift, GPR:$Rn))]> {
2107 let Inst{11-0} = shift;
2108 let Inst{15-12} = Rd;
2109 let Inst{19-16} = Rn;
2112 // RSB with 's' bit set.
2113 let Defs = [CPSR] in {
2114 def RSBSri : AI1<0b0011, (outs GPR:$Rd), (ins GPR:$Rn, so_imm:$imm), DPFrm,
2115 IIC_iALUi, "rsbs", "\t$Rd, $Rn, $imm",
2116 [(set GPR:$Rd, (subc so_imm:$imm, GPR:$Rn))]> {
2122 let Inst{15-12} = Rd;
2123 let Inst{19-16} = Rn;
2124 let Inst{11-0} = imm;
2126 def RSBSrs : AI1<0b0011, (outs GPR:$Rd), (ins GPR:$Rn, so_reg:$shift),
2127 DPSoRegFrm, IIC_iALUsr, "rsbs", "\t$Rd, $Rn, $shift",
2128 [(set GPR:$Rd, (subc so_reg:$shift, GPR:$Rn))]> {
2134 let Inst{11-0} = shift;
2135 let Inst{15-12} = Rd;
2136 let Inst{19-16} = Rn;
2140 let Uses = [CPSR] in {
2141 def RSCri : AsI1<0b0111, (outs GPR:$Rd), (ins GPR:$Rn, so_imm:$imm),
2142 DPFrm, IIC_iALUi, "rsc", "\t$Rd, $Rn, $imm",
2143 [(set GPR:$Rd, (sube_dead_carry so_imm:$imm, GPR:$Rn))]>,
2149 let Inst{15-12} = Rd;
2150 let Inst{19-16} = Rn;
2151 let Inst{11-0} = imm;
2153 // The reg/reg form is only defined for the disassembler; for codegen it is
2154 // equivalent to SUBrr.
2155 def RSCrr : AsI1<0b0111, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm),
2156 DPFrm, IIC_iALUr, "rsc", "\t$Rd, $Rn, $Rm",
2157 [/* For disassembly only; pattern left blank */]> {
2161 let Inst{11-4} = 0b00000000;
2164 let Inst{15-12} = Rd;
2165 let Inst{19-16} = Rn;
2167 def RSCrs : AsI1<0b0111, (outs GPR:$Rd), (ins GPR:$Rn, so_reg:$shift),
2168 DPSoRegFrm, IIC_iALUsr, "rsc", "\t$Rd, $Rn, $shift",
2169 [(set GPR:$Rd, (sube_dead_carry so_reg:$shift, GPR:$Rn))]>,
2175 let Inst{11-0} = shift;
2176 let Inst{15-12} = Rd;
2177 let Inst{19-16} = Rn;
2181 // FIXME: Allow these to be predicated.
2182 let Defs = [CPSR], Uses = [CPSR] in {
2183 def RSCSri : AXI1<0b0111, (outs GPR:$Rd), (ins GPR:$Rn, so_imm:$imm),
2184 DPFrm, IIC_iALUi, "rscs\t$Rd, $Rn, $imm",
2185 [(set GPR:$Rd, (sube_dead_carry so_imm:$imm, GPR:$Rn))]>,
2192 let Inst{15-12} = Rd;
2193 let Inst{19-16} = Rn;
2194 let Inst{11-0} = imm;
2196 def RSCSrs : AXI1<0b0111, (outs GPR:$Rd), (ins GPR:$Rn, so_reg:$shift),
2197 DPSoRegFrm, IIC_iALUsr, "rscs\t$Rd, $Rn, $shift",
2198 [(set GPR:$Rd, (sube_dead_carry so_reg:$shift, GPR:$Rn))]>,
2205 let Inst{11-0} = shift;
2206 let Inst{15-12} = Rd;
2207 let Inst{19-16} = Rn;
2211 // (sub X, imm) gets canonicalized to (add X, -imm). Match this form.
2212 // The assume-no-carry-in form uses the negation of the input since add/sub
2213 // assume opposite meanings of the carry flag (i.e., carry == !borrow).
2214 // See the definition of AddWithCarry() in the ARM ARM A2.2.1 for the gory
2216 def : ARMPat<(add GPR:$src, so_imm_neg:$imm),
2217 (SUBri GPR:$src, so_imm_neg:$imm)>;
2218 def : ARMPat<(addc GPR:$src, so_imm_neg:$imm),
2219 (SUBSri GPR:$src, so_imm_neg:$imm)>;
2220 // The with-carry-in form matches bitwise not instead of the negation.
2221 // Effectively, the inverse interpretation of the carry flag already accounts
2222 // for part of the negation.
2223 def : ARMPat<(adde GPR:$src, so_imm_not:$imm),
2224 (SBCri GPR:$src, so_imm_not:$imm)>;
2226 // Note: These are implemented in C++ code, because they have to generate
2227 // ADD/SUBrs instructions, which use a complex pattern that a xform function
2229 // (mul X, 2^n+1) -> (add (X << n), X)
2230 // (mul X, 2^n-1) -> (rsb X, (X << n))
2232 // ARM Arithmetic Instruction -- for disassembly only
2233 // GPR:$dst = GPR:$a op GPR:$b
2234 class AAI<bits<8> op27_20, bits<8> op11_4, string opc,
2235 list<dag> pattern = [/* For disassembly only; pattern left blank */]>
2236 : AI<(outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm), DPFrm, IIC_iALUr,
2237 opc, "\t$Rd, $Rn, $Rm", pattern> {
2241 let Inst{27-20} = op27_20;
2242 let Inst{11-4} = op11_4;
2243 let Inst{19-16} = Rn;
2244 let Inst{15-12} = Rd;
2248 // Saturating add/subtract -- for disassembly only
2250 def QADD : AAI<0b00010000, 0b00000101, "qadd",
2251 [(set GPR:$Rd, (int_arm_qadd GPR:$Rn, GPR:$Rm))]>;
2252 def QSUB : AAI<0b00010010, 0b00000101, "qsub",
2253 [(set GPR:$Rd, (int_arm_qsub GPR:$Rn, GPR:$Rm))]>;
2254 def QDADD : AAI<0b00010100, 0b00000101, "qdadd">;
2255 def QDSUB : AAI<0b00010110, 0b00000101, "qdsub">;
2257 def QADD16 : AAI<0b01100010, 0b11110001, "qadd16">;
2258 def QADD8 : AAI<0b01100010, 0b11111001, "qadd8">;
2259 def QASX : AAI<0b01100010, 0b11110011, "qasx">;
2260 def QSAX : AAI<0b01100010, 0b11110101, "qsax">;
2261 def QSUB16 : AAI<0b01100010, 0b11110111, "qsub16">;
2262 def QSUB8 : AAI<0b01100010, 0b11111111, "qsub8">;
2263 def UQADD16 : AAI<0b01100110, 0b11110001, "uqadd16">;
2264 def UQADD8 : AAI<0b01100110, 0b11111001, "uqadd8">;
2265 def UQASX : AAI<0b01100110, 0b11110011, "uqasx">;
2266 def UQSAX : AAI<0b01100110, 0b11110101, "uqsax">;
2267 def UQSUB16 : AAI<0b01100110, 0b11110111, "uqsub16">;
2268 def UQSUB8 : AAI<0b01100110, 0b11111111, "uqsub8">;
2270 // Signed/Unsigned add/subtract -- for disassembly only
2272 def SASX : AAI<0b01100001, 0b11110011, "sasx">;
2273 def SADD16 : AAI<0b01100001, 0b11110001, "sadd16">;
2274 def SADD8 : AAI<0b01100001, 0b11111001, "sadd8">;
2275 def SSAX : AAI<0b01100001, 0b11110101, "ssax">;
2276 def SSUB16 : AAI<0b01100001, 0b11110111, "ssub16">;
2277 def SSUB8 : AAI<0b01100001, 0b11111111, "ssub8">;
2278 def UASX : AAI<0b01100101, 0b11110011, "uasx">;
2279 def UADD16 : AAI<0b01100101, 0b11110001, "uadd16">;
2280 def UADD8 : AAI<0b01100101, 0b11111001, "uadd8">;
2281 def USAX : AAI<0b01100101, 0b11110101, "usax">;
2282 def USUB16 : AAI<0b01100101, 0b11110111, "usub16">;
2283 def USUB8 : AAI<0b01100101, 0b11111111, "usub8">;
2285 // Signed/Unsigned halving add/subtract -- for disassembly only
2287 def SHASX : AAI<0b01100011, 0b11110011, "shasx">;
2288 def SHADD16 : AAI<0b01100011, 0b11110001, "shadd16">;
2289 def SHADD8 : AAI<0b01100011, 0b11111001, "shadd8">;
2290 def SHSAX : AAI<0b01100011, 0b11110101, "shsax">;
2291 def SHSUB16 : AAI<0b01100011, 0b11110111, "shsub16">;
2292 def SHSUB8 : AAI<0b01100011, 0b11111111, "shsub8">;
2293 def UHASX : AAI<0b01100111, 0b11110011, "uhasx">;
2294 def UHADD16 : AAI<0b01100111, 0b11110001, "uhadd16">;
2295 def UHADD8 : AAI<0b01100111, 0b11111001, "uhadd8">;
2296 def UHSAX : AAI<0b01100111, 0b11110101, "uhsax">;
2297 def UHSUB16 : AAI<0b01100111, 0b11110111, "uhsub16">;
2298 def UHSUB8 : AAI<0b01100111, 0b11111111, "uhsub8">;
2300 // Unsigned Sum of Absolute Differences [and Accumulate] -- for disassembly only
2302 def USAD8 : AI<(outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm),
2303 MulFrm /* for convenience */, NoItinerary, "usad8",
2304 "\t$Rd, $Rn, $Rm", []>,
2305 Requires<[IsARM, HasV6]> {
2309 let Inst{27-20} = 0b01111000;
2310 let Inst{15-12} = 0b1111;
2311 let Inst{7-4} = 0b0001;
2312 let Inst{19-16} = Rd;
2313 let Inst{11-8} = Rm;
2316 def USADA8 : AI<(outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm, GPR:$Ra),
2317 MulFrm /* for convenience */, NoItinerary, "usada8",
2318 "\t$Rd, $Rn, $Rm, $Ra", []>,
2319 Requires<[IsARM, HasV6]> {
2324 let Inst{27-20} = 0b01111000;
2325 let Inst{7-4} = 0b0001;
2326 let Inst{19-16} = Rd;
2327 let Inst{15-12} = Ra;
2328 let Inst{11-8} = Rm;
2332 // Signed/Unsigned saturate -- for disassembly only
2334 def SSAT : AI<(outs GPR:$Rd), (ins i32imm:$sat_imm, GPR:$a, shift_imm:$sh),
2335 SatFrm, NoItinerary, "ssat", "\t$Rd, $sat_imm, $a$sh",
2336 [/* For disassembly only; pattern left blank */]> {
2341 let Inst{27-21} = 0b0110101;
2342 let Inst{5-4} = 0b01;
2343 let Inst{20-16} = sat_imm;
2344 let Inst{15-12} = Rd;
2345 let Inst{11-7} = sh{7-3};
2346 let Inst{6} = sh{0};
2350 def SSAT16 : AI<(outs GPR:$Rd), (ins i32imm:$sat_imm, GPR:$Rn), SatFrm,
2351 NoItinerary, "ssat16", "\t$Rd, $sat_imm, $Rn",
2352 [/* For disassembly only; pattern left blank */]> {
2356 let Inst{27-20} = 0b01101010;
2357 let Inst{11-4} = 0b11110011;
2358 let Inst{15-12} = Rd;
2359 let Inst{19-16} = sat_imm;
2363 def USAT : AI<(outs GPR:$Rd), (ins i32imm:$sat_imm, GPR:$a, shift_imm:$sh),
2364 SatFrm, NoItinerary, "usat", "\t$Rd, $sat_imm, $a$sh",
2365 [/* For disassembly only; pattern left blank */]> {
2370 let Inst{27-21} = 0b0110111;
2371 let Inst{5-4} = 0b01;
2372 let Inst{15-12} = Rd;
2373 let Inst{11-7} = sh{7-3};
2374 let Inst{6} = sh{0};
2375 let Inst{20-16} = sat_imm;
2379 def USAT16 : AI<(outs GPR:$Rd), (ins i32imm:$sat_imm, GPR:$a), SatFrm,
2380 NoItinerary, "usat16", "\t$Rd, $sat_imm, $a",
2381 [/* For disassembly only; pattern left blank */]> {
2385 let Inst{27-20} = 0b01101110;
2386 let Inst{11-4} = 0b11110011;
2387 let Inst{15-12} = Rd;
2388 let Inst{19-16} = sat_imm;
2392 def : ARMV6Pat<(int_arm_ssat GPR:$a, imm:$pos), (SSAT imm:$pos, GPR:$a, 0)>;
2393 def : ARMV6Pat<(int_arm_usat GPR:$a, imm:$pos), (USAT imm:$pos, GPR:$a, 0)>;
2395 //===----------------------------------------------------------------------===//
2396 // Bitwise Instructions.
2399 defm AND : AsI1_bin_irs<0b0000, "and",
2400 IIC_iBITi, IIC_iBITr, IIC_iBITsr,
2401 BinOpFrag<(and node:$LHS, node:$RHS)>, 1>;
2402 defm ORR : AsI1_bin_irs<0b1100, "orr",
2403 IIC_iBITi, IIC_iBITr, IIC_iBITsr,
2404 BinOpFrag<(or node:$LHS, node:$RHS)>, 1>;
2405 defm EOR : AsI1_bin_irs<0b0001, "eor",
2406 IIC_iBITi, IIC_iBITr, IIC_iBITsr,
2407 BinOpFrag<(xor node:$LHS, node:$RHS)>, 1>;
2408 defm BIC : AsI1_bin_irs<0b1110, "bic",
2409 IIC_iBITi, IIC_iBITr, IIC_iBITsr,
2410 BinOpFrag<(and node:$LHS, (not node:$RHS))>>;
2412 def BFC : I<(outs GPR:$Rd), (ins GPR:$src, bf_inv_mask_imm:$imm),
2413 AddrMode1, Size4Bytes, IndexModeNone, DPFrm, IIC_iUNAsi,
2414 "bfc", "\t$Rd, $imm", "$src = $Rd",
2415 [(set GPR:$Rd, (and GPR:$src, bf_inv_mask_imm:$imm))]>,
2416 Requires<[IsARM, HasV6T2]> {
2419 let Inst{27-21} = 0b0111110;
2420 let Inst{6-0} = 0b0011111;
2421 let Inst{15-12} = Rd;
2422 let Inst{11-7} = imm{4-0}; // lsb
2423 let Inst{20-16} = imm{9-5}; // width
2426 // A8.6.18 BFI - Bitfield insert (Encoding A1)
2427 def BFI : I<(outs GPR:$Rd), (ins GPR:$src, GPR:$Rn, bf_inv_mask_imm:$imm),
2428 AddrMode1, Size4Bytes, IndexModeNone, DPFrm, IIC_iUNAsi,
2429 "bfi", "\t$Rd, $Rn, $imm", "$src = $Rd",
2430 [(set GPR:$Rd, (ARMbfi GPR:$src, GPR:$Rn,
2431 bf_inv_mask_imm:$imm))]>,
2432 Requires<[IsARM, HasV6T2]> {
2436 let Inst{27-21} = 0b0111110;
2437 let Inst{6-4} = 0b001; // Rn: Inst{3-0} != 15
2438 let Inst{15-12} = Rd;
2439 let Inst{11-7} = imm{4-0}; // lsb
2440 let Inst{20-16} = imm{9-5}; // width
2444 def MVNr : AsI1<0b1111, (outs GPR:$Rd), (ins GPR:$Rm), DPFrm, IIC_iMVNr,
2445 "mvn", "\t$Rd, $Rm",
2446 [(set GPR:$Rd, (not GPR:$Rm))]>, UnaryDP {
2450 let Inst{19-16} = 0b0000;
2451 let Inst{11-4} = 0b00000000;
2452 let Inst{15-12} = Rd;
2455 def MVNs : AsI1<0b1111, (outs GPR:$Rd), (ins so_reg:$shift), DPSoRegFrm,
2456 IIC_iMVNsr, "mvn", "\t$Rd, $shift",
2457 [(set GPR:$Rd, (not so_reg:$shift))]>, UnaryDP {
2461 let Inst{19-16} = 0b0000;
2462 let Inst{15-12} = Rd;
2463 let Inst{11-0} = shift;
2465 let isReMaterializable = 1, isAsCheapAsAMove = 1 in
2466 def MVNi : AsI1<0b1111, (outs GPR:$Rd), (ins so_imm:$imm), DPFrm,
2467 IIC_iMVNi, "mvn", "\t$Rd, $imm",
2468 [(set GPR:$Rd, so_imm_not:$imm)]>,UnaryDP {
2472 let Inst{19-16} = 0b0000;
2473 let Inst{15-12} = Rd;
2474 let Inst{11-0} = imm;
2477 def : ARMPat<(and GPR:$src, so_imm_not:$imm),
2478 (BICri GPR:$src, so_imm_not:$imm)>;
2480 //===----------------------------------------------------------------------===//
2481 // Multiply Instructions.
2483 class AsMul1I32<bits<7> opcod, dag oops, dag iops, InstrItinClass itin,
2484 string opc, string asm, list<dag> pattern>
2485 : AsMul1I<opcod, oops, iops, itin, opc, asm, pattern> {
2489 let Inst{19-16} = Rd;
2490 let Inst{11-8} = Rm;
2493 class AsMul1I64<bits<7> opcod, dag oops, dag iops, InstrItinClass itin,
2494 string opc, string asm, list<dag> pattern>
2495 : AsMul1I<opcod, oops, iops, itin, opc, asm, pattern> {
2500 let Inst{19-16} = RdHi;
2501 let Inst{15-12} = RdLo;
2502 let Inst{11-8} = Rm;
2506 let isCommutable = 1 in
2507 def MUL : AsMul1I32<0b0000000, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm),
2508 IIC_iMUL32, "mul", "\t$Rd, $Rn, $Rm",
2509 [(set GPR:$Rd, (mul GPR:$Rn, GPR:$Rm))]>;
2511 def MLA : AsMul1I32<0b0000001, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm, GPR:$Ra),
2512 IIC_iMAC32, "mla", "\t$Rd, $Rn, $Rm, $Ra",
2513 [(set GPR:$Rd, (add (mul GPR:$Rn, GPR:$Rm), GPR:$Ra))]> {
2515 let Inst{15-12} = Ra;
2518 def MLS : AMul1I<0b0000011, (outs GPR:$dst), (ins GPR:$a, GPR:$b, GPR:$c),
2519 IIC_iMAC32, "mls", "\t$dst, $a, $b, $c",
2520 [(set GPR:$dst, (sub GPR:$c, (mul GPR:$a, GPR:$b)))]>,
2521 Requires<[IsARM, HasV6T2]> {
2525 let Inst{19-16} = Rd;
2526 let Inst{11-8} = Rm;
2530 // Extra precision multiplies with low / high results
2532 let neverHasSideEffects = 1 in {
2533 let isCommutable = 1 in {
2534 def SMULL : AsMul1I64<0b0000110, (outs GPR:$RdLo, GPR:$RdHi),
2535 (ins GPR:$Rn, GPR:$Rm), IIC_iMUL64,
2536 "smull", "\t$RdLo, $RdHi, $Rn, $Rm", []>;
2538 def UMULL : AsMul1I64<0b0000100, (outs GPR:$RdLo, GPR:$RdHi),
2539 (ins GPR:$Rn, GPR:$Rm), IIC_iMUL64,
2540 "umull", "\t$RdLo, $RdHi, $Rn, $Rm", []>;
2543 // Multiply + accumulate
2544 def SMLAL : AsMul1I64<0b0000111, (outs GPR:$RdLo, GPR:$RdHi),
2545 (ins GPR:$Rn, GPR:$Rm), IIC_iMAC64,
2546 "smlal", "\t$RdLo, $RdHi, $Rn, $Rm", []>;
2548 def UMLAL : AsMul1I64<0b0000101, (outs GPR:$RdLo, GPR:$RdHi),
2549 (ins GPR:$Rn, GPR:$Rm), IIC_iMAC64,
2550 "umlal", "\t$RdLo, $RdHi, $Rn, $Rm", []>;
2552 def UMAAL : AMul1I <0b0000010, (outs GPR:$RdLo, GPR:$RdHi),
2553 (ins GPR:$Rn, GPR:$Rm), IIC_iMAC64,
2554 "umaal", "\t$RdLo, $RdHi, $Rn, $Rm", []>,
2555 Requires<[IsARM, HasV6]> {
2560 let Inst{19-16} = RdLo;
2561 let Inst{15-12} = RdHi;
2562 let Inst{11-8} = Rm;
2565 } // neverHasSideEffects
2567 // Most significant word multiply
2568 def SMMUL : AMul2I <0b0111010, 0b0001, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm),
2569 IIC_iMUL32, "smmul", "\t$Rd, $Rn, $Rm",
2570 [(set GPR:$Rd, (mulhs GPR:$Rn, GPR:$Rm))]>,
2571 Requires<[IsARM, HasV6]> {
2572 let Inst{15-12} = 0b1111;
2575 def SMMULR : AMul2I <0b0111010, 0b0011, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm),
2576 IIC_iMUL32, "smmulr", "\t$Rd, $Rn, $Rm",
2577 [/* For disassembly only; pattern left blank */]>,
2578 Requires<[IsARM, HasV6]> {
2579 let Inst{15-12} = 0b1111;
2582 def SMMLA : AMul2Ia <0b0111010, 0b0001, (outs GPR:$Rd),
2583 (ins GPR:$Rn, GPR:$Rm, GPR:$Ra),
2584 IIC_iMAC32, "smmla", "\t$Rd, $Rn, $Rm, $Ra",
2585 [(set GPR:$Rd, (add (mulhs GPR:$Rn, GPR:$Rm), GPR:$Ra))]>,
2586 Requires<[IsARM, HasV6]>;
2588 def SMMLAR : AMul2Ia <0b0111010, 0b0011, (outs GPR:$Rd),
2589 (ins GPR:$Rn, GPR:$Rm, GPR:$Ra),
2590 IIC_iMAC32, "smmlar", "\t$Rd, $Rn, $Rm, $Ra",
2591 [/* For disassembly only; pattern left blank */]>,
2592 Requires<[IsARM, HasV6]>;
2594 def SMMLS : AMul2Ia <0b0111010, 0b1101, (outs GPR:$Rd),
2595 (ins GPR:$Rn, GPR:$Rm, GPR:$Ra),
2596 IIC_iMAC32, "smmls", "\t$Rd, $Rn, $Rm, $Ra",
2597 [(set GPR:$Rd, (sub GPR:$Ra, (mulhs GPR:$Rn, GPR:$Rm)))]>,
2598 Requires<[IsARM, HasV6]>;
2600 def SMMLSR : AMul2Ia <0b0111010, 0b1111, (outs GPR:$Rd),
2601 (ins GPR:$Rn, GPR:$Rm, GPR:$Ra),
2602 IIC_iMAC32, "smmlsr", "\t$Rd, $Rn, $Rm, $Ra",
2603 [/* For disassembly only; pattern left blank */]>,
2604 Requires<[IsARM, HasV6]>;
2606 multiclass AI_smul<string opc, PatFrag opnode> {
2607 def BB : AMulxyI<0b0001011, 0b00, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm),
2608 IIC_iMUL16, !strconcat(opc, "bb"), "\t$Rd, $Rn, $Rm",
2609 [(set GPR:$Rd, (opnode (sext_inreg GPR:$Rn, i16),
2610 (sext_inreg GPR:$Rm, i16)))]>,
2611 Requires<[IsARM, HasV5TE]>;
2613 def BT : AMulxyI<0b0001011, 0b10, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm),
2614 IIC_iMUL16, !strconcat(opc, "bt"), "\t$Rd, $Rn, $Rm",
2615 [(set GPR:$Rd, (opnode (sext_inreg GPR:$Rn, i16),
2616 (sra GPR:$Rm, (i32 16))))]>,
2617 Requires<[IsARM, HasV5TE]>;
2619 def TB : AMulxyI<0b0001011, 0b01, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm),
2620 IIC_iMUL16, !strconcat(opc, "tb"), "\t$Rd, $Rn, $Rm",
2621 [(set GPR:$Rd, (opnode (sra GPR:$Rn, (i32 16)),
2622 (sext_inreg GPR:$Rm, i16)))]>,
2623 Requires<[IsARM, HasV5TE]>;
2625 def TT : AMulxyI<0b0001011, 0b11, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm),
2626 IIC_iMUL16, !strconcat(opc, "tt"), "\t$Rd, $Rn, $Rm",
2627 [(set GPR:$Rd, (opnode (sra GPR:$Rn, (i32 16)),
2628 (sra GPR:$Rm, (i32 16))))]>,
2629 Requires<[IsARM, HasV5TE]>;
2631 def WB : AMulxyI<0b0001001, 0b01, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm),
2632 IIC_iMUL16, !strconcat(opc, "wb"), "\t$Rd, $Rn, $Rm",
2633 [(set GPR:$Rd, (sra (opnode GPR:$Rn,
2634 (sext_inreg GPR:$Rm, i16)), (i32 16)))]>,
2635 Requires<[IsARM, HasV5TE]>;
2637 def WT : AMulxyI<0b0001001, 0b11, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm),
2638 IIC_iMUL16, !strconcat(opc, "wt"), "\t$Rd, $Rn, $Rm",
2639 [(set GPR:$Rd, (sra (opnode GPR:$Rn,
2640 (sra GPR:$Rm, (i32 16))), (i32 16)))]>,
2641 Requires<[IsARM, HasV5TE]>;
2645 multiclass AI_smla<string opc, PatFrag opnode> {
2646 def BB : AMulxyIa<0b0001000, 0b00, (outs GPR:$Rd),
2647 (ins GPR:$Rn, GPR:$Rm, GPR:$Ra),
2648 IIC_iMAC16, !strconcat(opc, "bb"), "\t$Rd, $Rn, $Rm, $Ra",
2649 [(set GPR:$Rd, (add GPR:$Ra,
2650 (opnode (sext_inreg GPR:$Rn, i16),
2651 (sext_inreg GPR:$Rm, i16))))]>,
2652 Requires<[IsARM, HasV5TE]>;
2654 def BT : AMulxyIa<0b0001000, 0b10, (outs GPR:$Rd),
2655 (ins GPR:$Rn, GPR:$Rm, GPR:$Ra),
2656 IIC_iMAC16, !strconcat(opc, "bt"), "\t$Rd, $Rn, $Rm, $Ra",
2657 [(set GPR:$Rd, (add GPR:$Ra, (opnode (sext_inreg GPR:$Rn, i16),
2658 (sra GPR:$Rm, (i32 16)))))]>,
2659 Requires<[IsARM, HasV5TE]>;
2661 def TB : AMulxyIa<0b0001000, 0b01, (outs GPR:$Rd),
2662 (ins GPR:$Rn, GPR:$Rm, GPR:$Ra),
2663 IIC_iMAC16, !strconcat(opc, "tb"), "\t$Rd, $Rn, $Rm, $Ra",
2664 [(set GPR:$Rd, (add GPR:$Ra, (opnode (sra GPR:$Rn, (i32 16)),
2665 (sext_inreg GPR:$Rm, i16))))]>,
2666 Requires<[IsARM, HasV5TE]>;
2668 def TT : AMulxyIa<0b0001000, 0b11, (outs GPR:$Rd),
2669 (ins GPR:$Rn, GPR:$Rm, GPR:$Ra),
2670 IIC_iMAC16, !strconcat(opc, "tt"), "\t$Rd, $Rn, $Rm, $Ra",
2671 [(set GPR:$Rd, (add GPR:$Ra, (opnode (sra GPR:$Rn, (i32 16)),
2672 (sra GPR:$Rm, (i32 16)))))]>,
2673 Requires<[IsARM, HasV5TE]>;
2675 def WB : AMulxyIa<0b0001001, 0b00, (outs GPR:$Rd),
2676 (ins GPR:$Rn, GPR:$Rm, GPR:$Ra),
2677 IIC_iMAC16, !strconcat(opc, "wb"), "\t$Rd, $Rn, $Rm, $Ra",
2678 [(set GPR:$Rd, (add GPR:$Ra, (sra (opnode GPR:$Rn,
2679 (sext_inreg GPR:$Rm, i16)), (i32 16))))]>,
2680 Requires<[IsARM, HasV5TE]>;
2682 def WT : AMulxyIa<0b0001001, 0b10, (outs GPR:$Rd),
2683 (ins GPR:$Rn, GPR:$Rm, GPR:$Ra),
2684 IIC_iMAC16, !strconcat(opc, "wt"), "\t$Rd, $Rn, $Rm, $Ra",
2685 [(set GPR:$Rd, (add GPR:$Ra, (sra (opnode GPR:$Rn,
2686 (sra GPR:$Rm, (i32 16))), (i32 16))))]>,
2687 Requires<[IsARM, HasV5TE]>;
2690 defm SMUL : AI_smul<"smul", BinOpFrag<(mul node:$LHS, node:$RHS)>>;
2691 defm SMLA : AI_smla<"smla", BinOpFrag<(mul node:$LHS, node:$RHS)>>;
2693 // Halfword multiply accumulate long: SMLAL<x><y> -- for disassembly only
2694 def SMLALBB : AMulxyI64<0b0001010, 0b00, (outs GPR:$RdLo, GPR:$RdHi),
2695 (ins GPR:$Rn, GPR:$Rm),
2696 IIC_iMAC64, "smlalbb", "\t$RdLo, $RdHi, $Rn, $Rm",
2697 [/* For disassembly only; pattern left blank */]>,
2698 Requires<[IsARM, HasV5TE]>;
2700 def SMLALBT : AMulxyI64<0b0001010, 0b10, (outs GPR:$RdLo, GPR:$RdHi),
2701 (ins GPR:$Rn, GPR:$Rm),
2702 IIC_iMAC64, "smlalbt", "\t$RdLo, $RdHi, $Rn, $Rm",
2703 [/* For disassembly only; pattern left blank */]>,
2704 Requires<[IsARM, HasV5TE]>;
2706 def SMLALTB : AMulxyI64<0b0001010, 0b01, (outs GPR:$RdLo, GPR:$RdHi),
2707 (ins GPR:$Rn, GPR:$Rm),
2708 IIC_iMAC64, "smlaltb", "\t$RdLo, $RdHi, $Rn, $Rm",
2709 [/* For disassembly only; pattern left blank */]>,
2710 Requires<[IsARM, HasV5TE]>;
2712 def SMLALTT : AMulxyI64<0b0001010, 0b11, (outs GPR:$RdLo, GPR:$RdHi),
2713 (ins GPR:$Rn, GPR:$Rm),
2714 IIC_iMAC64, "smlaltt", "\t$RdLo, $RdHi, $Rn, $Rm",
2715 [/* For disassembly only; pattern left blank */]>,
2716 Requires<[IsARM, HasV5TE]>;
2718 // Helper class for AI_smld -- for disassembly only
2719 class AMulDualIbase<bit long, bit sub, bit swap, dag oops, dag iops,
2720 InstrItinClass itin, string opc, string asm>
2721 : AI<oops, iops, MulFrm, itin, opc, asm, []>, Requires<[IsARM, HasV6]> {
2728 let Inst{21-20} = 0b00;
2729 let Inst{22} = long;
2730 let Inst{27-23} = 0b01110;
2731 let Inst{11-8} = Rm;
2734 class AMulDualI<bit long, bit sub, bit swap, dag oops, dag iops,
2735 InstrItinClass itin, string opc, string asm>
2736 : AMulDualIbase<long, sub, swap, oops, iops, itin, opc, asm> {
2738 let Inst{15-12} = 0b1111;
2739 let Inst{19-16} = Rd;
2741 class AMulDualIa<bit long, bit sub, bit swap, dag oops, dag iops,
2742 InstrItinClass itin, string opc, string asm>
2743 : AMulDualIbase<long, sub, swap, oops, iops, itin, opc, asm> {
2745 let Inst{15-12} = Ra;
2747 class AMulDualI64<bit long, bit sub, bit swap, dag oops, dag iops,
2748 InstrItinClass itin, string opc, string asm>
2749 : AMulDualIbase<long, sub, swap, oops, iops, itin, opc, asm> {
2752 let Inst{19-16} = RdHi;
2753 let Inst{15-12} = RdLo;
2756 multiclass AI_smld<bit sub, string opc> {
2758 def D : AMulDualIa<0, sub, 0, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm, GPR:$Ra),
2759 NoItinerary, !strconcat(opc, "d"), "\t$Rd, $Rn, $Rm, $Ra">;
2761 def DX: AMulDualIa<0, sub, 1, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm, GPR:$Ra),
2762 NoItinerary, !strconcat(opc, "dx"), "\t$Rd, $Rn, $Rm, $Ra">;
2764 def LD: AMulDualI64<1, sub, 0, (outs GPR:$RdLo,GPR:$RdHi),
2765 (ins GPR:$Rn, GPR:$Rm), NoItinerary,
2766 !strconcat(opc, "ld"), "\t$RdLo, $RdHi, $Rn, $Rm">;
2768 def LDX : AMulDualI64<1, sub, 1, (outs GPR:$RdLo,GPR:$RdHi),
2769 (ins GPR:$Rn, GPR:$Rm), NoItinerary,
2770 !strconcat(opc, "ldx"),"\t$RdLo, $RdHi, $Rn, $Rm">;
2774 defm SMLA : AI_smld<0, "smla">;
2775 defm SMLS : AI_smld<1, "smls">;
2777 multiclass AI_sdml<bit sub, string opc> {
2779 def D : AMulDualI<0, sub, 0, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm),
2780 NoItinerary, !strconcat(opc, "d"), "\t$Rd, $Rn, $Rm">;
2781 def DX : AMulDualI<0, sub, 1, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm),
2782 NoItinerary, !strconcat(opc, "dx"), "\t$Rd, $Rn, $Rm">;
2785 defm SMUA : AI_sdml<0, "smua">;
2786 defm SMUS : AI_sdml<1, "smus">;
2788 //===----------------------------------------------------------------------===//
2789 // Misc. Arithmetic Instructions.
2792 def CLZ : AMiscA1I<0b000010110, 0b0001, (outs GPR:$Rd), (ins GPR:$Rm),
2793 IIC_iUNAr, "clz", "\t$Rd, $Rm",
2794 [(set GPR:$Rd, (ctlz GPR:$Rm))]>, Requires<[IsARM, HasV5T]>;
2796 def RBIT : AMiscA1I<0b01101111, 0b0011, (outs GPR:$Rd), (ins GPR:$Rm),
2797 IIC_iUNAr, "rbit", "\t$Rd, $Rm",
2798 [(set GPR:$Rd, (ARMrbit GPR:$Rm))]>,
2799 Requires<[IsARM, HasV6T2]>;
2801 def REV : AMiscA1I<0b01101011, 0b0011, (outs GPR:$Rd), (ins GPR:$Rm),
2802 IIC_iUNAr, "rev", "\t$Rd, $Rm",
2803 [(set GPR:$Rd, (bswap GPR:$Rm))]>, Requires<[IsARM, HasV6]>;
2805 def REV16 : AMiscA1I<0b01101011, 0b1011, (outs GPR:$Rd), (ins GPR:$Rm),
2806 IIC_iUNAr, "rev16", "\t$Rd, $Rm",
2808 (or (and (srl GPR:$Rm, (i32 8)), 0xFF),
2809 (or (and (shl GPR:$Rm, (i32 8)), 0xFF00),
2810 (or (and (srl GPR:$Rm, (i32 8)), 0xFF0000),
2811 (and (shl GPR:$Rm, (i32 8)), 0xFF000000)))))]>,
2812 Requires<[IsARM, HasV6]>;
2814 def REVSH : AMiscA1I<0b01101111, 0b1011, (outs GPR:$Rd), (ins GPR:$Rm),
2815 IIC_iUNAr, "revsh", "\t$Rd, $Rm",
2818 (or (srl (and GPR:$Rm, 0xFF00), (i32 8)),
2819 (shl GPR:$Rm, (i32 8))), i16))]>,
2820 Requires<[IsARM, HasV6]>;
2822 def lsl_shift_imm : SDNodeXForm<imm, [{
2823 unsigned Sh = ARM_AM::getSORegOpc(ARM_AM::lsl, N->getZExtValue());
2824 return CurDAG->getTargetConstant(Sh, MVT::i32);
2827 def lsl_amt : PatLeaf<(i32 imm), [{
2828 return (N->getZExtValue() < 32);
2831 def PKHBT : APKHI<0b01101000, 0, (outs GPR:$Rd),
2832 (ins GPR:$Rn, GPR:$Rm, shift_imm:$sh),
2833 IIC_iALUsi, "pkhbt", "\t$Rd, $Rn, $Rm$sh",
2834 [(set GPR:$Rd, (or (and GPR:$Rn, 0xFFFF),
2835 (and (shl GPR:$Rm, lsl_amt:$sh),
2837 Requires<[IsARM, HasV6]>;
2839 // Alternate cases for PKHBT where identities eliminate some nodes.
2840 def : ARMV6Pat<(or (and GPR:$Rn, 0xFFFF), (and GPR:$Rm, 0xFFFF0000)),
2841 (PKHBT GPR:$Rn, GPR:$Rm, 0)>;
2842 def : ARMV6Pat<(or (and GPR:$Rn, 0xFFFF), (shl GPR:$Rm, imm16_31:$sh)),
2843 (PKHBT GPR:$Rn, GPR:$Rm, (lsl_shift_imm imm16_31:$sh))>;
2845 def asr_shift_imm : SDNodeXForm<imm, [{
2846 unsigned Sh = ARM_AM::getSORegOpc(ARM_AM::asr, N->getZExtValue());
2847 return CurDAG->getTargetConstant(Sh, MVT::i32);
2850 def asr_amt : PatLeaf<(i32 imm), [{
2851 return (N->getZExtValue() <= 32);
2854 // Note: Shifts of 1-15 bits will be transformed to srl instead of sra and
2855 // will match the pattern below.
2856 def PKHTB : APKHI<0b01101000, 1, (outs GPR:$Rd),
2857 (ins GPR:$Rn, GPR:$Rm, shift_imm:$sh),
2858 IIC_iBITsi, "pkhtb", "\t$Rd, $Rn, $Rm$sh",
2859 [(set GPR:$Rd, (or (and GPR:$Rn, 0xFFFF0000),
2860 (and (sra GPR:$Rm, asr_amt:$sh),
2862 Requires<[IsARM, HasV6]>;
2864 // Alternate cases for PKHTB where identities eliminate some nodes. Note that
2865 // a shift amount of 0 is *not legal* here, it is PKHBT instead.
2866 def : ARMV6Pat<(or (and GPR:$src1, 0xFFFF0000), (srl GPR:$src2, imm16_31:$sh)),
2867 (PKHTB GPR:$src1, GPR:$src2, (asr_shift_imm imm16_31:$sh))>;
2868 def : ARMV6Pat<(or (and GPR:$src1, 0xFFFF0000),
2869 (and (srl GPR:$src2, imm1_15:$sh), 0xFFFF)),
2870 (PKHTB GPR:$src1, GPR:$src2, (asr_shift_imm imm1_15:$sh))>;
2872 //===----------------------------------------------------------------------===//
2873 // Comparison Instructions...
2876 defm CMP : AI1_cmp_irs<0b1010, "cmp",
2877 IIC_iCMPi, IIC_iCMPr, IIC_iCMPsr,
2878 BinOpFrag<(ARMcmp node:$LHS, node:$RHS)>>;
2880 // FIXME: We have to be careful when using the CMN instruction and comparison
2881 // with 0. One would expect these two pieces of code should give identical
2897 // However, the CMN gives the *opposite* result when r1 is 0. This is because
2898 // the carry flag is set in the CMP case but not in the CMN case. In short, the
2899 // CMP instruction doesn't perform a truncate of the (logical) NOT of 0 plus the
2900 // value of r0 and the carry bit (because the "carry bit" parameter to
2901 // AddWithCarry is defined as 1 in this case, the carry flag will always be set
2902 // when r0 >= 0). The CMN instruction doesn't perform a NOT of 0 so there is
2903 // never a "carry" when this AddWithCarry is performed (because the "carry bit"
2904 // parameter to AddWithCarry is defined as 0).
2906 // When x is 0 and unsigned:
2910 // ~x + 1 = 0x1 0000 0000
2911 // (-x = 0) != (0x1 0000 0000 = ~x + 1)
2913 // Therefore, we should disable CMN when comparing against zero, until we can
2914 // limit when the CMN instruction is used (when we know that the RHS is not 0 or
2915 // when it's a comparison which doesn't look at the 'carry' flag).
2917 // (See the ARM docs for the "AddWithCarry" pseudo-code.)
2919 // This is related to <rdar://problem/7569620>.
2921 //defm CMN : AI1_cmp_irs<0b1011, "cmn",
2922 // BinOpFrag<(ARMcmp node:$LHS,(ineg node:$RHS))>>;
2924 // Note that TST/TEQ don't set all the same flags that CMP does!
2925 defm TST : AI1_cmp_irs<0b1000, "tst",
2926 IIC_iTSTi, IIC_iTSTr, IIC_iTSTsr,
2927 BinOpFrag<(ARMcmpZ (and node:$LHS, node:$RHS), 0)>, 1>;
2928 defm TEQ : AI1_cmp_irs<0b1001, "teq",
2929 IIC_iTSTi, IIC_iTSTr, IIC_iTSTsr,
2930 BinOpFrag<(ARMcmpZ (xor node:$LHS, node:$RHS), 0)>, 1>;
2932 defm CMPz : AI1_cmp_irs<0b1010, "cmp",
2933 IIC_iCMPi, IIC_iCMPr, IIC_iCMPsr,
2934 BinOpFrag<(ARMcmpZ node:$LHS, node:$RHS)>>;
2935 defm CMNz : AI1_cmp_irs<0b1011, "cmn",
2936 IIC_iCMPi, IIC_iCMPr, IIC_iCMPsr,
2937 BinOpFrag<(ARMcmpZ node:$LHS,(ineg node:$RHS))>>;
2939 //def : ARMPat<(ARMcmp GPR:$src, so_imm_neg:$imm),
2940 // (CMNri GPR:$src, so_imm_neg:$imm)>;
2942 def : ARMPat<(ARMcmpZ GPR:$src, so_imm_neg:$imm),
2943 (CMNzri GPR:$src, so_imm_neg:$imm)>;
2945 // Pseudo i64 compares for some floating point compares.
2946 let usesCustomInserter = 1, isBranch = 1, isTerminator = 1,
2948 def BCCi64 : PseudoInst<(outs),
2949 (ins i32imm:$cc, GPR:$lhs1, GPR:$lhs2, GPR:$rhs1, GPR:$rhs2, brtarget:$dst),
2951 [(ARMBcci64 imm:$cc, GPR:$lhs1, GPR:$lhs2, GPR:$rhs1, GPR:$rhs2, bb:$dst)]>;
2953 def BCCZi64 : PseudoInst<(outs),
2954 (ins i32imm:$cc, GPR:$lhs1, GPR:$lhs2, brtarget:$dst), IIC_Br, "",
2955 [(ARMBcci64 imm:$cc, GPR:$lhs1, GPR:$lhs2, 0, 0, bb:$dst)]>;
2956 } // usesCustomInserter
2959 // Conditional moves
2960 // FIXME: should be able to write a pattern for ARMcmov, but can't use
2961 // a two-value operand where a dag node expects two operands. :(
2962 // FIXME: These should all be pseudo-instructions that get expanded to
2963 // the normal MOV instructions. That would fix the dependency on
2964 // special casing them in tblgen.
2965 let neverHasSideEffects = 1 in {
2966 def MOVCCr : AI1<0b1101, (outs GPR:$Rd), (ins GPR:$false, GPR:$Rm), DPFrm,
2967 IIC_iCMOVr, "mov", "\t$Rd, $Rm",
2968 [/*(set GPR:$Rd, (ARMcmov GPR:$false, GPR:$Rm, imm:$cc, CCR:$ccr))*/]>,
2969 RegConstraint<"$false = $Rd">, UnaryDP {
2974 let Inst{15-12} = Rd;
2975 let Inst{11-4} = 0b00000000;
2979 def MOVCCs : AI1<0b1101, (outs GPR:$Rd),
2980 (ins GPR:$false, so_reg:$shift), DPSoRegFrm, IIC_iCMOVsr,
2981 "mov", "\t$Rd, $shift",
2982 [/*(set GPR:$Rd, (ARMcmov GPR:$false, so_reg:$shift, imm:$cc, CCR:$ccr))*/]>,
2983 RegConstraint<"$false = $Rd">, UnaryDP {
2989 let Inst{19-16} = Rn;
2990 let Inst{15-12} = Rd;
2991 let Inst{11-0} = shift;
2994 def MOVCCi16 : AI1<0b1000, (outs GPR:$Rd), (ins GPR:$false, i32imm:$imm),
2996 "movw", "\t$Rd, $imm",
2998 RegConstraint<"$false = $Rd">, Requires<[IsARM, HasV6T2]>,
3004 let Inst{19-16} = imm{15-12};
3005 let Inst{15-12} = Rd;
3006 let Inst{11-0} = imm{11-0};
3009 def MOVCCi : AI1<0b1101, (outs GPR:$Rd),
3010 (ins GPR:$false, so_imm:$imm), DPFrm, IIC_iCMOVi,
3011 "mov", "\t$Rd, $imm",
3012 [/*(set GPR:$Rd, (ARMcmov GPR:$false, so_imm:$imm, imm:$cc, CCR:$ccr))*/]>,
3013 RegConstraint<"$false = $Rd">, UnaryDP {
3018 let Inst{19-16} = 0b0000;
3019 let Inst{15-12} = Rd;
3020 let Inst{11-0} = imm;
3023 // Two instruction predicate mov immediate.
3024 def MOVCCi32imm : PseudoInst<(outs GPR:$Rd),
3025 (ins GPR:$false, i32imm:$src, pred:$p),
3026 IIC_iCMOVix2, "", []>, RegConstraint<"$false = $Rd">;
3028 def MVNCCi : AI1<0b1111, (outs GPR:$Rd),
3029 (ins GPR:$false, so_imm:$imm), DPFrm, IIC_iCMOVi,
3030 "mvn", "\t$Rd, $imm",
3031 [/*(set GPR:$Rd, (ARMcmov GPR:$false, so_imm_not:$imm, imm:$cc, CCR:$ccr))*/]>,
3032 RegConstraint<"$false = $Rd">, UnaryDP {
3037 let Inst{19-16} = 0b0000;
3038 let Inst{15-12} = Rd;
3039 let Inst{11-0} = imm;
3041 } // neverHasSideEffects
3043 //===----------------------------------------------------------------------===//
3044 // Atomic operations intrinsics
3047 def memb_opt : Operand<i32> {
3048 let PrintMethod = "printMemBOption";
3051 // memory barriers protect the atomic sequences
3052 let hasSideEffects = 1 in {
3053 def DMB : AInoP<(outs), (ins memb_opt:$opt), MiscFrm, NoItinerary,
3054 "dmb", "\t$opt", [(ARMMemBarrier (i32 imm:$opt))]>,
3055 Requires<[IsARM, HasDB]> {
3057 let Inst{31-4} = 0xf57ff05;
3058 let Inst{3-0} = opt;
3061 def DMB_MCR : AInoP<(outs), (ins GPR:$zero), MiscFrm, NoItinerary,
3062 "mcr", "\tp15, 0, $zero, c7, c10, 5",
3063 [(ARMMemBarrierMCR GPR:$zero)]>,
3064 Requires<[IsARM, HasV6]> {
3065 // FIXME: add encoding
3069 def DSB : AInoP<(outs), (ins memb_opt:$opt), MiscFrm, NoItinerary,
3071 [/* For disassembly only; pattern left blank */]>,
3072 Requires<[IsARM, HasDB]> {
3074 let Inst{31-4} = 0xf57ff04;
3075 let Inst{3-0} = opt;
3078 // ISB has only full system option -- for disassembly only
3079 def ISB : AInoP<(outs), (ins), MiscFrm, NoItinerary, "isb", "", []>,
3080 Requires<[IsARM, HasDB]> {
3081 let Inst{31-4} = 0xf57ff06;
3082 let Inst{3-0} = 0b1111;
3085 let usesCustomInserter = 1 in {
3086 let Uses = [CPSR] in {
3087 def ATOMIC_LOAD_ADD_I8 : PseudoInst<
3088 (outs GPR:$dst), (ins GPR:$ptr, GPR:$incr), NoItinerary, "",
3089 [(set GPR:$dst, (atomic_load_add_8 GPR:$ptr, GPR:$incr))]>;
3090 def ATOMIC_LOAD_SUB_I8 : PseudoInst<
3091 (outs GPR:$dst), (ins GPR:$ptr, GPR:$incr), NoItinerary, "",
3092 [(set GPR:$dst, (atomic_load_sub_8 GPR:$ptr, GPR:$incr))]>;
3093 def ATOMIC_LOAD_AND_I8 : PseudoInst<
3094 (outs GPR:$dst), (ins GPR:$ptr, GPR:$incr), NoItinerary, "",
3095 [(set GPR:$dst, (atomic_load_and_8 GPR:$ptr, GPR:$incr))]>;
3096 def ATOMIC_LOAD_OR_I8 : PseudoInst<
3097 (outs GPR:$dst), (ins GPR:$ptr, GPR:$incr), NoItinerary, "",
3098 [(set GPR:$dst, (atomic_load_or_8 GPR:$ptr, GPR:$incr))]>;
3099 def ATOMIC_LOAD_XOR_I8 : PseudoInst<
3100 (outs GPR:$dst), (ins GPR:$ptr, GPR:$incr), NoItinerary, "",
3101 [(set GPR:$dst, (atomic_load_xor_8 GPR:$ptr, GPR:$incr))]>;
3102 def ATOMIC_LOAD_NAND_I8 : PseudoInst<
3103 (outs GPR:$dst), (ins GPR:$ptr, GPR:$incr), NoItinerary, "",
3104 [(set GPR:$dst, (atomic_load_nand_8 GPR:$ptr, GPR:$incr))]>;
3105 def ATOMIC_LOAD_ADD_I16 : PseudoInst<
3106 (outs GPR:$dst), (ins GPR:$ptr, GPR:$incr), NoItinerary, "",
3107 [(set GPR:$dst, (atomic_load_add_16 GPR:$ptr, GPR:$incr))]>;
3108 def ATOMIC_LOAD_SUB_I16 : PseudoInst<
3109 (outs GPR:$dst), (ins GPR:$ptr, GPR:$incr), NoItinerary, "",
3110 [(set GPR:$dst, (atomic_load_sub_16 GPR:$ptr, GPR:$incr))]>;
3111 def ATOMIC_LOAD_AND_I16 : PseudoInst<
3112 (outs GPR:$dst), (ins GPR:$ptr, GPR:$incr), NoItinerary, "",
3113 [(set GPR:$dst, (atomic_load_and_16 GPR:$ptr, GPR:$incr))]>;
3114 def ATOMIC_LOAD_OR_I16 : PseudoInst<
3115 (outs GPR:$dst), (ins GPR:$ptr, GPR:$incr), NoItinerary, "",
3116 [(set GPR:$dst, (atomic_load_or_16 GPR:$ptr, GPR:$incr))]>;
3117 def ATOMIC_LOAD_XOR_I16 : PseudoInst<
3118 (outs GPR:$dst), (ins GPR:$ptr, GPR:$incr), NoItinerary, "",
3119 [(set GPR:$dst, (atomic_load_xor_16 GPR:$ptr, GPR:$incr))]>;
3120 def ATOMIC_LOAD_NAND_I16 : PseudoInst<
3121 (outs GPR:$dst), (ins GPR:$ptr, GPR:$incr), NoItinerary, "",
3122 [(set GPR:$dst, (atomic_load_nand_16 GPR:$ptr, GPR:$incr))]>;
3123 def ATOMIC_LOAD_ADD_I32 : PseudoInst<
3124 (outs GPR:$dst), (ins GPR:$ptr, GPR:$incr), NoItinerary, "",
3125 [(set GPR:$dst, (atomic_load_add_32 GPR:$ptr, GPR:$incr))]>;
3126 def ATOMIC_LOAD_SUB_I32 : PseudoInst<
3127 (outs GPR:$dst), (ins GPR:$ptr, GPR:$incr), NoItinerary, "",
3128 [(set GPR:$dst, (atomic_load_sub_32 GPR:$ptr, GPR:$incr))]>;
3129 def ATOMIC_LOAD_AND_I32 : PseudoInst<
3130 (outs GPR:$dst), (ins GPR:$ptr, GPR:$incr), NoItinerary, "",
3131 [(set GPR:$dst, (atomic_load_and_32 GPR:$ptr, GPR:$incr))]>;
3132 def ATOMIC_LOAD_OR_I32 : PseudoInst<
3133 (outs GPR:$dst), (ins GPR:$ptr, GPR:$incr), NoItinerary, "",
3134 [(set GPR:$dst, (atomic_load_or_32 GPR:$ptr, GPR:$incr))]>;
3135 def ATOMIC_LOAD_XOR_I32 : PseudoInst<
3136 (outs GPR:$dst), (ins GPR:$ptr, GPR:$incr), NoItinerary, "",
3137 [(set GPR:$dst, (atomic_load_xor_32 GPR:$ptr, GPR:$incr))]>;
3138 def ATOMIC_LOAD_NAND_I32 : PseudoInst<
3139 (outs GPR:$dst), (ins GPR:$ptr, GPR:$incr), NoItinerary, "",
3140 [(set GPR:$dst, (atomic_load_nand_32 GPR:$ptr, GPR:$incr))]>;
3142 def ATOMIC_SWAP_I8 : PseudoInst<
3143 (outs GPR:$dst), (ins GPR:$ptr, GPR:$new), NoItinerary, "",
3144 [(set GPR:$dst, (atomic_swap_8 GPR:$ptr, GPR:$new))]>;
3145 def ATOMIC_SWAP_I16 : PseudoInst<
3146 (outs GPR:$dst), (ins GPR:$ptr, GPR:$new), NoItinerary, "",
3147 [(set GPR:$dst, (atomic_swap_16 GPR:$ptr, GPR:$new))]>;
3148 def ATOMIC_SWAP_I32 : PseudoInst<
3149 (outs GPR:$dst), (ins GPR:$ptr, GPR:$new), NoItinerary, "",
3150 [(set GPR:$dst, (atomic_swap_32 GPR:$ptr, GPR:$new))]>;
3152 def ATOMIC_CMP_SWAP_I8 : PseudoInst<
3153 (outs GPR:$dst), (ins GPR:$ptr, GPR:$old, GPR:$new), NoItinerary, "",
3154 [(set GPR:$dst, (atomic_cmp_swap_8 GPR:$ptr, GPR:$old, GPR:$new))]>;
3155 def ATOMIC_CMP_SWAP_I16 : PseudoInst<
3156 (outs GPR:$dst), (ins GPR:$ptr, GPR:$old, GPR:$new), NoItinerary, "",
3157 [(set GPR:$dst, (atomic_cmp_swap_16 GPR:$ptr, GPR:$old, GPR:$new))]>;
3158 def ATOMIC_CMP_SWAP_I32 : PseudoInst<
3159 (outs GPR:$dst), (ins GPR:$ptr, GPR:$old, GPR:$new), NoItinerary, "",
3160 [(set GPR:$dst, (atomic_cmp_swap_32 GPR:$ptr, GPR:$old, GPR:$new))]>;
3164 let mayLoad = 1 in {
3165 def LDREXB : AIldrex<0b10, (outs GPR:$Rt), (ins GPR:$Rn), NoItinerary,
3166 "ldrexb", "\t$Rt, [$Rn]",
3168 def LDREXH : AIldrex<0b11, (outs GPR:$Rt), (ins GPR:$Rn), NoItinerary,
3169 "ldrexh", "\t$Rt, [$Rn]",
3171 def LDREX : AIldrex<0b00, (outs GPR:$Rt), (ins GPR:$Rn), NoItinerary,
3172 "ldrex", "\t$Rt, [$Rn]",
3174 def LDREXD : AIldrex<0b01, (outs GPR:$Rt, GPR:$Rt2), (ins GPR:$Rn),
3176 "ldrexd", "\t$Rt, $Rt2, [$Rn]",
3180 let mayStore = 1, Constraints = "@earlyclobber $Rd" in {
3181 def STREXB : AIstrex<0b10, (outs GPR:$Rd), (ins GPR:$src, GPR:$Rn),
3183 "strexb", "\t$Rd, $src, [$Rn]",
3185 def STREXH : AIstrex<0b11, (outs GPR:$Rd), (ins GPR:$Rt, GPR:$Rn),
3187 "strexh", "\t$Rd, $Rt, [$Rn]",
3189 def STREX : AIstrex<0b00, (outs GPR:$Rd), (ins GPR:$Rt, GPR:$Rn),
3191 "strex", "\t$Rd, $Rt, [$Rn]",
3193 def STREXD : AIstrex<0b01, (outs GPR:$Rd),
3194 (ins GPR:$Rt, GPR:$Rt2, GPR:$Rn),
3196 "strexd", "\t$Rd, $Rt, $Rt2, [$Rn]",
3200 // Clear-Exclusive is for disassembly only.
3201 def CLREX : AXI<(outs), (ins), MiscFrm, NoItinerary, "clrex",
3202 [/* For disassembly only; pattern left blank */]>,
3203 Requires<[IsARM, HasV7]> {
3204 let Inst{31-0} = 0b11110101011111111111000000011111;
3207 // SWP/SWPB are deprecated in V6/V7 and for disassembly only.
3208 let mayLoad = 1 in {
3209 def SWP : AIswp<0, (outs GPR:$Rt), (ins GPR:$Rt2, GPR:$Rn), "swp",
3210 [/* For disassembly only; pattern left blank */]>;
3211 def SWPB : AIswp<1, (outs GPR:$Rt), (ins GPR:$Rt2, GPR:$Rn), "swpb",
3212 [/* For disassembly only; pattern left blank */]>;
3215 //===----------------------------------------------------------------------===//
3219 // __aeabi_read_tp preserves the registers r1-r3.
3220 // FIXME: This needs to be a pseudo of some sort so that we can get the
3221 // encoding right, complete with fixup for the aeabi_read_tp function.
3223 Defs = [R0, R12, LR, CPSR] in {
3224 def TPsoft : ABXI<0b1011, (outs), (ins), IIC_Br,
3225 "bl\t__aeabi_read_tp",
3226 [(set R0, ARMthread_pointer)]>;
3229 //===----------------------------------------------------------------------===//
3230 // SJLJ Exception handling intrinsics
3231 // eh_sjlj_setjmp() is an instruction sequence to store the return
3232 // address and save #0 in R0 for the non-longjmp case.
3233 // Since by its nature we may be coming from some other function to get
3234 // here, and we're using the stack frame for the containing function to
3235 // save/restore registers, we can't keep anything live in regs across
3236 // the eh_sjlj_setjmp(), else it will almost certainly have been tromped upon
3237 // when we get here from a longjmp(). We force everthing out of registers
3238 // except for our own input by listing the relevant registers in Defs. By
3239 // doing so, we also cause the prologue/epilogue code to actively preserve
3240 // all of the callee-saved resgisters, which is exactly what we want.
3241 // A constant value is passed in $val, and we use the location as a scratch.
3243 // These are pseudo-instructions and are lowered to individual MC-insts, so
3244 // no encoding information is necessary.
3246 [ R0, R1, R2, R3, R4, R5, R6, R7, R8, R9, R10, R11, R12, LR, D0,
3247 D1, D2, D3, D4, D5, D6, D7, D8, D9, D10, D11, D12, D13, D14, D15,
3248 D16, D17, D18, D19, D20, D21, D22, D23, D24, D25, D26, D27, D28, D29, D30,
3249 D31 ], hasSideEffects = 1, isBarrier = 1 in {
3250 def Int_eh_sjlj_setjmp : XI<(outs), (ins GPR:$src, GPR:$val),
3251 AddrModeNone, SizeSpecial, IndexModeNone,
3252 Pseudo, NoItinerary, "", "",
3253 [(set R0, (ARMeh_sjlj_setjmp GPR:$src, GPR:$val))]>,
3254 Requires<[IsARM, HasVFP2]>;
3258 [ R0, R1, R2, R3, R4, R5, R6, R7, R8, R9, R10, R11, R12, LR ],
3259 hasSideEffects = 1, isBarrier = 1 in {
3260 def Int_eh_sjlj_setjmp_nofp : XI<(outs), (ins GPR:$src, GPR:$val),
3261 AddrModeNone, SizeSpecial, IndexModeNone,
3262 Pseudo, NoItinerary, "", "",
3263 [(set R0, (ARMeh_sjlj_setjmp GPR:$src, GPR:$val))]>,
3264 Requires<[IsARM, NoVFP]>;
3267 // FIXME: Non-Darwin version(s)
3268 let isBarrier = 1, hasSideEffects = 1, isTerminator = 1,
3269 Defs = [ R7, LR, SP ] in {
3270 def Int_eh_sjlj_longjmp : XI<(outs), (ins GPR:$src, GPR:$scratch),
3271 AddrModeNone, SizeSpecial, IndexModeNone,
3272 Pseudo, NoItinerary, "", "",
3273 [(ARMeh_sjlj_longjmp GPR:$src, GPR:$scratch)]>,
3274 Requires<[IsARM, IsDarwin]>;
3277 // eh.sjlj.dispatchsetup pseudo-instruction.
3278 // This pseudo is used for ARM, Thumb1 and Thumb2. Any differences are
3279 // handled when the pseudo is expanded (which happens before any passes
3280 // that need the instruction size).
3281 let isBarrier = 1, hasSideEffects = 1 in
3282 def Int_eh_sjlj_dispatchsetup :
3283 PseudoInst<(outs), (ins GPR:$src), NoItinerary, "",
3284 [(ARMeh_sjlj_dispatchsetup GPR:$src)]>,
3285 Requires<[IsDarwin]>;
3287 //===----------------------------------------------------------------------===//
3288 // Non-Instruction Patterns
3291 // Large immediate handling.
3293 // FIXME: Folding immediates into these logical operations aren't necessary
3294 // good ideas. If it's in a loop machine licm could have hoisted the immediate
3295 // computation out of the loop.
3296 def : ARMPat<(or GPR:$LHS, so_imm2part:$RHS),
3297 (ORRri (ORRri GPR:$LHS, (so_imm2part_1 imm:$RHS)),
3298 (so_imm2part_2 imm:$RHS))>;
3299 def : ARMPat<(xor GPR:$LHS, so_imm2part:$RHS),
3300 (EORri (EORri GPR:$LHS, (so_imm2part_1 imm:$RHS)),
3301 (so_imm2part_2 imm:$RHS))>;
3302 def : ARMPat<(add GPR:$LHS, so_imm2part:$RHS),
3303 (ADDri (ADDri GPR:$LHS, (so_imm2part_1 imm:$RHS)),
3304 (so_imm2part_2 imm:$RHS))>;
3305 def : ARMPat<(add GPR:$LHS, so_neg_imm2part:$RHS),
3306 (SUBri (SUBri GPR:$LHS, (so_neg_imm2part_1 imm:$RHS)),
3307 (so_neg_imm2part_2 imm:$RHS))>;
3309 // 32-bit immediate using two piece so_imms or movw + movt.
3310 // This is a single pseudo instruction, the benefit is that it can be remat'd
3311 // as a single unit instead of having to handle reg inputs.
3312 // FIXME: Remove this when we can do generalized remat.
3313 let isReMaterializable = 1 in
3314 def MOVi32imm : PseudoInst<(outs GPR:$dst), (ins i32imm:$src), IIC_iMOVix2, "",
3315 [(set GPR:$dst, (arm_i32imm:$src))]>,
3318 // ConstantPool, GlobalAddress, and JumpTable
3319 def : ARMPat<(ARMWrapper tglobaladdr :$dst), (LEApcrel tglobaladdr :$dst)>,
3320 Requires<[IsARM, DontUseMovt]>;
3321 def : ARMPat<(ARMWrapper tconstpool :$dst), (LEApcrel tconstpool :$dst)>;
3322 def : ARMPat<(ARMWrapper tglobaladdr :$dst), (MOVi32imm tglobaladdr :$dst)>,
3323 Requires<[IsARM, UseMovt]>;
3324 def : ARMPat<(ARMWrapperJT tjumptable:$dst, imm:$id),
3325 (LEApcrelJT tjumptable:$dst, imm:$id)>;
3327 // TODO: add,sub,and, 3-instr forms?
3330 def : ARMPat<(ARMtcret tcGPR:$dst),
3331 (TCRETURNri tcGPR:$dst)>, Requires<[IsDarwin]>;
3333 def : ARMPat<(ARMtcret (i32 tglobaladdr:$dst)),
3334 (TCRETURNdi texternalsym:$dst)>, Requires<[IsDarwin]>;
3336 def : ARMPat<(ARMtcret (i32 texternalsym:$dst)),
3337 (TCRETURNdi texternalsym:$dst)>, Requires<[IsDarwin]>;
3339 def : ARMPat<(ARMtcret tcGPR:$dst),
3340 (TCRETURNriND tcGPR:$dst)>, Requires<[IsNotDarwin]>;
3342 def : ARMPat<(ARMtcret (i32 tglobaladdr:$dst)),
3343 (TCRETURNdiND texternalsym:$dst)>, Requires<[IsNotDarwin]>;
3345 def : ARMPat<(ARMtcret (i32 texternalsym:$dst)),
3346 (TCRETURNdiND texternalsym:$dst)>, Requires<[IsNotDarwin]>;
3349 def : ARMPat<(ARMcall texternalsym:$func), (BL texternalsym:$func)>,
3350 Requires<[IsARM, IsNotDarwin]>;
3351 def : ARMPat<(ARMcall texternalsym:$func), (BLr9 texternalsym:$func)>,
3352 Requires<[IsARM, IsDarwin]>;
3354 // zextload i1 -> zextload i8
3355 def : ARMPat<(zextloadi1 addrmode_imm12:$addr), (LDRBi12 addrmode_imm12:$addr)>;
3356 def : ARMPat<(zextloadi1 ldst_so_reg:$addr), (LDRBrs ldst_so_reg:$addr)>;
3358 // extload -> zextload
3359 def : ARMPat<(extloadi1 addrmode_imm12:$addr), (LDRBi12 addrmode_imm12:$addr)>;
3360 def : ARMPat<(extloadi1 ldst_so_reg:$addr), (LDRBrs ldst_so_reg:$addr)>;
3361 def : ARMPat<(extloadi8 addrmode_imm12:$addr), (LDRBi12 addrmode_imm12:$addr)>;
3362 def : ARMPat<(extloadi8 ldst_so_reg:$addr), (LDRBrs ldst_so_reg:$addr)>;
3364 def : ARMPat<(extloadi16 addrmode3:$addr), (LDRH addrmode3:$addr)>;
3366 def : ARMPat<(extloadi8 addrmodepc:$addr), (PICLDRB addrmodepc:$addr)>;
3367 def : ARMPat<(extloadi16 addrmodepc:$addr), (PICLDRH addrmodepc:$addr)>;
3370 def : ARMV5TEPat<(mul (sra (shl GPR:$a, (i32 16)), (i32 16)),
3371 (sra (shl GPR:$b, (i32 16)), (i32 16))),
3372 (SMULBB GPR:$a, GPR:$b)>;
3373 def : ARMV5TEPat<(mul sext_16_node:$a, sext_16_node:$b),
3374 (SMULBB GPR:$a, GPR:$b)>;
3375 def : ARMV5TEPat<(mul (sra (shl GPR:$a, (i32 16)), (i32 16)),
3376 (sra GPR:$b, (i32 16))),
3377 (SMULBT GPR:$a, GPR:$b)>;
3378 def : ARMV5TEPat<(mul sext_16_node:$a, (sra GPR:$b, (i32 16))),
3379 (SMULBT GPR:$a, GPR:$b)>;
3380 def : ARMV5TEPat<(mul (sra GPR:$a, (i32 16)),
3381 (sra (shl GPR:$b, (i32 16)), (i32 16))),
3382 (SMULTB GPR:$a, GPR:$b)>;
3383 def : ARMV5TEPat<(mul (sra GPR:$a, (i32 16)), sext_16_node:$b),
3384 (SMULTB GPR:$a, GPR:$b)>;
3385 def : ARMV5TEPat<(sra (mul GPR:$a, (sra (shl GPR:$b, (i32 16)), (i32 16))),
3387 (SMULWB GPR:$a, GPR:$b)>;
3388 def : ARMV5TEPat<(sra (mul GPR:$a, sext_16_node:$b), (i32 16)),
3389 (SMULWB GPR:$a, GPR:$b)>;
3391 def : ARMV5TEPat<(add GPR:$acc,
3392 (mul (sra (shl GPR:$a, (i32 16)), (i32 16)),
3393 (sra (shl GPR:$b, (i32 16)), (i32 16)))),
3394 (SMLABB GPR:$a, GPR:$b, GPR:$acc)>;
3395 def : ARMV5TEPat<(add GPR:$acc,
3396 (mul sext_16_node:$a, sext_16_node:$b)),
3397 (SMLABB GPR:$a, GPR:$b, GPR:$acc)>;
3398 def : ARMV5TEPat<(add GPR:$acc,
3399 (mul (sra (shl GPR:$a, (i32 16)), (i32 16)),
3400 (sra GPR:$b, (i32 16)))),
3401 (SMLABT GPR:$a, GPR:$b, GPR:$acc)>;
3402 def : ARMV5TEPat<(add GPR:$acc,
3403 (mul sext_16_node:$a, (sra GPR:$b, (i32 16)))),
3404 (SMLABT GPR:$a, GPR:$b, GPR:$acc)>;
3405 def : ARMV5TEPat<(add GPR:$acc,
3406 (mul (sra GPR:$a, (i32 16)),
3407 (sra (shl GPR:$b, (i32 16)), (i32 16)))),
3408 (SMLATB GPR:$a, GPR:$b, GPR:$acc)>;
3409 def : ARMV5TEPat<(add GPR:$acc,
3410 (mul (sra GPR:$a, (i32 16)), sext_16_node:$b)),
3411 (SMLATB GPR:$a, GPR:$b, GPR:$acc)>;
3412 def : ARMV5TEPat<(add GPR:$acc,
3413 (sra (mul GPR:$a, (sra (shl GPR:$b, (i32 16)), (i32 16))),
3415 (SMLAWB GPR:$a, GPR:$b, GPR:$acc)>;
3416 def : ARMV5TEPat<(add GPR:$acc,
3417 (sra (mul GPR:$a, sext_16_node:$b), (i32 16))),
3418 (SMLAWB GPR:$a, GPR:$b, GPR:$acc)>;
3420 //===----------------------------------------------------------------------===//
3424 include "ARMInstrThumb.td"
3426 //===----------------------------------------------------------------------===//
3430 include "ARMInstrThumb2.td"
3432 //===----------------------------------------------------------------------===//
3433 // Floating Point Support
3436 include "ARMInstrVFP.td"
3438 //===----------------------------------------------------------------------===//
3439 // Advanced SIMD (NEON) Support
3442 include "ARMInstrNEON.td"
3444 //===----------------------------------------------------------------------===//
3445 // Coprocessor Instructions. For disassembly only.
3448 def CDP : ABI<0b1110, (outs), (ins nohash_imm:$cop, i32imm:$opc1,
3449 nohash_imm:$CRd, nohash_imm:$CRn, nohash_imm:$CRm, i32imm:$opc2),
3450 NoItinerary, "cdp", "\tp$cop, $opc1, cr$CRd, cr$CRn, cr$CRm, $opc2",
3451 [/* For disassembly only; pattern left blank */]> {
3455 def CDP2 : ABXI<0b1110, (outs), (ins nohash_imm:$cop, i32imm:$opc1,
3456 nohash_imm:$CRd, nohash_imm:$CRn, nohash_imm:$CRm, i32imm:$opc2),
3457 NoItinerary, "cdp2\tp$cop, $opc1, cr$CRd, cr$CRn, cr$CRm, $opc2",
3458 [/* For disassembly only; pattern left blank */]> {
3459 let Inst{31-28} = 0b1111;
3463 class ACI<dag oops, dag iops, string opc, string asm>
3464 : I<oops, iops, AddrModeNone, Size4Bytes, IndexModeNone, BrFrm, NoItinerary,
3465 opc, asm, "", [/* For disassembly only; pattern left blank */]> {
3466 let Inst{27-25} = 0b110;
3469 multiclass LdStCop<bits<4> op31_28, bit load, string opc> {
3471 def _OFFSET : ACI<(outs),
3472 (ins nohash_imm:$cop, nohash_imm:$CRd, addrmode2:$addr),
3473 opc, "\tp$cop, cr$CRd, $addr"> {
3474 let Inst{31-28} = op31_28;
3475 let Inst{24} = 1; // P = 1
3476 let Inst{21} = 0; // W = 0
3477 let Inst{22} = 0; // D = 0
3478 let Inst{20} = load;
3481 def _PRE : ACI<(outs),
3482 (ins nohash_imm:$cop, nohash_imm:$CRd, addrmode2:$addr),
3483 opc, "\tp$cop, cr$CRd, $addr!"> {
3484 let Inst{31-28} = op31_28;
3485 let Inst{24} = 1; // P = 1
3486 let Inst{21} = 1; // W = 1
3487 let Inst{22} = 0; // D = 0
3488 let Inst{20} = load;
3491 def _POST : ACI<(outs),
3492 (ins nohash_imm:$cop, nohash_imm:$CRd, GPR:$base, am2offset:$offset),
3493 opc, "\tp$cop, cr$CRd, [$base], $offset"> {
3494 let Inst{31-28} = op31_28;
3495 let Inst{24} = 0; // P = 0
3496 let Inst{21} = 1; // W = 1
3497 let Inst{22} = 0; // D = 0
3498 let Inst{20} = load;
3501 def _OPTION : ACI<(outs),
3502 (ins nohash_imm:$cop, nohash_imm:$CRd, GPR:$base, i32imm:$option),
3503 opc, "\tp$cop, cr$CRd, [$base], $option"> {
3504 let Inst{31-28} = op31_28;
3505 let Inst{24} = 0; // P = 0
3506 let Inst{23} = 1; // U = 1
3507 let Inst{21} = 0; // W = 0
3508 let Inst{22} = 0; // D = 0
3509 let Inst{20} = load;
3512 def L_OFFSET : ACI<(outs),
3513 (ins nohash_imm:$cop, nohash_imm:$CRd, addrmode2:$addr),
3514 !strconcat(opc, "l"), "\tp$cop, cr$CRd, $addr"> {
3515 let Inst{31-28} = op31_28;
3516 let Inst{24} = 1; // P = 1
3517 let Inst{21} = 0; // W = 0
3518 let Inst{22} = 1; // D = 1
3519 let Inst{20} = load;
3522 def L_PRE : ACI<(outs),
3523 (ins nohash_imm:$cop, nohash_imm:$CRd, addrmode2:$addr),
3524 !strconcat(opc, "l"), "\tp$cop, cr$CRd, $addr!"> {
3525 let Inst{31-28} = op31_28;
3526 let Inst{24} = 1; // P = 1
3527 let Inst{21} = 1; // W = 1
3528 let Inst{22} = 1; // D = 1
3529 let Inst{20} = load;
3532 def L_POST : ACI<(outs),
3533 (ins nohash_imm:$cop, nohash_imm:$CRd, GPR:$base, am2offset:$offset),
3534 !strconcat(opc, "l"), "\tp$cop, cr$CRd, [$base], $offset"> {
3535 let Inst{31-28} = op31_28;
3536 let Inst{24} = 0; // P = 0
3537 let Inst{21} = 1; // W = 1
3538 let Inst{22} = 1; // D = 1
3539 let Inst{20} = load;
3542 def L_OPTION : ACI<(outs),
3543 (ins nohash_imm:$cop, nohash_imm:$CRd, GPR:$base, nohash_imm:$option),
3544 !strconcat(opc, "l"), "\tp$cop, cr$CRd, [$base], $option"> {
3545 let Inst{31-28} = op31_28;
3546 let Inst{24} = 0; // P = 0
3547 let Inst{23} = 1; // U = 1
3548 let Inst{21} = 0; // W = 0
3549 let Inst{22} = 1; // D = 1
3550 let Inst{20} = load;
3554 defm LDC : LdStCop<{?,?,?,?}, 1, "ldc">;
3555 defm LDC2 : LdStCop<0b1111, 1, "ldc2">;
3556 defm STC : LdStCop<{?,?,?,?}, 0, "stc">;
3557 defm STC2 : LdStCop<0b1111, 0, "stc2">;
3559 def MCR : ABI<0b1110, (outs), (ins nohash_imm:$cop, i32imm:$opc1,
3560 GPR:$Rt, nohash_imm:$CRn, nohash_imm:$CRm, i32imm:$opc2),
3561 NoItinerary, "mcr", "\tp$cop, $opc1, $Rt, cr$CRn, cr$CRm, $opc2",
3562 [/* For disassembly only; pattern left blank */]> {
3567 def MCR2 : ABXI<0b1110, (outs), (ins nohash_imm:$cop, i32imm:$opc1,
3568 GPR:$Rt, nohash_imm:$CRn, nohash_imm:$CRm, i32imm:$opc2),
3569 NoItinerary, "mcr2\tp$cop, $opc1, $Rt, cr$CRn, cr$CRm, $opc2",
3570 [/* For disassembly only; pattern left blank */]> {
3571 let Inst{31-28} = 0b1111;
3576 def MRC : ABI<0b1110, (outs), (ins nohash_imm:$cop, i32imm:$opc1,
3577 GPR:$Rt, nohash_imm:$CRn, nohash_imm:$CRm, i32imm:$opc2),
3578 NoItinerary, "mrc", "\tp$cop, $opc1, $Rt, cr$CRn, cr$CRm, $opc2",
3579 [/* For disassembly only; pattern left blank */]> {
3584 def MRC2 : ABXI<0b1110, (outs), (ins nohash_imm:$cop, i32imm:$opc1,
3585 GPR:$Rt, nohash_imm:$CRn, nohash_imm:$CRm, i32imm:$opc2),
3586 NoItinerary, "mrc2\tp$cop, $opc1, $Rt, cr$CRn, cr$CRm, $opc2",
3587 [/* For disassembly only; pattern left blank */]> {
3588 let Inst{31-28} = 0b1111;
3593 def MCRR : ABI<0b1100, (outs), (ins nohash_imm:$cop, i32imm:$opc,
3594 GPR:$Rt, GPR:$Rt2, nohash_imm:$CRm),
3595 NoItinerary, "mcrr", "\tp$cop, $opc, $Rt, $Rt2, cr$CRm",
3596 [/* For disassembly only; pattern left blank */]> {
3597 let Inst{23-20} = 0b0100;
3600 def MCRR2 : ABXI<0b1100, (outs), (ins nohash_imm:$cop, i32imm:$opc,
3601 GPR:$Rt, GPR:$Rt2, nohash_imm:$CRm),
3602 NoItinerary, "mcrr2\tp$cop, $opc, $Rt, $Rt2, cr$CRm",
3603 [/* For disassembly only; pattern left blank */]> {
3604 let Inst{31-28} = 0b1111;
3605 let Inst{23-20} = 0b0100;
3608 def MRRC : ABI<0b1100, (outs), (ins nohash_imm:$cop, i32imm:$opc,
3609 GPR:$Rt, GPR:$Rt2, nohash_imm:$CRm),
3610 NoItinerary, "mrrc", "\tp$cop, $opc, $Rt, $Rt2, cr$CRm",
3611 [/* For disassembly only; pattern left blank */]> {
3612 let Inst{23-20} = 0b0101;
3615 def MRRC2 : ABXI<0b1100, (outs), (ins nohash_imm:$cop, i32imm:$opc,
3616 GPR:$Rt, GPR:$Rt2, nohash_imm:$CRm),
3617 NoItinerary, "mrrc2\tp$cop, $opc, $Rt, $Rt2, cr$CRm",
3618 [/* For disassembly only; pattern left blank */]> {
3619 let Inst{31-28} = 0b1111;
3620 let Inst{23-20} = 0b0101;
3623 //===----------------------------------------------------------------------===//
3624 // Move between special register and ARM core register -- for disassembly only
3627 def MRS : ABI<0b0001,(outs GPR:$dst),(ins), NoItinerary, "mrs", "\t$dst, cpsr",
3628 [/* For disassembly only; pattern left blank */]> {
3629 let Inst{23-20} = 0b0000;
3630 let Inst{7-4} = 0b0000;
3633 def MRSsys : ABI<0b0001,(outs GPR:$dst),(ins), NoItinerary,"mrs","\t$dst, spsr",
3634 [/* For disassembly only; pattern left blank */]> {
3635 let Inst{23-20} = 0b0100;
3636 let Inst{7-4} = 0b0000;
3639 def MSR : ABI<0b0001, (outs), (ins GPR:$src, msr_mask:$mask), NoItinerary,
3640 "msr", "\tcpsr$mask, $src",
3641 [/* For disassembly only; pattern left blank */]> {
3642 let Inst{23-20} = 0b0010;
3643 let Inst{7-4} = 0b0000;
3646 def MSRi : ABI<0b0011, (outs), (ins so_imm:$a, msr_mask:$mask), NoItinerary,
3647 "msr", "\tcpsr$mask, $a",
3648 [/* For disassembly only; pattern left blank */]> {
3649 let Inst{23-20} = 0b0010;
3650 let Inst{7-4} = 0b0000;
3653 def MSRsys : ABI<0b0001, (outs), (ins GPR:$src, msr_mask:$mask), NoItinerary,
3654 "msr", "\tspsr$mask, $src",
3655 [/* For disassembly only; pattern left blank */]> {
3656 let Inst{23-20} = 0b0110;
3657 let Inst{7-4} = 0b0000;
3660 def MSRsysi : ABI<0b0011, (outs), (ins so_imm:$a, msr_mask:$mask), NoItinerary,
3661 "msr", "\tspsr$mask, $a",
3662 [/* For disassembly only; pattern left blank */]> {
3663 let Inst{23-20} = 0b0110;
3664 let Inst{7-4} = 0b0000;