1 //===- ARMInstrInfo.td - Target Description for ARM Target ----------------===//
3 // The LLVM Compiler Infrastructure
5 // This file was developed by the "Instituto Nokia de Tecnologia" and
6 // is distributed under the University of Illinois Open Source
7 // License. See LICENSE.TXT for details.
9 //===----------------------------------------------------------------------===//
11 // This file describes the ARM instructions in TableGen format.
13 //===----------------------------------------------------------------------===//
16 def op_addr_mode1 : Operand<iPTR> {
17 let PrintMethod = "printAddrMode1";
18 let MIOperandInfo = (ops ptr_rc, ptr_rc, i32imm);
21 def op_addr_mode5 : Operand<iPTR> {
22 let PrintMethod = "printAddrMode5";
23 let MIOperandInfo = (ops ptr_rc, i32imm);
26 def memri : Operand<iPTR> {
27 let PrintMethod = "printMemRegImm";
28 let MIOperandInfo = (ops i32imm, ptr_rc);
31 // Define ARM specific addressing mode.
32 //Addressing Mode 1: data processing operands
33 def addr_mode1 : ComplexPattern<iPTR, 3, "SelectAddrMode1", [imm, sra, shl, srl],
36 //Addressing Mode 5: VFP load/store
37 def addr_mode5 : ComplexPattern<iPTR, 2, "SelectAddrMode5", [], []>;
39 //register plus/minus 12 bit offset
40 def iaddr : ComplexPattern<iPTR, 2, "SelectAddrRegImm", [frameindex], []>;
41 //register plus scaled register
42 //def raddr : ComplexPattern<iPTR, 2, "SelectAddrRegReg", [], []>;
44 //===----------------------------------------------------------------------===//
45 // Instruction Class Templates
46 //===----------------------------------------------------------------------===//
47 class InstARM<dag ops, string asmstr, list<dag> pattern> : Instruction {
48 let Namespace = "ARM";
50 dag OperandList = ops;
51 let AsmString = asmstr;
52 let Pattern = pattern;
55 class IntBinOp<string OpcStr, SDNode OpNode> :
56 InstARM<(ops IntRegs:$dst, IntRegs:$a, IntRegs:$b),
57 !strconcat(OpcStr, " $dst, $a, $b"),
58 [(set IntRegs:$dst, (OpNode IntRegs:$a, IntRegs:$b))]>;
60 class FPBinOp<string OpcStr, SDNode OpNode> :
61 InstARM<(ops FPRegs:$dst, FPRegs:$a, FPRegs:$b),
62 !strconcat(OpcStr, " $dst, $a, $b"),
63 [(set FPRegs:$dst, (OpNode FPRegs:$a, FPRegs:$b))]>;
65 class DFPBinOp<string OpcStr, SDNode OpNode> :
66 InstARM<(ops DFPRegs:$dst, DFPRegs:$a, DFPRegs:$b),
67 !strconcat(OpcStr, " $dst, $a, $b"),
68 [(set DFPRegs:$dst, (OpNode DFPRegs:$a, DFPRegs:$b))]>;
70 class FPUnaryOp<string OpcStr, SDNode OpNode> :
71 InstARM<(ops FPRegs:$dst, FPRegs:$src),
72 !strconcat(OpcStr, " $dst, $src"),
73 [(set FPRegs:$dst, (OpNode FPRegs:$src))]>;
75 class DFPUnaryOp<string OpcStr, SDNode OpNode> :
76 InstARM<(ops DFPRegs:$dst, DFPRegs:$src),
77 !strconcat(OpcStr, " $dst, $src"),
78 [(set DFPRegs:$dst, (OpNode DFPRegs:$src))]>;
80 class Addr1BinOp<string OpcStr, SDNode OpNode> :
81 InstARM<(ops IntRegs:$dst, IntRegs:$a, op_addr_mode1:$b),
82 !strconcat(OpcStr, " $dst, $a, $b"),
83 [(set IntRegs:$dst, (OpNode IntRegs:$a, addr_mode1:$b))]>;
85 //===----------------------------------------------------------------------===//
87 //===----------------------------------------------------------------------===//
89 def brtarget : Operand<OtherVT>;
91 // Operand for printing out a condition code.
92 let PrintMethod = "printCCOperand" in
93 def CCOp : Operand<i32>;
95 def SDT_ARMCallSeq : SDTypeProfile<0, 1, [ SDTCisVT<0, i32> ]>;
96 def callseq_start : SDNode<"ISD::CALLSEQ_START", SDT_ARMCallSeq,
97 [SDNPHasChain, SDNPOutFlag]>;
98 def callseq_end : SDNode<"ISD::CALLSEQ_END", SDT_ARMCallSeq,
99 [SDNPHasChain, SDNPOutFlag]>;
101 def SDT_ARMcall : SDTypeProfile<0, -1, [SDTCisInt<0>]>;
102 def ARMcall : SDNode<"ARMISD::CALL", SDT_ARMcall,
103 [SDNPHasChain, SDNPOptInFlag, SDNPOutFlag]>;
104 def retflag : SDNode<"ARMISD::RET_FLAG", SDTRet,
105 [SDNPHasChain, SDNPOptInFlag]>;
107 def SDTarmselect : SDTypeProfile<1, 3, [SDTCisSameAs<0, 1>, SDTCisSameAs<0, 2>, SDTCisInt<0>, SDTCisVT<2, i32>]>;
108 def armselect : SDNode<"ARMISD::SELECT", SDTarmselect, [SDNPInFlag, SDNPOutFlag]>;
110 def SDTarmfmstat : SDTypeProfile<0, 0, []>;
111 def armfmstat : SDNode<"ARMISD::FMSTAT", SDTarmfmstat, [SDNPInFlag, SDNPOutFlag]>;
113 def SDTarmbr : SDTypeProfile<0, 2, [SDTCisVT<0, OtherVT>, SDTCisVT<1, i32>]>;
114 def armbr : SDNode<"ARMISD::BR", SDTarmbr, [SDNPHasChain, SDNPInFlag]>;
116 def SDTVoidBinOp : SDTypeProfile<0, 2, [SDTCisSameAs<0, 1>]>;
117 def armcmp : SDNode<"ARMISD::CMP", SDTVoidBinOp, [SDNPOutFlag]>;
119 def armfsitos : SDNode<"ARMISD::FSITOS", SDTUnaryOp>;
120 def armftosis : SDNode<"ARMISD::FTOSIS", SDTUnaryOp>;
121 def armfsitod : SDNode<"ARMISD::FSITOD", SDTUnaryOp>;
122 def armftosid : SDNode<"ARMISD::FTOSID", SDTUnaryOp>;
123 def armfuitos : SDNode<"ARMISD::FUITOS", SDTUnaryOp>;
124 def armftouis : SDNode<"ARMISD::FTOUIS", SDTUnaryOp>;
125 def armfuitod : SDNode<"ARMISD::FUITOD", SDTUnaryOp>;
126 def armftouid : SDNode<"ARMISD::FTOUID", SDTUnaryOp>;
128 def SDTarmfmrrd : SDTypeProfile<0, 3, [SDTCisInt<0>, SDTCisInt<1>, SDTCisFP<2>]>;
129 def armfmrrd : SDNode<"ARMISD::FMRRD", SDTarmfmrrd,
130 [SDNPHasChain, SDNPOptInFlag, SDNPOutFlag]>;
132 def SDTarmfmdrr : SDTypeProfile<1, 2, [SDTCisFP<0>, SDTCisInt<1>, SDTCisInt<2>]>;
133 def armfmdrr : SDNode<"ARMISD::FMDRR", SDTarmfmdrr, []>;
135 def ADJCALLSTACKUP : InstARM<(ops i32imm:$amt),
136 "!ADJCALLSTACKUP $amt",
137 [(callseq_end imm:$amt)]>, Imp<[R13],[R13]>;
139 def ADJCALLSTACKDOWN : InstARM<(ops i32imm:$amt),
140 "!ADJCALLSTACKDOWN $amt",
141 [(callseq_start imm:$amt)]>, Imp<[R13],[R13]>;
143 def IMPLICIT_DEF_Int : InstARM<(ops IntRegs:$dst),
144 "@IMPLICIT_DEF $dst",
145 [(set IntRegs:$dst, (undef))]>;
146 def IMPLICIT_DEF_FP : InstARM<(ops FPRegs:$dst), "@IMPLICIT_DEF $dst",
147 [(set FPRegs:$dst, (undef))]>;
148 def IMPLICIT_DEF_DFP : InstARM<(ops DFPRegs:$dst), "@IMPLICIT_DEF $dst",
149 [(set DFPRegs:$dst, (undef))]>;
151 let isReturn = 1 in {
152 def bx: InstARM<(ops), "bx r14", [(retflag)]>;
155 let noResults = 1, Defs = [R0, R1, R2, R3, R14] in {
156 def bl: InstARM<(ops i32imm:$func, variable_ops), "bl $func", []>;
157 def blx : InstARM<(ops IntRegs:$func, variable_ops), "blx $func", [(ARMcall IntRegs:$func)]>;
160 def ldr : InstARM<(ops IntRegs:$dst, memri:$addr),
162 [(set IntRegs:$dst, (load iaddr:$addr))]>;
164 def LDRB : InstARM<(ops IntRegs:$dst, IntRegs:$addr),
165 "ldrb $dst, [$addr]",
166 [(set IntRegs:$dst, (zextloadi8 IntRegs:$addr))]>;
168 def LDRSB : InstARM<(ops IntRegs:$dst, IntRegs:$addr),
169 "ldrsb $dst, [$addr]",
170 [(set IntRegs:$dst, (sextloadi8 IntRegs:$addr))]>;
172 def LDRH : InstARM<(ops IntRegs:$dst, IntRegs:$addr),
173 "ldrh $dst, [$addr]",
174 [(set IntRegs:$dst, (zextloadi16 IntRegs:$addr))]>;
176 def LDRSH : InstARM<(ops IntRegs:$dst, IntRegs:$addr),
177 "ldrsh $dst, [$addr]",
178 [(set IntRegs:$dst, (sextloadi16 IntRegs:$addr))]>;
180 def str : InstARM<(ops IntRegs:$src, memri:$addr),
182 [(store IntRegs:$src, iaddr:$addr)]>;
184 def STRB : InstARM<(ops IntRegs:$src, IntRegs:$addr),
185 "strb $src, [$addr]",
186 [(truncstorei8 IntRegs:$src, IntRegs:$addr)]>;
188 def STRH : InstARM<(ops IntRegs:$src, IntRegs:$addr),
189 "strh $src, [$addr]",
190 [(truncstorei16 IntRegs:$src, IntRegs:$addr)]>;
192 def MOV : InstARM<(ops IntRegs:$dst, op_addr_mode1:$src),
193 "mov $dst, $src", [(set IntRegs:$dst, addr_mode1:$src)]>;
195 def ADD : Addr1BinOp<"add", add>;
196 def ADCS : Addr1BinOp<"adcs", adde>;
197 def ADDS : Addr1BinOp<"adds", addc>;
199 // "LEA" forms of add
200 def lea_addri : InstARM<(ops IntRegs:$dst, memri:$addr),
201 "add $dst, ${addr:arith}",
202 [(set IntRegs:$dst, iaddr:$addr)]>;
205 def SUB : Addr1BinOp<"sub", sub>;
206 def SBCS : Addr1BinOp<"sbcs", sube>;
207 def SUBS : Addr1BinOp<"subs", subc>;
208 def AND : Addr1BinOp<"and", and>;
209 def EOR : Addr1BinOp<"eor", xor>;
210 def ORR : Addr1BinOp<"orr", or>;
212 let isTwoAddress = 1 in {
213 def movcond : InstARM<(ops IntRegs:$dst, IntRegs:$false,
214 op_addr_mode1:$true, CCOp:$cc),
215 "mov$cc $dst, $true",
216 [(set IntRegs:$dst, (armselect addr_mode1:$true,
217 IntRegs:$false, imm:$cc))]>;
220 def MUL : IntBinOp<"mul", mul>;
223 def SMULL : IntBinOp<"smull r12,", mulhs>;
224 def UMULL : IntBinOp<"umull r12,", mulhu>;
227 let isTerminator = 1, isBranch = 1 in {
228 def bcond : InstARM<(ops brtarget:$dst, CCOp:$cc),
230 [(armbr bb:$dst, imm:$cc)]>;
232 def b : InstARM<(ops brtarget:$dst),
237 def cmp : InstARM<(ops IntRegs:$a, op_addr_mode1:$b),
239 [(armcmp IntRegs:$a, addr_mode1:$b)]>;
241 // Floating Point Compare
242 def fcmps : InstARM<(ops FPRegs:$a, FPRegs:$b),
244 [(armcmp FPRegs:$a, FPRegs:$b)]>;
246 def fcmpd : InstARM<(ops DFPRegs:$a, DFPRegs:$b),
248 [(armcmp DFPRegs:$a, DFPRegs:$b)]>;
250 // Floating Point Copy
251 def FCPYS : InstARM<(ops FPRegs:$dst, FPRegs:$src), "fcpys $dst, $src", []>;
253 def FCPYD : InstARM<(ops DFPRegs:$dst, DFPRegs:$src), "fcpyd $dst, $src", []>;
255 // Floating Point Conversion
256 // We use bitconvert for moving the data between the register classes.
257 // The format conversion is done with ARM specific nodes
259 def FMSR : InstARM<(ops FPRegs:$dst, IntRegs:$src),
260 "fmsr $dst, $src", [(set FPRegs:$dst, (bitconvert IntRegs:$src))]>;
262 def FMRS : InstARM<(ops IntRegs:$dst, FPRegs:$src),
263 "fmrs $dst, $src", [(set IntRegs:$dst, (bitconvert FPRegs:$src))]>;
265 def FMRRD : InstARM<(ops IntRegs:$i0, IntRegs:$i1, DFPRegs:$src),
266 "fmrrd $i0, $i1, $src", [(armfmrrd IntRegs:$i0, IntRegs:$i1, DFPRegs:$src)]>;
268 def FMDRR : InstARM<(ops DFPRegs:$dst, IntRegs:$i0, IntRegs:$i1),
269 "fmdrr $dst, $i0, $i1", [(set DFPRegs:$dst, (armfmdrr IntRegs:$i0, IntRegs:$i1))]>;
271 def FSITOS : InstARM<(ops FPRegs:$dst, FPRegs:$src),
272 "fsitos $dst, $src", [(set FPRegs:$dst, (armfsitos FPRegs:$src))]>;
274 def FTOSIS : InstARM<(ops FPRegs:$dst, FPRegs:$src),
275 "ftosis $dst, $src", [(set FPRegs:$dst, (armftosis FPRegs:$src))]>;
277 def FSITOD : InstARM<(ops DFPRegs:$dst, FPRegs:$src),
278 "fsitod $dst, $src", [(set DFPRegs:$dst, (armfsitod FPRegs:$src))]>;
280 def FTOSID : InstARM<(ops FPRegs:$dst, DFPRegs:$src),
281 "ftosid $dst, $src", [(set FPRegs:$dst, (armftosid DFPRegs:$src))]>;
283 def FUITOS : InstARM<(ops FPRegs:$dst, FPRegs:$src),
284 "fuitos $dst, $src", [(set FPRegs:$dst, (armfuitos FPRegs:$src))]>;
286 def FTOUIS : InstARM<(ops FPRegs:$dst, FPRegs:$src),
287 "ftouis $dst, $src", [(set FPRegs:$dst, (armftouis FPRegs:$src))]>;
289 def FUITOD : InstARM<(ops DFPRegs:$dst, FPRegs:$src),
290 "fuitod $dst, $src", [(set DFPRegs:$dst, (armfuitod FPRegs:$src))]>;
292 def FTOUID : InstARM<(ops FPRegs:$dst, DFPRegs:$src),
293 "ftouid $dst, $src", [(set FPRegs:$dst, (armftouid DFPRegs:$src))]>;
295 def FCVTDS : InstARM<(ops DFPRegs:$dst, FPRegs:$src),
296 "fcvtds $dst, $src", [(set DFPRegs:$dst, (fextend FPRegs:$src))]>;
298 def FCVTSD : InstARM<(ops FPRegs:$dst, DFPRegs:$src),
299 "fcvtsd $dst, $src", [(set FPRegs:$dst, (fround DFPRegs:$src))]>;
301 def FMSTAT : InstARM<(ops ), "fmstat", [(armfmstat)]>;
303 // Floating Point Arithmetic
304 def FADDS : FPBinOp<"fadds", fadd>;
305 def FADDD : DFPBinOp<"faddd", fadd>;
306 def FSUBS : FPBinOp<"fsubs", fsub>;
307 def FSUBD : DFPBinOp<"fsubd", fsub>;
309 def FNEGS : FPUnaryOp<"fnegs", fneg>;
310 def FNEGD : DFPUnaryOp<"fnegd", fneg>;
311 def FABSS : FPUnaryOp<"fabss", fabs>;
312 def FABSD : DFPUnaryOp<"fabsd", fabs>;
314 def FMULS : FPBinOp<"fmuls", fmul>;
315 def FMULD : DFPBinOp<"fmuld", fmul>;
316 def FDIVS : FPBinOp<"fdivs", fdiv>;
317 def FDIVD : DFPBinOp<"fdivd", fdiv>;
319 // Floating Point Load
320 def FLDS : InstARM<(ops FPRegs:$dst, op_addr_mode5:$addr),
322 [(set FPRegs:$dst, (load addr_mode5:$addr))]>;
324 def FLDD : InstARM<(ops DFPRegs:$dst, op_addr_mode5:$addr),
326 [(set DFPRegs:$dst, (load addr_mode5:$addr))]>;
328 // Floating Point Store
329 def FSTS : InstARM<(ops FPRegs:$src, op_addr_mode5:$addr),
331 [(store FPRegs:$src, addr_mode5:$addr)]>;
333 def FSTD : InstARM<(ops DFPRegs:$src, op_addr_mode5:$addr),
335 [(store DFPRegs:$src, addr_mode5:$addr)]>;
337 def : Pat<(ARMcall tglobaladdr:$dst),
338 (bl tglobaladdr:$dst)>;
340 def : Pat<(ARMcall texternalsym:$dst),
341 (bl texternalsym:$dst)>;
343 def : Pat<(extloadi8 IntRegs:$addr),
344 (LDRB IntRegs:$addr)>;
345 def : Pat<(extloadi16 IntRegs:$addr),
346 (LDRH IntRegs:$addr)>;
348 // zextload bool -> zextload byte
349 def : Pat<(i32 (zextloadi1 IntRegs:$addr)), (LDRB IntRegs:$addr)>;
350 def : Pat<(i32 (zextloadi1 IntRegs:$addr)), (LDRB IntRegs:$addr)>;
352 // truncstore bool -> truncstore byte.
353 def : Pat<(truncstorei1 IntRegs:$src, IntRegs:$addr),
354 (STRB IntRegs:$addr, IntRegs:$src)>;
355 def : Pat<(truncstorei1 IntRegs:$src, IntRegs:$addr),
356 (STRB IntRegs:$addr, IntRegs:$src)>;