1 //===- ARMInstrInfo.td - Target Description for ARM Target -*- tablegen -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file describes the ARM instructions in TableGen format.
12 //===----------------------------------------------------------------------===//
14 //===----------------------------------------------------------------------===//
15 // ARM specific DAG Nodes.
19 def SDT_ARMCallSeqStart : SDCallSeqStart<[ SDTCisVT<0, i32> ]>;
20 def SDT_ARMCallSeqEnd : SDCallSeqEnd<[ SDTCisVT<0, i32>, SDTCisVT<1, i32> ]>;
22 def SDT_ARMSaveCallPC : SDTypeProfile<0, 1, []>;
24 def SDT_ARMcall : SDTypeProfile<0, -1, [SDTCisInt<0>]>;
26 def SDT_ARMCMov : SDTypeProfile<1, 3,
27 [SDTCisSameAs<0, 1>, SDTCisSameAs<0, 2>,
30 def SDT_ARMBrcond : SDTypeProfile<0, 2,
31 [SDTCisVT<0, OtherVT>, SDTCisVT<1, i32>]>;
33 def SDT_ARMBrJT : SDTypeProfile<0, 3,
34 [SDTCisPtrTy<0>, SDTCisVT<1, i32>,
37 def SDT_ARMCmp : SDTypeProfile<0, 2, [SDTCisSameAs<0, 1>]>;
39 def SDT_ARMPICAdd : SDTypeProfile<1, 2, [SDTCisSameAs<0, 1>,
40 SDTCisPtrTy<1>, SDTCisVT<2, i32>]>;
42 def SDT_ARMThreadPointer : SDTypeProfile<1, 0, [SDTCisPtrTy<0>]>;
45 def ARMWrapper : SDNode<"ARMISD::Wrapper", SDTIntUnaryOp>;
46 def ARMWrapperJT : SDNode<"ARMISD::WrapperJT", SDTIntBinOp>;
48 def ARMcallseq_start : SDNode<"ISD::CALLSEQ_START", SDT_ARMCallSeqStart,
49 [SDNPHasChain, SDNPOutFlag]>;
50 def ARMcallseq_end : SDNode<"ISD::CALLSEQ_END", SDT_ARMCallSeqEnd,
51 [SDNPHasChain, SDNPOptInFlag, SDNPOutFlag]>;
53 def ARMcall : SDNode<"ARMISD::CALL", SDT_ARMcall,
54 [SDNPHasChain, SDNPOptInFlag, SDNPOutFlag]>;
55 def ARMcall_pred : SDNode<"ARMISD::CALL_PRED", SDT_ARMcall,
56 [SDNPHasChain, SDNPOptInFlag, SDNPOutFlag]>;
57 def ARMcall_nolink : SDNode<"ARMISD::CALL_NOLINK", SDT_ARMcall,
58 [SDNPHasChain, SDNPOptInFlag, SDNPOutFlag]>;
60 def ARMretflag : SDNode<"ARMISD::RET_FLAG", SDTNone,
61 [SDNPHasChain, SDNPOptInFlag]>;
63 def ARMcmov : SDNode<"ARMISD::CMOV", SDT_ARMCMov,
65 def ARMcneg : SDNode<"ARMISD::CNEG", SDT_ARMCMov,
68 def ARMbrcond : SDNode<"ARMISD::BRCOND", SDT_ARMBrcond,
69 [SDNPHasChain, SDNPInFlag, SDNPOutFlag]>;
71 def ARMbrjt : SDNode<"ARMISD::BR_JT", SDT_ARMBrJT,
74 def ARMcmp : SDNode<"ARMISD::CMP", SDT_ARMCmp,
77 def ARMcmpNZ : SDNode<"ARMISD::CMPNZ", SDT_ARMCmp,
80 def ARMpic_add : SDNode<"ARMISD::PIC_ADD", SDT_ARMPICAdd>;
82 def ARMsrl_flag : SDNode<"ARMISD::SRL_FLAG", SDTIntUnaryOp, [SDNPOutFlag]>;
83 def ARMsra_flag : SDNode<"ARMISD::SRA_FLAG", SDTIntUnaryOp, [SDNPOutFlag]>;
84 def ARMrrx : SDNode<"ARMISD::RRX" , SDTIntUnaryOp, [SDNPInFlag ]>;
86 def ARMthread_pointer: SDNode<"ARMISD::THREAD_POINTER", SDT_ARMThreadPointer>;
88 //===----------------------------------------------------------------------===//
89 // ARM Instruction Predicate Definitions.
91 def HasV5T : Predicate<"Subtarget->hasV5TOps()">;
92 def HasV5TE : Predicate<"Subtarget->hasV5TEOps()">;
93 def HasV6 : Predicate<"Subtarget->hasV6Ops()">;
94 def IsThumb : Predicate<"Subtarget->isThumb()">;
95 def IsARM : Predicate<"!Subtarget->isThumb()">;
97 //===----------------------------------------------------------------------===//
98 // ARM Flag Definitions.
100 class RegConstraint<string C> {
101 string Constraints = C;
104 //===----------------------------------------------------------------------===//
105 // ARM specific transformation functions and pattern fragments.
108 // so_imm_XFORM - Return a so_imm value packed into the format described for
110 def so_imm_XFORM : SDNodeXForm<imm, [{
111 return CurDAG->getTargetConstant(ARM_AM::getSOImmVal(N->getValue()),
115 // so_imm_neg_XFORM - Return a so_imm value packed into the format described for
116 // so_imm_neg def below.
117 def so_imm_neg_XFORM : SDNodeXForm<imm, [{
118 return CurDAG->getTargetConstant(ARM_AM::getSOImmVal(-(int)N->getValue()),
122 // so_imm_not_XFORM - Return a so_imm value packed into the format described for
123 // so_imm_not def below.
124 def so_imm_not_XFORM : SDNodeXForm<imm, [{
125 return CurDAG->getTargetConstant(ARM_AM::getSOImmVal(~(int)N->getValue()),
129 // rot_imm predicate - True if the 32-bit immediate is equal to 8, 16, or 24.
130 def rot_imm : PatLeaf<(i32 imm), [{
131 int32_t v = (int32_t)N->getValue();
132 return v == 8 || v == 16 || v == 24;
135 /// imm1_15 predicate - True if the 32-bit immediate is in the range [1,15].
136 def imm1_15 : PatLeaf<(i32 imm), [{
137 return (int32_t)N->getValue() >= 1 && (int32_t)N->getValue() < 16;
140 /// imm16_31 predicate - True if the 32-bit immediate is in the range [16,31].
141 def imm16_31 : PatLeaf<(i32 imm), [{
142 return (int32_t)N->getValue() >= 16 && (int32_t)N->getValue() < 32;
146 PatLeaf<(imm), [{ return ARM_AM::getSOImmVal(-(int)N->getValue()) != -1; }],
150 PatLeaf<(imm), [{ return ARM_AM::getSOImmVal(~(int)N->getValue()) != -1; }],
153 // sext_16_node predicate - True if the SDNode is sign-extended 16 or more bits.
154 def sext_16_node : PatLeaf<(i32 GPR:$a), [{
155 return CurDAG->ComputeNumSignBits(SDValue(N,0)) >= 17;
158 class BinOpFrag<dag res> : PatFrag<(ops node:$LHS, node:$RHS), res>;
159 class UnOpFrag <dag res> : PatFrag<(ops node:$Src), res>;
161 //===----------------------------------------------------------------------===//
162 // Operand Definitions.
166 def brtarget : Operand<OtherVT>;
168 // A list of registers separated by comma. Used by load/store multiple.
169 def reglist : Operand<i32> {
170 let PrintMethod = "printRegisterList";
173 // An operand for the CONSTPOOL_ENTRY pseudo-instruction.
174 def cpinst_operand : Operand<i32> {
175 let PrintMethod = "printCPInstOperand";
178 def jtblock_operand : Operand<i32> {
179 let PrintMethod = "printJTBlockOperand";
183 def pclabel : Operand<i32> {
184 let PrintMethod = "printPCLabel";
187 // shifter_operand operands: so_reg and so_imm.
188 def so_reg : Operand<i32>, // reg reg imm
189 ComplexPattern<i32, 3, "SelectShifterOperandReg",
190 [shl,srl,sra,rotr]> {
191 let PrintMethod = "printSORegOperand";
192 let MIOperandInfo = (ops GPR, GPR, i32imm);
195 // so_imm - Match a 32-bit shifter_operand immediate operand, which is an
196 // 8-bit immediate rotated by an arbitrary number of bits. so_imm values are
197 // represented in the imm field in the same 12-bit form that they are encoded
198 // into so_imm instructions: the 8-bit immediate is the least significant bits
199 // [bits 0-7], the 4-bit shift amount is the next 4 bits [bits 8-11].
200 def so_imm : Operand<i32>,
202 [{ return ARM_AM::getSOImmVal(N->getValue()) != -1; }],
204 let PrintMethod = "printSOImmOperand";
207 // Break so_imm's up into two pieces. This handles immediates with up to 16
208 // bits set in them. This uses so_imm2part to match and so_imm2part_[12] to
209 // get the first/second pieces.
210 def so_imm2part : Operand<i32>,
212 [{ return ARM_AM::isSOImmTwoPartVal((unsigned)N->getValue()); }]> {
213 let PrintMethod = "printSOImm2PartOperand";
216 def so_imm2part_1 : SDNodeXForm<imm, [{
217 unsigned V = ARM_AM::getSOImmTwoPartFirst((unsigned)N->getValue());
218 return CurDAG->getTargetConstant(ARM_AM::getSOImmVal(V), MVT::i32);
221 def so_imm2part_2 : SDNodeXForm<imm, [{
222 unsigned V = ARM_AM::getSOImmTwoPartSecond((unsigned)N->getValue());
223 return CurDAG->getTargetConstant(ARM_AM::getSOImmVal(V), MVT::i32);
227 // Define ARM specific addressing modes.
229 // addrmode2 := reg +/- reg shop imm
230 // addrmode2 := reg +/- imm12
232 def addrmode2 : Operand<i32>,
233 ComplexPattern<i32, 3, "SelectAddrMode2", []> {
234 let PrintMethod = "printAddrMode2Operand";
235 let MIOperandInfo = (ops GPR:$base, GPR:$offsreg, i32imm:$offsimm);
238 def am2offset : Operand<i32>,
239 ComplexPattern<i32, 2, "SelectAddrMode2Offset", []> {
240 let PrintMethod = "printAddrMode2OffsetOperand";
241 let MIOperandInfo = (ops GPR, i32imm);
244 // addrmode3 := reg +/- reg
245 // addrmode3 := reg +/- imm8
247 def addrmode3 : Operand<i32>,
248 ComplexPattern<i32, 3, "SelectAddrMode3", []> {
249 let PrintMethod = "printAddrMode3Operand";
250 let MIOperandInfo = (ops GPR:$base, GPR:$offsreg, i32imm:$offsimm);
253 def am3offset : Operand<i32>,
254 ComplexPattern<i32, 2, "SelectAddrMode3Offset", []> {
255 let PrintMethod = "printAddrMode3OffsetOperand";
256 let MIOperandInfo = (ops GPR, i32imm);
259 // addrmode4 := reg, <mode|W>
261 def addrmode4 : Operand<i32>,
262 ComplexPattern<i32, 2, "", []> {
263 let PrintMethod = "printAddrMode4Operand";
264 let MIOperandInfo = (ops GPR, i32imm);
267 // addrmode5 := reg +/- imm8*4
269 def addrmode5 : Operand<i32>,
270 ComplexPattern<i32, 2, "SelectAddrMode5", []> {
271 let PrintMethod = "printAddrMode5Operand";
272 let MIOperandInfo = (ops GPR, i32imm);
275 // addrmodepc := pc + reg
277 def addrmodepc : Operand<i32>,
278 ComplexPattern<i32, 2, "SelectAddrModePC", []> {
279 let PrintMethod = "printAddrModePCOperand";
280 let MIOperandInfo = (ops GPR, i32imm);
283 // ARM Predicate operand. Default to 14 = always (AL). Second part is CC
284 // register whose default is 0 (no register).
285 def pred : PredicateOperand<OtherVT, (ops i32imm, CCR),
286 (ops (i32 14), (i32 zero_reg))> {
287 let PrintMethod = "printPredicateOperand";
290 // Conditional code result for instructions whose 's' bit is set, e.g. subs.
292 def cc_out : OptionalDefOperand<OtherVT, (ops CCR), (ops (i32 zero_reg))> {
293 let PrintMethod = "printSBitModifierOperand";
296 //===----------------------------------------------------------------------===//
297 // ARM Instruction flags. These need to match ARMInstrInfo.h.
301 class AddrMode<bits<4> val> {
304 def AddrModeNone : AddrMode<0>;
305 def AddrMode1 : AddrMode<1>;
306 def AddrMode2 : AddrMode<2>;
307 def AddrMode3 : AddrMode<3>;
308 def AddrMode4 : AddrMode<4>;
309 def AddrMode5 : AddrMode<5>;
310 def AddrModeT1 : AddrMode<6>;
311 def AddrModeT2 : AddrMode<7>;
312 def AddrModeT4 : AddrMode<8>;
313 def AddrModeTs : AddrMode<9>;
316 class SizeFlagVal<bits<3> val> {
319 def SizeInvalid : SizeFlagVal<0>; // Unset.
320 def SizeSpecial : SizeFlagVal<1>; // Pseudo or special.
321 def Size8Bytes : SizeFlagVal<2>;
322 def Size4Bytes : SizeFlagVal<3>;
323 def Size2Bytes : SizeFlagVal<4>;
325 // Load / store index mode.
326 class IndexMode<bits<2> val> {
329 def IndexModeNone : IndexMode<0>;
330 def IndexModePre : IndexMode<1>;
331 def IndexModePost : IndexMode<2>;
333 //===----------------------------------------------------------------------===//
335 include "ARMInstrFormats.td"
337 //===----------------------------------------------------------------------===//
338 // Multiclass helpers...
341 /// AsI1_bin_irs - Defines a set of (op r, {so_imm|r|so_reg}) patterns for a
342 /// binop that produces a value.
343 multiclass AsI1_bin_irs<bits<4> opcod, string opc, PatFrag opnode> {
344 def ri : AsI1<opcod, (outs GPR:$dst), (ins GPR:$a, so_imm:$b), DPRIm,
345 opc, " $dst, $a, $b",
346 [(set GPR:$dst, (opnode GPR:$a, so_imm:$b))]>;
347 def rr : AsI1<opcod, (outs GPR:$dst), (ins GPR:$a, GPR:$b), DPRReg,
348 opc, " $dst, $a, $b",
349 [(set GPR:$dst, (opnode GPR:$a, GPR:$b))]>;
350 def rs : AsI1<opcod, (outs GPR:$dst), (ins GPR:$a, so_reg:$b), DPRSoReg,
351 opc, " $dst, $a, $b",
352 [(set GPR:$dst, (opnode GPR:$a, so_reg:$b))]>;
355 /// ASI1_bin_s_irs - Similar to AsI1_bin_irs except it sets the 's' bit so the
356 /// instruction modifies the CSPR register.
357 let Defs = [CPSR] in {
358 multiclass ASI1_bin_s_irs<bits<4> opcod, string opc, PatFrag opnode> {
359 def ri : AI1<opcod, (outs GPR:$dst), (ins GPR:$a, so_imm:$b), DPRImS,
360 opc, "s $dst, $a, $b",
361 [(set GPR:$dst, (opnode GPR:$a, so_imm:$b))]>;
362 def rr : AI1<opcod, (outs GPR:$dst), (ins GPR:$a, GPR:$b), DPRRegS,
363 opc, "s $dst, $a, $b",
364 [(set GPR:$dst, (opnode GPR:$a, GPR:$b))]>;
365 def rs : AI1<opcod, (outs GPR:$dst), (ins GPR:$a, so_reg:$b), DPRSoRegS,
366 opc, "s $dst, $a, $b",
367 [(set GPR:$dst, (opnode GPR:$a, so_reg:$b))]>;
371 /// AI1_cmp_irs - Defines a set of (op r, {so_imm|r|so_reg}) cmp / test
372 /// patterns. Similar to AsI1_bin_irs except the instruction does not produce
373 /// a explicit result, only implicitly set CPSR.
374 let Defs = [CPSR] in {
375 multiclass AI1_cmp_irs<bits<4> opcod, string opc, PatFrag opnode> {
376 def ri : AI1<opcod, (outs), (ins GPR:$a, so_imm:$b), DPRnIm,
378 [(opnode GPR:$a, so_imm:$b)]>;
379 def rr : AI1<opcod, (outs), (ins GPR:$a, GPR:$b), DPRnReg,
381 [(opnode GPR:$a, GPR:$b)]>;
382 def rs : AI1<opcod, (outs), (ins GPR:$a, so_reg:$b), DPRnSoReg,
384 [(opnode GPR:$a, so_reg:$b)]>;
388 /// AI_unary_rrot - A unary operation with two forms: one whose operand is a
389 /// register and one whose operand is a register rotated by 8/16/24.
390 multiclass AI_unary_rrot<bits<4> opcod, string opc, PatFrag opnode> {
391 def r : AI<opcod, (outs GPR:$dst), (ins GPR:$Src), Pseudo,
393 [(set GPR:$dst, (opnode GPR:$Src))]>, Requires<[IsARM, HasV6]>;
394 def r_rot : AI<opcod, (outs GPR:$dst), (ins GPR:$Src, i32imm:$rot), Pseudo,
395 opc, " $dst, $Src, ror $rot",
396 [(set GPR:$dst, (opnode (rotr GPR:$Src, rot_imm:$rot)))]>,
397 Requires<[IsARM, HasV6]>;
400 /// AI_bin_rrot - A binary operation with two forms: one whose operand is a
401 /// register and one whose operand is a register rotated by 8/16/24.
402 multiclass AI_bin_rrot<bits<4> opcod, string opc, PatFrag opnode> {
403 def rr : AI<opcod, (outs GPR:$dst), (ins GPR:$LHS, GPR:$RHS),
404 Pseudo, opc, " $dst, $LHS, $RHS",
405 [(set GPR:$dst, (opnode GPR:$LHS, GPR:$RHS))]>,
406 Requires<[IsARM, HasV6]>;
407 def rr_rot : AI<opcod, (outs GPR:$dst), (ins GPR:$LHS, GPR:$RHS, i32imm:$rot),
408 Pseudo, opc, " $dst, $LHS, $RHS, ror $rot",
409 [(set GPR:$dst, (opnode GPR:$LHS,
410 (rotr GPR:$RHS, rot_imm:$rot)))]>,
411 Requires<[IsARM, HasV6]>;
414 /// AsXI1_bin_c_irs - Same as AsI1_bin_irs but without the predicate operand and
415 /// setting carry bit. But it can optionally set CPSR.
416 let Uses = [CPSR] in {
417 multiclass AsXI1_bin_c_irs<bits<4> opcod, string opc, PatFrag opnode> {
418 def ri : AXI1<opcod, (outs GPR:$dst), (ins GPR:$a, so_imm:$b, cc_out:$s),
419 DPRIm, !strconcat(opc, "${s} $dst, $a, $b"),
420 [(set GPR:$dst, (opnode GPR:$a, so_imm:$b))]>;
421 def rr : AXI1<opcod, (outs GPR:$dst), (ins GPR:$a, GPR:$b, cc_out:$s),
422 DPRReg, !strconcat(opc, "${s} $dst, $a, $b"),
423 [(set GPR:$dst, (opnode GPR:$a, GPR:$b))]>;
424 def rs : AXI1<opcod, (outs GPR:$dst), (ins GPR:$a, so_reg:$b, cc_out:$s),
425 DPRSoReg, !strconcat(opc, "${s} $dst, $a, $b"),
426 [(set GPR:$dst, (opnode GPR:$a, so_reg:$b))]>;
430 //===----------------------------------------------------------------------===//
432 //===----------------------------------------------------------------------===//
434 //===----------------------------------------------------------------------===//
435 // Miscellaneous Instructions.
438 /// CONSTPOOL_ENTRY - This instruction represents a floating constant pool in
439 /// the function. The first operand is the ID# for this instruction, the second
440 /// is the index into the MachineConstantPool that this is, the third is the
441 /// size in bytes of this constant pool entry.
442 let isNotDuplicable = 1 in
443 def CONSTPOOL_ENTRY :
444 PseudoInst<(outs), (ins cpinst_operand:$instid, cpinst_operand:$cpidx,
446 "${instid:label} ${cpidx:cpentry}", []>;
448 let Defs = [SP], Uses = [SP] in {
450 PseudoInst<(outs), (ins i32imm:$amt1, i32imm:$amt2, pred:$p),
451 "@ ADJCALLSTACKUP $amt1",
452 [(ARMcallseq_end imm:$amt1, imm:$amt2)]>;
454 def ADJCALLSTACKDOWN :
455 PseudoInst<(outs), (ins i32imm:$amt, pred:$p),
456 "@ ADJCALLSTACKDOWN $amt",
457 [(ARMcallseq_start imm:$amt)]>;
461 PseudoInst<(outs), (ins i32imm:$line, i32imm:$col, i32imm:$file),
462 ".loc $file, $line, $col",
463 [(dwarf_loc (i32 imm:$line), (i32 imm:$col), (i32 imm:$file))]>;
465 let isNotDuplicable = 1 in {
466 def PICADD : AXI1<0x0, (outs GPR:$dst), (ins GPR:$a, pclabel:$cp, pred:$p),
467 Pseudo, "$cp:\n\tadd$p $dst, pc, $a",
468 [(set GPR:$dst, (ARMpic_add GPR:$a, imm:$cp))]>;
470 let AddedComplexity = 10 in {
471 let isSimpleLoad = 1 in
472 def PICLD : AXI2ldw<0x0, (outs GPR:$dst), (ins addrmodepc:$addr, pred:$p),
473 Pseudo, "${addr:label}:\n\tldr$p $dst, $addr",
474 [(set GPR:$dst, (load addrmodepc:$addr))]>;
476 def PICLDZH : AXI3ldh<0x0, (outs GPR:$dst), (ins addrmodepc:$addr, pred:$p),
477 Pseudo, "${addr:label}:\n\tldr${p}h $dst, $addr",
478 [(set GPR:$dst, (zextloadi16 addrmodepc:$addr))]>;
480 def PICLDZB : AXI2ldb<0x0, (outs GPR:$dst), (ins addrmodepc:$addr, pred:$p),
481 Pseudo, "${addr:label}:\n\tldr${p}b $dst, $addr",
482 [(set GPR:$dst, (zextloadi8 addrmodepc:$addr))]>;
484 def PICLDH : AXI3ldh<0x0, (outs GPR:$dst), (ins addrmodepc:$addr, pred:$p),
485 Pseudo, "${addr:label}:\n\tldr${p}h $dst, $addr",
486 [(set GPR:$dst, (extloadi16 addrmodepc:$addr))]>;
488 def PICLDB : AXI2ldb<0x0, (outs GPR:$dst), (ins addrmodepc:$addr, pred:$p),
489 Pseudo, "${addr:label}:\n\tldr${p}b $dst, $addr",
490 [(set GPR:$dst, (extloadi8 addrmodepc:$addr))]>;
492 def PICLDSH : AXI3ldsh<0x0, (outs GPR:$dst), (ins addrmodepc:$addr, pred:$p),
493 Pseudo, "${addr:label}:\n\tldr${p}sh $dst, $addr",
494 [(set GPR:$dst, (sextloadi16 addrmodepc:$addr))]>;
496 def PICLDSB : AXI3ldsb<0x0, (outs GPR:$dst), (ins addrmodepc:$addr, pred:$p),
497 Pseudo, "${addr:label}:\n\tldr${p}sb $dst, $addr",
498 [(set GPR:$dst, (sextloadi8 addrmodepc:$addr))]>;
500 let AddedComplexity = 10 in {
501 def PICSTR : AXI2stw<0x0, (outs), (ins GPR:$src, addrmodepc:$addr, pred:$p),
502 Pseudo, "${addr:label}:\n\tstr$p $src, $addr",
503 [(store GPR:$src, addrmodepc:$addr)]>;
505 def PICSTRH : AXI3sth<0x0, (outs), (ins GPR:$src, addrmodepc:$addr, pred:$p),
506 Pseudo, "${addr:label}:\n\tstr${p}h $src, $addr",
507 [(truncstorei16 GPR:$src, addrmodepc:$addr)]>;
509 def PICSTRB : AXI2stb<0x0, (outs), (ins GPR:$src, addrmodepc:$addr, pred:$p),
510 Pseudo, "${addr:label}:\n\tstr${p}b $src, $addr",
511 [(truncstorei8 GPR:$src, addrmodepc:$addr)]>;
515 //===----------------------------------------------------------------------===//
516 // Control Flow Instructions.
519 let isReturn = 1, isTerminator = 1 in
520 def BX_RET : AI<0x1, (outs), (ins), BranchMisc, "bx", " lr", [(ARMretflag)]>;
522 // FIXME: remove when we have a way to marking a MI with these properties.
523 // FIXME: $dst1 should be a def. But the extra ops must be in the end of the
525 let isReturn = 1, isTerminator = 1 in
526 def LDM_RET : AXI4ldpc<0x0, (outs),
527 (ins addrmode4:$addr, pred:$p, reglist:$dst1, variable_ops),
528 LdFrm, "ldm${p}${addr:submode} $addr, $dst1",
532 Defs = [R0, R1, R2, R3, R12, LR,
533 D0, D1, D2, D3, D4, D5, D6, D7, CPSR] in {
534 def BL : AXI<0xB, (outs), (ins i32imm:$func, variable_ops), Branch,
536 [(ARMcall tglobaladdr:$func)]>;
538 def BL_pred : AI<0xB, (outs), (ins i32imm:$func, variable_ops),
539 Branch, "bl", " ${func:call}",
540 [(ARMcall_pred tglobaladdr:$func)]>;
543 def BLX : AXI<0x2, (outs), (ins GPR:$func, variable_ops), BranchMisc,
545 [(ARMcall GPR:$func)]>, Requires<[IsARM, HasV5T]>;
548 def BX : AXIx2<0x0, (outs), (ins GPR:$func, variable_ops),
549 BranchMisc, "mov lr, pc\n\tbx $func",
550 [(ARMcall_nolink GPR:$func)]>;
554 let isBranch = 1, isTerminator = 1 in {
555 // B is "predicable" since it can be xformed into a Bcc.
556 let isBarrier = 1 in {
557 let isPredicable = 1 in
558 def B : AXI<0xA, (outs), (ins brtarget:$target), Branch, "b $target",
561 let isNotDuplicable = 1, isIndirectBranch = 1 in {
562 def BR_JTr : JTI<0x0, (outs), (ins GPR:$target, jtblock_operand:$jt, i32imm:$id),
563 "mov pc, $target \n$jt",
564 [(ARMbrjt GPR:$target, tjumptable:$jt, imm:$id)]>;
565 def BR_JTm : JTI2<0x0, (outs), (ins addrmode2:$target, jtblock_operand:$jt, i32imm:$id),
566 "ldr pc, $target \n$jt",
567 [(ARMbrjt (i32 (load addrmode2:$target)), tjumptable:$jt,
569 def BR_JTadd : JTI1<0x0, (outs), (ins GPR:$target, GPR:$idx, jtblock_operand:$jt,
571 "add pc, $target, $idx \n$jt",
572 [(ARMbrjt (add GPR:$target, GPR:$idx), tjumptable:$jt,
577 // FIXME: should be able to write a pattern for ARMBrcond, but can't use
578 // a two-value operand where a dag node expects two operands. :(
579 def Bcc : AI<0xA, (outs), (ins brtarget:$target), Branch,
581 [/*(ARMbrcond bb:$target, imm:$cc, CCR:$ccr)*/]>;
584 //===----------------------------------------------------------------------===//
585 // Load / store Instructions.
589 let isSimpleLoad = 1 in
590 def LDR : AI2ldw<0x0, (outs GPR:$dst), (ins addrmode2:$addr), LdFrm,
591 "ldr", " $dst, $addr",
592 [(set GPR:$dst, (load addrmode2:$addr))]>;
594 // Special LDR for loads from non-pc-relative constpools.
595 let isSimpleLoad = 1, mayLoad = 1, isReMaterializable = 1 in
596 def LDRcp : AI2ldw<0x0, (outs GPR:$dst), (ins addrmode2:$addr), LdFrm,
597 "ldr", " $dst, $addr", []>;
599 // Loads with zero extension
600 def LDRH : AI3ldh<0xB, (outs GPR:$dst), (ins addrmode3:$addr), LdFrm,
601 "ldr", "h $dst, $addr",
602 [(set GPR:$dst, (zextloadi16 addrmode3:$addr))]>;
604 def LDRB : AI2ldb<0x1, (outs GPR:$dst), (ins addrmode2:$addr), LdFrm,
605 "ldr", "b $dst, $addr",
606 [(set GPR:$dst, (zextloadi8 addrmode2:$addr))]>;
608 // Loads with sign extension
609 def LDRSH : AI3ldsh<0xE, (outs GPR:$dst), (ins addrmode3:$addr), LdFrm,
610 "ldr", "sh $dst, $addr",
611 [(set GPR:$dst, (sextloadi16 addrmode3:$addr))]>;
613 def LDRSB : AI3ldsb<0xD, (outs GPR:$dst), (ins addrmode3:$addr), LdFrm,
614 "ldr", "sb $dst, $addr",
615 [(set GPR:$dst, (sextloadi8 addrmode3:$addr))]>;
619 def LDRD : AI3ldd<0xD, (outs GPR:$dst), (ins addrmode3:$addr), LdFrm,
620 "ldr", "d $dst, $addr",
621 []>, Requires<[IsARM, HasV5T]>;
624 def LDR_PRE : AI2ldwpr<0x0, (outs GPR:$dst, GPR:$base_wb),
625 (ins addrmode2:$addr), LdFrm,
626 "ldr", " $dst, $addr!", "$addr.base = $base_wb", []>;
628 def LDR_POST : AI2ldwpo<0x0, (outs GPR:$dst, GPR:$base_wb),
629 (ins GPR:$base, am2offset:$offset), LdFrm,
630 "ldr", " $dst, [$base], $offset", "$base = $base_wb", []>;
632 def LDRH_PRE : AI3ldhpr<0xB, (outs GPR:$dst, GPR:$base_wb),
633 (ins addrmode3:$addr), LdFrm,
634 "ldr", "h $dst, $addr!", "$addr.base = $base_wb", []>;
636 def LDRH_POST : AI3ldhpo<0xB, (outs GPR:$dst, GPR:$base_wb),
637 (ins GPR:$base,am3offset:$offset), LdFrm,
638 "ldr", "h $dst, [$base], $offset", "$base = $base_wb", []>;
640 def LDRB_PRE : AI2ldbpr<0x1, (outs GPR:$dst, GPR:$base_wb),
641 (ins addrmode2:$addr), LdFrm,
642 "ldr", "b $dst, $addr!", "$addr.base = $base_wb", []>;
644 def LDRB_POST : AI2ldbpo<0x1, (outs GPR:$dst, GPR:$base_wb),
645 (ins GPR:$base,am2offset:$offset), LdFrm,
646 "ldr", "b $dst, [$base], $offset", "$base = $base_wb", []>;
648 def LDRSH_PRE : AI3ldshpr<0xE, (outs GPR:$dst, GPR:$base_wb),
649 (ins addrmode3:$addr), LdFrm,
650 "ldr", "sh $dst, $addr!", "$addr.base = $base_wb", []>;
652 def LDRSH_POST: AI3ldshpo<0xE, (outs GPR:$dst, GPR:$base_wb),
653 (ins GPR:$base,am3offset:$offset), LdFrm,
654 "ldr", "sh $dst, [$base], $offset", "$base = $base_wb", []>;
656 def LDRSB_PRE : AI3ldsbpr<0xD, (outs GPR:$dst, GPR:$base_wb),
657 (ins addrmode3:$addr), LdFrm,
658 "ldr", "sb $dst, $addr!", "$addr.base = $base_wb", []>;
660 def LDRSB_POST: AI3ldsbpo<0xD, (outs GPR:$dst, GPR:$base_wb),
661 (ins GPR:$base,am3offset:$offset), LdFrm,
662 "ldr", "sb $dst, [$base], $offset", "$base = $base_wb", []>;
666 def STR : AI2stw<0x0, (outs), (ins GPR:$src, addrmode2:$addr), StFrm,
667 "str", " $src, $addr",
668 [(store GPR:$src, addrmode2:$addr)]>;
670 // Stores with truncate
671 def STRH : AI3sth<0xB, (outs), (ins GPR:$src, addrmode3:$addr), StFrm,
672 "str", "h $src, $addr",
673 [(truncstorei16 GPR:$src, addrmode3:$addr)]>;
675 def STRB : AI2stb<0x1, (outs), (ins GPR:$src, addrmode2:$addr), StFrm,
676 "str", "b $src, $addr",
677 [(truncstorei8 GPR:$src, addrmode2:$addr)]>;
681 def STRD : AI3std<0xF, (outs), (ins GPR:$src, addrmode3:$addr), StFrm,
682 "str", "d $src, $addr",
683 []>, Requires<[IsARM, HasV5T]>;
686 def STR_PRE : AI2stwpr<0x0, (outs GPR:$base_wb),
687 (ins GPR:$src, GPR:$base, am2offset:$offset), StFrm,
688 "str", " $src, [$base, $offset]!", "$base = $base_wb",
690 (pre_store GPR:$src, GPR:$base, am2offset:$offset))]>;
692 def STR_POST : AI2stwpo<0x0, (outs GPR:$base_wb),
693 (ins GPR:$src, GPR:$base,am2offset:$offset), StFrm,
694 "str", " $src, [$base], $offset", "$base = $base_wb",
696 (post_store GPR:$src, GPR:$base, am2offset:$offset))]>;
698 def STRH_PRE : AI3sthpr<0xB, (outs GPR:$base_wb),
699 (ins GPR:$src, GPR:$base,am3offset:$offset), StFrm,
700 "str", "h $src, [$base, $offset]!", "$base = $base_wb",
702 (pre_truncsti16 GPR:$src, GPR:$base,am3offset:$offset))]>;
704 def STRH_POST: AI3sthpo<0xB, (outs GPR:$base_wb),
705 (ins GPR:$src, GPR:$base,am3offset:$offset), StFrm,
706 "str", "h $src, [$base], $offset", "$base = $base_wb",
707 [(set GPR:$base_wb, (post_truncsti16 GPR:$src,
708 GPR:$base, am3offset:$offset))]>;
710 def STRB_PRE : AI2stbpr<0x1, (outs GPR:$base_wb),
711 (ins GPR:$src, GPR:$base,am2offset:$offset), StFrm,
712 "str", "b $src, [$base, $offset]!", "$base = $base_wb",
713 [(set GPR:$base_wb, (pre_truncsti8 GPR:$src,
714 GPR:$base, am2offset:$offset))]>;
716 def STRB_POST: AI2stbpo<0x1, (outs GPR:$base_wb),
717 (ins GPR:$src, GPR:$base,am2offset:$offset), StFrm,
718 "str", "b $src, [$base], $offset", "$base = $base_wb",
719 [(set GPR:$base_wb, (post_truncsti8 GPR:$src,
720 GPR:$base, am2offset:$offset))]>;
722 //===----------------------------------------------------------------------===//
723 // Load / store multiple Instructions.
726 // FIXME: $dst1 should be a def.
728 def LDM : AXI4ld<0x0, (outs),
729 (ins addrmode4:$addr, pred:$p, reglist:$dst1, variable_ops),
730 LdFrm, "ldm${p}${addr:submode} $addr, $dst1",
734 def STM : AXI4st<0x0, (outs),
735 (ins addrmode4:$addr, pred:$p, reglist:$src1, variable_ops),
736 StFrm, "stm${p}${addr:submode} $addr, $src1",
739 //===----------------------------------------------------------------------===//
740 // Move Instructions.
743 def MOVr : AsI1<0xD, (outs GPR:$dst), (ins GPR:$src), DPRdReg,
744 "mov", " $dst, $src", []>;
745 def MOVs : AsI1<0xD, (outs GPR:$dst), (ins so_reg:$src), DPRdSoReg,
746 "mov", " $dst, $src", [(set GPR:$dst, so_reg:$src)]>;
748 let isReMaterializable = 1 in
749 def MOVi : AsI1<0xD, (outs GPR:$dst), (ins so_imm:$src), DPRdIm,
750 "mov", " $dst, $src", [(set GPR:$dst, so_imm:$src)]>;
752 def MOVrx : AsI1<0xD, (outs GPR:$dst), (ins GPR:$src), DPRdMisc,
753 "mov", " $dst, $src, rrx",
754 [(set GPR:$dst, (ARMrrx GPR:$src))]>;
756 // These aren't really mov instructions, but we have to define them this way
757 // due to flag operands.
759 let Defs = [CPSR] in {
760 def MOVsrl_flag : AI1<0xD, (outs GPR:$dst), (ins GPR:$src), DPRdMisc,
761 "mov", "s $dst, $src, lsr #1",
762 [(set GPR:$dst, (ARMsrl_flag GPR:$src))]>;
763 def MOVsra_flag : AI1<0xD, (outs GPR:$dst), (ins GPR:$src), DPRdMisc,
764 "mov", "s $dst, $src, asr #1",
765 [(set GPR:$dst, (ARMsra_flag GPR:$src))]>;
768 //===----------------------------------------------------------------------===//
769 // Extend Instructions.
774 defm SXTB : AI_unary_rrot<0x0, "sxtb", UnOpFrag<(sext_inreg node:$Src, i8)>>;
775 defm SXTH : AI_unary_rrot<0x0, "sxth", UnOpFrag<(sext_inreg node:$Src, i16)>>;
777 defm SXTAB : AI_bin_rrot<0x0, "sxtab",
778 BinOpFrag<(add node:$LHS, (sext_inreg node:$RHS, i8))>>;
779 defm SXTAH : AI_bin_rrot<0x0, "sxtah",
780 BinOpFrag<(add node:$LHS, (sext_inreg node:$RHS,i16))>>;
782 // TODO: SXT(A){B|H}16
786 let AddedComplexity = 16 in {
787 defm UXTB : AI_unary_rrot<0x0, "uxtb" , UnOpFrag<(and node:$Src, 0x000000FF)>>;
788 defm UXTH : AI_unary_rrot<0x0, "uxth" , UnOpFrag<(and node:$Src, 0x0000FFFF)>>;
789 defm UXTB16 : AI_unary_rrot<0x0, "uxtb16", UnOpFrag<(and node:$Src, 0x00FF00FF)>>;
791 def : ARMV6Pat<(and (shl GPR:$Src, 8), 0xFF00FF),
792 (UXTB16r_rot GPR:$Src, 24)>;
793 def : ARMV6Pat<(and (srl GPR:$Src, 8), 0xFF00FF),
794 (UXTB16r_rot GPR:$Src, 8)>;
796 defm UXTAB : AI_bin_rrot<0x0, "uxtab",
797 BinOpFrag<(add node:$LHS, (and node:$RHS, 0x00FF))>>;
798 defm UXTAH : AI_bin_rrot<0x0, "uxtah",
799 BinOpFrag<(add node:$LHS, (and node:$RHS, 0xFFFF))>>;
802 // This isn't safe in general, the add is two 16-bit units, not a 32-bit add.
803 //defm UXTAB16 : xxx<"uxtab16", 0xff00ff>;
805 // TODO: UXT(A){B|H}16
807 //===----------------------------------------------------------------------===//
808 // Arithmetic Instructions.
811 defm ADD : AsI1_bin_irs<0x4, "add", BinOpFrag<(add node:$LHS, node:$RHS)>>;
812 defm SUB : AsI1_bin_irs<0x2, "sub", BinOpFrag<(sub node:$LHS, node:$RHS)>>;
814 // ADD and SUB with 's' bit set.
815 defm ADDS : ASI1_bin_s_irs<0x4, "add", BinOpFrag<(addc node:$LHS, node:$RHS)>>;
816 defm SUBS : ASI1_bin_s_irs<0x2, "sub", BinOpFrag<(subc node:$LHS, node:$RHS)>>;
818 // FIXME: Do not allow ADC / SBC to be predicated for now.
819 defm ADC : AsXI1_bin_c_irs<0x5, "adc", BinOpFrag<(adde node:$LHS, node:$RHS)>>;
820 defm SBC : AsXI1_bin_c_irs<0x6, "sbc", BinOpFrag<(sube node:$LHS, node:$RHS)>>;
822 // These don't define reg/reg forms, because they are handled above.
823 def RSBri : AsI1<0x3, (outs GPR:$dst), (ins GPR:$a, so_imm:$b), DPRIm,
824 "rsb", " $dst, $a, $b",
825 [(set GPR:$dst, (sub so_imm:$b, GPR:$a))]>;
827 def RSBrs : AsI1<0x3, (outs GPR:$dst), (ins GPR:$a, so_reg:$b), DPRSoReg,
828 "rsb", " $dst, $a, $b",
829 [(set GPR:$dst, (sub so_reg:$b, GPR:$a))]>;
831 // RSB with 's' bit set.
832 let Defs = [CPSR] in {
833 def RSBSri : AI1<0x3, (outs GPR:$dst), (ins GPR:$a, so_imm:$b), DPRIm,
834 "rsb", "s $dst, $a, $b",
835 [(set GPR:$dst, (subc so_imm:$b, GPR:$a))]>;
836 def RSBSrs : AI1<0x3, (outs GPR:$dst), (ins GPR:$a, so_reg:$b), DPRSoReg,
837 "rsb", "s $dst, $a, $b",
838 [(set GPR:$dst, (subc so_reg:$b, GPR:$a))]>;
841 // FIXME: Do not allow RSC to be predicated for now. But they can set CPSR.
842 let Uses = [CPSR] in {
843 def RSCri : AXI1<0x7, (outs GPR:$dst), (ins GPR:$a, so_imm:$b, cc_out:$s),
844 DPRIm, "rsc${s} $dst, $a, $b",
845 [(set GPR:$dst, (sube so_imm:$b, GPR:$a))]>;
846 def RSCrs : AXI1<0x7, (outs GPR:$dst), (ins GPR:$a, so_reg:$b, cc_out:$s),
847 DPRSoReg, "rsc${s} $dst, $a, $b",
848 [(set GPR:$dst, (sube so_reg:$b, GPR:$a))]>;
851 // (sub X, imm) gets canonicalized to (add X, -imm). Match this form.
852 def : ARMPat<(add GPR:$src, so_imm_neg:$imm),
853 (SUBri GPR:$src, so_imm_neg:$imm)>;
855 //def : ARMPat<(addc GPR:$src, so_imm_neg:$imm),
856 // (SUBSri GPR:$src, so_imm_neg:$imm)>;
857 //def : ARMPat<(adde GPR:$src, so_imm_neg:$imm),
858 // (SBCri GPR:$src, so_imm_neg:$imm)>;
860 // Note: These are implemented in C++ code, because they have to generate
861 // ADD/SUBrs instructions, which use a complex pattern that a xform function
863 // (mul X, 2^n+1) -> (add (X << n), X)
864 // (mul X, 2^n-1) -> (rsb X, (X << n))
867 //===----------------------------------------------------------------------===//
868 // Bitwise Instructions.
871 defm AND : AsI1_bin_irs<0x0, "and", BinOpFrag<(and node:$LHS, node:$RHS)>>;
872 defm ORR : AsI1_bin_irs<0xC, "orr", BinOpFrag<(or node:$LHS, node:$RHS)>>;
873 defm EOR : AsI1_bin_irs<0x1, "eor", BinOpFrag<(xor node:$LHS, node:$RHS)>>;
874 defm BIC : AsI1_bin_irs<0xE, "bic", BinOpFrag<(and node:$LHS, (not node:$RHS))>>;
876 def MVNr : AsI1<0xE, (outs GPR:$dst), (ins GPR:$src), DPRdReg,
877 "mvn", " $dst, $src", [(set GPR:$dst, (not GPR:$src))]>;
878 def MVNs : AsI1<0xE, (outs GPR:$dst), (ins so_reg:$src), DPRdSoReg,
879 "mvn", " $dst, $src", [(set GPR:$dst, (not so_reg:$src))]>;
880 let isReMaterializable = 1 in
881 def MVNi : AsI1<0xE, (outs GPR:$dst), (ins so_imm:$imm), DPRdIm,
882 "mvn", " $dst, $imm", [(set GPR:$dst, so_imm_not:$imm)]>;
884 def : ARMPat<(and GPR:$src, so_imm_not:$imm),
885 (BICri GPR:$src, so_imm_not:$imm)>;
887 //===----------------------------------------------------------------------===//
888 // Multiply Instructions.
891 def MUL : AsI<0x0, (outs GPR:$dst), (ins GPR:$a, GPR:$b), MulFrm,
892 "mul", " $dst, $a, $b",
893 [(set GPR:$dst, (mul GPR:$a, GPR:$b))]>;
895 def MLA : AsI<0x2, (outs GPR:$dst), (ins GPR:$a, GPR:$b, GPR:$c),
896 MulFrm, "mla", " $dst, $a, $b, $c",
897 [(set GPR:$dst, (add (mul GPR:$a, GPR:$b), GPR:$c))]>;
899 // Extra precision multiplies with low / high results
900 def SMULL : AsI<0xC, (outs GPR:$ldst, GPR:$hdst), (ins GPR:$a, GPR:$b),
901 MulFrm, "smull", " $ldst, $hdst, $a, $b", []>;
903 def UMULL : AsI<0x8, (outs GPR:$ldst, GPR:$hdst), (ins GPR:$a, GPR:$b),
904 MulFrm, "umull", " $ldst, $hdst, $a, $b", []>;
906 // Multiply + accumulate
907 def SMLAL : AsI<0xE, (outs GPR:$ldst, GPR:$hdst), (ins GPR:$a, GPR:$b),
908 MulFrm, "smlal", " $ldst, $hdst, $a, $b", []>;
910 def UMLAL : AsI<0xA, (outs GPR:$ldst, GPR:$hdst), (ins GPR:$a, GPR:$b),
911 MulFrm, "umlal", " $ldst, $hdst, $a, $b", []>;
913 def UMAAL : AI<0x0, (outs GPR:$ldst, GPR:$hdst), (ins GPR:$a, GPR:$b), MulFrm,
914 "umaal", " $ldst, $hdst, $a, $b", []>,
915 Requires<[IsARM, HasV6]>;
917 // Most significant word multiply
918 def SMMUL : AI<0x0, (outs GPR:$dst), (ins GPR:$a, GPR:$b), MulFrm,
919 "smmul", " $dst, $a, $b",
920 [(set GPR:$dst, (mulhs GPR:$a, GPR:$b))]>,
921 Requires<[IsARM, HasV6]>;
923 def SMMLA : AI<0x0, (outs GPR:$dst), (ins GPR:$a, GPR:$b, GPR:$c), MulFrm,
924 "smmla", " $dst, $a, $b, $c",
925 [(set GPR:$dst, (add (mulhs GPR:$a, GPR:$b), GPR:$c))]>,
926 Requires<[IsARM, HasV6]>;
929 def SMMLS : AI<0x0, (outs GPR:$dst), (ins GPR:$a, GPR:$b, GPR:$c), MulFrm,
930 "smmls", " $dst, $a, $b, $c",
931 [(set GPR:$dst, (sub GPR:$c, (mulhs GPR:$a, GPR:$b)))]>,
932 Requires<[IsARM, HasV6]>;
934 multiclass AI_smul<string opc, PatFrag opnode> {
935 def BB : AI<0x8, (outs GPR:$dst), (ins GPR:$a, GPR:$b), MulSMUL,
936 !strconcat(opc, "bb"), " $dst, $a, $b",
937 [(set GPR:$dst, (opnode (sext_inreg GPR:$a, i16),
938 (sext_inreg GPR:$b, i16)))]>,
939 Requires<[IsARM, HasV5TE]>;
941 def BT : AI<0xC, (outs GPR:$dst), (ins GPR:$a, GPR:$b), MulSMUL,
942 !strconcat(opc, "bt"), " $dst, $a, $b",
943 [(set GPR:$dst, (opnode (sext_inreg GPR:$a, i16),
944 (sra GPR:$b, 16)))]>,
945 Requires<[IsARM, HasV5TE]>;
947 def TB : AI<0xA, (outs GPR:$dst), (ins GPR:$a, GPR:$b), MulSMUL,
948 !strconcat(opc, "tb"), " $dst, $a, $b",
949 [(set GPR:$dst, (opnode (sra GPR:$a, 16),
950 (sext_inreg GPR:$b, i16)))]>,
951 Requires<[IsARM, HasV5TE]>;
953 def TT : AI<0xE, (outs GPR:$dst), (ins GPR:$a, GPR:$b), MulSMUL,
954 !strconcat(opc, "tt"), " $dst, $a, $b",
955 [(set GPR:$dst, (opnode (sra GPR:$a, 16),
956 (sra GPR:$b, 16)))]>,
957 Requires<[IsARM, HasV5TE]>;
959 def WB : AI<0xA, (outs GPR:$dst), (ins GPR:$a, GPR:$b), MulSMULW,
960 !strconcat(opc, "wb"), " $dst, $a, $b",
961 [(set GPR:$dst, (sra (opnode GPR:$a,
962 (sext_inreg GPR:$b, i16)), 16))]>,
963 Requires<[IsARM, HasV5TE]>;
965 def WT : AI<0xE, (outs GPR:$dst), (ins GPR:$a, GPR:$b), MulSMULW,
966 !strconcat(opc, "wt"), " $dst, $a, $b",
967 [(set GPR:$dst, (sra (opnode GPR:$a,
968 (sra GPR:$b, 16)), 16))]>,
969 Requires<[IsARM, HasV5TE]>;
973 multiclass AI_smla<string opc, PatFrag opnode> {
974 def BB : AI<0x8, (outs GPR:$dst), (ins GPR:$a, GPR:$b, GPR:$acc), MulSMLA,
975 !strconcat(opc, "bb"), " $dst, $a, $b, $acc",
976 [(set GPR:$dst, (add GPR:$acc,
977 (opnode (sext_inreg GPR:$a, i16),
978 (sext_inreg GPR:$b, i16))))]>,
979 Requires<[IsARM, HasV5TE]>;
981 def BT : AI<0xC, (outs GPR:$dst), (ins GPR:$a, GPR:$b, GPR:$acc), MulSMLA,
982 !strconcat(opc, "bt"), " $dst, $a, $b, $acc",
983 [(set GPR:$dst, (add GPR:$acc, (opnode (sext_inreg GPR:$a, i16),
984 (sra GPR:$b, 16))))]>,
985 Requires<[IsARM, HasV5TE]>;
987 def TB : AI<0xA, (outs GPR:$dst), (ins GPR:$a, GPR:$b, GPR:$acc), MulSMLA,
988 !strconcat(opc, "tb"), " $dst, $a, $b, $acc",
989 [(set GPR:$dst, (add GPR:$acc, (opnode (sra GPR:$a, 16),
990 (sext_inreg GPR:$b, i16))))]>,
991 Requires<[IsARM, HasV5TE]>;
993 def TT : AI<0xE, (outs GPR:$dst), (ins GPR:$a, GPR:$b, GPR:$acc), MulSMLA,
994 !strconcat(opc, "tt"), " $dst, $a, $b, $acc",
995 [(set GPR:$dst, (add GPR:$acc, (opnode (sra GPR:$a, 16),
996 (sra GPR:$b, 16))))]>,
997 Requires<[IsARM, HasV5TE]>;
999 def WB : AI<0xA, (outs GPR:$dst), (ins GPR:$a, GPR:$b, GPR:$acc), MulSMLAW,
1000 !strconcat(opc, "wb"), " $dst, $a, $b, $acc",
1001 [(set GPR:$dst, (add GPR:$acc, (sra (opnode GPR:$a,
1002 (sext_inreg GPR:$b, i16)), 16)))]>,
1003 Requires<[IsARM, HasV5TE]>;
1005 def WT : AI<0xE, (outs GPR:$dst), (ins GPR:$a, GPR:$b, GPR:$acc), MulSMLAW,
1006 !strconcat(opc, "wt"), " $dst, $a, $b, $acc",
1007 [(set GPR:$dst, (add GPR:$acc, (sra (opnode GPR:$a,
1008 (sra GPR:$b, 16)), 16)))]>,
1009 Requires<[IsARM, HasV5TE]>;
1012 defm SMUL : AI_smul<"smul", BinOpFrag<(mul node:$LHS, node:$RHS)>>;
1013 defm SMLA : AI_smla<"smla", BinOpFrag<(mul node:$LHS, node:$RHS)>>;
1015 // TODO: Halfword multiple accumulate long: SMLAL<x><y>
1016 // TODO: Dual halfword multiple: SMUAD, SMUSD, SMLAD, SMLSD, SMLALD, SMLSLD
1018 //===----------------------------------------------------------------------===//
1019 // Misc. Arithmetic Instructions.
1022 def CLZ : AI<0x0, (outs GPR:$dst), (ins GPR:$src), ArithMisc,
1023 "clz", " $dst, $src",
1024 [(set GPR:$dst, (ctlz GPR:$src))]>, Requires<[IsARM, HasV5T]>;
1026 def REV : AI<0x0, (outs GPR:$dst), (ins GPR:$src), ArithMisc,
1027 "rev", " $dst, $src",
1028 [(set GPR:$dst, (bswap GPR:$src))]>, Requires<[IsARM, HasV6]>;
1030 def REV16 : AI<0x0, (outs GPR:$dst), (ins GPR:$src), ArithMisc,
1031 "rev16", " $dst, $src",
1033 (or (and (srl GPR:$src, 8), 0xFF),
1034 (or (and (shl GPR:$src, 8), 0xFF00),
1035 (or (and (srl GPR:$src, 8), 0xFF0000),
1036 (and (shl GPR:$src, 8), 0xFF000000)))))]>,
1037 Requires<[IsARM, HasV6]>;
1039 def REVSH : AI<0x0, (outs GPR:$dst), (ins GPR:$src), ArithMisc,
1040 "revsh", " $dst, $src",
1043 (or (srl (and GPR:$src, 0xFF00), 8),
1044 (shl GPR:$src, 8)), i16))]>,
1045 Requires<[IsARM, HasV6]>;
1047 def PKHBT : AI<0x0, (outs GPR:$dst), (ins GPR:$src1, GPR:$src2, i32imm:$shamt),
1048 Pseudo, "pkhbt", " $dst, $src1, $src2, LSL $shamt",
1049 [(set GPR:$dst, (or (and GPR:$src1, 0xFFFF),
1050 (and (shl GPR:$src2, (i32 imm:$shamt)),
1052 Requires<[IsARM, HasV6]>;
1054 // Alternate cases for PKHBT where identities eliminate some nodes.
1055 def : ARMV6Pat<(or (and GPR:$src1, 0xFFFF), (and GPR:$src2, 0xFFFF0000)),
1056 (PKHBT GPR:$src1, GPR:$src2, 0)>;
1057 def : ARMV6Pat<(or (and GPR:$src1, 0xFFFF), (shl GPR:$src2, imm16_31:$shamt)),
1058 (PKHBT GPR:$src1, GPR:$src2, imm16_31:$shamt)>;
1061 def PKHTB : AI<0x0, (outs GPR:$dst), (ins GPR:$src1, GPR:$src2, i32imm:$shamt),
1062 Pseudo, "pkhtb", " $dst, $src1, $src2, ASR $shamt",
1063 [(set GPR:$dst, (or (and GPR:$src1, 0xFFFF0000),
1064 (and (sra GPR:$src2, imm16_31:$shamt),
1065 0xFFFF)))]>, Requires<[IsARM, HasV6]>;
1067 // Alternate cases for PKHTB where identities eliminate some nodes. Note that
1068 // a shift amount of 0 is *not legal* here, it is PKHBT instead.
1069 def : ARMV6Pat<(or (and GPR:$src1, 0xFFFF0000), (srl GPR:$src2, 16)),
1070 (PKHTB GPR:$src1, GPR:$src2, 16)>;
1071 def : ARMV6Pat<(or (and GPR:$src1, 0xFFFF0000),
1072 (and (srl GPR:$src2, imm1_15:$shamt), 0xFFFF)),
1073 (PKHTB GPR:$src1, GPR:$src2, imm1_15:$shamt)>;
1076 //===----------------------------------------------------------------------===//
1077 // Comparison Instructions...
1080 defm CMP : AI1_cmp_irs<0xA, "cmp",
1081 BinOpFrag<(ARMcmp node:$LHS, node:$RHS)>>;
1082 defm CMN : AI1_cmp_irs<0xB, "cmn",
1083 BinOpFrag<(ARMcmp node:$LHS,(ineg node:$RHS))>>;
1085 // Note that TST/TEQ don't set all the same flags that CMP does!
1086 defm TST : AI1_cmp_irs<0x8, "tst",
1087 BinOpFrag<(ARMcmpNZ (and node:$LHS, node:$RHS), 0)>>;
1088 defm TEQ : AI1_cmp_irs<0x9, "teq",
1089 BinOpFrag<(ARMcmpNZ (xor node:$LHS, node:$RHS), 0)>>;
1091 defm CMPnz : AI1_cmp_irs<0xA, "cmp",
1092 BinOpFrag<(ARMcmpNZ node:$LHS, node:$RHS)>>;
1093 defm CMNnz : AI1_cmp_irs<0xA, "cmn",
1094 BinOpFrag<(ARMcmpNZ node:$LHS,(ineg node:$RHS))>>;
1096 def : ARMPat<(ARMcmp GPR:$src, so_imm_neg:$imm),
1097 (CMNri GPR:$src, so_imm_neg:$imm)>;
1099 def : ARMPat<(ARMcmpNZ GPR:$src, so_imm_neg:$imm),
1100 (CMNri GPR:$src, so_imm_neg:$imm)>;
1103 // Conditional moves
1104 // FIXME: should be able to write a pattern for ARMcmov, but can't use
1105 // a two-value operand where a dag node expects two operands. :(
1106 def MOVCCr : AI<0xD, (outs GPR:$dst), (ins GPR:$false, GPR:$true),
1107 DPRdReg, "mov", " $dst, $true",
1108 [/*(set GPR:$dst, (ARMcmov GPR:$false, GPR:$true, imm:$cc, CCR:$ccr))*/]>,
1109 RegConstraint<"$false = $dst">;
1111 def MOVCCs : AI<0xD, (outs GPR:$dst), (ins GPR:$false, so_reg:$true),
1112 DPRdSoReg, "mov", " $dst, $true",
1113 [/*(set GPR:$dst, (ARMcmov GPR:$false, so_reg:$true, imm:$cc, CCR:$ccr))*/]>,
1114 RegConstraint<"$false = $dst">;
1116 def MOVCCi : AI<0xD, (outs GPR:$dst), (ins GPR:$false, so_imm:$true),
1117 DPRdIm, "mov", " $dst, $true",
1118 [/*(set GPR:$dst, (ARMcmov GPR:$false, so_imm:$true, imm:$cc, CCR:$ccr))*/]>,
1119 RegConstraint<"$false = $dst">;
1122 // LEApcrel - Load a pc-relative address into a register without offending the
1124 def LEApcrel : AXI1<0x0, (outs GPR:$dst), (ins i32imm:$label, pred:$p), Pseudo,
1125 !strconcat(!strconcat(".set PCRELV${:uid}, ($label-(",
1126 "${:private}PCRELL${:uid}+8))\n"),
1127 !strconcat("${:private}PCRELL${:uid}:\n\t",
1128 "add$p $dst, pc, #PCRELV${:uid}")),
1131 def LEApcrelJT : AXI1<0x0, (outs GPR:$dst), (ins i32imm:$label, i32imm:$id, pred:$p),
1133 !strconcat(!strconcat(".set PCRELV${:uid}, (${label}_${id:no_hash}-(",
1134 "${:private}PCRELL${:uid}+8))\n"),
1135 !strconcat("${:private}PCRELL${:uid}:\n\t",
1136 "add$p $dst, pc, #PCRELV${:uid}")),
1139 //===----------------------------------------------------------------------===//
1143 // __aeabi_read_tp preserves the registers r1-r3.
1145 Defs = [R0, R12, LR, CPSR] in {
1146 def TPsoft : AXI<0x0, (outs), (ins), BranchMisc,
1147 "bl __aeabi_read_tp",
1148 [(set R0, ARMthread_pointer)]>;
1151 //===----------------------------------------------------------------------===//
1152 // Non-Instruction Patterns
1155 // ConstantPool, GlobalAddress, and JumpTable
1156 def : ARMPat<(ARMWrapper tglobaladdr :$dst), (LEApcrel tglobaladdr :$dst)>;
1157 def : ARMPat<(ARMWrapper tconstpool :$dst), (LEApcrel tconstpool :$dst)>;
1158 def : ARMPat<(ARMWrapperJT tjumptable:$dst, imm:$id),
1159 (LEApcrelJT tjumptable:$dst, imm:$id)>;
1161 // Large immediate handling.
1163 // Two piece so_imms.
1164 let isReMaterializable = 1 in
1165 def MOVi2pieces : AI1x2<0x0, (outs GPR:$dst), (ins so_imm2part:$src), DPRdMisc,
1166 "mov", " $dst, $src",
1167 [(set GPR:$dst, so_imm2part:$src)]>;
1169 def : ARMPat<(or GPR:$LHS, so_imm2part:$RHS),
1170 (ORRri (ORRri GPR:$LHS, (so_imm2part_1 imm:$RHS)),
1171 (so_imm2part_2 imm:$RHS))>;
1172 def : ARMPat<(xor GPR:$LHS, so_imm2part:$RHS),
1173 (EORri (EORri GPR:$LHS, (so_imm2part_1 imm:$RHS)),
1174 (so_imm2part_2 imm:$RHS))>;
1176 // TODO: add,sub,and, 3-instr forms?
1180 def : ARMPat<(ARMcall texternalsym:$func), (BL texternalsym:$func)>;
1182 // zextload i1 -> zextload i8
1183 def : ARMPat<(zextloadi1 addrmode2:$addr), (LDRB addrmode2:$addr)>;
1185 // extload -> zextload
1186 def : ARMPat<(extloadi1 addrmode2:$addr), (LDRB addrmode2:$addr)>;
1187 def : ARMPat<(extloadi8 addrmode2:$addr), (LDRB addrmode2:$addr)>;
1188 def : ARMPat<(extloadi16 addrmode3:$addr), (LDRH addrmode3:$addr)>;
1191 def : ARMV5TEPat<(mul (sra (shl GPR:$a, 16), 16), (sra (shl GPR:$b, 16), 16)),
1192 (SMULBB GPR:$a, GPR:$b)>;
1193 def : ARMV5TEPat<(mul sext_16_node:$a, sext_16_node:$b),
1194 (SMULBB GPR:$a, GPR:$b)>;
1195 def : ARMV5TEPat<(mul (sra (shl GPR:$a, 16), 16), (sra GPR:$b, 16)),
1196 (SMULBT GPR:$a, GPR:$b)>;
1197 def : ARMV5TEPat<(mul sext_16_node:$a, (sra GPR:$b, 16)),
1198 (SMULBT GPR:$a, GPR:$b)>;
1199 def : ARMV5TEPat<(mul (sra GPR:$a, 16), (sra (shl GPR:$b, 16), 16)),
1200 (SMULTB GPR:$a, GPR:$b)>;
1201 def : ARMV5TEPat<(mul (sra GPR:$a, 16), sext_16_node:$b),
1202 (SMULTB GPR:$a, GPR:$b)>;
1203 def : ARMV5TEPat<(sra (mul GPR:$a, (sra (shl GPR:$b, 16), 16)), 16),
1204 (SMULWB GPR:$a, GPR:$b)>;
1205 def : ARMV5TEPat<(sra (mul GPR:$a, sext_16_node:$b), 16),
1206 (SMULWB GPR:$a, GPR:$b)>;
1208 def : ARMV5TEPat<(add GPR:$acc,
1209 (mul (sra (shl GPR:$a, 16), 16),
1210 (sra (shl GPR:$b, 16), 16))),
1211 (SMLABB GPR:$a, GPR:$b, GPR:$acc)>;
1212 def : ARMV5TEPat<(add GPR:$acc,
1213 (mul sext_16_node:$a, sext_16_node:$b)),
1214 (SMLABB GPR:$a, GPR:$b, GPR:$acc)>;
1215 def : ARMV5TEPat<(add GPR:$acc,
1216 (mul (sra (shl GPR:$a, 16), 16), (sra GPR:$b, 16))),
1217 (SMLABT GPR:$a, GPR:$b, GPR:$acc)>;
1218 def : ARMV5TEPat<(add GPR:$acc,
1219 (mul sext_16_node:$a, (sra GPR:$b, 16))),
1220 (SMLABT GPR:$a, GPR:$b, GPR:$acc)>;
1221 def : ARMV5TEPat<(add GPR:$acc,
1222 (mul (sra GPR:$a, 16), (sra (shl GPR:$b, 16), 16))),
1223 (SMLATB GPR:$a, GPR:$b, GPR:$acc)>;
1224 def : ARMV5TEPat<(add GPR:$acc,
1225 (mul (sra GPR:$a, 16), sext_16_node:$b)),
1226 (SMLATB GPR:$a, GPR:$b, GPR:$acc)>;
1227 def : ARMV5TEPat<(add GPR:$acc,
1228 (sra (mul GPR:$a, (sra (shl GPR:$b, 16), 16)), 16)),
1229 (SMLAWB GPR:$a, GPR:$b, GPR:$acc)>;
1230 def : ARMV5TEPat<(add GPR:$acc,
1231 (sra (mul GPR:$a, sext_16_node:$b), 16)),
1232 (SMLAWB GPR:$a, GPR:$b, GPR:$acc)>;
1234 //===----------------------------------------------------------------------===//
1238 include "ARMInstrThumb.td"
1240 //===----------------------------------------------------------------------===//
1241 // Floating Point Support
1244 include "ARMInstrVFP.td"