1 //===- ARMInstrInfo.td - Target Description for ARM Target -*- tablegen -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file describes the ARM instructions in TableGen format.
12 //===----------------------------------------------------------------------===//
14 //===----------------------------------------------------------------------===//
15 // ARM specific DAG Nodes.
19 def SDT_ARMCallSeqStart : SDCallSeqStart<[ SDTCisVT<0, i32> ]>;
20 def SDT_ARMCallSeqEnd : SDCallSeqEnd<[ SDTCisVT<0, i32>, SDTCisVT<1, i32> ]>;
22 def SDT_ARMSaveCallPC : SDTypeProfile<0, 1, []>;
24 def SDT_ARMcall : SDTypeProfile<0, -1, [SDTCisInt<0>]>;
26 def SDT_ARMCMov : SDTypeProfile<1, 3,
27 [SDTCisSameAs<0, 1>, SDTCisSameAs<0, 2>,
30 def SDT_ARMBrcond : SDTypeProfile<0, 2,
31 [SDTCisVT<0, OtherVT>, SDTCisVT<1, i32>]>;
33 def SDT_ARMBrJT : SDTypeProfile<0, 3,
34 [SDTCisPtrTy<0>, SDTCisVT<1, i32>,
37 def SDT_ARMBr2JT : SDTypeProfile<0, 4,
38 [SDTCisPtrTy<0>, SDTCisVT<1, i32>,
39 SDTCisVT<2, i32>, SDTCisVT<3, i32>]>;
41 def SDT_ARMCmp : SDTypeProfile<0, 2, [SDTCisSameAs<0, 1>]>;
43 def SDT_ARMPICAdd : SDTypeProfile<1, 2, [SDTCisSameAs<0, 1>,
44 SDTCisPtrTy<1>, SDTCisVT<2, i32>]>;
46 def SDT_ARMThreadPointer : SDTypeProfile<1, 0, [SDTCisPtrTy<0>]>;
47 def SDT_ARMEH_SJLJ_Setjmp : SDTypeProfile<1, 1, [SDTCisInt<0>, SDTCisPtrTy<1>]>;
50 def ARMWrapper : SDNode<"ARMISD::Wrapper", SDTIntUnaryOp>;
51 def ARMWrapperJT : SDNode<"ARMISD::WrapperJT", SDTIntBinOp>;
53 def ARMcallseq_start : SDNode<"ISD::CALLSEQ_START", SDT_ARMCallSeqStart,
54 [SDNPHasChain, SDNPOutFlag]>;
55 def ARMcallseq_end : SDNode<"ISD::CALLSEQ_END", SDT_ARMCallSeqEnd,
56 [SDNPHasChain, SDNPOptInFlag, SDNPOutFlag]>;
58 def ARMcall : SDNode<"ARMISD::CALL", SDT_ARMcall,
59 [SDNPHasChain, SDNPOptInFlag, SDNPOutFlag]>;
60 def ARMcall_pred : SDNode<"ARMISD::CALL_PRED", SDT_ARMcall,
61 [SDNPHasChain, SDNPOptInFlag, SDNPOutFlag]>;
62 def ARMcall_nolink : SDNode<"ARMISD::CALL_NOLINK", SDT_ARMcall,
63 [SDNPHasChain, SDNPOptInFlag, SDNPOutFlag]>;
65 def ARMretflag : SDNode<"ARMISD::RET_FLAG", SDTNone,
66 [SDNPHasChain, SDNPOptInFlag]>;
68 def ARMcmov : SDNode<"ARMISD::CMOV", SDT_ARMCMov,
70 def ARMcneg : SDNode<"ARMISD::CNEG", SDT_ARMCMov,
73 def ARMbrcond : SDNode<"ARMISD::BRCOND", SDT_ARMBrcond,
74 [SDNPHasChain, SDNPInFlag, SDNPOutFlag]>;
76 def ARMbrjt : SDNode<"ARMISD::BR_JT", SDT_ARMBrJT,
78 def ARMbr2jt : SDNode<"ARMISD::BR2_JT", SDT_ARMBr2JT,
81 def ARMcmp : SDNode<"ARMISD::CMP", SDT_ARMCmp,
84 def ARMcmpZ : SDNode<"ARMISD::CMPZ", SDT_ARMCmp,
85 [SDNPOutFlag,SDNPCommutative]>;
87 def ARMpic_add : SDNode<"ARMISD::PIC_ADD", SDT_ARMPICAdd>;
89 def ARMsrl_flag : SDNode<"ARMISD::SRL_FLAG", SDTIntUnaryOp, [SDNPOutFlag]>;
90 def ARMsra_flag : SDNode<"ARMISD::SRA_FLAG", SDTIntUnaryOp, [SDNPOutFlag]>;
91 def ARMrrx : SDNode<"ARMISD::RRX" , SDTIntUnaryOp, [SDNPInFlag ]>;
93 def ARMthread_pointer: SDNode<"ARMISD::THREAD_POINTER", SDT_ARMThreadPointer>;
94 def ARMeh_sjlj_setjmp: SDNode<"ARMISD::EH_SJLJ_SETJMP", SDT_ARMEH_SJLJ_Setjmp>;
96 //===----------------------------------------------------------------------===//
97 // ARM Instruction Predicate Definitions.
99 def HasV5T : Predicate<"Subtarget->hasV5TOps()">;
100 def HasV5TE : Predicate<"Subtarget->hasV5TEOps()">;
101 def HasV6 : Predicate<"Subtarget->hasV6Ops()">;
102 def HasV6T2 : Predicate<"Subtarget->hasV6T2Ops()">;
103 def NoV6T2 : Predicate<"!Subtarget->hasV6T2Ops()">;
104 def HasV7 : Predicate<"Subtarget->hasV7Ops()">;
105 def HasVFP2 : Predicate<"Subtarget->hasVFP2()">;
106 def HasVFP3 : Predicate<"Subtarget->hasVFP3()">;
107 def HasNEON : Predicate<"Subtarget->hasNEON()">;
108 def UseNEONForFP : Predicate<"Subtarget->useNEONForSinglePrecisionFP()">;
109 def DontUseNEONForFP : Predicate<"!Subtarget->useNEONForSinglePrecisionFP()">;
110 def IsThumb : Predicate<"Subtarget->isThumb()">;
111 def IsThumb1Only : Predicate<"Subtarget->isThumb1Only()">;
112 def IsThumb2 : Predicate<"Subtarget->isThumb2()">;
113 def IsARM : Predicate<"!Subtarget->isThumb()">;
114 def IsDarwin : Predicate<"Subtarget->isTargetDarwin()">;
115 def IsNotDarwin : Predicate<"!Subtarget->isTargetDarwin()">;
116 def CarryDefIsUnused : Predicate<"!N.getNode()->hasAnyUseOfValue(1)">;
117 def CarryDefIsUsed : Predicate<"N.getNode()->hasAnyUseOfValue(1)">;
119 //===----------------------------------------------------------------------===//
120 // ARM Flag Definitions.
122 class RegConstraint<string C> {
123 string Constraints = C;
126 //===----------------------------------------------------------------------===//
127 // ARM specific transformation functions and pattern fragments.
130 // so_imm_neg_XFORM - Return a so_imm value packed into the format described for
131 // so_imm_neg def below.
132 def so_imm_neg_XFORM : SDNodeXForm<imm, [{
133 return CurDAG->getTargetConstant(-(int)N->getZExtValue(), MVT::i32);
136 // so_imm_not_XFORM - Return a so_imm value packed into the format described for
137 // so_imm_not def below.
138 def so_imm_not_XFORM : SDNodeXForm<imm, [{
139 return CurDAG->getTargetConstant(~(int)N->getZExtValue(), MVT::i32);
142 // rot_imm predicate - True if the 32-bit immediate is equal to 8, 16, or 24.
143 def rot_imm : PatLeaf<(i32 imm), [{
144 int32_t v = (int32_t)N->getZExtValue();
145 return v == 8 || v == 16 || v == 24;
148 /// imm1_15 predicate - True if the 32-bit immediate is in the range [1,15].
149 def imm1_15 : PatLeaf<(i32 imm), [{
150 return (int32_t)N->getZExtValue() >= 1 && (int32_t)N->getZExtValue() < 16;
153 /// imm16_31 predicate - True if the 32-bit immediate is in the range [16,31].
154 def imm16_31 : PatLeaf<(i32 imm), [{
155 return (int32_t)N->getZExtValue() >= 16 && (int32_t)N->getZExtValue() < 32;
160 return ARM_AM::getSOImmVal(-(int)N->getZExtValue()) != -1;
161 }], so_imm_neg_XFORM>;
165 return ARM_AM::getSOImmVal(~(int)N->getZExtValue()) != -1;
166 }], so_imm_not_XFORM>;
168 // sext_16_node predicate - True if the SDNode is sign-extended 16 or more bits.
169 def sext_16_node : PatLeaf<(i32 GPR:$a), [{
170 return CurDAG->ComputeNumSignBits(SDValue(N,0)) >= 17;
173 /// bf_inv_mask_imm predicate - An AND mask to clear an arbitrary width bitfield
175 def bf_inv_mask_imm : Operand<i32>,
177 uint32_t v = (uint32_t)N->getZExtValue();
180 // there can be 1's on either or both "outsides", all the "inside"
182 unsigned int lsb = 0, msb = 31;
183 while (v & (1 << msb)) --msb;
184 while (v & (1 << lsb)) ++lsb;
185 for (unsigned int i = lsb; i <= msb; ++i) {
191 let PrintMethod = "printBitfieldInvMaskImmOperand";
194 /// Split a 32-bit immediate into two 16 bit parts.
195 def lo16 : SDNodeXForm<imm, [{
196 return CurDAG->getTargetConstant((uint32_t)N->getZExtValue() & 0xffff,
200 def hi16 : SDNodeXForm<imm, [{
201 return CurDAG->getTargetConstant((uint32_t)N->getZExtValue() >> 16, MVT::i32);
204 def lo16AllZero : PatLeaf<(i32 imm), [{
205 // Returns true if all low 16-bits are 0.
206 return (((uint32_t)N->getZExtValue()) & 0xFFFFUL) == 0;
209 /// imm0_65535 predicate - True if the 32-bit immediate is in the range
211 def imm0_65535 : PatLeaf<(i32 imm), [{
212 return (uint32_t)N->getZExtValue() < 65536;
215 class BinOpFrag<dag res> : PatFrag<(ops node:$LHS, node:$RHS), res>;
216 class UnOpFrag <dag res> : PatFrag<(ops node:$Src), res>;
218 //===----------------------------------------------------------------------===//
219 // Operand Definitions.
223 def brtarget : Operand<OtherVT>;
225 // A list of registers separated by comma. Used by load/store multiple.
226 def reglist : Operand<i32> {
227 let PrintMethod = "printRegisterList";
230 // An operand for the CONSTPOOL_ENTRY pseudo-instruction.
231 def cpinst_operand : Operand<i32> {
232 let PrintMethod = "printCPInstOperand";
235 def jtblock_operand : Operand<i32> {
236 let PrintMethod = "printJTBlockOperand";
238 def jt2block_operand : Operand<i32> {
239 let PrintMethod = "printJT2BlockOperand";
243 def pclabel : Operand<i32> {
244 let PrintMethod = "printPCLabel";
247 // shifter_operand operands: so_reg and so_imm.
248 def so_reg : Operand<i32>, // reg reg imm
249 ComplexPattern<i32, 3, "SelectShifterOperandReg",
250 [shl,srl,sra,rotr]> {
251 let PrintMethod = "printSORegOperand";
252 let MIOperandInfo = (ops GPR, GPR, i32imm);
255 // so_imm - Match a 32-bit shifter_operand immediate operand, which is an
256 // 8-bit immediate rotated by an arbitrary number of bits. so_imm values are
257 // represented in the imm field in the same 12-bit form that they are encoded
258 // into so_imm instructions: the 8-bit immediate is the least significant bits
259 // [bits 0-7], the 4-bit shift amount is the next 4 bits [bits 8-11].
260 def so_imm : Operand<i32>,
262 return ARM_AM::getSOImmVal(N->getZExtValue()) != -1;
264 let PrintMethod = "printSOImmOperand";
267 // Break so_imm's up into two pieces. This handles immediates with up to 16
268 // bits set in them. This uses so_imm2part to match and so_imm2part_[12] to
269 // get the first/second pieces.
270 def so_imm2part : Operand<i32>,
272 return ARM_AM::isSOImmTwoPartVal((unsigned)N->getZExtValue());
274 let PrintMethod = "printSOImm2PartOperand";
277 def so_imm2part_1 : SDNodeXForm<imm, [{
278 unsigned V = ARM_AM::getSOImmTwoPartFirst((unsigned)N->getZExtValue());
279 return CurDAG->getTargetConstant(V, MVT::i32);
282 def so_imm2part_2 : SDNodeXForm<imm, [{
283 unsigned V = ARM_AM::getSOImmTwoPartSecond((unsigned)N->getZExtValue());
284 return CurDAG->getTargetConstant(V, MVT::i32);
287 /// imm0_31 predicate - True if the 32-bit immediate is in the range [0,31].
288 def imm0_31 : Operand<i32>, PatLeaf<(imm), [{
289 return (int32_t)N->getZExtValue() < 32;
292 // Define ARM specific addressing modes.
294 // addrmode2 := reg +/- reg shop imm
295 // addrmode2 := reg +/- imm12
297 def addrmode2 : Operand<i32>,
298 ComplexPattern<i32, 3, "SelectAddrMode2", []> {
299 let PrintMethod = "printAddrMode2Operand";
300 let MIOperandInfo = (ops GPR:$base, GPR:$offsreg, i32imm:$offsimm);
303 def am2offset : Operand<i32>,
304 ComplexPattern<i32, 2, "SelectAddrMode2Offset", []> {
305 let PrintMethod = "printAddrMode2OffsetOperand";
306 let MIOperandInfo = (ops GPR, i32imm);
309 // addrmode3 := reg +/- reg
310 // addrmode3 := reg +/- imm8
312 def addrmode3 : Operand<i32>,
313 ComplexPattern<i32, 3, "SelectAddrMode3", []> {
314 let PrintMethod = "printAddrMode3Operand";
315 let MIOperandInfo = (ops GPR:$base, GPR:$offsreg, i32imm:$offsimm);
318 def am3offset : Operand<i32>,
319 ComplexPattern<i32, 2, "SelectAddrMode3Offset", []> {
320 let PrintMethod = "printAddrMode3OffsetOperand";
321 let MIOperandInfo = (ops GPR, i32imm);
324 // addrmode4 := reg, <mode|W>
326 def addrmode4 : Operand<i32>,
327 ComplexPattern<i32, 2, "SelectAddrMode4", []> {
328 let PrintMethod = "printAddrMode4Operand";
329 let MIOperandInfo = (ops GPR, i32imm);
332 // addrmode5 := reg +/- imm8*4
334 def addrmode5 : Operand<i32>,
335 ComplexPattern<i32, 2, "SelectAddrMode5", []> {
336 let PrintMethod = "printAddrMode5Operand";
337 let MIOperandInfo = (ops GPR, i32imm);
340 // addrmode6 := reg with optional writeback
342 def addrmode6 : Operand<i32>,
343 ComplexPattern<i32, 3, "SelectAddrMode6", []> {
344 let PrintMethod = "printAddrMode6Operand";
345 let MIOperandInfo = (ops GPR:$addr, GPR:$upd, i32imm);
348 // addrmodepc := pc + reg
350 def addrmodepc : Operand<i32>,
351 ComplexPattern<i32, 2, "SelectAddrModePC", []> {
352 let PrintMethod = "printAddrModePCOperand";
353 let MIOperandInfo = (ops GPR, i32imm);
356 def nohash_imm : Operand<i32> {
357 let PrintMethod = "printNoHashImmediate";
360 //===----------------------------------------------------------------------===//
362 include "ARMInstrFormats.td"
364 //===----------------------------------------------------------------------===//
365 // Multiclass helpers...
368 /// AsI1_bin_irs - Defines a set of (op r, {so_imm|r|so_reg}) patterns for a
369 /// binop that produces a value.
370 multiclass AsI1_bin_irs<bits<4> opcod, string opc, PatFrag opnode,
371 bit Commutable = 0> {
372 def ri : AsI1<opcod, (outs GPR:$dst), (ins GPR:$a, so_imm:$b), DPFrm,
373 IIC_iALUi, opc, " $dst, $a, $b",
374 [(set GPR:$dst, (opnode GPR:$a, so_imm:$b))]> {
377 def rr : AsI1<opcod, (outs GPR:$dst), (ins GPR:$a, GPR:$b), DPFrm,
378 IIC_iALUr, opc, " $dst, $a, $b",
379 [(set GPR:$dst, (opnode GPR:$a, GPR:$b))]> {
381 let isCommutable = Commutable;
383 def rs : AsI1<opcod, (outs GPR:$dst), (ins GPR:$a, so_reg:$b), DPSoRegFrm,
384 IIC_iALUsr, opc, " $dst, $a, $b",
385 [(set GPR:$dst, (opnode GPR:$a, so_reg:$b))]> {
390 /// AI1_bin_s_irs - Similar to AsI1_bin_irs except it sets the 's' bit so the
391 /// instruction modifies the CPSR register.
392 let Defs = [CPSR] in {
393 multiclass AI1_bin_s_irs<bits<4> opcod, string opc, PatFrag opnode,
394 bit Commutable = 0> {
395 def ri : AI1<opcod, (outs GPR:$dst), (ins GPR:$a, so_imm:$b), DPFrm,
396 IIC_iALUi, opc, "s $dst, $a, $b",
397 [(set GPR:$dst, (opnode GPR:$a, so_imm:$b))]> {
400 def rr : AI1<opcod, (outs GPR:$dst), (ins GPR:$a, GPR:$b), DPFrm,
401 IIC_iALUr, opc, "s $dst, $a, $b",
402 [(set GPR:$dst, (opnode GPR:$a, GPR:$b))]> {
403 let isCommutable = Commutable;
406 def rs : AI1<opcod, (outs GPR:$dst), (ins GPR:$a, so_reg:$b), DPSoRegFrm,
407 IIC_iALUsr, opc, "s $dst, $a, $b",
408 [(set GPR:$dst, (opnode GPR:$a, so_reg:$b))]> {
414 /// AI1_cmp_irs - Defines a set of (op r, {so_imm|r|so_reg}) cmp / test
415 /// patterns. Similar to AsI1_bin_irs except the instruction does not produce
416 /// a explicit result, only implicitly set CPSR.
417 let Defs = [CPSR] in {
418 multiclass AI1_cmp_irs<bits<4> opcod, string opc, PatFrag opnode,
419 bit Commutable = 0> {
420 def ri : AI1<opcod, (outs), (ins GPR:$a, so_imm:$b), DPFrm, IIC_iCMPi,
422 [(opnode GPR:$a, so_imm:$b)]> {
426 def rr : AI1<opcod, (outs), (ins GPR:$a, GPR:$b), DPFrm, IIC_iCMPr,
428 [(opnode GPR:$a, GPR:$b)]> {
431 let isCommutable = Commutable;
433 def rs : AI1<opcod, (outs), (ins GPR:$a, so_reg:$b), DPSoRegFrm, IIC_iCMPsr,
435 [(opnode GPR:$a, so_reg:$b)]> {
442 /// AI_unary_rrot - A unary operation with two forms: one whose operand is a
443 /// register and one whose operand is a register rotated by 8/16/24.
444 /// FIXME: Remove the 'r' variant. Its rot_imm is zero.
445 multiclass AI_unary_rrot<bits<8> opcod, string opc, PatFrag opnode> {
446 def r : AExtI<opcod, (outs GPR:$dst), (ins GPR:$src),
447 IIC_iUNAr, opc, " $dst, $src",
448 [(set GPR:$dst, (opnode GPR:$src))]>,
449 Requires<[IsARM, HasV6]> {
450 let Inst{19-16} = 0b1111;
452 def r_rot : AExtI<opcod, (outs GPR:$dst), (ins GPR:$src, i32imm:$rot),
453 IIC_iUNAsi, opc, " $dst, $src, ror $rot",
454 [(set GPR:$dst, (opnode (rotr GPR:$src, rot_imm:$rot)))]>,
455 Requires<[IsARM, HasV6]> {
456 let Inst{19-16} = 0b1111;
460 /// AI_bin_rrot - A binary operation with two forms: one whose operand is a
461 /// register and one whose operand is a register rotated by 8/16/24.
462 multiclass AI_bin_rrot<bits<8> opcod, string opc, PatFrag opnode> {
463 def rr : AExtI<opcod, (outs GPR:$dst), (ins GPR:$LHS, GPR:$RHS),
464 IIC_iALUr, opc, " $dst, $LHS, $RHS",
465 [(set GPR:$dst, (opnode GPR:$LHS, GPR:$RHS))]>,
466 Requires<[IsARM, HasV6]>;
467 def rr_rot : AExtI<opcod, (outs GPR:$dst), (ins GPR:$LHS, GPR:$RHS, i32imm:$rot),
468 IIC_iALUsi, opc, " $dst, $LHS, $RHS, ror $rot",
469 [(set GPR:$dst, (opnode GPR:$LHS,
470 (rotr GPR:$RHS, rot_imm:$rot)))]>,
471 Requires<[IsARM, HasV6]>;
474 /// AI1_adde_sube_irs - Define instructions and patterns for adde and sube.
475 let Uses = [CPSR] in {
476 multiclass AI1_adde_sube_irs<bits<4> opcod, string opc, PatFrag opnode,
477 bit Commutable = 0> {
478 def ri : AsI1<opcod, (outs GPR:$dst), (ins GPR:$a, so_imm:$b),
479 DPFrm, IIC_iALUi, opc, " $dst, $a, $b",
480 [(set GPR:$dst, (opnode GPR:$a, so_imm:$b))]>,
481 Requires<[IsARM, CarryDefIsUnused]> {
484 def rr : AsI1<opcod, (outs GPR:$dst), (ins GPR:$a, GPR:$b),
485 DPFrm, IIC_iALUr, opc, " $dst, $a, $b",
486 [(set GPR:$dst, (opnode GPR:$a, GPR:$b))]>,
487 Requires<[IsARM, CarryDefIsUnused]> {
488 let isCommutable = Commutable;
491 def rs : AsI1<opcod, (outs GPR:$dst), (ins GPR:$a, so_reg:$b),
492 DPSoRegFrm, IIC_iALUsr, opc, " $dst, $a, $b",
493 [(set GPR:$dst, (opnode GPR:$a, so_reg:$b))]>,
494 Requires<[IsARM, CarryDefIsUnused]> {
497 // Carry setting variants
498 def Sri : AXI1<opcod, (outs GPR:$dst), (ins GPR:$a, so_imm:$b),
499 DPFrm, IIC_iALUi, !strconcat(opc, "s $dst, $a, $b"),
500 [(set GPR:$dst, (opnode GPR:$a, so_imm:$b))]>,
501 Requires<[IsARM, CarryDefIsUsed]> {
505 def Srr : AXI1<opcod, (outs GPR:$dst), (ins GPR:$a, GPR:$b),
506 DPFrm, IIC_iALUr, !strconcat(opc, "s $dst, $a, $b"),
507 [(set GPR:$dst, (opnode GPR:$a, GPR:$b))]>,
508 Requires<[IsARM, CarryDefIsUsed]> {
512 def Srs : AXI1<opcod, (outs GPR:$dst), (ins GPR:$a, so_reg:$b),
513 DPSoRegFrm, IIC_iALUsr, !strconcat(opc, "s $dst, $a, $b"),
514 [(set GPR:$dst, (opnode GPR:$a, so_reg:$b))]>,
515 Requires<[IsARM, CarryDefIsUsed]> {
522 //===----------------------------------------------------------------------===//
524 //===----------------------------------------------------------------------===//
526 //===----------------------------------------------------------------------===//
527 // Miscellaneous Instructions.
530 /// CONSTPOOL_ENTRY - This instruction represents a floating constant pool in
531 /// the function. The first operand is the ID# for this instruction, the second
532 /// is the index into the MachineConstantPool that this is, the third is the
533 /// size in bytes of this constant pool entry.
534 let neverHasSideEffects = 1, isNotDuplicable = 1 in
535 def CONSTPOOL_ENTRY :
536 PseudoInst<(outs), (ins cpinst_operand:$instid, cpinst_operand:$cpidx,
537 i32imm:$size), NoItinerary,
538 "${instid:label} ${cpidx:cpentry}", []>;
540 let Defs = [SP], Uses = [SP] in {
542 PseudoInst<(outs), (ins i32imm:$amt1, i32imm:$amt2, pred:$p), NoItinerary,
543 "@ ADJCALLSTACKUP $amt1",
544 [(ARMcallseq_end timm:$amt1, timm:$amt2)]>;
546 def ADJCALLSTACKDOWN :
547 PseudoInst<(outs), (ins i32imm:$amt, pred:$p), NoItinerary,
548 "@ ADJCALLSTACKDOWN $amt",
549 [(ARMcallseq_start timm:$amt)]>;
553 PseudoInst<(outs), (ins i32imm:$line, i32imm:$col, i32imm:$file), NoItinerary,
554 ".loc $file, $line, $col",
555 [(dwarf_loc (i32 imm:$line), (i32 imm:$col), (i32 imm:$file))]>;
558 // Address computation and loads and stores in PIC mode.
559 let isNotDuplicable = 1 in {
560 def PICADD : AXI1<0b0100, (outs GPR:$dst), (ins GPR:$a, pclabel:$cp, pred:$p),
561 Pseudo, IIC_iALUr, "\n$cp:\n\tadd$p $dst, pc, $a",
562 [(set GPR:$dst, (ARMpic_add GPR:$a, imm:$cp))]>;
564 let AddedComplexity = 10 in {
565 let canFoldAsLoad = 1 in
566 def PICLDR : AXI2ldw<(outs GPR:$dst), (ins addrmodepc:$addr, pred:$p),
567 Pseudo, IIC_iLoadr, "\n${addr:label}:\n\tldr$p $dst, $addr",
568 [(set GPR:$dst, (load addrmodepc:$addr))]>;
570 def PICLDRH : AXI3ldh<(outs GPR:$dst), (ins addrmodepc:$addr, pred:$p),
571 Pseudo, IIC_iLoadr, "\n${addr:label}:\n\tldr${p}h $dst, $addr",
572 [(set GPR:$dst, (zextloadi16 addrmodepc:$addr))]>;
574 def PICLDRB : AXI2ldb<(outs GPR:$dst), (ins addrmodepc:$addr, pred:$p),
575 Pseudo, IIC_iLoadr, "\n${addr:label}:\n\tldr${p}b $dst, $addr",
576 [(set GPR:$dst, (zextloadi8 addrmodepc:$addr))]>;
578 def PICLDRSH : AXI3ldsh<(outs GPR:$dst), (ins addrmodepc:$addr, pred:$p),
579 Pseudo, IIC_iLoadr, "\n${addr:label}:\n\tldr${p}sh $dst, $addr",
580 [(set GPR:$dst, (sextloadi16 addrmodepc:$addr))]>;
582 def PICLDRSB : AXI3ldsb<(outs GPR:$dst), (ins addrmodepc:$addr, pred:$p),
583 Pseudo, IIC_iLoadr, "\n${addr:label}:\n\tldr${p}sb $dst, $addr",
584 [(set GPR:$dst, (sextloadi8 addrmodepc:$addr))]>;
586 let AddedComplexity = 10 in {
587 def PICSTR : AXI2stw<(outs), (ins GPR:$src, addrmodepc:$addr, pred:$p),
588 Pseudo, IIC_iStorer, "\n${addr:label}:\n\tstr$p $src, $addr",
589 [(store GPR:$src, addrmodepc:$addr)]>;
591 def PICSTRH : AXI3sth<(outs), (ins GPR:$src, addrmodepc:$addr, pred:$p),
592 Pseudo, IIC_iStorer, "\n${addr:label}:\n\tstr${p}h $src, $addr",
593 [(truncstorei16 GPR:$src, addrmodepc:$addr)]>;
595 def PICSTRB : AXI2stb<(outs), (ins GPR:$src, addrmodepc:$addr, pred:$p),
596 Pseudo, IIC_iStorer, "\n${addr:label}:\n\tstr${p}b $src, $addr",
597 [(truncstorei8 GPR:$src, addrmodepc:$addr)]>;
599 } // isNotDuplicable = 1
602 // LEApcrel - Load a pc-relative address into a register without offending the
604 def LEApcrel : AXI1<0x0, (outs GPR:$dst), (ins i32imm:$label, pred:$p),
606 !strconcat(!strconcat(".set ${:private}PCRELV${:uid}, ($label-(",
607 "${:private}PCRELL${:uid}+8))\n"),
608 !strconcat("${:private}PCRELL${:uid}:\n\t",
609 "add$p $dst, pc, #${:private}PCRELV${:uid}")),
612 def LEApcrelJT : AXI1<0x0, (outs GPR:$dst),
613 (ins i32imm:$label, nohash_imm:$id, pred:$p),
615 !strconcat(!strconcat(".set ${:private}PCRELV${:uid}, "
617 "${:private}PCRELL${:uid}+8))\n"),
618 !strconcat("${:private}PCRELL${:uid}:\n\t",
619 "add$p $dst, pc, #${:private}PCRELV${:uid}")),
624 //===----------------------------------------------------------------------===//
625 // Control Flow Instructions.
628 let isReturn = 1, isTerminator = 1, isBarrier = 1 in
629 def BX_RET : AI<(outs), (ins), BrMiscFrm, IIC_Br,
630 "bx", " lr", [(ARMretflag)]> {
631 let Inst{7-4} = 0b0001;
632 let Inst{19-8} = 0b111111111111;
633 let Inst{27-20} = 0b00010010;
636 // FIXME: remove when we have a way to marking a MI with these properties.
637 // FIXME: Should pc be an implicit operand like PICADD, etc?
638 let isReturn = 1, isTerminator = 1, isBarrier = 1, mayLoad = 1,
639 hasExtraDefRegAllocReq = 1 in
640 def LDM_RET : AXI4ld<(outs),
641 (ins addrmode4:$addr, pred:$p, reglist:$wb, variable_ops),
642 LdStMulFrm, IIC_Br, "ldm${p}${addr:submode} $addr, $wb",
645 // On non-Darwin platforms R9 is callee-saved.
647 Defs = [R0, R1, R2, R3, R12, LR,
648 D0, D1, D2, D3, D4, D5, D6, D7,
649 D16, D17, D18, D19, D20, D21, D22, D23,
650 D24, D25, D26, D27, D28, D29, D30, D31, CPSR, FPSCR] in {
651 def BL : ABXI<0b1011, (outs), (ins i32imm:$func, variable_ops),
652 IIC_Br, "bl ${func:call}",
653 [(ARMcall tglobaladdr:$func)]>,
654 Requires<[IsARM, IsNotDarwin]>;
656 def BL_pred : ABI<0b1011, (outs), (ins i32imm:$func, variable_ops),
657 IIC_Br, "bl", " ${func:call}",
658 [(ARMcall_pred tglobaladdr:$func)]>,
659 Requires<[IsARM, IsNotDarwin]>;
662 def BLX : AXI<(outs), (ins GPR:$func, variable_ops), BrMiscFrm,
664 [(ARMcall GPR:$func)]>,
665 Requires<[IsARM, HasV5T, IsNotDarwin]> {
666 let Inst{7-4} = 0b0011;
667 let Inst{19-8} = 0b111111111111;
668 let Inst{27-20} = 0b00010010;
672 def BX : ABXIx2<(outs), (ins GPR:$func, variable_ops),
673 IIC_Br, "mov lr, pc\n\tbx $func",
674 [(ARMcall_nolink GPR:$func)]>,
675 Requires<[IsARM, IsNotDarwin]> {
676 let Inst{7-4} = 0b0001;
677 let Inst{19-8} = 0b111111111111;
678 let Inst{27-20} = 0b00010010;
682 // On Darwin R9 is call-clobbered.
684 Defs = [R0, R1, R2, R3, R9, R12, LR,
685 D0, D1, D2, D3, D4, D5, D6, D7,
686 D16, D17, D18, D19, D20, D21, D22, D23,
687 D24, D25, D26, D27, D28, D29, D30, D31, CPSR, FPSCR] in {
688 def BLr9 : ABXI<0b1011, (outs), (ins i32imm:$func, variable_ops),
689 IIC_Br, "bl ${func:call}",
690 [(ARMcall tglobaladdr:$func)]>, Requires<[IsARM, IsDarwin]>;
692 def BLr9_pred : ABI<0b1011, (outs), (ins i32imm:$func, variable_ops),
693 IIC_Br, "bl", " ${func:call}",
694 [(ARMcall_pred tglobaladdr:$func)]>,
695 Requires<[IsARM, IsDarwin]>;
698 def BLXr9 : AXI<(outs), (ins GPR:$func, variable_ops), BrMiscFrm,
700 [(ARMcall GPR:$func)]>, Requires<[IsARM, HasV5T, IsDarwin]> {
701 let Inst{7-4} = 0b0011;
702 let Inst{19-8} = 0b111111111111;
703 let Inst{27-20} = 0b00010010;
707 def BXr9 : ABXIx2<(outs), (ins GPR:$func, variable_ops),
708 IIC_Br, "mov lr, pc\n\tbx $func",
709 [(ARMcall_nolink GPR:$func)]>, Requires<[IsARM, IsDarwin]> {
710 let Inst{7-4} = 0b0001;
711 let Inst{19-8} = 0b111111111111;
712 let Inst{27-20} = 0b00010010;
716 let isBranch = 1, isTerminator = 1 in {
717 // B is "predicable" since it can be xformed into a Bcc.
718 let isBarrier = 1 in {
719 let isPredicable = 1 in
720 def B : ABXI<0b1010, (outs), (ins brtarget:$target), IIC_Br,
721 "b $target", [(br bb:$target)]>;
723 let isNotDuplicable = 1, isIndirectBranch = 1 in {
724 def BR_JTr : JTI<(outs), (ins GPR:$target, jtblock_operand:$jt, i32imm:$id),
725 IIC_Br, "mov pc, $target \n$jt",
726 [(ARMbrjt GPR:$target, tjumptable:$jt, imm:$id)]> {
727 let Inst{20} = 0; // S Bit
728 let Inst{24-21} = 0b1101;
729 let Inst{27-25} = 0b000;
731 def BR_JTm : JTI<(outs),
732 (ins addrmode2:$target, jtblock_operand:$jt, i32imm:$id),
733 IIC_Br, "ldr pc, $target \n$jt",
734 [(ARMbrjt (i32 (load addrmode2:$target)), tjumptable:$jt,
736 let Inst{20} = 1; // L bit
737 let Inst{21} = 0; // W bit
738 let Inst{22} = 0; // B bit
739 let Inst{24} = 1; // P bit
740 let Inst{27-25} = 0b011;
742 def BR_JTadd : JTI<(outs),
743 (ins GPR:$target, GPR:$idx, jtblock_operand:$jt, i32imm:$id),
744 IIC_Br, "add pc, $target, $idx \n$jt",
745 [(ARMbrjt (add GPR:$target, GPR:$idx), tjumptable:$jt,
747 let Inst{20} = 0; // S bit
748 let Inst{24-21} = 0b0100;
749 let Inst{27-25} = 0b000;
751 } // isNotDuplicable = 1, isIndirectBranch = 1
754 // FIXME: should be able to write a pattern for ARMBrcond, but can't use
755 // a two-value operand where a dag node expects two operands. :(
756 def Bcc : ABI<0b1010, (outs), (ins brtarget:$target),
757 IIC_Br, "b", " $target",
758 [/*(ARMbrcond bb:$target, imm:$cc, CCR:$ccr)*/]>;
761 //===----------------------------------------------------------------------===//
762 // Load / store Instructions.
766 let canFoldAsLoad = 1, isReMaterializable = 1 in
767 def LDR : AI2ldw<(outs GPR:$dst), (ins addrmode2:$addr), LdFrm, IIC_iLoadr,
768 "ldr", " $dst, $addr",
769 [(set GPR:$dst, (load addrmode2:$addr))]>;
771 // Special LDR for loads from non-pc-relative constpools.
772 let canFoldAsLoad = 1, mayLoad = 1, isReMaterializable = 1 in
773 def LDRcp : AI2ldw<(outs GPR:$dst), (ins addrmode2:$addr), LdFrm, IIC_iLoadr,
774 "ldr", " $dst, $addr", []>;
776 // Loads with zero extension
777 def LDRH : AI3ldh<(outs GPR:$dst), (ins addrmode3:$addr), LdMiscFrm,
778 IIC_iLoadr, "ldr", "h $dst, $addr",
779 [(set GPR:$dst, (zextloadi16 addrmode3:$addr))]>;
781 def LDRB : AI2ldb<(outs GPR:$dst), (ins addrmode2:$addr), LdFrm,
782 IIC_iLoadr, "ldr", "b $dst, $addr",
783 [(set GPR:$dst, (zextloadi8 addrmode2:$addr))]>;
785 // Loads with sign extension
786 def LDRSH : AI3ldsh<(outs GPR:$dst), (ins addrmode3:$addr), LdMiscFrm,
787 IIC_iLoadr, "ldr", "sh $dst, $addr",
788 [(set GPR:$dst, (sextloadi16 addrmode3:$addr))]>;
790 def LDRSB : AI3ldsb<(outs GPR:$dst), (ins addrmode3:$addr), LdMiscFrm,
791 IIC_iLoadr, "ldr", "sb $dst, $addr",
792 [(set GPR:$dst, (sextloadi8 addrmode3:$addr))]>;
794 let mayLoad = 1, hasExtraDefRegAllocReq = 1 in {
796 def LDRD : AI3ldd<(outs GPR:$dst1, GPR:$dst2), (ins addrmode3:$addr), LdMiscFrm,
797 IIC_iLoadr, "ldr", "d $dst1, $addr",
798 []>, Requires<[IsARM, HasV5TE]>;
801 def LDR_PRE : AI2ldwpr<(outs GPR:$dst, GPR:$base_wb),
802 (ins addrmode2:$addr), LdFrm, IIC_iLoadru,
803 "ldr", " $dst, $addr!", "$addr.base = $base_wb", []>;
805 def LDR_POST : AI2ldwpo<(outs GPR:$dst, GPR:$base_wb),
806 (ins GPR:$base, am2offset:$offset), LdFrm, IIC_iLoadru,
807 "ldr", " $dst, [$base], $offset", "$base = $base_wb", []>;
809 def LDRH_PRE : AI3ldhpr<(outs GPR:$dst, GPR:$base_wb),
810 (ins addrmode3:$addr), LdMiscFrm, IIC_iLoadru,
811 "ldr", "h $dst, $addr!", "$addr.base = $base_wb", []>;
813 def LDRH_POST : AI3ldhpo<(outs GPR:$dst, GPR:$base_wb),
814 (ins GPR:$base,am3offset:$offset), LdMiscFrm, IIC_iLoadru,
815 "ldr", "h $dst, [$base], $offset", "$base = $base_wb", []>;
817 def LDRB_PRE : AI2ldbpr<(outs GPR:$dst, GPR:$base_wb),
818 (ins addrmode2:$addr), LdFrm, IIC_iLoadru,
819 "ldr", "b $dst, $addr!", "$addr.base = $base_wb", []>;
821 def LDRB_POST : AI2ldbpo<(outs GPR:$dst, GPR:$base_wb),
822 (ins GPR:$base,am2offset:$offset), LdFrm, IIC_iLoadru,
823 "ldr", "b $dst, [$base], $offset", "$base = $base_wb", []>;
825 def LDRSH_PRE : AI3ldshpr<(outs GPR:$dst, GPR:$base_wb),
826 (ins addrmode3:$addr), LdMiscFrm, IIC_iLoadru,
827 "ldr", "sh $dst, $addr!", "$addr.base = $base_wb", []>;
829 def LDRSH_POST: AI3ldshpo<(outs GPR:$dst, GPR:$base_wb),
830 (ins GPR:$base,am3offset:$offset), LdMiscFrm, IIC_iLoadru,
831 "ldr", "sh $dst, [$base], $offset", "$base = $base_wb", []>;
833 def LDRSB_PRE : AI3ldsbpr<(outs GPR:$dst, GPR:$base_wb),
834 (ins addrmode3:$addr), LdMiscFrm, IIC_iLoadru,
835 "ldr", "sb $dst, $addr!", "$addr.base = $base_wb", []>;
837 def LDRSB_POST: AI3ldsbpo<(outs GPR:$dst, GPR:$base_wb),
838 (ins GPR:$base,am3offset:$offset), LdMiscFrm, IIC_iLoadru,
839 "ldr", "sb $dst, [$base], $offset", "$base = $base_wb", []>;
843 def STR : AI2stw<(outs), (ins GPR:$src, addrmode2:$addr), StFrm, IIC_iStorer,
844 "str", " $src, $addr",
845 [(store GPR:$src, addrmode2:$addr)]>;
847 // Stores with truncate
848 def STRH : AI3sth<(outs), (ins GPR:$src, addrmode3:$addr), StMiscFrm, IIC_iStorer,
849 "str", "h $src, $addr",
850 [(truncstorei16 GPR:$src, addrmode3:$addr)]>;
852 def STRB : AI2stb<(outs), (ins GPR:$src, addrmode2:$addr), StFrm, IIC_iStorer,
853 "str", "b $src, $addr",
854 [(truncstorei8 GPR:$src, addrmode2:$addr)]>;
857 let mayStore = 1, hasExtraSrcRegAllocReq = 1 in
858 def STRD : AI3std<(outs), (ins GPR:$src1, GPR:$src2, addrmode3:$addr),
859 StMiscFrm, IIC_iStorer,
860 "str", "d $src1, $addr", []>, Requires<[IsARM, HasV5TE]>;
863 def STR_PRE : AI2stwpr<(outs GPR:$base_wb),
864 (ins GPR:$src, GPR:$base, am2offset:$offset),
866 "str", " $src, [$base, $offset]!", "$base = $base_wb",
868 (pre_store GPR:$src, GPR:$base, am2offset:$offset))]>;
870 def STR_POST : AI2stwpo<(outs GPR:$base_wb),
871 (ins GPR:$src, GPR:$base,am2offset:$offset),
873 "str", " $src, [$base], $offset", "$base = $base_wb",
875 (post_store GPR:$src, GPR:$base, am2offset:$offset))]>;
877 def STRH_PRE : AI3sthpr<(outs GPR:$base_wb),
878 (ins GPR:$src, GPR:$base,am3offset:$offset),
879 StMiscFrm, IIC_iStoreru,
880 "str", "h $src, [$base, $offset]!", "$base = $base_wb",
882 (pre_truncsti16 GPR:$src, GPR:$base,am3offset:$offset))]>;
884 def STRH_POST: AI3sthpo<(outs GPR:$base_wb),
885 (ins GPR:$src, GPR:$base,am3offset:$offset),
886 StMiscFrm, IIC_iStoreru,
887 "str", "h $src, [$base], $offset", "$base = $base_wb",
888 [(set GPR:$base_wb, (post_truncsti16 GPR:$src,
889 GPR:$base, am3offset:$offset))]>;
891 def STRB_PRE : AI2stbpr<(outs GPR:$base_wb),
892 (ins GPR:$src, GPR:$base,am2offset:$offset),
894 "str", "b $src, [$base, $offset]!", "$base = $base_wb",
895 [(set GPR:$base_wb, (pre_truncsti8 GPR:$src,
896 GPR:$base, am2offset:$offset))]>;
898 def STRB_POST: AI2stbpo<(outs GPR:$base_wb),
899 (ins GPR:$src, GPR:$base,am2offset:$offset),
901 "str", "b $src, [$base], $offset", "$base = $base_wb",
902 [(set GPR:$base_wb, (post_truncsti8 GPR:$src,
903 GPR:$base, am2offset:$offset))]>;
905 //===----------------------------------------------------------------------===//
906 // Load / store multiple Instructions.
909 let mayLoad = 1, hasExtraDefRegAllocReq = 1 in
910 def LDM : AXI4ld<(outs),
911 (ins addrmode4:$addr, pred:$p, reglist:$wb, variable_ops),
912 LdStMulFrm, IIC_iLoadm, "ldm${p}${addr:submode} $addr, $wb",
915 let mayStore = 1, hasExtraSrcRegAllocReq = 1 in
916 def STM : AXI4st<(outs),
917 (ins addrmode4:$addr, pred:$p, reglist:$wb, variable_ops),
918 LdStMulFrm, IIC_iStorem, "stm${p}${addr:submode} $addr, $wb",
921 //===----------------------------------------------------------------------===//
922 // Move Instructions.
925 let neverHasSideEffects = 1 in
926 def MOVr : AsI1<0b1101, (outs GPR:$dst), (ins GPR:$src), DPFrm, IIC_iMOVr,
927 "mov", " $dst, $src", []>, UnaryDP;
928 def MOVs : AsI1<0b1101, (outs GPR:$dst), (ins so_reg:$src),
929 DPSoRegFrm, IIC_iMOVsr,
930 "mov", " $dst, $src", [(set GPR:$dst, so_reg:$src)]>, UnaryDP;
932 let isReMaterializable = 1, isAsCheapAsAMove = 1 in
933 def MOVi : AsI1<0b1101, (outs GPR:$dst), (ins so_imm:$src), DPFrm, IIC_iMOVi,
934 "mov", " $dst, $src", [(set GPR:$dst, so_imm:$src)]>, UnaryDP {
938 let isReMaterializable = 1, isAsCheapAsAMove = 1 in
939 def MOVi16 : AI1<0b1000, (outs GPR:$dst), (ins i32imm:$src),
941 "movw", " $dst, $src",
942 [(set GPR:$dst, imm0_65535:$src)]>,
943 Requires<[IsARM, HasV6T2]> {
948 let Constraints = "$src = $dst" in
949 def MOVTi16 : AI1<0b1010, (outs GPR:$dst), (ins GPR:$src, i32imm:$imm),
951 "movt", " $dst, $imm",
953 (or (and GPR:$src, 0xffff),
954 lo16AllZero:$imm))]>, UnaryDP,
955 Requires<[IsARM, HasV6T2]> {
961 def MOVrx : AsI1<0b1101, (outs GPR:$dst), (ins GPR:$src), Pseudo, IIC_iMOVsi,
962 "mov", " $dst, $src, rrx",
963 [(set GPR:$dst, (ARMrrx GPR:$src))]>, UnaryDP;
965 // These aren't really mov instructions, but we have to define them this way
966 // due to flag operands.
968 let Defs = [CPSR] in {
969 def MOVsrl_flag : AI1<0b1101, (outs GPR:$dst), (ins GPR:$src), Pseudo,
970 IIC_iMOVsi, "mov", "s $dst, $src, lsr #1",
971 [(set GPR:$dst, (ARMsrl_flag GPR:$src))]>, UnaryDP;
972 def MOVsra_flag : AI1<0b1101, (outs GPR:$dst), (ins GPR:$src), Pseudo,
973 IIC_iMOVsi, "mov", "s $dst, $src, asr #1",
974 [(set GPR:$dst, (ARMsra_flag GPR:$src))]>, UnaryDP;
977 //===----------------------------------------------------------------------===//
978 // Extend Instructions.
983 defm SXTB : AI_unary_rrot<0b01101010,
984 "sxtb", UnOpFrag<(sext_inreg node:$Src, i8)>>;
985 defm SXTH : AI_unary_rrot<0b01101011,
986 "sxth", UnOpFrag<(sext_inreg node:$Src, i16)>>;
988 defm SXTAB : AI_bin_rrot<0b01101010,
989 "sxtab", BinOpFrag<(add node:$LHS, (sext_inreg node:$RHS, i8))>>;
990 defm SXTAH : AI_bin_rrot<0b01101011,
991 "sxtah", BinOpFrag<(add node:$LHS, (sext_inreg node:$RHS,i16))>>;
993 // TODO: SXT(A){B|H}16
997 let AddedComplexity = 16 in {
998 defm UXTB : AI_unary_rrot<0b01101110,
999 "uxtb" , UnOpFrag<(and node:$Src, 0x000000FF)>>;
1000 defm UXTH : AI_unary_rrot<0b01101111,
1001 "uxth" , UnOpFrag<(and node:$Src, 0x0000FFFF)>>;
1002 defm UXTB16 : AI_unary_rrot<0b01101100,
1003 "uxtb16", UnOpFrag<(and node:$Src, 0x00FF00FF)>>;
1005 def : ARMV6Pat<(and (shl GPR:$Src, (i32 8)), 0xFF00FF),
1006 (UXTB16r_rot GPR:$Src, 24)>;
1007 def : ARMV6Pat<(and (srl GPR:$Src, (i32 8)), 0xFF00FF),
1008 (UXTB16r_rot GPR:$Src, 8)>;
1010 defm UXTAB : AI_bin_rrot<0b01101110, "uxtab",
1011 BinOpFrag<(add node:$LHS, (and node:$RHS, 0x00FF))>>;
1012 defm UXTAH : AI_bin_rrot<0b01101111, "uxtah",
1013 BinOpFrag<(add node:$LHS, (and node:$RHS, 0xFFFF))>>;
1016 // This isn't safe in general, the add is two 16-bit units, not a 32-bit add.
1017 //defm UXTAB16 : xxx<"uxtab16", 0xff00ff>;
1019 // TODO: UXT(A){B|H}16
1021 def SBFX : I<(outs GPR:$dst),
1022 (ins GPR:$src, imm0_31:$lsb, imm0_31:$width),
1023 AddrMode1, Size4Bytes, IndexModeNone, DPFrm, IIC_iALUi,
1024 "sbfx", " $dst, $src, $lsb, $width", "", []>,
1025 Requires<[IsARM, HasV6T2]> {
1026 let Inst{27-21} = 0b0111101;
1027 let Inst{6-4} = 0b101;
1030 def UBFX : I<(outs GPR:$dst),
1031 (ins GPR:$src, imm0_31:$lsb, imm0_31:$width),
1032 AddrMode1, Size4Bytes, IndexModeNone, DPFrm, IIC_iALUi,
1033 "ubfx", " $dst, $src, $lsb, $width", "", []>,
1034 Requires<[IsARM, HasV6T2]> {
1035 let Inst{27-21} = 0b0111111;
1036 let Inst{6-4} = 0b101;
1039 //===----------------------------------------------------------------------===//
1040 // Arithmetic Instructions.
1043 defm ADD : AsI1_bin_irs<0b0100, "add",
1044 BinOpFrag<(add node:$LHS, node:$RHS)>, 1>;
1045 defm SUB : AsI1_bin_irs<0b0010, "sub",
1046 BinOpFrag<(sub node:$LHS, node:$RHS)>>;
1048 // ADD and SUB with 's' bit set.
1049 defm ADDS : AI1_bin_s_irs<0b0100, "add",
1050 BinOpFrag<(addc node:$LHS, node:$RHS)>>;
1051 defm SUBS : AI1_bin_s_irs<0b0010, "sub",
1052 BinOpFrag<(subc node:$LHS, node:$RHS)>>;
1054 defm ADC : AI1_adde_sube_irs<0b0101, "adc",
1055 BinOpFrag<(adde node:$LHS, node:$RHS)>, 1>;
1056 defm SBC : AI1_adde_sube_irs<0b0110, "sbc",
1057 BinOpFrag<(sube node:$LHS, node:$RHS)>>;
1059 // These don't define reg/reg forms, because they are handled above.
1060 def RSBri : AsI1<0b0011, (outs GPR:$dst), (ins GPR:$a, so_imm:$b), DPFrm,
1061 IIC_iALUi, "rsb", " $dst, $a, $b",
1062 [(set GPR:$dst, (sub so_imm:$b, GPR:$a))]> {
1066 def RSBrs : AsI1<0b0011, (outs GPR:$dst), (ins GPR:$a, so_reg:$b), DPSoRegFrm,
1067 IIC_iALUsr, "rsb", " $dst, $a, $b",
1068 [(set GPR:$dst, (sub so_reg:$b, GPR:$a))]>;
1070 // RSB with 's' bit set.
1071 let Defs = [CPSR] in {
1072 def RSBSri : AI1<0b0011, (outs GPR:$dst), (ins GPR:$a, so_imm:$b), DPFrm,
1073 IIC_iALUi, "rsb", "s $dst, $a, $b",
1074 [(set GPR:$dst, (subc so_imm:$b, GPR:$a))]> {
1077 def RSBSrs : AI1<0b0011, (outs GPR:$dst), (ins GPR:$a, so_reg:$b), DPSoRegFrm,
1078 IIC_iALUsr, "rsb", "s $dst, $a, $b",
1079 [(set GPR:$dst, (subc so_reg:$b, GPR:$a))]>;
1082 let Uses = [CPSR] in {
1083 def RSCri : AsI1<0b0111, (outs GPR:$dst), (ins GPR:$a, so_imm:$b),
1084 DPFrm, IIC_iALUi, "rsc", " $dst, $a, $b",
1085 [(set GPR:$dst, (sube so_imm:$b, GPR:$a))]>,
1086 Requires<[IsARM, CarryDefIsUnused]> {
1089 def RSCrs : AsI1<0b0111, (outs GPR:$dst), (ins GPR:$a, so_reg:$b),
1090 DPSoRegFrm, IIC_iALUsr, "rsc", " $dst, $a, $b",
1091 [(set GPR:$dst, (sube so_reg:$b, GPR:$a))]>,
1092 Requires<[IsARM, CarryDefIsUnused]>;
1095 // FIXME: Allow these to be predicated.
1096 let Defs = [CPSR], Uses = [CPSR] in {
1097 def RSCSri : AXI1<0b0111, (outs GPR:$dst), (ins GPR:$a, so_imm:$b),
1098 DPFrm, IIC_iALUi, "rscs $dst, $a, $b",
1099 [(set GPR:$dst, (sube so_imm:$b, GPR:$a))]>,
1100 Requires<[IsARM, CarryDefIsUnused]> {
1103 def RSCSrs : AXI1<0b0111, (outs GPR:$dst), (ins GPR:$a, so_reg:$b),
1104 DPSoRegFrm, IIC_iALUsr, "rscs $dst, $a, $b",
1105 [(set GPR:$dst, (sube so_reg:$b, GPR:$a))]>,
1106 Requires<[IsARM, CarryDefIsUnused]>;
1109 // (sub X, imm) gets canonicalized to (add X, -imm). Match this form.
1110 def : ARMPat<(add GPR:$src, so_imm_neg:$imm),
1111 (SUBri GPR:$src, so_imm_neg:$imm)>;
1113 //def : ARMPat<(addc GPR:$src, so_imm_neg:$imm),
1114 // (SUBSri GPR:$src, so_imm_neg:$imm)>;
1115 //def : ARMPat<(adde GPR:$src, so_imm_neg:$imm),
1116 // (SBCri GPR:$src, so_imm_neg:$imm)>;
1118 // Note: These are implemented in C++ code, because they have to generate
1119 // ADD/SUBrs instructions, which use a complex pattern that a xform function
1121 // (mul X, 2^n+1) -> (add (X << n), X)
1122 // (mul X, 2^n-1) -> (rsb X, (X << n))
1125 //===----------------------------------------------------------------------===//
1126 // Bitwise Instructions.
1129 defm AND : AsI1_bin_irs<0b0000, "and",
1130 BinOpFrag<(and node:$LHS, node:$RHS)>, 1>;
1131 defm ORR : AsI1_bin_irs<0b1100, "orr",
1132 BinOpFrag<(or node:$LHS, node:$RHS)>, 1>;
1133 defm EOR : AsI1_bin_irs<0b0001, "eor",
1134 BinOpFrag<(xor node:$LHS, node:$RHS)>, 1>;
1135 defm BIC : AsI1_bin_irs<0b1110, "bic",
1136 BinOpFrag<(and node:$LHS, (not node:$RHS))>>;
1138 def BFC : I<(outs GPR:$dst), (ins GPR:$src, bf_inv_mask_imm:$imm),
1139 AddrMode1, Size4Bytes, IndexModeNone, DPFrm, IIC_iALUi,
1140 "bfc", " $dst, $imm", "$src = $dst",
1141 [(set GPR:$dst, (and GPR:$src, bf_inv_mask_imm:$imm))]>,
1142 Requires<[IsARM, HasV6T2]> {
1143 let Inst{27-21} = 0b0111110;
1144 let Inst{6-0} = 0b0011111;
1147 def MVNr : AsI1<0b1111, (outs GPR:$dst), (ins GPR:$src), DPFrm, IIC_iMOVr,
1148 "mvn", " $dst, $src",
1149 [(set GPR:$dst, (not GPR:$src))]>, UnaryDP;
1150 def MVNs : AsI1<0b1111, (outs GPR:$dst), (ins so_reg:$src), DPSoRegFrm,
1151 IIC_iMOVsr, "mvn", " $dst, $src",
1152 [(set GPR:$dst, (not so_reg:$src))]>, UnaryDP;
1153 let isReMaterializable = 1, isAsCheapAsAMove = 1 in
1154 def MVNi : AsI1<0b1111, (outs GPR:$dst), (ins so_imm:$imm), DPFrm,
1155 IIC_iMOVi, "mvn", " $dst, $imm",
1156 [(set GPR:$dst, so_imm_not:$imm)]>,UnaryDP {
1160 def : ARMPat<(and GPR:$src, so_imm_not:$imm),
1161 (BICri GPR:$src, so_imm_not:$imm)>;
1163 //===----------------------------------------------------------------------===//
1164 // Multiply Instructions.
1167 let isCommutable = 1 in
1168 def MUL : AsMul1I<0b0000000, (outs GPR:$dst), (ins GPR:$a, GPR:$b),
1169 IIC_iMUL32, "mul", " $dst, $a, $b",
1170 [(set GPR:$dst, (mul GPR:$a, GPR:$b))]>;
1172 def MLA : AsMul1I<0b0000001, (outs GPR:$dst), (ins GPR:$a, GPR:$b, GPR:$c),
1173 IIC_iMAC32, "mla", " $dst, $a, $b, $c",
1174 [(set GPR:$dst, (add (mul GPR:$a, GPR:$b), GPR:$c))]>;
1176 def MLS : AMul1I<0b0000011, (outs GPR:$dst), (ins GPR:$a, GPR:$b, GPR:$c),
1177 IIC_iMAC32, "mls", " $dst, $a, $b, $c",
1178 [(set GPR:$dst, (sub GPR:$c, (mul GPR:$a, GPR:$b)))]>,
1179 Requires<[IsARM, HasV6T2]>;
1181 // Extra precision multiplies with low / high results
1182 let neverHasSideEffects = 1 in {
1183 let isCommutable = 1 in {
1184 def SMULL : AsMul1I<0b0000110, (outs GPR:$ldst, GPR:$hdst),
1185 (ins GPR:$a, GPR:$b), IIC_iMUL64,
1186 "smull", " $ldst, $hdst, $a, $b", []>;
1188 def UMULL : AsMul1I<0b0000100, (outs GPR:$ldst, GPR:$hdst),
1189 (ins GPR:$a, GPR:$b), IIC_iMUL64,
1190 "umull", " $ldst, $hdst, $a, $b", []>;
1193 // Multiply + accumulate
1194 def SMLAL : AsMul1I<0b0000111, (outs GPR:$ldst, GPR:$hdst),
1195 (ins GPR:$a, GPR:$b), IIC_iMAC64,
1196 "smlal", " $ldst, $hdst, $a, $b", []>;
1198 def UMLAL : AsMul1I<0b0000101, (outs GPR:$ldst, GPR:$hdst),
1199 (ins GPR:$a, GPR:$b), IIC_iMAC64,
1200 "umlal", " $ldst, $hdst, $a, $b", []>;
1202 def UMAAL : AMul1I <0b0000010, (outs GPR:$ldst, GPR:$hdst),
1203 (ins GPR:$a, GPR:$b), IIC_iMAC64,
1204 "umaal", " $ldst, $hdst, $a, $b", []>,
1205 Requires<[IsARM, HasV6]>;
1206 } // neverHasSideEffects
1208 // Most significant word multiply
1209 def SMMUL : AMul2I <0b0111010, (outs GPR:$dst), (ins GPR:$a, GPR:$b),
1210 IIC_iMUL32, "smmul", " $dst, $a, $b",
1211 [(set GPR:$dst, (mulhs GPR:$a, GPR:$b))]>,
1212 Requires<[IsARM, HasV6]> {
1213 let Inst{7-4} = 0b0001;
1214 let Inst{15-12} = 0b1111;
1217 def SMMLA : AMul2I <0b0111010, (outs GPR:$dst), (ins GPR:$a, GPR:$b, GPR:$c),
1218 IIC_iMAC32, "smmla", " $dst, $a, $b, $c",
1219 [(set GPR:$dst, (add (mulhs GPR:$a, GPR:$b), GPR:$c))]>,
1220 Requires<[IsARM, HasV6]> {
1221 let Inst{7-4} = 0b0001;
1225 def SMMLS : AMul2I <0b0111010, (outs GPR:$dst), (ins GPR:$a, GPR:$b, GPR:$c),
1226 IIC_iMAC32, "smmls", " $dst, $a, $b, $c",
1227 [(set GPR:$dst, (sub GPR:$c, (mulhs GPR:$a, GPR:$b)))]>,
1228 Requires<[IsARM, HasV6]> {
1229 let Inst{7-4} = 0b1101;
1232 multiclass AI_smul<string opc, PatFrag opnode> {
1233 def BB : AMulxyI<0b0001011, (outs GPR:$dst), (ins GPR:$a, GPR:$b),
1234 IIC_iMUL32, !strconcat(opc, "bb"), " $dst, $a, $b",
1235 [(set GPR:$dst, (opnode (sext_inreg GPR:$a, i16),
1236 (sext_inreg GPR:$b, i16)))]>,
1237 Requires<[IsARM, HasV5TE]> {
1242 def BT : AMulxyI<0b0001011, (outs GPR:$dst), (ins GPR:$a, GPR:$b),
1243 IIC_iMUL32, !strconcat(opc, "bt"), " $dst, $a, $b",
1244 [(set GPR:$dst, (opnode (sext_inreg GPR:$a, i16),
1245 (sra GPR:$b, (i32 16))))]>,
1246 Requires<[IsARM, HasV5TE]> {
1251 def TB : AMulxyI<0b0001011, (outs GPR:$dst), (ins GPR:$a, GPR:$b),
1252 IIC_iMUL32, !strconcat(opc, "tb"), " $dst, $a, $b",
1253 [(set GPR:$dst, (opnode (sra GPR:$a, (i32 16)),
1254 (sext_inreg GPR:$b, i16)))]>,
1255 Requires<[IsARM, HasV5TE]> {
1260 def TT : AMulxyI<0b0001011, (outs GPR:$dst), (ins GPR:$a, GPR:$b),
1261 IIC_iMUL32, !strconcat(opc, "tt"), " $dst, $a, $b",
1262 [(set GPR:$dst, (opnode (sra GPR:$a, (i32 16)),
1263 (sra GPR:$b, (i32 16))))]>,
1264 Requires<[IsARM, HasV5TE]> {
1269 def WB : AMulxyI<0b0001001, (outs GPR:$dst), (ins GPR:$a, GPR:$b),
1270 IIC_iMUL16, !strconcat(opc, "wb"), " $dst, $a, $b",
1271 [(set GPR:$dst, (sra (opnode GPR:$a,
1272 (sext_inreg GPR:$b, i16)), (i32 16)))]>,
1273 Requires<[IsARM, HasV5TE]> {
1278 def WT : AMulxyI<0b0001001, (outs GPR:$dst), (ins GPR:$a, GPR:$b),
1279 IIC_iMUL16, !strconcat(opc, "wt"), " $dst, $a, $b",
1280 [(set GPR:$dst, (sra (opnode GPR:$a,
1281 (sra GPR:$b, (i32 16))), (i32 16)))]>,
1282 Requires<[IsARM, HasV5TE]> {
1289 multiclass AI_smla<string opc, PatFrag opnode> {
1290 def BB : AMulxyI<0b0001000, (outs GPR:$dst), (ins GPR:$a, GPR:$b, GPR:$acc),
1291 IIC_iMAC16, !strconcat(opc, "bb"), " $dst, $a, $b, $acc",
1292 [(set GPR:$dst, (add GPR:$acc,
1293 (opnode (sext_inreg GPR:$a, i16),
1294 (sext_inreg GPR:$b, i16))))]>,
1295 Requires<[IsARM, HasV5TE]> {
1300 def BT : AMulxyI<0b0001000, (outs GPR:$dst), (ins GPR:$a, GPR:$b, GPR:$acc),
1301 IIC_iMAC16, !strconcat(opc, "bt"), " $dst, $a, $b, $acc",
1302 [(set GPR:$dst, (add GPR:$acc, (opnode (sext_inreg GPR:$a, i16),
1303 (sra GPR:$b, (i32 16)))))]>,
1304 Requires<[IsARM, HasV5TE]> {
1309 def TB : AMulxyI<0b0001000, (outs GPR:$dst), (ins GPR:$a, GPR:$b, GPR:$acc),
1310 IIC_iMAC16, !strconcat(opc, "tb"), " $dst, $a, $b, $acc",
1311 [(set GPR:$dst, (add GPR:$acc, (opnode (sra GPR:$a, (i32 16)),
1312 (sext_inreg GPR:$b, i16))))]>,
1313 Requires<[IsARM, HasV5TE]> {
1318 def TT : AMulxyI<0b0001000, (outs GPR:$dst), (ins GPR:$a, GPR:$b, GPR:$acc),
1319 IIC_iMAC16, !strconcat(opc, "tt"), " $dst, $a, $b, $acc",
1320 [(set GPR:$dst, (add GPR:$acc, (opnode (sra GPR:$a, (i32 16)),
1321 (sra GPR:$b, (i32 16)))))]>,
1322 Requires<[IsARM, HasV5TE]> {
1327 def WB : AMulxyI<0b0001001, (outs GPR:$dst), (ins GPR:$a, GPR:$b, GPR:$acc),
1328 IIC_iMAC16, !strconcat(opc, "wb"), " $dst, $a, $b, $acc",
1329 [(set GPR:$dst, (add GPR:$acc, (sra (opnode GPR:$a,
1330 (sext_inreg GPR:$b, i16)), (i32 16))))]>,
1331 Requires<[IsARM, HasV5TE]> {
1336 def WT : AMulxyI<0b0001001, (outs GPR:$dst), (ins GPR:$a, GPR:$b, GPR:$acc),
1337 IIC_iMAC16, !strconcat(opc, "wt"), " $dst, $a, $b, $acc",
1338 [(set GPR:$dst, (add GPR:$acc, (sra (opnode GPR:$a,
1339 (sra GPR:$b, (i32 16))), (i32 16))))]>,
1340 Requires<[IsARM, HasV5TE]> {
1346 defm SMUL : AI_smul<"smul", BinOpFrag<(mul node:$LHS, node:$RHS)>>;
1347 defm SMLA : AI_smla<"smla", BinOpFrag<(mul node:$LHS, node:$RHS)>>;
1349 // TODO: Halfword multiple accumulate long: SMLAL<x><y>
1350 // TODO: Dual halfword multiple: SMUAD, SMUSD, SMLAD, SMLSD, SMLALD, SMLSLD
1352 //===----------------------------------------------------------------------===//
1353 // Misc. Arithmetic Instructions.
1356 def CLZ : AMiscA1I<0b000010110, (outs GPR:$dst), (ins GPR:$src), IIC_iUNAr,
1357 "clz", " $dst, $src",
1358 [(set GPR:$dst, (ctlz GPR:$src))]>, Requires<[IsARM, HasV5T]> {
1359 let Inst{7-4} = 0b0001;
1360 let Inst{11-8} = 0b1111;
1361 let Inst{19-16} = 0b1111;
1364 def REV : AMiscA1I<0b01101011, (outs GPR:$dst), (ins GPR:$src), IIC_iUNAr,
1365 "rev", " $dst, $src",
1366 [(set GPR:$dst, (bswap GPR:$src))]>, Requires<[IsARM, HasV6]> {
1367 let Inst{7-4} = 0b0011;
1368 let Inst{11-8} = 0b1111;
1369 let Inst{19-16} = 0b1111;
1372 def REV16 : AMiscA1I<0b01101011, (outs GPR:$dst), (ins GPR:$src), IIC_iUNAr,
1373 "rev16", " $dst, $src",
1375 (or (and (srl GPR:$src, (i32 8)), 0xFF),
1376 (or (and (shl GPR:$src, (i32 8)), 0xFF00),
1377 (or (and (srl GPR:$src, (i32 8)), 0xFF0000),
1378 (and (shl GPR:$src, (i32 8)), 0xFF000000)))))]>,
1379 Requires<[IsARM, HasV6]> {
1380 let Inst{7-4} = 0b1011;
1381 let Inst{11-8} = 0b1111;
1382 let Inst{19-16} = 0b1111;
1385 def REVSH : AMiscA1I<0b01101111, (outs GPR:$dst), (ins GPR:$src), IIC_iUNAr,
1386 "revsh", " $dst, $src",
1389 (or (srl (and GPR:$src, 0xFF00), (i32 8)),
1390 (shl GPR:$src, (i32 8))), i16))]>,
1391 Requires<[IsARM, HasV6]> {
1392 let Inst{7-4} = 0b1011;
1393 let Inst{11-8} = 0b1111;
1394 let Inst{19-16} = 0b1111;
1397 def PKHBT : AMiscA1I<0b01101000, (outs GPR:$dst),
1398 (ins GPR:$src1, GPR:$src2, i32imm:$shamt),
1399 IIC_iALUsi, "pkhbt", " $dst, $src1, $src2, LSL $shamt",
1400 [(set GPR:$dst, (or (and GPR:$src1, 0xFFFF),
1401 (and (shl GPR:$src2, (i32 imm:$shamt)),
1403 Requires<[IsARM, HasV6]> {
1404 let Inst{6-4} = 0b001;
1407 // Alternate cases for PKHBT where identities eliminate some nodes.
1408 def : ARMV6Pat<(or (and GPR:$src1, 0xFFFF), (and GPR:$src2, 0xFFFF0000)),
1409 (PKHBT GPR:$src1, GPR:$src2, 0)>;
1410 def : ARMV6Pat<(or (and GPR:$src1, 0xFFFF), (shl GPR:$src2, imm16_31:$shamt)),
1411 (PKHBT GPR:$src1, GPR:$src2, imm16_31:$shamt)>;
1414 def PKHTB : AMiscA1I<0b01101000, (outs GPR:$dst),
1415 (ins GPR:$src1, GPR:$src2, i32imm:$shamt),
1416 IIC_iALUsi, "pkhtb", " $dst, $src1, $src2, ASR $shamt",
1417 [(set GPR:$dst, (or (and GPR:$src1, 0xFFFF0000),
1418 (and (sra GPR:$src2, imm16_31:$shamt),
1419 0xFFFF)))]>, Requires<[IsARM, HasV6]> {
1420 let Inst{6-4} = 0b101;
1423 // Alternate cases for PKHTB where identities eliminate some nodes. Note that
1424 // a shift amount of 0 is *not legal* here, it is PKHBT instead.
1425 def : ARMV6Pat<(or (and GPR:$src1, 0xFFFF0000), (srl GPR:$src2, (i32 16))),
1426 (PKHTB GPR:$src1, GPR:$src2, 16)>;
1427 def : ARMV6Pat<(or (and GPR:$src1, 0xFFFF0000),
1428 (and (srl GPR:$src2, imm1_15:$shamt), 0xFFFF)),
1429 (PKHTB GPR:$src1, GPR:$src2, imm1_15:$shamt)>;
1431 //===----------------------------------------------------------------------===//
1432 // Comparison Instructions...
1435 defm CMP : AI1_cmp_irs<0b1010, "cmp",
1436 BinOpFrag<(ARMcmp node:$LHS, node:$RHS)>>;
1437 defm CMN : AI1_cmp_irs<0b1011, "cmn",
1438 BinOpFrag<(ARMcmp node:$LHS,(ineg node:$RHS))>>;
1440 // Note that TST/TEQ don't set all the same flags that CMP does!
1441 defm TST : AI1_cmp_irs<0b1000, "tst",
1442 BinOpFrag<(ARMcmpZ (and node:$LHS, node:$RHS), 0)>, 1>;
1443 defm TEQ : AI1_cmp_irs<0b1001, "teq",
1444 BinOpFrag<(ARMcmpZ (xor node:$LHS, node:$RHS), 0)>, 1>;
1446 defm CMPz : AI1_cmp_irs<0b1010, "cmp",
1447 BinOpFrag<(ARMcmpZ node:$LHS, node:$RHS)>>;
1448 defm CMNz : AI1_cmp_irs<0b1011, "cmn",
1449 BinOpFrag<(ARMcmpZ node:$LHS,(ineg node:$RHS))>>;
1451 def : ARMPat<(ARMcmp GPR:$src, so_imm_neg:$imm),
1452 (CMNri GPR:$src, so_imm_neg:$imm)>;
1454 def : ARMPat<(ARMcmpZ GPR:$src, so_imm_neg:$imm),
1455 (CMNri GPR:$src, so_imm_neg:$imm)>;
1458 // Conditional moves
1459 // FIXME: should be able to write a pattern for ARMcmov, but can't use
1460 // a two-value operand where a dag node expects two operands. :(
1461 def MOVCCr : AI1<0b1101, (outs GPR:$dst), (ins GPR:$false, GPR:$true), DPFrm,
1462 IIC_iCMOVr, "mov", " $dst, $true",
1463 [/*(set GPR:$dst, (ARMcmov GPR:$false, GPR:$true, imm:$cc, CCR:$ccr))*/]>,
1464 RegConstraint<"$false = $dst">, UnaryDP;
1466 def MOVCCs : AI1<0b1101, (outs GPR:$dst),
1467 (ins GPR:$false, so_reg:$true), DPSoRegFrm, IIC_iCMOVsr,
1468 "mov", " $dst, $true",
1469 [/*(set GPR:$dst, (ARMcmov GPR:$false, so_reg:$true, imm:$cc, CCR:$ccr))*/]>,
1470 RegConstraint<"$false = $dst">, UnaryDP;
1472 def MOVCCi : AI1<0b1101, (outs GPR:$dst),
1473 (ins GPR:$false, so_imm:$true), DPFrm, IIC_iCMOVi,
1474 "mov", " $dst, $true",
1475 [/*(set GPR:$dst, (ARMcmov GPR:$false, so_imm:$true, imm:$cc, CCR:$ccr))*/]>,
1476 RegConstraint<"$false = $dst">, UnaryDP {
1481 //===----------------------------------------------------------------------===//
1485 // __aeabi_read_tp preserves the registers r1-r3.
1487 Defs = [R0, R12, LR, CPSR] in {
1488 def TPsoft : ABXI<0b1011, (outs), (ins), IIC_Br,
1489 "bl __aeabi_read_tp",
1490 [(set R0, ARMthread_pointer)]>;
1493 //===----------------------------------------------------------------------===//
1494 // SJLJ Exception handling intrinsics
1495 // eh_sjlj_setjmp() is an instruction sequence to store the return
1496 // address and save #0 in R0 for the non-longjmp case.
1497 // Since by its nature we may be coming from some other function to get
1498 // here, and we're using the stack frame for the containing function to
1499 // save/restore registers, we can't keep anything live in regs across
1500 // the eh_sjlj_setjmp(), else it will almost certainly have been tromped upon
1501 // when we get here from a longjmp(). We force everthing out of registers
1502 // except for our own input by listing the relevant registers in Defs. By
1503 // doing so, we also cause the prologue/epilogue code to actively preserve
1504 // all of the callee-saved resgisters, which is exactly what we want.
1506 [ R0, R1, R2, R3, R4, R5, R6, R7, R8, R9, R10, R11, R12, LR, D0,
1507 D1, D2, D3, D4, D5, D6, D7, D8, D9, D10, D11, D12, D13, D14, D15,
1508 D16, D17, D18, D19, D20, D21, D22, D23, D24, D25, D26, D27, D28, D29, D30,
1510 def Int_eh_sjlj_setjmp : XI<(outs), (ins GPR:$src),
1511 AddrModeNone, SizeSpecial, IndexModeNone,
1512 Pseudo, NoItinerary,
1513 "str sp, [$src, #+8] @ eh_setjmp begin\n\t"
1514 "add r12, pc, #8\n\t"
1515 "str r12, [$src, #+4]\n\t"
1517 "add pc, pc, #0\n\t"
1518 "mov r0, #1 @ eh_setjmp end", "",
1519 [(set R0, (ARMeh_sjlj_setjmp GPR:$src))]>;
1522 //===----------------------------------------------------------------------===//
1523 // Non-Instruction Patterns
1526 // ConstantPool, GlobalAddress, and JumpTable
1527 def : ARMPat<(ARMWrapper tglobaladdr :$dst), (LEApcrel tglobaladdr :$dst)>;
1528 def : ARMPat<(ARMWrapper tconstpool :$dst), (LEApcrel tconstpool :$dst)>;
1529 def : ARMPat<(ARMWrapperJT tjumptable:$dst, imm:$id),
1530 (LEApcrelJT tjumptable:$dst, imm:$id)>;
1532 // Large immediate handling.
1534 // Two piece so_imms.
1535 let isReMaterializable = 1 in
1536 def MOVi2pieces : AI1x2<(outs GPR:$dst), (ins so_imm2part:$src),
1538 "mov", " $dst, $src",
1539 [(set GPR:$dst, so_imm2part:$src)]>,
1540 Requires<[IsARM, NoV6T2]>;
1542 def : ARMPat<(or GPR:$LHS, so_imm2part:$RHS),
1543 (ORRri (ORRri GPR:$LHS, (so_imm2part_1 imm:$RHS)),
1544 (so_imm2part_2 imm:$RHS))>;
1545 def : ARMPat<(xor GPR:$LHS, so_imm2part:$RHS),
1546 (EORri (EORri GPR:$LHS, (so_imm2part_1 imm:$RHS)),
1547 (so_imm2part_2 imm:$RHS))>;
1549 // 32-bit immediate using movw + movt.
1550 // This is a single pseudo instruction to make it re-materializable. Remove
1551 // when we can do generalized remat.
1552 let isReMaterializable = 1 in
1553 def MOVi32imm : AI1x2<(outs GPR:$dst), (ins i32imm:$src), Pseudo, IIC_iMOVi,
1554 "movw", " $dst, ${src:lo16}\n\tmovt${p} $dst, ${src:hi16}",
1555 [(set GPR:$dst, (i32 imm:$src))]>,
1556 Requires<[IsARM, HasV6T2]>;
1558 // TODO: add,sub,and, 3-instr forms?
1562 def : ARMPat<(ARMcall texternalsym:$func), (BL texternalsym:$func)>,
1563 Requires<[IsARM, IsNotDarwin]>;
1564 def : ARMPat<(ARMcall texternalsym:$func), (BLr9 texternalsym:$func)>,
1565 Requires<[IsARM, IsDarwin]>;
1567 // zextload i1 -> zextload i8
1568 def : ARMPat<(zextloadi1 addrmode2:$addr), (LDRB addrmode2:$addr)>;
1570 // extload -> zextload
1571 def : ARMPat<(extloadi1 addrmode2:$addr), (LDRB addrmode2:$addr)>;
1572 def : ARMPat<(extloadi8 addrmode2:$addr), (LDRB addrmode2:$addr)>;
1573 def : ARMPat<(extloadi16 addrmode3:$addr), (LDRH addrmode3:$addr)>;
1575 def : ARMPat<(extloadi8 addrmodepc:$addr), (PICLDRB addrmodepc:$addr)>;
1576 def : ARMPat<(extloadi16 addrmodepc:$addr), (PICLDRH addrmodepc:$addr)>;
1579 def : ARMV5TEPat<(mul (sra (shl GPR:$a, (i32 16)), (i32 16)),
1580 (sra (shl GPR:$b, (i32 16)), (i32 16))),
1581 (SMULBB GPR:$a, GPR:$b)>;
1582 def : ARMV5TEPat<(mul sext_16_node:$a, sext_16_node:$b),
1583 (SMULBB GPR:$a, GPR:$b)>;
1584 def : ARMV5TEPat<(mul (sra (shl GPR:$a, (i32 16)), (i32 16)),
1585 (sra GPR:$b, (i32 16))),
1586 (SMULBT GPR:$a, GPR:$b)>;
1587 def : ARMV5TEPat<(mul sext_16_node:$a, (sra GPR:$b, (i32 16))),
1588 (SMULBT GPR:$a, GPR:$b)>;
1589 def : ARMV5TEPat<(mul (sra GPR:$a, (i32 16)),
1590 (sra (shl GPR:$b, (i32 16)), (i32 16))),
1591 (SMULTB GPR:$a, GPR:$b)>;
1592 def : ARMV5TEPat<(mul (sra GPR:$a, (i32 16)), sext_16_node:$b),
1593 (SMULTB GPR:$a, GPR:$b)>;
1594 def : ARMV5TEPat<(sra (mul GPR:$a, (sra (shl GPR:$b, (i32 16)), (i32 16))),
1596 (SMULWB GPR:$a, GPR:$b)>;
1597 def : ARMV5TEPat<(sra (mul GPR:$a, sext_16_node:$b), (i32 16)),
1598 (SMULWB GPR:$a, GPR:$b)>;
1600 def : ARMV5TEPat<(add GPR:$acc,
1601 (mul (sra (shl GPR:$a, (i32 16)), (i32 16)),
1602 (sra (shl GPR:$b, (i32 16)), (i32 16)))),
1603 (SMLABB GPR:$a, GPR:$b, GPR:$acc)>;
1604 def : ARMV5TEPat<(add GPR:$acc,
1605 (mul sext_16_node:$a, sext_16_node:$b)),
1606 (SMLABB GPR:$a, GPR:$b, GPR:$acc)>;
1607 def : ARMV5TEPat<(add GPR:$acc,
1608 (mul (sra (shl GPR:$a, (i32 16)), (i32 16)),
1609 (sra GPR:$b, (i32 16)))),
1610 (SMLABT GPR:$a, GPR:$b, GPR:$acc)>;
1611 def : ARMV5TEPat<(add GPR:$acc,
1612 (mul sext_16_node:$a, (sra GPR:$b, (i32 16)))),
1613 (SMLABT GPR:$a, GPR:$b, GPR:$acc)>;
1614 def : ARMV5TEPat<(add GPR:$acc,
1615 (mul (sra GPR:$a, (i32 16)),
1616 (sra (shl GPR:$b, (i32 16)), (i32 16)))),
1617 (SMLATB GPR:$a, GPR:$b, GPR:$acc)>;
1618 def : ARMV5TEPat<(add GPR:$acc,
1619 (mul (sra GPR:$a, (i32 16)), sext_16_node:$b)),
1620 (SMLATB GPR:$a, GPR:$b, GPR:$acc)>;
1621 def : ARMV5TEPat<(add GPR:$acc,
1622 (sra (mul GPR:$a, (sra (shl GPR:$b, (i32 16)), (i32 16))),
1624 (SMLAWB GPR:$a, GPR:$b, GPR:$acc)>;
1625 def : ARMV5TEPat<(add GPR:$acc,
1626 (sra (mul GPR:$a, sext_16_node:$b), (i32 16))),
1627 (SMLAWB GPR:$a, GPR:$b, GPR:$acc)>;
1629 //===----------------------------------------------------------------------===//
1633 include "ARMInstrThumb.td"
1635 //===----------------------------------------------------------------------===//
1639 include "ARMInstrThumb2.td"
1641 //===----------------------------------------------------------------------===//
1642 // Floating Point Support
1645 include "ARMInstrVFP.td"
1647 //===----------------------------------------------------------------------===//
1648 // Advanced SIMD (NEON) Support
1651 include "ARMInstrNEON.td"