1 //===- ARMInstrInfo.td - Target Description for ARM Target -*- tablegen -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file describes the ARM instructions in TableGen format.
12 //===----------------------------------------------------------------------===//
14 //===----------------------------------------------------------------------===//
15 // ARM specific DAG Nodes.
19 def SDT_ARMCallSeqStart : SDCallSeqStart<[ SDTCisVT<0, i32> ]>;
20 def SDT_ARMCallSeqEnd : SDCallSeqEnd<[ SDTCisVT<0, i32>, SDTCisVT<1, i32> ]>;
21 def SDT_ARMStructByVal : SDTypeProfile<0, 4,
22 [SDTCisVT<0, i32>, SDTCisVT<1, i32>,
23 SDTCisVT<2, i32>, SDTCisVT<3, i32>]>;
25 def SDT_ARMSaveCallPC : SDTypeProfile<0, 1, []>;
27 def SDT_ARMcall : SDTypeProfile<0, -1, [SDTCisPtrTy<0>]>;
29 def SDT_ARMCMov : SDTypeProfile<1, 3,
30 [SDTCisSameAs<0, 1>, SDTCisSameAs<0, 2>,
33 def SDT_ARMBrcond : SDTypeProfile<0, 2,
34 [SDTCisVT<0, OtherVT>, SDTCisVT<1, i32>]>;
36 def SDT_ARMBrJT : SDTypeProfile<0, 3,
37 [SDTCisPtrTy<0>, SDTCisVT<1, i32>,
40 def SDT_ARMBr2JT : SDTypeProfile<0, 4,
41 [SDTCisPtrTy<0>, SDTCisVT<1, i32>,
42 SDTCisVT<2, i32>, SDTCisVT<3, i32>]>;
44 def SDT_ARMBCC_i64 : SDTypeProfile<0, 6,
46 SDTCisVT<1, i32>, SDTCisVT<2, i32>,
47 SDTCisVT<3, i32>, SDTCisVT<4, i32>,
48 SDTCisVT<5, OtherVT>]>;
50 def SDT_ARMAnd : SDTypeProfile<1, 2,
51 [SDTCisVT<0, i32>, SDTCisVT<1, i32>,
54 def SDT_ARMCmp : SDTypeProfile<0, 2, [SDTCisSameAs<0, 1>]>;
56 def SDT_ARMPICAdd : SDTypeProfile<1, 2, [SDTCisSameAs<0, 1>,
57 SDTCisPtrTy<1>, SDTCisVT<2, i32>]>;
59 def SDT_ARMThreadPointer : SDTypeProfile<1, 0, [SDTCisPtrTy<0>]>;
60 def SDT_ARMEH_SJLJ_Setjmp : SDTypeProfile<1, 2, [SDTCisInt<0>, SDTCisPtrTy<1>,
62 def SDT_ARMEH_SJLJ_Longjmp: SDTypeProfile<0, 2, [SDTCisPtrTy<0>, SDTCisInt<1>]>;
64 def SDT_ARMMEMBARRIER : SDTypeProfile<0, 1, [SDTCisInt<0>]>;
66 def SDT_ARMPREFETCH : SDTypeProfile<0, 3, [SDTCisPtrTy<0>, SDTCisSameAs<1, 2>,
69 def SDT_ARMTCRET : SDTypeProfile<0, 1, [SDTCisPtrTy<0>]>;
71 def SDT_ARMBFI : SDTypeProfile<1, 3, [SDTCisVT<0, i32>, SDTCisVT<1, i32>,
72 SDTCisVT<2, i32>, SDTCisVT<3, i32>]>;
74 def SDT_ARMVMAXNM : SDTypeProfile<1, 2, [SDTCisFP<0>, SDTCisFP<1>, SDTCisFP<2>]>;
75 def SDT_ARMVMINNM : SDTypeProfile<1, 2, [SDTCisFP<0>, SDTCisFP<1>, SDTCisFP<2>]>;
77 def SDTBinaryArithWithFlags : SDTypeProfile<2, 2,
80 SDTCisInt<0>, SDTCisVT<1, i32>]>;
82 // SDTBinaryArithWithFlagsInOut - RES1, CPSR = op LHS, RHS, CPSR
83 def SDTBinaryArithWithFlagsInOut : SDTypeProfile<2, 3,
90 def SDT_ARM64bitmlal : SDTypeProfile<2,4, [ SDTCisVT<0, i32>, SDTCisVT<1, i32>,
91 SDTCisVT<2, i32>, SDTCisVT<3, i32>,
92 SDTCisVT<4, i32>, SDTCisVT<5, i32> ] >;
93 def ARMUmlal : SDNode<"ARMISD::UMLAL", SDT_ARM64bitmlal>;
94 def ARMSmlal : SDNode<"ARMISD::SMLAL", SDT_ARM64bitmlal>;
97 def ARMWrapper : SDNode<"ARMISD::Wrapper", SDTIntUnaryOp>;
98 def ARMWrapperPIC : SDNode<"ARMISD::WrapperPIC", SDTIntUnaryOp>;
99 def ARMWrapperJT : SDNode<"ARMISD::WrapperJT", SDTIntBinOp>;
101 def ARMcallseq_start : SDNode<"ISD::CALLSEQ_START", SDT_ARMCallSeqStart,
102 [SDNPHasChain, SDNPSideEffect, SDNPOutGlue]>;
103 def ARMcallseq_end : SDNode<"ISD::CALLSEQ_END", SDT_ARMCallSeqEnd,
104 [SDNPHasChain, SDNPSideEffect,
105 SDNPOptInGlue, SDNPOutGlue]>;
106 def ARMcopystructbyval : SDNode<"ARMISD::COPY_STRUCT_BYVAL" ,
108 [SDNPHasChain, SDNPInGlue, SDNPOutGlue,
109 SDNPMayStore, SDNPMayLoad]>;
111 def ARMcall : SDNode<"ARMISD::CALL", SDT_ARMcall,
112 [SDNPHasChain, SDNPOptInGlue, SDNPOutGlue,
114 def ARMcall_pred : SDNode<"ARMISD::CALL_PRED", SDT_ARMcall,
115 [SDNPHasChain, SDNPOptInGlue, SDNPOutGlue,
117 def ARMcall_nolink : SDNode<"ARMISD::CALL_NOLINK", SDT_ARMcall,
118 [SDNPHasChain, SDNPOptInGlue, SDNPOutGlue,
121 def ARMretflag : SDNode<"ARMISD::RET_FLAG", SDTNone,
122 [SDNPHasChain, SDNPOptInGlue, SDNPVariadic]>;
123 def ARMintretflag : SDNode<"ARMISD::INTRET_FLAG", SDT_ARMcall,
124 [SDNPHasChain, SDNPOptInGlue, SDNPVariadic]>;
125 def ARMcmov : SDNode<"ARMISD::CMOV", SDT_ARMCMov,
128 def ARMbrcond : SDNode<"ARMISD::BRCOND", SDT_ARMBrcond,
129 [SDNPHasChain, SDNPInGlue, SDNPOutGlue]>;
131 def ARMbrjt : SDNode<"ARMISD::BR_JT", SDT_ARMBrJT,
133 def ARMbr2jt : SDNode<"ARMISD::BR2_JT", SDT_ARMBr2JT,
136 def ARMBcci64 : SDNode<"ARMISD::BCC_i64", SDT_ARMBCC_i64,
139 def ARMcmp : SDNode<"ARMISD::CMP", SDT_ARMCmp,
142 def ARMcmn : SDNode<"ARMISD::CMN", SDT_ARMCmp,
145 def ARMcmpZ : SDNode<"ARMISD::CMPZ", SDT_ARMCmp,
146 [SDNPOutGlue, SDNPCommutative]>;
148 def ARMpic_add : SDNode<"ARMISD::PIC_ADD", SDT_ARMPICAdd>;
150 def ARMsrl_flag : SDNode<"ARMISD::SRL_FLAG", SDTIntUnaryOp, [SDNPOutGlue]>;
151 def ARMsra_flag : SDNode<"ARMISD::SRA_FLAG", SDTIntUnaryOp, [SDNPOutGlue]>;
152 def ARMrrx : SDNode<"ARMISD::RRX" , SDTIntUnaryOp, [SDNPInGlue ]>;
154 def ARMaddc : SDNode<"ARMISD::ADDC", SDTBinaryArithWithFlags,
156 def ARMsubc : SDNode<"ARMISD::SUBC", SDTBinaryArithWithFlags>;
157 def ARMadde : SDNode<"ARMISD::ADDE", SDTBinaryArithWithFlagsInOut>;
158 def ARMsube : SDNode<"ARMISD::SUBE", SDTBinaryArithWithFlagsInOut>;
160 def ARMthread_pointer: SDNode<"ARMISD::THREAD_POINTER", SDT_ARMThreadPointer>;
161 def ARMeh_sjlj_setjmp: SDNode<"ARMISD::EH_SJLJ_SETJMP",
162 SDT_ARMEH_SJLJ_Setjmp,
163 [SDNPHasChain, SDNPSideEffect]>;
164 def ARMeh_sjlj_longjmp: SDNode<"ARMISD::EH_SJLJ_LONGJMP",
165 SDT_ARMEH_SJLJ_Longjmp,
166 [SDNPHasChain, SDNPSideEffect]>;
168 def ARMMemBarrierMCR : SDNode<"ARMISD::MEMBARRIER_MCR", SDT_ARMMEMBARRIER,
169 [SDNPHasChain, SDNPSideEffect]>;
170 def ARMPreload : SDNode<"ARMISD::PRELOAD", SDT_ARMPREFETCH,
171 [SDNPHasChain, SDNPMayLoad, SDNPMayStore]>;
173 def ARMrbit : SDNode<"ARMISD::RBIT", SDTIntUnaryOp>;
175 def ARMtcret : SDNode<"ARMISD::TC_RETURN", SDT_ARMTCRET,
176 [SDNPHasChain, SDNPOptInGlue, SDNPVariadic]>;
178 def ARMbfi : SDNode<"ARMISD::BFI", SDT_ARMBFI>;
180 def ARMvmaxnm : SDNode<"ARMISD::VMAXNM", SDT_ARMVMAXNM, []>;
181 def ARMvminnm : SDNode<"ARMISD::VMINNM", SDT_ARMVMINNM, []>;
183 //===----------------------------------------------------------------------===//
184 // ARM Instruction Predicate Definitions.
186 def HasV4T : Predicate<"Subtarget->hasV4TOps()">,
187 AssemblerPredicate<"HasV4TOps", "armv4t">;
188 def NoV4T : Predicate<"!Subtarget->hasV4TOps()">;
189 def HasV5T : Predicate<"Subtarget->hasV5TOps()">,
190 AssemblerPredicate<"HasV5TOps", "armv5t">;
191 def HasV5TE : Predicate<"Subtarget->hasV5TEOps()">,
192 AssemblerPredicate<"HasV5TEOps", "armv5te">;
193 def HasV6 : Predicate<"Subtarget->hasV6Ops()">,
194 AssemblerPredicate<"HasV6Ops", "armv6">;
195 def NoV6 : Predicate<"!Subtarget->hasV6Ops()">;
196 def HasV6M : Predicate<"Subtarget->hasV6MOps()">,
197 AssemblerPredicate<"HasV6MOps",
198 "armv6m or armv6t2">;
199 def HasV6T2 : Predicate<"Subtarget->hasV6T2Ops()">,
200 AssemblerPredicate<"HasV6T2Ops", "armv6t2">;
201 def NoV6T2 : Predicate<"!Subtarget->hasV6T2Ops()">;
202 def HasV6K : Predicate<"Subtarget->hasV6KOps()">,
203 AssemblerPredicate<"HasV6KOps", "armv6k">;
204 def NoV6K : Predicate<"!Subtarget->hasV6KOps()">;
205 def HasV7 : Predicate<"Subtarget->hasV7Ops()">,
206 AssemblerPredicate<"HasV7Ops", "armv7">;
207 def HasV8 : Predicate<"Subtarget->hasV8Ops()">,
208 AssemblerPredicate<"HasV8Ops", "armv8">;
209 def PreV8 : Predicate<"!Subtarget->hasV8Ops()">,
210 AssemblerPredicate<"!HasV8Ops", "armv7 or earlier">;
211 def HasV8_1a : Predicate<"Subtarget->hasV8_1aOps()">,
212 AssemblerPredicate<"HasV8_1aOps", "armv8.1a">;
213 def NoVFP : Predicate<"!Subtarget->hasVFP2()">;
214 def HasVFP2 : Predicate<"Subtarget->hasVFP2()">,
215 AssemblerPredicate<"FeatureVFP2", "VFP2">;
216 def HasVFP3 : Predicate<"Subtarget->hasVFP3()">,
217 AssemblerPredicate<"FeatureVFP3", "VFP3">;
218 def HasVFP4 : Predicate<"Subtarget->hasVFP4()">,
219 AssemblerPredicate<"FeatureVFP4", "VFP4">;
220 def HasDPVFP : Predicate<"!Subtarget->isFPOnlySP()">,
221 AssemblerPredicate<"!FeatureVFPOnlySP",
222 "double precision VFP">;
223 def HasFPARMv8 : Predicate<"Subtarget->hasFPARMv8()">,
224 AssemblerPredicate<"FeatureFPARMv8", "FPARMv8">;
225 def HasNEON : Predicate<"Subtarget->hasNEON()">,
226 AssemblerPredicate<"FeatureNEON", "NEON">;
227 def HasCrypto : Predicate<"Subtarget->hasCrypto()">,
228 AssemblerPredicate<"FeatureCrypto", "crypto">;
229 def HasCRC : Predicate<"Subtarget->hasCRC()">,
230 AssemblerPredicate<"FeatureCRC", "crc">;
231 def HasFP16 : Predicate<"Subtarget->hasFP16()">,
232 AssemblerPredicate<"FeatureFP16","half-float">;
233 def HasDivide : Predicate<"Subtarget->hasDivide()">,
234 AssemblerPredicate<"FeatureHWDiv", "divide in THUMB">;
235 def HasDivideInARM : Predicate<"Subtarget->hasDivideInARMMode()">,
236 AssemblerPredicate<"FeatureHWDivARM", "divide in ARM">;
237 def HasT2ExtractPack : Predicate<"Subtarget->hasT2ExtractPack()">,
238 AssemblerPredicate<"FeatureT2XtPk",
240 def HasThumb2DSP : Predicate<"Subtarget->hasThumb2DSP()">,
241 AssemblerPredicate<"FeatureDSPThumb2",
243 def HasDB : Predicate<"Subtarget->hasDataBarrier()">,
244 AssemblerPredicate<"FeatureDB",
246 def HasMP : Predicate<"Subtarget->hasMPExtension()">,
247 AssemblerPredicate<"FeatureMP",
249 def HasVirtualization: Predicate<"false">,
250 AssemblerPredicate<"FeatureVirtualization",
251 "virtualization-extensions">;
252 def HasTrustZone : Predicate<"Subtarget->hasTrustZone()">,
253 AssemblerPredicate<"FeatureTrustZone",
255 def HasZCZ : Predicate<"Subtarget->hasZeroCycleZeroing()">;
256 def UseNEONForFP : Predicate<"Subtarget->useNEONForSinglePrecisionFP()">;
257 def DontUseNEONForFP : Predicate<"!Subtarget->useNEONForSinglePrecisionFP()">;
258 def IsThumb : Predicate<"Subtarget->isThumb()">,
259 AssemblerPredicate<"ModeThumb", "thumb">;
260 def IsThumb1Only : Predicate<"Subtarget->isThumb1Only()">;
261 def IsThumb2 : Predicate<"Subtarget->isThumb2()">,
262 AssemblerPredicate<"ModeThumb,FeatureThumb2",
264 def IsMClass : Predicate<"Subtarget->isMClass()">,
265 AssemblerPredicate<"FeatureMClass", "armv*m">;
266 def IsNotMClass : Predicate<"!Subtarget->isMClass()">,
267 AssemblerPredicate<"!FeatureMClass",
269 def IsARM : Predicate<"!Subtarget->isThumb()">,
270 AssemblerPredicate<"!ModeThumb", "arm-mode">;
271 def IsMachO : Predicate<"Subtarget->isTargetMachO()">;
272 def IsNotMachO : Predicate<"!Subtarget->isTargetMachO()">;
273 def IsNaCl : Predicate<"Subtarget->isTargetNaCl()">;
274 def UseNaClTrap : Predicate<"Subtarget->useNaClTrap()">,
275 AssemblerPredicate<"FeatureNaClTrap", "NaCl">;
276 def DontUseNaClTrap : Predicate<"!Subtarget->useNaClTrap()">;
278 // FIXME: Eventually this will be just "hasV6T2Ops".
279 def UseMovt : Predicate<"Subtarget->useMovt(*MF)">;
280 def DontUseMovt : Predicate<"!Subtarget->useMovt(*MF)">;
281 def UseFPVMLx : Predicate<"Subtarget->useFPVMLx()">;
282 def UseMulOps : Predicate<"Subtarget->useMulOps()">;
284 // Prefer fused MAC for fp mul + add over fp VMLA / VMLS if they are available.
285 // But only select them if more precision in FP computation is allowed.
286 // Do not use them for Darwin platforms.
287 def UseFusedMAC : Predicate<"(TM.Options.AllowFPOpFusion =="
288 " FPOpFusion::Fast && "
289 " Subtarget->hasVFP4()) && "
290 "!Subtarget->isTargetDarwin()">;
291 def DontUseFusedMAC : Predicate<"!(TM.Options.AllowFPOpFusion =="
292 " FPOpFusion::Fast &&"
293 " Subtarget->hasVFP4()) || "
294 "Subtarget->isTargetDarwin()">;
296 // VGETLNi32 is microcoded on Swift - prefer VMOV.
297 def HasFastVGETLNi32 : Predicate<"!Subtarget->isSwift()">;
298 def HasSlowVGETLNi32 : Predicate<"Subtarget->isSwift()">;
300 // VDUP.32 is microcoded on Swift - prefer VMOV.
301 def HasFastVDUP32 : Predicate<"!Subtarget->isSwift()">;
302 def HasSlowVDUP32 : Predicate<"Subtarget->isSwift()">;
304 // Cortex-A9 prefers VMOVSR to VMOVDRR even when using NEON for scalar FP, as
305 // this allows more effective execution domain optimization. See
306 // setExecutionDomain().
307 def UseVMOVSR : Predicate<"Subtarget->isCortexA9() || !Subtarget->useNEONForSinglePrecisionFP()">;
308 def DontUseVMOVSR : Predicate<"!Subtarget->isCortexA9() && Subtarget->useNEONForSinglePrecisionFP()">;
310 def IsLE : Predicate<"getTargetLowering()->isLittleEndian()">;
311 def IsBE : Predicate<"getTargetLowering()->isBigEndian()">;
313 //===----------------------------------------------------------------------===//
314 // ARM Flag Definitions.
316 class RegConstraint<string C> {
317 string Constraints = C;
320 //===----------------------------------------------------------------------===//
321 // ARM specific transformation functions and pattern fragments.
324 // imm_neg_XFORM - Return the negation of an i32 immediate value.
325 def imm_neg_XFORM : SDNodeXForm<imm, [{
326 return CurDAG->getTargetConstant(-(int)N->getZExtValue(), MVT::i32);
329 // imm_not_XFORM - Return the complement of a i32 immediate value.
330 def imm_not_XFORM : SDNodeXForm<imm, [{
331 return CurDAG->getTargetConstant(~(int)N->getZExtValue(), MVT::i32);
334 /// imm16_31 predicate - True if the 32-bit immediate is in the range [16,31].
335 def imm16_31 : ImmLeaf<i32, [{
336 return (int32_t)Imm >= 16 && (int32_t)Imm < 32;
339 // sext_16_node predicate - True if the SDNode is sign-extended 16 or more bits.
340 def sext_16_node : PatLeaf<(i32 GPR:$a), [{
341 return CurDAG->ComputeNumSignBits(SDValue(N,0)) >= 17;
344 /// Split a 32-bit immediate into two 16 bit parts.
345 def hi16 : SDNodeXForm<imm, [{
346 return CurDAG->getTargetConstant((uint32_t)N->getZExtValue() >> 16, MVT::i32);
349 def lo16AllZero : PatLeaf<(i32 imm), [{
350 // Returns true if all low 16-bits are 0.
351 return (((uint32_t)N->getZExtValue()) & 0xFFFFUL) == 0;
354 class BinOpWithFlagFrag<dag res> :
355 PatFrag<(ops node:$LHS, node:$RHS, node:$FLAG), res>;
356 class BinOpFrag<dag res> : PatFrag<(ops node:$LHS, node:$RHS), res>;
357 class UnOpFrag <dag res> : PatFrag<(ops node:$Src), res>;
359 // An 'and' node with a single use.
360 def and_su : PatFrag<(ops node:$lhs, node:$rhs), (and node:$lhs, node:$rhs), [{
361 return N->hasOneUse();
364 // An 'xor' node with a single use.
365 def xor_su : PatFrag<(ops node:$lhs, node:$rhs), (xor node:$lhs, node:$rhs), [{
366 return N->hasOneUse();
369 // An 'fmul' node with a single use.
370 def fmul_su : PatFrag<(ops node:$lhs, node:$rhs), (fmul node:$lhs, node:$rhs),[{
371 return N->hasOneUse();
374 // An 'fadd' node which checks for single non-hazardous use.
375 def fadd_mlx : PatFrag<(ops node:$lhs, node:$rhs),(fadd node:$lhs, node:$rhs),[{
376 return hasNoVMLxHazardUse(N);
379 // An 'fsub' node which checks for single non-hazardous use.
380 def fsub_mlx : PatFrag<(ops node:$lhs, node:$rhs),(fsub node:$lhs, node:$rhs),[{
381 return hasNoVMLxHazardUse(N);
384 //===----------------------------------------------------------------------===//
385 // Operand Definitions.
388 // Immediate operands with a shared generic asm render method.
389 class ImmAsmOperand : AsmOperandClass { let RenderMethod = "addImmOperands"; }
391 // Operands that are part of a memory addressing mode.
392 class MemOperand : Operand<i32> { let OperandType = "OPERAND_MEMORY"; }
395 // FIXME: rename brtarget to t2_brtarget
396 def brtarget : Operand<OtherVT> {
397 let EncoderMethod = "getBranchTargetOpValue";
398 let OperandType = "OPERAND_PCREL";
399 let DecoderMethod = "DecodeT2BROperand";
402 // FIXME: get rid of this one?
403 def uncondbrtarget : Operand<OtherVT> {
404 let EncoderMethod = "getUnconditionalBranchTargetOpValue";
405 let OperandType = "OPERAND_PCREL";
408 // Branch target for ARM. Handles conditional/unconditional
409 def br_target : Operand<OtherVT> {
410 let EncoderMethod = "getARMBranchTargetOpValue";
411 let OperandType = "OPERAND_PCREL";
415 // FIXME: rename bltarget to t2_bl_target?
416 def bltarget : Operand<i32> {
417 // Encoded the same as branch targets.
418 let EncoderMethod = "getBranchTargetOpValue";
419 let OperandType = "OPERAND_PCREL";
422 // Call target for ARM. Handles conditional/unconditional
423 // FIXME: rename bl_target to t2_bltarget?
424 def bl_target : Operand<i32> {
425 let EncoderMethod = "getARMBLTargetOpValue";
426 let OperandType = "OPERAND_PCREL";
429 def blx_target : Operand<i32> {
430 let EncoderMethod = "getARMBLXTargetOpValue";
431 let OperandType = "OPERAND_PCREL";
434 // A list of registers separated by comma. Used by load/store multiple.
435 def RegListAsmOperand : AsmOperandClass { let Name = "RegList"; }
436 def reglist : Operand<i32> {
437 let EncoderMethod = "getRegisterListOpValue";
438 let ParserMatchClass = RegListAsmOperand;
439 let PrintMethod = "printRegisterList";
440 let DecoderMethod = "DecodeRegListOperand";
443 def GPRPairOp : RegisterOperand<GPRPair, "printGPRPairOperand">;
445 def DPRRegListAsmOperand : AsmOperandClass { let Name = "DPRRegList"; }
446 def dpr_reglist : Operand<i32> {
447 let EncoderMethod = "getRegisterListOpValue";
448 let ParserMatchClass = DPRRegListAsmOperand;
449 let PrintMethod = "printRegisterList";
450 let DecoderMethod = "DecodeDPRRegListOperand";
453 def SPRRegListAsmOperand : AsmOperandClass { let Name = "SPRRegList"; }
454 def spr_reglist : Operand<i32> {
455 let EncoderMethod = "getRegisterListOpValue";
456 let ParserMatchClass = SPRRegListAsmOperand;
457 let PrintMethod = "printRegisterList";
458 let DecoderMethod = "DecodeSPRRegListOperand";
461 // An operand for the CONSTPOOL_ENTRY pseudo-instruction.
462 def cpinst_operand : Operand<i32> {
463 let PrintMethod = "printCPInstOperand";
467 def pclabel : Operand<i32> {
468 let PrintMethod = "printPCLabel";
471 // ADR instruction labels.
472 def AdrLabelAsmOperand : AsmOperandClass { let Name = "AdrLabel"; }
473 def adrlabel : Operand<i32> {
474 let EncoderMethod = "getAdrLabelOpValue";
475 let ParserMatchClass = AdrLabelAsmOperand;
476 let PrintMethod = "printAdrLabelOperand<0>";
479 def neon_vcvt_imm32 : Operand<i32> {
480 let EncoderMethod = "getNEONVcvtImm32OpValue";
481 let DecoderMethod = "DecodeVCVTImmOperand";
484 // rot_imm: An integer that encodes a rotate amount. Must be 8, 16, or 24.
485 def rot_imm_XFORM: SDNodeXForm<imm, [{
486 switch (N->getZExtValue()){
487 default: llvm_unreachable(nullptr);
488 case 0: return CurDAG->getTargetConstant(0, MVT::i32);
489 case 8: return CurDAG->getTargetConstant(1, MVT::i32);
490 case 16: return CurDAG->getTargetConstant(2, MVT::i32);
491 case 24: return CurDAG->getTargetConstant(3, MVT::i32);
494 def RotImmAsmOperand : AsmOperandClass {
496 let ParserMethod = "parseRotImm";
498 def rot_imm : Operand<i32>, PatLeaf<(i32 imm), [{
499 int32_t v = N->getZExtValue();
500 return v == 8 || v == 16 || v == 24; }],
502 let PrintMethod = "printRotImmOperand";
503 let ParserMatchClass = RotImmAsmOperand;
506 // shift_imm: An integer that encodes a shift amount and the type of shift
507 // (asr or lsl). The 6-bit immediate encodes as:
510 // {4-0} imm5 shift amount.
511 // asr #32 encoded as imm5 == 0.
512 def ShifterImmAsmOperand : AsmOperandClass {
513 let Name = "ShifterImm";
514 let ParserMethod = "parseShifterImm";
516 def shift_imm : Operand<i32> {
517 let PrintMethod = "printShiftImmOperand";
518 let ParserMatchClass = ShifterImmAsmOperand;
521 // shifter_operand operands: so_reg_reg, so_reg_imm, and mod_imm.
522 def ShiftedRegAsmOperand : AsmOperandClass { let Name = "RegShiftedReg"; }
523 def so_reg_reg : Operand<i32>, // reg reg imm
524 ComplexPattern<i32, 3, "SelectRegShifterOperand",
525 [shl, srl, sra, rotr]> {
526 let EncoderMethod = "getSORegRegOpValue";
527 let PrintMethod = "printSORegRegOperand";
528 let DecoderMethod = "DecodeSORegRegOperand";
529 let ParserMatchClass = ShiftedRegAsmOperand;
530 let MIOperandInfo = (ops GPRnopc, GPRnopc, i32imm);
533 def ShiftedImmAsmOperand : AsmOperandClass { let Name = "RegShiftedImm"; }
534 def so_reg_imm : Operand<i32>, // reg imm
535 ComplexPattern<i32, 2, "SelectImmShifterOperand",
536 [shl, srl, sra, rotr]> {
537 let EncoderMethod = "getSORegImmOpValue";
538 let PrintMethod = "printSORegImmOperand";
539 let DecoderMethod = "DecodeSORegImmOperand";
540 let ParserMatchClass = ShiftedImmAsmOperand;
541 let MIOperandInfo = (ops GPR, i32imm);
544 // FIXME: Does this need to be distinct from so_reg?
545 def shift_so_reg_reg : Operand<i32>, // reg reg imm
546 ComplexPattern<i32, 3, "SelectShiftRegShifterOperand",
547 [shl,srl,sra,rotr]> {
548 let EncoderMethod = "getSORegRegOpValue";
549 let PrintMethod = "printSORegRegOperand";
550 let DecoderMethod = "DecodeSORegRegOperand";
551 let ParserMatchClass = ShiftedRegAsmOperand;
552 let MIOperandInfo = (ops GPR, GPR, i32imm);
555 // FIXME: Does this need to be distinct from so_reg?
556 def shift_so_reg_imm : Operand<i32>, // reg reg imm
557 ComplexPattern<i32, 2, "SelectShiftImmShifterOperand",
558 [shl,srl,sra,rotr]> {
559 let EncoderMethod = "getSORegImmOpValue";
560 let PrintMethod = "printSORegImmOperand";
561 let DecoderMethod = "DecodeSORegImmOperand";
562 let ParserMatchClass = ShiftedImmAsmOperand;
563 let MIOperandInfo = (ops GPR, i32imm);
566 // mod_imm: match a 32-bit immediate operand, which can be encoded into
567 // a 12-bit immediate; an 8-bit integer and a 4-bit rotator (See ARMARM
568 // - "Modified Immediate Constants"). Within the MC layer we keep this
569 // immediate in its encoded form.
570 def ModImmAsmOperand: AsmOperandClass {
572 let ParserMethod = "parseModImm";
574 def mod_imm : Operand<i32>, ImmLeaf<i32, [{
575 return ARM_AM::getSOImmVal(Imm) != -1;
577 let EncoderMethod = "getModImmOpValue";
578 let PrintMethod = "printModImmOperand";
579 let ParserMatchClass = ModImmAsmOperand;
582 // Note: the patterns mod_imm_not and mod_imm_neg do not require an encoder
583 // method and such, as they are only used on aliases (Pat<> and InstAlias<>).
584 // The actual parsing, encoding, decoding are handled by the destination
585 // instructions, which use mod_imm.
587 def ModImmNotAsmOperand : AsmOperandClass { let Name = "ModImmNot"; }
588 def mod_imm_not : Operand<i32>, PatLeaf<(imm), [{
589 return ARM_AM::getSOImmVal(~(uint32_t)N->getZExtValue()) != -1;
591 let ParserMatchClass = ModImmNotAsmOperand;
594 def ModImmNegAsmOperand : AsmOperandClass { let Name = "ModImmNeg"; }
595 def mod_imm_neg : Operand<i32>, PatLeaf<(imm), [{
596 unsigned Value = -(unsigned)N->getZExtValue();
597 return Value && ARM_AM::getSOImmVal(Value) != -1;
599 let ParserMatchClass = ModImmNegAsmOperand;
602 /// arm_i32imm - True for +V6T2, or when isSOImmTwoParVal()
603 def arm_i32imm : PatLeaf<(imm), [{
604 if (Subtarget->useMovt(*MF))
606 return ARM_AM::isSOImmTwoPartVal((unsigned)N->getZExtValue());
609 /// imm0_1 predicate - Immediate in the range [0,1].
610 def Imm0_1AsmOperand: ImmAsmOperand { let Name = "Imm0_1"; }
611 def imm0_1 : Operand<i32> { let ParserMatchClass = Imm0_1AsmOperand; }
613 /// imm0_3 predicate - Immediate in the range [0,3].
614 def Imm0_3AsmOperand: ImmAsmOperand { let Name = "Imm0_3"; }
615 def imm0_3 : Operand<i32> { let ParserMatchClass = Imm0_3AsmOperand; }
617 /// imm0_7 predicate - Immediate in the range [0,7].
618 def Imm0_7AsmOperand: ImmAsmOperand { let Name = "Imm0_7"; }
619 def imm0_7 : Operand<i32>, ImmLeaf<i32, [{
620 return Imm >= 0 && Imm < 8;
622 let ParserMatchClass = Imm0_7AsmOperand;
625 /// imm8 predicate - Immediate is exactly 8.
626 def Imm8AsmOperand: ImmAsmOperand { let Name = "Imm8"; }
627 def imm8 : Operand<i32>, ImmLeaf<i32, [{ return Imm == 8; }]> {
628 let ParserMatchClass = Imm8AsmOperand;
631 /// imm16 predicate - Immediate is exactly 16.
632 def Imm16AsmOperand: ImmAsmOperand { let Name = "Imm16"; }
633 def imm16 : Operand<i32>, ImmLeaf<i32, [{ return Imm == 16; }]> {
634 let ParserMatchClass = Imm16AsmOperand;
637 /// imm32 predicate - Immediate is exactly 32.
638 def Imm32AsmOperand: ImmAsmOperand { let Name = "Imm32"; }
639 def imm32 : Operand<i32>, ImmLeaf<i32, [{ return Imm == 32; }]> {
640 let ParserMatchClass = Imm32AsmOperand;
643 def imm8_or_16 : ImmLeaf<i32, [{ return Imm == 8 || Imm == 16;}]>;
645 /// imm1_7 predicate - Immediate in the range [1,7].
646 def Imm1_7AsmOperand: ImmAsmOperand { let Name = "Imm1_7"; }
647 def imm1_7 : Operand<i32>, ImmLeaf<i32, [{ return Imm > 0 && Imm < 8; }]> {
648 let ParserMatchClass = Imm1_7AsmOperand;
651 /// imm1_15 predicate - Immediate in the range [1,15].
652 def Imm1_15AsmOperand: ImmAsmOperand { let Name = "Imm1_15"; }
653 def imm1_15 : Operand<i32>, ImmLeaf<i32, [{ return Imm > 0 && Imm < 16; }]> {
654 let ParserMatchClass = Imm1_15AsmOperand;
657 /// imm1_31 predicate - Immediate in the range [1,31].
658 def Imm1_31AsmOperand: ImmAsmOperand { let Name = "Imm1_31"; }
659 def imm1_31 : Operand<i32>, ImmLeaf<i32, [{ return Imm > 0 && Imm < 32; }]> {
660 let ParserMatchClass = Imm1_31AsmOperand;
663 /// imm0_15 predicate - Immediate in the range [0,15].
664 def Imm0_15AsmOperand: ImmAsmOperand {
665 let Name = "Imm0_15";
666 let DiagnosticType = "ImmRange0_15";
668 def imm0_15 : Operand<i32>, ImmLeaf<i32, [{
669 return Imm >= 0 && Imm < 16;
671 let ParserMatchClass = Imm0_15AsmOperand;
674 /// imm0_31 predicate - True if the 32-bit immediate is in the range [0,31].
675 def Imm0_31AsmOperand: ImmAsmOperand { let Name = "Imm0_31"; }
676 def imm0_31 : Operand<i32>, ImmLeaf<i32, [{
677 return Imm >= 0 && Imm < 32;
679 let ParserMatchClass = Imm0_31AsmOperand;
682 /// imm0_32 predicate - True if the 32-bit immediate is in the range [0,32].
683 def Imm0_32AsmOperand: ImmAsmOperand { let Name = "Imm0_32"; }
684 def imm0_32 : Operand<i32>, ImmLeaf<i32, [{
685 return Imm >= 0 && Imm < 32;
687 let ParserMatchClass = Imm0_32AsmOperand;
690 /// imm0_63 predicate - True if the 32-bit immediate is in the range [0,63].
691 def Imm0_63AsmOperand: ImmAsmOperand { let Name = "Imm0_63"; }
692 def imm0_63 : Operand<i32>, ImmLeaf<i32, [{
693 return Imm >= 0 && Imm < 64;
695 let ParserMatchClass = Imm0_63AsmOperand;
698 /// imm0_239 predicate - Immediate in the range [0,239].
699 def Imm0_239AsmOperand : ImmAsmOperand {
700 let Name = "Imm0_239";
701 let DiagnosticType = "ImmRange0_239";
703 def imm0_239 : Operand<i32>, ImmLeaf<i32, [{ return Imm >= 0 && Imm < 240; }]> {
704 let ParserMatchClass = Imm0_239AsmOperand;
707 /// imm0_255 predicate - Immediate in the range [0,255].
708 def Imm0_255AsmOperand : ImmAsmOperand { let Name = "Imm0_255"; }
709 def imm0_255 : Operand<i32>, ImmLeaf<i32, [{ return Imm >= 0 && Imm < 256; }]> {
710 let ParserMatchClass = Imm0_255AsmOperand;
713 /// imm0_65535 - An immediate is in the range [0.65535].
714 def Imm0_65535AsmOperand: ImmAsmOperand { let Name = "Imm0_65535"; }
715 def imm0_65535 : Operand<i32>, ImmLeaf<i32, [{
716 return Imm >= 0 && Imm < 65536;
718 let ParserMatchClass = Imm0_65535AsmOperand;
721 // imm0_65535_neg - An immediate whose negative value is in the range [0.65535].
722 def imm0_65535_neg : Operand<i32>, ImmLeaf<i32, [{
723 return -Imm >= 0 && -Imm < 65536;
726 // imm0_65535_expr - For movt/movw - 16-bit immediate that can also reference
727 // a relocatable expression.
729 // FIXME: This really needs a Thumb version separate from the ARM version.
730 // While the range is the same, and can thus use the same match class,
731 // the encoding is different so it should have a different encoder method.
732 def Imm0_65535ExprAsmOperand: ImmAsmOperand { let Name = "Imm0_65535Expr"; }
733 def imm0_65535_expr : Operand<i32> {
734 let EncoderMethod = "getHiLo16ImmOpValue";
735 let ParserMatchClass = Imm0_65535ExprAsmOperand;
738 def Imm256_65535ExprAsmOperand: ImmAsmOperand { let Name = "Imm256_65535Expr"; }
739 def imm256_65535_expr : Operand<i32> {
740 let ParserMatchClass = Imm256_65535ExprAsmOperand;
743 /// imm24b - True if the 32-bit immediate is encodable in 24 bits.
744 def Imm24bitAsmOperand: ImmAsmOperand { let Name = "Imm24bit"; }
745 def imm24b : Operand<i32>, ImmLeaf<i32, [{
746 return Imm >= 0 && Imm <= 0xffffff;
748 let ParserMatchClass = Imm24bitAsmOperand;
752 /// bf_inv_mask_imm predicate - An AND mask to clear an arbitrary width bitfield
754 def BitfieldAsmOperand : AsmOperandClass {
755 let Name = "Bitfield";
756 let ParserMethod = "parseBitfield";
759 def bf_inv_mask_imm : Operand<i32>,
761 return ARM::isBitFieldInvertedMask(N->getZExtValue());
763 let EncoderMethod = "getBitfieldInvertedMaskOpValue";
764 let PrintMethod = "printBitfieldInvMaskImmOperand";
765 let DecoderMethod = "DecodeBitfieldMaskOperand";
766 let ParserMatchClass = BitfieldAsmOperand;
769 def imm1_32_XFORM: SDNodeXForm<imm, [{
770 return CurDAG->getTargetConstant((int)N->getZExtValue() - 1, MVT::i32);
772 def Imm1_32AsmOperand: AsmOperandClass { let Name = "Imm1_32"; }
773 def imm1_32 : Operand<i32>, PatLeaf<(imm), [{
774 uint64_t Imm = N->getZExtValue();
775 return Imm > 0 && Imm <= 32;
778 let PrintMethod = "printImmPlusOneOperand";
779 let ParserMatchClass = Imm1_32AsmOperand;
782 def imm1_16_XFORM: SDNodeXForm<imm, [{
783 return CurDAG->getTargetConstant((int)N->getZExtValue() - 1, MVT::i32);
785 def Imm1_16AsmOperand: AsmOperandClass { let Name = "Imm1_16"; }
786 def imm1_16 : Operand<i32>, PatLeaf<(imm), [{ return Imm > 0 && Imm <= 16; }],
788 let PrintMethod = "printImmPlusOneOperand";
789 let ParserMatchClass = Imm1_16AsmOperand;
792 // Define ARM specific addressing modes.
793 // addrmode_imm12 := reg +/- imm12
795 def MemImm12OffsetAsmOperand : AsmOperandClass { let Name = "MemImm12Offset"; }
796 class AddrMode_Imm12 : MemOperand,
797 ComplexPattern<i32, 2, "SelectAddrModeImm12", []> {
798 // 12-bit immediate operand. Note that instructions using this encode
799 // #0 and #-0 differently. We flag #-0 as the magic value INT32_MIN. All other
800 // immediate values are as normal.
802 let EncoderMethod = "getAddrModeImm12OpValue";
803 let DecoderMethod = "DecodeAddrModeImm12Operand";
804 let ParserMatchClass = MemImm12OffsetAsmOperand;
805 let MIOperandInfo = (ops GPR:$base, i32imm:$offsimm);
808 def addrmode_imm12 : AddrMode_Imm12 {
809 let PrintMethod = "printAddrModeImm12Operand<false>";
812 def addrmode_imm12_pre : AddrMode_Imm12 {
813 let PrintMethod = "printAddrModeImm12Operand<true>";
816 // ldst_so_reg := reg +/- reg shop imm
818 def MemRegOffsetAsmOperand : AsmOperandClass { let Name = "MemRegOffset"; }
819 def ldst_so_reg : MemOperand,
820 ComplexPattern<i32, 3, "SelectLdStSOReg", []> {
821 let EncoderMethod = "getLdStSORegOpValue";
822 // FIXME: Simplify the printer
823 let PrintMethod = "printAddrMode2Operand";
824 let DecoderMethod = "DecodeSORegMemOperand";
825 let ParserMatchClass = MemRegOffsetAsmOperand;
826 let MIOperandInfo = (ops GPR:$base, GPRnopc:$offsreg, i32imm:$shift);
829 // postidx_imm8 := +/- [0,255]
832 // {8} 1 is imm8 is non-negative. 0 otherwise.
833 // {7-0} [0,255] imm8 value.
834 def PostIdxImm8AsmOperand : AsmOperandClass { let Name = "PostIdxImm8"; }
835 def postidx_imm8 : MemOperand {
836 let PrintMethod = "printPostIdxImm8Operand";
837 let ParserMatchClass = PostIdxImm8AsmOperand;
838 let MIOperandInfo = (ops i32imm);
841 // postidx_imm8s4 := +/- [0,1020]
844 // {8} 1 is imm8 is non-negative. 0 otherwise.
845 // {7-0} [0,255] imm8 value, scaled by 4.
846 def PostIdxImm8s4AsmOperand : AsmOperandClass { let Name = "PostIdxImm8s4"; }
847 def postidx_imm8s4 : MemOperand {
848 let PrintMethod = "printPostIdxImm8s4Operand";
849 let ParserMatchClass = PostIdxImm8s4AsmOperand;
850 let MIOperandInfo = (ops i32imm);
854 // postidx_reg := +/- reg
856 def PostIdxRegAsmOperand : AsmOperandClass {
857 let Name = "PostIdxReg";
858 let ParserMethod = "parsePostIdxReg";
860 def postidx_reg : MemOperand {
861 let EncoderMethod = "getPostIdxRegOpValue";
862 let DecoderMethod = "DecodePostIdxReg";
863 let PrintMethod = "printPostIdxRegOperand";
864 let ParserMatchClass = PostIdxRegAsmOperand;
865 let MIOperandInfo = (ops GPRnopc, i32imm);
869 // addrmode2 := reg +/- imm12
870 // := reg +/- reg shop imm
872 // FIXME: addrmode2 should be refactored the rest of the way to always
873 // use explicit imm vs. reg versions above (addrmode_imm12 and ldst_so_reg).
874 def AddrMode2AsmOperand : AsmOperandClass { let Name = "AddrMode2"; }
875 def addrmode2 : MemOperand,
876 ComplexPattern<i32, 3, "SelectAddrMode2", []> {
877 let EncoderMethod = "getAddrMode2OpValue";
878 let PrintMethod = "printAddrMode2Operand";
879 let ParserMatchClass = AddrMode2AsmOperand;
880 let MIOperandInfo = (ops GPR:$base, GPR:$offsreg, i32imm:$offsimm);
883 def PostIdxRegShiftedAsmOperand : AsmOperandClass {
884 let Name = "PostIdxRegShifted";
885 let ParserMethod = "parsePostIdxReg";
887 def am2offset_reg : MemOperand,
888 ComplexPattern<i32, 2, "SelectAddrMode2OffsetReg",
889 [], [SDNPWantRoot]> {
890 let EncoderMethod = "getAddrMode2OffsetOpValue";
891 let PrintMethod = "printAddrMode2OffsetOperand";
892 // When using this for assembly, it's always as a post-index offset.
893 let ParserMatchClass = PostIdxRegShiftedAsmOperand;
894 let MIOperandInfo = (ops GPRnopc, i32imm);
897 // FIXME: am2offset_imm should only need the immediate, not the GPR. Having
898 // the GPR is purely vestigal at this point.
899 def AM2OffsetImmAsmOperand : AsmOperandClass { let Name = "AM2OffsetImm"; }
900 def am2offset_imm : MemOperand,
901 ComplexPattern<i32, 2, "SelectAddrMode2OffsetImm",
902 [], [SDNPWantRoot]> {
903 let EncoderMethod = "getAddrMode2OffsetOpValue";
904 let PrintMethod = "printAddrMode2OffsetOperand";
905 let ParserMatchClass = AM2OffsetImmAsmOperand;
906 let MIOperandInfo = (ops GPRnopc, i32imm);
910 // addrmode3 := reg +/- reg
911 // addrmode3 := reg +/- imm8
913 // FIXME: split into imm vs. reg versions.
914 def AddrMode3AsmOperand : AsmOperandClass { let Name = "AddrMode3"; }
915 class AddrMode3 : MemOperand,
916 ComplexPattern<i32, 3, "SelectAddrMode3", []> {
917 let EncoderMethod = "getAddrMode3OpValue";
918 let ParserMatchClass = AddrMode3AsmOperand;
919 let MIOperandInfo = (ops GPR:$base, GPR:$offsreg, i32imm:$offsimm);
922 def addrmode3 : AddrMode3
924 let PrintMethod = "printAddrMode3Operand<false>";
927 def addrmode3_pre : AddrMode3
929 let PrintMethod = "printAddrMode3Operand<true>";
932 // FIXME: split into imm vs. reg versions.
933 // FIXME: parser method to handle +/- register.
934 def AM3OffsetAsmOperand : AsmOperandClass {
935 let Name = "AM3Offset";
936 let ParserMethod = "parseAM3Offset";
938 def am3offset : MemOperand,
939 ComplexPattern<i32, 2, "SelectAddrMode3Offset",
940 [], [SDNPWantRoot]> {
941 let EncoderMethod = "getAddrMode3OffsetOpValue";
942 let PrintMethod = "printAddrMode3OffsetOperand";
943 let ParserMatchClass = AM3OffsetAsmOperand;
944 let MIOperandInfo = (ops GPR, i32imm);
947 // ldstm_mode := {ia, ib, da, db}
949 def ldstm_mode : OptionalDefOperand<OtherVT, (ops i32), (ops (i32 1))> {
950 let EncoderMethod = "getLdStmModeOpValue";
951 let PrintMethod = "printLdStmModeOperand";
954 // addrmode5 := reg +/- imm8*4
956 def AddrMode5AsmOperand : AsmOperandClass { let Name = "AddrMode5"; }
957 class AddrMode5 : MemOperand,
958 ComplexPattern<i32, 2, "SelectAddrMode5", []> {
959 let EncoderMethod = "getAddrMode5OpValue";
960 let DecoderMethod = "DecodeAddrMode5Operand";
961 let ParserMatchClass = AddrMode5AsmOperand;
962 let MIOperandInfo = (ops GPR:$base, i32imm);
965 def addrmode5 : AddrMode5 {
966 let PrintMethod = "printAddrMode5Operand<false>";
969 def addrmode5_pre : AddrMode5 {
970 let PrintMethod = "printAddrMode5Operand<true>";
973 // addrmode6 := reg with optional alignment
975 def AddrMode6AsmOperand : AsmOperandClass { let Name = "AlignedMemory"; }
976 def addrmode6 : MemOperand,
977 ComplexPattern<i32, 2, "SelectAddrMode6", [], [SDNPWantParent]>{
978 let PrintMethod = "printAddrMode6Operand";
979 let MIOperandInfo = (ops GPR:$addr, i32imm:$align);
980 let EncoderMethod = "getAddrMode6AddressOpValue";
981 let DecoderMethod = "DecodeAddrMode6Operand";
982 let ParserMatchClass = AddrMode6AsmOperand;
985 def am6offset : MemOperand,
986 ComplexPattern<i32, 1, "SelectAddrMode6Offset",
987 [], [SDNPWantRoot]> {
988 let PrintMethod = "printAddrMode6OffsetOperand";
989 let MIOperandInfo = (ops GPR);
990 let EncoderMethod = "getAddrMode6OffsetOpValue";
991 let DecoderMethod = "DecodeGPRRegisterClass";
994 // Special version of addrmode6 to handle alignment encoding for VST1/VLD1
995 // (single element from one lane) for size 32.
996 def addrmode6oneL32 : MemOperand,
997 ComplexPattern<i32, 2, "SelectAddrMode6", [], [SDNPWantParent]>{
998 let PrintMethod = "printAddrMode6Operand";
999 let MIOperandInfo = (ops GPR:$addr, i32imm);
1000 let EncoderMethod = "getAddrMode6OneLane32AddressOpValue";
1003 // Base class for addrmode6 with specific alignment restrictions.
1004 class AddrMode6Align : MemOperand,
1005 ComplexPattern<i32, 2, "SelectAddrMode6", [], [SDNPWantParent]>{
1006 let PrintMethod = "printAddrMode6Operand";
1007 let MIOperandInfo = (ops GPR:$addr, i32imm:$align);
1008 let EncoderMethod = "getAddrMode6AddressOpValue";
1009 let DecoderMethod = "DecodeAddrMode6Operand";
1012 // Special version of addrmode6 to handle no allowed alignment encoding for
1013 // VLD/VST instructions and checking the alignment is not specified.
1014 def AddrMode6AlignNoneAsmOperand : AsmOperandClass {
1015 let Name = "AlignedMemoryNone";
1016 let DiagnosticType = "AlignedMemoryRequiresNone";
1018 def addrmode6alignNone : AddrMode6Align {
1019 // The alignment specifier can only be omitted.
1020 let ParserMatchClass = AddrMode6AlignNoneAsmOperand;
1023 // Special version of addrmode6 to handle 16-bit alignment encoding for
1024 // VLD/VST instructions and checking the alignment value.
1025 def AddrMode6Align16AsmOperand : AsmOperandClass {
1026 let Name = "AlignedMemory16";
1027 let DiagnosticType = "AlignedMemoryRequires16";
1029 def addrmode6align16 : AddrMode6Align {
1030 // The alignment specifier can only be 16 or omitted.
1031 let ParserMatchClass = AddrMode6Align16AsmOperand;
1034 // Special version of addrmode6 to handle 32-bit alignment encoding for
1035 // VLD/VST instructions and checking the alignment value.
1036 def AddrMode6Align32AsmOperand : AsmOperandClass {
1037 let Name = "AlignedMemory32";
1038 let DiagnosticType = "AlignedMemoryRequires32";
1040 def addrmode6align32 : AddrMode6Align {
1041 // The alignment specifier can only be 32 or omitted.
1042 let ParserMatchClass = AddrMode6Align32AsmOperand;
1045 // Special version of addrmode6 to handle 64-bit alignment encoding for
1046 // VLD/VST instructions and checking the alignment value.
1047 def AddrMode6Align64AsmOperand : AsmOperandClass {
1048 let Name = "AlignedMemory64";
1049 let DiagnosticType = "AlignedMemoryRequires64";
1051 def addrmode6align64 : AddrMode6Align {
1052 // The alignment specifier can only be 64 or omitted.
1053 let ParserMatchClass = AddrMode6Align64AsmOperand;
1056 // Special version of addrmode6 to handle 64-bit or 128-bit alignment encoding
1057 // for VLD/VST instructions and checking the alignment value.
1058 def AddrMode6Align64or128AsmOperand : AsmOperandClass {
1059 let Name = "AlignedMemory64or128";
1060 let DiagnosticType = "AlignedMemoryRequires64or128";
1062 def addrmode6align64or128 : AddrMode6Align {
1063 // The alignment specifier can only be 64, 128 or omitted.
1064 let ParserMatchClass = AddrMode6Align64or128AsmOperand;
1067 // Special version of addrmode6 to handle 64-bit, 128-bit or 256-bit alignment
1068 // encoding for VLD/VST instructions and checking the alignment value.
1069 def AddrMode6Align64or128or256AsmOperand : AsmOperandClass {
1070 let Name = "AlignedMemory64or128or256";
1071 let DiagnosticType = "AlignedMemoryRequires64or128or256";
1073 def addrmode6align64or128or256 : AddrMode6Align {
1074 // The alignment specifier can only be 64, 128, 256 or omitted.
1075 let ParserMatchClass = AddrMode6Align64or128or256AsmOperand;
1078 // Special version of addrmode6 to handle alignment encoding for VLD-dup
1079 // instructions, specifically VLD4-dup.
1080 def addrmode6dup : MemOperand,
1081 ComplexPattern<i32, 2, "SelectAddrMode6", [], [SDNPWantParent]>{
1082 let PrintMethod = "printAddrMode6Operand";
1083 let MIOperandInfo = (ops GPR:$addr, i32imm);
1084 let EncoderMethod = "getAddrMode6DupAddressOpValue";
1085 // FIXME: This is close, but not quite right. The alignment specifier is
1087 let ParserMatchClass = AddrMode6AsmOperand;
1090 // Base class for addrmode6dup with specific alignment restrictions.
1091 class AddrMode6DupAlign : MemOperand,
1092 ComplexPattern<i32, 2, "SelectAddrMode6", [], [SDNPWantParent]>{
1093 let PrintMethod = "printAddrMode6Operand";
1094 let MIOperandInfo = (ops GPR:$addr, i32imm);
1095 let EncoderMethod = "getAddrMode6DupAddressOpValue";
1098 // Special version of addrmode6 to handle no allowed alignment encoding for
1099 // VLD-dup instruction and checking the alignment is not specified.
1100 def AddrMode6dupAlignNoneAsmOperand : AsmOperandClass {
1101 let Name = "DupAlignedMemoryNone";
1102 let DiagnosticType = "DupAlignedMemoryRequiresNone";
1104 def addrmode6dupalignNone : AddrMode6DupAlign {
1105 // The alignment specifier can only be omitted.
1106 let ParserMatchClass = AddrMode6dupAlignNoneAsmOperand;
1109 // Special version of addrmode6 to handle 16-bit alignment encoding for VLD-dup
1110 // instruction and checking the alignment value.
1111 def AddrMode6dupAlign16AsmOperand : AsmOperandClass {
1112 let Name = "DupAlignedMemory16";
1113 let DiagnosticType = "DupAlignedMemoryRequires16";
1115 def addrmode6dupalign16 : AddrMode6DupAlign {
1116 // The alignment specifier can only be 16 or omitted.
1117 let ParserMatchClass = AddrMode6dupAlign16AsmOperand;
1120 // Special version of addrmode6 to handle 32-bit alignment encoding for VLD-dup
1121 // instruction and checking the alignment value.
1122 def AddrMode6dupAlign32AsmOperand : AsmOperandClass {
1123 let Name = "DupAlignedMemory32";
1124 let DiagnosticType = "DupAlignedMemoryRequires32";
1126 def addrmode6dupalign32 : AddrMode6DupAlign {
1127 // The alignment specifier can only be 32 or omitted.
1128 let ParserMatchClass = AddrMode6dupAlign32AsmOperand;
1131 // Special version of addrmode6 to handle 64-bit alignment encoding for VLD
1132 // instructions and checking the alignment value.
1133 def AddrMode6dupAlign64AsmOperand : AsmOperandClass {
1134 let Name = "DupAlignedMemory64";
1135 let DiagnosticType = "DupAlignedMemoryRequires64";
1137 def addrmode6dupalign64 : AddrMode6DupAlign {
1138 // The alignment specifier can only be 64 or omitted.
1139 let ParserMatchClass = AddrMode6dupAlign64AsmOperand;
1142 // Special version of addrmode6 to handle 64-bit or 128-bit alignment encoding
1143 // for VLD instructions and checking the alignment value.
1144 def AddrMode6dupAlign64or128AsmOperand : AsmOperandClass {
1145 let Name = "DupAlignedMemory64or128";
1146 let DiagnosticType = "DupAlignedMemoryRequires64or128";
1148 def addrmode6dupalign64or128 : AddrMode6DupAlign {
1149 // The alignment specifier can only be 64, 128 or omitted.
1150 let ParserMatchClass = AddrMode6dupAlign64or128AsmOperand;
1153 // addrmodepc := pc + reg
1155 def addrmodepc : MemOperand,
1156 ComplexPattern<i32, 2, "SelectAddrModePC", []> {
1157 let PrintMethod = "printAddrModePCOperand";
1158 let MIOperandInfo = (ops GPR, i32imm);
1161 // addr_offset_none := reg
1163 def MemNoOffsetAsmOperand : AsmOperandClass { let Name = "MemNoOffset"; }
1164 def addr_offset_none : MemOperand,
1165 ComplexPattern<i32, 1, "SelectAddrOffsetNone", []> {
1166 let PrintMethod = "printAddrMode7Operand";
1167 let DecoderMethod = "DecodeAddrMode7Operand";
1168 let ParserMatchClass = MemNoOffsetAsmOperand;
1169 let MIOperandInfo = (ops GPR:$base);
1172 def nohash_imm : Operand<i32> {
1173 let PrintMethod = "printNoHashImmediate";
1176 def CoprocNumAsmOperand : AsmOperandClass {
1177 let Name = "CoprocNum";
1178 let ParserMethod = "parseCoprocNumOperand";
1180 def p_imm : Operand<i32> {
1181 let PrintMethod = "printPImmediate";
1182 let ParserMatchClass = CoprocNumAsmOperand;
1183 let DecoderMethod = "DecodeCoprocessor";
1186 def CoprocRegAsmOperand : AsmOperandClass {
1187 let Name = "CoprocReg";
1188 let ParserMethod = "parseCoprocRegOperand";
1190 def c_imm : Operand<i32> {
1191 let PrintMethod = "printCImmediate";
1192 let ParserMatchClass = CoprocRegAsmOperand;
1194 def CoprocOptionAsmOperand : AsmOperandClass {
1195 let Name = "CoprocOption";
1196 let ParserMethod = "parseCoprocOptionOperand";
1198 def coproc_option_imm : Operand<i32> {
1199 let PrintMethod = "printCoprocOptionImm";
1200 let ParserMatchClass = CoprocOptionAsmOperand;
1203 //===----------------------------------------------------------------------===//
1205 include "ARMInstrFormats.td"
1207 //===----------------------------------------------------------------------===//
1208 // Multiclass helpers...
1211 /// AsI1_bin_irs - Defines a set of (op r, {mod_imm|r|so_reg}) patterns for a
1212 /// binop that produces a value.
1213 let TwoOperandAliasConstraint = "$Rn = $Rd" in
1214 multiclass AsI1_bin_irs<bits<4> opcod, string opc,
1215 InstrItinClass iii, InstrItinClass iir, InstrItinClass iis,
1216 PatFrag opnode, bit Commutable = 0> {
1217 // The register-immediate version is re-materializable. This is useful
1218 // in particular for taking the address of a local.
1219 let isReMaterializable = 1 in {
1220 def ri : AsI1<opcod, (outs GPR:$Rd), (ins GPR:$Rn, mod_imm:$imm), DPFrm,
1221 iii, opc, "\t$Rd, $Rn, $imm",
1222 [(set GPR:$Rd, (opnode GPR:$Rn, mod_imm:$imm))]>,
1223 Sched<[WriteALU, ReadALU]> {
1228 let Inst{19-16} = Rn;
1229 let Inst{15-12} = Rd;
1230 let Inst{11-0} = imm;
1233 def rr : AsI1<opcod, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm), DPFrm,
1234 iir, opc, "\t$Rd, $Rn, $Rm",
1235 [(set GPR:$Rd, (opnode GPR:$Rn, GPR:$Rm))]>,
1236 Sched<[WriteALU, ReadALU, ReadALU]> {
1241 let isCommutable = Commutable;
1242 let Inst{19-16} = Rn;
1243 let Inst{15-12} = Rd;
1244 let Inst{11-4} = 0b00000000;
1248 def rsi : AsI1<opcod, (outs GPR:$Rd),
1249 (ins GPR:$Rn, so_reg_imm:$shift), DPSoRegImmFrm,
1250 iis, opc, "\t$Rd, $Rn, $shift",
1251 [(set GPR:$Rd, (opnode GPR:$Rn, so_reg_imm:$shift))]>,
1252 Sched<[WriteALUsi, ReadALU]> {
1257 let Inst{19-16} = Rn;
1258 let Inst{15-12} = Rd;
1259 let Inst{11-5} = shift{11-5};
1261 let Inst{3-0} = shift{3-0};
1264 def rsr : AsI1<opcod, (outs GPR:$Rd),
1265 (ins GPR:$Rn, so_reg_reg:$shift), DPSoRegRegFrm,
1266 iis, opc, "\t$Rd, $Rn, $shift",
1267 [(set GPR:$Rd, (opnode GPR:$Rn, so_reg_reg:$shift))]>,
1268 Sched<[WriteALUsr, ReadALUsr]> {
1273 let Inst{19-16} = Rn;
1274 let Inst{15-12} = Rd;
1275 let Inst{11-8} = shift{11-8};
1277 let Inst{6-5} = shift{6-5};
1279 let Inst{3-0} = shift{3-0};
1283 /// AsI1_rbin_irs - Same as AsI1_bin_irs except the order of operands are
1284 /// reversed. The 'rr' form is only defined for the disassembler; for codegen
1285 /// it is equivalent to the AsI1_bin_irs counterpart.
1286 let TwoOperandAliasConstraint = "$Rn = $Rd" in
1287 multiclass AsI1_rbin_irs<bits<4> opcod, string opc,
1288 InstrItinClass iii, InstrItinClass iir, InstrItinClass iis,
1289 PatFrag opnode, bit Commutable = 0> {
1290 // The register-immediate version is re-materializable. This is useful
1291 // in particular for taking the address of a local.
1292 let isReMaterializable = 1 in {
1293 def ri : AsI1<opcod, (outs GPR:$Rd), (ins GPR:$Rn, mod_imm:$imm), DPFrm,
1294 iii, opc, "\t$Rd, $Rn, $imm",
1295 [(set GPR:$Rd, (opnode mod_imm:$imm, GPR:$Rn))]>,
1296 Sched<[WriteALU, ReadALU]> {
1301 let Inst{19-16} = Rn;
1302 let Inst{15-12} = Rd;
1303 let Inst{11-0} = imm;
1306 def rr : AsI1<opcod, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm), DPFrm,
1307 iir, opc, "\t$Rd, $Rn, $Rm",
1308 [/* pattern left blank */]>,
1309 Sched<[WriteALU, ReadALU, ReadALU]> {
1313 let Inst{11-4} = 0b00000000;
1316 let Inst{15-12} = Rd;
1317 let Inst{19-16} = Rn;
1320 def rsi : AsI1<opcod, (outs GPR:$Rd),
1321 (ins GPR:$Rn, so_reg_imm:$shift), DPSoRegImmFrm,
1322 iis, opc, "\t$Rd, $Rn, $shift",
1323 [(set GPR:$Rd, (opnode so_reg_imm:$shift, GPR:$Rn))]>,
1324 Sched<[WriteALUsi, ReadALU]> {
1329 let Inst{19-16} = Rn;
1330 let Inst{15-12} = Rd;
1331 let Inst{11-5} = shift{11-5};
1333 let Inst{3-0} = shift{3-0};
1336 def rsr : AsI1<opcod, (outs GPR:$Rd),
1337 (ins GPR:$Rn, so_reg_reg:$shift), DPSoRegRegFrm,
1338 iis, opc, "\t$Rd, $Rn, $shift",
1339 [(set GPR:$Rd, (opnode so_reg_reg:$shift, GPR:$Rn))]>,
1340 Sched<[WriteALUsr, ReadALUsr]> {
1345 let Inst{19-16} = Rn;
1346 let Inst{15-12} = Rd;
1347 let Inst{11-8} = shift{11-8};
1349 let Inst{6-5} = shift{6-5};
1351 let Inst{3-0} = shift{3-0};
1355 /// AsI1_bin_s_irs - Same as AsI1_bin_irs except it sets the 's' bit by default.
1357 /// These opcodes will be converted to the real non-S opcodes by
1358 /// AdjustInstrPostInstrSelection after giving them an optional CPSR operand.
1359 let hasPostISelHook = 1, Defs = [CPSR] in {
1360 multiclass AsI1_bin_s_irs<InstrItinClass iii, InstrItinClass iir,
1361 InstrItinClass iis, PatFrag opnode,
1362 bit Commutable = 0> {
1363 def ri : ARMPseudoInst<(outs GPR:$Rd), (ins GPR:$Rn, mod_imm:$imm, pred:$p),
1365 [(set GPR:$Rd, CPSR, (opnode GPR:$Rn, mod_imm:$imm))]>,
1366 Sched<[WriteALU, ReadALU]>;
1368 def rr : ARMPseudoInst<(outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm, pred:$p),
1370 [(set GPR:$Rd, CPSR, (opnode GPR:$Rn, GPR:$Rm))]>,
1371 Sched<[WriteALU, ReadALU, ReadALU]> {
1372 let isCommutable = Commutable;
1374 def rsi : ARMPseudoInst<(outs GPR:$Rd),
1375 (ins GPR:$Rn, so_reg_imm:$shift, pred:$p),
1377 [(set GPR:$Rd, CPSR, (opnode GPR:$Rn,
1378 so_reg_imm:$shift))]>,
1379 Sched<[WriteALUsi, ReadALU]>;
1381 def rsr : ARMPseudoInst<(outs GPR:$Rd),
1382 (ins GPR:$Rn, so_reg_reg:$shift, pred:$p),
1384 [(set GPR:$Rd, CPSR, (opnode GPR:$Rn,
1385 so_reg_reg:$shift))]>,
1386 Sched<[WriteALUSsr, ReadALUsr]>;
1390 /// AsI1_rbin_s_is - Same as AsI1_bin_s_irs, except selection DAG
1391 /// operands are reversed.
1392 let hasPostISelHook = 1, Defs = [CPSR] in {
1393 multiclass AsI1_rbin_s_is<InstrItinClass iii, InstrItinClass iir,
1394 InstrItinClass iis, PatFrag opnode,
1395 bit Commutable = 0> {
1396 def ri : ARMPseudoInst<(outs GPR:$Rd), (ins GPR:$Rn, mod_imm:$imm, pred:$p),
1398 [(set GPR:$Rd, CPSR, (opnode mod_imm:$imm, GPR:$Rn))]>,
1399 Sched<[WriteALU, ReadALU]>;
1401 def rsi : ARMPseudoInst<(outs GPR:$Rd),
1402 (ins GPR:$Rn, so_reg_imm:$shift, pred:$p),
1404 [(set GPR:$Rd, CPSR, (opnode so_reg_imm:$shift,
1406 Sched<[WriteALUsi, ReadALU]>;
1408 def rsr : ARMPseudoInst<(outs GPR:$Rd),
1409 (ins GPR:$Rn, so_reg_reg:$shift, pred:$p),
1411 [(set GPR:$Rd, CPSR, (opnode so_reg_reg:$shift,
1413 Sched<[WriteALUSsr, ReadALUsr]>;
1417 /// AI1_cmp_irs - Defines a set of (op r, {mod_imm|r|so_reg}) cmp / test
1418 /// patterns. Similar to AsI1_bin_irs except the instruction does not produce
1419 /// a explicit result, only implicitly set CPSR.
1420 let isCompare = 1, Defs = [CPSR] in {
1421 multiclass AI1_cmp_irs<bits<4> opcod, string opc,
1422 InstrItinClass iii, InstrItinClass iir, InstrItinClass iis,
1423 PatFrag opnode, bit Commutable = 0,
1424 string rrDecoderMethod = ""> {
1425 def ri : AI1<opcod, (outs), (ins GPR:$Rn, mod_imm:$imm), DPFrm, iii,
1427 [(opnode GPR:$Rn, mod_imm:$imm)]>,
1428 Sched<[WriteCMP, ReadALU]> {
1433 let Inst{19-16} = Rn;
1434 let Inst{15-12} = 0b0000;
1435 let Inst{11-0} = imm;
1437 let Unpredictable{15-12} = 0b1111;
1439 def rr : AI1<opcod, (outs), (ins GPR:$Rn, GPR:$Rm), DPFrm, iir,
1441 [(opnode GPR:$Rn, GPR:$Rm)]>,
1442 Sched<[WriteCMP, ReadALU, ReadALU]> {
1445 let isCommutable = Commutable;
1448 let Inst{19-16} = Rn;
1449 let Inst{15-12} = 0b0000;
1450 let Inst{11-4} = 0b00000000;
1452 let DecoderMethod = rrDecoderMethod;
1454 let Unpredictable{15-12} = 0b1111;
1456 def rsi : AI1<opcod, (outs),
1457 (ins GPR:$Rn, so_reg_imm:$shift), DPSoRegImmFrm, iis,
1458 opc, "\t$Rn, $shift",
1459 [(opnode GPR:$Rn, so_reg_imm:$shift)]>,
1460 Sched<[WriteCMPsi, ReadALU]> {
1465 let Inst{19-16} = Rn;
1466 let Inst{15-12} = 0b0000;
1467 let Inst{11-5} = shift{11-5};
1469 let Inst{3-0} = shift{3-0};
1471 let Unpredictable{15-12} = 0b1111;
1473 def rsr : AI1<opcod, (outs),
1474 (ins GPRnopc:$Rn, so_reg_reg:$shift), DPSoRegRegFrm, iis,
1475 opc, "\t$Rn, $shift",
1476 [(opnode GPRnopc:$Rn, so_reg_reg:$shift)]>,
1477 Sched<[WriteCMPsr, ReadALU]> {
1482 let Inst{19-16} = Rn;
1483 let Inst{15-12} = 0b0000;
1484 let Inst{11-8} = shift{11-8};
1486 let Inst{6-5} = shift{6-5};
1488 let Inst{3-0} = shift{3-0};
1490 let Unpredictable{15-12} = 0b1111;
1496 /// AI_ext_rrot - A unary operation with two forms: one whose operand is a
1497 /// register and one whose operand is a register rotated by 8/16/24.
1498 /// FIXME: Remove the 'r' variant. Its rot_imm is zero.
1499 class AI_ext_rrot<bits<8> opcod, string opc, PatFrag opnode>
1500 : AExtI<opcod, (outs GPRnopc:$Rd), (ins GPRnopc:$Rm, rot_imm:$rot),
1501 IIC_iEXTr, opc, "\t$Rd, $Rm$rot",
1502 [(set GPRnopc:$Rd, (opnode (rotr GPRnopc:$Rm, rot_imm:$rot)))]>,
1503 Requires<[IsARM, HasV6]>, Sched<[WriteALUsi]> {
1507 let Inst{19-16} = 0b1111;
1508 let Inst{15-12} = Rd;
1509 let Inst{11-10} = rot;
1513 class AI_ext_rrot_np<bits<8> opcod, string opc>
1514 : AExtI<opcod, (outs GPRnopc:$Rd), (ins GPRnopc:$Rm, rot_imm:$rot),
1515 IIC_iEXTr, opc, "\t$Rd, $Rm$rot", []>,
1516 Requires<[IsARM, HasV6]>, Sched<[WriteALUsi]> {
1518 let Inst{19-16} = 0b1111;
1519 let Inst{11-10} = rot;
1522 /// AI_exta_rrot - A binary operation with two forms: one whose operand is a
1523 /// register and one whose operand is a register rotated by 8/16/24.
1524 class AI_exta_rrot<bits<8> opcod, string opc, PatFrag opnode>
1525 : AExtI<opcod, (outs GPRnopc:$Rd), (ins GPR:$Rn, GPRnopc:$Rm, rot_imm:$rot),
1526 IIC_iEXTAr, opc, "\t$Rd, $Rn, $Rm$rot",
1527 [(set GPRnopc:$Rd, (opnode GPR:$Rn,
1528 (rotr GPRnopc:$Rm, rot_imm:$rot)))]>,
1529 Requires<[IsARM, HasV6]>, Sched<[WriteALUsr]> {
1534 let Inst{19-16} = Rn;
1535 let Inst{15-12} = Rd;
1536 let Inst{11-10} = rot;
1537 let Inst{9-4} = 0b000111;
1541 class AI_exta_rrot_np<bits<8> opcod, string opc>
1542 : AExtI<opcod, (outs GPRnopc:$Rd), (ins GPR:$Rn, GPRnopc:$Rm, rot_imm:$rot),
1543 IIC_iEXTAr, opc, "\t$Rd, $Rn, $Rm$rot", []>,
1544 Requires<[IsARM, HasV6]>, Sched<[WriteALUsr]> {
1547 let Inst{19-16} = Rn;
1548 let Inst{11-10} = rot;
1551 /// AI1_adde_sube_irs - Define instructions and patterns for adde and sube.
1552 let TwoOperandAliasConstraint = "$Rn = $Rd" in
1553 multiclass AI1_adde_sube_irs<bits<4> opcod, string opc, PatFrag opnode,
1554 bit Commutable = 0> {
1555 let hasPostISelHook = 1, Defs = [CPSR], Uses = [CPSR] in {
1556 def ri : AsI1<opcod, (outs GPR:$Rd), (ins GPR:$Rn, mod_imm:$imm),
1557 DPFrm, IIC_iALUi, opc, "\t$Rd, $Rn, $imm",
1558 [(set GPR:$Rd, CPSR, (opnode GPR:$Rn, mod_imm:$imm, CPSR))]>,
1560 Sched<[WriteALU, ReadALU]> {
1565 let Inst{15-12} = Rd;
1566 let Inst{19-16} = Rn;
1567 let Inst{11-0} = imm;
1569 def rr : AsI1<opcod, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm),
1570 DPFrm, IIC_iALUr, opc, "\t$Rd, $Rn, $Rm",
1571 [(set GPR:$Rd, CPSR, (opnode GPR:$Rn, GPR:$Rm, CPSR))]>,
1573 Sched<[WriteALU, ReadALU, ReadALU]> {
1577 let Inst{11-4} = 0b00000000;
1579 let isCommutable = Commutable;
1581 let Inst{15-12} = Rd;
1582 let Inst{19-16} = Rn;
1584 def rsi : AsI1<opcod, (outs GPR:$Rd),
1585 (ins GPR:$Rn, so_reg_imm:$shift),
1586 DPSoRegImmFrm, IIC_iALUsr, opc, "\t$Rd, $Rn, $shift",
1587 [(set GPR:$Rd, CPSR, (opnode GPR:$Rn, so_reg_imm:$shift, CPSR))]>,
1589 Sched<[WriteALUsi, ReadALU]> {
1594 let Inst{19-16} = Rn;
1595 let Inst{15-12} = Rd;
1596 let Inst{11-5} = shift{11-5};
1598 let Inst{3-0} = shift{3-0};
1600 def rsr : AsI1<opcod, (outs GPRnopc:$Rd),
1601 (ins GPRnopc:$Rn, so_reg_reg:$shift),
1602 DPSoRegRegFrm, IIC_iALUsr, opc, "\t$Rd, $Rn, $shift",
1603 [(set GPRnopc:$Rd, CPSR,
1604 (opnode GPRnopc:$Rn, so_reg_reg:$shift, CPSR))]>,
1606 Sched<[WriteALUsr, ReadALUsr]> {
1611 let Inst{19-16} = Rn;
1612 let Inst{15-12} = Rd;
1613 let Inst{11-8} = shift{11-8};
1615 let Inst{6-5} = shift{6-5};
1617 let Inst{3-0} = shift{3-0};
1622 /// AI1_rsc_irs - Define instructions and patterns for rsc
1623 let TwoOperandAliasConstraint = "$Rn = $Rd" in
1624 multiclass AI1_rsc_irs<bits<4> opcod, string opc, PatFrag opnode> {
1625 let hasPostISelHook = 1, Defs = [CPSR], Uses = [CPSR] in {
1626 def ri : AsI1<opcod, (outs GPR:$Rd), (ins GPR:$Rn, mod_imm:$imm),
1627 DPFrm, IIC_iALUi, opc, "\t$Rd, $Rn, $imm",
1628 [(set GPR:$Rd, CPSR, (opnode mod_imm:$imm, GPR:$Rn, CPSR))]>,
1630 Sched<[WriteALU, ReadALU]> {
1635 let Inst{15-12} = Rd;
1636 let Inst{19-16} = Rn;
1637 let Inst{11-0} = imm;
1639 def rr : AsI1<opcod, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm),
1640 DPFrm, IIC_iALUr, opc, "\t$Rd, $Rn, $Rm",
1641 [/* pattern left blank */]>,
1642 Sched<[WriteALU, ReadALU, ReadALU]> {
1646 let Inst{11-4} = 0b00000000;
1649 let Inst{15-12} = Rd;
1650 let Inst{19-16} = Rn;
1652 def rsi : AsI1<opcod, (outs GPR:$Rd), (ins GPR:$Rn, so_reg_imm:$shift),
1653 DPSoRegImmFrm, IIC_iALUsr, opc, "\t$Rd, $Rn, $shift",
1654 [(set GPR:$Rd, CPSR, (opnode so_reg_imm:$shift, GPR:$Rn, CPSR))]>,
1656 Sched<[WriteALUsi, ReadALU]> {
1661 let Inst{19-16} = Rn;
1662 let Inst{15-12} = Rd;
1663 let Inst{11-5} = shift{11-5};
1665 let Inst{3-0} = shift{3-0};
1667 def rsr : AsI1<opcod, (outs GPR:$Rd), (ins GPR:$Rn, so_reg_reg:$shift),
1668 DPSoRegRegFrm, IIC_iALUsr, opc, "\t$Rd, $Rn, $shift",
1669 [(set GPR:$Rd, CPSR, (opnode so_reg_reg:$shift, GPR:$Rn, CPSR))]>,
1671 Sched<[WriteALUsr, ReadALUsr]> {
1676 let Inst{19-16} = Rn;
1677 let Inst{15-12} = Rd;
1678 let Inst{11-8} = shift{11-8};
1680 let Inst{6-5} = shift{6-5};
1682 let Inst{3-0} = shift{3-0};
1687 let canFoldAsLoad = 1, isReMaterializable = 1 in {
1688 multiclass AI_ldr1<bit isByte, string opc, InstrItinClass iii,
1689 InstrItinClass iir, PatFrag opnode> {
1690 // Note: We use the complex addrmode_imm12 rather than just an input
1691 // GPR and a constrained immediate so that we can use this to match
1692 // frame index references and avoid matching constant pool references.
1693 def i12: AI2ldst<0b010, 1, isByte, (outs GPR:$Rt), (ins addrmode_imm12:$addr),
1694 AddrMode_i12, LdFrm, iii, opc, "\t$Rt, $addr",
1695 [(set GPR:$Rt, (opnode addrmode_imm12:$addr))]> {
1698 let Inst{23} = addr{12}; // U (add = ('U' == 1))
1699 let Inst{19-16} = addr{16-13}; // Rn
1700 let Inst{15-12} = Rt;
1701 let Inst{11-0} = addr{11-0}; // imm12
1703 def rs : AI2ldst<0b011, 1, isByte, (outs GPR:$Rt), (ins ldst_so_reg:$shift),
1704 AddrModeNone, LdFrm, iir, opc, "\t$Rt, $shift",
1705 [(set GPR:$Rt, (opnode ldst_so_reg:$shift))]> {
1708 let shift{4} = 0; // Inst{4} = 0
1709 let Inst{23} = shift{12}; // U (add = ('U' == 1))
1710 let Inst{19-16} = shift{16-13}; // Rn
1711 let Inst{15-12} = Rt;
1712 let Inst{11-0} = shift{11-0};
1717 let canFoldAsLoad = 1, isReMaterializable = 1 in {
1718 multiclass AI_ldr1nopc<bit isByte, string opc, InstrItinClass iii,
1719 InstrItinClass iir, PatFrag opnode> {
1720 // Note: We use the complex addrmode_imm12 rather than just an input
1721 // GPR and a constrained immediate so that we can use this to match
1722 // frame index references and avoid matching constant pool references.
1723 def i12: AI2ldst<0b010, 1, isByte, (outs GPRnopc:$Rt),
1724 (ins addrmode_imm12:$addr),
1725 AddrMode_i12, LdFrm, iii, opc, "\t$Rt, $addr",
1726 [(set GPRnopc:$Rt, (opnode addrmode_imm12:$addr))]> {
1729 let Inst{23} = addr{12}; // U (add = ('U' == 1))
1730 let Inst{19-16} = addr{16-13}; // Rn
1731 let Inst{15-12} = Rt;
1732 let Inst{11-0} = addr{11-0}; // imm12
1734 def rs : AI2ldst<0b011, 1, isByte, (outs GPRnopc:$Rt),
1735 (ins ldst_so_reg:$shift),
1736 AddrModeNone, LdFrm, iir, opc, "\t$Rt, $shift",
1737 [(set GPRnopc:$Rt, (opnode ldst_so_reg:$shift))]> {
1740 let shift{4} = 0; // Inst{4} = 0
1741 let Inst{23} = shift{12}; // U (add = ('U' == 1))
1742 let Inst{19-16} = shift{16-13}; // Rn
1743 let Inst{15-12} = Rt;
1744 let Inst{11-0} = shift{11-0};
1750 multiclass AI_str1<bit isByte, string opc, InstrItinClass iii,
1751 InstrItinClass iir, PatFrag opnode> {
1752 // Note: We use the complex addrmode_imm12 rather than just an input
1753 // GPR and a constrained immediate so that we can use this to match
1754 // frame index references and avoid matching constant pool references.
1755 def i12 : AI2ldst<0b010, 0, isByte, (outs),
1756 (ins GPR:$Rt, addrmode_imm12:$addr),
1757 AddrMode_i12, StFrm, iii, opc, "\t$Rt, $addr",
1758 [(opnode GPR:$Rt, addrmode_imm12:$addr)]> {
1761 let Inst{23} = addr{12}; // U (add = ('U' == 1))
1762 let Inst{19-16} = addr{16-13}; // Rn
1763 let Inst{15-12} = Rt;
1764 let Inst{11-0} = addr{11-0}; // imm12
1766 def rs : AI2ldst<0b011, 0, isByte, (outs), (ins GPR:$Rt, ldst_so_reg:$shift),
1767 AddrModeNone, StFrm, iir, opc, "\t$Rt, $shift",
1768 [(opnode GPR:$Rt, ldst_so_reg:$shift)]> {
1771 let shift{4} = 0; // Inst{4} = 0
1772 let Inst{23} = shift{12}; // U (add = ('U' == 1))
1773 let Inst{19-16} = shift{16-13}; // Rn
1774 let Inst{15-12} = Rt;
1775 let Inst{11-0} = shift{11-0};
1779 multiclass AI_str1nopc<bit isByte, string opc, InstrItinClass iii,
1780 InstrItinClass iir, PatFrag opnode> {
1781 // Note: We use the complex addrmode_imm12 rather than just an input
1782 // GPR and a constrained immediate so that we can use this to match
1783 // frame index references and avoid matching constant pool references.
1784 def i12 : AI2ldst<0b010, 0, isByte, (outs),
1785 (ins GPRnopc:$Rt, addrmode_imm12:$addr),
1786 AddrMode_i12, StFrm, iii, opc, "\t$Rt, $addr",
1787 [(opnode GPRnopc:$Rt, addrmode_imm12:$addr)]> {
1790 let Inst{23} = addr{12}; // U (add = ('U' == 1))
1791 let Inst{19-16} = addr{16-13}; // Rn
1792 let Inst{15-12} = Rt;
1793 let Inst{11-0} = addr{11-0}; // imm12
1795 def rs : AI2ldst<0b011, 0, isByte, (outs),
1796 (ins GPRnopc:$Rt, ldst_so_reg:$shift),
1797 AddrModeNone, StFrm, iir, opc, "\t$Rt, $shift",
1798 [(opnode GPRnopc:$Rt, ldst_so_reg:$shift)]> {
1801 let shift{4} = 0; // Inst{4} = 0
1802 let Inst{23} = shift{12}; // U (add = ('U' == 1))
1803 let Inst{19-16} = shift{16-13}; // Rn
1804 let Inst{15-12} = Rt;
1805 let Inst{11-0} = shift{11-0};
1810 //===----------------------------------------------------------------------===//
1812 //===----------------------------------------------------------------------===//
1814 //===----------------------------------------------------------------------===//
1815 // Miscellaneous Instructions.
1818 /// CONSTPOOL_ENTRY - This instruction represents a floating constant pool in
1819 /// the function. The first operand is the ID# for this instruction, the second
1820 /// is the index into the MachineConstantPool that this is, the third is the
1821 /// size in bytes of this constant pool entry.
1822 let hasSideEffects = 0, isNotDuplicable = 1 in
1823 def CONSTPOOL_ENTRY :
1824 PseudoInst<(outs), (ins cpinst_operand:$instid, cpinst_operand:$cpidx,
1825 i32imm:$size), NoItinerary, []>;
1827 // FIXME: Marking these as hasSideEffects is necessary to prevent machine DCE
1828 // from removing one half of the matched pairs. That breaks PEI, which assumes
1829 // these will always be in pairs, and asserts if it finds otherwise. Better way?
1830 let Defs = [SP], Uses = [SP], hasSideEffects = 1 in {
1831 def ADJCALLSTACKUP :
1832 PseudoInst<(outs), (ins i32imm:$amt1, i32imm:$amt2, pred:$p), NoItinerary,
1833 [(ARMcallseq_end timm:$amt1, timm:$amt2)]>;
1835 def ADJCALLSTACKDOWN :
1836 PseudoInst<(outs), (ins i32imm:$amt, pred:$p), NoItinerary,
1837 [(ARMcallseq_start timm:$amt)]>;
1840 def HINT : AI<(outs), (ins imm0_239:$imm), MiscFrm, NoItinerary,
1841 "hint", "\t$imm", [(int_arm_hint imm0_239:$imm)]>,
1842 Requires<[IsARM, HasV6]> {
1844 let Inst{27-8} = 0b00110010000011110000;
1845 let Inst{7-0} = imm;
1848 def : InstAlias<"nop$p", (HINT 0, pred:$p)>, Requires<[IsARM, HasV6K]>;
1849 def : InstAlias<"yield$p", (HINT 1, pred:$p)>, Requires<[IsARM, HasV6K]>;
1850 def : InstAlias<"wfe$p", (HINT 2, pred:$p)>, Requires<[IsARM, HasV6K]>;
1851 def : InstAlias<"wfi$p", (HINT 3, pred:$p)>, Requires<[IsARM, HasV6K]>;
1852 def : InstAlias<"sev$p", (HINT 4, pred:$p)>, Requires<[IsARM, HasV6K]>;
1853 def : InstAlias<"sevl$p", (HINT 5, pred:$p)>, Requires<[IsARM, HasV8]>;
1855 def SEL : AI<(outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm), DPFrm, NoItinerary, "sel",
1856 "\t$Rd, $Rn, $Rm", []>, Requires<[IsARM, HasV6]> {
1861 let Inst{15-12} = Rd;
1862 let Inst{19-16} = Rn;
1863 let Inst{27-20} = 0b01101000;
1864 let Inst{7-4} = 0b1011;
1865 let Inst{11-8} = 0b1111;
1866 let Unpredictable{11-8} = 0b1111;
1869 // The 16-bit operand $val can be used by a debugger to store more information
1870 // about the breakpoint.
1871 def BKPT : AInoP<(outs), (ins imm0_65535:$val), MiscFrm, NoItinerary,
1872 "bkpt", "\t$val", []>, Requires<[IsARM]> {
1874 let Inst{3-0} = val{3-0};
1875 let Inst{19-8} = val{15-4};
1876 let Inst{27-20} = 0b00010010;
1877 let Inst{31-28} = 0xe; // AL
1878 let Inst{7-4} = 0b0111;
1880 // default immediate for breakpoint mnemonic
1881 def : InstAlias<"bkpt", (BKPT 0)>, Requires<[IsARM]>;
1883 def HLT : AInoP<(outs), (ins imm0_65535:$val), MiscFrm, NoItinerary,
1884 "hlt", "\t$val", []>, Requires<[IsARM, HasV8]> {
1886 let Inst{3-0} = val{3-0};
1887 let Inst{19-8} = val{15-4};
1888 let Inst{27-20} = 0b00010000;
1889 let Inst{31-28} = 0xe; // AL
1890 let Inst{7-4} = 0b0111;
1893 // Change Processor State
1894 // FIXME: We should use InstAlias to handle the optional operands.
1895 class CPS<dag iops, string asm_ops>
1896 : AXI<(outs), iops, MiscFrm, NoItinerary, !strconcat("cps", asm_ops),
1897 []>, Requires<[IsARM]> {
1903 let Inst{31-28} = 0b1111;
1904 let Inst{27-20} = 0b00010000;
1905 let Inst{19-18} = imod;
1906 let Inst{17} = M; // Enabled if mode is set;
1907 let Inst{16-9} = 0b00000000;
1908 let Inst{8-6} = iflags;
1910 let Inst{4-0} = mode;
1913 let DecoderMethod = "DecodeCPSInstruction" in {
1915 def CPS3p : CPS<(ins imod_op:$imod, iflags_op:$iflags, imm0_31:$mode),
1916 "$imod\t$iflags, $mode">;
1917 let mode = 0, M = 0 in
1918 def CPS2p : CPS<(ins imod_op:$imod, iflags_op:$iflags), "$imod\t$iflags">;
1920 let imod = 0, iflags = 0, M = 1 in
1921 def CPS1p : CPS<(ins imm0_31:$mode), "\t$mode">;
1924 // Preload signals the memory system of possible future data/instruction access.
1925 multiclass APreLoad<bits<1> read, bits<1> data, string opc> {
1927 def i12 : AXIM<(outs), (ins addrmode_imm12:$addr), AddrMode_i12, MiscFrm,
1928 IIC_Preload, !strconcat(opc, "\t$addr"),
1929 [(ARMPreload addrmode_imm12:$addr, (i32 read), (i32 data))]>,
1930 Sched<[WritePreLd]> {
1933 let Inst{31-26} = 0b111101;
1934 let Inst{25} = 0; // 0 for immediate form
1935 let Inst{24} = data;
1936 let Inst{23} = addr{12}; // U (add = ('U' == 1))
1937 let Inst{22} = read;
1938 let Inst{21-20} = 0b01;
1939 let Inst{19-16} = addr{16-13}; // Rn
1940 let Inst{15-12} = 0b1111;
1941 let Inst{11-0} = addr{11-0}; // imm12
1944 def rs : AXI<(outs), (ins ldst_so_reg:$shift), MiscFrm, IIC_Preload,
1945 !strconcat(opc, "\t$shift"),
1946 [(ARMPreload ldst_so_reg:$shift, (i32 read), (i32 data))]>,
1947 Sched<[WritePreLd]> {
1949 let Inst{31-26} = 0b111101;
1950 let Inst{25} = 1; // 1 for register form
1951 let Inst{24} = data;
1952 let Inst{23} = shift{12}; // U (add = ('U' == 1))
1953 let Inst{22} = read;
1954 let Inst{21-20} = 0b01;
1955 let Inst{19-16} = shift{16-13}; // Rn
1956 let Inst{15-12} = 0b1111;
1957 let Inst{11-0} = shift{11-0};
1962 defm PLD : APreLoad<1, 1, "pld">, Requires<[IsARM]>;
1963 defm PLDW : APreLoad<0, 1, "pldw">, Requires<[IsARM,HasV7,HasMP]>;
1964 defm PLI : APreLoad<1, 0, "pli">, Requires<[IsARM,HasV7]>;
1966 def SETEND : AXI<(outs), (ins setend_op:$end), MiscFrm, NoItinerary,
1967 "setend\t$end", []>, Requires<[IsARM]>, Deprecated<HasV8Ops> {
1969 let Inst{31-10} = 0b1111000100000001000000;
1974 def DBG : AI<(outs), (ins imm0_15:$opt), MiscFrm, NoItinerary, "dbg", "\t$opt",
1975 [(int_arm_dbg imm0_15:$opt)]>, Requires<[IsARM, HasV7]> {
1977 let Inst{27-4} = 0b001100100000111100001111;
1978 let Inst{3-0} = opt;
1981 // A8.8.247 UDF - Undefined (Encoding A1)
1982 def UDF : AInoP<(outs), (ins imm0_65535:$imm16), MiscFrm, NoItinerary,
1983 "udf", "\t$imm16", [(int_arm_undefined imm0_65535:$imm16)]> {
1985 let Inst{31-28} = 0b1110; // AL
1986 let Inst{27-25} = 0b011;
1987 let Inst{24-20} = 0b11111;
1988 let Inst{19-8} = imm16{15-4};
1989 let Inst{7-4} = 0b1111;
1990 let Inst{3-0} = imm16{3-0};
1994 * A5.4 Permanently UNDEFINED instructions.
1996 * For most targets use UDF #65006, for which the OS will generate SIGTRAP.
1997 * Other UDF encodings generate SIGILL.
1999 * NaCl's OS instead chooses an ARM UDF encoding that's also a UDF in Thumb.
2001 * 1110 0111 1111 iiii iiii iiii 1111 iiii
2003 * 1101 1110 iiii iiii
2004 * It uses the following encoding:
2005 * 1110 0111 1111 1110 1101 1110 1111 0000
2006 * - In ARM: UDF #60896;
2007 * - In Thumb: UDF #254 followed by a branch-to-self.
2009 let isBarrier = 1, isTerminator = 1 in
2010 def TRAPNaCl : AXI<(outs), (ins), MiscFrm, NoItinerary,
2012 Requires<[IsARM,UseNaClTrap]> {
2013 let Inst = 0xe7fedef0;
2015 let isBarrier = 1, isTerminator = 1 in
2016 def TRAP : AXI<(outs), (ins), MiscFrm, NoItinerary,
2018 Requires<[IsARM,DontUseNaClTrap]> {
2019 let Inst = 0xe7ffdefe;
2022 // Address computation and loads and stores in PIC mode.
2023 let isNotDuplicable = 1 in {
2024 def PICADD : ARMPseudoInst<(outs GPR:$dst), (ins GPR:$a, pclabel:$cp, pred:$p),
2026 [(set GPR:$dst, (ARMpic_add GPR:$a, imm:$cp))]>,
2027 Sched<[WriteALU, ReadALU]>;
2029 let AddedComplexity = 10 in {
2030 def PICLDR : ARMPseudoInst<(outs GPR:$dst), (ins addrmodepc:$addr, pred:$p),
2032 [(set GPR:$dst, (load addrmodepc:$addr))]>;
2034 def PICLDRH : ARMPseudoInst<(outs GPR:$Rt), (ins addrmodepc:$addr, pred:$p),
2036 [(set GPR:$Rt, (zextloadi16 addrmodepc:$addr))]>;
2038 def PICLDRB : ARMPseudoInst<(outs GPR:$Rt), (ins addrmodepc:$addr, pred:$p),
2040 [(set GPR:$Rt, (zextloadi8 addrmodepc:$addr))]>;
2042 def PICLDRSH : ARMPseudoInst<(outs GPR:$Rt), (ins addrmodepc:$addr, pred:$p),
2044 [(set GPR:$Rt, (sextloadi16 addrmodepc:$addr))]>;
2046 def PICLDRSB : ARMPseudoInst<(outs GPR:$Rt), (ins addrmodepc:$addr, pred:$p),
2048 [(set GPR:$Rt, (sextloadi8 addrmodepc:$addr))]>;
2050 let AddedComplexity = 10 in {
2051 def PICSTR : ARMPseudoInst<(outs), (ins GPR:$src, addrmodepc:$addr, pred:$p),
2052 4, IIC_iStore_r, [(store GPR:$src, addrmodepc:$addr)]>;
2054 def PICSTRH : ARMPseudoInst<(outs), (ins GPR:$src, addrmodepc:$addr, pred:$p),
2055 4, IIC_iStore_bh_r, [(truncstorei16 GPR:$src,
2056 addrmodepc:$addr)]>;
2058 def PICSTRB : ARMPseudoInst<(outs), (ins GPR:$src, addrmodepc:$addr, pred:$p),
2059 4, IIC_iStore_bh_r, [(truncstorei8 GPR:$src, addrmodepc:$addr)]>;
2061 } // isNotDuplicable = 1
2064 // LEApcrel - Load a pc-relative address into a register without offending the
2066 let hasSideEffects = 0, isReMaterializable = 1 in
2067 // The 'adr' mnemonic encodes differently if the label is before or after
2068 // the instruction. The {24-21} opcode bits are set by the fixup, as we don't
2069 // know until then which form of the instruction will be used.
2070 def ADR : AI1<{0,?,?,0}, (outs GPR:$Rd), (ins adrlabel:$label),
2071 MiscFrm, IIC_iALUi, "adr", "\t$Rd, $label", []>,
2072 Sched<[WriteALU, ReadALU]> {
2075 let Inst{27-25} = 0b001;
2077 let Inst{23-22} = label{13-12};
2080 let Inst{19-16} = 0b1111;
2081 let Inst{15-12} = Rd;
2082 let Inst{11-0} = label{11-0};
2085 let hasSideEffects = 1 in {
2086 def LEApcrel : ARMPseudoInst<(outs GPR:$Rd), (ins i32imm:$label, pred:$p),
2087 4, IIC_iALUi, []>, Sched<[WriteALU, ReadALU]>;
2089 def LEApcrelJT : ARMPseudoInst<(outs GPR:$Rd),
2090 (ins i32imm:$label, nohash_imm:$id, pred:$p),
2091 4, IIC_iALUi, []>, Sched<[WriteALU, ReadALU]>;
2094 //===----------------------------------------------------------------------===//
2095 // Control Flow Instructions.
2098 let isReturn = 1, isTerminator = 1, isBarrier = 1 in {
2100 def BX_RET : AI<(outs), (ins), BrMiscFrm, IIC_Br,
2101 "bx", "\tlr", [(ARMretflag)]>,
2102 Requires<[IsARM, HasV4T]>, Sched<[WriteBr]> {
2103 let Inst{27-0} = 0b0001001011111111111100011110;
2107 def MOVPCLR : AI<(outs), (ins), BrMiscFrm, IIC_Br,
2108 "mov", "\tpc, lr", [(ARMretflag)]>,
2109 Requires<[IsARM, NoV4T]>, Sched<[WriteBr]> {
2110 let Inst{27-0} = 0b0001101000001111000000001110;
2113 // Exception return: N.b. doesn't set CPSR as far as we're concerned (it sets
2114 // the user-space one).
2115 def SUBS_PC_LR : ARMPseudoInst<(outs), (ins i32imm:$offset, pred:$p),
2117 [(ARMintretflag imm:$offset)]>;
2120 // Indirect branches
2121 let isBranch = 1, isTerminator = 1, isBarrier = 1, isIndirectBranch = 1 in {
2123 def BX : AXI<(outs), (ins GPR:$dst), BrMiscFrm, IIC_Br, "bx\t$dst",
2124 [(brind GPR:$dst)]>,
2125 Requires<[IsARM, HasV4T]>, Sched<[WriteBr]> {
2127 let Inst{31-4} = 0b1110000100101111111111110001;
2128 let Inst{3-0} = dst;
2131 def BX_pred : AI<(outs), (ins GPR:$dst), BrMiscFrm, IIC_Br,
2132 "bx", "\t$dst", [/* pattern left blank */]>,
2133 Requires<[IsARM, HasV4T]>, Sched<[WriteBr]> {
2135 let Inst{27-4} = 0b000100101111111111110001;
2136 let Inst{3-0} = dst;
2140 // SP is marked as a use to prevent stack-pointer assignments that appear
2141 // immediately before calls from potentially appearing dead.
2143 // FIXME: Do we really need a non-predicated version? If so, it should
2144 // at least be a pseudo instruction expanding to the predicated version
2145 // at MC lowering time.
2146 Defs = [LR], Uses = [SP] in {
2147 def BL : ABXI<0b1011, (outs), (ins bl_target:$func),
2148 IIC_Br, "bl\t$func",
2149 [(ARMcall tglobaladdr:$func)]>,
2150 Requires<[IsARM]>, Sched<[WriteBrL]> {
2151 let Inst{31-28} = 0b1110;
2153 let Inst{23-0} = func;
2154 let DecoderMethod = "DecodeBranchImmInstruction";
2157 def BL_pred : ABI<0b1011, (outs), (ins bl_target:$func),
2158 IIC_Br, "bl", "\t$func",
2159 [(ARMcall_pred tglobaladdr:$func)]>,
2160 Requires<[IsARM]>, Sched<[WriteBrL]> {
2162 let Inst{23-0} = func;
2163 let DecoderMethod = "DecodeBranchImmInstruction";
2167 def BLX : AXI<(outs), (ins GPR:$func), BrMiscFrm,
2168 IIC_Br, "blx\t$func",
2169 [(ARMcall GPR:$func)]>,
2170 Requires<[IsARM, HasV5T]>, Sched<[WriteBrL]> {
2172 let Inst{31-4} = 0b1110000100101111111111110011;
2173 let Inst{3-0} = func;
2176 def BLX_pred : AI<(outs), (ins GPR:$func), BrMiscFrm,
2177 IIC_Br, "blx", "\t$func",
2178 [(ARMcall_pred GPR:$func)]>,
2179 Requires<[IsARM, HasV5T]>, Sched<[WriteBrL]> {
2181 let Inst{27-4} = 0b000100101111111111110011;
2182 let Inst{3-0} = func;
2186 // Note: Restrict $func to the tGPR regclass to prevent it being in LR.
2187 def BX_CALL : ARMPseudoInst<(outs), (ins tGPR:$func),
2188 8, IIC_Br, [(ARMcall_nolink tGPR:$func)]>,
2189 Requires<[IsARM, HasV4T]>, Sched<[WriteBr]>;
2192 def BMOVPCRX_CALL : ARMPseudoInst<(outs), (ins tGPR:$func),
2193 8, IIC_Br, [(ARMcall_nolink tGPR:$func)]>,
2194 Requires<[IsARM, NoV4T]>, Sched<[WriteBr]>;
2196 // mov lr, pc; b if callee is marked noreturn to avoid confusing the
2197 // return stack predictor.
2198 def BMOVPCB_CALL : ARMPseudoInst<(outs), (ins bl_target:$func),
2199 8, IIC_Br, [(ARMcall_nolink tglobaladdr:$func)]>,
2200 Requires<[IsARM]>, Sched<[WriteBr]>;
2203 let isBranch = 1, isTerminator = 1 in {
2204 // FIXME: should be able to write a pattern for ARMBrcond, but can't use
2205 // a two-value operand where a dag node expects two operands. :(
2206 def Bcc : ABI<0b1010, (outs), (ins br_target:$target),
2207 IIC_Br, "b", "\t$target",
2208 [/*(ARMbrcond bb:$target, imm:$cc, CCR:$ccr)*/]>,
2211 let Inst{23-0} = target;
2212 let DecoderMethod = "DecodeBranchImmInstruction";
2215 let isBarrier = 1 in {
2216 // B is "predicable" since it's just a Bcc with an 'always' condition.
2217 let isPredicable = 1 in
2218 // FIXME: We shouldn't need this pseudo at all. Just using Bcc directly
2219 // should be sufficient.
2220 // FIXME: Is B really a Barrier? That doesn't seem right.
2221 def B : ARMPseudoExpand<(outs), (ins br_target:$target), 4, IIC_Br,
2222 [(br bb:$target)], (Bcc br_target:$target, (ops 14, zero_reg))>,
2225 let isNotDuplicable = 1, isIndirectBranch = 1 in {
2226 def BR_JTr : ARMPseudoInst<(outs),
2227 (ins GPR:$target, i32imm:$jt, i32imm:$id),
2229 [(ARMbrjt GPR:$target, tjumptable:$jt, imm:$id)]>,
2231 // FIXME: This shouldn't use the generic "addrmode2," but rather be split
2232 // into i12 and rs suffixed versions.
2233 def BR_JTm : ARMPseudoInst<(outs),
2234 (ins addrmode2:$target, i32imm:$jt, i32imm:$id),
2236 [(ARMbrjt (i32 (load addrmode2:$target)), tjumptable:$jt,
2237 imm:$id)]>, Sched<[WriteBrTbl]>;
2238 def BR_JTadd : ARMPseudoInst<(outs),
2239 (ins GPR:$target, GPR:$idx, i32imm:$jt, i32imm:$id),
2241 [(ARMbrjt (add GPR:$target, GPR:$idx), tjumptable:$jt,
2242 imm:$id)]>, Sched<[WriteBrTbl]>;
2243 } // isNotDuplicable = 1, isIndirectBranch = 1
2249 def BLXi : AXI<(outs), (ins blx_target:$target), BrMiscFrm, NoItinerary,
2250 "blx\t$target", []>,
2251 Requires<[IsARM, HasV5T]>, Sched<[WriteBrL]> {
2252 let Inst{31-25} = 0b1111101;
2254 let Inst{23-0} = target{24-1};
2255 let Inst{24} = target{0};
2258 // Branch and Exchange Jazelle
2259 def BXJ : ABI<0b0001, (outs), (ins GPR:$func), NoItinerary, "bxj", "\t$func",
2260 [/* pattern left blank */]>, Sched<[WriteBr]> {
2262 let Inst{23-20} = 0b0010;
2263 let Inst{19-8} = 0xfff;
2264 let Inst{7-4} = 0b0010;
2265 let Inst{3-0} = func;
2270 let isCall = 1, isTerminator = 1, isReturn = 1, isBarrier = 1, Uses = [SP] in {
2271 def TCRETURNdi : PseudoInst<(outs), (ins i32imm:$dst), IIC_Br, []>,
2274 def TCRETURNri : PseudoInst<(outs), (ins tcGPR:$dst), IIC_Br, []>,
2277 def TAILJMPd : ARMPseudoExpand<(outs), (ins br_target:$dst),
2279 (Bcc br_target:$dst, (ops 14, zero_reg))>,
2280 Requires<[IsARM]>, Sched<[WriteBr]>;
2282 def TAILJMPr : ARMPseudoExpand<(outs), (ins tcGPR:$dst),
2284 (BX GPR:$dst)>, Sched<[WriteBr]>,
2288 // Secure Monitor Call is a system instruction.
2289 def SMC : ABI<0b0001, (outs), (ins imm0_15:$opt), NoItinerary, "smc", "\t$opt",
2290 []>, Requires<[IsARM, HasTrustZone]> {
2292 let Inst{23-4} = 0b01100000000000000111;
2293 let Inst{3-0} = opt;
2296 // Supervisor Call (Software Interrupt)
2297 let isCall = 1, Uses = [SP] in {
2298 def SVC : ABI<0b1111, (outs), (ins imm24b:$svc), IIC_Br, "svc", "\t$svc", []>,
2301 let Inst{23-0} = svc;
2305 // Store Return State
2306 class SRSI<bit wb, string asm>
2307 : XI<(outs), (ins imm0_31:$mode), AddrModeNone, 4, IndexModeNone, BrFrm,
2308 NoItinerary, asm, "", []> {
2310 let Inst{31-28} = 0b1111;
2311 let Inst{27-25} = 0b100;
2315 let Inst{19-16} = 0b1101; // SP
2316 let Inst{15-5} = 0b00000101000;
2317 let Inst{4-0} = mode;
2320 def SRSDA : SRSI<0, "srsda\tsp, $mode"> {
2321 let Inst{24-23} = 0;
2323 def SRSDA_UPD : SRSI<1, "srsda\tsp!, $mode"> {
2324 let Inst{24-23} = 0;
2326 def SRSDB : SRSI<0, "srsdb\tsp, $mode"> {
2327 let Inst{24-23} = 0b10;
2329 def SRSDB_UPD : SRSI<1, "srsdb\tsp!, $mode"> {
2330 let Inst{24-23} = 0b10;
2332 def SRSIA : SRSI<0, "srsia\tsp, $mode"> {
2333 let Inst{24-23} = 0b01;
2335 def SRSIA_UPD : SRSI<1, "srsia\tsp!, $mode"> {
2336 let Inst{24-23} = 0b01;
2338 def SRSIB : SRSI<0, "srsib\tsp, $mode"> {
2339 let Inst{24-23} = 0b11;
2341 def SRSIB_UPD : SRSI<1, "srsib\tsp!, $mode"> {
2342 let Inst{24-23} = 0b11;
2345 def : ARMInstAlias<"srsda $mode", (SRSDA imm0_31:$mode)>;
2346 def : ARMInstAlias<"srsda $mode!", (SRSDA_UPD imm0_31:$mode)>;
2348 def : ARMInstAlias<"srsdb $mode", (SRSDB imm0_31:$mode)>;
2349 def : ARMInstAlias<"srsdb $mode!", (SRSDB_UPD imm0_31:$mode)>;
2351 def : ARMInstAlias<"srsia $mode", (SRSIA imm0_31:$mode)>;
2352 def : ARMInstAlias<"srsia $mode!", (SRSIA_UPD imm0_31:$mode)>;
2354 def : ARMInstAlias<"srsib $mode", (SRSIB imm0_31:$mode)>;
2355 def : ARMInstAlias<"srsib $mode!", (SRSIB_UPD imm0_31:$mode)>;
2357 // Return From Exception
2358 class RFEI<bit wb, string asm>
2359 : XI<(outs), (ins GPR:$Rn), AddrModeNone, 4, IndexModeNone, BrFrm,
2360 NoItinerary, asm, "", []> {
2362 let Inst{31-28} = 0b1111;
2363 let Inst{27-25} = 0b100;
2367 let Inst{19-16} = Rn;
2368 let Inst{15-0} = 0xa00;
2371 def RFEDA : RFEI<0, "rfeda\t$Rn"> {
2372 let Inst{24-23} = 0;
2374 def RFEDA_UPD : RFEI<1, "rfeda\t$Rn!"> {
2375 let Inst{24-23} = 0;
2377 def RFEDB : RFEI<0, "rfedb\t$Rn"> {
2378 let Inst{24-23} = 0b10;
2380 def RFEDB_UPD : RFEI<1, "rfedb\t$Rn!"> {
2381 let Inst{24-23} = 0b10;
2383 def RFEIA : RFEI<0, "rfeia\t$Rn"> {
2384 let Inst{24-23} = 0b01;
2386 def RFEIA_UPD : RFEI<1, "rfeia\t$Rn!"> {
2387 let Inst{24-23} = 0b01;
2389 def RFEIB : RFEI<0, "rfeib\t$Rn"> {
2390 let Inst{24-23} = 0b11;
2392 def RFEIB_UPD : RFEI<1, "rfeib\t$Rn!"> {
2393 let Inst{24-23} = 0b11;
2396 // Hypervisor Call is a system instruction
2398 def HVC : AInoP< (outs), (ins imm0_65535:$imm), BrFrm, NoItinerary,
2399 "hvc", "\t$imm", []>,
2400 Requires<[IsARM, HasVirtualization]> {
2403 // Even though HVC isn't predicable, it's encoding includes a condition field.
2404 // The instruction is undefined if the condition field is 0xf otherwise it is
2405 // unpredictable if it isn't condition AL (0xe).
2406 let Inst{31-28} = 0b1110;
2407 let Unpredictable{31-28} = 0b1111;
2408 let Inst{27-24} = 0b0001;
2409 let Inst{23-20} = 0b0100;
2410 let Inst{19-8} = imm{15-4};
2411 let Inst{7-4} = 0b0111;
2412 let Inst{3-0} = imm{3-0};
2416 // Return from exception in Hypervisor mode.
2417 let isReturn = 1, isBarrier = 1, isTerminator = 1, Defs = [PC] in
2418 def ERET : ABI<0b0001, (outs), (ins), NoItinerary, "eret", "", []>,
2419 Requires<[IsARM, HasVirtualization]> {
2420 let Inst{23-0} = 0b011000000000000001101110;
2423 //===----------------------------------------------------------------------===//
2424 // Load / Store Instructions.
2430 defm LDR : AI_ldr1<0, "ldr", IIC_iLoad_r, IIC_iLoad_si,
2431 UnOpFrag<(load node:$Src)>>;
2432 defm LDRB : AI_ldr1nopc<1, "ldrb", IIC_iLoad_bh_r, IIC_iLoad_bh_si,
2433 UnOpFrag<(zextloadi8 node:$Src)>>;
2434 defm STR : AI_str1<0, "str", IIC_iStore_r, IIC_iStore_si,
2435 BinOpFrag<(store node:$LHS, node:$RHS)>>;
2436 defm STRB : AI_str1nopc<1, "strb", IIC_iStore_bh_r, IIC_iStore_bh_si,
2437 BinOpFrag<(truncstorei8 node:$LHS, node:$RHS)>>;
2439 // Special LDR for loads from non-pc-relative constpools.
2440 let canFoldAsLoad = 1, mayLoad = 1, hasSideEffects = 0,
2441 isReMaterializable = 1, isCodeGenOnly = 1 in
2442 def LDRcp : AI2ldst<0b010, 1, 0, (outs GPR:$Rt), (ins addrmode_imm12:$addr),
2443 AddrMode_i12, LdFrm, IIC_iLoad_r, "ldr", "\t$Rt, $addr",
2447 let Inst{23} = addr{12}; // U (add = ('U' == 1))
2448 let Inst{19-16} = 0b1111;
2449 let Inst{15-12} = Rt;
2450 let Inst{11-0} = addr{11-0}; // imm12
2453 // Loads with zero extension
2454 def LDRH : AI3ld<0b1011, 1, (outs GPR:$Rt), (ins addrmode3:$addr), LdMiscFrm,
2455 IIC_iLoad_bh_r, "ldrh", "\t$Rt, $addr",
2456 [(set GPR:$Rt, (zextloadi16 addrmode3:$addr))]>;
2458 // Loads with sign extension
2459 def LDRSH : AI3ld<0b1111, 1, (outs GPR:$Rt), (ins addrmode3:$addr), LdMiscFrm,
2460 IIC_iLoad_bh_r, "ldrsh", "\t$Rt, $addr",
2461 [(set GPR:$Rt, (sextloadi16 addrmode3:$addr))]>;
2463 def LDRSB : AI3ld<0b1101, 1, (outs GPR:$Rt), (ins addrmode3:$addr), LdMiscFrm,
2464 IIC_iLoad_bh_r, "ldrsb", "\t$Rt, $addr",
2465 [(set GPR:$Rt, (sextloadi8 addrmode3:$addr))]>;
2467 let mayLoad = 1, hasSideEffects = 0, hasExtraDefRegAllocReq = 1 in {
2469 def LDRD : AI3ld<0b1101, 0, (outs GPR:$Rt, GPR:$Rt2), (ins addrmode3:$addr),
2470 LdMiscFrm, IIC_iLoad_d_r, "ldrd", "\t$Rt, $Rt2, $addr", []>,
2471 Requires<[IsARM, HasV5TE]>;
2474 def LDA : AIldracq<0b00, (outs GPR:$Rt), (ins addr_offset_none:$addr),
2475 NoItinerary, "lda", "\t$Rt, $addr", []>;
2476 def LDAB : AIldracq<0b10, (outs GPR:$Rt), (ins addr_offset_none:$addr),
2477 NoItinerary, "ldab", "\t$Rt, $addr", []>;
2478 def LDAH : AIldracq<0b11, (outs GPR:$Rt), (ins addr_offset_none:$addr),
2479 NoItinerary, "ldah", "\t$Rt, $addr", []>;
2482 multiclass AI2_ldridx<bit isByte, string opc,
2483 InstrItinClass iii, InstrItinClass iir> {
2484 def _PRE_IMM : AI2ldstidx<1, isByte, 1, (outs GPR:$Rt, GPR:$Rn_wb),
2485 (ins addrmode_imm12_pre:$addr), IndexModePre, LdFrm, iii,
2486 opc, "\t$Rt, $addr!", "$addr.base = $Rn_wb", []> {
2489 let Inst{23} = addr{12};
2490 let Inst{19-16} = addr{16-13};
2491 let Inst{11-0} = addr{11-0};
2492 let DecoderMethod = "DecodeLDRPreImm";
2495 def _PRE_REG : AI2ldstidx<1, isByte, 1, (outs GPR:$Rt, GPR:$Rn_wb),
2496 (ins ldst_so_reg:$addr), IndexModePre, LdFrm, iir,
2497 opc, "\t$Rt, $addr!", "$addr.base = $Rn_wb", []> {
2500 let Inst{23} = addr{12};
2501 let Inst{19-16} = addr{16-13};
2502 let Inst{11-0} = addr{11-0};
2504 let DecoderMethod = "DecodeLDRPreReg";
2507 def _POST_REG : AI2ldstidx<1, isByte, 0, (outs GPR:$Rt, GPR:$Rn_wb),
2508 (ins addr_offset_none:$addr, am2offset_reg:$offset),
2509 IndexModePost, LdFrm, iir,
2510 opc, "\t$Rt, $addr, $offset",
2511 "$addr.base = $Rn_wb", []> {
2517 let Inst{23} = offset{12};
2518 let Inst{19-16} = addr;
2519 let Inst{11-0} = offset{11-0};
2522 let DecoderMethod = "DecodeAddrMode2IdxInstruction";
2525 def _POST_IMM : AI2ldstidx<1, isByte, 0, (outs GPR:$Rt, GPR:$Rn_wb),
2526 (ins addr_offset_none:$addr, am2offset_imm:$offset),
2527 IndexModePost, LdFrm, iii,
2528 opc, "\t$Rt, $addr, $offset",
2529 "$addr.base = $Rn_wb", []> {
2535 let Inst{23} = offset{12};
2536 let Inst{19-16} = addr;
2537 let Inst{11-0} = offset{11-0};
2539 let DecoderMethod = "DecodeAddrMode2IdxInstruction";
2544 let mayLoad = 1, hasSideEffects = 0 in {
2545 // FIXME: for LDR_PRE_REG etc. the itineray should be either IIC_iLoad_ru or
2546 // IIC_iLoad_siu depending on whether it the offset register is shifted.
2547 defm LDR : AI2_ldridx<0, "ldr", IIC_iLoad_iu, IIC_iLoad_ru>;
2548 defm LDRB : AI2_ldridx<1, "ldrb", IIC_iLoad_bh_iu, IIC_iLoad_bh_ru>;
2551 multiclass AI3_ldridx<bits<4> op, string opc, InstrItinClass itin> {
2552 def _PRE : AI3ldstidx<op, 1, 1, (outs GPR:$Rt, GPR:$Rn_wb),
2553 (ins addrmode3_pre:$addr), IndexModePre,
2555 opc, "\t$Rt, $addr!", "$addr.base = $Rn_wb", []> {
2557 let Inst{23} = addr{8}; // U bit
2558 let Inst{22} = addr{13}; // 1 == imm8, 0 == Rm
2559 let Inst{19-16} = addr{12-9}; // Rn
2560 let Inst{11-8} = addr{7-4}; // imm7_4/zero
2561 let Inst{3-0} = addr{3-0}; // imm3_0/Rm
2562 let DecoderMethod = "DecodeAddrMode3Instruction";
2564 def _POST : AI3ldstidx<op, 1, 0, (outs GPR:$Rt, GPR:$Rn_wb),
2565 (ins addr_offset_none:$addr, am3offset:$offset),
2566 IndexModePost, LdMiscFrm, itin,
2567 opc, "\t$Rt, $addr, $offset", "$addr.base = $Rn_wb",
2571 let Inst{23} = offset{8}; // U bit
2572 let Inst{22} = offset{9}; // 1 == imm8, 0 == Rm
2573 let Inst{19-16} = addr;
2574 let Inst{11-8} = offset{7-4}; // imm7_4/zero
2575 let Inst{3-0} = offset{3-0}; // imm3_0/Rm
2576 let DecoderMethod = "DecodeAddrMode3Instruction";
2580 let mayLoad = 1, hasSideEffects = 0 in {
2581 defm LDRH : AI3_ldridx<0b1011, "ldrh", IIC_iLoad_bh_ru>;
2582 defm LDRSH : AI3_ldridx<0b1111, "ldrsh", IIC_iLoad_bh_ru>;
2583 defm LDRSB : AI3_ldridx<0b1101, "ldrsb", IIC_iLoad_bh_ru>;
2584 let hasExtraDefRegAllocReq = 1 in {
2585 def LDRD_PRE : AI3ldstidx<0b1101, 0, 1, (outs GPR:$Rt, GPR:$Rt2, GPR:$Rn_wb),
2586 (ins addrmode3_pre:$addr), IndexModePre,
2587 LdMiscFrm, IIC_iLoad_d_ru,
2588 "ldrd", "\t$Rt, $Rt2, $addr!",
2589 "$addr.base = $Rn_wb", []> {
2591 let Inst{23} = addr{8}; // U bit
2592 let Inst{22} = addr{13}; // 1 == imm8, 0 == Rm
2593 let Inst{19-16} = addr{12-9}; // Rn
2594 let Inst{11-8} = addr{7-4}; // imm7_4/zero
2595 let Inst{3-0} = addr{3-0}; // imm3_0/Rm
2596 let DecoderMethod = "DecodeAddrMode3Instruction";
2598 def LDRD_POST: AI3ldstidx<0b1101, 0, 0, (outs GPR:$Rt, GPR:$Rt2, GPR:$Rn_wb),
2599 (ins addr_offset_none:$addr, am3offset:$offset),
2600 IndexModePost, LdMiscFrm, IIC_iLoad_d_ru,
2601 "ldrd", "\t$Rt, $Rt2, $addr, $offset",
2602 "$addr.base = $Rn_wb", []> {
2605 let Inst{23} = offset{8}; // U bit
2606 let Inst{22} = offset{9}; // 1 == imm8, 0 == Rm
2607 let Inst{19-16} = addr;
2608 let Inst{11-8} = offset{7-4}; // imm7_4/zero
2609 let Inst{3-0} = offset{3-0}; // imm3_0/Rm
2610 let DecoderMethod = "DecodeAddrMode3Instruction";
2612 } // hasExtraDefRegAllocReq = 1
2613 } // mayLoad = 1, hasSideEffects = 0
2615 // LDRT, LDRBT, LDRSBT, LDRHT, LDRSHT.
2616 let mayLoad = 1, hasSideEffects = 0 in {
2617 def LDRT_POST_REG : AI2ldstidx<1, 0, 0, (outs GPR:$Rt, GPR:$Rn_wb),
2618 (ins addr_offset_none:$addr, am2offset_reg:$offset),
2619 IndexModePost, LdFrm, IIC_iLoad_ru,
2620 "ldrt", "\t$Rt, $addr, $offset",
2621 "$addr.base = $Rn_wb", []> {
2627 let Inst{23} = offset{12};
2628 let Inst{21} = 1; // overwrite
2629 let Inst{19-16} = addr;
2630 let Inst{11-5} = offset{11-5};
2632 let Inst{3-0} = offset{3-0};
2633 let DecoderMethod = "DecodeAddrMode2IdxInstruction";
2637 : AI2ldstidx<1, 0, 0, (outs GPR:$Rt, GPR:$Rn_wb),
2638 (ins addr_offset_none:$addr, am2offset_imm:$offset),
2639 IndexModePost, LdFrm, IIC_iLoad_ru,
2640 "ldrt", "\t$Rt, $addr, $offset", "$addr.base = $Rn_wb", []> {
2646 let Inst{23} = offset{12};
2647 let Inst{21} = 1; // overwrite
2648 let Inst{19-16} = addr;
2649 let Inst{11-0} = offset{11-0};
2650 let DecoderMethod = "DecodeAddrMode2IdxInstruction";
2653 def LDRBT_POST_REG : AI2ldstidx<1, 1, 0, (outs GPR:$Rt, GPR:$Rn_wb),
2654 (ins addr_offset_none:$addr, am2offset_reg:$offset),
2655 IndexModePost, LdFrm, IIC_iLoad_bh_ru,
2656 "ldrbt", "\t$Rt, $addr, $offset",
2657 "$addr.base = $Rn_wb", []> {
2663 let Inst{23} = offset{12};
2664 let Inst{21} = 1; // overwrite
2665 let Inst{19-16} = addr;
2666 let Inst{11-5} = offset{11-5};
2668 let Inst{3-0} = offset{3-0};
2669 let DecoderMethod = "DecodeAddrMode2IdxInstruction";
2673 : AI2ldstidx<1, 1, 0, (outs GPR:$Rt, GPR:$Rn_wb),
2674 (ins addr_offset_none:$addr, am2offset_imm:$offset),
2675 IndexModePost, LdFrm, IIC_iLoad_bh_ru,
2676 "ldrbt", "\t$Rt, $addr, $offset", "$addr.base = $Rn_wb", []> {
2682 let Inst{23} = offset{12};
2683 let Inst{21} = 1; // overwrite
2684 let Inst{19-16} = addr;
2685 let Inst{11-0} = offset{11-0};
2686 let DecoderMethod = "DecodeAddrMode2IdxInstruction";
2689 multiclass AI3ldrT<bits<4> op, string opc> {
2690 def i : AI3ldstidxT<op, 1, (outs GPR:$Rt, GPR:$base_wb),
2691 (ins addr_offset_none:$addr, postidx_imm8:$offset),
2692 IndexModePost, LdMiscFrm, IIC_iLoad_bh_ru, opc,
2693 "\t$Rt, $addr, $offset", "$addr.base = $base_wb", []> {
2695 let Inst{23} = offset{8};
2697 let Inst{11-8} = offset{7-4};
2698 let Inst{3-0} = offset{3-0};
2700 def r : AI3ldstidxT<op, 1, (outs GPRnopc:$Rt, GPRnopc:$base_wb),
2701 (ins addr_offset_none:$addr, postidx_reg:$Rm),
2702 IndexModePost, LdMiscFrm, IIC_iLoad_bh_ru, opc,
2703 "\t$Rt, $addr, $Rm", "$addr.base = $base_wb", []> {
2705 let Inst{23} = Rm{4};
2708 let Unpredictable{11-8} = 0b1111;
2709 let Inst{3-0} = Rm{3-0};
2710 let DecoderMethod = "DecodeLDR";
2714 defm LDRSBT : AI3ldrT<0b1101, "ldrsbt">;
2715 defm LDRHT : AI3ldrT<0b1011, "ldrht">;
2716 defm LDRSHT : AI3ldrT<0b1111, "ldrsht">;
2720 : ARMAsmPseudo<"ldrt${q} $Rt, $addr", (ins addr_offset_none:$addr, pred:$q),
2724 : ARMAsmPseudo<"ldrbt${q} $Rt, $addr", (ins addr_offset_none:$addr, pred:$q),
2729 // Stores with truncate
2730 def STRH : AI3str<0b1011, (outs), (ins GPR:$Rt, addrmode3:$addr), StMiscFrm,
2731 IIC_iStore_bh_r, "strh", "\t$Rt, $addr",
2732 [(truncstorei16 GPR:$Rt, addrmode3:$addr)]>;
2735 let mayStore = 1, hasSideEffects = 0, hasExtraSrcRegAllocReq = 1 in {
2736 def STRD : AI3str<0b1111, (outs), (ins GPR:$Rt, GPR:$Rt2, addrmode3:$addr),
2737 StMiscFrm, IIC_iStore_d_r, "strd", "\t$Rt, $Rt2, $addr", []>,
2738 Requires<[IsARM, HasV5TE]> {
2744 multiclass AI2_stridx<bit isByte, string opc,
2745 InstrItinClass iii, InstrItinClass iir> {
2746 def _PRE_IMM : AI2ldstidx<0, isByte, 1, (outs GPR:$Rn_wb),
2747 (ins GPR:$Rt, addrmode_imm12_pre:$addr), IndexModePre,
2749 opc, "\t$Rt, $addr!",
2750 "$addr.base = $Rn_wb,@earlyclobber $Rn_wb", []> {
2753 let Inst{23} = addr{12}; // U (add = ('U' == 1))
2754 let Inst{19-16} = addr{16-13}; // Rn
2755 let Inst{11-0} = addr{11-0}; // imm12
2756 let DecoderMethod = "DecodeSTRPreImm";
2759 def _PRE_REG : AI2ldstidx<0, isByte, 1, (outs GPR:$Rn_wb),
2760 (ins GPR:$Rt, ldst_so_reg:$addr),
2761 IndexModePre, StFrm, iir,
2762 opc, "\t$Rt, $addr!",
2763 "$addr.base = $Rn_wb,@earlyclobber $Rn_wb", []> {
2766 let Inst{23} = addr{12}; // U (add = ('U' == 1))
2767 let Inst{19-16} = addr{16-13}; // Rn
2768 let Inst{11-0} = addr{11-0};
2769 let Inst{4} = 0; // Inst{4} = 0
2770 let DecoderMethod = "DecodeSTRPreReg";
2772 def _POST_REG : AI2ldstidx<0, isByte, 0, (outs GPR:$Rn_wb),
2773 (ins GPR:$Rt, addr_offset_none:$addr, am2offset_reg:$offset),
2774 IndexModePost, StFrm, iir,
2775 opc, "\t$Rt, $addr, $offset",
2776 "$addr.base = $Rn_wb,@earlyclobber $Rn_wb", []> {
2782 let Inst{23} = offset{12};
2783 let Inst{19-16} = addr;
2784 let Inst{11-0} = offset{11-0};
2787 let DecoderMethod = "DecodeAddrMode2IdxInstruction";
2790 def _POST_IMM : AI2ldstidx<0, isByte, 0, (outs GPR:$Rn_wb),
2791 (ins GPR:$Rt, addr_offset_none:$addr, am2offset_imm:$offset),
2792 IndexModePost, StFrm, iii,
2793 opc, "\t$Rt, $addr, $offset",
2794 "$addr.base = $Rn_wb,@earlyclobber $Rn_wb", []> {
2800 let Inst{23} = offset{12};
2801 let Inst{19-16} = addr;
2802 let Inst{11-0} = offset{11-0};
2804 let DecoderMethod = "DecodeAddrMode2IdxInstruction";
2808 let mayStore = 1, hasSideEffects = 0 in {
2809 // FIXME: for STR_PRE_REG etc. the itineray should be either IIC_iStore_ru or
2810 // IIC_iStore_siu depending on whether it the offset register is shifted.
2811 defm STR : AI2_stridx<0, "str", IIC_iStore_iu, IIC_iStore_ru>;
2812 defm STRB : AI2_stridx<1, "strb", IIC_iStore_bh_iu, IIC_iStore_bh_ru>;
2815 def : ARMPat<(post_store GPR:$Rt, addr_offset_none:$addr,
2816 am2offset_reg:$offset),
2817 (STR_POST_REG GPR:$Rt, addr_offset_none:$addr,
2818 am2offset_reg:$offset)>;
2819 def : ARMPat<(post_store GPR:$Rt, addr_offset_none:$addr,
2820 am2offset_imm:$offset),
2821 (STR_POST_IMM GPR:$Rt, addr_offset_none:$addr,
2822 am2offset_imm:$offset)>;
2823 def : ARMPat<(post_truncsti8 GPR:$Rt, addr_offset_none:$addr,
2824 am2offset_reg:$offset),
2825 (STRB_POST_REG GPR:$Rt, addr_offset_none:$addr,
2826 am2offset_reg:$offset)>;
2827 def : ARMPat<(post_truncsti8 GPR:$Rt, addr_offset_none:$addr,
2828 am2offset_imm:$offset),
2829 (STRB_POST_IMM GPR:$Rt, addr_offset_none:$addr,
2830 am2offset_imm:$offset)>;
2832 // Pseudo-instructions for pattern matching the pre-indexed stores. We can't
2833 // put the patterns on the instruction definitions directly as ISel wants
2834 // the address base and offset to be separate operands, not a single
2835 // complex operand like we represent the instructions themselves. The
2836 // pseudos map between the two.
2837 let usesCustomInserter = 1,
2838 Constraints = "$Rn = $Rn_wb,@earlyclobber $Rn_wb" in {
2839 def STRi_preidx: ARMPseudoInst<(outs GPR:$Rn_wb),
2840 (ins GPR:$Rt, GPR:$Rn, am2offset_imm:$offset, pred:$p),
2843 (pre_store GPR:$Rt, GPR:$Rn, am2offset_imm:$offset))]>;
2844 def STRr_preidx: ARMPseudoInst<(outs GPR:$Rn_wb),
2845 (ins GPR:$Rt, GPR:$Rn, am2offset_reg:$offset, pred:$p),
2848 (pre_store GPR:$Rt, GPR:$Rn, am2offset_reg:$offset))]>;
2849 def STRBi_preidx: ARMPseudoInst<(outs GPR:$Rn_wb),
2850 (ins GPR:$Rt, GPR:$Rn, am2offset_imm:$offset, pred:$p),
2853 (pre_truncsti8 GPR:$Rt, GPR:$Rn, am2offset_imm:$offset))]>;
2854 def STRBr_preidx: ARMPseudoInst<(outs GPR:$Rn_wb),
2855 (ins GPR:$Rt, GPR:$Rn, am2offset_reg:$offset, pred:$p),
2858 (pre_truncsti8 GPR:$Rt, GPR:$Rn, am2offset_reg:$offset))]>;
2859 def STRH_preidx: ARMPseudoInst<(outs GPR:$Rn_wb),
2860 (ins GPR:$Rt, GPR:$Rn, am3offset:$offset, pred:$p),
2863 (pre_truncsti16 GPR:$Rt, GPR:$Rn, am3offset:$offset))]>;
2868 def STRH_PRE : AI3ldstidx<0b1011, 0, 1, (outs GPR:$Rn_wb),
2869 (ins GPR:$Rt, addrmode3_pre:$addr), IndexModePre,
2870 StMiscFrm, IIC_iStore_bh_ru,
2871 "strh", "\t$Rt, $addr!",
2872 "$addr.base = $Rn_wb,@earlyclobber $Rn_wb", []> {
2874 let Inst{23} = addr{8}; // U bit
2875 let Inst{22} = addr{13}; // 1 == imm8, 0 == Rm
2876 let Inst{19-16} = addr{12-9}; // Rn
2877 let Inst{11-8} = addr{7-4}; // imm7_4/zero
2878 let Inst{3-0} = addr{3-0}; // imm3_0/Rm
2879 let DecoderMethod = "DecodeAddrMode3Instruction";
2882 def STRH_POST : AI3ldstidx<0b1011, 0, 0, (outs GPR:$Rn_wb),
2883 (ins GPR:$Rt, addr_offset_none:$addr, am3offset:$offset),
2884 IndexModePost, StMiscFrm, IIC_iStore_bh_ru,
2885 "strh", "\t$Rt, $addr, $offset",
2886 "$addr.base = $Rn_wb,@earlyclobber $Rn_wb",
2887 [(set GPR:$Rn_wb, (post_truncsti16 GPR:$Rt,
2888 addr_offset_none:$addr,
2889 am3offset:$offset))]> {
2892 let Inst{23} = offset{8}; // U bit
2893 let Inst{22} = offset{9}; // 1 == imm8, 0 == Rm
2894 let Inst{19-16} = addr;
2895 let Inst{11-8} = offset{7-4}; // imm7_4/zero
2896 let Inst{3-0} = offset{3-0}; // imm3_0/Rm
2897 let DecoderMethod = "DecodeAddrMode3Instruction";
2900 let mayStore = 1, hasSideEffects = 0, hasExtraSrcRegAllocReq = 1 in {
2901 def STRD_PRE : AI3ldstidx<0b1111, 0, 1, (outs GPR:$Rn_wb),
2902 (ins GPR:$Rt, GPR:$Rt2, addrmode3_pre:$addr),
2903 IndexModePre, StMiscFrm, IIC_iStore_d_ru,
2904 "strd", "\t$Rt, $Rt2, $addr!",
2905 "$addr.base = $Rn_wb", []> {
2907 let Inst{23} = addr{8}; // U bit
2908 let Inst{22} = addr{13}; // 1 == imm8, 0 == Rm
2909 let Inst{19-16} = addr{12-9}; // Rn
2910 let Inst{11-8} = addr{7-4}; // imm7_4/zero
2911 let Inst{3-0} = addr{3-0}; // imm3_0/Rm
2912 let DecoderMethod = "DecodeAddrMode3Instruction";
2915 def STRD_POST: AI3ldstidx<0b1111, 0, 0, (outs GPR:$Rn_wb),
2916 (ins GPR:$Rt, GPR:$Rt2, addr_offset_none:$addr,
2918 IndexModePost, StMiscFrm, IIC_iStore_d_ru,
2919 "strd", "\t$Rt, $Rt2, $addr, $offset",
2920 "$addr.base = $Rn_wb", []> {
2923 let Inst{23} = offset{8}; // U bit
2924 let Inst{22} = offset{9}; // 1 == imm8, 0 == Rm
2925 let Inst{19-16} = addr;
2926 let Inst{11-8} = offset{7-4}; // imm7_4/zero
2927 let Inst{3-0} = offset{3-0}; // imm3_0/Rm
2928 let DecoderMethod = "DecodeAddrMode3Instruction";
2930 } // mayStore = 1, hasSideEffects = 0, hasExtraSrcRegAllocReq = 1
2932 // STRT, STRBT, and STRHT
2934 def STRBT_POST_REG : AI2ldstidx<0, 1, 0, (outs GPR:$Rn_wb),
2935 (ins GPR:$Rt, addr_offset_none:$addr, am2offset_reg:$offset),
2936 IndexModePost, StFrm, IIC_iStore_bh_ru,
2937 "strbt", "\t$Rt, $addr, $offset",
2938 "$addr.base = $Rn_wb", []> {
2944 let Inst{23} = offset{12};
2945 let Inst{21} = 1; // overwrite
2946 let Inst{19-16} = addr;
2947 let Inst{11-5} = offset{11-5};
2949 let Inst{3-0} = offset{3-0};
2950 let DecoderMethod = "DecodeAddrMode2IdxInstruction";
2954 : AI2ldstidx<0, 1, 0, (outs GPR:$Rn_wb),
2955 (ins GPR:$Rt, addr_offset_none:$addr, am2offset_imm:$offset),
2956 IndexModePost, StFrm, IIC_iStore_bh_ru,
2957 "strbt", "\t$Rt, $addr, $offset", "$addr.base = $Rn_wb", []> {
2963 let Inst{23} = offset{12};
2964 let Inst{21} = 1; // overwrite
2965 let Inst{19-16} = addr;
2966 let Inst{11-0} = offset{11-0};
2967 let DecoderMethod = "DecodeAddrMode2IdxInstruction";
2971 : ARMAsmPseudo<"strbt${q} $Rt, $addr",
2972 (ins GPR:$Rt, addr_offset_none:$addr, pred:$q)>;
2974 let mayStore = 1, hasSideEffects = 0 in {
2975 def STRT_POST_REG : AI2ldstidx<0, 0, 0, (outs GPR:$Rn_wb),
2976 (ins GPR:$Rt, addr_offset_none:$addr, am2offset_reg:$offset),
2977 IndexModePost, StFrm, IIC_iStore_ru,
2978 "strt", "\t$Rt, $addr, $offset",
2979 "$addr.base = $Rn_wb", []> {
2985 let Inst{23} = offset{12};
2986 let Inst{21} = 1; // overwrite
2987 let Inst{19-16} = addr;
2988 let Inst{11-5} = offset{11-5};
2990 let Inst{3-0} = offset{3-0};
2991 let DecoderMethod = "DecodeAddrMode2IdxInstruction";
2995 : AI2ldstidx<0, 0, 0, (outs GPR:$Rn_wb),
2996 (ins GPR:$Rt, addr_offset_none:$addr, am2offset_imm:$offset),
2997 IndexModePost, StFrm, IIC_iStore_ru,
2998 "strt", "\t$Rt, $addr, $offset", "$addr.base = $Rn_wb", []> {
3004 let Inst{23} = offset{12};
3005 let Inst{21} = 1; // overwrite
3006 let Inst{19-16} = addr;
3007 let Inst{11-0} = offset{11-0};
3008 let DecoderMethod = "DecodeAddrMode2IdxInstruction";
3013 : ARMAsmPseudo<"strt${q} $Rt, $addr",
3014 (ins GPR:$Rt, addr_offset_none:$addr, pred:$q)>;
3016 multiclass AI3strT<bits<4> op, string opc> {
3017 def i : AI3ldstidxT<op, 0, (outs GPR:$base_wb),
3018 (ins GPR:$Rt, addr_offset_none:$addr, postidx_imm8:$offset),
3019 IndexModePost, StMiscFrm, IIC_iStore_bh_ru, opc,
3020 "\t$Rt, $addr, $offset", "$addr.base = $base_wb", []> {
3022 let Inst{23} = offset{8};
3024 let Inst{11-8} = offset{7-4};
3025 let Inst{3-0} = offset{3-0};
3027 def r : AI3ldstidxT<op, 0, (outs GPR:$base_wb),
3028 (ins GPR:$Rt, addr_offset_none:$addr, postidx_reg:$Rm),
3029 IndexModePost, StMiscFrm, IIC_iStore_bh_ru, opc,
3030 "\t$Rt, $addr, $Rm", "$addr.base = $base_wb", []> {
3032 let Inst{23} = Rm{4};
3035 let Inst{3-0} = Rm{3-0};
3040 defm STRHT : AI3strT<0b1011, "strht">;
3042 def STL : AIstrrel<0b00, (outs), (ins GPR:$Rt, addr_offset_none:$addr),
3043 NoItinerary, "stl", "\t$Rt, $addr", []>;
3044 def STLB : AIstrrel<0b10, (outs), (ins GPR:$Rt, addr_offset_none:$addr),
3045 NoItinerary, "stlb", "\t$Rt, $addr", []>;
3046 def STLH : AIstrrel<0b11, (outs), (ins GPR:$Rt, addr_offset_none:$addr),
3047 NoItinerary, "stlh", "\t$Rt, $addr", []>;
3049 //===----------------------------------------------------------------------===//
3050 // Load / store multiple Instructions.
3053 multiclass arm_ldst_mult<string asm, string sfx, bit L_bit, bit P_bit, Format f,
3054 InstrItinClass itin, InstrItinClass itin_upd> {
3055 // IA is the default, so no need for an explicit suffix on the
3056 // mnemonic here. Without it is the canonical spelling.
3058 AXI4<(outs), (ins GPR:$Rn, pred:$p, reglist:$regs, variable_ops),
3059 IndexModeNone, f, itin,
3060 !strconcat(asm, "${p}\t$Rn, $regs", sfx), "", []> {
3061 let Inst{24-23} = 0b01; // Increment After
3062 let Inst{22} = P_bit;
3063 let Inst{21} = 0; // No writeback
3064 let Inst{20} = L_bit;
3067 AXI4<(outs GPR:$wb), (ins GPR:$Rn, pred:$p, reglist:$regs, variable_ops),
3068 IndexModeUpd, f, itin_upd,
3069 !strconcat(asm, "${p}\t$Rn!, $regs", sfx), "$Rn = $wb", []> {
3070 let Inst{24-23} = 0b01; // Increment After
3071 let Inst{22} = P_bit;
3072 let Inst{21} = 1; // Writeback
3073 let Inst{20} = L_bit;
3075 let DecoderMethod = "DecodeMemMultipleWritebackInstruction";
3078 AXI4<(outs), (ins GPR:$Rn, pred:$p, reglist:$regs, variable_ops),
3079 IndexModeNone, f, itin,
3080 !strconcat(asm, "da${p}\t$Rn, $regs", sfx), "", []> {
3081 let Inst{24-23} = 0b00; // Decrement After
3082 let Inst{22} = P_bit;
3083 let Inst{21} = 0; // No writeback
3084 let Inst{20} = L_bit;
3087 AXI4<(outs GPR:$wb), (ins GPR:$Rn, pred:$p, reglist:$regs, variable_ops),
3088 IndexModeUpd, f, itin_upd,
3089 !strconcat(asm, "da${p}\t$Rn!, $regs", sfx), "$Rn = $wb", []> {
3090 let Inst{24-23} = 0b00; // Decrement After
3091 let Inst{22} = P_bit;
3092 let Inst{21} = 1; // Writeback
3093 let Inst{20} = L_bit;
3095 let DecoderMethod = "DecodeMemMultipleWritebackInstruction";
3098 AXI4<(outs), (ins GPR:$Rn, pred:$p, reglist:$regs, variable_ops),
3099 IndexModeNone, f, itin,
3100 !strconcat(asm, "db${p}\t$Rn, $regs", sfx), "", []> {
3101 let Inst{24-23} = 0b10; // Decrement Before
3102 let Inst{22} = P_bit;
3103 let Inst{21} = 0; // No writeback
3104 let Inst{20} = L_bit;
3107 AXI4<(outs GPR:$wb), (ins GPR:$Rn, pred:$p, reglist:$regs, variable_ops),
3108 IndexModeUpd, f, itin_upd,
3109 !strconcat(asm, "db${p}\t$Rn!, $regs", sfx), "$Rn = $wb", []> {
3110 let Inst{24-23} = 0b10; // Decrement Before
3111 let Inst{22} = P_bit;
3112 let Inst{21} = 1; // Writeback
3113 let Inst{20} = L_bit;
3115 let DecoderMethod = "DecodeMemMultipleWritebackInstruction";
3118 AXI4<(outs), (ins GPR:$Rn, pred:$p, reglist:$regs, variable_ops),
3119 IndexModeNone, f, itin,
3120 !strconcat(asm, "ib${p}\t$Rn, $regs", sfx), "", []> {
3121 let Inst{24-23} = 0b11; // Increment Before
3122 let Inst{22} = P_bit;
3123 let Inst{21} = 0; // No writeback
3124 let Inst{20} = L_bit;
3127 AXI4<(outs GPR:$wb), (ins GPR:$Rn, pred:$p, reglist:$regs, variable_ops),
3128 IndexModeUpd, f, itin_upd,
3129 !strconcat(asm, "ib${p}\t$Rn!, $regs", sfx), "$Rn = $wb", []> {
3130 let Inst{24-23} = 0b11; // Increment Before
3131 let Inst{22} = P_bit;
3132 let Inst{21} = 1; // Writeback
3133 let Inst{20} = L_bit;
3135 let DecoderMethod = "DecodeMemMultipleWritebackInstruction";
3139 let hasSideEffects = 0 in {
3141 let mayLoad = 1, hasExtraDefRegAllocReq = 1 in
3142 defm LDM : arm_ldst_mult<"ldm", "", 1, 0, LdStMulFrm, IIC_iLoad_m,
3143 IIC_iLoad_mu>, ComplexDeprecationPredicate<"ARMLoad">;
3145 let mayStore = 1, hasExtraSrcRegAllocReq = 1 in
3146 defm STM : arm_ldst_mult<"stm", "", 0, 0, LdStMulFrm, IIC_iStore_m,
3148 ComplexDeprecationPredicate<"ARMStore">;
3152 // FIXME: remove when we have a way to marking a MI with these properties.
3153 // FIXME: Should pc be an implicit operand like PICADD, etc?
3154 let isReturn = 1, isTerminator = 1, isBarrier = 1, mayLoad = 1,
3155 hasExtraDefRegAllocReq = 1, isCodeGenOnly = 1 in
3156 def LDMIA_RET : ARMPseudoExpand<(outs GPR:$wb), (ins GPR:$Rn, pred:$p,
3157 reglist:$regs, variable_ops),
3158 4, IIC_iLoad_mBr, [],
3159 (LDMIA_UPD GPR:$wb, GPR:$Rn, pred:$p, reglist:$regs)>,
3160 RegConstraint<"$Rn = $wb">;
3162 let mayLoad = 1, hasExtraDefRegAllocReq = 1 in
3163 defm sysLDM : arm_ldst_mult<"ldm", " ^", 1, 1, LdStMulFrm, IIC_iLoad_m,
3166 let mayStore = 1, hasExtraSrcRegAllocReq = 1 in
3167 defm sysSTM : arm_ldst_mult<"stm", " ^", 0, 1, LdStMulFrm, IIC_iStore_m,
3172 //===----------------------------------------------------------------------===//
3173 // Move Instructions.
3176 let hasSideEffects = 0 in
3177 def MOVr : AsI1<0b1101, (outs GPR:$Rd), (ins GPR:$Rm), DPFrm, IIC_iMOVr,
3178 "mov", "\t$Rd, $Rm", []>, UnaryDP, Sched<[WriteALU]> {
3182 let Inst{19-16} = 0b0000;
3183 let Inst{11-4} = 0b00000000;
3186 let Inst{15-12} = Rd;
3189 // A version for the smaller set of tail call registers.
3190 let hasSideEffects = 0 in
3191 def MOVr_TC : AsI1<0b1101, (outs tcGPR:$Rd), (ins tcGPR:$Rm), DPFrm,
3192 IIC_iMOVr, "mov", "\t$Rd, $Rm", []>, UnaryDP, Sched<[WriteALU]> {
3196 let Inst{11-4} = 0b00000000;
3199 let Inst{15-12} = Rd;
3202 def MOVsr : AsI1<0b1101, (outs GPRnopc:$Rd), (ins shift_so_reg_reg:$src),
3203 DPSoRegRegFrm, IIC_iMOVsr,
3204 "mov", "\t$Rd, $src",
3205 [(set GPRnopc:$Rd, shift_so_reg_reg:$src)]>, UnaryDP,
3209 let Inst{15-12} = Rd;
3210 let Inst{19-16} = 0b0000;
3211 let Inst{11-8} = src{11-8};
3213 let Inst{6-5} = src{6-5};
3215 let Inst{3-0} = src{3-0};
3219 def MOVsi : AsI1<0b1101, (outs GPR:$Rd), (ins shift_so_reg_imm:$src),
3220 DPSoRegImmFrm, IIC_iMOVsr,
3221 "mov", "\t$Rd, $src", [(set GPR:$Rd, shift_so_reg_imm:$src)]>,
3222 UnaryDP, Sched<[WriteALU]> {
3225 let Inst{15-12} = Rd;
3226 let Inst{19-16} = 0b0000;
3227 let Inst{11-5} = src{11-5};
3229 let Inst{3-0} = src{3-0};
3233 let isReMaterializable = 1, isAsCheapAsAMove = 1, isMoveImm = 1 in
3234 def MOVi : AsI1<0b1101, (outs GPR:$Rd), (ins mod_imm:$imm), DPFrm, IIC_iMOVi,
3235 "mov", "\t$Rd, $imm", [(set GPR:$Rd, mod_imm:$imm)]>, UnaryDP,
3240 let Inst{15-12} = Rd;
3241 let Inst{19-16} = 0b0000;
3242 let Inst{11-0} = imm;
3245 let isReMaterializable = 1, isAsCheapAsAMove = 1, isMoveImm = 1 in
3246 def MOVi16 : AI1<0b1000, (outs GPR:$Rd), (ins imm0_65535_expr:$imm),
3248 "movw", "\t$Rd, $imm",
3249 [(set GPR:$Rd, imm0_65535:$imm)]>,
3250 Requires<[IsARM, HasV6T2]>, UnaryDP, Sched<[WriteALU]> {
3253 let Inst{15-12} = Rd;
3254 let Inst{11-0} = imm{11-0};
3255 let Inst{19-16} = imm{15-12};
3258 let DecoderMethod = "DecodeArmMOVTWInstruction";
3261 def : InstAlias<"mov${p} $Rd, $imm",
3262 (MOVi16 GPR:$Rd, imm0_65535_expr:$imm, pred:$p)>,
3265 def MOVi16_ga_pcrel : PseudoInst<(outs GPR:$Rd),
3266 (ins i32imm:$addr, pclabel:$id), IIC_iMOVi, []>,
3269 let Constraints = "$src = $Rd" in {
3270 def MOVTi16 : AI1<0b1010, (outs GPRnopc:$Rd),
3271 (ins GPR:$src, imm0_65535_expr:$imm),
3273 "movt", "\t$Rd, $imm",
3275 (or (and GPR:$src, 0xffff),
3276 lo16AllZero:$imm))]>, UnaryDP,
3277 Requires<[IsARM, HasV6T2]>, Sched<[WriteALU]> {
3280 let Inst{15-12} = Rd;
3281 let Inst{11-0} = imm{11-0};
3282 let Inst{19-16} = imm{15-12};
3285 let DecoderMethod = "DecodeArmMOVTWInstruction";
3288 def MOVTi16_ga_pcrel : PseudoInst<(outs GPR:$Rd),
3289 (ins GPR:$src, i32imm:$addr, pclabel:$id), IIC_iMOVi, []>,
3294 def : ARMPat<(or GPR:$src, 0xffff0000), (MOVTi16 GPR:$src, 0xffff)>,
3295 Requires<[IsARM, HasV6T2]>;
3297 let Uses = [CPSR] in
3298 def RRX: PseudoInst<(outs GPR:$Rd), (ins GPR:$Rm), IIC_iMOVsi,
3299 [(set GPR:$Rd, (ARMrrx GPR:$Rm))]>, UnaryDP,
3300 Requires<[IsARM]>, Sched<[WriteALU]>;
3302 // These aren't really mov instructions, but we have to define them this way
3303 // due to flag operands.
3305 let Defs = [CPSR] in {
3306 def MOVsrl_flag : PseudoInst<(outs GPR:$dst), (ins GPR:$src), IIC_iMOVsi,
3307 [(set GPR:$dst, (ARMsrl_flag GPR:$src))]>, UnaryDP,
3308 Sched<[WriteALU]>, Requires<[IsARM]>;
3309 def MOVsra_flag : PseudoInst<(outs GPR:$dst), (ins GPR:$src), IIC_iMOVsi,
3310 [(set GPR:$dst, (ARMsra_flag GPR:$src))]>, UnaryDP,
3311 Sched<[WriteALU]>, Requires<[IsARM]>;
3314 //===----------------------------------------------------------------------===//
3315 // Extend Instructions.
3320 def SXTB : AI_ext_rrot<0b01101010,
3321 "sxtb", UnOpFrag<(sext_inreg node:$Src, i8)>>;
3322 def SXTH : AI_ext_rrot<0b01101011,
3323 "sxth", UnOpFrag<(sext_inreg node:$Src, i16)>>;
3325 def SXTAB : AI_exta_rrot<0b01101010,
3326 "sxtab", BinOpFrag<(add node:$LHS, (sext_inreg node:$RHS, i8))>>;
3327 def SXTAH : AI_exta_rrot<0b01101011,
3328 "sxtah", BinOpFrag<(add node:$LHS, (sext_inreg node:$RHS,i16))>>;
3330 def SXTB16 : AI_ext_rrot_np<0b01101000, "sxtb16">;
3332 def SXTAB16 : AI_exta_rrot_np<0b01101000, "sxtab16">;
3336 let AddedComplexity = 16 in {
3337 def UXTB : AI_ext_rrot<0b01101110,
3338 "uxtb" , UnOpFrag<(and node:$Src, 0x000000FF)>>;
3339 def UXTH : AI_ext_rrot<0b01101111,
3340 "uxth" , UnOpFrag<(and node:$Src, 0x0000FFFF)>>;
3341 def UXTB16 : AI_ext_rrot<0b01101100,
3342 "uxtb16", UnOpFrag<(and node:$Src, 0x00FF00FF)>>;
3344 // FIXME: This pattern incorrectly assumes the shl operator is a rotate.
3345 // The transformation should probably be done as a combiner action
3346 // instead so we can include a check for masking back in the upper
3347 // eight bits of the source into the lower eight bits of the result.
3348 //def : ARMV6Pat<(and (shl GPR:$Src, (i32 8)), 0xFF00FF),
3349 // (UXTB16r_rot GPR:$Src, 3)>;
3350 def : ARMV6Pat<(and (srl GPR:$Src, (i32 8)), 0xFF00FF),
3351 (UXTB16 GPR:$Src, 1)>;
3353 def UXTAB : AI_exta_rrot<0b01101110, "uxtab",
3354 BinOpFrag<(add node:$LHS, (and node:$RHS, 0x00FF))>>;
3355 def UXTAH : AI_exta_rrot<0b01101111, "uxtah",
3356 BinOpFrag<(add node:$LHS, (and node:$RHS, 0xFFFF))>>;
3359 // This isn't safe in general, the add is two 16-bit units, not a 32-bit add.
3360 def UXTAB16 : AI_exta_rrot_np<0b01101100, "uxtab16">;
3363 def SBFX : I<(outs GPRnopc:$Rd),
3364 (ins GPRnopc:$Rn, imm0_31:$lsb, imm1_32:$width),
3365 AddrMode1, 4, IndexModeNone, DPFrm, IIC_iUNAsi,
3366 "sbfx", "\t$Rd, $Rn, $lsb, $width", "", []>,
3367 Requires<[IsARM, HasV6T2]> {
3372 let Inst{27-21} = 0b0111101;
3373 let Inst{6-4} = 0b101;
3374 let Inst{20-16} = width;
3375 let Inst{15-12} = Rd;
3376 let Inst{11-7} = lsb;
3380 def UBFX : I<(outs GPRnopc:$Rd),
3381 (ins GPRnopc:$Rn, imm0_31:$lsb, imm1_32:$width),
3382 AddrMode1, 4, IndexModeNone, DPFrm, IIC_iUNAsi,
3383 "ubfx", "\t$Rd, $Rn, $lsb, $width", "", []>,
3384 Requires<[IsARM, HasV6T2]> {
3389 let Inst{27-21} = 0b0111111;
3390 let Inst{6-4} = 0b101;
3391 let Inst{20-16} = width;
3392 let Inst{15-12} = Rd;
3393 let Inst{11-7} = lsb;
3397 //===----------------------------------------------------------------------===//
3398 // Arithmetic Instructions.
3401 defm ADD : AsI1_bin_irs<0b0100, "add",
3402 IIC_iALUi, IIC_iALUr, IIC_iALUsr,
3403 BinOpFrag<(add node:$LHS, node:$RHS)>, 1>;
3404 defm SUB : AsI1_bin_irs<0b0010, "sub",
3405 IIC_iALUi, IIC_iALUr, IIC_iALUsr,
3406 BinOpFrag<(sub node:$LHS, node:$RHS)>>;
3408 // ADD and SUB with 's' bit set.
3410 // Currently, ADDS/SUBS are pseudo opcodes that exist only in the
3411 // selection DAG. They are "lowered" to real ADD/SUB opcodes by
3412 // AdjustInstrPostInstrSelection where we determine whether or not to
3413 // set the "s" bit based on CPSR liveness.
3415 // FIXME: Eliminate ADDS/SUBS pseudo opcodes after adding tablegen
3416 // support for an optional CPSR definition that corresponds to the DAG
3417 // node's second value. We can then eliminate the implicit def of CPSR.
3418 defm ADDS : AsI1_bin_s_irs<IIC_iALUi, IIC_iALUr, IIC_iALUsr,
3419 BinOpFrag<(ARMaddc node:$LHS, node:$RHS)>, 1>;
3420 defm SUBS : AsI1_bin_s_irs<IIC_iALUi, IIC_iALUr, IIC_iALUsr,
3421 BinOpFrag<(ARMsubc node:$LHS, node:$RHS)>>;
3423 defm ADC : AI1_adde_sube_irs<0b0101, "adc",
3424 BinOpWithFlagFrag<(ARMadde node:$LHS, node:$RHS, node:$FLAG)>, 1>;
3425 defm SBC : AI1_adde_sube_irs<0b0110, "sbc",
3426 BinOpWithFlagFrag<(ARMsube node:$LHS, node:$RHS, node:$FLAG)>>;
3428 defm RSB : AsI1_rbin_irs<0b0011, "rsb",
3429 IIC_iALUi, IIC_iALUr, IIC_iALUsr,
3430 BinOpFrag<(sub node:$LHS, node:$RHS)>>;
3432 // FIXME: Eliminate them if we can write def : Pat patterns which defines
3433 // CPSR and the implicit def of CPSR is not needed.
3434 defm RSBS : AsI1_rbin_s_is<IIC_iALUi, IIC_iALUr, IIC_iALUsr,
3435 BinOpFrag<(ARMsubc node:$LHS, node:$RHS)>>;
3437 defm RSC : AI1_rsc_irs<0b0111, "rsc",
3438 BinOpWithFlagFrag<(ARMsube node:$LHS, node:$RHS, node:$FLAG)>>;
3440 // (sub X, imm) gets canonicalized to (add X, -imm). Match this form.
3441 // The assume-no-carry-in form uses the negation of the input since add/sub
3442 // assume opposite meanings of the carry flag (i.e., carry == !borrow).
3443 // See the definition of AddWithCarry() in the ARM ARM A2.2.1 for the gory
3445 def : ARMPat<(add GPR:$src, mod_imm_neg:$imm),
3446 (SUBri GPR:$src, mod_imm_neg:$imm)>;
3447 def : ARMPat<(ARMaddc GPR:$src, mod_imm_neg:$imm),
3448 (SUBSri GPR:$src, mod_imm_neg:$imm)>;
3450 def : ARMPat<(add GPR:$src, imm0_65535_neg:$imm),
3451 (SUBrr GPR:$src, (MOVi16 (imm_neg_XFORM imm:$imm)))>,
3452 Requires<[IsARM, HasV6T2]>;
3453 def : ARMPat<(ARMaddc GPR:$src, imm0_65535_neg:$imm),
3454 (SUBSrr GPR:$src, (MOVi16 (imm_neg_XFORM imm:$imm)))>,
3455 Requires<[IsARM, HasV6T2]>;
3457 // The with-carry-in form matches bitwise not instead of the negation.
3458 // Effectively, the inverse interpretation of the carry flag already accounts
3459 // for part of the negation.
3460 def : ARMPat<(ARMadde GPR:$src, mod_imm_not:$imm, CPSR),
3461 (SBCri GPR:$src, mod_imm_not:$imm)>;
3462 def : ARMPat<(ARMadde GPR:$src, imm0_65535_neg:$imm, CPSR),
3463 (SBCrr GPR:$src, (MOVi16 (imm_not_XFORM imm:$imm)))>,
3464 Requires<[IsARM, HasV6T2]>;
3466 // Note: These are implemented in C++ code, because they have to generate
3467 // ADD/SUBrs instructions, which use a complex pattern that a xform function
3469 // (mul X, 2^n+1) -> (add (X << n), X)
3470 // (mul X, 2^n-1) -> (rsb X, (X << n))
3472 // ARM Arithmetic Instruction
3473 // GPR:$dst = GPR:$a op GPR:$b
3474 class AAI<bits<8> op27_20, bits<8> op11_4, string opc,
3475 list<dag> pattern = [],
3476 dag iops = (ins GPRnopc:$Rn, GPRnopc:$Rm),
3477 string asm = "\t$Rd, $Rn, $Rm">
3478 : AI<(outs GPRnopc:$Rd), iops, DPFrm, IIC_iALUr, opc, asm, pattern>,
3479 Sched<[WriteALU, ReadALU, ReadALU]> {
3483 let Inst{27-20} = op27_20;
3484 let Inst{11-4} = op11_4;
3485 let Inst{19-16} = Rn;
3486 let Inst{15-12} = Rd;
3489 let Unpredictable{11-8} = 0b1111;
3492 // Saturating add/subtract
3494 let DecoderMethod = "DecodeQADDInstruction" in
3495 def QADD : AAI<0b00010000, 0b00000101, "qadd",
3496 [(set GPRnopc:$Rd, (int_arm_qadd GPRnopc:$Rm, GPRnopc:$Rn))],
3497 (ins GPRnopc:$Rm, GPRnopc:$Rn), "\t$Rd, $Rm, $Rn">;
3499 def QSUB : AAI<0b00010010, 0b00000101, "qsub",
3500 [(set GPRnopc:$Rd, (int_arm_qsub GPRnopc:$Rm, GPRnopc:$Rn))],
3501 (ins GPRnopc:$Rm, GPRnopc:$Rn), "\t$Rd, $Rm, $Rn">;
3502 def QDADD : AAI<0b00010100, 0b00000101, "qdadd", [],
3503 (ins GPRnopc:$Rm, GPRnopc:$Rn),
3505 def QDSUB : AAI<0b00010110, 0b00000101, "qdsub", [],
3506 (ins GPRnopc:$Rm, GPRnopc:$Rn),
3509 def QADD16 : AAI<0b01100010, 0b11110001, "qadd16">;
3510 def QADD8 : AAI<0b01100010, 0b11111001, "qadd8">;
3511 def QASX : AAI<0b01100010, 0b11110011, "qasx">;
3512 def QSAX : AAI<0b01100010, 0b11110101, "qsax">;
3513 def QSUB16 : AAI<0b01100010, 0b11110111, "qsub16">;
3514 def QSUB8 : AAI<0b01100010, 0b11111111, "qsub8">;
3515 def UQADD16 : AAI<0b01100110, 0b11110001, "uqadd16">;
3516 def UQADD8 : AAI<0b01100110, 0b11111001, "uqadd8">;
3517 def UQASX : AAI<0b01100110, 0b11110011, "uqasx">;
3518 def UQSAX : AAI<0b01100110, 0b11110101, "uqsax">;
3519 def UQSUB16 : AAI<0b01100110, 0b11110111, "uqsub16">;
3520 def UQSUB8 : AAI<0b01100110, 0b11111111, "uqsub8">;
3522 // Signed/Unsigned add/subtract
3524 def SASX : AAI<0b01100001, 0b11110011, "sasx">;
3525 def SADD16 : AAI<0b01100001, 0b11110001, "sadd16">;
3526 def SADD8 : AAI<0b01100001, 0b11111001, "sadd8">;
3527 def SSAX : AAI<0b01100001, 0b11110101, "ssax">;
3528 def SSUB16 : AAI<0b01100001, 0b11110111, "ssub16">;
3529 def SSUB8 : AAI<0b01100001, 0b11111111, "ssub8">;
3530 def UASX : AAI<0b01100101, 0b11110011, "uasx">;
3531 def UADD16 : AAI<0b01100101, 0b11110001, "uadd16">;
3532 def UADD8 : AAI<0b01100101, 0b11111001, "uadd8">;
3533 def USAX : AAI<0b01100101, 0b11110101, "usax">;
3534 def USUB16 : AAI<0b01100101, 0b11110111, "usub16">;
3535 def USUB8 : AAI<0b01100101, 0b11111111, "usub8">;
3537 // Signed/Unsigned halving add/subtract
3539 def SHASX : AAI<0b01100011, 0b11110011, "shasx">;
3540 def SHADD16 : AAI<0b01100011, 0b11110001, "shadd16">;
3541 def SHADD8 : AAI<0b01100011, 0b11111001, "shadd8">;
3542 def SHSAX : AAI<0b01100011, 0b11110101, "shsax">;
3543 def SHSUB16 : AAI<0b01100011, 0b11110111, "shsub16">;
3544 def SHSUB8 : AAI<0b01100011, 0b11111111, "shsub8">;
3545 def UHASX : AAI<0b01100111, 0b11110011, "uhasx">;
3546 def UHADD16 : AAI<0b01100111, 0b11110001, "uhadd16">;
3547 def UHADD8 : AAI<0b01100111, 0b11111001, "uhadd8">;
3548 def UHSAX : AAI<0b01100111, 0b11110101, "uhsax">;
3549 def UHSUB16 : AAI<0b01100111, 0b11110111, "uhsub16">;
3550 def UHSUB8 : AAI<0b01100111, 0b11111111, "uhsub8">;
3552 // Unsigned Sum of Absolute Differences [and Accumulate].
3554 def USAD8 : AI<(outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm),
3555 MulFrm /* for convenience */, NoItinerary, "usad8",
3556 "\t$Rd, $Rn, $Rm", []>,
3557 Requires<[IsARM, HasV6]>, Sched<[WriteALU, ReadALU, ReadALU]> {
3561 let Inst{27-20} = 0b01111000;
3562 let Inst{15-12} = 0b1111;
3563 let Inst{7-4} = 0b0001;
3564 let Inst{19-16} = Rd;
3565 let Inst{11-8} = Rm;
3568 def USADA8 : AI<(outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm, GPR:$Ra),
3569 MulFrm /* for convenience */, NoItinerary, "usada8",
3570 "\t$Rd, $Rn, $Rm, $Ra", []>,
3571 Requires<[IsARM, HasV6]>, Sched<[WriteALU, ReadALU, ReadALU]>{
3576 let Inst{27-20} = 0b01111000;
3577 let Inst{7-4} = 0b0001;
3578 let Inst{19-16} = Rd;
3579 let Inst{15-12} = Ra;
3580 let Inst{11-8} = Rm;
3584 // Signed/Unsigned saturate
3586 def SSAT : AI<(outs GPRnopc:$Rd),
3587 (ins imm1_32:$sat_imm, GPRnopc:$Rn, shift_imm:$sh),
3588 SatFrm, NoItinerary, "ssat", "\t$Rd, $sat_imm, $Rn$sh", []> {
3593 let Inst{27-21} = 0b0110101;
3594 let Inst{5-4} = 0b01;
3595 let Inst{20-16} = sat_imm;
3596 let Inst{15-12} = Rd;
3597 let Inst{11-7} = sh{4-0};
3598 let Inst{6} = sh{5};
3602 def SSAT16 : AI<(outs GPRnopc:$Rd),
3603 (ins imm1_16:$sat_imm, GPRnopc:$Rn), SatFrm,
3604 NoItinerary, "ssat16", "\t$Rd, $sat_imm, $Rn", []> {
3608 let Inst{27-20} = 0b01101010;
3609 let Inst{11-4} = 0b11110011;
3610 let Inst{15-12} = Rd;
3611 let Inst{19-16} = sat_imm;
3615 def USAT : AI<(outs GPRnopc:$Rd),
3616 (ins imm0_31:$sat_imm, GPRnopc:$Rn, shift_imm:$sh),
3617 SatFrm, NoItinerary, "usat", "\t$Rd, $sat_imm, $Rn$sh", []> {
3622 let Inst{27-21} = 0b0110111;
3623 let Inst{5-4} = 0b01;
3624 let Inst{15-12} = Rd;
3625 let Inst{11-7} = sh{4-0};
3626 let Inst{6} = sh{5};
3627 let Inst{20-16} = sat_imm;
3631 def USAT16 : AI<(outs GPRnopc:$Rd),
3632 (ins imm0_15:$sat_imm, GPRnopc:$Rn), SatFrm,
3633 NoItinerary, "usat16", "\t$Rd, $sat_imm, $Rn", []> {
3637 let Inst{27-20} = 0b01101110;
3638 let Inst{11-4} = 0b11110011;
3639 let Inst{15-12} = Rd;
3640 let Inst{19-16} = sat_imm;
3644 def : ARMV6Pat<(int_arm_ssat GPRnopc:$a, imm:$pos),
3645 (SSAT imm:$pos, GPRnopc:$a, 0)>;
3646 def : ARMV6Pat<(int_arm_usat GPRnopc:$a, imm:$pos),
3647 (USAT imm:$pos, GPRnopc:$a, 0)>;
3649 //===----------------------------------------------------------------------===//
3650 // Bitwise Instructions.
3653 defm AND : AsI1_bin_irs<0b0000, "and",
3654 IIC_iBITi, IIC_iBITr, IIC_iBITsr,
3655 BinOpFrag<(and node:$LHS, node:$RHS)>, 1>;
3656 defm ORR : AsI1_bin_irs<0b1100, "orr",
3657 IIC_iBITi, IIC_iBITr, IIC_iBITsr,
3658 BinOpFrag<(or node:$LHS, node:$RHS)>, 1>;
3659 defm EOR : AsI1_bin_irs<0b0001, "eor",
3660 IIC_iBITi, IIC_iBITr, IIC_iBITsr,
3661 BinOpFrag<(xor node:$LHS, node:$RHS)>, 1>;
3662 defm BIC : AsI1_bin_irs<0b1110, "bic",
3663 IIC_iBITi, IIC_iBITr, IIC_iBITsr,
3664 BinOpFrag<(and node:$LHS, (not node:$RHS))>>;
3666 // FIXME: bf_inv_mask_imm should be two operands, the lsb and the msb, just
3667 // like in the actual instruction encoding. The complexity of mapping the mask
3668 // to the lsb/msb pair should be handled by ISel, not encapsulated in the
3669 // instruction description.
3670 def BFC : I<(outs GPR:$Rd), (ins GPR:$src, bf_inv_mask_imm:$imm),
3671 AddrMode1, 4, IndexModeNone, DPFrm, IIC_iUNAsi,
3672 "bfc", "\t$Rd, $imm", "$src = $Rd",
3673 [(set GPR:$Rd, (and GPR:$src, bf_inv_mask_imm:$imm))]>,
3674 Requires<[IsARM, HasV6T2]> {
3677 let Inst{27-21} = 0b0111110;
3678 let Inst{6-0} = 0b0011111;
3679 let Inst{15-12} = Rd;
3680 let Inst{11-7} = imm{4-0}; // lsb
3681 let Inst{20-16} = imm{9-5}; // msb
3684 // A8.6.18 BFI - Bitfield insert (Encoding A1)
3685 def BFI:I<(outs GPRnopc:$Rd), (ins GPRnopc:$src, GPR:$Rn, bf_inv_mask_imm:$imm),
3686 AddrMode1, 4, IndexModeNone, DPFrm, IIC_iUNAsi,
3687 "bfi", "\t$Rd, $Rn, $imm", "$src = $Rd",
3688 [(set GPRnopc:$Rd, (ARMbfi GPRnopc:$src, GPR:$Rn,
3689 bf_inv_mask_imm:$imm))]>,
3690 Requires<[IsARM, HasV6T2]> {
3694 let Inst{27-21} = 0b0111110;
3695 let Inst{6-4} = 0b001; // Rn: Inst{3-0} != 15
3696 let Inst{15-12} = Rd;
3697 let Inst{11-7} = imm{4-0}; // lsb
3698 let Inst{20-16} = imm{9-5}; // width
3702 def MVNr : AsI1<0b1111, (outs GPR:$Rd), (ins GPR:$Rm), DPFrm, IIC_iMVNr,
3703 "mvn", "\t$Rd, $Rm",
3704 [(set GPR:$Rd, (not GPR:$Rm))]>, UnaryDP, Sched<[WriteALU]> {
3708 let Inst{19-16} = 0b0000;
3709 let Inst{11-4} = 0b00000000;
3710 let Inst{15-12} = Rd;
3713 def MVNsi : AsI1<0b1111, (outs GPR:$Rd), (ins so_reg_imm:$shift),
3714 DPSoRegImmFrm, IIC_iMVNsr, "mvn", "\t$Rd, $shift",
3715 [(set GPR:$Rd, (not so_reg_imm:$shift))]>, UnaryDP,
3720 let Inst{19-16} = 0b0000;
3721 let Inst{15-12} = Rd;
3722 let Inst{11-5} = shift{11-5};
3724 let Inst{3-0} = shift{3-0};
3726 def MVNsr : AsI1<0b1111, (outs GPR:$Rd), (ins so_reg_reg:$shift),
3727 DPSoRegRegFrm, IIC_iMVNsr, "mvn", "\t$Rd, $shift",
3728 [(set GPR:$Rd, (not so_reg_reg:$shift))]>, UnaryDP,
3733 let Inst{19-16} = 0b0000;
3734 let Inst{15-12} = Rd;
3735 let Inst{11-8} = shift{11-8};
3737 let Inst{6-5} = shift{6-5};
3739 let Inst{3-0} = shift{3-0};
3741 let isReMaterializable = 1, isAsCheapAsAMove = 1, isMoveImm = 1 in
3742 def MVNi : AsI1<0b1111, (outs GPR:$Rd), (ins mod_imm:$imm), DPFrm,
3743 IIC_iMVNi, "mvn", "\t$Rd, $imm",
3744 [(set GPR:$Rd, mod_imm_not:$imm)]>,UnaryDP, Sched<[WriteALU]> {
3748 let Inst{19-16} = 0b0000;
3749 let Inst{15-12} = Rd;
3750 let Inst{11-0} = imm;
3753 def : ARMPat<(and GPR:$src, mod_imm_not:$imm),
3754 (BICri GPR:$src, mod_imm_not:$imm)>;
3756 //===----------------------------------------------------------------------===//
3757 // Multiply Instructions.
3759 class AsMul1I32<bits<7> opcod, dag oops, dag iops, InstrItinClass itin,
3760 string opc, string asm, list<dag> pattern>
3761 : AsMul1I<opcod, oops, iops, itin, opc, asm, pattern> {
3765 let Inst{19-16} = Rd;
3766 let Inst{11-8} = Rm;
3769 class AsMul1I64<bits<7> opcod, dag oops, dag iops, InstrItinClass itin,
3770 string opc, string asm, list<dag> pattern>
3771 : AsMul1I<opcod, oops, iops, itin, opc, asm, pattern> {
3776 let Inst{19-16} = RdHi;
3777 let Inst{15-12} = RdLo;
3778 let Inst{11-8} = Rm;
3781 class AsMla1I64<bits<7> opcod, dag oops, dag iops, InstrItinClass itin,
3782 string opc, string asm, list<dag> pattern>
3783 : AsMul1I<opcod, oops, iops, itin, opc, asm, pattern> {
3788 let Inst{19-16} = RdHi;
3789 let Inst{15-12} = RdLo;
3790 let Inst{11-8} = Rm;
3794 // FIXME: The v5 pseudos are only necessary for the additional Constraint
3795 // property. Remove them when it's possible to add those properties
3796 // on an individual MachineInstr, not just an instruction description.
3797 let isCommutable = 1, TwoOperandAliasConstraint = "$Rn = $Rd" in {
3798 def MUL : AsMul1I32<0b0000000, (outs GPRnopc:$Rd),
3799 (ins GPRnopc:$Rn, GPRnopc:$Rm),
3800 IIC_iMUL32, "mul", "\t$Rd, $Rn, $Rm",
3801 [(set GPRnopc:$Rd, (mul GPRnopc:$Rn, GPRnopc:$Rm))]>,
3802 Requires<[IsARM, HasV6]> {
3803 let Inst{15-12} = 0b0000;
3804 let Unpredictable{15-12} = 0b1111;
3807 let Constraints = "@earlyclobber $Rd" in
3808 def MULv5: ARMPseudoExpand<(outs GPRnopc:$Rd), (ins GPRnopc:$Rn, GPRnopc:$Rm,
3809 pred:$p, cc_out:$s),
3811 [(set GPRnopc:$Rd, (mul GPRnopc:$Rn, GPRnopc:$Rm))],
3812 (MUL GPRnopc:$Rd, GPRnopc:$Rn, GPRnopc:$Rm, pred:$p, cc_out:$s)>,
3813 Requires<[IsARM, NoV6, UseMulOps]>;
3816 def MLA : AsMul1I32<0b0000001, (outs GPRnopc:$Rd),
3817 (ins GPRnopc:$Rn, GPRnopc:$Rm, GPRnopc:$Ra),
3818 IIC_iMAC32, "mla", "\t$Rd, $Rn, $Rm, $Ra",
3819 [(set GPRnopc:$Rd, (add (mul GPRnopc:$Rn, GPRnopc:$Rm), GPRnopc:$Ra))]>,
3820 Requires<[IsARM, HasV6, UseMulOps]> {
3822 let Inst{15-12} = Ra;
3825 let Constraints = "@earlyclobber $Rd" in
3826 def MLAv5: ARMPseudoExpand<(outs GPRnopc:$Rd),
3827 (ins GPRnopc:$Rn, GPRnopc:$Rm, GPRnopc:$Ra,
3828 pred:$p, cc_out:$s), 4, IIC_iMAC32,
3829 [(set GPRnopc:$Rd, (add (mul GPRnopc:$Rn, GPRnopc:$Rm), GPRnopc:$Ra))],
3830 (MLA GPRnopc:$Rd, GPRnopc:$Rn, GPRnopc:$Rm, GPRnopc:$Ra, pred:$p, cc_out:$s)>,
3831 Requires<[IsARM, NoV6]>;
3833 def MLS : AMul1I<0b0000011, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm, GPR:$Ra),
3834 IIC_iMAC32, "mls", "\t$Rd, $Rn, $Rm, $Ra",
3835 [(set GPR:$Rd, (sub GPR:$Ra, (mul GPR:$Rn, GPR:$Rm)))]>,
3836 Requires<[IsARM, HasV6T2, UseMulOps]> {
3841 let Inst{19-16} = Rd;
3842 let Inst{15-12} = Ra;
3843 let Inst{11-8} = Rm;
3847 // Extra precision multiplies with low / high results
3848 let hasSideEffects = 0 in {
3849 let isCommutable = 1 in {
3850 def SMULL : AsMul1I64<0b0000110, (outs GPR:$RdLo, GPR:$RdHi),
3851 (ins GPR:$Rn, GPR:$Rm), IIC_iMUL64,
3852 "smull", "\t$RdLo, $RdHi, $Rn, $Rm", []>,
3853 Requires<[IsARM, HasV6]>;
3855 def UMULL : AsMul1I64<0b0000100, (outs GPR:$RdLo, GPR:$RdHi),
3856 (ins GPR:$Rn, GPR:$Rm), IIC_iMUL64,
3857 "umull", "\t$RdLo, $RdHi, $Rn, $Rm", []>,
3858 Requires<[IsARM, HasV6]>;
3860 let Constraints = "@earlyclobber $RdLo,@earlyclobber $RdHi" in {
3861 def SMULLv5 : ARMPseudoExpand<(outs GPR:$RdLo, GPR:$RdHi),
3862 (ins GPR:$Rn, GPR:$Rm, pred:$p, cc_out:$s),
3864 (SMULL GPR:$RdLo, GPR:$RdHi, GPR:$Rn, GPR:$Rm, pred:$p, cc_out:$s)>,
3865 Requires<[IsARM, NoV6]>;
3867 def UMULLv5 : ARMPseudoExpand<(outs GPR:$RdLo, GPR:$RdHi),
3868 (ins GPR:$Rn, GPR:$Rm, pred:$p, cc_out:$s),
3870 (UMULL GPR:$RdLo, GPR:$RdHi, GPR:$Rn, GPR:$Rm, pred:$p, cc_out:$s)>,
3871 Requires<[IsARM, NoV6]>;
3875 // Multiply + accumulate
3876 def SMLAL : AsMla1I64<0b0000111, (outs GPR:$RdLo, GPR:$RdHi),
3877 (ins GPR:$Rn, GPR:$Rm, GPR:$RLo, GPR:$RHi), IIC_iMAC64,
3878 "smlal", "\t$RdLo, $RdHi, $Rn, $Rm", []>,
3879 RegConstraint<"$RLo = $RdLo, $RHi = $RdHi">, Requires<[IsARM, HasV6]>;
3880 def UMLAL : AsMla1I64<0b0000101, (outs GPR:$RdLo, GPR:$RdHi),
3881 (ins GPR:$Rn, GPR:$Rm, GPR:$RLo, GPR:$RHi), IIC_iMAC64,
3882 "umlal", "\t$RdLo, $RdHi, $Rn, $Rm", []>,
3883 RegConstraint<"$RLo = $RdLo, $RHi = $RdHi">, Requires<[IsARM, HasV6]>;
3885 def UMAAL : AMul1I <0b0000010, (outs GPR:$RdLo, GPR:$RdHi),
3886 (ins GPR:$Rn, GPR:$Rm), IIC_iMAC64,
3887 "umaal", "\t$RdLo, $RdHi, $Rn, $Rm", []>,
3888 Requires<[IsARM, HasV6]> {
3893 let Inst{19-16} = RdHi;
3894 let Inst{15-12} = RdLo;
3895 let Inst{11-8} = Rm;
3900 "@earlyclobber $RdLo,@earlyclobber $RdHi,$RLo = $RdLo,$RHi = $RdHi" in {
3901 def SMLALv5 : ARMPseudoExpand<(outs GPR:$RdLo, GPR:$RdHi),
3902 (ins GPR:$Rn, GPR:$Rm, GPR:$RLo, GPR:$RHi, pred:$p, cc_out:$s),
3904 (SMLAL GPR:$RdLo, GPR:$RdHi, GPR:$Rn, GPR:$Rm, GPR:$RLo, GPR:$RHi,
3905 pred:$p, cc_out:$s)>,
3906 Requires<[IsARM, NoV6]>;
3907 def UMLALv5 : ARMPseudoExpand<(outs GPR:$RdLo, GPR:$RdHi),
3908 (ins GPR:$Rn, GPR:$Rm, GPR:$RLo, GPR:$RHi, pred:$p, cc_out:$s),
3910 (UMLAL GPR:$RdLo, GPR:$RdHi, GPR:$Rn, GPR:$Rm, GPR:$RLo, GPR:$RHi,
3911 pred:$p, cc_out:$s)>,
3912 Requires<[IsARM, NoV6]>;
3917 // Most significant word multiply
3918 def SMMUL : AMul2I <0b0111010, 0b0001, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm),
3919 IIC_iMUL32, "smmul", "\t$Rd, $Rn, $Rm",
3920 [(set GPR:$Rd, (mulhs GPR:$Rn, GPR:$Rm))]>,
3921 Requires<[IsARM, HasV6]> {
3922 let Inst{15-12} = 0b1111;
3925 def SMMULR : AMul2I <0b0111010, 0b0011, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm),
3926 IIC_iMUL32, "smmulr", "\t$Rd, $Rn, $Rm", []>,
3927 Requires<[IsARM, HasV6]> {
3928 let Inst{15-12} = 0b1111;
3931 def SMMLA : AMul2Ia <0b0111010, 0b0001, (outs GPR:$Rd),
3932 (ins GPR:$Rn, GPR:$Rm, GPR:$Ra),
3933 IIC_iMAC32, "smmla", "\t$Rd, $Rn, $Rm, $Ra",
3934 [(set GPR:$Rd, (add (mulhs GPR:$Rn, GPR:$Rm), GPR:$Ra))]>,
3935 Requires<[IsARM, HasV6, UseMulOps]>;
3937 def SMMLAR : AMul2Ia <0b0111010, 0b0011, (outs GPR:$Rd),
3938 (ins GPR:$Rn, GPR:$Rm, GPR:$Ra),
3939 IIC_iMAC32, "smmlar", "\t$Rd, $Rn, $Rm, $Ra", []>,
3940 Requires<[IsARM, HasV6]>;
3942 def SMMLS : AMul2Ia <0b0111010, 0b1101, (outs GPR:$Rd),
3943 (ins GPR:$Rn, GPR:$Rm, GPR:$Ra),
3944 IIC_iMAC32, "smmls", "\t$Rd, $Rn, $Rm, $Ra", []>,
3945 Requires<[IsARM, HasV6, UseMulOps]>;
3947 def SMMLSR : AMul2Ia <0b0111010, 0b1111, (outs GPR:$Rd),
3948 (ins GPR:$Rn, GPR:$Rm, GPR:$Ra),
3949 IIC_iMAC32, "smmlsr", "\t$Rd, $Rn, $Rm, $Ra", []>,
3950 Requires<[IsARM, HasV6]>;
3952 multiclass AI_smul<string opc, PatFrag opnode> {
3953 def BB : AMulxyI<0b0001011, 0b00, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm),
3954 IIC_iMUL16, !strconcat(opc, "bb"), "\t$Rd, $Rn, $Rm",
3955 [(set GPR:$Rd, (opnode (sext_inreg GPR:$Rn, i16),
3956 (sext_inreg GPR:$Rm, i16)))]>,
3957 Requires<[IsARM, HasV5TE]>;
3959 def BT : AMulxyI<0b0001011, 0b10, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm),
3960 IIC_iMUL16, !strconcat(opc, "bt"), "\t$Rd, $Rn, $Rm",
3961 [(set GPR:$Rd, (opnode (sext_inreg GPR:$Rn, i16),
3962 (sra GPR:$Rm, (i32 16))))]>,
3963 Requires<[IsARM, HasV5TE]>;
3965 def TB : AMulxyI<0b0001011, 0b01, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm),
3966 IIC_iMUL16, !strconcat(opc, "tb"), "\t$Rd, $Rn, $Rm",
3967 [(set GPR:$Rd, (opnode (sra GPR:$Rn, (i32 16)),
3968 (sext_inreg GPR:$Rm, i16)))]>,
3969 Requires<[IsARM, HasV5TE]>;
3971 def TT : AMulxyI<0b0001011, 0b11, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm),
3972 IIC_iMUL16, !strconcat(opc, "tt"), "\t$Rd, $Rn, $Rm",
3973 [(set GPR:$Rd, (opnode (sra GPR:$Rn, (i32 16)),
3974 (sra GPR:$Rm, (i32 16))))]>,
3975 Requires<[IsARM, HasV5TE]>;
3977 def WB : AMulxyI<0b0001001, 0b01, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm),
3978 IIC_iMUL16, !strconcat(opc, "wb"), "\t$Rd, $Rn, $Rm",
3980 Requires<[IsARM, HasV5TE]>;
3982 def WT : AMulxyI<0b0001001, 0b11, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm),
3983 IIC_iMUL16, !strconcat(opc, "wt"), "\t$Rd, $Rn, $Rm",
3985 Requires<[IsARM, HasV5TE]>;
3989 multiclass AI_smla<string opc, PatFrag opnode> {
3990 let DecoderMethod = "DecodeSMLAInstruction" in {
3991 def BB : AMulxyIa<0b0001000, 0b00, (outs GPRnopc:$Rd),
3992 (ins GPRnopc:$Rn, GPRnopc:$Rm, GPR:$Ra),
3993 IIC_iMAC16, !strconcat(opc, "bb"), "\t$Rd, $Rn, $Rm, $Ra",
3994 [(set GPRnopc:$Rd, (add GPR:$Ra,
3995 (opnode (sext_inreg GPRnopc:$Rn, i16),
3996 (sext_inreg GPRnopc:$Rm, i16))))]>,
3997 Requires<[IsARM, HasV5TE, UseMulOps]>;
3999 def BT : AMulxyIa<0b0001000, 0b10, (outs GPRnopc:$Rd),
4000 (ins GPRnopc:$Rn, GPRnopc:$Rm, GPR:$Ra),
4001 IIC_iMAC16, !strconcat(opc, "bt"), "\t$Rd, $Rn, $Rm, $Ra",
4003 (add GPR:$Ra, (opnode (sext_inreg GPRnopc:$Rn, i16),
4004 (sra GPRnopc:$Rm, (i32 16)))))]>,
4005 Requires<[IsARM, HasV5TE, UseMulOps]>;
4007 def TB : AMulxyIa<0b0001000, 0b01, (outs GPRnopc:$Rd),
4008 (ins GPRnopc:$Rn, GPRnopc:$Rm, GPR:$Ra),
4009 IIC_iMAC16, !strconcat(opc, "tb"), "\t$Rd, $Rn, $Rm, $Ra",
4011 (add GPR:$Ra, (opnode (sra GPRnopc:$Rn, (i32 16)),
4012 (sext_inreg GPRnopc:$Rm, i16))))]>,
4013 Requires<[IsARM, HasV5TE, UseMulOps]>;
4015 def TT : AMulxyIa<0b0001000, 0b11, (outs GPRnopc:$Rd),
4016 (ins GPRnopc:$Rn, GPRnopc:$Rm, GPR:$Ra),
4017 IIC_iMAC16, !strconcat(opc, "tt"), "\t$Rd, $Rn, $Rm, $Ra",
4019 (add GPR:$Ra, (opnode (sra GPRnopc:$Rn, (i32 16)),
4020 (sra GPRnopc:$Rm, (i32 16)))))]>,
4021 Requires<[IsARM, HasV5TE, UseMulOps]>;
4023 def WB : AMulxyIa<0b0001001, 0b00, (outs GPRnopc:$Rd),
4024 (ins GPRnopc:$Rn, GPRnopc:$Rm, GPR:$Ra),
4025 IIC_iMAC16, !strconcat(opc, "wb"), "\t$Rd, $Rn, $Rm, $Ra",
4027 Requires<[IsARM, HasV5TE, UseMulOps]>;
4029 def WT : AMulxyIa<0b0001001, 0b10, (outs GPRnopc:$Rd),
4030 (ins GPRnopc:$Rn, GPRnopc:$Rm, GPR:$Ra),
4031 IIC_iMAC16, !strconcat(opc, "wt"), "\t$Rd, $Rn, $Rm, $Ra",
4033 Requires<[IsARM, HasV5TE, UseMulOps]>;
4037 defm SMUL : AI_smul<"smul", BinOpFrag<(mul node:$LHS, node:$RHS)>>;
4038 defm SMLA : AI_smla<"smla", BinOpFrag<(mul node:$LHS, node:$RHS)>>;
4040 // Halfword multiply accumulate long: SMLAL<x><y>.
4041 def SMLALBB : AMulxyI64<0b0001010, 0b00, (outs GPRnopc:$RdLo, GPRnopc:$RdHi),
4042 (ins GPRnopc:$Rn, GPRnopc:$Rm),
4043 IIC_iMAC64, "smlalbb", "\t$RdLo, $RdHi, $Rn, $Rm", []>,
4044 Requires<[IsARM, HasV5TE]>;
4046 def SMLALBT : AMulxyI64<0b0001010, 0b10, (outs GPRnopc:$RdLo, GPRnopc:$RdHi),
4047 (ins GPRnopc:$Rn, GPRnopc:$Rm),
4048 IIC_iMAC64, "smlalbt", "\t$RdLo, $RdHi, $Rn, $Rm", []>,
4049 Requires<[IsARM, HasV5TE]>;
4051 def SMLALTB : AMulxyI64<0b0001010, 0b01, (outs GPRnopc:$RdLo, GPRnopc:$RdHi),
4052 (ins GPRnopc:$Rn, GPRnopc:$Rm),
4053 IIC_iMAC64, "smlaltb", "\t$RdLo, $RdHi, $Rn, $Rm", []>,
4054 Requires<[IsARM, HasV5TE]>;
4056 def SMLALTT : AMulxyI64<0b0001010, 0b11, (outs GPRnopc:$RdLo, GPRnopc:$RdHi),
4057 (ins GPRnopc:$Rn, GPRnopc:$Rm),
4058 IIC_iMAC64, "smlaltt", "\t$RdLo, $RdHi, $Rn, $Rm", []>,
4059 Requires<[IsARM, HasV5TE]>;
4061 // Helper class for AI_smld.
4062 class AMulDualIbase<bit long, bit sub, bit swap, dag oops, dag iops,
4063 InstrItinClass itin, string opc, string asm>
4064 : AI<oops, iops, MulFrm, itin, opc, asm, []>, Requires<[IsARM, HasV6]> {
4067 let Inst{27-23} = 0b01110;
4068 let Inst{22} = long;
4069 let Inst{21-20} = 0b00;
4070 let Inst{11-8} = Rm;
4077 class AMulDualI<bit long, bit sub, bit swap, dag oops, dag iops,
4078 InstrItinClass itin, string opc, string asm>
4079 : AMulDualIbase<long, sub, swap, oops, iops, itin, opc, asm> {
4081 let Inst{15-12} = 0b1111;
4082 let Inst{19-16} = Rd;
4084 class AMulDualIa<bit long, bit sub, bit swap, dag oops, dag iops,
4085 InstrItinClass itin, string opc, string asm>
4086 : AMulDualIbase<long, sub, swap, oops, iops, itin, opc, asm> {
4089 let Inst{19-16} = Rd;
4090 let Inst{15-12} = Ra;
4092 class AMulDualI64<bit long, bit sub, bit swap, dag oops, dag iops,
4093 InstrItinClass itin, string opc, string asm>
4094 : AMulDualIbase<long, sub, swap, oops, iops, itin, opc, asm> {
4097 let Inst{19-16} = RdHi;
4098 let Inst{15-12} = RdLo;
4101 multiclass AI_smld<bit sub, string opc> {
4103 def D : AMulDualIa<0, sub, 0, (outs GPRnopc:$Rd),
4104 (ins GPRnopc:$Rn, GPRnopc:$Rm, GPR:$Ra),
4105 NoItinerary, !strconcat(opc, "d"), "\t$Rd, $Rn, $Rm, $Ra">;
4107 def DX: AMulDualIa<0, sub, 1, (outs GPRnopc:$Rd),
4108 (ins GPRnopc:$Rn, GPRnopc:$Rm, GPR:$Ra),
4109 NoItinerary, !strconcat(opc, "dx"), "\t$Rd, $Rn, $Rm, $Ra">;
4111 def LD: AMulDualI64<1, sub, 0, (outs GPRnopc:$RdLo, GPRnopc:$RdHi),
4112 (ins GPRnopc:$Rn, GPRnopc:$Rm), NoItinerary,
4113 !strconcat(opc, "ld"), "\t$RdLo, $RdHi, $Rn, $Rm">;
4115 def LDX : AMulDualI64<1, sub, 1, (outs GPRnopc:$RdLo, GPRnopc:$RdHi),
4116 (ins GPRnopc:$Rn, GPRnopc:$Rm), NoItinerary,
4117 !strconcat(opc, "ldx"),"\t$RdLo, $RdHi, $Rn, $Rm">;
4121 defm SMLA : AI_smld<0, "smla">;
4122 defm SMLS : AI_smld<1, "smls">;
4124 multiclass AI_sdml<bit sub, string opc> {
4126 def D:AMulDualI<0, sub, 0, (outs GPRnopc:$Rd), (ins GPRnopc:$Rn, GPRnopc:$Rm),
4127 NoItinerary, !strconcat(opc, "d"), "\t$Rd, $Rn, $Rm">;
4128 def DX:AMulDualI<0, sub, 1, (outs GPRnopc:$Rd),(ins GPRnopc:$Rn, GPRnopc:$Rm),
4129 NoItinerary, !strconcat(opc, "dx"), "\t$Rd, $Rn, $Rm">;
4132 defm SMUA : AI_sdml<0, "smua">;
4133 defm SMUS : AI_sdml<1, "smus">;
4135 //===----------------------------------------------------------------------===//
4136 // Division Instructions (ARMv7-A with virtualization extension)
4138 def SDIV : ADivA1I<0b001, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm), IIC_iDIV,
4139 "sdiv", "\t$Rd, $Rn, $Rm",
4140 [(set GPR:$Rd, (sdiv GPR:$Rn, GPR:$Rm))]>,
4141 Requires<[IsARM, HasDivideInARM]>;
4143 def UDIV : ADivA1I<0b011, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm), IIC_iDIV,
4144 "udiv", "\t$Rd, $Rn, $Rm",
4145 [(set GPR:$Rd, (udiv GPR:$Rn, GPR:$Rm))]>,
4146 Requires<[IsARM, HasDivideInARM]>;
4148 //===----------------------------------------------------------------------===//
4149 // Misc. Arithmetic Instructions.
4152 def CLZ : AMiscA1I<0b00010110, 0b0001, (outs GPR:$Rd), (ins GPR:$Rm),
4153 IIC_iUNAr, "clz", "\t$Rd, $Rm",
4154 [(set GPR:$Rd, (ctlz GPR:$Rm))]>, Requires<[IsARM, HasV5T]>,
4157 def RBIT : AMiscA1I<0b01101111, 0b0011, (outs GPR:$Rd), (ins GPR:$Rm),
4158 IIC_iUNAr, "rbit", "\t$Rd, $Rm",
4159 [(set GPR:$Rd, (ARMrbit GPR:$Rm))]>,
4160 Requires<[IsARM, HasV6T2]>,
4163 def REV : AMiscA1I<0b01101011, 0b0011, (outs GPR:$Rd), (ins GPR:$Rm),
4164 IIC_iUNAr, "rev", "\t$Rd, $Rm",
4165 [(set GPR:$Rd, (bswap GPR:$Rm))]>, Requires<[IsARM, HasV6]>,
4168 let AddedComplexity = 5 in
4169 def REV16 : AMiscA1I<0b01101011, 0b1011, (outs GPR:$Rd), (ins GPR:$Rm),
4170 IIC_iUNAr, "rev16", "\t$Rd, $Rm",
4171 [(set GPR:$Rd, (rotr (bswap GPR:$Rm), (i32 16)))]>,
4172 Requires<[IsARM, HasV6]>,
4175 def : ARMV6Pat<(srl (bswap (extloadi16 addrmode3:$addr)), (i32 16)),
4176 (REV16 (LDRH addrmode3:$addr))>;
4177 def : ARMV6Pat<(truncstorei16 (srl (bswap GPR:$Rn), (i32 16)), addrmode3:$addr),
4178 (STRH (REV16 GPR:$Rn), addrmode3:$addr)>;
4180 let AddedComplexity = 5 in
4181 def REVSH : AMiscA1I<0b01101111, 0b1011, (outs GPR:$Rd), (ins GPR:$Rm),
4182 IIC_iUNAr, "revsh", "\t$Rd, $Rm",
4183 [(set GPR:$Rd, (sra (bswap GPR:$Rm), (i32 16)))]>,
4184 Requires<[IsARM, HasV6]>,
4187 def : ARMV6Pat<(or (sra (shl GPR:$Rm, (i32 24)), (i32 16)),
4188 (and (srl GPR:$Rm, (i32 8)), 0xFF)),
4191 def PKHBT : APKHI<0b01101000, 0, (outs GPRnopc:$Rd),
4192 (ins GPRnopc:$Rn, GPRnopc:$Rm, pkh_lsl_amt:$sh),
4193 IIC_iALUsi, "pkhbt", "\t$Rd, $Rn, $Rm$sh",
4194 [(set GPRnopc:$Rd, (or (and GPRnopc:$Rn, 0xFFFF),
4195 (and (shl GPRnopc:$Rm, pkh_lsl_amt:$sh),
4197 Requires<[IsARM, HasV6]>,
4198 Sched<[WriteALUsi, ReadALU]>;
4200 // Alternate cases for PKHBT where identities eliminate some nodes.
4201 def : ARMV6Pat<(or (and GPRnopc:$Rn, 0xFFFF), (and GPRnopc:$Rm, 0xFFFF0000)),
4202 (PKHBT GPRnopc:$Rn, GPRnopc:$Rm, 0)>;
4203 def : ARMV6Pat<(or (and GPRnopc:$Rn, 0xFFFF), (shl GPRnopc:$Rm, imm16_31:$sh)),
4204 (PKHBT GPRnopc:$Rn, GPRnopc:$Rm, imm16_31:$sh)>;
4206 // Note: Shifts of 1-15 bits will be transformed to srl instead of sra and
4207 // will match the pattern below.
4208 def PKHTB : APKHI<0b01101000, 1, (outs GPRnopc:$Rd),
4209 (ins GPRnopc:$Rn, GPRnopc:$Rm, pkh_asr_amt:$sh),
4210 IIC_iBITsi, "pkhtb", "\t$Rd, $Rn, $Rm$sh",
4211 [(set GPRnopc:$Rd, (or (and GPRnopc:$Rn, 0xFFFF0000),
4212 (and (sra GPRnopc:$Rm, pkh_asr_amt:$sh),
4214 Requires<[IsARM, HasV6]>,
4215 Sched<[WriteALUsi, ReadALU]>;
4217 // Alternate cases for PKHTB where identities eliminate some nodes. Note that
4218 // a shift amount of 0 is *not legal* here, it is PKHBT instead.
4219 // We also can not replace a srl (17..31) by an arithmetic shift we would use in
4220 // pkhtb src1, src2, asr (17..31).
4221 def : ARMV6Pat<(or (and GPRnopc:$src1, 0xFFFF0000),
4222 (srl GPRnopc:$src2, imm16:$sh)),
4223 (PKHTB GPRnopc:$src1, GPRnopc:$src2, imm16:$sh)>;
4224 def : ARMV6Pat<(or (and GPRnopc:$src1, 0xFFFF0000),
4225 (sra GPRnopc:$src2, imm16_31:$sh)),
4226 (PKHTB GPRnopc:$src1, GPRnopc:$src2, imm16_31:$sh)>;
4227 def : ARMV6Pat<(or (and GPRnopc:$src1, 0xFFFF0000),
4228 (and (srl GPRnopc:$src2, imm1_15:$sh), 0xFFFF)),
4229 (PKHTB GPRnopc:$src1, GPRnopc:$src2, imm1_15:$sh)>;
4231 //===----------------------------------------------------------------------===//
4235 // + CRC32{B,H,W} 0x04C11DB7
4236 // + CRC32C{B,H,W} 0x1EDC6F41
4239 class AI_crc32<bit C, bits<2> sz, string suffix, SDPatternOperator builtin>
4240 : AInoP<(outs GPRnopc:$Rd), (ins GPRnopc:$Rn, GPRnopc:$Rm), MiscFrm, NoItinerary,
4241 !strconcat("crc32", suffix), "\t$Rd, $Rn, $Rm",
4242 [(set GPRnopc:$Rd, (builtin GPRnopc:$Rn, GPRnopc:$Rm))]>,
4243 Requires<[IsARM, HasV8, HasCRC]> {
4248 let Inst{31-28} = 0b1110;
4249 let Inst{27-23} = 0b00010;
4250 let Inst{22-21} = sz;
4252 let Inst{19-16} = Rn;
4253 let Inst{15-12} = Rd;
4254 let Inst{11-10} = 0b00;
4257 let Inst{7-4} = 0b0100;
4260 let Unpredictable{11-8} = 0b1101;
4263 def CRC32B : AI_crc32<0, 0b00, "b", int_arm_crc32b>;
4264 def CRC32CB : AI_crc32<1, 0b00, "cb", int_arm_crc32cb>;
4265 def CRC32H : AI_crc32<0, 0b01, "h", int_arm_crc32h>;
4266 def CRC32CH : AI_crc32<1, 0b01, "ch", int_arm_crc32ch>;
4267 def CRC32W : AI_crc32<0, 0b10, "w", int_arm_crc32w>;
4268 def CRC32CW : AI_crc32<1, 0b10, "cw", int_arm_crc32cw>;
4270 //===----------------------------------------------------------------------===//
4271 // ARMv8.1a Privilege Access Never extension
4275 def SETPAN : AInoP<(outs), (ins imm0_1:$imm), MiscFrm, NoItinerary, "setpan",
4276 "\t$imm", []>, Requires<[IsARM, HasV8, HasV8_1a]> {
4279 let Inst{31-28} = 0b1111;
4280 let Inst{27-20} = 0b00010001;
4281 let Inst{19-16} = 0b0000;
4282 let Inst{15-10} = 0b000000;
4285 let Inst{7-4} = 0b0000;
4286 let Inst{3-0} = 0b0000;
4288 let Unpredictable{19-16} = 0b1111;
4289 let Unpredictable{15-10} = 0b111111;
4290 let Unpredictable{8} = 0b1;
4291 let Unpredictable{3-0} = 0b1111;
4294 //===----------------------------------------------------------------------===//
4295 // Comparison Instructions...
4298 defm CMP : AI1_cmp_irs<0b1010, "cmp",
4299 IIC_iCMPi, IIC_iCMPr, IIC_iCMPsr,
4300 BinOpFrag<(ARMcmp node:$LHS, node:$RHS)>>;
4302 // ARMcmpZ can re-use the above instruction definitions.
4303 def : ARMPat<(ARMcmpZ GPR:$src, mod_imm:$imm),
4304 (CMPri GPR:$src, mod_imm:$imm)>;
4305 def : ARMPat<(ARMcmpZ GPR:$src, GPR:$rhs),
4306 (CMPrr GPR:$src, GPR:$rhs)>;
4307 def : ARMPat<(ARMcmpZ GPR:$src, so_reg_imm:$rhs),
4308 (CMPrsi GPR:$src, so_reg_imm:$rhs)>;
4309 def : ARMPat<(ARMcmpZ GPR:$src, so_reg_reg:$rhs),
4310 (CMPrsr GPR:$src, so_reg_reg:$rhs)>;
4312 // CMN register-integer
4313 let isCompare = 1, Defs = [CPSR] in {
4314 def CMNri : AI1<0b1011, (outs), (ins GPR:$Rn, mod_imm:$imm), DPFrm, IIC_iCMPi,
4315 "cmn", "\t$Rn, $imm",
4316 [(ARMcmn GPR:$Rn, mod_imm:$imm)]>,
4317 Sched<[WriteCMP, ReadALU]> {
4322 let Inst{19-16} = Rn;
4323 let Inst{15-12} = 0b0000;
4324 let Inst{11-0} = imm;
4326 let Unpredictable{15-12} = 0b1111;
4329 // CMN register-register/shift
4330 def CMNzrr : AI1<0b1011, (outs), (ins GPR:$Rn, GPR:$Rm), DPFrm, IIC_iCMPr,
4331 "cmn", "\t$Rn, $Rm",
4332 [(BinOpFrag<(ARMcmpZ node:$LHS,(ineg node:$RHS))>
4333 GPR:$Rn, GPR:$Rm)]>, Sched<[WriteCMP, ReadALU, ReadALU]> {
4336 let isCommutable = 1;
4339 let Inst{19-16} = Rn;
4340 let Inst{15-12} = 0b0000;
4341 let Inst{11-4} = 0b00000000;
4344 let Unpredictable{15-12} = 0b1111;
4347 def CMNzrsi : AI1<0b1011, (outs),
4348 (ins GPR:$Rn, so_reg_imm:$shift), DPSoRegImmFrm, IIC_iCMPsr,
4349 "cmn", "\t$Rn, $shift",
4350 [(BinOpFrag<(ARMcmpZ node:$LHS,(ineg node:$RHS))>
4351 GPR:$Rn, so_reg_imm:$shift)]>,
4352 Sched<[WriteCMPsi, ReadALU]> {
4357 let Inst{19-16} = Rn;
4358 let Inst{15-12} = 0b0000;
4359 let Inst{11-5} = shift{11-5};
4361 let Inst{3-0} = shift{3-0};
4363 let Unpredictable{15-12} = 0b1111;
4366 def CMNzrsr : AI1<0b1011, (outs),
4367 (ins GPRnopc:$Rn, so_reg_reg:$shift), DPSoRegRegFrm, IIC_iCMPsr,
4368 "cmn", "\t$Rn, $shift",
4369 [(BinOpFrag<(ARMcmpZ node:$LHS,(ineg node:$RHS))>
4370 GPRnopc:$Rn, so_reg_reg:$shift)]>,
4371 Sched<[WriteCMPsr, ReadALU]> {
4376 let Inst{19-16} = Rn;
4377 let Inst{15-12} = 0b0000;
4378 let Inst{11-8} = shift{11-8};
4380 let Inst{6-5} = shift{6-5};
4382 let Inst{3-0} = shift{3-0};
4384 let Unpredictable{15-12} = 0b1111;
4389 def : ARMPat<(ARMcmp GPR:$src, mod_imm_neg:$imm),
4390 (CMNri GPR:$src, mod_imm_neg:$imm)>;
4392 def : ARMPat<(ARMcmpZ GPR:$src, mod_imm_neg:$imm),
4393 (CMNri GPR:$src, mod_imm_neg:$imm)>;
4395 // Note that TST/TEQ don't set all the same flags that CMP does!
4396 defm TST : AI1_cmp_irs<0b1000, "tst",
4397 IIC_iTSTi, IIC_iTSTr, IIC_iTSTsr,
4398 BinOpFrag<(ARMcmpZ (and_su node:$LHS, node:$RHS), 0)>, 1,
4399 "DecodeTSTInstruction">;
4400 defm TEQ : AI1_cmp_irs<0b1001, "teq",
4401 IIC_iTSTi, IIC_iTSTr, IIC_iTSTsr,
4402 BinOpFrag<(ARMcmpZ (xor_su node:$LHS, node:$RHS), 0)>, 1>;
4404 // Pseudo i64 compares for some floating point compares.
4405 let usesCustomInserter = 1, isBranch = 1, isTerminator = 1,
4407 def BCCi64 : PseudoInst<(outs),
4408 (ins i32imm:$cc, GPR:$lhs1, GPR:$lhs2, GPR:$rhs1, GPR:$rhs2, brtarget:$dst),
4410 [(ARMBcci64 imm:$cc, GPR:$lhs1, GPR:$lhs2, GPR:$rhs1, GPR:$rhs2, bb:$dst)]>,
4413 def BCCZi64 : PseudoInst<(outs),
4414 (ins i32imm:$cc, GPR:$lhs1, GPR:$lhs2, brtarget:$dst), IIC_Br,
4415 [(ARMBcci64 imm:$cc, GPR:$lhs1, GPR:$lhs2, 0, 0, bb:$dst)]>,
4417 } // usesCustomInserter
4420 // Conditional moves
4421 let hasSideEffects = 0 in {
4423 let isCommutable = 1, isSelect = 1 in
4424 def MOVCCr : ARMPseudoInst<(outs GPR:$Rd),
4425 (ins GPR:$false, GPR:$Rm, cmovpred:$p),
4427 [(set GPR:$Rd, (ARMcmov GPR:$false, GPR:$Rm,
4429 RegConstraint<"$false = $Rd">, Sched<[WriteALU]>;
4431 def MOVCCsi : ARMPseudoInst<(outs GPR:$Rd),
4432 (ins GPR:$false, so_reg_imm:$shift, cmovpred:$p),
4435 (ARMcmov GPR:$false, so_reg_imm:$shift,
4437 RegConstraint<"$false = $Rd">, Sched<[WriteALU]>;
4438 def MOVCCsr : ARMPseudoInst<(outs GPR:$Rd),
4439 (ins GPR:$false, so_reg_reg:$shift, cmovpred:$p),
4441 [(set GPR:$Rd, (ARMcmov GPR:$false, so_reg_reg:$shift,
4443 RegConstraint<"$false = $Rd">, Sched<[WriteALU]>;
4446 let isMoveImm = 1 in
4448 : ARMPseudoInst<(outs GPR:$Rd),
4449 (ins GPR:$false, imm0_65535_expr:$imm, cmovpred:$p),
4451 [(set GPR:$Rd, (ARMcmov GPR:$false, imm0_65535:$imm,
4453 RegConstraint<"$false = $Rd">, Requires<[IsARM, HasV6T2]>,
4456 let isMoveImm = 1 in
4457 def MOVCCi : ARMPseudoInst<(outs GPR:$Rd),
4458 (ins GPR:$false, mod_imm:$imm, cmovpred:$p),
4460 [(set GPR:$Rd, (ARMcmov GPR:$false, mod_imm:$imm,
4462 RegConstraint<"$false = $Rd">, Sched<[WriteALU]>;
4464 // Two instruction predicate mov immediate.
4465 let isMoveImm = 1 in
4467 : ARMPseudoInst<(outs GPR:$Rd),
4468 (ins GPR:$false, i32imm:$src, cmovpred:$p),
4470 [(set GPR:$Rd, (ARMcmov GPR:$false, imm:$src,
4472 RegConstraint<"$false = $Rd">, Requires<[IsARM, HasV6T2]>;
4474 let isMoveImm = 1 in
4475 def MVNCCi : ARMPseudoInst<(outs GPR:$Rd),
4476 (ins GPR:$false, mod_imm:$imm, cmovpred:$p),
4478 [(set GPR:$Rd, (ARMcmov GPR:$false, mod_imm_not:$imm,
4480 RegConstraint<"$false = $Rd">, Sched<[WriteALU]>;
4485 //===----------------------------------------------------------------------===//
4486 // Atomic operations intrinsics
4489 def MemBarrierOptOperand : AsmOperandClass {
4490 let Name = "MemBarrierOpt";
4491 let ParserMethod = "parseMemBarrierOptOperand";
4493 def memb_opt : Operand<i32> {
4494 let PrintMethod = "printMemBOption";
4495 let ParserMatchClass = MemBarrierOptOperand;
4496 let DecoderMethod = "DecodeMemBarrierOption";
4499 def InstSyncBarrierOptOperand : AsmOperandClass {
4500 let Name = "InstSyncBarrierOpt";
4501 let ParserMethod = "parseInstSyncBarrierOptOperand";
4503 def instsyncb_opt : Operand<i32> {
4504 let PrintMethod = "printInstSyncBOption";
4505 let ParserMatchClass = InstSyncBarrierOptOperand;
4506 let DecoderMethod = "DecodeInstSyncBarrierOption";
4509 // Memory barriers protect the atomic sequences
4510 let hasSideEffects = 1 in {
4511 def DMB : AInoP<(outs), (ins memb_opt:$opt), MiscFrm, NoItinerary,
4512 "dmb", "\t$opt", [(int_arm_dmb (i32 imm0_15:$opt))]>,
4513 Requires<[IsARM, HasDB]> {
4515 let Inst{31-4} = 0xf57ff05;
4516 let Inst{3-0} = opt;
4519 def DSB : AInoP<(outs), (ins memb_opt:$opt), MiscFrm, NoItinerary,
4520 "dsb", "\t$opt", [(int_arm_dsb (i32 imm0_15:$opt))]>,
4521 Requires<[IsARM, HasDB]> {
4523 let Inst{31-4} = 0xf57ff04;
4524 let Inst{3-0} = opt;
4527 // ISB has only full system option
4528 def ISB : AInoP<(outs), (ins instsyncb_opt:$opt), MiscFrm, NoItinerary,
4529 "isb", "\t$opt", [(int_arm_isb (i32 imm0_15:$opt))]>,
4530 Requires<[IsARM, HasDB]> {
4532 let Inst{31-4} = 0xf57ff06;
4533 let Inst{3-0} = opt;
4537 let usesCustomInserter = 1, Defs = [CPSR] in {
4539 // Pseudo instruction that combines movs + predicated rsbmi
4540 // to implement integer ABS
4541 def ABS : ARMPseudoInst<(outs GPR:$dst), (ins GPR:$src), 8, NoItinerary, []>;
4544 let usesCustomInserter = 1 in {
4545 def COPY_STRUCT_BYVAL_I32 : PseudoInst<
4546 (outs), (ins GPR:$dst, GPR:$src, i32imm:$size, i32imm:$alignment),
4548 [(ARMcopystructbyval GPR:$dst, GPR:$src, imm:$size, imm:$alignment)]>;
4551 def ldrex_1 : PatFrag<(ops node:$ptr), (int_arm_ldrex node:$ptr), [{
4552 return cast<MemIntrinsicSDNode>(N)->getMemoryVT() == MVT::i8;
4555 def ldrex_2 : PatFrag<(ops node:$ptr), (int_arm_ldrex node:$ptr), [{
4556 return cast<MemIntrinsicSDNode>(N)->getMemoryVT() == MVT::i16;
4559 def ldrex_4 : PatFrag<(ops node:$ptr), (int_arm_ldrex node:$ptr), [{
4560 return cast<MemIntrinsicSDNode>(N)->getMemoryVT() == MVT::i32;
4563 def strex_1 : PatFrag<(ops node:$val, node:$ptr),
4564 (int_arm_strex node:$val, node:$ptr), [{
4565 return cast<MemIntrinsicSDNode>(N)->getMemoryVT() == MVT::i8;
4568 def strex_2 : PatFrag<(ops node:$val, node:$ptr),
4569 (int_arm_strex node:$val, node:$ptr), [{
4570 return cast<MemIntrinsicSDNode>(N)->getMemoryVT() == MVT::i16;
4573 def strex_4 : PatFrag<(ops node:$val, node:$ptr),
4574 (int_arm_strex node:$val, node:$ptr), [{
4575 return cast<MemIntrinsicSDNode>(N)->getMemoryVT() == MVT::i32;
4578 def ldaex_1 : PatFrag<(ops node:$ptr), (int_arm_ldaex node:$ptr), [{
4579 return cast<MemIntrinsicSDNode>(N)->getMemoryVT() == MVT::i8;
4582 def ldaex_2 : PatFrag<(ops node:$ptr), (int_arm_ldaex node:$ptr), [{
4583 return cast<MemIntrinsicSDNode>(N)->getMemoryVT() == MVT::i16;
4586 def ldaex_4 : PatFrag<(ops node:$ptr), (int_arm_ldaex node:$ptr), [{
4587 return cast<MemIntrinsicSDNode>(N)->getMemoryVT() == MVT::i32;
4590 def stlex_1 : PatFrag<(ops node:$val, node:$ptr),
4591 (int_arm_stlex node:$val, node:$ptr), [{
4592 return cast<MemIntrinsicSDNode>(N)->getMemoryVT() == MVT::i8;
4595 def stlex_2 : PatFrag<(ops node:$val, node:$ptr),
4596 (int_arm_stlex node:$val, node:$ptr), [{
4597 return cast<MemIntrinsicSDNode>(N)->getMemoryVT() == MVT::i16;
4600 def stlex_4 : PatFrag<(ops node:$val, node:$ptr),
4601 (int_arm_stlex node:$val, node:$ptr), [{
4602 return cast<MemIntrinsicSDNode>(N)->getMemoryVT() == MVT::i32;
4605 let mayLoad = 1 in {
4606 def LDREXB : AIldrex<0b10, (outs GPR:$Rt), (ins addr_offset_none:$addr),
4607 NoItinerary, "ldrexb", "\t$Rt, $addr",
4608 [(set GPR:$Rt, (ldrex_1 addr_offset_none:$addr))]>;
4609 def LDREXH : AIldrex<0b11, (outs GPR:$Rt), (ins addr_offset_none:$addr),
4610 NoItinerary, "ldrexh", "\t$Rt, $addr",
4611 [(set GPR:$Rt, (ldrex_2 addr_offset_none:$addr))]>;
4612 def LDREX : AIldrex<0b00, (outs GPR:$Rt), (ins addr_offset_none:$addr),
4613 NoItinerary, "ldrex", "\t$Rt, $addr",
4614 [(set GPR:$Rt, (ldrex_4 addr_offset_none:$addr))]>;
4615 let hasExtraDefRegAllocReq = 1 in
4616 def LDREXD : AIldrex<0b01, (outs GPRPairOp:$Rt),(ins addr_offset_none:$addr),
4617 NoItinerary, "ldrexd", "\t$Rt, $addr", []> {
4618 let DecoderMethod = "DecodeDoubleRegLoad";
4621 def LDAEXB : AIldaex<0b10, (outs GPR:$Rt), (ins addr_offset_none:$addr),
4622 NoItinerary, "ldaexb", "\t$Rt, $addr",
4623 [(set GPR:$Rt, (ldaex_1 addr_offset_none:$addr))]>;
4624 def LDAEXH : AIldaex<0b11, (outs GPR:$Rt), (ins addr_offset_none:$addr),
4625 NoItinerary, "ldaexh", "\t$Rt, $addr",
4626 [(set GPR:$Rt, (ldaex_2 addr_offset_none:$addr))]>;
4627 def LDAEX : AIldaex<0b00, (outs GPR:$Rt), (ins addr_offset_none:$addr),
4628 NoItinerary, "ldaex", "\t$Rt, $addr",
4629 [(set GPR:$Rt, (ldaex_4 addr_offset_none:$addr))]>;
4630 let hasExtraDefRegAllocReq = 1 in
4631 def LDAEXD : AIldaex<0b01, (outs GPRPairOp:$Rt),(ins addr_offset_none:$addr),
4632 NoItinerary, "ldaexd", "\t$Rt, $addr", []> {
4633 let DecoderMethod = "DecodeDoubleRegLoad";
4637 let mayStore = 1, Constraints = "@earlyclobber $Rd" in {
4638 def STREXB: AIstrex<0b10, (outs GPR:$Rd), (ins GPR:$Rt, addr_offset_none:$addr),
4639 NoItinerary, "strexb", "\t$Rd, $Rt, $addr",
4640 [(set GPR:$Rd, (strex_1 GPR:$Rt,
4641 addr_offset_none:$addr))]>;
4642 def STREXH: AIstrex<0b11, (outs GPR:$Rd), (ins GPR:$Rt, addr_offset_none:$addr),
4643 NoItinerary, "strexh", "\t$Rd, $Rt, $addr",
4644 [(set GPR:$Rd, (strex_2 GPR:$Rt,
4645 addr_offset_none:$addr))]>;
4646 def STREX : AIstrex<0b00, (outs GPR:$Rd), (ins GPR:$Rt, addr_offset_none:$addr),
4647 NoItinerary, "strex", "\t$Rd, $Rt, $addr",
4648 [(set GPR:$Rd, (strex_4 GPR:$Rt,
4649 addr_offset_none:$addr))]>;
4650 let hasExtraSrcRegAllocReq = 1 in
4651 def STREXD : AIstrex<0b01, (outs GPR:$Rd),
4652 (ins GPRPairOp:$Rt, addr_offset_none:$addr),
4653 NoItinerary, "strexd", "\t$Rd, $Rt, $addr", []> {
4654 let DecoderMethod = "DecodeDoubleRegStore";
4656 def STLEXB: AIstlex<0b10, (outs GPR:$Rd), (ins GPR:$Rt, addr_offset_none:$addr),
4657 NoItinerary, "stlexb", "\t$Rd, $Rt, $addr",
4659 (stlex_1 GPR:$Rt, addr_offset_none:$addr))]>;
4660 def STLEXH: AIstlex<0b11, (outs GPR:$Rd), (ins GPR:$Rt, addr_offset_none:$addr),
4661 NoItinerary, "stlexh", "\t$Rd, $Rt, $addr",
4663 (stlex_2 GPR:$Rt, addr_offset_none:$addr))]>;
4664 def STLEX : AIstlex<0b00, (outs GPR:$Rd), (ins GPR:$Rt, addr_offset_none:$addr),
4665 NoItinerary, "stlex", "\t$Rd, $Rt, $addr",
4667 (stlex_4 GPR:$Rt, addr_offset_none:$addr))]>;
4668 let hasExtraSrcRegAllocReq = 1 in
4669 def STLEXD : AIstlex<0b01, (outs GPR:$Rd),
4670 (ins GPRPairOp:$Rt, addr_offset_none:$addr),
4671 NoItinerary, "stlexd", "\t$Rd, $Rt, $addr", []> {
4672 let DecoderMethod = "DecodeDoubleRegStore";
4676 def CLREX : AXI<(outs), (ins), MiscFrm, NoItinerary, "clrex",
4678 Requires<[IsARM, HasV7]> {
4679 let Inst{31-0} = 0b11110101011111111111000000011111;
4682 def : ARMPat<(strex_1 (and GPR:$Rt, 0xff), addr_offset_none:$addr),
4683 (STREXB GPR:$Rt, addr_offset_none:$addr)>;
4684 def : ARMPat<(strex_2 (and GPR:$Rt, 0xffff), addr_offset_none:$addr),
4685 (STREXH GPR:$Rt, addr_offset_none:$addr)>;
4687 def : ARMPat<(stlex_1 (and GPR:$Rt, 0xff), addr_offset_none:$addr),
4688 (STLEXB GPR:$Rt, addr_offset_none:$addr)>;
4689 def : ARMPat<(stlex_2 (and GPR:$Rt, 0xffff), addr_offset_none:$addr),
4690 (STLEXH GPR:$Rt, addr_offset_none:$addr)>;
4692 class acquiring_load<PatFrag base>
4693 : PatFrag<(ops node:$ptr), (base node:$ptr), [{
4694 AtomicOrdering Ordering = cast<AtomicSDNode>(N)->getOrdering();
4695 return isAtLeastAcquire(Ordering);
4698 def atomic_load_acquire_8 : acquiring_load<atomic_load_8>;
4699 def atomic_load_acquire_16 : acquiring_load<atomic_load_16>;
4700 def atomic_load_acquire_32 : acquiring_load<atomic_load_32>;
4702 class releasing_store<PatFrag base>
4703 : PatFrag<(ops node:$ptr, node:$val), (base node:$ptr, node:$val), [{
4704 AtomicOrdering Ordering = cast<AtomicSDNode>(N)->getOrdering();
4705 return isAtLeastRelease(Ordering);
4708 def atomic_store_release_8 : releasing_store<atomic_store_8>;
4709 def atomic_store_release_16 : releasing_store<atomic_store_16>;
4710 def atomic_store_release_32 : releasing_store<atomic_store_32>;
4712 let AddedComplexity = 8 in {
4713 def : ARMPat<(atomic_load_acquire_8 addr_offset_none:$addr), (LDAB addr_offset_none:$addr)>;
4714 def : ARMPat<(atomic_load_acquire_16 addr_offset_none:$addr), (LDAH addr_offset_none:$addr)>;
4715 def : ARMPat<(atomic_load_acquire_32 addr_offset_none:$addr), (LDA addr_offset_none:$addr)>;
4716 def : ARMPat<(atomic_store_release_8 addr_offset_none:$addr, GPR:$val), (STLB GPR:$val, addr_offset_none:$addr)>;
4717 def : ARMPat<(atomic_store_release_16 addr_offset_none:$addr, GPR:$val), (STLH GPR:$val, addr_offset_none:$addr)>;
4718 def : ARMPat<(atomic_store_release_32 addr_offset_none:$addr, GPR:$val), (STL GPR:$val, addr_offset_none:$addr)>;
4721 // SWP/SWPB are deprecated in V6/V7.
4722 let mayLoad = 1, mayStore = 1 in {
4723 def SWP : AIswp<0, (outs GPRnopc:$Rt),
4724 (ins GPRnopc:$Rt2, addr_offset_none:$addr), "swp", []>,
4726 def SWPB: AIswp<1, (outs GPRnopc:$Rt),
4727 (ins GPRnopc:$Rt2, addr_offset_none:$addr), "swpb", []>,
4731 //===----------------------------------------------------------------------===//
4732 // Coprocessor Instructions.
4735 def CDP : ABI<0b1110, (outs), (ins p_imm:$cop, imm0_15:$opc1,
4736 c_imm:$CRd, c_imm:$CRn, c_imm:$CRm, imm0_7:$opc2),
4737 NoItinerary, "cdp", "\t$cop, $opc1, $CRd, $CRn, $CRm, $opc2",
4738 [(int_arm_cdp imm:$cop, imm:$opc1, imm:$CRd, imm:$CRn,
4739 imm:$CRm, imm:$opc2)]>,
4748 let Inst{3-0} = CRm;
4750 let Inst{7-5} = opc2;
4751 let Inst{11-8} = cop;
4752 let Inst{15-12} = CRd;
4753 let Inst{19-16} = CRn;
4754 let Inst{23-20} = opc1;
4757 def CDP2 : ABXI<0b1110, (outs), (ins p_imm:$cop, imm0_15:$opc1,
4758 c_imm:$CRd, c_imm:$CRn, c_imm:$CRm, imm0_7:$opc2),
4759 NoItinerary, "cdp2\t$cop, $opc1, $CRd, $CRn, $CRm, $opc2",
4760 [(int_arm_cdp2 imm:$cop, imm:$opc1, imm:$CRd, imm:$CRn,
4761 imm:$CRm, imm:$opc2)]>,
4763 let Inst{31-28} = 0b1111;
4771 let Inst{3-0} = CRm;
4773 let Inst{7-5} = opc2;
4774 let Inst{11-8} = cop;
4775 let Inst{15-12} = CRd;
4776 let Inst{19-16} = CRn;
4777 let Inst{23-20} = opc1;
4780 class ACI<dag oops, dag iops, string opc, string asm,
4781 IndexMode im = IndexModeNone>
4782 : I<oops, iops, AddrModeNone, 4, im, BrFrm, NoItinerary,
4784 let Inst{27-25} = 0b110;
4786 class ACInoP<dag oops, dag iops, string opc, string asm,
4787 IndexMode im = IndexModeNone>
4788 : InoP<oops, iops, AddrModeNone, 4, im, BrFrm, NoItinerary,
4790 let Inst{31-28} = 0b1111;
4791 let Inst{27-25} = 0b110;
4793 multiclass LdStCop<bit load, bit Dbit, string asm> {
4794 def _OFFSET : ACI<(outs), (ins p_imm:$cop, c_imm:$CRd, addrmode5:$addr),
4795 asm, "\t$cop, $CRd, $addr"> {
4799 let Inst{24} = 1; // P = 1
4800 let Inst{23} = addr{8};
4801 let Inst{22} = Dbit;
4802 let Inst{21} = 0; // W = 0
4803 let Inst{20} = load;
4804 let Inst{19-16} = addr{12-9};
4805 let Inst{15-12} = CRd;
4806 let Inst{11-8} = cop;
4807 let Inst{7-0} = addr{7-0};
4808 let DecoderMethod = "DecodeCopMemInstruction";
4810 def _PRE : ACI<(outs), (ins p_imm:$cop, c_imm:$CRd, addrmode5_pre:$addr),
4811 asm, "\t$cop, $CRd, $addr!", IndexModePre> {
4815 let Inst{24} = 1; // P = 1
4816 let Inst{23} = addr{8};
4817 let Inst{22} = Dbit;
4818 let Inst{21} = 1; // W = 1
4819 let Inst{20} = load;
4820 let Inst{19-16} = addr{12-9};
4821 let Inst{15-12} = CRd;
4822 let Inst{11-8} = cop;
4823 let Inst{7-0} = addr{7-0};
4824 let DecoderMethod = "DecodeCopMemInstruction";
4826 def _POST: ACI<(outs), (ins p_imm:$cop, c_imm:$CRd, addr_offset_none:$addr,
4827 postidx_imm8s4:$offset),
4828 asm, "\t$cop, $CRd, $addr, $offset", IndexModePost> {
4833 let Inst{24} = 0; // P = 0
4834 let Inst{23} = offset{8};
4835 let Inst{22} = Dbit;
4836 let Inst{21} = 1; // W = 1
4837 let Inst{20} = load;
4838 let Inst{19-16} = addr;
4839 let Inst{15-12} = CRd;
4840 let Inst{11-8} = cop;
4841 let Inst{7-0} = offset{7-0};
4842 let DecoderMethod = "DecodeCopMemInstruction";
4844 def _OPTION : ACI<(outs),
4845 (ins p_imm:$cop, c_imm:$CRd, addr_offset_none:$addr,
4846 coproc_option_imm:$option),
4847 asm, "\t$cop, $CRd, $addr, $option"> {
4852 let Inst{24} = 0; // P = 0
4853 let Inst{23} = 1; // U = 1
4854 let Inst{22} = Dbit;
4855 let Inst{21} = 0; // W = 0
4856 let Inst{20} = load;
4857 let Inst{19-16} = addr;
4858 let Inst{15-12} = CRd;
4859 let Inst{11-8} = cop;
4860 let Inst{7-0} = option;
4861 let DecoderMethod = "DecodeCopMemInstruction";
4864 multiclass LdSt2Cop<bit load, bit Dbit, string asm> {
4865 def _OFFSET : ACInoP<(outs), (ins p_imm:$cop, c_imm:$CRd, addrmode5:$addr),
4866 asm, "\t$cop, $CRd, $addr"> {
4870 let Inst{24} = 1; // P = 1
4871 let Inst{23} = addr{8};
4872 let Inst{22} = Dbit;
4873 let Inst{21} = 0; // W = 0
4874 let Inst{20} = load;
4875 let Inst{19-16} = addr{12-9};
4876 let Inst{15-12} = CRd;
4877 let Inst{11-8} = cop;
4878 let Inst{7-0} = addr{7-0};
4879 let DecoderMethod = "DecodeCopMemInstruction";
4881 def _PRE : ACInoP<(outs), (ins p_imm:$cop, c_imm:$CRd, addrmode5_pre:$addr),
4882 asm, "\t$cop, $CRd, $addr!", IndexModePre> {
4886 let Inst{24} = 1; // P = 1
4887 let Inst{23} = addr{8};
4888 let Inst{22} = Dbit;
4889 let Inst{21} = 1; // W = 1
4890 let Inst{20} = load;
4891 let Inst{19-16} = addr{12-9};
4892 let Inst{15-12} = CRd;
4893 let Inst{11-8} = cop;
4894 let Inst{7-0} = addr{7-0};
4895 let DecoderMethod = "DecodeCopMemInstruction";
4897 def _POST: ACInoP<(outs), (ins p_imm:$cop, c_imm:$CRd, addr_offset_none:$addr,
4898 postidx_imm8s4:$offset),
4899 asm, "\t$cop, $CRd, $addr, $offset", IndexModePost> {
4904 let Inst{24} = 0; // P = 0
4905 let Inst{23} = offset{8};
4906 let Inst{22} = Dbit;
4907 let Inst{21} = 1; // W = 1
4908 let Inst{20} = load;
4909 let Inst{19-16} = addr;
4910 let Inst{15-12} = CRd;
4911 let Inst{11-8} = cop;
4912 let Inst{7-0} = offset{7-0};
4913 let DecoderMethod = "DecodeCopMemInstruction";
4915 def _OPTION : ACInoP<(outs),
4916 (ins p_imm:$cop, c_imm:$CRd, addr_offset_none:$addr,
4917 coproc_option_imm:$option),
4918 asm, "\t$cop, $CRd, $addr, $option"> {
4923 let Inst{24} = 0; // P = 0
4924 let Inst{23} = 1; // U = 1
4925 let Inst{22} = Dbit;
4926 let Inst{21} = 0; // W = 0
4927 let Inst{20} = load;
4928 let Inst{19-16} = addr;
4929 let Inst{15-12} = CRd;
4930 let Inst{11-8} = cop;
4931 let Inst{7-0} = option;
4932 let DecoderMethod = "DecodeCopMemInstruction";
4936 defm LDC : LdStCop <1, 0, "ldc">;
4937 defm LDCL : LdStCop <1, 1, "ldcl">;
4938 defm STC : LdStCop <0, 0, "stc">;
4939 defm STCL : LdStCop <0, 1, "stcl">;
4940 defm LDC2 : LdSt2Cop<1, 0, "ldc2">, Requires<[PreV8]>;
4941 defm LDC2L : LdSt2Cop<1, 1, "ldc2l">, Requires<[PreV8]>;
4942 defm STC2 : LdSt2Cop<0, 0, "stc2">, Requires<[PreV8]>;
4943 defm STC2L : LdSt2Cop<0, 1, "stc2l">, Requires<[PreV8]>;
4945 //===----------------------------------------------------------------------===//
4946 // Move between coprocessor and ARM core register.
4949 class MovRCopro<string opc, bit direction, dag oops, dag iops,
4951 : ABI<0b1110, oops, iops, NoItinerary, opc,
4952 "\t$cop, $opc1, $Rt, $CRn, $CRm, $opc2", pattern> {
4953 let Inst{20} = direction;
4963 let Inst{15-12} = Rt;
4964 let Inst{11-8} = cop;
4965 let Inst{23-21} = opc1;
4966 let Inst{7-5} = opc2;
4967 let Inst{3-0} = CRm;
4968 let Inst{19-16} = CRn;
4971 def MCR : MovRCopro<"mcr", 0 /* from ARM core register to coprocessor */,
4973 (ins p_imm:$cop, imm0_7:$opc1, GPR:$Rt, c_imm:$CRn,
4974 c_imm:$CRm, imm0_7:$opc2),
4975 [(int_arm_mcr imm:$cop, imm:$opc1, GPR:$Rt, imm:$CRn,
4976 imm:$CRm, imm:$opc2)]>,
4977 ComplexDeprecationPredicate<"MCR">;
4978 def : ARMInstAlias<"mcr${p} $cop, $opc1, $Rt, $CRn, $CRm",
4979 (MCR p_imm:$cop, imm0_7:$opc1, GPR:$Rt, c_imm:$CRn,
4980 c_imm:$CRm, 0, pred:$p)>;
4981 def MRC : MovRCopro<"mrc", 1 /* from coprocessor to ARM core register */,
4982 (outs GPRwithAPSR:$Rt),
4983 (ins p_imm:$cop, imm0_7:$opc1, c_imm:$CRn, c_imm:$CRm,
4985 def : ARMInstAlias<"mrc${p} $cop, $opc1, $Rt, $CRn, $CRm",
4986 (MRC GPRwithAPSR:$Rt, p_imm:$cop, imm0_7:$opc1, c_imm:$CRn,
4987 c_imm:$CRm, 0, pred:$p)>;
4989 def : ARMPat<(int_arm_mrc imm:$cop, imm:$opc1, imm:$CRn, imm:$CRm, imm:$opc2),
4990 (MRC imm:$cop, imm:$opc1, imm:$CRn, imm:$CRm, imm:$opc2)>;
4992 class MovRCopro2<string opc, bit direction, dag oops, dag iops,
4994 : ABXI<0b1110, oops, iops, NoItinerary,
4995 !strconcat(opc, "\t$cop, $opc1, $Rt, $CRn, $CRm, $opc2"), pattern> {
4996 let Inst{31-24} = 0b11111110;
4997 let Inst{20} = direction;
5007 let Inst{15-12} = Rt;
5008 let Inst{11-8} = cop;
5009 let Inst{23-21} = opc1;
5010 let Inst{7-5} = opc2;
5011 let Inst{3-0} = CRm;
5012 let Inst{19-16} = CRn;
5015 def MCR2 : MovRCopro2<"mcr2", 0 /* from ARM core register to coprocessor */,
5017 (ins p_imm:$cop, imm0_7:$opc1, GPR:$Rt, c_imm:$CRn,
5018 c_imm:$CRm, imm0_7:$opc2),
5019 [(int_arm_mcr2 imm:$cop, imm:$opc1, GPR:$Rt, imm:$CRn,
5020 imm:$CRm, imm:$opc2)]>,
5022 def : ARMInstAlias<"mcr2 $cop, $opc1, $Rt, $CRn, $CRm",
5023 (MCR2 p_imm:$cop, imm0_7:$opc1, GPR:$Rt, c_imm:$CRn,
5025 def MRC2 : MovRCopro2<"mrc2", 1 /* from coprocessor to ARM core register */,
5026 (outs GPRwithAPSR:$Rt),
5027 (ins p_imm:$cop, imm0_7:$opc1, c_imm:$CRn, c_imm:$CRm,
5030 def : ARMInstAlias<"mrc2 $cop, $opc1, $Rt, $CRn, $CRm",
5031 (MRC2 GPRwithAPSR:$Rt, p_imm:$cop, imm0_7:$opc1, c_imm:$CRn,
5034 def : ARMV5TPat<(int_arm_mrc2 imm:$cop, imm:$opc1, imm:$CRn,
5035 imm:$CRm, imm:$opc2),
5036 (MRC2 imm:$cop, imm:$opc1, imm:$CRn, imm:$CRm, imm:$opc2)>;
5038 class MovRRCopro<string opc, bit direction, list<dag> pattern = []>
5039 : ABI<0b1100, (outs), (ins p_imm:$cop, imm0_15:$opc1,
5040 GPRnopc:$Rt, GPRnopc:$Rt2, c_imm:$CRm),
5041 NoItinerary, opc, "\t$cop, $opc1, $Rt, $Rt2, $CRm", pattern> {
5042 let Inst{23-21} = 0b010;
5043 let Inst{20} = direction;
5051 let Inst{15-12} = Rt;
5052 let Inst{19-16} = Rt2;
5053 let Inst{11-8} = cop;
5054 let Inst{7-4} = opc1;
5055 let Inst{3-0} = CRm;
5058 def MCRR : MovRRCopro<"mcrr", 0 /* from ARM core register to coprocessor */,
5059 [(int_arm_mcrr imm:$cop, imm:$opc1, GPRnopc:$Rt,
5060 GPRnopc:$Rt2, imm:$CRm)]>;
5061 def MRRC : MovRRCopro<"mrrc", 1 /* from coprocessor to ARM core register */>;
5063 class MovRRCopro2<string opc, bit direction, list<dag> pattern = []>
5064 : ABXI<0b1100, (outs), (ins p_imm:$cop, imm0_15:$opc1,
5065 GPRnopc:$Rt, GPRnopc:$Rt2, c_imm:$CRm), NoItinerary,
5066 !strconcat(opc, "\t$cop, $opc1, $Rt, $Rt2, $CRm"), pattern>,
5068 let Inst{31-28} = 0b1111;
5069 let Inst{23-21} = 0b010;
5070 let Inst{20} = direction;
5078 let Inst{15-12} = Rt;
5079 let Inst{19-16} = Rt2;
5080 let Inst{11-8} = cop;
5081 let Inst{7-4} = opc1;
5082 let Inst{3-0} = CRm;
5084 let DecoderMethod = "DecodeMRRC2";
5087 def MCRR2 : MovRRCopro2<"mcrr2", 0 /* from ARM core register to coprocessor */,
5088 [(int_arm_mcrr2 imm:$cop, imm:$opc1, GPRnopc:$Rt,
5089 GPRnopc:$Rt2, imm:$CRm)]>;
5090 def MRRC2 : MovRRCopro2<"mrrc2", 1 /* from coprocessor to ARM core register */>;
5092 //===----------------------------------------------------------------------===//
5093 // Move between special register and ARM core register
5096 // Move to ARM core register from Special Register
5097 def MRS : ABI<0b0001, (outs GPRnopc:$Rd), (ins), NoItinerary,
5098 "mrs", "\t$Rd, apsr", []> {
5100 let Inst{23-16} = 0b00001111;
5101 let Unpredictable{19-17} = 0b111;
5103 let Inst{15-12} = Rd;
5105 let Inst{11-0} = 0b000000000000;
5106 let Unpredictable{11-0} = 0b110100001111;
5109 def : InstAlias<"mrs${p} $Rd, cpsr", (MRS GPRnopc:$Rd, pred:$p)>,
5112 // The MRSsys instruction is the MRS instruction from the ARM ARM,
5113 // section B9.3.9, with the R bit set to 1.
5114 def MRSsys : ABI<0b0001, (outs GPRnopc:$Rd), (ins), NoItinerary,
5115 "mrs", "\t$Rd, spsr", []> {
5117 let Inst{23-16} = 0b01001111;
5118 let Unpredictable{19-16} = 0b1111;
5120 let Inst{15-12} = Rd;
5122 let Inst{11-0} = 0b000000000000;
5123 let Unpredictable{11-0} = 0b110100001111;
5126 // However, the MRS (banked register) system instruction (ARMv7VE) *does* have a
5127 // separate encoding (distinguished by bit 5.
5128 def MRSbanked : ABI<0b0001, (outs GPRnopc:$Rd), (ins banked_reg:$banked),
5129 NoItinerary, "mrs", "\t$Rd, $banked", []>,
5130 Requires<[IsARM, HasVirtualization]> {
5135 let Inst{22} = banked{5}; // R bit
5136 let Inst{21-20} = 0b00;
5137 let Inst{19-16} = banked{3-0};
5138 let Inst{15-12} = Rd;
5139 let Inst{11-9} = 0b001;
5140 let Inst{8} = banked{4};
5141 let Inst{7-0} = 0b00000000;
5144 // Move from ARM core register to Special Register
5146 // No need to have both system and application versions of MSR (immediate) or
5147 // MSR (register), the encodings are the same and the assembly parser has no way
5148 // to distinguish between them. The mask operand contains the special register
5149 // (R Bit) in bit 4 and bits 3-0 contains the mask with the fields to be
5150 // accessed in the special register.
5151 def MSR : ABI<0b0001, (outs), (ins msr_mask:$mask, GPR:$Rn), NoItinerary,
5152 "msr", "\t$mask, $Rn", []> {
5157 let Inst{22} = mask{4}; // R bit
5158 let Inst{21-20} = 0b10;
5159 let Inst{19-16} = mask{3-0};
5160 let Inst{15-12} = 0b1111;
5161 let Inst{11-4} = 0b00000000;
5165 def MSRi : ABI<0b0011, (outs), (ins msr_mask:$mask, mod_imm:$imm), NoItinerary,
5166 "msr", "\t$mask, $imm", []> {
5171 let Inst{22} = mask{4}; // R bit
5172 let Inst{21-20} = 0b10;
5173 let Inst{19-16} = mask{3-0};
5174 let Inst{15-12} = 0b1111;
5175 let Inst{11-0} = imm;
5178 // However, the MSR (banked register) system instruction (ARMv7VE) *does* have a
5179 // separate encoding (distinguished by bit 5.
5180 def MSRbanked : ABI<0b0001, (outs), (ins banked_reg:$banked, GPRnopc:$Rn),
5181 NoItinerary, "msr", "\t$banked, $Rn", []>,
5182 Requires<[IsARM, HasVirtualization]> {
5187 let Inst{22} = banked{5}; // R bit
5188 let Inst{21-20} = 0b10;
5189 let Inst{19-16} = banked{3-0};
5190 let Inst{15-12} = 0b1111;
5191 let Inst{11-9} = 0b001;
5192 let Inst{8} = banked{4};
5193 let Inst{7-4} = 0b0000;
5197 // Dynamic stack allocation yields a _chkstk for Windows targets. These calls
5198 // are needed to probe the stack when allocating more than
5199 // 4k bytes in one go. Touching the stack at 4K increments is necessary to
5200 // ensure that the guard pages used by the OS virtual memory manager are
5201 // allocated in correct sequence.
5202 // The main point of having separate instruction are extra unmodelled effects
5203 // (compared to ordinary calls) like stack pointer change.
5205 def win__chkstk : SDNode<"ARMISD::WIN__CHKSTK", SDTNone,
5206 [SDNPHasChain, SDNPSideEffect]>;
5207 let usesCustomInserter = 1, Uses = [R4], Defs = [R4, SP] in
5208 def WIN__CHKSTK : PseudoInst<(outs), (ins), NoItinerary, [(win__chkstk)]>;
5210 //===----------------------------------------------------------------------===//
5214 // __aeabi_read_tp preserves the registers r1-r3.
5215 // This is a pseudo inst so that we can get the encoding right,
5216 // complete with fixup for the aeabi_read_tp function.
5217 // TPsoft is valid for ARM mode only, in case of Thumb mode a tTPsoft pattern
5218 // is defined in "ARMInstrThumb.td".
5220 Defs = [R0, R12, LR, CPSR], Uses = [SP] in {
5221 def TPsoft : ARMPseudoInst<(outs), (ins), 4, IIC_Br,
5222 [(set R0, ARMthread_pointer)]>, Sched<[WriteBr]>;
5225 //===----------------------------------------------------------------------===//
5226 // SJLJ Exception handling intrinsics
5227 // eh_sjlj_setjmp() is an instruction sequence to store the return
5228 // address and save #0 in R0 for the non-longjmp case.
5229 // Since by its nature we may be coming from some other function to get
5230 // here, and we're using the stack frame for the containing function to
5231 // save/restore registers, we can't keep anything live in regs across
5232 // the eh_sjlj_setjmp(), else it will almost certainly have been tromped upon
5233 // when we get here from a longjmp(). We force everything out of registers
5234 // except for our own input by listing the relevant registers in Defs. By
5235 // doing so, we also cause the prologue/epilogue code to actively preserve
5236 // all of the callee-saved resgisters, which is exactly what we want.
5237 // A constant value is passed in $val, and we use the location as a scratch.
5239 // These are pseudo-instructions and are lowered to individual MC-insts, so
5240 // no encoding information is necessary.
5242 [ R0, R1, R2, R3, R4, R5, R6, R7, R8, R9, R10, R11, R12, LR, CPSR,
5243 Q0, Q1, Q2, Q3, Q4, Q5, Q6, Q7, Q8, Q9, Q10, Q11, Q12, Q13, Q14, Q15 ],
5244 hasSideEffects = 1, isBarrier = 1, usesCustomInserter = 1 in {
5245 def Int_eh_sjlj_setjmp : PseudoInst<(outs), (ins GPR:$src, GPR:$val),
5247 [(set R0, (ARMeh_sjlj_setjmp GPR:$src, GPR:$val))]>,
5248 Requires<[IsARM, HasVFP2]>;
5252 [ R0, R1, R2, R3, R4, R5, R6, R7, R8, R9, R10, R11, R12, LR, CPSR ],
5253 hasSideEffects = 1, isBarrier = 1, usesCustomInserter = 1 in {
5254 def Int_eh_sjlj_setjmp_nofp : PseudoInst<(outs), (ins GPR:$src, GPR:$val),
5256 [(set R0, (ARMeh_sjlj_setjmp GPR:$src, GPR:$val))]>,
5257 Requires<[IsARM, NoVFP]>;
5260 // FIXME: Non-IOS version(s)
5261 let isBarrier = 1, hasSideEffects = 1, isTerminator = 1,
5262 Defs = [ R7, LR, SP ] in {
5263 def Int_eh_sjlj_longjmp : PseudoInst<(outs), (ins GPR:$src, GPR:$scratch),
5265 [(ARMeh_sjlj_longjmp GPR:$src, GPR:$scratch)]>,
5269 // eh.sjlj.dispatchsetup pseudo-instruction.
5270 // This pseudo is used for both ARM and Thumb. Any differences are handled when
5271 // the pseudo is expanded (which happens before any passes that need the
5272 // instruction size).
5273 let isBarrier = 1 in
5274 def Int_eh_sjlj_dispatchsetup : PseudoInst<(outs), (ins), NoItinerary, []>;
5277 //===----------------------------------------------------------------------===//
5278 // Non-Instruction Patterns
5281 // ARMv4 indirect branch using (MOVr PC, dst)
5282 let isBranch = 1, isTerminator = 1, isBarrier = 1, isIndirectBranch = 1 in
5283 def MOVPCRX : ARMPseudoExpand<(outs), (ins GPR:$dst),
5284 4, IIC_Br, [(brind GPR:$dst)],
5285 (MOVr PC, GPR:$dst, (ops 14, zero_reg), zero_reg)>,
5286 Requires<[IsARM, NoV4T]>, Sched<[WriteBr]>;
5288 // Large immediate handling.
5290 // 32-bit immediate using two piece mod_imms or movw + movt.
5291 // This is a single pseudo instruction, the benefit is that it can be remat'd
5292 // as a single unit instead of having to handle reg inputs.
5293 // FIXME: Remove this when we can do generalized remat.
5294 let isReMaterializable = 1, isMoveImm = 1 in
5295 def MOVi32imm : PseudoInst<(outs GPR:$dst), (ins i32imm:$src), IIC_iMOVix2,
5296 [(set GPR:$dst, (arm_i32imm:$src))]>,
5299 def LDRLIT_ga_abs : PseudoInst<(outs GPR:$dst), (ins i32imm:$src), IIC_iLoad_i,
5300 [(set GPR:$dst, (ARMWrapper tglobaladdr:$src))]>,
5301 Requires<[IsARM, DontUseMovt]>;
5303 // Pseudo instruction that combines movw + movt + add pc (if PIC).
5304 // It also makes it possible to rematerialize the instructions.
5305 // FIXME: Remove this when we can do generalized remat and when machine licm
5306 // can properly the instructions.
5307 let isReMaterializable = 1 in {
5308 def MOV_ga_pcrel : PseudoInst<(outs GPR:$dst), (ins i32imm:$addr),
5310 [(set GPR:$dst, (ARMWrapperPIC tglobaladdr:$addr))]>,
5311 Requires<[IsARM, UseMovt]>;
5313 def LDRLIT_ga_pcrel : PseudoInst<(outs GPR:$dst), (ins i32imm:$addr),
5316 (ARMWrapperPIC tglobaladdr:$addr))]>,
5317 Requires<[IsARM, DontUseMovt]>;
5319 let AddedComplexity = 10 in
5320 def LDRLIT_ga_pcrel_ldr : PseudoInst<(outs GPR:$dst), (ins i32imm:$addr),
5323 (load (ARMWrapperPIC tglobaladdr:$addr)))]>,
5324 Requires<[IsARM, DontUseMovt]>;
5326 let AddedComplexity = 10 in
5327 def MOV_ga_pcrel_ldr : PseudoInst<(outs GPR:$dst), (ins i32imm:$addr),
5329 [(set GPR:$dst, (load (ARMWrapperPIC tglobaladdr:$addr)))]>,
5330 Requires<[IsARM, UseMovt]>;
5331 } // isReMaterializable
5333 // ConstantPool, GlobalAddress, and JumpTable
5334 def : ARMPat<(ARMWrapper tconstpool :$dst), (LEApcrel tconstpool :$dst)>;
5335 def : ARMPat<(ARMWrapper tglobaladdr :$dst), (MOVi32imm tglobaladdr :$dst)>,
5336 Requires<[IsARM, UseMovt]>;
5337 def : ARMPat<(ARMWrapperJT tjumptable:$dst, imm:$id),
5338 (LEApcrelJT tjumptable:$dst, imm:$id)>;
5340 // TODO: add,sub,and, 3-instr forms?
5342 // Tail calls. These patterns also apply to Thumb mode.
5343 def : Pat<(ARMtcret tcGPR:$dst), (TCRETURNri tcGPR:$dst)>;
5344 def : Pat<(ARMtcret (i32 tglobaladdr:$dst)), (TCRETURNdi texternalsym:$dst)>;
5345 def : Pat<(ARMtcret (i32 texternalsym:$dst)), (TCRETURNdi texternalsym:$dst)>;
5348 def : ARMPat<(ARMcall texternalsym:$func), (BL texternalsym:$func)>;
5349 def : ARMPat<(ARMcall_nolink texternalsym:$func),
5350 (BMOVPCB_CALL texternalsym:$func)>;
5352 // zextload i1 -> zextload i8
5353 def : ARMPat<(zextloadi1 addrmode_imm12:$addr), (LDRBi12 addrmode_imm12:$addr)>;
5354 def : ARMPat<(zextloadi1 ldst_so_reg:$addr), (LDRBrs ldst_so_reg:$addr)>;
5356 // extload -> zextload
5357 def : ARMPat<(extloadi1 addrmode_imm12:$addr), (LDRBi12 addrmode_imm12:$addr)>;
5358 def : ARMPat<(extloadi1 ldst_so_reg:$addr), (LDRBrs ldst_so_reg:$addr)>;
5359 def : ARMPat<(extloadi8 addrmode_imm12:$addr), (LDRBi12 addrmode_imm12:$addr)>;
5360 def : ARMPat<(extloadi8 ldst_so_reg:$addr), (LDRBrs ldst_so_reg:$addr)>;
5362 def : ARMPat<(extloadi16 addrmode3:$addr), (LDRH addrmode3:$addr)>;
5364 def : ARMPat<(extloadi8 addrmodepc:$addr), (PICLDRB addrmodepc:$addr)>;
5365 def : ARMPat<(extloadi16 addrmodepc:$addr), (PICLDRH addrmodepc:$addr)>;
5368 def : ARMV5TEPat<(mul (sra (shl GPR:$a, (i32 16)), (i32 16)),
5369 (sra (shl GPR:$b, (i32 16)), (i32 16))),
5370 (SMULBB GPR:$a, GPR:$b)>;
5371 def : ARMV5TEPat<(mul sext_16_node:$a, sext_16_node:$b),
5372 (SMULBB GPR:$a, GPR:$b)>;
5373 def : ARMV5TEPat<(mul (sra (shl GPR:$a, (i32 16)), (i32 16)),
5374 (sra GPR:$b, (i32 16))),
5375 (SMULBT GPR:$a, GPR:$b)>;
5376 def : ARMV5TEPat<(mul sext_16_node:$a, (sra GPR:$b, (i32 16))),
5377 (SMULBT GPR:$a, GPR:$b)>;
5378 def : ARMV5TEPat<(mul (sra GPR:$a, (i32 16)),
5379 (sra (shl GPR:$b, (i32 16)), (i32 16))),
5380 (SMULTB GPR:$a, GPR:$b)>;
5381 def : ARMV5TEPat<(mul (sra GPR:$a, (i32 16)), sext_16_node:$b),
5382 (SMULTB GPR:$a, GPR:$b)>;
5384 def : ARMV5MOPat<(add GPR:$acc,
5385 (mul (sra (shl GPR:$a, (i32 16)), (i32 16)),
5386 (sra (shl GPR:$b, (i32 16)), (i32 16)))),
5387 (SMLABB GPR:$a, GPR:$b, GPR:$acc)>;
5388 def : ARMV5MOPat<(add GPR:$acc,
5389 (mul sext_16_node:$a, sext_16_node:$b)),
5390 (SMLABB GPR:$a, GPR:$b, GPR:$acc)>;
5391 def : ARMV5MOPat<(add GPR:$acc,
5392 (mul (sra (shl GPR:$a, (i32 16)), (i32 16)),
5393 (sra GPR:$b, (i32 16)))),
5394 (SMLABT GPR:$a, GPR:$b, GPR:$acc)>;
5395 def : ARMV5MOPat<(add GPR:$acc,
5396 (mul sext_16_node:$a, (sra GPR:$b, (i32 16)))),
5397 (SMLABT GPR:$a, GPR:$b, GPR:$acc)>;
5398 def : ARMV5MOPat<(add GPR:$acc,
5399 (mul (sra GPR:$a, (i32 16)),
5400 (sra (shl GPR:$b, (i32 16)), (i32 16)))),
5401 (SMLATB GPR:$a, GPR:$b, GPR:$acc)>;
5402 def : ARMV5MOPat<(add GPR:$acc,
5403 (mul (sra GPR:$a, (i32 16)), sext_16_node:$b)),
5404 (SMLATB GPR:$a, GPR:$b, GPR:$acc)>;
5407 // Pre-v7 uses MCR for synchronization barriers.
5408 def : ARMPat<(ARMMemBarrierMCR GPR:$zero), (MCR 15, 0, GPR:$zero, 7, 10, 5)>,
5409 Requires<[IsARM, HasV6]>;
5411 // SXT/UXT with no rotate
5412 let AddedComplexity = 16 in {
5413 def : ARMV6Pat<(and GPR:$Src, 0x000000FF), (UXTB GPR:$Src, 0)>;
5414 def : ARMV6Pat<(and GPR:$Src, 0x0000FFFF), (UXTH GPR:$Src, 0)>;
5415 def : ARMV6Pat<(and GPR:$Src, 0x00FF00FF), (UXTB16 GPR:$Src, 0)>;
5416 def : ARMV6Pat<(add GPR:$Rn, (and GPR:$Rm, 0x00FF)),
5417 (UXTAB GPR:$Rn, GPR:$Rm, 0)>;
5418 def : ARMV6Pat<(add GPR:$Rn, (and GPR:$Rm, 0xFFFF)),
5419 (UXTAH GPR:$Rn, GPR:$Rm, 0)>;
5422 def : ARMV6Pat<(sext_inreg GPR:$Src, i8), (SXTB GPR:$Src, 0)>;
5423 def : ARMV6Pat<(sext_inreg GPR:$Src, i16), (SXTH GPR:$Src, 0)>;
5425 def : ARMV6Pat<(add GPR:$Rn, (sext_inreg GPRnopc:$Rm, i8)),
5426 (SXTAB GPR:$Rn, GPRnopc:$Rm, 0)>;
5427 def : ARMV6Pat<(add GPR:$Rn, (sext_inreg GPRnopc:$Rm, i16)),
5428 (SXTAH GPR:$Rn, GPRnopc:$Rm, 0)>;
5430 // Atomic load/store patterns
5431 def : ARMPat<(atomic_load_8 ldst_so_reg:$src),
5432 (LDRBrs ldst_so_reg:$src)>;
5433 def : ARMPat<(atomic_load_8 addrmode_imm12:$src),
5434 (LDRBi12 addrmode_imm12:$src)>;
5435 def : ARMPat<(atomic_load_16 addrmode3:$src),
5436 (LDRH addrmode3:$src)>;
5437 def : ARMPat<(atomic_load_32 ldst_so_reg:$src),
5438 (LDRrs ldst_so_reg:$src)>;
5439 def : ARMPat<(atomic_load_32 addrmode_imm12:$src),
5440 (LDRi12 addrmode_imm12:$src)>;
5441 def : ARMPat<(atomic_store_8 ldst_so_reg:$ptr, GPR:$val),
5442 (STRBrs GPR:$val, ldst_so_reg:$ptr)>;
5443 def : ARMPat<(atomic_store_8 addrmode_imm12:$ptr, GPR:$val),
5444 (STRBi12 GPR:$val, addrmode_imm12:$ptr)>;
5445 def : ARMPat<(atomic_store_16 addrmode3:$ptr, GPR:$val),
5446 (STRH GPR:$val, addrmode3:$ptr)>;
5447 def : ARMPat<(atomic_store_32 ldst_so_reg:$ptr, GPR:$val),
5448 (STRrs GPR:$val, ldst_so_reg:$ptr)>;
5449 def : ARMPat<(atomic_store_32 addrmode_imm12:$ptr, GPR:$val),
5450 (STRi12 GPR:$val, addrmode_imm12:$ptr)>;
5453 //===----------------------------------------------------------------------===//
5457 include "ARMInstrThumb.td"
5459 //===----------------------------------------------------------------------===//
5463 include "ARMInstrThumb2.td"
5465 //===----------------------------------------------------------------------===//
5466 // Floating Point Support
5469 include "ARMInstrVFP.td"
5471 //===----------------------------------------------------------------------===//
5472 // Advanced SIMD (NEON) Support
5475 include "ARMInstrNEON.td"
5477 //===----------------------------------------------------------------------===//
5478 // Assembler aliases
5482 def : InstAlias<"dmb", (DMB 0xf)>, Requires<[IsARM, HasDB]>;
5483 def : InstAlias<"dsb", (DSB 0xf)>, Requires<[IsARM, HasDB]>;
5484 def : InstAlias<"isb", (ISB 0xf)>, Requires<[IsARM, HasDB]>;
5486 // System instructions
5487 def : MnemonicAlias<"swi", "svc">;
5489 // Load / Store Multiple
5490 def : MnemonicAlias<"ldmfd", "ldm">;
5491 def : MnemonicAlias<"ldmia", "ldm">;
5492 def : MnemonicAlias<"ldmea", "ldmdb">;
5493 def : MnemonicAlias<"stmfd", "stmdb">;
5494 def : MnemonicAlias<"stmia", "stm">;
5495 def : MnemonicAlias<"stmea", "stm">;
5497 // PKHBT/PKHTB with default shift amount. PKHTB is equivalent to PKHBT when the
5498 // shift amount is zero (i.e., unspecified).
5499 def : InstAlias<"pkhbt${p} $Rd, $Rn, $Rm",
5500 (PKHBT GPRnopc:$Rd, GPRnopc:$Rn, GPRnopc:$Rm, 0, pred:$p)>,
5501 Requires<[IsARM, HasV6]>;
5502 def : InstAlias<"pkhtb${p} $Rd, $Rn, $Rm",
5503 (PKHBT GPRnopc:$Rd, GPRnopc:$Rn, GPRnopc:$Rm, 0, pred:$p)>,
5504 Requires<[IsARM, HasV6]>;
5506 // PUSH/POP aliases for STM/LDM
5507 def : ARMInstAlias<"push${p} $regs", (STMDB_UPD SP, pred:$p, reglist:$regs)>;
5508 def : ARMInstAlias<"pop${p} $regs", (LDMIA_UPD SP, pred:$p, reglist:$regs)>;
5510 // SSAT/USAT optional shift operand.
5511 def : ARMInstAlias<"ssat${p} $Rd, $sat_imm, $Rn",
5512 (SSAT GPRnopc:$Rd, imm1_32:$sat_imm, GPRnopc:$Rn, 0, pred:$p)>;
5513 def : ARMInstAlias<"usat${p} $Rd, $sat_imm, $Rn",
5514 (USAT GPRnopc:$Rd, imm0_31:$sat_imm, GPRnopc:$Rn, 0, pred:$p)>;
5517 // Extend instruction optional rotate operand.
5518 def : ARMInstAlias<"sxtab${p} $Rd, $Rn, $Rm",
5519 (SXTAB GPRnopc:$Rd, GPR:$Rn, GPRnopc:$Rm, 0, pred:$p)>;
5520 def : ARMInstAlias<"sxtah${p} $Rd, $Rn, $Rm",
5521 (SXTAH GPRnopc:$Rd, GPR:$Rn, GPRnopc:$Rm, 0, pred:$p)>;
5522 def : ARMInstAlias<"sxtab16${p} $Rd, $Rn, $Rm",
5523 (SXTAB16 GPRnopc:$Rd, GPR:$Rn, GPRnopc:$Rm, 0, pred:$p)>;
5524 def : ARMInstAlias<"sxtb${p} $Rd, $Rm",
5525 (SXTB GPRnopc:$Rd, GPRnopc:$Rm, 0, pred:$p)>;
5526 def : ARMInstAlias<"sxtb16${p} $Rd, $Rm",
5527 (SXTB16 GPRnopc:$Rd, GPRnopc:$Rm, 0, pred:$p)>;
5528 def : ARMInstAlias<"sxth${p} $Rd, $Rm",
5529 (SXTH GPRnopc:$Rd, GPRnopc:$Rm, 0, pred:$p)>;
5531 def : ARMInstAlias<"uxtab${p} $Rd, $Rn, $Rm",
5532 (UXTAB GPRnopc:$Rd, GPR:$Rn, GPRnopc:$Rm, 0, pred:$p)>;
5533 def : ARMInstAlias<"uxtah${p} $Rd, $Rn, $Rm",
5534 (UXTAH GPRnopc:$Rd, GPR:$Rn, GPRnopc:$Rm, 0, pred:$p)>;
5535 def : ARMInstAlias<"uxtab16${p} $Rd, $Rn, $Rm",
5536 (UXTAB16 GPRnopc:$Rd, GPR:$Rn, GPRnopc:$Rm, 0, pred:$p)>;
5537 def : ARMInstAlias<"uxtb${p} $Rd, $Rm",
5538 (UXTB GPRnopc:$Rd, GPRnopc:$Rm, 0, pred:$p)>;
5539 def : ARMInstAlias<"uxtb16${p} $Rd, $Rm",
5540 (UXTB16 GPRnopc:$Rd, GPRnopc:$Rm, 0, pred:$p)>;
5541 def : ARMInstAlias<"uxth${p} $Rd, $Rm",
5542 (UXTH GPRnopc:$Rd, GPRnopc:$Rm, 0, pred:$p)>;
5546 def : MnemonicAlias<"rfefa", "rfeda">;
5547 def : MnemonicAlias<"rfeea", "rfedb">;
5548 def : MnemonicAlias<"rfefd", "rfeia">;
5549 def : MnemonicAlias<"rfeed", "rfeib">;
5550 def : MnemonicAlias<"rfe", "rfeia">;
5553 def : MnemonicAlias<"srsfa", "srsib">;
5554 def : MnemonicAlias<"srsea", "srsia">;
5555 def : MnemonicAlias<"srsfd", "srsdb">;
5556 def : MnemonicAlias<"srsed", "srsda">;
5557 def : MnemonicAlias<"srs", "srsia">;
5560 def : MnemonicAlias<"qsubaddx", "qsax">;
5562 def : MnemonicAlias<"saddsubx", "sasx">;
5563 // SHASX == SHADDSUBX
5564 def : MnemonicAlias<"shaddsubx", "shasx">;
5565 // SHSAX == SHSUBADDX
5566 def : MnemonicAlias<"shsubaddx", "shsax">;
5568 def : MnemonicAlias<"ssubaddx", "ssax">;
5570 def : MnemonicAlias<"uaddsubx", "uasx">;
5571 // UHASX == UHADDSUBX
5572 def : MnemonicAlias<"uhaddsubx", "uhasx">;
5573 // UHSAX == UHSUBADDX
5574 def : MnemonicAlias<"uhsubaddx", "uhsax">;
5575 // UQASX == UQADDSUBX
5576 def : MnemonicAlias<"uqaddsubx", "uqasx">;
5577 // UQSAX == UQSUBADDX
5578 def : MnemonicAlias<"uqsubaddx", "uqsax">;
5580 def : MnemonicAlias<"usubaddx", "usax">;
5582 // "mov Rd, mod_imm_not" can be handled via "mvn" in assembly, just like
5584 def : ARMInstAlias<"mov${s}${p} $Rd, $imm",
5585 (MVNi rGPR:$Rd, mod_imm_not:$imm, pred:$p, cc_out:$s)>;
5586 def : ARMInstAlias<"mvn${s}${p} $Rd, $imm",
5587 (MOVi rGPR:$Rd, mod_imm_not:$imm, pred:$p, cc_out:$s)>;
5588 // Same for AND <--> BIC
5589 def : ARMInstAlias<"bic${s}${p} $Rd, $Rn, $imm",
5590 (ANDri rGPR:$Rd, rGPR:$Rn, mod_imm_not:$imm,
5591 pred:$p, cc_out:$s)>;
5592 def : ARMInstAlias<"bic${s}${p} $Rdn, $imm",
5593 (ANDri rGPR:$Rdn, rGPR:$Rdn, mod_imm_not:$imm,
5594 pred:$p, cc_out:$s)>;
5595 def : ARMInstAlias<"and${s}${p} $Rd, $Rn, $imm",
5596 (BICri rGPR:$Rd, rGPR:$Rn, mod_imm_not:$imm,
5597 pred:$p, cc_out:$s)>;
5598 def : ARMInstAlias<"and${s}${p} $Rdn, $imm",
5599 (BICri rGPR:$Rdn, rGPR:$Rdn, mod_imm_not:$imm,
5600 pred:$p, cc_out:$s)>;
5602 // Likewise, "add Rd, mod_imm_neg" -> sub
5603 def : ARMInstAlias<"add${s}${p} $Rd, $Rn, $imm",
5604 (SUBri GPR:$Rd, GPR:$Rn, mod_imm_neg:$imm, pred:$p, cc_out:$s)>;
5605 def : ARMInstAlias<"add${s}${p} $Rd, $imm",
5606 (SUBri GPR:$Rd, GPR:$Rd, mod_imm_neg:$imm, pred:$p, cc_out:$s)>;
5607 // Same for CMP <--> CMN via mod_imm_neg
5608 def : ARMInstAlias<"cmp${p} $Rd, $imm",
5609 (CMNri rGPR:$Rd, mod_imm_neg:$imm, pred:$p)>;
5610 def : ARMInstAlias<"cmn${p} $Rd, $imm",
5611 (CMPri rGPR:$Rd, mod_imm_neg:$imm, pred:$p)>;
5613 // The shifter forms of the MOV instruction are aliased to the ASR, LSL,
5614 // LSR, ROR, and RRX instructions.
5615 // FIXME: We need C++ parser hooks to map the alias to the MOV
5616 // encoding. It seems we should be able to do that sort of thing
5617 // in tblgen, but it could get ugly.
5618 let TwoOperandAliasConstraint = "$Rm = $Rd" in {
5619 def ASRi : ARMAsmPseudo<"asr${s}${p} $Rd, $Rm, $imm",
5620 (ins GPR:$Rd, GPR:$Rm, imm0_32:$imm, pred:$p,
5622 def LSRi : ARMAsmPseudo<"lsr${s}${p} $Rd, $Rm, $imm",
5623 (ins GPR:$Rd, GPR:$Rm, imm0_32:$imm, pred:$p,
5625 def LSLi : ARMAsmPseudo<"lsl${s}${p} $Rd, $Rm, $imm",
5626 (ins GPR:$Rd, GPR:$Rm, imm0_31:$imm, pred:$p,
5628 def RORi : ARMAsmPseudo<"ror${s}${p} $Rd, $Rm, $imm",
5629 (ins GPR:$Rd, GPR:$Rm, imm0_31:$imm, pred:$p,
5632 def RRXi : ARMAsmPseudo<"rrx${s}${p} $Rd, $Rm",
5633 (ins GPR:$Rd, GPR:$Rm, pred:$p, cc_out:$s)>;
5634 let TwoOperandAliasConstraint = "$Rn = $Rd" in {
5635 def ASRr : ARMAsmPseudo<"asr${s}${p} $Rd, $Rn, $Rm",
5636 (ins GPRnopc:$Rd, GPRnopc:$Rn, GPRnopc:$Rm, pred:$p,
5638 def LSRr : ARMAsmPseudo<"lsr${s}${p} $Rd, $Rn, $Rm",
5639 (ins GPRnopc:$Rd, GPRnopc:$Rn, GPRnopc:$Rm, pred:$p,
5641 def LSLr : ARMAsmPseudo<"lsl${s}${p} $Rd, $Rn, $Rm",
5642 (ins GPRnopc:$Rd, GPRnopc:$Rn, GPRnopc:$Rm, pred:$p,
5644 def RORr : ARMAsmPseudo<"ror${s}${p} $Rd, $Rn, $Rm",
5645 (ins GPRnopc:$Rd, GPRnopc:$Rn, GPRnopc:$Rm, pred:$p,
5649 // "neg" is and alias for "rsb rd, rn, #0"
5650 def : ARMInstAlias<"neg${s}${p} $Rd, $Rm",
5651 (RSBri GPR:$Rd, GPR:$Rm, 0, pred:$p, cc_out:$s)>;
5653 // Pre-v6, 'mov r0, r0' was used as a NOP encoding.
5654 def : InstAlias<"nop${p}", (MOVr R0, R0, pred:$p, zero_reg)>,
5655 Requires<[IsARM, NoV6]>;
5657 // MUL/UMLAL/SMLAL/UMULL/SMULL are available on all arches, but
5658 // the instruction definitions need difference constraints pre-v6.
5659 // Use these aliases for the assembly parsing on pre-v6.
5660 def : InstAlias<"mul${s}${p} $Rd, $Rn, $Rm",
5661 (MUL GPRnopc:$Rd, GPRnopc:$Rn, GPRnopc:$Rm, pred:$p, cc_out:$s)>,
5662 Requires<[IsARM, NoV6]>;
5663 def : InstAlias<"mla${s}${p} $Rd, $Rn, $Rm, $Ra",
5664 (MLA GPRnopc:$Rd, GPRnopc:$Rn, GPRnopc:$Rm, GPRnopc:$Ra,
5665 pred:$p, cc_out:$s)>,
5666 Requires<[IsARM, NoV6]>;
5667 def : InstAlias<"smlal${s}${p} $RdLo, $RdHi, $Rn, $Rm",
5668 (SMLAL GPR:$RdLo, GPR:$RdHi, GPR:$Rn, GPR:$Rm, pred:$p, cc_out:$s)>,
5669 Requires<[IsARM, NoV6]>;
5670 def : InstAlias<"umlal${s}${p} $RdLo, $RdHi, $Rn, $Rm",
5671 (UMLAL GPR:$RdLo, GPR:$RdHi, GPR:$Rn, GPR:$Rm, pred:$p, cc_out:$s)>,
5672 Requires<[IsARM, NoV6]>;
5673 def : InstAlias<"smull${s}${p} $RdLo, $RdHi, $Rn, $Rm",
5674 (SMULL GPR:$RdLo, GPR:$RdHi, GPR:$Rn, GPR:$Rm, pred:$p, cc_out:$s)>,
5675 Requires<[IsARM, NoV6]>;
5676 def : InstAlias<"umull${s}${p} $RdLo, $RdHi, $Rn, $Rm",
5677 (UMULL GPR:$RdLo, GPR:$RdHi, GPR:$Rn, GPR:$Rm, pred:$p, cc_out:$s)>,
5678 Requires<[IsARM, NoV6]>;
5680 // 'it' blocks in ARM mode just validate the predicates. The IT itself
5682 def ITasm : ARMAsmPseudo<"it$mask $cc", (ins it_pred:$cc, it_mask:$mask)>,
5683 ComplexDeprecationPredicate<"IT">;
5685 let mayLoad = 1, mayStore =1, hasSideEffects = 1 in
5686 def SPACE : PseudoInst<(outs GPR:$Rd), (ins i32imm:$size, GPR:$Rn),
5688 [(set GPR:$Rd, (int_arm_space imm:$size, GPR:$Rn))]>;