1 //===- ARMInstrInfo.td - Target Description for ARM Target -*- tablegen -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file describes the ARM instructions in TableGen format.
12 //===----------------------------------------------------------------------===//
14 //===----------------------------------------------------------------------===//
15 // ARM specific DAG Nodes.
19 def SDT_ARMCallSeqStart : SDCallSeqStart<[ SDTCisVT<0, i32> ]>;
20 def SDT_ARMCallSeqEnd : SDCallSeqEnd<[ SDTCisVT<0, i32>, SDTCisVT<1, i32> ]>;
22 def SDT_ARMSaveCallPC : SDTypeProfile<0, 1, []>;
24 def SDT_ARMcall : SDTypeProfile<0, -1, [SDTCisPtrTy<0>]>;
26 def SDT_ARMCMov : SDTypeProfile<1, 3,
27 [SDTCisSameAs<0, 1>, SDTCisSameAs<0, 2>,
30 def SDT_ARMBrcond : SDTypeProfile<0, 2,
31 [SDTCisVT<0, OtherVT>, SDTCisVT<1, i32>]>;
33 def SDT_ARMBrJT : SDTypeProfile<0, 3,
34 [SDTCisPtrTy<0>, SDTCisVT<1, i32>,
37 def SDT_ARMBr2JT : SDTypeProfile<0, 4,
38 [SDTCisPtrTy<0>, SDTCisVT<1, i32>,
39 SDTCisVT<2, i32>, SDTCisVT<3, i32>]>;
41 def SDT_ARMBCC_i64 : SDTypeProfile<0, 6,
43 SDTCisVT<1, i32>, SDTCisVT<2, i32>,
44 SDTCisVT<3, i32>, SDTCisVT<4, i32>,
45 SDTCisVT<5, OtherVT>]>;
47 def SDT_ARMAnd : SDTypeProfile<1, 2,
48 [SDTCisVT<0, i32>, SDTCisVT<1, i32>,
51 def SDT_ARMCmp : SDTypeProfile<0, 2, [SDTCisSameAs<0, 1>]>;
53 def SDT_ARMPICAdd : SDTypeProfile<1, 2, [SDTCisSameAs<0, 1>,
54 SDTCisPtrTy<1>, SDTCisVT<2, i32>]>;
56 def SDT_ARMThreadPointer : SDTypeProfile<1, 0, [SDTCisPtrTy<0>]>;
57 def SDT_ARMEH_SJLJ_Setjmp : SDTypeProfile<1, 2, [SDTCisInt<0>, SDTCisPtrTy<1>,
59 def SDT_ARMEH_SJLJ_Longjmp: SDTypeProfile<0, 2, [SDTCisPtrTy<0>, SDTCisInt<1>]>;
61 def SDT_ARMEH_SJLJ_DispatchSetup: SDTypeProfile<0, 1, [SDTCisInt<0>]>;
63 def SDT_ARMMEMBARRIER : SDTypeProfile<0, 1, [SDTCisInt<0>]>;
65 def SDT_ARMPREFETCH : SDTypeProfile<0, 3, [SDTCisPtrTy<0>, SDTCisSameAs<1, 2>,
68 def SDT_ARMTCRET : SDTypeProfile<0, 1, [SDTCisPtrTy<0>]>;
70 def SDT_ARMBFI : SDTypeProfile<1, 3, [SDTCisVT<0, i32>, SDTCisVT<1, i32>,
71 SDTCisVT<2, i32>, SDTCisVT<3, i32>]>;
74 def ARMWrapper : SDNode<"ARMISD::Wrapper", SDTIntUnaryOp>;
75 def ARMWrapperDYN : SDNode<"ARMISD::WrapperDYN", SDTIntUnaryOp>;
76 def ARMWrapperPIC : SDNode<"ARMISD::WrapperPIC", SDTIntUnaryOp>;
77 def ARMWrapperJT : SDNode<"ARMISD::WrapperJT", SDTIntBinOp>;
79 def ARMcallseq_start : SDNode<"ISD::CALLSEQ_START", SDT_ARMCallSeqStart,
80 [SDNPHasChain, SDNPOutGlue]>;
81 def ARMcallseq_end : SDNode<"ISD::CALLSEQ_END", SDT_ARMCallSeqEnd,
82 [SDNPHasChain, SDNPOptInGlue, SDNPOutGlue]>;
84 def ARMcall : SDNode<"ARMISD::CALL", SDT_ARMcall,
85 [SDNPHasChain, SDNPOptInGlue, SDNPOutGlue,
87 def ARMcall_pred : SDNode<"ARMISD::CALL_PRED", SDT_ARMcall,
88 [SDNPHasChain, SDNPOptInGlue, SDNPOutGlue,
90 def ARMcall_nolink : SDNode<"ARMISD::CALL_NOLINK", SDT_ARMcall,
91 [SDNPHasChain, SDNPOptInGlue, SDNPOutGlue,
94 def ARMretflag : SDNode<"ARMISD::RET_FLAG", SDTNone,
95 [SDNPHasChain, SDNPOptInGlue]>;
97 def ARMcmov : SDNode<"ARMISD::CMOV", SDT_ARMCMov,
100 def ARMbrcond : SDNode<"ARMISD::BRCOND", SDT_ARMBrcond,
101 [SDNPHasChain, SDNPInGlue, SDNPOutGlue]>;
103 def ARMbrjt : SDNode<"ARMISD::BR_JT", SDT_ARMBrJT,
105 def ARMbr2jt : SDNode<"ARMISD::BR2_JT", SDT_ARMBr2JT,
108 def ARMBcci64 : SDNode<"ARMISD::BCC_i64", SDT_ARMBCC_i64,
111 def ARMcmp : SDNode<"ARMISD::CMP", SDT_ARMCmp,
114 def ARMcmpZ : SDNode<"ARMISD::CMPZ", SDT_ARMCmp,
115 [SDNPOutGlue, SDNPCommutative]>;
117 def ARMpic_add : SDNode<"ARMISD::PIC_ADD", SDT_ARMPICAdd>;
119 def ARMsrl_flag : SDNode<"ARMISD::SRL_FLAG", SDTIntUnaryOp, [SDNPOutGlue]>;
120 def ARMsra_flag : SDNode<"ARMISD::SRA_FLAG", SDTIntUnaryOp, [SDNPOutGlue]>;
121 def ARMrrx : SDNode<"ARMISD::RRX" , SDTIntUnaryOp, [SDNPInGlue ]>;
123 def ARMthread_pointer: SDNode<"ARMISD::THREAD_POINTER", SDT_ARMThreadPointer>;
124 def ARMeh_sjlj_setjmp: SDNode<"ARMISD::EH_SJLJ_SETJMP",
125 SDT_ARMEH_SJLJ_Setjmp, [SDNPHasChain]>;
126 def ARMeh_sjlj_longjmp: SDNode<"ARMISD::EH_SJLJ_LONGJMP",
127 SDT_ARMEH_SJLJ_Longjmp, [SDNPHasChain]>;
128 def ARMeh_sjlj_dispatchsetup: SDNode<"ARMISD::EH_SJLJ_DISPATCHSETUP",
129 SDT_ARMEH_SJLJ_DispatchSetup, [SDNPHasChain]>;
132 def ARMMemBarrier : SDNode<"ARMISD::MEMBARRIER", SDT_ARMMEMBARRIER,
134 def ARMMemBarrierMCR : SDNode<"ARMISD::MEMBARRIER_MCR", SDT_ARMMEMBARRIER,
136 def ARMPreload : SDNode<"ARMISD::PRELOAD", SDT_ARMPREFETCH,
137 [SDNPHasChain, SDNPMayLoad, SDNPMayStore]>;
139 def ARMrbit : SDNode<"ARMISD::RBIT", SDTIntUnaryOp>;
141 def ARMtcret : SDNode<"ARMISD::TC_RETURN", SDT_ARMTCRET,
142 [SDNPHasChain, SDNPOptInGlue, SDNPVariadic]>;
145 def ARMbfi : SDNode<"ARMISD::BFI", SDT_ARMBFI>;
147 //===----------------------------------------------------------------------===//
148 // ARM Instruction Predicate Definitions.
150 def HasV4T : Predicate<"Subtarget->hasV4TOps()">,
151 AssemblerPredicate<"HasV4TOps">;
152 def NoV4T : Predicate<"!Subtarget->hasV4TOps()">;
153 def HasV5T : Predicate<"Subtarget->hasV5TOps()">;
154 def HasV5TE : Predicate<"Subtarget->hasV5TEOps()">,
155 AssemblerPredicate<"HasV5TEOps">;
156 def HasV6 : Predicate<"Subtarget->hasV6Ops()">,
157 AssemblerPredicate<"HasV6Ops">;
158 def NoV6 : Predicate<"!Subtarget->hasV6Ops()">;
159 def HasV6T2 : Predicate<"Subtarget->hasV6T2Ops()">,
160 AssemblerPredicate<"HasV6T2Ops">;
161 def NoV6T2 : Predicate<"!Subtarget->hasV6T2Ops()">;
162 def HasV7 : Predicate<"Subtarget->hasV7Ops()">,
163 AssemblerPredicate<"HasV7Ops">;
164 def NoVFP : Predicate<"!Subtarget->hasVFP2()">;
165 def HasVFP2 : Predicate<"Subtarget->hasVFP2()">,
166 AssemblerPredicate<"FeatureVFP2">;
167 def HasVFP3 : Predicate<"Subtarget->hasVFP3()">,
168 AssemblerPredicate<"FeatureVFP3">;
169 def HasNEON : Predicate<"Subtarget->hasNEON()">,
170 AssemblerPredicate<"FeatureNEON">;
171 def HasFP16 : Predicate<"Subtarget->hasFP16()">,
172 AssemblerPredicate<"FeatureFP16">;
173 def HasDivide : Predicate<"Subtarget->hasDivide()">,
174 AssemblerPredicate<"FeatureHWDiv">;
175 def HasT2ExtractPack : Predicate<"Subtarget->hasT2ExtractPack()">,
176 AssemblerPredicate<"FeatureT2XtPk">;
177 def HasThumb2DSP : Predicate<"Subtarget->hasThumb2DSP()">,
178 AssemblerPredicate<"FeatureDSPThumb2">;
179 def HasDB : Predicate<"Subtarget->hasDataBarrier()">,
180 AssemblerPredicate<"FeatureDB">;
181 def HasMP : Predicate<"Subtarget->hasMPExtension()">,
182 AssemblerPredicate<"FeatureMP">;
183 def UseNEONForFP : Predicate<"Subtarget->useNEONForSinglePrecisionFP()">;
184 def DontUseNEONForFP : Predicate<"!Subtarget->useNEONForSinglePrecisionFP()">;
185 def IsThumb : Predicate<"Subtarget->isThumb()">,
186 AssemblerPredicate<"ModeThumb">;
187 def IsThumb1Only : Predicate<"Subtarget->isThumb1Only()">;
188 def IsThumb2 : Predicate<"Subtarget->isThumb2()">,
189 AssemblerPredicate<"ModeThumb,FeatureThumb2">;
190 def IsARM : Predicate<"!Subtarget->isThumb()">,
191 AssemblerPredicate<"!ModeThumb">;
192 def IsDarwin : Predicate<"Subtarget->isTargetDarwin()">;
193 def IsNotDarwin : Predicate<"!Subtarget->isTargetDarwin()">;
195 // FIXME: Eventually this will be just "hasV6T2Ops".
196 def UseMovt : Predicate<"Subtarget->useMovt()">;
197 def DontUseMovt : Predicate<"!Subtarget->useMovt()">;
198 def UseFPVMLx : Predicate<"Subtarget->useFPVMLx()">;
200 //===----------------------------------------------------------------------===//
201 // ARM Flag Definitions.
203 class RegConstraint<string C> {
204 string Constraints = C;
207 //===----------------------------------------------------------------------===//
208 // ARM specific transformation functions and pattern fragments.
211 // so_imm_neg_XFORM - Return a so_imm value packed into the format described for
212 // so_imm_neg def below.
213 def so_imm_neg_XFORM : SDNodeXForm<imm, [{
214 return CurDAG->getTargetConstant(-(int)N->getZExtValue(), MVT::i32);
217 // so_imm_not_XFORM - Return a so_imm value packed into the format described for
218 // so_imm_not def below.
219 def so_imm_not_XFORM : SDNodeXForm<imm, [{
220 return CurDAG->getTargetConstant(~(int)N->getZExtValue(), MVT::i32);
223 /// imm1_15 predicate - True if the 32-bit immediate is in the range [1,15].
224 def imm1_15 : ImmLeaf<i32, [{
225 return (int32_t)Imm >= 1 && (int32_t)Imm < 16;
228 /// imm16_31 predicate - True if the 32-bit immediate is in the range [16,31].
229 def imm16_31 : ImmLeaf<i32, [{
230 return (int32_t)Imm >= 16 && (int32_t)Imm < 32;
235 return ARM_AM::getSOImmVal(-(uint32_t)N->getZExtValue()) != -1;
236 }], so_imm_neg_XFORM>;
240 return ARM_AM::getSOImmVal(~(uint32_t)N->getZExtValue()) != -1;
241 }], so_imm_not_XFORM>;
243 // sext_16_node predicate - True if the SDNode is sign-extended 16 or more bits.
244 def sext_16_node : PatLeaf<(i32 GPR:$a), [{
245 return CurDAG->ComputeNumSignBits(SDValue(N,0)) >= 17;
248 /// Split a 32-bit immediate into two 16 bit parts.
249 def hi16 : SDNodeXForm<imm, [{
250 return CurDAG->getTargetConstant((uint32_t)N->getZExtValue() >> 16, MVT::i32);
253 def lo16AllZero : PatLeaf<(i32 imm), [{
254 // Returns true if all low 16-bits are 0.
255 return (((uint32_t)N->getZExtValue()) & 0xFFFFUL) == 0;
258 /// imm0_65535 predicate - True if the 32-bit immediate is in the range
260 def imm0_65535 : ImmLeaf<i32, [{
261 return Imm >= 0 && Imm < 65536;
264 class BinOpFrag<dag res> : PatFrag<(ops node:$LHS, node:$RHS), res>;
265 class UnOpFrag <dag res> : PatFrag<(ops node:$Src), res>;
267 /// adde and sube predicates - True based on whether the carry flag output
268 /// will be needed or not.
269 def adde_dead_carry :
270 PatFrag<(ops node:$LHS, node:$RHS), (adde node:$LHS, node:$RHS),
271 [{return !N->hasAnyUseOfValue(1);}]>;
272 def sube_dead_carry :
273 PatFrag<(ops node:$LHS, node:$RHS), (sube node:$LHS, node:$RHS),
274 [{return !N->hasAnyUseOfValue(1);}]>;
275 def adde_live_carry :
276 PatFrag<(ops node:$LHS, node:$RHS), (adde node:$LHS, node:$RHS),
277 [{return N->hasAnyUseOfValue(1);}]>;
278 def sube_live_carry :
279 PatFrag<(ops node:$LHS, node:$RHS), (sube node:$LHS, node:$RHS),
280 [{return N->hasAnyUseOfValue(1);}]>;
282 // An 'and' node with a single use.
283 def and_su : PatFrag<(ops node:$lhs, node:$rhs), (and node:$lhs, node:$rhs), [{
284 return N->hasOneUse();
287 // An 'xor' node with a single use.
288 def xor_su : PatFrag<(ops node:$lhs, node:$rhs), (xor node:$lhs, node:$rhs), [{
289 return N->hasOneUse();
292 // An 'fmul' node with a single use.
293 def fmul_su : PatFrag<(ops node:$lhs, node:$rhs), (fmul node:$lhs, node:$rhs),[{
294 return N->hasOneUse();
297 // An 'fadd' node which checks for single non-hazardous use.
298 def fadd_mlx : PatFrag<(ops node:$lhs, node:$rhs),(fadd node:$lhs, node:$rhs),[{
299 return hasNoVMLxHazardUse(N);
302 // An 'fsub' node which checks for single non-hazardous use.
303 def fsub_mlx : PatFrag<(ops node:$lhs, node:$rhs),(fsub node:$lhs, node:$rhs),[{
304 return hasNoVMLxHazardUse(N);
307 //===----------------------------------------------------------------------===//
308 // Operand Definitions.
312 // FIXME: rename brtarget to t2_brtarget
313 def brtarget : Operand<OtherVT> {
314 let EncoderMethod = "getBranchTargetOpValue";
317 // FIXME: get rid of this one?
318 def uncondbrtarget : Operand<OtherVT> {
319 let EncoderMethod = "getUnconditionalBranchTargetOpValue";
322 // Branch target for ARM. Handles conditional/unconditional
323 def br_target : Operand<OtherVT> {
324 let EncoderMethod = "getARMBranchTargetOpValue";
328 // FIXME: rename bltarget to t2_bl_target?
329 def bltarget : Operand<i32> {
330 // Encoded the same as branch targets.
331 let EncoderMethod = "getBranchTargetOpValue";
334 // Call target for ARM. Handles conditional/unconditional
335 // FIXME: rename bl_target to t2_bltarget?
336 def bl_target : Operand<i32> {
337 // Encoded the same as branch targets.
338 let EncoderMethod = "getARMBranchTargetOpValue";
342 // A list of registers separated by comma. Used by load/store multiple.
343 def RegListAsmOperand : AsmOperandClass {
344 let Name = "RegList";
345 let SuperClasses = [];
348 def DPRRegListAsmOperand : AsmOperandClass {
349 let Name = "DPRRegList";
350 let SuperClasses = [];
353 def SPRRegListAsmOperand : AsmOperandClass {
354 let Name = "SPRRegList";
355 let SuperClasses = [];
358 def reglist : Operand<i32> {
359 let EncoderMethod = "getRegisterListOpValue";
360 let ParserMatchClass = RegListAsmOperand;
361 let PrintMethod = "printRegisterList";
364 def dpr_reglist : Operand<i32> {
365 let EncoderMethod = "getRegisterListOpValue";
366 let ParserMatchClass = DPRRegListAsmOperand;
367 let PrintMethod = "printRegisterList";
370 def spr_reglist : Operand<i32> {
371 let EncoderMethod = "getRegisterListOpValue";
372 let ParserMatchClass = SPRRegListAsmOperand;
373 let PrintMethod = "printRegisterList";
376 // An operand for the CONSTPOOL_ENTRY pseudo-instruction.
377 def cpinst_operand : Operand<i32> {
378 let PrintMethod = "printCPInstOperand";
382 def pclabel : Operand<i32> {
383 let PrintMethod = "printPCLabel";
386 // ADR instruction labels.
387 def adrlabel : Operand<i32> {
388 let EncoderMethod = "getAdrLabelOpValue";
391 def neon_vcvt_imm32 : Operand<i32> {
392 let EncoderMethod = "getNEONVcvtImm32OpValue";
395 // rot_imm: An integer that encodes a rotate amount. Must be 8, 16, or 24.
396 def rot_imm : Operand<i32>, ImmLeaf<i32, [{
397 int32_t v = (int32_t)Imm;
398 return v == 8 || v == 16 || v == 24; }]> {
399 let EncoderMethod = "getRotImmOpValue";
402 def ShifterAsmOperand : AsmOperandClass {
403 let Name = "Shifter";
404 let SuperClasses = [];
407 // shift_imm: An integer that encodes a shift amount and the type of shift
408 // (currently either asr or lsl) using the same encoding used for the
409 // immediates in so_reg operands.
410 def shift_imm : Operand<i32> {
411 let PrintMethod = "printShiftImmOperand";
412 let ParserMatchClass = ShifterAsmOperand;
415 // shifter_operand operands: so_reg and so_imm.
416 def so_reg : Operand<i32>, // reg reg imm
417 ComplexPattern<i32, 3, "SelectShifterOperandReg",
418 [shl,srl,sra,rotr]> {
419 let EncoderMethod = "getSORegOpValue";
420 let PrintMethod = "printSORegOperand";
421 let MIOperandInfo = (ops GPR, GPR, shift_imm);
423 def shift_so_reg : Operand<i32>, // reg reg imm
424 ComplexPattern<i32, 3, "SelectShiftShifterOperandReg",
425 [shl,srl,sra,rotr]> {
426 let EncoderMethod = "getSORegOpValue";
427 let PrintMethod = "printSORegOperand";
428 let MIOperandInfo = (ops GPR, GPR, shift_imm);
431 // so_imm - Match a 32-bit shifter_operand immediate operand, which is an
432 // 8-bit immediate rotated by an arbitrary number of bits.
433 def so_imm : Operand<i32>, ImmLeaf<i32, [{
434 return ARM_AM::getSOImmVal(Imm) != -1;
436 let EncoderMethod = "getSOImmOpValue";
437 let PrintMethod = "printSOImmOperand";
440 // Break so_imm's up into two pieces. This handles immediates with up to 16
441 // bits set in them. This uses so_imm2part to match and so_imm2part_[12] to
442 // get the first/second pieces.
443 def so_imm2part : PatLeaf<(imm), [{
444 return ARM_AM::isSOImmTwoPartVal((unsigned)N->getZExtValue());
447 /// arm_i32imm - True for +V6T2, or true only if so_imm2part is true.
449 def arm_i32imm : PatLeaf<(imm), [{
450 if (Subtarget->hasV6T2Ops())
452 return ARM_AM::isSOImmTwoPartVal((unsigned)N->getZExtValue());
455 /// imm0_31 predicate - True if the 32-bit immediate is in the range [0,31].
456 def imm0_31 : Operand<i32>, ImmLeaf<i32, [{
457 return Imm >= 0 && Imm < 32;
460 /// imm0_31_m1 - Matches and prints like imm0_31, but encodes as 'value - 1'.
461 def imm0_31_m1 : Operand<i32>, ImmLeaf<i32, [{
462 return Imm >= 0 && Imm < 32;
464 let EncoderMethod = "getImmMinusOneOpValue";
467 // i32imm_hilo16 - For movt/movw - sets the MC Encoder method.
468 // The imm is split into imm{15-12}, imm{11-0}
470 def i32imm_hilo16 : Operand<i32> {
471 let EncoderMethod = "getHiLo16ImmOpValue";
474 /// bf_inv_mask_imm predicate - An AND mask to clear an arbitrary width bitfield
476 def bf_inv_mask_imm : Operand<i32>,
478 return ARM::isBitFieldInvertedMask(N->getZExtValue());
480 let EncoderMethod = "getBitfieldInvertedMaskOpValue";
481 let PrintMethod = "printBitfieldInvMaskImmOperand";
484 /// lsb_pos_imm - position of the lsb bit, used by BFI4p and t2BFI4p
485 def lsb_pos_imm : Operand<i32>, ImmLeaf<i32, [{
486 return isInt<5>(Imm);
489 /// width_imm - number of bits to be copied, used by BFI4p and t2BFI4p
490 def width_imm : Operand<i32>, ImmLeaf<i32, [{
491 return Imm > 0 && Imm <= 32;
493 let EncoderMethod = "getMsbOpValue";
496 def ssat_imm : Operand<i32>, ImmLeaf<i32, [{
497 return Imm > 0 && Imm <= 32;
499 let EncoderMethod = "getSsatBitPosValue";
502 // Define ARM specific addressing modes.
504 def MemMode2AsmOperand : AsmOperandClass {
505 let Name = "MemMode2";
506 let SuperClasses = [];
507 let ParserMethod = "tryParseMemMode2Operand";
510 def MemMode3AsmOperand : AsmOperandClass {
511 let Name = "MemMode3";
512 let SuperClasses = [];
513 let ParserMethod = "tryParseMemMode3Operand";
516 // addrmode_imm12 := reg +/- imm12
518 def addrmode_imm12 : Operand<i32>,
519 ComplexPattern<i32, 2, "SelectAddrModeImm12", []> {
520 // 12-bit immediate operand. Note that instructions using this encode
521 // #0 and #-0 differently. We flag #-0 as the magic value INT32_MIN. All other
522 // immediate values are as normal.
524 let EncoderMethod = "getAddrModeImm12OpValue";
525 let PrintMethod = "printAddrModeImm12Operand";
526 let MIOperandInfo = (ops GPR:$base, i32imm:$offsimm);
528 // ldst_so_reg := reg +/- reg shop imm
530 def ldst_so_reg : Operand<i32>,
531 ComplexPattern<i32, 3, "SelectLdStSOReg", []> {
532 let EncoderMethod = "getLdStSORegOpValue";
533 // FIXME: Simplify the printer
534 let PrintMethod = "printAddrMode2Operand";
535 let MIOperandInfo = (ops GPR:$base, GPR:$offsreg, i32imm:$offsimm);
538 // addrmode2 := reg +/- imm12
539 // := reg +/- reg shop imm
541 def addrmode2 : Operand<i32>,
542 ComplexPattern<i32, 3, "SelectAddrMode2", []> {
543 let EncoderMethod = "getAddrMode2OpValue";
544 let PrintMethod = "printAddrMode2Operand";
545 let ParserMatchClass = MemMode2AsmOperand;
546 let MIOperandInfo = (ops GPR:$base, GPR:$offsreg, i32imm:$offsimm);
549 def am2offset : Operand<i32>,
550 ComplexPattern<i32, 2, "SelectAddrMode2Offset",
551 [], [SDNPWantRoot]> {
552 let EncoderMethod = "getAddrMode2OffsetOpValue";
553 let PrintMethod = "printAddrMode2OffsetOperand";
554 let MIOperandInfo = (ops GPR, i32imm);
557 // addrmode3 := reg +/- reg
558 // addrmode3 := reg +/- imm8
560 def addrmode3 : Operand<i32>,
561 ComplexPattern<i32, 3, "SelectAddrMode3", []> {
562 let EncoderMethod = "getAddrMode3OpValue";
563 let PrintMethod = "printAddrMode3Operand";
564 let ParserMatchClass = MemMode3AsmOperand;
565 let MIOperandInfo = (ops GPR:$base, GPR:$offsreg, i32imm:$offsimm);
568 def am3offset : Operand<i32>,
569 ComplexPattern<i32, 2, "SelectAddrMode3Offset",
570 [], [SDNPWantRoot]> {
571 let EncoderMethod = "getAddrMode3OffsetOpValue";
572 let PrintMethod = "printAddrMode3OffsetOperand";
573 let MIOperandInfo = (ops GPR, i32imm);
576 // ldstm_mode := {ia, ib, da, db}
578 def ldstm_mode : OptionalDefOperand<OtherVT, (ops i32), (ops (i32 1))> {
579 let EncoderMethod = "getLdStmModeOpValue";
580 let PrintMethod = "printLdStmModeOperand";
583 def MemMode5AsmOperand : AsmOperandClass {
584 let Name = "MemMode5";
585 let SuperClasses = [];
588 // addrmode5 := reg +/- imm8*4
590 def addrmode5 : Operand<i32>,
591 ComplexPattern<i32, 2, "SelectAddrMode5", []> {
592 let PrintMethod = "printAddrMode5Operand";
593 let MIOperandInfo = (ops GPR:$base, i32imm);
594 let ParserMatchClass = MemMode5AsmOperand;
595 let EncoderMethod = "getAddrMode5OpValue";
598 // addrmode6 := reg with optional alignment
600 def addrmode6 : Operand<i32>,
601 ComplexPattern<i32, 2, "SelectAddrMode6", [], [SDNPWantParent]>{
602 let PrintMethod = "printAddrMode6Operand";
603 let MIOperandInfo = (ops GPR:$addr, i32imm);
604 let EncoderMethod = "getAddrMode6AddressOpValue";
607 def am6offset : Operand<i32>,
608 ComplexPattern<i32, 1, "SelectAddrMode6Offset",
609 [], [SDNPWantRoot]> {
610 let PrintMethod = "printAddrMode6OffsetOperand";
611 let MIOperandInfo = (ops GPR);
612 let EncoderMethod = "getAddrMode6OffsetOpValue";
615 // Special version of addrmode6 to handle alignment encoding for VST1/VLD1
616 // (single element from one lane) for size 32.
617 def addrmode6oneL32 : Operand<i32>,
618 ComplexPattern<i32, 2, "SelectAddrMode6", [], [SDNPWantParent]>{
619 let PrintMethod = "printAddrMode6Operand";
620 let MIOperandInfo = (ops GPR:$addr, i32imm);
621 let EncoderMethod = "getAddrMode6OneLane32AddressOpValue";
624 // Special version of addrmode6 to handle alignment encoding for VLD-dup
625 // instructions, specifically VLD4-dup.
626 def addrmode6dup : Operand<i32>,
627 ComplexPattern<i32, 2, "SelectAddrMode6", [], [SDNPWantParent]>{
628 let PrintMethod = "printAddrMode6Operand";
629 let MIOperandInfo = (ops GPR:$addr, i32imm);
630 let EncoderMethod = "getAddrMode6DupAddressOpValue";
633 // addrmodepc := pc + reg
635 def addrmodepc : Operand<i32>,
636 ComplexPattern<i32, 2, "SelectAddrModePC", []> {
637 let PrintMethod = "printAddrModePCOperand";
638 let MIOperandInfo = (ops GPR, i32imm);
641 def MemMode7AsmOperand : AsmOperandClass {
642 let Name = "MemMode7";
643 let SuperClasses = [];
647 // Used by load/store exclusive instructions. Useful to enable right assembly
648 // parsing and printing. Not used for any codegen matching.
650 def addrmode7 : Operand<i32> {
651 let PrintMethod = "printAddrMode7Operand";
652 let MIOperandInfo = (ops GPR);
653 let ParserMatchClass = MemMode7AsmOperand;
656 def nohash_imm : Operand<i32> {
657 let PrintMethod = "printNoHashImmediate";
660 def CoprocNumAsmOperand : AsmOperandClass {
661 let Name = "CoprocNum";
662 let SuperClasses = [];
663 let ParserMethod = "tryParseCoprocNumOperand";
666 def CoprocRegAsmOperand : AsmOperandClass {
667 let Name = "CoprocReg";
668 let SuperClasses = [];
669 let ParserMethod = "tryParseCoprocRegOperand";
672 def p_imm : Operand<i32> {
673 let PrintMethod = "printPImmediate";
674 let ParserMatchClass = CoprocNumAsmOperand;
677 def c_imm : Operand<i32> {
678 let PrintMethod = "printCImmediate";
679 let ParserMatchClass = CoprocRegAsmOperand;
682 //===----------------------------------------------------------------------===//
684 include "ARMInstrFormats.td"
686 //===----------------------------------------------------------------------===//
687 // Multiclass helpers...
690 /// AsI1_bin_irs - Defines a set of (op r, {so_imm|r|so_reg}) patterns for a
691 /// binop that produces a value.
692 multiclass AsI1_bin_irs<bits<4> opcod, string opc,
693 InstrItinClass iii, InstrItinClass iir, InstrItinClass iis,
694 PatFrag opnode, string baseOpc, bit Commutable = 0> {
695 // The register-immediate version is re-materializable. This is useful
696 // in particular for taking the address of a local.
697 let isReMaterializable = 1 in {
698 def ri : AsI1<opcod, (outs GPR:$Rd), (ins GPR:$Rn, so_imm:$imm), DPFrm,
699 iii, opc, "\t$Rd, $Rn, $imm",
700 [(set GPR:$Rd, (opnode GPR:$Rn, so_imm:$imm))]> {
705 let Inst{19-16} = Rn;
706 let Inst{15-12} = Rd;
707 let Inst{11-0} = imm;
710 def rr : AsI1<opcod, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm), DPFrm,
711 iir, opc, "\t$Rd, $Rn, $Rm",
712 [(set GPR:$Rd, (opnode GPR:$Rn, GPR:$Rm))]> {
717 let isCommutable = Commutable;
718 let Inst{19-16} = Rn;
719 let Inst{15-12} = Rd;
720 let Inst{11-4} = 0b00000000;
723 def rs : AsI1<opcod, (outs GPR:$Rd), (ins GPR:$Rn, so_reg:$shift), DPSoRegFrm,
724 iis, opc, "\t$Rd, $Rn, $shift",
725 [(set GPR:$Rd, (opnode GPR:$Rn, so_reg:$shift))]> {
730 let Inst{19-16} = Rn;
731 let Inst{15-12} = Rd;
732 let Inst{11-0} = shift;
735 // Assembly aliases for optional destination operand when it's the same
736 // as the source operand.
737 def : InstAlias<!strconcat(opc, "${s}${p} $Rdn, $imm"),
738 (!cast<Instruction>(!strconcat(baseOpc, "ri")) GPR:$Rdn, GPR:$Rdn,
739 so_imm:$imm, pred:$p,
742 def : InstAlias<!strconcat(opc, "${s}${p} $Rdn, $Rm"),
743 (!cast<Instruction>(!strconcat(baseOpc, "rr")) GPR:$Rdn, GPR:$Rdn,
747 def : InstAlias<!strconcat(opc, "${s}${p} $Rdn, $shift"),
748 (!cast<Instruction>(!strconcat(baseOpc, "rs")) GPR:$Rdn, GPR:$Rdn,
749 so_reg:$shift, pred:$p,
754 /// AI1_bin_s_irs - Similar to AsI1_bin_irs except it sets the 's' bit so the
755 /// instruction modifies the CPSR register.
756 let isCodeGenOnly = 1, Defs = [CPSR] in {
757 multiclass AI1_bin_s_irs<bits<4> opcod, string opc,
758 InstrItinClass iii, InstrItinClass iir, InstrItinClass iis,
759 PatFrag opnode, bit Commutable = 0> {
760 def ri : AI1<opcod, (outs GPR:$Rd), (ins GPR:$Rn, so_imm:$imm), DPFrm,
761 iii, opc, "\t$Rd, $Rn, $imm",
762 [(set GPR:$Rd, (opnode GPR:$Rn, so_imm:$imm))]> {
768 let Inst{19-16} = Rn;
769 let Inst{15-12} = Rd;
770 let Inst{11-0} = imm;
772 def rr : AI1<opcod, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm), DPFrm,
773 iir, opc, "\t$Rd, $Rn, $Rm",
774 [(set GPR:$Rd, (opnode GPR:$Rn, GPR:$Rm))]> {
778 let isCommutable = Commutable;
781 let Inst{19-16} = Rn;
782 let Inst{15-12} = Rd;
783 let Inst{11-4} = 0b00000000;
786 def rs : AI1<opcod, (outs GPR:$Rd), (ins GPR:$Rn, so_reg:$shift), DPSoRegFrm,
787 iis, opc, "\t$Rd, $Rn, $shift",
788 [(set GPR:$Rd, (opnode GPR:$Rn, so_reg:$shift))]> {
794 let Inst{19-16} = Rn;
795 let Inst{15-12} = Rd;
796 let Inst{11-0} = shift;
801 /// AI1_cmp_irs - Defines a set of (op r, {so_imm|r|so_reg}) cmp / test
802 /// patterns. Similar to AsI1_bin_irs except the instruction does not produce
803 /// a explicit result, only implicitly set CPSR.
804 let isCompare = 1, Defs = [CPSR] in {
805 multiclass AI1_cmp_irs<bits<4> opcod, string opc,
806 InstrItinClass iii, InstrItinClass iir, InstrItinClass iis,
807 PatFrag opnode, bit Commutable = 0> {
808 def ri : AI1<opcod, (outs), (ins GPR:$Rn, so_imm:$imm), DPFrm, iii,
810 [(opnode GPR:$Rn, so_imm:$imm)]> {
815 let Inst{19-16} = Rn;
816 let Inst{15-12} = 0b0000;
817 let Inst{11-0} = imm;
819 def rr : AI1<opcod, (outs), (ins GPR:$Rn, GPR:$Rm), DPFrm, iir,
821 [(opnode GPR:$Rn, GPR:$Rm)]> {
824 let isCommutable = Commutable;
827 let Inst{19-16} = Rn;
828 let Inst{15-12} = 0b0000;
829 let Inst{11-4} = 0b00000000;
832 def rs : AI1<opcod, (outs), (ins GPR:$Rn, so_reg:$shift), DPSoRegFrm, iis,
833 opc, "\t$Rn, $shift",
834 [(opnode GPR:$Rn, so_reg:$shift)]> {
839 let Inst{19-16} = Rn;
840 let Inst{15-12} = 0b0000;
841 let Inst{11-0} = shift;
846 /// AI_ext_rrot - A unary operation with two forms: one whose operand is a
847 /// register and one whose operand is a register rotated by 8/16/24.
848 /// FIXME: Remove the 'r' variant. Its rot_imm is zero.
849 multiclass AI_ext_rrot<bits<8> opcod, string opc, PatFrag opnode> {
850 def r : AExtI<opcod, (outs GPR:$Rd), (ins GPR:$Rm),
851 IIC_iEXTr, opc, "\t$Rd, $Rm",
852 [(set GPR:$Rd, (opnode GPR:$Rm))]>,
853 Requires<[IsARM, HasV6]> {
856 let Inst{19-16} = 0b1111;
857 let Inst{15-12} = Rd;
858 let Inst{11-10} = 0b00;
861 def r_rot : AExtI<opcod, (outs GPR:$Rd), (ins GPR:$Rm, rot_imm:$rot),
862 IIC_iEXTr, opc, "\t$Rd, $Rm, ror $rot",
863 [(set GPR:$Rd, (opnode (rotr GPR:$Rm, rot_imm:$rot)))]>,
864 Requires<[IsARM, HasV6]> {
868 let Inst{19-16} = 0b1111;
869 let Inst{15-12} = Rd;
870 let Inst{11-10} = rot;
875 multiclass AI_ext_rrot_np<bits<8> opcod, string opc> {
876 def r : AExtI<opcod, (outs GPR:$Rd), (ins GPR:$Rm),
877 IIC_iEXTr, opc, "\t$Rd, $Rm",
878 [/* For disassembly only; pattern left blank */]>,
879 Requires<[IsARM, HasV6]> {
880 let Inst{19-16} = 0b1111;
881 let Inst{11-10} = 0b00;
883 def r_rot : AExtI<opcod, (outs GPR:$Rd), (ins GPR:$Rm, rot_imm:$rot),
884 IIC_iEXTr, opc, "\t$Rd, $Rm, ror $rot",
885 [/* For disassembly only; pattern left blank */]>,
886 Requires<[IsARM, HasV6]> {
888 let Inst{19-16} = 0b1111;
889 let Inst{11-10} = rot;
893 /// AI_exta_rrot - A binary operation with two forms: one whose operand is a
894 /// register and one whose operand is a register rotated by 8/16/24.
895 multiclass AI_exta_rrot<bits<8> opcod, string opc, PatFrag opnode> {
896 def rr : AExtI<opcod, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm),
897 IIC_iEXTAr, opc, "\t$Rd, $Rn, $Rm",
898 [(set GPR:$Rd, (opnode GPR:$Rn, GPR:$Rm))]>,
899 Requires<[IsARM, HasV6]> {
903 let Inst{19-16} = Rn;
904 let Inst{15-12} = Rd;
905 let Inst{11-10} = 0b00;
906 let Inst{9-4} = 0b000111;
909 def rr_rot : AExtI<opcod, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm,
911 IIC_iEXTAr, opc, "\t$Rd, $Rn, $Rm, ror $rot",
912 [(set GPR:$Rd, (opnode GPR:$Rn,
913 (rotr GPR:$Rm, rot_imm:$rot)))]>,
914 Requires<[IsARM, HasV6]> {
919 let Inst{19-16} = Rn;
920 let Inst{15-12} = Rd;
921 let Inst{11-10} = rot;
922 let Inst{9-4} = 0b000111;
927 // For disassembly only.
928 multiclass AI_exta_rrot_np<bits<8> opcod, string opc> {
929 def rr : AExtI<opcod, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm),
930 IIC_iEXTAr, opc, "\t$Rd, $Rn, $Rm",
931 [/* For disassembly only; pattern left blank */]>,
932 Requires<[IsARM, HasV6]> {
933 let Inst{11-10} = 0b00;
935 def rr_rot : AExtI<opcod, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm,
937 IIC_iEXTAr, opc, "\t$Rd, $Rn, $Rm, ror $rot",
938 [/* For disassembly only; pattern left blank */]>,
939 Requires<[IsARM, HasV6]> {
942 let Inst{19-16} = Rn;
943 let Inst{11-10} = rot;
947 /// AI1_adde_sube_irs - Define instructions and patterns for adde and sube.
948 let Uses = [CPSR] in {
949 multiclass AI1_adde_sube_irs<bits<4> opcod, string opc, PatFrag opnode,
950 bit Commutable = 0> {
951 def ri : AsI1<opcod, (outs GPR:$Rd), (ins GPR:$Rn, so_imm:$imm),
952 DPFrm, IIC_iALUi, opc, "\t$Rd, $Rn, $imm",
953 [(set GPR:$Rd, (opnode GPR:$Rn, so_imm:$imm))]>,
959 let Inst{15-12} = Rd;
960 let Inst{19-16} = Rn;
961 let Inst{11-0} = imm;
963 def rr : AsI1<opcod, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm),
964 DPFrm, IIC_iALUr, opc, "\t$Rd, $Rn, $Rm",
965 [(set GPR:$Rd, (opnode GPR:$Rn, GPR:$Rm))]>,
970 let Inst{11-4} = 0b00000000;
972 let isCommutable = Commutable;
974 let Inst{15-12} = Rd;
975 let Inst{19-16} = Rn;
977 def rs : AsI1<opcod, (outs GPR:$Rd), (ins GPR:$Rn, so_reg:$shift),
978 DPSoRegFrm, IIC_iALUsr, opc, "\t$Rd, $Rn, $shift",
979 [(set GPR:$Rd, (opnode GPR:$Rn, so_reg:$shift))]>,
985 let Inst{11-0} = shift;
986 let Inst{15-12} = Rd;
987 let Inst{19-16} = Rn;
992 // Carry setting variants
993 // NOTE: CPSR def omitted because it will be handled by the custom inserter.
994 let usesCustomInserter = 1 in {
995 multiclass AI1_adde_sube_s_irs<PatFrag opnode, bit Commutable = 0> {
996 def ri : ARMPseudoInst<(outs GPR:$Rd), (ins GPR:$Rn, so_imm:$imm),
997 Size4Bytes, IIC_iALUi,
998 [(set GPR:$Rd, (opnode GPR:$Rn, so_imm:$imm))]>;
999 def rr : ARMPseudoInst<(outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm),
1000 Size4Bytes, IIC_iALUr,
1001 [(set GPR:$Rd, (opnode GPR:$Rn, GPR:$Rm))]> {
1002 let isCommutable = Commutable;
1004 def rs : ARMPseudoInst<(outs GPR:$Rd), (ins GPR:$Rn, so_reg:$shift),
1005 Size4Bytes, IIC_iALUsr,
1006 [(set GPR:$Rd, (opnode GPR:$Rn, so_reg:$shift))]>;
1010 let canFoldAsLoad = 1, isReMaterializable = 1 in {
1011 multiclass AI_ldr1<bit isByte, string opc, InstrItinClass iii,
1012 InstrItinClass iir, PatFrag opnode> {
1013 // Note: We use the complex addrmode_imm12 rather than just an input
1014 // GPR and a constrained immediate so that we can use this to match
1015 // frame index references and avoid matching constant pool references.
1016 def i12: AI2ldst<0b010, 1, isByte, (outs GPR:$Rt), (ins addrmode_imm12:$addr),
1017 AddrMode_i12, LdFrm, iii, opc, "\t$Rt, $addr",
1018 [(set GPR:$Rt, (opnode addrmode_imm12:$addr))]> {
1021 let Inst{23} = addr{12}; // U (add = ('U' == 1))
1022 let Inst{19-16} = addr{16-13}; // Rn
1023 let Inst{15-12} = Rt;
1024 let Inst{11-0} = addr{11-0}; // imm12
1026 def rs : AI2ldst<0b011, 1, isByte, (outs GPR:$Rt), (ins ldst_so_reg:$shift),
1027 AddrModeNone, LdFrm, iir, opc, "\t$Rt, $shift",
1028 [(set GPR:$Rt, (opnode ldst_so_reg:$shift))]> {
1031 let shift{4} = 0; // Inst{4} = 0
1032 let Inst{23} = shift{12}; // U (add = ('U' == 1))
1033 let Inst{19-16} = shift{16-13}; // Rn
1034 let Inst{15-12} = Rt;
1035 let Inst{11-0} = shift{11-0};
1040 multiclass AI_str1<bit isByte, string opc, InstrItinClass iii,
1041 InstrItinClass iir, PatFrag opnode> {
1042 // Note: We use the complex addrmode_imm12 rather than just an input
1043 // GPR and a constrained immediate so that we can use this to match
1044 // frame index references and avoid matching constant pool references.
1045 def i12 : AI2ldst<0b010, 0, isByte, (outs),
1046 (ins GPR:$Rt, addrmode_imm12:$addr),
1047 AddrMode_i12, StFrm, iii, opc, "\t$Rt, $addr",
1048 [(opnode GPR:$Rt, addrmode_imm12:$addr)]> {
1051 let Inst{23} = addr{12}; // U (add = ('U' == 1))
1052 let Inst{19-16} = addr{16-13}; // Rn
1053 let Inst{15-12} = Rt;
1054 let Inst{11-0} = addr{11-0}; // imm12
1056 def rs : AI2ldst<0b011, 0, isByte, (outs), (ins GPR:$Rt, ldst_so_reg:$shift),
1057 AddrModeNone, StFrm, iir, opc, "\t$Rt, $shift",
1058 [(opnode GPR:$Rt, ldst_so_reg:$shift)]> {
1061 let shift{4} = 0; // Inst{4} = 0
1062 let Inst{23} = shift{12}; // U (add = ('U' == 1))
1063 let Inst{19-16} = shift{16-13}; // Rn
1064 let Inst{15-12} = Rt;
1065 let Inst{11-0} = shift{11-0};
1068 //===----------------------------------------------------------------------===//
1070 //===----------------------------------------------------------------------===//
1072 //===----------------------------------------------------------------------===//
1073 // Miscellaneous Instructions.
1076 /// CONSTPOOL_ENTRY - This instruction represents a floating constant pool in
1077 /// the function. The first operand is the ID# for this instruction, the second
1078 /// is the index into the MachineConstantPool that this is, the third is the
1079 /// size in bytes of this constant pool entry.
1080 let neverHasSideEffects = 1, isNotDuplicable = 1 in
1081 def CONSTPOOL_ENTRY :
1082 PseudoInst<(outs), (ins cpinst_operand:$instid, cpinst_operand:$cpidx,
1083 i32imm:$size), NoItinerary, []>;
1085 // FIXME: Marking these as hasSideEffects is necessary to prevent machine DCE
1086 // from removing one half of the matched pairs. That breaks PEI, which assumes
1087 // these will always be in pairs, and asserts if it finds otherwise. Better way?
1088 let Defs = [SP], Uses = [SP], hasSideEffects = 1 in {
1089 def ADJCALLSTACKUP :
1090 PseudoInst<(outs), (ins i32imm:$amt1, i32imm:$amt2, pred:$p), NoItinerary,
1091 [(ARMcallseq_end timm:$amt1, timm:$amt2)]>;
1093 def ADJCALLSTACKDOWN :
1094 PseudoInst<(outs), (ins i32imm:$amt, pred:$p), NoItinerary,
1095 [(ARMcallseq_start timm:$amt)]>;
1098 def NOP : AI<(outs), (ins), MiscFrm, NoItinerary, "nop", "",
1099 [/* For disassembly only; pattern left blank */]>,
1100 Requires<[IsARM, HasV6T2]> {
1101 let Inst{27-16} = 0b001100100000;
1102 let Inst{15-8} = 0b11110000;
1103 let Inst{7-0} = 0b00000000;
1106 def YIELD : AI<(outs), (ins), MiscFrm, NoItinerary, "yield", "",
1107 [/* For disassembly only; pattern left blank */]>,
1108 Requires<[IsARM, HasV6T2]> {
1109 let Inst{27-16} = 0b001100100000;
1110 let Inst{15-8} = 0b11110000;
1111 let Inst{7-0} = 0b00000001;
1114 def WFE : AI<(outs), (ins), MiscFrm, NoItinerary, "wfe", "",
1115 [/* For disassembly only; pattern left blank */]>,
1116 Requires<[IsARM, HasV6T2]> {
1117 let Inst{27-16} = 0b001100100000;
1118 let Inst{15-8} = 0b11110000;
1119 let Inst{7-0} = 0b00000010;
1122 def WFI : AI<(outs), (ins), MiscFrm, NoItinerary, "wfi", "",
1123 [/* For disassembly only; pattern left blank */]>,
1124 Requires<[IsARM, HasV6T2]> {
1125 let Inst{27-16} = 0b001100100000;
1126 let Inst{15-8} = 0b11110000;
1127 let Inst{7-0} = 0b00000011;
1130 def SEL : AI<(outs GPR:$dst), (ins GPR:$a, GPR:$b), DPFrm, NoItinerary, "sel",
1132 [/* For disassembly only; pattern left blank */]>,
1133 Requires<[IsARM, HasV6]> {
1138 let Inst{15-12} = Rd;
1139 let Inst{19-16} = Rn;
1140 let Inst{27-20} = 0b01101000;
1141 let Inst{7-4} = 0b1011;
1142 let Inst{11-8} = 0b1111;
1145 def SEV : AI<(outs), (ins), MiscFrm, NoItinerary, "sev", "",
1146 [/* For disassembly only; pattern left blank */]>,
1147 Requires<[IsARM, HasV6T2]> {
1148 let Inst{27-16} = 0b001100100000;
1149 let Inst{15-8} = 0b11110000;
1150 let Inst{7-0} = 0b00000100;
1153 // The i32imm operand $val can be used by a debugger to store more information
1154 // about the breakpoint.
1155 def BKPT : AI<(outs), (ins i32imm:$val), MiscFrm, NoItinerary, "bkpt", "\t$val",
1156 [/* For disassembly only; pattern left blank */]>,
1159 let Inst{3-0} = val{3-0};
1160 let Inst{19-8} = val{15-4};
1161 let Inst{27-20} = 0b00010010;
1162 let Inst{7-4} = 0b0111;
1165 // Change Processor State is a system instruction -- for disassembly and
1167 // FIXME: Since the asm parser has currently no clean way to handle optional
1168 // operands, create 3 versions of the same instruction. Once there's a clean
1169 // framework to represent optional operands, change this behavior.
1170 class CPS<dag iops, string asm_ops>
1171 : AXI<(outs), iops, MiscFrm, NoItinerary, !strconcat("cps", asm_ops),
1172 [/* For disassembly only; pattern left blank */]>, Requires<[IsARM]> {
1178 let Inst{31-28} = 0b1111;
1179 let Inst{27-20} = 0b00010000;
1180 let Inst{19-18} = imod;
1181 let Inst{17} = M; // Enabled if mode is set;
1183 let Inst{8-6} = iflags;
1185 let Inst{4-0} = mode;
1189 def CPS3p : CPS<(ins imod_op:$imod, iflags_op:$iflags, i32imm:$mode),
1190 "$imod\t$iflags, $mode">;
1191 let mode = 0, M = 0 in
1192 def CPS2p : CPS<(ins imod_op:$imod, iflags_op:$iflags), "$imod\t$iflags">;
1194 let imod = 0, iflags = 0, M = 1 in
1195 def CPS1p : CPS<(ins i32imm:$mode), "\t$mode">;
1197 // Preload signals the memory system of possible future data/instruction access.
1198 // These are for disassembly only.
1199 multiclass APreLoad<bits<1> read, bits<1> data, string opc> {
1201 def i12 : AXI<(outs), (ins addrmode_imm12:$addr), MiscFrm, IIC_Preload,
1202 !strconcat(opc, "\t$addr"),
1203 [(ARMPreload addrmode_imm12:$addr, (i32 read), (i32 data))]> {
1206 let Inst{31-26} = 0b111101;
1207 let Inst{25} = 0; // 0 for immediate form
1208 let Inst{24} = data;
1209 let Inst{23} = addr{12}; // U (add = ('U' == 1))
1210 let Inst{22} = read;
1211 let Inst{21-20} = 0b01;
1212 let Inst{19-16} = addr{16-13}; // Rn
1213 let Inst{15-12} = 0b1111;
1214 let Inst{11-0} = addr{11-0}; // imm12
1217 def rs : AXI<(outs), (ins ldst_so_reg:$shift), MiscFrm, IIC_Preload,
1218 !strconcat(opc, "\t$shift"),
1219 [(ARMPreload ldst_so_reg:$shift, (i32 read), (i32 data))]> {
1221 let Inst{31-26} = 0b111101;
1222 let Inst{25} = 1; // 1 for register form
1223 let Inst{24} = data;
1224 let Inst{23} = shift{12}; // U (add = ('U' == 1))
1225 let Inst{22} = read;
1226 let Inst{21-20} = 0b01;
1227 let Inst{19-16} = shift{16-13}; // Rn
1228 let Inst{15-12} = 0b1111;
1229 let Inst{11-0} = shift{11-0};
1233 defm PLD : APreLoad<1, 1, "pld">, Requires<[IsARM]>;
1234 defm PLDW : APreLoad<0, 1, "pldw">, Requires<[IsARM,HasV7,HasMP]>;
1235 defm PLI : APreLoad<1, 0, "pli">, Requires<[IsARM,HasV7]>;
1237 def SETEND : AXI<(outs),(ins setend_op:$end), MiscFrm, NoItinerary,
1239 [/* For disassembly only; pattern left blank */]>,
1242 let Inst{31-10} = 0b1111000100000001000000;
1247 def DBG : AI<(outs), (ins i32imm:$opt), MiscFrm, NoItinerary, "dbg", "\t$opt",
1248 [/* For disassembly only; pattern left blank */]>,
1249 Requires<[IsARM, HasV7]> {
1251 let Inst{27-4} = 0b001100100000111100001111;
1252 let Inst{3-0} = opt;
1255 // A5.4 Permanently UNDEFINED instructions.
1256 let isBarrier = 1, isTerminator = 1 in
1257 def TRAP : AXI<(outs), (ins), MiscFrm, NoItinerary,
1260 let Inst = 0xe7ffdefe;
1263 // Address computation and loads and stores in PIC mode.
1264 let isNotDuplicable = 1 in {
1265 def PICADD : ARMPseudoInst<(outs GPR:$dst), (ins GPR:$a, pclabel:$cp, pred:$p),
1266 Size4Bytes, IIC_iALUr,
1267 [(set GPR:$dst, (ARMpic_add GPR:$a, imm:$cp))]>;
1269 let AddedComplexity = 10 in {
1270 def PICLDR : ARMPseudoInst<(outs GPR:$dst), (ins addrmodepc:$addr, pred:$p),
1271 Size4Bytes, IIC_iLoad_r,
1272 [(set GPR:$dst, (load addrmodepc:$addr))]>;
1274 def PICLDRH : ARMPseudoInst<(outs GPR:$Rt), (ins addrmodepc:$addr, pred:$p),
1275 Size4Bytes, IIC_iLoad_bh_r,
1276 [(set GPR:$Rt, (zextloadi16 addrmodepc:$addr))]>;
1278 def PICLDRB : ARMPseudoInst<(outs GPR:$Rt), (ins addrmodepc:$addr, pred:$p),
1279 Size4Bytes, IIC_iLoad_bh_r,
1280 [(set GPR:$Rt, (zextloadi8 addrmodepc:$addr))]>;
1282 def PICLDRSH : ARMPseudoInst<(outs GPR:$Rt), (ins addrmodepc:$addr, pred:$p),
1283 Size4Bytes, IIC_iLoad_bh_r,
1284 [(set GPR:$Rt, (sextloadi16 addrmodepc:$addr))]>;
1286 def PICLDRSB : ARMPseudoInst<(outs GPR:$Rt), (ins addrmodepc:$addr, pred:$p),
1287 Size4Bytes, IIC_iLoad_bh_r,
1288 [(set GPR:$Rt, (sextloadi8 addrmodepc:$addr))]>;
1290 let AddedComplexity = 10 in {
1291 def PICSTR : ARMPseudoInst<(outs), (ins GPR:$src, addrmodepc:$addr, pred:$p),
1292 Size4Bytes, IIC_iStore_r, [(store GPR:$src, addrmodepc:$addr)]>;
1294 def PICSTRH : ARMPseudoInst<(outs), (ins GPR:$src, addrmodepc:$addr, pred:$p),
1295 Size4Bytes, IIC_iStore_bh_r, [(truncstorei16 GPR:$src,
1296 addrmodepc:$addr)]>;
1298 def PICSTRB : ARMPseudoInst<(outs), (ins GPR:$src, addrmodepc:$addr, pred:$p),
1299 Size4Bytes, IIC_iStore_bh_r, [(truncstorei8 GPR:$src, addrmodepc:$addr)]>;
1301 } // isNotDuplicable = 1
1304 // LEApcrel - Load a pc-relative address into a register without offending the
1306 let neverHasSideEffects = 1, isReMaterializable = 1 in
1307 // The 'adr' mnemonic encodes differently if the label is before or after
1308 // the instruction. The {24-21} opcode bits are set by the fixup, as we don't
1309 // know until then which form of the instruction will be used.
1310 def ADR : AI1<{0,?,?,0}, (outs GPR:$Rd), (ins adrlabel:$label),
1311 MiscFrm, IIC_iALUi, "adr", "\t$Rd, #$label", []> {
1314 let Inst{27-25} = 0b001;
1316 let Inst{19-16} = 0b1111;
1317 let Inst{15-12} = Rd;
1318 let Inst{11-0} = label;
1320 def LEApcrel : ARMPseudoInst<(outs GPR:$Rd), (ins i32imm:$label, pred:$p),
1321 Size4Bytes, IIC_iALUi, []>;
1323 def LEApcrelJT : ARMPseudoInst<(outs GPR:$Rd),
1324 (ins i32imm:$label, nohash_imm:$id, pred:$p),
1325 Size4Bytes, IIC_iALUi, []>;
1327 //===----------------------------------------------------------------------===//
1328 // Control Flow Instructions.
1331 let isReturn = 1, isTerminator = 1, isBarrier = 1 in {
1333 def BX_RET : AI<(outs), (ins), BrMiscFrm, IIC_Br,
1334 "bx", "\tlr", [(ARMretflag)]>,
1335 Requires<[IsARM, HasV4T]> {
1336 let Inst{27-0} = 0b0001001011111111111100011110;
1340 def MOVPCLR : AI<(outs), (ins), BrMiscFrm, IIC_Br,
1341 "mov", "\tpc, lr", [(ARMretflag)]>,
1342 Requires<[IsARM, NoV4T]> {
1343 let Inst{27-0} = 0b0001101000001111000000001110;
1347 // Indirect branches
1348 let isBranch = 1, isTerminator = 1, isBarrier = 1, isIndirectBranch = 1 in {
1350 def BX : AXI<(outs), (ins GPR:$dst), BrMiscFrm, IIC_Br, "bx\t$dst",
1351 [(brind GPR:$dst)]>,
1352 Requires<[IsARM, HasV4T]> {
1354 let Inst{31-4} = 0b1110000100101111111111110001;
1355 let Inst{3-0} = dst;
1358 // For disassembly only.
1359 def BX_pred : AXI<(outs), (ins GPR:$dst, pred:$p), BrMiscFrm, IIC_Br,
1360 "bx$p\t$dst", [/* pattern left blank */]>,
1361 Requires<[IsARM, HasV4T]> {
1363 let Inst{27-4} = 0b000100101111111111110001;
1364 let Inst{3-0} = dst;
1368 // All calls clobber the non-callee saved registers. SP is marked as
1369 // a use to prevent stack-pointer assignments that appear immediately
1370 // before calls from potentially appearing dead.
1372 // On non-Darwin platforms R9 is callee-saved.
1373 // FIXME: Do we really need a non-predicated version? If so, it should
1374 // at least be a pseudo instruction expanding to the predicated version
1375 // at MC lowering time.
1376 Defs = [R0, R1, R2, R3, R12, LR, QQQQ0, QQQQ2, QQQQ3, CPSR, FPSCR],
1378 def BL : ABXI<0b1011, (outs), (ins bl_target:$func, variable_ops),
1379 IIC_Br, "bl\t$func",
1380 [(ARMcall tglobaladdr:$func)]>,
1381 Requires<[IsARM, IsNotDarwin]> {
1382 let Inst{31-28} = 0b1110;
1384 let Inst{23-0} = func;
1387 def BL_pred : ABI<0b1011, (outs), (ins bl_target:$func, variable_ops),
1388 IIC_Br, "bl", "\t$func",
1389 [(ARMcall_pred tglobaladdr:$func)]>,
1390 Requires<[IsARM, IsNotDarwin]> {
1392 let Inst{23-0} = func;
1396 def BLX : AXI<(outs), (ins GPR:$func, variable_ops), BrMiscFrm,
1397 IIC_Br, "blx\t$func",
1398 [(ARMcall GPR:$func)]>,
1399 Requires<[IsARM, HasV5T, IsNotDarwin]> {
1401 let Inst{31-4} = 0b1110000100101111111111110011;
1402 let Inst{3-0} = func;
1405 def BLX_pred : AI<(outs), (ins GPR:$func, variable_ops), BrMiscFrm,
1406 IIC_Br, "blx", "\t$func",
1407 [(ARMcall_pred GPR:$func)]>,
1408 Requires<[IsARM, HasV5T, IsNotDarwin]> {
1410 let Inst{27-4} = 0b000100101111111111110011;
1411 let Inst{3-0} = func;
1415 // Note: Restrict $func to the tGPR regclass to prevent it being in LR.
1416 def BX_CALL : ARMPseudoInst<(outs), (ins tGPR:$func, variable_ops),
1417 Size8Bytes, IIC_Br, [(ARMcall_nolink tGPR:$func)]>,
1418 Requires<[IsARM, HasV4T, IsNotDarwin]>;
1421 def BMOVPCRX_CALL : ARMPseudoInst<(outs), (ins tGPR:$func, variable_ops),
1422 Size8Bytes, IIC_Br, [(ARMcall_nolink tGPR:$func)]>,
1423 Requires<[IsARM, NoV4T, IsNotDarwin]>;
1427 // On Darwin R9 is call-clobbered.
1428 // R7 is marked as a use to prevent frame-pointer assignments from being
1429 // moved above / below calls.
1430 Defs = [R0, R1, R2, R3, R9, R12, LR, QQQQ0, QQQQ2, QQQQ3, CPSR, FPSCR],
1431 Uses = [R7, SP] in {
1432 def BLr9 : ARMPseudoInst<(outs), (ins bltarget:$func, variable_ops),
1434 [(ARMcall tglobaladdr:$func)]>, Requires<[IsARM, IsDarwin]>;
1436 def BLr9_pred : ARMPseudoInst<(outs),
1437 (ins bltarget:$func, pred:$p, variable_ops),
1439 [(ARMcall_pred tglobaladdr:$func)]>,
1440 Requires<[IsARM, IsDarwin]>;
1443 def BLXr9 : ARMPseudoInst<(outs), (ins GPR:$func, variable_ops),
1445 [(ARMcall GPR:$func)]>, Requires<[IsARM, HasV5T, IsDarwin]>;
1447 def BLXr9_pred: ARMPseudoInst<(outs), (ins GPR:$func, pred:$p, variable_ops),
1449 [(ARMcall_pred GPR:$func)]>,
1450 Requires<[IsARM, HasV5T, IsDarwin]>;
1453 // Note: Restrict $func to the tGPR regclass to prevent it being in LR.
1454 def BXr9_CALL : ARMPseudoInst<(outs), (ins tGPR:$func, variable_ops),
1455 Size8Bytes, IIC_Br, [(ARMcall_nolink tGPR:$func)]>,
1456 Requires<[IsARM, HasV4T, IsDarwin]>;
1459 def BMOVPCRXr9_CALL : ARMPseudoInst<(outs), (ins tGPR:$func, variable_ops),
1460 Size8Bytes, IIC_Br, [(ARMcall_nolink tGPR:$func)]>,
1461 Requires<[IsARM, NoV4T, IsDarwin]>;
1466 // FIXME: The Thumb versions of these should live in ARMInstrThumb.td
1467 let isCall = 1, isTerminator = 1, isReturn = 1, isBarrier = 1 in {
1469 let Defs = [R0, R1, R2, R3, R9, R12, QQQQ0, QQQQ2, QQQQ3, PC],
1471 def TCRETURNdi : PseudoInst<(outs), (ins i32imm:$dst, variable_ops),
1472 IIC_Br, []>, Requires<[IsDarwin]>;
1474 def TCRETURNri : PseudoInst<(outs), (ins tcGPR:$dst, variable_ops),
1475 IIC_Br, []>, Requires<[IsDarwin]>;
1477 def TAILJMPd : ARMPseudoInst<(outs), (ins brtarget:$dst, variable_ops),
1479 []>, Requires<[IsARM, IsDarwin]>;
1481 def tTAILJMPd: tPseudoInst<(outs), (ins brtarget:$dst, variable_ops),
1483 []>, Requires<[IsThumb, IsDarwin]>;
1485 def TAILJMPr : ARMPseudoInst<(outs), (ins tcGPR:$dst, variable_ops),
1487 []>, Requires<[IsARM, IsDarwin]>;
1489 def tTAILJMPr : tPseudoInst<(outs), (ins tcGPR:$dst, variable_ops),
1491 []>, Requires<[IsThumb, IsDarwin]>;
1494 // Non-Darwin versions (the difference is R9).
1495 let Defs = [R0, R1, R2, R3, R12, QQQQ0, QQQQ2, QQQQ3, PC],
1497 def TCRETURNdiND : PseudoInst<(outs), (ins i32imm:$dst, variable_ops),
1498 IIC_Br, []>, Requires<[IsNotDarwin]>;
1500 def TCRETURNriND : PseudoInst<(outs), (ins tcGPR:$dst, variable_ops),
1501 IIC_Br, []>, Requires<[IsNotDarwin]>;
1503 def TAILJMPdND : ARMPseudoInst<(outs), (ins brtarget:$dst, variable_ops),
1505 []>, Requires<[IsARM, IsNotDarwin]>;
1507 def tTAILJMPdND : tPseudoInst<(outs), (ins brtarget:$dst, variable_ops),
1509 []>, Requires<[IsThumb, IsNotDarwin]>;
1511 def TAILJMPrND : ARMPseudoInst<(outs), (ins tcGPR:$dst, variable_ops),
1513 []>, Requires<[IsARM, IsNotDarwin]>;
1514 def tTAILJMPrND : tPseudoInst<(outs), (ins tcGPR:$dst, variable_ops),
1516 []>, Requires<[IsThumb, IsNotDarwin]>;
1520 let isBranch = 1, isTerminator = 1 in {
1521 // FIXME: should be able to write a pattern for ARMBrcond, but can't use
1522 // a two-value operand where a dag node expects two operands. :(
1523 def Bcc : ABI<0b1010, (outs), (ins br_target:$target),
1524 IIC_Br, "b", "\t$target",
1525 [/*(ARMbrcond bb:$target, imm:$cc, CCR:$ccr)*/]> {
1527 let Inst{23-0} = target;
1530 let isBarrier = 1 in {
1531 // B is "predicable" since it's just a Bcc with an 'always' condition.
1532 let isPredicable = 1 in
1533 // FIXME: We shouldn't need this pseudo at all. Just using Bcc directly
1534 // should be sufficient.
1535 // FIXME: Is B really a Barrier? That doesn't seem right.
1536 def B : ARMPseudoExpand<(outs), (ins br_target:$target), Size4Bytes, IIC_Br,
1537 [(br bb:$target)], (Bcc br_target:$target, (ops 14, zero_reg))>;
1539 let isNotDuplicable = 1, isIndirectBranch = 1 in {
1540 def BR_JTr : ARMPseudoInst<(outs),
1541 (ins GPR:$target, i32imm:$jt, i32imm:$id),
1542 SizeSpecial, IIC_Br,
1543 [(ARMbrjt GPR:$target, tjumptable:$jt, imm:$id)]>;
1544 // FIXME: This shouldn't use the generic "addrmode2," but rather be split
1545 // into i12 and rs suffixed versions.
1546 def BR_JTm : ARMPseudoInst<(outs),
1547 (ins addrmode2:$target, i32imm:$jt, i32imm:$id),
1548 SizeSpecial, IIC_Br,
1549 [(ARMbrjt (i32 (load addrmode2:$target)), tjumptable:$jt,
1551 def BR_JTadd : ARMPseudoInst<(outs),
1552 (ins GPR:$target, GPR:$idx, i32imm:$jt, i32imm:$id),
1553 SizeSpecial, IIC_Br,
1554 [(ARMbrjt (add GPR:$target, GPR:$idx), tjumptable:$jt,
1556 } // isNotDuplicable = 1, isIndirectBranch = 1
1561 // BLX (immediate) -- for disassembly only
1562 def BLXi : AXI<(outs), (ins br_target:$target), BrMiscFrm, NoItinerary,
1563 "blx\t$target", [/* pattern left blank */]>,
1564 Requires<[IsARM, HasV5T]> {
1565 let Inst{31-25} = 0b1111101;
1567 let Inst{23-0} = target{24-1};
1568 let Inst{24} = target{0};
1571 // Branch and Exchange Jazelle -- for disassembly only
1572 def BXJ : ABI<0b0001, (outs), (ins GPR:$func), NoItinerary, "bxj", "\t$func",
1573 [/* For disassembly only; pattern left blank */]> {
1574 let Inst{23-20} = 0b0010;
1575 //let Inst{19-8} = 0xfff;
1576 let Inst{7-4} = 0b0010;
1579 // Secure Monitor Call is a system instruction -- for disassembly only
1580 def SMC : ABI<0b0001, (outs), (ins i32imm:$opt), NoItinerary, "smc", "\t$opt",
1581 [/* For disassembly only; pattern left blank */]> {
1583 let Inst{23-4} = 0b01100000000000000111;
1584 let Inst{3-0} = opt;
1587 // Supervisor Call (Software Interrupt) -- for disassembly only
1588 let isCall = 1, Uses = [SP] in {
1589 def SVC : ABI<0b1111, (outs), (ins i32imm:$svc), IIC_Br, "svc", "\t$svc",
1590 [/* For disassembly only; pattern left blank */]> {
1592 let Inst{23-0} = svc;
1595 def : MnemonicAlias<"swi", "svc">;
1597 // Store Return State is a system instruction -- for disassembly only
1598 let isCodeGenOnly = 1 in { // FIXME: This should not use submode!
1599 def SRSW : ABXI<{1,0,0,?}, (outs), (ins ldstm_mode:$amode, i32imm:$mode),
1600 NoItinerary, "srs${amode}\tsp!, $mode",
1601 [/* For disassembly only; pattern left blank */]> {
1602 let Inst{31-28} = 0b1111;
1603 let Inst{22-20} = 0b110; // W = 1
1604 let Inst{19-8} = 0xd05;
1605 let Inst{7-5} = 0b000;
1608 def SRS : ABXI<{1,0,0,?}, (outs), (ins ldstm_mode:$amode, i32imm:$mode),
1609 NoItinerary, "srs${amode}\tsp, $mode",
1610 [/* For disassembly only; pattern left blank */]> {
1611 let Inst{31-28} = 0b1111;
1612 let Inst{22-20} = 0b100; // W = 0
1613 let Inst{19-8} = 0xd05;
1614 let Inst{7-5} = 0b000;
1617 // Return From Exception is a system instruction -- for disassembly only
1618 def RFEW : ABXI<{1,0,0,?}, (outs), (ins ldstm_mode:$amode, GPR:$base),
1619 NoItinerary, "rfe${amode}\t$base!",
1620 [/* For disassembly only; pattern left blank */]> {
1621 let Inst{31-28} = 0b1111;
1622 let Inst{22-20} = 0b011; // W = 1
1623 let Inst{15-0} = 0x0a00;
1626 def RFE : ABXI<{1,0,0,?}, (outs), (ins ldstm_mode:$amode, GPR:$base),
1627 NoItinerary, "rfe${amode}\t$base",
1628 [/* For disassembly only; pattern left blank */]> {
1629 let Inst{31-28} = 0b1111;
1630 let Inst{22-20} = 0b001; // W = 0
1631 let Inst{15-0} = 0x0a00;
1633 } // isCodeGenOnly = 1
1635 //===----------------------------------------------------------------------===//
1636 // Load / store Instructions.
1642 defm LDR : AI_ldr1<0, "ldr", IIC_iLoad_r, IIC_iLoad_si,
1643 UnOpFrag<(load node:$Src)>>;
1644 defm LDRB : AI_ldr1<1, "ldrb", IIC_iLoad_bh_r, IIC_iLoad_bh_si,
1645 UnOpFrag<(zextloadi8 node:$Src)>>;
1646 defm STR : AI_str1<0, "str", IIC_iStore_r, IIC_iStore_si,
1647 BinOpFrag<(store node:$LHS, node:$RHS)>>;
1648 defm STRB : AI_str1<1, "strb", IIC_iStore_bh_r, IIC_iStore_bh_si,
1649 BinOpFrag<(truncstorei8 node:$LHS, node:$RHS)>>;
1651 // Special LDR for loads from non-pc-relative constpools.
1652 let canFoldAsLoad = 1, mayLoad = 1, neverHasSideEffects = 1,
1653 isReMaterializable = 1 in
1654 def LDRcp : AI2ldst<0b010, 1, 0, (outs GPR:$Rt), (ins addrmode_imm12:$addr),
1655 AddrMode_i12, LdFrm, IIC_iLoad_r, "ldr", "\t$Rt, $addr",
1659 let Inst{23} = addr{12}; // U (add = ('U' == 1))
1660 let Inst{19-16} = 0b1111;
1661 let Inst{15-12} = Rt;
1662 let Inst{11-0} = addr{11-0}; // imm12
1665 // Loads with zero extension
1666 def LDRH : AI3ld<0b1011, 1, (outs GPR:$Rt), (ins addrmode3:$addr), LdMiscFrm,
1667 IIC_iLoad_bh_r, "ldrh", "\t$Rt, $addr",
1668 [(set GPR:$Rt, (zextloadi16 addrmode3:$addr))]>;
1670 // Loads with sign extension
1671 def LDRSH : AI3ld<0b1111, 1, (outs GPR:$Rt), (ins addrmode3:$addr), LdMiscFrm,
1672 IIC_iLoad_bh_r, "ldrsh", "\t$Rt, $addr",
1673 [(set GPR:$Rt, (sextloadi16 addrmode3:$addr))]>;
1675 def LDRSB : AI3ld<0b1101, 1, (outs GPR:$Rt), (ins addrmode3:$addr), LdMiscFrm,
1676 IIC_iLoad_bh_r, "ldrsb", "\t$Rt, $addr",
1677 [(set GPR:$Rt, (sextloadi8 addrmode3:$addr))]>;
1679 let mayLoad = 1, neverHasSideEffects = 1, hasExtraDefRegAllocReq = 1 in {
1681 def LDRD : AI3ld<0b1101, 0, (outs GPR:$Rd, GPR:$dst2),
1682 (ins addrmode3:$addr), LdMiscFrm,
1683 IIC_iLoad_d_r, "ldrd", "\t$Rd, $dst2, $addr",
1684 []>, Requires<[IsARM, HasV5TE]>;
1688 multiclass AI2_ldridx<bit isByte, string opc, InstrItinClass itin> {
1689 def _PRE : AI2ldstidx<1, isByte, 1, (outs GPR:$Rt, GPR:$Rn_wb),
1690 (ins addrmode2:$addr), IndexModePre, LdFrm, itin,
1691 opc, "\t$Rt, $addr!", "$addr.base = $Rn_wb", []> {
1693 // {13} 1 == Rm, 0 == imm12
1697 let Inst{25} = addr{13};
1698 let Inst{23} = addr{12};
1699 let Inst{19-16} = addr{17-14};
1700 let Inst{11-0} = addr{11-0};
1701 let AsmMatchConverter = "CvtLdWriteBackRegAddrMode2";
1703 def _POST : AI2ldstidx<1, isByte, 0, (outs GPR:$Rt, GPR:$Rn_wb),
1704 (ins GPR:$Rn, am2offset:$offset),
1705 IndexModePost, LdFrm, itin,
1706 opc, "\t$Rt, [$Rn], $offset", "$Rn = $Rn_wb", []> {
1707 // {13} 1 == Rm, 0 == imm12
1712 let Inst{25} = offset{13};
1713 let Inst{23} = offset{12};
1714 let Inst{19-16} = Rn;
1715 let Inst{11-0} = offset{11-0};
1719 let mayLoad = 1, neverHasSideEffects = 1 in {
1720 defm LDR : AI2_ldridx<0, "ldr", IIC_iLoad_ru>;
1721 defm LDRB : AI2_ldridx<1, "ldrb", IIC_iLoad_bh_ru>;
1724 multiclass AI3_ldridx<bits<4> op, bit op20, string opc, InstrItinClass itin> {
1725 def _PRE : AI3ldstidx<op, op20, 1, 1, (outs GPR:$Rt, GPR:$Rn_wb),
1726 (ins addrmode3:$addr), IndexModePre,
1728 opc, "\t$Rt, $addr!", "$addr.base = $Rn_wb", []> {
1730 let Inst{23} = addr{8}; // U bit
1731 let Inst{22} = addr{13}; // 1 == imm8, 0 == Rm
1732 let Inst{19-16} = addr{12-9}; // Rn
1733 let Inst{11-8} = addr{7-4}; // imm7_4/zero
1734 let Inst{3-0} = addr{3-0}; // imm3_0/Rm
1736 def _POST : AI3ldstidx<op, op20, 1, 0, (outs GPR:$Rt, GPR:$Rn_wb),
1737 (ins GPR:$Rn, am3offset:$offset), IndexModePost,
1739 opc, "\t$Rt, [$Rn], $offset", "$Rn = $Rn_wb", []> {
1742 let Inst{23} = offset{8}; // U bit
1743 let Inst{22} = offset{9}; // 1 == imm8, 0 == Rm
1744 let Inst{19-16} = Rn;
1745 let Inst{11-8} = offset{7-4}; // imm7_4/zero
1746 let Inst{3-0} = offset{3-0}; // imm3_0/Rm
1750 let mayLoad = 1, neverHasSideEffects = 1 in {
1751 defm LDRH : AI3_ldridx<0b1011, 1, "ldrh", IIC_iLoad_bh_ru>;
1752 defm LDRSH : AI3_ldridx<0b1111, 1, "ldrsh", IIC_iLoad_bh_ru>;
1753 defm LDRSB : AI3_ldridx<0b1101, 1, "ldrsb", IIC_iLoad_bh_ru>;
1754 let hasExtraDefRegAllocReq = 1 in {
1755 def LDRD_PRE : AI3ldstidx<0b1101, 0, 1, 1, (outs GPR:$Rt, GPR:$Rt2, GPR:$Rn_wb),
1756 (ins addrmode3:$addr), IndexModePre,
1757 LdMiscFrm, IIC_iLoad_d_ru,
1758 "ldrd", "\t$Rt, $Rt2, $addr!",
1759 "$addr.base = $Rn_wb", []> {
1761 let Inst{23} = addr{8}; // U bit
1762 let Inst{22} = addr{13}; // 1 == imm8, 0 == Rm
1763 let Inst{19-16} = addr{12-9}; // Rn
1764 let Inst{11-8} = addr{7-4}; // imm7_4/zero
1765 let Inst{3-0} = addr{3-0}; // imm3_0/Rm
1767 def LDRD_POST: AI3ldstidx<0b1101, 0, 1, 0, (outs GPR:$Rt, GPR:$Rt2, GPR:$Rn_wb),
1768 (ins GPR:$Rn, am3offset:$offset), IndexModePost,
1769 LdMiscFrm, IIC_iLoad_d_ru,
1770 "ldrd", "\t$Rt, $Rt2, [$Rn], $offset",
1771 "$Rn = $Rn_wb", []> {
1774 let Inst{23} = offset{8}; // U bit
1775 let Inst{22} = offset{9}; // 1 == imm8, 0 == Rm
1776 let Inst{19-16} = Rn;
1777 let Inst{11-8} = offset{7-4}; // imm7_4/zero
1778 let Inst{3-0} = offset{3-0}; // imm3_0/Rm
1780 } // hasExtraDefRegAllocReq = 1
1781 } // mayLoad = 1, neverHasSideEffects = 1
1783 // LDRT, LDRBT, LDRSBT, LDRHT, LDRSHT are for disassembly only.
1784 let mayLoad = 1, neverHasSideEffects = 1 in {
1785 def LDRT : AI2ldstidx<1, 0, 0, (outs GPR:$Rt, GPR:$base_wb),
1786 (ins addrmode2:$addr), IndexModePost, LdFrm, IIC_iLoad_ru,
1787 "ldrt", "\t$Rt, $addr", "$addr.base = $base_wb", []> {
1789 // {13} 1 == Rm, 0 == imm12
1793 let Inst{25} = addr{13};
1794 let Inst{23} = addr{12};
1795 let Inst{21} = 1; // overwrite
1796 let Inst{19-16} = addr{17-14};
1797 let Inst{11-0} = addr{11-0};
1798 let AsmMatchConverter = "CvtLdWriteBackRegAddrMode2";
1800 def LDRBT : AI2ldstidx<1, 1, 0, (outs GPR:$Rt, GPR:$base_wb),
1801 (ins addrmode2:$addr), IndexModePost, LdFrm, IIC_iLoad_bh_ru,
1802 "ldrbt", "\t$Rt, $addr", "$addr.base = $base_wb", []> {
1804 // {13} 1 == Rm, 0 == imm12
1808 let Inst{25} = addr{13};
1809 let Inst{23} = addr{12};
1810 let Inst{21} = 1; // overwrite
1811 let Inst{19-16} = addr{17-14};
1812 let Inst{11-0} = addr{11-0};
1813 let AsmMatchConverter = "CvtLdWriteBackRegAddrMode2";
1815 def LDRSBT : AI3ldstidxT<0b1101, 1, 1, 0, (outs GPR:$Rt, GPR:$base_wb),
1816 (ins addrmode3:$addr), IndexModePost, LdMiscFrm, IIC_iLoad_bh_ru,
1817 "ldrsbt", "\t$Rt, $addr", "$addr.base = $base_wb", []> {
1818 let Inst{21} = 1; // overwrite
1820 def LDRHT : AI3ldstidxT<0b1011, 1, 1, 0, (outs GPR:$Rt, GPR:$base_wb),
1821 (ins addrmode3:$addr), IndexModePost, LdMiscFrm, IIC_iLoad_bh_ru,
1822 "ldrht", "\t$Rt, $addr", "$addr.base = $base_wb", []> {
1823 let Inst{21} = 1; // overwrite
1825 def LDRSHT : AI3ldstidxT<0b1111, 1, 1, 0, (outs GPR:$Rt, GPR:$base_wb),
1826 (ins addrmode3:$addr), IndexModePost, LdMiscFrm, IIC_iLoad_bh_ru,
1827 "ldrsht", "\t$Rt, $addr", "$addr.base = $base_wb", []> {
1828 let Inst{21} = 1; // overwrite
1834 // Stores with truncate
1835 def STRH : AI3str<0b1011, (outs), (ins GPR:$Rt, addrmode3:$addr), StMiscFrm,
1836 IIC_iStore_bh_r, "strh", "\t$Rt, $addr",
1837 [(truncstorei16 GPR:$Rt, addrmode3:$addr)]>;
1840 let mayStore = 1, neverHasSideEffects = 1, hasExtraSrcRegAllocReq = 1 in
1841 def STRD : AI3str<0b1111, (outs), (ins GPR:$Rt, GPR:$src2, addrmode3:$addr),
1842 StMiscFrm, IIC_iStore_d_r,
1843 "strd", "\t$Rt, $src2, $addr", []>, Requires<[IsARM, HasV5TE]>;
1846 def STR_PRE : AI2stridx<0, 1, (outs GPR:$Rn_wb),
1847 (ins GPR:$Rt, GPR:$Rn, am2offset:$offset),
1848 IndexModePre, StFrm, IIC_iStore_ru,
1849 "str", "\t$Rt, [$Rn, $offset]!",
1850 "$Rn = $Rn_wb,@earlyclobber $Rn_wb",
1852 (pre_store GPR:$Rt, GPR:$Rn, am2offset:$offset))]>;
1854 def STR_POST : AI2stridx<0, 0, (outs GPR:$Rn_wb),
1855 (ins GPR:$Rt, GPR:$Rn, am2offset:$offset),
1856 IndexModePost, StFrm, IIC_iStore_ru,
1857 "str", "\t$Rt, [$Rn], $offset",
1858 "$Rn = $Rn_wb,@earlyclobber $Rn_wb",
1860 (post_store GPR:$Rt, GPR:$Rn, am2offset:$offset))]>;
1862 def STRB_PRE : AI2stridx<1, 1, (outs GPR:$Rn_wb),
1863 (ins GPR:$Rt, GPR:$Rn, am2offset:$offset),
1864 IndexModePre, StFrm, IIC_iStore_bh_ru,
1865 "strb", "\t$Rt, [$Rn, $offset]!",
1866 "$Rn = $Rn_wb,@earlyclobber $Rn_wb",
1867 [(set GPR:$Rn_wb, (pre_truncsti8 GPR:$Rt,
1868 GPR:$Rn, am2offset:$offset))]>;
1869 def STRB_POST: AI2stridx<1, 0, (outs GPR:$Rn_wb),
1870 (ins GPR:$Rt, GPR:$Rn, am2offset:$offset),
1871 IndexModePost, StFrm, IIC_iStore_bh_ru,
1872 "strb", "\t$Rt, [$Rn], $offset",
1873 "$Rn = $Rn_wb,@earlyclobber $Rn_wb",
1874 [(set GPR:$Rn_wb, (post_truncsti8 GPR:$Rt,
1875 GPR:$Rn, am2offset:$offset))]>;
1877 def STRH_PRE : AI3stridx<0b1011, 0, 1, (outs GPR:$Rn_wb),
1878 (ins GPR:$Rt, GPR:$Rn, am3offset:$offset),
1879 IndexModePre, StMiscFrm, IIC_iStore_ru,
1880 "strh", "\t$Rt, [$Rn, $offset]!",
1881 "$Rn = $Rn_wb,@earlyclobber $Rn_wb",
1883 (pre_truncsti16 GPR:$Rt, GPR:$Rn, am3offset:$offset))]>;
1885 def STRH_POST: AI3stridx<0b1011, 0, 0, (outs GPR:$Rn_wb),
1886 (ins GPR:$Rt, GPR:$Rn, am3offset:$offset),
1887 IndexModePost, StMiscFrm, IIC_iStore_bh_ru,
1888 "strh", "\t$Rt, [$Rn], $offset",
1889 "$Rn = $Rn_wb,@earlyclobber $Rn_wb",
1890 [(set GPR:$Rn_wb, (post_truncsti16 GPR:$Rt,
1891 GPR:$Rn, am3offset:$offset))]>;
1893 // For disassembly only
1894 let mayStore = 1, neverHasSideEffects = 1, hasExtraSrcRegAllocReq = 1 in {
1895 def STRD_PRE : AI3stdpr<(outs GPR:$base_wb),
1896 (ins GPR:$src1, GPR:$src2, GPR:$base, am3offset:$offset),
1897 StMiscFrm, IIC_iStore_d_ru,
1898 "strd", "\t$src1, $src2, [$base, $offset]!",
1899 "$base = $base_wb", []>;
1901 // For disassembly only
1902 def STRD_POST: AI3stdpo<(outs GPR:$base_wb),
1903 (ins GPR:$src1, GPR:$src2, GPR:$base, am3offset:$offset),
1904 StMiscFrm, IIC_iStore_d_ru,
1905 "strd", "\t$src1, $src2, [$base], $offset",
1906 "$base = $base_wb", []>;
1907 } // mayStore = 1, neverHasSideEffects = 1, hasExtraSrcRegAllocReq = 1
1909 // STRT, STRBT, and STRHT are for disassembly only.
1911 def STRT : AI2stridxT<0, 0, (outs GPR:$Rn_wb), (ins GPR:$Rt, addrmode2:$addr),
1912 IndexModePost, StFrm, IIC_iStore_ru,
1913 "strt", "\t$Rt, $addr", "$addr.base = $Rn_wb",
1914 [/* For disassembly only; pattern left blank */]> {
1915 let Inst{21} = 1; // overwrite
1916 let AsmMatchConverter = "CvtStWriteBackRegAddrMode2";
1919 def STRBT : AI2stridxT<1, 0, (outs GPR:$Rn_wb), (ins GPR:$Rt, addrmode2:$addr),
1920 IndexModePost, StFrm, IIC_iStore_bh_ru,
1921 "strbt", "\t$Rt, $addr", "$addr.base = $Rn_wb",
1922 [/* For disassembly only; pattern left blank */]> {
1923 let Inst{21} = 1; // overwrite
1924 let AsmMatchConverter = "CvtStWriteBackRegAddrMode2";
1927 def STRHT: AI3sthpo<(outs GPR:$base_wb), (ins GPR:$Rt, addrmode3:$addr),
1928 StMiscFrm, IIC_iStore_bh_ru,
1929 "strht", "\t$Rt, $addr", "$addr.base = $base_wb",
1930 [/* For disassembly only; pattern left blank */]> {
1931 let Inst{21} = 1; // overwrite
1932 let AsmMatchConverter = "CvtStWriteBackRegAddrMode3";
1935 //===----------------------------------------------------------------------===//
1936 // Load / store multiple Instructions.
1939 multiclass arm_ldst_mult<string asm, bit L_bit, Format f,
1940 InstrItinClass itin, InstrItinClass itin_upd> {
1942 AXI4<(outs), (ins GPR:$Rn, pred:$p, reglist:$regs, variable_ops),
1943 IndexModeNone, f, itin,
1944 !strconcat(asm, "ia${p}\t$Rn, $regs"), "", []> {
1945 let Inst{24-23} = 0b01; // Increment After
1946 let Inst{21} = 0; // No writeback
1947 let Inst{20} = L_bit;
1950 AXI4<(outs GPR:$wb), (ins GPR:$Rn, pred:$p, reglist:$regs, variable_ops),
1951 IndexModeUpd, f, itin_upd,
1952 !strconcat(asm, "ia${p}\t$Rn!, $regs"), "$Rn = $wb", []> {
1953 let Inst{24-23} = 0b01; // Increment After
1954 let Inst{21} = 1; // Writeback
1955 let Inst{20} = L_bit;
1958 AXI4<(outs), (ins GPR:$Rn, pred:$p, reglist:$regs, variable_ops),
1959 IndexModeNone, f, itin,
1960 !strconcat(asm, "da${p}\t$Rn, $regs"), "", []> {
1961 let Inst{24-23} = 0b00; // Decrement After
1962 let Inst{21} = 0; // No writeback
1963 let Inst{20} = L_bit;
1966 AXI4<(outs GPR:$wb), (ins GPR:$Rn, pred:$p, reglist:$regs, variable_ops),
1967 IndexModeUpd, f, itin_upd,
1968 !strconcat(asm, "da${p}\t$Rn!, $regs"), "$Rn = $wb", []> {
1969 let Inst{24-23} = 0b00; // Decrement After
1970 let Inst{21} = 1; // Writeback
1971 let Inst{20} = L_bit;
1974 AXI4<(outs), (ins GPR:$Rn, pred:$p, reglist:$regs, variable_ops),
1975 IndexModeNone, f, itin,
1976 !strconcat(asm, "db${p}\t$Rn, $regs"), "", []> {
1977 let Inst{24-23} = 0b10; // Decrement Before
1978 let Inst{21} = 0; // No writeback
1979 let Inst{20} = L_bit;
1982 AXI4<(outs GPR:$wb), (ins GPR:$Rn, pred:$p, reglist:$regs, variable_ops),
1983 IndexModeUpd, f, itin_upd,
1984 !strconcat(asm, "db${p}\t$Rn!, $regs"), "$Rn = $wb", []> {
1985 let Inst{24-23} = 0b10; // Decrement Before
1986 let Inst{21} = 1; // Writeback
1987 let Inst{20} = L_bit;
1990 AXI4<(outs), (ins GPR:$Rn, pred:$p, reglist:$regs, variable_ops),
1991 IndexModeNone, f, itin,
1992 !strconcat(asm, "ib${p}\t$Rn, $regs"), "", []> {
1993 let Inst{24-23} = 0b11; // Increment Before
1994 let Inst{21} = 0; // No writeback
1995 let Inst{20} = L_bit;
1998 AXI4<(outs GPR:$wb), (ins GPR:$Rn, pred:$p, reglist:$regs, variable_ops),
1999 IndexModeUpd, f, itin_upd,
2000 !strconcat(asm, "ib${p}\t$Rn!, $regs"), "$Rn = $wb", []> {
2001 let Inst{24-23} = 0b11; // Increment Before
2002 let Inst{21} = 1; // Writeback
2003 let Inst{20} = L_bit;
2007 let neverHasSideEffects = 1 in {
2009 let mayLoad = 1, hasExtraDefRegAllocReq = 1 in
2010 defm LDM : arm_ldst_mult<"ldm", 1, LdStMulFrm, IIC_iLoad_m, IIC_iLoad_mu>;
2012 let mayStore = 1, hasExtraSrcRegAllocReq = 1 in
2013 defm STM : arm_ldst_mult<"stm", 0, LdStMulFrm, IIC_iStore_m, IIC_iStore_mu>;
2015 } // neverHasSideEffects
2017 // Load / Store Multiple Mnemonic Aliases
2018 def : MnemonicAlias<"ldmfd", "ldmia">;
2019 def : MnemonicAlias<"stmfd", "stmdb">;
2020 def : MnemonicAlias<"ldm", "ldmia">;
2021 def : MnemonicAlias<"stm", "stmia">;
2023 // FIXME: remove when we have a way to marking a MI with these properties.
2024 // FIXME: Should pc be an implicit operand like PICADD, etc?
2025 let isReturn = 1, isTerminator = 1, isBarrier = 1, mayLoad = 1,
2026 hasExtraDefRegAllocReq = 1, isCodeGenOnly = 1 in
2027 def LDMIA_RET : ARMPseudoExpand<(outs GPR:$wb), (ins GPR:$Rn, pred:$p,
2028 reglist:$regs, variable_ops),
2029 Size4Bytes, IIC_iLoad_mBr, [],
2030 (LDMIA_UPD GPR:$wb, GPR:$Rn, pred:$p, reglist:$regs)>,
2031 RegConstraint<"$Rn = $wb">;
2033 //===----------------------------------------------------------------------===//
2034 // Move Instructions.
2037 let neverHasSideEffects = 1 in
2038 def MOVr : AsI1<0b1101, (outs GPR:$Rd), (ins GPR:$Rm), DPFrm, IIC_iMOVr,
2039 "mov", "\t$Rd, $Rm", []>, UnaryDP {
2043 let Inst{19-16} = 0b0000;
2044 let Inst{11-4} = 0b00000000;
2047 let Inst{15-12} = Rd;
2050 // A version for the smaller set of tail call registers.
2051 let neverHasSideEffects = 1 in
2052 def MOVr_TC : AsI1<0b1101, (outs tcGPR:$Rd), (ins tcGPR:$Rm), DPFrm,
2053 IIC_iMOVr, "mov", "\t$Rd, $Rm", []>, UnaryDP {
2057 let Inst{11-4} = 0b00000000;
2060 let Inst{15-12} = Rd;
2063 def MOVs : AsI1<0b1101, (outs GPR:$Rd), (ins shift_so_reg:$src),
2064 DPSoRegFrm, IIC_iMOVsr,
2065 "mov", "\t$Rd, $src", [(set GPR:$Rd, shift_so_reg:$src)]>,
2069 let Inst{15-12} = Rd;
2070 let Inst{19-16} = 0b0000;
2071 let Inst{11-0} = src;
2075 let isReMaterializable = 1, isAsCheapAsAMove = 1, isMoveImm = 1 in
2076 def MOVi : AsI1<0b1101, (outs GPR:$Rd), (ins so_imm:$imm), DPFrm, IIC_iMOVi,
2077 "mov", "\t$Rd, $imm", [(set GPR:$Rd, so_imm:$imm)]>, UnaryDP {
2081 let Inst{15-12} = Rd;
2082 let Inst{19-16} = 0b0000;
2083 let Inst{11-0} = imm;
2086 let isReMaterializable = 1, isAsCheapAsAMove = 1, isMoveImm = 1 in
2087 def MOVi16 : AI1<0b1000, (outs GPR:$Rd), (ins i32imm_hilo16:$imm),
2089 "movw", "\t$Rd, $imm",
2090 [(set GPR:$Rd, imm0_65535:$imm)]>,
2091 Requires<[IsARM, HasV6T2]>, UnaryDP {
2094 let Inst{15-12} = Rd;
2095 let Inst{11-0} = imm{11-0};
2096 let Inst{19-16} = imm{15-12};
2101 def MOVi16_ga_pcrel : PseudoInst<(outs GPR:$Rd),
2102 (ins i32imm:$addr, pclabel:$id), IIC_iMOVi, []>;
2104 let Constraints = "$src = $Rd" in {
2105 def MOVTi16 : AI1<0b1010, (outs GPR:$Rd), (ins GPR:$src, i32imm_hilo16:$imm),
2107 "movt", "\t$Rd, $imm",
2109 (or (and GPR:$src, 0xffff),
2110 lo16AllZero:$imm))]>, UnaryDP,
2111 Requires<[IsARM, HasV6T2]> {
2114 let Inst{15-12} = Rd;
2115 let Inst{11-0} = imm{11-0};
2116 let Inst{19-16} = imm{15-12};
2121 def MOVTi16_ga_pcrel : PseudoInst<(outs GPR:$Rd),
2122 (ins GPR:$src, i32imm:$addr, pclabel:$id), IIC_iMOVi, []>;
2126 def : ARMPat<(or GPR:$src, 0xffff0000), (MOVTi16 GPR:$src, 0xffff)>,
2127 Requires<[IsARM, HasV6T2]>;
2129 let Uses = [CPSR] in
2130 def RRX: PseudoInst<(outs GPR:$Rd), (ins GPR:$Rm), IIC_iMOVsi,
2131 [(set GPR:$Rd, (ARMrrx GPR:$Rm))]>, UnaryDP,
2134 // These aren't really mov instructions, but we have to define them this way
2135 // due to flag operands.
2137 let Defs = [CPSR] in {
2138 def MOVsrl_flag : PseudoInst<(outs GPR:$dst), (ins GPR:$src), IIC_iMOVsi,
2139 [(set GPR:$dst, (ARMsrl_flag GPR:$src))]>, UnaryDP,
2141 def MOVsra_flag : PseudoInst<(outs GPR:$dst), (ins GPR:$src), IIC_iMOVsi,
2142 [(set GPR:$dst, (ARMsra_flag GPR:$src))]>, UnaryDP,
2146 //===----------------------------------------------------------------------===//
2147 // Extend Instructions.
2152 defm SXTB : AI_ext_rrot<0b01101010,
2153 "sxtb", UnOpFrag<(sext_inreg node:$Src, i8)>>;
2154 defm SXTH : AI_ext_rrot<0b01101011,
2155 "sxth", UnOpFrag<(sext_inreg node:$Src, i16)>>;
2157 defm SXTAB : AI_exta_rrot<0b01101010,
2158 "sxtab", BinOpFrag<(add node:$LHS, (sext_inreg node:$RHS, i8))>>;
2159 defm SXTAH : AI_exta_rrot<0b01101011,
2160 "sxtah", BinOpFrag<(add node:$LHS, (sext_inreg node:$RHS,i16))>>;
2162 // For disassembly only
2163 defm SXTB16 : AI_ext_rrot_np<0b01101000, "sxtb16">;
2165 // For disassembly only
2166 defm SXTAB16 : AI_exta_rrot_np<0b01101000, "sxtab16">;
2170 let AddedComplexity = 16 in {
2171 defm UXTB : AI_ext_rrot<0b01101110,
2172 "uxtb" , UnOpFrag<(and node:$Src, 0x000000FF)>>;
2173 defm UXTH : AI_ext_rrot<0b01101111,
2174 "uxth" , UnOpFrag<(and node:$Src, 0x0000FFFF)>>;
2175 defm UXTB16 : AI_ext_rrot<0b01101100,
2176 "uxtb16", UnOpFrag<(and node:$Src, 0x00FF00FF)>>;
2178 // FIXME: This pattern incorrectly assumes the shl operator is a rotate.
2179 // The transformation should probably be done as a combiner action
2180 // instead so we can include a check for masking back in the upper
2181 // eight bits of the source into the lower eight bits of the result.
2182 //def : ARMV6Pat<(and (shl GPR:$Src, (i32 8)), 0xFF00FF),
2183 // (UXTB16r_rot GPR:$Src, 24)>;
2184 def : ARMV6Pat<(and (srl GPR:$Src, (i32 8)), 0xFF00FF),
2185 (UXTB16r_rot GPR:$Src, 8)>;
2187 defm UXTAB : AI_exta_rrot<0b01101110, "uxtab",
2188 BinOpFrag<(add node:$LHS, (and node:$RHS, 0x00FF))>>;
2189 defm UXTAH : AI_exta_rrot<0b01101111, "uxtah",
2190 BinOpFrag<(add node:$LHS, (and node:$RHS, 0xFFFF))>>;
2193 // This isn't safe in general, the add is two 16-bit units, not a 32-bit add.
2194 // For disassembly only
2195 defm UXTAB16 : AI_exta_rrot_np<0b01101100, "uxtab16">;
2198 def SBFX : I<(outs GPR:$Rd),
2199 (ins GPR:$Rn, imm0_31:$lsb, imm0_31_m1:$width),
2200 AddrMode1, Size4Bytes, IndexModeNone, DPFrm, IIC_iUNAsi,
2201 "sbfx", "\t$Rd, $Rn, $lsb, $width", "", []>,
2202 Requires<[IsARM, HasV6T2]> {
2207 let Inst{27-21} = 0b0111101;
2208 let Inst{6-4} = 0b101;
2209 let Inst{20-16} = width;
2210 let Inst{15-12} = Rd;
2211 let Inst{11-7} = lsb;
2215 def UBFX : I<(outs GPR:$Rd),
2216 (ins GPR:$Rn, imm0_31:$lsb, imm0_31_m1:$width),
2217 AddrMode1, Size4Bytes, IndexModeNone, DPFrm, IIC_iUNAsi,
2218 "ubfx", "\t$Rd, $Rn, $lsb, $width", "", []>,
2219 Requires<[IsARM, HasV6T2]> {
2224 let Inst{27-21} = 0b0111111;
2225 let Inst{6-4} = 0b101;
2226 let Inst{20-16} = width;
2227 let Inst{15-12} = Rd;
2228 let Inst{11-7} = lsb;
2232 //===----------------------------------------------------------------------===//
2233 // Arithmetic Instructions.
2236 defm ADD : AsI1_bin_irs<0b0100, "add",
2237 IIC_iALUi, IIC_iALUr, IIC_iALUsr,
2238 BinOpFrag<(add node:$LHS, node:$RHS)>, "ADD", 1>;
2239 defm SUB : AsI1_bin_irs<0b0010, "sub",
2240 IIC_iALUi, IIC_iALUr, IIC_iALUsr,
2241 BinOpFrag<(sub node:$LHS, node:$RHS)>, "SUB">;
2243 // ADD and SUB with 's' bit set.
2244 defm ADDS : AI1_bin_s_irs<0b0100, "adds",
2245 IIC_iALUi, IIC_iALUr, IIC_iALUsr,
2246 BinOpFrag<(addc node:$LHS, node:$RHS)>, 1>;
2247 defm SUBS : AI1_bin_s_irs<0b0010, "subs",
2248 IIC_iALUi, IIC_iALUr, IIC_iALUsr,
2249 BinOpFrag<(subc node:$LHS, node:$RHS)>>;
2251 defm ADC : AI1_adde_sube_irs<0b0101, "adc",
2252 BinOpFrag<(adde_dead_carry node:$LHS, node:$RHS)>, 1>;
2253 defm SBC : AI1_adde_sube_irs<0b0110, "sbc",
2254 BinOpFrag<(sube_dead_carry node:$LHS, node:$RHS)>>;
2256 // ADC and SUBC with 's' bit set.
2257 let usesCustomInserter = 1 in {
2258 defm ADCS : AI1_adde_sube_s_irs<
2259 BinOpFrag<(adde_live_carry node:$LHS, node:$RHS)>, 1>;
2260 defm SBCS : AI1_adde_sube_s_irs<
2261 BinOpFrag<(sube_live_carry node:$LHS, node:$RHS) >>;
2264 def RSBri : AsI1<0b0011, (outs GPR:$Rd), (ins GPR:$Rn, so_imm:$imm), DPFrm,
2265 IIC_iALUi, "rsb", "\t$Rd, $Rn, $imm",
2266 [(set GPR:$Rd, (sub so_imm:$imm, GPR:$Rn))]> {
2271 let Inst{15-12} = Rd;
2272 let Inst{19-16} = Rn;
2273 let Inst{11-0} = imm;
2276 // The reg/reg form is only defined for the disassembler; for codegen it is
2277 // equivalent to SUBrr.
2278 def RSBrr : AsI1<0b0011, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm), DPFrm,
2279 IIC_iALUr, "rsb", "\t$Rd, $Rn, $Rm",
2280 [/* For disassembly only; pattern left blank */]> {
2284 let Inst{11-4} = 0b00000000;
2287 let Inst{15-12} = Rd;
2288 let Inst{19-16} = Rn;
2291 def RSBrs : AsI1<0b0011, (outs GPR:$Rd), (ins GPR:$Rn, so_reg:$shift),
2292 DPSoRegFrm, IIC_iALUsr, "rsb", "\t$Rd, $Rn, $shift",
2293 [(set GPR:$Rd, (sub so_reg:$shift, GPR:$Rn))]> {
2298 let Inst{11-0} = shift;
2299 let Inst{15-12} = Rd;
2300 let Inst{19-16} = Rn;
2303 // RSB with 's' bit set.
2304 // NOTE: CPSR def omitted because it will be handled by the custom inserter.
2305 let usesCustomInserter = 1 in {
2306 def RSBSri : ARMPseudoInst<(outs GPR:$Rd), (ins GPR:$Rn, so_imm:$imm),
2307 Size4Bytes, IIC_iALUi,
2308 [(set GPR:$Rd, (subc so_imm:$imm, GPR:$Rn))]>;
2309 def RSBSrr : ARMPseudoInst<(outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm),
2310 Size4Bytes, IIC_iALUr,
2311 [/* For disassembly only; pattern left blank */]>;
2312 def RSBSrs : ARMPseudoInst<(outs GPR:$Rd), (ins GPR:$Rn, so_reg:$shift),
2313 Size4Bytes, IIC_iALUsr,
2314 [(set GPR:$Rd, (subc so_reg:$shift, GPR:$Rn))]>;
2317 let Uses = [CPSR] in {
2318 def RSCri : AsI1<0b0111, (outs GPR:$Rd), (ins GPR:$Rn, so_imm:$imm),
2319 DPFrm, IIC_iALUi, "rsc", "\t$Rd, $Rn, $imm",
2320 [(set GPR:$Rd, (sube_dead_carry so_imm:$imm, GPR:$Rn))]>,
2326 let Inst{15-12} = Rd;
2327 let Inst{19-16} = Rn;
2328 let Inst{11-0} = imm;
2330 // The reg/reg form is only defined for the disassembler; for codegen it is
2331 // equivalent to SUBrr.
2332 def RSCrr : AsI1<0b0111, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm),
2333 DPFrm, IIC_iALUr, "rsc", "\t$Rd, $Rn, $Rm",
2334 [/* For disassembly only; pattern left blank */]> {
2338 let Inst{11-4} = 0b00000000;
2341 let Inst{15-12} = Rd;
2342 let Inst{19-16} = Rn;
2344 def RSCrs : AsI1<0b0111, (outs GPR:$Rd), (ins GPR:$Rn, so_reg:$shift),
2345 DPSoRegFrm, IIC_iALUsr, "rsc", "\t$Rd, $Rn, $shift",
2346 [(set GPR:$Rd, (sube_dead_carry so_reg:$shift, GPR:$Rn))]>,
2352 let Inst{11-0} = shift;
2353 let Inst{15-12} = Rd;
2354 let Inst{19-16} = Rn;
2358 // NOTE: CPSR def omitted because it will be handled by the custom inserter.
2359 let usesCustomInserter = 1, Uses = [CPSR] in {
2360 def RSCSri : ARMPseudoInst<(outs GPR:$Rd), (ins GPR:$Rn, so_imm:$imm),
2361 Size4Bytes, IIC_iALUi,
2362 [(set GPR:$Rd, (sube_dead_carry so_imm:$imm, GPR:$Rn))]>;
2363 def RSCSrs : ARMPseudoInst<(outs GPR:$Rd), (ins GPR:$Rn, so_reg:$shift),
2364 Size4Bytes, IIC_iALUsr,
2365 [(set GPR:$Rd, (sube_dead_carry so_reg:$shift, GPR:$Rn))]>;
2368 // (sub X, imm) gets canonicalized to (add X, -imm). Match this form.
2369 // The assume-no-carry-in form uses the negation of the input since add/sub
2370 // assume opposite meanings of the carry flag (i.e., carry == !borrow).
2371 // See the definition of AddWithCarry() in the ARM ARM A2.2.1 for the gory
2373 def : ARMPat<(add GPR:$src, so_imm_neg:$imm),
2374 (SUBri GPR:$src, so_imm_neg:$imm)>;
2375 def : ARMPat<(addc GPR:$src, so_imm_neg:$imm),
2376 (SUBSri GPR:$src, so_imm_neg:$imm)>;
2377 // The with-carry-in form matches bitwise not instead of the negation.
2378 // Effectively, the inverse interpretation of the carry flag already accounts
2379 // for part of the negation.
2380 def : ARMPat<(adde_dead_carry GPR:$src, so_imm_not:$imm),
2381 (SBCri GPR:$src, so_imm_not:$imm)>;
2382 def : ARMPat<(adde_live_carry GPR:$src, so_imm_not:$imm),
2383 (SBCSri GPR:$src, so_imm_not:$imm)>;
2385 // Note: These are implemented in C++ code, because they have to generate
2386 // ADD/SUBrs instructions, which use a complex pattern that a xform function
2388 // (mul X, 2^n+1) -> (add (X << n), X)
2389 // (mul X, 2^n-1) -> (rsb X, (X << n))
2391 // ARM Arithmetic Instruction -- for disassembly only
2392 // GPR:$dst = GPR:$a op GPR:$b
2393 class AAI<bits<8> op27_20, bits<8> op11_4, string opc,
2394 list<dag> pattern = [/* For disassembly only; pattern left blank */],
2395 dag iops = (ins GPR:$Rn, GPR:$Rm), string asm = "\t$Rd, $Rn, $Rm">
2396 : AI<(outs GPR:$Rd), iops, DPFrm, IIC_iALUr, opc, asm, pattern> {
2400 let Inst{27-20} = op27_20;
2401 let Inst{11-4} = op11_4;
2402 let Inst{19-16} = Rn;
2403 let Inst{15-12} = Rd;
2407 // Saturating add/subtract -- for disassembly only
2409 def QADD : AAI<0b00010000, 0b00000101, "qadd",
2410 [(set GPR:$Rd, (int_arm_qadd GPR:$Rm, GPR:$Rn))],
2411 (ins GPR:$Rm, GPR:$Rn), "\t$Rd, $Rm, $Rn">;
2412 def QSUB : AAI<0b00010010, 0b00000101, "qsub",
2413 [(set GPR:$Rd, (int_arm_qsub GPR:$Rm, GPR:$Rn))],
2414 (ins GPR:$Rm, GPR:$Rn), "\t$Rd, $Rm, $Rn">;
2415 def QDADD : AAI<0b00010100, 0b00000101, "qdadd", [], (ins GPR:$Rm, GPR:$Rn),
2417 def QDSUB : AAI<0b00010110, 0b00000101, "qdsub", [], (ins GPR:$Rm, GPR:$Rn),
2420 def QADD16 : AAI<0b01100010, 0b11110001, "qadd16">;
2421 def QADD8 : AAI<0b01100010, 0b11111001, "qadd8">;
2422 def QASX : AAI<0b01100010, 0b11110011, "qasx">;
2423 def QSAX : AAI<0b01100010, 0b11110101, "qsax">;
2424 def QSUB16 : AAI<0b01100010, 0b11110111, "qsub16">;
2425 def QSUB8 : AAI<0b01100010, 0b11111111, "qsub8">;
2426 def UQADD16 : AAI<0b01100110, 0b11110001, "uqadd16">;
2427 def UQADD8 : AAI<0b01100110, 0b11111001, "uqadd8">;
2428 def UQASX : AAI<0b01100110, 0b11110011, "uqasx">;
2429 def UQSAX : AAI<0b01100110, 0b11110101, "uqsax">;
2430 def UQSUB16 : AAI<0b01100110, 0b11110111, "uqsub16">;
2431 def UQSUB8 : AAI<0b01100110, 0b11111111, "uqsub8">;
2433 // Signed/Unsigned add/subtract -- for disassembly only
2435 def SASX : AAI<0b01100001, 0b11110011, "sasx">;
2436 def SADD16 : AAI<0b01100001, 0b11110001, "sadd16">;
2437 def SADD8 : AAI<0b01100001, 0b11111001, "sadd8">;
2438 def SSAX : AAI<0b01100001, 0b11110101, "ssax">;
2439 def SSUB16 : AAI<0b01100001, 0b11110111, "ssub16">;
2440 def SSUB8 : AAI<0b01100001, 0b11111111, "ssub8">;
2441 def UASX : AAI<0b01100101, 0b11110011, "uasx">;
2442 def UADD16 : AAI<0b01100101, 0b11110001, "uadd16">;
2443 def UADD8 : AAI<0b01100101, 0b11111001, "uadd8">;
2444 def USAX : AAI<0b01100101, 0b11110101, "usax">;
2445 def USUB16 : AAI<0b01100101, 0b11110111, "usub16">;
2446 def USUB8 : AAI<0b01100101, 0b11111111, "usub8">;
2448 // Signed/Unsigned halving add/subtract -- for disassembly only
2450 def SHASX : AAI<0b01100011, 0b11110011, "shasx">;
2451 def SHADD16 : AAI<0b01100011, 0b11110001, "shadd16">;
2452 def SHADD8 : AAI<0b01100011, 0b11111001, "shadd8">;
2453 def SHSAX : AAI<0b01100011, 0b11110101, "shsax">;
2454 def SHSUB16 : AAI<0b01100011, 0b11110111, "shsub16">;
2455 def SHSUB8 : AAI<0b01100011, 0b11111111, "shsub8">;
2456 def UHASX : AAI<0b01100111, 0b11110011, "uhasx">;
2457 def UHADD16 : AAI<0b01100111, 0b11110001, "uhadd16">;
2458 def UHADD8 : AAI<0b01100111, 0b11111001, "uhadd8">;
2459 def UHSAX : AAI<0b01100111, 0b11110101, "uhsax">;
2460 def UHSUB16 : AAI<0b01100111, 0b11110111, "uhsub16">;
2461 def UHSUB8 : AAI<0b01100111, 0b11111111, "uhsub8">;
2463 // Unsigned Sum of Absolute Differences [and Accumulate] -- for disassembly only
2465 def USAD8 : AI<(outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm),
2466 MulFrm /* for convenience */, NoItinerary, "usad8",
2467 "\t$Rd, $Rn, $Rm", []>,
2468 Requires<[IsARM, HasV6]> {
2472 let Inst{27-20} = 0b01111000;
2473 let Inst{15-12} = 0b1111;
2474 let Inst{7-4} = 0b0001;
2475 let Inst{19-16} = Rd;
2476 let Inst{11-8} = Rm;
2479 def USADA8 : AI<(outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm, GPR:$Ra),
2480 MulFrm /* for convenience */, NoItinerary, "usada8",
2481 "\t$Rd, $Rn, $Rm, $Ra", []>,
2482 Requires<[IsARM, HasV6]> {
2487 let Inst{27-20} = 0b01111000;
2488 let Inst{7-4} = 0b0001;
2489 let Inst{19-16} = Rd;
2490 let Inst{15-12} = Ra;
2491 let Inst{11-8} = Rm;
2495 // Signed/Unsigned saturate -- for disassembly only
2497 def SSAT : AI<(outs GPR:$Rd), (ins ssat_imm:$sat_imm, GPR:$a, shift_imm:$sh),
2498 SatFrm, NoItinerary, "ssat", "\t$Rd, $sat_imm, $a$sh",
2499 [/* For disassembly only; pattern left blank */]> {
2504 let Inst{27-21} = 0b0110101;
2505 let Inst{5-4} = 0b01;
2506 let Inst{20-16} = sat_imm;
2507 let Inst{15-12} = Rd;
2508 let Inst{11-7} = sh{7-3};
2509 let Inst{6} = sh{0};
2513 def SSAT16 : AI<(outs GPR:$Rd), (ins ssat_imm:$sat_imm, GPR:$Rn), SatFrm,
2514 NoItinerary, "ssat16", "\t$Rd, $sat_imm, $Rn",
2515 [/* For disassembly only; pattern left blank */]> {
2519 let Inst{27-20} = 0b01101010;
2520 let Inst{11-4} = 0b11110011;
2521 let Inst{15-12} = Rd;
2522 let Inst{19-16} = sat_imm;
2526 def USAT : AI<(outs GPR:$Rd), (ins i32imm:$sat_imm, GPR:$a, shift_imm:$sh),
2527 SatFrm, NoItinerary, "usat", "\t$Rd, $sat_imm, $a$sh",
2528 [/* For disassembly only; pattern left blank */]> {
2533 let Inst{27-21} = 0b0110111;
2534 let Inst{5-4} = 0b01;
2535 let Inst{15-12} = Rd;
2536 let Inst{11-7} = sh{7-3};
2537 let Inst{6} = sh{0};
2538 let Inst{20-16} = sat_imm;
2542 def USAT16 : AI<(outs GPR:$Rd), (ins i32imm:$sat_imm, GPR:$a), SatFrm,
2543 NoItinerary, "usat16", "\t$Rd, $sat_imm, $a",
2544 [/* For disassembly only; pattern left blank */]> {
2548 let Inst{27-20} = 0b01101110;
2549 let Inst{11-4} = 0b11110011;
2550 let Inst{15-12} = Rd;
2551 let Inst{19-16} = sat_imm;
2555 def : ARMV6Pat<(int_arm_ssat GPR:$a, imm:$pos), (SSAT imm:$pos, GPR:$a, 0)>;
2556 def : ARMV6Pat<(int_arm_usat GPR:$a, imm:$pos), (USAT imm:$pos, GPR:$a, 0)>;
2558 //===----------------------------------------------------------------------===//
2559 // Bitwise Instructions.
2562 defm AND : AsI1_bin_irs<0b0000, "and",
2563 IIC_iBITi, IIC_iBITr, IIC_iBITsr,
2564 BinOpFrag<(and node:$LHS, node:$RHS)>, "AND", 1>;
2565 defm ORR : AsI1_bin_irs<0b1100, "orr",
2566 IIC_iBITi, IIC_iBITr, IIC_iBITsr,
2567 BinOpFrag<(or node:$LHS, node:$RHS)>, "ORR", 1>;
2568 defm EOR : AsI1_bin_irs<0b0001, "eor",
2569 IIC_iBITi, IIC_iBITr, IIC_iBITsr,
2570 BinOpFrag<(xor node:$LHS, node:$RHS)>, "EOR", 1>;
2571 defm BIC : AsI1_bin_irs<0b1110, "bic",
2572 IIC_iBITi, IIC_iBITr, IIC_iBITsr,
2573 BinOpFrag<(and node:$LHS, (not node:$RHS))>, "BIC">;
2575 def BFC : I<(outs GPR:$Rd), (ins GPR:$src, bf_inv_mask_imm:$imm),
2576 AddrMode1, Size4Bytes, IndexModeNone, DPFrm, IIC_iUNAsi,
2577 "bfc", "\t$Rd, $imm", "$src = $Rd",
2578 [(set GPR:$Rd, (and GPR:$src, bf_inv_mask_imm:$imm))]>,
2579 Requires<[IsARM, HasV6T2]> {
2582 let Inst{27-21} = 0b0111110;
2583 let Inst{6-0} = 0b0011111;
2584 let Inst{15-12} = Rd;
2585 let Inst{11-7} = imm{4-0}; // lsb
2586 let Inst{20-16} = imm{9-5}; // width
2589 // A8.6.18 BFI - Bitfield insert (Encoding A1)
2590 def BFI : I<(outs GPR:$Rd), (ins GPR:$src, GPR:$Rn, bf_inv_mask_imm:$imm),
2591 AddrMode1, Size4Bytes, IndexModeNone, DPFrm, IIC_iUNAsi,
2592 "bfi", "\t$Rd, $Rn, $imm", "$src = $Rd",
2593 [(set GPR:$Rd, (ARMbfi GPR:$src, GPR:$Rn,
2594 bf_inv_mask_imm:$imm))]>,
2595 Requires<[IsARM, HasV6T2]> {
2599 let Inst{27-21} = 0b0111110;
2600 let Inst{6-4} = 0b001; // Rn: Inst{3-0} != 15
2601 let Inst{15-12} = Rd;
2602 let Inst{11-7} = imm{4-0}; // lsb
2603 let Inst{20-16} = imm{9-5}; // width
2607 // GNU as only supports this form of bfi (w/ 4 arguments)
2608 let isAsmParserOnly = 1 in
2609 def BFI4p : I<(outs GPR:$Rd), (ins GPR:$src, GPR:$Rn,
2610 lsb_pos_imm:$lsb, width_imm:$width),
2611 AddrMode1, Size4Bytes, IndexModeNone, DPFrm, IIC_iUNAsi,
2612 "bfi", "\t$Rd, $Rn, $lsb, $width", "$src = $Rd",
2613 []>, Requires<[IsARM, HasV6T2]> {
2618 let Inst{27-21} = 0b0111110;
2619 let Inst{6-4} = 0b001; // Rn: Inst{3-0} != 15
2620 let Inst{15-12} = Rd;
2621 let Inst{11-7} = lsb;
2622 let Inst{20-16} = width; // Custom encoder => lsb+width-1
2626 def MVNr : AsI1<0b1111, (outs GPR:$Rd), (ins GPR:$Rm), DPFrm, IIC_iMVNr,
2627 "mvn", "\t$Rd, $Rm",
2628 [(set GPR:$Rd, (not GPR:$Rm))]>, UnaryDP {
2632 let Inst{19-16} = 0b0000;
2633 let Inst{11-4} = 0b00000000;
2634 let Inst{15-12} = Rd;
2637 def MVNs : AsI1<0b1111, (outs GPR:$Rd), (ins so_reg:$shift), DPSoRegFrm,
2638 IIC_iMVNsr, "mvn", "\t$Rd, $shift",
2639 [(set GPR:$Rd, (not so_reg:$shift))]>, UnaryDP {
2643 let Inst{19-16} = 0b0000;
2644 let Inst{15-12} = Rd;
2645 let Inst{11-0} = shift;
2647 let isReMaterializable = 1, isAsCheapAsAMove = 1, isMoveImm = 1 in
2648 def MVNi : AsI1<0b1111, (outs GPR:$Rd), (ins so_imm:$imm), DPFrm,
2649 IIC_iMVNi, "mvn", "\t$Rd, $imm",
2650 [(set GPR:$Rd, so_imm_not:$imm)]>,UnaryDP {
2654 let Inst{19-16} = 0b0000;
2655 let Inst{15-12} = Rd;
2656 let Inst{11-0} = imm;
2659 def : ARMPat<(and GPR:$src, so_imm_not:$imm),
2660 (BICri GPR:$src, so_imm_not:$imm)>;
2662 //===----------------------------------------------------------------------===//
2663 // Multiply Instructions.
2665 class AsMul1I32<bits<7> opcod, dag oops, dag iops, InstrItinClass itin,
2666 string opc, string asm, list<dag> pattern>
2667 : AsMul1I<opcod, oops, iops, itin, opc, asm, pattern> {
2671 let Inst{19-16} = Rd;
2672 let Inst{11-8} = Rm;
2675 class AsMul1I64<bits<7> opcod, dag oops, dag iops, InstrItinClass itin,
2676 string opc, string asm, list<dag> pattern>
2677 : AsMul1I<opcod, oops, iops, itin, opc, asm, pattern> {
2682 let Inst{19-16} = RdHi;
2683 let Inst{15-12} = RdLo;
2684 let Inst{11-8} = Rm;
2688 // FIXME: The v5 pseudos are only necessary for the additional Constraint
2689 // property. Remove them when it's possible to add those properties
2690 // on an individual MachineInstr, not just an instuction description.
2691 let isCommutable = 1 in {
2692 def MUL : AsMul1I32<0b0000000, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm),
2693 IIC_iMUL32, "mul", "\t$Rd, $Rn, $Rm",
2694 [(set GPR:$Rd, (mul GPR:$Rn, GPR:$Rm))]>,
2695 Requires<[IsARM, HasV6]> {
2696 let Inst{15-12} = 0b0000;
2699 let Constraints = "@earlyclobber $Rd" in
2700 def MULv5: ARMPseudoExpand<(outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm,
2701 pred:$p, cc_out:$s),
2702 Size4Bytes, IIC_iMUL32,
2703 [(set GPR:$Rd, (mul GPR:$Rn, GPR:$Rm))],
2704 (MUL GPR:$Rd, GPR:$Rn, GPR:$Rm, pred:$p, cc_out:$s)>,
2705 Requires<[IsARM, NoV6]>;
2708 def MLA : AsMul1I32<0b0000001, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm, GPR:$Ra),
2709 IIC_iMAC32, "mla", "\t$Rd, $Rn, $Rm, $Ra",
2710 [(set GPR:$Rd, (add (mul GPR:$Rn, GPR:$Rm), GPR:$Ra))]>,
2711 Requires<[IsARM, HasV6]> {
2713 let Inst{15-12} = Ra;
2716 let Constraints = "@earlyclobber $Rd" in
2717 def MLAv5: ARMPseudoExpand<(outs GPR:$Rd),
2718 (ins GPR:$Rn, GPR:$Rm, GPR:$Ra, pred:$p, cc_out:$s),
2719 Size4Bytes, IIC_iMAC32,
2720 [(set GPR:$Rd, (add (mul GPR:$Rn, GPR:$Rm), GPR:$Ra))],
2721 (MLA GPR:$Rd, GPR:$Rn, GPR:$Rm, GPR:$Ra, pred:$p, cc_out:$s)>,
2722 Requires<[IsARM, NoV6]>;
2724 def MLS : AMul1I<0b0000011, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm, GPR:$Ra),
2725 IIC_iMAC32, "mls", "\t$Rd, $Rn, $Rm, $Ra",
2726 [(set GPR:$Rd, (sub GPR:$Ra, (mul GPR:$Rn, GPR:$Rm)))]>,
2727 Requires<[IsARM, HasV6T2]> {
2732 let Inst{19-16} = Rd;
2733 let Inst{15-12} = Ra;
2734 let Inst{11-8} = Rm;
2738 // Extra precision multiplies with low / high results
2739 let neverHasSideEffects = 1 in {
2740 let isCommutable = 1 in {
2741 def SMULL : AsMul1I64<0b0000110, (outs GPR:$RdLo, GPR:$RdHi),
2742 (ins GPR:$Rn, GPR:$Rm), IIC_iMUL64,
2743 "smull", "\t$RdLo, $RdHi, $Rn, $Rm", []>,
2744 Requires<[IsARM, HasV6]>;
2746 def UMULL : AsMul1I64<0b0000100, (outs GPR:$RdLo, GPR:$RdHi),
2747 (ins GPR:$Rn, GPR:$Rm), IIC_iMUL64,
2748 "umull", "\t$RdLo, $RdHi, $Rn, $Rm", []>,
2749 Requires<[IsARM, HasV6]>;
2751 let Constraints = "@earlyclobber $RdLo,@earlyclobber $RdHi" in {
2752 def SMULLv5 : ARMPseudoExpand<(outs GPR:$RdLo, GPR:$RdHi),
2753 (ins GPR:$Rn, GPR:$Rm, pred:$p, cc_out:$s),
2754 Size4Bytes, IIC_iMUL64, [],
2755 (SMULL GPR:$RdLo, GPR:$RdHi, GPR:$Rn, GPR:$Rm, pred:$p, cc_out:$s)>,
2756 Requires<[IsARM, NoV6]>;
2758 def UMULLv5 : ARMPseudoExpand<(outs GPR:$RdLo, GPR:$RdHi),
2759 (ins GPR:$Rn, GPR:$Rm, pred:$p, cc_out:$s),
2760 Size4Bytes, IIC_iMUL64, [],
2761 (UMULL GPR:$RdLo, GPR:$RdHi, GPR:$Rn, GPR:$Rm, pred:$p, cc_out:$s)>,
2762 Requires<[IsARM, NoV6]>;
2766 // Multiply + accumulate
2767 def SMLAL : AsMul1I64<0b0000111, (outs GPR:$RdLo, GPR:$RdHi),
2768 (ins GPR:$Rn, GPR:$Rm), IIC_iMAC64,
2769 "smlal", "\t$RdLo, $RdHi, $Rn, $Rm", []>,
2770 Requires<[IsARM, HasV6]>;
2771 def UMLAL : AsMul1I64<0b0000101, (outs GPR:$RdLo, GPR:$RdHi),
2772 (ins GPR:$Rn, GPR:$Rm), IIC_iMAC64,
2773 "umlal", "\t$RdLo, $RdHi, $Rn, $Rm", []>,
2774 Requires<[IsARM, HasV6]>;
2776 def UMAAL : AMul1I <0b0000010, (outs GPR:$RdLo, GPR:$RdHi),
2777 (ins GPR:$Rn, GPR:$Rm), IIC_iMAC64,
2778 "umaal", "\t$RdLo, $RdHi, $Rn, $Rm", []>,
2779 Requires<[IsARM, HasV6]> {
2784 let Inst{19-16} = RdLo;
2785 let Inst{15-12} = RdHi;
2786 let Inst{11-8} = Rm;
2790 let Constraints = "@earlyclobber $RdLo,@earlyclobber $RdHi" in {
2791 def SMLALv5 : ARMPseudoExpand<(outs GPR:$RdLo, GPR:$RdHi),
2792 (ins GPR:$Rn, GPR:$Rm, pred:$p, cc_out:$s),
2793 Size4Bytes, IIC_iMAC64, [],
2794 (SMLAL GPR:$RdLo, GPR:$RdHi, GPR:$Rn, GPR:$Rm, pred:$p, cc_out:$s)>,
2795 Requires<[IsARM, NoV6]>;
2796 def UMLALv5 : ARMPseudoExpand<(outs GPR:$RdLo, GPR:$RdHi),
2797 (ins GPR:$Rn, GPR:$Rm, pred:$p, cc_out:$s),
2798 Size4Bytes, IIC_iMAC64, [],
2799 (UMLAL GPR:$RdLo, GPR:$RdHi, GPR:$Rn, GPR:$Rm, pred:$p, cc_out:$s)>,
2800 Requires<[IsARM, NoV6]>;
2801 def UMAALv5 : ARMPseudoExpand<(outs GPR:$RdLo, GPR:$RdHi),
2802 (ins GPR:$Rn, GPR:$Rm, pred:$p),
2803 Size4Bytes, IIC_iMAC64, [],
2804 (UMAAL GPR:$RdLo, GPR:$RdHi, GPR:$Rn, GPR:$Rm, pred:$p)>,
2805 Requires<[IsARM, NoV6]>;
2808 } // neverHasSideEffects
2810 // Most significant word multiply
2811 def SMMUL : AMul2I <0b0111010, 0b0001, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm),
2812 IIC_iMUL32, "smmul", "\t$Rd, $Rn, $Rm",
2813 [(set GPR:$Rd, (mulhs GPR:$Rn, GPR:$Rm))]>,
2814 Requires<[IsARM, HasV6]> {
2815 let Inst{15-12} = 0b1111;
2818 def SMMULR : AMul2I <0b0111010, 0b0011, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm),
2819 IIC_iMUL32, "smmulr", "\t$Rd, $Rn, $Rm",
2820 [/* For disassembly only; pattern left blank */]>,
2821 Requires<[IsARM, HasV6]> {
2822 let Inst{15-12} = 0b1111;
2825 def SMMLA : AMul2Ia <0b0111010, 0b0001, (outs GPR:$Rd),
2826 (ins GPR:$Rn, GPR:$Rm, GPR:$Ra),
2827 IIC_iMAC32, "smmla", "\t$Rd, $Rn, $Rm, $Ra",
2828 [(set GPR:$Rd, (add (mulhs GPR:$Rn, GPR:$Rm), GPR:$Ra))]>,
2829 Requires<[IsARM, HasV6]>;
2831 def SMMLAR : AMul2Ia <0b0111010, 0b0011, (outs GPR:$Rd),
2832 (ins GPR:$Rn, GPR:$Rm, GPR:$Ra),
2833 IIC_iMAC32, "smmlar", "\t$Rd, $Rn, $Rm, $Ra",
2834 [/* For disassembly only; pattern left blank */]>,
2835 Requires<[IsARM, HasV6]>;
2837 def SMMLS : AMul2Ia <0b0111010, 0b1101, (outs GPR:$Rd),
2838 (ins GPR:$Rn, GPR:$Rm, GPR:$Ra),
2839 IIC_iMAC32, "smmls", "\t$Rd, $Rn, $Rm, $Ra",
2840 [(set GPR:$Rd, (sub GPR:$Ra, (mulhs GPR:$Rn, GPR:$Rm)))]>,
2841 Requires<[IsARM, HasV6]>;
2843 def SMMLSR : AMul2Ia <0b0111010, 0b1111, (outs GPR:$Rd),
2844 (ins GPR:$Rn, GPR:$Rm, GPR:$Ra),
2845 IIC_iMAC32, "smmlsr", "\t$Rd, $Rn, $Rm, $Ra",
2846 [/* For disassembly only; pattern left blank */]>,
2847 Requires<[IsARM, HasV6]>;
2849 multiclass AI_smul<string opc, PatFrag opnode> {
2850 def BB : AMulxyI<0b0001011, 0b00, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm),
2851 IIC_iMUL16, !strconcat(opc, "bb"), "\t$Rd, $Rn, $Rm",
2852 [(set GPR:$Rd, (opnode (sext_inreg GPR:$Rn, i16),
2853 (sext_inreg GPR:$Rm, i16)))]>,
2854 Requires<[IsARM, HasV5TE]>;
2856 def BT : AMulxyI<0b0001011, 0b10, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm),
2857 IIC_iMUL16, !strconcat(opc, "bt"), "\t$Rd, $Rn, $Rm",
2858 [(set GPR:$Rd, (opnode (sext_inreg GPR:$Rn, i16),
2859 (sra GPR:$Rm, (i32 16))))]>,
2860 Requires<[IsARM, HasV5TE]>;
2862 def TB : AMulxyI<0b0001011, 0b01, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm),
2863 IIC_iMUL16, !strconcat(opc, "tb"), "\t$Rd, $Rn, $Rm",
2864 [(set GPR:$Rd, (opnode (sra GPR:$Rn, (i32 16)),
2865 (sext_inreg GPR:$Rm, i16)))]>,
2866 Requires<[IsARM, HasV5TE]>;
2868 def TT : AMulxyI<0b0001011, 0b11, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm),
2869 IIC_iMUL16, !strconcat(opc, "tt"), "\t$Rd, $Rn, $Rm",
2870 [(set GPR:$Rd, (opnode (sra GPR:$Rn, (i32 16)),
2871 (sra GPR:$Rm, (i32 16))))]>,
2872 Requires<[IsARM, HasV5TE]>;
2874 def WB : AMulxyI<0b0001001, 0b01, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm),
2875 IIC_iMUL16, !strconcat(opc, "wb"), "\t$Rd, $Rn, $Rm",
2876 [(set GPR:$Rd, (sra (opnode GPR:$Rn,
2877 (sext_inreg GPR:$Rm, i16)), (i32 16)))]>,
2878 Requires<[IsARM, HasV5TE]>;
2880 def WT : AMulxyI<0b0001001, 0b11, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm),
2881 IIC_iMUL16, !strconcat(opc, "wt"), "\t$Rd, $Rn, $Rm",
2882 [(set GPR:$Rd, (sra (opnode GPR:$Rn,
2883 (sra GPR:$Rm, (i32 16))), (i32 16)))]>,
2884 Requires<[IsARM, HasV5TE]>;
2888 multiclass AI_smla<string opc, PatFrag opnode> {
2889 def BB : AMulxyIa<0b0001000, 0b00, (outs GPR:$Rd),
2890 (ins GPR:$Rn, GPR:$Rm, GPR:$Ra),
2891 IIC_iMAC16, !strconcat(opc, "bb"), "\t$Rd, $Rn, $Rm, $Ra",
2892 [(set GPR:$Rd, (add GPR:$Ra,
2893 (opnode (sext_inreg GPR:$Rn, i16),
2894 (sext_inreg GPR:$Rm, i16))))]>,
2895 Requires<[IsARM, HasV5TE]>;
2897 def BT : AMulxyIa<0b0001000, 0b10, (outs GPR:$Rd),
2898 (ins GPR:$Rn, GPR:$Rm, GPR:$Ra),
2899 IIC_iMAC16, !strconcat(opc, "bt"), "\t$Rd, $Rn, $Rm, $Ra",
2900 [(set GPR:$Rd, (add GPR:$Ra, (opnode (sext_inreg GPR:$Rn, i16),
2901 (sra GPR:$Rm, (i32 16)))))]>,
2902 Requires<[IsARM, HasV5TE]>;
2904 def TB : AMulxyIa<0b0001000, 0b01, (outs GPR:$Rd),
2905 (ins GPR:$Rn, GPR:$Rm, GPR:$Ra),
2906 IIC_iMAC16, !strconcat(opc, "tb"), "\t$Rd, $Rn, $Rm, $Ra",
2907 [(set GPR:$Rd, (add GPR:$Ra, (opnode (sra GPR:$Rn, (i32 16)),
2908 (sext_inreg GPR:$Rm, i16))))]>,
2909 Requires<[IsARM, HasV5TE]>;
2911 def TT : AMulxyIa<0b0001000, 0b11, (outs GPR:$Rd),
2912 (ins GPR:$Rn, GPR:$Rm, GPR:$Ra),
2913 IIC_iMAC16, !strconcat(opc, "tt"), "\t$Rd, $Rn, $Rm, $Ra",
2914 [(set GPR:$Rd, (add GPR:$Ra, (opnode (sra GPR:$Rn, (i32 16)),
2915 (sra GPR:$Rm, (i32 16)))))]>,
2916 Requires<[IsARM, HasV5TE]>;
2918 def WB : AMulxyIa<0b0001001, 0b00, (outs GPR:$Rd),
2919 (ins GPR:$Rn, GPR:$Rm, GPR:$Ra),
2920 IIC_iMAC16, !strconcat(opc, "wb"), "\t$Rd, $Rn, $Rm, $Ra",
2921 [(set GPR:$Rd, (add GPR:$Ra, (sra (opnode GPR:$Rn,
2922 (sext_inreg GPR:$Rm, i16)), (i32 16))))]>,
2923 Requires<[IsARM, HasV5TE]>;
2925 def WT : AMulxyIa<0b0001001, 0b10, (outs GPR:$Rd),
2926 (ins GPR:$Rn, GPR:$Rm, GPR:$Ra),
2927 IIC_iMAC16, !strconcat(opc, "wt"), "\t$Rd, $Rn, $Rm, $Ra",
2928 [(set GPR:$Rd, (add GPR:$Ra, (sra (opnode GPR:$Rn,
2929 (sra GPR:$Rm, (i32 16))), (i32 16))))]>,
2930 Requires<[IsARM, HasV5TE]>;
2933 defm SMUL : AI_smul<"smul", BinOpFrag<(mul node:$LHS, node:$RHS)>>;
2934 defm SMLA : AI_smla<"smla", BinOpFrag<(mul node:$LHS, node:$RHS)>>;
2936 // Halfword multiply accumulate long: SMLAL<x><y> -- for disassembly only
2937 def SMLALBB : AMulxyI64<0b0001010, 0b00, (outs GPR:$RdLo, GPR:$RdHi),
2938 (ins GPR:$Rn, GPR:$Rm),
2939 IIC_iMAC64, "smlalbb", "\t$RdLo, $RdHi, $Rn, $Rm",
2940 [/* For disassembly only; pattern left blank */]>,
2941 Requires<[IsARM, HasV5TE]>;
2943 def SMLALBT : AMulxyI64<0b0001010, 0b10, (outs GPR:$RdLo, GPR:$RdHi),
2944 (ins GPR:$Rn, GPR:$Rm),
2945 IIC_iMAC64, "smlalbt", "\t$RdLo, $RdHi, $Rn, $Rm",
2946 [/* For disassembly only; pattern left blank */]>,
2947 Requires<[IsARM, HasV5TE]>;
2949 def SMLALTB : AMulxyI64<0b0001010, 0b01, (outs GPR:$RdLo, GPR:$RdHi),
2950 (ins GPR:$Rn, GPR:$Rm),
2951 IIC_iMAC64, "smlaltb", "\t$RdLo, $RdHi, $Rn, $Rm",
2952 [/* For disassembly only; pattern left blank */]>,
2953 Requires<[IsARM, HasV5TE]>;
2955 def SMLALTT : AMulxyI64<0b0001010, 0b11, (outs GPR:$RdLo, GPR:$RdHi),
2956 (ins GPR:$Rn, GPR:$Rm),
2957 IIC_iMAC64, "smlaltt", "\t$RdLo, $RdHi, $Rn, $Rm",
2958 [/* For disassembly only; pattern left blank */]>,
2959 Requires<[IsARM, HasV5TE]>;
2961 // Helper class for AI_smld -- for disassembly only
2962 class AMulDualIbase<bit long, bit sub, bit swap, dag oops, dag iops,
2963 InstrItinClass itin, string opc, string asm>
2964 : AI<oops, iops, MulFrm, itin, opc, asm, []>, Requires<[IsARM, HasV6]> {
2971 let Inst{21-20} = 0b00;
2972 let Inst{22} = long;
2973 let Inst{27-23} = 0b01110;
2974 let Inst{11-8} = Rm;
2977 class AMulDualI<bit long, bit sub, bit swap, dag oops, dag iops,
2978 InstrItinClass itin, string opc, string asm>
2979 : AMulDualIbase<long, sub, swap, oops, iops, itin, opc, asm> {
2981 let Inst{15-12} = 0b1111;
2982 let Inst{19-16} = Rd;
2984 class AMulDualIa<bit long, bit sub, bit swap, dag oops, dag iops,
2985 InstrItinClass itin, string opc, string asm>
2986 : AMulDualIbase<long, sub, swap, oops, iops, itin, opc, asm> {
2988 let Inst{15-12} = Ra;
2990 class AMulDualI64<bit long, bit sub, bit swap, dag oops, dag iops,
2991 InstrItinClass itin, string opc, string asm>
2992 : AMulDualIbase<long, sub, swap, oops, iops, itin, opc, asm> {
2995 let Inst{19-16} = RdHi;
2996 let Inst{15-12} = RdLo;
2999 multiclass AI_smld<bit sub, string opc> {
3001 def D : AMulDualIa<0, sub, 0, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm, GPR:$Ra),
3002 NoItinerary, !strconcat(opc, "d"), "\t$Rd, $Rn, $Rm, $Ra">;
3004 def DX: AMulDualIa<0, sub, 1, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm, GPR:$Ra),
3005 NoItinerary, !strconcat(opc, "dx"), "\t$Rd, $Rn, $Rm, $Ra">;
3007 def LD: AMulDualI64<1, sub, 0, (outs GPR:$RdLo,GPR:$RdHi),
3008 (ins GPR:$Rn, GPR:$Rm), NoItinerary,
3009 !strconcat(opc, "ld"), "\t$RdLo, $RdHi, $Rn, $Rm">;
3011 def LDX : AMulDualI64<1, sub, 1, (outs GPR:$RdLo,GPR:$RdHi),
3012 (ins GPR:$Rn, GPR:$Rm), NoItinerary,
3013 !strconcat(opc, "ldx"),"\t$RdLo, $RdHi, $Rn, $Rm">;
3017 defm SMLA : AI_smld<0, "smla">;
3018 defm SMLS : AI_smld<1, "smls">;
3020 multiclass AI_sdml<bit sub, string opc> {
3022 def D : AMulDualI<0, sub, 0, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm),
3023 NoItinerary, !strconcat(opc, "d"), "\t$Rd, $Rn, $Rm">;
3024 def DX : AMulDualI<0, sub, 1, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm),
3025 NoItinerary, !strconcat(opc, "dx"), "\t$Rd, $Rn, $Rm">;
3028 defm SMUA : AI_sdml<0, "smua">;
3029 defm SMUS : AI_sdml<1, "smus">;
3031 //===----------------------------------------------------------------------===//
3032 // Misc. Arithmetic Instructions.
3035 def CLZ : AMiscA1I<0b000010110, 0b0001, (outs GPR:$Rd), (ins GPR:$Rm),
3036 IIC_iUNAr, "clz", "\t$Rd, $Rm",
3037 [(set GPR:$Rd, (ctlz GPR:$Rm))]>, Requires<[IsARM, HasV5T]>;
3039 def RBIT : AMiscA1I<0b01101111, 0b0011, (outs GPR:$Rd), (ins GPR:$Rm),
3040 IIC_iUNAr, "rbit", "\t$Rd, $Rm",
3041 [(set GPR:$Rd, (ARMrbit GPR:$Rm))]>,
3042 Requires<[IsARM, HasV6T2]>;
3044 def REV : AMiscA1I<0b01101011, 0b0011, (outs GPR:$Rd), (ins GPR:$Rm),
3045 IIC_iUNAr, "rev", "\t$Rd, $Rm",
3046 [(set GPR:$Rd, (bswap GPR:$Rm))]>, Requires<[IsARM, HasV6]>;
3048 let AddedComplexity = 5 in
3049 def REV16 : AMiscA1I<0b01101011, 0b1011, (outs GPR:$Rd), (ins GPR:$Rm),
3050 IIC_iUNAr, "rev16", "\t$Rd, $Rm",
3051 [(set GPR:$Rd, (rotr (bswap GPR:$Rm), (i32 16)))]>,
3052 Requires<[IsARM, HasV6]>;
3054 let AddedComplexity = 5 in
3055 def REVSH : AMiscA1I<0b01101111, 0b1011, (outs GPR:$Rd), (ins GPR:$Rm),
3056 IIC_iUNAr, "revsh", "\t$Rd, $Rm",
3057 [(set GPR:$Rd, (sra (bswap GPR:$Rm), (i32 16)))]>,
3058 Requires<[IsARM, HasV6]>;
3060 def : ARMV6Pat<(or (sra (shl GPR:$Rm, (i32 24)), (i32 16)),
3061 (and (srl GPR:$Rm, (i32 8)), 0xFF)),
3064 def lsl_shift_imm : SDNodeXForm<imm, [{
3065 unsigned Sh = ARM_AM::getSORegOpc(ARM_AM::lsl, N->getZExtValue());
3066 return CurDAG->getTargetConstant(Sh, MVT::i32);
3069 def lsl_amt : ImmLeaf<i32, [{
3070 return Imm > 0 && Imm < 32;
3073 def PKHBT : APKHI<0b01101000, 0, (outs GPR:$Rd),
3074 (ins GPR:$Rn, GPR:$Rm, shift_imm:$sh),
3075 IIC_iALUsi, "pkhbt", "\t$Rd, $Rn, $Rm$sh",
3076 [(set GPR:$Rd, (or (and GPR:$Rn, 0xFFFF),
3077 (and (shl GPR:$Rm, lsl_amt:$sh),
3079 Requires<[IsARM, HasV6]>;
3081 // Alternate cases for PKHBT where identities eliminate some nodes.
3082 def : ARMV6Pat<(or (and GPR:$Rn, 0xFFFF), (and GPR:$Rm, 0xFFFF0000)),
3083 (PKHBT GPR:$Rn, GPR:$Rm, 0)>;
3084 def : ARMV6Pat<(or (and GPR:$Rn, 0xFFFF), (shl GPR:$Rm, imm16_31:$sh)),
3085 (PKHBT GPR:$Rn, GPR:$Rm, (lsl_shift_imm imm16_31:$sh))>;
3087 def asr_shift_imm : SDNodeXForm<imm, [{
3088 unsigned Sh = ARM_AM::getSORegOpc(ARM_AM::asr, N->getZExtValue());
3089 return CurDAG->getTargetConstant(Sh, MVT::i32);
3092 def asr_amt : ImmLeaf<i32, [{
3093 return Imm > 0 && Imm <= 32;
3096 // Note: Shifts of 1-15 bits will be transformed to srl instead of sra and
3097 // will match the pattern below.
3098 def PKHTB : APKHI<0b01101000, 1, (outs GPR:$Rd),
3099 (ins GPR:$Rn, GPR:$Rm, shift_imm:$sh),
3100 IIC_iBITsi, "pkhtb", "\t$Rd, $Rn, $Rm$sh",
3101 [(set GPR:$Rd, (or (and GPR:$Rn, 0xFFFF0000),
3102 (and (sra GPR:$Rm, asr_amt:$sh),
3104 Requires<[IsARM, HasV6]>;
3106 // Alternate cases for PKHTB where identities eliminate some nodes. Note that
3107 // a shift amount of 0 is *not legal* here, it is PKHBT instead.
3108 def : ARMV6Pat<(or (and GPR:$src1, 0xFFFF0000), (srl GPR:$src2, imm16_31:$sh)),
3109 (PKHTB GPR:$src1, GPR:$src2, (asr_shift_imm imm16_31:$sh))>;
3110 def : ARMV6Pat<(or (and GPR:$src1, 0xFFFF0000),
3111 (and (srl GPR:$src2, imm1_15:$sh), 0xFFFF)),
3112 (PKHTB GPR:$src1, GPR:$src2, (asr_shift_imm imm1_15:$sh))>;
3114 //===----------------------------------------------------------------------===//
3115 // Comparison Instructions...
3118 defm CMP : AI1_cmp_irs<0b1010, "cmp",
3119 IIC_iCMPi, IIC_iCMPr, IIC_iCMPsr,
3120 BinOpFrag<(ARMcmp node:$LHS, node:$RHS)>>;
3122 // ARMcmpZ can re-use the above instruction definitions.
3123 def : ARMPat<(ARMcmpZ GPR:$src, so_imm:$imm),
3124 (CMPri GPR:$src, so_imm:$imm)>;
3125 def : ARMPat<(ARMcmpZ GPR:$src, GPR:$rhs),
3126 (CMPrr GPR:$src, GPR:$rhs)>;
3127 def : ARMPat<(ARMcmpZ GPR:$src, so_reg:$rhs),
3128 (CMPrs GPR:$src, so_reg:$rhs)>;
3130 // FIXME: We have to be careful when using the CMN instruction and comparison
3131 // with 0. One would expect these two pieces of code should give identical
3147 // However, the CMN gives the *opposite* result when r1 is 0. This is because
3148 // the carry flag is set in the CMP case but not in the CMN case. In short, the
3149 // CMP instruction doesn't perform a truncate of the (logical) NOT of 0 plus the
3150 // value of r0 and the carry bit (because the "carry bit" parameter to
3151 // AddWithCarry is defined as 1 in this case, the carry flag will always be set
3152 // when r0 >= 0). The CMN instruction doesn't perform a NOT of 0 so there is
3153 // never a "carry" when this AddWithCarry is performed (because the "carry bit"
3154 // parameter to AddWithCarry is defined as 0).
3156 // When x is 0 and unsigned:
3160 // ~x + 1 = 0x1 0000 0000
3161 // (-x = 0) != (0x1 0000 0000 = ~x + 1)
3163 // Therefore, we should disable CMN when comparing against zero, until we can
3164 // limit when the CMN instruction is used (when we know that the RHS is not 0 or
3165 // when it's a comparison which doesn't look at the 'carry' flag).
3167 // (See the ARM docs for the "AddWithCarry" pseudo-code.)
3169 // This is related to <rdar://problem/7569620>.
3171 //defm CMN : AI1_cmp_irs<0b1011, "cmn",
3172 // BinOpFrag<(ARMcmp node:$LHS,(ineg node:$RHS))>>;
3174 // Note that TST/TEQ don't set all the same flags that CMP does!
3175 defm TST : AI1_cmp_irs<0b1000, "tst",
3176 IIC_iTSTi, IIC_iTSTr, IIC_iTSTsr,
3177 BinOpFrag<(ARMcmpZ (and_su node:$LHS, node:$RHS), 0)>, 1>;
3178 defm TEQ : AI1_cmp_irs<0b1001, "teq",
3179 IIC_iTSTi, IIC_iTSTr, IIC_iTSTsr,
3180 BinOpFrag<(ARMcmpZ (xor_su node:$LHS, node:$RHS), 0)>, 1>;
3182 defm CMNz : AI1_cmp_irs<0b1011, "cmn",
3183 IIC_iCMPi, IIC_iCMPr, IIC_iCMPsr,
3184 BinOpFrag<(ARMcmpZ node:$LHS,(ineg node:$RHS))>>;
3186 //def : ARMPat<(ARMcmp GPR:$src, so_imm_neg:$imm),
3187 // (CMNri GPR:$src, so_imm_neg:$imm)>;
3189 def : ARMPat<(ARMcmpZ GPR:$src, so_imm_neg:$imm),
3190 (CMNzri GPR:$src, so_imm_neg:$imm)>;
3192 // Pseudo i64 compares for some floating point compares.
3193 let usesCustomInserter = 1, isBranch = 1, isTerminator = 1,
3195 def BCCi64 : PseudoInst<(outs),
3196 (ins i32imm:$cc, GPR:$lhs1, GPR:$lhs2, GPR:$rhs1, GPR:$rhs2, brtarget:$dst),
3198 [(ARMBcci64 imm:$cc, GPR:$lhs1, GPR:$lhs2, GPR:$rhs1, GPR:$rhs2, bb:$dst)]>;
3200 def BCCZi64 : PseudoInst<(outs),
3201 (ins i32imm:$cc, GPR:$lhs1, GPR:$lhs2, brtarget:$dst), IIC_Br,
3202 [(ARMBcci64 imm:$cc, GPR:$lhs1, GPR:$lhs2, 0, 0, bb:$dst)]>;
3203 } // usesCustomInserter
3206 // Conditional moves
3207 // FIXME: should be able to write a pattern for ARMcmov, but can't use
3208 // a two-value operand where a dag node expects two operands. :(
3209 let neverHasSideEffects = 1 in {
3210 def MOVCCr : ARMPseudoInst<(outs GPR:$Rd), (ins GPR:$false, GPR:$Rm, pred:$p),
3211 Size4Bytes, IIC_iCMOVr,
3212 [/*(set GPR:$Rd, (ARMcmov GPR:$false, GPR:$Rm, imm:$cc, CCR:$ccr))*/]>,
3213 RegConstraint<"$false = $Rd">;
3214 def MOVCCs : ARMPseudoInst<(outs GPR:$Rd),
3215 (ins GPR:$false, so_reg:$shift, pred:$p),
3216 Size4Bytes, IIC_iCMOVsr,
3217 [/*(set GPR:$Rd, (ARMcmov GPR:$false, so_reg:$shift, imm:$cc, CCR:$ccr))*/]>,
3218 RegConstraint<"$false = $Rd">;
3220 let isMoveImm = 1 in
3221 def MOVCCi16 : ARMPseudoInst<(outs GPR:$Rd),
3222 (ins GPR:$false, i32imm_hilo16:$imm, pred:$p),
3223 Size4Bytes, IIC_iMOVi,
3225 RegConstraint<"$false = $Rd">, Requires<[IsARM, HasV6T2]>;
3227 let isMoveImm = 1 in
3228 def MOVCCi : ARMPseudoInst<(outs GPR:$Rd),
3229 (ins GPR:$false, so_imm:$imm, pred:$p),
3230 Size4Bytes, IIC_iCMOVi,
3231 [/*(set GPR:$Rd, (ARMcmov GPR:$false, so_imm:$imm, imm:$cc, CCR:$ccr))*/]>,
3232 RegConstraint<"$false = $Rd">;
3234 // Two instruction predicate mov immediate.
3235 let isMoveImm = 1 in
3236 def MOVCCi32imm : ARMPseudoInst<(outs GPR:$Rd),
3237 (ins GPR:$false, i32imm:$src, pred:$p),
3238 Size8Bytes, IIC_iCMOVix2, []>, RegConstraint<"$false = $Rd">;
3240 let isMoveImm = 1 in
3241 def MVNCCi : ARMPseudoInst<(outs GPR:$Rd),
3242 (ins GPR:$false, so_imm:$imm, pred:$p),
3243 Size4Bytes, IIC_iCMOVi,
3244 [/*(set GPR:$Rd, (ARMcmov GPR:$false, so_imm_not:$imm, imm:$cc, CCR:$ccr))*/]>,
3245 RegConstraint<"$false = $Rd">;
3246 } // neverHasSideEffects
3248 //===----------------------------------------------------------------------===//
3249 // Atomic operations intrinsics
3252 def memb_opt : Operand<i32> {
3253 let PrintMethod = "printMemBOption";
3254 let ParserMatchClass = MemBarrierOptOperand;
3257 // memory barriers protect the atomic sequences
3258 let hasSideEffects = 1 in {
3259 def DMB : AInoP<(outs), (ins memb_opt:$opt), MiscFrm, NoItinerary,
3260 "dmb", "\t$opt", [(ARMMemBarrier (i32 imm:$opt))]>,
3261 Requires<[IsARM, HasDB]> {
3263 let Inst{31-4} = 0xf57ff05;
3264 let Inst{3-0} = opt;
3268 def DSB : AInoP<(outs), (ins memb_opt:$opt), MiscFrm, NoItinerary,
3270 [/* For disassembly only; pattern left blank */]>,
3271 Requires<[IsARM, HasDB]> {
3273 let Inst{31-4} = 0xf57ff04;
3274 let Inst{3-0} = opt;
3277 // ISB has only full system option -- for disassembly only
3278 def ISB : AInoP<(outs), (ins), MiscFrm, NoItinerary, "isb", "", []>,
3279 Requires<[IsARM, HasDB]> {
3280 let Inst{31-4} = 0xf57ff06;
3281 let Inst{3-0} = 0b1111;
3284 let usesCustomInserter = 1 in {
3285 let Uses = [CPSR] in {
3286 def ATOMIC_LOAD_ADD_I8 : PseudoInst<
3287 (outs GPR:$dst), (ins GPR:$ptr, GPR:$incr), NoItinerary,
3288 [(set GPR:$dst, (atomic_load_add_8 GPR:$ptr, GPR:$incr))]>;
3289 def ATOMIC_LOAD_SUB_I8 : PseudoInst<
3290 (outs GPR:$dst), (ins GPR:$ptr, GPR:$incr), NoItinerary,
3291 [(set GPR:$dst, (atomic_load_sub_8 GPR:$ptr, GPR:$incr))]>;
3292 def ATOMIC_LOAD_AND_I8 : PseudoInst<
3293 (outs GPR:$dst), (ins GPR:$ptr, GPR:$incr), NoItinerary,
3294 [(set GPR:$dst, (atomic_load_and_8 GPR:$ptr, GPR:$incr))]>;
3295 def ATOMIC_LOAD_OR_I8 : PseudoInst<
3296 (outs GPR:$dst), (ins GPR:$ptr, GPR:$incr), NoItinerary,
3297 [(set GPR:$dst, (atomic_load_or_8 GPR:$ptr, GPR:$incr))]>;
3298 def ATOMIC_LOAD_XOR_I8 : PseudoInst<
3299 (outs GPR:$dst), (ins GPR:$ptr, GPR:$incr), NoItinerary,
3300 [(set GPR:$dst, (atomic_load_xor_8 GPR:$ptr, GPR:$incr))]>;
3301 def ATOMIC_LOAD_NAND_I8 : PseudoInst<
3302 (outs GPR:$dst), (ins GPR:$ptr, GPR:$incr), NoItinerary,
3303 [(set GPR:$dst, (atomic_load_nand_8 GPR:$ptr, GPR:$incr))]>;
3304 def ATOMIC_LOAD_MIN_I8 : PseudoInst<
3305 (outs GPR:$dst), (ins GPR:$ptr, GPR:$val), NoItinerary,
3306 [(set GPR:$dst, (atomic_load_min_8 GPR:$ptr, GPR:$val))]>;
3307 def ATOMIC_LOAD_MAX_I8 : PseudoInst<
3308 (outs GPR:$dst), (ins GPR:$ptr, GPR:$val), NoItinerary,
3309 [(set GPR:$dst, (atomic_load_max_8 GPR:$ptr, GPR:$val))]>;
3310 def ATOMIC_LOAD_UMIN_I8 : PseudoInst<
3311 (outs GPR:$dst), (ins GPR:$ptr, GPR:$val), NoItinerary,
3312 [(set GPR:$dst, (atomic_load_min_8 GPR:$ptr, GPR:$val))]>;
3313 def ATOMIC_LOAD_UMAX_I8 : PseudoInst<
3314 (outs GPR:$dst), (ins GPR:$ptr, GPR:$val), NoItinerary,
3315 [(set GPR:$dst, (atomic_load_max_8 GPR:$ptr, GPR:$val))]>;
3316 def ATOMIC_LOAD_ADD_I16 : PseudoInst<
3317 (outs GPR:$dst), (ins GPR:$ptr, GPR:$incr), NoItinerary,
3318 [(set GPR:$dst, (atomic_load_add_16 GPR:$ptr, GPR:$incr))]>;
3319 def ATOMIC_LOAD_SUB_I16 : PseudoInst<
3320 (outs GPR:$dst), (ins GPR:$ptr, GPR:$incr), NoItinerary,
3321 [(set GPR:$dst, (atomic_load_sub_16 GPR:$ptr, GPR:$incr))]>;
3322 def ATOMIC_LOAD_AND_I16 : PseudoInst<
3323 (outs GPR:$dst), (ins GPR:$ptr, GPR:$incr), NoItinerary,
3324 [(set GPR:$dst, (atomic_load_and_16 GPR:$ptr, GPR:$incr))]>;
3325 def ATOMIC_LOAD_OR_I16 : PseudoInst<
3326 (outs GPR:$dst), (ins GPR:$ptr, GPR:$incr), NoItinerary,
3327 [(set GPR:$dst, (atomic_load_or_16 GPR:$ptr, GPR:$incr))]>;
3328 def ATOMIC_LOAD_XOR_I16 : PseudoInst<
3329 (outs GPR:$dst), (ins GPR:$ptr, GPR:$incr), NoItinerary,
3330 [(set GPR:$dst, (atomic_load_xor_16 GPR:$ptr, GPR:$incr))]>;
3331 def ATOMIC_LOAD_NAND_I16 : PseudoInst<
3332 (outs GPR:$dst), (ins GPR:$ptr, GPR:$incr), NoItinerary,
3333 [(set GPR:$dst, (atomic_load_nand_16 GPR:$ptr, GPR:$incr))]>;
3334 def ATOMIC_LOAD_MIN_I16 : PseudoInst<
3335 (outs GPR:$dst), (ins GPR:$ptr, GPR:$val), NoItinerary,
3336 [(set GPR:$dst, (atomic_load_min_16 GPR:$ptr, GPR:$val))]>;
3337 def ATOMIC_LOAD_MAX_I16 : PseudoInst<
3338 (outs GPR:$dst), (ins GPR:$ptr, GPR:$val), NoItinerary,
3339 [(set GPR:$dst, (atomic_load_max_16 GPR:$ptr, GPR:$val))]>;
3340 def ATOMIC_LOAD_UMIN_I16 : PseudoInst<
3341 (outs GPR:$dst), (ins GPR:$ptr, GPR:$val), NoItinerary,
3342 [(set GPR:$dst, (atomic_load_min_16 GPR:$ptr, GPR:$val))]>;
3343 def ATOMIC_LOAD_UMAX_I16 : PseudoInst<
3344 (outs GPR:$dst), (ins GPR:$ptr, GPR:$val), NoItinerary,
3345 [(set GPR:$dst, (atomic_load_max_16 GPR:$ptr, GPR:$val))]>;
3346 def ATOMIC_LOAD_ADD_I32 : PseudoInst<
3347 (outs GPR:$dst), (ins GPR:$ptr, GPR:$incr), NoItinerary,
3348 [(set GPR:$dst, (atomic_load_add_32 GPR:$ptr, GPR:$incr))]>;
3349 def ATOMIC_LOAD_SUB_I32 : PseudoInst<
3350 (outs GPR:$dst), (ins GPR:$ptr, GPR:$incr), NoItinerary,
3351 [(set GPR:$dst, (atomic_load_sub_32 GPR:$ptr, GPR:$incr))]>;
3352 def ATOMIC_LOAD_AND_I32 : PseudoInst<
3353 (outs GPR:$dst), (ins GPR:$ptr, GPR:$incr), NoItinerary,
3354 [(set GPR:$dst, (atomic_load_and_32 GPR:$ptr, GPR:$incr))]>;
3355 def ATOMIC_LOAD_OR_I32 : PseudoInst<
3356 (outs GPR:$dst), (ins GPR:$ptr, GPR:$incr), NoItinerary,
3357 [(set GPR:$dst, (atomic_load_or_32 GPR:$ptr, GPR:$incr))]>;
3358 def ATOMIC_LOAD_XOR_I32 : PseudoInst<
3359 (outs GPR:$dst), (ins GPR:$ptr, GPR:$incr), NoItinerary,
3360 [(set GPR:$dst, (atomic_load_xor_32 GPR:$ptr, GPR:$incr))]>;
3361 def ATOMIC_LOAD_NAND_I32 : PseudoInst<
3362 (outs GPR:$dst), (ins GPR:$ptr, GPR:$incr), NoItinerary,
3363 [(set GPR:$dst, (atomic_load_nand_32 GPR:$ptr, GPR:$incr))]>;
3364 def ATOMIC_LOAD_MIN_I32 : PseudoInst<
3365 (outs GPR:$dst), (ins GPR:$ptr, GPR:$val), NoItinerary,
3366 [(set GPR:$dst, (atomic_load_min_32 GPR:$ptr, GPR:$val))]>;
3367 def ATOMIC_LOAD_MAX_I32 : PseudoInst<
3368 (outs GPR:$dst), (ins GPR:$ptr, GPR:$val), NoItinerary,
3369 [(set GPR:$dst, (atomic_load_max_32 GPR:$ptr, GPR:$val))]>;
3370 def ATOMIC_LOAD_UMIN_I32 : PseudoInst<
3371 (outs GPR:$dst), (ins GPR:$ptr, GPR:$val), NoItinerary,
3372 [(set GPR:$dst, (atomic_load_min_32 GPR:$ptr, GPR:$val))]>;
3373 def ATOMIC_LOAD_UMAX_I32 : PseudoInst<
3374 (outs GPR:$dst), (ins GPR:$ptr, GPR:$val), NoItinerary,
3375 [(set GPR:$dst, (atomic_load_max_32 GPR:$ptr, GPR:$val))]>;
3377 def ATOMIC_SWAP_I8 : PseudoInst<
3378 (outs GPR:$dst), (ins GPR:$ptr, GPR:$new), NoItinerary,
3379 [(set GPR:$dst, (atomic_swap_8 GPR:$ptr, GPR:$new))]>;
3380 def ATOMIC_SWAP_I16 : PseudoInst<
3381 (outs GPR:$dst), (ins GPR:$ptr, GPR:$new), NoItinerary,
3382 [(set GPR:$dst, (atomic_swap_16 GPR:$ptr, GPR:$new))]>;
3383 def ATOMIC_SWAP_I32 : PseudoInst<
3384 (outs GPR:$dst), (ins GPR:$ptr, GPR:$new), NoItinerary,
3385 [(set GPR:$dst, (atomic_swap_32 GPR:$ptr, GPR:$new))]>;
3387 def ATOMIC_CMP_SWAP_I8 : PseudoInst<
3388 (outs GPR:$dst), (ins GPR:$ptr, GPR:$old, GPR:$new), NoItinerary,
3389 [(set GPR:$dst, (atomic_cmp_swap_8 GPR:$ptr, GPR:$old, GPR:$new))]>;
3390 def ATOMIC_CMP_SWAP_I16 : PseudoInst<
3391 (outs GPR:$dst), (ins GPR:$ptr, GPR:$old, GPR:$new), NoItinerary,
3392 [(set GPR:$dst, (atomic_cmp_swap_16 GPR:$ptr, GPR:$old, GPR:$new))]>;
3393 def ATOMIC_CMP_SWAP_I32 : PseudoInst<
3394 (outs GPR:$dst), (ins GPR:$ptr, GPR:$old, GPR:$new), NoItinerary,
3395 [(set GPR:$dst, (atomic_cmp_swap_32 GPR:$ptr, GPR:$old, GPR:$new))]>;
3399 let mayLoad = 1 in {
3400 def LDREXB : AIldrex<0b10, (outs GPR:$Rt), (ins addrmode7:$addr), NoItinerary,
3401 "ldrexb", "\t$Rt, $addr", []>;
3402 def LDREXH : AIldrex<0b11, (outs GPR:$Rt), (ins addrmode7:$addr), NoItinerary,
3403 "ldrexh", "\t$Rt, $addr", []>;
3404 def LDREX : AIldrex<0b00, (outs GPR:$Rt), (ins addrmode7:$addr), NoItinerary,
3405 "ldrex", "\t$Rt, $addr", []>;
3406 let hasExtraDefRegAllocReq = 1 in
3407 def LDREXD : AIldrex<0b01, (outs GPR:$Rt, GPR:$Rt2), (ins addrmode7:$addr),
3408 NoItinerary, "ldrexd", "\t$Rt, $Rt2, $addr", []>;
3411 let mayStore = 1, Constraints = "@earlyclobber $Rd" in {
3412 def STREXB : AIstrex<0b10, (outs GPR:$Rd), (ins GPR:$Rt, addrmode7:$addr),
3413 NoItinerary, "strexb", "\t$Rd, $Rt, $addr", []>;
3414 def STREXH : AIstrex<0b11, (outs GPR:$Rd), (ins GPR:$Rt, addrmode7:$addr),
3415 NoItinerary, "strexh", "\t$Rd, $Rt, $addr", []>;
3416 def STREX : AIstrex<0b00, (outs GPR:$Rd), (ins GPR:$Rt, addrmode7:$addr),
3417 NoItinerary, "strex", "\t$Rd, $Rt, $addr", []>;
3420 let hasExtraSrcRegAllocReq = 1, Constraints = "@earlyclobber $Rd" in
3421 def STREXD : AIstrex<0b01, (outs GPR:$Rd),
3422 (ins GPR:$Rt, GPR:$Rt2, addrmode7:$addr),
3423 NoItinerary, "strexd", "\t$Rd, $Rt, $Rt2, $addr", []>;
3425 // Clear-Exclusive is for disassembly only.
3426 def CLREX : AXI<(outs), (ins), MiscFrm, NoItinerary, "clrex",
3427 [/* For disassembly only; pattern left blank */]>,
3428 Requires<[IsARM, HasV7]> {
3429 let Inst{31-0} = 0b11110101011111111111000000011111;
3432 // SWP/SWPB are deprecated in V6/V7 and for disassembly only.
3433 let mayLoad = 1 in {
3434 def SWP : AIswp<0, (outs GPR:$Rt), (ins GPR:$Rt2, GPR:$Rn), "swp",
3435 [/* For disassembly only; pattern left blank */]>;
3436 def SWPB : AIswp<1, (outs GPR:$Rt), (ins GPR:$Rt2, GPR:$Rn), "swpb",
3437 [/* For disassembly only; pattern left blank */]>;
3440 //===----------------------------------------------------------------------===//
3441 // Coprocessor Instructions.
3444 def CDP : ABI<0b1110, (outs), (ins p_imm:$cop, i32imm:$opc1,
3445 c_imm:$CRd, c_imm:$CRn, c_imm:$CRm, i32imm:$opc2),
3446 NoItinerary, "cdp", "\t$cop, $opc1, $CRd, $CRn, $CRm, $opc2",
3447 [(int_arm_cdp imm:$cop, imm:$opc1, imm:$CRd, imm:$CRn,
3448 imm:$CRm, imm:$opc2)]> {
3456 let Inst{3-0} = CRm;
3458 let Inst{7-5} = opc2;
3459 let Inst{11-8} = cop;
3460 let Inst{15-12} = CRd;
3461 let Inst{19-16} = CRn;
3462 let Inst{23-20} = opc1;
3465 def CDP2 : ABXI<0b1110, (outs), (ins p_imm:$cop, i32imm:$opc1,
3466 c_imm:$CRd, c_imm:$CRn, c_imm:$CRm, i32imm:$opc2),
3467 NoItinerary, "cdp2\t$cop, $opc1, $CRd, $CRn, $CRm, $opc2",
3468 [(int_arm_cdp2 imm:$cop, imm:$opc1, imm:$CRd, imm:$CRn,
3469 imm:$CRm, imm:$opc2)]> {
3470 let Inst{31-28} = 0b1111;
3478 let Inst{3-0} = CRm;
3480 let Inst{7-5} = opc2;
3481 let Inst{11-8} = cop;
3482 let Inst{15-12} = CRd;
3483 let Inst{19-16} = CRn;
3484 let Inst{23-20} = opc1;
3487 class ACI<dag oops, dag iops, string opc, string asm,
3488 IndexMode im = IndexModeNone>
3489 : InoP<oops, iops, AddrModeNone, Size4Bytes, im, BrFrm, NoItinerary,
3490 opc, asm, "", [/* For disassembly only; pattern left blank */]> {
3491 let Inst{27-25} = 0b110;
3494 multiclass LdStCop<bits<4> op31_28, bit load, dag ops, string opc, string cond>{
3496 def _OFFSET : ACI<(outs),
3497 !con((ins nohash_imm:$cop, nohash_imm:$CRd, addrmode2:$addr), ops),
3498 !strconcat(opc, cond), "\tp$cop, cr$CRd, $addr"> {
3499 let Inst{31-28} = op31_28;
3500 let Inst{24} = 1; // P = 1
3501 let Inst{21} = 0; // W = 0
3502 let Inst{22} = 0; // D = 0
3503 let Inst{20} = load;
3506 def _PRE : ACI<(outs),
3507 !con((ins nohash_imm:$cop, nohash_imm:$CRd, addrmode2:$addr), ops),
3508 !strconcat(opc, cond), "\tp$cop, cr$CRd, $addr!", IndexModePre> {
3509 let Inst{31-28} = op31_28;
3510 let Inst{24} = 1; // P = 1
3511 let Inst{21} = 1; // W = 1
3512 let Inst{22} = 0; // D = 0
3513 let Inst{20} = load;
3516 def _POST : ACI<(outs),
3517 !con((ins nohash_imm:$cop, nohash_imm:$CRd, addrmode2:$addr), ops),
3518 !strconcat(opc, cond), "\tp$cop, cr$CRd, $addr", IndexModePost> {
3519 let Inst{31-28} = op31_28;
3520 let Inst{24} = 0; // P = 0
3521 let Inst{21} = 1; // W = 1
3522 let Inst{22} = 0; // D = 0
3523 let Inst{20} = load;
3526 def _OPTION : ACI<(outs),
3527 !con((ins nohash_imm:$cop,nohash_imm:$CRd,GPR:$base, nohash_imm:$option),
3529 !strconcat(opc, cond), "\tp$cop, cr$CRd, [$base], \\{$option\\}"> {
3530 let Inst{31-28} = op31_28;
3531 let Inst{24} = 0; // P = 0
3532 let Inst{23} = 1; // U = 1
3533 let Inst{21} = 0; // W = 0
3534 let Inst{22} = 0; // D = 0
3535 let Inst{20} = load;
3538 def L_OFFSET : ACI<(outs),
3539 !con((ins nohash_imm:$cop, nohash_imm:$CRd, addrmode2:$addr), ops),
3540 !strconcat(!strconcat(opc, "l"), cond), "\tp$cop, cr$CRd, $addr"> {
3541 let Inst{31-28} = op31_28;
3542 let Inst{24} = 1; // P = 1
3543 let Inst{21} = 0; // W = 0
3544 let Inst{22} = 1; // D = 1
3545 let Inst{20} = load;
3548 def L_PRE : ACI<(outs),
3549 !con((ins nohash_imm:$cop, nohash_imm:$CRd, addrmode2:$addr), ops),
3550 !strconcat(!strconcat(opc, "l"), cond), "\tp$cop, cr$CRd, $addr!",
3552 let Inst{31-28} = op31_28;
3553 let Inst{24} = 1; // P = 1
3554 let Inst{21} = 1; // W = 1
3555 let Inst{22} = 1; // D = 1
3556 let Inst{20} = load;
3559 def L_POST : ACI<(outs),
3560 !con((ins nohash_imm:$cop, nohash_imm:$CRd, addrmode2:$addr), ops),
3561 !strconcat(!strconcat(opc, "l"), cond), "\tp$cop, cr$CRd, $addr",
3563 let Inst{31-28} = op31_28;
3564 let Inst{24} = 0; // P = 0
3565 let Inst{21} = 1; // W = 1
3566 let Inst{22} = 1; // D = 1
3567 let Inst{20} = load;
3570 def L_OPTION : ACI<(outs),
3571 !con((ins nohash_imm:$cop, nohash_imm:$CRd,GPR:$base,nohash_imm:$option),
3573 !strconcat(!strconcat(opc, "l"), cond),
3574 "\tp$cop, cr$CRd, [$base], \\{$option\\}"> {
3575 let Inst{31-28} = op31_28;
3576 let Inst{24} = 0; // P = 0
3577 let Inst{23} = 1; // U = 1
3578 let Inst{21} = 0; // W = 0
3579 let Inst{22} = 1; // D = 1
3580 let Inst{20} = load;
3584 defm LDC : LdStCop<{?,?,?,?}, 1, (ins pred:$p), "ldc", "${p}">;
3585 defm LDC2 : LdStCop<0b1111, 1, (ins), "ldc2", "">;
3586 defm STC : LdStCop<{?,?,?,?}, 0, (ins pred:$p), "stc", "${p}">;
3587 defm STC2 : LdStCop<0b1111, 0, (ins), "stc2", "">;
3589 //===----------------------------------------------------------------------===//
3590 // Move between coprocessor and ARM core register -- for disassembly only
3593 class MovRCopro<string opc, bit direction, dag oops, dag iops,
3595 : ABI<0b1110, oops, iops, NoItinerary, opc,
3596 "\t$cop, $opc1, $Rt, $CRn, $CRm, $opc2", pattern> {
3597 let Inst{20} = direction;
3607 let Inst{15-12} = Rt;
3608 let Inst{11-8} = cop;
3609 let Inst{23-21} = opc1;
3610 let Inst{7-5} = opc2;
3611 let Inst{3-0} = CRm;
3612 let Inst{19-16} = CRn;
3615 def MCR : MovRCopro<"mcr", 0 /* from ARM core register to coprocessor */,
3617 (ins p_imm:$cop, i32imm:$opc1, GPR:$Rt, c_imm:$CRn,
3618 c_imm:$CRm, i32imm:$opc2),
3619 [(int_arm_mcr imm:$cop, imm:$opc1, GPR:$Rt, imm:$CRn,
3620 imm:$CRm, imm:$opc2)]>;
3621 def MRC : MovRCopro<"mrc", 1 /* from coprocessor to ARM core register */,
3623 (ins p_imm:$cop, i32imm:$opc1, c_imm:$CRn, c_imm:$CRm,
3626 def : ARMPat<(int_arm_mrc imm:$cop, imm:$opc1, imm:$CRn, imm:$CRm, imm:$opc2),
3627 (MRC imm:$cop, imm:$opc1, imm:$CRn, imm:$CRm, imm:$opc2)>;
3629 class MovRCopro2<string opc, bit direction, dag oops, dag iops,
3631 : ABXI<0b1110, oops, iops, NoItinerary,
3632 !strconcat(opc, "\t$cop, $opc1, $Rt, $CRn, $CRm, $opc2"), pattern> {
3633 let Inst{31-28} = 0b1111;
3634 let Inst{20} = direction;
3644 let Inst{15-12} = Rt;
3645 let Inst{11-8} = cop;
3646 let Inst{23-21} = opc1;
3647 let Inst{7-5} = opc2;
3648 let Inst{3-0} = CRm;
3649 let Inst{19-16} = CRn;
3652 def MCR2 : MovRCopro2<"mcr2", 0 /* from ARM core register to coprocessor */,
3654 (ins p_imm:$cop, i32imm:$opc1, GPR:$Rt, c_imm:$CRn,
3655 c_imm:$CRm, i32imm:$opc2),
3656 [(int_arm_mcr2 imm:$cop, imm:$opc1, GPR:$Rt, imm:$CRn,
3657 imm:$CRm, imm:$opc2)]>;
3658 def MRC2 : MovRCopro2<"mrc2", 1 /* from coprocessor to ARM core register */,
3660 (ins p_imm:$cop, i32imm:$opc1, c_imm:$CRn, c_imm:$CRm,
3663 def : ARMV5TPat<(int_arm_mrc2 imm:$cop, imm:$opc1, imm:$CRn,
3664 imm:$CRm, imm:$opc2),
3665 (MRC2 imm:$cop, imm:$opc1, imm:$CRn, imm:$CRm, imm:$opc2)>;
3667 class MovRRCopro<string opc, bit direction,
3668 list<dag> pattern = [/* For disassembly only */]>
3669 : ABI<0b1100, (outs), (ins p_imm:$cop, i32imm:$opc1,
3670 GPR:$Rt, GPR:$Rt2, c_imm:$CRm),
3671 NoItinerary, opc, "\t$cop, $opc1, $Rt, $Rt2, $CRm", pattern> {
3672 let Inst{23-21} = 0b010;
3673 let Inst{20} = direction;
3681 let Inst{15-12} = Rt;
3682 let Inst{19-16} = Rt2;
3683 let Inst{11-8} = cop;
3684 let Inst{7-4} = opc1;
3685 let Inst{3-0} = CRm;
3688 def MCRR : MovRRCopro<"mcrr", 0 /* from ARM core register to coprocessor */,
3689 [(int_arm_mcrr imm:$cop, imm:$opc1, GPR:$Rt, GPR:$Rt2,
3691 def MRRC : MovRRCopro<"mrrc", 1 /* from coprocessor to ARM core register */>;
3693 class MovRRCopro2<string opc, bit direction,
3694 list<dag> pattern = [/* For disassembly only */]>
3695 : ABXI<0b1100, (outs), (ins p_imm:$cop, i32imm:$opc1,
3696 GPR:$Rt, GPR:$Rt2, c_imm:$CRm), NoItinerary,
3697 !strconcat(opc, "\t$cop, $opc1, $Rt, $Rt2, $CRm"), pattern> {
3698 let Inst{31-28} = 0b1111;
3699 let Inst{23-21} = 0b010;
3700 let Inst{20} = direction;
3708 let Inst{15-12} = Rt;
3709 let Inst{19-16} = Rt2;
3710 let Inst{11-8} = cop;
3711 let Inst{7-4} = opc1;
3712 let Inst{3-0} = CRm;
3715 def MCRR2 : MovRRCopro2<"mcrr2", 0 /* from ARM core register to coprocessor */,
3716 [(int_arm_mcrr2 imm:$cop, imm:$opc1, GPR:$Rt, GPR:$Rt2,
3718 def MRRC2 : MovRRCopro2<"mrrc2", 1 /* from coprocessor to ARM core register */>;
3720 //===----------------------------------------------------------------------===//
3721 // Move between special register and ARM core register -- for disassembly only
3724 // Move to ARM core register from Special Register
3725 def MRS : ABI<0b0001, (outs GPR:$Rd), (ins), NoItinerary, "mrs", "\t$Rd, cpsr",
3726 [/* For disassembly only; pattern left blank */]> {
3728 let Inst{23-16} = 0b00001111;
3729 let Inst{15-12} = Rd;
3730 let Inst{7-4} = 0b0000;
3733 def MRSsys : ABI<0b0001, (outs GPR:$Rd), (ins), NoItinerary,"mrs","\t$Rd, spsr",
3734 [/* For disassembly only; pattern left blank */]> {
3736 let Inst{23-16} = 0b01001111;
3737 let Inst{15-12} = Rd;
3738 let Inst{7-4} = 0b0000;
3741 // Move from ARM core register to Special Register
3743 // No need to have both system and application versions, the encodings are the
3744 // same and the assembly parser has no way to distinguish between them. The mask
3745 // operand contains the special register (R Bit) in bit 4 and bits 3-0 contains
3746 // the mask with the fields to be accessed in the special register.
3747 def MSR : ABI<0b0001, (outs), (ins msr_mask:$mask, GPR:$Rn), NoItinerary,
3748 "msr", "\t$mask, $Rn",
3749 [/* For disassembly only; pattern left blank */]> {
3754 let Inst{22} = mask{4}; // R bit
3755 let Inst{21-20} = 0b10;
3756 let Inst{19-16} = mask{3-0};
3757 let Inst{15-12} = 0b1111;
3758 let Inst{11-4} = 0b00000000;
3762 def MSRi : ABI<0b0011, (outs), (ins msr_mask:$mask, so_imm:$a), NoItinerary,
3763 "msr", "\t$mask, $a",
3764 [/* For disassembly only; pattern left blank */]> {
3769 let Inst{22} = mask{4}; // R bit
3770 let Inst{21-20} = 0b10;
3771 let Inst{19-16} = mask{3-0};
3772 let Inst{15-12} = 0b1111;
3776 //===----------------------------------------------------------------------===//
3780 // __aeabi_read_tp preserves the registers r1-r3.
3781 // This is a pseudo inst so that we can get the encoding right,
3782 // complete with fixup for the aeabi_read_tp function.
3784 Defs = [R0, R12, LR, CPSR], Uses = [SP] in {
3785 def TPsoft : PseudoInst<(outs), (ins), IIC_Br,
3786 [(set R0, ARMthread_pointer)]>;
3789 //===----------------------------------------------------------------------===//
3790 // SJLJ Exception handling intrinsics
3791 // eh_sjlj_setjmp() is an instruction sequence to store the return
3792 // address and save #0 in R0 for the non-longjmp case.
3793 // Since by its nature we may be coming from some other function to get
3794 // here, and we're using the stack frame for the containing function to
3795 // save/restore registers, we can't keep anything live in regs across
3796 // the eh_sjlj_setjmp(), else it will almost certainly have been tromped upon
3797 // when we get here from a longjmp(). We force everything out of registers
3798 // except for our own input by listing the relevant registers in Defs. By
3799 // doing so, we also cause the prologue/epilogue code to actively preserve
3800 // all of the callee-saved resgisters, which is exactly what we want.
3801 // A constant value is passed in $val, and we use the location as a scratch.
3803 // These are pseudo-instructions and are lowered to individual MC-insts, so
3804 // no encoding information is necessary.
3806 [ R0, R1, R2, R3, R4, R5, R6, R7, R8, R9, R10, R11, R12, LR, CPSR,
3807 QQQQ0, QQQQ1, QQQQ2, QQQQ3 ], hasSideEffects = 1, isBarrier = 1 in {
3808 def Int_eh_sjlj_setjmp : PseudoInst<(outs), (ins GPR:$src, GPR:$val),
3810 [(set R0, (ARMeh_sjlj_setjmp GPR:$src, GPR:$val))]>,
3811 Requires<[IsARM, HasVFP2]>;
3815 [ R0, R1, R2, R3, R4, R5, R6, R7, R8, R9, R10, R11, R12, LR, CPSR ],
3816 hasSideEffects = 1, isBarrier = 1 in {
3817 def Int_eh_sjlj_setjmp_nofp : PseudoInst<(outs), (ins GPR:$src, GPR:$val),
3819 [(set R0, (ARMeh_sjlj_setjmp GPR:$src, GPR:$val))]>,
3820 Requires<[IsARM, NoVFP]>;
3823 // FIXME: Non-Darwin version(s)
3824 let isBarrier = 1, hasSideEffects = 1, isTerminator = 1,
3825 Defs = [ R7, LR, SP ] in {
3826 def Int_eh_sjlj_longjmp : PseudoInst<(outs), (ins GPR:$src, GPR:$scratch),
3828 [(ARMeh_sjlj_longjmp GPR:$src, GPR:$scratch)]>,
3829 Requires<[IsARM, IsDarwin]>;
3832 // eh.sjlj.dispatchsetup pseudo-instruction.
3833 // This pseudo is used for ARM, Thumb1 and Thumb2. Any differences are
3834 // handled when the pseudo is expanded (which happens before any passes
3835 // that need the instruction size).
3836 let isBarrier = 1, hasSideEffects = 1 in
3837 def Int_eh_sjlj_dispatchsetup :
3838 PseudoInst<(outs), (ins GPR:$src), NoItinerary,
3839 [(ARMeh_sjlj_dispatchsetup GPR:$src)]>,
3840 Requires<[IsDarwin]>;
3842 //===----------------------------------------------------------------------===//
3843 // Non-Instruction Patterns
3846 // ARMv4 indirect branch using (MOVr PC, dst)
3847 let isBranch = 1, isTerminator = 1, isBarrier = 1, isIndirectBranch = 1 in
3848 def MOVPCRX : ARMPseudoExpand<(outs), (ins GPR:$dst),
3849 Size4Bytes, IIC_Br, [(brind GPR:$dst)],
3850 (MOVr PC, GPR:$dst, (ops 14, zero_reg), zero_reg)>,
3851 Requires<[IsARM, NoV4T]>;
3853 // Large immediate handling.
3855 // 32-bit immediate using two piece so_imms or movw + movt.
3856 // This is a single pseudo instruction, the benefit is that it can be remat'd
3857 // as a single unit instead of having to handle reg inputs.
3858 // FIXME: Remove this when we can do generalized remat.
3859 let isReMaterializable = 1, isMoveImm = 1 in
3860 def MOVi32imm : PseudoInst<(outs GPR:$dst), (ins i32imm:$src), IIC_iMOVix2,
3861 [(set GPR:$dst, (arm_i32imm:$src))]>,
3864 // Pseudo instruction that combines movw + movt + add pc (if PIC).
3865 // It also makes it possible to rematerialize the instructions.
3866 // FIXME: Remove this when we can do generalized remat and when machine licm
3867 // can properly the instructions.
3868 let isReMaterializable = 1 in {
3869 def MOV_ga_pcrel : PseudoInst<(outs GPR:$dst), (ins i32imm:$addr),
3871 [(set GPR:$dst, (ARMWrapperPIC tglobaladdr:$addr))]>,
3872 Requires<[IsARM, UseMovt]>;
3874 def MOV_ga_dyn : PseudoInst<(outs GPR:$dst), (ins i32imm:$addr),
3876 [(set GPR:$dst, (ARMWrapperDYN tglobaladdr:$addr))]>,
3877 Requires<[IsARM, UseMovt]>;
3879 let AddedComplexity = 10 in
3880 def MOV_ga_pcrel_ldr : PseudoInst<(outs GPR:$dst), (ins i32imm:$addr),
3882 [(set GPR:$dst, (load (ARMWrapperPIC tglobaladdr:$addr)))]>,
3883 Requires<[IsARM, UseMovt]>;
3884 } // isReMaterializable
3886 // ConstantPool, GlobalAddress, and JumpTable
3887 def : ARMPat<(ARMWrapper tglobaladdr :$dst), (LEApcrel tglobaladdr :$dst)>,
3888 Requires<[IsARM, DontUseMovt]>;
3889 def : ARMPat<(ARMWrapper tconstpool :$dst), (LEApcrel tconstpool :$dst)>;
3890 def : ARMPat<(ARMWrapper tglobaladdr :$dst), (MOVi32imm tglobaladdr :$dst)>,
3891 Requires<[IsARM, UseMovt]>;
3892 def : ARMPat<(ARMWrapperJT tjumptable:$dst, imm:$id),
3893 (LEApcrelJT tjumptable:$dst, imm:$id)>;
3895 // TODO: add,sub,and, 3-instr forms?
3898 def : ARMPat<(ARMtcret tcGPR:$dst),
3899 (TCRETURNri tcGPR:$dst)>, Requires<[IsDarwin]>;
3901 def : ARMPat<(ARMtcret (i32 tglobaladdr:$dst)),
3902 (TCRETURNdi texternalsym:$dst)>, Requires<[IsDarwin]>;
3904 def : ARMPat<(ARMtcret (i32 texternalsym:$dst)),
3905 (TCRETURNdi texternalsym:$dst)>, Requires<[IsDarwin]>;
3907 def : ARMPat<(ARMtcret tcGPR:$dst),
3908 (TCRETURNriND tcGPR:$dst)>, Requires<[IsNotDarwin]>;
3910 def : ARMPat<(ARMtcret (i32 tglobaladdr:$dst)),
3911 (TCRETURNdiND texternalsym:$dst)>, Requires<[IsNotDarwin]>;
3913 def : ARMPat<(ARMtcret (i32 texternalsym:$dst)),
3914 (TCRETURNdiND texternalsym:$dst)>, Requires<[IsNotDarwin]>;
3917 def : ARMPat<(ARMcall texternalsym:$func), (BL texternalsym:$func)>,
3918 Requires<[IsARM, IsNotDarwin]>;
3919 def : ARMPat<(ARMcall texternalsym:$func), (BLr9 texternalsym:$func)>,
3920 Requires<[IsARM, IsDarwin]>;
3922 // zextload i1 -> zextload i8
3923 def : ARMPat<(zextloadi1 addrmode_imm12:$addr), (LDRBi12 addrmode_imm12:$addr)>;
3924 def : ARMPat<(zextloadi1 ldst_so_reg:$addr), (LDRBrs ldst_so_reg:$addr)>;
3926 // extload -> zextload
3927 def : ARMPat<(extloadi1 addrmode_imm12:$addr), (LDRBi12 addrmode_imm12:$addr)>;
3928 def : ARMPat<(extloadi1 ldst_so_reg:$addr), (LDRBrs ldst_so_reg:$addr)>;
3929 def : ARMPat<(extloadi8 addrmode_imm12:$addr), (LDRBi12 addrmode_imm12:$addr)>;
3930 def : ARMPat<(extloadi8 ldst_so_reg:$addr), (LDRBrs ldst_so_reg:$addr)>;
3932 def : ARMPat<(extloadi16 addrmode3:$addr), (LDRH addrmode3:$addr)>;
3934 def : ARMPat<(extloadi8 addrmodepc:$addr), (PICLDRB addrmodepc:$addr)>;
3935 def : ARMPat<(extloadi16 addrmodepc:$addr), (PICLDRH addrmodepc:$addr)>;
3938 def : ARMV5TEPat<(mul (sra (shl GPR:$a, (i32 16)), (i32 16)),
3939 (sra (shl GPR:$b, (i32 16)), (i32 16))),
3940 (SMULBB GPR:$a, GPR:$b)>;
3941 def : ARMV5TEPat<(mul sext_16_node:$a, sext_16_node:$b),
3942 (SMULBB GPR:$a, GPR:$b)>;
3943 def : ARMV5TEPat<(mul (sra (shl GPR:$a, (i32 16)), (i32 16)),
3944 (sra GPR:$b, (i32 16))),
3945 (SMULBT GPR:$a, GPR:$b)>;
3946 def : ARMV5TEPat<(mul sext_16_node:$a, (sra GPR:$b, (i32 16))),
3947 (SMULBT GPR:$a, GPR:$b)>;
3948 def : ARMV5TEPat<(mul (sra GPR:$a, (i32 16)),
3949 (sra (shl GPR:$b, (i32 16)), (i32 16))),
3950 (SMULTB GPR:$a, GPR:$b)>;
3951 def : ARMV5TEPat<(mul (sra GPR:$a, (i32 16)), sext_16_node:$b),
3952 (SMULTB GPR:$a, GPR:$b)>;
3953 def : ARMV5TEPat<(sra (mul GPR:$a, (sra (shl GPR:$b, (i32 16)), (i32 16))),
3955 (SMULWB GPR:$a, GPR:$b)>;
3956 def : ARMV5TEPat<(sra (mul GPR:$a, sext_16_node:$b), (i32 16)),
3957 (SMULWB GPR:$a, GPR:$b)>;
3959 def : ARMV5TEPat<(add GPR:$acc,
3960 (mul (sra (shl GPR:$a, (i32 16)), (i32 16)),
3961 (sra (shl GPR:$b, (i32 16)), (i32 16)))),
3962 (SMLABB GPR:$a, GPR:$b, GPR:$acc)>;
3963 def : ARMV5TEPat<(add GPR:$acc,
3964 (mul sext_16_node:$a, sext_16_node:$b)),
3965 (SMLABB GPR:$a, GPR:$b, GPR:$acc)>;
3966 def : ARMV5TEPat<(add GPR:$acc,
3967 (mul (sra (shl GPR:$a, (i32 16)), (i32 16)),
3968 (sra GPR:$b, (i32 16)))),
3969 (SMLABT GPR:$a, GPR:$b, GPR:$acc)>;
3970 def : ARMV5TEPat<(add GPR:$acc,
3971 (mul sext_16_node:$a, (sra GPR:$b, (i32 16)))),
3972 (SMLABT GPR:$a, GPR:$b, GPR:$acc)>;
3973 def : ARMV5TEPat<(add GPR:$acc,
3974 (mul (sra GPR:$a, (i32 16)),
3975 (sra (shl GPR:$b, (i32 16)), (i32 16)))),
3976 (SMLATB GPR:$a, GPR:$b, GPR:$acc)>;
3977 def : ARMV5TEPat<(add GPR:$acc,
3978 (mul (sra GPR:$a, (i32 16)), sext_16_node:$b)),
3979 (SMLATB GPR:$a, GPR:$b, GPR:$acc)>;
3980 def : ARMV5TEPat<(add GPR:$acc,
3981 (sra (mul GPR:$a, (sra (shl GPR:$b, (i32 16)), (i32 16))),
3983 (SMLAWB GPR:$a, GPR:$b, GPR:$acc)>;
3984 def : ARMV5TEPat<(add GPR:$acc,
3985 (sra (mul GPR:$a, sext_16_node:$b), (i32 16))),
3986 (SMLAWB GPR:$a, GPR:$b, GPR:$acc)>;
3989 // Pre-v7 uses MCR for synchronization barriers.
3990 def : ARMPat<(ARMMemBarrierMCR GPR:$zero), (MCR 15, 0, GPR:$zero, 7, 10, 5)>,
3991 Requires<[IsARM, HasV6]>;
3994 //===----------------------------------------------------------------------===//
3998 include "ARMInstrThumb.td"
4000 //===----------------------------------------------------------------------===//
4004 include "ARMInstrThumb2.td"
4006 //===----------------------------------------------------------------------===//
4007 // Floating Point Support
4010 include "ARMInstrVFP.td"
4012 //===----------------------------------------------------------------------===//
4013 // Advanced SIMD (NEON) Support
4016 include "ARMInstrNEON.td"