1 //===- ARMInstrInfo.td - Target Description for ARM Target ----------------===//
3 // The LLVM Compiler Infrastructure
5 // This file was developed by the "Instituto Nokia de Tecnologia" and
6 // is distributed under the University of Illinois Open Source
7 // License. See LICENSE.TXT for details.
9 //===----------------------------------------------------------------------===//
11 // This file describes the ARM instructions in TableGen format.
13 //===----------------------------------------------------------------------===//
17 //===----------------------------------------------------------------------===//
19 //===----------------------------------------------------------------------===//
21 class InstARM<dag ops, string asmstr, list<dag> pattern> : Instruction {
22 let Namespace = "ARM";
24 dag OperandList = ops;
25 let AsmString = asmstr;
26 let Pattern = pattern;
29 def SDT_ARMCallSeq : SDTypeProfile<0, 1, [ SDTCisVT<0, i32> ]>;
30 def callseq_start : SDNode<"ISD::CALLSEQ_START", SDT_ARMCallSeq, [SDNPHasChain]>;
31 def callseq_end : SDNode<"ISD::CALLSEQ_END", SDT_ARMCallSeq, [SDNPHasChain]>;
33 def ADJCALLSTACKUP : InstARM<(ops i32imm:$amt),
34 "!ADJCALLSTACKUP $amt",
35 [(callseq_end imm:$amt)]>;
37 def ADJCALLSTACKDOWN : InstARM<(ops i32imm:$amt),
38 "!ADJCALLSTACKDOWN $amt",
39 [(callseq_start imm:$amt)]>;
41 def bxr: InstARM<(ops IntRegs:$dst), "bx $dst", [(brind IntRegs:$dst)]>;
43 def ldr : InstARM<(ops IntRegs:$dst, IntRegs:$addr),
45 [(set IntRegs:$dst, (load IntRegs:$addr))]>;
47 def str : InstARM<(ops IntRegs:$src, IntRegs:$addr),
49 [(store IntRegs:$src, IntRegs:$addr)]>;
51 def movrr : InstARM<(ops IntRegs:$dst, IntRegs:$src),
52 "mov $dst, $src", []>;
54 def movri : InstARM<(ops IntRegs:$dst, i32imm:$src),
55 "mov $dst, $src", [(set IntRegs:$dst, imm:$src)]>;
57 def addri : InstARM<(ops IntRegs:$dst, IntRegs:$a, i32imm:$b),
59 [(set IntRegs:$dst, (add IntRegs:$a, imm:$b))]>;