1 //===- ARMInstrInfo.td - Target Description for ARM Target -*- tablegen -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file describes the ARM instructions in TableGen format.
12 //===----------------------------------------------------------------------===//
14 //===----------------------------------------------------------------------===//
15 // ARM specific DAG Nodes.
19 def SDT_ARMCallSeqStart : SDCallSeqStart<[ SDTCisVT<0, i32> ]>;
20 def SDT_ARMCallSeqEnd : SDCallSeqEnd<[ SDTCisVT<0, i32>, SDTCisVT<1, i32> ]>;
22 def SDT_ARMSaveCallPC : SDTypeProfile<0, 1, []>;
24 def SDT_ARMcall : SDTypeProfile<0, -1, [SDTCisPtrTy<0>]>;
26 def SDT_ARMCMov : SDTypeProfile<1, 3,
27 [SDTCisSameAs<0, 1>, SDTCisSameAs<0, 2>,
30 def SDT_ARMBrcond : SDTypeProfile<0, 2,
31 [SDTCisVT<0, OtherVT>, SDTCisVT<1, i32>]>;
33 def SDT_ARMBrJT : SDTypeProfile<0, 3,
34 [SDTCisPtrTy<0>, SDTCisVT<1, i32>,
37 def SDT_ARMBr2JT : SDTypeProfile<0, 4,
38 [SDTCisPtrTy<0>, SDTCisVT<1, i32>,
39 SDTCisVT<2, i32>, SDTCisVT<3, i32>]>;
41 def SDT_ARMBCC_i64 : SDTypeProfile<0, 6,
43 SDTCisVT<1, i32>, SDTCisVT<2, i32>,
44 SDTCisVT<3, i32>, SDTCisVT<4, i32>,
45 SDTCisVT<5, OtherVT>]>;
47 def SDT_ARMAnd : SDTypeProfile<1, 2,
48 [SDTCisVT<0, i32>, SDTCisVT<1, i32>,
51 def SDT_ARMCmp : SDTypeProfile<0, 2, [SDTCisSameAs<0, 1>]>;
53 def SDT_ARMPICAdd : SDTypeProfile<1, 2, [SDTCisSameAs<0, 1>,
54 SDTCisPtrTy<1>, SDTCisVT<2, i32>]>;
56 def SDT_ARMThreadPointer : SDTypeProfile<1, 0, [SDTCisPtrTy<0>]>;
57 def SDT_ARMEH_SJLJ_Setjmp : SDTypeProfile<1, 2, [SDTCisInt<0>, SDTCisPtrTy<1>,
59 def SDT_ARMEH_SJLJ_Longjmp: SDTypeProfile<0, 2, [SDTCisPtrTy<0>, SDTCisInt<1>]>;
61 def SDT_ARMEH_SJLJ_DispatchSetup: SDTypeProfile<0, 1, [SDTCisPtrTy<0>]>;
63 def SDT_ARMMEMBARRIER : SDTypeProfile<0, 1, [SDTCisInt<0>]>;
65 def SDT_ARMTCRET : SDTypeProfile<0, 1, [SDTCisPtrTy<0>]>;
67 def SDT_ARMBFI : SDTypeProfile<1, 3, [SDTCisVT<0, i32>, SDTCisVT<1, i32>,
68 SDTCisVT<2, i32>, SDTCisVT<3, i32>]>;
71 def ARMWrapper : SDNode<"ARMISD::Wrapper", SDTIntUnaryOp>;
72 def ARMWrapperJT : SDNode<"ARMISD::WrapperJT", SDTIntBinOp>;
74 def ARMcallseq_start : SDNode<"ISD::CALLSEQ_START", SDT_ARMCallSeqStart,
75 [SDNPHasChain, SDNPOutFlag]>;
76 def ARMcallseq_end : SDNode<"ISD::CALLSEQ_END", SDT_ARMCallSeqEnd,
77 [SDNPHasChain, SDNPOptInFlag, SDNPOutFlag]>;
79 def ARMcall : SDNode<"ARMISD::CALL", SDT_ARMcall,
80 [SDNPHasChain, SDNPOptInFlag, SDNPOutFlag,
82 def ARMcall_pred : SDNode<"ARMISD::CALL_PRED", SDT_ARMcall,
83 [SDNPHasChain, SDNPOptInFlag, SDNPOutFlag,
85 def ARMcall_nolink : SDNode<"ARMISD::CALL_NOLINK", SDT_ARMcall,
86 [SDNPHasChain, SDNPOptInFlag, SDNPOutFlag,
89 def ARMretflag : SDNode<"ARMISD::RET_FLAG", SDTNone,
90 [SDNPHasChain, SDNPOptInFlag]>;
92 def ARMcmov : SDNode<"ARMISD::CMOV", SDT_ARMCMov,
94 def ARMcneg : SDNode<"ARMISD::CNEG", SDT_ARMCMov,
97 def ARMbrcond : SDNode<"ARMISD::BRCOND", SDT_ARMBrcond,
98 [SDNPHasChain, SDNPInFlag, SDNPOutFlag]>;
100 def ARMbrjt : SDNode<"ARMISD::BR_JT", SDT_ARMBrJT,
102 def ARMbr2jt : SDNode<"ARMISD::BR2_JT", SDT_ARMBr2JT,
105 def ARMBcci64 : SDNode<"ARMISD::BCC_i64", SDT_ARMBCC_i64,
108 def ARMcmp : SDNode<"ARMISD::CMP", SDT_ARMCmp,
111 def ARMcmpZ : SDNode<"ARMISD::CMPZ", SDT_ARMCmp,
112 [SDNPOutFlag, SDNPCommutative]>;
114 def ARMpic_add : SDNode<"ARMISD::PIC_ADD", SDT_ARMPICAdd>;
116 def ARMsrl_flag : SDNode<"ARMISD::SRL_FLAG", SDTIntUnaryOp, [SDNPOutFlag]>;
117 def ARMsra_flag : SDNode<"ARMISD::SRA_FLAG", SDTIntUnaryOp, [SDNPOutFlag]>;
118 def ARMrrx : SDNode<"ARMISD::RRX" , SDTIntUnaryOp, [SDNPInFlag ]>;
120 def ARMthread_pointer: SDNode<"ARMISD::THREAD_POINTER", SDT_ARMThreadPointer>;
121 def ARMeh_sjlj_setjmp: SDNode<"ARMISD::EH_SJLJ_SETJMP",
122 SDT_ARMEH_SJLJ_Setjmp, [SDNPHasChain]>;
123 def ARMeh_sjlj_longjmp: SDNode<"ARMISD::EH_SJLJ_LONGJMP",
124 SDT_ARMEH_SJLJ_Longjmp, [SDNPHasChain]>;
125 def ARMeh_sjlj_dispatchsetup: SDNode<"ARMISD::EH_SJLJ_DISPATCHSETUP",
126 SDT_ARMEH_SJLJ_DispatchSetup, [SDNPHasChain]>;
129 def ARMMemBarrier : SDNode<"ARMISD::MEMBARRIER", SDT_ARMMEMBARRIER,
131 def ARMMemBarrierMCR : SDNode<"ARMISD::MEMBARRIER_MCR", SDT_ARMMEMBARRIER,
133 def ARMPreload : SDNode<"ARMISD::PRELOAD", SDTPrefetch,
134 [SDNPHasChain, SDNPMayLoad, SDNPMayStore]>;
136 def ARMrbit : SDNode<"ARMISD::RBIT", SDTIntUnaryOp>;
138 def ARMtcret : SDNode<"ARMISD::TC_RETURN", SDT_ARMTCRET,
139 [SDNPHasChain, SDNPOptInFlag, SDNPVariadic]>;
142 def ARMbfi : SDNode<"ARMISD::BFI", SDT_ARMBFI>;
144 //===----------------------------------------------------------------------===//
145 // ARM Instruction Predicate Definitions.
147 def HasV4T : Predicate<"Subtarget->hasV4TOps()">, AssemblerPredicate;
148 def NoV4T : Predicate<"!Subtarget->hasV4TOps()">;
149 def HasV5T : Predicate<"Subtarget->hasV5TOps()">;
150 def HasV5TE : Predicate<"Subtarget->hasV5TEOps()">, AssemblerPredicate;
151 def HasV6 : Predicate<"Subtarget->hasV6Ops()">, AssemblerPredicate;
152 def HasV6T2 : Predicate<"Subtarget->hasV6T2Ops()">, AssemblerPredicate;
153 def NoV6T2 : Predicate<"!Subtarget->hasV6T2Ops()">;
154 def HasV7 : Predicate<"Subtarget->hasV7Ops()">, AssemblerPredicate;
155 def NoVFP : Predicate<"!Subtarget->hasVFP2()">;
156 def HasVFP2 : Predicate<"Subtarget->hasVFP2()">, AssemblerPredicate;
157 def HasVFP3 : Predicate<"Subtarget->hasVFP3()">, AssemblerPredicate;
158 def HasNEON : Predicate<"Subtarget->hasNEON()">, AssemblerPredicate;
159 def HasDivide : Predicate<"Subtarget->hasDivide()">, AssemblerPredicate;
160 def HasT2ExtractPack : Predicate<"Subtarget->hasT2ExtractPack()">,
162 def HasDB : Predicate<"Subtarget->hasDataBarrier()">,
164 def HasMP : Predicate<"Subtarget->hasMPExtension()">,
166 def UseNEONForFP : Predicate<"Subtarget->useNEONForSinglePrecisionFP()">;
167 def DontUseNEONForFP : Predicate<"!Subtarget->useNEONForSinglePrecisionFP()">;
168 def IsThumb : Predicate<"Subtarget->isThumb()">, AssemblerPredicate;
169 def IsThumb1Only : Predicate<"Subtarget->isThumb1Only()">;
170 def IsThumb2 : Predicate<"Subtarget->isThumb2()">, AssemblerPredicate;
171 def IsARM : Predicate<"!Subtarget->isThumb()">, AssemblerPredicate;
172 def IsDarwin : Predicate<"Subtarget->isTargetDarwin()">;
173 def IsNotDarwin : Predicate<"!Subtarget->isTargetDarwin()">;
175 // FIXME: Eventually this will be just "hasV6T2Ops".
176 def UseMovt : Predicate<"Subtarget->useMovt()">;
177 def DontUseMovt : Predicate<"!Subtarget->useMovt()">;
178 def UseVMLx : Predicate<"Subtarget->useVMLx()">;
180 //===----------------------------------------------------------------------===//
181 // ARM Flag Definitions.
183 class RegConstraint<string C> {
184 string Constraints = C;
187 //===----------------------------------------------------------------------===//
188 // ARM specific transformation functions and pattern fragments.
191 // so_imm_neg_XFORM - Return a so_imm value packed into the format described for
192 // so_imm_neg def below.
193 def so_imm_neg_XFORM : SDNodeXForm<imm, [{
194 return CurDAG->getTargetConstant(-(int)N->getZExtValue(), MVT::i32);
197 // so_imm_not_XFORM - Return a so_imm value packed into the format described for
198 // so_imm_not def below.
199 def so_imm_not_XFORM : SDNodeXForm<imm, [{
200 return CurDAG->getTargetConstant(~(int)N->getZExtValue(), MVT::i32);
203 /// imm1_15 predicate - True if the 32-bit immediate is in the range [1,15].
204 def imm1_15 : PatLeaf<(i32 imm), [{
205 return (int32_t)N->getZExtValue() >= 1 && (int32_t)N->getZExtValue() < 16;
208 /// imm16_31 predicate - True if the 32-bit immediate is in the range [16,31].
209 def imm16_31 : PatLeaf<(i32 imm), [{
210 return (int32_t)N->getZExtValue() >= 16 && (int32_t)N->getZExtValue() < 32;
215 return ARM_AM::getSOImmVal(-(uint32_t)N->getZExtValue()) != -1;
216 }], so_imm_neg_XFORM>;
220 return ARM_AM::getSOImmVal(~(uint32_t)N->getZExtValue()) != -1;
221 }], so_imm_not_XFORM>;
223 // sext_16_node predicate - True if the SDNode is sign-extended 16 or more bits.
224 def sext_16_node : PatLeaf<(i32 GPR:$a), [{
225 return CurDAG->ComputeNumSignBits(SDValue(N,0)) >= 17;
228 /// bf_inv_mask_imm predicate - An AND mask to clear an arbitrary width bitfield
230 def bf_inv_mask_imm : Operand<i32>,
232 return ARM::isBitFieldInvertedMask(N->getZExtValue());
234 let EncoderMethod = "getBitfieldInvertedMaskOpValue";
235 let PrintMethod = "printBitfieldInvMaskImmOperand";
238 /// Split a 32-bit immediate into two 16 bit parts.
239 def hi16 : SDNodeXForm<imm, [{
240 return CurDAG->getTargetConstant((uint32_t)N->getZExtValue() >> 16, MVT::i32);
243 def lo16AllZero : PatLeaf<(i32 imm), [{
244 // Returns true if all low 16-bits are 0.
245 return (((uint32_t)N->getZExtValue()) & 0xFFFFUL) == 0;
248 /// imm0_65535 predicate - True if the 32-bit immediate is in the range
250 def imm0_65535 : PatLeaf<(i32 imm), [{
251 return (uint32_t)N->getZExtValue() < 65536;
254 class BinOpFrag<dag res> : PatFrag<(ops node:$LHS, node:$RHS), res>;
255 class UnOpFrag <dag res> : PatFrag<(ops node:$Src), res>;
257 /// adde and sube predicates - True based on whether the carry flag output
258 /// will be needed or not.
259 def adde_dead_carry :
260 PatFrag<(ops node:$LHS, node:$RHS), (adde node:$LHS, node:$RHS),
261 [{return !N->hasAnyUseOfValue(1);}]>;
262 def sube_dead_carry :
263 PatFrag<(ops node:$LHS, node:$RHS), (sube node:$LHS, node:$RHS),
264 [{return !N->hasAnyUseOfValue(1);}]>;
265 def adde_live_carry :
266 PatFrag<(ops node:$LHS, node:$RHS), (adde node:$LHS, node:$RHS),
267 [{return N->hasAnyUseOfValue(1);}]>;
268 def sube_live_carry :
269 PatFrag<(ops node:$LHS, node:$RHS), (sube node:$LHS, node:$RHS),
270 [{return N->hasAnyUseOfValue(1);}]>;
272 // An 'and' node with a single use.
273 def and_su : PatFrag<(ops node:$lhs, node:$rhs), (and node:$lhs, node:$rhs), [{
274 return N->hasOneUse();
277 // An 'xor' node with a single use.
278 def xor_su : PatFrag<(ops node:$lhs, node:$rhs), (xor node:$lhs, node:$rhs), [{
279 return N->hasOneUse();
282 //===----------------------------------------------------------------------===//
283 // Operand Definitions.
287 def brtarget : Operand<OtherVT> {
288 let EncoderMethod = "getBranchTargetOpValue";
292 def bltarget : Operand<i32> {
293 // Encoded the same as branch targets.
294 let EncoderMethod = "getBranchTargetOpValue";
297 // A list of registers separated by comma. Used by load/store multiple.
298 def RegListAsmOperand : AsmOperandClass {
299 let Name = "RegList";
300 let SuperClasses = [];
303 def DPRRegListAsmOperand : AsmOperandClass {
304 let Name = "DPRRegList";
305 let SuperClasses = [];
308 def SPRRegListAsmOperand : AsmOperandClass {
309 let Name = "SPRRegList";
310 let SuperClasses = [];
313 def reglist : Operand<i32> {
314 let EncoderMethod = "getRegisterListOpValue";
315 let ParserMatchClass = RegListAsmOperand;
316 let PrintMethod = "printRegisterList";
319 def dpr_reglist : Operand<i32> {
320 let EncoderMethod = "getRegisterListOpValue";
321 let ParserMatchClass = DPRRegListAsmOperand;
322 let PrintMethod = "printRegisterList";
325 def spr_reglist : Operand<i32> {
326 let EncoderMethod = "getRegisterListOpValue";
327 let ParserMatchClass = SPRRegListAsmOperand;
328 let PrintMethod = "printRegisterList";
331 // An operand for the CONSTPOOL_ENTRY pseudo-instruction.
332 def cpinst_operand : Operand<i32> {
333 let PrintMethod = "printCPInstOperand";
337 def pclabel : Operand<i32> {
338 let PrintMethod = "printPCLabel";
341 def neon_vcvt_imm32 : Operand<i32> {
342 let EncoderMethod = "getNEONVcvtImm32OpValue";
345 // rot_imm: An integer that encodes a rotate amount. Must be 8, 16, or 24.
346 def rot_imm : Operand<i32>, PatLeaf<(i32 imm), [{
347 int32_t v = (int32_t)N->getZExtValue();
348 return v == 8 || v == 16 || v == 24; }]> {
349 let EncoderMethod = "getRotImmOpValue";
352 // shift_imm: An integer that encodes a shift amount and the type of shift
353 // (currently either asr or lsl) using the same encoding used for the
354 // immediates in so_reg operands.
355 def shift_imm : Operand<i32> {
356 let PrintMethod = "printShiftImmOperand";
359 // shifter_operand operands: so_reg and so_imm.
360 def so_reg : Operand<i32>, // reg reg imm
361 ComplexPattern<i32, 3, "SelectShifterOperandReg",
362 [shl,srl,sra,rotr]> {
363 let EncoderMethod = "getSORegOpValue";
364 let PrintMethod = "printSORegOperand";
365 let MIOperandInfo = (ops GPR, GPR, i32imm);
367 def shift_so_reg : Operand<i32>, // reg reg imm
368 ComplexPattern<i32, 3, "SelectShiftShifterOperandReg",
369 [shl,srl,sra,rotr]> {
370 let EncoderMethod = "getSORegOpValue";
371 let PrintMethod = "printSORegOperand";
372 let MIOperandInfo = (ops GPR, GPR, i32imm);
375 // so_imm - Match a 32-bit shifter_operand immediate operand, which is an
376 // 8-bit immediate rotated by an arbitrary number of bits. so_imm values are
377 // represented in the imm field in the same 12-bit form that they are encoded
378 // into so_imm instructions: the 8-bit immediate is the least significant bits
379 // [bits 0-7], the 4-bit shift amount is the next 4 bits [bits 8-11].
380 def so_imm : Operand<i32>, PatLeaf<(imm), [{ return Pred_so_imm(N); }]> {
381 let EncoderMethod = "getSOImmOpValue";
382 let PrintMethod = "printSOImmOperand";
385 // Break so_imm's up into two pieces. This handles immediates with up to 16
386 // bits set in them. This uses so_imm2part to match and so_imm2part_[12] to
387 // get the first/second pieces.
388 def so_imm2part : PatLeaf<(imm), [{
389 return ARM_AM::isSOImmTwoPartVal((unsigned)N->getZExtValue());
392 /// arm_i32imm - True for +V6T2, or true only if so_imm2part is true.
394 def arm_i32imm : PatLeaf<(imm), [{
395 if (Subtarget->hasV6T2Ops())
397 return ARM_AM::isSOImmTwoPartVal((unsigned)N->getZExtValue());
400 def so_imm2part_1 : SDNodeXForm<imm, [{
401 unsigned V = ARM_AM::getSOImmTwoPartFirst((unsigned)N->getZExtValue());
402 return CurDAG->getTargetConstant(V, MVT::i32);
405 def so_imm2part_2 : SDNodeXForm<imm, [{
406 unsigned V = ARM_AM::getSOImmTwoPartSecond((unsigned)N->getZExtValue());
407 return CurDAG->getTargetConstant(V, MVT::i32);
410 def so_neg_imm2part : Operand<i32>, PatLeaf<(imm), [{
411 return ARM_AM::isSOImmTwoPartVal(-(int)N->getZExtValue());
413 let PrintMethod = "printSOImm2PartOperand";
416 def so_neg_imm2part_1 : SDNodeXForm<imm, [{
417 unsigned V = ARM_AM::getSOImmTwoPartFirst(-(int)N->getZExtValue());
418 return CurDAG->getTargetConstant(V, MVT::i32);
421 def so_neg_imm2part_2 : SDNodeXForm<imm, [{
422 unsigned V = ARM_AM::getSOImmTwoPartSecond(-(int)N->getZExtValue());
423 return CurDAG->getTargetConstant(V, MVT::i32);
426 /// imm0_31 predicate - True if the 32-bit immediate is in the range [0,31].
427 def imm0_31 : Operand<i32>, PatLeaf<(imm), [{
428 return (int32_t)N->getZExtValue() < 32;
431 /// imm0_31_m1 - Matches and prints like imm0_31, but encodes as 'value - 1'.
432 def imm0_31_m1 : Operand<i32>, PatLeaf<(imm), [{
433 return (int32_t)N->getZExtValue() < 32;
435 let EncoderMethod = "getImmMinusOneOpValue";
438 // For movt/movw - sets the MC Encoder method.
439 // The imm is split into imm{15-12}, imm{11-0}
441 def movt_imm : Operand<i32> {
442 let EncoderMethod = "getMovtImmOpValue";
445 // Define ARM specific addressing modes.
448 // addrmode_imm12 := reg +/- imm12
450 def addrmode_imm12 : Operand<i32>,
451 ComplexPattern<i32, 2, "SelectAddrModeImm12", []> {
452 // 12-bit immediate operand. Note that instructions using this encode
453 // #0 and #-0 differently. We flag #-0 as the magic value INT32_MIN. All other
454 // immediate values are as normal.
456 let EncoderMethod = "getAddrModeImm12OpValue";
457 let PrintMethod = "printAddrModeImm12Operand";
458 let MIOperandInfo = (ops GPR:$base, i32imm:$offsimm);
460 // ldst_so_reg := reg +/- reg shop imm
462 def ldst_so_reg : Operand<i32>,
463 ComplexPattern<i32, 3, "SelectLdStSOReg", []> {
464 let EncoderMethod = "getLdStSORegOpValue";
465 // FIXME: Simplify the printer
466 let PrintMethod = "printAddrMode2Operand";
467 let MIOperandInfo = (ops GPR:$base, GPR:$offsreg, i32imm:$offsimm);
470 // addrmode2 := reg +/- imm12
471 // := reg +/- reg shop imm
473 def addrmode2 : Operand<i32>,
474 ComplexPattern<i32, 3, "SelectAddrMode2", []> {
475 string EncoderMethod = "getAddrMode2OpValue";
476 let PrintMethod = "printAddrMode2Operand";
477 let MIOperandInfo = (ops GPR:$base, GPR:$offsreg, i32imm:$offsimm);
480 def am2offset : Operand<i32>,
481 ComplexPattern<i32, 2, "SelectAddrMode2Offset",
482 [], [SDNPWantRoot]> {
483 string EncoderMethod = "getAddrMode2OffsetOpValue";
484 let PrintMethod = "printAddrMode2OffsetOperand";
485 let MIOperandInfo = (ops GPR, i32imm);
488 // addrmode3 := reg +/- reg
489 // addrmode3 := reg +/- imm8
491 def addrmode3 : Operand<i32>,
492 ComplexPattern<i32, 3, "SelectAddrMode3", []> {
493 let EncoderMethod = "getAddrMode3OpValue";
494 let PrintMethod = "printAddrMode3Operand";
495 let MIOperandInfo = (ops GPR:$base, GPR:$offsreg, i32imm:$offsimm);
498 def am3offset : Operand<i32>,
499 ComplexPattern<i32, 2, "SelectAddrMode3Offset",
500 [], [SDNPWantRoot]> {
501 let EncoderMethod = "getAddrMode3OffsetOpValue";
502 let PrintMethod = "printAddrMode3OffsetOperand";
503 let MIOperandInfo = (ops GPR, i32imm);
506 // ldstm_mode := {ia, ib, da, db}
508 def ldstm_mode : OptionalDefOperand<OtherVT, (ops i32), (ops (i32 1))> {
509 let EncoderMethod = "getLdStmModeOpValue";
510 let PrintMethod = "printLdStmModeOperand";
513 def MemMode5AsmOperand : AsmOperandClass {
514 let Name = "MemMode5";
515 let SuperClasses = [];
518 // addrmode5 := reg +/- imm8*4
520 def addrmode5 : Operand<i32>,
521 ComplexPattern<i32, 2, "SelectAddrMode5", []> {
522 let PrintMethod = "printAddrMode5Operand";
523 let MIOperandInfo = (ops GPR:$base, i32imm);
524 let ParserMatchClass = MemMode5AsmOperand;
525 let EncoderMethod = "getAddrMode5OpValue";
528 // addrmode6 := reg with optional writeback
530 def addrmode6 : Operand<i32>,
531 ComplexPattern<i32, 2, "SelectAddrMode6", [], [SDNPWantParent]>{
532 let PrintMethod = "printAddrMode6Operand";
533 let MIOperandInfo = (ops GPR:$addr, i32imm);
534 let EncoderMethod = "getAddrMode6AddressOpValue";
537 def am6offset : Operand<i32> {
538 let PrintMethod = "printAddrMode6OffsetOperand";
539 let MIOperandInfo = (ops GPR);
540 let EncoderMethod = "getAddrMode6OffsetOpValue";
543 // addrmodepc := pc + reg
545 def addrmodepc : Operand<i32>,
546 ComplexPattern<i32, 2, "SelectAddrModePC", []> {
547 let PrintMethod = "printAddrModePCOperand";
548 let MIOperandInfo = (ops GPR, i32imm);
551 def nohash_imm : Operand<i32> {
552 let PrintMethod = "printNoHashImmediate";
555 //===----------------------------------------------------------------------===//
557 include "ARMInstrFormats.td"
559 //===----------------------------------------------------------------------===//
560 // Multiclass helpers...
563 /// AsI1_bin_irs - Defines a set of (op r, {so_imm|r|so_reg}) patterns for a
564 /// binop that produces a value.
565 multiclass AsI1_bin_irs<bits<4> opcod, string opc,
566 InstrItinClass iii, InstrItinClass iir, InstrItinClass iis,
567 PatFrag opnode, bit Commutable = 0> {
568 // The register-immediate version is re-materializable. This is useful
569 // in particular for taking the address of a local.
570 let isReMaterializable = 1 in {
571 def ri : AsI1<opcod, (outs GPR:$Rd), (ins GPR:$Rn, so_imm:$imm), DPFrm,
572 iii, opc, "\t$Rd, $Rn, $imm",
573 [(set GPR:$Rd, (opnode GPR:$Rn, so_imm:$imm))]> {
578 let Inst{19-16} = Rn;
579 let Inst{15-12} = Rd;
580 let Inst{11-0} = imm;
583 def rr : AsI1<opcod, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm), DPFrm,
584 iir, opc, "\t$Rd, $Rn, $Rm",
585 [(set GPR:$Rd, (opnode GPR:$Rn, GPR:$Rm))]> {
590 let isCommutable = Commutable;
591 let Inst{19-16} = Rn;
592 let Inst{15-12} = Rd;
593 let Inst{11-4} = 0b00000000;
596 def rs : AsI1<opcod, (outs GPR:$Rd), (ins GPR:$Rn, so_reg:$shift), DPSoRegFrm,
597 iis, opc, "\t$Rd, $Rn, $shift",
598 [(set GPR:$Rd, (opnode GPR:$Rn, so_reg:$shift))]> {
603 let Inst{19-16} = Rn;
604 let Inst{15-12} = Rd;
605 let Inst{11-0} = shift;
609 /// AI1_bin_s_irs - Similar to AsI1_bin_irs except it sets the 's' bit so the
610 /// instruction modifies the CPSR register.
611 let Defs = [CPSR] in {
612 multiclass AI1_bin_s_irs<bits<4> opcod, string opc,
613 InstrItinClass iii, InstrItinClass iir, InstrItinClass iis,
614 PatFrag opnode, bit Commutable = 0> {
615 def ri : AI1<opcod, (outs GPR:$Rd), (ins GPR:$Rn, so_imm:$imm), DPFrm,
616 iii, opc, "\t$Rd, $Rn, $imm",
617 [(set GPR:$Rd, (opnode GPR:$Rn, so_imm:$imm))]> {
623 let Inst{19-16} = Rn;
624 let Inst{15-12} = Rd;
625 let Inst{11-0} = imm;
627 def rr : AI1<opcod, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm), DPFrm,
628 iir, opc, "\t$Rd, $Rn, $Rm",
629 [(set GPR:$Rd, (opnode GPR:$Rn, GPR:$Rm))]> {
633 let isCommutable = Commutable;
636 let Inst{19-16} = Rn;
637 let Inst{15-12} = Rd;
638 let Inst{11-4} = 0b00000000;
641 def rs : AI1<opcod, (outs GPR:$Rd), (ins GPR:$Rn, so_reg:$shift), DPSoRegFrm,
642 iis, opc, "\t$Rd, $Rn, $shift",
643 [(set GPR:$Rd, (opnode GPR:$Rn, so_reg:$shift))]> {
649 let Inst{19-16} = Rn;
650 let Inst{15-12} = Rd;
651 let Inst{11-0} = shift;
656 /// AI1_cmp_irs - Defines a set of (op r, {so_imm|r|so_reg}) cmp / test
657 /// patterns. Similar to AsI1_bin_irs except the instruction does not produce
658 /// a explicit result, only implicitly set CPSR.
659 let isCompare = 1, Defs = [CPSR] in {
660 multiclass AI1_cmp_irs<bits<4> opcod, string opc,
661 InstrItinClass iii, InstrItinClass iir, InstrItinClass iis,
662 PatFrag opnode, bit Commutable = 0> {
663 def ri : AI1<opcod, (outs), (ins GPR:$Rn, so_imm:$imm), DPFrm, iii,
665 [(opnode GPR:$Rn, so_imm:$imm)]> {
670 let Inst{19-16} = Rn;
671 let Inst{15-12} = 0b0000;
672 let Inst{11-0} = imm;
674 def rr : AI1<opcod, (outs), (ins GPR:$Rn, GPR:$Rm), DPFrm, iir,
676 [(opnode GPR:$Rn, GPR:$Rm)]> {
679 let isCommutable = Commutable;
682 let Inst{19-16} = Rn;
683 let Inst{15-12} = 0b0000;
684 let Inst{11-4} = 0b00000000;
687 def rs : AI1<opcod, (outs), (ins GPR:$Rn, so_reg:$shift), DPSoRegFrm, iis,
688 opc, "\t$Rn, $shift",
689 [(opnode GPR:$Rn, so_reg:$shift)]> {
694 let Inst{19-16} = Rn;
695 let Inst{15-12} = 0b0000;
696 let Inst{11-0} = shift;
701 /// AI_ext_rrot - A unary operation with two forms: one whose operand is a
702 /// register and one whose operand is a register rotated by 8/16/24.
703 /// FIXME: Remove the 'r' variant. Its rot_imm is zero.
704 multiclass AI_ext_rrot<bits<8> opcod, string opc, PatFrag opnode> {
705 def r : AExtI<opcod, (outs GPR:$Rd), (ins GPR:$Rm),
706 IIC_iEXTr, opc, "\t$Rd, $Rm",
707 [(set GPR:$Rd, (opnode GPR:$Rm))]>,
708 Requires<[IsARM, HasV6]> {
711 let Inst{19-16} = 0b1111;
712 let Inst{15-12} = Rd;
713 let Inst{11-10} = 0b00;
716 def r_rot : AExtI<opcod, (outs GPR:$Rd), (ins GPR:$Rm, rot_imm:$rot),
717 IIC_iEXTr, opc, "\t$Rd, $Rm, ror $rot",
718 [(set GPR:$Rd, (opnode (rotr GPR:$Rm, rot_imm:$rot)))]>,
719 Requires<[IsARM, HasV6]> {
723 let Inst{19-16} = 0b1111;
724 let Inst{15-12} = Rd;
725 let Inst{11-10} = rot;
730 multiclass AI_ext_rrot_np<bits<8> opcod, string opc> {
731 def r : AExtI<opcod, (outs GPR:$Rd), (ins GPR:$Rm),
732 IIC_iEXTr, opc, "\t$Rd, $Rm",
733 [/* For disassembly only; pattern left blank */]>,
734 Requires<[IsARM, HasV6]> {
735 let Inst{19-16} = 0b1111;
736 let Inst{11-10} = 0b00;
738 def r_rot : AExtI<opcod, (outs GPR:$Rd), (ins GPR:$Rm, rot_imm:$rot),
739 IIC_iEXTr, opc, "\t$Rd, $Rm, ror $rot",
740 [/* For disassembly only; pattern left blank */]>,
741 Requires<[IsARM, HasV6]> {
743 let Inst{19-16} = 0b1111;
744 let Inst{11-10} = rot;
748 /// AI_exta_rrot - A binary operation with two forms: one whose operand is a
749 /// register and one whose operand is a register rotated by 8/16/24.
750 multiclass AI_exta_rrot<bits<8> opcod, string opc, PatFrag opnode> {
751 def rr : AExtI<opcod, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm),
752 IIC_iEXTAr, opc, "\t$Rd, $Rn, $Rm",
753 [(set GPR:$Rd, (opnode GPR:$Rn, GPR:$Rm))]>,
754 Requires<[IsARM, HasV6]> {
758 let Inst{19-16} = Rn;
759 let Inst{15-12} = Rd;
760 let Inst{11-10} = 0b00;
761 let Inst{9-4} = 0b000111;
764 def rr_rot : AExtI<opcod, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm,
766 IIC_iEXTAr, opc, "\t$Rd, $Rn, $Rm, ror $rot",
767 [(set GPR:$Rd, (opnode GPR:$Rn,
768 (rotr GPR:$Rm, rot_imm:$rot)))]>,
769 Requires<[IsARM, HasV6]> {
774 let Inst{19-16} = Rn;
775 let Inst{15-12} = Rd;
776 let Inst{11-10} = rot;
777 let Inst{9-4} = 0b000111;
782 // For disassembly only.
783 multiclass AI_exta_rrot_np<bits<8> opcod, string opc> {
784 def rr : AExtI<opcod, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm),
785 IIC_iEXTAr, opc, "\t$Rd, $Rn, $Rm",
786 [/* For disassembly only; pattern left blank */]>,
787 Requires<[IsARM, HasV6]> {
788 let Inst{11-10} = 0b00;
790 def rr_rot : AExtI<opcod, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm,
792 IIC_iEXTAr, opc, "\t$Rd, $Rn, $Rm, ror $rot",
793 [/* For disassembly only; pattern left blank */]>,
794 Requires<[IsARM, HasV6]> {
797 let Inst{19-16} = Rn;
798 let Inst{11-10} = rot;
802 /// AI1_adde_sube_irs - Define instructions and patterns for adde and sube.
803 let Uses = [CPSR] in {
804 multiclass AI1_adde_sube_irs<bits<4> opcod, string opc, PatFrag opnode,
805 bit Commutable = 0> {
806 def ri : AsI1<opcod, (outs GPR:$Rd), (ins GPR:$Rn, so_imm:$imm),
807 DPFrm, IIC_iALUi, opc, "\t$Rd, $Rn, $imm",
808 [(set GPR:$Rd, (opnode GPR:$Rn, so_imm:$imm))]>,
814 let Inst{15-12} = Rd;
815 let Inst{19-16} = Rn;
816 let Inst{11-0} = imm;
818 def rr : AsI1<opcod, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm),
819 DPFrm, IIC_iALUr, opc, "\t$Rd, $Rn, $Rm",
820 [(set GPR:$Rd, (opnode GPR:$Rn, GPR:$Rm))]>,
825 let Inst{11-4} = 0b00000000;
827 let isCommutable = Commutable;
829 let Inst{15-12} = Rd;
830 let Inst{19-16} = Rn;
832 def rs : AsI1<opcod, (outs GPR:$Rd), (ins GPR:$Rn, so_reg:$shift),
833 DPSoRegFrm, IIC_iALUsr, opc, "\t$Rd, $Rn, $shift",
834 [(set GPR:$Rd, (opnode GPR:$Rn, so_reg:$shift))]>,
840 let Inst{11-0} = shift;
841 let Inst{15-12} = Rd;
842 let Inst{19-16} = Rn;
845 // Carry setting variants
846 let Defs = [CPSR] in {
847 multiclass AI1_adde_sube_s_irs<bits<4> opcod, string opc, PatFrag opnode,
848 bit Commutable = 0> {
849 def Sri : AXI1<opcod, (outs GPR:$Rd), (ins GPR:$Rn, so_imm:$imm),
850 DPFrm, IIC_iALUi, !strconcat(opc, "\t$Rd, $Rn, $imm"),
851 [(set GPR:$Rd, (opnode GPR:$Rn, so_imm:$imm))]>,
856 let Inst{15-12} = Rd;
857 let Inst{19-16} = Rn;
858 let Inst{11-0} = imm;
862 def Srr : AXI1<opcod, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm),
863 DPFrm, IIC_iALUr, !strconcat(opc, "\t$Rd, $Rn, $Rm"),
864 [(set GPR:$Rd, (opnode GPR:$Rn, GPR:$Rm))]>,
869 let Inst{11-4} = 0b00000000;
870 let isCommutable = Commutable;
872 let Inst{15-12} = Rd;
873 let Inst{19-16} = Rn;
877 def Srs : AXI1<opcod, (outs GPR:$Rd), (ins GPR:$Rn, so_reg:$shift),
878 DPSoRegFrm, IIC_iALUsr, !strconcat(opc, "\t$Rd, $Rn, $shift"),
879 [(set GPR:$Rd, (opnode GPR:$Rn, so_reg:$shift))]>,
884 let Inst{11-0} = shift;
885 let Inst{15-12} = Rd;
886 let Inst{19-16} = Rn;
894 let canFoldAsLoad = 1, isReMaterializable = 1 in {
895 multiclass AI_ldr1<bit isByte, string opc, InstrItinClass iii,
896 InstrItinClass iir, PatFrag opnode> {
897 // Note: We use the complex addrmode_imm12 rather than just an input
898 // GPR and a constrained immediate so that we can use this to match
899 // frame index references and avoid matching constant pool references.
900 def i12: AI2ldst<0b010, 1, isByte, (outs GPR:$Rt), (ins addrmode_imm12:$addr),
901 AddrMode_i12, LdFrm, iii, opc, "\t$Rt, $addr",
902 [(set GPR:$Rt, (opnode addrmode_imm12:$addr))]> {
905 let Inst{23} = addr{12}; // U (add = ('U' == 1))
906 let Inst{19-16} = addr{16-13}; // Rn
907 let Inst{15-12} = Rt;
908 let Inst{11-0} = addr{11-0}; // imm12
910 def rs : AI2ldst<0b011, 1, isByte, (outs GPR:$Rt), (ins ldst_so_reg:$shift),
911 AddrModeNone, LdFrm, iir, opc, "\t$Rt, $shift",
912 [(set GPR:$Rt, (opnode ldst_so_reg:$shift))]> {
915 let Inst{23} = shift{12}; // U (add = ('U' == 1))
916 let Inst{19-16} = shift{16-13}; // Rn
917 let Inst{15-12} = Rt;
918 let Inst{11-0} = shift{11-0};
923 multiclass AI_str1<bit isByte, string opc, InstrItinClass iii,
924 InstrItinClass iir, PatFrag opnode> {
925 // Note: We use the complex addrmode_imm12 rather than just an input
926 // GPR and a constrained immediate so that we can use this to match
927 // frame index references and avoid matching constant pool references.
928 def i12 : AI2ldst<0b010, 0, isByte, (outs),
929 (ins GPR:$Rt, addrmode_imm12:$addr),
930 AddrMode_i12, StFrm, iii, opc, "\t$Rt, $addr",
931 [(opnode GPR:$Rt, addrmode_imm12:$addr)]> {
934 let Inst{23} = addr{12}; // U (add = ('U' == 1))
935 let Inst{19-16} = addr{16-13}; // Rn
936 let Inst{15-12} = Rt;
937 let Inst{11-0} = addr{11-0}; // imm12
939 def rs : AI2ldst<0b011, 0, isByte, (outs), (ins GPR:$Rt, ldst_so_reg:$shift),
940 AddrModeNone, StFrm, iir, opc, "\t$Rt, $shift",
941 [(opnode GPR:$Rt, ldst_so_reg:$shift)]> {
944 let Inst{23} = shift{12}; // U (add = ('U' == 1))
945 let Inst{19-16} = shift{16-13}; // Rn
946 let Inst{15-12} = Rt;
947 let Inst{11-0} = shift{11-0};
950 //===----------------------------------------------------------------------===//
952 //===----------------------------------------------------------------------===//
954 //===----------------------------------------------------------------------===//
955 // Miscellaneous Instructions.
958 /// CONSTPOOL_ENTRY - This instruction represents a floating constant pool in
959 /// the function. The first operand is the ID# for this instruction, the second
960 /// is the index into the MachineConstantPool that this is, the third is the
961 /// size in bytes of this constant pool entry.
962 let neverHasSideEffects = 1, isNotDuplicable = 1 in
963 def CONSTPOOL_ENTRY :
964 PseudoInst<(outs), (ins cpinst_operand:$instid, cpinst_operand:$cpidx,
965 i32imm:$size), NoItinerary, []>;
967 // FIXME: Marking these as hasSideEffects is necessary to prevent machine DCE
968 // from removing one half of the matched pairs. That breaks PEI, which assumes
969 // these will always be in pairs, and asserts if it finds otherwise. Better way?
970 let Defs = [SP], Uses = [SP], hasSideEffects = 1 in {
972 PseudoInst<(outs), (ins i32imm:$amt1, i32imm:$amt2, pred:$p), NoItinerary,
973 [(ARMcallseq_end timm:$amt1, timm:$amt2)]>;
975 def ADJCALLSTACKDOWN :
976 PseudoInst<(outs), (ins i32imm:$amt, pred:$p), NoItinerary,
977 [(ARMcallseq_start timm:$amt)]>;
980 def NOP : AI<(outs), (ins), MiscFrm, NoItinerary, "nop", "",
981 [/* For disassembly only; pattern left blank */]>,
982 Requires<[IsARM, HasV6T2]> {
983 let Inst{27-16} = 0b001100100000;
984 let Inst{15-8} = 0b11110000;
985 let Inst{7-0} = 0b00000000;
988 def YIELD : AI<(outs), (ins), MiscFrm, NoItinerary, "yield", "",
989 [/* For disassembly only; pattern left blank */]>,
990 Requires<[IsARM, HasV6T2]> {
991 let Inst{27-16} = 0b001100100000;
992 let Inst{15-8} = 0b11110000;
993 let Inst{7-0} = 0b00000001;
996 def WFE : AI<(outs), (ins), MiscFrm, NoItinerary, "wfe", "",
997 [/* For disassembly only; pattern left blank */]>,
998 Requires<[IsARM, HasV6T2]> {
999 let Inst{27-16} = 0b001100100000;
1000 let Inst{15-8} = 0b11110000;
1001 let Inst{7-0} = 0b00000010;
1004 def WFI : AI<(outs), (ins), MiscFrm, NoItinerary, "wfi", "",
1005 [/* For disassembly only; pattern left blank */]>,
1006 Requires<[IsARM, HasV6T2]> {
1007 let Inst{27-16} = 0b001100100000;
1008 let Inst{15-8} = 0b11110000;
1009 let Inst{7-0} = 0b00000011;
1012 def SEL : AI<(outs GPR:$dst), (ins GPR:$a, GPR:$b), DPFrm, NoItinerary, "sel",
1014 [/* For disassembly only; pattern left blank */]>,
1015 Requires<[IsARM, HasV6]> {
1020 let Inst{15-12} = Rd;
1021 let Inst{19-16} = Rn;
1022 let Inst{27-20} = 0b01101000;
1023 let Inst{7-4} = 0b1011;
1024 let Inst{11-8} = 0b1111;
1027 def SEV : AI<(outs), (ins), MiscFrm, NoItinerary, "sev", "",
1028 [/* For disassembly only; pattern left blank */]>,
1029 Requires<[IsARM, HasV6T2]> {
1030 let Inst{27-16} = 0b001100100000;
1031 let Inst{15-8} = 0b11110000;
1032 let Inst{7-0} = 0b00000100;
1035 // The i32imm operand $val can be used by a debugger to store more information
1036 // about the breakpoint.
1037 def BKPT : AI<(outs), (ins i32imm:$val), MiscFrm, NoItinerary, "bkpt", "\t$val",
1038 [/* For disassembly only; pattern left blank */]>,
1041 let Inst{3-0} = val{3-0};
1042 let Inst{19-8} = val{15-4};
1043 let Inst{27-20} = 0b00010010;
1044 let Inst{7-4} = 0b0111;
1047 // Change Processor State is a system instruction -- for disassembly only.
1048 // The singleton $opt operand contains the following information:
1049 // opt{4-0} = mode from Inst{4-0}
1050 // opt{5} = changemode from Inst{17}
1051 // opt{8-6} = AIF from Inst{8-6}
1052 // opt{10-9} = imod from Inst{19-18} with 0b10 as enable and 0b11 as disable
1053 // FIXME: Integrated assembler will need these split out.
1054 def CPS : AXI<(outs), (ins cps_opt:$opt), MiscFrm, NoItinerary, "cps$opt",
1055 [/* For disassembly only; pattern left blank */]>,
1057 let Inst{31-28} = 0b1111;
1058 let Inst{27-20} = 0b00010000;
1063 // Preload signals the memory system of possible future data/instruction access.
1064 // These are for disassembly only.
1065 multiclass APreLoad<bits<1> read, bits<1> data, string opc> {
1067 def i12 : AXI<(outs), (ins addrmode_imm12:$addr), MiscFrm, IIC_Preload,
1068 !strconcat(opc, "\t$addr"),
1069 [(ARMPreload addrmode_imm12:$addr, (i32 read), (i32 data))]> {
1072 let Inst{31-26} = 0b111101;
1073 let Inst{25} = 0; // 0 for immediate form
1074 let Inst{24} = data;
1075 let Inst{23} = addr{12}; // U (add = ('U' == 1))
1076 let Inst{22} = read;
1077 let Inst{21-20} = 0b01;
1078 let Inst{19-16} = addr{16-13}; // Rn
1079 let Inst{15-12} = Rt;
1080 let Inst{11-0} = addr{11-0}; // imm12
1083 def rs : AXI<(outs), (ins ldst_so_reg:$shift), MiscFrm, IIC_Preload,
1084 !strconcat(opc, "\t$shift"),
1085 [(ARMPreload ldst_so_reg:$shift, (i32 read), (i32 data))]> {
1088 let Inst{31-26} = 0b111101;
1089 let Inst{25} = 1; // 1 for register form
1090 let Inst{24} = data;
1091 let Inst{23} = shift{12}; // U (add = ('U' == 1))
1092 let Inst{22} = read;
1093 let Inst{21-20} = 0b01;
1094 let Inst{19-16} = shift{16-13}; // Rn
1095 let Inst{11-0} = shift{11-0};
1099 defm PLD : APreLoad<1, 1, "pld">, Requires<[IsARM]>;
1100 defm PLDW : APreLoad<0, 1, "pldw">, Requires<[IsARM,HasV7,HasMP]>;
1101 defm PLI : APreLoad<1, 0, "pli">, Requires<[IsARM,HasV7]>;
1103 def SETEND : AXI<(outs),(ins setend_op:$end), MiscFrm, NoItinerary,
1105 [/* For disassembly only; pattern left blank */]>,
1108 let Inst{31-10} = 0b1111000100000001000000;
1113 def DBG : AI<(outs), (ins i32imm:$opt), MiscFrm, NoItinerary, "dbg", "\t$opt",
1114 [/* For disassembly only; pattern left blank */]>,
1115 Requires<[IsARM, HasV7]> {
1117 let Inst{27-4} = 0b001100100000111100001111;
1118 let Inst{3-0} = opt;
1121 // A5.4 Permanently UNDEFINED instructions.
1122 let isBarrier = 1, isTerminator = 1 in
1123 def TRAP : AXI<(outs), (ins), MiscFrm, NoItinerary,
1126 let Inst = 0xe7ffdefe;
1129 // Address computation and loads and stores in PIC mode.
1130 let isNotDuplicable = 1 in {
1131 def PICADD : ARMPseudoInst<(outs GPR:$dst), (ins GPR:$a, pclabel:$cp, pred:$p),
1133 [(set GPR:$dst, (ARMpic_add GPR:$a, imm:$cp))]>;
1135 let AddedComplexity = 10 in {
1136 def PICLDR : ARMPseudoInst<(outs GPR:$dst), (ins addrmodepc:$addr, pred:$p),
1138 [(set GPR:$dst, (load addrmodepc:$addr))]>;
1140 def PICLDRH : ARMPseudoInst<(outs GPR:$Rt), (ins addrmodepc:$addr, pred:$p),
1142 [(set GPR:$Rt, (zextloadi16 addrmodepc:$addr))]>;
1144 def PICLDRB : ARMPseudoInst<(outs GPR:$Rt), (ins addrmodepc:$addr, pred:$p),
1146 [(set GPR:$Rt, (zextloadi8 addrmodepc:$addr))]>;
1148 def PICLDRSH : ARMPseudoInst<(outs GPR:$Rt), (ins addrmodepc:$addr, pred:$p),
1150 [(set GPR:$Rt, (sextloadi16 addrmodepc:$addr))]>;
1152 def PICLDRSB : ARMPseudoInst<(outs GPR:$Rt), (ins addrmodepc:$addr, pred:$p),
1154 [(set GPR:$Rt, (sextloadi8 addrmodepc:$addr))]>;
1156 let AddedComplexity = 10 in {
1157 def PICSTR : ARMPseudoInst<(outs), (ins GPR:$src, addrmodepc:$addr, pred:$p),
1158 IIC_iStore_r, [(store GPR:$src, addrmodepc:$addr)]>;
1160 def PICSTRH : ARMPseudoInst<(outs), (ins GPR:$src, addrmodepc:$addr, pred:$p),
1161 IIC_iStore_bh_r, [(truncstorei16 GPR:$src, addrmodepc:$addr)]>;
1163 def PICSTRB : ARMPseudoInst<(outs), (ins GPR:$src, addrmodepc:$addr, pred:$p),
1164 IIC_iStore_bh_r, [(truncstorei8 GPR:$src, addrmodepc:$addr)]>;
1166 } // isNotDuplicable = 1
1169 // LEApcrel - Load a pc-relative address into a register without offending the
1171 let neverHasSideEffects = 1 in {
1172 let isReMaterializable = 1 in
1173 // FIXME: We want one cannonical LEApcrel instruction and to express one or
1174 // both of these as pseudo-instructions that get expanded to it.
1175 def LEApcrel : AXI1<0, (outs GPR:$Rd), (ins i32imm:$label, pred:$p),
1177 "adr$p\t$Rd, #$label", []>;
1179 } // neverHasSideEffects
1180 def LEApcrelJT : AXI1<0b0100, (outs GPR:$Rd),
1181 (ins i32imm:$label, nohash_imm:$id, pred:$p),
1183 "adr$p\t$Rd, #${label}_${id}", []> {
1186 let Inst{31-28} = p;
1187 let Inst{27-25} = 0b001;
1189 let Inst{19-16} = 0b1111;
1190 let Inst{15-12} = Rd;
1191 // FIXME: Add label encoding/fixup
1194 //===----------------------------------------------------------------------===//
1195 // Control Flow Instructions.
1198 let isReturn = 1, isTerminator = 1, isBarrier = 1 in {
1200 def BX_RET : AI<(outs), (ins), BrMiscFrm, IIC_Br,
1201 "bx", "\tlr", [(ARMretflag)]>,
1202 Requires<[IsARM, HasV4T]> {
1203 let Inst{27-0} = 0b0001001011111111111100011110;
1207 def MOVPCLR : AI<(outs), (ins), BrMiscFrm, IIC_Br,
1208 "mov", "\tpc, lr", [(ARMretflag)]>,
1209 Requires<[IsARM, NoV4T]> {
1210 let Inst{27-0} = 0b0001101000001111000000001110;
1214 // Indirect branches
1215 let isBranch = 1, isTerminator = 1, isBarrier = 1, isIndirectBranch = 1 in {
1217 def BRIND : AXI<(outs), (ins GPR:$dst), BrMiscFrm, IIC_Br, "bx\t$dst",
1218 [(brind GPR:$dst)]>,
1219 Requires<[IsARM, HasV4T]> {
1221 let Inst{31-4} = 0b1110000100101111111111110001;
1222 let Inst{3-0} = dst;
1226 def MOVPCRX : AXI<(outs), (ins GPR:$dst), BrMiscFrm, IIC_Br, "mov\tpc, $dst",
1227 [(brind GPR:$dst)]>,
1228 Requires<[IsARM, NoV4T]> {
1230 let Inst{31-4} = 0b1110000110100000111100000000;
1231 let Inst{3-0} = dst;
1235 // On non-Darwin platforms R9 is callee-saved.
1237 Defs = [R0, R1, R2, R3, R12, LR,
1238 D0, D1, D2, D3, D4, D5, D6, D7,
1239 D16, D17, D18, D19, D20, D21, D22, D23,
1240 D24, D25, D26, D27, D28, D29, D30, D31, CPSR, FPSCR] in {
1241 def BL : ABXI<0b1011, (outs), (ins bltarget:$func, variable_ops),
1242 IIC_Br, "bl\t$func",
1243 [(ARMcall tglobaladdr:$func)]>,
1244 Requires<[IsARM, IsNotDarwin]> {
1245 let Inst{31-28} = 0b1110;
1247 let Inst{23-0} = func;
1250 def BL_pred : ABI<0b1011, (outs), (ins bltarget:$func, variable_ops),
1251 IIC_Br, "bl", "\t$func",
1252 [(ARMcall_pred tglobaladdr:$func)]>,
1253 Requires<[IsARM, IsNotDarwin]> {
1255 let Inst{23-0} = func;
1259 def BLX : AXI<(outs), (ins GPR:$func, variable_ops), BrMiscFrm,
1260 IIC_Br, "blx\t$func",
1261 [(ARMcall GPR:$func)]>,
1262 Requires<[IsARM, HasV5T, IsNotDarwin]> {
1264 let Inst{31-4} = 0b1110000100101111111111110011;
1265 let Inst{3-0} = func;
1269 // Note: Restrict $func to the tGPR regclass to prevent it being in LR.
1270 // FIXME: x2 insn patterns like this need to be pseudo instructions.
1271 def BX : ABXIx2<(outs), (ins tGPR:$func, variable_ops),
1272 IIC_Br, "mov\tlr, pc\n\tbx\t$func",
1273 [(ARMcall_nolink tGPR:$func)]>,
1274 Requires<[IsARM, HasV4T, IsNotDarwin]> {
1276 let Inst{27-4} = 0b000100101111111111110001;
1277 let Inst{3-0} = func;
1281 def BMOVPCRX : ABXIx2<(outs), (ins tGPR:$func, variable_ops),
1282 IIC_Br, "mov\tlr, pc\n\tmov\tpc, $func",
1283 [(ARMcall_nolink tGPR:$func)]>,
1284 Requires<[IsARM, NoV4T, IsNotDarwin]> {
1286 let Inst{27-4} = 0b000110100000111100000000;
1287 let Inst{3-0} = func;
1291 // On Darwin R9 is call-clobbered.
1293 Defs = [R0, R1, R2, R3, R9, R12, LR,
1294 D0, D1, D2, D3, D4, D5, D6, D7,
1295 D16, D17, D18, D19, D20, D21, D22, D23,
1296 D24, D25, D26, D27, D28, D29, D30, D31, CPSR, FPSCR] in {
1297 def BLr9 : ABXI<0b1011, (outs), (ins bltarget:$func, variable_ops),
1298 IIC_Br, "bl\t$func",
1299 [(ARMcall tglobaladdr:$func)]>, Requires<[IsARM, IsDarwin]> {
1300 let Inst{31-28} = 0b1110;
1302 let Inst{23-0} = func;
1305 def BLr9_pred : ABI<0b1011, (outs), (ins bltarget:$func, variable_ops),
1306 IIC_Br, "bl", "\t$func",
1307 [(ARMcall_pred tglobaladdr:$func)]>,
1308 Requires<[IsARM, IsDarwin]> {
1310 let Inst{23-0} = func;
1314 def BLXr9 : AXI<(outs), (ins GPR:$func, variable_ops), BrMiscFrm,
1315 IIC_Br, "blx\t$func",
1316 [(ARMcall GPR:$func)]>, Requires<[IsARM, HasV5T, IsDarwin]> {
1318 let Inst{31-4} = 0b1110000100101111111111110011;
1319 let Inst{3-0} = func;
1323 // Note: Restrict $func to the tGPR regclass to prevent it being in LR.
1324 def BXr9 : ABXIx2<(outs), (ins tGPR:$func, variable_ops),
1325 IIC_Br, "mov\tlr, pc\n\tbx\t$func",
1326 [(ARMcall_nolink tGPR:$func)]>,
1327 Requires<[IsARM, HasV4T, IsDarwin]> {
1329 let Inst{27-4} = 0b000100101111111111110001;
1330 let Inst{3-0} = func;
1334 def BMOVPCRXr9 : ABXIx2<(outs), (ins tGPR:$func, variable_ops),
1335 IIC_Br, "mov\tlr, pc\n\tmov\tpc, $func",
1336 [(ARMcall_nolink tGPR:$func)]>,
1337 Requires<[IsARM, NoV4T, IsDarwin]> {
1339 let Inst{27-4} = 0b000110100000111100000000;
1340 let Inst{3-0} = func;
1346 // FIXME: These should probably be xformed into the non-TC versions of the
1347 // instructions as part of MC lowering.
1348 let isCall = 1, isTerminator = 1, isReturn = 1, isBarrier = 1 in {
1350 let Defs = [R0, R1, R2, R3, R9, R12,
1351 D0, D1, D2, D3, D4, D5, D6, D7,
1352 D16, D17, D18, D19, D20, D21, D22, D23, D24, D25, D26,
1353 D27, D28, D29, D30, D31, PC],
1355 def TCRETURNdi : AInoP<(outs), (ins i32imm:$dst, variable_ops),
1357 "@TC_RETURN","\t$dst", []>, Requires<[IsDarwin]>;
1359 def TCRETURNri : AInoP<(outs), (ins tcGPR:$dst, variable_ops),
1361 "@TC_RETURN","\t$dst", []>, Requires<[IsDarwin]>;
1363 def TAILJMPd : ABXI<0b1010, (outs), (ins brtarget:$dst, variable_ops),
1364 IIC_Br, "b\t$dst @ TAILCALL",
1365 []>, Requires<[IsDarwin]>;
1367 def TAILJMPdt: ABXI<0b1010, (outs), (ins brtarget:$dst, variable_ops),
1368 IIC_Br, "b.w\t$dst @ TAILCALL",
1369 []>, Requires<[IsDarwin]>;
1371 def TAILJMPr : AXI<(outs), (ins tcGPR:$dst, variable_ops),
1372 BrMiscFrm, IIC_Br, "bx\t$dst @ TAILCALL",
1373 []>, Requires<[IsDarwin]> {
1375 let Inst{31-4} = 0b1110000100101111111111110001;
1376 let Inst{3-0} = dst;
1380 // Non-Darwin versions (the difference is R9).
1381 let Defs = [R0, R1, R2, R3, R12,
1382 D0, D1, D2, D3, D4, D5, D6, D7,
1383 D16, D17, D18, D19, D20, D21, D22, D23, D24, D25, D26,
1384 D27, D28, D29, D30, D31, PC],
1386 def TCRETURNdiND : AInoP<(outs), (ins i32imm:$dst, variable_ops),
1388 "@TC_RETURN","\t$dst", []>, Requires<[IsNotDarwin]>;
1390 def TCRETURNriND : AInoP<(outs), (ins tcGPR:$dst, variable_ops),
1392 "@TC_RETURN","\t$dst", []>, Requires<[IsNotDarwin]>;
1394 def TAILJMPdND : ABXI<0b1010, (outs), (ins brtarget:$dst, variable_ops),
1395 IIC_Br, "b\t$dst @ TAILCALL",
1396 []>, Requires<[IsARM, IsNotDarwin]>;
1398 def TAILJMPdNDt : ABXI<0b1010, (outs), (ins brtarget:$dst, variable_ops),
1399 IIC_Br, "b.w\t$dst @ TAILCALL",
1400 []>, Requires<[IsThumb, IsNotDarwin]>;
1402 def TAILJMPrND : AXI<(outs), (ins tcGPR:$dst, variable_ops),
1403 BrMiscFrm, IIC_Br, "bx\t$dst @ TAILCALL",
1404 []>, Requires<[IsNotDarwin]> {
1406 let Inst{31-4} = 0b1110000100101111111111110001;
1407 let Inst{3-0} = dst;
1412 let isBranch = 1, isTerminator = 1 in {
1413 // B is "predicable" since it can be xformed into a Bcc.
1414 let isBarrier = 1 in {
1415 let isPredicable = 1 in
1416 def B : ABXI<0b1010, (outs), (ins brtarget:$target), IIC_Br,
1417 "b\t$target", [(br bb:$target)]> {
1419 let Inst{31-28} = 0b1110;
1420 let Inst{23-0} = target;
1423 let isNotDuplicable = 1, isIndirectBranch = 1 in {
1424 def BR_JTr : ARMPseudoInst<(outs),
1425 (ins GPR:$target, i32imm:$jt, i32imm:$id),
1427 [(ARMbrjt GPR:$target, tjumptable:$jt, imm:$id)]> {
1428 let SZ = SizeSpecial;
1430 // FIXME: This shouldn't use the generic "addrmode2," but rather be split
1431 // into i12 and rs suffixed versions.
1432 def BR_JTm : ARMPseudoInst<(outs),
1433 (ins addrmode2:$target, i32imm:$jt, i32imm:$id),
1435 [(ARMbrjt (i32 (load addrmode2:$target)), tjumptable:$jt,
1437 let SZ = SizeSpecial;
1439 def BR_JTadd : ARMPseudoInst<(outs),
1440 (ins GPR:$target, GPR:$idx, i32imm:$jt, i32imm:$id),
1442 [(ARMbrjt (add GPR:$target, GPR:$idx), tjumptable:$jt,
1444 let SZ = SizeSpecial;
1446 } // isNotDuplicable = 1, isIndirectBranch = 1
1449 // FIXME: should be able to write a pattern for ARMBrcond, but can't use
1450 // a two-value operand where a dag node expects two operands. :(
1451 def Bcc : ABI<0b1010, (outs), (ins brtarget:$target),
1452 IIC_Br, "b", "\t$target",
1453 [/*(ARMbrcond bb:$target, imm:$cc, CCR:$ccr)*/]> {
1455 let Inst{23-0} = target;
1459 // Branch and Exchange Jazelle -- for disassembly only
1460 def BXJ : ABI<0b0001, (outs), (ins GPR:$func), NoItinerary, "bxj", "\t$func",
1461 [/* For disassembly only; pattern left blank */]> {
1462 let Inst{23-20} = 0b0010;
1463 //let Inst{19-8} = 0xfff;
1464 let Inst{7-4} = 0b0010;
1467 // Secure Monitor Call is a system instruction -- for disassembly only
1468 def SMC : ABI<0b0001, (outs), (ins i32imm:$opt), NoItinerary, "smc", "\t$opt",
1469 [/* For disassembly only; pattern left blank */]> {
1471 let Inst{23-4} = 0b01100000000000000111;
1472 let Inst{3-0} = opt;
1475 // Supervisor Call (Software Interrupt) -- for disassembly only
1477 def SVC : ABI<0b1111, (outs), (ins i32imm:$svc), IIC_Br, "svc", "\t$svc",
1478 [/* For disassembly only; pattern left blank */]> {
1480 let Inst{23-0} = svc;
1484 // Store Return State is a system instruction -- for disassembly only
1485 let isCodeGenOnly = 1 in { // FIXME: This should not use submode!
1486 def SRSW : ABXI<{1,0,0,?}, (outs), (ins ldstm_mode:$amode, i32imm:$mode),
1487 NoItinerary, "srs${amode}\tsp!, $mode",
1488 [/* For disassembly only; pattern left blank */]> {
1489 let Inst{31-28} = 0b1111;
1490 let Inst{22-20} = 0b110; // W = 1
1493 def SRS : ABXI<{1,0,0,?}, (outs), (ins ldstm_mode:$amode, i32imm:$mode),
1494 NoItinerary, "srs${amode}\tsp, $mode",
1495 [/* For disassembly only; pattern left blank */]> {
1496 let Inst{31-28} = 0b1111;
1497 let Inst{22-20} = 0b100; // W = 0
1500 // Return From Exception is a system instruction -- for disassembly only
1501 def RFEW : ABXI<{1,0,0,?}, (outs), (ins ldstm_mode:$amode, GPR:$base),
1502 NoItinerary, "rfe${amode}\t$base!",
1503 [/* For disassembly only; pattern left blank */]> {
1504 let Inst{31-28} = 0b1111;
1505 let Inst{22-20} = 0b011; // W = 1
1508 def RFE : ABXI<{1,0,0,?}, (outs), (ins ldstm_mode:$amode, GPR:$base),
1509 NoItinerary, "rfe${amode}\t$base",
1510 [/* For disassembly only; pattern left blank */]> {
1511 let Inst{31-28} = 0b1111;
1512 let Inst{22-20} = 0b001; // W = 0
1514 } // isCodeGenOnly = 1
1516 //===----------------------------------------------------------------------===//
1517 // Load / store Instructions.
1523 defm LDR : AI_ldr1<0, "ldr", IIC_iLoad_r, IIC_iLoad_si,
1524 UnOpFrag<(load node:$Src)>>;
1525 defm LDRB : AI_ldr1<1, "ldrb", IIC_iLoad_bh_r, IIC_iLoad_bh_si,
1526 UnOpFrag<(zextloadi8 node:$Src)>>;
1527 defm STR : AI_str1<0, "str", IIC_iStore_r, IIC_iStore_si,
1528 BinOpFrag<(store node:$LHS, node:$RHS)>>;
1529 defm STRB : AI_str1<1, "strb", IIC_iStore_bh_r, IIC_iStore_bh_si,
1530 BinOpFrag<(truncstorei8 node:$LHS, node:$RHS)>>;
1532 // Special LDR for loads from non-pc-relative constpools.
1533 let canFoldAsLoad = 1, mayLoad = 1, neverHasSideEffects = 1,
1534 isReMaterializable = 1 in
1535 def LDRcp : AI2ldst<0b010, 1, 0, (outs GPR:$Rt), (ins addrmode_imm12:$addr),
1536 AddrMode_i12, LdFrm, IIC_iLoad_r, "ldr", "\t$Rt, $addr",
1540 let Inst{23} = addr{12}; // U (add = ('U' == 1))
1541 let Inst{19-16} = 0b1111;
1542 let Inst{15-12} = Rt;
1543 let Inst{11-0} = addr{11-0}; // imm12
1546 // Loads with zero extension
1547 def LDRH : AI3ld<0b1011, 1, (outs GPR:$Rt), (ins addrmode3:$addr), LdMiscFrm,
1548 IIC_iLoad_bh_r, "ldrh", "\t$Rt, $addr",
1549 [(set GPR:$Rt, (zextloadi16 addrmode3:$addr))]>;
1551 // Loads with sign extension
1552 def LDRSH : AI3ld<0b1111, 1, (outs GPR:$Rt), (ins addrmode3:$addr), LdMiscFrm,
1553 IIC_iLoad_bh_r, "ldrsh", "\t$Rt, $addr",
1554 [(set GPR:$Rt, (sextloadi16 addrmode3:$addr))]>;
1556 def LDRSB : AI3ld<0b1101, 1, (outs GPR:$Rt), (ins addrmode3:$addr), LdMiscFrm,
1557 IIC_iLoad_bh_r, "ldrsb", "\t$Rt, $addr",
1558 [(set GPR:$Rt, (sextloadi8 addrmode3:$addr))]>;
1560 let mayLoad = 1, neverHasSideEffects = 1, hasExtraDefRegAllocReq = 1,
1561 isCodeGenOnly = 1 in { // $dst2 doesn't exist in asmstring?
1562 // FIXME: $dst2 isn't in the asm string as it's implied by $Rd (dst2 = Rd+1)
1563 // how to represent that such that tblgen is happy and we don't
1564 // mark this codegen only?
1566 def LDRD : AI3ld<0b1101, 0, (outs GPR:$Rd, GPR:$dst2),
1567 (ins addrmode3:$addr), LdMiscFrm,
1568 IIC_iLoad_d_r, "ldrd", "\t$Rd, $addr",
1569 []>, Requires<[IsARM, HasV5TE]>;
1573 multiclass AI2_ldridx<bit isByte, string opc, InstrItinClass itin> {
1574 def _PRE : AI2ldstidx<1, isByte, 1, (outs GPR:$Rt, GPR:$Rn_wb),
1575 (ins addrmode2:$addr), IndexModePre, LdFrm, itin,
1576 opc, "\t$Rt, $addr!", "$addr.base = $Rn_wb", []> {
1578 // {13} 1 == Rm, 0 == imm12
1582 let Inst{25} = addr{13};
1583 let Inst{23} = addr{12};
1584 let Inst{19-16} = addr{17-14};
1585 let Inst{11-0} = addr{11-0};
1587 def _POST : AI2ldstidx<1, isByte, 0, (outs GPR:$Rt, GPR:$Rn_wb),
1588 (ins GPR:$Rn, am2offset:$offset),
1589 IndexModePost, LdFrm, itin,
1590 opc, "\t$Rt, [$Rn], $offset", "$Rn = $Rn_wb", []> {
1591 // {13} 1 == Rm, 0 == imm12
1596 let Inst{25} = offset{13};
1597 let Inst{23} = offset{12};
1598 let Inst{19-16} = Rn;
1599 let Inst{11-0} = offset{11-0};
1603 let mayLoad = 1, neverHasSideEffects = 1 in {
1604 defm LDR : AI2_ldridx<0, "ldr", IIC_iLoad_ru>;
1605 defm LDRB : AI2_ldridx<1, "ldrb", IIC_iLoad_bh_ru>;
1608 multiclass AI3_ldridx<bits<4> op, bit op20, string opc, InstrItinClass itin> {
1609 def _PRE : AI3ldstidx<op, op20, 1, 1, (outs GPR:$Rt, GPR:$Rn_wb),
1610 (ins addrmode3:$addr), IndexModePre,
1612 opc, "\t$Rt, $addr!", "$addr.base = $Rn_wb", []> {
1614 let Inst{23} = addr{8}; // U bit
1615 let Inst{22} = addr{13}; // 1 == imm8, 0 == Rm
1616 let Inst{19-16} = addr{12-9}; // Rn
1617 let Inst{11-8} = addr{7-4}; // imm7_4/zero
1618 let Inst{3-0} = addr{3-0}; // imm3_0/Rm
1620 def _POST : AI3ldstidx<op, op20, 1, 0, (outs GPR:$Rt, GPR:$Rn_wb),
1621 (ins GPR:$Rn, am3offset:$offset), IndexModePost,
1623 opc, "\t$Rt, [$Rn], $offset", "$Rn = $Rn_wb", []> {
1626 let Inst{23} = offset{8}; // U bit
1627 let Inst{22} = offset{9}; // 1 == imm8, 0 == Rm
1628 let Inst{19-16} = Rn;
1629 let Inst{11-8} = offset{7-4}; // imm7_4/zero
1630 let Inst{3-0} = offset{3-0}; // imm3_0/Rm
1634 let mayLoad = 1, neverHasSideEffects = 1 in {
1635 defm LDRH : AI3_ldridx<0b1011, 1, "ldrh", IIC_iLoad_bh_ru>;
1636 defm LDRSH : AI3_ldridx<0b1111, 1, "ldrsh", IIC_iLoad_bh_ru>;
1637 defm LDRSB : AI3_ldridx<0b1101, 1, "ldrsb", IIC_iLoad_bh_ru>;
1638 let hasExtraDefRegAllocReq = 1, isCodeGenOnly = 1 in
1639 defm LDRD : AI3_ldridx<0b1101, 0, "ldrd", IIC_iLoad_d_ru>;
1640 } // mayLoad = 1, neverHasSideEffects = 1
1642 // LDRT, LDRBT, LDRSBT, LDRHT, LDRSHT are for disassembly only.
1643 let mayLoad = 1, neverHasSideEffects = 1 in {
1644 def LDRT : AI2ldstidx<1, 0, 0, (outs GPR:$dst, GPR:$base_wb),
1645 (ins GPR:$base, am2offset:$offset), IndexModeNone,
1646 LdFrm, IIC_iLoad_ru,
1647 "ldrt", "\t$dst, [$base], $offset", "$base = $base_wb", []> {
1648 let Inst{21} = 1; // overwrite
1650 def LDRBT : AI2ldstidx<1, 1, 0, (outs GPR:$dst, GPR:$base_wb),
1651 (ins GPR:$base, am2offset:$offset), IndexModeNone,
1652 LdFrm, IIC_iLoad_bh_ru,
1653 "ldrbt", "\t$dst, [$base], $offset", "$base = $base_wb", []> {
1654 let Inst{21} = 1; // overwrite
1656 def LDRSBT : AI3ldstidx<0b1101, 1, 1, 0, (outs GPR:$dst, GPR:$base_wb),
1657 (ins GPR:$base, am3offset:$offset), IndexModePost,
1658 LdMiscFrm, IIC_iLoad_bh_ru,
1659 "ldrsbt", "\t$dst, [$base], $offset", "$base = $base_wb", []> {
1660 let Inst{21} = 1; // overwrite
1662 def LDRHT : AI3ldstidx<0b1011, 1, 1, 0, (outs GPR:$dst, GPR:$base_wb),
1663 (ins GPR:$base, am3offset:$offset), IndexModePost,
1664 LdMiscFrm, IIC_iLoad_bh_ru,
1665 "ldrht", "\t$dst, [$base], $offset", "$base = $base_wb", []> {
1666 let Inst{21} = 1; // overwrite
1668 def LDRSHT : AI3ldstidx<0b1111, 1, 1, 0, (outs GPR:$dst, GPR:$base_wb),
1669 (ins GPR:$base, am3offset:$offset), IndexModePost,
1670 LdMiscFrm, IIC_iLoad_bh_ru,
1671 "ldrsht", "\t$dst, [$base], $offset", "$base = $base_wb", []> {
1672 let Inst{21} = 1; // overwrite
1678 // Stores with truncate
1679 def STRH : AI3str<0b1011, (outs), (ins GPR:$Rt, addrmode3:$addr), StMiscFrm,
1680 IIC_iStore_bh_r, "strh", "\t$Rt, $addr",
1681 [(truncstorei16 GPR:$Rt, addrmode3:$addr)]>;
1684 let mayStore = 1, neverHasSideEffects = 1, hasExtraSrcRegAllocReq = 1,
1685 isCodeGenOnly = 1 in // $src2 doesn't exist in asm string
1686 def STRD : AI3str<0b1111, (outs), (ins GPR:$src1, GPR:$src2, addrmode3:$addr),
1687 StMiscFrm, IIC_iStore_d_r,
1688 "strd", "\t$src1, $addr", []>, Requires<[IsARM, HasV5TE]>;
1691 def STR_PRE : AI2stridx<0, 1, (outs GPR:$Rn_wb),
1692 (ins GPR:$Rt, GPR:$Rn, am2offset:$offset),
1693 IndexModePre, StFrm, IIC_iStore_ru,
1694 "str", "\t$Rt, [$Rn, $offset]!", "$Rn = $Rn_wb",
1696 (pre_store GPR:$Rt, GPR:$Rn, am2offset:$offset))]>;
1698 def STR_POST : AI2stridx<0, 0, (outs GPR:$Rn_wb),
1699 (ins GPR:$Rt, GPR:$Rn, am2offset:$offset),
1700 IndexModePost, StFrm, IIC_iStore_ru,
1701 "str", "\t$Rt, [$Rn], $offset", "$Rn = $Rn_wb",
1703 (post_store GPR:$Rt, GPR:$Rn, am2offset:$offset))]>;
1705 def STRB_PRE : AI2stridx<1, 1, (outs GPR:$Rn_wb),
1706 (ins GPR:$Rt, GPR:$Rn, am2offset:$offset),
1707 IndexModePre, StFrm, IIC_iStore_bh_ru,
1708 "strb", "\t$Rt, [$Rn, $offset]!", "$Rn = $Rn_wb",
1709 [(set GPR:$Rn_wb, (pre_truncsti8 GPR:$Rt,
1710 GPR:$Rn, am2offset:$offset))]>;
1711 def STRB_POST: AI2stridx<1, 0, (outs GPR:$Rn_wb),
1712 (ins GPR:$Rt, GPR:$Rn, am2offset:$offset),
1713 IndexModePost, StFrm, IIC_iStore_bh_ru,
1714 "strb", "\t$Rt, [$Rn], $offset", "$Rn = $Rn_wb",
1715 [(set GPR:$Rn_wb, (post_truncsti8 GPR:$Rt,
1716 GPR:$Rn, am2offset:$offset))]>;
1718 def STRH_PRE : AI3stridx<0b1011, 0, 1, (outs GPR:$Rn_wb),
1719 (ins GPR:$Rt, GPR:$Rn, am3offset:$offset),
1720 IndexModePre, StMiscFrm, IIC_iStore_ru,
1721 "strh", "\t$Rt, [$Rn, $offset]!", "$Rn = $Rn_wb",
1723 (pre_truncsti16 GPR:$Rt, GPR:$Rn, am3offset:$offset))]>;
1725 def STRH_POST: AI3stridx<0b1011, 0, 0, (outs GPR:$Rn_wb),
1726 (ins GPR:$Rt, GPR:$Rn, am3offset:$offset),
1727 IndexModePost, StMiscFrm, IIC_iStore_bh_ru,
1728 "strh", "\t$Rt, [$Rn], $offset", "$Rn = $Rn_wb",
1729 [(set GPR:$Rn_wb, (post_truncsti16 GPR:$Rt,
1730 GPR:$Rn, am3offset:$offset))]>;
1732 // For disassembly only
1733 def STRD_PRE : AI3stdpr<(outs GPR:$base_wb),
1734 (ins GPR:$src1, GPR:$src2, GPR:$base, am3offset:$offset),
1735 StMiscFrm, IIC_iStore_d_ru,
1736 "strd", "\t$src1, $src2, [$base, $offset]!",
1737 "$base = $base_wb", []>;
1739 // For disassembly only
1740 def STRD_POST: AI3stdpo<(outs GPR:$base_wb),
1741 (ins GPR:$src1, GPR:$src2, GPR:$base, am3offset:$offset),
1742 StMiscFrm, IIC_iStore_d_ru,
1743 "strd", "\t$src1, $src2, [$base], $offset",
1744 "$base = $base_wb", []>;
1746 // STRT, STRBT, and STRHT are for disassembly only.
1748 def STRT : AI2stridx<0, 0, (outs GPR:$Rn_wb),
1749 (ins GPR:$Rt, GPR:$Rn,am2offset:$offset),
1750 IndexModeNone, StFrm, IIC_iStore_ru,
1751 "strt", "\t$Rt, [$Rn], $offset", "$Rn = $Rn_wb",
1752 [/* For disassembly only; pattern left blank */]> {
1753 let Inst{21} = 1; // overwrite
1756 def STRBT : AI2stridx<1, 0, (outs GPR:$Rn_wb),
1757 (ins GPR:$Rt, GPR:$Rn, am2offset:$offset),
1758 IndexModeNone, StFrm, IIC_iStore_bh_ru,
1759 "strbt", "\t$Rt, [$Rn], $offset", "$Rn = $Rn_wb",
1760 [/* For disassembly only; pattern left blank */]> {
1761 let Inst{21} = 1; // overwrite
1764 def STRHT: AI3sthpo<(outs GPR:$base_wb),
1765 (ins GPR:$src, GPR:$base,am3offset:$offset),
1766 StMiscFrm, IIC_iStore_bh_ru,
1767 "strht", "\t$src, [$base], $offset", "$base = $base_wb",
1768 [/* For disassembly only; pattern left blank */]> {
1769 let Inst{21} = 1; // overwrite
1772 //===----------------------------------------------------------------------===//
1773 // Load / store multiple Instructions.
1776 multiclass arm_ldst_mult<string asm, bit L_bit, Format f,
1777 InstrItinClass itin, InstrItinClass itin_upd> {
1779 AXI4<(outs), (ins GPR:$Rn, pred:$p, reglist:$regs, variable_ops),
1780 IndexModeNone, f, itin,
1781 !strconcat(asm, "ia${p}\t$Rn, $regs"), "", []> {
1782 let Inst{24-23} = 0b01; // Increment After
1783 let Inst{21} = 0; // No writeback
1784 let Inst{20} = L_bit;
1787 AXI4<(outs GPR:$wb), (ins GPR:$Rn, pred:$p, reglist:$regs, variable_ops),
1788 IndexModeUpd, f, itin_upd,
1789 !strconcat(asm, "ia${p}\t$Rn!, $regs"), "$Rn = $wb", []> {
1790 let Inst{24-23} = 0b01; // Increment After
1791 let Inst{21} = 1; // Writeback
1792 let Inst{20} = L_bit;
1795 AXI4<(outs), (ins GPR:$Rn, pred:$p, reglist:$regs, variable_ops),
1796 IndexModeNone, f, itin,
1797 !strconcat(asm, "da${p}\t$Rn, $regs"), "", []> {
1798 let Inst{24-23} = 0b00; // Decrement After
1799 let Inst{21} = 0; // No writeback
1800 let Inst{20} = L_bit;
1803 AXI4<(outs GPR:$wb), (ins GPR:$Rn, pred:$p, reglist:$regs, variable_ops),
1804 IndexModeUpd, f, itin_upd,
1805 !strconcat(asm, "da${p}\t$Rn!, $regs"), "$Rn = $wb", []> {
1806 let Inst{24-23} = 0b00; // Decrement After
1807 let Inst{21} = 1; // Writeback
1808 let Inst{20} = L_bit;
1811 AXI4<(outs), (ins GPR:$Rn, pred:$p, reglist:$regs, variable_ops),
1812 IndexModeNone, f, itin,
1813 !strconcat(asm, "db${p}\t$Rn, $regs"), "", []> {
1814 let Inst{24-23} = 0b10; // Decrement Before
1815 let Inst{21} = 0; // No writeback
1816 let Inst{20} = L_bit;
1819 AXI4<(outs GPR:$wb), (ins GPR:$Rn, pred:$p, reglist:$regs, variable_ops),
1820 IndexModeUpd, f, itin_upd,
1821 !strconcat(asm, "db${p}\t$Rn!, $regs"), "$Rn = $wb", []> {
1822 let Inst{24-23} = 0b10; // Decrement Before
1823 let Inst{21} = 1; // Writeback
1824 let Inst{20} = L_bit;
1827 AXI4<(outs), (ins GPR:$Rn, pred:$p, reglist:$regs, variable_ops),
1828 IndexModeNone, f, itin,
1829 !strconcat(asm, "ib${p}\t$Rn, $regs"), "", []> {
1830 let Inst{24-23} = 0b11; // Increment Before
1831 let Inst{21} = 0; // No writeback
1832 let Inst{20} = L_bit;
1835 AXI4<(outs GPR:$wb), (ins GPR:$Rn, pred:$p, reglist:$regs, variable_ops),
1836 IndexModeUpd, f, itin_upd,
1837 !strconcat(asm, "ib${p}\t$Rn!, $regs"), "$Rn = $wb", []> {
1838 let Inst{24-23} = 0b11; // Increment Before
1839 let Inst{21} = 1; // Writeback
1840 let Inst{20} = L_bit;
1844 let neverHasSideEffects = 1 in {
1846 let mayLoad = 1, hasExtraDefRegAllocReq = 1 in
1847 defm LDM : arm_ldst_mult<"ldm", 1, LdStMulFrm, IIC_iLoad_m, IIC_iLoad_mu>;
1849 let mayStore = 1, hasExtraSrcRegAllocReq = 1 in
1850 defm STM : arm_ldst_mult<"stm", 0, LdStMulFrm, IIC_iStore_m, IIC_iStore_mu>;
1852 } // neverHasSideEffects
1854 // Load / Store Multiple Mnemnoic Aliases
1855 def : MnemonicAlias<"ldm", "ldmia">;
1856 def : MnemonicAlias<"stm", "stmia">;
1858 // FIXME: remove when we have a way to marking a MI with these properties.
1859 // FIXME: Should pc be an implicit operand like PICADD, etc?
1860 let isReturn = 1, isTerminator = 1, isBarrier = 1, mayLoad = 1,
1861 hasExtraDefRegAllocReq = 1, isCodeGenOnly = 1 in
1862 def LDMIA_RET : AXI4<(outs GPR:$wb), (ins GPR:$Rn, pred:$p,
1863 reglist:$regs, variable_ops),
1864 IndexModeUpd, LdStMulFrm, IIC_iLoad_mBr,
1865 "ldmia${p}\t$Rn!, $regs",
1867 let Inst{24-23} = 0b01; // Increment After
1868 let Inst{21} = 1; // Writeback
1869 let Inst{20} = 1; // Load
1872 //===----------------------------------------------------------------------===//
1873 // Move Instructions.
1876 let neverHasSideEffects = 1 in
1877 def MOVr : AsI1<0b1101, (outs GPR:$Rd), (ins GPR:$Rm), DPFrm, IIC_iMOVr,
1878 "mov", "\t$Rd, $Rm", []>, UnaryDP {
1882 let Inst{11-4} = 0b00000000;
1885 let Inst{15-12} = Rd;
1888 // A version for the smaller set of tail call registers.
1889 let neverHasSideEffects = 1 in
1890 def MOVr_TC : AsI1<0b1101, (outs tcGPR:$Rd), (ins tcGPR:$Rm), DPFrm,
1891 IIC_iMOVr, "mov", "\t$Rd, $Rm", []>, UnaryDP {
1895 let Inst{11-4} = 0b00000000;
1898 let Inst{15-12} = Rd;
1901 def MOVs : AsI1<0b1101, (outs GPR:$Rd), (ins shift_so_reg:$src),
1902 DPSoRegFrm, IIC_iMOVsr,
1903 "mov", "\t$Rd, $src", [(set GPR:$Rd, shift_so_reg:$src)]>,
1907 let Inst{15-12} = Rd;
1908 let Inst{11-0} = src;
1912 let isReMaterializable = 1, isAsCheapAsAMove = 1, isMoveImm = 1 in
1913 def MOVi : AsI1<0b1101, (outs GPR:$Rd), (ins so_imm:$imm), DPFrm, IIC_iMOVi,
1914 "mov", "\t$Rd, $imm", [(set GPR:$Rd, so_imm:$imm)]>, UnaryDP {
1918 let Inst{15-12} = Rd;
1919 let Inst{19-16} = 0b0000;
1920 let Inst{11-0} = imm;
1923 let isReMaterializable = 1, isAsCheapAsAMove = 1, isMoveImm = 1 in
1924 def MOVi16 : AI1<0b1000, (outs GPR:$Rd), (ins movt_imm:$imm),
1926 "movw", "\t$Rd, $imm",
1927 [(set GPR:$Rd, imm0_65535:$imm)]>,
1928 Requires<[IsARM, HasV6T2]>, UnaryDP {
1931 let Inst{15-12} = Rd;
1932 let Inst{11-0} = imm{11-0};
1933 let Inst{19-16} = imm{15-12};
1938 let Constraints = "$src = $Rd" in
1939 def MOVTi16 : AI1<0b1010, (outs GPR:$Rd), (ins GPR:$src, movt_imm:$imm),
1941 "movt", "\t$Rd, $imm",
1943 (or (and GPR:$src, 0xffff),
1944 lo16AllZero:$imm))]>, UnaryDP,
1945 Requires<[IsARM, HasV6T2]> {
1948 let Inst{15-12} = Rd;
1949 let Inst{11-0} = imm{11-0};
1950 let Inst{19-16} = imm{15-12};
1955 def : ARMPat<(or GPR:$src, 0xffff0000), (MOVTi16 GPR:$src, 0xffff)>,
1956 Requires<[IsARM, HasV6T2]>;
1958 let Uses = [CPSR] in
1959 def RRX: PseudoInst<(outs GPR:$Rd), (ins GPR:$Rm), IIC_iMOVsi,
1960 [(set GPR:$Rd, (ARMrrx GPR:$Rm))]>, UnaryDP,
1963 // These aren't really mov instructions, but we have to define them this way
1964 // due to flag operands.
1966 let Defs = [CPSR] in {
1967 def MOVsrl_flag : PseudoInst<(outs GPR:$dst), (ins GPR:$src), IIC_iMOVsi,
1968 [(set GPR:$dst, (ARMsrl_flag GPR:$src))]>, UnaryDP,
1970 def MOVsra_flag : PseudoInst<(outs GPR:$dst), (ins GPR:$src), IIC_iMOVsi,
1971 [(set GPR:$dst, (ARMsra_flag GPR:$src))]>, UnaryDP,
1975 //===----------------------------------------------------------------------===//
1976 // Extend Instructions.
1981 defm SXTB : AI_ext_rrot<0b01101010,
1982 "sxtb", UnOpFrag<(sext_inreg node:$Src, i8)>>;
1983 defm SXTH : AI_ext_rrot<0b01101011,
1984 "sxth", UnOpFrag<(sext_inreg node:$Src, i16)>>;
1986 defm SXTAB : AI_exta_rrot<0b01101010,
1987 "sxtab", BinOpFrag<(add node:$LHS, (sext_inreg node:$RHS, i8))>>;
1988 defm SXTAH : AI_exta_rrot<0b01101011,
1989 "sxtah", BinOpFrag<(add node:$LHS, (sext_inreg node:$RHS,i16))>>;
1991 // For disassembly only
1992 defm SXTB16 : AI_ext_rrot_np<0b01101000, "sxtb16">;
1994 // For disassembly only
1995 defm SXTAB16 : AI_exta_rrot_np<0b01101000, "sxtab16">;
1999 let AddedComplexity = 16 in {
2000 defm UXTB : AI_ext_rrot<0b01101110,
2001 "uxtb" , UnOpFrag<(and node:$Src, 0x000000FF)>>;
2002 defm UXTH : AI_ext_rrot<0b01101111,
2003 "uxth" , UnOpFrag<(and node:$Src, 0x0000FFFF)>>;
2004 defm UXTB16 : AI_ext_rrot<0b01101100,
2005 "uxtb16", UnOpFrag<(and node:$Src, 0x00FF00FF)>>;
2007 // FIXME: This pattern incorrectly assumes the shl operator is a rotate.
2008 // The transformation should probably be done as a combiner action
2009 // instead so we can include a check for masking back in the upper
2010 // eight bits of the source into the lower eight bits of the result.
2011 //def : ARMV6Pat<(and (shl GPR:$Src, (i32 8)), 0xFF00FF),
2012 // (UXTB16r_rot GPR:$Src, 24)>;
2013 def : ARMV6Pat<(and (srl GPR:$Src, (i32 8)), 0xFF00FF),
2014 (UXTB16r_rot GPR:$Src, 8)>;
2016 defm UXTAB : AI_exta_rrot<0b01101110, "uxtab",
2017 BinOpFrag<(add node:$LHS, (and node:$RHS, 0x00FF))>>;
2018 defm UXTAH : AI_exta_rrot<0b01101111, "uxtah",
2019 BinOpFrag<(add node:$LHS, (and node:$RHS, 0xFFFF))>>;
2022 // This isn't safe in general, the add is two 16-bit units, not a 32-bit add.
2023 // For disassembly only
2024 defm UXTAB16 : AI_exta_rrot_np<0b01101100, "uxtab16">;
2027 def SBFX : I<(outs GPR:$Rd),
2028 (ins GPR:$Rn, imm0_31:$lsb, imm0_31_m1:$width),
2029 AddrMode1, Size4Bytes, IndexModeNone, DPFrm, IIC_iUNAsi,
2030 "sbfx", "\t$Rd, $Rn, $lsb, $width", "", []>,
2031 Requires<[IsARM, HasV6T2]> {
2036 let Inst{27-21} = 0b0111101;
2037 let Inst{6-4} = 0b101;
2038 let Inst{20-16} = width;
2039 let Inst{15-12} = Rd;
2040 let Inst{11-7} = lsb;
2044 def UBFX : I<(outs GPR:$Rd),
2045 (ins GPR:$Rn, imm0_31:$lsb, imm0_31_m1:$width),
2046 AddrMode1, Size4Bytes, IndexModeNone, DPFrm, IIC_iUNAsi,
2047 "ubfx", "\t$Rd, $Rn, $lsb, $width", "", []>,
2048 Requires<[IsARM, HasV6T2]> {
2053 let Inst{27-21} = 0b0111111;
2054 let Inst{6-4} = 0b101;
2055 let Inst{20-16} = width;
2056 let Inst{15-12} = Rd;
2057 let Inst{11-7} = lsb;
2061 //===----------------------------------------------------------------------===//
2062 // Arithmetic Instructions.
2065 defm ADD : AsI1_bin_irs<0b0100, "add",
2066 IIC_iALUi, IIC_iALUr, IIC_iALUsr,
2067 BinOpFrag<(add node:$LHS, node:$RHS)>, 1>;
2068 defm SUB : AsI1_bin_irs<0b0010, "sub",
2069 IIC_iALUi, IIC_iALUr, IIC_iALUsr,
2070 BinOpFrag<(sub node:$LHS, node:$RHS)>>;
2072 // ADD and SUB with 's' bit set.
2073 defm ADDS : AI1_bin_s_irs<0b0100, "adds",
2074 IIC_iALUi, IIC_iALUr, IIC_iALUsr,
2075 BinOpFrag<(addc node:$LHS, node:$RHS)>, 1>;
2076 defm SUBS : AI1_bin_s_irs<0b0010, "subs",
2077 IIC_iALUi, IIC_iALUr, IIC_iALUsr,
2078 BinOpFrag<(subc node:$LHS, node:$RHS)>>;
2080 defm ADC : AI1_adde_sube_irs<0b0101, "adc",
2081 BinOpFrag<(adde_dead_carry node:$LHS, node:$RHS)>, 1>;
2082 defm SBC : AI1_adde_sube_irs<0b0110, "sbc",
2083 BinOpFrag<(sube_dead_carry node:$LHS, node:$RHS)>>;
2084 defm ADCS : AI1_adde_sube_s_irs<0b0101, "adcs",
2085 BinOpFrag<(adde_live_carry node:$LHS, node:$RHS)>, 1>;
2086 defm SBCS : AI1_adde_sube_s_irs<0b0110, "sbcs",
2087 BinOpFrag<(sube_live_carry node:$LHS, node:$RHS) >>;
2089 def RSBri : AsI1<0b0011, (outs GPR:$Rd), (ins GPR:$Rn, so_imm:$imm), DPFrm,
2090 IIC_iALUi, "rsb", "\t$Rd, $Rn, $imm",
2091 [(set GPR:$Rd, (sub so_imm:$imm, GPR:$Rn))]> {
2096 let Inst{15-12} = Rd;
2097 let Inst{19-16} = Rn;
2098 let Inst{11-0} = imm;
2101 // The reg/reg form is only defined for the disassembler; for codegen it is
2102 // equivalent to SUBrr.
2103 def RSBrr : AsI1<0b0011, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm), DPFrm,
2104 IIC_iALUr, "rsb", "\t$Rd, $Rn, $Rm",
2105 [/* For disassembly only; pattern left blank */]> {
2109 let Inst{11-4} = 0b00000000;
2112 let Inst{15-12} = Rd;
2113 let Inst{19-16} = Rn;
2116 def RSBrs : AsI1<0b0011, (outs GPR:$Rd), (ins GPR:$Rn, so_reg:$shift),
2117 DPSoRegFrm, IIC_iALUsr, "rsb", "\t$Rd, $Rn, $shift",
2118 [(set GPR:$Rd, (sub so_reg:$shift, GPR:$Rn))]> {
2123 let Inst{11-0} = shift;
2124 let Inst{15-12} = Rd;
2125 let Inst{19-16} = Rn;
2128 // RSB with 's' bit set.
2129 let Defs = [CPSR] in {
2130 def RSBSri : AI1<0b0011, (outs GPR:$Rd), (ins GPR:$Rn, so_imm:$imm), DPFrm,
2131 IIC_iALUi, "rsbs", "\t$Rd, $Rn, $imm",
2132 [(set GPR:$Rd, (subc so_imm:$imm, GPR:$Rn))]> {
2138 let Inst{15-12} = Rd;
2139 let Inst{19-16} = Rn;
2140 let Inst{11-0} = imm;
2142 def RSBSrs : AI1<0b0011, (outs GPR:$Rd), (ins GPR:$Rn, so_reg:$shift),
2143 DPSoRegFrm, IIC_iALUsr, "rsbs", "\t$Rd, $Rn, $shift",
2144 [(set GPR:$Rd, (subc so_reg:$shift, GPR:$Rn))]> {
2150 let Inst{11-0} = shift;
2151 let Inst{15-12} = Rd;
2152 let Inst{19-16} = Rn;
2156 let Uses = [CPSR] in {
2157 def RSCri : AsI1<0b0111, (outs GPR:$Rd), (ins GPR:$Rn, so_imm:$imm),
2158 DPFrm, IIC_iALUi, "rsc", "\t$Rd, $Rn, $imm",
2159 [(set GPR:$Rd, (sube_dead_carry so_imm:$imm, GPR:$Rn))]>,
2165 let Inst{15-12} = Rd;
2166 let Inst{19-16} = Rn;
2167 let Inst{11-0} = imm;
2169 // The reg/reg form is only defined for the disassembler; for codegen it is
2170 // equivalent to SUBrr.
2171 def RSCrr : AsI1<0b0111, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm),
2172 DPFrm, IIC_iALUr, "rsc", "\t$Rd, $Rn, $Rm",
2173 [/* For disassembly only; pattern left blank */]> {
2177 let Inst{11-4} = 0b00000000;
2180 let Inst{15-12} = Rd;
2181 let Inst{19-16} = Rn;
2183 def RSCrs : AsI1<0b0111, (outs GPR:$Rd), (ins GPR:$Rn, so_reg:$shift),
2184 DPSoRegFrm, IIC_iALUsr, "rsc", "\t$Rd, $Rn, $shift",
2185 [(set GPR:$Rd, (sube_dead_carry so_reg:$shift, GPR:$Rn))]>,
2191 let Inst{11-0} = shift;
2192 let Inst{15-12} = Rd;
2193 let Inst{19-16} = Rn;
2197 // FIXME: Allow these to be predicated.
2198 let Defs = [CPSR], Uses = [CPSR] in {
2199 def RSCSri : AXI1<0b0111, (outs GPR:$Rd), (ins GPR:$Rn, so_imm:$imm),
2200 DPFrm, IIC_iALUi, "rscs\t$Rd, $Rn, $imm",
2201 [(set GPR:$Rd, (sube_dead_carry so_imm:$imm, GPR:$Rn))]>,
2208 let Inst{15-12} = Rd;
2209 let Inst{19-16} = Rn;
2210 let Inst{11-0} = imm;
2212 def RSCSrs : AXI1<0b0111, (outs GPR:$Rd), (ins GPR:$Rn, so_reg:$shift),
2213 DPSoRegFrm, IIC_iALUsr, "rscs\t$Rd, $Rn, $shift",
2214 [(set GPR:$Rd, (sube_dead_carry so_reg:$shift, GPR:$Rn))]>,
2221 let Inst{11-0} = shift;
2222 let Inst{15-12} = Rd;
2223 let Inst{19-16} = Rn;
2227 // (sub X, imm) gets canonicalized to (add X, -imm). Match this form.
2228 // The assume-no-carry-in form uses the negation of the input since add/sub
2229 // assume opposite meanings of the carry flag (i.e., carry == !borrow).
2230 // See the definition of AddWithCarry() in the ARM ARM A2.2.1 for the gory
2232 def : ARMPat<(add GPR:$src, so_imm_neg:$imm),
2233 (SUBri GPR:$src, so_imm_neg:$imm)>;
2234 def : ARMPat<(addc GPR:$src, so_imm_neg:$imm),
2235 (SUBSri GPR:$src, so_imm_neg:$imm)>;
2236 // The with-carry-in form matches bitwise not instead of the negation.
2237 // Effectively, the inverse interpretation of the carry flag already accounts
2238 // for part of the negation.
2239 def : ARMPat<(adde GPR:$src, so_imm_not:$imm),
2240 (SBCri GPR:$src, so_imm_not:$imm)>;
2242 // Note: These are implemented in C++ code, because they have to generate
2243 // ADD/SUBrs instructions, which use a complex pattern that a xform function
2245 // (mul X, 2^n+1) -> (add (X << n), X)
2246 // (mul X, 2^n-1) -> (rsb X, (X << n))
2248 // ARM Arithmetic Instruction -- for disassembly only
2249 // GPR:$dst = GPR:$a op GPR:$b
2250 class AAI<bits<8> op27_20, bits<8> op11_4, string opc,
2251 list<dag> pattern = [/* For disassembly only; pattern left blank */]>
2252 : AI<(outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm), DPFrm, IIC_iALUr,
2253 opc, "\t$Rd, $Rn, $Rm", pattern> {
2257 let Inst{27-20} = op27_20;
2258 let Inst{11-4} = op11_4;
2259 let Inst{19-16} = Rn;
2260 let Inst{15-12} = Rd;
2264 // Saturating add/subtract -- for disassembly only
2266 def QADD : AAI<0b00010000, 0b00000101, "qadd",
2267 [(set GPR:$Rd, (int_arm_qadd GPR:$Rn, GPR:$Rm))]>;
2268 def QSUB : AAI<0b00010010, 0b00000101, "qsub",
2269 [(set GPR:$Rd, (int_arm_qsub GPR:$Rn, GPR:$Rm))]>;
2270 def QDADD : AAI<0b00010100, 0b00000101, "qdadd">;
2271 def QDSUB : AAI<0b00010110, 0b00000101, "qdsub">;
2273 def QADD16 : AAI<0b01100010, 0b11110001, "qadd16">;
2274 def QADD8 : AAI<0b01100010, 0b11111001, "qadd8">;
2275 def QASX : AAI<0b01100010, 0b11110011, "qasx">;
2276 def QSAX : AAI<0b01100010, 0b11110101, "qsax">;
2277 def QSUB16 : AAI<0b01100010, 0b11110111, "qsub16">;
2278 def QSUB8 : AAI<0b01100010, 0b11111111, "qsub8">;
2279 def UQADD16 : AAI<0b01100110, 0b11110001, "uqadd16">;
2280 def UQADD8 : AAI<0b01100110, 0b11111001, "uqadd8">;
2281 def UQASX : AAI<0b01100110, 0b11110011, "uqasx">;
2282 def UQSAX : AAI<0b01100110, 0b11110101, "uqsax">;
2283 def UQSUB16 : AAI<0b01100110, 0b11110111, "uqsub16">;
2284 def UQSUB8 : AAI<0b01100110, 0b11111111, "uqsub8">;
2286 // Signed/Unsigned add/subtract -- for disassembly only
2288 def SASX : AAI<0b01100001, 0b11110011, "sasx">;
2289 def SADD16 : AAI<0b01100001, 0b11110001, "sadd16">;
2290 def SADD8 : AAI<0b01100001, 0b11111001, "sadd8">;
2291 def SSAX : AAI<0b01100001, 0b11110101, "ssax">;
2292 def SSUB16 : AAI<0b01100001, 0b11110111, "ssub16">;
2293 def SSUB8 : AAI<0b01100001, 0b11111111, "ssub8">;
2294 def UASX : AAI<0b01100101, 0b11110011, "uasx">;
2295 def UADD16 : AAI<0b01100101, 0b11110001, "uadd16">;
2296 def UADD8 : AAI<0b01100101, 0b11111001, "uadd8">;
2297 def USAX : AAI<0b01100101, 0b11110101, "usax">;
2298 def USUB16 : AAI<0b01100101, 0b11110111, "usub16">;
2299 def USUB8 : AAI<0b01100101, 0b11111111, "usub8">;
2301 // Signed/Unsigned halving add/subtract -- for disassembly only
2303 def SHASX : AAI<0b01100011, 0b11110011, "shasx">;
2304 def SHADD16 : AAI<0b01100011, 0b11110001, "shadd16">;
2305 def SHADD8 : AAI<0b01100011, 0b11111001, "shadd8">;
2306 def SHSAX : AAI<0b01100011, 0b11110101, "shsax">;
2307 def SHSUB16 : AAI<0b01100011, 0b11110111, "shsub16">;
2308 def SHSUB8 : AAI<0b01100011, 0b11111111, "shsub8">;
2309 def UHASX : AAI<0b01100111, 0b11110011, "uhasx">;
2310 def UHADD16 : AAI<0b01100111, 0b11110001, "uhadd16">;
2311 def UHADD8 : AAI<0b01100111, 0b11111001, "uhadd8">;
2312 def UHSAX : AAI<0b01100111, 0b11110101, "uhsax">;
2313 def UHSUB16 : AAI<0b01100111, 0b11110111, "uhsub16">;
2314 def UHSUB8 : AAI<0b01100111, 0b11111111, "uhsub8">;
2316 // Unsigned Sum of Absolute Differences [and Accumulate] -- for disassembly only
2318 def USAD8 : AI<(outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm),
2319 MulFrm /* for convenience */, NoItinerary, "usad8",
2320 "\t$Rd, $Rn, $Rm", []>,
2321 Requires<[IsARM, HasV6]> {
2325 let Inst{27-20} = 0b01111000;
2326 let Inst{15-12} = 0b1111;
2327 let Inst{7-4} = 0b0001;
2328 let Inst{19-16} = Rd;
2329 let Inst{11-8} = Rm;
2332 def USADA8 : AI<(outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm, GPR:$Ra),
2333 MulFrm /* for convenience */, NoItinerary, "usada8",
2334 "\t$Rd, $Rn, $Rm, $Ra", []>,
2335 Requires<[IsARM, HasV6]> {
2340 let Inst{27-20} = 0b01111000;
2341 let Inst{7-4} = 0b0001;
2342 let Inst{19-16} = Rd;
2343 let Inst{15-12} = Ra;
2344 let Inst{11-8} = Rm;
2348 // Signed/Unsigned saturate -- for disassembly only
2350 def SSAT : AI<(outs GPR:$Rd), (ins i32imm:$sat_imm, GPR:$a, shift_imm:$sh),
2351 SatFrm, NoItinerary, "ssat", "\t$Rd, $sat_imm, $a$sh",
2352 [/* For disassembly only; pattern left blank */]> {
2357 let Inst{27-21} = 0b0110101;
2358 let Inst{5-4} = 0b01;
2359 let Inst{20-16} = sat_imm;
2360 let Inst{15-12} = Rd;
2361 let Inst{11-7} = sh{7-3};
2362 let Inst{6} = sh{0};
2366 def SSAT16 : AI<(outs GPR:$Rd), (ins i32imm:$sat_imm, GPR:$Rn), SatFrm,
2367 NoItinerary, "ssat16", "\t$Rd, $sat_imm, $Rn",
2368 [/* For disassembly only; pattern left blank */]> {
2372 let Inst{27-20} = 0b01101010;
2373 let Inst{11-4} = 0b11110011;
2374 let Inst{15-12} = Rd;
2375 let Inst{19-16} = sat_imm;
2379 def USAT : AI<(outs GPR:$Rd), (ins i32imm:$sat_imm, GPR:$a, shift_imm:$sh),
2380 SatFrm, NoItinerary, "usat", "\t$Rd, $sat_imm, $a$sh",
2381 [/* For disassembly only; pattern left blank */]> {
2386 let Inst{27-21} = 0b0110111;
2387 let Inst{5-4} = 0b01;
2388 let Inst{15-12} = Rd;
2389 let Inst{11-7} = sh{7-3};
2390 let Inst{6} = sh{0};
2391 let Inst{20-16} = sat_imm;
2395 def USAT16 : AI<(outs GPR:$Rd), (ins i32imm:$sat_imm, GPR:$a), SatFrm,
2396 NoItinerary, "usat16", "\t$Rd, $sat_imm, $a",
2397 [/* For disassembly only; pattern left blank */]> {
2401 let Inst{27-20} = 0b01101110;
2402 let Inst{11-4} = 0b11110011;
2403 let Inst{15-12} = Rd;
2404 let Inst{19-16} = sat_imm;
2408 def : ARMV6Pat<(int_arm_ssat GPR:$a, imm:$pos), (SSAT imm:$pos, GPR:$a, 0)>;
2409 def : ARMV6Pat<(int_arm_usat GPR:$a, imm:$pos), (USAT imm:$pos, GPR:$a, 0)>;
2411 //===----------------------------------------------------------------------===//
2412 // Bitwise Instructions.
2415 defm AND : AsI1_bin_irs<0b0000, "and",
2416 IIC_iBITi, IIC_iBITr, IIC_iBITsr,
2417 BinOpFrag<(and node:$LHS, node:$RHS)>, 1>;
2418 defm ORR : AsI1_bin_irs<0b1100, "orr",
2419 IIC_iBITi, IIC_iBITr, IIC_iBITsr,
2420 BinOpFrag<(or node:$LHS, node:$RHS)>, 1>;
2421 defm EOR : AsI1_bin_irs<0b0001, "eor",
2422 IIC_iBITi, IIC_iBITr, IIC_iBITsr,
2423 BinOpFrag<(xor node:$LHS, node:$RHS)>, 1>;
2424 defm BIC : AsI1_bin_irs<0b1110, "bic",
2425 IIC_iBITi, IIC_iBITr, IIC_iBITsr,
2426 BinOpFrag<(and node:$LHS, (not node:$RHS))>>;
2428 def BFC : I<(outs GPR:$Rd), (ins GPR:$src, bf_inv_mask_imm:$imm),
2429 AddrMode1, Size4Bytes, IndexModeNone, DPFrm, IIC_iUNAsi,
2430 "bfc", "\t$Rd, $imm", "$src = $Rd",
2431 [(set GPR:$Rd, (and GPR:$src, bf_inv_mask_imm:$imm))]>,
2432 Requires<[IsARM, HasV6T2]> {
2435 let Inst{27-21} = 0b0111110;
2436 let Inst{6-0} = 0b0011111;
2437 let Inst{15-12} = Rd;
2438 let Inst{11-7} = imm{4-0}; // lsb
2439 let Inst{20-16} = imm{9-5}; // width
2442 // A8.6.18 BFI - Bitfield insert (Encoding A1)
2443 def BFI : I<(outs GPR:$Rd), (ins GPR:$src, GPR:$Rn, bf_inv_mask_imm:$imm),
2444 AddrMode1, Size4Bytes, IndexModeNone, DPFrm, IIC_iUNAsi,
2445 "bfi", "\t$Rd, $Rn, $imm", "$src = $Rd",
2446 [(set GPR:$Rd, (ARMbfi GPR:$src, GPR:$Rn,
2447 bf_inv_mask_imm:$imm))]>,
2448 Requires<[IsARM, HasV6T2]> {
2452 let Inst{27-21} = 0b0111110;
2453 let Inst{6-4} = 0b001; // Rn: Inst{3-0} != 15
2454 let Inst{15-12} = Rd;
2455 let Inst{11-7} = imm{4-0}; // lsb
2456 let Inst{20-16} = imm{9-5}; // width
2460 def MVNr : AsI1<0b1111, (outs GPR:$Rd), (ins GPR:$Rm), DPFrm, IIC_iMVNr,
2461 "mvn", "\t$Rd, $Rm",
2462 [(set GPR:$Rd, (not GPR:$Rm))]>, UnaryDP {
2466 let Inst{19-16} = 0b0000;
2467 let Inst{11-4} = 0b00000000;
2468 let Inst{15-12} = Rd;
2471 def MVNs : AsI1<0b1111, (outs GPR:$Rd), (ins so_reg:$shift), DPSoRegFrm,
2472 IIC_iMVNsr, "mvn", "\t$Rd, $shift",
2473 [(set GPR:$Rd, (not so_reg:$shift))]>, UnaryDP {
2477 let Inst{19-16} = 0b0000;
2478 let Inst{15-12} = Rd;
2479 let Inst{11-0} = shift;
2481 let isReMaterializable = 1, isAsCheapAsAMove = 1, isMoveImm = 1 in
2482 def MVNi : AsI1<0b1111, (outs GPR:$Rd), (ins so_imm:$imm), DPFrm,
2483 IIC_iMVNi, "mvn", "\t$Rd, $imm",
2484 [(set GPR:$Rd, so_imm_not:$imm)]>,UnaryDP {
2488 let Inst{19-16} = 0b0000;
2489 let Inst{15-12} = Rd;
2490 let Inst{11-0} = imm;
2493 def : ARMPat<(and GPR:$src, so_imm_not:$imm),
2494 (BICri GPR:$src, so_imm_not:$imm)>;
2496 //===----------------------------------------------------------------------===//
2497 // Multiply Instructions.
2499 class AsMul1I32<bits<7> opcod, dag oops, dag iops, InstrItinClass itin,
2500 string opc, string asm, list<dag> pattern>
2501 : AsMul1I<opcod, oops, iops, itin, opc, asm, pattern> {
2505 let Inst{19-16} = Rd;
2506 let Inst{11-8} = Rm;
2509 class AsMul1I64<bits<7> opcod, dag oops, dag iops, InstrItinClass itin,
2510 string opc, string asm, list<dag> pattern>
2511 : AsMul1I<opcod, oops, iops, itin, opc, asm, pattern> {
2516 let Inst{19-16} = RdHi;
2517 let Inst{15-12} = RdLo;
2518 let Inst{11-8} = Rm;
2522 let isCommutable = 1 in
2523 def MUL : AsMul1I32<0b0000000, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm),
2524 IIC_iMUL32, "mul", "\t$Rd, $Rn, $Rm",
2525 [(set GPR:$Rd, (mul GPR:$Rn, GPR:$Rm))]>;
2527 def MLA : AsMul1I32<0b0000001, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm, GPR:$Ra),
2528 IIC_iMAC32, "mla", "\t$Rd, $Rn, $Rm, $Ra",
2529 [(set GPR:$Rd, (add (mul GPR:$Rn, GPR:$Rm), GPR:$Ra))]> {
2531 let Inst{15-12} = Ra;
2534 def MLS : AMul1I<0b0000011, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm, GPR:$Ra),
2535 IIC_iMAC32, "mls", "\t$Rd, $Rn, $Rm, $Ra",
2536 [(set GPR:$Rd, (sub GPR:$Ra, (mul GPR:$Rn, GPR:$Rm)))]>,
2537 Requires<[IsARM, HasV6T2]> {
2542 let Inst{19-16} = Rd;
2543 let Inst{15-12} = Ra;
2544 let Inst{11-8} = Rm;
2548 // Extra precision multiplies with low / high results
2550 let neverHasSideEffects = 1 in {
2551 let isCommutable = 1 in {
2552 def SMULL : AsMul1I64<0b0000110, (outs GPR:$RdLo, GPR:$RdHi),
2553 (ins GPR:$Rn, GPR:$Rm), IIC_iMUL64,
2554 "smull", "\t$RdLo, $RdHi, $Rn, $Rm", []>;
2556 def UMULL : AsMul1I64<0b0000100, (outs GPR:$RdLo, GPR:$RdHi),
2557 (ins GPR:$Rn, GPR:$Rm), IIC_iMUL64,
2558 "umull", "\t$RdLo, $RdHi, $Rn, $Rm", []>;
2561 // Multiply + accumulate
2562 def SMLAL : AsMul1I64<0b0000111, (outs GPR:$RdLo, GPR:$RdHi),
2563 (ins GPR:$Rn, GPR:$Rm), IIC_iMAC64,
2564 "smlal", "\t$RdLo, $RdHi, $Rn, $Rm", []>;
2566 def UMLAL : AsMul1I64<0b0000101, (outs GPR:$RdLo, GPR:$RdHi),
2567 (ins GPR:$Rn, GPR:$Rm), IIC_iMAC64,
2568 "umlal", "\t$RdLo, $RdHi, $Rn, $Rm", []>;
2570 def UMAAL : AMul1I <0b0000010, (outs GPR:$RdLo, GPR:$RdHi),
2571 (ins GPR:$Rn, GPR:$Rm), IIC_iMAC64,
2572 "umaal", "\t$RdLo, $RdHi, $Rn, $Rm", []>,
2573 Requires<[IsARM, HasV6]> {
2578 let Inst{19-16} = RdLo;
2579 let Inst{15-12} = RdHi;
2580 let Inst{11-8} = Rm;
2583 } // neverHasSideEffects
2585 // Most significant word multiply
2586 def SMMUL : AMul2I <0b0111010, 0b0001, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm),
2587 IIC_iMUL32, "smmul", "\t$Rd, $Rn, $Rm",
2588 [(set GPR:$Rd, (mulhs GPR:$Rn, GPR:$Rm))]>,
2589 Requires<[IsARM, HasV6]> {
2590 let Inst{15-12} = 0b1111;
2593 def SMMULR : AMul2I <0b0111010, 0b0011, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm),
2594 IIC_iMUL32, "smmulr", "\t$Rd, $Rn, $Rm",
2595 [/* For disassembly only; pattern left blank */]>,
2596 Requires<[IsARM, HasV6]> {
2597 let Inst{15-12} = 0b1111;
2600 def SMMLA : AMul2Ia <0b0111010, 0b0001, (outs GPR:$Rd),
2601 (ins GPR:$Rn, GPR:$Rm, GPR:$Ra),
2602 IIC_iMAC32, "smmla", "\t$Rd, $Rn, $Rm, $Ra",
2603 [(set GPR:$Rd, (add (mulhs GPR:$Rn, GPR:$Rm), GPR:$Ra))]>,
2604 Requires<[IsARM, HasV6]>;
2606 def SMMLAR : AMul2Ia <0b0111010, 0b0011, (outs GPR:$Rd),
2607 (ins GPR:$Rn, GPR:$Rm, GPR:$Ra),
2608 IIC_iMAC32, "smmlar", "\t$Rd, $Rn, $Rm, $Ra",
2609 [/* For disassembly only; pattern left blank */]>,
2610 Requires<[IsARM, HasV6]>;
2612 def SMMLS : AMul2Ia <0b0111010, 0b1101, (outs GPR:$Rd),
2613 (ins GPR:$Rn, GPR:$Rm, GPR:$Ra),
2614 IIC_iMAC32, "smmls", "\t$Rd, $Rn, $Rm, $Ra",
2615 [(set GPR:$Rd, (sub GPR:$Ra, (mulhs GPR:$Rn, GPR:$Rm)))]>,
2616 Requires<[IsARM, HasV6]>;
2618 def SMMLSR : AMul2Ia <0b0111010, 0b1111, (outs GPR:$Rd),
2619 (ins GPR:$Rn, GPR:$Rm, GPR:$Ra),
2620 IIC_iMAC32, "smmlsr", "\t$Rd, $Rn, $Rm, $Ra",
2621 [/* For disassembly only; pattern left blank */]>,
2622 Requires<[IsARM, HasV6]>;
2624 multiclass AI_smul<string opc, PatFrag opnode> {
2625 def BB : AMulxyI<0b0001011, 0b00, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm),
2626 IIC_iMUL16, !strconcat(opc, "bb"), "\t$Rd, $Rn, $Rm",
2627 [(set GPR:$Rd, (opnode (sext_inreg GPR:$Rn, i16),
2628 (sext_inreg GPR:$Rm, i16)))]>,
2629 Requires<[IsARM, HasV5TE]>;
2631 def BT : AMulxyI<0b0001011, 0b10, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm),
2632 IIC_iMUL16, !strconcat(opc, "bt"), "\t$Rd, $Rn, $Rm",
2633 [(set GPR:$Rd, (opnode (sext_inreg GPR:$Rn, i16),
2634 (sra GPR:$Rm, (i32 16))))]>,
2635 Requires<[IsARM, HasV5TE]>;
2637 def TB : AMulxyI<0b0001011, 0b01, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm),
2638 IIC_iMUL16, !strconcat(opc, "tb"), "\t$Rd, $Rn, $Rm",
2639 [(set GPR:$Rd, (opnode (sra GPR:$Rn, (i32 16)),
2640 (sext_inreg GPR:$Rm, i16)))]>,
2641 Requires<[IsARM, HasV5TE]>;
2643 def TT : AMulxyI<0b0001011, 0b11, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm),
2644 IIC_iMUL16, !strconcat(opc, "tt"), "\t$Rd, $Rn, $Rm",
2645 [(set GPR:$Rd, (opnode (sra GPR:$Rn, (i32 16)),
2646 (sra GPR:$Rm, (i32 16))))]>,
2647 Requires<[IsARM, HasV5TE]>;
2649 def WB : AMulxyI<0b0001001, 0b01, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm),
2650 IIC_iMUL16, !strconcat(opc, "wb"), "\t$Rd, $Rn, $Rm",
2651 [(set GPR:$Rd, (sra (opnode GPR:$Rn,
2652 (sext_inreg GPR:$Rm, i16)), (i32 16)))]>,
2653 Requires<[IsARM, HasV5TE]>;
2655 def WT : AMulxyI<0b0001001, 0b11, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm),
2656 IIC_iMUL16, !strconcat(opc, "wt"), "\t$Rd, $Rn, $Rm",
2657 [(set GPR:$Rd, (sra (opnode GPR:$Rn,
2658 (sra GPR:$Rm, (i32 16))), (i32 16)))]>,
2659 Requires<[IsARM, HasV5TE]>;
2663 multiclass AI_smla<string opc, PatFrag opnode> {
2664 def BB : AMulxyIa<0b0001000, 0b00, (outs GPR:$Rd),
2665 (ins GPR:$Rn, GPR:$Rm, GPR:$Ra),
2666 IIC_iMAC16, !strconcat(opc, "bb"), "\t$Rd, $Rn, $Rm, $Ra",
2667 [(set GPR:$Rd, (add GPR:$Ra,
2668 (opnode (sext_inreg GPR:$Rn, i16),
2669 (sext_inreg GPR:$Rm, i16))))]>,
2670 Requires<[IsARM, HasV5TE]>;
2672 def BT : AMulxyIa<0b0001000, 0b10, (outs GPR:$Rd),
2673 (ins GPR:$Rn, GPR:$Rm, GPR:$Ra),
2674 IIC_iMAC16, !strconcat(opc, "bt"), "\t$Rd, $Rn, $Rm, $Ra",
2675 [(set GPR:$Rd, (add GPR:$Ra, (opnode (sext_inreg GPR:$Rn, i16),
2676 (sra GPR:$Rm, (i32 16)))))]>,
2677 Requires<[IsARM, HasV5TE]>;
2679 def TB : AMulxyIa<0b0001000, 0b01, (outs GPR:$Rd),
2680 (ins GPR:$Rn, GPR:$Rm, GPR:$Ra),
2681 IIC_iMAC16, !strconcat(opc, "tb"), "\t$Rd, $Rn, $Rm, $Ra",
2682 [(set GPR:$Rd, (add GPR:$Ra, (opnode (sra GPR:$Rn, (i32 16)),
2683 (sext_inreg GPR:$Rm, i16))))]>,
2684 Requires<[IsARM, HasV5TE]>;
2686 def TT : AMulxyIa<0b0001000, 0b11, (outs GPR:$Rd),
2687 (ins GPR:$Rn, GPR:$Rm, GPR:$Ra),
2688 IIC_iMAC16, !strconcat(opc, "tt"), "\t$Rd, $Rn, $Rm, $Ra",
2689 [(set GPR:$Rd, (add GPR:$Ra, (opnode (sra GPR:$Rn, (i32 16)),
2690 (sra GPR:$Rm, (i32 16)))))]>,
2691 Requires<[IsARM, HasV5TE]>;
2693 def WB : AMulxyIa<0b0001001, 0b00, (outs GPR:$Rd),
2694 (ins GPR:$Rn, GPR:$Rm, GPR:$Ra),
2695 IIC_iMAC16, !strconcat(opc, "wb"), "\t$Rd, $Rn, $Rm, $Ra",
2696 [(set GPR:$Rd, (add GPR:$Ra, (sra (opnode GPR:$Rn,
2697 (sext_inreg GPR:$Rm, i16)), (i32 16))))]>,
2698 Requires<[IsARM, HasV5TE]>;
2700 def WT : AMulxyIa<0b0001001, 0b10, (outs GPR:$Rd),
2701 (ins GPR:$Rn, GPR:$Rm, GPR:$Ra),
2702 IIC_iMAC16, !strconcat(opc, "wt"), "\t$Rd, $Rn, $Rm, $Ra",
2703 [(set GPR:$Rd, (add GPR:$Ra, (sra (opnode GPR:$Rn,
2704 (sra GPR:$Rm, (i32 16))), (i32 16))))]>,
2705 Requires<[IsARM, HasV5TE]>;
2708 defm SMUL : AI_smul<"smul", BinOpFrag<(mul node:$LHS, node:$RHS)>>;
2709 defm SMLA : AI_smla<"smla", BinOpFrag<(mul node:$LHS, node:$RHS)>>;
2711 // Halfword multiply accumulate long: SMLAL<x><y> -- for disassembly only
2712 def SMLALBB : AMulxyI64<0b0001010, 0b00, (outs GPR:$RdLo, GPR:$RdHi),
2713 (ins GPR:$Rn, GPR:$Rm),
2714 IIC_iMAC64, "smlalbb", "\t$RdLo, $RdHi, $Rn, $Rm",
2715 [/* For disassembly only; pattern left blank */]>,
2716 Requires<[IsARM, HasV5TE]>;
2718 def SMLALBT : AMulxyI64<0b0001010, 0b10, (outs GPR:$RdLo, GPR:$RdHi),
2719 (ins GPR:$Rn, GPR:$Rm),
2720 IIC_iMAC64, "smlalbt", "\t$RdLo, $RdHi, $Rn, $Rm",
2721 [/* For disassembly only; pattern left blank */]>,
2722 Requires<[IsARM, HasV5TE]>;
2724 def SMLALTB : AMulxyI64<0b0001010, 0b01, (outs GPR:$RdLo, GPR:$RdHi),
2725 (ins GPR:$Rn, GPR:$Rm),
2726 IIC_iMAC64, "smlaltb", "\t$RdLo, $RdHi, $Rn, $Rm",
2727 [/* For disassembly only; pattern left blank */]>,
2728 Requires<[IsARM, HasV5TE]>;
2730 def SMLALTT : AMulxyI64<0b0001010, 0b11, (outs GPR:$RdLo, GPR:$RdHi),
2731 (ins GPR:$Rn, GPR:$Rm),
2732 IIC_iMAC64, "smlaltt", "\t$RdLo, $RdHi, $Rn, $Rm",
2733 [/* For disassembly only; pattern left blank */]>,
2734 Requires<[IsARM, HasV5TE]>;
2736 // Helper class for AI_smld -- for disassembly only
2737 class AMulDualIbase<bit long, bit sub, bit swap, dag oops, dag iops,
2738 InstrItinClass itin, string opc, string asm>
2739 : AI<oops, iops, MulFrm, itin, opc, asm, []>, Requires<[IsARM, HasV6]> {
2746 let Inst{21-20} = 0b00;
2747 let Inst{22} = long;
2748 let Inst{27-23} = 0b01110;
2749 let Inst{11-8} = Rm;
2752 class AMulDualI<bit long, bit sub, bit swap, dag oops, dag iops,
2753 InstrItinClass itin, string opc, string asm>
2754 : AMulDualIbase<long, sub, swap, oops, iops, itin, opc, asm> {
2756 let Inst{15-12} = 0b1111;
2757 let Inst{19-16} = Rd;
2759 class AMulDualIa<bit long, bit sub, bit swap, dag oops, dag iops,
2760 InstrItinClass itin, string opc, string asm>
2761 : AMulDualIbase<long, sub, swap, oops, iops, itin, opc, asm> {
2763 let Inst{15-12} = Ra;
2765 class AMulDualI64<bit long, bit sub, bit swap, dag oops, dag iops,
2766 InstrItinClass itin, string opc, string asm>
2767 : AMulDualIbase<long, sub, swap, oops, iops, itin, opc, asm> {
2770 let Inst{19-16} = RdHi;
2771 let Inst{15-12} = RdLo;
2774 multiclass AI_smld<bit sub, string opc> {
2776 def D : AMulDualIa<0, sub, 0, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm, GPR:$Ra),
2777 NoItinerary, !strconcat(opc, "d"), "\t$Rd, $Rn, $Rm, $Ra">;
2779 def DX: AMulDualIa<0, sub, 1, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm, GPR:$Ra),
2780 NoItinerary, !strconcat(opc, "dx"), "\t$Rd, $Rn, $Rm, $Ra">;
2782 def LD: AMulDualI64<1, sub, 0, (outs GPR:$RdLo,GPR:$RdHi),
2783 (ins GPR:$Rn, GPR:$Rm), NoItinerary,
2784 !strconcat(opc, "ld"), "\t$RdLo, $RdHi, $Rn, $Rm">;
2786 def LDX : AMulDualI64<1, sub, 1, (outs GPR:$RdLo,GPR:$RdHi),
2787 (ins GPR:$Rn, GPR:$Rm), NoItinerary,
2788 !strconcat(opc, "ldx"),"\t$RdLo, $RdHi, $Rn, $Rm">;
2792 defm SMLA : AI_smld<0, "smla">;
2793 defm SMLS : AI_smld<1, "smls">;
2795 multiclass AI_sdml<bit sub, string opc> {
2797 def D : AMulDualI<0, sub, 0, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm),
2798 NoItinerary, !strconcat(opc, "d"), "\t$Rd, $Rn, $Rm">;
2799 def DX : AMulDualI<0, sub, 1, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm),
2800 NoItinerary, !strconcat(opc, "dx"), "\t$Rd, $Rn, $Rm">;
2803 defm SMUA : AI_sdml<0, "smua">;
2804 defm SMUS : AI_sdml<1, "smus">;
2806 //===----------------------------------------------------------------------===//
2807 // Misc. Arithmetic Instructions.
2810 def CLZ : AMiscA1I<0b000010110, 0b0001, (outs GPR:$Rd), (ins GPR:$Rm),
2811 IIC_iUNAr, "clz", "\t$Rd, $Rm",
2812 [(set GPR:$Rd, (ctlz GPR:$Rm))]>, Requires<[IsARM, HasV5T]>;
2814 def RBIT : AMiscA1I<0b01101111, 0b0011, (outs GPR:$Rd), (ins GPR:$Rm),
2815 IIC_iUNAr, "rbit", "\t$Rd, $Rm",
2816 [(set GPR:$Rd, (ARMrbit GPR:$Rm))]>,
2817 Requires<[IsARM, HasV6T2]>;
2819 def REV : AMiscA1I<0b01101011, 0b0011, (outs GPR:$Rd), (ins GPR:$Rm),
2820 IIC_iUNAr, "rev", "\t$Rd, $Rm",
2821 [(set GPR:$Rd, (bswap GPR:$Rm))]>, Requires<[IsARM, HasV6]>;
2823 def REV16 : AMiscA1I<0b01101011, 0b1011, (outs GPR:$Rd), (ins GPR:$Rm),
2824 IIC_iUNAr, "rev16", "\t$Rd, $Rm",
2826 (or (and (srl GPR:$Rm, (i32 8)), 0xFF),
2827 (or (and (shl GPR:$Rm, (i32 8)), 0xFF00),
2828 (or (and (srl GPR:$Rm, (i32 8)), 0xFF0000),
2829 (and (shl GPR:$Rm, (i32 8)), 0xFF000000)))))]>,
2830 Requires<[IsARM, HasV6]>;
2832 def REVSH : AMiscA1I<0b01101111, 0b1011, (outs GPR:$Rd), (ins GPR:$Rm),
2833 IIC_iUNAr, "revsh", "\t$Rd, $Rm",
2836 (or (srl (and GPR:$Rm, 0xFF00), (i32 8)),
2837 (shl GPR:$Rm, (i32 8))), i16))]>,
2838 Requires<[IsARM, HasV6]>;
2840 def lsl_shift_imm : SDNodeXForm<imm, [{
2841 unsigned Sh = ARM_AM::getSORegOpc(ARM_AM::lsl, N->getZExtValue());
2842 return CurDAG->getTargetConstant(Sh, MVT::i32);
2845 def lsl_amt : PatLeaf<(i32 imm), [{
2846 return (N->getZExtValue() < 32);
2849 def PKHBT : APKHI<0b01101000, 0, (outs GPR:$Rd),
2850 (ins GPR:$Rn, GPR:$Rm, shift_imm:$sh),
2851 IIC_iALUsi, "pkhbt", "\t$Rd, $Rn, $Rm$sh",
2852 [(set GPR:$Rd, (or (and GPR:$Rn, 0xFFFF),
2853 (and (shl GPR:$Rm, lsl_amt:$sh),
2855 Requires<[IsARM, HasV6]>;
2857 // Alternate cases for PKHBT where identities eliminate some nodes.
2858 def : ARMV6Pat<(or (and GPR:$Rn, 0xFFFF), (and GPR:$Rm, 0xFFFF0000)),
2859 (PKHBT GPR:$Rn, GPR:$Rm, 0)>;
2860 def : ARMV6Pat<(or (and GPR:$Rn, 0xFFFF), (shl GPR:$Rm, imm16_31:$sh)),
2861 (PKHBT GPR:$Rn, GPR:$Rm, (lsl_shift_imm imm16_31:$sh))>;
2863 def asr_shift_imm : SDNodeXForm<imm, [{
2864 unsigned Sh = ARM_AM::getSORegOpc(ARM_AM::asr, N->getZExtValue());
2865 return CurDAG->getTargetConstant(Sh, MVT::i32);
2868 def asr_amt : PatLeaf<(i32 imm), [{
2869 return (N->getZExtValue() <= 32);
2872 // Note: Shifts of 1-15 bits will be transformed to srl instead of sra and
2873 // will match the pattern below.
2874 def PKHTB : APKHI<0b01101000, 1, (outs GPR:$Rd),
2875 (ins GPR:$Rn, GPR:$Rm, shift_imm:$sh),
2876 IIC_iBITsi, "pkhtb", "\t$Rd, $Rn, $Rm$sh",
2877 [(set GPR:$Rd, (or (and GPR:$Rn, 0xFFFF0000),
2878 (and (sra GPR:$Rm, asr_amt:$sh),
2880 Requires<[IsARM, HasV6]>;
2882 // Alternate cases for PKHTB where identities eliminate some nodes. Note that
2883 // a shift amount of 0 is *not legal* here, it is PKHBT instead.
2884 def : ARMV6Pat<(or (and GPR:$src1, 0xFFFF0000), (srl GPR:$src2, imm16_31:$sh)),
2885 (PKHTB GPR:$src1, GPR:$src2, (asr_shift_imm imm16_31:$sh))>;
2886 def : ARMV6Pat<(or (and GPR:$src1, 0xFFFF0000),
2887 (and (srl GPR:$src2, imm1_15:$sh), 0xFFFF)),
2888 (PKHTB GPR:$src1, GPR:$src2, (asr_shift_imm imm1_15:$sh))>;
2890 //===----------------------------------------------------------------------===//
2891 // Comparison Instructions...
2894 defm CMP : AI1_cmp_irs<0b1010, "cmp",
2895 IIC_iCMPi, IIC_iCMPr, IIC_iCMPsr,
2896 BinOpFrag<(ARMcmp node:$LHS, node:$RHS)>>;
2898 // FIXME: We have to be careful when using the CMN instruction and comparison
2899 // with 0. One would expect these two pieces of code should give identical
2915 // However, the CMN gives the *opposite* result when r1 is 0. This is because
2916 // the carry flag is set in the CMP case but not in the CMN case. In short, the
2917 // CMP instruction doesn't perform a truncate of the (logical) NOT of 0 plus the
2918 // value of r0 and the carry bit (because the "carry bit" parameter to
2919 // AddWithCarry is defined as 1 in this case, the carry flag will always be set
2920 // when r0 >= 0). The CMN instruction doesn't perform a NOT of 0 so there is
2921 // never a "carry" when this AddWithCarry is performed (because the "carry bit"
2922 // parameter to AddWithCarry is defined as 0).
2924 // When x is 0 and unsigned:
2928 // ~x + 1 = 0x1 0000 0000
2929 // (-x = 0) != (0x1 0000 0000 = ~x + 1)
2931 // Therefore, we should disable CMN when comparing against zero, until we can
2932 // limit when the CMN instruction is used (when we know that the RHS is not 0 or
2933 // when it's a comparison which doesn't look at the 'carry' flag).
2935 // (See the ARM docs for the "AddWithCarry" pseudo-code.)
2937 // This is related to <rdar://problem/7569620>.
2939 //defm CMN : AI1_cmp_irs<0b1011, "cmn",
2940 // BinOpFrag<(ARMcmp node:$LHS,(ineg node:$RHS))>>;
2942 // Note that TST/TEQ don't set all the same flags that CMP does!
2943 defm TST : AI1_cmp_irs<0b1000, "tst",
2944 IIC_iTSTi, IIC_iTSTr, IIC_iTSTsr,
2945 BinOpFrag<(ARMcmpZ (and_su node:$LHS, node:$RHS), 0)>, 1>;
2946 defm TEQ : AI1_cmp_irs<0b1001, "teq",
2947 IIC_iTSTi, IIC_iTSTr, IIC_iTSTsr,
2948 BinOpFrag<(ARMcmpZ (xor_su node:$LHS, node:$RHS), 0)>, 1>;
2950 defm CMPz : AI1_cmp_irs<0b1010, "cmp",
2951 IIC_iCMPi, IIC_iCMPr, IIC_iCMPsr,
2952 BinOpFrag<(ARMcmpZ node:$LHS, node:$RHS)>>;
2953 defm CMNz : AI1_cmp_irs<0b1011, "cmn",
2954 IIC_iCMPi, IIC_iCMPr, IIC_iCMPsr,
2955 BinOpFrag<(ARMcmpZ node:$LHS,(ineg node:$RHS))>>;
2957 //def : ARMPat<(ARMcmp GPR:$src, so_imm_neg:$imm),
2958 // (CMNri GPR:$src, so_imm_neg:$imm)>;
2960 def : ARMPat<(ARMcmpZ GPR:$src, so_imm_neg:$imm),
2961 (CMNzri GPR:$src, so_imm_neg:$imm)>;
2963 // Pseudo i64 compares for some floating point compares.
2964 let usesCustomInserter = 1, isBranch = 1, isTerminator = 1,
2966 def BCCi64 : PseudoInst<(outs),
2967 (ins i32imm:$cc, GPR:$lhs1, GPR:$lhs2, GPR:$rhs1, GPR:$rhs2, brtarget:$dst),
2969 [(ARMBcci64 imm:$cc, GPR:$lhs1, GPR:$lhs2, GPR:$rhs1, GPR:$rhs2, bb:$dst)]>;
2971 def BCCZi64 : PseudoInst<(outs),
2972 (ins i32imm:$cc, GPR:$lhs1, GPR:$lhs2, brtarget:$dst), IIC_Br,
2973 [(ARMBcci64 imm:$cc, GPR:$lhs1, GPR:$lhs2, 0, 0, bb:$dst)]>;
2974 } // usesCustomInserter
2977 // Conditional moves
2978 // FIXME: should be able to write a pattern for ARMcmov, but can't use
2979 // a two-value operand where a dag node expects two operands. :(
2980 // FIXME: These should all be pseudo-instructions that get expanded to
2981 // the normal MOV instructions. That would fix the dependency on
2982 // special casing them in tblgen.
2983 let neverHasSideEffects = 1 in {
2984 def MOVCCr : AI1<0b1101, (outs GPR:$Rd), (ins GPR:$false, GPR:$Rm), DPFrm,
2985 IIC_iCMOVr, "mov", "\t$Rd, $Rm",
2986 [/*(set GPR:$Rd, (ARMcmov GPR:$false, GPR:$Rm, imm:$cc, CCR:$ccr))*/]>,
2987 RegConstraint<"$false = $Rd">, UnaryDP {
2992 let Inst{15-12} = Rd;
2993 let Inst{11-4} = 0b00000000;
2997 def MOVCCs : AI1<0b1101, (outs GPR:$Rd),
2998 (ins GPR:$false, so_reg:$shift), DPSoRegFrm, IIC_iCMOVsr,
2999 "mov", "\t$Rd, $shift",
3000 [/*(set GPR:$Rd, (ARMcmov GPR:$false, so_reg:$shift, imm:$cc, CCR:$ccr))*/]>,
3001 RegConstraint<"$false = $Rd">, UnaryDP {
3006 let Inst{19-16} = 0;
3007 let Inst{15-12} = Rd;
3008 let Inst{11-0} = shift;
3011 let isMoveImm = 1 in
3012 def MOVCCi16 : AI1<0b1000, (outs GPR:$Rd), (ins GPR:$false, movt_imm:$imm),
3014 "movw", "\t$Rd, $imm",
3016 RegConstraint<"$false = $Rd">, Requires<[IsARM, HasV6T2]>,
3022 let Inst{19-16} = imm{15-12};
3023 let Inst{15-12} = Rd;
3024 let Inst{11-0} = imm{11-0};
3027 let isMoveImm = 1 in
3028 def MOVCCi : AI1<0b1101, (outs GPR:$Rd),
3029 (ins GPR:$false, so_imm:$imm), DPFrm, IIC_iCMOVi,
3030 "mov", "\t$Rd, $imm",
3031 [/*(set GPR:$Rd, (ARMcmov GPR:$false, so_imm:$imm, imm:$cc, CCR:$ccr))*/]>,
3032 RegConstraint<"$false = $Rd">, UnaryDP {
3037 let Inst{19-16} = 0b0000;
3038 let Inst{15-12} = Rd;
3039 let Inst{11-0} = imm;
3042 // Two instruction predicate mov immediate.
3043 let isMoveImm = 1 in
3044 def MOVCCi32imm : PseudoInst<(outs GPR:$Rd),
3045 (ins GPR:$false, i32imm:$src, pred:$p),
3046 IIC_iCMOVix2, []>, RegConstraint<"$false = $Rd">;
3048 let isMoveImm = 1 in
3049 def MVNCCi : AI1<0b1111, (outs GPR:$Rd),
3050 (ins GPR:$false, so_imm:$imm), DPFrm, IIC_iCMOVi,
3051 "mvn", "\t$Rd, $imm",
3052 [/*(set GPR:$Rd, (ARMcmov GPR:$false, so_imm_not:$imm, imm:$cc, CCR:$ccr))*/]>,
3053 RegConstraint<"$false = $Rd">, UnaryDP {
3058 let Inst{19-16} = 0b0000;
3059 let Inst{15-12} = Rd;
3060 let Inst{11-0} = imm;
3062 } // neverHasSideEffects
3064 //===----------------------------------------------------------------------===//
3065 // Atomic operations intrinsics
3068 def memb_opt : Operand<i32> {
3069 let PrintMethod = "printMemBOption";
3072 // memory barriers protect the atomic sequences
3073 let hasSideEffects = 1 in {
3074 def DMB : AInoP<(outs), (ins memb_opt:$opt), MiscFrm, NoItinerary,
3075 "dmb", "\t$opt", [(ARMMemBarrier (i32 imm:$opt))]>,
3076 Requires<[IsARM, HasDB]> {
3078 let Inst{31-4} = 0xf57ff05;
3079 let Inst{3-0} = opt;
3082 def DMB_MCR : AInoP<(outs), (ins GPR:$zero), MiscFrm, NoItinerary,
3083 "mcr", "\tp15, 0, $zero, c7, c10, 5",
3084 [(ARMMemBarrierMCR GPR:$zero)]>,
3085 Requires<[IsARM, HasV6]> {
3086 // FIXME: add encoding
3090 def DSB : AInoP<(outs), (ins memb_opt:$opt), MiscFrm, NoItinerary,
3092 [/* For disassembly only; pattern left blank */]>,
3093 Requires<[IsARM, HasDB]> {
3095 let Inst{31-4} = 0xf57ff04;
3096 let Inst{3-0} = opt;
3099 // ISB has only full system option -- for disassembly only
3100 def ISB : AInoP<(outs), (ins), MiscFrm, NoItinerary, "isb", "", []>,
3101 Requires<[IsARM, HasDB]> {
3102 let Inst{31-4} = 0xf57ff06;
3103 let Inst{3-0} = 0b1111;
3106 let usesCustomInserter = 1 in {
3107 let Uses = [CPSR] in {
3108 def ATOMIC_LOAD_ADD_I8 : PseudoInst<
3109 (outs GPR:$dst), (ins GPR:$ptr, GPR:$incr), NoItinerary,
3110 [(set GPR:$dst, (atomic_load_add_8 GPR:$ptr, GPR:$incr))]>;
3111 def ATOMIC_LOAD_SUB_I8 : PseudoInst<
3112 (outs GPR:$dst), (ins GPR:$ptr, GPR:$incr), NoItinerary,
3113 [(set GPR:$dst, (atomic_load_sub_8 GPR:$ptr, GPR:$incr))]>;
3114 def ATOMIC_LOAD_AND_I8 : PseudoInst<
3115 (outs GPR:$dst), (ins GPR:$ptr, GPR:$incr), NoItinerary,
3116 [(set GPR:$dst, (atomic_load_and_8 GPR:$ptr, GPR:$incr))]>;
3117 def ATOMIC_LOAD_OR_I8 : PseudoInst<
3118 (outs GPR:$dst), (ins GPR:$ptr, GPR:$incr), NoItinerary,
3119 [(set GPR:$dst, (atomic_load_or_8 GPR:$ptr, GPR:$incr))]>;
3120 def ATOMIC_LOAD_XOR_I8 : PseudoInst<
3121 (outs GPR:$dst), (ins GPR:$ptr, GPR:$incr), NoItinerary,
3122 [(set GPR:$dst, (atomic_load_xor_8 GPR:$ptr, GPR:$incr))]>;
3123 def ATOMIC_LOAD_NAND_I8 : PseudoInst<
3124 (outs GPR:$dst), (ins GPR:$ptr, GPR:$incr), NoItinerary,
3125 [(set GPR:$dst, (atomic_load_nand_8 GPR:$ptr, GPR:$incr))]>;
3126 def ATOMIC_LOAD_ADD_I16 : PseudoInst<
3127 (outs GPR:$dst), (ins GPR:$ptr, GPR:$incr), NoItinerary,
3128 [(set GPR:$dst, (atomic_load_add_16 GPR:$ptr, GPR:$incr))]>;
3129 def ATOMIC_LOAD_SUB_I16 : PseudoInst<
3130 (outs GPR:$dst), (ins GPR:$ptr, GPR:$incr), NoItinerary,
3131 [(set GPR:$dst, (atomic_load_sub_16 GPR:$ptr, GPR:$incr))]>;
3132 def ATOMIC_LOAD_AND_I16 : PseudoInst<
3133 (outs GPR:$dst), (ins GPR:$ptr, GPR:$incr), NoItinerary,
3134 [(set GPR:$dst, (atomic_load_and_16 GPR:$ptr, GPR:$incr))]>;
3135 def ATOMIC_LOAD_OR_I16 : PseudoInst<
3136 (outs GPR:$dst), (ins GPR:$ptr, GPR:$incr), NoItinerary,
3137 [(set GPR:$dst, (atomic_load_or_16 GPR:$ptr, GPR:$incr))]>;
3138 def ATOMIC_LOAD_XOR_I16 : PseudoInst<
3139 (outs GPR:$dst), (ins GPR:$ptr, GPR:$incr), NoItinerary,
3140 [(set GPR:$dst, (atomic_load_xor_16 GPR:$ptr, GPR:$incr))]>;
3141 def ATOMIC_LOAD_NAND_I16 : PseudoInst<
3142 (outs GPR:$dst), (ins GPR:$ptr, GPR:$incr), NoItinerary,
3143 [(set GPR:$dst, (atomic_load_nand_16 GPR:$ptr, GPR:$incr))]>;
3144 def ATOMIC_LOAD_ADD_I32 : PseudoInst<
3145 (outs GPR:$dst), (ins GPR:$ptr, GPR:$incr), NoItinerary,
3146 [(set GPR:$dst, (atomic_load_add_32 GPR:$ptr, GPR:$incr))]>;
3147 def ATOMIC_LOAD_SUB_I32 : PseudoInst<
3148 (outs GPR:$dst), (ins GPR:$ptr, GPR:$incr), NoItinerary,
3149 [(set GPR:$dst, (atomic_load_sub_32 GPR:$ptr, GPR:$incr))]>;
3150 def ATOMIC_LOAD_AND_I32 : PseudoInst<
3151 (outs GPR:$dst), (ins GPR:$ptr, GPR:$incr), NoItinerary,
3152 [(set GPR:$dst, (atomic_load_and_32 GPR:$ptr, GPR:$incr))]>;
3153 def ATOMIC_LOAD_OR_I32 : PseudoInst<
3154 (outs GPR:$dst), (ins GPR:$ptr, GPR:$incr), NoItinerary,
3155 [(set GPR:$dst, (atomic_load_or_32 GPR:$ptr, GPR:$incr))]>;
3156 def ATOMIC_LOAD_XOR_I32 : PseudoInst<
3157 (outs GPR:$dst), (ins GPR:$ptr, GPR:$incr), NoItinerary,
3158 [(set GPR:$dst, (atomic_load_xor_32 GPR:$ptr, GPR:$incr))]>;
3159 def ATOMIC_LOAD_NAND_I32 : PseudoInst<
3160 (outs GPR:$dst), (ins GPR:$ptr, GPR:$incr), NoItinerary,
3161 [(set GPR:$dst, (atomic_load_nand_32 GPR:$ptr, GPR:$incr))]>;
3163 def ATOMIC_SWAP_I8 : PseudoInst<
3164 (outs GPR:$dst), (ins GPR:$ptr, GPR:$new), NoItinerary,
3165 [(set GPR:$dst, (atomic_swap_8 GPR:$ptr, GPR:$new))]>;
3166 def ATOMIC_SWAP_I16 : PseudoInst<
3167 (outs GPR:$dst), (ins GPR:$ptr, GPR:$new), NoItinerary,
3168 [(set GPR:$dst, (atomic_swap_16 GPR:$ptr, GPR:$new))]>;
3169 def ATOMIC_SWAP_I32 : PseudoInst<
3170 (outs GPR:$dst), (ins GPR:$ptr, GPR:$new), NoItinerary,
3171 [(set GPR:$dst, (atomic_swap_32 GPR:$ptr, GPR:$new))]>;
3173 def ATOMIC_CMP_SWAP_I8 : PseudoInst<
3174 (outs GPR:$dst), (ins GPR:$ptr, GPR:$old, GPR:$new), NoItinerary,
3175 [(set GPR:$dst, (atomic_cmp_swap_8 GPR:$ptr, GPR:$old, GPR:$new))]>;
3176 def ATOMIC_CMP_SWAP_I16 : PseudoInst<
3177 (outs GPR:$dst), (ins GPR:$ptr, GPR:$old, GPR:$new), NoItinerary,
3178 [(set GPR:$dst, (atomic_cmp_swap_16 GPR:$ptr, GPR:$old, GPR:$new))]>;
3179 def ATOMIC_CMP_SWAP_I32 : PseudoInst<
3180 (outs GPR:$dst), (ins GPR:$ptr, GPR:$old, GPR:$new), NoItinerary,
3181 [(set GPR:$dst, (atomic_cmp_swap_32 GPR:$ptr, GPR:$old, GPR:$new))]>;
3185 let mayLoad = 1 in {
3186 def LDREXB : AIldrex<0b10, (outs GPR:$Rt), (ins GPR:$Rn), NoItinerary,
3187 "ldrexb", "\t$Rt, [$Rn]",
3189 def LDREXH : AIldrex<0b11, (outs GPR:$Rt), (ins GPR:$Rn), NoItinerary,
3190 "ldrexh", "\t$Rt, [$Rn]",
3192 def LDREX : AIldrex<0b00, (outs GPR:$Rt), (ins GPR:$Rn), NoItinerary,
3193 "ldrex", "\t$Rt, [$Rn]",
3195 def LDREXD : AIldrex<0b01, (outs GPR:$Rt, GPR:$Rt2), (ins GPR:$Rn),
3197 "ldrexd", "\t$Rt, $Rt2, [$Rn]",
3201 let mayStore = 1, Constraints = "@earlyclobber $Rd" in {
3202 def STREXB : AIstrex<0b10, (outs GPR:$Rd), (ins GPR:$src, GPR:$Rn),
3204 "strexb", "\t$Rd, $src, [$Rn]",
3206 def STREXH : AIstrex<0b11, (outs GPR:$Rd), (ins GPR:$Rt, GPR:$Rn),
3208 "strexh", "\t$Rd, $Rt, [$Rn]",
3210 def STREX : AIstrex<0b00, (outs GPR:$Rd), (ins GPR:$Rt, GPR:$Rn),
3212 "strex", "\t$Rd, $Rt, [$Rn]",
3214 def STREXD : AIstrex<0b01, (outs GPR:$Rd),
3215 (ins GPR:$Rt, GPR:$Rt2, GPR:$Rn),
3217 "strexd", "\t$Rd, $Rt, $Rt2, [$Rn]",
3221 // Clear-Exclusive is for disassembly only.
3222 def CLREX : AXI<(outs), (ins), MiscFrm, NoItinerary, "clrex",
3223 [/* For disassembly only; pattern left blank */]>,
3224 Requires<[IsARM, HasV7]> {
3225 let Inst{31-0} = 0b11110101011111111111000000011111;
3228 // SWP/SWPB are deprecated in V6/V7 and for disassembly only.
3229 let mayLoad = 1 in {
3230 def SWP : AIswp<0, (outs GPR:$Rt), (ins GPR:$Rt2, GPR:$Rn), "swp",
3231 [/* For disassembly only; pattern left blank */]>;
3232 def SWPB : AIswp<1, (outs GPR:$Rt), (ins GPR:$Rt2, GPR:$Rn), "swpb",
3233 [/* For disassembly only; pattern left blank */]>;
3236 //===----------------------------------------------------------------------===//
3240 // __aeabi_read_tp preserves the registers r1-r3.
3241 // FIXME: This needs to be a pseudo of some sort so that we can get the
3242 // encoding right, complete with fixup for the aeabi_read_tp function.
3244 Defs = [R0, R12, LR, CPSR] in {
3245 def TPsoft : ABXI<0b1011, (outs), (ins), IIC_Br,
3246 "bl\t__aeabi_read_tp",
3247 [(set R0, ARMthread_pointer)]>;
3250 //===----------------------------------------------------------------------===//
3251 // SJLJ Exception handling intrinsics
3252 // eh_sjlj_setjmp() is an instruction sequence to store the return
3253 // address and save #0 in R0 for the non-longjmp case.
3254 // Since by its nature we may be coming from some other function to get
3255 // here, and we're using the stack frame for the containing function to
3256 // save/restore registers, we can't keep anything live in regs across
3257 // the eh_sjlj_setjmp(), else it will almost certainly have been tromped upon
3258 // when we get here from a longjmp(). We force everthing out of registers
3259 // except for our own input by listing the relevant registers in Defs. By
3260 // doing so, we also cause the prologue/epilogue code to actively preserve
3261 // all of the callee-saved resgisters, which is exactly what we want.
3262 // A constant value is passed in $val, and we use the location as a scratch.
3264 // These are pseudo-instructions and are lowered to individual MC-insts, so
3265 // no encoding information is necessary.
3267 [ R0, R1, R2, R3, R4, R5, R6, R7, R8, R9, R10, R11, R12, LR, D0,
3268 D1, D2, D3, D4, D5, D6, D7, D8, D9, D10, D11, D12, D13, D14, D15,
3269 D16, D17, D18, D19, D20, D21, D22, D23, D24, D25, D26, D27, D28, D29, D30,
3270 D31 ], hasSideEffects = 1, isBarrier = 1 in {
3271 def Int_eh_sjlj_setjmp : XI<(outs), (ins GPR:$src, GPR:$val),
3272 AddrModeNone, SizeSpecial, IndexModeNone,
3273 Pseudo, NoItinerary, "", "",
3274 [(set R0, (ARMeh_sjlj_setjmp GPR:$src, GPR:$val))]>,
3275 Requires<[IsARM, HasVFP2]>;
3279 [ R0, R1, R2, R3, R4, R5, R6, R7, R8, R9, R10, R11, R12, LR ],
3280 hasSideEffects = 1, isBarrier = 1 in {
3281 def Int_eh_sjlj_setjmp_nofp : XI<(outs), (ins GPR:$src, GPR:$val),
3282 AddrModeNone, SizeSpecial, IndexModeNone,
3283 Pseudo, NoItinerary, "", "",
3284 [(set R0, (ARMeh_sjlj_setjmp GPR:$src, GPR:$val))]>,
3285 Requires<[IsARM, NoVFP]>;
3288 // FIXME: Non-Darwin version(s)
3289 let isBarrier = 1, hasSideEffects = 1, isTerminator = 1,
3290 Defs = [ R7, LR, SP ] in {
3291 def Int_eh_sjlj_longjmp : XI<(outs), (ins GPR:$src, GPR:$scratch),
3292 AddrModeNone, SizeSpecial, IndexModeNone,
3293 Pseudo, NoItinerary, "", "",
3294 [(ARMeh_sjlj_longjmp GPR:$src, GPR:$scratch)]>,
3295 Requires<[IsARM, IsDarwin]>;
3298 // eh.sjlj.dispatchsetup pseudo-instruction.
3299 // This pseudo is used for ARM, Thumb1 and Thumb2. Any differences are
3300 // handled when the pseudo is expanded (which happens before any passes
3301 // that need the instruction size).
3302 let isBarrier = 1, hasSideEffects = 1 in
3303 def Int_eh_sjlj_dispatchsetup :
3304 PseudoInst<(outs), (ins GPR:$src), NoItinerary,
3305 [(ARMeh_sjlj_dispatchsetup GPR:$src)]>,
3306 Requires<[IsDarwin]>;
3308 //===----------------------------------------------------------------------===//
3309 // Non-Instruction Patterns
3312 // Large immediate handling.
3314 // 32-bit immediate using two piece so_imms or movw + movt.
3315 // This is a single pseudo instruction, the benefit is that it can be remat'd
3316 // as a single unit instead of having to handle reg inputs.
3317 // FIXME: Remove this when we can do generalized remat.
3318 let isReMaterializable = 1, isMoveImm = 1 in
3319 def MOVi32imm : PseudoInst<(outs GPR:$dst), (ins i32imm:$src), IIC_iMOVix2,
3320 [(set GPR:$dst, (arm_i32imm:$src))]>,
3323 // ConstantPool, GlobalAddress, and JumpTable
3324 def : ARMPat<(ARMWrapper tglobaladdr :$dst), (LEApcrel tglobaladdr :$dst)>,
3325 Requires<[IsARM, DontUseMovt]>;
3326 def : ARMPat<(ARMWrapper tconstpool :$dst), (LEApcrel tconstpool :$dst)>;
3327 def : ARMPat<(ARMWrapper tglobaladdr :$dst), (MOVi32imm tglobaladdr :$dst)>,
3328 Requires<[IsARM, UseMovt]>;
3329 def : ARMPat<(ARMWrapperJT tjumptable:$dst, imm:$id),
3330 (LEApcrelJT tjumptable:$dst, imm:$id)>;
3332 // TODO: add,sub,and, 3-instr forms?
3335 def : ARMPat<(ARMtcret tcGPR:$dst),
3336 (TCRETURNri tcGPR:$dst)>, Requires<[IsDarwin]>;
3338 def : ARMPat<(ARMtcret (i32 tglobaladdr:$dst)),
3339 (TCRETURNdi texternalsym:$dst)>, Requires<[IsDarwin]>;
3341 def : ARMPat<(ARMtcret (i32 texternalsym:$dst)),
3342 (TCRETURNdi texternalsym:$dst)>, Requires<[IsDarwin]>;
3344 def : ARMPat<(ARMtcret tcGPR:$dst),
3345 (TCRETURNriND tcGPR:$dst)>, Requires<[IsNotDarwin]>;
3347 def : ARMPat<(ARMtcret (i32 tglobaladdr:$dst)),
3348 (TCRETURNdiND texternalsym:$dst)>, Requires<[IsNotDarwin]>;
3350 def : ARMPat<(ARMtcret (i32 texternalsym:$dst)),
3351 (TCRETURNdiND texternalsym:$dst)>, Requires<[IsNotDarwin]>;
3354 def : ARMPat<(ARMcall texternalsym:$func), (BL texternalsym:$func)>,
3355 Requires<[IsARM, IsNotDarwin]>;
3356 def : ARMPat<(ARMcall texternalsym:$func), (BLr9 texternalsym:$func)>,
3357 Requires<[IsARM, IsDarwin]>;
3359 // zextload i1 -> zextload i8
3360 def : ARMPat<(zextloadi1 addrmode_imm12:$addr), (LDRBi12 addrmode_imm12:$addr)>;
3361 def : ARMPat<(zextloadi1 ldst_so_reg:$addr), (LDRBrs ldst_so_reg:$addr)>;
3363 // extload -> zextload
3364 def : ARMPat<(extloadi1 addrmode_imm12:$addr), (LDRBi12 addrmode_imm12:$addr)>;
3365 def : ARMPat<(extloadi1 ldst_so_reg:$addr), (LDRBrs ldst_so_reg:$addr)>;
3366 def : ARMPat<(extloadi8 addrmode_imm12:$addr), (LDRBi12 addrmode_imm12:$addr)>;
3367 def : ARMPat<(extloadi8 ldst_so_reg:$addr), (LDRBrs ldst_so_reg:$addr)>;
3369 def : ARMPat<(extloadi16 addrmode3:$addr), (LDRH addrmode3:$addr)>;
3371 def : ARMPat<(extloadi8 addrmodepc:$addr), (PICLDRB addrmodepc:$addr)>;
3372 def : ARMPat<(extloadi16 addrmodepc:$addr), (PICLDRH addrmodepc:$addr)>;
3375 def : ARMV5TEPat<(mul (sra (shl GPR:$a, (i32 16)), (i32 16)),
3376 (sra (shl GPR:$b, (i32 16)), (i32 16))),
3377 (SMULBB GPR:$a, GPR:$b)>;
3378 def : ARMV5TEPat<(mul sext_16_node:$a, sext_16_node:$b),
3379 (SMULBB GPR:$a, GPR:$b)>;
3380 def : ARMV5TEPat<(mul (sra (shl GPR:$a, (i32 16)), (i32 16)),
3381 (sra GPR:$b, (i32 16))),
3382 (SMULBT GPR:$a, GPR:$b)>;
3383 def : ARMV5TEPat<(mul sext_16_node:$a, (sra GPR:$b, (i32 16))),
3384 (SMULBT GPR:$a, GPR:$b)>;
3385 def : ARMV5TEPat<(mul (sra GPR:$a, (i32 16)),
3386 (sra (shl GPR:$b, (i32 16)), (i32 16))),
3387 (SMULTB GPR:$a, GPR:$b)>;
3388 def : ARMV5TEPat<(mul (sra GPR:$a, (i32 16)), sext_16_node:$b),
3389 (SMULTB GPR:$a, GPR:$b)>;
3390 def : ARMV5TEPat<(sra (mul GPR:$a, (sra (shl GPR:$b, (i32 16)), (i32 16))),
3392 (SMULWB GPR:$a, GPR:$b)>;
3393 def : ARMV5TEPat<(sra (mul GPR:$a, sext_16_node:$b), (i32 16)),
3394 (SMULWB GPR:$a, GPR:$b)>;
3396 def : ARMV5TEPat<(add GPR:$acc,
3397 (mul (sra (shl GPR:$a, (i32 16)), (i32 16)),
3398 (sra (shl GPR:$b, (i32 16)), (i32 16)))),
3399 (SMLABB GPR:$a, GPR:$b, GPR:$acc)>;
3400 def : ARMV5TEPat<(add GPR:$acc,
3401 (mul sext_16_node:$a, sext_16_node:$b)),
3402 (SMLABB GPR:$a, GPR:$b, GPR:$acc)>;
3403 def : ARMV5TEPat<(add GPR:$acc,
3404 (mul (sra (shl GPR:$a, (i32 16)), (i32 16)),
3405 (sra GPR:$b, (i32 16)))),
3406 (SMLABT GPR:$a, GPR:$b, GPR:$acc)>;
3407 def : ARMV5TEPat<(add GPR:$acc,
3408 (mul sext_16_node:$a, (sra GPR:$b, (i32 16)))),
3409 (SMLABT GPR:$a, GPR:$b, GPR:$acc)>;
3410 def : ARMV5TEPat<(add GPR:$acc,
3411 (mul (sra GPR:$a, (i32 16)),
3412 (sra (shl GPR:$b, (i32 16)), (i32 16)))),
3413 (SMLATB GPR:$a, GPR:$b, GPR:$acc)>;
3414 def : ARMV5TEPat<(add GPR:$acc,
3415 (mul (sra GPR:$a, (i32 16)), sext_16_node:$b)),
3416 (SMLATB GPR:$a, GPR:$b, GPR:$acc)>;
3417 def : ARMV5TEPat<(add GPR:$acc,
3418 (sra (mul GPR:$a, (sra (shl GPR:$b, (i32 16)), (i32 16))),
3420 (SMLAWB GPR:$a, GPR:$b, GPR:$acc)>;
3421 def : ARMV5TEPat<(add GPR:$acc,
3422 (sra (mul GPR:$a, sext_16_node:$b), (i32 16))),
3423 (SMLAWB GPR:$a, GPR:$b, GPR:$acc)>;
3425 //===----------------------------------------------------------------------===//
3429 include "ARMInstrThumb.td"
3431 //===----------------------------------------------------------------------===//
3435 include "ARMInstrThumb2.td"
3437 //===----------------------------------------------------------------------===//
3438 // Floating Point Support
3441 include "ARMInstrVFP.td"
3443 //===----------------------------------------------------------------------===//
3444 // Advanced SIMD (NEON) Support
3447 include "ARMInstrNEON.td"
3449 //===----------------------------------------------------------------------===//
3450 // Coprocessor Instructions. For disassembly only.
3453 def CDP : ABI<0b1110, (outs), (ins nohash_imm:$cop, i32imm:$opc1,
3454 nohash_imm:$CRd, nohash_imm:$CRn, nohash_imm:$CRm, i32imm:$opc2),
3455 NoItinerary, "cdp", "\tp$cop, $opc1, cr$CRd, cr$CRn, cr$CRm, $opc2",
3456 [/* For disassembly only; pattern left blank */]> {
3460 def CDP2 : ABXI<0b1110, (outs), (ins nohash_imm:$cop, i32imm:$opc1,
3461 nohash_imm:$CRd, nohash_imm:$CRn, nohash_imm:$CRm, i32imm:$opc2),
3462 NoItinerary, "cdp2\tp$cop, $opc1, cr$CRd, cr$CRn, cr$CRm, $opc2",
3463 [/* For disassembly only; pattern left blank */]> {
3464 let Inst{31-28} = 0b1111;
3468 class ACI<dag oops, dag iops, string opc, string asm>
3469 : I<oops, iops, AddrModeNone, Size4Bytes, IndexModeNone, BrFrm, NoItinerary,
3470 opc, asm, "", [/* For disassembly only; pattern left blank */]> {
3471 let Inst{27-25} = 0b110;
3474 multiclass LdStCop<bits<4> op31_28, bit load, string opc> {
3476 def _OFFSET : ACI<(outs),
3477 (ins nohash_imm:$cop, nohash_imm:$CRd, addrmode2:$addr),
3478 opc, "\tp$cop, cr$CRd, $addr"> {
3479 let Inst{31-28} = op31_28;
3480 let Inst{24} = 1; // P = 1
3481 let Inst{21} = 0; // W = 0
3482 let Inst{22} = 0; // D = 0
3483 let Inst{20} = load;
3486 def _PRE : ACI<(outs),
3487 (ins nohash_imm:$cop, nohash_imm:$CRd, addrmode2:$addr),
3488 opc, "\tp$cop, cr$CRd, $addr!"> {
3489 let Inst{31-28} = op31_28;
3490 let Inst{24} = 1; // P = 1
3491 let Inst{21} = 1; // W = 1
3492 let Inst{22} = 0; // D = 0
3493 let Inst{20} = load;
3496 def _POST : ACI<(outs),
3497 (ins nohash_imm:$cop, nohash_imm:$CRd, GPR:$base, am2offset:$offset),
3498 opc, "\tp$cop, cr$CRd, [$base], $offset"> {
3499 let Inst{31-28} = op31_28;
3500 let Inst{24} = 0; // P = 0
3501 let Inst{21} = 1; // W = 1
3502 let Inst{22} = 0; // D = 0
3503 let Inst{20} = load;
3506 def _OPTION : ACI<(outs),
3507 (ins nohash_imm:$cop, nohash_imm:$CRd, GPR:$base, i32imm:$option),
3508 opc, "\tp$cop, cr$CRd, [$base], $option"> {
3509 let Inst{31-28} = op31_28;
3510 let Inst{24} = 0; // P = 0
3511 let Inst{23} = 1; // U = 1
3512 let Inst{21} = 0; // W = 0
3513 let Inst{22} = 0; // D = 0
3514 let Inst{20} = load;
3517 def L_OFFSET : ACI<(outs),
3518 (ins nohash_imm:$cop, nohash_imm:$CRd, addrmode2:$addr),
3519 !strconcat(opc, "l"), "\tp$cop, cr$CRd, $addr"> {
3520 let Inst{31-28} = op31_28;
3521 let Inst{24} = 1; // P = 1
3522 let Inst{21} = 0; // W = 0
3523 let Inst{22} = 1; // D = 1
3524 let Inst{20} = load;
3527 def L_PRE : ACI<(outs),
3528 (ins nohash_imm:$cop, nohash_imm:$CRd, addrmode2:$addr),
3529 !strconcat(opc, "l"), "\tp$cop, cr$CRd, $addr!"> {
3530 let Inst{31-28} = op31_28;
3531 let Inst{24} = 1; // P = 1
3532 let Inst{21} = 1; // W = 1
3533 let Inst{22} = 1; // D = 1
3534 let Inst{20} = load;
3537 def L_POST : ACI<(outs),
3538 (ins nohash_imm:$cop, nohash_imm:$CRd, GPR:$base, am2offset:$offset),
3539 !strconcat(opc, "l"), "\tp$cop, cr$CRd, [$base], $offset"> {
3540 let Inst{31-28} = op31_28;
3541 let Inst{24} = 0; // P = 0
3542 let Inst{21} = 1; // W = 1
3543 let Inst{22} = 1; // D = 1
3544 let Inst{20} = load;
3547 def L_OPTION : ACI<(outs),
3548 (ins nohash_imm:$cop, nohash_imm:$CRd, GPR:$base, nohash_imm:$option),
3549 !strconcat(opc, "l"), "\tp$cop, cr$CRd, [$base], $option"> {
3550 let Inst{31-28} = op31_28;
3551 let Inst{24} = 0; // P = 0
3552 let Inst{23} = 1; // U = 1
3553 let Inst{21} = 0; // W = 0
3554 let Inst{22} = 1; // D = 1
3555 let Inst{20} = load;
3559 defm LDC : LdStCop<{?,?,?,?}, 1, "ldc">;
3560 defm LDC2 : LdStCop<0b1111, 1, "ldc2">;
3561 defm STC : LdStCop<{?,?,?,?}, 0, "stc">;
3562 defm STC2 : LdStCop<0b1111, 0, "stc2">;
3564 def MCR : ABI<0b1110, (outs), (ins nohash_imm:$cop, i32imm:$opc1,
3565 GPR:$Rt, nohash_imm:$CRn, nohash_imm:$CRm, i32imm:$opc2),
3566 NoItinerary, "mcr", "\tp$cop, $opc1, $Rt, cr$CRn, cr$CRm, $opc2",
3567 [/* For disassembly only; pattern left blank */]> {
3572 def MCR2 : ABXI<0b1110, (outs), (ins nohash_imm:$cop, i32imm:$opc1,
3573 GPR:$Rt, nohash_imm:$CRn, nohash_imm:$CRm, i32imm:$opc2),
3574 NoItinerary, "mcr2\tp$cop, $opc1, $Rt, cr$CRn, cr$CRm, $opc2",
3575 [/* For disassembly only; pattern left blank */]> {
3576 let Inst{31-28} = 0b1111;
3581 def MRC : ABI<0b1110, (outs), (ins nohash_imm:$cop, i32imm:$opc1,
3582 GPR:$Rt, nohash_imm:$CRn, nohash_imm:$CRm, i32imm:$opc2),
3583 NoItinerary, "mrc", "\tp$cop, $opc1, $Rt, cr$CRn, cr$CRm, $opc2",
3584 [/* For disassembly only; pattern left blank */]> {
3589 def MRC2 : ABXI<0b1110, (outs), (ins nohash_imm:$cop, i32imm:$opc1,
3590 GPR:$Rt, nohash_imm:$CRn, nohash_imm:$CRm, i32imm:$opc2),
3591 NoItinerary, "mrc2\tp$cop, $opc1, $Rt, cr$CRn, cr$CRm, $opc2",
3592 [/* For disassembly only; pattern left blank */]> {
3593 let Inst{31-28} = 0b1111;
3598 def MCRR : ABI<0b1100, (outs), (ins nohash_imm:$cop, i32imm:$opc,
3599 GPR:$Rt, GPR:$Rt2, nohash_imm:$CRm),
3600 NoItinerary, "mcrr", "\tp$cop, $opc, $Rt, $Rt2, cr$CRm",
3601 [/* For disassembly only; pattern left blank */]> {
3602 let Inst{23-20} = 0b0100;
3605 def MCRR2 : ABXI<0b1100, (outs), (ins nohash_imm:$cop, i32imm:$opc,
3606 GPR:$Rt, GPR:$Rt2, nohash_imm:$CRm),
3607 NoItinerary, "mcrr2\tp$cop, $opc, $Rt, $Rt2, cr$CRm",
3608 [/* For disassembly only; pattern left blank */]> {
3609 let Inst{31-28} = 0b1111;
3610 let Inst{23-20} = 0b0100;
3613 def MRRC : ABI<0b1100, (outs), (ins nohash_imm:$cop, i32imm:$opc,
3614 GPR:$Rt, GPR:$Rt2, nohash_imm:$CRm),
3615 NoItinerary, "mrrc", "\tp$cop, $opc, $Rt, $Rt2, cr$CRm",
3616 [/* For disassembly only; pattern left blank */]> {
3617 let Inst{23-20} = 0b0101;
3620 def MRRC2 : ABXI<0b1100, (outs), (ins nohash_imm:$cop, i32imm:$opc,
3621 GPR:$Rt, GPR:$Rt2, nohash_imm:$CRm),
3622 NoItinerary, "mrrc2\tp$cop, $opc, $Rt, $Rt2, cr$CRm",
3623 [/* For disassembly only; pattern left blank */]> {
3624 let Inst{31-28} = 0b1111;
3625 let Inst{23-20} = 0b0101;
3628 //===----------------------------------------------------------------------===//
3629 // Move between special register and ARM core register -- for disassembly only
3632 def MRS : ABI<0b0001,(outs GPR:$dst),(ins), NoItinerary, "mrs", "\t$dst, cpsr",
3633 [/* For disassembly only; pattern left blank */]> {
3634 let Inst{23-20} = 0b0000;
3635 let Inst{7-4} = 0b0000;
3638 def MRSsys : ABI<0b0001,(outs GPR:$dst),(ins), NoItinerary,"mrs","\t$dst, spsr",
3639 [/* For disassembly only; pattern left blank */]> {
3640 let Inst{23-20} = 0b0100;
3641 let Inst{7-4} = 0b0000;
3644 def MSR : ABI<0b0001, (outs), (ins GPR:$src, msr_mask:$mask), NoItinerary,
3645 "msr", "\tcpsr$mask, $src",
3646 [/* For disassembly only; pattern left blank */]> {
3647 let Inst{23-20} = 0b0010;
3648 let Inst{7-4} = 0b0000;
3651 def MSRi : ABI<0b0011, (outs), (ins so_imm:$a, msr_mask:$mask), NoItinerary,
3652 "msr", "\tcpsr$mask, $a",
3653 [/* For disassembly only; pattern left blank */]> {
3654 let Inst{23-20} = 0b0010;
3655 let Inst{7-4} = 0b0000;
3658 def MSRsys : ABI<0b0001, (outs), (ins GPR:$src, msr_mask:$mask), NoItinerary,
3659 "msr", "\tspsr$mask, $src",
3660 [/* For disassembly only; pattern left blank */]> {
3661 let Inst{23-20} = 0b0110;
3662 let Inst{7-4} = 0b0000;
3665 def MSRsysi : ABI<0b0011, (outs), (ins so_imm:$a, msr_mask:$mask), NoItinerary,
3666 "msr", "\tspsr$mask, $a",
3667 [/* For disassembly only; pattern left blank */]> {
3668 let Inst{23-20} = 0b0110;
3669 let Inst{7-4} = 0b0000;