1 //===- ARMInstrInfo.td - Target Description for ARM Target -*- tablegen -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file describes the ARM instructions in TableGen format.
12 //===----------------------------------------------------------------------===//
14 //===----------------------------------------------------------------------===//
15 // ARM specific DAG Nodes.
19 def SDT_ARMCallSeqStart : SDCallSeqStart<[ SDTCisVT<0, i32> ]>;
20 def SDT_ARMCallSeqEnd : SDCallSeqEnd<[ SDTCisVT<0, i32>, SDTCisVT<1, i32> ]>;
22 def SDT_ARMSaveCallPC : SDTypeProfile<0, 1, []>;
24 def SDT_ARMcall : SDTypeProfile<0, -1, [SDTCisInt<0>]>;
26 def SDT_ARMCMov : SDTypeProfile<1, 3,
27 [SDTCisSameAs<0, 1>, SDTCisSameAs<0, 2>,
30 def SDT_ARMBrcond : SDTypeProfile<0, 2,
31 [SDTCisVT<0, OtherVT>, SDTCisVT<1, i32>]>;
33 def SDT_ARMBrJT : SDTypeProfile<0, 3,
34 [SDTCisPtrTy<0>, SDTCisVT<1, i32>,
37 def SDT_ARMCmp : SDTypeProfile<0, 2, [SDTCisSameAs<0, 1>]>;
39 def SDT_ARMPICAdd : SDTypeProfile<1, 2, [SDTCisSameAs<0, 1>,
40 SDTCisPtrTy<1>, SDTCisVT<2, i32>]>;
42 def SDT_ARMThreadPointer : SDTypeProfile<1, 0, [SDTCisPtrTy<0>]>;
43 def SDT_ARMEH_SJLJ_Setjmp : SDTypeProfile<1, 1, [SDTCisInt<0>, SDTCisPtrTy<1>]>;
46 def ARMWrapper : SDNode<"ARMISD::Wrapper", SDTIntUnaryOp>;
47 def ARMWrapperJT : SDNode<"ARMISD::WrapperJT", SDTIntBinOp>;
49 def ARMcallseq_start : SDNode<"ISD::CALLSEQ_START", SDT_ARMCallSeqStart,
50 [SDNPHasChain, SDNPOutFlag]>;
51 def ARMcallseq_end : SDNode<"ISD::CALLSEQ_END", SDT_ARMCallSeqEnd,
52 [SDNPHasChain, SDNPOptInFlag, SDNPOutFlag]>;
54 def ARMcall : SDNode<"ARMISD::CALL", SDT_ARMcall,
55 [SDNPHasChain, SDNPOptInFlag, SDNPOutFlag]>;
56 def ARMcall_pred : SDNode<"ARMISD::CALL_PRED", SDT_ARMcall,
57 [SDNPHasChain, SDNPOptInFlag, SDNPOutFlag]>;
58 def ARMcall_nolink : SDNode<"ARMISD::CALL_NOLINK", SDT_ARMcall,
59 [SDNPHasChain, SDNPOptInFlag, SDNPOutFlag]>;
61 def ARMretflag : SDNode<"ARMISD::RET_FLAG", SDTNone,
62 [SDNPHasChain, SDNPOptInFlag]>;
64 def ARMcmov : SDNode<"ARMISD::CMOV", SDT_ARMCMov,
66 def ARMcneg : SDNode<"ARMISD::CNEG", SDT_ARMCMov,
69 def ARMbrcond : SDNode<"ARMISD::BRCOND", SDT_ARMBrcond,
70 [SDNPHasChain, SDNPInFlag, SDNPOutFlag]>;
72 def ARMbrjt : SDNode<"ARMISD::BR_JT", SDT_ARMBrJT,
75 def ARMcmp : SDNode<"ARMISD::CMP", SDT_ARMCmp,
78 def ARMcmpNZ : SDNode<"ARMISD::CMPNZ", SDT_ARMCmp,
81 def ARMpic_add : SDNode<"ARMISD::PIC_ADD", SDT_ARMPICAdd>;
83 def ARMsrl_flag : SDNode<"ARMISD::SRL_FLAG", SDTIntUnaryOp, [SDNPOutFlag]>;
84 def ARMsra_flag : SDNode<"ARMISD::SRA_FLAG", SDTIntUnaryOp, [SDNPOutFlag]>;
85 def ARMrrx : SDNode<"ARMISD::RRX" , SDTIntUnaryOp, [SDNPInFlag ]>;
87 def ARMthread_pointer: SDNode<"ARMISD::THREAD_POINTER", SDT_ARMThreadPointer>;
88 def ARMeh_sjlj_setjmp: SDNode<"ARMISD::EH_SJLJ_SETJMP", SDT_ARMEH_SJLJ_Setjmp>;
90 //===----------------------------------------------------------------------===//
91 // ARM Instruction Predicate Definitions.
93 def HasV5T : Predicate<"Subtarget->hasV5TOps()">;
94 def HasV5TE : Predicate<"Subtarget->hasV5TEOps()">;
95 def HasV6 : Predicate<"Subtarget->hasV6Ops()">;
96 def HasV7 : Predicate<"Subtarget->hasV7Ops()">;
97 def HasVFP2 : Predicate<"Subtarget->hasVFP2()">;
98 def HasVFP3 : Predicate<"Subtarget->hasVFP3()">;
99 def HasNEON : Predicate<"Subtarget->hasNEON()">;
100 def IsThumb : Predicate<"Subtarget->isThumb()">;
101 def IsThumb1Only : Predicate<"Subtarget->isThumb1Only()">;
102 def HasThumb2 : Predicate<"Subtarget->hasThumb2()">;
103 def IsARM : Predicate<"!Subtarget->isThumb()">;
104 def IsDarwin : Predicate<"Subtarget->isTargetDarwin()">;
105 def IsNotDarwin : Predicate<"!Subtarget->isTargetDarwin()">;
106 def CarryDefIsUnused : Predicate<"N.getNode()->hasNUsesOfValue(0, 1)">;
107 def CarryDefIsUsed : Predicate<"N.getNode()->hasAnyUseOfValue(1)">;
109 //===----------------------------------------------------------------------===//
110 // ARM Flag Definitions.
112 class RegConstraint<string C> {
113 string Constraints = C;
116 //===----------------------------------------------------------------------===//
117 // ARM specific transformation functions and pattern fragments.
120 // so_imm_XFORM - Return a so_imm value packed into the format described for
122 def so_imm_XFORM : SDNodeXForm<imm, [{
123 return CurDAG->getTargetConstant(ARM_AM::getSOImmVal(N->getZExtValue()),
127 // so_imm_neg_XFORM - Return a so_imm value packed into the format described for
128 // so_imm_neg def below.
129 def so_imm_neg_XFORM : SDNodeXForm<imm, [{
130 return CurDAG->getTargetConstant(ARM_AM::getSOImmVal(-(int)N->getZExtValue()),
134 // so_imm_not_XFORM - Return a so_imm value packed into the format described for
135 // so_imm_not def below.
136 def so_imm_not_XFORM : SDNodeXForm<imm, [{
137 return CurDAG->getTargetConstant(ARM_AM::getSOImmVal(~(int)N->getZExtValue()),
141 // rot_imm predicate - True if the 32-bit immediate is equal to 8, 16, or 24.
142 def rot_imm : PatLeaf<(i32 imm), [{
143 int32_t v = (int32_t)N->getZExtValue();
144 return v == 8 || v == 16 || v == 24;
147 /// imm1_15 predicate - True if the 32-bit immediate is in the range [1,15].
148 def imm1_15 : PatLeaf<(i32 imm), [{
149 return (int32_t)N->getZExtValue() >= 1 && (int32_t)N->getZExtValue() < 16;
152 /// imm16_31 predicate - True if the 32-bit immediate is in the range [16,31].
153 def imm16_31 : PatLeaf<(i32 imm), [{
154 return (int32_t)N->getZExtValue() >= 16 && (int32_t)N->getZExtValue() < 32;
159 return ARM_AM::getSOImmVal(-(int)N->getZExtValue()) != -1;
160 }], so_imm_neg_XFORM>;
164 return ARM_AM::getSOImmVal(~(int)N->getZExtValue()) != -1;
165 }], so_imm_not_XFORM>;
167 // sext_16_node predicate - True if the SDNode is sign-extended 16 or more bits.
168 def sext_16_node : PatLeaf<(i32 GPR:$a), [{
169 return CurDAG->ComputeNumSignBits(SDValue(N,0)) >= 17;
172 class BinOpFrag<dag res> : PatFrag<(ops node:$LHS, node:$RHS), res>;
173 class UnOpFrag <dag res> : PatFrag<(ops node:$Src), res>;
175 //===----------------------------------------------------------------------===//
176 // Operand Definitions.
180 def brtarget : Operand<OtherVT>;
182 // A list of registers separated by comma. Used by load/store multiple.
183 def reglist : Operand<i32> {
184 let PrintMethod = "printRegisterList";
187 // An operand for the CONSTPOOL_ENTRY pseudo-instruction.
188 def cpinst_operand : Operand<i32> {
189 let PrintMethod = "printCPInstOperand";
192 def jtblock_operand : Operand<i32> {
193 let PrintMethod = "printJTBlockOperand";
197 def pclabel : Operand<i32> {
198 let PrintMethod = "printPCLabel";
201 // shifter_operand operands: so_reg and so_imm.
202 def so_reg : Operand<i32>, // reg reg imm
203 ComplexPattern<i32, 3, "SelectShifterOperandReg",
204 [shl,srl,sra,rotr]> {
205 let PrintMethod = "printSORegOperand";
206 let MIOperandInfo = (ops GPR, GPR, i32imm);
209 // so_imm - Match a 32-bit shifter_operand immediate operand, which is an
210 // 8-bit immediate rotated by an arbitrary number of bits. so_imm values are
211 // represented in the imm field in the same 12-bit form that they are encoded
212 // into so_imm instructions: the 8-bit immediate is the least significant bits
213 // [bits 0-7], the 4-bit shift amount is the next 4 bits [bits 8-11].
214 def so_imm : Operand<i32>,
216 [{ return ARM_AM::getSOImmVal(N->getZExtValue()) != -1; }],
218 let PrintMethod = "printSOImmOperand";
221 // Break so_imm's up into two pieces. This handles immediates with up to 16
222 // bits set in them. This uses so_imm2part to match and so_imm2part_[12] to
223 // get the first/second pieces.
224 def so_imm2part : Operand<i32>,
226 return ARM_AM::isSOImmTwoPartVal((unsigned)N->getZExtValue());
228 let PrintMethod = "printSOImm2PartOperand";
231 def so_imm2part_1 : SDNodeXForm<imm, [{
232 unsigned V = ARM_AM::getSOImmTwoPartFirst((unsigned)N->getZExtValue());
233 return CurDAG->getTargetConstant(ARM_AM::getSOImmVal(V), MVT::i32);
236 def so_imm2part_2 : SDNodeXForm<imm, [{
237 unsigned V = ARM_AM::getSOImmTwoPartSecond((unsigned)N->getZExtValue());
238 return CurDAG->getTargetConstant(ARM_AM::getSOImmVal(V), MVT::i32);
242 // Define ARM specific addressing modes.
244 // addrmode2 := reg +/- reg shop imm
245 // addrmode2 := reg +/- imm12
247 def addrmode2 : Operand<i32>,
248 ComplexPattern<i32, 3, "SelectAddrMode2", []> {
249 let PrintMethod = "printAddrMode2Operand";
250 let MIOperandInfo = (ops GPR:$base, GPR:$offsreg, i32imm:$offsimm);
253 def am2offset : Operand<i32>,
254 ComplexPattern<i32, 2, "SelectAddrMode2Offset", []> {
255 let PrintMethod = "printAddrMode2OffsetOperand";
256 let MIOperandInfo = (ops GPR, i32imm);
259 // addrmode3 := reg +/- reg
260 // addrmode3 := reg +/- imm8
262 def addrmode3 : Operand<i32>,
263 ComplexPattern<i32, 3, "SelectAddrMode3", []> {
264 let PrintMethod = "printAddrMode3Operand";
265 let MIOperandInfo = (ops GPR:$base, GPR:$offsreg, i32imm:$offsimm);
268 def am3offset : Operand<i32>,
269 ComplexPattern<i32, 2, "SelectAddrMode3Offset", []> {
270 let PrintMethod = "printAddrMode3OffsetOperand";
271 let MIOperandInfo = (ops GPR, i32imm);
274 // addrmode4 := reg, <mode|W>
276 def addrmode4 : Operand<i32>,
277 ComplexPattern<i32, 2, "", []> {
278 let PrintMethod = "printAddrMode4Operand";
279 let MIOperandInfo = (ops GPR, i32imm);
282 // addrmode5 := reg +/- imm8*4
284 def addrmode5 : Operand<i32>,
285 ComplexPattern<i32, 2, "SelectAddrMode5", []> {
286 let PrintMethod = "printAddrMode5Operand";
287 let MIOperandInfo = (ops GPR, i32imm);
290 // addrmodepc := pc + reg
292 def addrmodepc : Operand<i32>,
293 ComplexPattern<i32, 2, "SelectAddrModePC", []> {
294 let PrintMethod = "printAddrModePCOperand";
295 let MIOperandInfo = (ops GPR, i32imm);
298 // ARM Predicate operand. Default to 14 = always (AL). Second part is CC
299 // register whose default is 0 (no register).
300 def pred : PredicateOperand<OtherVT, (ops i32imm, CCR),
301 (ops (i32 14), (i32 zero_reg))> {
302 let PrintMethod = "printPredicateOperand";
305 // Conditional code result for instructions whose 's' bit is set, e.g. subs.
307 def cc_out : OptionalDefOperand<OtherVT, (ops CCR), (ops (i32 zero_reg))> {
308 let PrintMethod = "printSBitModifierOperand";
311 //===----------------------------------------------------------------------===//
312 // ARM Instruction flags. These need to match ARMInstrInfo.h.
316 class AddrMode<bits<4> val> {
319 def AddrModeNone : AddrMode<0>;
320 def AddrMode1 : AddrMode<1>;
321 def AddrMode2 : AddrMode<2>;
322 def AddrMode3 : AddrMode<3>;
323 def AddrMode4 : AddrMode<4>;
324 def AddrMode5 : AddrMode<5>;
325 def AddrModeT1 : AddrMode<6>;
326 def AddrModeT2 : AddrMode<7>;
327 def AddrModeT4 : AddrMode<8>;
328 def AddrModeTs : AddrMode<9>;
331 class SizeFlagVal<bits<3> val> {
334 def SizeInvalid : SizeFlagVal<0>; // Unset.
335 def SizeSpecial : SizeFlagVal<1>; // Pseudo or special.
336 def Size8Bytes : SizeFlagVal<2>;
337 def Size4Bytes : SizeFlagVal<3>;
338 def Size2Bytes : SizeFlagVal<4>;
340 // Load / store index mode.
341 class IndexMode<bits<2> val> {
344 def IndexModeNone : IndexMode<0>;
345 def IndexModePre : IndexMode<1>;
346 def IndexModePost : IndexMode<2>;
348 //===----------------------------------------------------------------------===//
350 include "ARMInstrFormats.td"
352 //===----------------------------------------------------------------------===//
353 // Multiclass helpers...
356 /// AsI1_bin_irs - Defines a set of (op r, {so_imm|r|so_reg}) patterns for a
357 /// binop that produces a value.
358 multiclass AsI1_bin_irs<bits<4> opcod, string opc, PatFrag opnode> {
359 def ri : AsI1<opcod, (outs GPR:$dst), (ins GPR:$a, so_imm:$b), DPFrm,
360 opc, " $dst, $a, $b",
361 [(set GPR:$dst, (opnode GPR:$a, so_imm:$b))]>;
362 def rr : AsI1<opcod, (outs GPR:$dst), (ins GPR:$a, GPR:$b), DPFrm,
363 opc, " $dst, $a, $b",
364 [(set GPR:$dst, (opnode GPR:$a, GPR:$b))]>;
365 def rs : AsI1<opcod, (outs GPR:$dst), (ins GPR:$a, so_reg:$b), DPSoRegFrm,
366 opc, " $dst, $a, $b",
367 [(set GPR:$dst, (opnode GPR:$a, so_reg:$b))]>;
370 /// AI1_bin_s_irs - Similar to AsI1_bin_irs except it sets the 's' bit so the
371 /// instruction modifies the CSPR register.
372 let Defs = [CPSR] in {
373 multiclass AI1_bin_s_irs<bits<4> opcod, string opc, PatFrag opnode> {
374 def ri : AI1<opcod, (outs GPR:$dst), (ins GPR:$a, so_imm:$b), DPFrm,
375 opc, "s $dst, $a, $b",
376 [(set GPR:$dst, (opnode GPR:$a, so_imm:$b))]>;
377 def rr : AI1<opcod, (outs GPR:$dst), (ins GPR:$a, GPR:$b), DPFrm,
378 opc, "s $dst, $a, $b",
379 [(set GPR:$dst, (opnode GPR:$a, GPR:$b))]>;
380 def rs : AI1<opcod, (outs GPR:$dst), (ins GPR:$a, so_reg:$b), DPSoRegFrm,
381 opc, "s $dst, $a, $b",
382 [(set GPR:$dst, (opnode GPR:$a, so_reg:$b))]>;
386 /// AI1_cmp_irs - Defines a set of (op r, {so_imm|r|so_reg}) cmp / test
387 /// patterns. Similar to AsI1_bin_irs except the instruction does not produce
388 /// a explicit result, only implicitly set CPSR.
389 let Defs = [CPSR] in {
390 multiclass AI1_cmp_irs<bits<4> opcod, string opc, PatFrag opnode> {
391 def ri : AI1<opcod, (outs), (ins GPR:$a, so_imm:$b), DPFrm,
393 [(opnode GPR:$a, so_imm:$b)]>;
394 def rr : AI1<opcod, (outs), (ins GPR:$a, GPR:$b), DPFrm,
396 [(opnode GPR:$a, GPR:$b)]>;
397 def rs : AI1<opcod, (outs), (ins GPR:$a, so_reg:$b), DPSoRegFrm,
399 [(opnode GPR:$a, so_reg:$b)]>;
403 /// AI_unary_rrot - A unary operation with two forms: one whose operand is a
404 /// register and one whose operand is a register rotated by 8/16/24.
405 /// FIXME: Remove the 'r' variant. Its rot_imm is zero.
406 multiclass AI_unary_rrot<bits<8> opcod, string opc, PatFrag opnode> {
407 def r : AExtI<opcod, (outs GPR:$dst), (ins GPR:$Src),
409 [(set GPR:$dst, (opnode GPR:$Src))]>,
410 Requires<[IsARM, HasV6]> {
411 let Inst{19-16} = 0b1111;
413 def r_rot : AExtI<opcod, (outs GPR:$dst), (ins GPR:$Src, i32imm:$rot),
414 opc, " $dst, $Src, ror $rot",
415 [(set GPR:$dst, (opnode (rotr GPR:$Src, rot_imm:$rot)))]>,
416 Requires<[IsARM, HasV6]> {
417 let Inst{19-16} = 0b1111;
421 /// AI_bin_rrot - A binary operation with two forms: one whose operand is a
422 /// register and one whose operand is a register rotated by 8/16/24.
423 multiclass AI_bin_rrot<bits<8> opcod, string opc, PatFrag opnode> {
424 def rr : AExtI<opcod, (outs GPR:$dst), (ins GPR:$LHS, GPR:$RHS),
425 opc, " $dst, $LHS, $RHS",
426 [(set GPR:$dst, (opnode GPR:$LHS, GPR:$RHS))]>,
427 Requires<[IsARM, HasV6]>;
428 def rr_rot : AExtI<opcod, (outs GPR:$dst), (ins GPR:$LHS, GPR:$RHS, i32imm:$rot),
429 opc, " $dst, $LHS, $RHS, ror $rot",
430 [(set GPR:$dst, (opnode GPR:$LHS,
431 (rotr GPR:$RHS, rot_imm:$rot)))]>,
432 Requires<[IsARM, HasV6]>;
435 /// AI1_adde_sube_irs - Define instructions and patterns for adde and sube.
436 let Uses = [CPSR] in {
437 multiclass AI1_adde_sube_irs<bits<4> opcod, string opc, PatFrag opnode> {
438 def ri : AsI1<opcod, (outs GPR:$dst), (ins GPR:$a, so_imm:$b),
439 DPFrm, opc, " $dst, $a, $b",
440 [(set GPR:$dst, (opnode GPR:$a, so_imm:$b))]>,
441 Requires<[IsARM, CarryDefIsUnused]>;
442 def rr : AsI1<opcod, (outs GPR:$dst), (ins GPR:$a, GPR:$b),
443 DPFrm, opc, " $dst, $a, $b",
444 [(set GPR:$dst, (opnode GPR:$a, GPR:$b))]>,
445 Requires<[IsARM, CarryDefIsUnused]>;
446 def rs : AsI1<opcod, (outs GPR:$dst), (ins GPR:$a, so_reg:$b),
447 DPSoRegFrm, opc, " $dst, $a, $b",
448 [(set GPR:$dst, (opnode GPR:$a, so_reg:$b))]>,
449 Requires<[IsARM, CarryDefIsUnused]>;
450 // Carry setting variants
451 def Sri : AXI1<opcod, (outs GPR:$dst), (ins GPR:$a, so_imm:$b),
452 DPFrm, !strconcat(opc, "s $dst, $a, $b"),
453 [(set GPR:$dst, (opnode GPR:$a, so_imm:$b))]>,
454 Requires<[IsARM, CarryDefIsUsed]> {
457 def Srr : AXI1<opcod, (outs GPR:$dst), (ins GPR:$a, GPR:$b),
458 DPFrm, !strconcat(opc, "s $dst, $a, $b"),
459 [(set GPR:$dst, (opnode GPR:$a, GPR:$b))]>,
460 Requires<[IsARM, CarryDefIsUsed]> {
463 def Srs : AXI1<opcod, (outs GPR:$dst), (ins GPR:$a, so_reg:$b),
464 DPSoRegFrm, !strconcat(opc, "s $dst, $a, $b"),
465 [(set GPR:$dst, (opnode GPR:$a, so_reg:$b))]>,
466 Requires<[IsARM, CarryDefIsUsed]> {
472 //===----------------------------------------------------------------------===//
474 //===----------------------------------------------------------------------===//
476 //===----------------------------------------------------------------------===//
477 // Miscellaneous Instructions.
480 /// CONSTPOOL_ENTRY - This instruction represents a floating constant pool in
481 /// the function. The first operand is the ID# for this instruction, the second
482 /// is the index into the MachineConstantPool that this is, the third is the
483 /// size in bytes of this constant pool entry.
484 let neverHasSideEffects = 1, isNotDuplicable = 1 in
485 def CONSTPOOL_ENTRY :
486 PseudoInst<(outs), (ins cpinst_operand:$instid, cpinst_operand:$cpidx,
488 "${instid:label} ${cpidx:cpentry}", []>;
490 let Defs = [SP], Uses = [SP] in {
492 PseudoInst<(outs), (ins i32imm:$amt1, i32imm:$amt2, pred:$p),
493 "@ ADJCALLSTACKUP $amt1",
494 [(ARMcallseq_end timm:$amt1, timm:$amt2)]>;
496 def ADJCALLSTACKDOWN :
497 PseudoInst<(outs), (ins i32imm:$amt, pred:$p),
498 "@ ADJCALLSTACKDOWN $amt",
499 [(ARMcallseq_start timm:$amt)]>;
503 PseudoInst<(outs), (ins i32imm:$line, i32imm:$col, i32imm:$file),
504 ".loc $file, $line, $col",
505 [(dwarf_loc (i32 imm:$line), (i32 imm:$col), (i32 imm:$file))]>;
508 // Address computation and loads and stores in PIC mode.
509 let isNotDuplicable = 1 in {
510 def PICADD : AXI1<0b0100, (outs GPR:$dst), (ins GPR:$a, pclabel:$cp, pred:$p),
511 Pseudo, "$cp:\n\tadd$p $dst, pc, $a",
512 [(set GPR:$dst, (ARMpic_add GPR:$a, imm:$cp))]>;
514 let AddedComplexity = 10 in {
515 let canFoldAsLoad = 1 in
516 def PICLDR : AXI2ldw<(outs GPR:$dst), (ins addrmodepc:$addr, pred:$p),
517 Pseudo, "${addr:label}:\n\tldr$p $dst, $addr",
518 [(set GPR:$dst, (load addrmodepc:$addr))]>;
520 def PICLDRH : AXI3ldh<(outs GPR:$dst), (ins addrmodepc:$addr, pred:$p),
521 Pseudo, "${addr:label}:\n\tldr${p}h $dst, $addr",
522 [(set GPR:$dst, (zextloadi16 addrmodepc:$addr))]>;
524 def PICLDRB : AXI2ldb<(outs GPR:$dst), (ins addrmodepc:$addr, pred:$p),
525 Pseudo, "${addr:label}:\n\tldr${p}b $dst, $addr",
526 [(set GPR:$dst, (zextloadi8 addrmodepc:$addr))]>;
528 def PICLDRSH : AXI3ldsh<(outs GPR:$dst), (ins addrmodepc:$addr, pred:$p),
529 Pseudo, "${addr:label}:\n\tldr${p}sh $dst, $addr",
530 [(set GPR:$dst, (sextloadi16 addrmodepc:$addr))]>;
532 def PICLDRSB : AXI3ldsb<(outs GPR:$dst), (ins addrmodepc:$addr, pred:$p),
533 Pseudo, "${addr:label}:\n\tldr${p}sb $dst, $addr",
534 [(set GPR:$dst, (sextloadi8 addrmodepc:$addr))]>;
536 let AddedComplexity = 10 in {
537 def PICSTR : AXI2stw<(outs), (ins GPR:$src, addrmodepc:$addr, pred:$p),
538 Pseudo, "${addr:label}:\n\tstr$p $src, $addr",
539 [(store GPR:$src, addrmodepc:$addr)]>;
541 def PICSTRH : AXI3sth<(outs), (ins GPR:$src, addrmodepc:$addr, pred:$p),
542 Pseudo, "${addr:label}:\n\tstr${p}h $src, $addr",
543 [(truncstorei16 GPR:$src, addrmodepc:$addr)]>;
545 def PICSTRB : AXI2stb<(outs), (ins GPR:$src, addrmodepc:$addr, pred:$p),
546 Pseudo, "${addr:label}:\n\tstr${p}b $src, $addr",
547 [(truncstorei8 GPR:$src, addrmodepc:$addr)]>;
549 } // isNotDuplicable = 1
552 // LEApcrel - Load a pc-relative address into a register without offending the
554 def LEApcrel : AXI1<0x0, (outs GPR:$dst), (ins i32imm:$label, pred:$p), Pseudo,
555 !strconcat(!strconcat(".set PCRELV${:uid}, ($label-(",
556 "${:private}PCRELL${:uid}+8))\n"),
557 !strconcat("${:private}PCRELL${:uid}:\n\t",
558 "add$p $dst, pc, #PCRELV${:uid}")),
561 def LEApcrelJT : AXI1<0x0, (outs GPR:$dst),
562 (ins i32imm:$label, i32imm:$id, pred:$p),
564 !strconcat(!strconcat(".set PCRELV${:uid}, (${label}_${id:no_hash}-(",
565 "${:private}PCRELL${:uid}+8))\n"),
566 !strconcat("${:private}PCRELL${:uid}:\n\t",
567 "add$p $dst, pc, #PCRELV${:uid}")),
570 //===----------------------------------------------------------------------===//
571 // Control Flow Instructions.
574 let isReturn = 1, isTerminator = 1 in
575 def BX_RET : AI<(outs), (ins), BrMiscFrm, "bx", " lr", [(ARMretflag)]> {
576 let Inst{7-4} = 0b0001;
577 let Inst{19-8} = 0b111111111111;
578 let Inst{27-20} = 0b00010010;
581 // FIXME: remove when we have a way to marking a MI with these properties.
582 // FIXME: $dst1 should be a def. But the extra ops must be in the end of the
584 // FIXME: Should pc be an implicit operand like PICADD, etc?
585 let isReturn = 1, isTerminator = 1 in
586 def LDM_RET : AXI4ld<(outs),
587 (ins addrmode4:$addr, pred:$p, reglist:$dst1, variable_ops),
588 LdStMulFrm, "ldm${p}${addr:submode} $addr, $dst1",
591 // On non-Darwin platforms R9 is callee-saved.
592 let isCall = 1, Itinerary = IIC_Br,
593 Defs = [R0, R1, R2, R3, R12, LR,
594 D0, D1, D2, D3, D4, D5, D6, D7, CPSR] in {
595 def BL : ABXI<0b1011, (outs), (ins i32imm:$func, variable_ops),
597 [(ARMcall tglobaladdr:$func)]>, Requires<[IsNotDarwin]>;
599 def BL_pred : ABI<0b1011, (outs), (ins i32imm:$func, variable_ops),
600 "bl", " ${func:call}",
601 [(ARMcall_pred tglobaladdr:$func)]>, Requires<[IsNotDarwin]>;
604 def BLX : AXI<(outs), (ins GPR:$func, variable_ops), BrMiscFrm,
606 [(ARMcall GPR:$func)]>, Requires<[IsARM, HasV5T, IsNotDarwin]> {
607 let Inst{7-4} = 0b0011;
608 let Inst{19-8} = 0b111111111111;
609 let Inst{27-20} = 0b00010010;
614 def BX : ABXIx2<(outs), (ins GPR:$func, variable_ops),
615 "mov lr, pc\n\tbx $func",
616 [(ARMcall_nolink GPR:$func)]>, Requires<[IsNotDarwin]>;
620 // On Darwin R9 is call-clobbered.
621 let isCall = 1, Itinerary = IIC_Br,
622 Defs = [R0, R1, R2, R3, R9, R12, LR,
623 D0, D1, D2, D3, D4, D5, D6, D7, CPSR] in {
624 def BLr9 : ABXI<0b1011, (outs), (ins i32imm:$func, variable_ops),
626 [(ARMcall tglobaladdr:$func)]>, Requires<[IsDarwin]>;
628 def BLr9_pred : ABI<0b1011, (outs), (ins i32imm:$func, variable_ops),
629 "bl", " ${func:call}",
630 [(ARMcall_pred tglobaladdr:$func)]>, Requires<[IsDarwin]>;
633 def BLXr9 : AXI<(outs), (ins GPR:$func, variable_ops), BrMiscFrm,
635 [(ARMcall GPR:$func)]>, Requires<[IsARM, HasV5T, IsDarwin]> {
636 let Inst{7-4} = 0b0011;
637 let Inst{19-8} = 0b111111111111;
638 let Inst{27-20} = 0b00010010;
643 def BXr9 : ABXIx2<(outs), (ins GPR:$func, variable_ops),
644 "mov lr, pc\n\tbx $func",
645 [(ARMcall_nolink GPR:$func)]>, Requires<[IsDarwin]>;
649 let isBranch = 1, isTerminator = 1, Itinerary = IIC_Br in {
650 // B is "predicable" since it can be xformed into a Bcc.
651 let isBarrier = 1 in {
652 let isPredicable = 1 in
653 def B : ABXI<0b1010, (outs), (ins brtarget:$target), "b $target",
656 let isNotDuplicable = 1, isIndirectBranch = 1 in {
657 def BR_JTr : JTI<(outs), (ins GPR:$target, jtblock_operand:$jt, i32imm:$id),
658 "mov pc, $target \n$jt",
659 [(ARMbrjt GPR:$target, tjumptable:$jt, imm:$id)]> {
660 let Inst{20} = 0; // S Bit
661 let Inst{24-21} = 0b1101;
662 let Inst{27-26} = {0,0};
664 def BR_JTm : JTI<(outs),
665 (ins addrmode2:$target, jtblock_operand:$jt, i32imm:$id),
666 "ldr pc, $target \n$jt",
667 [(ARMbrjt (i32 (load addrmode2:$target)), tjumptable:$jt,
669 let Inst{20} = 1; // L bit
670 let Inst{21} = 0; // W bit
671 let Inst{22} = 0; // B bit
672 let Inst{24} = 1; // P bit
673 let Inst{27-26} = {0,1};
675 def BR_JTadd : JTI<(outs),
676 (ins GPR:$target, GPR:$idx, jtblock_operand:$jt, i32imm:$id),
677 "add pc, $target, $idx \n$jt",
678 [(ARMbrjt (add GPR:$target, GPR:$idx), tjumptable:$jt,
680 let Inst{20} = 0; // S bit
681 let Inst{24-21} = 0b0100;
682 let Inst{27-26} = {0,0};
684 } // isNotDuplicable = 1, isIndirectBranch = 1
687 // FIXME: should be able to write a pattern for ARMBrcond, but can't use
688 // a two-value operand where a dag node expects two operands. :(
689 def Bcc : ABI<0b1010, (outs), (ins brtarget:$target),
691 [/*(ARMbrcond bb:$target, imm:$cc, CCR:$ccr)*/]>;
694 //===----------------------------------------------------------------------===//
695 // Load / store Instructions.
699 let canFoldAsLoad = 1 in
700 def LDR : AI2ldw<(outs GPR:$dst), (ins addrmode2:$addr), LdFrm,
701 "ldr", " $dst, $addr",
702 [(set GPR:$dst, (load addrmode2:$addr))]>;
704 // Special LDR for loads from non-pc-relative constpools.
705 let canFoldAsLoad = 1, mayLoad = 1, isReMaterializable = 1 in
706 def LDRcp : AI2ldw<(outs GPR:$dst), (ins addrmode2:$addr), LdFrm,
707 "ldr", " $dst, $addr", []>;
709 // Loads with zero extension
710 def LDRH : AI3ldh<(outs GPR:$dst), (ins addrmode3:$addr), LdMiscFrm,
711 "ldr", "h $dst, $addr",
712 [(set GPR:$dst, (zextloadi16 addrmode3:$addr))]>;
714 def LDRB : AI2ldb<(outs GPR:$dst), (ins addrmode2:$addr), LdFrm,
715 "ldr", "b $dst, $addr",
716 [(set GPR:$dst, (zextloadi8 addrmode2:$addr))]>;
718 // Loads with sign extension
719 def LDRSH : AI3ldsh<(outs GPR:$dst), (ins addrmode3:$addr), LdMiscFrm,
720 "ldr", "sh $dst, $addr",
721 [(set GPR:$dst, (sextloadi16 addrmode3:$addr))]>;
723 def LDRSB : AI3ldsb<(outs GPR:$dst), (ins addrmode3:$addr), LdMiscFrm,
724 "ldr", "sb $dst, $addr",
725 [(set GPR:$dst, (sextloadi8 addrmode3:$addr))]>;
729 def LDRD : AI3ldd<(outs GPR:$dst1, GPR:$dst2), (ins addrmode3:$addr), LdMiscFrm,
730 "ldr", "d $dst1, $addr", []>, Requires<[IsARM, HasV5T]>;
733 def LDR_PRE : AI2ldwpr<(outs GPR:$dst, GPR:$base_wb),
734 (ins addrmode2:$addr), LdFrm,
735 "ldr", " $dst, $addr!", "$addr.base = $base_wb", []>;
737 def LDR_POST : AI2ldwpo<(outs GPR:$dst, GPR:$base_wb),
738 (ins GPR:$base, am2offset:$offset), LdFrm,
739 "ldr", " $dst, [$base], $offset", "$base = $base_wb", []>;
741 def LDRH_PRE : AI3ldhpr<(outs GPR:$dst, GPR:$base_wb),
742 (ins addrmode3:$addr), LdMiscFrm,
743 "ldr", "h $dst, $addr!", "$addr.base = $base_wb", []>;
745 def LDRH_POST : AI3ldhpo<(outs GPR:$dst, GPR:$base_wb),
746 (ins GPR:$base,am3offset:$offset), LdMiscFrm,
747 "ldr", "h $dst, [$base], $offset", "$base = $base_wb", []>;
749 def LDRB_PRE : AI2ldbpr<(outs GPR:$dst, GPR:$base_wb),
750 (ins addrmode2:$addr), LdFrm,
751 "ldr", "b $dst, $addr!", "$addr.base = $base_wb", []>;
753 def LDRB_POST : AI2ldbpo<(outs GPR:$dst, GPR:$base_wb),
754 (ins GPR:$base,am2offset:$offset), LdFrm,
755 "ldr", "b $dst, [$base], $offset", "$base = $base_wb", []>;
757 def LDRSH_PRE : AI3ldshpr<(outs GPR:$dst, GPR:$base_wb),
758 (ins addrmode3:$addr), LdMiscFrm,
759 "ldr", "sh $dst, $addr!", "$addr.base = $base_wb", []>;
761 def LDRSH_POST: AI3ldshpo<(outs GPR:$dst, GPR:$base_wb),
762 (ins GPR:$base,am3offset:$offset), LdMiscFrm,
763 "ldr", "sh $dst, [$base], $offset", "$base = $base_wb", []>;
765 def LDRSB_PRE : AI3ldsbpr<(outs GPR:$dst, GPR:$base_wb),
766 (ins addrmode3:$addr), LdMiscFrm,
767 "ldr", "sb $dst, $addr!", "$addr.base = $base_wb", []>;
769 def LDRSB_POST: AI3ldsbpo<(outs GPR:$dst, GPR:$base_wb),
770 (ins GPR:$base,am3offset:$offset), LdMiscFrm,
771 "ldr", "sb $dst, [$base], $offset", "$base = $base_wb", []>;
775 def STR : AI2stw<(outs), (ins GPR:$src, addrmode2:$addr), StFrm,
776 "str", " $src, $addr",
777 [(store GPR:$src, addrmode2:$addr)]>;
779 // Stores with truncate
780 def STRH : AI3sth<(outs), (ins GPR:$src, addrmode3:$addr), StMiscFrm,
781 "str", "h $src, $addr",
782 [(truncstorei16 GPR:$src, addrmode3:$addr)]>;
784 def STRB : AI2stb<(outs), (ins GPR:$src, addrmode2:$addr), StFrm,
785 "str", "b $src, $addr",
786 [(truncstorei8 GPR:$src, addrmode2:$addr)]>;
790 def STRD : AI3std<(outs), (ins GPR:$src1, GPR:$src2, addrmode3:$addr),StMiscFrm,
791 "str", "d $src1, $addr", []>, Requires<[IsARM, HasV5T]>;
794 def STR_PRE : AI2stwpr<(outs GPR:$base_wb),
795 (ins GPR:$src, GPR:$base, am2offset:$offset), StFrm,
796 "str", " $src, [$base, $offset]!", "$base = $base_wb",
798 (pre_store GPR:$src, GPR:$base, am2offset:$offset))]>;
800 def STR_POST : AI2stwpo<(outs GPR:$base_wb),
801 (ins GPR:$src, GPR:$base,am2offset:$offset), StFrm,
802 "str", " $src, [$base], $offset", "$base = $base_wb",
804 (post_store GPR:$src, GPR:$base, am2offset:$offset))]>;
806 def STRH_PRE : AI3sthpr<(outs GPR:$base_wb),
807 (ins GPR:$src, GPR:$base,am3offset:$offset), StMiscFrm,
808 "str", "h $src, [$base, $offset]!", "$base = $base_wb",
810 (pre_truncsti16 GPR:$src, GPR:$base,am3offset:$offset))]>;
812 def STRH_POST: AI3sthpo<(outs GPR:$base_wb),
813 (ins GPR:$src, GPR:$base,am3offset:$offset), StMiscFrm,
814 "str", "h $src, [$base], $offset", "$base = $base_wb",
815 [(set GPR:$base_wb, (post_truncsti16 GPR:$src,
816 GPR:$base, am3offset:$offset))]>;
818 def STRB_PRE : AI2stbpr<(outs GPR:$base_wb),
819 (ins GPR:$src, GPR:$base,am2offset:$offset), StFrm,
820 "str", "b $src, [$base, $offset]!", "$base = $base_wb",
821 [(set GPR:$base_wb, (pre_truncsti8 GPR:$src,
822 GPR:$base, am2offset:$offset))]>;
824 def STRB_POST: AI2stbpo<(outs GPR:$base_wb),
825 (ins GPR:$src, GPR:$base,am2offset:$offset), StFrm,
826 "str", "b $src, [$base], $offset", "$base = $base_wb",
827 [(set GPR:$base_wb, (post_truncsti8 GPR:$src,
828 GPR:$base, am2offset:$offset))]>;
830 //===----------------------------------------------------------------------===//
831 // Load / store multiple Instructions.
834 // FIXME: $dst1 should be a def.
836 def LDM : AXI4ld<(outs),
837 (ins addrmode4:$addr, pred:$p, reglist:$dst1, variable_ops),
838 LdStMulFrm, "ldm${p}${addr:submode} $addr, $dst1",
842 def STM : AXI4st<(outs),
843 (ins addrmode4:$addr, pred:$p, reglist:$src1, variable_ops),
844 LdStMulFrm, "stm${p}${addr:submode} $addr, $src1",
847 //===----------------------------------------------------------------------===//
848 // Move Instructions.
851 let neverHasSideEffects = 1 in
852 def MOVr : AsI1<0b1101, (outs GPR:$dst), (ins GPR:$src), DPFrm,
853 "mov", " $dst, $src", []>, UnaryDP;
854 def MOVs : AsI1<0b1101, (outs GPR:$dst), (ins so_reg:$src), DPSoRegFrm,
855 "mov", " $dst, $src", [(set GPR:$dst, so_reg:$src)]>, UnaryDP;
857 let isReMaterializable = 1, isAsCheapAsAMove = 1 in
858 def MOVi : AsI1<0b1101, (outs GPR:$dst), (ins so_imm:$src), DPFrm,
859 "mov", " $dst, $src", [(set GPR:$dst, so_imm:$src)]>, UnaryDP;
861 def MOVrx : AsI1<0b1101, (outs GPR:$dst), (ins GPR:$src), Pseudo,
862 "mov", " $dst, $src, rrx",
863 [(set GPR:$dst, (ARMrrx GPR:$src))]>, UnaryDP;
865 // These aren't really mov instructions, but we have to define them this way
866 // due to flag operands.
868 let Defs = [CPSR] in {
869 def MOVsrl_flag : AI1<0b1101, (outs GPR:$dst), (ins GPR:$src), Pseudo,
870 "mov", "s $dst, $src, lsr #1",
871 [(set GPR:$dst, (ARMsrl_flag GPR:$src))]>, UnaryDP;
872 def MOVsra_flag : AI1<0b1101, (outs GPR:$dst), (ins GPR:$src), Pseudo,
873 "mov", "s $dst, $src, asr #1",
874 [(set GPR:$dst, (ARMsra_flag GPR:$src))]>, UnaryDP;
877 //===----------------------------------------------------------------------===//
878 // Extend Instructions.
883 defm SXTB : AI_unary_rrot<0b01101010,
884 "sxtb", UnOpFrag<(sext_inreg node:$Src, i8)>>;
885 defm SXTH : AI_unary_rrot<0b01101011,
886 "sxth", UnOpFrag<(sext_inreg node:$Src, i16)>>;
888 defm SXTAB : AI_bin_rrot<0b01101010,
889 "sxtab", BinOpFrag<(add node:$LHS, (sext_inreg node:$RHS, i8))>>;
890 defm SXTAH : AI_bin_rrot<0b01101011,
891 "sxtah", BinOpFrag<(add node:$LHS, (sext_inreg node:$RHS,i16))>>;
893 // TODO: SXT(A){B|H}16
897 let AddedComplexity = 16 in {
898 defm UXTB : AI_unary_rrot<0b01101110,
899 "uxtb" , UnOpFrag<(and node:$Src, 0x000000FF)>>;
900 defm UXTH : AI_unary_rrot<0b01101111,
901 "uxth" , UnOpFrag<(and node:$Src, 0x0000FFFF)>>;
902 defm UXTB16 : AI_unary_rrot<0b01101100,
903 "uxtb16", UnOpFrag<(and node:$Src, 0x00FF00FF)>>;
905 def : ARMV6Pat<(and (shl GPR:$Src, (i32 8)), 0xFF00FF),
906 (UXTB16r_rot GPR:$Src, 24)>;
907 def : ARMV6Pat<(and (srl GPR:$Src, (i32 8)), 0xFF00FF),
908 (UXTB16r_rot GPR:$Src, 8)>;
910 defm UXTAB : AI_bin_rrot<0b01101110, "uxtab",
911 BinOpFrag<(add node:$LHS, (and node:$RHS, 0x00FF))>>;
912 defm UXTAH : AI_bin_rrot<0b01101111, "uxtah",
913 BinOpFrag<(add node:$LHS, (and node:$RHS, 0xFFFF))>>;
916 // This isn't safe in general, the add is two 16-bit units, not a 32-bit add.
917 //defm UXTAB16 : xxx<"uxtab16", 0xff00ff>;
919 // TODO: UXT(A){B|H}16
921 //===----------------------------------------------------------------------===//
922 // Arithmetic Instructions.
925 defm ADD : AsI1_bin_irs<0b0100, "add",
926 BinOpFrag<(add node:$LHS, node:$RHS)>>;
927 defm SUB : AsI1_bin_irs<0b0010, "sub",
928 BinOpFrag<(sub node:$LHS, node:$RHS)>>;
930 // ADD and SUB with 's' bit set.
931 defm ADDS : AI1_bin_s_irs<0b0100, "add",
932 BinOpFrag<(addc node:$LHS, node:$RHS)>>;
933 defm SUBS : AI1_bin_s_irs<0b0010, "sub",
934 BinOpFrag<(subc node:$LHS, node:$RHS)>>;
936 defm ADC : AI1_adde_sube_irs<0b0101, "adc",
937 BinOpFrag<(adde node:$LHS, node:$RHS)>>;
938 defm SBC : AI1_adde_sube_irs<0b0110, "sbc",
939 BinOpFrag<(sube node:$LHS, node:$RHS)>>;
941 // These don't define reg/reg forms, because they are handled above.
942 def RSBri : AsI1<0b0011, (outs GPR:$dst), (ins GPR:$a, so_imm:$b), DPFrm,
943 "rsb", " $dst, $a, $b",
944 [(set GPR:$dst, (sub so_imm:$b, GPR:$a))]>;
946 def RSBrs : AsI1<0b0011, (outs GPR:$dst), (ins GPR:$a, so_reg:$b), DPSoRegFrm,
947 "rsb", " $dst, $a, $b",
948 [(set GPR:$dst, (sub so_reg:$b, GPR:$a))]>;
950 // RSB with 's' bit set.
951 let Defs = [CPSR] in {
952 def RSBSri : AI1<0b0011, (outs GPR:$dst), (ins GPR:$a, so_imm:$b), DPFrm,
953 "rsb", "s $dst, $a, $b",
954 [(set GPR:$dst, (subc so_imm:$b, GPR:$a))]>;
955 def RSBSrs : AI1<0b0011, (outs GPR:$dst), (ins GPR:$a, so_reg:$b), DPSoRegFrm,
956 "rsb", "s $dst, $a, $b",
957 [(set GPR:$dst, (subc so_reg:$b, GPR:$a))]>;
960 let Uses = [CPSR] in {
961 def RSCri : AsI1<0b0111, (outs GPR:$dst), (ins GPR:$a, so_imm:$b),
962 DPFrm, "rsc", " $dst, $a, $b",
963 [(set GPR:$dst, (sube so_imm:$b, GPR:$a))]>,
964 Requires<[IsARM, CarryDefIsUnused]>;
965 def RSCrs : AsI1<0b0111, (outs GPR:$dst), (ins GPR:$a, so_reg:$b),
966 DPSoRegFrm, "rsc", " $dst, $a, $b",
967 [(set GPR:$dst, (sube so_reg:$b, GPR:$a))]>,
968 Requires<[IsARM, CarryDefIsUnused]>;
971 // FIXME: Allow these to be predicated.
972 let Defs = [CPSR], Uses = [CPSR] in {
973 def RSCSri : AXI1<0b0111, (outs GPR:$dst), (ins GPR:$a, so_imm:$b),
974 DPFrm, "rscs $dst, $a, $b",
975 [(set GPR:$dst, (sube so_imm:$b, GPR:$a))]>,
976 Requires<[IsARM, CarryDefIsUnused]>;
977 def RSCSrs : AXI1<0b0111, (outs GPR:$dst), (ins GPR:$a, so_reg:$b),
978 DPSoRegFrm, "rscs $dst, $a, $b",
979 [(set GPR:$dst, (sube so_reg:$b, GPR:$a))]>,
980 Requires<[IsARM, CarryDefIsUnused]>;
983 // (sub X, imm) gets canonicalized to (add X, -imm). Match this form.
984 def : ARMPat<(add GPR:$src, so_imm_neg:$imm),
985 (SUBri GPR:$src, so_imm_neg:$imm)>;
987 //def : ARMPat<(addc GPR:$src, so_imm_neg:$imm),
988 // (SUBSri GPR:$src, so_imm_neg:$imm)>;
989 //def : ARMPat<(adde GPR:$src, so_imm_neg:$imm),
990 // (SBCri GPR:$src, so_imm_neg:$imm)>;
992 // Note: These are implemented in C++ code, because they have to generate
993 // ADD/SUBrs instructions, which use a complex pattern that a xform function
995 // (mul X, 2^n+1) -> (add (X << n), X)
996 // (mul X, 2^n-1) -> (rsb X, (X << n))
999 //===----------------------------------------------------------------------===//
1000 // Bitwise Instructions.
1003 defm AND : AsI1_bin_irs<0b0000, "and",
1004 BinOpFrag<(and node:$LHS, node:$RHS)>>;
1005 defm ORR : AsI1_bin_irs<0b1100, "orr",
1006 BinOpFrag<(or node:$LHS, node:$RHS)>>;
1007 defm EOR : AsI1_bin_irs<0b0001, "eor",
1008 BinOpFrag<(xor node:$LHS, node:$RHS)>>;
1009 defm BIC : AsI1_bin_irs<0b1110, "bic",
1010 BinOpFrag<(and node:$LHS, (not node:$RHS))>>;
1012 def MVNr : AsI1<0b1111, (outs GPR:$dst), (ins GPR:$src), DPFrm,
1013 "mvn", " $dst, $src",
1014 [(set GPR:$dst, (not GPR:$src))]>, UnaryDP;
1015 def MVNs : AsI1<0b1111, (outs GPR:$dst), (ins so_reg:$src), DPSoRegFrm,
1016 "mvn", " $dst, $src",
1017 [(set GPR:$dst, (not so_reg:$src))]>, UnaryDP;
1018 let isReMaterializable = 1, isAsCheapAsAMove = 1 in
1019 def MVNi : AsI1<0b1111, (outs GPR:$dst), (ins so_imm:$imm), DPFrm,
1020 "mvn", " $dst, $imm",
1021 [(set GPR:$dst, so_imm_not:$imm)]>,UnaryDP;
1023 def : ARMPat<(and GPR:$src, so_imm_not:$imm),
1024 (BICri GPR:$src, so_imm_not:$imm)>;
1026 //===----------------------------------------------------------------------===//
1027 // Multiply Instructions.
1030 def MUL : AsMul1I<0b0000000, (outs GPR:$dst), (ins GPR:$a, GPR:$b),
1031 "mul", " $dst, $a, $b",
1032 [(set GPR:$dst, (mul GPR:$a, GPR:$b))]>;
1034 def MLA : AsMul1I<0b0000001, (outs GPR:$dst), (ins GPR:$a, GPR:$b, GPR:$c),
1035 "mla", " $dst, $a, $b, $c",
1036 [(set GPR:$dst, (add (mul GPR:$a, GPR:$b), GPR:$c))]>;
1038 // Extra precision multiplies with low / high results
1039 let neverHasSideEffects = 1 in {
1040 def SMULL : AsMul1I<0b0000110, (outs GPR:$ldst, GPR:$hdst),
1041 (ins GPR:$a, GPR:$b),
1042 "smull", " $ldst, $hdst, $a, $b", []>;
1044 def UMULL : AsMul1I<0b0000100, (outs GPR:$ldst, GPR:$hdst),
1045 (ins GPR:$a, GPR:$b),
1046 "umull", " $ldst, $hdst, $a, $b", []>;
1048 // Multiply + accumulate
1049 def SMLAL : AsMul1I<0b0000111, (outs GPR:$ldst, GPR:$hdst),
1050 (ins GPR:$a, GPR:$b),
1051 "smlal", " $ldst, $hdst, $a, $b", []>;
1053 def UMLAL : AsMul1I<0b0000101, (outs GPR:$ldst, GPR:$hdst),
1054 (ins GPR:$a, GPR:$b),
1055 "umlal", " $ldst, $hdst, $a, $b", []>;
1057 def UMAAL : AMul1I <0b0000010, (outs GPR:$ldst, GPR:$hdst),
1058 (ins GPR:$a, GPR:$b),
1059 "umaal", " $ldst, $hdst, $a, $b", []>,
1060 Requires<[IsARM, HasV6]>;
1061 } // neverHasSideEffects
1063 // Most significant word multiply
1064 def SMMUL : AMul2I <0b0111010, (outs GPR:$dst), (ins GPR:$a, GPR:$b),
1065 "smmul", " $dst, $a, $b",
1066 [(set GPR:$dst, (mulhs GPR:$a, GPR:$b))]>,
1067 Requires<[IsARM, HasV6]> {
1068 let Inst{7-4} = 0b0001;
1069 let Inst{15-12} = 0b1111;
1072 def SMMLA : AMul2I <0b0111010, (outs GPR:$dst), (ins GPR:$a, GPR:$b, GPR:$c),
1073 "smmla", " $dst, $a, $b, $c",
1074 [(set GPR:$dst, (add (mulhs GPR:$a, GPR:$b), GPR:$c))]>,
1075 Requires<[IsARM, HasV6]> {
1076 let Inst{7-4} = 0b0001;
1080 def SMMLS : AMul2I <0b0111010, (outs GPR:$dst), (ins GPR:$a, GPR:$b, GPR:$c),
1081 "smmls", " $dst, $a, $b, $c",
1082 [(set GPR:$dst, (sub GPR:$c, (mulhs GPR:$a, GPR:$b)))]>,
1083 Requires<[IsARM, HasV6]> {
1084 let Inst{7-4} = 0b1101;
1087 multiclass AI_smul<string opc, PatFrag opnode> {
1088 def BB : AMulxyI<0b0001011, (outs GPR:$dst), (ins GPR:$a, GPR:$b),
1089 !strconcat(opc, "bb"), " $dst, $a, $b",
1090 [(set GPR:$dst, (opnode (sext_inreg GPR:$a, i16),
1091 (sext_inreg GPR:$b, i16)))]>,
1092 Requires<[IsARM, HasV5TE]> {
1097 def BT : AMulxyI<0b0001011, (outs GPR:$dst), (ins GPR:$a, GPR:$b),
1098 !strconcat(opc, "bt"), " $dst, $a, $b",
1099 [(set GPR:$dst, (opnode (sext_inreg GPR:$a, i16),
1100 (sra GPR:$b, (i32 16))))]>,
1101 Requires<[IsARM, HasV5TE]> {
1106 def TB : AMulxyI<0b0001011, (outs GPR:$dst), (ins GPR:$a, GPR:$b),
1107 !strconcat(opc, "tb"), " $dst, $a, $b",
1108 [(set GPR:$dst, (opnode (sra GPR:$a, (i32 16)),
1109 (sext_inreg GPR:$b, i16)))]>,
1110 Requires<[IsARM, HasV5TE]> {
1115 def TT : AMulxyI<0b0001011, (outs GPR:$dst), (ins GPR:$a, GPR:$b),
1116 !strconcat(opc, "tt"), " $dst, $a, $b",
1117 [(set GPR:$dst, (opnode (sra GPR:$a, (i32 16)),
1118 (sra GPR:$b, (i32 16))))]>,
1119 Requires<[IsARM, HasV5TE]> {
1124 def WB : AMulxyI<0b0001001, (outs GPR:$dst), (ins GPR:$a, GPR:$b),
1125 !strconcat(opc, "wb"), " $dst, $a, $b",
1126 [(set GPR:$dst, (sra (opnode GPR:$a,
1127 (sext_inreg GPR:$b, i16)), (i32 16)))]>,
1128 Requires<[IsARM, HasV5TE]> {
1133 def WT : AMulxyI<0b0001001, (outs GPR:$dst), (ins GPR:$a, GPR:$b),
1134 !strconcat(opc, "wt"), " $dst, $a, $b",
1135 [(set GPR:$dst, (sra (opnode GPR:$a,
1136 (sra GPR:$b, (i32 16))), (i32 16)))]>,
1137 Requires<[IsARM, HasV5TE]> {
1144 multiclass AI_smla<string opc, PatFrag opnode> {
1145 def BB : AMulxyI<0b0001000, (outs GPR:$dst), (ins GPR:$a, GPR:$b, GPR:$acc),
1146 !strconcat(opc, "bb"), " $dst, $a, $b, $acc",
1147 [(set GPR:$dst, (add GPR:$acc,
1148 (opnode (sext_inreg GPR:$a, i16),
1149 (sext_inreg GPR:$b, i16))))]>,
1150 Requires<[IsARM, HasV5TE]> {
1155 def BT : AMulxyI<0b0001000, (outs GPR:$dst), (ins GPR:$a, GPR:$b, GPR:$acc),
1156 !strconcat(opc, "bt"), " $dst, $a, $b, $acc",
1157 [(set GPR:$dst, (add GPR:$acc, (opnode (sext_inreg GPR:$a, i16),
1158 (sra GPR:$b, (i32 16)))))]>,
1159 Requires<[IsARM, HasV5TE]> {
1164 def TB : AMulxyI<0b0001000, (outs GPR:$dst), (ins GPR:$a, GPR:$b, GPR:$acc),
1165 !strconcat(opc, "tb"), " $dst, $a, $b, $acc",
1166 [(set GPR:$dst, (add GPR:$acc, (opnode (sra GPR:$a, (i32 16)),
1167 (sext_inreg GPR:$b, i16))))]>,
1168 Requires<[IsARM, HasV5TE]> {
1173 def TT : AMulxyI<0b0001000, (outs GPR:$dst), (ins GPR:$a, GPR:$b, GPR:$acc),
1174 !strconcat(opc, "tt"), " $dst, $a, $b, $acc",
1175 [(set GPR:$dst, (add GPR:$acc, (opnode (sra GPR:$a, (i32 16)),
1176 (sra GPR:$b, (i32 16)))))]>,
1177 Requires<[IsARM, HasV5TE]> {
1182 def WB : AMulxyI<0b0001001, (outs GPR:$dst), (ins GPR:$a, GPR:$b, GPR:$acc),
1183 !strconcat(opc, "wb"), " $dst, $a, $b, $acc",
1184 [(set GPR:$dst, (add GPR:$acc, (sra (opnode GPR:$a,
1185 (sext_inreg GPR:$b, i16)), (i32 16))))]>,
1186 Requires<[IsARM, HasV5TE]> {
1191 def WT : AMulxyI<0b0001001, (outs GPR:$dst), (ins GPR:$a, GPR:$b, GPR:$acc),
1192 !strconcat(opc, "wt"), " $dst, $a, $b, $acc",
1193 [(set GPR:$dst, (add GPR:$acc, (sra (opnode GPR:$a,
1194 (sra GPR:$b, (i32 16))), (i32 16))))]>,
1195 Requires<[IsARM, HasV5TE]> {
1201 defm SMUL : AI_smul<"smul", BinOpFrag<(mul node:$LHS, node:$RHS)>>;
1202 defm SMLA : AI_smla<"smla", BinOpFrag<(mul node:$LHS, node:$RHS)>>;
1204 // TODO: Halfword multiple accumulate long: SMLAL<x><y>
1205 // TODO: Dual halfword multiple: SMUAD, SMUSD, SMLAD, SMLSD, SMLALD, SMLSLD
1207 //===----------------------------------------------------------------------===//
1208 // Misc. Arithmetic Instructions.
1211 def CLZ : AMiscA1I<0b000010110, (outs GPR:$dst), (ins GPR:$src),
1212 "clz", " $dst, $src",
1213 [(set GPR:$dst, (ctlz GPR:$src))]>, Requires<[IsARM, HasV5T]> {
1214 let Inst{7-4} = 0b0001;
1215 let Inst{11-8} = 0b1111;
1216 let Inst{19-16} = 0b1111;
1219 def REV : AMiscA1I<0b01101011, (outs GPR:$dst), (ins GPR:$src),
1220 "rev", " $dst, $src",
1221 [(set GPR:$dst, (bswap GPR:$src))]>, Requires<[IsARM, HasV6]> {
1222 let Inst{7-4} = 0b0011;
1223 let Inst{11-8} = 0b1111;
1224 let Inst{19-16} = 0b1111;
1227 def REV16 : AMiscA1I<0b01101011, (outs GPR:$dst), (ins GPR:$src),
1228 "rev16", " $dst, $src",
1230 (or (and (srl GPR:$src, (i32 8)), 0xFF),
1231 (or (and (shl GPR:$src, (i32 8)), 0xFF00),
1232 (or (and (srl GPR:$src, (i32 8)), 0xFF0000),
1233 (and (shl GPR:$src, (i32 8)), 0xFF000000)))))]>,
1234 Requires<[IsARM, HasV6]> {
1235 let Inst{7-4} = 0b1011;
1236 let Inst{11-8} = 0b1111;
1237 let Inst{19-16} = 0b1111;
1240 def REVSH : AMiscA1I<0b01101111, (outs GPR:$dst), (ins GPR:$src),
1241 "revsh", " $dst, $src",
1244 (or (srl (and GPR:$src, 0xFF00), (i32 8)),
1245 (shl GPR:$src, (i32 8))), i16))]>,
1246 Requires<[IsARM, HasV6]> {
1247 let Inst{7-4} = 0b1011;
1248 let Inst{11-8} = 0b1111;
1249 let Inst{19-16} = 0b1111;
1252 def PKHBT : AMiscA1I<0b01101000, (outs GPR:$dst),
1253 (ins GPR:$src1, GPR:$src2, i32imm:$shamt),
1254 "pkhbt", " $dst, $src1, $src2, LSL $shamt",
1255 [(set GPR:$dst, (or (and GPR:$src1, 0xFFFF),
1256 (and (shl GPR:$src2, (i32 imm:$shamt)),
1258 Requires<[IsARM, HasV6]> {
1259 let Inst{6-4} = 0b001;
1262 // Alternate cases for PKHBT where identities eliminate some nodes.
1263 def : ARMV6Pat<(or (and GPR:$src1, 0xFFFF), (and GPR:$src2, 0xFFFF0000)),
1264 (PKHBT GPR:$src1, GPR:$src2, 0)>;
1265 def : ARMV6Pat<(or (and GPR:$src1, 0xFFFF), (shl GPR:$src2, imm16_31:$shamt)),
1266 (PKHBT GPR:$src1, GPR:$src2, imm16_31:$shamt)>;
1269 def PKHTB : AMiscA1I<0b01101000, (outs GPR:$dst),
1270 (ins GPR:$src1, GPR:$src2, i32imm:$shamt),
1271 "pkhtb", " $dst, $src1, $src2, ASR $shamt",
1272 [(set GPR:$dst, (or (and GPR:$src1, 0xFFFF0000),
1273 (and (sra GPR:$src2, imm16_31:$shamt),
1274 0xFFFF)))]>, Requires<[IsARM, HasV6]> {
1275 let Inst{6-4} = 0b101;
1278 // Alternate cases for PKHTB where identities eliminate some nodes. Note that
1279 // a shift amount of 0 is *not legal* here, it is PKHBT instead.
1280 def : ARMV6Pat<(or (and GPR:$src1, 0xFFFF0000), (srl GPR:$src2, (i32 16))),
1281 (PKHTB GPR:$src1, GPR:$src2, 16)>;
1282 def : ARMV6Pat<(or (and GPR:$src1, 0xFFFF0000),
1283 (and (srl GPR:$src2, imm1_15:$shamt), 0xFFFF)),
1284 (PKHTB GPR:$src1, GPR:$src2, imm1_15:$shamt)>;
1286 //===----------------------------------------------------------------------===//
1287 // Comparison Instructions...
1290 defm CMP : AI1_cmp_irs<0b1010, "cmp",
1291 BinOpFrag<(ARMcmp node:$LHS, node:$RHS)>>;
1292 defm CMN : AI1_cmp_irs<0b1011, "cmn",
1293 BinOpFrag<(ARMcmp node:$LHS,(ineg node:$RHS))>>;
1295 // Note that TST/TEQ don't set all the same flags that CMP does!
1296 defm TST : AI1_cmp_irs<0b1000, "tst",
1297 BinOpFrag<(ARMcmpNZ (and node:$LHS, node:$RHS), 0)>>;
1298 defm TEQ : AI1_cmp_irs<0b1001, "teq",
1299 BinOpFrag<(ARMcmpNZ (xor node:$LHS, node:$RHS), 0)>>;
1301 defm CMPnz : AI1_cmp_irs<0b1010, "cmp",
1302 BinOpFrag<(ARMcmpNZ node:$LHS, node:$RHS)>>;
1303 defm CMNnz : AI1_cmp_irs<0b1011, "cmn",
1304 BinOpFrag<(ARMcmpNZ node:$LHS,(ineg node:$RHS))>>;
1306 def : ARMPat<(ARMcmp GPR:$src, so_imm_neg:$imm),
1307 (CMNri GPR:$src, so_imm_neg:$imm)>;
1309 def : ARMPat<(ARMcmpNZ GPR:$src, so_imm_neg:$imm),
1310 (CMNri GPR:$src, so_imm_neg:$imm)>;
1313 // Conditional moves
1314 // FIXME: should be able to write a pattern for ARMcmov, but can't use
1315 // a two-value operand where a dag node expects two operands. :(
1316 def MOVCCr : AI1<0b1101, (outs GPR:$dst), (ins GPR:$false, GPR:$true), DPFrm,
1317 "mov", " $dst, $true",
1318 [/*(set GPR:$dst, (ARMcmov GPR:$false, GPR:$true, imm:$cc, CCR:$ccr))*/]>,
1319 RegConstraint<"$false = $dst">, UnaryDP;
1321 def MOVCCs : AI1<0b1101, (outs GPR:$dst),
1322 (ins GPR:$false, so_reg:$true), DPSoRegFrm,
1323 "mov", " $dst, $true",
1324 [/*(set GPR:$dst, (ARMcmov GPR:$false, so_reg:$true, imm:$cc, CCR:$ccr))*/]>,
1325 RegConstraint<"$false = $dst">, UnaryDP;
1327 def MOVCCi : AI1<0b1101, (outs GPR:$dst),
1328 (ins GPR:$false, so_imm:$true), DPFrm,
1329 "mov", " $dst, $true",
1330 [/*(set GPR:$dst, (ARMcmov GPR:$false, so_imm:$true, imm:$cc, CCR:$ccr))*/]>,
1331 RegConstraint<"$false = $dst">, UnaryDP;
1334 //===----------------------------------------------------------------------===//
1338 // __aeabi_read_tp preserves the registers r1-r3.
1340 Defs = [R0, R12, LR, CPSR] in {
1341 def TPsoft : ABXI<0b1011, (outs), (ins),
1342 "bl __aeabi_read_tp",
1343 [(set R0, ARMthread_pointer)]>;
1346 //===----------------------------------------------------------------------===//
1347 // SJLJ Exception handling intrinsics
1348 // eh_sjlj_setjmp() is a three instruction sequence to store the return
1349 // address and save #0 in R0 for the non-longjmp case.
1350 // Since by its nature we may be coming from some other function to get
1351 // here, and we're using the stack frame for the containing function to
1352 // save/restore registers, we can't keep anything live in regs across
1353 // the eh_sjlj_setjmp(), else it will almost certainly have been tromped upon
1354 // when we get here from a longjmp(). We force everthing out of registers
1355 // except for our own input by listing the relevant registers in Defs. By
1356 // doing so, we also cause the prologue/epilogue code to actively preserve
1357 // all of the callee-saved resgisters, which is exactly what we want.
1359 [ R0, R1, R3, R4, R5, R6, R7, R8, R9, R10, R11, R12, LR,
1360 D0, D2, D3, D4, D5, D6, D7, D8, D9, D10, D11, D12, D13, D14, D15 ] in {
1361 def Int_eh_sjlj_setjmp : XI<(outs), (ins GPR:$src),
1362 AddrModeNone, SizeSpecial, IndexModeNone, Pseudo,
1363 "add r0, pc, #4\n\t"
1364 "str r0, [$src, #+4]\n\t"
1365 "mov r0, #0 @ eh_setjmp", "",
1366 [(set R0, (ARMeh_sjlj_setjmp GPR:$src))]>;
1369 //===----------------------------------------------------------------------===//
1370 // Non-Instruction Patterns
1373 // ConstantPool, GlobalAddress, and JumpTable
1374 def : ARMPat<(ARMWrapper tglobaladdr :$dst), (LEApcrel tglobaladdr :$dst)>;
1375 def : ARMPat<(ARMWrapper tconstpool :$dst), (LEApcrel tconstpool :$dst)>;
1376 def : ARMPat<(ARMWrapperJT tjumptable:$dst, imm:$id),
1377 (LEApcrelJT tjumptable:$dst, imm:$id)>;
1379 // Large immediate handling.
1381 // Two piece so_imms.
1382 let isReMaterializable = 1 in
1383 def MOVi2pieces : AI1x2<(outs GPR:$dst), (ins so_imm2part:$src), Pseudo,
1384 "mov", " $dst, $src",
1385 [(set GPR:$dst, so_imm2part:$src)]>;
1387 def : ARMPat<(or GPR:$LHS, so_imm2part:$RHS),
1388 (ORRri (ORRri GPR:$LHS, (so_imm2part_1 imm:$RHS)),
1389 (so_imm2part_2 imm:$RHS))>;
1390 def : ARMPat<(xor GPR:$LHS, so_imm2part:$RHS),
1391 (EORri (EORri GPR:$LHS, (so_imm2part_1 imm:$RHS)),
1392 (so_imm2part_2 imm:$RHS))>;
1394 // TODO: add,sub,and, 3-instr forms?
1398 def : ARMPat<(ARMcall texternalsym:$func), (BL texternalsym:$func)>,
1399 Requires<[IsNotDarwin]>;
1400 def : ARMPat<(ARMcall texternalsym:$func), (BLr9 texternalsym:$func)>,
1401 Requires<[IsDarwin]>;
1403 // zextload i1 -> zextload i8
1404 def : ARMPat<(zextloadi1 addrmode2:$addr), (LDRB addrmode2:$addr)>;
1406 // extload -> zextload
1407 def : ARMPat<(extloadi1 addrmode2:$addr), (LDRB addrmode2:$addr)>;
1408 def : ARMPat<(extloadi8 addrmode2:$addr), (LDRB addrmode2:$addr)>;
1409 def : ARMPat<(extloadi16 addrmode3:$addr), (LDRH addrmode3:$addr)>;
1411 def : ARMPat<(extloadi8 addrmodepc:$addr), (PICLDRB addrmodepc:$addr)>;
1412 def : ARMPat<(extloadi16 addrmodepc:$addr), (PICLDRH addrmodepc:$addr)>;
1415 def : ARMV5TEPat<(mul (sra (shl GPR:$a, (i32 16)), (i32 16)),
1416 (sra (shl GPR:$b, (i32 16)), (i32 16))),
1417 (SMULBB GPR:$a, GPR:$b)>;
1418 def : ARMV5TEPat<(mul sext_16_node:$a, sext_16_node:$b),
1419 (SMULBB GPR:$a, GPR:$b)>;
1420 def : ARMV5TEPat<(mul (sra (shl GPR:$a, (i32 16)), (i32 16)),
1421 (sra GPR:$b, (i32 16))),
1422 (SMULBT GPR:$a, GPR:$b)>;
1423 def : ARMV5TEPat<(mul sext_16_node:$a, (sra GPR:$b, (i32 16))),
1424 (SMULBT GPR:$a, GPR:$b)>;
1425 def : ARMV5TEPat<(mul (sra GPR:$a, (i32 16)),
1426 (sra (shl GPR:$b, (i32 16)), (i32 16))),
1427 (SMULTB GPR:$a, GPR:$b)>;
1428 def : ARMV5TEPat<(mul (sra GPR:$a, (i32 16)), sext_16_node:$b),
1429 (SMULTB GPR:$a, GPR:$b)>;
1430 def : ARMV5TEPat<(sra (mul GPR:$a, (sra (shl GPR:$b, (i32 16)), (i32 16))),
1432 (SMULWB GPR:$a, GPR:$b)>;
1433 def : ARMV5TEPat<(sra (mul GPR:$a, sext_16_node:$b), (i32 16)),
1434 (SMULWB GPR:$a, GPR:$b)>;
1436 def : ARMV5TEPat<(add GPR:$acc,
1437 (mul (sra (shl GPR:$a, (i32 16)), (i32 16)),
1438 (sra (shl GPR:$b, (i32 16)), (i32 16)))),
1439 (SMLABB GPR:$a, GPR:$b, GPR:$acc)>;
1440 def : ARMV5TEPat<(add GPR:$acc,
1441 (mul sext_16_node:$a, sext_16_node:$b)),
1442 (SMLABB GPR:$a, GPR:$b, GPR:$acc)>;
1443 def : ARMV5TEPat<(add GPR:$acc,
1444 (mul (sra (shl GPR:$a, (i32 16)), (i32 16)),
1445 (sra GPR:$b, (i32 16)))),
1446 (SMLABT GPR:$a, GPR:$b, GPR:$acc)>;
1447 def : ARMV5TEPat<(add GPR:$acc,
1448 (mul sext_16_node:$a, (sra GPR:$b, (i32 16)))),
1449 (SMLABT GPR:$a, GPR:$b, GPR:$acc)>;
1450 def : ARMV5TEPat<(add GPR:$acc,
1451 (mul (sra GPR:$a, (i32 16)),
1452 (sra (shl GPR:$b, (i32 16)), (i32 16)))),
1453 (SMLATB GPR:$a, GPR:$b, GPR:$acc)>;
1454 def : ARMV5TEPat<(add GPR:$acc,
1455 (mul (sra GPR:$a, (i32 16)), sext_16_node:$b)),
1456 (SMLATB GPR:$a, GPR:$b, GPR:$acc)>;
1457 def : ARMV5TEPat<(add GPR:$acc,
1458 (sra (mul GPR:$a, (sra (shl GPR:$b, (i32 16)), (i32 16))),
1460 (SMLAWB GPR:$a, GPR:$b, GPR:$acc)>;
1461 def : ARMV5TEPat<(add GPR:$acc,
1462 (sra (mul GPR:$a, sext_16_node:$b), (i32 16))),
1463 (SMLAWB GPR:$a, GPR:$b, GPR:$acc)>;
1465 //===----------------------------------------------------------------------===//
1469 include "ARMInstrThumb.td"
1471 //===----------------------------------------------------------------------===//
1475 include "ARMInstrThumb2.td"
1477 //===----------------------------------------------------------------------===//
1478 // Floating Point Support
1481 include "ARMInstrVFP.td"
1483 //===----------------------------------------------------------------------===//
1484 // Advanced SIMD (NEON) Support
1487 include "ARMInstrNEON.td"